diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 8383ab5977..69ccb69e8f 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -29,6 +29,7 @@ jobs: fail-fast: false matrix: legs: + - {RTT_BSP: "acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -134,6 +135,8 @@ jobs: - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "raspberry-pi/raspi4-32", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "hc32l196", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "tae32f5300", RTT_TOOL_CHAIN: "sourcery-arm"} steps: - uses: actions/checkout@v2 - name: Set up Python diff --git a/.gitignore b/.gitignore index 4e6126542c..cef857a69e 100644 --- a/.gitignore +++ b/.gitignore @@ -25,6 +25,7 @@ documentation/html tools/kconfig-frontends/kconfig-mconf packages dist +dist_ide_project cconfig.h GPUCache diff --git a/.ignore_format.yml b/.ignore_format.yml index 6622a90397..5e3780d203 100644 --- a/.ignore_format.yml +++ b/.ignore_format.yml @@ -23,4 +23,3 @@ dir_path: - bsp/stm32/libraries/STM32MPxx_HAL - bsp/stm32/libraries/STM32WBxx_HAL - bsp/stm32/libraries/STM32H7xx_HAL -- bsp/hk32/libraries diff --git a/bsp/Copyright_Notice.md b/bsp/Copyright_Notice.md index 8ec2687a75..63c25ab499 100644 --- a/bsp/Copyright_Notice.md +++ b/bsp/Copyright_Notice.md @@ -10,6 +10,16 @@ The peripheral library or firmware library of the chip manufacturer is authorize ## BSP's License and Coyright: +### acm32f0x0-nucleo + +License: bsd-new + +Copyright: Copyright (c) 2021, AisinoChip + +Path: + +- bsp/acm32f0x0-nucleo/libraries + ### apollo2 License: bsd-new @@ -216,6 +226,28 @@ Path: - bsp/hc32f4a0/Libraries/CMSIS - bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver +### hc32f460 + +License: bsd-new + +Copyright: Copyright (c) 2020, Huada Semiconductor Co., Ltd. + +Path: + +- bsp/hc32f460/Libraries/CMSIS +- bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver + +### hc32l196 + +License: bsd-new + +Copyright: Copyright (c) 2020, Huada Semiconductor Co., Ltd. + +Path: + +- bsp/hc32l196/Libraries/CMSIS +- bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver + ### hk32 License: free-unknown @@ -697,6 +729,16 @@ Path: - bsp/swm320/libraries/CMSIS - bsp/swm320-lq100/Libraries/CMSIS/CoreSupport +### tae32f5300 + +License: BSD 3-Clause + +Copyright (c) 2020 Tai-Action. + +Path: + +- bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver + ### tm4c License: unknown-license-reference(bsd-new) @@ -748,3 +790,20 @@ Path: - bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver +### n32 + +License: 未注明 + +Copyright: Copyright (c) 2019, Nations Technologies Inc. + +Path: + +- bsp/n32g452xx/n32g452xx-mini-system/board/msp + +License: bsd-new + +Copyright: Copyright (c) 2010-2015 ARM Limited + +Path: + +- bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS diff --git a/bsp/acm32f0x0-nucleo/.ignore_format.yml b/bsp/acm32f0x0-nucleo/.ignore_format.yml new file mode 100644 index 0000000000..29b7c31648 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- libraries diff --git a/bsp/acm32f0x0-nucleo/Kconfig b/bsp/acm32f0x0-nucleo/Kconfig new file mode 100644 index 0000000000..851a0c7409 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_SERIES_ACM32F0 + bool + select ARCH_ARM_CORTEX_M0 + default y + +source "$BSP_DIR/drivers/Kconfig" + diff --git a/bsp/acm32f0x0-nucleo/README.md b/bsp/acm32f0x0-nucleo/README.md new file mode 100644 index 0000000000..43cb4484a6 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/README.md @@ -0,0 +1,58 @@ +# acm32f0x0板级支持包 + +## 1. 简介 + +ACM32F0x0芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性： + +|--------------------------|--------------------| +| 硬件 | 描述 | +| -------------------------|--------------------| +|芯片型号 | ACM32F0X0系列 | +|CPU | ARM Cortex-M0 | +|主频 | 64MHz | +|片内SRAM | 32K | +|片内Flash | 128K | +|--------------------------|--------------------| + +具体型号及资源请参考上海航芯官方网站[ACM32F0](www.aisinochip.com/index.php/product/child1/id/217.html)。 + +## 2. 编译说明 + +推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f0x0-nucleo`目录中，运行以下命令： + +`scons` + +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。 + +也可以通过`scons --target=iar`或`scons --target=mdk5`生成IAR或是keil工程，再使用相应的工具进行编译。 + +## 3. 烧写及执行 + +开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。 + +### 3.1 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +## 4. 驱动支持情况及计划 + +| **片上外设** | **支持情况** | **备注** | +| ------------- | ------------ | ------------------------------------- | +| GPIO | 支持 | PA0, PA1... PD15 ---> PIN: 0, 1...63 | +| UART | 支持 | UART1/UART2 | +| LED | 支持 | LED1 | +| WDT | 支持 | WDT/IWDT | +| ADC | 支持 | | + +## 5. 联系人信息 + +维护人：AisinoChip < xiangfeng.liu@aisinochip.com > + +## 6. 参考 + +* 板子[数据手册][2] +* 芯片[数据手册][3] + + [1]: https://www.rt-thread.org/page/download.html + [2]: www.aisinochip.com/index.php/product/detail/id/32.html + [3]: www.aisinochip.com/index.php/product/detail/id/32.html diff --git a/bsp/acm32f0x0-nucleo/SConscript b/bsp/acm32f0x0-nucleo/SConscript new file mode 100644 index 0000000000..7c098f9c8a --- /dev/null +++ b/bsp/acm32f0x0-nucleo/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') + diff --git a/bsp/acm32f0x0-nucleo/SConstruct b/bsp/acm32f0x0-nucleo/SConstruct new file mode 100644 index 0000000000..855909626f --- /dev/null +++ b/bsp/acm32f0x0-nucleo/SConstruct @@ -0,0 +1,52 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) + diff --git a/bsp/acm32f0x0-nucleo/applications/SConscript b/bsp/acm32f0x0-nucleo/applications/SConscript new file mode 100644 index 0000000000..fc2501998c --- /dev/null +++ b/bsp/acm32f0x0-nucleo/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/acm32f0x0-nucleo/applications/main.c b/bsp/acm32f0x0-nucleo/applications/main.c new file mode 100644 index 0000000000..2e827e89f2 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 AisinoChip the first version + */ + +#include +#include +#include "board.h" +#include + +#define LED_PIN_NUM 1 /* PA1 */ + +int main(void) +{ + rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT); + + while(1) + { + rt_pin_write(LED_PIN_NUM, PIN_LOW); + rt_thread_delay(RT_TICK_PER_SECOND/2); + rt_pin_write(LED_PIN_NUM, PIN_HIGH); + rt_thread_delay(RT_TICK_PER_SECOND/2); + } +} + diff --git a/bsp/acm32f0x0-nucleo/drivers/Kconfig b/bsp/acm32f0x0-nucleo/drivers/Kconfig new file mode 100644 index 0000000000..59145af73f --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/Kconfig @@ -0,0 +1,237 @@ +menu "Hardware Drivers Config" + +config SOC_ACM32F070RBT7 + bool + select SOC_SERIES_ACM32F0 + select RT_USING_COMPONENTS_INIT + default y + +config SOC_SRAM_START_ADDR + hex + default 0x20000000 + +config SOC_SRAM_SIZE + hex + default 0x20 + +config SOC_FLASH_START_ADDR + hex + default 0x00000000 + +config SOC_FLASH_SIZE + hex + default 0x80 + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + menu "Hardware GPIO" + config BSP_USING_GPIO1 + bool "Enable GPIOAB" + default y + select RT_USING_PIN + config BSP_USING_GPIO2 + bool "Enable GPIOCD" + default y + select RT_USING_PIN + endmenu + + config BSP_USING_ADC + bool "Enable ADC" + select RT_USING_ADC + default n + + menu "Hardware UART" + config BSP_USING_UART1 + bool "Enable UART1 (PA9/PA10)" + default y + select RT_USING_SERIAL + + config BSP_USING_UART2 + bool "Enable UART2 (PA2/PA3)" + default y + select RT_USING_SERIAL + + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_UART3 + bool "Enable UART3 (PC4/PC5)" + default n + select RT_USING_SERIAL + + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 + select RT_SERIAL_USING_DMA + default n + endif + endmenu + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + menu "Hardware I2C" + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + select RT_USING_I2C + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + select RT_USING_I2C + endmenu + + menu "Hardware CAN" + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + select RT_USING_CAN + endmenu + + menu "Hardware TIMER" + config BSP_USING_TIM1 + bool "Enable Timer1" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM3 + bool "Enable Timer3" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM6 + bool "Enable Timer6" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM14 + bool "Enable Timer14" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM15 + bool "Enable Timer15" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM16 + bool "Enable Timer16" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM17 + bool "Enable Timer17" + default n + select RT_USING_HWTIMER + endmenu + + menu "Hardware WDT" + config BSP_USING_WDT + bool "Enable Watch Dog Timer" + default n + select RT_USING_WDT + config BSP_USING_IWDT + bool "Enable Independent Watch Dog Timer" + default n + select RT_USING_WDT + endmenu + + config BSP_USING_LCD + bool "Enable LCD" + default n + + menu "Hardware SPI" + config BSP_USING_SPI1 + bool "Enable SPI1" + select RT_USING_SPI + default n + + if BSP_USING_SPI1 + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + default n + endif + + config BSP_USING_SPI2 + bool "Enable SPI2" + select RT_USING_SPI + default n + + if BSP_USING_SPI2 + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + default n + endif + endmenu + + menu "Hardware CRYPTO" + config BSP_USING_CRC + select RT_HWCRYPTO_USING_CRC + bool "Enable CRC" + default n + select RT_USING_HWCRYPTO + config BSP_USING_AES + select RT_HWCRYPTO_USING_AES + bool "Enable AES" + default n + select RT_USING_HWCRYPTO + + config BSP_USING_HRNG + select RT_HWCRYPTO_USING_RNG + bool "Enable HRNG" + default n + select RT_USING_HWCRYPTO + endmenu + + config BSP_USING_CMP + bool "Enable Analog Voltage Comparer" + default n + + config BSP_USING_OPA + bool "Enable Operational Amplifier" + default n + + config BSP_USING_TKEY + bool "Enable Touch Key" + select RT_USING_TOUCH + default n + + config BSP_USING_RPMU + bool "Enable RTC PMU" + select RT_USING_PM + default n + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu + diff --git a/bsp/acm32f0x0-nucleo/drivers/SConscript b/bsp/acm32f0x0-nucleo/drivers/SConscript new file mode 100644 index 0000000000..46b2007329 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/SConscript @@ -0,0 +1,16 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +#remove other no use files +#SrcRemove(src, '*.c') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') + + diff --git a/bsp/acm32f0x0-nucleo/drivers/board.c b/bsp/acm32f0x0-nucleo/drivers/board.c new file mode 100644 index 0000000000..28e8b77322 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/board.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-25 AisinoChip first implementation + */ + +#include +#include +#include "rtconfig.h" +#include "board.h" +#include + +#define SOC_SRAM_END_ADDR (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024) + +extern int rt_application_init(void); + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ + #pragma section="HEAP" +#else + extern int __bss_end; +#endif + +extern void rt_hw_uart_init(void); + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial EVB board. + */ +void rt_hw_board_init(void) +{ + /* system init, clock, NVIC */ + System_Init(); + + /* Configure the SysTick */ + SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND); + + rt_hw_uart_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + +#ifdef RT_USING_HEAP +#if defined(__CC_ARM) || defined(__CLANG_ARM) + rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR); +#else + /* init memory system */ + rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR); +#endif +#endif /* RT_USING_HEAP */ + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + diff --git a/bsp/acm32f0x0-nucleo/drivers/board.h b/bsp/acm32f0x0-nucleo/drivers/board.h new file mode 100644 index 0000000000..39032064cb --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/board.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-27 AisinoCip add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ACM32Fxx_HAL.h" + +/*-------------------------- UART CONFIG BEGIN --------------------------*/ + +/** After configuring corresponding UART or UART DMA, you can use it. + * + * STEP 1, define macro define related to the serial port opening based on the serial port number + * such as #define BSP_USING_UATR1 + * + * STEP 2, according to the corresponding pin of serial port, modify the related serial port information + * such as #define UART1_TX_PORT GPIOX -> GPIOA + * #define UART1_RX_PORT GPIOX -> GPIOA + * #define UART1_TX_PIN GPIO_PIN_X -> GPIO_PIN_9 + * #define UART1_RX_PIN GPIO_PIN_X -> GPIO_PIN_10 + * + * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings. + * RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode + * + * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file + * such as #define BSP_UART1_RX_USING_DMA + * + */ + +#if defined(BSP_USING_UART1) + #define UART1_TX_PORT GPIOA + #define UART1_RX_PORT GPIOA + #define UART1_TX_PIN GPIO_PIN_9 + #define UART1_RX_PIN GPIO_PIN_10 + + #if defined(BSP_UART1_RX_USING_DMA) + #define UART1_RX_DMA_INSTANCE DMA_Channel0 + #define UART1_RX_DMA_RCC BIT12 + #define UART1_RX_DMA_IRQ DMA_IRQn + #define UART1_RX_DMA_CHANNEL 0 + #define UART1_RX_DMA_REQUEST REQ6_UART1_RECV + #endif /* BSP_UART1_RX_USING_DMA */ + + #if defined(BSP_UART1_TX_USING_DMA) + #define UART1_TX_DMA_INSTANCE DMA_Channel1 + #define UART1_TX_DMA_RCC BIT12 + #define UART1_TX_DMA_IRQ DMA_IRQn + #define UART1_TX_DMA_CHANNEL 1 + #define UART1_TX_DMA_REQUEST REQ5_UART1_SEND + #endif /* BSP_UART1_TX_USING_DMA */ + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) + #define UART2_TX_PORT GPIOA + #define UART2_RX_PORT GPIOA + #define UART2_TX_PIN GPIO_PIN_2 + #define UART2_RX_PIN GPIO_PIN_3 + + #if defined(BSP_UART2_RX_USING_DMA) + #define UART2_RX_DMA_INSTANCE DMA_Channel0 + #define UART2_RX_DMA_RCC BIT12 + #define UART2_RX_DMA_IRQ DMA_IRQn + #define UART2_RX_DMA_CHANNEL 0 + #define UART2_RX_DMA_REQUEST REQ8_UART2_RECV + #endif /* BSP_UART2_RX_USING_DMA */ + + #if defined(BSP_UART2_TX_USING_DMA) + #define UART2_TX_DMA_INSTANCE DMA_Channel1 + #define UART2_TX_DMA_RCC BIT12 + #define UART2_TX_DMA_IRQ DMA_IRQn + #define UART2_TX_DMA_CHANNEL 1 + #define UART2_TX_DMA_REQUEST REQ7_UART2_SEND + #endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) + #define UART3_TX_PORT GPIOB + #define UART3_RX_PORT GPIOB + #define UART3_TX_PIN GPIO_PIN_10 + #define UART3_RX_PIN GPIO_PIN_11 + + #if defined(BSP_UART3_RX_USING_DMA) + #define UART3_RX_DMA_INSTANCE DMA_Channel0 + #define UART3_RX_DMA_RCC BIT12 + #define UART3_RX_DMA_IRQ DMA_IRQn + #define UART3_RX_DMA_CHANNEL 2 + #define UART3_RX_DMA_REQUEST REQ29_UART3_RECV + #endif /* BSP_UART3_RX_USING_DMA */ + + #if defined(BSP_UART3_TX_USING_DMA) + #define UART3_TX_DMA_INSTANCE DMA_Channel1 + #define UART3_TX_DMA_RCC BIT12 + #define UART3_TX_DMA_IRQ DMA_IRQn + #define UART3_TX_DMA_CHANNEL 3 + #define UART3_TX_DMA_REQUEST REQ27_UART3_SEND + #endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ +/*-------------------------- UART CONFIG END --------------------------*/ + +/* board configuration */ + +void rt_hw_board_init(void); + +#endif /* __BOARD_H__ */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_adc.c b/bsp/acm32f0x0-nucleo/drivers/drv_adc.c new file mode 100644 index 0000000000..7f7675beaa --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_adc.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 AisinoChip first implementation + */ + +#include +#include +#include + +#define ADC_NAME "adc" + +#if defined(BSP_USING_ADC) + +struct acm32_adc +{ + ADC_HandleTypeDef handle; + struct rt_adc_device acm32_adc_device; +}; + +static struct acm32_adc acm32_adc_obj = {0}; + +static rt_err_t acm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + struct acm32_adc *adcObj = RT_NULL; + + RT_ASSERT(device != RT_NULL); + + adcObj = rt_container_of(device, struct acm32_adc, acm32_adc_device); + + if (enabled) + { + /* channel enabled */ + if (0 != (adcObj->handle.Init.ChannelEn & (1 << channel))) + { + return RT_EOK; + } + + adcObj->handle.Instance = ADC; + adcObj->handle.Init.ClockDiv = ADC_CLOCK_DIV8; + adcObj->handle.Init.ConConvMode = ADC_CONCONVMODE_DISABLE; + adcObj->handle.Init.JChannelMode = ADC_JCHANNELMODE_DISABLE; + adcObj->handle.Init.DiffMode = ADC_DIFFMODE_DISABLE; + adcObj->handle.Init.DMAMode = ADC_DMAMODE_DISABLE; + adcObj->handle.Init.OverMode = ADC_OVERMODE_DISABLE; + adcObj->handle.Init.OverSampMode = ADC_OVERSAMPMODE_DISABLE; + adcObj->handle.Init.AnalogWDGEn = ADC_ANALOGWDGEN_DISABLE; + adcObj->handle.Init.ExTrigMode.ExTrigSel = ADC_SOFTWARE_START; + adcObj->handle.Init.ChannelEn |= 1 << channel; + + HAL_ADC_Init(&adcObj->handle); + + adcObj->handle.ChannelNum ++; + } + else + { + /* channel disabled */ + if (0 == (adcObj->handle.Init.ChannelEn & (1 << channel))) + { + return RT_EOK; + } + adcObj->handle.Init.ChannelEn &= ~(1 << channel); + adcObj->handle.ChannelNum --; + } + + return RT_EOK; +} + +static rt_err_t acm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + struct acm32_adc *adcObj = RT_NULL; + ADC_ChannelConfTypeDef channelConf = {0}; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + if (channel > ADC_CHANNEL_15) + { + return -RT_ERROR; + } + *value = RT_UINT32_MAX; + adcObj = rt_container_of(device, struct acm32_adc, acm32_adc_device); + + /* channel disabled */ + if (0 == (adcObj->handle.Init.ChannelEn & (1 << channel))) + { + return -RT_ERROR; + } + + channelConf.Channel = channel; + channelConf.RjMode = 0; + channelConf.Sq = ADC_SEQUENCE_SQ1; + channelConf.Smp = ADC_SMP_CLOCK_320; + HAL_ADC_ConfigChannel(&adcObj->handle, &channelConf); + + if (HAL_OK != HAL_ADC_Polling(&adcObj->handle, (uint32_t *)value, 1, 100)) + { + return -RT_ERROR; + } + *value &= ~(HAL_ADC_EOC_FLAG); + + return RT_EOK; +} + +static const struct rt_adc_ops acm_adc_ops = +{ + .enabled = acm32_adc_enabled, + .convert = acm32_get_adc_value, +}; + +static int acm32_adc_init(void) +{ + return rt_hw_adc_register(&acm32_adc_obj.acm32_adc_device, + ADC_NAME, + &acm_adc_ops, + RT_NULL); +} +INIT_BOARD_EXPORT(acm32_adc_init); + +#endif /* BSP_USING_ADC */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_gpio.c b/bsp/acm32f0x0-nucleo/drivers/drv_gpio.c new file mode 100644 index 0000000000..b26b837d79 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_gpio.c @@ -0,0 +1,460 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-26 AisinoChip first version + */ + +#include +#include +#include +#include +#include "board.h" + +#ifdef RT_USING_PIN + +#include + +#define __ACM32_PIN(index, gpio, gpio_index) \ + { \ + index, GPIO##gpio, GPIO_PIN_##gpio_index \ + } + +#define __ACM32_PIN_RESERVE \ + { \ + -1, 0, 0 \ + } + +/* ACM32 GPIO driver */ +struct pin_index +{ + int index; + enum_GPIOx_t gpio; + uint32_t pin; +}; + +struct pin_irq_map +{ + rt_uint16_t line; + EXTI_HandleTypeDef handle; +}; + +static const struct pin_index pins[] = +{ +#if defined(BSP_USING_GPIO1) + __ACM32_PIN(0, A, 0), + __ACM32_PIN(1, A, 1), + __ACM32_PIN(2, A, 2), + __ACM32_PIN(3, A, 3), + __ACM32_PIN(4, A, 4), + __ACM32_PIN(5, A, 5), + __ACM32_PIN(6, A, 6), + __ACM32_PIN(7, A, 7), + __ACM32_PIN(8, A, 8), + __ACM32_PIN(9, A, 9), + __ACM32_PIN(10, A, 10), + __ACM32_PIN(11, A, 11), + __ACM32_PIN(12, A, 12), + __ACM32_PIN(13, A, 13), + __ACM32_PIN(14, A, 14), + __ACM32_PIN(15, A, 15), + __ACM32_PIN(16, B, 0), + __ACM32_PIN(17, B, 1), + __ACM32_PIN(18, B, 2), + __ACM32_PIN(19, B, 3), + __ACM32_PIN(20, B, 4), + __ACM32_PIN(21, B, 5), + __ACM32_PIN(22, B, 6), + __ACM32_PIN(23, B, 7), + __ACM32_PIN(24, B, 8), + __ACM32_PIN(25, B, 9), + __ACM32_PIN(26, B, 10), + __ACM32_PIN(27, B, 11), + __ACM32_PIN(28, B, 12), + __ACM32_PIN(29, B, 13), + __ACM32_PIN(30, B, 14), + __ACM32_PIN(31, B, 15), +#if defined(BSP_USING_GPIO2) + __ACM32_PIN(32, C, 0), + __ACM32_PIN(33, C, 1), + __ACM32_PIN(34, C, 2), + __ACM32_PIN(35, C, 3), + __ACM32_PIN(36, C, 4), + __ACM32_PIN(37, C, 5), + __ACM32_PIN(38, C, 6), + __ACM32_PIN(39, C, 7), + __ACM32_PIN(40, C, 8), + __ACM32_PIN(41, C, 9), + __ACM32_PIN(42, C, 10), + __ACM32_PIN(43, C, 11), + __ACM32_PIN(44, C, 12), + __ACM32_PIN(45, C, 13), + __ACM32_PIN(46, C, 14), + __ACM32_PIN(47, C, 15), + __ACM32_PIN(48, D, 0), + __ACM32_PIN(49, D, 1), + __ACM32_PIN(50, D, 2), + __ACM32_PIN(51, D, 3), + __ACM32_PIN(52, D, 4), + __ACM32_PIN(53, D, 5), + __ACM32_PIN(54, D, 6), + __ACM32_PIN(55, D, 7), + __ACM32_PIN(56, D, 8), + __ACM32_PIN(57, D, 9), + __ACM32_PIN(58, D, 10), + __ACM32_PIN(59, D, 11), + __ACM32_PIN(60, D, 12), + __ACM32_PIN(61, D, 13), + __ACM32_PIN(62, D, 14), + __ACM32_PIN(63, D, 15), +#endif /* defined(BSP_USING_GPIO2) */ +#endif /* defined(BSP_USING_GPIO1) */ +}; + +static struct pin_irq_map pin_irq_map[] = +{ + {EXTI_LINE_0, {0}}, + {EXTI_LINE_1, {0}}, + {EXTI_LINE_2, {0}}, + {EXTI_LINE_3, {0}}, + {EXTI_LINE_4, {0}}, + {EXTI_LINE_5, {0}}, + {EXTI_LINE_6, {0}}, + {EXTI_LINE_7, {0}}, + {EXTI_LINE_8, {0}}, + {EXTI_LINE_9, {0}}, + {EXTI_LINE_10, {0}}, + {EXTI_LINE_11, {0}}, + {EXTI_LINE_12, {0}}, + {EXTI_LINE_13, {0}}, + {EXTI_LINE_14, {0}}, + {EXTI_LINE_15, {0}}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +static const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void acm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value); +} + +static int acm32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = HAL_GPIO_ReadPin(index->gpio, index->pin); + + return value; +} + +static void acm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_0; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + + /* special PIN process */ + __HAL_RTC_PC13_DIGIT(); + + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); +} + +#define PIN2INDEX(pin) ((pin) % 16) + +static rt_err_t acm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t acm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t acm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + irqmap = &pin_irq_map[irqindex]; + + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_0; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + + irqmap->handle.u32_Line = irqmap->line; + irqmap->handle.u32_Mode = EXTI_MODE_INTERRUPT; + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Pull = GPIO_PULLUP; + irqmap->handle.u32_Trigger = EXTI_TRIGGER_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Pull = GPIO_NOPULL; + irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING_FALLING; + break; + } + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); + + irqmap->handle.u32_GPIOSel = pin / 16; + + HAL_EXTI_SetConfigLine(&irqmap->handle); + + pin_irq_enable_mask |= 1 << irqindex; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + if ((pin_irq_enable_mask & (1 << irqindex)) == 0) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + EXTI->IENR &= ~irqmap->line; + EXTI->EENR &= ~irqmap->line; + + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} + +const static struct rt_pin_ops _acm32_pin_ops = +{ + acm32_pin_mode, + acm32_pin_write, + acm32_pin_read, + acm32_pin_attach_irq, + acm32_pin_dettach_irq, + acm32_pin_irq_enable, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +void EXTI_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + for (int i = 0; i < 16; i++) + { + if (EXTI->PDR & pin_irq_map[i].line) + { + EXTI->PDR = pin_irq_map[i].line; + pin_irq_hdr(i); + break; + } + } + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_PIN */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c b/bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c new file mode 100644 index 0000000000..1d168c10de --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-26 AisinoChip first version + */ + +#include +#include +#include + +#ifdef BSP_USING_TIM +#include "tim_config.h" + +#ifdef RT_USING_HWTIMER +enum +{ +#ifdef BSP_USING_TIM1 + TIM1_INDEX, +#endif +#ifdef BSP_USING_TIM3 + TIM3_INDEX, +#endif +#ifdef BSP_USING_TIM6 + TIM6_INDEX, +#endif +#ifdef BSP_USING_TIM14 + TIM14_INDEX, +#endif +#ifdef BSP_USING_TIM15 + TIM15_INDEX, +#endif +#ifdef BSP_USING_TIM16 + TIM16_INDEX, +#endif +#ifdef BSP_USING_TIM17 + TIM17_INDEX, +#endif +}; + +struct acm32_hwtimer +{ + rt_hwtimer_t time_device; + TIM_HandleTypeDef tim_handle; + IRQn_Type tim_irqn; + char *name; +}; + +static struct acm32_hwtimer acm32_hwtimer_obj[] = +{ +#ifdef BSP_USING_TIM1 + TIM1_CONFIG, +#endif + +#ifdef BSP_USING_TIM3 + TIM3_CONFIG, +#endif + +#ifdef BSP_USING_TIM6 + TIM6_CONFIG, +#endif + +#ifdef BSP_USING_TIM14 + TIM14_CONFIG, +#endif + +#ifdef BSP_USING_TIM15 + TIM15_CONFIG, +#endif + +#ifdef BSP_USING_TIM16 + TIM16_CONFIG, +#endif + +#ifdef BSP_USING_TIM17 + TIM17_CONFIG, +#endif +}; + +static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ + rt_uint32_t timer_clock = 0; + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + if (state) + { + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + /* time init */ + timer_clock = System_Get_APBClock(); + if (System_Get_SystemClock() != System_Get_APBClock()) /* if hclk/pclk != 1, then timer clk = pclk * 2 */ + { + timer_clock = System_Get_APBClock() << 1; + } + + tim->Init.Period = (timer->freq) - 1; + tim->Init.Prescaler = (timer_clock / timer->freq) - 1 ; + + tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + { + tim->Init.CounterMode = TIM_COUNTERMODE_UP; + } + else + { + tim->Init.CounterMode = TIM_COUNTERMODE_DOWN; + } + tim->Init.RepetitionCounter = 0; + tim->Init.ARRPreLoadEn = TIM_ARR_PRELOAD_ENABLE; + + HAL_TIMER_MSP_Init(tim); + HAL_TIMER_Base_Init(tim); + } +} + +static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +{ + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + /* set tim cnt */ + tim->Instance->CNT = 0; + /* set tim arr */ + tim->Instance->ARR = t - 1; + + if (opmode == HWTIMER_MODE_ONESHOT) + { + /* set timer to single mode */ + SET_BIT(tim->Instance->CR1, BIT3); + } + else + { + /* set timer to period mode */ + CLEAR_BIT(tim->Instance->CR1, BIT3); + } + + /* enable IRQ */ + HAL_TIM_ENABLE_IT(tim, TIMER_INT_EN_UPD); + + /* start timer */ + HAL_TIMER_Base_Start(tim->Instance); + + return RT_EOK; +} + +static void timer_stop(rt_hwtimer_t *timer) +{ + TIM_HandleTypeDef *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + /* stop timer */ + HAL_TIMER_Base_Stop(tim->Instance); +} + +static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +{ + TIM_HandleTypeDef *tim = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(arg != RT_NULL); + + tim = (TIM_HandleTypeDef *)timer->parent.user_data; + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + rt_uint32_t timer_clock; + rt_uint16_t val; + + /* set timer frequence */ + freq = *((rt_uint32_t *)arg); + + timer_clock = System_Get_APBClock(); + if (System_Get_SystemClock() != System_Get_APBClock()) /* if hclk/pclk != 1, then timer clk = pclk * 2 */ + { + timer_clock = System_Get_APBClock() << 1; + } + + val = timer_clock / freq; + tim->Instance->PSC = val - 1; + + /* Update frequency value */ + tim->Instance->CR1 = BIT2; /* CEN=0, URS=1, OPM = 0 */ + tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE; + } + break; + default: + { + result = -RT_ENOSYS; + } + break; + } + + return result; +} + +static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +{ + RT_ASSERT(timer != RT_NULL); + + return ((TIM_HandleTypeDef *)timer->parent.user_data)->Instance->CNT; +} + +static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; + +static const struct rt_hwtimer_ops _ops = +{ + .init = timer_init, + .start = timer_start, + .stop = timer_stop, + .count_get = timer_counter_get, + .control = timer_ctrl, +}; + +#ifdef BSP_USING_TIM1 +void TIM1_BRK_UP_TRG_COM_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* interrupt service routine */ + if (TIM1->SR & TIMER_SR_UIF) + { + rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM1_INDEX].time_device); + } + + TIM1->SR = 0; /* write 0 to clear hardware flag */ + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIM3 +void TIM3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (TIM3->SR & TIMER_SR_UIF) + { + rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM3_INDEX].time_device); + } + + TIM3->SR = 0; /* write 0 to clear hardware flag */ + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIM6 +void TIM6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* interrupt service routine */ + if (TIM6->SR & TIMER_SR_UIF) + { + rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM6_INDEX].time_device); + } + TIM6->SR = 0; /* write 0 to clear hardware flag */ + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM14 +void TIM14_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* interrupt service routine */ + if (TIM14->SR & TIMER_SR_UIF) + { + rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM14_INDEX].time_device); + } + TIM14->SR = 0; /* write 0 to clear hardware flag */ + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM15 +void TIM15_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* interrupt service routine */ + if (TIM15->SR & TIMER_SR_UIF) + { + rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM15_INDEX].time_device); + } + TIM15->SR = 0; /* write 0 to clear hardware flag */ + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM16 +void TIM16_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if (TIM16->SR & TIMER_SR_UIF) + { + rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM16_INDEX].time_device); + } + TIM16->SR = 0; /* write 0 to clear hardware flag */ + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_TIM17 +void TIM17_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if (TIM17->SR & TIMER_SR_UIF) + { + rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM17_INDEX].time_device); + } + TIM17->SR = 0; /* write 0 to clear hardware flag */ + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +static int acm32_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(acm32_hwtimer_obj) / sizeof(acm32_hwtimer_obj[0]); i++) + { + acm32_hwtimer_obj[i].time_device.info = &_info; + acm32_hwtimer_obj[i].time_device.ops = &_ops; + result = rt_device_hwtimer_register(&acm32_hwtimer_obj[i].time_device, + acm32_hwtimer_obj[i].name, + &acm32_hwtimer_obj[i].tim_handle); + if (result != RT_EOK) + { + result = -RT_ERROR; + break; + } + } + + return result; +} +INIT_BOARD_EXPORT(acm32_hwtimer_init); + +#endif /* RT_USING_HWTIMER */ +#endif /* BSP_USING_TIM */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_uart.c b/bsp/acm32f0x0-nucleo/drivers/drv_uart.c new file mode 100644 index 0000000000..f84d0c9874 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_uart.c @@ -0,0 +1,632 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 AisinoChip the first version + */ + +#include +#include +#include +#include "rtconfig.h" +#include "board.h" +#include "uart_config.h" + +#ifdef RT_USING_SERIAL + +#ifdef RT_SERIAL_USING_DMA +struct dma_config +{ + DMA_Channel_TypeDef *Instance; + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + + rt_uint32_t channel; + rt_uint32_t request; +}; +#endif + +#ifdef RT_SERIAL_USING_DMA + static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag); +#endif /* RT_SERIAL_USING_DMA */ + +struct acm32_uart_config +{ + const char *name; + UART_TypeDef *Instance; + IRQn_Type irq_type; + enum_Enable_ID_t enable_id; + +#ifdef RT_SERIAL_USING_DMA + struct dma_config *dma_rx; + struct dma_config *dma_tx; +#endif + + enum_GPIOx_t tx_port; + enum_GPIOx_t rx_port; + rt_uint32_t tx_pin; + rt_uint32_t rx_pin; +}; + +struct acm32_uart +{ + UART_HandleTypeDef handle; + struct acm32_uart_config *config; +#ifdef RT_SERIAL_USING_DMA + struct + { + DMA_HandleTypeDef handle; + rt_size_t last_index; + } dma_rx; + + struct + { + DMA_HandleTypeDef handle; + } dma_tx; +#endif + + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size) +{ + return RT_EOK; +} + +static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + uart->handle.Instance = uart->config->Instance; + + uart->handle.Init.BaudRate = cfg->baud_rate; + if (cfg->data_bits == DATA_BITS_8) + { + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + } + else /* not support */ + { + return -RT_EINVAL; + } + + if (cfg->stop_bits == STOP_BITS_1) + { + uart->handle.Init.StopBits = UART_STOPBITS_1; + } + else if (cfg->stop_bits == STOP_BITS_2) + { + uart->handle.Init.StopBits = UART_STOPBITS_2; + } + else /* not support */ + { + return -RT_EINVAL; + } + + if (cfg->parity == PARITY_NONE) + { + uart->handle.Init.Parity = UART_PARITY_NONE; + } + else if (cfg->parity == PARITY_ODD) + { + uart->handle.Init.Parity = UART_PARITY_ODD; + } + else if (cfg->parity == PARITY_EVEN) + { + uart->handle.Init.Parity = UART_PARITY_EVEN; + } + else /* not support */ + { + return -RT_EINVAL; + } + + uart->handle.Init.Mode = UART_MODE_TX_RX; + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + + HAL_UART_Init(&uart->handle); + + uart->handle.Instance->LCRH &= ~UART_LCRH_FEN; + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct acm32_uart *uart; +#ifdef RT_SERIAL_USING_DMA + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#endif + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + NVIC_DisableIRQ(uart->config->irq_type); + /* Disable RX interrupt */ + uart->handle.Instance->IE &= ~UART_IE_RXI; + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + NVIC_EnableIRQ(uart->config->irq_type); + /* Enable RX interrupt */ + uart->handle.Instance->IE |= UART_IE_RXI; + break; +#ifdef RT_SERIAL_USING_DMA + /* UART config */ + case RT_DEVICE_CTRL_CONFIG : + DMA_Configuration(serial, (rt_uint32_t)ctrl_arg); + rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb); + break; +#endif /* RT_SERIAL_USING_DMA */ + } + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial, char c) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + while (uart->handle.Instance->FR & UART_FR_TXFF); /* wait Tx FIFO not full */ + uart->handle.Instance->DR = c; + while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */ + + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + + int ch; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + ch = -1; + if (!(uart->handle.Instance->FR & UART_FR_RXFE)) /* Rx FIFO not empty */ + { + ch = uart->handle.Instance->DR & 0xff; + } + + return ch; +} + +#ifdef RT_SERIAL_USING_DMA +/** + * Serial port receive idle process. This need add to uart idle ISR. + * + * @param serial serial device + */ +static void dma_uart_rx_idle_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + rt_size_t recv_total_index, recv_len; + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF); + recv_len = recv_total_index - uart->handle.lu32_RxCount; + uart->handle.lu32_RxCount = recv_total_index; + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +/* + DMA receive done process. This need add to DMA receive done ISR. + + @param serial serial device +*/ +static void dma_rx_done_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + rt_size_t recv_len; + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF); + uart->dma_rx.last_index = 0; + + DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel); /* clear channel0 TC flag */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + + HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz); +} + +static rt_size_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + struct acm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct acm32_uart, serial); + + if (size == 0) + { + return 0; + } + + if (RT_SERIAL_DMA_TX == direction) + { + if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); + return size; + } + else + { + return 0; + } + } + return 0; +} + +#endif /* RT_SERIAL_USING_DMA */ + +static const struct rt_uart_ops acm32_uart_ops = +{ + _uart_configure, + _uart_control, + _uart_putc, + _uart_getc, +#ifdef RT_SERIAL_USING_DMA + _uart_dma_transmit, +#endif +}; + +#ifdef RT_SERIAL_USING_DMA +static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag) +{ + struct rt_serial_rx_fifo *rx_fifo; + DMA_HandleTypeDef *DMA_Handle; + struct dma_config *dma_config; + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle = &uart->dma_rx.handle; + dma_config = uart->config->dma_rx; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle = &uart->dma_tx.handle; + dma_config = uart->config->dma_tx; + } + else + { + return; + } + + DMA_Handle->Instance = dma_config->Instance; + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_P2M; + DMA_Handle->Init.Mode = DMA_NORMAL; + DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE; + DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE; + + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_M2P; + DMA_Handle->Init.Mode = DMA_NORMAL; + DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_ENABLE; + DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_DISABLE; + } + + DMA_Handle->Init.Request_ID = dma_config->request; + DMA_Handle->Init.Source_Width = DMA_SRC_WIDTH_BYTE; + DMA_Handle->Init.Desination_Width = DMA_DST_WIDTH_BYTE; + + if (HAL_DMA_Init(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + __HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle); + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + __HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle); + } + /* enable interrupt */ + if (flag == RT_DEVICE_FLAG_DMA_RX) + { + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + /* Start DMA transfer */ + if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK) + { + /* Transfer error in reception process */ + RT_ASSERT(0); + } + + } +} +#endif /* RT_SERIAL_USING_DMA */ + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif + UART_MAX_INDEX, +}; + +static struct acm32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif +}; + +static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +#ifdef RT_SERIAL_USING_DMA +static void uart_get_dma_config(void) +{ +#if defined(BSP_USING_UART1) +#if defined(BSP_UART1_RX_USING_DMA) + static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf; +#endif /* BSP_UART1_RX_USING_DMA */ +#if defined(BSP_UART1_TX_USING_DMA) + static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf; +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#if defined(BSP_UART2_RX_USING_DMA) + static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf; +#endif /* BSP_UART2_RX_USING_DMA */ +#if defined(BSP_UART2_TX_USING_DMA) + static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf; +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#if defined(BSP_UART3_RX_USING_DMA) + static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf; +#endif /* BSP_UART3_RX_USING_DMA */ +#if defined(BSP_UART3_TX_USING_DMA) + static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf; +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ +} +#endif + +rt_err_t rt_hw_uart_init(void) +{ + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t rc = RT_EOK; + +#ifdef RT_SERIAL_USING_DMA + uart_get_dma_config(); +#endif + + for (int i = 0; i < obj_num; i++) + { + uart_obj[i].config = &uart_config[i]; + + uart_obj[i].serial.ops = &acm32_uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR + | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX + | uart_obj[i].uart_dma_flag + , NULL); + RT_ASSERT(rc == RT_EOK); + } + + return rc; +} + +static void uart_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial); + + RT_ASSERT(serial != RT_NULL); + + /* receive interrupt enabled */ + if (uart->handle.Instance->IE & UART_IE_RXI) + { + if (uart->handle.Instance->RIS & UART_RIS_RXI) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + } + +#ifdef RT_SERIAL_USING_DMA + if (uart->handle.Instance->IE & UART_IE_RTI) /* Receive TimeOut Interrupt */ + { + dma_uart_rx_idle_isr(serial); + /* Clear RTI Status */ + uart->handle.Instance->ICR = UART_ICR_RTI; + } +#endif /* RT_SERIAL_USING_DMA */ + + if (uart->handle.Instance->IE & UART_IE_TXI && \ + uart->handle.Instance->RIS & UART_RIS_TXI) + { + /* Clear TXI Status */ + uart->handle.Instance->ICR = UART_ICR_TXI; + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + /* Disable TX interrupt */ + uart->handle.Instance->IE &= ~UART_IE_TXI; + } +} + +#if defined(BSP_USING_UART1) +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART1_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART2_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART3) +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART3_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#ifdef RT_SERIAL_USING_DMA +void DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + for (int i = 0; i < UART_MAX_INDEX; i++) + { + if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel)) + { + dma_rx_done_isr(&uart_obj[i].serial); + break; + } + + if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel)) + { + DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel); /* clear channel0 TC flag */ + break; + } + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_SERIAL_USING_DMA */ + +void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + struct acm32_uart *uart; + GPIO_InitTypeDef GPIO_Uart; + + RT_ASSERT(huart != RT_NULL); + + /* get uart object */ + uart = rt_container_of(huart, struct acm32_uart, handle); + + /* Enable Clock */ + System_Module_Enable(uart->config->enable_id); + + /* Initialization GPIO */ + GPIO_Uart.Pin = uart->config->tx_pin; + GPIO_Uart.Mode = GPIO_MODE_AF_PP; + GPIO_Uart.Pull = GPIO_PULLUP; + GPIO_Uart.Alternate = GPIO_FUNCTION_2; + HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart); + + GPIO_Uart.Pin = uart->config->rx_pin; + GPIO_Uart.Mode = GPIO_MODE_AF_PP; + GPIO_Uart.Pull = GPIO_PULLUP; + GPIO_Uart.Alternate = GPIO_FUNCTION_2; + HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart); + + /* NVIC Config */ + NVIC_ClearPendingIRQ(uart->config->irq_type); + NVIC_SetPriority(uart->config->irq_type, 5); + NVIC_EnableIRQ(uart->config->irq_type); +} + +#endif /* RT_USING_SEARIAL */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_wdt.c b/bsp/acm32f0x0-nucleo/drivers/drv_wdt.c new file mode 100644 index 0000000000..6ea8767692 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_wdt.c @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-25 AisinoChip First Version + */ + +#include +#include +#include + + +#ifdef RT_USING_WDT +#include "board.h" + +struct acm32_wdt_obj +{ + union + { + WDT_HandleTypeDef wdt; + IWDT_HandleTypeDef iwdt; + } handle; + rt_uint16_t is_start; + rt_uint16_t type; + rt_watchdog_t watchdog; +}; + +#define TYPE_WDT 0 +#define TYPE_IWDT 1 +#define IWDT_FREQ (32000) + +#ifdef BSP_USING_WDT + #define WDT_NAME "wdt" + static struct acm32_wdt_obj acm32_wdt; +#endif + +#ifdef BSP_USING_IWDT + #define IWDT_NAME "iwdt" + static struct acm32_wdt_obj acm32_iwdt; +#endif + +static struct rt_watchdog_ops ops; + +rt_inline rt_base_t calc_wdt_divisor_load(rt_uint32_t freq, rt_uint32_t sec, rt_uint32_t *divisor, rt_uint32_t *load) +{ + rt_uint32_t freqMaxSec = 0; + rt_uint32_t minFreqDiv = WDT_DIVISOR_NONE; + + freqMaxSec = RT_UINT32_MAX / freq; + + while (minFreqDiv <= WDT_DIVISOR_128) + { + if (sec < freqMaxSec) + { + break; + } + minFreqDiv ++; + freqMaxSec = RT_UINT32_MAX / freq * (1 << minFreqDiv); + } + + if (minFreqDiv > WDT_DIVISOR_128) + { + return -1; + } + + *divisor = minFreqDiv; + *load = sec * (freq >> minFreqDiv); + return 0; +} + +rt_inline rt_base_t calc_iwdt_divisor_load(rt_uint32_t freq, rt_uint32_t sec, rt_uint32_t *divisor, rt_uint32_t *load) +{ + rt_uint32_t minFreqDiv = IWDT_CLOCK_PRESCALER_4; + rt_uint32_t freqMaxMs = 0; + + freqMaxMs = IWDT_RELOAD_MAX_VALUE * 1000 / (freq >> (2 + minFreqDiv)); + + while (minFreqDiv <= IWDT_CLOCK_PRESCALER_256) + { + if (sec * 1000 < freqMaxMs) + { + break; + } + minFreqDiv ++; + freqMaxMs = IWDT_RELOAD_MAX_VALUE * 1000 / (freq >> (2 + minFreqDiv)); + } + + if (minFreqDiv > IWDT_CLOCK_PRESCALER_256) + { + return -1; + } + + *divisor = minFreqDiv; + if (sec < 1000) + { + *load = (sec * 1000) * IWDT_RELOAD_MAX_VALUE / freqMaxMs; + } + else + { + *load = (sec) * IWDT_RELOAD_MAX_VALUE / freqMaxMs / 1000; + } + return 0; +} + +rt_inline rt_uint32_t calc_wdt_timeout(rt_uint32_t freq, rt_uint32_t divisor, rt_uint32_t count) +{ + /* 1 / ( freq / (1<> (2+divisor)) / IWDT_RELOAD_MAX_VALUE * count */ + return count / (freq >> (2 + divisor)); +} + +static rt_err_t wdt_init(rt_watchdog_t *wdt) +{ + return RT_EOK; +} + +static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + struct acm32_wdt_obj *wdtObj = NULL; + rt_uint32_t timer_clk_hz; + rt_uint32_t divisor, load; + + RT_ASSERT(wdt != RT_NULL); + + wdtObj = rt_container_of(wdt, struct acm32_wdt_obj, watchdog); + timer_clk_hz = System_Get_APBClock(); + + switch (cmd) + { + /* feed the watchdog */ + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + if (TYPE_WDT == wdtObj->type) + { + HAL_WDT_Feed(&wdtObj->handle.wdt); + } + else + { + HAL_IWDT_Kick_Watchdog_Wait_For_Done(&wdtObj->handle.iwdt); + } + break; + /* set watchdog timeout, seconds */ + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + if (TYPE_WDT == wdtObj->type) + { + if (calc_wdt_divisor_load(timer_clk_hz, (*((rt_uint32_t *)arg)), &divisor, &load)) + { + return -RT_ERROR; + } + wdtObj->handle.wdt.Init.WDTDivisor = (WDT_DIVISOR)divisor; + wdtObj->handle.wdt.Init.WDTLoad = load; + HAL_WDT_Init(&wdtObj->handle.wdt); + } + else + { + if (calc_iwdt_divisor_load(IWDT_FREQ, (*((rt_uint32_t *)arg)), &divisor, &load)) + { + return -RT_ERROR; + } + wdtObj->handle.iwdt.Instance = IWDT; + wdtObj->handle.iwdt.Init.Prescaler = divisor; + wdtObj->handle.iwdt.Init.Reload = load; + } + + if (wdtObj->is_start) + { + if (TYPE_WDT == wdtObj->type) + { + HAL_WDT_Init(&wdtObj->handle.wdt); + } + else + { + HAL_IWDT_Init(&wdtObj->handle.iwdt); + } + } + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + if (TYPE_WDT == wdtObj->type) + { + (*((rt_uint32_t *)arg)) = calc_wdt_timeout(timer_clk_hz, + wdtObj->handle.wdt.Init.WDTDivisor, + wdtObj->handle.wdt.Instance->COUNT); + } + else + { + return -RT_EINVAL; + } + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + if (TYPE_WDT == wdtObj->type) + { + (*((rt_uint32_t *)arg)) = calc_wdt_timeout(timer_clk_hz, + wdtObj->handle.wdt.Init.WDTDivisor, + wdtObj->handle.wdt.Init.WDTLoad); + } + else + { + (*((rt_uint32_t *)arg)) = calc_iwdt_timeout(IWDT_FREQ, + wdtObj->handle.iwdt.Init.Prescaler, + wdtObj->handle.iwdt.Init.Reload); + } + break; + case RT_DEVICE_CTRL_WDT_START: + if (TYPE_WDT == wdtObj->type) + { + wdtObj->handle.wdt.Instance = WDT; + wdtObj->handle.wdt.Init.WDTMode = WDT_MODE_RST; + wdtObj->handle.wdt.Init.WDTINTCLRTIME = 0xffff; + HAL_WDT_Init(&wdtObj->handle.wdt); + HAL_WDT_Start(&wdtObj->handle.wdt); + } + else + { + wdtObj->handle.iwdt.Instance->CMDR = IWDT_ENABLE_COMMAND; + wdtObj->handle.iwdt.Init.Window = IWDT_RELOAD_MAX_VALUE; /* window function disabled when window >= reload */ + wdtObj->handle.iwdt.Init.Wakeup = IWDT_RELOAD_MAX_VALUE; /* wakeup function disabled when wakeup >= reload */ + HAL_IWDT_Init(&wdtObj->handle.iwdt); + } + wdtObj->is_start = 1; + break; + case RT_DEVICE_CTRL_WDT_STOP: + if (TYPE_WDT == wdtObj->type) + { + HAL_WDT_Stop(&wdtObj->handle.wdt); + } + else + { + wdtObj->handle.iwdt.Instance->CMDR = IWDT_DISABLE_COMMAND; + } + wdtObj->is_start = 0; + break; + default: + return -RT_ERROR; + } + return RT_EOK; +} + +int rt_wdt_init(void) +{ + ops.init = &wdt_init; + ops.control = &wdt_control; + +#ifdef BSP_USING_WDT + acm32_wdt.type = TYPE_WDT; + acm32_wdt.is_start = 0; + acm32_wdt.watchdog.ops = &ops; + if (rt_hw_watchdog_register(&acm32_wdt.watchdog, WDT_NAME, RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) + { + return -RT_ERROR; + } +#endif +#ifdef BSP_USING_IWDT + acm32_iwdt.type = TYPE_IWDT; + acm32_iwdt.is_start = 0; + acm32_iwdt.watchdog.ops = &ops; + if (rt_hw_watchdog_register(&acm32_iwdt.watchdog, IWDT_NAME, RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) + { + return -RT_ERROR; + } +#endif + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_wdt_init); + +#endif /* RT_USING_WDT */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.icf b/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000..bf3975c7e7 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0800; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; + diff --git a/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.lds b/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.lds new file mode 100644 index 0000000000..a2e80b263f --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.lds @@ -0,0 +1,155 @@ +/* + * linker script for ACM32F030 with GNU ld + */ + +/* describes the location and size of blocks of memory in the target. */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 128k /* 128KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 32k /* 32KB sram */ +} +/* Program Entry, set to mark it as "used" and avoid gc */ +ENTRY(Reset_Handler) +_system_stack_size = 0x800; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + _etext = .; + } > ROM = 8 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } > RAM + + .stack : + { + . = ALIGN(8); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(8); + _estack = .; + } > RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.sct b/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000..02415a94c7 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/linker_scripts/link.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00008000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/acm32f0x0-nucleo/drivers/tim_config.h b/bsp/acm32f0x0-nucleo/drivers/tim_config.h new file mode 100644 index 0000000000..5ae9cf3c6b --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/tim_config.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-26 AisinoChip first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 2000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM1 +#ifndef TIM1_CONFIG +#define TIM1_CONFIG \ + { \ + .tim_handle.Instance = TIM1, \ + .tim_irqn = TIM1_BRK_UP_TRG_COM_IRQn, \ + .name = "timer1", \ + } +#endif /* TIM1_CONFIG */ +#endif /* BSP_USING_TIM1 */ + +#ifdef BSP_USING_TIM3 +#ifndef TIM3_CONFIG +#define TIM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .tim_irqn = TIM3_IRQn, \ + .name = "timer3", \ + } +#endif /* TIM3_CONFIG */ +#endif /* BSP_USING_TIM3 */ + +#ifdef BSP_USING_TIM6 +#ifndef TIM6_CONFIG +#define TIM6_CONFIG \ + { \ + .tim_handle.Instance = TIM6, \ + .tim_irqn = TIM6_IRQn, \ + .name = "timer6", \ + } +#endif /* TIM6_CONFIG */ +#endif /* BSP_USING_TIM6 */ + +#ifdef BSP_USING_TIM14 +#ifndef TIM14_CONFIG +#define TIM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .tim_irqn = TIM14_IRQn, \ + .name = "timer14", \ + } +#endif /* TIM14_CONFIG */ +#endif /* BSP_USING_TIM14 */ + +#ifdef BSP_USING_TIM15 +#ifndef TIM15_CONFIG +#define TIM15_CONFIG \ + { \ + .tim_handle.Instance = TIM15, \ + .tim_irqn = TIM15_IRQn, \ + .name = "timer15", \ + } +#endif /* TIM15_CONFIG */ +#endif /* BSP_USING_TIM15 */ + +#ifdef BSP_USING_TIM16 +#ifndef TIM16_CONFIG +#define TIM16_CONFIG \ + { \ + .tim_handle.Instance = TIM16, \ + .tim_irqn = TIM16_IRQn, \ + .name = "timer16", \ + } +#endif /* TIM16_CONFIG */ +#endif /* BSP_USING_TIM16 */ + +#ifdef BSP_USING_TIM17 +#ifndef TIM17_CONFIG +#define TIM17_CONFIG \ + { \ + .tim_handle.Instance = TIM17, \ + .tim_irqn = TIM17_IRQn, \ + .name = "timer17", \ + } +#endif /* TIM17_CONFIG */ +#endif /* BSP_USING_TIM17 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/acm32f0x0-nucleo/drivers/uart_config.h b/bsp/acm32f0x0-nucleo/drivers/uart_config.h new file mode 100644 index 0000000000..90e5a10d67 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/uart_config.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 AisinoChip the first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "board.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_SERIAL) + +#if defined(BSP_USING_UART1) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .request = UART1_RX_DMA_REQUEST, \ + } +#endif /* UART1_DMA_RX_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .dma_rcc = UART1_TX_DMA_RCC, \ + .dma_irq = UART1_TX_DMA_IRQ, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .request = UART1_RX_DMA_REQUEST, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = UART1, \ + .irq_type = UART1_IRQn, \ + .enable_id = EN_UART1, \ + .tx_port = UART1_TX_PORT, \ + .rx_port = UART1_RX_PORT, \ + .tx_pin = UART1_TX_PIN, \ + .rx_pin = UART1_RX_PIN, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .request = UART2_RX_DMA_REQUEST, \ + } +#endif /* UART2_DMA_RX_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .dma_rcc = UART2_TX_DMA_RCC, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .request = UART2_TX_DMA_REQUEST, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = UART2, \ + .irq_type = UART2_IRQn, \ + .enable_id = EN_UART2, \ + .tx_port = UART2_TX_PORT, \ + .rx_port = UART2_RX_PORT, \ + .tx_pin = UART2_TX_PIN, \ + .rx_pin = UART2_RX_PIN, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .dma_rcc = UART3_RX_DMA_RCC, \ + .dma_irq = UART3_RX_DMA_IRQ, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .request = UART3_RX_DMA_REQUEST, \ + } +#endif /* UART3_DMA_RX_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ + +#if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_DMA_TX_CONFIG +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .dma_rcc = UART3_TX_DMA_RCC, \ + .dma_irq = UART3_TX_DMA_IRQ, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .request = UART3_TX_DMA_REQUEST, \ + } +#endif /* UART3_DMA_TX_CONFIG */ +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = UART3, \ + .irq_type = UART3_IRQn, \ + .enable_id = EN_UART3, \ + .tx_port = UART3_TX_PORT, \ + .rx_port = UART3_RX_PORT, \ + .tx_pin = UART3_TX_PIN, \ + .rx_pin = UART3_RX_PIN, \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* RT_USING_SERIAL */ + +#endif /* __UART_CONFIG_H__ */ diff --git a/bsp/acm32f0x0-nucleo/libraries/CMSIS/cmsis_armcc.h b/bsp/acm32f0x0-nucleo/libraries/CMSIS/cmsis_armcc.h new file mode 100644 index 0000000000..74c49c67de --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/CMSIS/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/acm32f0x0-nucleo/libraries/CMSIS/cmsis_gcc.h b/bsp/acm32f0x0-nucleo/libraries/CMSIS/cmsis_gcc.h new file mode 100644 index 0000000000..0578f28173 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/CMSIS/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cm0.h b/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cm0.h new file mode 100644 index 0000000000..711dad5517 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cmFunc.h b/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..652a48af07 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cmInstr.h b/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..f474b0e6f3 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/CMSIS/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/acm32f0x0-nucleo/libraries/Device/ACM32F0x0.h b/bsp/acm32f0x0-nucleo/libraries/Device/ACM32F0x0.h new file mode 100644 index 0000000000..70bddbe0ae --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/Device/ACM32F0x0.h @@ -0,0 +1,762 @@ +/* + ****************************************************************************** + * @file ACM32F0x0.h + * @brief CMSIS ACM32F0x0 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** +*/ +#ifndef __ACM32F0x0_H__ +#define __ACM32F0x0_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +///*------------------- Interrupt Number Definition ----------------------*/ +typedef enum IRQn +{ +/* ---------------------- SC000 Processor Exceptions Numbers --------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemManage_IRQn = -12, /* 4 MemManage Interrupt */ + + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ---------------------- ARMCM0 Specific Interrupt Numbers --------------------- */ + WDT_IRQn = 0, // 0: WDT_IRQHandler + RTC_IRQn = 1, // 1: RTC_IRQHandler + EFC_IRQn = 2, // 2: EFC_IRQHandler + GPIOAB_IRQn = 3, // 3: GPIOAB_IRQHandler + GPIOCD_IRQn = 4, // 4: GPIOCD_IRQHandler + EXTI_IRQn = 5, // 5: EXTI_IRQHandler + SRAM_PARITY_IRQn = 6, // 6: SRAM_PARITY_IRQHandler + CLKRDY_IRQn = 7, // 7: CLKRDY_IRQHandler + LCD_IRQn = 8, // 8: LCD_IRQHandler + DMA_IRQn = 9, // 9: DMA_IRQHandler + UART3_IRQn = 10, // 10: UART3_IRQHandler + TKEY_IRQn = 11, // 11: TKEY_IRQHandler + ADC_IRQn = 12, // 12: ADC_IRQHandler + TIM1_BRK_UP_TRG_COM_IRQn = 13, // 13: TIM1_BRK_UP_TRG_COM_IRQHandler + TIM1_CC_IRQn = 14, // 14: TIM1_CC_IRQHandler + TIM3_IRQn = 16, // 16: TIM3_IRQHandler + TIM6_IRQn = 17, // 17: TIM6_IRQHandler + TIM14_IRQn = 19, // 19: TIM14_IRQHandler + TIM15_IRQn = 20, // 20: TIM15_IRQHandler + TIM16_IRQn = 21, // 21: TIM16_IRQHandler + TIM17_IRQn = 22, // 22: TIM17_IRQHandler + I2C1_IRQn = 23, // 23: I2C1_IRQHandler + I2C2_IRQn = 24, // 24: I2C2_IRQHandler + SPI1_IRQn = 25, // 25: SPI1_IRQHandler + SPI2_IRQn = 26, // 26: SPI2_IRQHandler + UART1_IRQn = 27, // 27: UART1_IRQHandler + UART2_IRQn = 28, // 28: UART2_IRQHandler + LPUART_IRQn = 29, // 29: LPUART_IRQHandler + CAN1_IRQn = 30, // 30: CAN1_IRQHandler + AES_IRQn = 31, // 31: AES_IRQhandler +} IRQn_Type; + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* Configuration of the SC000 Processor and Core Peripherals */ +#define __CM0_REV 0x0000U /* Core revision r0p0 */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0.h" /* Processor and core peripherals */ + +#include "stdio.h" +#include "string.h" + +#include "stdint.h" +#include "stdbool.h" + +///*------------------- Bit Opertions ----------------------*/ +#define BIT0 (1U << 0) +#define BIT1 (1U << 1) +#define BIT2 (1U << 2) +#define BIT3 (1U << 3) +#define BIT4 (1U << 4) +#define BIT5 (1U << 5) +#define BIT6 (1U << 6) +#define BIT7 (1U << 7) +#define BIT8 (1U << 8) +#define BIT9 (1U << 9) +#define BIT10 (1U << 10) +#define BIT11 (1U << 11) +#define BIT12 (1U << 12) +#define BIT13 (1U << 13) +#define BIT14 (1U << 14) +#define BIT15 (1U << 15) +#define BIT16 (1U << 16) +#define BIT17 (1U << 17) +#define BIT18 (1U << 18) +#define BIT19 (1U << 19) +#define BIT20 (1U << 20) +#define BIT21 (1U << 21) +#define BIT22 (1U << 22) +#define BIT23 (1U << 23) +#define BIT24 (1U << 24) +#define BIT25 (1U << 25) +#define BIT26 (1U << 26) +#define BIT27 (1U << 27) +#define BIT28 (1U << 28) +#define BIT29 (1U << 29) +#define BIT30 (1U << 30) +#define BIT31 (1U << 31) + +/** @Addtogroup Peripheral_Registers_Structures + * @{ + */ + +///*------------------- FLASH Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CTRL; // 0x00 + __IO uint32_t SEC; // 0x04 + __IO uint32_t ADCT; // 0x08 + __IO uint32_t TERASE; // 0x0C + __IO uint32_t TPROG; // 0x10 + __IO uint32_t STATUS; // 0x14 + __IO uint32_t INTSTATUS; // 0x18 + __IO uint32_t INTEN; // 0x1C + __IO uint32_t RSV0[6]; // 0x20-0x34 + __IO uint32_t NVS; // 0x38 +}EFC_TypeDef; + + +///*------------------- Timer Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CR1; // 0x00 + __IO uint32_t CR2; // 0x04 + __IO uint32_t SMCR; // 0x08 + __IO uint32_t DIER; // 0x0C + __IO uint32_t SR; // 0x10 + __IO uint32_t EGR; // 0x14 + __IO uint32_t CCMR1; // 0x18 + __IO uint32_t CCMR2; // 0x1C + __IO uint32_t CCER; // 0x20 + __IO uint32_t CNT; // 0x24 + __IO uint32_t PSC; // 0x28 + __IO uint32_t ARR; // 0x2C + __IO uint32_t RCR; // 0x30 + __IO uint32_t CCR1; // 0x34 + __IO uint32_t CCR2; // 0x38 + __IO uint32_t CCR3; // 0x3C + __IO uint32_t CCR4; // 0x40 + __IO uint32_t BDTR; // 0x44 + __IO uint32_t DCR; // 0x48 + __IO uint32_t DMAR; // 0x4C + __IO uint32_t RSV0[4]; // 0x50-0x5C + __IO uint32_t AF1; // 0x60 + __IO uint32_t RSV1; // 0x64 + __IO uint32_t TISEL; // 0x68 + __IO uint32_t DBER; // 0x6C +}TIM_TypeDef; + + +///*------------------- RTC、PMU Registers ----------------------*/ +typedef struct +{ + __IO uint32_t WP; // 0x00 + __IO uint32_t IE; // 0x04 + __IO uint32_t SR; // 0x08 + __IO uint32_t SEC; // 0x0C + __IO uint32_t MIN; // 0x10 + __IO uint32_t HOUR; // 0x14 + __IO uint32_t DATE; // 0x18 + __IO uint32_t WEEK; // 0x1C + __IO uint32_t MONTH; // 0x20 + __IO uint32_t YEAR; // 0x24 + __IO uint32_t ALM; // 0x28 + __IO uint32_t CR; // 0x2C + __IO uint32_t ADJUST; // 0x30 + __IO uint32_t RSV0[4]; // 0x34 ~ 0x40 + __IO uint32_t CLKSTAMP1_TIME; // 0x44 + __IO uint32_t CALSTAMP1_DATE; // 0x48 + __IO uint32_t CLKSTAMP2_TIME; // 0x4C + __IO uint32_t CALSTAMP2_DATE; // 0x50 + __IO uint32_t RSV1[7]; // 0x54-0x6C + __IO uint32_t BACKUP[5]; // 0x70 ~ 0x80 +}RTC_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; // 0x00 + __IO uint32_t SR; // 0x04 + __IO uint32_t IOSEL; // 0x08 + __IO uint32_t IOCR; // 0x0C + __IO uint32_t ANACR; // 0x10 + __IO uint32_t CR2; // 0x14 +}PMU_TypeDef; + + +///*------------------- WDT Registers ----------------------*/ +typedef struct +{ + __IO uint32_t LOAD; + __IO uint32_t COUNT; + __IO uint32_t CTRL; + __IO uint32_t FEED; + __IO uint32_t INTCLRTIME; + __IO uint32_t RIS; +}WDT_TypeDef; + + +///*------------------- IWDT Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CMDR; // 0x00 + __IO uint32_t PR; // 0x04 + __IO uint32_t RLR; // 0x08 + __IO uint32_t SR; // 0x0C + __IO uint32_t WINR; // 0x10 + __IO uint32_t WUTR; // 0x14 +}IWDT_TypeDef; + + +///*------------------- LCD Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CR0; // 0x00 + __IO uint32_t CR1; // 0x04 + __IO uint32_t INTCLR; // 0x08 + __IO uint32_t LCD_POEN0; // 0x0C + __IO uint32_t LCD_POEN1; // 0x10 + __IO uint32_t RSV[11]; + __IO uint32_t LCD_RAM[16]; /*!< LCD display memory, Address offset: 0x40-0x7c */ +}LCD_TypeDef; + + +///*------------------- UART Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DR; // 0x00 + __IO uint32_t RSR; // 0x04 + __IO uint32_t RSV0[4]; // 0x08-0x14 + __IO uint32_t FR; // 0x18 + __IO uint32_t RSV1; // 0x1C + __IO uint32_t ILPR; // 0x20 + __IO uint32_t IBRD; // 0x24 + __IO uint32_t FBRD; // 0x28 + __IO uint32_t LCRH; // 0x2C + __IO uint32_t CR; // 0x30 + __IO uint32_t IFLS; // 0x34 + __IO uint32_t IE; // 0x38 + __IO uint32_t RIS; // 0x3C + __IO uint32_t MIS; // 0x40 + __IO uint32_t ICR; // 0x44 + __IO uint32_t DMACR; // 0x48 + __IO uint32_t RSV2[2]; // 0x4C-0x50 + __IO uint32_t CR2; // 0x54 + __IO uint32_t BCNT; // 0x58 +}UART_TypeDef; + +///*------------------- CAN Registers ----------------------*/ +typedef struct +{ + __IO uint32_t ACR[4]; + __IO uint32_t AMR[4]; + __IO uint32_t RSV[5]; +}Filter_typedef; + +typedef union +{ + __IO uint32_t DATABUF[13]; + Filter_typedef FILTER; +}DF_typedef; + +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t CMR; + __IO uint32_t SR; + __IO uint32_t IR; + __IO uint32_t IER; + __IO uint32_t RSV0; + __IO uint32_t BTR0; + __IO uint32_t BTR1; + __IO uint32_t OCR; + __IO uint32_t RSV1; + __IO uint32_t RSV2; + __IO uint32_t ALC; + __IO uint32_t ECC; + __IO uint32_t EWLR; + __IO uint32_t RXERR; + __IO uint32_t TXERR; + __IO DF_typedef DF; + __IO uint32_t RMC; + __IO uint32_t RBSA; + __IO uint32_t CDR; + __IO uint32_t RXFIFO[64]; + __IO uint32_t TXFIFO[13]; +}CAN_TypeDef; + +///*------------------- I2C Registers ----------------------*/ +typedef struct +{ + __IO uint32_t SLAVE_ADDR1; // 0x00 + __IO uint32_t CLK_DIV; // 0x04 + __IO uint32_t CR; // 0x08 + __IO uint32_t SR; // 0x0C + __IO uint32_t DR; // 0x10 + __IO uint32_t SLAVE_ADDR23; // 0x14 + __IO uint32_t RSV0[3]; // 0x18-0x20 + __IO uint32_t TIMEOUT; // 0x24 +}I2C_TypeDef; + + +///*------------------- LPUART Registers ----------------------*/ +typedef struct +{ + __IO uint32_t RXDR; // 0x00 + __IO uint32_t TXDR; // 0x04 + __IO uint32_t LCR; // 0x08 + __IO uint32_t CR; // 0x0C + __IO uint32_t IBAUD; // 0x10 + __IO uint32_t FBAUD; // 0x14 + __IO uint32_t IE; // 0x18 + __IO uint32_t SR; // 0x1C + __IO uint32_t ADDR; // 0x20 +}LPUART_TypeDef; + + +///*------------------- COMP Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CR1; // 0x00 + __IO uint32_t CR2; // 0x04 + __IO uint32_t SR; // 0x08 +}COMP_TypeDef; + + +///*------------------- OPA Registers ----------------------*/ +typedef struct +{ + __IO uint32_t OPA1_CSR; // 0x00 + __IO uint32_t OPA2_CSR; // 0x04 + __IO uint32_t OPA3_CSR; // 0x08 +}OPA_TypeDef; + + +///*------------------- EXTI Registers ----------------------*/ +typedef struct +{ + __IO uint32_t IENR; // 0x00 + __IO uint32_t EENR; // 0x04 + __IO uint32_t RTENR; // 0x08 + __IO uint32_t FTENR; // 0x0C + __IO uint32_t SWIER; // 0x10 + __IO uint32_t PDR; // 0x14 + __IO uint32_t EXTICR1; // 0x18 + __IO uint32_t EXTICR2; // 0x1C +}EXTI_TypeDef; + + +///*------------------- SCU Registers ----------------------*/ +typedef struct +{ + __IO uint32_t RCR; // 0x00 + __IO uint32_t RSR; // 0x04 + __IO uint32_t RSV0; // 0x08 + __IO uint32_t IPRST; // 0x0C + __IO uint32_t CCR1; // 0x10 + __IO uint32_t CCR2; // 0x14 + __IO uint32_t CIR; // 0x18 + __IO uint32_t IPCKENR1; // 0x1C + __IO uint32_t IPCKENR2; // 0x20 + __IO uint32_t RCHCR; // 0x24 + __IO uint32_t XTHCR; // 0x28 + __IO uint32_t PLLCR; // 0x2C + __IO uint32_t LDOCR; // 0x30 + __IO uint32_t RSV1; // 0x34 + __IO uint32_t WMR; // 0x38 + __IO uint32_t CLKOCR; // 0x3C + __IO uint32_t VER; // 0x40 + __IO uint32_t SYSCFG1; // 0x44 + __IO uint32_t LVDCFG; // 0x48 + __IO uint32_t STOPCFG; // 0x4C + __IO uint32_t VECTOROFFSET; // 0x50 + __IO uint32_t RSV2; // 0x54 + __IO uint32_t MEMCFG; // 0x58 + __IO uint32_t RSV3; // 0x5C + __IO uint32_t PASEL1; // 0x60 + __IO uint32_t PASEL2; // 0x64 + __IO uint32_t PBSEL1; // 0x68 + __IO uint32_t PBSEL2; // 0x6C + __IO uint32_t PABPUR; // 0x70 + __IO uint32_t PABPDR; // 0x74 + __IO uint32_t PASTR; // 0x78 + __IO uint32_t PBSTR; // 0x7C + __IO uint32_t PABSMTR; // 0x80 + __IO uint32_t PABODR; // 0x84 + __IO uint32_t PABADS; // 0x88 + __IO uint32_t RSV4; // 0x8C + __IO uint32_t PCSEL1; // 0x90 + __IO uint32_t PCSEL2; // 0x94 + __IO uint32_t PDSEL1; // 0x98 + __IO uint32_t RSV5; // 0x9C + __IO uint32_t PCDPUR; // 0xA0 + __IO uint32_t PCDPDR; // 0xA4 + __IO uint32_t PCSTR; // 0xA8 + __IO uint32_t PDSTR; // 0xAC + __IO uint32_t PCDSMTR; // 0xB0 + __IO uint32_t PCDODR; // 0xB4 + __IO uint32_t PCDADS; // 0xB8 +}SCU_TypeDef; + + +///*------------------- CRC Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DATA; // 0x00 + __IO uint32_t CTRL; // 0x04 + __IO uint32_t INIT; // 0x08 + __IO uint32_t RSV0; // 0x0C + __IO uint32_t OUTXOR; // 0x10 + __IO uint32_t POLY; // 0x14 + __IO uint32_t FDATA; // 0x18 +}CRC_TypeDef; + + +///*------------------- ADC Registers ----------------------*/ +typedef struct +{ + __IO uint32_t SR; // 0x00 + __IO uint32_t IE; // 0x04 + __IO uint32_t CR1; // 0x08 + __IO uint32_t CR2; // 0x0C + __IO uint32_t SMPR1; // 0x10 + __IO uint32_t SMPR2; // 0x14 + __IO uint32_t HTR; // 0x18 + __IO uint32_t LTR; // 0x1C + __IO uint32_t SQR1; // 0x20 + __IO uint32_t SQR2; // 0x24 + __IO uint32_t SQR3; // 0x28 + __IO uint32_t JSQR; // 0x2C + __IO uint32_t JDR; // 0x30 + __IO uint32_t DR; // 0x34 + __IO uint32_t DIFF; // 0x38 + __IO uint32_t SIGN; // 0x3C + __IO uint32_t TSREF; // 0x40 + __IO uint32_t SMPR3; // 0x44 +}ADC_TypeDef; + + +///*-----------------------TKEY------------------------*/ +typedef struct +{ + __IO uint32_t ISR; // 0x00 + __IO uint32_t IER; // 0x04 + __IO uint32_t CR; // 0x08 + __IO uint32_t SMPR; // 0x0C + __IO uint32_t SOFR; // 0x10 + __IO uint32_t CXSELR; // 0x14 + __IO uint32_t CRSELR; // 0x18 + __IO uint32_t DR; // 0x1C + __IO uint32_t TH0; // 0x20 + __IO uint32_t TH1; // 0x24 + __IO uint32_t TH2; // 0x28 + __IO uint32_t TH3; // 0x2C + __IO uint32_t TH4; // 0x30 + __IO uint32_t TH5; // 0x34 + __IO uint32_t TH6; // 0x38 + __IO uint32_t TH7; // 0x3C + __IO uint32_t TH8; // 0x40 + __IO uint32_t TH9; // 0x44 + __IO uint32_t TH10; // 0x48 + __IO uint32_t TH11; // 0x4C + __IO uint32_t TH12; // 0x50 + __IO uint32_t TH13; // 0x54 + __IO uint32_t TH14; // 0x58 + __IO uint32_t TH15; // 0x5C + __IO uint32_t CH0; // 0x60 + __IO uint32_t CH1; // 0x64 + __IO uint32_t CH2; // 0x68 + __IO uint32_t CH3; // 0x6C + __IO uint32_t CH4; // 0x70 + __IO uint32_t CH5; // 0x74 + __IO uint32_t CH6; // 0x78 + __IO uint32_t CH7; // 0x7C + __IO uint32_t CH8; // 0x80 + __IO uint32_t CH9; // 0x84 + __IO uint32_t CH10; // 0x88 + __IO uint32_t CH11; // 0x8C + __IO uint32_t CH12; // 0x90 + __IO uint32_t CH13; // 0x94 + __IO uint32_t CH14; // 0x98 + __IO uint32_t CH15; // 0x9C +}TKEY_TypeDef; + + +///*------------------- GPIO Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DIR; // 0x00 + __IO uint32_t RSV0; // 0x04 + __IO uint32_t SET; // 0x08 + __IO uint32_t CLR; // 0x0C + __IO uint32_t ODATA; // 0x10 + __IO uint32_t IDATA; // 0x14 + __IO uint32_t IEN; // 0x18 + __IO uint32_t IS; // 0x1C + __IO uint32_t IBE; // 0x20 + __IO uint32_t IEV; // 0x24 + __IO uint32_t IC; // 0x28 + __IO uint32_t RIS; // 0x2C + __IO uint32_t MIS; // 0x30 +}GPIO_TypeDef; + + +///*------------------- SPI Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DAT; // 0x00 + __IO uint32_t BAUD; // 0x04 + __IO uint32_t CTL; // 0x08 + __IO uint32_t TX_CTL; // 0x0C + __IO uint32_t RX_CTL; // 0x10 + __IO uint32_t IE; // 0x14 + __IO uint32_t STATUS; // 0x18 + __IO uint32_t TXDELAY; // 0x1C + __IO uint32_t BATCH; // 0x20 + __IO uint32_t CS; // 0x24 + __IO uint32_t OUT_EN; // 0x28 +}SPI_TypeDef; + + +///*------------------- DMA Registers ----------------------*/ +typedef struct +{ + __IO uint32_t INT_STATUS; // 0x00 + __IO uint32_t INT_TC_STATUS; // 0x04 + __IO uint32_t INT_TC_CLR; // 0x08 + __IO uint32_t INT_ERR_STATUS; // 0x0C + __IO uint32_t INT_ERR_CLR; // 0x10 + __IO uint32_t RAW_INT_TC_STATUS; // 0x14 + __IO uint32_t RAW_INT_ERR_STATUS; // 0x18 + __IO uint32_t EN_CH_STATUS; // 0x1C + __IO uint32_t RSV0[4]; // 0x20-0x2C + __IO uint32_t CONFIG; // 0x30 + __IO uint32_t SYNC; // 0x34 +}DMA_TypeDef; + +typedef struct +{ + __IO uint32_t SRC_ADDR; + __IO uint32_t DEST_ADDR; + __IO uint32_t LLI; + __IO uint32_t CTRL; + __IO uint32_t CONFIG; +}DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t REG_AESDATAIN; //0x00 + __IO uint32_t REG_AESKEYIN; //0x04 + __IO uint32_t REG_AESIVIN; //0x08 + __IO uint32_t REG_AESCTRL; //0x0C + __IO uint32_t REG_AESSTATE; //0x10 + __IO uint32_t REG_AESDATAOUT; //0x14 +}AES_TypeDef; + +typedef struct +{ + __IO uint32_t CTRL; //0x00 + __IO uint32_t LFSR; //0x04 +}HRNG_TypeDef; + +typedef struct +{ + __IO uint32_t DIVIDENED; //0x00 + __IO uint32_t DIVISOR; //0x04 + __IO uint32_t REMAIN; //0x08 + __IO uint32_t QUOTIENT; //0x0c + __IO uint32_t STATUS; //0x10 + +}DIV_TypeDef; + +/** + * @} + */ + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define EFLASH_BASE (0x00000000UL) +#define EFC_BASE (0x00100000UL) +#define SRAM_BASE (0x20000000UL) +#define PERIPH_BASE (0x40000000UL) + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x30000UL) + +///*----------------------APB1 peripherals------------------------*/ +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x00002000UL) +#define PMU_BASE (APB1PERIPH_BASE + 0x00002400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WDT_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDT_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define UART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define UART3_BASE (APB1PERIPH_BASE + 0x00004800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) +#define LPUART_BASE (APB1PERIPH_BASE + 0x00008000UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x0000F000UL) + +///*----------------------APB2 peripherals------------------------*/ +#define COMP_BASE (APB2PERIPH_BASE + 0x00000200UL) +#define OPA_BASE (APB2PERIPH_BASE + 0x00000300UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) +#define SCU_BASE (APB2PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (APB2PERIPH_BASE + 0x00000C00UL) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define UART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) +#define TKEY_BASE (APB2PERIPH_BASE + 0x00006400UL) +#define GPIOAB_BASE (APB2PERIPH_BASE + 0x0000F000UL) +#define GPIOCD_BASE (APB2PERIPH_BASE + 0x0000F400UL) + +//#define ACM32F0X0_VER_0 +#ifdef ACM32F0X0_VER_0 +#undef GPIOAB_BASE +#undef GPIOCD_BASE +#undef UART3_BASE +#undef PMU_BASE +#undef RTC_BASE +#undef COMP_BASE +#undef OPA_BASE + +#define GPIOAB_BASE 0x40006800 +#define GPIOCD_BASE 0x40016800 +#define UART3_BASE 0x40004800 +#define PMU_BASE 0x40002400 +#define RTC_BASE 0x40002800 +#define COMP_BASE 0x40010200 +#define OPA_BASE 0x40010300 +#endif + +///*----------------------AHB1 peripherals------------------------*/ +#define SPI1_BASE (AHB1PERIPH_BASE) +#define SPI2_BASE (AHB1PERIPH_BASE + 0x00000400UL) +#define DMAC_BASE (AHB1PERIPH_BASE + 0x00001000UL) +#define DMA_Channel0_BASE (AHB1PERIPH_BASE + 0x00001100UL) +#define DMA_Channel1_BASE (AHB1PERIPH_BASE + 0x00001120UL) +#define DMA_Channel2_BASE (AHB1PERIPH_BASE + 0x00001140UL) +#define DMA_Channel3_BASE (AHB1PERIPH_BASE + 0x00001160UL) +#define DMA_Channel4_BASE (AHB1PERIPH_BASE + 0x00001180UL) + +///*----------------------AHB2 peripherals------------------------*/ +#define AES_BASE (AHB2PERIPH_BASE) +#define DIV_BASE (AHB2PERIPH_BASE + 0x00000400UL) +#define HRNG_BASE (AHB2PERIPH_BASE + 0x00000800UL) +/** + * @} + */ + + + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define EFC ((EFC_TypeDef *)EFC_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM14 ((TIM_TypeDef *)TIM14_BASE) +#define PMU ((PMU_TypeDef *)PMU_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define IWDT ((IWDT_TypeDef *)IWDT_BASE) +#define LCD ((LCD_TypeDef *)LCD_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define LPUART ((LPUART_TypeDef *)LPUART_BASE) +#define GPIOAB ((GPIO_TypeDef *)GPIOAB_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define SCU ((SCU_TypeDef *)SCU_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define COMP ((COMP_TypeDef *)COMP_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define ADC ((ADC_TypeDef *)ADC_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define TIM15 ((TIM_TypeDef *)TIM15_BASE) +#define TIM16 ((TIM_TypeDef *)TIM16_BASE) +#define TIM17 ((TIM_TypeDef *)TIM17_BASE) +#define TKEY ((TKEY_TypeDef *)TKEY_BASE) +#define GPIOCD ((GPIO_TypeDef *)GPIOCD_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define DMA ((DMA_TypeDef *)DMAC_BASE) +#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) +#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) +#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) +#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) +#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) +#define HRNG ((HRNG_TypeDef *)HRNG_BASE) +#define AES ((AES_TypeDef *)AES_BASE) +#define DIV ((DIV_TypeDef *)DIV_BASE) + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG,MASK,BITS) ((REG) = (((REG)&(~(MASK)))|((BITS)&(MASK)))) +/** + * @} + */ + +/* Compatible with old code */ +typedef signed char INT8; +typedef signed short int INT16; +typedef signed int INT32; + +typedef unsigned char UINT8; +typedef unsigned short int UINT16; +typedef unsigned int UINT32; + +#ifdef __cplusplus +} +#endif + +#endif /* ACM32F0x0_H */ diff --git a/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0.s b/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0.s new file mode 100644 index 0000000000..c6fb61d400 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0.s @@ -0,0 +1,215 @@ +;* File Name : Startup_ACM32F0x0.s +;* Version : V1.0.0 +;* Date : 2020 +;* Description : ACM32F0x0 Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the SC000 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* + +Stack_Size EQU 0x00000800 +Heap_Size EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: WDT_IRQHandler + DCD RTC_IRQHandler ; 1: RTC_IRQHandler + DCD EFC_IRQHandler ; 2: EFC_IRQHandler + DCD GPIOAB_IRQHandler ; 3: GPIOAB_IRQHandler + DCD GPIOCD_IRQHandler ; 4: GPIOCD_IRQHandler + DCD EXTI_IRQHandler ; 5: EXTI_IRQHandler + DCD SRAM_PARITY_IRQHandler ; 6: SRAM_PARITY_IRQHandler + DCD CLKRDY_IRQHandler ; 7: CLKRDY_IRQHandler + DCD LCD_IRQHandler ; 8: LCD_IRQHandler + DCD DMA_IRQHandler ; 9: DMA_IRQHandler + DCD UART3_IRQHandler ; 10: UART3_IRQHandler + DCD TKEY_IRQHandler ; 11: TKEY_IRQHandler + DCD ADC_IRQHandler ; 12: ADC_IRQHandler + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13: TIM1_BRK_UP_TRG_COM_IRQHandler + DCD TIM1_CC_IRQHandler ; 14: TIM1_CC_IRQHandler + DCD RSV_IRQHandler ; 15: Reserved + DCD TIM3_IRQHandler ; 16: TIM3_IRQHandler + DCD TIM6_IRQHandler ; 17: TIM6_IRQHandler + DCD RSV_IRQHandler ; 18: Reserved + DCD TIM14_IRQHandler ; 19: TIM14_IRQHandler + DCD TIM15_IRQHandler ; 20: TIM15_IRQHandler + DCD TIM16_IRQHandler ; 21: TIM16_IRQHandler + DCD TIM17_IRQHandler ; 22: TIM17_IRQHandler + DCD I2C1_IRQHandler ; 23: I2C1_IRQHandler + DCD I2C2_IRQHandler ; 24: I2C2_IRQHandler + DCD SPI1_IRQHandler ; 25: SPI1_IRQHandler + DCD SPI2_IRQHandler ; 26: SPI2_IRQHandler + DCD UART1_IRQHandler ; 27: UART1_IRQHandler + DCD UART2_IRQHandler ; 28: UART2_IRQHandler + DCD LPUART_IRQHandler ; 29: LPUART_IRQHandler + DCD CAN1_IRQHandler ; 30: CAN1_IRQHandler + DCD AES_IRQHandler ; 31: AES_IRQHandler + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT EFC_IRQHandler [WEAK] + EXPORT GPIOAB_IRQHandler [WEAK] + EXPORT GPIOCD_IRQHandler [WEAK] + EXPORT EXTI_IRQHandler [WEAK] + EXPORT SRAM_PARITY_IRQHandler [WEAK] + EXPORT CLKRDY_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT TKEY_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT LPUART_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT RSV_IRQHandler [WEAK] +WDT_IRQHandler +RTC_IRQHandler +EFC_IRQHandler +GPIOAB_IRQHandler +GPIOCD_IRQHandler +EXTI_IRQHandler +SRAM_PARITY_IRQHandler +CLKRDY_IRQHandler +LCD_IRQHandler +DMA_IRQHandler +UART3_IRQHandler +TKEY_IRQHandler +ADC_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM3_IRQHandler +TIM6_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +LPUART_IRQHandler +CAN1_IRQHandler +AES_IRQHandler +RSV_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0_gcc.s b/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0_gcc.s new file mode 100644 index 0000000000..6a103bdffe --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0_gcc.s @@ -0,0 +1,279 @@ +/******************************************************************************* +;* File Name : Startup_ACM32F0x0_gcc.s +;* Version : V1.0.0 +;* Date : 2021 +;* Description : ACM32F0x0 Devices vector table for GCC toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the SC000 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;*******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2, #4] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + /* bl SystemInit */ +/* Call the application's entry point.*/ + bl entry +LoopForever: + b LoopForever +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/******************************************************************************* +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WDT_IRQHandler /* 0: WDT_IRQHandler */ + .word RTC_IRQHandler /* 1: RTC_IRQHandler */ + .word EFC_IRQHandler /* 2: EFC_IRQHandler */ + .word GPIOAB_IRQHandler /* 3: GPIOAB_IRQHandler */ + .word GPIOCD_IRQHandler /* 4: GPIOCD_IRQHandler */ + .word EXTI_IRQHandler /* 5: EXTI_IRQHandler */ + .word SRAM_PARITY_IRQHandler /* 6: SRAM_PARITY_IRQHandler */ + .word CLKRDY_IRQHandler /* 7: CLKRDY_IRQHandler */ + .word LCD_IRQHandler /* 8: LCD_IRQHandler */ + .word DMA_IRQHandler /* 9: DMA_IRQHandler */ + .word UART3_IRQHandler /* 10: UART3_IRQHandler */ + .word TKEY_IRQHandler /* 11: TKEY_IRQHandler */ + .word ADC_IRQHandler /* 12: ADC_IRQHandler */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* 13: TIM1_BRK_UP_TRG_COM_IRQHandler */ + .word TIM1_CC_IRQHandler /* 14: TIM1_CC_IRQHandler */ + .word RSV_IRQHandler /* 15: Reserved */ + .word TIM3_IRQHandler /* 16: TIM3_IRQHandler */ + .word TIM6_IRQHandler /* 17: TIM6_IRQHandler */ + .word RSV_IRQHandler /* 18: Reserved */ + .word TIM14_IRQHandler /* 19: TIM14_IRQHandler */ + .word TIM15_IRQHandler /* 20: TIM15_IRQHandler */ + .word TIM16_IRQHandler /* 21: TIM16_IRQHandler */ + .word TIM17_IRQHandler /* 22: TIM17_IRQHandler */ + .word I2C1_IRQHandler /* 23: I2C1_IRQHandler */ + .word I2C2_IRQHandler /* 24: I2C2_IRQHandler */ + .word SPI1_IRQHandler /* 25: SPI1_IRQHandler */ + .word SPI2_IRQHandler /* 26: SPI2_IRQHandler */ + .word UART1_IRQHandler /* 27: UART1_IRQHandler */ + .word UART2_IRQHandler /* 28: UART2_IRQHandler */ + .word LPUART_IRQHandler /* 29: LPUART_IRQHandler */ + .word CAN1_IRQHandler /* 30: CAN1_IRQHandler */ + .word AES_IRQHandler /* 31: AES_IRQHandler */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WDT_IRQHandler + .thumb_set WDT_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak EFC_IRQHandler + .thumb_set EFC_IRQHandler,Default_Handler + + .weak GPIOAB_IRQHandler + .thumb_set GPIOAB_IRQHandler,Default_Handler + + .weak GPIOCD_IRQHandler + .thumb_set GPIOCD_IRQHandler,Default_Handler + + .weak EXTI_IRQHandler + .thumb_set EXTI_IRQHandler,Default_Handler + + .weak SRAM_PARITY_IRQHandler + .thumb_set SRAM_PARITY_IRQHandler,Default_Handler + + .weak CLKRDY_IRQHandler + .thumb_set CLKRDY_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak TKEY_IRQHandler + .thumb_set TKEY_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak RSV_IRQHandler + .thumb_set RSV_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak LPUART_IRQHandler + .thumb_set LPUART_IRQHandler,Default_Handler + + .weak CAN1_IRQHandler + .thumb_set CAN1_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT AisinoChip *****END OF FILE****/ diff --git a/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0_iar.s b/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0_iar.s new file mode 100644 index 0000000000..e82fd096e5 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/Device/Startup_ACM32F0x0_iar.s @@ -0,0 +1,278 @@ +;* File Name : Startup_ACM32F0x0.s +;* Version : V1.0.0 +;* Date : 2020 +;* Description : ACM32F0x0 Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the SC000 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MemManage_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: WDT_IRQHandler + DCD RTC_IRQHandler ; 1: RTC_IRQHandler + DCD EFC_IRQHandler ; 2: EFC_IRQHandler + DCD GPIOAB_IRQHandler ; 3: GPIOAB_IRQHandler + DCD GPIOCD_IRQHandler ; 4: GPIOCD_IRQHandler + DCD EXTI_IRQHandler ; 5: EXTI_IRQHandler + DCD SRAM_PARITY_IRQHandler ; 6: SRAM_PARITY_IRQHandler + DCD CLKRDY_IRQHandler ; 7: CLKRDY_IRQHandler + DCD LCD_IRQHandler ; 8: LCD_IRQHandler + DCD DMA_IRQHandler ; 9: DMA_IRQHandler + DCD UART3_IRQHandler ; 10: UART3_IRQHandler + DCD TKEY_IRQHandler ; 11: TKEY_IRQHandler + DCD ADC_IRQHandler ; 12: ADC_IRQHandler + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13: TIM1_BRK_UP_TRG_COM_IRQHandler + DCD TIM1_CC_IRQHandler ; 14: TIM1_CC_IRQHandler + DCD RSV_IRQHandler ; 15: Reserved + DCD TIM3_IRQHandler ; 16: TIM3_IRQHandler + DCD TIM6_IRQHandler ; 17: TIM6_IRQHandler + DCD RSV_IRQHandler ; 18: Reserved + DCD TIM14_IRQHandler ; 19: TIM14_IRQHandler + DCD TIM15_IRQHandler ; 20: TIM15_IRQHandler + DCD TIM16_IRQHandler ; 21: TIM16_IRQHandler + DCD TIM17_IRQHandler ; 22: TIM17_IRQHandler + DCD I2C1_IRQHandler ; 23: I2C1_IRQHandler + DCD I2C2_IRQHandler ; 24: I2C2_IRQHandler + DCD SPI1_IRQHandler ; 25: SPI1_IRQHandler + DCD SPI2_IRQHandler ; 26: SPI2_IRQHandler + DCD UART1_IRQHandler ; 27: UART1_IRQHandler + DCD UART2_IRQHandler ; 28: UART2_IRQHandler + DCD LPUART_IRQHandler ; 29: LPUART_IRQHandler + DCD CAN1_IRQHandler ; 30: CAN1_IRQHandler + DCD AES_IRQHandler ; 31: AES_IRQHandler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK EFC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EFC_IRQHandler + B EFC_IRQHandler + + PUBWEAK GPIOAB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOAB_IRQHandler + B GPIOAB_IRQHandler + + PUBWEAK GPIOCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOCD_IRQHandler + B GPIOCD_IRQHandler + + PUBWEAK EXTI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI_IRQHandler + B EXTI_IRQHandler + + PUBWEAK SRAM_PARITY_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SRAM_PARITY_IRQHandler + B SRAM_PARITY_IRQHandler + + PUBWEAK CLKRDY_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CLKRDY_IRQHandler + B CLKRDY_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK TKEY_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TKEY_IRQHandler + B TKEY_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + PUBWEAK LPUART_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART_IRQHandler + B LPUART_IRQHandler + + PUBWEAK CAN1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_IRQHandler + B CAN1_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK RSV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RSV_IRQHandler + B RSV_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/bsp/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.c b/bsp/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.c new file mode 100644 index 0000000000..352f93fd59 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.c @@ -0,0 +1,617 @@ +/* + ****************************************************************************** + * @file System_ACM32F0x0.c + * @version V1.0.0 + * @date 2021 + * @brief System Source File, includes clock management, reset management + * and IO configuration, ... + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +uint32_t gu32_SystemClock; +uint32_t gu32_APBClock; + +RESET_REASON Reset_Reason_Save; + +/* System count in SysTick_Handler */ +volatile uint32_t gu32_SystemCount; + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +#if 0 +/********************************************************************************* +* Function : HardFault_Handler +* Description : Hard Fault handle, while(1) loop, wait for debug +* Input : none +* Output : none +* Author : xwl +**********************************************************************************/ +void HardFault_Handler(void) +{ + while(1); +} + +/********************************************************************************* +* Function : SysTick_Handler +* Description : System tick handler +* Input : none +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void SysTick_Handler(void) +{ + gu32_SystemCount++; +} + +/********************************************************************************* +* Function : System_SysTick_Init +* Description : System Tick Init. Period is 1 ms +* Input : none +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_SysTick_Init(void) +{ + gu32_SystemCount = 0; + SysTick_Config(gu32_SystemClock / 1000); //1ms/tick +} +#endif +/********************************************************************************* +* Function : System_SysTick_Off +* Description : Turn off System Tick +* Input : none +* Output : none +* Author : xwl +**********************************************************************************/ +void System_SysTick_Off(void) +{ + SysTick->CTRL = 0; +} +/********************************************************************************* +* Function : System_Init +* Description : Initialize the system clock +* Input : none +* Outpu : none +* Author : Chris_Kyle Date : 2021 +**********************************************************************************/ +void System_Init(void) +{ + SCU->RCR |= SCU_RCR_REMAP_EN; + System_Set_Buzzer_Divider(80, FUNC_DISABLE); // disable clock out + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + /* Vector Table Relocation in Internal SRAM */ + SCU->VECTOROFFSET = SRAM_BASE | VECT_TAB_OFFSET | SCU_VECTOROFFSET_VOFFSETEN; +#else + /* Vector Table Relocation in Internal FLASH */ + SCU->VECTOROFFSET = EFLASH_BASE | VECT_TAB_OFFSET | SCU_VECTOROFFSET_VOFFSETEN; +#endif + + /* Initialize the system clock */ + if (false == System_Clock_Init(DEFAULT_SYSTEM_CLOCK)) + { + while(1); + } + +#ifdef HAL_SYSTICK_ENABLED // To activate macro in ACM32Fxx_HAL.h + System_SysTick_Init(); +#endif +} + +/********************************************************************************* +* Function : System_Clock_Init +* Description : Clock init +* Input : fu32_Clock: System core clock +* Outpu : 0: success, other value: fail reason +* Author : xwl Date : 2021 +**********************************************************************************/ +bool System_Clock_Init(uint32_t fu32_Clock) +{ + uint32_t lu32_DIV, lu32_system_clk_source, lu32_result, lu32_timeout; + + lu32_system_clk_source = CLK_SRC_RC64M; + + SET_EFC_RD_WAIT(RD_WAIT_SET_DEFAULT) + + switch (fu32_Clock) + { + /* 64MHz */ + case 64000000: lu32_DIV = 1; break; + + /* 32MHz */ + case 32000000: lu32_DIV = 2; break; + + /* 16MHz */ + case 16000000: lu32_DIV = 4; break; + + /* 8MHz */ + case 8000000: lu32_DIV = 8; break; + + default: return false; + } + + lu32_result = 0; + + if (lu32_system_clk_source == CLK_SRC_XTH_PLL) + { + lu32_timeout = 0; + + SCU->XTHCR = SCU_XTHCR_XTH_EN | SCU_XTHCR_READYTIME_32768; + while (0 == (SCU->XTHCR & SCU_XTHCR_XTHRDY)) + { + if (lu32_timeout == SYSTEM_TIMEOUT) + { + lu32_result = 1; + break; + } + lu32_timeout++; + } + + if (0 == lu32_result) + { + SCU->PLLCR |= SCU_PLLCR_PLL_EN; + SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP); + while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) )) {} + +#ifdef XTH_8M_CRYSTAL + SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (15U << 3) | (1U << 12) | (0U << 16); +#endif + +#ifdef XTH_12M_CRYSTAL + SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (15U << 3) | (2U << 12) | (0U << 16); +#endif + + SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); + SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN; + while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) ); + + /* Division Config */ + SCU->CCR2 = (SCU->CCR2 & (~0xFF)) | APB_CLK_DIV_0 | (lu32_DIV - 1); + while((SCU->CCR2 & (1UL << 31)) == 0x00); + + /* Clock Select PLL */ + SCU->CCR1 = SYS_CLK_SRC_PLLCLK; + } + else + { + SCU->XTHCR &= (~SCU_XTHCR_XTH_EN); + } + } + + if ( (lu32_system_clk_source == CLK_SRC_RC64M) || (0 != lu32_result) ) + { + /* Division Config */ + SCU->CCR2 = (SCU->CCR2 & (~0xFF)) | APB_CLK_DIV_0 | (lu32_DIV - 1); + while((SCU->CCR2 & (1UL << 31)) == 0x00); + + /* Clock Select RCH */ + SCU->CCR1 = SYS_CLK_SRC_RCH; + } + + gu32_SystemClock = fu32_Clock; + gu32_APBClock = fu32_Clock; + + /* Eflash Config */ + //HAL_EFlash_Init(gu32_SystemClock); + + return true; +} + +/********************************************************************************* +* Function : System_Get_SystemClock +* Description : get AHB clock frequency +* Input : none +* Outpu : frequency, measured as Hz +* Author : Chris_Kyle Date : 2020 +**********************************************************************************/ +uint32_t System_Get_SystemClock(void) +{ + return gu32_SystemClock; +} + +/********************************************************************************* +* Function : System_Get_APBClock +* Description : get APB clock frequency +* Input : none +* Outpu : frequency, measured as Hz +* Author : Chris_Kyle Date : 2021 +**********************************************************************************/ +uint32_t System_Get_APBClock(void) +{ + return gu32_APBClock; +} + +/********************************************************************************* +* Function : System_Module_Reset +* Description : reset module +* Input : module id +* Outpu : none +* Author : Chris_Kyle Date : 2021 +**********************************************************************************/ +void System_Module_Reset(enum_RST_ID_t fe_ID_Index) +{ + SCU->IPRST &= (~(1 << fe_ID_Index)); + System_Delay(2); + SCU->IPRST |= (1 << fe_ID_Index); +} + +/********************************************************************************* +* Function : System_Module_Enable +* Description : enable module clock +* Input : module id +* Outpu : none +* Author : Chris_Kyle Date : 2021 +**********************************************************************************/ +void System_Module_Enable(enum_Enable_ID_t fe_ID_Index) +{ + if (fe_ID_Index > 6) + { + SCU->IPCKENR1 |= (1U << (fe_ID_Index - 7) ); + } + else + { + SCU->IPCKENR2 |= (1U << fe_ID_Index); + } + + System_Delay(2); +} + +/********************************************************************************* +* Function : System_Module_Disable +* Description : disable module clock +* Input : module id +* Outpu : none +* Author : Chris_Kyle Date : 2021 +**********************************************************************************/ +void System_Module_Disable(enum_Enable_ID_t fe_ID_Index) +{ + if (fe_ID_Index > 6) + { + SCU->IPCKENR1 &= ~(1U << (fe_ID_Index - 7)); + } + else + { + SCU->IPCKENR2 &= ~(1U << fe_ID_Index); + } +} + +/********************************************************************************* +* Function : System_Delay +* Description : NOP delay +* Input : count +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Delay(volatile uint32_t fu32_Delay) +{ + while (fu32_Delay--); +} + +/********************************************************************************* +* Function : System_Delay_MS +* Description : ms delay. Use this Function must call System_SysTick_Init() +* Input : delay period, measured as ms +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Delay_MS(volatile uint32_t fu32_Delay) +{ + uint32_t lu32_SystemCountBackup; + + lu32_SystemCountBackup = gu32_SystemCount; + + while ( (gu32_SystemCount - lu32_SystemCountBackup) < fu32_Delay); +} + +/********************************************************************************* +* Function : System_Enable_RC32K +* Description : Enable RC32K, make sure RTC Domain Access is allowed +* Input : none +* Outpu : none +* Author : Chris_Kyle Date : 2021 +**********************************************************************************/ +void System_Enable_RC32K(void) +{ + PMU->ANACR |= RPMU_ANACR_RC32K_EN; + while(!(PMU->ANACR & RPMU_ANACR_RC32K_RDY)); +} + +/********************************************************************************* +* Function : System_Disable_RC32K +* Description : Disable RC32K +* Input : none +* Outpu : none +* Author : CWT Date : 2021 +**********************************************************************************/ +void System_Disable_RC32K(void) +{ + PMU->ANACR &= (~RPMU_ANACR_RC32K_EN); +} + +/********************************************************************************* +* Function : System_Enable_XTAL +* Description : Enable XTAL, make sure RTC Domain Access is allowed +* Input : none +* Outpu : none +* Author : Chris_Kyle Date : 2021 +**********************************************************************************/ +void System_Enable_XTAL(void) +{ + PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0); + PMU->ANACR |= RPMU_ANACR_XTLEN; + while(!(PMU->ANACR & RPMU_ANACR_XTLRDY)); + PMU->CR1 |= RTC_CLOCK_XTL; +} + +/********************************************************************************* +* Function : System_Disable_XTAL +* Description : Disable XTAL +* Input : none +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Disable_XTAL(void) +{ + PMU->ANACR &= (~(RPMU_ANACR_XTLEN)); +} + +/********************************************************************************* +* Function : System_Enable_Disable_RTC_Domain_Access +* Description : Enable or Disable RTC Domain Access. +* Input : enable or disable +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Enable_Disable_RTC_Domain_Access(FUNC_DISABLE_ENABLE enable_disable) +{ + if (FUNC_DISABLE == enable_disable) + { + SCU->STOPCFG &= (~SCU_STOPCFG_RTC_WE); + } + else + { + SCU->STOPCFG |= SCU_STOPCFG_RTC_WE; + System_Delay(1); + RTC->WP = 0xCA53CA53U; + } +} + +/********************************************************************************* +* Function : System_Enable_Disable_Reset +* Description : Enable or Disable System Reset source. +* Input : none +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Enable_Disable_Reset(RESET_ENABLE_SOURCE source, FUNC_DISABLE_ENABLE enable_disable) +{ + switch(source) + { + /* reset source: from bit0 to bit3 */ + case RESET_ENABLE_SOURCE_LVD: + case RESET_ENABLE_SOURCE_WDT: + case RESET_ENABLE_SOURCE_IWDT: + case RESET_ENABLE_SOURCE_LOCKUP: + + if (FUNC_DISABLE == enable_disable) + { + SCU->RCR &= (~(1U << source)); + } + else + { + SCU->RCR |= (1U << source); + } + break; + + default: break; + } +} + +/********************************************************************************* +* Function : System_Reset_MCU +* Description : reset mcu +* Input : reset source +* Output : none +* Author : xwl +**********************************************************************************/ +void System_Reset_MCU(RESET_SOURCE source) +{ + switch(source) + { + case RESET_SOURCE_EFC: + { + SCU->RCR &= (~BIT29); + while(1); + } + + case RESET_SOURCE_NVIC_RESET: + { + NVIC_SystemReset(); + while(1); + } + + case RESET_SOFT_RESET: + { + SCU->RCR &= (~BIT30); + while(1); + } + + default: break; + } +} + +/********************************************************************************* +* Function : System_Enter_Standby_Mode +* Description : try to enter standby mode +* Input : none +* Output : none +* Author : xwl Date : 2021 +**********************************************************************************/ +void System_Enter_Standby_Mode(void) +{ + __set_PRIMASK(1); // disable interrupt + SysTick->CTRL = 0; // disable systick + SCU->STOPCFG |= BIT11; // set PDDS=1 + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + __WFI(); + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + System_Delay(100); + + printfS("Enter Standby Mode Failed! \n"); // should not go here +} + +/********************************************************************************* +* Function : System_Clear_Stop_Wakeup +* Description : clear all stop setting and status +* Input : none +* Output : none +* Author : CWT Date : 2021 +**********************************************************************************/ +void System_Clear_Stop_Wakeup(void) +{ + EXTI->IENR = 0; + EXTI->RTENR = 0; + EXTI->FTENR = 0; + EXTI->SWIER = 0; + EXTI->PDR = 0x7FFFFFU; +} + +/********************************************************************************* +* Function : System_Enter_Stop_Mode +* Description : try to enter stop mode +* Input : STOPEntry: STOPENTRY_WFI or STOPENTRY_WFE +* Output : none +* Author : CWT Date : 2021 +**********************************************************************************/ +void System_Enter_Stop_Mode(uint8_t STOPEntry) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + SCU->STOPCFG &= (~BIT11); // PDDS=0 + + System_SysTick_Off(); + /* Select Stop mode entry */ + if(STOPEntry == STOPENTRY_WFI) + { + /* Wait For Interrupt */ + __WFI(); + } + else + { + __SEV(); + __WFE(); + __WFE(); /* Wait For Event */ + } + + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + +#ifdef HAL_SYSTICK_ENABLED // To activate macro in ACM32Fxx_HAL.h + System_SysTick_Init(); +#endif +} + +/********************************************************************************* +* Function : System_Enter_Sleep_Mode +* Description : try to enter sleep mode +* Input : SleepEntry: SLEEPENTRY_WFI or SLEEPENTRY_WFE +* Output : none +* Author : CWT Date : 2021 +**********************************************************************************/ +void System_Enter_Sleep_Mode(uint8_t SleepEntry) +{ + /* clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry */ + if(SleepEntry == SLEEPENTRY_WFI) + { + /* Wait For Interrupt */ + __WFI(); + } + else + { + + __SEV(); + __WFE(); + __WFE(); /*Wait For Event */ + } + +} + + /********************************************************************************* +* Function : System_Return_Last_Reset_Reason +* Description : Get System Last Reset Reason +* Input : none +* Output : RESET_REASON +* Author : CWT Date : 2021 +**********************************************************************************/ +RESET_REASON System_Return_Last_Reset_Reason(void) +{ + RESET_REASON i = RESET_REASON_POR; + Reset_Reason_Save = RESET_REASON_POR; + + for(i = RESET_REASON_POR; i >= RESET_REASON_POR12; i--) + { + if ((SCU->RSR) & (1U << i)) + { + SCU->RSR |= SCU_RSR_RSTFLAG_CLR; // clear reset reason flags + Reset_Reason_Save = i; + return i; + } + } + + for(i = RESET_REASON_LOW_VOLTAGE; i <= RESET_REASON_SOFT; i++) + { + if ((SCU->RSR) & (1U << i)) + { + SCU->RSR |= SCU_RSR_RSTFLAG_CLR; // clear reset reason flags + Reset_Reason_Save = i; + return i; + } + } + + return RESET_REASON_INVALID; // this should not happen +} + + /********************************************************************************* +* Function : System_Return_Saved_Reset_Reason +* Description : Get saved Reset Reason +* Input : none +* Output : RESET_REASON +* Author : CWT Date : 2021 +**********************************************************************************/ +RESET_REASON System_Return_Saved_Reset_Reason(void) +{ + return Reset_Reason_Save; +} + /********************************************************************************* +* Function : System_Set_Buzzer_Divider +* Description : set buzzer divide factor +* Input : + div: div factor, if div = 80 then output buzzer freq=HCLK/80 + enable: FUNC_DISABLE and FUNC_ENABLE +* Output : none +* Author : xwl Date : 2021 +**********************************************************************************/ +void System_Set_Buzzer_Divider(uint32_t div, FUNC_DISABLE_ENABLE enable) +{ + if (FUNC_ENABLE == enable) + { + SCU->CLKOCR = (SCU->CLKOCR & (~(0x1FFFFU << 5) ) ) | (div << 5); + SCU->CLKOCR |= BIT23; + } + else + { + SCU->CLKOCR &= (~BIT23); + } +} + diff --git a/bsp/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.h b/bsp/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.h new file mode 100644 index 0000000000..831075b7fb --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.h @@ -0,0 +1,717 @@ +/* + ****************************************************************************** + * @file System_ACM32F0x0.h + * @version V1.0.0 + * @date 2020 + * @brief CMSIS CM0 Device Peripheral Access Layer System Headler File. + ****************************************************************************** +*/ +#ifndef __SYSTEM_ACM32F0x0_H__ +#define __SYSTEM_ACM32F0x0_H__ + +#include "ACM32Fxx_HAL.h" + +/* ================================================================================ */ +/* ======================= Use Uart to Debug print ======================== */ +/* ================================================================================ */ +#define UART_DEBUG_ENABLE + +#ifdef UART_DEBUG_ENABLE + #define printfS printf +#else + #define printfS(format, ...) ((void)0) +#endif +/* ================================================================================ */ + +#define CLK_SRC_RC64M (0x00) +#define CLK_SRC_XTH_PLL (0x01) + +#define XTH_8M_CRYSTAL +//#define XTH_12M_CRYSTAL + +#define DEFAULT_SYSTEM_CLOCK (64000000) // 默认系统时钟为64MHz + +#define RD_WAIT_SET_DEFAULT 2 + +/* CLK source Index */ +#define SYS_CLK_SRC_RCH (0x00) // CLK source from RC64M +#define SYS_CLK_SRC_RC32K (0x01) // CLK source from RC32K +#define SYS_CLK_SRC_XTH (0x02) // CLK source from XTH +#define SYS_CLK_SRC_XTL (0x03) // CLK source from XTL +#define SYS_CLK_SRC_PLLCLK (0x04) // CLK source from PLLCLK + +/* APB Frequencey Division */ +#define APB_CLK_DIV_0 (0 << 8) +#define APB_CLK_DIV_2 (4 << 8) +#define APB_CLK_DIV_4 (5 << 8) +#define APB_CLK_DIV_8 (6 << 8) +#define APB_CLK_DIV_16 (7 << 8) + +/* STOP WAKEUP Sorce */ +#define STOP_WAKEUP_GPIO_PIN0 BIT0 +#define STOP_WAKEUP_GPIO_PIN1 BIT1 +#define STOP_WAKEUP_GPIO_PIN2 BIT2 +#define STOP_WAKEUP_GPIO_PIN3 BIT3 +#define STOP_WAKEUP_GPIO_PIN4 BIT4 +#define STOP_WAKEUP_GPIO_PIN5 BIT5 +#define STOP_WAKEUP_GPIO_PIN6 BIT6 +#define STOP_WAKEUP_GPIO_PIN7 BIT7 +#define STOP_WAKEUP_GPIO_PIN8 BIT8 +#define STOP_WAKEUP_GPIO_PIN9 BIT9 +#define STOP_WAKEUP_GPIO_PIN10 BIT10 +#define STOP_WAKEUP_GPIO_PIN11 BIT11 +#define STOP_WAKEUP_GPIO_PIN12 BIT12 +#define STOP_WAKEUP_GPIO_PIN13 BIT13 +#define STOP_WAKEUP_GPIO_PIN14 BIT14 +#define STOP_WAKEUP_GPIO_PIN15 BIT15 +#define STOP_WAKEUP_PERIPHERAL_LVD BIT16 +#define STOP_WAKEUP_PERIPHERAL_RTC BIT17 +#define STOP_WAKEUP_PERIPHERAL_LPUART BIT18 +#define STOP_WAKEUP_PERIPHERAL_IWDT BIT19 +#define STOP_WAKEUP_PERIPHERAL_COMP1 BIT20 +#define STOP_WAKEUP_PERIPHERAL_COMP2 BIT21 +#define STOP_WAKEUP_RESERVE BIT22 +#define STOP_WAKEUP_PERIPHERAL_USB BIT23 +#define STOP_WAKEUP_ALL (0xFFFFFFU) + +#define STANDBY_WAKEUP_PINS 6 +#define STANDBY_WAKEUP_SOURCE_IO1 BIT0 +#define STANDBY_WAKEUP_SOURCE_IO2 BIT1 +#define STANDBY_WAKEUP_SOURCE_IO3 BIT2 +#define STANDBY_WAKEUP_SOURCE_IO4 BIT3 +#define STANDBY_WAKEUP_SOURCE_IO5 BIT4 +#define STANDBY_WAKEUP_SOURCE_IO6 BIT5 +#define STANDBY_WAKEUP_SOURCE_RTC BIT6 +#define STANDBY_WAKEUP_SOURCE_ALL 0x7FU + +// sleep/low power mode definition +#define STOPENTRY_WFI 0 +#define STOPENTRY_WFE 1 + +#define SLEEPENTRY_WFI 0 +#define SLEEPENTRY_WFE 1 +/* + * @brief STOP WAKEUP EDGE structures definition + */ +typedef enum +{ + WAKEUP_RISING = 0, + WAKEUP_FALLING = 1, + WAKEUP_RISING_FALLING = 2, // 0:rising, 1:falling, 2: rising and falling +}STOP_WAKEUP_EDGE; + +typedef enum +{ + FUNC_DISABLE = 0x00U, + FUNC_ENABLE = 0x01U, +}FUNC_DISABLE_ENABLE; + +typedef enum +{ + RESET_ENABLE_SOURCE_LVD = 0x00U, + RESET_ENABLE_SOURCE_WDT = 0x01U, + RESET_ENABLE_SOURCE_IWDT = 0x02U, + RESET_ENABLE_SOURCE_LOCKUP = 0x03U, +}RESET_ENABLE_SOURCE; + +/* + * @brief Entry lowpower select interrupt mode or event mdoe + */ +typedef enum +{ + MODE_WFI = 0x01U, + MODE_WFE = 0x00U, +}enum_ENTRY_MODE_t; + +/* + * @brief System reset source + */ +typedef enum +{ + RESET_SOURCE_LOCK = 0x08U, + RESET_SOURCE_IWDT = 0x04U, + RESET_SOURCE_WDT = 0x02U, + RESET_SOURCE_LVD = 0x01U, +}enum_SRST_t; + +typedef enum +{ + RESET_SOURCE_EFC = 0x00U, + RESET_SOURCE_NVIC_RESET = 0x01U, + RESET_SOFT_RESET = 0x02U, +}RESET_SOURCE; + +/* + * @brief Peripheral Reset structures definition + */ +typedef enum +{ + RST_CAN1 = 31, + /* RSV */ + RST_LCD = 29, + RST_UAC = 28, + RST_TIM17 = 27, + RST_TIM16 = 26, + RST_TIM15 = 25, + RST_TIM14 = 24, + /* RSV */ + RST_TIM6 = 22, + RST_TIM3 = 21, + RST_TIM1 = 20, + RST_UART3 = 19, + RST_EXTI = 18, + RST_OPA = 17, + RST_COMP = 16, + RST_TKEY = 15, + RST_ADC = 14, + /* RSV */ + RST_DMA = 12, + RST_CRC = 11, + /* RSV */ + RST_WDT = 9, + RST_LPUART = 8, + RST_I2C2 = 7, + RST_I2C1 = 6, + RST_SPI2 = 5, + RST_SPI1 = 4, + RST_UART2 = 3, + RST_UART1 = 2, + RST_GPIOCD = 1, + RST_GPIOAB = 0, +}enum_RST_ID_t; + +/* + * @brief Peripheral Enable structures definition + */ +typedef enum +{ + EN_CAN1 = 38, + EN_ROM = 37, + EN_HRNG = 36, + EN_AES = 35, + EN_TIM17 = 34, + EN_TIM16 = 33, + EN_TIM15 = 32, + EN_TIM14 = 31, + /* RSV */ + EN_TIM6 = 29, + EN_TIM3 = 28, + EN_TIM1 = 27, + EN_UART3 = 26, + /* RSV */ + EN_OPA = 24, + EN_COMP = 23, + EN_TKEY = 22, + EN_ADC = 21, + EN_RTC = 20, + EN_DMA = 19, + EN_CRC = 18, + /* RSV */ + EN_LCD = 16, + EN_LPUART = 15, + EN_I2C2 = 14, + EN_I2C1 = 13, + EN_SPI2 = 12, + EN_SPI1 = 11, + EN_UART2 = 10, + EN_UART1 = 9, + + + EN_EFC = 6, + EN_SRAM = 5, + EN_EXTI = 4, + /* RSV */ + EN_WDT = 2, + EN_GPIOCD = 1, + EN_GPIOAB = 0, +}enum_Enable_ID_t; + +typedef enum +{ + RESET_REASON_LOW_VOLTAGE = 0x00U, // low voltage detected, leads to reset + RESET_REASON_WDT = 0x01U, // System WDT reset + RESET_REASON_IWDT = 0x02U, // IWDT reset + RESET_REASON_LOCKUP = 0x03U, // cortex-m0 lockup leads to reset + RESET_REASON_SYSREQ = 0x04U, // system reset + RESET_REASON_RSTN = 0x05U, // RSTN negative pulse leads to reset + RESET_REASON_EFC = 0x06U, // efc reset leads to reset + RESET_REASON_SOFT = 0x07U, // soft reset + RESET_REASON_POR12 = 0x09U, // core power on reset, rtc not reset, eg:wakeup from standby + RESET_REASON_POR = 0x0AU, // chip power on reset + RESET_REASON_INVALID, +}RESET_REASON; + +#define SYSTEM_TIMEOUT (1000000) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* (SCU) */ +/******************************************************************************/ + +/**************** Bit definition for SCU RCR register ***********************/ +#define SCU_RCR_SRST_NOMAP BIT30 +#define SCU_RCR_EFC_RST BIT29 +#define SCU_RCR_REMAP_EN BIT16 +#define SCU_RCR_LOCKRST_EN BIT3 +#define SCU_RCR_IWDTRST_EN BIT2 +#define SCU_RCR_WDTRST_EN BIT1 +#define SCU_RCR_LVDRST_EN BIT0 + +/**************** Bit definition for SCU RSR register ***********************/ +#define SCU_RSR_RSTFLAG_CLR BIT16 +#define SCU_RSR_PWRRST_F BIT10 +#define SCU_RSR_POR12RST_F BIT9 +#define SCU_RSR_SRST_F BIT8 +#define SCU_RSR_SRSTNM_F BIT7 +#define SCU_RSR_EFC_RST_F BIT6 +#define SCU_RSR_RSTN_F BIT5 +#define SCU_RSR_SYSREQRST_F BIT4 +#define SCU_RSR_LOCKRST_F BIT3 +#define SCU_RSR_IWDTRST_F BIT2 +#define SCU_RSR_WDTRST_F BIT1 +#define SCU_RSR_VDLRST_F BIT0 + +/**************** Bit definition for SCU IPRST register **********************/ +#define SCU_IPRST_UACRST BIT28 +#define SCU_IPRST_TIM17RST BIT27 +#define SCU_IPRST_TIM16RST BIT26 +#define SCU_IPRST_TIM15RST BIT25 +#define SCU_IPRST_TIM14RST BIT24 +#define SCU_IPRST_TIM6RST BIT22 +#define SCU_IPRST_TIM3RST BIT21 +#define SCU_IPRST_TIM1RST BIT20 +#define SCU_IPRST_UART3RST BIT19 +#define SCU_IPRST_EXTIRST BIT18 +#define SCU_IPRST_OPARST BIT17 +#define SCU_IPRST_CMPRST BIT16 +#define SCU_IPRST_TKEYRST BIT15 +#define SCU_IPRST_ADCRST BIT14 +#define SCU_IPRST_DMACRST BIT12 +#define SCU_IPRST_CRCRST BIT11 +#define SCU_IPRST_IWDTRST BIT10 +#define SCU_IPRST_WDTRST BIT9 +#define SCU_IPRST_LPUART BIT8 +#define SCU_IPRST_I2C2RST BIT7 +#define SCU_IPRST_I2C1RST BIT6 +#define SCU_IPRST_SPI2RST BIT5 +#define SCU_IPRST_SPI1RST BIT4 +#define SCU_IPRST_UART2RST BIT3 +#define SCU_IPRST_UART1RST BIT2 +#define SCU_IPRST_GPIO2RST BIT1 +#define SCU_IPRST_GPIO1RST BIT0 + +/**************** Bit definition for SCU CCR1 register ***********************/ +#define SCU_CCR1_SYS_CLK_SEL (BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU CCR2 register ***********************/ +#define SCU_CCR2_DIVDONE BIT31 +#define SCU_CCR2_TKSCLK_SEL BIT16 +#define SCU_CCR2_FLTCLK_SEL BIT15 +#define SCU_CCR2_LPUCLK_SEL (BIT14|BIT13) +#define SCU_CCR2_LPUARTDIV (BIT12|BIT11) +#define SCU_CCR2_PCLKDIV (BIT10|BIT9|BIT8) +#define SCU_CCR2_SYSDIV1 (BIT7|BIT6|BIT5|BIT4) +#define SCU_CCR2_SYSDIV0 (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU CIR register ***********************/ +#define SCU_CIR_RC4MRDYIC BIT21 +#define SCU_CIR_PLLLOCKIC BIT20 +#define SCU_CIR_XTHRDYIC BIT19 +#define SCU_CIR_RCHRDYIC BIT18 +#define SCU_CIR_XTLRDYIC BIT17 +#define SCU_CIR_RC32KRDYIC BIT16 +#define SCU_CIR_RC4MRDYIE BIT13 +#define SCU_CIR_PLLLOCKIE BIT12 +#define SCU_CIR_XTHRDYIE BIT11 +#define SCU_CIR_RCHRDYIE BIT10 +#define SCU_CIR_XTLRDYIE BIT9 +#define SCU_CIR_RC32KRDYIE BIT8 +#define SCU_CIR_RC4MRDYIF BIT5 +#define SCU_CIR_PLLLOCKIF BIT4 +#define SCU_CIR_XTHRDYIF BIT3 +#define SCU_CIR_RCHRDYIF BIT2 +#define SCU_CIR_XTLRDYIF BIT1 +#define SCU_CIR_RC32KRDYIF BIT0 + +/**************** Bit definition for SCU IPCKENR register ********************/ +#define SCU_IPCKENR_ROMCLKEN BIT30 +#define SCU_IPCKENR_HRNGCLKEN BIT29 +#define SCU_IPCKENR_AESCLKEN BIT28 +#define SCU_IPCKENR_TIM17CLKEN BIT27 +#define SCU_IPCKENR_TIM16CLKEN BIT26 +#define SCU_IPCKENR_TIM15CLKEN BIT25 +#define SCU_IPCKENR_TIM14CLKEN BIT24 +#define SCU_IPCKENR_TIM6CLKEN BIT22 +#define SCU_IPCKENR_TIM3CLKEN BIT21 +#define SCU_IPCKENR_TIM1CLKEN BIT20 +#define SCU_IPCKENR_UART3CLKEN BIT19 +#define SCU_IPCKENR_OPACLKEN BIT17 +#define SCU_IPCKENR_CMPCLKEN BIT16 +#define SCU_IPCKENR_TKEYCLKEN BIT15 +#define SCU_IPCKENR_ADCCLKEN BIT14 +#define SCU_IPCKENR_RTCCLKEN BIT13 +#define SCU_IPCKENR_DMACCLKEN BIT12 +#define SCU_IPCKENR_CRCCLKEN BIT11 +#define SCU_IPCKENR_LPUARTCLKEN BIT8 +#define SCU_IPCKENR_I2C2CLKEN BIT7 +#define SCU_IPCKENR_I2C1CLKEN BIT6 +#define SCU_IPCKENR_SPI2CLKEN BIT5 +#define SCU_IPCKENR_SPI1CLKEN BIT4 +#define SCU_IPCKENR_UART2CLKEN BIT3 +#define SCU_IPCKENR_UART1CLKEN BIT2 + +/**************** Bit definition for SCU IPCKENR2 register ********************/ +#define SCU_IPCKENR2_EFCCLKEN BIT6 +#define SCU_IPCKENR2_SRAMCLKEN BIT5 +#define SCU_IPCKENR2_EXTICLKEN BIT4 +#define SCU_IPCKENR2_IWDTCLKEN BIT3 +#define SCU_IPCKENR2_WDTCLKEN BIT2 +#define SCU_IPCKENR2_GPIO2CLKEN BIT1 +#define SCU_IPCKENR2_GPIO1CLKEN BIT0 + +/**************** Bit definition for SCU RCHCR register **********************/ +#define SCU_RCHCR_RC4MRDY BIT22 +#define SCU_RCHCR_RC4M_TRIM (BIT21|BIT20|BIT19|BIT18|BIT17) +#define SCU_RCHCR_RC4M_EN BIT16 +#define SCU_RCHCR_RCHRDY BIT9 +#define SCU_RCHCR_RCH_DIV BIT8 +#define SCU_RCHCR_RCH_TRIM (BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1) +#define SCU_RCHCR_RCH_EN BIT0 + +/**************** Bit definition for SCU RCHCR register **********************/ +#define SCU_XTHCR_XTHRDY BIT4 +#define SCU_XTHCR_XTH_RDYTIME (BIT3|BIT2) +#define SCU_XTHCR_XTH_BYP BIT1 +#define SCU_XTHCR_XTH_EN BIT0 +#define SCU_XTHCR_READYTIME_1024 0 +#define SCU_XTHCR_READYTIME_4096 BIT2 +#define SCU_XTHCR_READYTIME_16384 BIT3 +#define SCU_XTHCR_READYTIME_32768 (BIT3|BIT2) + +/**************** Bit definition for SCU PLLCR register **********************/ +#define SCU_PLLCR_PLL_LOCK_SEL BIT31 +#define SCU_PLLCR_PLL_FREE_RUN BIT30 +#define SCU_PLLCR_PLL_LOCK BIT29 +#define SCU_PLLCR_PLL_RUN_DLY (BIT28|BIT27|BIT26|BIT25|BIT24|BIT23) +#define SCU_PLLCR_PLL_UPDATE_EN BIT22 +#define SCU_PLLCR_PLL_SLEEP BIT21 +#define SCU_PLLCR_PLL_OD (BIT19|BIT18) +#define SCU_PLLCR_PLL_N (BIT15|BIT14) +#define SCU_PLLCR_PLL_M (BIT6|BIT5|BIT4|BIT3) +#define SCU_PLLCR_PLL_SRC_SEL (BIT2|BIT1) +#define SCU_PLLCR_PLL_EN (BIT0) + +/**************** Bit definition for SCU LDOCR register **********************/ +#define SCU_LDOCR_LPLDO12_TRIM (BIT28|BIT27|BIT26) +#define SCU_LDOCR_LPSTP_SFT BIT25 +#define SCU_LDOCR_LPLDO12_EN_SFT BIT24 +#define SCU_LDOCR_MLDO12_LOWP_SFT BIT22 +#define SCU_LDOCR_MLDO12_LV_SFT (BIT21|BIT20) +#define SCU_LDOCR_LDO18A_EN BIT19 +#define SCU_LDOCR_ANATEST_SEL (BIT18|BIT17|BIT16) +#define SCU_LDOCR_LDO18A_TRIM (BIT15|BIT14|BIT13) +#define SCU_LDOCR_LDO18_TRIM (BIT12|BIT11|BIT10) +#define SCU_LDOCR_LDO18_EN BIT9 +#define SCU_LDOCR_LDOCTL_SEL BIT8 +#define SCU_LDOCR_LDO12_TRIM (BIT7|BIT6|BIT5|BIT4) +#define SCU_LDOCR_VREF_TRIM (BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU WMR register ***********************/ +#define SCU_WMR_RTC_READY BIT6 +#define SCU_WMR_REMAP_FLAG BIT4 +#define SCU_WMR_BOOTPIN BIT3 + +/**************** Bit definition for SCU CLKOCR register ********************/ +#define SCU_CLKOCR_BUZZER2_EN BIT31 +#define SCU_CLKOCR_BUZZER2_POL BIT30 +#define SCU_CLKOCR_BUZZER2_DIV (BIT29|BIT28|BIT27|BIT26|BIT25|BIT24) +#define SCU_CLKOCR_BUZZER_EN BIT23 +#define SCU_CLKOCR_BUZZER_POL BIT22 +#define SCU_CLKOCR_BUZZER_DIV (0x3FFFE0) +#define SCU_CLKOCR_CLKOUT_SEL BIT4 +#define SCU_CLKOCR_CLKTEST_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU SYSCFG1 register ********************/ +#define SCU_SYSCFG1_TIM15_CH2_SEL (BIT25|BIT24) +#define SCU_SYSCFG1_TIM15_CH1_SEL (BIT23|BIT22) +#define SCU_SYSCFG1_TIM14_CH1_SEL BIT20 +#define SCU_SYSCFG1_IR_MODE (BIT18|BIT17) +#define SCU_SYSCFG1_IR_POL BIT16 +#define SCU_SYSCFG1_SRAM_PEF BIT8 +#define SCU_SYSCFG1_LVD_LOCK BIT2 +#define SCU_SYSCFG1_SRAM_PARITY_LOCK BIT1 +#define SCU_SYSCFG1_LOCKUP_LOCK BIT0 + +/**************** Bit definition for SCU LVDCFG register ********************/ +#define SCU_LVDCFG_LVD_VALUE BIT15 +#define SCU_LVDCFG_LVD_FILTER BIT14 +#define SCU_LVDCFG_FLT_TIME (BIT11|BIT10|BIT9) +#define SCU_LVDCFG_LVD_FLTEN BIT8 +#define SCU_LVDCFG_LVD_TRIM (BIT4|BIT3|BIT2|BIT1) +#define SCU_LVDCFG_LVDEN BIT0 + +/**************** Bit definition for SCU STOPCFG register ********************/ +#define SCU_STOPCFG_LPLDO12_LV (BIT15|BIT14|BIT13) +#define SCU_STOPCFG_TKPCLK_SEL BIT12 +#define SCU_STOPCFG_PDDS BIT11 +#define SCU_STOPCFG_TK_LPLDOLV BIT10 +#define SCU_STOPCFG_LPSTOP BIT9 +#define SCU_STOPCFG_RCH_DIV_EN BIT8 +#define SCU_STOPCFG_MLDO12_LOWP BIT6 +#define SCU_STOPCFG_MLDO12_LV (BIT5|BIT4) +#define SCU_STOPCFG_RC64MPDEN BIT3 +#define SCU_STOPCFG_RTC_WE BIT0 + +/************** Bit definition for SCU VECTOROFFSET register *****************/ +#define SCU_VECTOROFFSET_VOFFSETEN BIT0 + +/**************** Bit definition for SCU PASEL1 register *********************/ +#define SCU_PASEL1_PA7_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PASEL1_PA6_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PASEL1_PA5_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PASEL1_PA4_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PASEL1_PA3_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PASEL1_PA2_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PASEL1_PA1_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PASEL1_PA0_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PASEL2 register *********************/ +#define SCU_PASEL2_PA15_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PASEL2_PA14_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PASEL2_PA13_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PASEL2_PA12_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PASEL2_PA11_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PASEL2_PA10_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PASEL2_PA9_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PASEL2_PA8_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PBSEL1 register *********************/ +#define SCU_PBSEL1_PB7_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PBSEL1_PB6_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PBSEL1_PB5_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PBSEL1_PB4_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PBSEL1_PB3_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PBSEL1_PB2_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PBSEL1_PB1_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PBSEL1_PB0_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PBSEL2 register *********************/ +#define SCU_PBSEL2_PB15_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PBSEL2_PB14_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PBSEL2_PB13_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PBSEL2_PB12_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PBSEL2_PB11_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PBSEL2_PB10_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PBSEL2_PB9_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PBSEL2_PB8_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PASTR register **********************/ +#define SCU_PASTR_PA15_STH (BIT31|BIT30) +#define SCU_PASTR_PA14_STH (BIT29|BIT28) +#define SCU_PASTR_PA13_STH (BIT27|BIT26) +#define SCU_PASTR_PA12_STH (BIT25|BIT24) +#define SCU_PASTR_PA11_STH (BIT23|BIT22) +#define SCU_PASTR_PA10_STH (BIT21|BIT20) +#define SCU_PASTR_PA9_STH (BIT19|BIT18) +#define SCU_PASTR_PA8_STH (BIT17|BIT16) +#define SCU_PASTR_PA7_STH (BIT15|BIT14) +#define SCU_PASTR_PA6_STH (BIT13|BIT12) +#define SCU_PASTR_PA5_STH (BIT11|BIT10) +#define SCU_PASTR_PA4_STH (BIT9|BIT8) +#define SCU_PASTR_PA3_STH (BIT7|BIT6) +#define SCU_PASTR_PA2_STH (BIT5|BIT4) +#define SCU_PASTR_PA1_STH (BIT3|BIT2) +#define SCU_PASTR_PA0_STH (BIT1|BIT0) + +/**************** Bit definition for SCU PBSTR register **********************/ +#define SCU_PBSTR_PB15_STH (BIT31|BIT30) +#define SCU_PBSTR_PB14_STH (BIT29|BIT28) +#define SCU_PBSTR_PB13_STH (BIT27|BIT26) +#define SCU_PBSTR_PB12_STH (BIT25|BIT24) +#define SCU_PBSTR_PB11_STH (BIT23|BIT22) +#define SCU_PBSTR_PB10_STH (BIT21|BIT20) +#define SCU_PBSTR_PB9_STH (BIT19|BIT18) +#define SCU_PBSTR_PB8_STH (BIT17|BIT16) +#define SCU_PBSTR_PB7_STH (BIT15|BIT14) +#define SCU_PBSTR_PB6_STH (BIT13|BIT12) +#define SCU_PBSTR_PB5_STH (BIT11|BIT10) +#define SCU_PBSTR_PB4_STH (BIT9|BIT8) +#define SCU_PBSTR_PB3_STH (BIT7|BIT6) +#define SCU_PBSTR_PB2_STH (BIT5|BIT4) +#define SCU_PBSTR_PB1_STH (BIT3|BIT2) +#define SCU_PBSTR_PB0_STH (BIT1|BIT0) + +/**************** Bit definition for SCU PCSEL1 register *********************/ +#define SCU_PCSEL1_PC7_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PCSEL1_PC6_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PCSEL1_PC5_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PCSEL1_PC4_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PCSEL1_PC3_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PCSEL1_PC2_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PCSEL1_PC1_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PCSEL1_PC0_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PCSEL2 register *********************/ +#define SCU_PCSEL2_PC15_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PCSEL2_PC14_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PCSEL2_PC13_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PCSEL2_PC12_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PCSEL2_PC11_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PCSEL2_PC10_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PCSEL2_PC9_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PCSEL2_PC8_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PDSEL1 register *********************/ +#define SCU_PDSEL1_PD7_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PDSEL1_PD6_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PDSEL1_PD5_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PDSEL1_PD4_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PDSEL1_PD3_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PDSEL1_PD2_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PDSEL1_PD1_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PDSEL1_PD0_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PCSTR register **********************/ +#define SCU_PCSTR_PC12_STH (BIT25|BIT24) +#define SCU_PCSTR_PC11_STH (BIT23|BIT22) +#define SCU_PCSTR_PC10_STH (BIT21|BIT20) +#define SCU_PCSTR_PC9_STH (BIT19|BIT18) +#define SCU_PCSTR_PC8_STH (BIT17|BIT16) +#define SCU_PCSTR_PC7_STH (BIT15|BIT14) +#define SCU_PCSTR_PC6_STH (BIT13|BIT12) +#define SCU_PCSTR_PC5_STH (BIT11|BIT10) +#define SCU_PCSTR_PC4_STH (BIT9|BIT8) +#define SCU_PCSTR_PC3_STH (BIT7|BIT6) +#define SCU_PCSTR_PC2_STH (BIT5|BIT4) +#define SCU_PCSTR_PC1_STH (BIT3|BIT2) +#define SCU_PCSTR_PC0_STH (BIT1|BIT0) + +/**************** Bit definition for SCU PDSTR register **********************/ +#define SCU_PDSTR_PD7_STH (BIT15|BIT14) +#define SCU_PDSTR_PD6_STH (BIT13|BIT12) +#define SCU_PDSTR_PD5_STH (BIT11|BIT10) +#define SCU_PDSTR_PD4_STH (BIT9|BIT8) +#define SCU_PDSTR_PD3_STH (BIT7|BIT6) +#define SCU_PDSTR_PD2_STH (BIT5|BIT4) +#define SCU_PDSTR_PD1_STH (BIT3|BIT2) +#define SCU_PDSTR_PD0_STH (BIT1|BIT0) + + +/******************************************************************************/ +/* (PMU) */ +/******************************************************************************/ + +/***************** Bit definition for RTC_PMU CR Register *******************/ +#define RPMU_CR_WU6FILEN BIT29 +#define RPMU_CR_WU5FILEN BIT28 +#define RPMU_CR_WU4FILEN BIT27 +#define RPMU_CR_WU3FILEN BIT26 +#define RPMU_CR_WU2FILEN BIT25 +#define RPMU_CR_WU1FILEN BIT24 +#define RPMU_CR_EWUP6 BIT21 +#define RPMU_CR_EWUP5 BIT20 +#define RPMU_CR_EWUP4 BIT19 +#define RPMU_CR_EWUP3 BIT18 +#define RPMU_CR_EWUP2 BIT17 +#define RPMU_CR_EWUP1 BIT16 +#define RPMU_CR_BORRST_EN BIT12 +#define RPMU_CR_WK_TIME (BIT9|BIT10|BIT11) +#define RPMU_CR_STB_EN BIT8 +#define RPMU_CR_BDRST BIT6 +#define RPMU_CR_RTCEN BIT5 +#define RPMU_CR_RTCSEL (BIT2|BIT3) +#define RPMU_CR_CWUF BIT1 +#define RPMU_CR_CSBF BIT0 + +/***************** Bit definition for RTC_PMU ANACR Register *****************/ +#define RPMU_ANACR_BOR_CFG (BIT24|BIT25) +#define RPMU_ANACR_BOR_EN BIT23 +#define RPMU_ANACR_LPBGR_TRIM (BIT20|BIT21|BIT22) +#define RPMU_ANACR_RC32K_TRIM (BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) +#define RPMU_ANACR_RC32K_RDY BIT9 +#define RPMU_ANACR_RC32K_EN BIT8 +#define RPMU_ANACR_XTLDRV (BIT3|BIT4|BIT5) +#define RPMU_ANACR_XTLBYP BIT2 +#define RPMU_ANACR_XTLRDY BIT1 +#define RPMU_ANACR_XTLEN BIT0 + +/* System_Init */ +void System_Init(void); + +/* System_Core_Config */ +void System_Core_Config(void); + +/* System_Clock_Init */ +bool System_Clock_Init(uint32_t fu32_Clock); + +/* System_SysTick_Init */ +void System_SysTick_Init(void); + +/* System_Get_SystemClock */ +uint32_t System_Get_SystemClock(void); + +/* System_Get_APBClock */ +uint32_t System_Get_APBClock(void); + +/* System_Module_Reset */ +void System_Module_Reset(enum_RST_ID_t fe_ID_Index); + +/* System_Module_Enable */ +void System_Module_Enable(enum_Enable_ID_t fe_ID_Index); + +/* System_Module_Disable */ +void System_Module_Disable(enum_Enable_ID_t fe_ID_Index); + +/* System_Delay */ +void System_Delay(volatile uint32_t fu32_Delay); + +/* System_Delay_MS */ +void System_Delay_MS(volatile uint32_t fu32_Delay); + +/* System_Enable_RC32K */ +void System_Enable_RC32K(void); + +/* System_Disable_RC32K */ +void System_Disable_RC32K(void); + +/* System_Enable_XTAL */ +void System_Enable_XTAL(void); + +/* System_Disable_XTAL */ +void System_Disable_XTAL(void); + +/* System_Clear_Stop_Wakeup */ +void System_Clear_Stop_Wakeup(void); + +/* System_Enter_Standby_Mode */ +void System_Enter_Standby_Mode(void); + +/* System_Enter_Stop_Mode */ +void System_Enter_Stop_Mode(uint8_t STOPEntry); + +/* System_Enter_Sleep_Mode */ +void System_Enter_Sleep_Mode(uint8_t SleepEntry); + +/* System_Enable_Disable_Reset */ +void System_Enable_Disable_Reset(RESET_ENABLE_SOURCE source, FUNC_DISABLE_ENABLE enable_disable); + +/* System_Reset_MCU */ +void System_Reset_MCU(RESET_SOURCE source); + +/* System_Enable_Disable_RTC_Domain_Access */ +void System_Enable_Disable_RTC_Domain_Access(FUNC_DISABLE_ENABLE enable_disable); + +/* System_Return_Last_Reset_Reason */ +RESET_REASON System_Return_Last_Reset_Reason(void) ; + +/* System_Set_Buzzer_Divider */ +void System_Set_Buzzer_Divider(uint32_t div, FUNC_DISABLE_ENABLE enable); + +#endif + + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h new file mode 100644 index 0000000000..49fc76b2e0 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h @@ -0,0 +1,170 @@ +/* + ****************************************************************************** + * @file ACM32Fxx_HAL.h + * @version V1.0.0 + * @date 2020 + * @brief HAL Config header file. + ****************************************************************************** +*/ +#ifndef __ACM32FXX_HAL_H__ +#define __ACM32FXX_HAL_H__ +#ifdef __GNUC__ +#define __weak __attribute__((weak)) +#endif +/* + Uncomment the line below according to the target device used in your application +*/ + #define ACM32F0X0 /*!< ACM32F0x0xx */ +/* #define ACM32FP0X */ /*!< ACM32FP0xxx */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(ACM32F0X0) + #include "ACM32F0x0.h" +#elif defined(ACM32FP0X) + #include "ACM32FP0X.h" +#else + #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)" +#endif +/** + * @} + */ + + +/* + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +}HAL_StatusTypeDef; + +/* USE FULL ASSERT */ +#define USE_FULL_ASSERT (1) + +#define HAL_DMA_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDT_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_EFLASH_MODULE_ENABLED +#define HAL_OPA_MODULE_ENABLED +#define HAL_COMP_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_LPUART_MODULE_ENABLED +#define HAL_WDT_MODULE_ENABLED +#define HAL_FSUSB_MODULE_ENABLED +#define HAL_LCD_MODULE_ENABLED +//#define HAL_SYSTICK_ENABLED +#define HAL_CRC_ENABLED +#define HAL_TKEY_MODULE_ENABLED +#define HAL_AES_ENABLED +#define HAL_HRNG_ENABLED +#define HAL_DIV_ENABLED + +#include "System_ACM32F0x0.h" + +#ifdef HAL_DMA_MODULE_ENABLED + #include "HAL_DMA.h" +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "HAL_GPIO.h" +#endif + +#ifdef HAL_UART_MODULE_ENABLED + #include "HAL_UART.h" + #include "HAL_UART_EX.h" +#endif + +#ifdef HAL_ADC_MODULE_ENABLED + #include "HAL_ADC.h" +#endif + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "HAL_EXTI.h" +#endif + +#ifdef HAL_I2C_MODULE_ENABLED + #include "HAL_I2C.h" +#endif + + +#ifdef HAL_RTC_MODULE_ENABLED + #include "HAL_RTC.h" +#endif + +#ifdef HAL_SPI_MODULE_ENABLED + #include "HAL_SPI.h" +#endif + +#ifdef HAL_IWDT_MODULE_ENABLED + #include "HAL_IWDT.h" +#endif + +#ifdef HAL_EFLASH_MODULE_ENABLED + #include "HAL_EFLASH.h" + #include "HAL_EFlash_EX.h" +#endif + +#ifdef HAL_OPA_MODULE_ENABLED + #include "HAL_OPA.h" +#endif + +#ifdef HAL_COMP_MODULE_ENABLED + #include "HAL_COMP.h" +#endif + +#ifdef HAL_CAN_MODULE_ENABLED + #include "HAL_CAN.h" +#endif + +#ifdef HAL_LPUART_MODULE_ENABLED + #include "HAL_LPUART.h" +#endif + +#ifdef HAL_WDT_MODULE_ENABLED + #include "HAL_WDT.h" +#endif + +#ifdef HAL_TIMER_MODULE_ENABLED + #include "HAL_TIMER.h" + #include "HAL_TIMER_EX.h" +#endif +#ifdef HAL_LCD_MODULE_ENABLED + #include "HAL_LCD.h" +#endif + + +#ifdef HAL_TKEY_MODULE_ENABLED + #include "HAL_TKEY.h" +#endif +#ifdef HAL_CRC_ENABLED +#include "HAL_CRC.h" +#endif + +#ifdef HAL_AES_ENABLED +#include "HAL_AES.h" +#endif + +#ifdef HAL_HRNG_ENABLED +#include "HAL_HRNG.h" +#endif + +#ifdef HAL_DIV_ENABLED +#include "HAL_DIV.h" +#endif + + +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_ADC.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_ADC.h new file mode 100644 index 0000000000..5804459f37 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_ADC.h @@ -0,0 +1,638 @@ +/* + ****************************************************************************** + * @file HAL_ADC.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of ADC HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_ADC_H__ +#define __HAL_ADC_H__ + +#include "ACM32Fxx_HAL.h" + +/**************** Total definition for ADC **************************/ +#define ADC_CH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_SR register **************************/ +#define ADC_SR_AWD (BIT5) +#define ADC_SR_OVERF (BIT4) +#define ADC_SR_EOG (BIT3) +#define ADC_SR_JEOC (BIT2) +#define ADC_SR_EOC (BIT1) +#define ADC_SR_ADRDY (BIT0) + +/**************** Bit definition for ADC_IE register **************************/ +#define ADC_IE_AWDIE (BIT5) +#define ADC_IE_OVERFIE (BIT4) +#define ADC_IE_EOGIE (BIT3) +#define ADC_IE_JEOCIE (BIT2) +#define ADC_IE_EOCIE (BIT1) + +/**************** Bit definition for ADC_CR1 register **************************/ +#define ADC_CR1_AWDJCH_POS (27U) +#define ADC_CR1_AWDJCH_MASK (BIT31|BIT30|BIT29|BIT28|BIT27) +#define ADC_CR1_DISCNUM_POS (23U) +#define ADC_CR1_DISCNUM_MASK (BIT26|BIT25|BIT24|BIT23) +#define ADC_CR1_DISCEN BIT22 +#define ADC_CR1_CONT BIT21 +#define ADC_CR1_SWSTART BIT20 +#define ADC_CR1_JSWSTART BIT19 +#define ADC_CR1_EXTSEL_POS (16U) +#define ADC_CR1_EXTSEL_MASK (BIT18|BIT17|BIT16) +#define ADC_CR1_JEXTSEL_POS (13U) +#define ADC_CR1_JEXTSEL_MASK (BIT15|BIT14|BIT13) +#define ADC_CR1_DMA BIT12 +#define ADC_CR1_AWDEN BIT11 +#define ADC_CR1_JAWDEN BIT10 +#define ADC_CR1_JEN BIT9 +#define ADC_CR1_AWDSGL BIT8 +#define ADC_CR1_AWDCH_POS (0U) +#define ADC_CR1_AWDCH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_CR2 register **************************/ +#define ADC_CR2_FASTMOD BIT27 +#define ADC_CR2_AFE_RSTN BIT26 +#define ADC_CR2_JOVSE BIT25 +#define ADC_CR2_JTOVS BIT24 +#define ADC_CR2_OVSS_POS (20U) +#define ADC_CR2_OVSS_MASK (BIT23|BIT22|BIT21|BIT20) +#define ADC_CR2_OVSR_POS (17U) +#define ADC_CR2_OVSR_MASK (BIT19|BIT18|BIT17) +#define ADC_CR2_OVSE BIT16 +#define ADC_CR2_BUF_STIME_POS (8U) +#define ADC_CR2_BUF_STIME_MASK (BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8) +#define ADC_CR2_EN_BUF BIT7 +#define ADC_CR2_DIV_POS (3U) +#define ADC_CR2_DIV_MASK (BIT6|BIT5|BIT4|BIT3) +#define ADC_CR2_ADC_STP BIT2 +#define ADC_CR2_OVRMOD BIT1 +#define ADC_CR2_ADC_EN BIT0 + +/**************** Bit definition for ADC_SMPR1 register **************************/ +#define ADC_SMPR_CH_MASK (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_DIFF register **************************/ +#define ADC_DIFF_DIFF7_F BIT7 +#define ADC_DIFF_DIFF6_E BIT6 +#define ADC_DIFF_DIFF5_D BIT5 +#define ADC_DIFF_DIFF4_C BIT4 +#define ADC_DIFF_DIFF3_B BIT3 +#define ADC_DIFF_DIFF2_A BIT2 +#define ADC_DIFF_DIFF1_9 BIT1 +#define ADC_DIFF_DIFF0_8 BIT0 + +/**************** Bit definition for ADC_HTR register ***********************/ +#define ADC_HTR_DHT (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16) +#define ADC_HTR_HT (BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_LTR register ***********************/ +#define ADC_LTR_DLT (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16) +#define ADC_LTR_LT (BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_SQR1 register ***********************/ +#define ADC_SQR1_L (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_JSQR register ***********************/ +#define ADC_JSQR_JSQ (BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_JDR register ***********************/ +#define ADC_JDR_JCH (BIT20|BIT19|BIT18|BIT17|BIT16) + +/**************** Bit definition for ADC_DR register ***********************/ +#define ADC_DR_CH (BIT20|BIT19|BIT18|BIT17|BIT16) + +/**************** Bit definition for ADC_SIGN register ***********************/ +#define ADC_SIGN_SIGN7_F BIT7 +#define ADC_SIGN_SIGN6_E BIT6 +#define ADC_SIGN_SIGN5_D BIT5 +#define ADC_SIGN_SIGN4_C BIT4 +#define ADC_SIGN_SIGN3_B BIT3 +#define ADC_SIGN_SIGN2_A BIT2 +#define ADC_SIGN_SIGN1_9 BIT1 +#define ADC_SIGN_SIGN0_8 BIT0 + +/**************** Bit definition for ADC_TSREF register ***********************/ +#define ADC_TSREF_VREF1P2_EN BIT31 +#define ADC_TSREF_HIZ_EN BIT27 +#define ADC_TSREF_VREFBI_SEL_POS (25U) +#define ADC_TSREF_VREFBI_SEL_MASK (BIT26|BIT25) +#define ADC_TSREF_VREFBI_EN BIT24 +#define ADC_TSREF_VTRIM_POS (19U) +#define ADC_TSREF_VTRIM_MASK (BIT23|BIT22|BIT21|BIT20|BIT19) +#define ADC_TSREF_TTRIM_POS (15U) +#define ADC_TSREF_TTRIM_MASK (BIT18|BIT17|BIT16|BIT15) +#define ADC_TSREF_ALG_MEAN_POS (9U) +#define ADC_TSREF_ALG_MEAN_MASK (BIT10|BIT9) +#define ADC_TSREF_ADJ_TD_OS_POS (5U) +#define ADC_TSREF_ADJ_TD_OS_MASK (BIT8|BIT7|BIT6|BIT5) +#define ADC_TSREF_ADJ_TD_GA_POS (1U) +#define ADC_TSREF_ADJ_TD_GA_MASK (BIT4|BIT3|BIT2|BIT1) +#define ADC_TSREF_EN_TS BIT0 + +/**************** Macro definition for register operation **************************/ + + +/**************** Enable the specified ADC. **************************/ +#define __HAL_ADC_ENABLE(__HANDLE__) \ + (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADC_EN))) + +/**************** Disable the specified ADC. **************************/ +#define __HAL_ADC_DISABLE(__HANDLE__) \ + (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADC_EN))) + +/**************** Enable the specified ADC interrupt source. **************************/ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (SET_BIT((__HANDLE__)->Instance->IE, (__INTERRUPT__))) + +/**************** Disable the specified ADC interrupt source. **************************/ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (CLEAR_BIT((__HANDLE__)->Instance->IE, (__INTERRUPT__))) + +/**************** Checks if the specified ADC interrupt source is enabled or disabled. **************************/ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IE & (__INTERRUPT__)) == (__INTERRUPT__)) + +/**************** Get the selected ADC's flag status. **************************/ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/**************** Clear the selected ADC's flag status. **************************/ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (SET_BIT((__HANDLE__)->Instance->SR, (__FLAG__))) + +/**************** Checks if the ADC regular group trig source is the specified source. **************************/ +#define __HAL_ADC_CHECK_TRIG_REGULAR(__HANDLE__, __TRIGSOURCE__) \ + ((((__HANDLE__)->Instance->CR1 & ADC_CR1_EXTSEL_MASK) >> ADC_CR1_EXTSEL_POS) == (__TRIGSOURCE__)) + +/**************** Checks if the ADC injected channel trig source is the specified source. **************************/ +#define __HAL_ADC_CHECK_TRIG_INJECTED(__HANDLE__, __TRIGSOURCE__) \ + ((((__HANDLE__)->Instance->CR1 & ADC_CR1_JEXTSEL_MASK) >> ADC_CR1_JEXTSEL_POS) == (__TRIGSOURCE__)) + +/**************** Bit definition for ADC_SMPR3 register **************************/ +#define ADC_SMPR3_CONV_PLUS_POS (20U) +#define ADC_SMPR3_CONV_PLUS_MASK (BIT21|BIT20) + +/** + * @brief ADC ExTigger structure definition + */ +typedef struct +{ + uint32_t ExTrigSel; /*!< Configures the regular channel trig mode. */ + uint32_t JExTrigSel; /*!< Configures the inject channel trig mode. */ +}ADC_ExTrigTypeDef; + +/** + * @brief ADC group regular oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_CR2_OVSR_2X*/ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_CR2_OVSS_0 */ + + uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. + This parameter can be a value of + 0 : trig 1 time; other: trig N times, N refer to the oversampling Ratio*/ +}ADC_OversamplingTypeDef; + +/******************************** ADC Init mode define *******************************/ +/******************************** ConConvMode define *******************************/ +#define ADC_CONCONVMODE_DISABLE (0) +#define ADC_CONCONVMODE_ENABLE (1) + +/******************************** JChannelMode define *******************************/ +#define ADC_JCHANNELMODE_DISABLE (0) +#define ADC_JCHANNELMODE_ENABLE (1) + +/******************************** DiffMode define *******************************/ +#define ADC_DIFFMODE_DISABLE (0) +#define ADC_DIFFMODE_ENABLE (1) + +/******************************** DMAMode define *******************************/ +#define ADC_DMAMODE_DISABLE (0) +#define ADC_DMAMODE_ENABLE (1) + +/******************************** OverMode define *******************************/ +#define ADC_OVERMODE_DISABLE (0) +#define ADC_OVERMODE_ENABLE (1) + +/******************************** OverSampMode define *******************************/ +#define ADC_OVERSAMPMODE_DISABLE (0) +#define ADC_OVERSAMPMODE_ENABLE (1) + +/******************************** AnalogWDGEn define *******************************/ +#define ADC_ANALOGWDGEN_DISABLE (0) +#define ADC_ANALOGWDGEN_ENABLE (1) + +/** + * @brief ADC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockDiv; /*!< Specify the ADC clock div from the PCLK. + This parameter can be set to ADC_CLOCK_DIV1 | ADC_CLOCK_DIV2 |... ADC_CLOCK_DIV16 */ + + uint32_t ConConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, + after the first ADC conversion start trigger occurred (software start or external trigger). + This parameter can be set to ADC_CONCONVMODE_DISABLE or ADC_CONCONVMODE_ENABLE. */ + uint32_t JChannelMode; /*!< Specify if support inject channel. This parameter can be set to ADC_JCHANNELMODE_DISABLE or ADC_JCHANNELMODE_ENABLE*/ + uint32_t DiffMode; /*!< Specify the differential parameters. + ADC_DIFFMODE_DISABLE:single end mode, + ADC_DIFFMODE_ENABLE:differential end mode */ + uint32_t ChannelEn; /*!< Specify the enable ADC channels. + This parameter can be set to ADC_CHANNEL_0_EN | ADC_CHANNEL_1_EN |... ADC_CHANNEL_15_EN*/ + + ADC_ExTrigTypeDef ExTrigMode; /*!< ADC ExTigger structure, config the regular and inject channel trig mode */ + + uint32_t DMAMode; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) + or in continuous mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be set to ADC_DMAMODE_ENABLE or ADC_DMAMODE_DISABLE. + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ + + uint32_t OverMode; /*!< ADC_OVERMODE_DISABLE,ADC_OVERMODE_ENABLE*/ + + uint32_t OverSampMode; /*!< Specify whether the oversampling feature is enabled or disabled. + This parameter can be set to ADC_OVERSAMPMODE_ENABLE or ADC_OVERSAMPMODE_DISABLE. + Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ + ADC_OversamplingTypeDef Oversampling; /*!< Specify ADC group regular oversampling structure. */ + + uint32_t AnalogWDGEn; +}ADC_InitTypeDef; + + +typedef struct +{ + uint32_t RjMode; /*!< Specify the channel mode, 0:regular, Other:inject*/ + uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_CHANNEL_0 + Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ + + uint32_t Sq; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Channels ordering into each rank of scan sequence: + whatever channel can be placed into whatever rank. + - sequencer configured to not fully configurable: + rank of each channel is fixed by channel HW number. + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. + This parameter can be a value of @ref ADC_SEQUENCE_SQ1 */ + + uint32_t Smp; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + This parameter can be a value of @ref ADC_SMP_CLOCK_3 */ +}ADC_ChannelConfTypeDef; + +typedef struct +{ + uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. + This parameter can be a value of @ref ADC_ANALOGWATCHDOG_RCH_ALL. */ + + uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). + This parameter can be a value of @ref ADC_CHANNEL_0. */ + + uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. */ + + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. */ +}ADC_AnalogWDGConfTypeDef; + +/******************************** ADC Over Sample Shift define *******************************/ +#define ADC_CR2_OVSS_0 (0U) +#define ADC_CR2_OVSS_1 (1U) +#define ADC_CR2_OVSS_2 (2U) +#define ADC_CR2_OVSS_3 (3U) +#define ADC_CR2_OVSS_4 (4U) +#define ADC_CR2_OVSS_5 (5U) +#define ADC_CR2_OVSS_6 (6U) +#define ADC_CR2_OVSS_7 (7U) +#define ADC_CR2_OVSS_8 (8U) + +/******************************** ADC Over Sample Rate define *******************************/ +#define ADC_CR2_OVSR_2X (0U) +#define ADC_CR2_OVSR_4X (1U) +#define ADC_CR2_OVSR_8X (2U) +#define ADC_CR2_OVSR_16X (3U) +#define ADC_CR2_OVSR_32X (4U) +#define ADC_CR2_OVSR_64X (5U) +#define ADC_CR2_OVSR_128X (6U) +#define ADC_CR2_OVSR_256X (7U) + +/******************************** ADC Sample period define *******************************/ +#define ADC_SMP_CLOCK_3 (0U) +#define ADC_SMP_CLOCK_5 (1U) +#define ADC_SMP_CLOCK_7 (2U) +#define ADC_SMP_CLOCK_10 (3U) +#define ADC_SMP_CLOCK_13 (4U) +#define ADC_SMP_CLOCK_16 (5U) +#define ADC_SMP_CLOCK_20 (6U) +#define ADC_SMP_CLOCK_30 (7U) +#define ADC_SMP_CLOCK_60 (8U) +#define ADC_SMP_CLOCK_80 (9U) +#define ADC_SMP_CLOCK_100 (10U) +#define ADC_SMP_CLOCK_120 (11U) +#define ADC_SMP_CLOCK_160 (12U) +#define ADC_SMP_CLOCK_320 (13U) +#define ADC_SMP_CLOCK_480 (14U) +#define ADC_SMP_CLOCK_640 (15U) + + +/******************************** ADC ClockPrescale define *******************************/ +#define ADC_CLOCK_DIV1 (0U) +#define ADC_CLOCK_DIV2 (1U) +#define ADC_CLOCK_DIV3 (2U) +#define ADC_CLOCK_DIV4 (3U) +#define ADC_CLOCK_DIV5 (4U) +#define ADC_CLOCK_DIV6 (5U) +#define ADC_CLOCK_DIV7 (6U) +#define ADC_CLOCK_DIV8 (7U) +#define ADC_CLOCK_DIV9 (8U) +#define ADC_CLOCK_DIV10 (9U) +#define ADC_CLOCK_DIV11 (10U) +#define ADC_CLOCK_DIV12 (11U) +#define ADC_CLOCK_DIV13 (12U) +#define ADC_CLOCK_DIV14 (13U) +#define ADC_CLOCK_DIV15 (14U) +#define ADC_CLOCK_DIV16 (15U) + +/************************ADC_AnalogWDGConfTypeDef->WatchdogMode define********************/ +#define ADC_ANALOGWATCHDOG_RCH_ALL (1U) //All regular channels +#define ADC_ANALOGWATCHDOG_JCH_ALL (2U) //All inject channels +#define ADC_ANALOGWATCHDOG_RCH_AND_JCH_ALL (3U) //All regular and inject channels +#define ADC_ANALOGWATCHDOG_RCH_SINGLE (4U) //Single regular channel +#define ADC_ANALOGWATCHDOG_JCH_SINGLE (5U) //Single Inject channel +#define ADC_ANALOGWATCHDOG_RCH_OR_JCH_SINGLE (6U) //Regular or inject channel + +/******************************** ADC sequence number define *******************************/ +#define ADC_SEQUENCE_SQ1 (1U) +#define ADC_SEQUENCE_SQ2 (2U) +#define ADC_SEQUENCE_SQ3 (3U) +#define ADC_SEQUENCE_SQ4 (4U) +#define ADC_SEQUENCE_SQ5 (5U) +#define ADC_SEQUENCE_SQ6 (6U) +#define ADC_SEQUENCE_SQ7 (7U) +#define ADC_SEQUENCE_SQ8 (8U) +#define ADC_SEQUENCE_SQ9 (9U) +#define ADC_SEQUENCE_SQ10 (10U) +#define ADC_SEQUENCE_SQ11 (11U) +#define ADC_SEQUENCE_SQ12 (12U) +#define ADC_SEQUENCE_SQ13 (13U) +#define ADC_SEQUENCE_SQ14 (14U) +#define ADC_SEQUENCE_SQ15 (15U) +#define ADC_SEQUENCE_SQ16 (16U) + +/******************************** ADC channel number define *******************************/ +#define ADC_CHANNEL_0 (0U) +#define ADC_CHANNEL_1 (1U) +#define ADC_CHANNEL_2 (2U) +#define ADC_CHANNEL_3 (3U) +#define ADC_CHANNEL_4 (4U) +#define ADC_CHANNEL_5 (5U) +#define ADC_CHANNEL_6 (6U) +#define ADC_CHANNEL_7 (7U) +#define ADC_CHANNEL_8 (8U) +#define ADC_CHANNEL_9 (9U) +#define ADC_CHANNEL_10 (10U) +#define ADC_CHANNEL_11 (11U) +#define ADC_CHANNEL_12 (12U) +#define ADC_CHANNEL_13 (13U) +#define ADC_CHANNEL_14 (14U) +#define ADC_CHANNEL_15 (15U) +#define ADC_CHANNEL_TEMP (16U) +#define ADC_CHANNEL_VBAT (17U) +#define ADC_CHANNEL_VBGR (18U) +#define ADC_CHANNEL_EXT2 (19U) +#define ADC_CHANNEL_EXT3 (20U) + +/******************************** ADC channel enable define *******************************/ +#define ADC_CHANNEL_0_EN (BIT0) +#define ADC_CHANNEL_1_EN (BIT1) +#define ADC_CHANNEL_2_EN (BIT2) +#define ADC_CHANNEL_3_EN (BIT3) +#define ADC_CHANNEL_4_EN (BIT4) +#define ADC_CHANNEL_5_EN (BIT5) +#define ADC_CHANNEL_6_EN (BIT6) +#define ADC_CHANNEL_7_EN (BIT7) +#define ADC_CHANNEL_8_EN (BIT8) +#define ADC_CHANNEL_9_EN (BIT9) +#define ADC_CHANNEL_10_EN (BIT10) +#define ADC_CHANNEL_11_EN (BIT11) +#define ADC_CHANNEL_12_EN (BIT12) +#define ADC_CHANNEL_13_EN (BIT13) +#define ADC_CHANNEL_14_EN (BIT14) +#define ADC_CHANNEL_15_EN (BIT15) +#define ADC_CHANNEL_TEMP_EN (BIT16) +#define ADC_CHANNEL_VBAT_EN (BIT17) +#define ADC_CHANNEL_VBGR_EN (BIT18) +#define ADC_CHANNEL_EXT2_EN (BIT19) +#define ADC_CHANNEL_EXT3_EN (BIT20) + +/******************************** ADC Trig source define******************************* + * | Trig Source | ACM32FXXX/FPXXX | ACM32F0X0 | * + * | ADC_SOFTWARE_START | SWSTART/JSWSTART | SWSTART/JSWSTART | * + * | ADC_EXTERNAL_TIG1 | TIM1_TRGO | TIM1_TRGO | * + * | ADC_EXTERNAL_TIG2 | TIM1_CC4 | TIM1_CC4 | * + * | ADC_EXTERNAL_TIG3 | TIM2_TRGO | RSV | * + * | ADC_EXTERNAL_TIG4 | TIM3_TRGO | TIM3_TRGO | * + * | ADC_EXTERNAL_TIG5 | TIM4_TRGO | TIM15_TRGO | * + * | ADC_EXTERNAL_TIG6 | TIM6_TRGO | TIM6_TRGO | * + * | ADC_EXTERNAL_TIG7 | EXTi Line 11 | EXTi Line 11 | */ +#define ADC_SOFTWARE_START (0U) +#define ADC_EXTERNAL_TIG1 (1U) +#define ADC_EXTERNAL_TIG2 (2U) +#define ADC_EXTERNAL_TIG3 (3U) +#define ADC_EXTERNAL_TIG4 (4U) +#define ADC_EXTERNAL_TIG5 (5U) +#define ADC_EXTERNAL_TIG6 (6U) +#define ADC_EXTERNAL_TIG7 (7U) + + +/******************************** ADC results flag define for HAL level*******************************/ +#define HAL_ADC_EOC_FLAG 0x80000000 +#define HAL_ADC_JEOC_FLAG 0x40000000 +#define HAL_ADC_AWD_FLAG 0x20000000 + +/** + * @brief ADC handle Structure definition + */ +typedef struct __ADC_HandleTypeDef +{ + ADC_TypeDef *Instance; /*!< Register base address */ + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + uint32_t ChannelNum; /*!< Total enable regular group channel number*/ + uint32_t *AdcResults; /*!< Point to the convert results*/ + void (*ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (*GroupCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC regular group conversion complete callback */ + void (*InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC injected conversion complete callback */ + void (*LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog callback */ +}ADC_HandleTypeDef; + +/******************************** ADC Instances *******************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC) +#define IS_ADC_ALL_CONCONVMODE(CONCONVMODE) (((CONCONVMODE) == ADC_CONCONVMODE_DISABLE) || \ + ((CONCONVMODE) == ADC_CONCONVMODE_ENABLE)) + +#define IS_ADC_ALL_JCHANNELMODE(JCHANNELMODE) (((JCHANNELMODE) == ADC_JCHANNELMODE_DISABLE) || \ + ((JCHANNELMODE) == ADC_JCHANNELMODE_ENABLE)) + +#define IS_ADC_ALL_DIFFMODE(DIFFMODE) (((DIFFMODE) == ADC_DIFFMODE_DISABLE) || \ + ((DIFFMODE) == ADC_DIFFMODE_ENABLE)) + +#define IS_ADC_ALL_DMAMODE(DMAMODE) (((DMAMODE) == ADC_DMAMODE_DISABLE) || \ + ((DMAMODE) == ADC_DMAMODE_ENABLE)) + +#define IS_ADC_ALL_OVERMODE(OVERMODE) (((OVERMODE) == ADC_OVERMODE_DISABLE) || \ + ((OVERMODE) == ADC_OVERMODE_ENABLE)) + +#define IS_ADC_ALL_OVERSAMPMODE(OVERSAMPMODE) (((OVERSAMPMODE) == ADC_OVERSAMPMODE_DISABLE) || \ + ((OVERSAMPMODE) == ADC_OVERSAMPMODE_ENABLE)) + +#define IS_ADC_ALL_OVSS(_OVSS) (((_OVSS) == ADC_CR2_OVSS_0) || \ + ((_OVSS) == ADC_CR2_OVSS_1) || \ + ((_OVSS) == ADC_CR2_OVSS_2) || \ + ((_OVSS) == ADC_CR2_OVSS_3) || \ + ((_OVSS) == ADC_CR2_OVSS_4) || \ + ((_OVSS) == ADC_CR2_OVSS_5) || \ + ((_OVSS) == ADC_CR2_OVSS_6) || \ + ((_OVSS) == ADC_CR2_OVSS_7) || \ + ((_OVSS) == ADC_CR2_OVSS_8)) + +#define IS_ADC_ALL_OVSR(_OVSR) (((_OVSR) == ADC_CR2_OVSR_2X) || \ + ((_OVSR) == ADC_CR2_OVSR_4X) || \ + ((_OVSR) == ADC_CR2_OVSR_8X) || \ + ((_OVSR) == ADC_CR2_OVSR_16X) || \ + ((_OVSR) == ADC_CR2_OVSR_32X) || \ + ((_OVSR) == ADC_CR2_OVSR_64X) || \ + ((_OVSR) == ADC_CR2_OVSR_128X) || \ + ((_OVSR) == ADC_CR2_OVSR_256X)) + +#define IS_ADC_ALL_ANALOGWDGEN(ANALOGWDGEN) (((ANALOGWDGEN) == ADC_ANALOGWDGEN_DISABLE) || \ + ((ANALOGWDGEN) == ADC_ANALOGWDGEN_ENABLE)) + +#define IS_ADC_ALL_CLOCKDIV(CLOCKDIV) (((CLOCKDIV) == ADC_CLOCK_DIV1) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV2) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV3) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV4) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV5) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV6) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV7) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV8) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV9) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV10) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV11) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV12) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV13) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV14) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV15) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV16)) + +#define IS_ADC_ALL_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_SEQUENCE_SQ1) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ2) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ3) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ4) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ5) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ6) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ7) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ8) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ9) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ10) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ11) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ12) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ13) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ14) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ15) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ16)) + +#define IS_ADC_ALL_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_TEMP) || \ + ((CHANNEL) == ADC_CHANNEL_VBAT) || \ + ((CHANNEL) == ADC_CHANNEL_VBGR) || \ + ((CHANNEL) == ADC_CHANNEL_EXT2) || \ + ((CHANNEL) == ADC_CHANNEL_EXT3)) + +#define IS_ADC_ALL_CHANNELEN(CHANNELEN) ((CHANNELEN) <= 0x1FFFFF) + +#define IS_ADC_ALL_SMPCLOCK(SMPCLOCK) (((SMPCLOCK) == ADC_SMP_CLOCK_3) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_5) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_7) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_10) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_13) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_16) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_20) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_30) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_60) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_80) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_100) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_120) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_160) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_320) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_480) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_640)) + +#define IS_ADC_ALL_TRIG(_TRIG) (((_TRIG) == ADC_SOFTWARE_START) || \ + ((_TRIG) == ADC_EXTERNAL_TIG1) || \ + ((_TRIG) == ADC_EXTERNAL_TIG2) || \ + ((_TRIG) == ADC_EXTERNAL_TIG3) || \ + ((_TRIG) == ADC_EXTERNAL_TIG4) || \ + ((_TRIG) == ADC_EXTERNAL_TIG5) || \ + ((_TRIG) == ADC_EXTERNAL_TIG6) || \ + ((_TRIG) == ADC_EXTERNAL_TIG7)) + +#define IS_ADC_EVENT_TYPE(_EVENT) (((_EVENT) == ADC_SR_AWD) || \ + ((_EVENT) == ADC_SR_OVERF) || \ + ((_EVENT) == ADC_SR_EOG) || \ + ((_EVENT) == ADC_SR_JEOC) || \ + ((_EVENT) == ADC_SR_EOC)) + +/* Function : HAL_ADC_IRQHandler */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_InjectedGetValue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Polling(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length, uint32_t Timeout); + +#endif + + + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h new file mode 100644 index 0000000000..ded00bff01 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h @@ -0,0 +1,83 @@ +/*********************************************************************** + * Copyright (c) 2008 - 2016, Shanghai AisinoChip Co.,Ltd . + * All rights reserved. + * Filename : aes.h + * Description : aes driver header file + * Author(s) : Eric + * version : V1.0 + * Modify date : 2016-03-24 + ***********************************************************************/ +#ifndef __AES_H__ +#define __AES_H__ + +#include "ACM32Fxx_HAL.h" + +#define AES_ENCRYPTION 1 +#define AES_DECRYPTION 0 +#define AES_ECB_MODE 0 +#define AES_CBC_MODE 1 +#define AES_SWAP_ENABLE 1 +#define AES_SWAP_DISABLE 0 + +#define AES_NORMAL_MODE 0x12345678 +#define AES_SECURITY_MODE 0 + +#define AES_KEY_128 0 +#define AES_KEY_192 1 +#define AES_KEY_256 2 + +#define AES_FAIL 0x00 +#define AES_PASS 0xa59ada68 + +/****************************************************************************** +Name: HAL_AES_Set_Key +Function: set aes key for encryption and decryption +Input: + keyin -- pointer to buffer of key + swap_en -- AES_SWAP_ENABLE, AES_SWAP_DISABLE +Return: None +*******************************************************************************/ +void HAL_AES_Set_Key(UINT32 *keyin, UINT8 key_len, UINT8 swap_en); +void HAL_AES_Set_Key_U8(UINT8 *keyin, UINT8 key_len, UINT8 swap_en); + + +/****************************************************************************** + +Name: HAL_Aes_Crypt +Function: Function for des encryption and decryption +Input: + indata -- pointer to buffer of input + outdata -- pointer to buffer of result + block_len -- block(128bit) length for des cryption + operation -- AES_ENCRYPTION,AES_DECRYPTION + mode -- AES_ECB_MODE, AES_CBC_MODE, + iv -- initial vector for CBC mode + security_mode -- AES_NORMAL_MODE, AES_SECURITY_MDOE， +Return: None + +*******************************************************************************/ +UINT32 HAL_AES_Crypt( + UINT32 *indata, + UINT32 *outdata, + UINT32 block_len, + UINT8 operation, + UINT8 mode, + UINT32 *iv, + UINT32 security_mode +); + + +UINT32 HAL_AES_Crypt_U8( + UINT8 *indata, + UINT8 *outdata, + UINT32 block_len, + UINT8 operation, + UINT8 mode, + UINT8 *iv, + UINT32 security_mode +); + +#endif +/****************************************************************************** + * end of file +*******************************************************************************/ diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h new file mode 100644 index 0000000000..72fa39b9d4 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h @@ -0,0 +1,393 @@ +/* + ****************************************************************************** + * @file HAL_Can.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of CAN HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_CAN_H__ +#define __HAL_CAN_H__ + +#include "ACM32Fxx_HAL.h" + +/** + * @} + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* (CAN) */ +/******************************************************************************/ + +/**************** Bit definition for CAN MOD register ***********************/ +#define CAN_MOD_RM BIT0 +#define CAN_MOD_LOM BIT1 +#define CAN_MOD_STM BIT2 +#define CAN_MOD_AFM BIT3 +#define CAN_MOD_SM BIT4 +/**************** Bit definition for CAN CMR register ***********************/ +#define CAN_CMR_TR BIT0 +#define CAN_CMR_AT BIT1 +#define CAN_CMR_RRB BIT2 +#define CAN_CMR_CDO BIT3 +#define CAN_CMR_SRR BIT4 +/**************** Bit definition for CAN SR register ***********************/ +#define CAN_SR_RBS BIT0 +#define CAN_SR_DOS BIT1 +#define CAN_SR_TBS BIT2 +#define CAN_SR_TCS BIT3 +#define CAN_SR_RS BIT4 +#define CAN_SR_TS BIT5 +#define CAN_SR_ES BIT6 +#define CAN_SR_BS BIT7 +/**************** Bit definition for CAN IR register ***********************/ +#define CAN_IR_RI BIT0 +#define CAN_IR_TI BIT1 +#define CAN_IR_EI BIT2 +#define CAN_IR_DOI BIT3 +#define CAN_IR_WUI BIT4 +#define CAN_IR_EPI BIT5 +#define CAN_IR_ALI BIT6 +#define CAN_IR_BEI BIT7 +/**************** Bit definition for CAN IER register ***********************/ +#define CAN_IER_RIE BIT0 +#define CAN_IER_TIE BIT1 +#define CAN_IER_EIE BIT2 +#define CAN_IER_DOIE BIT3 +#define CAN_IER_WUIE BIT4 +#define CAN_IER_EPIE BIT5 +#define CAN_IER_ALIE BIT6 +#define CAN_IER_BEIE BIT7 + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_mode e.g:CAN_Mode_Normal CAN_Mode_Normal*/ + + uint32_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_SJW e.g:CAN_SJW_1tq--CAN_SJW_4tq*/ + + uint32_t CAN_BRP ; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value between 0 and 63 */ + + uint32_t CAN_TSEG1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_TSEG1 e.g: CAN_TSEG1_1tq-CAN_TSEG1_16tq*/ + + uint32_t CAN_TSEG2; /*!< Specifies the number of time quanta in Bit + Segment 2.This parameter can be a value of + @ref CAN_TSEG2 e.g:CAN_TSEG1_1tq-CAN_TSEG16_tq*/ + + uint32_t CAN_SAM ; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_SAM e.g:CAN_SAM_1time CAN_SAM_3time*/ +} CAN_InitTypeDef; + + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint32_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of + @ref CAN_filter_mode e.g:CAN_FilterMode_Dual CAN_FilterMode_Single*/ + + uint32_t CAN_FilterId1; /*!< Specifies the filter identification number + This parameter can be a value between 0x0000 and 0x1FFFFFFF */ + + uint32_t CAN_FilterId2; /*!< Specifies the filter identification number + only CAN_FilterMode=CAN_FilterMode_Dual Enable + This parameter can be a value between 0x0000 and 0x1FFFFFFF */ + + uint32_t CAN_FilterMaskId1; /*!< Specifies the filter identification mask number + This parameter can be a value between 0x0000 and 0x1FFFFFFF */ + + uint32_t CAN_FilterMaskId2; /*!< Specifies the filter identification mask number + only CAN_FilterMode=CAN_FilterMode_Dual Enable + This parameter can be a value between 0x0000 and 0x1FFFFFFF */ +} CAN_FilterInitTypeDef; + + + +/** + * @brief CAN RxTxMessege structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type e.g: CAN_Id_Standard CAN_Id_Extended*/ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission e.g: CAN_RTR_Data CAN_RTR_Remote */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ +} CanTxRxMsg; + + +/** + * @brief CAN handle Structure definition + */ +typedef struct __CAN_HandleTypeDef +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxRxMsg *RxMessage; /*!< CAN RxMessage */ + + void (*CAN_ReceiveIT_Callback)(struct __CAN_HandleTypeDef *hcan); /* CAN ReceiveIT complete callback */ + + void (*CAN_TransmitIT_Callback)(struct __CAN_HandleTypeDef *hcan); /* CAN TransmitIT complete callback */ + +} CAN_HandleTypeDef; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1)) + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000001) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) +/** + * @} + */ +/** @defgroup CAN_remote_transmission + * @{ + */ + +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000001) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/** + * @} + */ +/** @defgroup CAN_TxRxMessege + * @{ + */ + +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_SR_RBS) || ((FLAG) == CAN_SR_DOS) || \ + ((FLAG) == CAN_SR_TBS) || ((FLAG) == CAN_SR_TCS) || \ + ((FLAG) == CAN_SR_RS) || ((FLAG) == CAN_SR_TS) || \ + ((FLAG) == CAN_SR_ES) || ((FLAG) == CAN_SR_BS)) + +#define IS_CAN_BRP(BRP) (((BRP) <= 63)) + +/** + * @defgroup CAN_Mode + * @{ + */ +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< Normal mode */ +#define CAN_Mode_SlefTest ((uint8_t)0x01) /*!< SlefTest mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) ||\ + ((MODE) == CAN_Mode_SlefTest)) +/** + * @} + */ + +/** + * @defgroup CAN_Operating_Mode + * @{ + */ +#define CAN_OperatingMode_Normal ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Listen ((uint8_t)0x02) /*!< Listen mode */ +#define CAN_OperatingMode_SelfTest ((uint8_t)0x04) /*!< Listen mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x10) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)|| \ + ((MODE) == CAN_OperatingMode_SelfTest)|| \ + ((MODE) == CAN_OperatingMode_Listen)) +/** + * @} + */ + +/** @defgroup CAN_SAM + * @{ + */ + +#define CAN_SAM_1time ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SAM_3time ((uint8_t)0x01) /*!< 2 time quantum */ + +#define IS_CAN_SAM(SAM) (((SAM) == CAN_SAM_1time) || ((SAM) == CAN_SAM_3time)) +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + + /** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_TSEG1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TSEG1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TSEG1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TSEG1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TSEG1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TSEG1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TSEG1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TSEG1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_TSEG1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_TSEG1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_TSEG1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_TSEG1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_TSEG1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_TSEG1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_TSEG1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_TSEG1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_TSEG1(TSEG1) ((TSEG1) <= CAN_TSEG1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_TSEG2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TSEG2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TSEG2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TSEG2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TSEG2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TSEG2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TSEG2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TSEG2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define IS_CAN_TSEG2(TSEG) ((TSEG) <= CAN_TSEG2_8tq) +/** + * @} + */ + + +/** @defgroup CAN_filter_mode + * @{ + */ +#define CAN_FilterMode_Dual ((uint8_t)0x00) /*!< identifier list mode */ +#define CAN_FilterMode_Single ((uint8_t)0x01) /*!< identifier/mask mode */ +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_Dual) || \ + ((MODE) == CAN_FilterMode_Single)) + + /** + * @} + */ + +/** @defgroup CAN_ErrorCode + * @{ + */ +#define CAN_ErrorType_ErrCode ((uint8_t)0xC0) /*!< identifier list mode */ +#define CAN_ErrorType_Direction ((uint8_t)0x20) /*!< identifier/mask mode */ +#define CAN_ErrorType_SegCode ((uint8_t)0x1F) /*!< identifier/mask mode */ +#define IS_CAN_ErrorType(ErrorType) (((ErrorType) == CAN_ErrorType_ErrCode) || \ + ((ErrorType) == CAN_ErrorType_Direction)|| \ + ((ErrorType) == CAN_ErrorType_SegCode)) +/** + * @} + */ +/* Initialization and Configuration functions *********************************/ +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); + +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); + +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); + +void HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan,CAN_FilterInitTypeDef* CAN_FilterInitStruct); + +/* Transmit functions *********************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, CanTxRxMsg* TxMessage); + +void HAL_CAN_CancelTransmit(CAN_HandleTypeDef *hcan); + +/* Receive functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage); + +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage); + +int8_t HAL_CAN_GetReceiveFiFoCounter(CAN_HandleTypeDef *hcan); + +int8_t HAL_CAN_GetReceiveFiFoAddr(CAN_HandleTypeDef *hcan); + +void HAL_CAN_ReleaseReceiveFIFO(CAN_HandleTypeDef *hcan); + +void HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage); + +/* Operation modes functions **************************************************/ +HAL_StatusTypeDef HAL_CAN_OperatingModeRequest(CAN_HandleTypeDef *hcan, uint8_t CAN_OperatingMode); + +void HAL_CAN_ClearOverload(CAN_HandleTypeDef *hcan); + +void HAL_CAN_SelfReceive(CAN_HandleTypeDef *hcan); + +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); + +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); + +/* Error Code management functions **********************************/ +int8_t HAL_CAN_GetErrorCode(CAN_HandleTypeDef *hcan,uint32_t Error_Type); + +int8_t HAL_CAN_GetErrorAlarmCounter(CAN_HandleTypeDef *hcan); + +int8_t HAL_CAN_GetArbitrationErrorPosition(CAN_HandleTypeDef *hcan); + +int8_t HAL_CAN_GetReceiveErrorCounter(CAN_HandleTypeDef *hcan); + +int8_t HAL_CAN_GetTransmitErrorCounter(CAN_HandleTypeDef *hcan); + +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h new file mode 100644 index 0000000000..713ebcef2d --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h @@ -0,0 +1,216 @@ +/* + ****************************************************************************** + * @file HAL_COMP.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of COMP HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_COMP_H__ +#define __HAL_COMP_H__ + +#include "ACM32Fxx_HAL.h" + +#define COMP1 (0x01) +#define COMP2 (0x02) + +/**************** Bit definition for COMP_CR1 and COMP_CR2 register **************************/ +#define COMP_CR_LOCK (BIT31) +#define COMP_CR_BLANKTIME_POS (29U) +#define COMP_CR_BLANKTIME_MASK (BIT30|BIT29) +#define COMP_CR_CRV_CFG_POS (25U) +#define COMP_CR_CRV_CFG_MASK (BIT28|BIT27|BIT26|BIT25) +#define COMP_CR_CRV_SEL (BIT24) +#define COMP_CR_CRV_EN (BIT23) +#define COMP_CR_WINMODE (BIT22) +#define COMP_CR_WINOUT (BIT21) +#define COMP_CR_POLARITY (BIT20) +#define COMP_CR_FLTEN (BIT19) +#define COMP_CR_FLTTIME_POS (16U) +#define COMP_CR_FLTTIME_MASK (BIT18|BIT17|BIT16) +#define COMP_CR_BLANKSEL_POS (12U) +#define COMP_CR_BLANKSEL_MASK (BIT15|BIT14|BIT13|BIT12) +#define COMP_CR_INPSEL_POS (8U) +#define COMP_CR_INPSEL_MASK (BIT11|BIT10|BIT9|BIT8) +#define COMP_CR_INMSEL_POS (4U) +#define COMP_CR_INMSEL_MASK (BIT7|BIT6|BIT5|BIT4) +#define COMP_CR_HYS_POS (1U) +#define COMP_CR_HYS_MASK (BIT3|BIT2|BIT1) +#define COMP_CR_EN (BIT0) + +/**************** Bit definition for COMP_SR register **************************/ +#define COMP_SR_VCOUT2_ORG (BIT3) +#define COMP_SR_VCOUT1_ORG (BIT2) +#define COMP_SR_VCOUT2 (BIT1) +#define COMP_SR_VCOUT1 (BIT0) + +/** + * @brief COMP Configuration Structure definition + */ +typedef struct +{ + uint8_t Comparator; /*!< Specify witch comparator be selected */ + uint32_t Crv_En; + uint32_t BlankTime; + uint32_t Crv_Sel; + uint32_t Crv_Cfg; + uint32_t WinMode; + uint32_t WinOut; + uint32_t Polarity; + uint32_t FltEn; + uint32_t FltTime; + uint32_t BlankSel; + uint32_t InPSel; + uint32_t InMSel; + uint32_t HYS; +}COMP_InitTypeDef; + +/** + * @brief COMP handle Structure definition + */ +typedef struct +{ + COMP_TypeDef *Instance; /*!< Register base address */ + COMP_InitTypeDef Init; /*!< COMP required parameters */ + uint8_t OutputLevel_Org; /*!< COMP OutputLevel original */ + uint8_t OutputLevel; /*!< COMP OutputLevel with filter */ +} COMP_HandleTypeDef; + +#define COMP_CR_CRV_EN_DISABLE (0U) +#define COMP_CR_CRV_EN_ENABLE (1U) + +#define COMP_CR_CRV_SEL_AVDD (0U) +#define COMP_CR_CRV_SEL_VREF (1U) + +#define COMP_CR1_WINMODE_COMP1_INPSEL (0U) +#define COMP_CR1_WINMODE_COMP2_INPSEL (1U) + +#define COMP_CR2_WINMODE_COMP2_INPSEL (0U) +#define COMP_CR2_WINMODE_COMP1_INPSEL (1U) + +#define COMP_CR1_WINOUT_VCOUT1 (0U) +#define COMP_CR2_WINOUT_VCOUT2 (0U) +#define COMP_CR_WINOUT_VCOUT12 (1U) + +#define COMP_CR_POLARITY_P (0U) +#define COMP_CR_POLARITY_N (1U) + +#define COMP_CR_FLTEN_DISABLE (0U) +#define COMP_CR_FLTEN_ENABLE (1U) + +#define COMP_CR_FLTTIME_1_CLK (0U) +#define COMP_CR_FLTTIME_2_CLK (1U) +#define COMP_CR_FLTTIME_4_CLK (2U) +#define COMP_CR_FLTTIME_16_CLK (3U) +#define COMP_CR_FLTTIME_64_CLK (4U) +#define COMP_CR_FLTTIME_256_CLK (5U) +#define COMP_CR_FLTTIME_1024_CLK (6U) +#define COMP_CR_FLTTIME_4095_CLK (7U) + +#define COMP_CR_BLANKTIME_32_CLK (0U) +#define COMP_CR_BLANKTIME_64_CLK (1U) +#define COMP_CR_BLANKTIME_128_CLK (2U) +#define COMP_CR_BLANKTIME_256_CLK (3U) + +#define COMP_CR_BLANKSEL_NONE (0U) +#define COMP_CR_BLANKSEL_1 (1U) +#define COMP_CR_BLANKSEL_2 (2U) +#define COMP_CR_BLANKSEL_3 (4U) +#define COMP_CR_BLANKSEL_4 (8U) + +#define COMP_CR_INPSEL_0 (0U) +#define COMP_CR_INPSEL_1 (1U) +#define COMP_CR_INPSEL_2 (2U) + +#define COMP_CR_INMSEL_0 (0U) +#define COMP_CR_INMSEL_1 (1U) +#define COMP_CR_INMSEL_2 (2U) +#define COMP_CR_INMSEL_3 (3U) + +#define COMP_CR_HYS_DISABLE (0U) +#define COMP_CR_HYS_1 (4U) +#define COMP_CR_HYS_2 (5U) +#define COMP_CR_HYS_3 (6U) +#define COMP_CR_HYS_4 (7U) + +/******************************** COMP Instances *******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == COMP) +#define IS_COMP_ALL_COMP(_COMP) (((_COMP) == COMP1) || \ + ((_COMP) == COMP2)) + +#define IS_COMP_ALL_CRV_EN(_CRV_EN) (((_CRV_EN) == COMP_CR_CRV_EN_DISABLE) || \ + ((_CRV_EN) == COMP_CR_CRV_EN_ENABLE)) + +#define IS_COMP_ALL_CRV_SEL(_CRV_SEL) (((_CRV_SEL) == COMP_CR_CRV_SEL_AVDD) || \ + ((_CRV_SEL) == COMP_CR_CRV_SEL_VREF)) + +#define IS_COMP_ALL_CRV_CFG(_CRV_CFG) ((_CRV_CFG) <= 15U) + +#define IS_COMP_ALL_WINMODE(WINMODE) (((WINMODE) == COMP_CR1_WINMODE_COMP1_INPSEL) || \ + ((WINMODE) == COMP_CR1_WINMODE_COMP2_INPSEL) || \ + ((WINMODE) == COMP_CR2_WINMODE_COMP2_INPSEL) || \ + ((WINMODE) == COMP_CR2_WINMODE_COMP1_INPSEL)) + +#define IS_COMP_ALL_WINOUT(_WINOUT) (((_WINOUT) == COMP_CR1_WINOUT_VCOUT1) || \ + ((_WINOUT) == COMP_CR2_WINOUT_VCOUT2) || \ + ((_WINOUT) == COMP_CR_WINOUT_VCOUT12)) + +#define IS_COMP_ALL_POLARITY(POLARITY) (((POLARITY) == COMP_CR_POLARITY_N) || \ + ((POLARITY) == COMP_CR_POLARITY_P)) + +#define IS_COMP_ALL_FLTEN(FLTEN) (((FLTEN) == COMP_CR_FLTEN_DISABLE) || \ + ((FLTEN) == COMP_CR_FLTEN_ENABLE)) + +#define IS_COMP_ALL_FLTTIME(FLTTIME) (((FLTTIME) == COMP_CR_FLTTIME_1_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_2_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_4_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_16_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_64_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_256_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_1024_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_4095_CLK)) + +#define IS_COMP_ALL_BLANKTIME(BLANKTIME) (((BLANKTIME) == COMP_CR_BLANKTIME_32_CLK) || \ + ((BLANKTIME) == COMP_CR_BLANKTIME_64_CLK) || \ + ((BLANKTIME) == COMP_CR_BLANKTIME_128_CLK) || \ + ((BLANKTIME) == COMP_CR_BLANKTIME_256_CLK)) + +#define IS_COMP_ALL_BLANKSEL(BLANKSEL) (((BLANKSEL) == COMP_CR_BLANKSEL_NONE) || \ + ((BLANKSEL) == COMP_CR_BLANKSEL_1) || \ + ((BLANKSEL) == COMP_CR_BLANKSEL_2) || \ + ((BLANKSEL) == COMP_CR_BLANKSEL_3) || \ + ((BLANKSEL) == COMP_CR_BLANKSEL_4)) + +#define IS_COMP_ALL_INPSEL(INPSEL) (((INPSEL) == COMP_CR_INPSEL_0) || \ + ((INPSEL) == COMP_CR_INPSEL_1) || \ + ((INPSEL) == COMP_CR_INPSEL_2)) + +#define IS_COMP_ALL_INMSEL(INMSEL) (((INMSEL) == COMP_CR_INMSEL_0 ) || \ + ((INMSEL) == COMP_CR_INMSEL_1 ) || \ + ((INMSEL) == COMP_CR_INMSEL_2 ) || \ + ((INMSEL) == COMP_CR_INMSEL_3 )) + +#define IS_COMP_ALL_HYS(_HYS) (((_HYS) == COMP_CR_HYS_DISABLE) || \ + ((_HYS) == COMP_CR_HYS_1) || \ + ((_HYS) == COMP_CR_HYS_2) || \ + ((_HYS) == COMP_CR_HYS_3) || \ + ((_HYS) == COMP_CR_HYS_4)) + +/* Function */ +void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp); +void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); + +#endif + + + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h new file mode 100644 index 0000000000..75590b1ff2 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h @@ -0,0 +1,154 @@ +/* + ****************************************************************************** + * @file HAL_CRC.h + * @version V1.0.0 + * @date 2021 + * @brief Header file of CRC HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_CRC_H__ +#define __HAL_CRC_H__ +#include "ACM32Fxx_HAL.h" + +/** @defgroup CRC POLY Reverse + * @{ + */ + #define CRC_POLY_REV_EN (0x00000400U) /*!< Poly Reverse Enable */ + #define CRC_POLY_REV_DIS (0x00000000U) /*!< Poly Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC OUTXOR Reverse + * @{ + */ + #define CRC_OUTXOR_REV_EN (0x00000200U) /*!< OUTXOR Reverse Enable */ + #define CRC_OUTXOR_REV_DIS (0x00000000U) /*!< OUTXOR Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC INIT Reverse + * @{ + */ + #define CRC_INIT_REV_EN (0x00000100U) /*!< INIT Reverse Enable */ + #define CRC_INIT_REV_DIS (0x00000000U) /*!< INIT Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC RSLT Reverse + * @{ + */ + #define CRC_RSLT_REV_EN (0x00000080U) /*!< RSLT Reverse Enable */ + #define CRC_RSLT_REV_DIS (0x00000000U) /*!< RSLT Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC DATA Reverse + * @{ + */ + #define CRC_DATA_REV_DISABLE (0x00000000U) /*!< DATA Reverse Disable */ + #define CRC_DATA_REV_BY_BYTE (0x00000020U) /*!< DATA Reverse By Byte */ + #define CRC_DATA_REV_BY_HALFWORD (0x00000040U) /*!< DATA Reverse By HalfWord */ + #define CRC_DATA_REV_BY_WORD (0x00000060U) /*!< DATA Reverse By Word */ +/** + * @} + */ + +/** @defgroup CRC Poly Len + * @{ + */ + #define CRC_POLTY_LEN_32 (0x00000000U) /*!< POLY len = 32bit */ + #define CRC_POLTY_LEN_16 (0x00000008U) /*!< POLY len = 16bit */ + #define CRC_POLTY_LEN_8 (0x00000010U) /*!< POLY len = 8bit */ + #define CRC_POLTY_LEN_7 (0x00000018U) /*!< POLY len = 7bit */ +/** + * @} + */ + +/** @defgroup CRC Data Len + * @{ + */ + #define CRC_DATA_LEN_1B (0x00000000U) /*!< DATA len = 1 Byte */ + #define CRC_DATA_LEN_2B (0x00000002U) /*!< DATA len = 2 Byte */ + #define CRC_DATA_LEN_3B (0x00000004U) /*!< DATA len = 3 Byte */ + #define CRC_DATA_LEN_4B (0x00000006U) /*!< DATA len = 4 Byte */ +/** + * @} + */ + +/** @defgroup CRC RST + * @{ + */ + #define CRC_RST_EN (0x00000001U) /*!< RST CRC_DATA To CRC_INIT */ + #define CRC_RST_DIS (0x00000000U) /*!< RST CRC_DATA To CRC_INIT */ + +/** + * @} + */ + +/* + * @brief CRC Init Structure definition + */ +typedef struct +{ + uint32_t PolyRev; /*!< Specifies if the Poly is reversed in CRC + This parameter can be a value of @ref CRC POLY Reverse. */ + uint32_t OutxorRev; /*!< Specifies if the Outxor is reversed in CRC + This parameter can be a value of @ref CRC OUTXOR Reverse. */ + uint32_t InitRev; /*!< Specifies if the Init is reversed in CRC + This parameter can be a value of @ref CRC INIT Reverse. */ + uint32_t RsltRev; /*!< Specifies if the Result is reversed in CRC + This parameter can be a value of @ref CRC RSLT Reverse. */ + uint32_t DataRev; /*!< Specifies if the Data is reversed in CRC + This parameter can be a value of @ref CRC DATA Reverse. */ + uint32_t PolyLen; /*!< Specifies the Poly Len in CRC + This parameter can be a value of @ref CRC Poly Len. */ + uint32_t DataLen; /*!< Specifies the Data Len in CRC + This parameter can be a value of @ref CRC Data Len. */ + uint32_t RST; /*!< Specifies if CRC is reset + This parameter can be a value of @ref CRC RST. */ + + uint32_t InitData; /*!< This member configures the InitData. */ + + uint32_t OutXorData; /*!< This member configures the OutXorData. */ + + uint32_t PolyData; /*!< This member configures the PolyData. */ + + uint32_t FData; /*!< This member configures the FData. */ + +}CRC_InitTypeDef; + +/* + * @brief UART handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< CRC registers base address */ + + CRC_InitTypeDef Init; /*!< CRC calculate parameters */ + + uint8_t* CRC_Data_Buff; /*!< CRC databuff base address */ + + uint32_t CRC_Data_Len; /*!< amount of CRC data to be calculated */ + +}CRC_HandleTypeDef; + + +/********************************************************************************* +* Function : HAL_CRC_Calculate +* Description : Calculate the crc calue of input data. +* Input : hcrc: CRC handle. +* Output : CRC value +* Author : cl Data : 2021 +**********************************************************************************/ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc); + + +#endif + + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_DIV.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_DIV.h new file mode 100644 index 0000000000..86168307e2 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_DIV.h @@ -0,0 +1,24 @@ +#ifndef _HAL_DIV_H_ +#define _HAL_DIV_H_ + +#include "ACM32Fxx_HAL.h" + +/************************************************************************ +* function : hardwareNN_Div_q32 +* Description: Computes q = b div c and a = b mod c. + cDigits must be 1, and *c < 0xffffffff +* input : UINT32 *b -- input b databuffer + UINT32 *c -- input c databuffer +* output: UINT32 *q -- quotient of result + UINT32 *a -- remainder of result + +* return: none +************************************************************************/ +void HAL_DIV_Q32(UINT32 *q,UINT32 *a,UINT32 *b,UINT32 bDigits,UINT32 *c,UINT32 cDigits); + + + +#endif + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_DMA.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_DMA.h new file mode 100644 index 0000000000..5d7aef5fdf --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_DMA.h @@ -0,0 +1,278 @@ +/* + ****************************************************************************** + * @file HAL_DMA.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of DMA HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_DMA_H__ +#define __HAL_DMA_H__ + +#include "ACM32Fxx_HAL.h" + +#define DMA_CHANNEL_NUM (5) + +/** @defgroup DMA_DATA_FLOW + * @{ + */ +#define DMA_DATA_FLOW_M2M (0x00000000) +#define DMA_DATA_FLOW_M2P (0x00000800) +#define DMA_DATA_FLOW_P2M (0x00001000) +/** + * @} + */ + + +/** @defgroup REQUEST_ID + * @{ + */ +#define REG_M2M (0) + +#define REQ0_ADC (0) +#define REQ1_SPI1_SEND (1) +#define REQ2_SPI1_RECV (2) +#define REQ3_SPI2_SEND (3) +#define REQ4_SPI2_RECV (4) +#define REQ5_UART1_SEND (5) +#define REQ6_UART1_RECV (6) +#define REQ7_UART2_SEND (7) +#define REQ8_UART2_RECV (8) +#define REQ9_I2C1_SEND (9) +#define REQ10_I2C1_RECV (10) +#define REQ11_I2C2_SEND (11) +#define REQ12_I2C2_RECV (12) +#define REQ13_TIM1_CH1 (13) +#define REQ14_TIM1_CH2 (14) +#define REQ15_TIM1_CH3 (15) +#define REQ16_TIM1_CH4 (16) +#define REQ17_TIM1_UP (17) +#define REQ18_TIM1_TRIG_COM (18) +#define REQ19_TIM3_CH3 (19) +#define REQ20_TIM3_CH4_OR_UP (20) +#define REQ21_TIM3_CH1_OR_TRIG (21) +#define REQ22_TIM3_CH2_LCDFRAME (22) +#define REQ23_TIM6_UP (23) +#define REQ24_TIM15_CH1_UP_TRIG_COM (24) +#define REQ25_TIM15_CH2 (25) +#define REQ26_TIM16_CH1_UP (26) +#define REQ27_UART3_SEND (27) +#define REQ28_TIM17_CH1_UP (28) +#define REQ29_UART3_RECV (29) +#define REQ30_LPUART_SEND (30) +#define REQ31_LPUART_RECV (31) + +#define REQ_MAX_LIMIT (32) +/** + * @} + */ + + +/** @defgroup DMA_SOURCE_ADDR_INCREASE + * @{ + */ +#define DMA_SOURCE_ADDR_INCREASE_DISABLE (0x00000000) +#define DMA_SOURCE_ADDR_INCREASE_ENABLE (0x04000000) +/** + * @} + */ + + +/** @defgroup DMA_DST_ADDR_INCREASE + * @{ + */ +#define DMA_DST_ADDR_INCREASE_DISABLE (0x00000000) +#define DMA_DST_ADDR_INCREASE_ENABLE (0x08000000) +/** + * @} + */ + + +/** @defgroup DMA_SRC_WIDTH + * @{ + */ +#define DMA_SRC_WIDTH_BYTE (0x00000000) /* 8bit */ +#define DMA_SRC_WIDTH_HALF_WORD (0x00040000) /* 16bit */ +#define DMA_SRC_WIDTH_WORD (0x00080000) /* 36bit */ +/** + * @} + */ + +/** @defgroup DMA_DST_WIDTH + * @{ + */ +#define DMA_DST_WIDTH_BYTE (0x00000000) /* 8bit */ +#define DMA_DST_WIDTH_HALF_WORD (0x00200000) /* 16bit */ +#define DMA_DST_WIDTH_WORD (0x00400000) /* 36bit */ +/** + * @} + */ + + + + /** @defgroup DMA_MODE DMA MODE + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR 0x00000001U /*!< Circular mode */ +/** + * @} + */ + +/** + * @brief DMA burst length Structure definition + */ +typedef enum +{ + DMA_BURST_LENGTH_1 = 0, + DMA_BURST_LENGTH_4 = 1, + DMA_BURST_LENGTH_8 = 2, + DMA_BURST_LENGTH_16 = 3, + DMA_BURST_LENGTH_32 = 4, + DMA_BURST_LENGTH_64 = 5, + DMA_BURST_LENGTH_128 = 6, + DMA_BURST_LENGTH_256 = 7, +}DMA_BURST_LENGTH; + + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /* This parameter can be a value of @ref DMA_MODE */ + + uint32_t Data_Flow; /* This parameter can be a value of @ref DMA_DATA_FLOW */ + + uint32_t Request_ID; /* This parameter can be a value of @ref REQUEST_ID */ + + uint32_t Source_Inc; /* This parameter can be a value of @ref DMA_SOURCE_ADDR_INCREASE */ + + uint32_t Desination_Inc; /* This parameter can be a value of @ref DMA_DST_ADDR_INCREASE */ + + uint32_t Source_Width; /* This parameter can be a value of @ref DMA_SRC_WIDTH */ + + uint32_t Desination_Width; /* This parameter can be a value of @ref DMA_DST_WIDTH */ + +}DMA_InitParaTypeDef; + + +/** + * @brief DMA handle Structure definition + */ +typedef struct +{ + DMA_Channel_TypeDef *Instance; /* DMA registers base address */ + + DMA_InitParaTypeDef Init; /* DMA initialization parameters */ + + void (*DMA_ITC_Callback)(void); /* DMA transfer complete callback */ + + void (*DMA_IE_Callback)(void); /* DMA error complete callback */ + +}DMA_HandleTypeDef; + +/** + * @brief DMA Link List Item Structure + */ +typedef struct DMA_NextLink +{ + uint32_t SrcAddr; /* source address */ + + uint32_t DstAddr; /* desination address */ + + struct DMA_NextLink *Next; /* Next Link */ + + uint32_t Control; /* Control */ + +}DMA_LLI_InitTypeDef; + + +/** @defgroup GPIO Private Macros + * @{ + */ +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA_Channel0) || \ + ((INSTANCE) == DMA_Channel1) || \ + ((INSTANCE) == DMA_Channel2) || \ + ((INSTANCE) == DMA_Channel3) || \ + ((INSTANCE) == DMA_Channel4)) + +#define IS_DMA_DATA_FLOW(DATA_FLOW) (((DATA_FLOW) == DMA_DATA_FLOW_M2M) || \ + ((DATA_FLOW) == DMA_DATA_FLOW_M2P) || \ + ((DATA_FLOW) == DMA_DATA_FLOW_P2M)) + +#define IS_DMA_REQUEST_ID(REQUEST_ID) ((REQUEST_ID < REQ_MAX_LIMIT) ? true : false) + +#define IS_DMA_SRC_WIDTH(WIDTH) (((WIDTH) == DMA_SRC_WIDTH_BYTE) || \ + ((WIDTH) == DMA_SRC_WIDTH_HALF_WORD) || \ + ((WIDTH) == DMA_SRC_WIDTH_WORD)) + +#define IS_DMA_DST_WIDTH(WIDTH) (((WIDTH) == DMA_DST_WIDTH_BYTE) || \ + ((WIDTH) == DMA_DST_WIDTH_HALF_WORD) || \ + ((WIDTH) == DMA_DST_WIDTH_WORD)) +/** + * @} + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* (DMA) */ +/******************************************************************************/ + +/**************** Bit definition for DMA CONFIG register ***********************/ +#define DMA_CONFIG_M2ENDIAN BIT2 +#define DMA_CONFIG_M1ENDIAN BIT1 +#define DMA_CONFIG_EN BIT0 + +/**************** Bit definition for DMA Channel CTRL register ***********************/ +#define DMA_CHANNEL_CTRL_ITC BIT31 +#define DMA_CHANNEL_CTRL_DI BIT27 +#define DMA_CHANNEL_CTRL_SI BIT26 + + +/**************** Bit definition for DMA Channel CONFIG register ***********************/ +#define DMA_CHANNEL_CONFIG_HALT BIT18 +#define DMA_CHANNEL_CONFIG_ACTIVE BIT17 +#define DMA_CHANNEL_CONFIG_LOCK BIT16 +#define DMA_CHANNEL_CONFIG_ITC BIT15 +#define DMA_CHANNEL_CONFIG_IE BIT14 +#define DMA_CHANNEL_CONFIG_FLOW_CTRL (BIT11|BIT12|BIT13) +#define DMA_CHANNEL_CONFIG_DEST_PERIPH (BIT6|BIT7|BIT8|BIT9|BIT10) +#define DMA_CHANNEL_CONFIG_DEST_PERIPH_POS (6) +#define DMA_CHANNEL_CONFIG_SRC_PERIPH (BIT1|BIT2|BIT3|BIT4|BIT5) +#define DMA_CHANNEL_CONFIG_SRC_PERIPH_POS (1) +#define DMA_CHANNEL_CONFIG_EN BIT0 + + +/* Exported functions --------------------------------------------------------*/ + +#define __HAL_LINK_DMA(_HANDLE_, _DMA_LINK_, _DMA_HANDLE_) (_HANDLE_._DMA_LINK_ = &_DMA_HANDLE_) + +/* HAL_DMA_IRQHandler */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); + +/* HAL_DMA_Init */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); + +/* HAL_DMA_DeInit */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); + +/* HAL_DMA_Start */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size); + +/* HAL_DMA_Start */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size); + +/* HAL_DMA_Abort */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); + +/* HAL_DMA_GetState */ +HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); + +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EFLASH.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EFLASH.h new file mode 100644 index 0000000000..2d1986758b --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EFLASH.h @@ -0,0 +1,41 @@ +/* + ****************************************************************************** + * @file HAL_EFlash.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of EFlash HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_EFlash_H__ +#define __HAL_EFlash_H__ + +#include "ACM32Fxx_HAL.h" + +#define EFLASH_PAGE_SIZE (512UL) + +#define HAL_EFLASH_READ_WORD(Addr) (*(volatile uint32_t *)(Addr)) // Read By Word +#define HAL_EFLASH_READ_HALFWORD(Addr) (*(volatile uint16_t *)(Addr)) // Read By Half Word +#define HAL_EFLASH_READ_BYTE(Addr) (*(volatile uint8_t *)(Addr)) // Read By Byte + +/******************** Bit definition for EFC_CTRL register ******************/ +#define EFC_CTRL_CHIP_ERASE_MODE (1 << 2) +#define EFC_CTRL_PAGE_ERASE_MODE (1 << 1) +#define EFC_CTRL_PROGRAM_MODE (1 << 0) + +#define EFLASH_RD_WAIT_POS 7 +/******************** Bit definition for EFC_STATUS register ***************/ +#define EFC_STATUS_EFLASH_RDY (1 << 0) + +#define SET_EFC_RD_WAIT(wait) {EFC->CTRL = (EFC->CTRL & ~(0x1F << 7)) | (wait << 7);} + +/* Exported functions --------------------------------------------------------*/ + +/* HAL_EFlash_Init */ +void HAL_EFlash_Init(uint32_t fu32_freq); +/* HAL_EFlash_ErasePage */ +bool HAL_EFlash_ErasePage(uint32_t fu32_Addr); + +/* HAL_EFlash_Program_Word */ +bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data); + +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h new file mode 100644 index 0000000000..7ddee8d2f3 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h @@ -0,0 +1,26 @@ +/* + ****************************************************************************** + * @file HAL_EFlash_EX.h + * @version V1.0.0 + * @date 2021 + * @brief Header file of EFlash extention module + ****************************************************************************** +*/ +#ifndef __HAL_EFlash_EX_H__ +#define __HAL_EFlash_EX_H__ + +#include "stdint.h" + +/* HAL_EFlash_Return_To_Boot */ +void HAL_EFlash_Return_to_Boot(void); + +/* HAL_EFlash_Init_Para */ +void HAL_EFlash_Init_Para(uint32_t fu32_freq); + +/* HAL_EFlash_ErasePage_EX */ +void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr); + +/* HAL_EFlash_Program_Word_EX */ +void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data); + +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h new file mode 100644 index 0000000000..b34e52eef7 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h @@ -0,0 +1,166 @@ +/* + ****************************************************************************** + * @file HAL_EXTI.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of EXTI HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_EXTI_H__ +#define __HAL_EXTI_H__ + +#include "ACM32Fxx_HAL.h" + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (0x000001) +#define EXTI_LINE_1 (0x000002) +#define EXTI_LINE_2 (0x000004) +#define EXTI_LINE_3 (0x000008) +#define EXTI_LINE_4 (0x000010) +#define EXTI_LINE_5 (0x000020) +#define EXTI_LINE_6 (0x000040) +#define EXTI_LINE_7 (0x000080) +#define EXTI_LINE_8 (0x000100) +#define EXTI_LINE_9 (0x000200) +#define EXTI_LINE_10 (0x000300) +#define EXTI_LINE_11 (0x000400) +#define EXTI_LINE_12 (0x001000) +#define EXTI_LINE_13 (0x002000) +#define EXTI_LINE_14 (0x004000) +#define EXTI_LINE_15 (0x008000) +#define EXTI_LINE_16 (0x010000) +#define EXTI_LINE_17 (0x020000) +#define EXTI_LINE_18 (0x040000) +#define EXTI_LINE_19 (0x080000) +#define EXTI_LINE_20 (0x100000) +#define EXTI_LINE_21 (0x200000) +#define EXTI_LINE_22 (0x400000) +#define EXTI_LINE_23 (0x800000) +#define EXTI_LINE_MASK (0xFFFFFFU) +/** + * @} + */ + + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_INTERRUPT (0x00000001) +#define EXTI_MODE_EVENT (0x00000002) +/** + * @} + */ + + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_RISING (0x00000001) +#define EXTI_TRIGGER_FALLING (0x00000002) +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#define EXTI_GPIOE 0x00000004u +#define EXTI_GPIOF 0x00000005u +/** + * @} + */ + + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t u32_Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t u32_Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t u32_Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t u32_GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +}EXTI_HandleTypeDef; + + +/** @defgroup EXTI Private Macros + * @{ + */ +#define IS_EXTI_ALL_LINE(LINE) ( (LINE) | (EXTI_LINE_MASK) ) + +#define IS_EXTI_MODE(__MODE__) (((__MODE__) == EXTI_MODE_INTERRUPT) || \ + ((__MODE__) == EXTI_MODE_EVENT)) + +#define IS_EXTI_TRIGGER(__TRIGGER__) (((__TRIGGER__) == EXTI_TRIGGER_RISING) || \ + ((__TRIGGER__) == EXTI_TRIGGER_FALLING) || \ + ((__TRIGGER__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_GPIOSEL(__GPIOSEL__) (((__GPIOSEL__) == EXTI_GPIOA) || \ + ((__GPIOSEL__) == EXTI_GPIOB) || \ + ((__GPIOSEL__) == EXTI_GPIOC) || \ + ((__GPIOSEL__) == EXTI_GPIOD) || \ + ((__GPIOSEL__) == EXTI_GPIOE) || \ + ((__GPIOSEL__) == EXTI_GPIOF)) +/** + * @} + */ + +/** @brief __HAL_EXTI_LINE_IT_ENABLE + * @param __LINE__: EXTI line. + * This parameter can be a value of @ref EXTI_Line + */ +#define __HAL_EXTI_LINE_IT_ENABLE(__LINE__) (EXTI->IENR |= (__LINE__)) + +/** @brief __HAL_EXTI_LINE_IT_DISABLE + * @param __LINE__: EXTI line. + * This parameter can be a value of @ref EXTI_Line + */ +#define __HAL_EXTI_LINE_IT_DISABLE(__LINE__) (EXTI->IENR &= ~(__LINE__)) + +/** @brief __HAL_EXTI_LINE_EVENT_ENABLE + * @param __LINE__: EXTI line. + * This parameter can be a value of @ref EXTI_Line + */ +#define __HAL_EXTI_LINE_EVENT_ENABLE(__LINE__) (EXTI->EENR |= (__LINE__)) + +/** @brief __HAL_EXTI_LINE_EVENT_DISABLE + * @param __LINE__: EXTI line. + * This parameter can be a value of @ref EXTI_Line + */ +#define __HAL_EXTI_LINE_EVENT_DISABLE(__LINE__) (EXTI->EENR &= ~(__LINE__)) + + +/* HAL_EXTI_IRQHandler */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *huart); + +/* HAL_EXTI_SetConfigLine */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti); + +/* HAL_EXTI_SoftTrigger */ +void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti); + +/* HAL_EXTI_GetPending */ +bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti); + +/* HAL_EXTI_ClearPending */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti); + +/* HAL_EXTI_ClearAllPending */ +void HAL_EXTI_ClearAllPending(void); + +#endif + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h new file mode 100644 index 0000000000..b9411f06f4 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h @@ -0,0 +1,210 @@ +/* + ****************************************************************************** + * @file HAL_GPIO.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of GPIO HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_GPIO_H__ +#define __HAL_GPIO_H__ + +#include "ACM32Fxx_HAL.h" + +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + + +/** @defgroup GPIO_mode GPIO mode + * @{ + */ +#define GPIO_MODE_INPUT (0x00010000u) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00010001u) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00011002u) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (0x00000003u) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (0x00001004u) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (0x00000005u) /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (0x10010000u) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10010001u) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10010002u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_HIGH_LEVEL (0x10010003u) /*!< External Interrupt Mode with high level trigger detection */ +#define GPIO_MODE_IT_LOW_LEVEL (0x10010004u) /*!< External Interrupt Mode with low level trigger detection */ + +#define GPIO_MODE_OD_MASK (0x00001000u) /*!< OD Mode Mask */ +#define GPIO_MODE_IO_MASK (0x00010000u) /*!< Use GPIO Function Mask */ +#define GPIO_MODE_IT_MASK (0x10000000u) /*!< GPIO interrupt Mask */ +/** + * @} + */ + + +/** @defgroup GPIO_pull GPIO pull + * @{ + */ +#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */ +/** + * @} + */ + + +/** @defgroup GPIOEx_function_selection GPIO pull + * @{ + */ +#define GPIO_FUNCTION_0 (0x00000000u) +#define GPIO_FUNCTION_1 (0x00000001u) +#define GPIO_FUNCTION_2 (0x00000002u) +#define GPIO_FUNCTION_3 (0x00000003u) +#define GPIO_FUNCTION_4 (0x00000004u) +#define GPIO_FUNCTION_5 (0x00000005u) +#define GPIO_FUNCTION_6 (0x00000006u) +#define GPIO_FUNCTION_7 (0x00000007u) +#define GPIO_FUNCTION_8 (0x00000008u) +#define GPIO_FUNCTION_9 (0x00000009u) +/** + * @} + */ + + + +/** @defgroup GPIOx Index + * @{ + */ +typedef enum +{ + GPIOA, + GPIOB, + GPIOC, + GPIOD, +}enum_GPIOx_t; +/** + * @} + */ + + +/** @defgroup GPIO Bit SET and Bit RESET enumeration + * @{ + */ +typedef enum +{ + GPIO_PIN_CLEAR = 0u, + GPIO_PIN_SET = 1u, +}enum_PinState_t; +/** + * @} + */ + + + +/* + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_function_selection */ +} GPIO_InitTypeDef; + + +/** @defgroup GPIO Private Macros + * @{ + */ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) ) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) + + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_HIGH_LEVEL) ||\ + ((__MODE__) == GPIO_MODE_IT_LOW_LEVEL) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + + + + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) ||\ + ((__PULL__) == GPIO_PULLDOWN)) + +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_CLEAR) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_FUNCTION(__FUNCTION__) (((__FUNCTION__) == GPIO_FUNCTION_0) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_1) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_2) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_3) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_4) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_5) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_6) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_7) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_8) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_9)) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/* HAL_GPIO_IRQHandler */ +void HAL_GPIO_IRQHandler(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin); + +/* HAL_GPIO_Init */ +void HAL_GPIO_Init(enum_GPIOx_t fe_GPIO, GPIO_InitTypeDef *GPIO_Init); + +/* HAL_GPIO_DeInit */ +void HAL_GPIO_DeInit(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin); + +/* HAL_GPIO_AnalogEnable */ +void HAL_GPIO_AnalogEnable(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin); + +/* HAL_GPIO_WritePin */ +void HAL_GPIO_WritePin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin, enum_PinState_t fe_PinState); + +/* HAL_GPIO_ReadPin */ +enum_PinState_t HAL_GPIO_ReadPin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin); + +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h new file mode 100644 index 0000000000..38fe4bf47f --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h @@ -0,0 +1,45 @@ +/*********************************************************************** + * Copyright (c) 2008 - 2016, Shanghai AisinoChip Co.,Ltd . + * All rights reserved. + * Filename : HAL_HRNG.h + * Description : hrng header file + * Author(s) : Eric + * version : V1.0 + * Modify date : 2021-03-24 + ***********************************************************************/ +#ifndef __HAL_HRNG_H__ +#define __HAL_HRNG_H__ +#include "ACM32Fxx_HAL.h" + + +/********************************************************************************* +* Function Name : HAL_HRNG_Initial +* Description : intial hrng module +* Input : None +* Output : None +* Return : None +*********************************************************************************/ +void HAL_HRNG_Initial(void); + +/********************************************************************************* +* Function Name : HAL_HRNG_Source_Disable +* Description : disable hrng source +* Input : None +* Output : None +* Return : None +*********************************************************************************/ +void HAL_HRNG_Source_Disable(void); + +/********************************************************************************* +* Function Name : HAL_HRNG_GetHrng +* Description : get random number +* Input : byte_len : the byte length of random number +* Output : *hdata : the start address of random number the size must be 16bytes +* Return : 0: hrng data is ok; 1: hrng data is bad +*********************************************************************************/ +UINT8 HAL_HRNG_GetHrng(UINT8 *hdata, UINT32 byte_len); + +#endif + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h new file mode 100644 index 0000000000..c746ba8ed1 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h @@ -0,0 +1,253 @@ +/* + ****************************************************************************** + * @file HAL_I2C.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of I2C HAL module. + ****************************************************************************** +*/ + +#ifndef __HAL_I2C_H__ +#define __HAL_I2C_H__ + +#include "ACM32Fxx_HAL.h" + +/**************** Bit definition for I2C CR register ********************/ +#define I2C_CR_STOPF_INTEN BIT20 +#define I2C_CR_RX_ADDR3_INTEN BIT19 +#define I2C_CR_DMA_EN BIT18 +#define I2C_CR_TXE_SEL BIT17 +#define I2C_CR_MARLO_INTEN BIT16 +#define I2C_CR_TX_AUTO_EN BIT15 +#define I2C_CR_OD_MODE BIT14 +#define I2C_CR_RX_ADDR2_INT_EN BIT12 +#define I2C_CR_OVR_INT_EN BIT11 +#define I2C_CR_RXNE_INT_EN BIT10 +#define I2C_CR_TXE_INT_EN BIT9 +#define I2C_CR_RX_ADDR1_INT_EN BIT8 +#define I2C_CR_MTF_INT_EN BIT7 +#define I2C_CR_TACK BIT6 +#define I2C_CR_STOP BIT5 +#define I2C_CR_START BIT4 +#define I2C_CR_TX BIT3 +#define I2C_CR_MASTER BIT2 +#define I2C_CR_NOSTRETCH BIT1 +#define I2C_CR_MEN BIT0 + +/**************** Bit definition for I2C SR register ********************/ +#define I2C_SR_TIMEOUTBF BIT16 +#define I2C_SR_TIMEOUTAF BIT15 +#define I2C_SR_RX_ADDR3 BIT14 +#define I2C_SR_RX_ADDR2 BIT12 +#define I2C_SR_OVR BIT11 +#define I2C_SR_RXNE BIT10 +#define I2C_SR_TXE BIT9 +#define I2C_SR_RX_ADDR1 BIT8 +#define I2C_SR_MTF BIT7 +#define I2C_SR_MARLO BIT6 +#define I2C_SR_TX_RX_FLAG BIT5 +#define I2C_SR_BUS_BUSY BIT4 +#define I2C_SR_SRW BIT3 +#define I2C_SR_STOPF BIT2 +#define I2C_SR_STARTF BIT1 +#define I2C_SR_RACK BIT0 + +/************** Bit definition for I2C SLAVE ADDR2/3 register **************/ +#define I2C_ADDR3_EN BIT8 +#define I2C_ADDR2_EN BIT0 + +/************** Bit definition for I2C TIMEOUT register **************/ +#define I2C_TIMEOUT_EXTEN BIT31 +#define I2C_TOUTB_INTEN BIT30 +#define I2C_EXT_MODE BIT29 +#define I2C_TIMEOUT_TIMOUTEN BIT15 +#define I2C_TOUTA_INTEN BIT14 + +/** @defgroup I2C_MODE + * @{ + */ +#define I2C_MODE_SLAVE (0U) +#define I2C_MODE_MASTER (1U) +/** + * @} + */ + +/** @defgroup CLOCK_SPEED + * @{ + */ +#define CLOCK_SPEED_STANDARD (100000U) +#define CLOCK_SPEED_FAST (400000U) +#define CLOCK_SPEED_FAST_PLUS (1000000U) +/** + * @} + */ + + +/** @defgroup TX_AUTO_EN + * @{ + */ +#define TX_AUTO_EN_DISABLE (0U) +#define TX_AUTO_EN_ENABLE (1U) +/** + * @} + */ + + +/** @defgroup NO_STRETCH_MODE + * @{ + */ +#define NO_STRETCH_MODE_STRETCH (0U) +#define NO_STRETCH_MODE_NOSTRETCH (1U) +/** + * @} + */ + +/** @defgroup SLAVE State machine + * @{ + */ +#define SLAVE_RX_STATE_IDLE (0U) +#define SLAVE_RX_STATE_RECEIVING (1U) +#define SLAVE_TX_STATE_IDLE (0U) +#define SLAVE_TX_STATE_SENDING (1U) +/** + * @} + */ + + /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0U) +#define I2C_MEMADD_SIZE_16BIT (1U) +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** + * @brief I2C Configuration Structure definition + */ + +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__) ) ? 1 : 0) + +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef struct +{ + uint32_t I2C_Mode; /* This parameter can be a value of @ref I2C_MODE */ + + uint32_t Tx_Auto_En; /* This parameter can be a value of @ref TX_AUTO_EN */ + + uint32_t No_Stretch_Mode; /* This parameter can be a value of @ref NO_STRETCH_MODE */ + + uint32_t Own_Address; /* This parameter can be a 7-bit address */ + + uint32_t Clock_Speed; /* This parameter can be a value of @ref CLOCK_SPEED */ +} I2C_InitTypeDef; + +/******************************** Check I2C Parameter *******************************/ +#define IS_I2C_ALL_MODE(I2C_MODE) (((I2C_MODE) == I2C_MODE_SLAVE) || \ + ((I2C_MODE) == I2C_MODE_MASTER)) + +#define IS_I2C_CLOCK_SPEED(CLOCK_SPEED) (((CLOCK_SPEED) > 0U) && ((CLOCK_SPEED) <=1000000U)) + +#define IS_I2C_TX_AUTO_EN(TX_AUTO_EN) (((TX_AUTO_EN) == TX_AUTO_EN_DISABLE) || \ + ((TX_AUTO_EN) == TX_AUTO_EN_ENABLE)) + +#define IS_I2C_STRETCH_EN(STRETCH_EN) (((STRETCH_EN) == NO_STRETCH_MODE_STRETCH) || \ + ((STRETCH_EN) == NO_STRETCH_MODE_NOSTRETCH)) + +/** + * @brief I2C handle Structure definition + */ +typedef struct +{ + I2C_TypeDef *Instance; /* I2C registers base address */ + + I2C_InitTypeDef Init; /* I2C communication parameters */ + + uint32_t Slave_RxState; /* I2C Slave state machine */ + uint32_t Slave_TxState; /* I2C Slave state machine */ + + uint8_t *Rx_Buffer; /* I2C Rx Buffer */ + uint8_t *Tx_Buffer; /* I2C Tx Buffer */ + + uint32_t Rx_Size; /* I2C Rx Size */ + uint32_t Tx_Size; /* I2C Tx Size */ + + uint32_t Rx_Count; /* I2C Rx Count */ + uint32_t Tx_Count; /* I2C Tx Count */ + + DMA_HandleTypeDef *HDMA_Rx; /* I2C Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* I2C Tx DMA handle parameters */ + + void (*I2C_STOPF_Callback)(void); /* I2C STOP flag interrupt callback */ + +}I2C_HandleTypeDef; + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2)) + +/* Function : HAL_I2C_IRQHandler */ +void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_MspInit */ +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_MspDeInit */ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_Init */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_DeInit */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_Master_Transmit */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Master_Receive */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Slave_Transmit */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Slave_Receive */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Slave_Transmit_IT */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + + +/* Function : HAL_I2C_Slave_Receive_IT */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + +/* Function : HAL_I2C_Slave_Receive_DMA */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + +/* Function : HAL_I2C_Slave_Transmit_DMA */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + +/* Function : HAL_I2C_Mem_Write */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Mem_Read */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_GetSlaveRxState */ +uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_GetSlaveTxState */ +uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c); + +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h new file mode 100644 index 0000000000..89783d1be9 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h @@ -0,0 +1,57 @@ + +/*********************************************************************** + * Filename : HAL_IWDT.h + * Description : IHAL WDT driver header file + * Author(s) : CWT + * version : V1.0 + * Modify date : 2020-04-17 + ***********************************************************************/ + +#ifndef __HAL_IWDT_H__ +#define __HAL_IWDT_H__ + +#include "ACM32Fxx_HAL.h" + + +/**************** Bit definition for IWDT register ***********************/ + + +/*----------------------macro definition------------------------*/ +#define IWDT_ENABLE_COMMAND (0xCCCCU) +#define IWDT_DISABLE_COMMAND (0xEF01ABCD) +#define IWDT_WRITE_ENABLE_COMMAND (0x5555U) +#define IWDT_WAKEUP_ENABLE_COMMAND (0x6666U) +#define IWDT_WAKEUP_DISABLE_COMMAND (0x9999U) +#define IWDT_RELOAD_COMMAND (0xAAAAU) + +#define IWDT_RELOAD_MAX_VALUE (0x0FFFU) + +/*----------------------type definition------------------------*/ +typedef enum _IWDT_CLOCK_PRESCALER{ + IWDT_CLOCK_PRESCALER_4 = 0, + IWDT_CLOCK_PRESCALER_8 = 1, + IWDT_CLOCK_PRESCALER_16 = 2, + IWDT_CLOCK_PRESCALER_32 = 3, + IWDT_CLOCK_PRESCALER_64 = 4, + IWDT_CLOCK_PRESCALER_128 = 5, + IWDT_CLOCK_PRESCALER_256 = 6, +}IWDT_CLOCK_PRESCALER; + +typedef struct +{ + uint32_t Prescaler; + uint32_t Reload; + uint32_t Window; + uint32_t Wakeup; +} IWDT_InitTypeDef; + +typedef struct +{ + IWDT_TypeDef *Instance; /*!< Register base address */ + IWDT_InitTypeDef Init; /*!< IWDT required parameters */ +} IWDT_HandleTypeDef; + + + HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt); + HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt); +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_LCD.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_LCD.h new file mode 100644 index 0000000000..352071045e --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_LCD.h @@ -0,0 +1,442 @@ +/* + ****************************************************************************** + * @file HAL_LCD.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of lcd HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_LCD_H__ +#define __HAL_LCD_H__ + +#include "ACM32Fxx_HAL.h" + +/******************************************************************************/ +/* */ +/* LCD Controller (LCD) */ +/* */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************* Bit definition for LCD_CR0 register *********************/ +#define LCD_CR0_LCDEN_Pos (0U) +#define LCD_CR0_LCDEN_Msk (0x1UL << LCD_CR0_LCDEN_Pos) +#define LCD_CR0_LCDEN LCD_CR0_LCDEN_Msk + +#define LCD_CR0_LCDCLK_Pos (1U) +#define LCD_CR0_LCDCLK_Msk (0x7UL << LCD_CR0_LCDCLK_Pos) +#define LCD_CR0_LCDCLK LCD_CR0_LCDCLK_Msk +#define LCD_CR0_LCDCLK_0 (0x1UL << LCD_CR0_LCDCLK_Pos) +#define LCD_CR0_LCDCLK_1 (0x2UL << LCD_CR0_LCDCLK_Pos) + +#define LCD_CR0_STATIC_Pos (4U) +#define LCD_CR0_STATIC_Msk (0x1UL << LCD_CR0_STATIC_Pos) +#define LCD_CR0_STATIC LCD_CR0_STATIC_Msk + +#define LCD_CR0_BIAS_Pos (5U) +#define LCD_CR0_BIAS_Msk (0x3UL << LCD_CR0_BIAS_Pos) +#define LCD_CR0_BIAS LCD_CR0_BIAS_Msk +#define LCD_CR0_BIAS_0 (0x1UL << LCD_CR0_BIAS_Pos) +#define LCD_CR0_BIAS_1 (0x2UL << LCD_CR0_BIAS_Pos) + +#define LCD_CR0_DUTY_Pos (7U) +#define LCD_CR0_DUTY_Msk (0x7UL << LCD_CR0_DUTY_Pos) +#define LCD_CR0_DUTY LCD_CR0_DUTY_Msk +#define LCD_CR0_DUTY_0 (0x1UL << LCD_CR0_DUTY_Pos) +#define LCD_CR0_DUTY_1 (0x2UL << LCD_CR0_DUTY_Pos) +#define LCD_CR0_DUTY_2 (0x4UL << LCD_CR0_DUTY_Pos) + +#define LCD_CR0_MOD_Pos (11U) +#define LCD_CR0_MOD_Msk (0x3UL << LCD_CR0_MOD_Pos) +#define LCD_CR0_MOD LCD_CR0_MOD_Msk +#define LCD_CR0_MOD_0 (0x1UL << LCD_CR0_MOD_Pos) +#define LCD_CR0_MOD_1 (0x2UL << LCD_CR0_MOD_Pos) + +#define LCD_CR0_CONTRAST_Pos (13U) +#define LCD_CR0_CONTRAST_Msk (0xfUL << LCD_CR0_CONTRAST_Pos) +#define LCD_CR0_CONTRAST LCD_CR0_CONTRAST_Msk +#define LCD_CR0_CONTRAST_0 (0x1UL << LCD_CR0_CONTRAST_Pos) +#define LCD_CR0_CONTRAST_1 (0x2UL << LCD_CR0_CONTRAST_Pos) +#define LCD_CR0_CONTRAST_2 (0x4UL << LCD_CR0_CONTRAST_Pos) +#define LCD_CR0_CONTRAST_3 (0x8UL << LCD_CR0_CONTRAST_Pos) + +#define LCD_CR0_WSEL_Pos (17U) +#define LCD_CR0_WSEL_Msk (0x1UL << LCD_CR0_WSEL_Pos) +#define LCD_CR0_WSEL LCD_CR0_WSEL_Msk + +/******************* Bit definition for LCD_CR1 register *********************/ +#define LCD_CR1_BLINKCNT_Pos (0U) +#define LCD_CR1_BLINKCNT_Msk (0x3FUL << LCD_CR1_BLINKCNT_Pos) +#define LCD_CR1_BLINKCNT LCD_CR1_BLINKCNT_Msk + + +#define LCD_CR1_BLINKEN_Pos (6U) +#define LCD_CR1_BLINKEN_Msk (0x1UL << LCD_CR1_BLINKEN_Pos) +#define LCD_CR1_BLINKEN LCD_CR1_BLINKEN_Msk + +#define LCD_CR1_MODE_Pos (8U) +#define LCD_CR1_MODE_Msk (0x1UL << LCD_CR1_MODE_Pos) +#define LCD_CR1_MODE LCD_CR1_MODE_Msk + +#define LCD_CR1_IE_Pos (9U) +#define LCD_CR1_IE_Msk (0x1UL << LCD_CR1_IE_Pos) +#define LCD_CR1_IE LCD_CR1_IE_Msk + +#define LCD_CR1_DMAEN_Pos (10U) +#define LCD_CR1_DMAEN_Msk (0x1UL << LCD_CR1_DMAEN_Pos) +#define LCD_CR1_DMAEN LCD_CR1_DMAEN_Msk + +#define LCD_CR1_INTF_Pos (11U) +#define LCD_CR1_INTF_Msk (0x1UL << LCD_CR1_INTF_Pos) +#define LCD_CR1_INTF LCD_CR1_INTF_Msk + +#define LCD_CR1_FCC_Pos (12U) +#define LCD_CR1_FCC_Msk (0x1UL << LCD_CR1_FCC_Pos) +#define LCD_CR1_FCC LCD_CR1_FCC_Msk + +#define LCD_CR1_MODSEL_Pos (13U) +#define LCD_CR1_MODSEL_Msk (0x3UL << LCD_CR1_MODSEL_Pos) +#define LCD_CR1_MODSEL LCD_CR1_MODSEL_Msk +#define LCD_CR1_MODSEL_0 (0x1UL << LCD_CR1_MODSEL_Pos) +#define LCD_CR1_MODSEL_1 (0x2UL << LCD_CR1_MODSEL_Pos) + +#define LCD_CR1_RSEL_Pos (15U) +#define LCD_CR1_RSEL_Msk (0x1UL << LCD_CR1_RSEL_Pos) +#define LCD_CR1_RSEL LCD_CR1_RSEL_Msk + +#define LCD_CR1_PON_Pos (13U) +#define LCD_CR1_PON_Msk (0x3fUL << LCD_CR1_PON_Pos) +#define LCD_CR1_PON LCD_CR1_PON_Msk + +/******************* Bit definition for LCD_CR1 register *********************/ +#define LCD_INTCLR_INTF_Pos (10U) +#define LCD_INTCLR_INTF_Msk (0x1UL << LCD_INTCLR_INTF_Pos) +#define LCD_INTCLR_INTFT LCD_INTCLR_INTF_Msk + + + +/** + * @brief LCD SegCom Init structure definition + */ +typedef struct +{ + uint32_t SEG0_31; /*!< Configures the SEG0 to SEG31 Enable or Disable. + This parameter can be a value between 0x0 and 0xFFFFFFFF */ + union{ + uint32_t SEG32_39_COM0_8; /*!< Configures the SEG32-35 and COM0-8 Enable or Disable. + This parameter can be a value between 0x0 and 0xFFF */ + struct + { + uint32_t SEG32_35 :4; /*!< Configures the SEG32-35 Enable or Disable. + This parameter can be a value between 0x0 and 0xF */ + uint32_t SEG36_COM7 :1; /*!< Configures the SEG36/COM7 Enable or Disable. */ + uint32_t SEG37_COM6 :1; /*!< Configures the SEG37/COM6 Enable or Disable. */ + uint32_t SEG38_COM5 :1; /*!< Configures the SEG38/COM5 Enable or Disable. */ + uint32_t SEG39_COM4 :1; /*!< Configures the SEG39/COM4 Enable or Disable. */ + uint32_t COM0_3 :4; /*!< Configures the COM0-3 Enable or Disable. + This parameter can be a value between 0x0 and 0xF */ + }SEGCOM_bit; + }Stc_SEG32_39_COM0_8; +}LCD_SegComInitTypeDef; + + +/** + * @brief LCD Init structure definition + */ + +typedef struct +{ + uint32_t PONTime; /*!< Configures the Pulse ON duration time. + This parameter can be a value between 0x00 and 0x3F */ + uint32_t BiasRes; /*!< Configures the LCD BiasRes. + This parameter can be one value of @ref BiasRes */ + uint32_t DriveMod; /*!< Configures the LCD DriveMod. + This parameter can be one value of @ref DriveMod */ + uint32_t FastCharge; /*!< Configures the LCD FastCharge. + This parameter can be one value of @ref FastCharge */ + uint32_t Contrast; /*!< Configures the LCD Contrast. + This parameter can be one value of @ref LCD_Contrast */ + +}LCD_InResInitTypeDef; +/** + * @brief LCD Init structure definition + */ + +typedef struct +{ + uint32_t Duty; /*!< Configures the LCD Duty. + This parameter can be one value of @ref LCD_Duty */ + uint32_t Bias; /*!< Configures the LCD Bias. + This parameter can be one value of @ref LCD_Bias */ + uint32_t Driving_Waveform; /*!< Configures the LCD Drive Waveform. + This parameter can be one value of @ref Driving_Waveform */ + + uint32_t BiasSrc; /*!< Configures the LCD Bias Src. + This parameter can be one value of @ref BiasSrc*/ + + uint32_t DisplayMode; /*!< Configures the LCD DisplayMode. + This parameter can be one value of @ref DisplayMode*/ + + uint32_t StaticPower; /*!< Configures the LCD StaticPower. + This parameter can be one value of @ref StaticPower*/ + + uint32_t LCDFrequency; /*!< Configures the LCD LCDFrequency. + This parameter can be one value of @ref LCDFrequency*/ + + uint32_t BlinkEN; /*!< Configures the LCD BlinkEN. + This parameter can be one value of @ref BlinkEN */ + + uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency. + This parameter can be a value between 0x00 and 0x3F */ +}LCD_InitTypeDef; + + +/** + * @brief LCD handle Structure definition + */ +typedef struct +{ + LCD_TypeDef *Instance; /* LCD registers base address */ + + LCD_InitTypeDef Init; /* LCD communication parameters */ + + DMA_HandleTypeDef *DMA_Handle; /*!< UART Rx DMA handle parameters */ +}LCD_HandleTypeDef; + + +#define IS_LCD_PERIPH(PERIPH) (((PERIPH) == LCD)) + +/** @defgroup LCD_Duty LCD Duty + * @{ + */ + +#define LCD_DUTY_STATIC ((uint32_t)0x00000000U) /*!< Static duty */ +#define LCD_DUTY_1_2 LCD_CR0_DUTY_0 /*!< 1/2 duty */ +#define LCD_DUTY_1_3 LCD_CR0_DUTY_1 /*!< 1/3 duty */ +#define LCD_DUTY_1_4 ((LCD_CR0_DUTY_1 | LCD_CR0_DUTY_0)) /*!< 1/4 duty */ +#define LCD_DUTY_1_6 ((LCD_CR0_DUTY_2 | LCD_CR0_DUTY_0)) /*!< 1/6 duty */ +#define LCD_DUTY_1_8 ((LCD_CR0_DUTY_2 | LCD_CR0_DUTY_1 | LCD_CR0_DUTY_0)) /*!< 1/8 duty */ + +#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_DUTY_STATIC) || \ + ((DUTY) == LCD_DUTY_1_2) || \ + ((DUTY) == LCD_DUTY_1_3) || \ + ((DUTY) == LCD_DUTY_1_4) || \ + ((DUTY) == LCD_DUTY_1_6) || \ + ((DUTY) == LCD_DUTY_1_8)) + +/** + * @} + */ + + /** + * @} + */ + + +/** @defgroup LCD_Bias LCD Bias + * @{ + */ + +#define LCD_BIAS_1_4 ((uint32_t)0x00000000U) /*!< 1/4 Bias */ +#define LCD_BIAS_1_2 LCD_CR0_BIAS_0 /*!< 1/2 Bias */ +#define LCD_BIAS_1_3 LCD_CR0_BIAS_1 /*!< 1/3 Bias */ + +#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \ + ((__BIAS__) == LCD_BIAS_1_2) || \ + ((__BIAS__) == LCD_BIAS_1_3)) +/** + * @} + */ + + /** @defgroup Driving_Waveform Driving_Waveform + * @{ + */ + +#define LCD_Driving_Waveform_A ((uint32_t)0x00000000U) /*!< A类波形*/ +#define LCD_Driving_Waveform_B LCD_CR0_WSEL /*!< B类波形 */ +#define IS_LCD_Driving_Waveform(__Driving_Waveform__) (((__Driving_Waveform__) == LCD_Driving_Waveform_A) || \ + ((__Driving_Waveform__) == LCD_Driving_Waveform_B)) +/** + * @} + */ + + /** @defgroup BiasSrc + * @{ + */ + +#define LCD_BiasSrc_InRes_Seg31_35_Normal ((uint32_t)0x00000000U) /*!< LCD Bias来源：内部电阻分压，且SEG31-35可以作为SEG/IO*/ +#define LCD_BiasSrc_InRes_Seg31_35_Cap LCD_CR0_MOD_0 /*!< LCD Bias来源：内部电阻分压，且SEG31-35用于外接电容滤波，SEG/IO功能关闭 */ +#define LCD_BiasSrc_ExRes_Seg31_35_Cap LCD_CR0_MOD_1 /*!< LCD Bias来源：外部电阻分压，且SEG31-35用于外接分压电阻和滤波电容，SEG/IO功能关闭 */ +#define IS_LCD_BiasSrc(__BiasSrc__) (((__BiasSrc__) == LCD_BiasSrc_InRes_Seg31_35_Normal) || \ + ((__BiasSrc__) == LCD_BiasSrc_InRes_Seg31_35_Cap)||\ + ((__BiasSrc__) == LCD_BiasSrc_ExRes_Seg31_35_Cap)) +/** + * @} + */ + + /** @defgroup DisplayMode + * @{ + */ + +#define LCD_DisplayMode_0 ((uint32_t)0x00000000U) /*!< LCD RAM显示模式0*/ +#define LCD_DisplayMode_1 LCD_CR1_MODE /*!< LCD RAM显示模式1 */ +#define IS_LCD_DisplayMode(__DisplayMode__) (((__DisplayMode__) == LCD_DisplayMode_0)||\ + ((__DisplayMode__) == LCD_DisplayMode_1)) +/** + * @} + */ + + + /** @defgroup StaticPower + * @{ + */ + +#define LCD_StaticPower_NormalPower ((uint32_t)0x00000000U) /*!< LCD RAM显示模式0*/ +#define LCD_StaticPower_LowPower LCD_CR0_STATIC /*!< LCD RAM显示模式1 */ +#define IS_LCD_StaticPower(__StaticPower__) (((__StaticPower__) == LCD_StaticPower_NormalPower) || \ + ((__StaticPower__) == LCD_StaticPower_LowPower)) +/** + * @} + */ + + +/** @defgroup LCDFrequency + * @{ + */ + +#define LCD_LCDFrequency_64HZ ((uint32_t)0x00000000U) /*!< LCD扫描频率选择*/ +#define LCD_LCDFrequency_128HZ LCD_CR0_LCDCLK_0 /*!< LCD扫描频率选择 */ +#define LCD_LCDFrequency_256HZ LCD_CR0_LCDCLK_1 /*!< LCD扫描频率选择 */ +#define LCD_LCDFrequency_512HZ ((LCD_CR0_LCDCLK_0 | LCD_CR0_LCDCLK_1)) /*!< LCD扫描频率选择*/ +#define IS_LCD_LCDFrequency(__LCDFrequency__) (((__LCDFrequency__) == LCD_LCDFrequency_64HZ) || \ + ((__LCDFrequency__) == LCD_LCDFrequency_128HZ)||\ + ((__LCDFrequency__) == LCD_LCDFrequency_256HZ)||\ + ((__LCDFrequency__) == LCD_LCDFrequency_512HZ)) +/** + * @} + */ + + /** @defgroup BlinkEN + * @{ + */ +#define LCD_BlinkEN_Disable ((uint32_t)0x00000000U) /*!IOSEL |= (PMU->IOSEL & ~(0x3)) | (__FUNC__)) + +/** @brief PC14 function select + * @param __FUNC__: PC14 function select. + * This parameter can be 0: GPIO，1：PC14 Value + */ +#define __HAL_RTC_PC14_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 3)) | (__FUNC__ << 3)) + +/** @brief PC15 function select + * @param __FUNC__: PC15 function select. + * This parameter can be 0: GPIO，1：PC15 Value + */ +#define __HAL_RTC_PC15_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 5)) | (__FUNC__ << 5)) + +/** @brief PC13 Value set + * @param __FUNC__: PC13 Value set. + * This parameter can be 0: set，1：claer + */ +#define __HAL_RTC_PC13_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 8)) | (__VALUE__ << 8)) + +/** @brief PC14 Value set + * @param __FUNC__: PC14 Value set. + * This parameter can be 0: set，1：claer + */ +#define __HAL_RTC_PC14_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 9)) | (__VALUE__ << 9)) + +/** @brief PC15 Value set + * @param __FUNC__: PC15 Value set. + * This parameter can be 0: set，1：claer + */ +#define __HAL_RTC_PC15_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 10)) | (__VALUE__ << 10)) + +/* @brief PC13、PC14、PC15 pull up or pull down */ +#define __HAL_RTC_PC13_PULL_UP_ENABLE() (PMU->IOCR |= BIT0) +#define __HAL_RTC_PC13_PULL_UP_DISABLE() (PMU->IOCR &= ~BIT0) +#define __HAL_RTC_PC13_PULL_DOWN_ENABLE() (PMU->IOCR |= BIT1) +#define __HAL_RTC_PC13_PULL_DOWN_DISABLE() (PMU->IOCR &= ~BIT1) + +#define __HAL_RTC_PC14_PULL_UP_ENABLE() (PMU->IOCR |= BIT8) +#define __HAL_RTC_PC14_PULL_UP_DISABLE() (PMU->IOCR &= ~BIT8) +#define __HAL_RTC_PC14_PULL_DOWN_ENABLE() (PMU->IOCR |= BIT9) +#define __HAL_RTC_PC14_PULL_DOWN_DISABLE() (PMU->IOCR &= ~BIT9) + +#define __HAL_RTC_PC15_PULL_UP_ENABLE() (PMU->IOCR |= BIT16) +#define __HAL_RTC_PC15_PULL_UP_DISABLE() (PMU->IOCR &= ~BIT16) +#define __HAL_RTC_PC15_PULL_DOWN_ENABLE() (PMU->IOCR |= BIT17) +#define __HAL_RTC_PC15_PULL_DOWN_DISABLE() (PMU->IOCR &= ~BIT17) + +/* @brief PC13、PC14、PC15 digit or analog */ +#define __HAL_RTC_PC13_ANALOG() (PMU->IOCR |= BIT6) +#define __HAL_RTC_PC13_DIGIT() (PMU->IOCR &= ~BIT6) + +#define __HAL_RTC_PC14_ANALOG() (PMU->IOCR |= BIT14) +#define __HAL_RTC_PC14_DIGIT() (PMU->IOCR &= ~BIT14) + +#define __HAL_RTC_PC15_ANALOG() (PMU->IOCR |= BIT22) +#define __HAL_RTC_PC15_DIGIT() (PMU->IOCR &= ~BIT22) + + +/** @defgroup RTC Private Macros + * @{ + */ +#define IS_RTC_CLOCKSRC(__CLOCKSRC__) (((__CLOCKSRC__) == RTC_CLOCK_RC32K) || \ + ((__CLOCKSRC__) == RTC_CLOCK_XTL)) + +#define IS_RTC_COMPENSATION(__COMPENSATION__) (((__COMPENSATION__) == COMPENSATION_INCREASE) || \ + ((__COMPENSATION__) == COMPENSATION_DECREASE)) + +#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= 0x99) + +#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) == RTC_MONTH_JANUARY) || \ + ((__MONTH__) == RTC_MONTH_FEBRUARY) || \ + ((__MONTH__) == RTC_MONTH_MARCH) || \ + ((__MONTH__) == RTC_MONTH_APRIL) || \ + ((__MONTH__) == RTC_MONTH_MAY) || \ + ((__MONTH__) == RTC_MONTH_JUNE) || \ + ((__MONTH__) == RTC_MONTH_JULY) || \ + ((__MONTH__) == RTC_MONTH_AUGUST) || \ + ((__MONTH__) == RTC_MONTH_SEPTEMBER) || \ + ((__MONTH__) == RTC_MONTH_OCTOBER) || \ + ((__MONTH__) == RTC_MONTH_NOVEMBER) || \ + ((__MONTH__) == RTC_MONTH_DECEMBER)) + +#define IS_RTC_DAY(__DAY__) ((__DAY__) >= 0x01 && (__DAY__) <= 0x31) + +#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_HOUR(__HOUR__) ((__HOUR__) <= 0x23) + +#define IS_RTC_MIN(__MIN__) ((__MIN__) <= 0x59) + +#define IS_RTC_SEC(__SEC__) ((__SEC__) <= 0x60) + + +#define IS_RTC_ALARM_MODE(__MODE__) (((__MODE__) == RTC_ALARM_WEEK_MODE) || \ + ((__MODE__) == RTC_ALARM_DAY_MODE)) + +#define IS_RTC_ALARM_INT(__INT__) (((__INT__) == RTC_ALARM_INT_ENABLE) || \ + ((__INT__) == RTC_ALARM_INT_DISABLE)) + +#define IS_RTC_ALARM_DAY_MASK(__MASKD__) (((__MASKD__) == RTC_ALARM_DAY_MASK_ENABLE) || \ + ((__MASKD__) == RTC_ALARM_DAY_MASK_DISABLE)) + +#define IS_RTC_ALARM_HOUR_MASK(__MASKH__) (((__MASKH__) == RTC_ALARM_HOUR_MASK_ENABLE) || \ + ((__MASKH__) == RTC_ALARM_HOUR_MASK_DISABLE)) + +#define IS_RTC_ALARM_MIN_MASK(__MASKM__) (((__MASKM__) == RTC_ALARM_MIN_MASK_ENABLE) || \ + ((__MASKM__) == RTC_ALARM_MIN_MASK_DISABLE)) + +#define IS_RTC_ALARM_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_ALARM_WEEK_SUNDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_MONDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_TUESDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_THURSDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_FRIDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_SATURDAY) || \ + ((__WEEKDAY__) >= 0x01000000 && (__WEEKDAY__) <= 0x7F000000)) + + +#define IS_RTC_TEMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TEMP_EDGE_RISING) || \ + ((__EDGE__) == RTC_TEMP_EDGE_FALLING)) + +#define IS_RTC_TEMP_INT(__INT__) (((__INT__) == RTC_TEMP_INT_ENABLE) || \ + ((__INT__) == RTC_TEMP_INT_DISABLE)) + +#define IS_RTC_TEMP_CLEAR_BACKUP(__CLEAR__) (((__CLEAR__) == RTC_TEMP_CLEAR_DISABLE) || \ + ((__CLEAR__) == RTC_TEMP_CLEAR_ENABLE)) + +#define IS_RTC_TEMP_FILTER(__FILTER__) (((__FILTER__) == RTC_TEMP_FILTER_DISABLE) || \ + ((__FILTER__) == RTC_TEMP_FILTER_512_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_1_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_2_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_4_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_8_RTCCLK)) +/** + * @} + */ + +/* RTC stamp1 interrupt enable、disable */ +#define __HAL_RTC_ENABLE_STAMP1_IT (RTC->IE |= (RTC_IE_STP1RIE | RTC_IE_STP1FIE)) +#define __HAL_RTC_DISABLE_STAMP1_IT (RTC->IE &= ~(RTC_IE_STP1RIE | RTC_IE_STP1FIE)) + +/* RTC stamp2 interrupt enable、disable */ +#define __HAL_RTC_ENABLE_STAMP2_IT (RTC->IE |= (RTC_IE_STP2RIE | RTC_IE_STP2FIE)) +#define __HAL_RTC_DISABLE_STAMP2_IT (RTC->IE &= ~(RTC_IE_STP2RIE | RTC_IE_STP2FIE)) + +/* RTC 32S interrupt enable、disable */ +#define __HAL_RTC_ENABLE_32S_IT (RTC->IE |= RTC_IE_ADJ32) +#define __HAL_RTC_DISABLE_32S_IT (RTC->IE &= ~RTC_IE_ADJ32) + +/* RTC alarm interrupt enable、disable */ +#define __HAL_RTC_ENABLE_ALM_IT (RTC->IE |= RTC_IE_ALM) +#define __HAL_RTC_DISABLE_ALM_IT (RTC->IE &= RTC_IE_ALM) + +/* RTC sec interrupt enable、disable */ +#define __HAL_RTC_ENABLE_SEC_IT (RTC->IE |= RTC_IE_SEC) +#define __HAL_RTC_DISABLE_SEC_IT (RTC->IE &= ~RTC_IE_SEC) + +/* RTC Minutes interrupt enable、disable */ +#define __HAL_RTC_ENABLE_MIN_IT (RTC->IE |= RTC_IE_MIN) +#define __HAL_RTC_DISABLE_MIN_IT (RTC->IE &= ~RTC_IE_MIN) + +/* RTC Hour interrupt enable、disable */ +#define __HAL_RTC_ENABLE_HOUR_IT (RTC->IE |= RTC_IE_HOUR) +#define __HAL_RTC_DISABLE_HOUR_IT (RTC->IE &= ~RTC_IE_HOUR) + +/* RTC Date interrupt enable、disable */ +#define __HAL_RTC_ENABLE_DATE_IT (RTC->IE |= RTC_IE_DATE) +#define __HAL_RTC_DISABLE_DATE_IT (RTC->IE &= ~RTC_IE_DATE) + +/* HAL_RTC_Config */ +HAL_StatusTypeDef HAL_RTC_Config(RTC_ConfigTypeDef *hrtc); + +/* HAL_RTC_SetTime */ +void HAL_RTC_SetTime(RTC_TimeTypeDef *fp_Time); + +/* HAL_RTC_GetTime */ +void HAL_RTC_GetTime(RTC_TimeTypeDef *fp_Time); + +/* HAL_RTC_SetDate */ +void HAL_RTC_SetDate(RTC_DateTypeDef *fp_Date); + +/* HAL_RTC_GetDate */ +void HAL_RTC_GetDate(RTC_DateTypeDef *fp_Date); + + +/* HAL_RTC_AlarmConfig */ +void HAL_RTC_AlarmConfig(RTC_AlarmTypeDef *fp_Alarm); + +/* HAL_RTC_AlarmEnable */ +void HAL_RTC_AlarmEnable(void); + +/* HAL_RTC_AlarmDisable */ +void HAL_RTC_AlarmDisable(void); + +/* HAL_RTC_Tamper */ +void HAL_RTC_Tamper(enum_Temper_t fe_Temper, RTC_TemperTypeDef *fp_Temper); + +/* HAL_RTC_TamperEnable */ +void HAL_RTC_TamperEnable(enum_Temper_t fe_Temper); + +/* HAL_RTC_TamperDisable */ +void HAL_RTC_TamperDisable(enum_Temper_t fe_Temper); + +/* HAL_RTC_Standby_Wakeup */ +void HAL_RTC_Standby_Wakeup(enum_WKUP_t fe_Wakeup, uint32_t fu32_Edge); + +/* HAL_RTC_Get_StandbyStatus */ +bool HAL_RTC_Get_StandbyStatus(void); + +/* HAL_RTC_Get_StandbyWakeupSource */ +uint32_t HAL_RTC_Get_StandbyWakeupSource(void); + +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_SPI.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_SPI.h new file mode 100644 index 0000000000..42748e5a70 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_SPI.h @@ -0,0 +1,301 @@ +/* + ****************************************************************************** + * @file HAL_SPI.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of SPI HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_SPI_H__ +#define __HAL_SPI_H__ + +#include "ACM32Fxx_HAL.h" + +/**************** Bit definition for SPI_CTL register **************************/ +#define SPI_CTL_CS_TIME (BIT11|BIT12|BIT13|BIT14|BIT15|BIT16|BIT17|BIT18) +#define SPI_CTL_CS_FILTER BIT10 +#define SPI_CTL_CS_RST BIT9 +#define SPI_CTL_SLAVE_EN BIT8 +#define SPI_CTL_IO_MODE BIT7 +#define SPI_CTL_X_MODE (BIT6|BIT5) +#define SPI_CTL_LSB_FIRST BIT4 +#define SPI_CTL_CPOL BIT3 +#define SPI_CTL_CPHA BIT2 +#define SPI_CTL_SFILTER BIT1 +#define SPI_CTL_MST_MODE BIT0 + +/**************** Bit definition for SPI_TX_CTL register ***********************/ +#define SPI_TX_CTL_DMA_LEVEL (BIT4|BIT5|BIT6|BIT7) +#define SPI_TX_CTL_DMA_LEVEL_3 BIT7 +#define SPI_TX_CTL_DMA_LEVEL_2 BIT6 +#define SPI_TX_CTL_DMA_LEVEL_1 BIT5 +#define SPI_TX_CTL_DMA_LEVEL_0 BIT4 +#define SPI_TX_CTL_DMA_REQ_EN BIT3 +#define SPI_TX_CTL_MODE BIT2 +#define SPI_TX_CTL_FIFO_RESET BIT1 +#define SPI_TX_CTL_EN BIT0 + +/**************** Bit definition for SPI_RX_CTL register ***********************/ +#define SPI_RX_CTL_DMA_LEVEL (BIT4|BIT5|BIT6|BIT7) +#define SPI_RX_CTL_DMA_LEVEL_3 BIT7 +#define SPI_RX_CTL_DMA_LEVEL_2 BIT6 +#define SPI_RX_CTL_DMA_LEVEL_1 BIT5 +#define SPI_RX_CTL_DMA_LEVEL_0 BIT4 +#define SPI_RX_CTL_DMA_REQ_EN BIT3 +#define SPI_RX_CTL_FIFO_RESET BIT1 +#define SPI_RX_CTL_EN BIT0 + +/**************** Bit definition for SPI_IE register ***************************/ +#define SPI_IE_RX_BATCH_DONE_EN BIT15 +#define SPI_IE_TX_BATCH_DONE_EN BIT14 +#define SPI_IE_RX_FIFO_FULL_OV_EN BIT13 +#define SPI_IE_RX_FIFO_EMPTY_OV_EN BIT12 +#define SPI_IE_RX_NOT_EMPTY_EN BIT11 +#define SPI_IE_CS_POS_EN BIT10 +#define SPI_IE_RX_FIFO_HALF_FULL_EN BIT9 +#define SPI_IE_RX_FIFO_HALF_EMPTY_EN BIT8 +#define SPI_IE_TX_FIFO_HALF_FULL_EN BIT7 +#define SPI_IE_TX_FIFO_HALF_EMPTY_EN BIT6 +#define SPI_IE_RX_FIFO_FULL_EN BIT5 +#define SPI_IE_RX_FIFO_EMPTY_EN BIT4 +#define SPI_IE_TX_FIFO_FULL_EN BIT3 +#define SPI_IE_TX_FIFO_EMPTY_EN BIT2 +#define SPI_IE_BATCH_DONE_EN BIT1 + +/**************** Bit definition for SPI_STATUS register ***********************/ +#define SPI_STATUS_RX_BATCH_DONE BIT15 +#define SPI_STATUS_TX_BATCH_DONE BIT14 +#define SPI_STATUS_RX_FIFO_FULL_OV BIT13 +#define SPI_STATUS_RX_FIFO_EMPTY_OV BIT12 +#define SPI_STATUS_RX_NOT_EMPTY BIT11 +#define SPI_STATUS_CS_POS BIT10 +#define SPI_STATUS_RX_FIFO_HALF_FULL BIT9 +#define SPI_STATUS_RX_FIFO_HALF_EMPTY BIT8 +#define SPI_STATUS_TX_FIFO_HALF_FULL BIT7 +#define SPI_STATUS_TX_FIFO_HALF_EMPTY BIT6 +#define SPI_STATUS_RX_FIFO_FULL BIT5 +#define SPI_STATUS_RX_FIFO_EMPTY BIT4 +#define SPI_STATUS_TX_FIFO_FULL BIT3 +#define SPI_STATUS_TX_FIFO_EMPTY BIT2 +#define SPI_STATUS_BATCH_DONE BIT1 +#define SPI_STATUS_TX_BUSY BIT0 + +/**************** Bit definition for SPI_CS register ***************************/ +#define SPI_CS_CSX BIT1 +#define SPI_CS_CS0 BIT0 + +/**************** Bit definition for SPI_OUT_EN register ***********************/ +#define SPI_HOLD_EN BIT3 +#define SPI_HOLD_WP_EN BIT2 +#define SPI_HOLD_MISO_EN BIT1 +#define SPI_HOLD_MOSI_EN BIT0 + +/**************** Bit definition for SPI_MEMO_ACC register ***********************/ +#define SPI_ADDR_WIDTH (BIT14|BIT15|BIT16|BIT17|BIT18) +#define SPI_PARA_NO2 (BIT9|BIT10|BIT11|BIT12|BIT13) +#define SPI_PARA_NO1 (BIT5|BIT6|BIT7|BIT8) +#define SPI_CON_RD_EN BIT3 +#define SPI_PARA_ORD2 BIT2 +#define SPI_PARA_ORD1 BIT1 +#define SPI_ACC_EN BIT0 + +/** @defgroup SLAVE State machine + * @{ + */ +#define SPI_RX_STATE_IDLE (0U) +#define SPI_RX_STATE_RECEIVING (1U) +#define SPI_TX_STATE_IDLE (0U) +#define SPI_TX_STATE_SENDING (1U) +/** + * @} + */ + + +/** @defgroup SPI_MODE + * @{ + */ +#define SPI_MODE_SLAVE (0U) +#define SPI_MODE_MASTER (1U) +/** + * @} + */ + + +/** @defgroup SPI_WORK_MODE + * @{ + */ +#define SPI_WORK_MODE_0 (0x00000000) +#define SPI_WORK_MODE_1 (0x00000004) +#define SPI_WORK_MODE_2 (0x00000008) +#define SPI_WORK_MODE_3 (0x0000000C) +/** + * @} + */ + + +/** @defgroup SPI_CLOCK_PHASE SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0U) +#define SPI_PHASE_2EDGE (1U) +/** + * @} + */ + + +/** @defgroup X_MODE SPI Clock Phase + * @{ + */ +#define SPI_1X_MODE (0x00000000) +#define SPI_2X_MODE (0x00000020) +#define SPI_4X_MODE (0x00000040) +/** + * @} + */ + + +/** @defgroup SPI_MSB_LSB_FIRST + * @{ + */ +#define SPI_FIRSTBIT_MSB (0U) +#define SPI_FIRSTBIT_LSB (1U) +/** + * @} + */ + + +/** @defgroup BAUDRATE_PRESCALER + * @{ + */ +#define SPI_BAUDRATE_PRESCALER_4 (4U) +#define SPI_BAUDRATE_PRESCALER_8 (8U) +#define SPI_BAUDRATE_PRESCALER_16 (16U) +#define SPI_BAUDRATE_PRESCALER_32 (32U) +#define SPI_BAUDRATE_PRESCALER_64 (64U) +#define SPI_BAUDRATE_PRESCALER_128 (128U) +#define SPI_BAUDRATE_PRESCALER_254 (254U) +/** + * @} + */ + + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t SPI_Mode; /* This parameter can be a value of @ref SPI_MODE */ + + uint32_t SPI_Work_Mode; /* This parameter can be a value of @ref SPI_WORK_MODE */ + + uint32_t X_Mode; /* This parameter can be a value of @ref X_MODE */ + + uint32_t First_Bit; /* This parameter can be a value of @ref SPI_MSB_LSB_FIRST */ + + uint32_t BaudRate_Prescaler; /* This parameter can be a value of @ref BAUDRATE_PRESCALER */ +}SPI_InitTypeDef; + +/******************************** Check SPI Parameter *******************************/ +#define IS_SPI_ALL_MODE(SPI_Mode) (((SPI_Mode) == SPI_MODE_SLAVE) || \ + ((SPI_Mode) == SPI_MODE_MASTER)) + +#define IS_SPI_WORK_MODE(WORK_MODE) (((WORK_MODE) == SPI_WORK_MODE_0) || \ + ((WORK_MODE) == SPI_WORK_MODE_1) || \ + ((WORK_MODE) == SPI_WORK_MODE_2) || \ + ((WORK_MODE) == SPI_WORK_MODE_3)) + +#define IS_SPI_X_MODE(X_MODE) (((X_MODE) == SPI_1X_MODE) || \ + ((X_MODE) == SPI_2X_MODE) || \ + ((X_MODE) == SPI_4X_MODE)) + +#define IS_SPI_FIRST_BIT(FIRST_BIT) (((FIRST_BIT) == SPI_FIRSTBIT_MSB) || \ + ((FIRST_BIT) == SPI_FIRSTBIT_LSB)) + +#define IS_SPI_BAUDRATE_PRESCALER(BAUDRATE) (((BAUDRATE) == SPI_BAUDRATE_PRESCALER_4) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_8) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_16) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_32) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_64) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_128) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_254)) + +/** + * @brief SPI handle Structure definition + */ +typedef struct +{ + SPI_TypeDef *Instance; /* SPI registers base address */ + + SPI_InitTypeDef Init; /* SPI communication parameters */ + + uint32_t RxState; /* SPI state machine */ + uint32_t TxState; /* SPI state machine */ + + uint8_t *Rx_Buffer; /* SPI Rx Buffer */ + uint8_t *Tx_Buffer; /* SPI Tx Buffer */ + + uint32_t Rx_Size; /* SPI Rx Size */ + uint32_t Tx_Size; /* SPI Tx Size */ + + uint32_t Rx_Count; /* SPI RX Count */ + uint32_t Tx_Count; /* SPI TX Count */ + + DMA_HandleTypeDef *HDMA_Rx; /* SPI Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* SPI Tx DMA handle parameters */ + +}SPI_HandleTypeDef; + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2)) + +/* Function : HAL_SPI_IRQHandler */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_MspInit */ +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_MspDeInit */ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_Init */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_DeInit */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_Transmit */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_SPI_Transmit_DMA */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +/* Function : HAL_SPI_Receive */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_SPI_Receive_DMA */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +/* Function : HAL_SPI_Wire_Config */ +HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode); + +/* Function : HAL_SPI_Transmit_IT */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +/* Function : HAL_SPI_Receive_IT */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +/* Function : HAL_SPI_TransmitReceive */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_SPI_GetTxState */ +uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_GetRxState */ +uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi); + +#endif + + + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_TIM.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_TIM.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER.h new file mode 100644 index 0000000000..49227e5620 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER.h @@ -0,0 +1,505 @@ +/*********************************************************************** + * Filename : hal_timer.h + * Description : timer driver header file + * Author(s) : Eric + * version : V1.0 + * Modify date : 2016-03-24 + ***********************************************************************/ +#ifndef __HAL_TIMER_H__ +#define __HAL_TIMER_H__ + +#include "ACM32Fxx_HAL.h" + +#define IS_TIMER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) \ + || ((INSTANCE) == TIM6) \ + || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16)\ + | ((INSTANCE) == TIM17) ) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM15)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_UDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ( (((INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) ) ) \ + || \ + (((INSTANCE) == TIM3) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)) ) \ + || \ + (((INSTANCE) == TIM14) && \ + (((CHANNEL) == TIM_CHANNEL_1)) ) \ + || \ + (((INSTANCE) == TIM15) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) ) \ + || \ + (((INSTANCE) == TIM16) && \ + (((CHANNEL) == TIM_CHANNEL_1)) ) \ + || \ + (((INSTANCE) == TIM17) && \ + ((CHANNEL) == TIM_CHANNEL_1) ) ) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((( (INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3)) ) \ + || \ + (((INSTANCE) == TIM15) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM16) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17) && \ + ((CHANNEL) == TIM_CHANNEL_1) ) ) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) \ + ((INSTANCE) == TIM3) \ + ((INSTANCE) == TIM4) ) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) \ + ((INSTANCE) == TIM3) \ + ((INSTANCE) == TIM4) ) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) \ + ((INSTANCE) == TIM3) \ + ((INSTANCE) == TIM4) ) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) \ + ((INSTANCE) == TIM3) \ + ((INSTANCE) == TIM4) ) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM15)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +#define HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) +#define HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +#define HAL_TIM_ENABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER |= (__INTERRUPT__)) +#define HAL_TIM_DISABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER &= ~(__INTERRUPT__)) + +#define HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER |= (__DMA_REQ__)) +#define HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER &= ~(__DMA_REQ__)) + + + +#define TIM_CR2_CCPC_Pos (0U) +#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) +#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk +#define TIM_CR2_CCUS_Pos (2U) +#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) +#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk +#define TIM_CR2_CCDS_Pos (3U) +#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) +#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk + +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS +#define TIM_COMMUTATION_SOFTWARE 0x00000000U + +#define TIM_IT_UPDATE BIT0 +#define TIM_IT_CC1 BIT1 +#define TIM_IT_CC2 BIT2 +#define TIM_IT_CC3 BIT3 +#define TIM_IT_CC4 BIT4 +#define TIM_IT_COM BIT5 +#define TIM_IT_TRIGGER BIT6 +#define TIM_IT_BREAK BIT7 + +#define TIM_DMA_UPDATE BIT8 +#define TIM_DMA_CC1 BIT9 +#define TIM_DMA_CC2 BIT10 +#define TIM_DMA_CC3 BIT11 +#define TIM_DMA_CC4 BIT12 +#define TIM_DMA_COM BIT13 +#define TIM_DMA_TRIGGER BIT14 +#define TIM_DMA_BREAK BIT15 + + + +#define TIM_EVENTSOURCE_UPDATE BIT0 /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 BIT1 /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 BIT2 /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 BIT3 /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 BIT4 /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM BIT5 /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER BIT6 /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK BIT7 /*!< A break event is generated */ + +#define TIM_ARR_PRELOAD_DISABLE 0 +#define TIM_ARR_PRELOAD_ENABLE 1 + +#define TIM_COUNTERMODE_DIR_INDEX 4 +#define TIM_COUNTERMODE_UP (0 << TIM_COUNTERMODE_DIR_INDEX) +#define TIM_COUNTERMODE_DOWN (1 << TIM_COUNTERMODE_DIR_INDEX) + +#define TIM_COUNTERMODE_CMS_INDEX 5 +#define TIM_COUNTERMODE_CENTERALIGNED1 (1 << TIM_COUNTERMODE_CMS_INDEX) +#define TIM_COUNTERMODE_CENTERALIGNED2 (2 << TIM_COUNTERMODE_CMS_INDEX) +#define TIM_COUNTERMODE_CENTERALIGNED3 (3 << TIM_COUNTERMODE_CMS_INDEX) + +#define TIM_CLKCK_DIV_INDEX 8 +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 (1U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 (2U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=4*tCK_INT */ + +#define TIM_TRGO_RESET (0 << 4) +#define TIM_TRGO_ENABLE (1 << 4) +#define TIM_TRGO_UPDATE (2 << 4) +#define TIM_TRGO_CMP_PULSE (3 << 4) +#define TIM_TRGO_OC1REF (4 << 4) +#define TIM_TRGO_OC2REF (5 << 4) +#define TIM_TRGO_OC3REF (6 << 4) +#define TIM_TRGO_OC4REF (7 << 4) + +#define TIM_MASTERSLAVEMODE_DISABLE 0 +#define TIM_MASTERSLAVEMODE_ENABLE BIT7 + + +#define TIM_SLAVE_MODE_INDEX 0 +#define TIM_SLAVE_MODE_DIS (0U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC1 (1U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC2 (2U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC3 (3U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_RST (4U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_GATE (5U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_TRIG (6U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_EXT1 (7U << TIM_SLAVE_MODE_INDEX) + +#define TIM_TRIGGER_SOURCE_INDEX 4 +#define TIM_TRIGGER_SOURCE_ITR0 (0U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_ITR1 (1U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_ITR2 (2U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_ITR3 (3U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_TI1F_ED (4U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_TI1FP1 (5U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_TI2FP2 (6U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_ETRF (7U << TIM_TRIGGER_SOURCE_INDEX) + +#define TIMER_SR_UIF BIT0 +#define TIMER_SR_CC1IF BIT1 +#define TIMER_SR_CC2IF BIT2 +#define TIMER_SR_CC3IF BIT3 +#define TIMER_SR_CC4IF BIT4 +#define TIMER_SR_COMIF BIT5 +#define TIMER_SR_TIF BIT6 +#define TIMER_SR_BIF BIT7 +#define TIMER_SR_CC1OF BIT9 +#define TIMER_SR_CC2OF BIT10 +#define TIMER_SR_CC3OF BIT11 +#define TIMER_SR_CC4OF BIT12 + +#define TIMER_INT_EN_UPD BIT0 +#define TIMER_INT_EN_CC1 BIT1 +#define TIMER_INT_EN_CC2 BIT2 +#define TIMER_INT_EN_CC3 BIT3 +#define TIMER_INT_EN_CC4 BIT4 +#define TIMER_INT_EN_COM BIT5 +#define TIMER_INT_EN_TRI BIT6 +#define TIMER_INT_EN_BRK BIT7 + +#define TIMER_DMA_EN_UPD BIT8 +#define TIMER_DMA_EN_CC1 BIT9 +#define TIMER_DMA_EN_CC2 BIT10 +#define TIMER_DMA_EN_CC3 BIT11 +#define TIMER_DMA_EN_CC4 BIT12 +#define TIMER_DMA_EN_COM BIT13 +#define TIMER_DMA_EN_TRI BIT14 + +#define TIM_CHANNEL_1 0 +#define TIM_CHANNEL_2 1 +#define TIM_CHANNEL_3 2 +#define TIM_CHANNEL_4 3 + +#define OUTPUT_FAST_MODE_DISABLE 0 +#define OUTPUT_FAST_MODE_ENABLE 1 + +#define OUTPUT_POL_ACTIVE_HIGH 0 +#define OUTPUT_POL_ACTIVE_LOW 1 + +#define OUTPUT_DISABLE_IDLE_STATE 0 +#define OUTPUT_ENABLE_IDLE_STATE 1 + +#define OUTPUT_IDLE_STATE_0 0 +#define OUTPUT_IDLE_STATE_1 1 + +#define OUTPUT_MODE_FROZEN 0 +#define OUTPUT_MODE_MATCH_HIGH 1 +#define OUTPUT_MODE_MATCH_LOW 2 +#define OUTPUT_MODE_MATCH_TOGGLE 3 +#define OUTPUT_MODE_FORCE_LOW 4 +#define OUTPUT_MODE_FORCE_HIGH 5 +#define OUTPUT_MODE_PWM1 6 +#define OUTPUT_MODE_PWM2 7 + +#define TIM_CLOCKSOURCE_INT 0 +#define TIM_CLOCKSOURCE_ITR0 1 +#define TIM_CLOCKSOURCE_ITR1 2 +#define TIM_CLOCKSOURCE_ITR2 3 +#define TIM_CLOCKSOURCE_ITR3 4 +#define TIM_CLOCKSOURCE_TI1FP1 5 +#define TIM_CLOCKSOURCE_TI2FP2 6 +#define TIM_CLOCKSOURCE_ETR 7 + +#define TIM_ETR_POLAIRTY_HIGH 0 +#define TIM_ETR_POLAIRTY_LOW (BIT15) +#define TIM_ETR_FILTER_LVL(x) (x << 8) //BIT8-BIT11 + +#define TIM_ETR_PRESCALER_1 0 +#define TIM_ETR_PRESCALER_2 (BIT12) +#define TIM_ETR_PRESCALER_4 (BIT13) +#define TIM_ETR_PRESCALER_8 (BIT12|BIT13) + +#define ETR_SELECT_GPIO 0 +#define ETR_SELECT_COMP1_OUT BIT14 +#define ETR_SELECT_COMP2_OUT BIT15 +#define ETR_SELECT_ADC_AWD BIT14|BIT15 +#define ETR_SELECT_MASK (BIT14|BIT15) + +#define TIM_TI1_FILTER_LVL(x) (x << 4) +#define TIM_TI2_FILTER_LVL(x) (x << 12) +#define TIM_TI3_FILTER_LVL(x) (x << 4) +#define TIM_TI4_FILTER_LVL(x) (x << 12) + +#define TIM_IC1_PRESCALER_1 0 +#define TIM_IC1_PRESCALER_2 (BIT2) +#define TIM_IC1_PRESCALER_4 (BIT3) +#define TIM_IC1_PRESCALER_8 (BIT2|BIT3) + +#define TIM_IC2_PRESCALER_1 0 +#define TIM_IC2_PRESCALER_2 (BIT10) +#define TIM_IC2_PRESCALER_4 (BIT11) +#define TIM_IC2_PRESCALER_8 (BIT10|BIT11) + +#define TIM_IC3_PRESCALER_1 0 +#define TIM_IC3_PRESCALER_2 (BIT2) +#define TIM_IC3_PRESCALER_4 (BIT3) +#define TIM_IC3_PRESCALER_8 (BIT2|BIT3) + +#define TIM_IC4_PRESCALER_1 0 +#define TIM_IC4_PRESCALER_2 (BIT10) +#define TIM_IC4_PRESCALER_4 (BIT11) +#define TIM_IC4_PRESCALER_8 (BIT10|BIT11) + +typedef struct +{ + uint32_t ClockSource; //TIMER clock sources + uint32_t ClockPolarity; //TIMER clock polarity + uint32_t ClockPrescaler; //TIMER clock prescaler + uint32_t ClockFilter; //TIMER clock filter +} TIM_ClockConfigTypeDef; + +typedef struct +{ + uint32_t OCMode; // Specifies the TIM mode. + uint32_t Pulse; // Specifies the pulse value to be loaded into the Capture Compare Register. + uint32_t OCPolarity; // Specifies the output polarity. + uint32_t OCNPolarity; // Specifies the complementary output polarity. + uint32_t OCFastMode; // Specifies the Fast mode state. + uint32_t OCIdleState; // Specifies the TIM Output Compare pin state during Idle state. + uint32_t OCNIdleState; // Specifies the TIM Output Compare complementary pin state during Idle state. +} TIM_OC_InitTypeDef; + + +#define TIM_SLAVE_CAPTURE_ACTIVE_RISING 0 +#define TIM_SLAVE_CAPTURE_ACTIVE_FALLING 1 +#define TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING 2 + +#define TIM_ICSELECTION_DIRECTTI 0 +#define TIM_ICSELECTION_INDIRECTTI 1 + +#define TIM_CC1_SLAVE_CAPTURE_POL_RISING (0) +#define TIM_CC1_SLAVE_CAPTURE_POL_FALLING (BIT1) +#define TIM_CC1_SLAVE_CAPTURE_POL_BOTH (BIT1 | BIT3) + +#define TIM_CC2_SLAVE_CAPTURE_POL_RISING (0) +#define TIM_CC2_SLAVE_CAPTURE_POL_FALLING (BIT5) +#define TIM_CC2_SLAVE_CAPTURE_POL_BOTH (BIT5 | BIT7) + +#define TIM_CC3_SLAVE_CAPTURE_POL_RISING (0) +#define TIM_CC3_SLAVE_CAPTURE_POL_FALLING (BIT9) +#define TIM_CC3_SLAVE_CAPTURE_POL_BOTH (BIT9 | BIT11) + +#define TIM_CC4_SLAVE_CAPTURE_POL_RISING (0) +#define TIM_CC4_SLAVE_CAPTURE_POL_FALLING (BIT13) +#define TIM_CC4_SLAVE_CAPTURE_POL_BOTH (BIT13 | BIT15) + +typedef struct +{ + uint32_t SlaveMode; // Slave mode selection + uint32_t InputTrigger; // Input Trigger source + uint32_t TriggerPolarity; // Input Trigger polarity + uint32_t TriggerPrescaler; // input prescaler, only for ETR input + uint32_t TriggerFilter; // Input trigger filter +} TIM_SlaveConfigTypeDef; + +typedef struct +{ + uint32_t ICPolarity; // Specifies the active edge of the input signal. + uint32_t ICSelection; // Specifies the input + uint32_t ICPrescaler; // Specifies the Input Capture Prescaler. + uint32_t TIFilter; // Specifies the input capture filter. +} TIM_IC_InitTypeDef; + +typedef struct +{ + uint32_t MasterOutputTrigger; // Trigger output (TRGO) selection + uint32_t MasterSlaveMode; // Master/slave mode selection +} TIM_MasterConfigTypeDef; + +#define TIM_DMA_UPDATE_INDEX 0 +#define TIM_DMA_CC1_INDEX 1 +#define TIM_DMA_CC2_INDEX 2 +#define TIM_DMA_CC3_INDEX 3 +#define TIM_DMA_CC4_INDEX 4 +#define TIM_DMA_COM_INDEX 5 +#define TIM_DMA_TRIG_INDEX 6 + +#define MAX_DMA_REQ_ONE_TIMER 7 + +typedef struct +{ + uint32_t Prescaler; // Specifies the prescaler value used to divide the TIM clock. + uint32_t Period; // Specifies the ARR value + uint32_t ARRPreLoadEn; // Specifies the preload enable or disable + uint32_t RepetitionCounter; // Specifies the repetition counter value + uint32_t CounterMode; // Specifies the counter mode.Up/Down/Center + uint32_t ClockDivision; // Specifies the clock division, used for deadtime or sampling +} TIM_Base_InitTypeDef; + +typedef struct +{ + TIM_TypeDef *Instance; + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + DMA_HandleTypeDef *hdma[MAX_DMA_REQ_ONE_TIMER]; +}TIM_HandleTypeDef; + +/* HAL_TIMER_MSP_Init */ +extern uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim); +/* HAL_TIMER_Slave_Mode_Config */ +extern uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +/* HAL_TIMER_Base_Init */ +extern uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim); +/* HAL_TIMER_Output_Config */ +extern uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel); +/* HAL_TIMER_Base_Start */ +extern void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx); +extern HAL_StatusTypeDef HAL_TIMER_Base_Stop(TIM_TypeDef *TIMx); +/* HAL_TIM_PWM_Output_Start */ +extern uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIM_PWM_Output_Stop */ +extern HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIMER_OC_Start */ +extern uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIMER_OCxN_Start */ +extern uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIMER_OC_Stop */ +extern HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIM_Capture_Start */ +extern uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIM_Capture_Stop */ +extern uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIMER_Capture_Config */ +extern uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel); +/* HAL_TIMER_Master_Mode_Config */ +extern uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig); +/* HAL_TIMER_SelectClockSource */ +extern HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +/* HAL_TIMER_ReadCapturedValue */ +extern uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/* HAL_TIMER_Clear_Capture_Flag */ +extern void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel); +#endif + + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER_EX.h b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER_EX.h new file mode 100644 index 0000000000..299988491e --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER_EX.h @@ -0,0 +1,128 @@ +/*********************************************************************** + * Filename : hal_timer_ex.h + * Description : timer driver header file + * Author(s) : xwl + * version : V1.0 + * Modify date : 2021-03-24 + ***********************************************************************/ +#ifndef __HAL_TIMER_EX_H__ +#define __HAL_TIMER_EX_H__ + +#include "ACM32Fxx_HAL.h" + + +#define TIM_BDTR_DTG_Pos (0U) +#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ +#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!Instance)) return; + if(!IS_ADC_ALL_CONCONVMODE(hadc->Init.ConConvMode)) return; + + Status = hadc->Instance->SR; + /************ Check End of Conversion flag for injected ************/ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_JEOCIE)) + { + if((Status & ADC_SR_JEOC) == ADC_SR_JEOC) + { + if(__HAL_ADC_CHECK_TRIG_INJECTED(hadc, ADC_SOFTWARE_START) || + ((__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) && + (hadc->Init.ConConvMode == 0))) + { + /* Disable ADC end of conversion interrupt on group injected */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_JEOCIE); + + } + + /* Conversion complete callback */ + if (NULL != hadc->InjectedConvCpltCallback) + hadc->InjectedConvCpltCallback(hadc); + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC); + } + } + + /************ Check Conversion flag for regular group ************/ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_EOCIE)) + { + if((Status & ADC_SR_EOC) == ADC_SR_EOC) + { + /* Conversion complete callback */ + if (NULL != hadc->ConvCpltCallback) + hadc->ConvCpltCallback(hadc); + + /* Clear conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOC); + } + } + + /************ Check Analog watchdog flags ************/ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_AWDIE)) + { + if((Status & ADC_SR_AWD) == ADC_SR_AWD) + { + /* Level out of window callback */ + if (NULL != hadc->LevelOutOfWindowCallback) + hadc->LevelOutOfWindowCallback(hadc); + + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_AWD); + } + } + + /************ Check End of Conversion flag for regular group ************/ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_EOGIE)) + { + if((Status & ADC_SR_EOG) == ADC_SR_EOG) + { + if((__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) && + (hadc->Init.ConConvMode == 0)) + { + /* Disable ADC end of conversion interrupt on group regular */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOGIE); + } + + /* Conversion complete callback */ + if (NULL != hadc->GroupCpltCallback) + hadc->GroupCpltCallback(hadc); + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOG); + } + } +} + +static volatile uint32_t gu32_ITC_Conunt = 0; // transfer complete interrupt count +static volatile uint32_t gu32_IE_Conunt = 0; // transfer error interrupt count + +/************************************************************************ + * function : DMA_ADC_ITC_Callback + * Description: DMA adc to memory transfer complete interrupt Callback. + ************************************************************************/ +static void DMA_ADC_ITC_Callback(void) +{ + gu32_ITC_Conunt++; +} + +/************************************************************************ + * function : DMA_ADC_IE_Callback + * Description: DMA adc to memory transfer error interrupt Callback. + ************************************************************************/ +static void DMA_ADC_IE_Callback(void) +{ + gu32_IE_Conunt++; +} + +/************************************************************************ + * function : HAL_ADC_MspInit + * Description: + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : none + ************************************************************************/ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + uint32_t i; + uint32_t ADC_Pin_Map[][3] = + { + { ADC_CHANNEL_0_EN, GPIOD, GPIO_PIN_5 }, + { ADC_CHANNEL_1_EN, GPIOA, GPIO_PIN_4 }, + { ADC_CHANNEL_2_EN, GPIOA, GPIO_PIN_5 }, + { ADC_CHANNEL_3_EN, GPIOA, GPIO_PIN_6 }, + { ADC_CHANNEL_4_EN, GPIOA, GPIO_PIN_7 }, + { ADC_CHANNEL_5_EN, GPIOC, GPIO_PIN_4 }, + { ADC_CHANNEL_6_EN, GPIOC, GPIO_PIN_5 }, + { ADC_CHANNEL_7_EN, GPIOB, GPIO_PIN_0 }, + { ADC_CHANNEL_8_EN, GPIOD, GPIO_PIN_4 }, + { ADC_CHANNEL_9_EN, GPIOA, GPIO_PIN_3 }, + { ADC_CHANNEL_10_EN, GPIOA, GPIO_PIN_2 }, + { ADC_CHANNEL_11_EN, GPIOA, GPIO_PIN_0 }, + { ADC_CHANNEL_12_EN, GPIOC, GPIO_PIN_3 }, + { ADC_CHANNEL_13_EN, GPIOC, GPIO_PIN_2 }, + { ADC_CHANNEL_14_EN, GPIOC, GPIO_PIN_1 }, + { ADC_CHANNEL_15_EN, GPIOC, GPIO_PIN_0 }, + { ADC_CHANNEL_VBAT_EN, GPIOA, GPIO_PIN_1 }, + { ADC_CHANNEL_EXT2_EN, GPIOB, GPIO_PIN_1 }, + { ADC_CHANNEL_EXT3_EN, GPIOB, GPIO_PIN_2 }, + { 0xffffffff, 0 }, //结束标志 + }; + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + static DMA_HandleTypeDef Dma_Adc_Handle; + + //Set gpio to analog. + for(i = 0; ADC_Pin_Map[i][0] != 0xffffffff; i++) + { + if(hadc->Init.ChannelEn & ADC_Pin_Map[i][0]) + { + GPIO_Handle.Pin = ADC_Pin_Map[i][2]; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init((enum_GPIOx_t)ADC_Pin_Map[i][1], &GPIO_Handle); + } + /* Enable GPIO Clock */ + if((ADC_Pin_Map[i][1] == GPIOA) || (ADC_Pin_Map[i][1] == GPIOB)) + System_Module_Enable(EN_GPIOAB); + else if((ADC_Pin_Map[i][1] == GPIOC) || (ADC_Pin_Map[i][1] == GPIOD)) + System_Module_Enable(EN_GPIOCD); + } + + if(hadc->Init.DMAMode) + { + Dma_Adc_Handle.Instance = DMA_Channel2; + Dma_Adc_Handle.Init.Request_ID = REQ0_ADC; + Dma_Adc_Handle.Init.Mode = DMA_CIRCULAR; + Dma_Adc_Handle.Init.Data_Flow = DMA_DATA_FLOW_P2M; + Dma_Adc_Handle.Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE; + Dma_Adc_Handle.Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE; + Dma_Adc_Handle.Init.Source_Width = DMA_SRC_WIDTH_WORD; + Dma_Adc_Handle.Init.Desination_Width = DMA_DST_WIDTH_WORD; + + /*-----------------------------------------------------------------------------------*/ + /* Note:If user dons not apply interrupt, Set DMA_ITC_CallbackbDMA_IE_Callback NULL */ + /*-----------------------------------------------------------------------------------*/ + Dma_Adc_Handle.DMA_ITC_Callback = DMA_ADC_ITC_Callback; + Dma_Adc_Handle.DMA_IE_Callback = DMA_ADC_IE_Callback; + + HAL_DMA_Init(&Dma_Adc_Handle); + + hadc->DMA_Handle = &Dma_Adc_Handle; + } + + /* Enable ADC Clock */ + System_Module_Enable(EN_ADC); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(ADC_IRQn); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(ADC_IRQn); +} + +/************************************************************************ + * function : HAL_ADC_MspDeInit + * Description: + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : none + ************************************************************************/ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + static DMA_HandleTypeDef Dma_Adc_Handle; + + if(hadc->Init.DMAMode) + { + HAL_DMA_DeInit(&Dma_Adc_Handle); + + hadc->DMA_Handle = NULL; + } + + /* Disable ADC Clock */ + System_Module_Disable(EN_ADC); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(ADC_IRQn); + + /* Disable External Interrupt */ + NVIC_DisableIRQ(ADC_IRQn); +} + +/************************************************************************ + * function : HAL_ADC_Init + * Description: Init the ADC module + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + /* Check the ADC handle allocation */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + if(!IS_ADC_ALL_CONCONVMODE(hadc->Init.ConConvMode)) return HAL_ERROR; + if(!IS_ADC_ALL_JCHANNELMODE(hadc->Init.JChannelMode)) return HAL_ERROR; + if(!IS_ADC_ALL_DIFFMODE(hadc->Init.DiffMode)) return HAL_ERROR; + if(!IS_ADC_ALL_DMAMODE(hadc->Init.DMAMode)) return HAL_ERROR; + if(!IS_ADC_ALL_OVERMODE(hadc->Init.OverMode)) return HAL_ERROR; + if(!IS_ADC_ALL_OVERSAMPMODE(hadc->Init.OverSampMode)) return HAL_ERROR; + if(!IS_ADC_ALL_OVSR(hadc->Init.Oversampling.Ratio)) return HAL_ERROR; + if(!IS_ADC_ALL_OVSS(hadc->Init.Oversampling.RightBitShift)) return HAL_ERROR; + if(!IS_ADC_ALL_ANALOGWDGEN(hadc->Init.AnalogWDGEn)) return HAL_ERROR; + if(!IS_ADC_ALL_CLOCKDIV(hadc->Init.ClockDiv)) return HAL_ERROR; + if(!IS_ADC_ALL_CHANNELEN(hadc->Init.ChannelEn)) return HAL_ERROR; + if(!IS_ADC_ALL_TRIG(hadc->Init.ExTrigMode.ExTrigSel)) return HAL_ERROR; + if(!IS_ADC_ALL_CHANNELEN(hadc->Init.ExTrigMode.JExTrigSel)) return HAL_ERROR; + + /* Init the low level hardware : GPIO, CLOCK, NVIC, DMA */ + HAL_ADC_MspInit(hadc); + + //Reset AFE. + SET_BIT(hadc->Instance->CR2,ADC_CR2_AFE_RSTN); + //Set Clock DIV. + MODIFY_REG(hadc->Instance->CR2,ADC_CR2_DIV_MASK,hadc->Init.ClockDiv<Init.ConConvMode) + SET_BIT(hadc->Instance->CR1,ADC_CR1_CONT); + else + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_CONT); + + //Overflow + if(hadc->Init.OverMode == ADC_OVERMODE_ENABLE) + SET_BIT(hadc->Instance->CR2,ADC_CR2_OVRMOD); + else + CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_OVRMOD); + + //Over Sample Set + if(hadc->Init.OverSampMode) + { + if(hadc->Init.JChannelMode) + { + SET_BIT(hadc->Instance->CR2,ADC_CR2_JOVSE); // Inject channel over sample en. + if(hadc->Init.Oversampling.TriggeredMode) + SET_BIT(hadc->Instance->CR2,ADC_CR2_JTOVS); // N times sample every trig. + else + CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_JTOVS); // 1 time sample every trig. + } + + MODIFY_REG(hadc->Instance->CR2,ADC_CR2_OVSR_MASK,hadc->Init.Oversampling.Ratio<Instance->CR2,ADC_CR2_OVSS_MASK,hadc->Init.Oversampling.RightBitShift<Instance->CR2,ADC_CR2_OVSE); // Regular channel over sample en. + } + + //ExTrigSel set + MODIFY_REG(hadc->Instance->CR1,ADC_CR1_EXTSEL_MASK,hadc->Init.ExTrigMode.ExTrigSel<Init.JChannelMode) + { + /* Enable the inject channel */ + SET_BIT(hadc->Instance->CR1, ADC_CR1_JEN); + //JExTrigSel set + MODIFY_REG(hadc->Instance->CR1,ADC_CR1_JEXTSEL_MASK,hadc->Init.ExTrigMode.JExTrigSel<Instance->SQR1,ADC_SQR1_L); //Clear the sequence length. + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_DeInit + * Description: DeInit the ADC module + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + /* Check the ADC handle allocation */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + HAL_ADC_MspDeInit(hadc); + + hadc->ChannelNum = 0; + hadc->ConvCpltCallback = NULL; + hadc->InjectedConvCpltCallback = NULL; + hadc->LevelOutOfWindowCallback = NULL; + memset(&hadc->Init, 0, sizeof(hadc->Init)); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_ConfigChannel + * Description: Config the regular channel + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * sConfig : pointer to a ADC_ChannelConfTypeDef structure that contains + * the configuration information for ADC channel + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + if(!IS_ADC_ALL_CHANNEL(sConfig->Channel)) return HAL_ERROR; + if(!IS_ADC_ALL_SMPCLOCK(sConfig->Smp)) return HAL_ERROR; + if(!IS_ADC_ALL_SEQUENCE(sConfig->Sq)) return HAL_ERROR; + + /* Differential mode set*/ + if(hadc->Init.DiffMode) + { + if(sConfig->Channel < 8) + { + SET_BIT(hadc->Instance->DIFF,1<Channel); + SET_BIT(hadc->Instance->SIGN,1<Channel); //If define differential mode ,set as sign resault + } + else + return HAL_ERROR; + } + else if(sConfig->Channel < 8) + { + CLEAR_BIT(hadc->Instance->DIFF,1<Channel); + CLEAR_BIT(hadc->Instance->SIGN,1<Channel); //If define differential mode ,set as unsign resault + } + + if((sConfig->Channel >= 8) && (hadc->Instance->DIFF & (1<<(sConfig->Channel-8)))) return HAL_ERROR; + + if(sConfig->RjMode == 0) + { + if((sConfig->Sq >= 1)&&(sConfig->Sq <= 5)) + MODIFY_REG(hadc->Instance->SQR1,(ADC_CH_MASK << (5*sConfig->Sq )),(sConfig->Channel << (5*sConfig->Sq ))); + else if((sConfig->Sq >= 6)&&(sConfig->Sq <= 11)) + MODIFY_REG(hadc->Instance->SQR2,(ADC_CH_MASK << (5*(sConfig->Sq-6))),(sConfig->Channel << (5*(sConfig->Sq-6)))); + else if((sConfig->Sq >= 12)&&(sConfig->Sq <= 16)) + MODIFY_REG(hadc->Instance->SQR3,(ADC_CH_MASK << (5*(sConfig->Sq-12))),(sConfig->Channel << (5*(sConfig->Sq-12)))); + else + return HAL_ERROR; + } + else + { + /* Inject channel */ + MODIFY_REG(hadc->Instance->JSQR,ADC_CH_MASK,sConfig->Channel); + } + + MODIFY_REG(hadc->Instance->SQR1,ADC_SQR1_L,(hadc->ChannelNum-1)); + + /* Set the SMPR to every register*/ + if(sConfig->Channel <= ADC_CHANNEL_7) + MODIFY_REG(hadc->Instance->SMPR1,(ADC_SMPR_CH_MASK << (4*sConfig->Channel )),(sConfig->Smp << (4*sConfig->Channel ))); + else if((sConfig->Channel >= ADC_CHANNEL_8)&&(sConfig->Channel <= ADC_CHANNEL_15)) + MODIFY_REG(hadc->Instance->SMPR2,(ADC_SMPR_CH_MASK << (4*(sConfig->Channel-8))),(sConfig->Smp << (4*(sConfig->Channel-8)))); + else if((sConfig->Channel >= ADC_CHANNEL_TEMP)&&(sConfig->Channel <= ADC_CHANNEL_EXT3)) + MODIFY_REG(hadc->Instance->SMPR3,(ADC_SMPR_CH_MASK << (4*(sConfig->Channel-16))),(sConfig->Smp << (4*(sConfig->Channel-16)))); + else + return HAL_ERROR; + + if(hadc->Init.ChannelEn & ADC_CHANNEL_TEMP_EN) + { + SET_BIT(hadc->Instance->TSREF,ADC_TSREF_EN_TS);//Enable the temperature sensor + System_Delay(1000); + } + + if(hadc->Init.ChannelEn & (ADC_CHANNEL_VBGR_EN | ADC_CHANNEL_EXT2_EN | ADC_CHANNEL_EXT3_EN)) + { + SET_BIT(hadc->Instance->CR2,ADC_CR2_EN_BUF);//Enable the buffer + if(hadc->Init.ChannelEn & ADC_CHANNEL_VBGR_EN) + SET_BIT(hadc->Instance->TSREF,ADC_TSREF_VREF1P2_EN);//Enable the BGR 1.2v to the buffer channel + else + CLEAR_BIT(hadc->Instance->TSREF,ADC_TSREF_VREF1P2_EN);//Disable the BGR 1.2v to the buffer channel + + System_Delay(1000); + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_AnalogWDGConfig + * Description: Config the analog watchdog + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * AnalogWDGConfig : pointer to a ADC_AnalogWDGConfTypeDef structure that contains + * the configuration information for ADC analog watchdog + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + if(!IS_ADC_ALL_CHANNEL(AnalogWDGConfig->Channel)) return HAL_ERROR; + + if (hadc->Init.AnalogWDGEn) + { + switch(AnalogWDGConfig->WatchdogMode) + { + /* AWDSGL:0; AWDEN:1; JAWDEN:0 */ + case ADC_ANALOGWATCHDOG_RCH_ALL: + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + break; + /* AWDSGL:0; AWDEN:0; JAWDEN:1 */ + case ADC_ANALOGWATCHDOG_JCH_ALL: + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + break; + /* AWDSGL:0; AWDEN:1; JAWDEN:1 */ + case ADC_ANALOGWATCHDOG_RCH_AND_JCH_ALL: + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + break; + /* AWDSGL:1; AWDEN:1; JAWDEN:0 */ + case ADC_ANALOGWATCHDOG_RCH_SINGLE: + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + MODIFY_REG(hadc->Instance->CR1,ADC_CH_MASK,AnalogWDGConfig->Channel); //The regular watchdog channel set + break; + /* AWDSGL:1; AWDEN:0; JAWDEN:1 */ + case ADC_ANALOGWATCHDOG_JCH_SINGLE: + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + MODIFY_REG(hadc->Instance->CR1,(ADC_CH_MASK<<27),AnalogWDGConfig->Channel<<27); //The inject watchdog channel set + break; + /* AWDSGL:1; AWDEN:1; JAWDEN:1 */ + case ADC_ANALOGWATCHDOG_RCH_OR_JCH_SINGLE: + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + MODIFY_REG(hadc->Instance->CR1,ADC_CH_MASK,AnalogWDGConfig->Channel); //The regular watchdog channel set + MODIFY_REG(hadc->Instance->CR1,(ADC_CH_MASK<<27),AnalogWDGConfig->Channel<<27); //The inject watchdog channel set + break; + + /* AWDSGL:x; AWDEN:0; JAWDEN:0 */ + default: /* ADC_ANALOGWATCHDOG_NONE */ + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + break; + } + + /* Configure ADC analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode) + __HAL_ADC_ENABLE_IT(hadc,ADC_IE_AWDIE); + else + __HAL_ADC_DISABLE_IT(hadc,ADC_IE_AWDIE); + } + + if(hadc->Init.DiffMode) + { + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold<<16; + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold<<16; + } + else + { + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; + } + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Start + * Description: Enable and start the ADC convertion + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + /* check the total number of the enabled channels */ + if((READ_BIT(hadc->Instance->SQR1,ADC_SQR1_L)+1) != hadc->ChannelNum) return HAL_ERROR; + + /* Enable the ADC */ + __HAL_ADC_ENABLE(hadc); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Wait ADC ready */ + while(!(hadc->Instance->SR & ADC_SR_ADRDY)); + + if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART); + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Stop + * Description: Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP)); + } + + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Start_IT + * Description: Enable ADC, start conversion of regular group with interruption. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + /* Enable the ADC */ + __HAL_ADC_ENABLE(hadc); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE); + + __HAL_ADC_ENABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE); + + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.OverMode is set to ADC_OVERMODE_DISABLE, only then is + ADC_IE_OVERFIE enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.OverMode == ADC_OVERMODE_DISABLE) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_IE_OVERFIE); + } + + if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART); + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Stop_IT + * Description: Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP)); + } + + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Start_DMA + * Description: Enable ADC, start conversion of regular group and transfer result through DMA. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * : pData : Destination Buffer address. + * : Length : Number of data to be transferred from ADC peripheral to memory. + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + /* Specific case for first call occurrence of this function (DMA transfer */ + /* not activated and ADC disabled), DMA transfer must be activated */ + /* with ADC disabled. */ + if (READ_BIT(hadc->Instance->CR1,ADC_CR1_DMA) == 0UL) + { + if(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_EN)) + { + /* Disable ADC */ + __HAL_ADC_DISABLE(hadc); + } + + /* Enable ADC DMA mode */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_DMA); + } + + /* Enable the ADC peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE); + + /* Start the DMA channel */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + + /* Start ADC group regular conversion */ + if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART); + } + + /* Return function status */ + return tmp_hal_status; +} + +/************************************************************************ + * function : HAL_ADC_Stop_DMA + * Description: Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP)); + } + + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP)); + + /* Disable the DMA channel (in case of DMA in circular mode or stop */ + /* while DMA transfer is on going) */ + HAL_DMA_Abort(hadc->DMA_Handle); + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_OVERFIE); + + /* 2. Disable the ADC peripheral */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ + /* in memory a potential failing status. */ + + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_DMA); + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_GetValue + * Description: ADC retrieve conversion value intended to be used with polling or interruption + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : uint32_t the ADC covert result. + ************************************************************************/ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + return (hadc->Instance->DR); +} + +/************************************************************************ + * function : HAL_ADC_PollForEvent + * Description: Poll for ADC event. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * : EventType: the ADC event type. can be ：ADC_SR_AWD,ADC_SR_OVERF,ADC_SR_EOG,ADC_SR_JEOC,ADC_SR_EOC + * : Timeout : Polling timeout. + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) +{ + __IO uint32_t uiTimeout; + + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + if(!IS_ADC_EVENT_TYPE(EventType)) return HAL_ERROR; + + uiTimeout = Timeout; + /* Check selected event flag */ + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + return HAL_TIMEOUT; + } + } + + if(EventType == ADC_SR_OVERF) + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_OVERF); + if (hadc->Init.OverMode == ADC_OVERMODE_ENABLE) + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVERMODE_ENABLE(Over written) */ + return HAL_ERROR; + } + } + else + { + __HAL_ADC_CLEAR_FLAG(hadc, EventType); + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_InjectedStart_IT + * Description: Enable ADC, start conversion of injected channel with interruption. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC); + + __HAL_ADC_ENABLE_IT(hadc, ADC_IE_JEOCIE); + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.OverMode is set to ADC_OVERMODE_DISABLE, only then is + ADC_IE_OVERFIE enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.OverMode == ADC_OVERMODE_DISABLE) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_IE_OVERFIE); + } + + if(__HAL_ADC_CHECK_TRIG_INJECTED(hadc, ADC_SOFTWARE_START)) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_JSWSTART); + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_InjectedStop_IT + * Description: Stop ADC conversion of injected channel, disable interrution of + * end-of-conversion, disable ADC peripheral. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc) +{ + /* Return function status */ + return (HAL_ADC_Stop_IT(hadc)); +} + +/************************************************************************ + * function : HAL_ADC_InjectedGetValue + * Description: ADC retrieve injected channel conversion value intended to be used with polling or interruption + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : uint32_t the ADC covert result. + ************************************************************************/ +uint32_t HAL_ADC_InjectedGetValue(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + return (hadc->Instance->JDR); +} + +/************************************************************************ + * function : HAL_ADC_Polling + * Description: Polling to get the results of the ADC converter. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * : pData : Destination Buffer address. + * : Length : Number of data to be transferred from ADC peripheral to memory. + * : Timeout : Polling timeout. + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Polling(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length, uint32_t Timeout) +{ + uint32_t tmp_hal_status; + __IO uint32_t uiTimeout; + + if(HAL_ADC_Start(hadc) != HAL_OK) return HAL_ERROR; + if(!pData) return HAL_ERROR; + + hadc->AdcResults = pData; + uiTimeout = Timeout; + + while(Length) + { + tmp_hal_status = hadc->Instance->SR; + if(tmp_hal_status & ADC_SR_EOC) + { + *hadc->AdcResults = hadc->Instance->DR | HAL_ADC_EOC_FLAG; + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOC); + + hadc->AdcResults++; + Length--; + } + if(tmp_hal_status & ADC_SR_JEOC) + { + *hadc->AdcResults = hadc->Instance->JDR | HAL_ADC_JEOC_FLAG; + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC); + hadc->AdcResults++; + Length--; + } + if(tmp_hal_status & ADC_SR_OVERF) + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_OVERF); + } + if(tmp_hal_status & ADC_SR_EOG) + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOG); + break; + } + + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + return HAL_TIMEOUT; + } + } + + HAL_ADC_Stop(hadc); + + return HAL_OK; +} + +/** + * @brief Use the DMA to get the results of the ADC converter. + * @param hadc ADC handle + * @retval HAL status. + */ +/************************************************************************ + * function : HAL_ADC_Dma + * Description: Use the DMA to get the results of the ADC converter. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * : pData : Destination Buffer address. + * : Length : Number of data to be transferred from ADC peripheral to memory. + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Dma(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + + if(!hadc->AdcResults) return HAL_ERROR; + + if(HAL_ADC_Start(hadc) != HAL_OK) return HAL_ERROR; + + if(!pData) return HAL_ERROR; + + hadc->AdcResults = pData; + + tmp_hal_status = HAL_ADC_Start_DMA(hadc,hadc->AdcResults,Length); + + if(tmp_hal_status != HAL_OK) return HAL_ERROR; + + while(!gu32_ITC_Conunt){} + + gu32_ITC_Conunt--; + + if(hadc->Init.ConConvMode == ADC_CONCONVMODE_DISABLE) + HAL_ADC_Stop_DMA(hadc); + + return tmp_hal_status; +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_CAN.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_CAN.c new file mode 100644 index 0000000000..59a2cef1c1 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_CAN.c @@ -0,0 +1,690 @@ +/* + ****************************************************************************** + * @file HAL_Can.c + * @version V1.0.0 + * @date 2020 + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (CAN). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_CAN_OperatingModeRequest +* Description : Select the CAN Operation mode. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : CAN_OperatingMode:CAN Operating Mode. This parameter can be one of @ref CAN_OperatingMode enumeration. +* Output : HAL status +* Author : CWT Date : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_OperatingModeRequest(CAN_HandleTypeDef *hcan, uint8_t CAN_OperatingMode) +{ + HAL_StatusTypeDef status = HAL_ERROR; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + if(!IS_CAN_OPERATING_MODE(CAN_OperatingMode)) return HAL_ERROR; + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + hcan->Instance->MOD |= CAN_OperatingMode_Initialization; // enter Initialization + if ((hcan->Instance->MOD & CAN_MOD_RM) != CAN_OperatingMode_Initialization) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Normal) + { + hcan->Instance->MOD &=~ CAN_OperatingMode_Initialization; //1-->0 enter Normal + if ((hcan->Instance->MOD & CAN_MOD_RM) != CAN_OperatingMode_Normal) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + hcan->Instance->MOD |= CAN_OperatingMode_Sleep; // enter Normal + if ((hcan->Instance->MOD & CAN_MOD_SM) != CAN_OperatingMode_Sleep) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Listen) + { + hcan->Instance->MOD |= CAN_OperatingMode_Listen; // enter Normal + if((hcan->Instance->MOD & CAN_MOD_LOM) != CAN_OperatingMode_Listen) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + } + else + { + status = HAL_ERROR; + } + return status; +} + + +/********************************************************************************* +* Function : HAL_CAN_MspInit +* Description : Initialize the CAN MSP. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2020 +**********************************************************************************/ + +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ + /* For Example */ + + /* Enable CAN clock */ + System_Module_Enable(EN_CAN1); + GPIO_InitTypeDef GPIO_InitStructure; + /* Initialization GPIO */ + /* PA11:Rx */ /* PA12:Tx */ + GPIO_InitStructure.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStructure.Alternate=GPIO_FUNCTION_5; + GPIO_InitStructure.Pull=GPIO_PULLUP; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + +} +/********************************************************************************* +* Function : HAL_CAN_MspDeInit +* Description : CAN MSP De-Initialization +* This function frees the hardware resources used in this example: +* - Disable the Peripheral's clock +* - Revert GPIO configuration to their default state +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + /* Reset CAN clock */ + System_Module_Disable(EN_CAN1); + /* Initialization GPIO */ + /* PA11:Rx */ /* PA12:Tx */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12); + + +} +/********************************************************************************* +* Function : HAL_CAN_Init +* Description : Initializes the CAN peripheral according to the specified parameters in the CAN_HandleTypeDef.. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : HAL status +* Author : CWT Date : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + if(!IS_CAN_MODE(hcan->Init.CAN_Mode)) return HAL_ERROR; + if(!IS_CAN_SJW(hcan->Init.CAN_SJW)) return HAL_ERROR; + if(!IS_CAN_TSEG1(hcan->Init.CAN_TSEG1)) return HAL_ERROR; + if(!IS_CAN_TSEG2(hcan->Init.CAN_TSEG2)) return HAL_ERROR; + if(!IS_CAN_BRP(hcan->Init.CAN_BRP)) return HAL_ERROR; + if(!IS_CAN_SAM(hcan->Init.CAN_SAM)) return HAL_ERROR; + /* Reset the CANx */ + System_Module_Reset(RST_CAN1); + HAL_CAN_MspInit(hcan); + HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Initialization);//enter CAN_OperatingMode_Initialization + hcan->Instance->BTR0=0xff; + hcan->Instance->BTR0=(hcan->Init.CAN_SJW<<6)|(hcan->Init.CAN_BRP); + hcan->Instance->BTR1=(hcan->Init.CAN_SAM<<7)|(hcan->Init.CAN_TSEG2<<4)|(hcan->Init.CAN_TSEG1); + HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Normal);//enter CAN_OperatingMode_Normal + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : HAL status +* Author : CWT Date : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + + HAL_CAN_MspDeInit(hcan); + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MOD, CAN_MOD_RM); + + /* Return function status */ + return HAL_OK; +} +/********************************************************************************* +* Function : HAL_CAN_Transmit +* Description : Initiates the transmission of a message. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : TxMessage : ppointer to a structure which contains CAN Id, CAN + * DLC and CAN data. +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, CanTxRxMsg* TxMessage) +{ + uint8_t i = 0; + uint8_t can_id[4]; + uint32_t frame_header; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ; + if(!IS_CAN_IDTYPE(TxMessage->IDE)) return HAL_ERROR; + if(!IS_CAN_RTR(TxMessage->RTR)) return HAL_ERROR; + if(!IS_CAN_DLC(TxMessage->DLC)) return HAL_ERROR; + /* Set up the DLC */ + frame_header =TxMessage->DLC & 0x0F; // standard data frame + /* Set up the Id */ + if(TxMessage->IDE==CAN_Id_Standard)//Standard ID + { + can_id[0] = TxMessage->StdId >>3; + can_id[1] = (TxMessage->StdId&0x07)<<5; + for(i=0;i<2;i++) + { + hcan->Instance->DF.DATABUF[1+i] = can_id[i]; + } + } + else//Id_Extended + { + can_id[0] = TxMessage->ExtId>>21; + can_id[1] = (TxMessage->ExtId&0x1FE000)>>13; + can_id[2] = (TxMessage->ExtId&0x1FE0)>>5; + can_id[3] = (TxMessage->ExtId&0x1F)<<3; + frame_header |= (CAN_Id_Extended<<7); // extended data frame + for(i=0;i<4;i++) + { + hcan->Instance->DF.DATABUF[1+i] = can_id[i]; + } + } + if(TxMessage->RTR==CAN_RTR_Data)//CAN_RTR_Data + { + frame_header&=~(CAN_RTR_Remote<<6); + for(i=0; iDLC; i++) + { + hcan->Instance->DF.DATABUF[3+(TxMessage->IDE*2)+i] = TxMessage->Data[i]; + } + } + else//CAN_RTR_Remote + { + frame_header|=(CAN_RTR_Remote<<6); + } + hcan->Instance->DF.DATABUF[0]=frame_header; + hcan->Instance->CMR = CAN_CMR_TR; // transfer request + while((hcan->Instance->SR & CAN_SR_TCS)==0x00); //wait for send ok + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_CAN_CancelTransmit +* Description : Cancels a transmit request. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +void HAL_CAN_CancelTransmit(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return ; + /* abort transmission */ + hcan->Instance->CMR |= CAN_CMR_AT; //Abort Transmission +} + +/********************************************************************************* +* Function : HAL_CAN_Receive +* Description : Receives a message. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : RxMessage : pointer to a structure receive message which contains +* CAN Id, CAN DLC, CAN datas . +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ; + + hcan->RxMessage=RxMessage; + + /* Enable the CAN Receive interrupt */ + hcan->Instance->IER |= CAN_IER_RIE; + NVIC_ClearPendingIRQ(CAN1_IRQn); + NVIC_SetPriority(CAN1_IRQn, 5); + NVIC_EnableIRQ(CAN1_IRQn); + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_CAN_Receive +* Description : Receives a message. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : RxMessage : pointer to a structure receive message which contains +* CAN Id, CAN DLC, CAN datas . +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ; + while(!(hcan->Instance->SR & CAN_SR_RBS)); + HAL_CAN_GetRxMessage(hcan, RxMessage); + return HAL_OK; +} + +void HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage) +{ + uint8_t i=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return ; + if(0 == (hcan->Instance->SR & CAN_SR_RBS) ) return; // receive fifo not empty + /* Get the IDE */ + RxMessage->IDE = (uint8_t)(0x80 & hcan->Instance->DF.DATABUF[0])>>7; + /* Get the RTR */ + RxMessage->RTR = (uint8_t)(0x40 & hcan->Instance->DF.DATABUF[0])>>6; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & hcan->Instance->DF.DATABUF[0]; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)(( hcan->Instance->DF.DATABUF[1]<<8) | hcan->Instance->DF.DATABUF[2])>>5;; + for(i=0; iDLC; i++) + { + RxMessage->Data[i] = hcan->Instance->DF.DATABUF[3+i]; + } + } + else + { + RxMessage->ExtId = (uint32_t)(( hcan->Instance->DF.DATABUF[1]<<24) | ( hcan->Instance->DF.DATABUF[2]<<16) | ( hcan->Instance->DF.DATABUF[3]<<8) | (hcan->Instance->DF.DATABUF[4] ))>>3;; + for(i=0; iDLC; i++) + { + RxMessage->Data[i] = hcan->Instance->DF.DATABUF[5+i]; + } + } + /* Release the FIFO */ + hcan->Instance->CMR |= CAN_CMR_RRB; //Release Receive Buffer +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration + * information. + * @retval None. + */ + +/********************************************************************************* +* Function : HAL_CAN_ConfigFilter +* Description : Initializes the CAN peripheral according to the specified parameters in the CAN_FilterInitStruct. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : CAN_FilterInitStruct : pointer to a CAN_FilterInitTypeDef structure that contains the configuration +* information. +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +void HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan,CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Initialization);//enter CAN_OperatingMode_Initialization + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode ==CAN_FilterMode_Dual) /*Dual mode*/ + { + hcan->Instance->MOD &= ~CAN_MOD_AFM; + /*Dual mode ACR set*/ + hcan->Instance->DF.FILTER.ACR[0] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE00000)>>21; /*Dual mode ACR0=ID28...ID21 of ID1*/ + hcan->Instance->DF.FILTER.ACR[1] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE000)>>13; /*Dual mode ACR0=ID20...ID13 of ID1*/ + hcan->Instance->DF.FILTER.ACR[2] = (CAN_FilterInitStruct->CAN_FilterId2&0x1FE00000)>>21; /*Dual mode ACR0=ID28...ID21 of ID2*/ + hcan->Instance->DF.FILTER.ACR[3] = (CAN_FilterInitStruct->CAN_FilterId2&0x1FE000)>>13; /*Dual mode ACR0=ID20...ID13 of ID2*/ + /*Dual mode AMR set*/ + hcan->Instance->DF.FILTER.AMR[0] = (CAN_FilterInitStruct->CAN_FilterMaskId1)>>24; + hcan->Instance->DF.FILTER.AMR[1] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF0000)>>16; + hcan->Instance->DF.FILTER.AMR[2] = (CAN_FilterInitStruct->CAN_FilterMaskId2)>>24; + hcan->Instance->DF.FILTER.AMR[3] = (CAN_FilterInitStruct->CAN_FilterMaskId2&0xFF0000)>>16; + } + else /*Single mode*/ + { + hcan->Instance->MOD |= CAN_MOD_AFM; + /*Single mode ACR set*/ + hcan->Instance->DF.FILTER.ACR[0] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE00000)>>21; /*Single mode ACR0=ID28...ID21*/ + hcan->Instance->DF.FILTER.ACR[1] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE000)>>13; /*Single mode ACR1=ID20...ID13*/ + hcan->Instance->DF.FILTER.ACR[2] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE0)>>5; /*Single mode ACR2=ID12...ID5*/ + hcan->Instance->DF.FILTER.ACR[3] = (CAN_FilterInitStruct->CAN_FilterId1&0x1F)<<3; /*Single mode ACR3=ID4...ID0*/ + /*Single mode AMR set*/ + hcan->Instance->DF.FILTER.AMR[0] = (CAN_FilterInitStruct->CAN_FilterMaskId1)>>24; + hcan->Instance->DF.FILTER.AMR[1] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF0000)>>16; + hcan->Instance->DF.FILTER.AMR[2] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF00)>>8; + hcan->Instance->DF.FILTER.AMR[3] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF); + } + + HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Normal);//enter CAN_OperatingMode_Initialization +} + + +/********************************************************************************* +* Function : HAL_CAN_Sleep +* Description : Enters the sleep mode. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + /* Request Sleep mode */ + hcan->Instance->MOD |= CAN_MOD_SM; //Enter Sleep Mode + + /* Sleep mode status */ + if ((hcan->Instance->MOD & CAN_MOD_SM) == CAN_MOD_SM) + { + /* Sleep mode entered */ + status= HAL_OK; + }else + { + status=HAL_ERROR; + } + /* return sleep mode status */ + return status; +} + +/********************************************************************************* +* Function : HAL_CAN_WakeUp +* Description : Wakes the CAN up. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + /* sleep wake mode */ + hcan->Instance->MOD &=~ CAN_MOD_SM; //Enter Sleep Mode + + /* sleep wake status */ + if ((hcan->Instance->MOD & CAN_MOD_SM)== CAN_MOD_SM) + { + /* sleep wake not entered */ + status= HAL_ERROR; + }else + { + status=HAL_OK; + } + /* return sleep mode status */ + return status; +} + +/********************************************************************************* +* Function : HAL_CAN_GetTransmitErrorCounter +* Description : Returns the CANx Transmit Error Counter(TXERR). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +int8_t HAL_CAN_GetTransmitErrorCounter(CAN_HandleTypeDef *hcan) +{ + uint8_t counter=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Transmit Error Counter(TXERR) */ + counter = (uint8_t)(hcan->Instance->TXERR); + /* Return the CANx Transmit Error Counter(TXERR) */ + return counter; +} + + +/********************************************************************************* +* Function : HAL_CAN_GetReceiveErrorCounter +* Description : Returns the CANx Receive Error Counter(RXERR). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +int8_t HAL_CAN_GetReceiveErrorCounter(CAN_HandleTypeDef *hcan) +{ + uint8_t counter=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Receive Error Counter(RXERR) */ + counter = (uint8_t)(hcan->Instance->RXERR); + /* Return the CANx Receive Error Counter(RXERR) */ + return counter; +} + + +/********************************************************************************* +* Function : HAL_CAN_GetErrorCode +* Description : Returns the CANx's error code (ECC). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : Error_Type:This parameter can be one of the following flags: +* CAN_ErrorType_SegCode +* CAN_ErrorType_Direction +* CAN_ErrorType_ErrCode +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +int8_t HAL_CAN_GetErrorCode(CAN_HandleTypeDef *hcan,uint32_t Error_Type) +{ + uint8_t ErrorCode=0; + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + if(!IS_CAN_ErrorType(Error_Type)) return -1; + /* Get the CANx Error SegCode */ + if(Error_Type==CAN_ErrorType_SegCode) + { + ErrorCode= (uint8_t)(hcan->Instance->ECC & CAN_ErrorType_SegCode); + } + /* Get the CANx Error Direction */ + else if(Error_Type==CAN_ErrorType_Direction) + { + ErrorCode= (uint8_t)((hcan->Instance->ECC & CAN_ErrorType_Direction)>>5); + } + /* Get the CANx Error ErrCode */ + else + { + ErrorCode= (uint8_t)((hcan->Instance->ECC & CAN_ErrorType_ErrCode)>>6); + } + return ErrorCode; +} + +/********************************************************************************* +* Function : HAL_CAN_GetErrorAlarmCounter +* Description : Returns the CANx Error Alarm Counter(EWLR). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +int8_t HAL_CAN_GetErrorAlarmCounter(CAN_HandleTypeDef *hcan) +{ + uint8_t counter=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Error Alarm Counter(EWLR) */ + counter = (uint8_t)(hcan->Instance->EWLR); + /* Return the CANx Error Alarm Counter(EWLR) */ + return counter; +} + +/********************************************************************************* +* Function : HAL_CAN_GetArbitrationErrorPosition +* Description : Returns the CANx Arbitration Error Position(ALC). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +int8_t HAL_CAN_GetArbitrationErrorPosition(CAN_HandleTypeDef *hcan) +{ + uint8_t position=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Arbitration Error Counter(ALC) */ + position = (uint8_t)((hcan->Instance->ALC)+1); + /* Return the CANx Arbitration Error Counter(ALC) */ + return position; +} + + +/********************************************************************************* +* Function : HAL_CAN_GetReceiveFiFoCounter +* Description : Returns the CANx Receive FiFo Counter(RMC). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +int8_t HAL_CAN_GetReceiveFiFoCounter(CAN_HandleTypeDef *hcan) +{ + uint8_t counter=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Receive FiFo Counter(RMC) */ + counter = (uint8_t)(hcan->Instance->RMC); + /* Return the CANx Receive FiFo Counter(RMC) */ + return counter; +} + + +/********************************************************************************* +* Function : HAL_CAN_GetReceiveFiFoAddr +* Description : Returns the CANx Receive FiFo start address(RBSA). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +int8_t HAL_CAN_GetReceiveFiFoAddr(CAN_HandleTypeDef *hcan) +{ + uint8_t addr=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Receive FiFo start address(RBSA) */ + addr = (uint8_t)(hcan->Instance->RBSA); + /* Return the CANx Receive FiFo start address(RBSA) */ + return addr; +} + + +/********************************************************************************* +* Function : HAL_CAN_ReleaseReceiveFIFO +* Description : Releases the Receive FIFO. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +void HAL_CAN_ReleaseReceiveFIFO(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return; + /* Releases the Receive FIFO. */ + hcan->Instance->CMR|=CAN_CMR_RRB; +} + + +/********************************************************************************* +* Function : HAL_CAN_ClearOverload +* Description : Clear Overload +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +void HAL_CAN_ClearOverload(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return; + /* Clear Overload. */ + hcan->Instance->CMR|=CAN_CMR_CDO; +} + + +/********************************************************************************* +* Function : HAL_CAN_SlefReceive +* Description : Slef Receive +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Date : 2021 +**********************************************************************************/ +void HAL_CAN_SelfReceive(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return; + /* Slef Receive. */ + hcan->Instance->CMR|=CAN_CMR_SRR; + while((hcan->Instance->SR & CAN_SR_TCS)==0x00); //wait for send ok +} + +/********************************************************************************* +* Function : HAL_CAN_IRQHandler +* Description : This function handles CAN interrupt request. +* Input : hdma : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Outpu : +* Author : Chris_Kyle Date : 2021 +**********************************************************************************/ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + volatile uint32_t lu32_IR; + lu32_IR = hcan->Instance->IR;//read clear + + if(lu32_IR & CAN_IR_RI) //RI + { + /* CAN ReceiveIT complete callback */ + HAL_CAN_GetRxMessage(hcan, hcan->RxMessage); + hcan->CAN_ReceiveIT_Callback(hcan); + } + if(lu32_IR & CAN_IR_TI) //TI + { + /* CAN TransmitIT complete callback */ + hcan->CAN_TransmitIT_Callback(hcan); + } +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_COMP.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_COMP.c new file mode 100644 index 0000000000..5c26842a45 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_COMP.c @@ -0,0 +1,315 @@ +/* + ****************************************************************************** + * @file HAL_COMP.c + * @version V1.0.0 + * @date 2020 + * @brief COMP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Comparator Peripheral (COMP). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/************************************************************************ + * function : HAL_COMP_MspInit + * Description: Inition the comparator gpio and clock + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + * output : none + ************************************************************************/ +__weak void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + System_Module_Enable(EN_COMP); + + if(hcomp->Init.Comparator == COMP1 ) + { + /* COMP1 GPIO inition VINP:PA5(INP_0)*/ + /* COMP1 GPIO inition VINM:PA4(INM_0)*/ + /* COMP1 GPIO inition VOUT:PA0(FUNCTION_7)*/ + GPIO_Handle.Pin = GPIO_PIN_4 | GPIO_PIN_5; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + + GPIO_Handle.Pin = GPIO_PIN_0; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Alternate = GPIO_FUNCTION_7; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + } + else if(hcomp->Init.Comparator == COMP2 ) + { + /* COMP2 GPIO inition VINP:PB4(INP_1)*/ + /* COMP2 GPIO inition VOUT:PA2(FUNCTION_7)*/ + GPIO_Handle.Pin = GPIO_PIN_4; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_Handle); + + GPIO_Handle.Pin = GPIO_PIN_2; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Alternate = GPIO_FUNCTION_7; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + } +} + +/************************************************************************ + * function : HAL_COMP_MspDeInit + * Description: De-Inition the comparator gpio and clock + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + * output : none + ************************************************************************/ +__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + System_Module_Reset(RST_COMP); + System_Module_Enable(EN_COMP); +} + +/************************************************************************ + * function : HAL_COMP_Init + * Description: Inition the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp) +{ + uint32_t u32RegTemp; + __IO uint32_t *gu32RegCrx; + + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + if(!IS_COMP_ALL_CRV_EN(hcomp->Init.Crv_En)) return HAL_ERROR; + if(!IS_COMP_ALL_CRV_SEL(hcomp->Init.Crv_Sel)) return HAL_ERROR; + if(!IS_COMP_ALL_CRV_CFG(hcomp->Init.Crv_Cfg)) return HAL_ERROR; + if(!IS_COMP_ALL_WINMODE(hcomp->Init.WinMode)) return HAL_ERROR; + if(!IS_COMP_ALL_WINOUT(hcomp->Init.WinOut)) return HAL_ERROR; + if(!IS_COMP_ALL_POLARITY(hcomp->Init.Polarity)) return HAL_ERROR; + if(!IS_COMP_ALL_FLTEN(hcomp->Init.FltEn)) return HAL_ERROR; + if(!IS_COMP_ALL_FLTTIME(hcomp->Init.FltTime)) return HAL_ERROR; + if(!IS_COMP_ALL_BLANKTIME(hcomp->Init.BlankTime)) return HAL_ERROR; + if(!IS_COMP_ALL_BLANKSEL(hcomp->Init.BlankSel)) return HAL_ERROR; + if(!IS_COMP_ALL_INPSEL(hcomp->Init.InPSel)) return HAL_ERROR; + if(!IS_COMP_ALL_INMSEL(hcomp->Init.InMSel)) return HAL_ERROR; + if(!IS_COMP_ALL_HYS(hcomp->Init.HYS)) return HAL_ERROR; + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_COMP_MspInit(hcomp); + + if(hcomp->Init.Comparator == COMP1 ) + gu32RegCrx = &hcomp->Instance->CR1; + else + gu32RegCrx = &hcomp->Instance->CR2; + + //Check if the register is locked + if(READ_BIT(*gu32RegCrx , COMP_CR_LOCK)) + { + System_Module_Reset(RST_COMP); + } + + //Check if the comparetor is enable + if(READ_BIT(*gu32RegCrx , COMP_CR_EN)) + CLEAR_BIT(*gu32RegCrx , COMP_CR_EN); + + u32RegTemp = *gu32RegCrx ; + + u32RegTemp = u32RegTemp | ((hcomp->Init.Crv_Cfg << COMP_CR_CRV_CFG_POS)& COMP_CR_CRV_CFG_MASK) | \ + ((hcomp->Init.Crv_Sel << 24) & COMP_CR_CRV_SEL) | \ + ((hcomp->Init.Crv_En << 23) & COMP_CR_CRV_EN) | \ + ((hcomp->Init.WinMode << 22) & COMP_CR_WINMODE) | \ + ((hcomp->Init.WinOut << 21) & COMP_CR_WINOUT) | \ + ((hcomp->Init.Polarity << 20) & COMP_CR_POLARITY) | \ + ((hcomp->Init.FltEn << 19) & COMP_CR_FLTEN) | \ + ((hcomp->Init.FltTime << COMP_CR_FLTTIME_POS)& COMP_CR_FLTTIME_MASK) | \ + ((hcomp->Init.BlankTime << COMP_CR_BLANKTIME_POS)& COMP_CR_BLANKTIME_MASK) | \ + ((hcomp->Init.BlankSel << COMP_CR_BLANKSEL_POS)& COMP_CR_BLANKSEL_MASK) | \ + ((hcomp->Init.InPSel << COMP_CR_INPSEL_POS)& COMP_CR_INPSEL_MASK) | \ + ((hcomp->Init.InMSel << COMP_CR_INMSEL_POS)& COMP_CR_INMSEL_MASK) | \ + ((hcomp->Init.HYS << COMP_CR_HYS_POS)& COMP_CR_HYS_MASK); + + //Write the COMP_CR register . + WRITE_REG(*gu32RegCrx,u32RegTemp); + + SET_BIT(*gu32RegCrx , COMP_CR_EN); //enable + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_Enable + * Description: Enable the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp) +{ + __IO uint32_t *gu32RegCrx; + + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + + if(hcomp->Init.Comparator == COMP1 ) + gu32RegCrx = &hcomp->Instance->CR1; + else + gu32RegCrx = &hcomp->Instance->CR2; + + SET_BIT(*gu32RegCrx , COMP_CR_EN); //enable + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_DeInit + * Description: Deinit and reset the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp) +{ + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + HAL_COMP_MspDeInit(hcomp); + + memset(&hcomp->Init, 0, sizeof(hcomp->Init)); + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_Disable + * Description: Disable the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp) +{ + __IO uint32_t *gu32RegCrx; + + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + + if(hcomp->Init.Comparator == COMP1 ) + gu32RegCrx = &hcomp->Instance->CR1; + else + gu32RegCrx = &hcomp->Instance->CR2; + + CLEAR_BIT(*gu32RegCrx , COMP_CR_EN); //disable + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_GetOutputLevel + * Description: Get the output level of the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp) +{ + uint32_t u32RegTemp; + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + + u32RegTemp = READ_REG(hcomp->Instance->SR); + + if(hcomp->Init.Comparator == COMP1 ) + { + hcomp->OutputLevel_Org = (u32RegTemp & COMP_SR_VCOUT1_ORG)? 1:0; + hcomp->OutputLevel = (u32RegTemp & COMP_SR_VCOUT1)? 1:0; + } + else + { + hcomp->OutputLevel_Org = (u32RegTemp & COMP_SR_VCOUT2_ORG)? 1:0; + hcomp->OutputLevel = (u32RegTemp & COMP_SR_VCOUT2)? 1:0; + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_Lock + * Description: Lock the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp) +{ + __IO uint32_t *gu32RegCrx; + + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + + if(hcomp->Init.Comparator == COMP1 ) + gu32RegCrx = &hcomp->Instance->CR1; + else + gu32RegCrx = &hcomp->Instance->CR2; + + SET_BIT(*gu32RegCrx , COMP_CR_LOCK); //lock + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_Start + * Description: Start the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) +{ + return(HAL_COMP_Enable(hcomp)); +} + + +/************************************************************************ + * function : HAL_COMP_Stop + * Description: Stop the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) +{ + return(HAL_COMP_Disable(hcomp)); +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_CRC.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_CRC.c new file mode 100644 index 0000000000..1041447488 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_CRC.c @@ -0,0 +1,54 @@ +/* + ****************************************************************************** + * @file HAL_Crc.c + * @author Firmware Team + * @version V1.0.0 + * @date 2020 + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_CRC_Init +* Description : Initialize the CRC MSP. +* Input : hcrc: CRC handle. +* Output : +* Author : cl Data : 2021 +**********************************************************************************/ +void HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + System_Module_Enable(EN_CRC); + hcrc->Instance->CTRL = hcrc->Init.PolyRev | hcrc->Init.OutxorRev | hcrc->Init.InitRev | hcrc->Init.RsltRev | + hcrc->Init.DataRev | hcrc->Init.PolyLen | hcrc->Init.DataLen; + + hcrc->Instance->INIT = hcrc->Init.InitData; + hcrc->Instance->OUTXOR = hcrc->Init.OutXorData; + hcrc->Instance->POLY = hcrc->Init.PolyData; +} + +/********************************************************************************* +* Function : HAL_CRC_Calculate +* Description : Calculate the crc calue of input data. +* Input : hcrc: CRC handle. +* Output : CRC value +* Author : cl Data : 2021 +**********************************************************************************/ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc) +{ + HAL_CRC_Init(hcrc); + + while(hcrc->CRC_Data_Len--) + { + hcrc->Instance->DATA = *hcrc->CRC_Data_Buff++; + } + + return (hcrc->Instance->DATA); +} + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_DIV.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_DIV.c new file mode 100644 index 0000000000..711aa74ebf --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_DIV.c @@ -0,0 +1,22 @@ +#include "HAL_DIV.h" + +//Computes q = b div c and a = b mod c +//cDigits must be 1, and *c < 0xffffffff +void hardwareNN_Div_q32(UINT32 *q,UINT32 *a,UINT32 *b,UINT32 bDigits,UINT32 *c,UINT32 cDigits) +{ + UINT32 * p; + int i; + + DIV->REMAIN = 0; + DIV->DIVISOR = *c; + for(i = (bDigits-1); i >= 0 ; i -- ) + { + p = (UINT32*) (b + i); + DIV->DIVIDENED = *p; + + while((DIV->STATUS&0x01)!=0x01); + DIV->STATUS = 0x01; + (*(q+i)) = (UINT32)DIV->QUOTIENT; + } + (*a) = DIV->REMAIN; +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_DMA.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_DMA.c new file mode 100644 index 0000000000..e48be23216 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_DMA.c @@ -0,0 +1,424 @@ +/* + ****************************************************************************** + * @file HAL_DMA.c + * @version V1.0.0 + * @date 2020 + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * @ Initialization and de-initialization functions + * @ IO operation functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/**************** Used in cycle mode ****************/ +static DMA_LLI_InitTypeDef Cycle_Channel[DMA_CHANNEL_NUM]; + +/********************************************************************************* +* Function : HAL_DMA_IRQHandler +* Description : This function handles DMA interrupt request. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t lu32_Channel_Index; + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* Channel has been interrupted */ + if (DMA->INT_STATUS & (1 << lu32_Channel_Index)) + { + /* Transfer complete interrupt */ + if (DMA->INT_TC_STATUS & (1 << lu32_Channel_Index)) + { + DMA->INT_TC_CLR |= (1 << lu32_Channel_Index); + + if (NULL != hdma->DMA_ITC_Callback) + { + hdma->DMA_ITC_Callback(); + } + } + + /* Transfer error interrupt */ + if (DMA->INT_ERR_STATUS & (1 << lu32_Channel_Index)) + { + DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index); + + if (NULL != hdma->DMA_IE_Callback) + { + hdma->DMA_IE_Callback(); + } + } + } +} + +/********************************************************************************* +* Function : HAL_DMA_Init +* Description : DMA initial with parameters. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; + if (!IS_DMA_DATA_FLOW(hdma->Init.Data_Flow)) return HAL_ERROR; + if (!IS_DMA_REQUEST_ID(hdma->Init.Request_ID)) return HAL_ERROR; + if (!IS_DMA_SRC_WIDTH(hdma->Init.Source_Width)) return HAL_ERROR; + if (!IS_DMA_DST_WIDTH(hdma->Init.Desination_Width)) return HAL_ERROR; +#endif + + /* Enable DMA Module */ + System_Module_Enable(EN_DMA); + + /* Enable External Interrupt */ + NVIC_ClearPendingIRQ(DMA_IRQn); + NVIC_EnableIRQ(DMA_IRQn); + + /* Default Little-Endian、Enable DMA */ + DMA->CONFIG = DMA_CONFIG_EN; + + /* Clear Channel Config */ + hdma->Instance->CONFIG = 0x00000000; + + if (hdma->Init.Data_Flow == DMA_DATA_FLOW_M2P) + { + hdma->Init.Request_ID <<= DMA_CHANNEL_CONFIG_DEST_PERIPH_POS; + } + else if (hdma->Init.Data_Flow == DMA_DATA_FLOW_P2M) + { + hdma->Init.Request_ID <<= DMA_CHANNEL_CONFIG_SRC_PERIPH_POS; + } + + hdma->Instance->CONFIG = hdma->Init.Data_Flow | hdma->Init.Request_ID; + + /* Config Channel Control */ + + hdma->Instance->CTRL = DMA_CHANNEL_CTRL_ITC; + + /* Source or Desination address increase */ + hdma->Instance->CTRL |= (hdma->Init.Desination_Inc | hdma->Init.Source_Inc); + /* Source or Desination date width */ + hdma->Instance->CTRL |= (hdma->Init.Desination_Width | hdma->Init.Source_Width); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_DeInit +* Description : DMA De-initial with parameters. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; + if (!IS_DMA_DATA_FLOW(hdma->Init.Data_Flow)) return HAL_ERROR; + if (!IS_DMA_REQUEST_ID(hdma->Init.Request_ID)) return HAL_ERROR; + if (!IS_DMA_SRC_WIDTH(hdma->Init.Source_Width)) return HAL_ERROR; + if (!IS_DMA_DST_WIDTH(hdma->Init.Desination_Width)) return HAL_ERROR; +#endif + + /* Reset DMA Module */ + System_Module_Reset(RST_DMA); + + /* Disable DMA Module */ + System_Module_Disable(EN_DMA); + + /* Disable Interrupt */ + NVIC_ClearPendingIRQ(DMA_IRQn); + NVIC_DisableIRQ(DMA_IRQn); + + hdma->DMA_IE_Callback = NULL; + hdma->DMA_ITC_Callback = NULL; + + memset(&hdma->Init, 0, sizeof(hdma->Init)); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_NormalMode_Start +* Description : DMA transfer start. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_NormalMode_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + if (fu32_Size > 0xFFF) + { + return HAL_ERROR; + } + + /* Set source address and desination address */ + hdma->Instance->SRC_ADDR = fu32_SrcAddr; + hdma->Instance->DEST_ADDR = fu32_DstAddr; + + /* Set Transfer Size */ + hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* DMA Channel Enable */ + hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_EN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_NormalMode_Start_IT +* Description : DMA transfer start with interrupt. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_NormalMode_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + /* Set source address and desination address */ + hdma->Instance->SRC_ADDR = fu32_SrcAddr; + hdma->Instance->DEST_ADDR = fu32_DstAddr; + + /* Set Transfer Size and enable LLI interrupt */ + hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; +// hdma->Instance->CTRL &=~(1<<31); + /* DMA Channel Enable and enable transfer error interrupt and transfer complete interrupt*/ + hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_ITC | DMA_CHANNEL_CONFIG_IE | DMA_CHANNEL_CONFIG_EN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_CycleMode_Start +* Description : DMA Cycle transfer start. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_CycleMode_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ + uint32_t lu32_Channel_Index; + +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* Set source address and desination address */ + hdma->Instance->SRC_ADDR = fu32_SrcAddr; + hdma->Instance->DEST_ADDR = fu32_DstAddr; + + /* Set Next Link */ + hdma->Instance->LLI = (uint32_t)&Cycle_Channel[lu32_Channel_Index]; + + /* Set Transfer Size */ + hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* The list point to oneself */ + Cycle_Channel[lu32_Channel_Index].SrcAddr = fu32_SrcAddr; + Cycle_Channel[lu32_Channel_Index].DstAddr = fu32_DstAddr; + Cycle_Channel[lu32_Channel_Index].Next = &Cycle_Channel[lu32_Channel_Index]; + Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* DMA Channel Enable */ + hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_EN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_CycleMode_Start_IT +* Description : DMA Cycle transfer start with interrupt. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_CycleMode_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ + uint32_t lu32_Channel_Index; + +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* Set source address and desination address */ + hdma->Instance->SRC_ADDR = fu32_SrcAddr; + hdma->Instance->DEST_ADDR = fu32_DstAddr; + + /* Set Next Link */ + hdma->Instance->LLI = (uint32_t)&Cycle_Channel[lu32_Channel_Index]; + + /* Set Transfer Size */ + hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* The list point to oneself */ + Cycle_Channel[lu32_Channel_Index].SrcAddr = fu32_SrcAddr; + Cycle_Channel[lu32_Channel_Index].DstAddr = fu32_DstAddr; + Cycle_Channel[lu32_Channel_Index].Next = &Cycle_Channel[lu32_Channel_Index]; + Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* DMA Channel Enable and enable transfer error interrupt and transfer complete interrupt*/ + hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_ITC | DMA_CHANNEL_CONFIG_IE | DMA_CHANNEL_CONFIG_EN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_Start +* Description : DMA transfer start. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ + /* Check DMA Parameter */ + if (!IS_DMA_MODE(hdma->Init.Mode)) return HAL_ERROR; + + if (hdma->Init.Mode == DMA_NORMAL) + { + return HAL_DMA_NormalMode_Start(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size); + } + else + { + return HAL_DMA_CycleMode_Start(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size); + } +} + +/********************************************************************************* +* Function : HAL_DMA_Start_IT +* Description : DMA transfer start with interrupt. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ + /* Check DMA Parameter */ + if (!IS_DMA_MODE(hdma->Init.Mode)) return HAL_ERROR; + + if (hdma->Init.Mode == DMA_NORMAL) + { + return HAL_DMA_NormalMode_Start_IT(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size); + } + else + { + return HAL_DMA_CycleMode_Start_IT(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size); + } +} + +/********************************************************************************* +* Function : HAL_DMA_Abort +* Description : Abort the DMA Transfer +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + uint32_t lu32_Channel_Index; + +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* DMA Channel Disable */ + hdma->Instance->CONFIG &= ~(1 << 0); + + /* Clear TC ERR Falg */ + DMA->INT_TC_CLR |= (1 << lu32_Channel_Index); + DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_GetState +* Description : Returns the DMA state.. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Data : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + uint32_t lu32_Channel_Index; + HAL_StatusTypeDef States = HAL_ERROR; + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* Transfer complete interrupt */ + if (DMA->RAW_INT_TC_STATUS & (1 << lu32_Channel_Index)) + { + DMA->INT_TC_CLR |= (1 << lu32_Channel_Index); + + States = HAL_OK; + } + + /* Transfer error interrupt */ + if (DMA->RAW_INT_ERR_STATUS & (1 << lu32_Channel_Index)) + { + DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index); + + States = HAL_ERROR; + } + + return States; +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_EFLASH.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_EFLASH.c new file mode 100644 index 0000000000..463ab7353a --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_EFLASH.c @@ -0,0 +1,77 @@ +/* + ****************************************************************************** + * @file HAL_EFlash.c + * @version V1.0.0 + * @date 2020 + * @brief EFlash HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * @ Program operations functions + * @ Erase operations functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_EFlash_Init +* Description : Configure eflash parameter as system clock +* Input : system clock frequency +* Output : None +* Author : Chris_Kyle +**********************************************************************************/ +void HAL_EFlash_Init(uint32_t fu32_freq) +{ + HAL_EFlash_Init_Para(fu32_freq); +} + +/* +* Function : HAL_EFlash_Erase_Page +* Description : Erase a Page, TERASE has been configured in System_Clock_Init() +* Input : +* Outpu : false: FAIL + true: SUCCESS +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +bool HAL_EFlash_ErasePage(uint32_t fu32_Addr) +{ + EFC->CTRL |= EFC_CTRL_PAGE_ERASE_MODE; + + EFC->SEC = 0x55AAAA55; + + *((volatile uint32_t *)fu32_Addr) = 0; + + while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY)); + + EFC->CTRL &= ~EFC_CTRL_PAGE_ERASE_MODE; + + return true; +} + +/********************************************************************************* +* Function : HAL_EFlash_Programe +* Description : Program a word, TPROG has been configured in System_Clock_Init() +* Input : +* Outpu : false: FAIL + true: SUCCESS +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data) +{ + if (fu32_Addr % 4) + { + return false; + } + + EFC->CTRL |= EFC_CTRL_PROGRAM_MODE; + + EFC->SEC = 0x55AAAA55; + + *((volatile uint32_t *)fu32_Addr) = fu32_Data; + + while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY)); + + EFC->CTRL &= ~EFC_CTRL_PROGRAM_MODE; + + return true; +} + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_EXTI.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_EXTI.c new file mode 100644 index 0000000000..2a0083002d --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_EXTI.c @@ -0,0 +1,184 @@ +/* + ****************************************************************************** + * @file HAL_EXTI.c + * @version V1.0.0 + * @date 2020 + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization functions + * + IO operation functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_EXTI_IRQHandler +* Description : Handle EXTI interrupt request. +* Input : huart: EXTI handle. +* Output : +* Author : Chris_Kyle Data : 2020�� +**********************************************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + if (EXTI->PDR & hexti->u32_Line) + { + EXTI->PDR = hexti->u32_Line; + } +} + +/********************************************************************************* +* Function : HAL_EXTI_SetConfigLine +* Description : +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t lu32_IndexLine; + +#if (USE_FULL_ASSERT == 1) + if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return HAL_ERROR; + if (!IS_EXTI_MODE(hexti->u32_Mode)) return HAL_ERROR; + if (!IS_EXTI_TRIGGER(hexti->u32_Trigger)) return HAL_ERROR; + + /* Line0 ~ 15 trigger from GPIO */ + if (!(hexti->u32_Line >> 16)) + { + if (!IS_EXTI_GPIOSEL(hexti->u32_GPIOSel)) return HAL_ERROR; + } +#endif + + lu32_IndexLine = hexti->u32_Line; + + /* Interrupt Mode */ + if (hexti->u32_Mode == EXTI_MODE_INTERRUPT) + { + EXTI->IENR |= lu32_IndexLine; + EXTI->EENR &= ~lu32_IndexLine; + + NVIC_ClearPendingIRQ(EXTI_IRQn); + NVIC_EnableIRQ(EXTI_IRQn); + } + /* Event Mode */ + else if (hexti->u32_Mode == EXTI_MODE_EVENT) + { + EXTI->EENR |= lu32_IndexLine; + EXTI->IENR &= ~lu32_IndexLine; + } + + + if (hexti->u32_Trigger == EXTI_TRIGGER_RISING) + { + EXTI->RTENR |= lu32_IndexLine; + EXTI->FTENR &= ~lu32_IndexLine; + } + else if (hexti->u32_Trigger == EXTI_TRIGGER_FALLING) + { + EXTI->FTENR |= lu32_IndexLine; + EXTI->RTENR &= ~lu32_IndexLine; + } + else + { + EXTI->FTENR |= lu32_IndexLine; + EXTI->RTENR |= lu32_IndexLine; + } + + /* Line0 ~ 15 trigger from GPIO */ + if (!(hexti->u32_Line >> 16)) + { + lu32_IndexLine = 0; + + while(hexti->u32_Line >> lu32_IndexLine != 0x01) + { + lu32_IndexLine++; + } + + /* Line0 ~ 7 */ + if (lu32_IndexLine < 8) + { + EXTI->EXTICR1 = (EXTI->EXTICR1 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4); + } + /* Line8 ~ 15 */ + else + { + lu32_IndexLine -= 8; + + EXTI->EXTICR2 = (EXTI->EXTICR2 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4); + } + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_EXTI_SoftTrigger +* Description : Software trigger EXTI +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return; +#endif + + /* Set pending BIT */ + EXTI->SWIER |= hexti->u32_Line; +} + +/********************************************************************************* +* Function : HAL_EXTI_GetPending +* Description : Get interrupt pending bit of a dedicated line. +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return HAL_ERROR; +#endif + + if (hexti->u32_Line & EXTI->PDR) + { + return true; + } + else + { + return false; + } +} + +/********************************************************************************* +* Function : HAL_EXTI_ClearPending +* Description : Clear interrupt pending bit of a dedicated line. +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return; +#endif + + /* Clear pending status */ + EXTI->PDR |= hexti->u32_Line; +} + +/********************************************************************************* +* Function : HAL_EXTI_ClearAllPending +* Description : Clear all interrupt pending bit. +* Input : +* Outpu : +* Author : xwl Data : 2021年 +**********************************************************************************/ +void HAL_EXTI_ClearAllPending(void) +{ + /* Clear pending status */ + EXTI->PDR |= EXTI_LINE_MASK; +} + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_GPIO.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_GPIO.c new file mode 100644 index 0000000000..47310154b3 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_GPIO.c @@ -0,0 +1,621 @@ +/* + ****************************************************************************** + * @file HAL_GPIO.c + * @version V1.0.0 + * @date 2020 + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * @ Initialization functions + * @ IO operation functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_GPIO_IRQHandler +* Description : GPIO interrupt Handler +* Input : +* Outpu : +* Author : Chris_Kyle Date : 2020年 +**********************************************************************************/ +void HAL_GPIO_IRQHandler(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin) +{ + GPIO_TypeDef *GPIOx; + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + }break; + + default: break; + } + + if (fe_GPIO == GPIOB || fe_GPIO == GPIOD ) + { + fu32_GPIO_Pin <<= 16; + } + + if (GPIOx->RIS & fu32_GPIO_Pin) + { + GPIOx->IC = fu32_GPIO_Pin; + + /* user can call your application process function here */ + /* ...... */ + } +} + +/********************************************************************************* +* Function : HAL_GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init +* Input : fe_GPIO: to select the GPIO peripheral. +* Input : GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + the configuration information for the specified GPIO peripheral. +* Outpu : +* Author : Chris_Kyle Date : 2020年 +**********************************************************************************/ +void HAL_GPIO_Init(enum_GPIOx_t fe_GPIO, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t lu32_Position = 0; + uint32_t lu32_Current_Pin; + uint32_t lu32_Position_Mask; + + volatile uint32_t *lu32_SEL1 = NULL; // 指向 -> 管脚复用寄存器1 + volatile uint32_t *lu32_SEL2 = NULL; // 指向 -> 管脚复用寄存器2 + volatile uint32_t *lu32_PollUP = NULL; // 指向 -> 上拉选择寄存器 + volatile uint32_t *lu32_PollDown = NULL; // 指向 -> 下拉选择寄存器 + volatile uint32_t *lu32_ODEnable = NULL; // 指向 -> 开漏使能寄存器 + volatile uint32_t *lu32_ADS = NULL; // 指向 -> 数字、模拟选择寄存器 + + GPIO_TypeDef *GPIOx; + +#if (USE_FULL_ASSERT == 1) + /* Check the parameters */ + if (!IS_GPIO_ALL_INSTANCE(fe_GPIO)) return; + if (!IS_GPIO_PIN(GPIO_Init->Pin)) return; + if (!IS_GPIO_MODE(GPIO_Init->Mode)) return; + if (!IS_GPIO_PULL(GPIO_Init->Pull)) return; +#endif + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + + System_Module_Enable(EN_GPIOAB); + + lu32_PollUP = &(SCU->PABPUR); + lu32_PollDown = &(SCU->PABPDR); + lu32_ODEnable = &(SCU->PABODR); + lu32_ADS = &(SCU->PABADS); + + if (fe_GPIO == GPIOB) + { + GPIO_Init->Pin <<= 16; + + lu32_SEL1 = &(SCU->PBSEL1); + lu32_SEL2 = &(SCU->PBSEL2); + } + else + { + lu32_SEL1 = &(SCU->PASEL1); + lu32_SEL2 = &(SCU->PASEL2); + } + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + + System_Module_Enable(EN_GPIOCD); + + lu32_PollUP = &(SCU->PCDPUR); + lu32_PollDown = &(SCU->PCDPDR); + lu32_ODEnable = &(SCU->PCDODR); + lu32_ADS = &(SCU->PCDADS); + + if (fe_GPIO == GPIOD) + { + GPIO_Init->Pin <<= 16; + + lu32_SEL1 = &(SCU->PDSEL1); + + } + else + { + lu32_SEL1 = &(SCU->PCSEL1); + lu32_SEL2 = &(SCU->PCSEL2); + } + }break; + + default: break; + } + + /* Configure Select pins */ + while ((GPIO_Init->Pin) >> lu32_Position != 0) + { + /* Get current pin position */ + lu32_Current_Pin = (GPIO_Init->Pin) & (1uL << lu32_Position); + + if (lu32_Current_Pin) + { + switch (GPIO_Init->Mode) + { + /* GPIO IN Function */ + case GPIO_MODE_INPUT: + { + GPIOx->DIR &= ~lu32_Current_Pin; + }break; + + /* GPIO OUT Function */ + case GPIO_MODE_OUTPUT_PP: + case GPIO_MODE_OUTPUT_OD: + { + GPIOx->DIR |= lu32_Current_Pin; + }break; + + /* Alternate Function */ + case GPIO_MODE_AF_PP: + case GPIO_MODE_AF_OD: + { + /* Get Position Mask */ + if (lu32_Position < 16) + { /* GOIOA、GPIOC、GPIOE */ + lu32_Position_Mask = lu32_Position; + } + else + { /* GPIOB、GPIOD、GPIOF */ + lu32_Position_Mask = lu32_Position - 16; + } + + /* SET GPIO Function */ + if (lu32_Position_Mask < 8) + { + *lu32_SEL1 = (*lu32_SEL1 & ~(0xF << (lu32_Position_Mask * 4))) | (GPIO_Init->Alternate << (lu32_Position_Mask * 4)); + } + else + { + *lu32_SEL2 = (*lu32_SEL2 & ~(0xF << ((lu32_Position_Mask - 8) * 4))) | (GPIO_Init->Alternate << ((lu32_Position_Mask - 8) * 4)); + } + }break; + + /* GPIO INT Function */ + case GPIO_MODE_IT_RISING: + case GPIO_MODE_IT_FALLING: + case GPIO_MODE_IT_RISING_FALLING: + case GPIO_MODE_IT_HIGH_LEVEL: + case GPIO_MODE_IT_LOW_LEVEL: + { + /* Set direction Input、Enable INT */ + GPIOx->DIR &= ~lu32_Current_Pin; + GPIOx->IEN |= lu32_Current_Pin; + + /* Single edge */ + if (GPIO_Init->Mode == GPIO_MODE_IT_RISING || GPIO_Init->Mode == GPIO_MODE_IT_FALLING) + { + /* edge trigger */ + GPIOx->IS &= ~lu32_Current_Pin; + /* Single trigger */ + GPIOx->IBE &= ~lu32_Current_Pin; + + if (GPIO_Init->Mode == GPIO_MODE_IT_RISING) + { + GPIOx->IEV |= lu32_Current_Pin; + } + else + { + GPIOx->IEV &= ~lu32_Current_Pin; + } + } + + /* Double edge */ + if (GPIO_Init->Mode == GPIO_MODE_IT_RISING_FALLING) + { + /* edge trigger */ + GPIOx->IS &= ~lu32_Current_Pin; + /* Double trigger */ + GPIOx->IBE |= lu32_Current_Pin; + } + + /* LEVEL trigger */ + if (GPIO_Init->Mode == GPIO_MODE_IT_HIGH_LEVEL || GPIO_Init->Mode == GPIO_MODE_IT_LOW_LEVEL) + { + /* LEVEL trigger */ + GPIOx->IS |= lu32_Current_Pin; + + if (GPIO_Init->Mode == GPIO_MODE_IT_HIGH_LEVEL) + { + GPIOx->IEV |= lu32_Current_Pin; + } + else + { + GPIOx->IEV &= ~lu32_Current_Pin; + } + } + }break; + + default: break; + } + + /* Set Pull UP or DOWN or NO */ + if (GPIO_Init->Pull == GPIO_NOPULL) + { + *lu32_PollUP &= ~lu32_Current_Pin; + *lu32_PollDown &= ~lu32_Current_Pin; + } + else if (GPIO_Init->Pull == GPIO_PULLUP) + { + *lu32_PollUP |= lu32_Current_Pin; + *lu32_PollDown &= ~lu32_Current_Pin; + } + else if (GPIO_Init->Pull == GPIO_PULLDOWN) + { + *lu32_PollUP &= ~lu32_Current_Pin; + *lu32_PollDown |= lu32_Current_Pin; + } + + /* Set Open Drain Mode */ + if (GPIO_Init->Mode & GPIO_MODE_OD_MASK) + { + *lu32_ODEnable |= lu32_Current_Pin; + } + else + { + *lu32_ODEnable &= ~lu32_Current_Pin; + } + + /* GPIO Function */ + if (GPIO_Init->Mode & GPIO_MODE_IO_MASK) + { + /* Get Position Mask */ + if (lu32_Position < 16) + { /* GOIOA、GPIOC、GPIOE */ + lu32_Position_Mask = lu32_Position; + } + else + { /* GPIOB、GPIOD、GPIOF */ + lu32_Position_Mask = lu32_Position - 16; + } + + /* SET GPIO Function */ + if (lu32_Position_Mask < 8) + { + *lu32_SEL1 = (*lu32_SEL1 & ~(0xF << (lu32_Position_Mask * 4))) | (GPIO_FUNCTION_0 << (lu32_Position_Mask * 4)); + } + else + { + *lu32_SEL2 = (*lu32_SEL2 & ~(0xF << ((lu32_Position_Mask - 8) * 4))) | (GPIO_FUNCTION_0 << ((lu32_Position_Mask - 8) * 4)); + } + } + + /* SET Digital or Analog */ + if (GPIO_Init->Mode == GPIO_MODE_ANALOG) + { + *lu32_ADS |= lu32_Current_Pin; + } + else + { + *lu32_ADS &= ~lu32_Current_Pin; + } + } + + lu32_Position++; + } +} + +/********************************************************************************* +* Function : HAL_GPIO_DeInit +* Description : De-initializes the GPIOx peripheral registers to their default reset values. +* Input : fe_GPIO：to select the GPIO peripheral. +* Input : fu32_Pin：specifies the port bit to be written. + This parameter can be one of GPIO_PIN_x where x can be (0..15). +* Outpu : +* Author : Chris_Kyle Date : 2020 +**********************************************************************************/ +void HAL_GPIO_DeInit(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin) +{ + uint32_t lu32_Position = 0; + uint32_t lu32_Current_Pin; + uint32_t lu32_Position_Mask; + + volatile uint32_t *lu32_SEL1 = NULL; // 指向 -> 管脚复用寄存器1 + volatile uint32_t *lu32_SEL2 = NULL; // 指向 -> 管脚复用寄存器2 + volatile uint32_t *lu32_PollUP = NULL; // 指向 -> 上拉选择寄存器 + volatile uint32_t *lu32_PollDown = NULL; // 指向 -> 下拉选择寄存器 + volatile uint32_t *lu32_ODEnable = NULL; // 指向 -> 开漏使能寄存器 + volatile uint32_t *lu32_ADS = NULL; // 指向 -> 数字、模拟选择寄存器 + + GPIO_TypeDef *GPIOx; + +#if (USE_FULL_ASSERT == 1) + /* Check the parameters */ + if (!IS_GPIO_ALL_INSTANCE(fe_GPIO)) return; + if (!IS_GPIO_PIN(fu32_Pin)) return; +#endif + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + + System_Module_Enable(EN_GPIOAB); + + lu32_PollUP = &(SCU->PABPUR); + lu32_PollDown = &(SCU->PABPDR); + lu32_ODEnable = &(SCU->PABODR); + lu32_ADS = &(SCU->PABADS); + + if (fe_GPIO == GPIOB) + { + fu32_Pin <<= 16; + + lu32_SEL1 = &(SCU->PBSEL1); + lu32_SEL2 = &(SCU->PBSEL2); + } + else + { + lu32_SEL1 = &(SCU->PASEL1); + lu32_SEL2 = &(SCU->PASEL2); + } + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + + System_Module_Enable(EN_GPIOCD); + + lu32_PollUP = &(SCU->PCDPUR); + lu32_PollDown = &(SCU->PCDPDR); + lu32_ODEnable = &(SCU->PCDODR); + lu32_ADS = &(SCU->PCDADS); + + if (fe_GPIO == GPIOD) + { + fu32_Pin <<= 16; + + lu32_SEL1 = &(SCU->PDSEL1); + } + else + { + lu32_SEL1 = &(SCU->PCSEL1); + lu32_SEL2 = &(SCU->PCSEL2); + } + }break; + + default: break; + } + + /* Configure Select pins */ + while (fu32_Pin >> lu32_Position != 0) + { + /* Get current pin position */ + lu32_Current_Pin = fu32_Pin & (1uL << lu32_Position); + + if (lu32_Current_Pin) + { + /* GPIO IN Function */ + GPIOx->DIR &= ~lu32_Current_Pin; + GPIOx->CLR |= lu32_Current_Pin; + + /* Disable Enable INT */ + GPIOx->IEN &= ~lu32_Current_Pin; + + /* Clear trigger config */ + GPIOx->IS &= ~lu32_Current_Pin; + GPIOx->IBE &= ~lu32_Current_Pin; + GPIOx->IEV &= ~lu32_Current_Pin; + + + /* Get Position Mask */ + if (lu32_Position < 16) + { /* GOIOA、GPIOC、GPIOE */ + lu32_Position_Mask = lu32_Position; + } + else + { /* GPIOB、GPIOD、GPIOF */ + lu32_Position_Mask = lu32_Position - 16; + } + + /* SET GPIO Function */ + if (lu32_Position_Mask < 8) + { + *lu32_SEL1 &= ~(0xF << (lu32_Position_Mask * 4)); + } + else + { + *lu32_SEL2 &= ~(0xF << ((lu32_Position_Mask - 8) * 4)); + } + + /* NO Pull */ + *lu32_PollUP &= ~lu32_Current_Pin; + *lu32_PollDown &= ~lu32_Current_Pin; + + /* Not Open Drain */ + *lu32_ODEnable &= ~lu32_Current_Pin; + + /* Analog Mode */ + *lu32_ADS |= lu32_Current_Pin; + } + + lu32_Position++; + } +} + +/********************************************************************************* +* Function : HAL_GPIO_AnalogEnable +* Description : Quickly Configure to analog function +* Input : fe_GPIO：to select the GPIO peripheral. +* Input : fu32_Pin：specifies the port bit to be written. + This parameter can be one of GPIO_PIN_x where x can be (0..15). +* Outpu : +* Author : Chris_Kyle Date : 2020年 +**********************************************************************************/ +void HAL_GPIO_AnalogEnable(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin) +{ + uint32_t lu32_Position = 0; + uint32_t lu32_Current_Pin; + + volatile uint32_t *lp32_ADS = NULL; // 指向 -> 数字、模拟选择寄存器 + +#if (USE_FULL_ASSERT == 1) + /* Check the parameters */ + if (!IS_GPIO_ALL_INSTANCE(fe_GPIO)) return; + if (!IS_GPIO_PIN(fu32_Pin)) return; +#endif + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + System_Module_Enable(EN_GPIOAB); + + lp32_ADS = &(SCU->PABADS); + + if (fe_GPIO == GPIOB) + { + fu32_Pin <<= 16; + } + }break; + + case GPIOC: + case GPIOD: + { + System_Module_Enable(EN_GPIOCD); + + lp32_ADS = &(SCU->PCDADS); + + if (fe_GPIO == GPIOD) + { + fu32_Pin <<= 16; + } + }break; + + + default: break; + } + + /* Configure Select pins */ + while ((fu32_Pin) >> lu32_Position != 0) + { + /* Get current pin position */ + lu32_Current_Pin = (fu32_Pin) & (1uL << lu32_Position); + + if (lu32_Current_Pin) + { + *lp32_ADS |= lu32_Current_Pin; + } + + lu32_Position++; + } +} + +/********************************************************************************* +* Function : HAL_GPIO_WritePin +* Description : Set or clear the selected data port bit. +* Input : +* Outpu : +* Author : Chris_Kyle Date : 2020年 +**********************************************************************************/ +void HAL_GPIO_WritePin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin, enum_PinState_t fe_PinState) +{ + GPIO_TypeDef *GPIOx; + +#if (USE_FULL_ASSERT == 1) + /* Check the parameters */ + if (!IS_GPIO_ALL_INSTANCE(fe_GPIO)) return; + if (!IS_GPIO_PIN(fu32_GPIO_Pin)) return; + if (!IS_GPIO_PIN_ACTION(fe_PinState)) return; +#endif + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + }break; + + default: break; + } + + if (fe_GPIO == GPIOB || fe_GPIO == GPIOD ) + { + fu32_GPIO_Pin <<= 16; + } + + if (GPIO_PIN_SET == fe_PinState) + { + GPIOx->ODATA |= fu32_GPIO_Pin; + } + else + { + GPIOx->ODATA &= ~fu32_GPIO_Pin; + } +} + +/********************************************************************************* +* Function : HAL_GPIO_ReadPin +* Description : Read the specified input port pin. +* Input : +* Outpu : +* Author : Chris_Kyle Date : 2020年 +**********************************************************************************/ +enum_PinState_t HAL_GPIO_ReadPin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin) +{ + GPIO_TypeDef *GPIOx; + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + }break; + + default: break; + } + + if (fe_GPIO == GPIOB || fe_GPIO == GPIOD ) + { + fu32_GPIO_Pin <<= 16; + } + + if (GPIOx->IDATA & fu32_GPIO_Pin) + { + return GPIO_PIN_SET; + } + else + { + return GPIO_PIN_CLEAR; + } +} + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_I2C.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_I2C.c new file mode 100644 index 0000000000..5ff446838c --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_I2C.c @@ -0,0 +1,1139 @@ +/* + ****************************************************************************** + * @file HAL_I2C.c + * @version V1.0.0 + * @date 2020 + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/* Private functions for I2C */ +static HAL_StatusTypeDef I2C_Set_Clock_Speed(I2C_HandleTypeDef *hi2c, uint32_t ClockSpeed); +static HAL_StatusTypeDef I2C_Master_Request_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_Master_Request_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_Check_Device_Ready(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/************************************************************************ + * function : HAL_I2C_IRQHandler + * Description: This function handles I2C interrupt request. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +__weak void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t i; + + /* Slave ADDR1 Interrupt */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1)) + { + /* Clear ADDR1 Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + /* Slave Transmit */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + i = 1; + + /* Wait for transmission End*/ + while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)); + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + if (i >= hi2c->Tx_Size && hi2c->Tx_Size != 0) + { + break; + } + + if (READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)) + { + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + } + + if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE)) + { + hi2c->Instance->DR = hi2c->Tx_Buffer[i++]; + hi2c->Tx_Count++; + } + } + + /* Set Slave machine is DILE */ + hi2c->Slave_TxState = SLAVE_TX_STATE_IDLE; + } + /* Slave Receive */ + else + { + i = 0; + + /* Wait for transmission End*/ + while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)); + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + /* Receive Data */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE)) + { + hi2c->Rx_Buffer[i++] = hi2c->Instance->DR; + + /* Wait for transmission End*/ + while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)); + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + hi2c->Rx_Count++; + + if (hi2c->Rx_Size != 0) + { + if (i >= hi2c->Rx_Size) + { + break; + } + } + } + } + + /* Set Slave machine is DILE */ + hi2c->Slave_RxState = SLAVE_RX_STATE_IDLE; + } + + if (hi2c->Slave_RxState == SLAVE_RX_STATE_IDLE && hi2c->Slave_TxState == SLAVE_TX_STATE_IDLE) + { + /* Disable RX_ADDR1_INT_EN */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN); + } + } + + /* STOP Flag Interrupt */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF)) + { + /* Clear STOPF Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF); + + /* Clear STOPF */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_STOPF_INTEN); + + if (hi2c->I2C_STOPF_Callback != NULL) + { + hi2c->I2C_STOPF_Callback(); + } + } +} + +/************************************************************************ + * function : HAL_I2C_MspInit + * Description: + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + /* I2C1 */ + if (hi2c->Instance == I2C1) + { + /* Enable Clock */ + System_Module_Enable(EN_I2C1); + System_Module_Enable(EN_GPIOAB); + + /* I2C1 SDA PortB Pin7 */ + /* I2C1 SCL PortB Pin6 */ + GPIO_Handle.Pin = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_6; + HAL_GPIO_Init(GPIOB, &GPIO_Handle); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(I2C1_IRQn); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(I2C1_IRQn); + } + /* I2C2 */ + else if (hi2c->Instance == I2C2) + { + } +} + +/************************************************************************ + * function : HAL_I2C_MspDeInit + * Description: + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + + /* I2C1 */ + if (hi2c->Instance == I2C1) + { + /* Disable Clock */ + System_Module_Disable(EN_I2C1); + + /* I2C1 SDA PortB Pin7 */ + /* I2C1 SCL PortB Pin6 */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6 | GPIO_PIN_7); + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(I2C1_IRQn); + + /* Disable External Interrupt */ + NVIC_DisableIRQ(I2C1_IRQn); + } + /* I2C2 */ + else if (hi2c->Instance == I2C2) + { + } +} + +/************************************************************************ + * function : HAL_I2C_Init + * Description: I2c initial with parameters. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + if (!IS_I2C_ALL_MODE(hi2c->Init.I2C_Mode)) return HAL_ERROR; + if (!IS_I2C_CLOCK_SPEED(hi2c->Init.Clock_Speed)) return HAL_ERROR; + if (!IS_I2C_TX_AUTO_EN(hi2c->Init.Tx_Auto_En)) return HAL_ERROR; + if (!IS_I2C_STRETCH_EN(hi2c->Init.No_Stretch_Mode)) return HAL_ERROR; + + /* Disable the selected I2C peripheral */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_MEN); + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + + switch (hi2c->Init.I2C_Mode) + { + /* Master Mode */ + case I2C_MODE_MASTER: + { + /* Set Master Mode */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MASTER); + + /* Set Clock Speed */ + I2C_Set_Clock_Speed(hi2c, hi2c->Init.Clock_Speed); + + /* Set SDA auto change the direction */ + if (hi2c->Init.Tx_Auto_En == TX_AUTO_EN_ENABLE) + SET_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + + /* Enable the selected I2C peripheral */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MEN); + }break; + + /* Slave Mode */ + case I2C_MODE_SLAVE: + { + SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + + /* Set SDA auto change the direction */ + if (hi2c->Init.Tx_Auto_En == TX_AUTO_EN_ENABLE) + SET_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + + /* Set Clock Stretch Mode */ + if (hi2c->Init.No_Stretch_Mode == NO_STRETCH_MODE_NOSTRETCH) + SET_BIT(hi2c->Instance->CR, I2C_CR_NOSTRETCH); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_NOSTRETCH); + + /* Set Address 1 */ + hi2c->Instance->SLAVE_ADDR1 = hi2c->Init.Own_Address; + + /* Enable the selected I2C peripheral */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MEN); + }break; + + default: break; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_DeInit + * Description: I2c De-initial with parameters. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Slave_RxState = SLAVE_RX_STATE_IDLE; + hi2c->Slave_TxState = SLAVE_TX_STATE_IDLE; + + HAL_I2C_MspDeInit(hi2c); + + hi2c->Tx_Size = 0; + hi2c->Rx_Size = 0; + hi2c->Tx_Count = 0; + hi2c->Rx_Count = 0; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Master_Transmit + * Description: Transmits in master mode an amount of data in blocking mode. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * DevAddress : Target device address + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value +************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress, 0) == HAL_OK) + { + for (i = 0; i < hi2c->Tx_Size; i++) + { + /* Wait TXE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TXE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Send Data */ + hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++]; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Master_Receive + * Description: Transmits in master mode an amount of data in blocking mode. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * DevAddress : Target device address + * pData : Pointer to data buffer + * Size : Amount of data to be Receive + * Timeout : Timeout value + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Send Read Access Request */ + if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK) + { + /* Wait Master Transition receiving state */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear TX_RX_FLAG */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + for (i = 0; i < hi2c->Rx_Size - 1; i++) + { + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + } + + /* Prepare for Generate NACK */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate STOP */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Transmit + * Description: Transmits in Slave mode an amount of data in blocking mode. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i = 0; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + /* Match the Address 1 */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RX_ADDR1, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + /* Slave Transmit */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + if (READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)) + { + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + hi2c->Tx_Count++; + } + + if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE)) + { + if (i < hi2c->Tx_Size || hi2c->Tx_Size == 0) + { + hi2c->Instance->DR = hi2c->Tx_Buffer[i++]; + } + } + } + hi2c->Instance->SR = READ_REG(hi2c->Instance->SR); + } + else + { + return HAL_ERROR; + } + + hi2c->Tx_Count--; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Transmit_IT + * Description: Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hi2c->Slave_TxState != SLAVE_TX_STATE_IDLE) + return HAL_ERROR; + + /* Set Slave machine is sending */ + hi2c->Slave_TxState = SLAVE_TX_STATE_SENDING; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + + hi2c->Instance->DR = hi2c->Tx_Buffer[0]; + + hi2c->Tx_Count++; + + /* Clear RX ADDR1 Flag */ + SET_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + /* RX ADDR1 Interrupt Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Receive + * Description: Receive in Slave mode an amount of data in blocking mode. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR;; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Match the Address 1 */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RX_ADDR1, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + /* Slave Receive */ + if (!READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + /* Receive Data */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE)) + { + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + if (hi2c->Rx_Size != 0) + { + if (hi2c->Rx_Count >= hi2c->Rx_Size) + { + break; + } + } + } + } + + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + hi2c->Instance->SR = READ_REG(hi2c->Instance->SR); + } + /* Slave Transmit */ + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Receive_IT + * Description: Receive in slave mode an amount of data in non-blocking mode with Interrupt + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hi2c->Slave_RxState != SLAVE_RX_STATE_IDLE) + return HAL_ERROR; + + /* Set Slave machine is receiving */ + hi2c->Slave_RxState = SLAVE_RX_STATE_RECEIVING; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Clear RX ADDR1 Flag */ + SET_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + /* RX ADDR1 Interrupt Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Receive_DMA + * Description: Receive in slave mode an amount of data in non-blocking mode with DMA + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = Size; + + /* DMA Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_DMA_EN); + + /* Clear STOPF Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF); + /* STOPF Interrupt Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOPF_INTEN); + + HAL_DMA_Start(hi2c->HDMA_Rx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->Rx_Buffer, hi2c->Rx_Size); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Transmit_DMA + * Description: Transmit in slave mode an amount of data in non-blocking mode with DMA + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = Size; + + /* Must Set TXE_SEL In DMA Mode !!! */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + /* DMA Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_DMA_EN); + + HAL_DMA_Start_IT(hi2c->HDMA_Tx, (uint32_t)hi2c->Tx_Buffer, (uint32_t)&hi2c->Instance->DR, hi2c->Tx_Size); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Mem_Write + * Description: Write an amount of data in blocking mode to a specific memory address + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * DevAddress : Target device address + * MemAddress : MemAddress Internal memory address + * MemAddSize : MemAddSize Size of internal memory address + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress,0) == HAL_OK) + { + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send Memory Address MSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + /* Send Memory Address LSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + for (i = 0; i < hi2c->Tx_Size; i++) + { + /* Wait TXE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TXE, RESET, Timeout)!= HAL_OK) return HAL_ERROR; + + /* Send Data */ + hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++]; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + /* Check Device Ready */ + while(I2C_Check_Device_Ready(hi2c, DevAddress, Timeout) != HAL_OK); + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Mem_Read + * Description: Read an amount of data in blocking mode to a specific memory address + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * DevAddress : Target device address + * MemAddress : MemAddress Internal memory address + * MemAddSize : MemAddSize Size of internal memory address + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress,0) == HAL_OK) + { + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send Memory Address MSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + /* Send Memory Address LSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + /* Send Write Read Request */ + if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK) + { + /* Wait Master Transition receiving state */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear TX_RX_FLAG */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); + + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + for (i = 0; i < hi2c->Rx_Size - 1; i++) + { + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + } + + /* Prepare for Generate NACK */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate STOP */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + } + else + { + /* Get NACK */ + return HAL_ERROR; + } + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_GetSlaveRxState + * Description: Get Slave Rx State + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * return : Slave State + ************************************************************************/ +uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Slave_RxState; +} + +/************************************************************************ + * function : HAL_I2C_GetSlaveTxState + * Description: Get Slave Tx State + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * return : Slave State + ************************************************************************/ +uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Slave_TxState; +} + +/************************************************************************ + * function : I2C_Set_Clock_Speed + * Description: Set I2C Clock Speed + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * ClockSpeed: I2C Clock Speed + ************************************************************************/ +static HAL_StatusTypeDef I2C_Set_Clock_Speed(I2C_HandleTypeDef *hi2c, uint32_t ClockSpeed) +{ + uint32_t APB_Clock; + + APB_Clock = System_Get_APBClock(); + + hi2c->Instance->CLK_DIV = APB_Clock / (4 * ClockSpeed) - 1; + + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + __IO uint32_t lu32_Timeout; + /* have no timeout */ + if (Timeout == 0) + { + while (__HAL_I2C_GET_FLAG(hi2c, Flag)==Status); + } + else + { + lu32_Timeout = Timeout * 0xFF; + + while (__HAL_I2C_GET_FLAG(hi2c, Flag)==Status) + { + if (lu32_Timeout-- == 0) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} +/************************************************************************ + * function : I2C_Master_Request_Write + * Description: I2C Write Access Request + * input : hi2c : pointer to a I2C_HandleTypeDef structure + * DevAddress: Device address + * Timeout: Timeout value + ************************************************************************/ +static HAL_StatusTypeDef I2C_Master_Request_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + /* Clear MTF, To Prevent Errors */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress & 0xFE; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + return HAL_OK; + } +} + +/************************************************************************ + * function : I2C_Master_Request_Read + * Description: I2C Read Access Request + * input : hi2c : pointer to a I2C_HandleTypeDef structure + * DevAddress: Device address + * Timeout: Timeout value + ************************************************************************/ +static HAL_StatusTypeDef I2C_Master_Request_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + /* Clear MTF, To Prevent Errors */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress | 0x01; + + /* Wait for transmission End */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + return HAL_OK; + } +} + +/************************************************************************ + * function : I2C_Check_Device_Ready + * Description: Check Device Ready + * input : hi2c : pointer to a I2C_HandleTypeDef structure + * DevAddress: Device address + * Timeout: Timeout value + ************************************************************************/ +static HAL_StatusTypeDef I2C_Check_Device_Ready(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress; + + /* Wait for transmission End */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_OK; + } +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_IWDT.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_IWDT.c new file mode 100644 index 0000000000..5383191db6 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_IWDT.c @@ -0,0 +1,71 @@ +/*********************************************************************** + * Filename : HAL_IWDT.c + * Description : HAL IWDT driver source file + * Author(s) : CWT + * version : V1.0 + * Modify date : 2020-04-17 + ***********************************************************************/ +#include "ACM32Fxx_HAL.h" + + +HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt) +{ + if (hidt == NULL) + { + return HAL_ERROR; + } + + System_Delay(1); + + System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE); + System_Enable_RC32K(); + System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_IWDT, FUNC_ENABLE); + /*Enable IWDT */ + hidt->Instance->CMDR = IWDT_ENABLE_COMMAND; + System_Delay(10); + /*Enable Write */ + hidt->Instance->CMDR = IWDT_WRITE_ENABLE_COMMAND; + System_Delay(10); + + hidt->Instance->PR = hidt->Init.Prescaler; + hidt->Instance->RLR = hidt->Init.Reload; + hidt->Instance->WINR = hidt->Init.Window; + hidt->Instance->WUTR = hidt->Init.Wakeup; + System_Delay(1); + while(hidt->Instance->SR & (0x0F)){}; // wait for configuration done + + if (hidt->Init.Reload > hidt->Init.Wakeup) + { + /*Enable Wake up */ + hidt->Instance->CMDR = IWDT_WAKEUP_ENABLE_COMMAND; + } + + hidt->Instance->CMDR = IWDT_RELOAD_COMMAND; + System_Delay(1); + while(hidt->Instance->SR & (1 << 4)){}; + + return HAL_OK; + +} + +HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt) +{ + hidt->Instance->CMDR = IWDT_RELOAD_COMMAND; + System_Delay(1); + while(hidt->Instance->SR & (1 << 4)){}; //wait for kick watchdog done + + return HAL_OK; +} + + + + + + + + + + + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_LCD.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_LCD.c new file mode 100644 index 0000000000..87364e9c5a --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_LCD.c @@ -0,0 +1,269 @@ +/* + ****************************************************************************** + * @file HAL_LCD.c + * @version V1.0.0 + * @date 2020 + * @brief LCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (LCD). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_LCD_MspInit +* Description : Initialize the LCD MSP. +* Input : hcan : pointer to a LCD structure that contains +* the configuration information for LCD module +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +__weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd) +{ + + /* NOTE : This function only enable lcd clk and config NVIC + Because lcd's SEG and COM is different，so the gpio of lcd need user config self.*/ + + /* Enable LCD clock */ + System_Module_Enable(EN_LCD); + /* Enable the LCD Frame interrupt */ + hlcd->Instance->CR1 |= LCD_CR1_IE; + NVIC_ClearPendingIRQ(LCD_IRQn); + NVIC_SetPriority(LCD_IRQn, 5); + NVIC_EnableIRQ(LCD_IRQn); +} + +/********************************************************************************* +* Function : HAL_LCD_MspDeInit +* Description : DeInitialize the LCD MSP. +* Input : hcan : pointer to a LCD structure that contains +* the configuration information for LCD module +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd) +{ + /* Disable LCD clock */ + System_Module_Disable(EN_LCD); +} +/********************************************************************************* +* Function : HAL_LCD_Init +* Description : Initialize the LCD. +* Input : hcan : pointer to a LCD structure that contains +* the configuration information for LCD module +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) +{ + /* Check the parameters */ + if(!IS_LCD_PERIPH(hlcd->Instance)) return HAL_ERROR; + if(!IS_LCD_DUTY(hlcd->Init.Duty)) return HAL_ERROR; + if(!IS_LCD_BIAS(hlcd->Init.Bias)) return HAL_ERROR; + if(!IS_LCD_Driving_Waveform(hlcd->Init.Driving_Waveform)) return HAL_ERROR; + if(!IS_LCD_BiasSrc(hlcd->Init.BiasSrc)) return HAL_ERROR; + if(!IS_LCD_DisplayMode(hlcd->Init.DisplayMode)) return HAL_ERROR; + + if(!IS_LCD_LCDFrequency(hlcd->Init.LCDFrequency)) return HAL_ERROR; + if(!IS_LCD_BlinkEN(hlcd->Init.BlinkEN)) return HAL_ERROR; + if(!IS_LCD_BlinkFrequency(hlcd->Init.BlinkFrequency)) return HAL_ERROR; + + /* Reset the RST_LCD */ + System_Module_Reset(RST_LCD); + HAL_LCD_MspInit(hlcd); + hlcd->Instance->CR0|=(LCD_CR0_LCDEN|hlcd->Init.LCDFrequency|hlcd->Init.Bias|hlcd->Init.Duty|hlcd->Init.BiasSrc|hlcd->Init.Driving_Waveform); + hlcd->Instance->CR1|=(hlcd->Init.BlinkEN|hlcd->Init.BlinkFrequency|hlcd->Init.DisplayMode); + if(hlcd->Init.Driving_Waveform==LCD_Driving_Waveform_A) + { + hlcd->Instance->CR0&=~(LCD_CR0_WSEL); + } + + if(hlcd->Init.Duty==LCD_DUTY_STATIC) + { + if(!IS_LCD_StaticPower(hlcd->Init.StaticPower)) return HAL_ERROR; + hlcd->Instance->CR0|=hlcd->Init.StaticPower; + } + else + { + hlcd->Instance->CR0&=~(LCD_CR0_STATIC);//当DUTY选择非静态时，该位必须设置为0 + } + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_LCD_DeInit +* Description : DeInitialize the LCD. +* Input : hcan : pointer to a LCD structure that contains +* the configuration information for LCD module +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) +{ + /* Check the parameters */ + if(!IS_LCD_PERIPH(hlcd->Instance)) return HAL_ERROR; + /* Reset the CAN peripheral */ + CLEAR_BIT(hlcd->Instance->CR0, LCD_CR0_LCDEN); + + HAL_LCD_MspDeInit(hlcd); + /* Return function status */ + return HAL_OK; +} +/********************************************************************************* +* Function : HAL_LCD_InResConfig +* Description : Initialize the LCD When LCD BiasSrc is LCD_BiasSrc_InRes_Seg31_35_Normal or LCD_BiasSrc_InRes_Seg31_35_Cap. +* Input : hlcd : pointer to a LCD structure that contains +* the configuration information for LCD module +* LCD_InResInitStruct:LCD_InResInitTypeDef +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_LCD_InResConfig(LCD_HandleTypeDef *hlcd,LCD_InResInitTypeDef* LCD_InResInitStruct) +{ + /* Check the parameters */ + if(!IS_LCD_PERIPH(hlcd->Instance)) return HAL_ERROR; + /* Config when BiasSrc is Inside Resistance Mod */ + if(hlcd->Init.BiasSrc!=LCD_BiasSrc_ExRes_Seg31_35_Cap) + { + /* Check the parameters */ + if(!IS_LCD_BiasRes(LCD_InResInitStruct->BiasRes)) return HAL_ERROR; + if(!IS_LCD_DriveMod(LCD_InResInitStruct->DriveMod)) return HAL_ERROR; + if(!IS_LCD_FastCharge(LCD_InResInitStruct->FastCharge)) return HAL_ERROR; + if(!IS_LCD_Contrast(LCD_InResInitStruct->Contrast)) return HAL_ERROR; + /* Config LCD Contrast and Bias Resistance and DriveMod */ + hlcd->Instance->CR0|=(LCD_InResInitStruct->Contrast); + hlcd->Instance->CR1|=(LCD_InResInitStruct->BiasRes|LCD_InResInitStruct->DriveMod); + + /* Config LCD PONTime when DriveMod is Fast Charge and Fast Charge(FCC) is Enable. */ + if(LCD_InResInitStruct->FastCharge==LCD_FastCharge_Enable && LCD_InResInitStruct->DriveMod==LCD_DriveMod_FC) + { + if(!IS_LCD_PONTime(LCD_InResInitStruct->PONTime)) return HAL_ERROR; + hlcd->Instance->CR1|=(LCD_InResInitStruct->PONTime<<18); + } + } + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_LCD_SegComConfig +* Description : Config the LCD SEG and COM enable/disable. +* Input : hlcd : pointer to a LCD structure that contains +* the configuration information for LCD module +* SegCom:LCD_SegComInitTypeDef +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_LCD_SegComConfig(LCD_HandleTypeDef *hlcd,LCD_SegComInitTypeDef *SegCom) +{ + /* Check the parameters */ + if(!IS_LCD_PERIPH(hlcd->Instance)) return HAL_ERROR; + hlcd->Instance->LCD_POEN0=SegCom->SEG0_31; + hlcd->Instance->LCD_POEN1=SegCom->Stc_SEG32_39_COM0_8.SEG32_39_COM0_8; + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_LCD_Write +* Description : Write LCD RAMx. +* Input : hlcd : pointer to a LCD structure that contains +* the configuration information for LCD module +* LCDRAMIndex:LCD RAM index +* Data:The data you want to write +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t LCDRAMIndex, uint32_t Data) +{ + /* Check the parameters */ + if(!IS_LCD_PERIPH(hlcd->Instance)) return HAL_ERROR; + if(LCDRAMIndex>15) return HAL_ERROR; + /* Wrete Data bytes to LCD RAM register */ + hlcd->Instance->LCD_RAM[LCDRAMIndex]=Data; + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_LCD_Clear +* Description : Clear LCD RAMx. +* Input : hlcd : pointer to a LCD structure that contains +* the configuration information for LCD module +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) +{ + uint8_t LCDRAMIndex=0; + /* Check the parameters */ + if(!IS_LCD_PERIPH(hlcd->Instance)) return HAL_ERROR; + /* Clear the LCD_RAM registers */ + for(LCDRAMIndex = 0; LCDRAMIndex <= 15; LCDRAMIndex++) + { + hlcd->Instance->LCD_RAM[LCDRAMIndex] = 0U; + } + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_LCD_Start_DMA +* Description : Start lcd dma transfer +* Input : hlcd : pointer to a LCD structure that contains +* the configuration information for LCD module +* pData:The data want to transfer +* Length:transfer Size +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_LCD_Start_DMA(LCD_HandleTypeDef *hlcd, uint32_t *pData, uint32_t Length) +{ + + /* Check the parameters */ + if(!IS_LCD_PERIPH(hlcd->Instance)) return HAL_ERROR; + + hlcd->Instance->CR1 |= LCD_CR1_DMAEN; + + if (HAL_DMA_Start_IT(hlcd->DMA_Handle,(uint32_t)pData,(uint32_t)(&hlcd->Instance->LCD_RAM[0]), Length)) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_LCD_Stop_DMA +* Description : Stop lcd dma transfer +* Input : hlcd : pointer to a LCD structure that contains +* the configuration information for LCD module +* pData:The data want to transfer +* Length:transfer Size +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_LCD_Stop_DMA(LCD_HandleTypeDef *hlcd) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + if(!IS_LCD_PERIPH(hlcd->Instance)) return HAL_ERROR; + + hlcd->Instance->CR1 &=~ LCD_CR1_DMAEN; + + status = HAL_DMA_Abort(hlcd->DMA_Handle); + + return status; +} + +/********************************************************************************* +* Function : HAL_LCD_IRQHandler +* Description : HAL_LCD_IRQHandler +* Input : hlcd : pointer to a LCD structure that contains +* the configuration information for LCD module +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +void HAL_LCD_IRQHandler(LCD_HandleTypeDef *hlcd) +{ + hlcd->Instance->INTCLR &=~ (LCD_INTCLR_INTFT); +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_LPUART.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_LPUART.c new file mode 100644 index 0000000000..62e8079a62 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_LPUART.c @@ -0,0 +1,437 @@ +/* + ****************************************************************************** + * @file HAL_LPUART.c + * @version V1.0.0 + * @date 2020 + * @brief LPUART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (LPUART). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_LPUART_IRQHander +* Description : LPUART IRQHander +* Input : +* Outpu : +* Author : CWT Data : 2020年 +**********************************************************************************/ +void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart) +{ + while ( (hlpuart->Instance->SR) & (1U << LPUART_SR_RX_INDEX)) + { + if(hlpuart->rx_read_index != (((hlpuart->rx_write_index) + 1)% (hlpuart->rx_buffer_size) ) ) + { + hlpuart->rx_buffer[hlpuart->rx_write_index] = hlpuart->Instance->RXDR; + hlpuart->rx_write_index = ((hlpuart->rx_write_index + 1)%(hlpuart->rx_buffer_size) ); + } + else + { + hlpuart->Instance->SR = (1U << LPUART_SR_RX_INDEX); // buffer overflow + return; + } + } +} +/************************************************************************ + * function : HAL_UART_Buffer_Init + * Description: uart buffer initiation. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Buffer_Init(LPUART_HandleTypeDef *hlpuart) +{ + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return HAL_ERROR; + } + hlpuart->rx_read_index = 0; + hlpuart->rx_write_index = 0; + hlpuart->tx_busy = 0; + return HAL_OK; +} + +/********************************************************************************** + * function : HAL_LPUART_MSPInit + * Description: UART MCU specific initiation, such as IO share, module clock, ... + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ***************************************************************************************/ + +__weak void HAL_LPUART_MSPInit(LPUART_HandleTypeDef *hlpuart) +{ + GPIO_InitTypeDef gpio_init; + + System_Module_Reset(RST_LPUART); + gpio_init.Pin = GPIO_PIN_2|GPIO_PIN_3; // TX PA2 RX PA3 + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Alternate = GPIO_FUNCTION_6; + HAL_GPIO_Init(GPIOA,&gpio_init); + System_Module_Enable(EN_LPUART); +} + +/********************************************************************************* +* Function : HAL_LPUART_MspDeInit +* Description : LPUART MSP De-Initialization +* This function frees the hardware resources used in this example: +* - Disable the Peripheral's clock +* - Revert GPIO configuration to their default state +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020年 +**********************************************************************************/ +void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart) +{ + /* Initialization GPIO */ + /* // TX PA2 RX PA3 */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3); +} +/********************************************************************************** + * function : HAL_LPUART_Set_Baud_Rate + * Description: set uart module's baud rate. It should be set when UART is disabled. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ***************************************************************************************/ +uint8_t HAL_LPUART_Set_Baud_Rate(LPUART_HandleTypeDef *hlpuart, uint32_t lpuart_clk, uint32_t baud_rate) +{ + uint32_t ibaud, fbaud, rxsamp; + + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return 0; + } + ibaud = 2; + fbaud = 0x952; + rxsamp = 1; + switch(lpuart_clk) + { + case 32000: + case 32768: + switch(baud_rate) + { + case 9600: + ibaud = 2; + fbaud = 0x952; +// ibaud = 2; +// fbaud = 0xA44; + break; + + case 4800: + ibaud = 5; + fbaud = 0xefb; + break; + + case 2400: + ibaud = 12; + fbaud = 0x6db; + break; + + case 1200: + ibaud = 26; + fbaud = 0x492; + break; + default: + ibaud = 2; + fbaud = 0x952; + break; + } + rxsamp = ibaud >> 1; + break; + + default: + switch(baud_rate) + { + case 115200: + ibaud = 16; + fbaud = 0x924; + break; + + case 9600: + ibaud = 203; + fbaud = 0x888; + break; + } + rxsamp = ibaud >> 1; + break; + } + hlpuart->Instance->IBAUD = ibaud | (rxsamp << 8); + hlpuart->Instance->FBAUD = fbaud; + return 1; +} + +/************************************************************************ + * function : HAL_LPUART_Config + * Description: Configure UART module parameters, such as baudrate, parity, + * stop bits, dataword. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ************************************************************************/ +uint8_t HAL_LPUART_Config(LPUART_HandleTypeDef *hlpuart) +{ + volatile uint32_t temp_reg; + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return 0; + } + temp_reg = 1U << 7; // default value + temp_reg |= ((hlpuart->ConfigParam.WordLength << 4) | (hlpuart->ConfigParam.StopBits << 3)); + switch(hlpuart->ConfigParam.Parity) + { + case LPUART_PARITY_NONE: + break; // do nothing + + case LPUART_PARITY_SELECT_ODD: + case LPUART_PARITY_SELECT_EVEN: + temp_reg |= (((hlpuart->ConfigParam.Parity - LPUART_PARITY_SELECT_ODD) << LPUART_EPS_INDEX) | (1 << LPUART_PEN_INDEX)); + break; + + case LPUART_PARITY_SELECT_ONE: + case LPUART_PARITY_SELECT_ZERO: + temp_reg |= (((hlpuart->ConfigParam.Parity - LPUART_PARITY_SELECT_ONE) << LPUART_EPS_INDEX) | (1 << LPUART_SPS_INDEX) | (1 << LPUART_PEN_INDEX) ); + break; + } + hlpuart->Instance->LCR = temp_reg; + return 1; +} + +/********************************************************************************* +* Function : LPUART_Clock_Select +* Description : Select the LPUART clock. +* Input : lpuart_clk_src:Could be LPUART_CLOCK_SOURCE_RC32K LPUART_CLOCK_SOURCE_XTAL LPUART_CLOCK_SOURCE_PLL_DIV +* Outpu : +* Author : CWT Data : 2020年 +**********************************************************************************/ +void LPUART_Clock_Select(uint8_t lpuart_clk_src) +{ + if (0 == lpuart_clk_src) + { + SCU->CCR2 &= (~(BIT13 | BIT14) ); // RC32K + } + else if (1 == lpuart_clk_src) + { + SCU->CCR2 = (SCU->CCR2 & (~(BIT13 | BIT14) )) | (BIT13); // XTAL + } + else + { + SCU->CCR2 = (SCU->CCR2 & (~(BIT11 | BIT12| BIT13 | BIT14) )) | (BIT11 | BIT12 | BIT14); // pclk/32 + } +} +/************************************************************************ + * function : HAL_LPUART_Init + * Description: uart initial with parameters. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart) +{ + uint32_t lpuart_clock; + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return HAL_ERROR;; + } + + HAL_LPUART_Buffer_Init(hlpuart); + /*reset module, configure tx and rx, enable module clock*/ + HAL_LPUART_MSPInit(hlpuart); + + if (LPUART_CLOCK_SOURCE_RC32K == hlpuart->ConfigParam.ClockSrc) + { + lpuart_clock = 32000; + System_Module_Enable(EN_RTC); + System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE); + System_Enable_RC32K(); + LPUART_Clock_Select(0); + } + else if (LPUART_CLOCK_SOURCE_XTAL == hlpuart->ConfigParam.ClockSrc) + { + lpuart_clock = 32768; + System_Module_Enable(EN_RTC); + System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE); + System_Enable_XTAL(); + LPUART_Clock_Select(1); + } + else + { + lpuart_clock = System_Get_APBClock()/32; + LPUART_Clock_Select(2); + } + HAL_LPUART_Set_Baud_Rate(hlpuart, lpuart_clock, hlpuart->ConfigParam.BaudRate); + + HAL_LPUART_Config(hlpuart); + + hlpuart->Instance->SR = LPUART_SR_BITS_ALL; + hlpuart->Instance->IE = (1U << LPUART_IE_RX_INDEX); + hlpuart->Instance->CR = (1U << LPUART_CR_RXE_INDEX) | (1 << LPUART_CR_TXE_INDEX); + hlpuart->Instance->LCR=((hlpuart->StopWakeup.Wakeup_Source<<5)|(hlpuart->StopWakeup.Wakeup_Check<<7)); + hlpuart->Instance->ADDR=(hlpuart->StopWakeup.Wakeup_Addr); + NVIC_ClearPendingIRQ(LPUART_IRQn); + NVIC_EnableIRQ(LPUART_IRQn); + return HAL_OK;; +} +HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart) +{ + /* Check handle */ + if(!IS_LPUART_INSTANCE(hlpuart->Instance)) return HAL_ERROR; + HAL_LPUART_MspDeInit(hlpuart); + /* Disable LPUART clock */ + System_Module_Disable(EN_LPUART); + /* Return function status */ + return HAL_OK; +} +/************************************************************************ + * function : HAL_LPUART_Wait_TX_Done + * Description: wait uart not busy + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Wait_TX_Done(LPUART_HandleTypeDef *hlpuart) +{ + while (0 == (hlpuart->Instance->SR & (1 << LPUART_SR_TX_FINISH_INDEX) ) ) {}; + hlpuart->Instance->SR = (1 << LPUART_SR_TX_FINISH_INDEX); + return HAL_OK; +} + +void HAL_LPUART_Output(LPUART_HandleTypeDef *hlpuart, unsigned char c) +{ + if ((hlpuart->Instance->SR) & (1U << LPUART_SR_TX_EMPTY_INDEX) ) + { + hlpuart->Instance->TXDR = c; + } + + HAL_LPUART_Wait_TX_Done(hlpuart); +} + +/************************************************************************ + * function : uart_send_bytes + * Description: uart send bytes + * input : + * UINT32 uart_index: Serial port number + * UINT8* buff: out buffer + * UINT32 length: buffer length + * return: none + ************************************************************************/ +void HAL_LPUART_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length) +{ + uint32_t i; + for (i = 0; i < length; i++) + { + HAL_LPUART_Output(hlpuart, *buff++); + } +} + +/************************************************************************ + * function : HAL_LPUART_Receive_Bytes_Timeout + * Description: uart receive bytes + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * UINT8* buff: out buffer + * UINT32 length: buffer length + * UINT32 ms: number of ms to delay one byte + * return: received bytes + ************************************************************************/ +uint32_t HAL_LPUART_Receive_Bytes_Timeout(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length, uint32_t ms) +{ + volatile uint32_t i, timeout, count;; + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return 0; + } + timeout = (System_Get_APBClock() >> 13) * ms; + count = timeout; + i = 0; + while(i < length) + { + if((hlpuart->rx_read_index) != (hlpuart->rx_write_index)) + { + rxbuff[i] = hlpuart->rx_buffer[hlpuart->rx_read_index]; + hlpuart->rx_read_index = (((hlpuart->rx_read_index) + 1)%(hlpuart->rx_buffer_size) ); + count = timeout; + i++; + } + else + { + if (0 == count)//timeout + { + break; + } + else + { + count--; + } + } + } + return i; +} +/************************************************************************ + * function : HAL_LPUART_Receive_Bytes + * Description: LPUART receive bytes. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * buff:receive data buff + * length:length of buff + * return:length + ************************************************************************/ +uint32_t HAL_LPUART_Receive_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length) +{ + volatile uint32_t i, ie_backup; + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return 0; + } + ie_backup = hlpuart->Instance->IE; + hlpuart->Instance->IE = 0; + i = 0; + while(i < length) + { + if( (hlpuart->Instance->SR) & (1U << LPUART_SR_RX_INDEX) ) + { + rxbuff[i] = hlpuart->Instance->RXDR; + i++; + } + } + hlpuart->Instance->IE = ie_backup; + return length; +} +/************************************************************************ + * function : HAL_LPUART_DMA_Send_Bytes + * Description: LPUART send bytes by DMA. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * buff:send data buff + * length:length of buff + * return:none + ************************************************************************/ +void HAL_LPUART_DMA_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length) +{ + hlpuart->Instance->CR |= (1U << LPUART_CR_DMA_EN_INDEX); + hlpuart->tx_busy = 1; + HAL_DMA_Start_IT(hlpuart->dma_tx_handler, (uint32_t)buff, (uint32_t)&hlpuart->Instance->TXDR, length); + } + +/************************************************************************ + * function : HAL_LPUART_Clear_Wakeup_Flags + * Description: Clear the LPUART STOP wake up flag. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * Wakeup_Bits:LPUART wakeup flag,could be: LPUART_WAKEUP_RX_BIT LPUART_WAKEUP_MATCH_BIT LPUART_WAKEUP_START_BIT + * return:none + ************************************************************************/ + +void HAL_LPUART_Clear_Wakeup_Flags(LPUART_HandleTypeDef *hlpuart, uint32_t Wakeup_Bits) +{ + hlpuart->Instance->SR = Wakeup_Bits; +} + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_OPA.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_OPA.c new file mode 100644 index 0000000000..ef1effeb04 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_OPA.c @@ -0,0 +1,247 @@ +/* + ****************************************************************************** + * @file HAL_OPA.c + * @version V1.0.0 + * @date 2020 + * @brief OPA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Operational Amplifier (OPA). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/************************************************************************ + * function : HAL_OPA_MspInit + * Description: OPA MCU specific initiation, such as IO share, module clock, ... + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + * return: none +************************************************************************/ +__weak void HAL_OPA_MspInit(OPA_HandleTypeDef* hopa) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_OPA; + + /* Enable Clock */ + System_Module_Enable(EN_OPA); + + if(hopa->Init.OpaX == OPA1) + { + /* OPA1 GPIO inition VINP:PB6*/ + /* OPA1 GPIO inition VINM:PB5*/ + /* OPA1 GPIO inition OPA1_VOUT:PC5*/ + GPIO_OPA.Pin = GPIO_PIN_5 | GPIO_PIN_6; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_OPA); + + GPIO_OPA.Pin = GPIO_PIN_5; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_OPA); + } + + else if(hopa->Init.OpaX == OPA2) + { + /* OPA2 GPIO inition VINP:PB3*/ + /* OPA2 GPIO inition VINM:PB1*/ + /* OPA2 GPIO inition OPA2_VOUT:PB0*/ + GPIO_OPA.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_OPA); + } + else if(hopa->Init.OpaX == OPA3) + { + /* OPA3 GPIO inition VINP:PA7*/ + /* OPA3 GPIO inition VINM:PA5*/ + /* OPA3 GPIO inition OPA2_VOUT:PA6*/ + GPIO_OPA.Pin = GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_OPA); + } +} + +/************************************************************************ + * function : HAL_OPA_MspDeInit + * Description: OPA MCU De-initiation, such as IO share, module clock, ... + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + * return: none +************************************************************************/ +__weak void HAL_OPA_MspDeInit(OPA_HandleTypeDef* hopa) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + + /* Reset the OPA */ + System_Module_Reset(RST_OPA); + /* Disable Clock */ + System_Module_Disable(EN_OPA); + +} + +/************************************************************************ + * function : HAL_OPA_Init + * Description: opa initial with parameters. + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + ************************************************************************/ +HAL_StatusTypeDef HAL_OPA_Init(OPA_HandleTypeDef* hopa) +{ + __IO uint32_t *gu32RegCrx; + uint8_t trim_value; + uint32_t u32NvrTrimValue; + + /* Check the OPA handle allocation */ + if (hopa == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR; + if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR; + if(!IS_OPA_ALL_VINP(hopa->Init.VinPSel)) return HAL_ERROR; + if(!IS_OPA_ALL_VINM(hopa->Init.VinMSel)) return HAL_ERROR; + if(!IS_OPA_ALL_TRIM(hopa->Init.TrimEn)) return HAL_ERROR; + + if(hopa->Init.OpaX == OPA1) + gu32RegCrx = &hopa->Instance->OPA1_CSR; + else if(hopa->Init.OpaX == OPA2) + gu32RegCrx = &hopa->Instance->OPA2_CSR; + else if(hopa->Init.OpaX == OPA3) + gu32RegCrx = &hopa->Instance->OPA3_CSR; + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_OPA_MspInit(hopa); + + /* Select the Vin P */ + MODIFY_REG(*gu32RegCrx, OPA_CSR_VINPSEL_MASK, (hopa->Init.VinPSel)<Init.VinMSel)<Init.TrimEn == OPA_CSR_TRIM_ENABLE) + { + /* Trim the OPA_CSR_CAL_H N channel */ + SET_BIT(*gu32RegCrx, OPA_CSR_CAL_H); + CLEAR_BIT(*gu32RegCrx, OPA_CSR_CAL_L); + + for(trim_value=0;trim_value<32;trim_value++) + { + MODIFY_REG(*gu32RegCrx,OPA_CSR_TRIM_HIGH_MASK,(trim_value)<Init.OpaX-1)*4); //Read the OPA trim value; + if(((~(u32NvrTrimValue>>16))&0xFFFF) != (u32NvrTrimValue&0xFFFF)) return HAL_ERROR; + + u32NvrTrimValue = u32NvrTrimValue & 0xFFFF; + + MODIFY_REG(*gu32RegCrx,OPA_CSR_TRIM_HIGH_MASK,((u32NvrTrimValue&0x1F)<>5)&0x1F)<Instance)) return HAL_ERROR; + if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR; + + if(hopa->Init.OpaX == OPA1) + gu32RegCrx = &hopa->Instance->OPA1_CSR; + else if(hopa->Init.OpaX == OPA2) + gu32RegCrx = &hopa->Instance->OPA2_CSR; + else if(hopa->Init.OpaX == OPA3) + gu32RegCrx = &hopa->Instance->OPA3_CSR; + + /* Enable the opa */ + SET_BIT(*gu32RegCrx, OPA_CSR_EN); + + return HAL_OK; +} +/************************************************************************ + * function : HAL_OPA_Disable + * Description: opa disable. + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + ************************************************************************/ +HAL_StatusTypeDef HAL_OPA_Disable(OPA_HandleTypeDef* hopa) +{ + __IO uint32_t *gu32RegCrx; + + /* Check the OPA handle allocation */ + if (hopa == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR; + if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR; + + if(hopa->Init.OpaX == OPA1) + gu32RegCrx = &hopa->Instance->OPA1_CSR; + else if(hopa->Init.OpaX == OPA2) + gu32RegCrx = &hopa->Instance->OPA2_CSR; + else if(hopa->Init.OpaX == OPA3) + gu32RegCrx = &hopa->Instance->OPA3_CSR; + + /* Disable the opa */ + CLEAR_BIT(*gu32RegCrx, OPA_CSR_EN); + + return HAL_OK; +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_RTC.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_RTC.c new file mode 100644 index 0000000000..b167dcf209 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_RTC.c @@ -0,0 +1,485 @@ +/* + ****************************************************************************** + * @file HAL_RTC.c + * @version V1.0.0 + * @date 2020 + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization functions + * + Time and Date configuration + * + Alarm configuration + * + WakeUp Timer configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + RTC Tamper and TimeStamp Pins Selection + * + Interrupts and flags management + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_RTC_Config +* Description : Initialize the RTC peripheral +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +HAL_StatusTypeDef HAL_RTC_Config(RTC_ConfigTypeDef *hrtc) +{ +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_CLOCKSRC(hrtc->u32_ClockSource)) return HAL_ERROR; + if (!IS_RTC_COMPENSATION(hrtc->u32_Compensation)) return HAL_ERROR; +#endif + + /* RTC domain write enable */ + SCU->STOPCFG |= (1 << 0); + + PMU->CR1 |= RPMU_CR_RTCEN; + + switch (hrtc->u32_ClockSource) + { + case RTC_CLOCK_RC32K: + { + PMU->ANACR |= RPMU_ANACR_RC32K_EN; + while(!(PMU->ANACR & RPMU_ANACR_RC32K_RDY)); + + PMU->CR1 &= ~RTC_CLOCK_XTL; + }break; + + case RTC_CLOCK_XTL: + { + PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0); + + PMU->ANACR |= RPMU_ANACR_XTLEN; + while(!(PMU->ANACR & RPMU_ANACR_XTLRDY)); + + PMU->CR1 |= RTC_CLOCK_XTL; + }break; + + default: break; + } + + if (hrtc->u32_CompensationValue) + { + RTC->ADJUST = hrtc->u32_Compensation | hrtc->u32_CompensationValue; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_RTC_SetTime +* Description : Set RTC current time. +* Input : fp_Time Pointer to Time structure. +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_SetTime(RTC_TimeTypeDef *fp_Time) +{ +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_HOUR(fp_Time->u8_Hours)) return; + if (!IS_RTC_MIN(fp_Time->u8_Minutes)) return; + if (!IS_RTC_SEC(fp_Time->u8_Seconds)) return; +#endif + + /* Write-Protect Disable */ + RTC->WP = 0xCA53CA53; + + RTC->HOUR = fp_Time->u8_Hours; + RTC->MIN = fp_Time->u8_Minutes; + RTC->SEC = fp_Time->u8_Seconds; + + /* Write-Protect Enable */ + RTC->WP = 0; +} + +/********************************************************************************* +* Function : HAL_RTC_GetTime +* Description : Get RTC current time. +* Input : fp_Time Pointer to Time structure. +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_GetTime(RTC_TimeTypeDef *fp_Time) +{ + fp_Time->u8_Hours = RTC->HOUR; + fp_Time->u8_Minutes = RTC->MIN; + fp_Time->u8_Seconds = RTC->SEC; +} + +/********************************************************************************* +* Function : HAL_RTC_SetDate +* Description : Set RTC current Date. +* Input : fp_Date Pointer to Date structure. +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_SetDate(RTC_DateTypeDef *fp_Date) +{ +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_YEAR(fp_Date->u8_Year)) return; + if (!IS_RTC_MONTH(fp_Date->u8_Month)) return; + if (!IS_RTC_DAY(fp_Date->u8_Date)) return; + if (!IS_RTC_WEEKDAY(fp_Date->u8_WeekDay)) return; +#endif + + /* Write-Protect Disable */ + RTC->WP = 0xCA53CA53; + + RTC->YEAR = fp_Date->u8_Year; + RTC->MONTH = fp_Date->u8_Month; + RTC->DATE = fp_Date->u8_Date; + RTC->WEEK = fp_Date->u8_WeekDay; + + /* Write-Protect Enable */ + RTC->WP = 0; +} + +/********************************************************************************* +* Function : HAL_RTC_GetDate +* Description : Get RTC current Date. +* Input : fp_Date Pointer to Date structure. +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_GetDate(RTC_DateTypeDef *fp_Date) +{ + fp_Date->u8_Year = RTC->YEAR; + fp_Date->u8_Month = RTC->MONTH; + fp_Date->u8_Date = RTC->DATE; + fp_Date->u8_WeekDay = RTC->WEEK; +} + +/********************************************************************************* +* Function : HAL_RTC_AlarmConfig +* Description : Alarm Config +* Input : fp_Alarm Pointer to ALarm structure. +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_AlarmConfig(RTC_AlarmTypeDef *fp_Alarm) +{ + uint32_t lu32_WeekDay; + +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_ALARM_MODE(fp_Alarm->u32_AlarmMode)) return; + if (!IS_RTC_ALARM_INT(fp_Alarm->u32_AlarmInterrupt)) return; + if (!IS_RTC_ALARM_DAY_MASK(fp_Alarm->u32_DayMask)) return; + if (!IS_RTC_ALARM_HOUR_MASK(fp_Alarm->u32_HourMask)) return; + if (!IS_RTC_ALARM_MIN_MASK(fp_Alarm->u32_MinMask)) return; + + if (fp_Alarm->u32_AlarmMode == RTC_ALARM_WEEK_MODE) + { + if (!IS_RTC_ALARM_WEEKDAY(fp_Alarm->u32_AlarmWeek)) return; + } + else + { + if (!IS_RTC_DAY(fp_Alarm->u32_AlarmDay)) return; + } + + if (!IS_RTC_HOUR(fp_Alarm->u32_Hours)) return; + if (!IS_RTC_MIN(fp_Alarm->u32_Minutes)) return; + if (!IS_RTC_SEC(fp_Alarm->u32_Seconds)) return; +#endif + + if (fp_Alarm->u32_AlarmMode == RTC_ALARM_WEEK_MODE) + { + lu32_WeekDay = fp_Alarm->u32_AlarmWeek; + } + else + { + lu32_WeekDay = fp_Alarm->u32_AlarmDay; + } + + /* Coinfig Week/Day、Hour、Min、Sec */ + RTC->ALM = fp_Alarm->u32_AlarmMode | lu32_WeekDay | fp_Alarm->u32_Hours << 16 | fp_Alarm->u32_Minutes << 8 | fp_Alarm->u32_Seconds; + + /* Interrupt Enable */ + if (RTC_ALARM_INT_ENABLE == fp_Alarm->u32_AlarmInterrupt) + { + RTC->IE |= RTC_IE_ALM; + } + + RTC->CR |= (fp_Alarm->u32_DayMask) ? RTC_ALARM_DAY_MASK_ENABLE : RTC_ALARM_DAY_MASK_DISABLE; + + RTC->CR |= (fp_Alarm->u32_HourMask) ? RTC_ALARM_HOUR_MASK_ENABLE : RTC_ALARM_HOUR_MASK_DISABLE; + + RTC->CR |= (fp_Alarm->u32_MinMask) ? RTC_ALARM_MIN_MASK_ENABLE : RTC_ALARM_MIN_MASK_DISABLE; +} + +/********************************************************************************* +* Function : HAL_RTC_AlarmEnable +* Description : Alarm Enable +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_AlarmEnable(void) +{ + RTC->CR |= RTC_CR_ALM_EN; +} + +/********************************************************************************* +* Function : HAL_RTC_AlarmDisable +* Description : Alarm Disable +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_AlarmDisable(void) +{ + RTC->CR &= ~RTC_CR_ALM_EN; +} + +/********************************************************************************* +* Function : HAL_RTC_Tamper +* Description : Temper1 use PC13、Temper2 use PA0 +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_Tamper(enum_Temper_t fe_Temper, RTC_TemperTypeDef *fp_Temper) +{ +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_TEMP_EDGE(fp_Temper->u32_TemperEdge)) return; + if (!IS_RTC_TEMP_INT(fp_Temper->u32_InterruptEN)) return; + if (!IS_RTC_TEMP_CLEAR_BACKUP(fp_Temper->u32_ClearBackup)) return; + if (!IS_RTC_TEMP_FILTER(fp_Temper->u32_Filter)) return; +#endif + + switch (fe_Temper) + { + case RTC_TEMPER_1: + { + PMU->IOCR &= ~0x40; // Configure PC13 as digital IO + PMU->IOSEL |= 0x02; // Configure PC13 as tamper function + + /* Clear Config */ + RTC->CR &= ~(RTC_CR_TAMP1RCLR | RTC_CR_TAMP1FCLR | RTC_CR_TAMP1FLTEN | RTC_CR_TAMP1FLT | RTC_CR_TS1EDGE | RTC_CR_TAMPFLTCLK); + /* Edge select */ + RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TS1EDGE : 0x00; + /* Auto clear backup register */ + if (fp_Temper->u32_ClearBackup) + { + RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TAMP1FCLR : RTC_CR_TAMP1RCLR; + } + /* Temper filter */ + if (fp_Temper->u32_Filter) + { + if (fp_Temper->u32_Filter == RTC_TEMP_FILTER_512_RTCCLK) + { + RTC->CR |= RTC_CR_TAMPFLTCLK; + } + else + { + RTC->CR |= (fp_Temper->u32_Filter - 2) << 13; + } + } + + RTC->CR |= RTC_CR_TAMP1EN; + System_Delay(2000); + RTC->SR |= (RTC_SR_STP1FIE|RTC_SR_STP1RIE); + RTC->IE &= (~(RTC_IE_STP1FIE|RTC_IE_STP1RIE)); + + /* Put Temper Interrupt enable here !!!*/ + if (fp_Temper->u32_InterruptEN) + { + RTC->IE |= fp_Temper->u32_TemperEdge ? RTC_IE_STP1FIE : RTC_IE_STP1RIE; + } + + }break; + + case RTC_TEMPER_2: + { + /* Clear Config */ + RTC->CR &= ~(RTC_CR_TAMP2RCLR | RTC_CR_TAMP2FCLR | RTC_CR_TAMP2FLTEN | RTC_CR_TAMP2FLT | RTC_CR_TS2EDGE | RTC_CR_TAMPFLTCLK); + /* Edge select */ + RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TS2EDGE : 0x00; + /* Auto clear backup register */ + if (fp_Temper->u32_ClearBackup) + { + RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TAMP2FCLR : RTC_CR_TAMP2RCLR; + } + /* Temper filter */ + if (fp_Temper->u32_Filter) + { + if (fp_Temper->u32_Filter == RTC_TEMP_FILTER_512_RTCCLK) + { + RTC->CR |= RTC_CR_TAMPFLTCLK; + } + else + { + RTC->CR |= (fp_Temper->u32_Filter - 2) << 19; + } + } + + RTC->CR |= RTC_CR_TAMP2EN; + System_Delay(2000); + RTC->SR |= (RTC_SR_STP2FIE|RTC_SR_STP2RIE); + RTC->IE &= (~(RTC_IE_STP2FIE|RTC_IE_STP2RIE)); + + /* Temper Interrupt */ + if (fp_Temper->u32_InterruptEN) + { + RTC->IE |= fp_Temper->u32_TemperEdge ? RTC_IE_STP2FIE : RTC_IE_STP2RIE; + } + + }break; + + default: break; + } +} + +/********************************************************************************* +* Function : HAL_RTC_TamperEnable +* Description : +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_TamperEnable(enum_Temper_t fe_Temper) +{ + if (fe_Temper == RTC_TEMPER_1) + { + RTC->CR |= RTC_CR_TAMP1EN; + } + else + { + RTC->CR |= RTC_CR_TAMP2EN; + } +} + +/********************************************************************************* +* Function : HAL_RTC_TamperDisable +* Description : +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020定 +**********************************************************************************/ +void HAL_RTC_TamperDisable(enum_Temper_t fe_Temper) +{ + if (fe_Temper == RTC_TEMPER_1) + { + RTC->CR &= ~RTC_CR_TAMP1EN; + } + else + { + RTC->CR &= ~RTC_CR_TAMP2EN; + } +} + +/*************************************************************************************************** +* Function : HAL_RTC_Standby_Wakeup +* Description : wakeup source select +* Input : fu32_Edge 0: Rising edge +* 1: Falling edge +* fe_Wakeup : wakeup source select, STANDBY_WAKEUP_RISING, STANDBY_WAKEUP_FALLING +* Outpu : +* Author : Chris_Kyle Date : 2021 +*******************************************************************************************************/ +void HAL_RTC_Standby_Wakeup(enum_WKUP_t fe_Wakeup, uint32_t fu32_Edge) +{ + switch (fe_Wakeup) + { + case RTC_WAKEUP_WKUP1: + case RTC_WAKEUP_WKUP2: + case RTC_WAKEUP_WKUP3: + case RTC_WAKEUP_WKUP4: + case RTC_WAKEUP_WKUP5: + case RTC_WAKEUP_WKUP6: + { + /* Clear flags、Standby Enable */ + PMU->CR1 |= RPMU_CR_STB_EN | RPMU_CR_CWUF | RPMU_CR_CSBF; + + /* Wakeup IO Filter Enable */ + PMU->CR1 |= fe_Wakeup << 8; + /* Wakeup IO Enable */ + PMU->CR1 |= fe_Wakeup; + + if (fe_Wakeup == RTC_WAKEUP_WKUP2) + { + /* PC13 */ + PMU->IOCR &= ~0x40; // must configure PC13 as digital function + } + + if (fu32_Edge) + { + PMU->CR2 |= fe_Wakeup >> 16; + } + else + { + PMU->CR2 &= ~(fe_Wakeup >> 16); + } + + PMU->CR1 |= RPMU_CR_CWUF; // clear wakeup flag + System_Enter_Standby_Mode(); + }break; + + case RTC_WAKEUP_STAMP2: + case RTC_WAKEUP_STAMP1: + case RTC_WAKEUP_32S: + case RTC_WAKEUP_SEC: + case RTC_WAKEUP_MIN: + case RTC_WAKEUP_HOUR: + case RTC_WAKEUP_DATE: + { + /* Clear flags、Standby Enable */ + PMU->CR1 |= RPMU_CR_STB_EN | RPMU_CR_CWUF | RPMU_CR_CSBF; + + RTC->SR |= fe_Wakeup; + RTC->IE |= fe_Wakeup; + + System_Enter_Standby_Mode(); + }break; + + default: break; + } +} + +/********************************************************************************* +* Function : HAL_RTC_GetStandbyStatus +* Description : Check MCU have entered standby mode +* Input : +* Outpu : 0: Not Enter Standby Mode + 1: Entered Standby Mode +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +bool HAL_RTC_Get_StandbyStatus(void) +{ + if (PMU->SR & RPMU_SR_SBF) + { + return true; + } + else + { + return false; + } +} + +/********************************************************************************* +* Function : HAL_RTC_Get_StandbyWakeupSource +* Description : Get MCU Standby Wakeup Source +* Input : +* Outpu : RTC_WAKEUP_SOURCE_BORWUF + RTC_WAKEUP_SOURCE_IWDTWUF + RTC_WAKEUP_SOURCE_RSTWUF + RTC_WAKEUP_SOURCE_RTCWUF + RTC_WAKEUP_SOURCE_WKUP6 + RTC_WAKEUP_SOURCE_WKUP5 + RTC_WAKEUP_SOURCE_WKUP4 + RTC_WAKEUP_SOURCE_WKUP3 + RTC_WAKEUP_SOURCE_WKUP2 + RTC_WAKEUP_SOURCE_WKUP1 +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +uint32_t HAL_RTC_Get_StandbyWakeupSource(void) +{ + return PMU->SR; +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_SPI.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_SPI.c new file mode 100644 index 0000000000..606860706e --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_SPI.c @@ -0,0 +1,1051 @@ +/* + ****************************************************************************** + * @file HAL_Spi.c + * @version V1.0.0 + * @date 2020 + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral. + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +#define SPI_RX_TIMEOUT 2000 +#define SPI_TX_DMA_TIMEOUT 2000 +volatile uint32_t lu32_ReceiveTimeOut = SPI_RX_TIMEOUT; +volatile uint32_t lu32_TX_DMA_TimeOut = SPI_TX_DMA_TIMEOUT; +/************************************************************************ + * function : HAL_SPI_IRQHandler + * Description: This function handles SPI interrupt request. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +__weak void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + /* + NOTE : This function should be modified by the user. + */ + if ( (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) && ((hspi->Instance->IE) & SPI_STATUS_RX_NOT_EMPTY) ) + { + /* In master mode */ + if (hspi->Instance->CTL & SPI_CTL_MST_MODE) + { + while (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + + if (hspi->Rx_Count >= hspi->Rx_Size) + { + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE)); + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Receive End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + + + /* Disable Rx Not Empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY); + + if(hspi->Instance == SPI1) + NVIC_ClearPendingIRQ(SPI1_IRQn); + else if(hspi->Instance == SPI2) + NVIC_ClearPendingIRQ(SPI2_IRQn); + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set machine is DILE */ + hspi->RxState = SPI_RX_STATE_IDLE; + } + } + } + /* In Slave mode */ + else + { + while ((hspi->Rx_Count < hspi->Rx_Size) && (lu32_ReceiveTimeOut > 0) ) + { + if (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + lu32_ReceiveTimeOut = SPI_RX_TIMEOUT; //If recieve data, Reset the timeout value + } + else + { + lu32_ReceiveTimeOut--; + } + + } + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Disable Rx Not Empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY); + + if(hspi->Instance == SPI1) + NVIC_ClearPendingIRQ(SPI1_IRQn); + else if(hspi->Instance == SPI2) + NVIC_ClearPendingIRQ(SPI2_IRQn); + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set machine is DILE */ + hspi->RxState = SPI_RX_STATE_IDLE; + } + } + + if ( (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_HALF_EMPTY) && ((hspi->Instance->IE) & SPI_IE_TX_FIFO_HALF_EMPTY_EN) ) + { + while (hspi->Tx_Count < hspi->Tx_Size) + { + if (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + } + else + { + break; + } + + } + /* Clear Tx FIFO half empty Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_FIFO_HALF_EMPTY); + if(hspi->Tx_Count == hspi->Tx_Size) + { + /* Disable Tx FIFO half empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN); + } + } + if ((hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_IE_TX_BATCH_DONE_EN) ) + { + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Disable TX Batch Done Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_TX_BATCH_DONE); + /* Disable Tx FIFO half empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN); + + if(hspi->Instance == SPI1) + NVIC_ClearPendingIRQ(SPI1_IRQn); + else if(hspi->Instance == SPI2) + NVIC_ClearPendingIRQ(SPI2_IRQn); + + lu32_TX_DMA_TimeOut = SPI_TX_DMA_TIMEOUT; + while (hspi->Instance->STATUS & SPI_STATUS_TX_BUSY) + { + lu32_TX_DMA_TimeOut--; + if(0 == lu32_TX_DMA_TimeOut) + { + break; + } + } + + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_DMA_REQ_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + } + + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + + hspi->TxState = SPI_TX_STATE_IDLE; + } + + if ( (hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_STATUS_RX_BATCH_DONE) ) + { + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Disable RX Batch Done Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE); + + if(hspi->Instance == SPI1) + NVIC_ClearPendingIRQ(SPI1_IRQn); + else if(hspi->Instance == SPI2) + NVIC_ClearPendingIRQ(SPI2_IRQn); + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_DMA_REQ_EN); + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + } + + hspi->RxState = SPI_RX_STATE_IDLE; + } +} + +/************************************************************************ + * function : HAL_SPI_MspInit + * Description: + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + /* SPI1 */ + if (hspi->Instance == SPI1) + { + } + /* SPI2 */ + else if (hspi->Instance == SPI2) + { + /* Enable Clock */ + System_Module_Enable(EN_SPI2); + + /* SPI2 CS PB12 */ + /* SPI2 SCK PB13 */ + /* SPI2 MOSI PB15 */ + /* SPI2 MISO PB14 */ + GPIO_Handle.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_4; + HAL_GPIO_Init(GPIOB, &GPIO_Handle); + + if (hspi->Init.X_Mode == SPI_4X_MODE) + { + /* SPI2 IO3 PC6 */ + /* SPI2 IO2 PC7 */ + GPIO_Handle.Pin = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_2; + HAL_GPIO_Init(GPIOC, &GPIO_Handle); + } + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(SPI2_IRQn); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(SPI2_IRQn); + } +} + +/************************************************************************ + * function : HAL_SPI_MspDeInit + * Description: SPI De-Initialize the SPI clock, GPIO, IRQ. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + + /* SPI1 */ + if (hspi->Instance == SPI1) + { + } + /* SPI2 */ + else if (hspi->Instance == SPI2) + { + /* Disable Clock */ + System_Module_Disable(EN_SPI2); + + /* Reset the used GPIO to analog */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + + if (hspi->Init.X_Mode == SPI_4X_MODE) + { + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6 | GPIO_PIN_7); + } + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(SPI2_IRQn); + + /* Disable External Interrupt */ + NVIC_DisableIRQ(SPI2_IRQn); + } +} + +/************************************************************************ + * function : HAL_SPI_Init + * Description: SPI initial with parameters. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + if (!IS_SPI_ALL_MODE(hspi->Init.SPI_Mode)) return HAL_ERROR; + if (!IS_SPI_WORK_MODE(hspi->Init.SPI_Work_Mode)) return HAL_ERROR; + if (!IS_SPI_X_MODE(hspi->Init.X_Mode)) return HAL_ERROR; + if (!IS_SPI_FIRST_BIT(hspi->Init.First_Bit)) return HAL_ERROR; + if (!IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRate_Prescaler)) return HAL_ERROR; + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_SPI_MspInit(hspi); + + /* Automatic change direction */ + hspi->Instance->CTL |= (SPI_CTL_IO_MODE); + + /* Set SPI Work mode */ + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + SET_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE); + } + else + { + CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE); + + hspi->Instance->BATCH = (hspi->Instance->BATCH & (~0x000FFFFFU)) | (1 << 0); + + hspi->Instance->TX_CTL |= SPI_TX_CTL_MODE | (0x88 << 8); // dummy data = 0x88 + + if (hspi->Init.X_Mode != SPI_1X_MODE) + { + hspi->Instance->CTL |= SPI_CTL_SFILTER; + } + + /* Slave Alternate Enable */ + hspi->Instance->CTL |= SPI_CTL_SLAVE_EN; + + /* Slave Mode Enable Rx By Default */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + } + + /* Set SPI First Bit */ + if (hspi->Init.First_Bit == SPI_FIRSTBIT_LSB) + SET_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST); + else + CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST); + + /* Set SPI Work Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~(SPI_CTL_CPHA | SPI_CTL_CPOL))) | (hspi->Init.SPI_Work_Mode); + + /* Set SPI X_Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | (hspi->Init.X_Mode); + + /* Set SPI BaudRate Prescaler */ + hspi->Instance->BAUD = ((hspi->Instance->BAUD) & (~0x0000FFFF)) | (hspi->Init.BaudRate_Prescaler); + + /* Disable All Interrupt */ + hspi->Instance->IE = 0x00000000; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_DeInit + * Description: De-Initialize the SPI peripheral. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * return : HAL_StatusTypeDef : HAL status + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + hspi->RxState = SPI_RX_STATE_IDLE; + hspi->TxState = SPI_TX_STATE_IDLE; + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->Rx_Size = 0; + hspi->Tx_Size = 0; + hspi->Rx_Count = 0; + hspi->Tx_Count = 0; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_Transmit + * Description: Transmits an amount of data in blocking mode. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Transmit Timeout + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + if(!Size) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + hspi->Tx_Count = 0; + hspi->Tx_Size = Size; + hspi->Tx_Buffer = pData; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + else + { + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + } + + while(hspi->Tx_Size > 0) + { + /* Wait Tx FIFO Not Full */ + while (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + hspi->Tx_Size--; + uiTimeout = Timeout; + } + + if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) + { + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BUSY)); + while (hspi->Instance->STATUS & SPI_STATUS_TX_BUSY) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + } + else + { + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE)); + Status = HAL_OK; + } + +End: + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + } + + return Status; +} + +/************************************************************************ + * function : HAL_SPI_Transmit_DMA + * Description: Transmits an amount of data in blocking mode with DMA. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hspi->TxState != SPI_TX_STATE_IDLE) + { + return HAL_ERROR; + } + /* Set machine is Sending */ + hspi->TxState = SPI_TX_STATE_SENDING; + + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Enable Tx Batch Done Interrupt */ + SET_BIT(hspi->Instance->IE, SPI_STATUS_TX_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Tx FIFO */ + hspi->Instance->TX_CTL &= ~SPI_TX_CTL_DMA_LEVEL; + hspi->Instance->TX_CTL |= SPI_TX_CTL_DMA_LEVEL_0; + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + else + { + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + } + + HAL_DMA_Start(hspi->HDMA_Tx, (uint32_t)pData, (uint32_t)&hspi->Instance->DAT, Size); + + hspi->Instance->TX_CTL |= SPI_TX_CTL_DMA_REQ_EN; + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_Receive + * Description: Receive an amount of data in blocking mode. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + * Size : Amount of data to be Receive + * Timeout : Receive Timeout + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + hspi->Rx_Count = 0; + hspi->Rx_Size = Size; + hspi->Rx_Buffer = pData; + uiTimeout = Timeout; + + if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) + { + hspi->Instance->BATCH = 1; + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + + while ( hspi->Rx_Size > 0) + { + while (READ_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_FIFO_EMPTY)) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + return HAL_TIMEOUT; + } + } + } + + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + hspi->Rx_Size--; + uiTimeout = Timeout; + } + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + return HAL_OK; + } + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + + /* Receive Start */ + hspi->Instance->CS |= SPI_CS_CS0; + + while(hspi->Rx_Size > 0) + { + /* have no timeout */ + if (uiTimeout == 0) + { + /* Wait Rx FIFO Not Empty */ + while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY); + } + else + { + while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY) + { + if (uiTimeout-- == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + hspi->Rx_Size--; + } + + Status = HAL_OK; + + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Receive End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + + return Status; +} + +/************************************************************************ + * function : HAL_SPI_Receive_DMA + * Description: Receive an amount of data in blocking mode with DMA. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + * Size : Amount of data to be Receive + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hspi->RxState != SPI_RX_STATE_IDLE) + { + return HAL_ERROR; + } + /* Set Slave machine is receiving */ + hspi->RxState = SPI_RX_STATE_RECEIVING; + + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Enable Rx Batch Done Interrupt */ + SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + /* Rx FIFO */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_LEVEL_0; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + + HAL_DMA_Start(hspi->HDMA_Rx, (uint32_t)&hspi->Instance->DAT, (uint32_t)pData, Size); + + hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_REQ_EN; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_Wire_Config + * Description: SPI Wire Config + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * Mode : This parameter can be a value of @ref X_MODE + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Set SPI X_Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | X_Mode; + + return HAL_OK; +} +/************************************************************************ + * function : HAL_SPI_Transmit_IT + * Description: Transmit an amount of data in blocking mode with interrupt. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Tx machine is running */ + if (hspi->TxState != SPI_TX_STATE_IDLE) + { + return HAL_ERROR; + } + + hspi->Tx_Size = Size; + hspi->Tx_Buffer = pData; + hspi->Tx_Count = 0; + + /* Set machine is Sending */ + hspi->TxState = SPI_TX_STATE_SENDING; + + /* Clear TX FIFO */ + SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + else + { + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + } + + while (hspi->Tx_Count < hspi->Tx_Size) + { + if (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + else + break; + } + /* Clear Tx FIFO half empty Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_FIFO_HALF_EMPTY); + + + /* Enable Tx FIFO half empty Interrupt and Tx batch done Interrupt*/ + SET_BIT(hspi->Instance->IE, (SPI_IE_TX_FIFO_HALF_EMPTY_EN | SPI_IE_TX_BATCH_DONE_EN)); + + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_Receive_IT + * Description: Receive an amount of data in blocking mode with interrupt. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hspi->RxState != SPI_RX_STATE_IDLE) + { + return HAL_ERROR; + } + + /* Set Slave machine is receiving */ + hspi->RxState = SPI_RX_STATE_RECEIVING; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + + /* Receive Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + else + { + /* Reset BATCH register */ + hspi->Instance->BATCH = 1; + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + } + + hspi->Rx_Size = Size; + hspi->Rx_Buffer = pData; + hspi->Rx_Count = 0; + lu32_ReceiveTimeOut = SPI_RX_TIMEOUT; + + /* Enable Rx FIFO Not Empty Interrupt */ + SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_TransmitReceive + * Description: Transmits and recieve an amount of data in blocking mode. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pTxData : Pointer to transmit data buffer + * pRxData : Pointer to recieve data buffer + * Size : Amount of data to be sent + * Timeout : TransmitReceive Timeout + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout) +{ + __IO uint32_t TxFlag = 1U, uiTimeout, uiRegTemp; + HAL_StatusTypeDef Status = HAL_OK; + + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR; + + hspi->Tx_Count = 0; + hspi->Rx_Count = 0; + hspi->Tx_Buffer = pTxData; + hspi->Rx_Buffer = pRxData; + hspi->Tx_Size = Size; + hspi->Rx_Size = Size; + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + + /* Clear TX FIFO */ + SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + + + if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) + { + while((!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0)) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + hspi->Tx_Size--; + } + + TxFlag = 0; + } + else + { + /* Set Data Size */ + hspi->Instance->BATCH = hspi->Tx_Size; + + /* Transmit Start */ + hspi->Instance->CS |= SPI_CS_CS0; + TxFlag = 1; + } + + while((hspi->Tx_Size>0) || (hspi->Rx_Size>0)) + { + uiRegTemp = hspi->Instance->STATUS; + + if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) + { + /* Wait Rx FIFO Not Empty */ + if((!(uiRegTemp & SPI_STATUS_RX_FIFO_EMPTY)) && (hspi->Rx_Size>0)) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + hspi->Rx_Size--; + TxFlag = 1U; + } + /* Wait Tx FIFO Not Full */ + if(((uiRegTemp & SPI_STATUS_TX_FIFO_HALF_EMPTY)) && (hspi->Tx_Size>0) && (TxFlag == 1U)) + { + while((!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0)) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + hspi->Tx_Size--; + } + TxFlag = 0; + } + } + else + { + /* Wait Tx FIFO Not Full */ + if((!(uiRegTemp & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0) && (TxFlag == 1U)) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + hspi->Tx_Size--; + TxFlag = 0; + } + + /* Wait Rx FIFO Not Empty */ + if((!(uiRegTemp & SPI_STATUS_RX_FIFO_EMPTY)) && (hspi->Rx_Size>0)) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + hspi->Rx_Size--; + TxFlag = 1U; + } + } + + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE)); + + Status = HAL_OK; + +End: + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + } + + return Status; +} + +/************************************************************************ + * function : HAL_SPI_GetTxState + * Description: Get Tx state. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi) +{ + return hspi->TxState; +} + +/************************************************************************ + * function : HAL_SPI_GetRxState + * Description: Get Rx state. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi) +{ + return hspi->RxState; +} + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_TIMER.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_TIMER.c new file mode 100644 index 0000000000..ff0a480df2 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_TIMER.c @@ -0,0 +1,1520 @@ +/*********************************************************************** + * Filename : hal_lpuart.c + * Description : lpuart driver source file + * Author(s) : xwl + * version : V1.0 + * Modify date : 2019-11-19 + ***********************************************************************/ +#include "ACM32Fxx_HAL.h" + +static void TIMER_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); +static void TIMER_TI1FP1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIMER_TI2FP2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIMER_IC1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); + +/********************************************************************************* +* Function : HAL_TIMER_MSP_Init +* Description : MSP init, mainly about clock, nvic +* Input : timer handler +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +__weak uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim) +{ + uint32_t Timer_Instance; + + if (0 == IS_TIMER_INSTANCE(htim->Instance)) + { + return HAL_ERROR; //instance error + } + + Timer_Instance = (uint32_t)(htim->Instance); + + switch(Timer_Instance) + { + case TIM1_BASE: + System_Module_Reset(RST_TIM1); + System_Module_Enable(EN_TIM1); + NVIC_ClearPendingIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + break; + + case TIM3_BASE: + System_Module_Reset(RST_TIM3); + System_Module_Enable(EN_TIM3); + NVIC_ClearPendingIRQ(TIM3_IRQn); + NVIC_EnableIRQ(TIM3_IRQn); + break; + + case TIM6_BASE: + System_Module_Reset(RST_TIM6); + System_Module_Enable(EN_TIM6); + NVIC_ClearPendingIRQ(TIM6_IRQn); + NVIC_EnableIRQ(TIM6_IRQn); + break; + + case TIM14_BASE: + System_Module_Reset(RST_TIM14); + System_Module_Enable(EN_TIM14); + NVIC_ClearPendingIRQ(TIM14_IRQn); + NVIC_EnableIRQ(TIM14_IRQn); + break; + + case TIM15_BASE: + System_Module_Reset(RST_TIM15); + System_Module_Enable(EN_TIM15); + NVIC_ClearPendingIRQ(TIM15_IRQn); + NVIC_EnableIRQ(TIM15_IRQn); + break; + + case TIM16_BASE: + System_Module_Reset(RST_TIM16); + System_Module_Enable(EN_TIM16); + NVIC_ClearPendingIRQ(TIM16_IRQn); + NVIC_EnableIRQ(TIM16_IRQn); + break; + + case TIM17_BASE: + System_Module_Reset(RST_TIM17); + System_Module_Enable(EN_TIM17); + NVIC_ClearPendingIRQ(TIM17_IRQn); + NVIC_EnableIRQ(TIM17_IRQn); + break; + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + + +__weak uint32_t HAL_TIMER_Base_MspDeInit(TIM_HandleTypeDef * htim) +{ + uint32_t Timer_Instance; + + if (0 == IS_TIMER_INSTANCE(htim->Instance)) + { + return HAL_ERROR; //instance error + } + + Timer_Instance = (uint32_t)(htim->Instance); + + switch(Timer_Instance) + { + case TIM1_BASE: + System_Module_Disable(EN_TIM1); + NVIC_ClearPendingIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_DisableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + break; + + + + case TIM3_BASE: + System_Module_Disable(EN_TIM3); + NVIC_ClearPendingIRQ(TIM3_IRQn); + NVIC_DisableIRQ(TIM3_IRQn); + break; + + + + case TIM6_BASE: + System_Module_Disable(EN_TIM6); + NVIC_ClearPendingIRQ(TIM6_IRQn); + NVIC_DisableIRQ(TIM6_IRQn); + break; + + + + case TIM14_BASE: + System_Module_Disable(EN_TIM14); + NVIC_ClearPendingIRQ(TIM14_IRQn); + NVIC_DisableIRQ(TIM14_IRQn); + break; + + case TIM15_BASE: + System_Module_Disable(EN_TIM15); + NVIC_ClearPendingIRQ(TIM15_IRQn); + NVIC_DisableIRQ(TIM15_IRQn); + break; + + case TIM16_BASE: + System_Module_Disable(EN_TIM16); + NVIC_ClearPendingIRQ(TIM16_IRQn); + NVIC_DisableIRQ(TIM16_IRQn); + break; + + case TIM17_BASE: + System_Module_Disable(EN_TIM17); + NVIC_ClearPendingIRQ(TIM17_IRQn); + NVIC_DisableIRQ(TIM17_IRQn); + break; + + default: + return HAL_ERROR; + } + + return HAL_OK; +} +/********************************************************************************* +* Function : HAL_TIMER_Slave_Mode_Config +* Description : configure timer in slave mode +* Input : + htim: timer handler + sSlaveConfig: slave mode parameter strcture + SlaveMode: TIM_SLAVE_MODE_DIS, TIM_SLAVE_MODE_ENC1... + InputTrigger: TIM_TRIGGER_SOURCE_ITR0, TIM_TRIGGER_SOURCE_ITR1... + TriggerPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + TriggerPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + if (0 == IS_TIM_SLAVE_INSTANCE(htim->Instance) ) + { + return 1; // not supported + } + /*reset SMS and TS bits*/ + htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2|BIT4|BIT5|BIT6)); + /*SET SMS bits*/ + htim->Instance->SMCR |= (sSlaveConfig->SlaveMode & (BIT0|BIT1|BIT2) ); + /*SET TS bits*/ + htim->Instance->SMCR |= (sSlaveConfig->InputTrigger & (BIT4|BIT5|BIT6) ); + + switch (sSlaveConfig->InputTrigger) + { + case TIM_TRIGGER_SOURCE_TI1FP1: + TIMER_TI1FP1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TRIGGER_SOURCE_TI2FP2: + TIMER_TI2FP2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TRIGGER_SOURCE_ETRF: + TIMER_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TRIGGER_SOURCE_ITR0: + case TIM_TRIGGER_SOURCE_ITR1: + case TIM_TRIGGER_SOURCE_ITR2: + case TIM_TRIGGER_SOURCE_ITR3: + // don't need do anything here + break; + + default: + return 1; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Master_Mode_Config +* Description : configure timer in master mode +* Input : + TIMx: timer instance + sMasterConfig: master mode parameter structure + MasterSlaveMode: TIM_TRGO_RESET, TIM_TRGO_ENABLE... + MasterOutputTrigger: TIM_MASTERSLAVEMODE_DISABLE, TIM_MASTERSLAVEMODE_ENABLE +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig) +{ + /*reset bits*/ + TIMx->SMCR &= (~BIT7); + TIMx->CR2 &= (~(BIT4|BIT5|BIT6)); + + TIMx->SMCR |= sMasterConfig->MasterSlaveMode; + TIMx->CR2 |= sMasterConfig->MasterOutputTrigger; + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Output_Config +* Description : configure output parameter +* Input : + TIMx: timer instance + Output_Config: output configration parameter structure + OCMode: OUTPUT_MODE_FROZEN, OUTPUT_MODE_MATCH_HIGH... + Pulse: write to ccrx register + OCPolarity: OC channel output polarity: OUTPUT_POL_ACTIVE_HIGH, OUTPUT_POL_ACTIVE_LOW + OCNPolarity: OCN channel output polarity: OUTPUT_POL_ACTIVE_HIGH, OUTPUT_POL_ACTIVE_LOW + OCFastMode: OUTPUT_FAST_MODE_DISABLE, OUTPUT_FAST_MODE_ENABLE + OCIdleState: OC channel idle state, OUTPUT_IDLE_STATE_0, OUTPUT_IDLE_STATE_1 + OCNIdleState: OCN channel idle state, OUTPUT_IDLE_STATE_0, OUTPUT_IDLE_STATE_1 + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~BIT0); //disable OC1 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT1); + } + else + { + TIMx->CCER |= (BIT1); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT2); //disable OC1N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT3); + } + else + { + TIMx->CCER |= (BIT3); + } + } + + TIMx->CCMR1 &= (~0x00FFU); // reset low 8 bits + TIMx->CCR1 = Output_Config->Pulse; + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR1 |= (BIT2); + } + TIMx->CCMR1 |= (BIT3); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT8); + } + else + { + TIMx->CR2 |= BIT8; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT9); + } + else + { + TIMx->CR2 |= BIT9; + } + + } + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~BIT4); //disable OC2 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT5); + } + else + { + TIMx->CCER |= (BIT5); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT6); //disable OC2N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT7); + } + else + { + TIMx->CCER |= (BIT7); + } + } + + TIMx->CCMR1 &= (~0xFF00U); // reset high 8 bits + TIMx->CCR2 = Output_Config->Pulse; // write value to ccr before preload enable + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR1 |= (BIT10); + } + TIMx->CCMR1 |= (BIT11); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT10); + } + else + { + TIMx->CR2 |= BIT10; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT11); + } + else + { + TIMx->CR2 |= BIT11; + } + + } + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~BIT8); //disable OC3 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT9); + } + else + { + TIMx->CCER |= (BIT9); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT10); //disable OC3N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT11); + } + else + { + TIMx->CCER |= (BIT11); + } + } + + TIMx->CCMR2 &= (~0x00FF); // reset low 8 bits + TIMx->CCMR2 |= (BIT3); // preload enable + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR2 |= (BIT2); + } + + TIMx->CCR3 = Output_Config->Pulse; + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT12); + } + else + { + TIMx->CR2 |= BIT12; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT13); + } + else + { + TIMx->CR2 |= BIT13; + } + + } + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~BIT12); //disable OC4 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT13); + } + else + { + TIMx->CCER |= (BIT13); + } + + TIMx->CCMR2 &= (~0xFF00); // reset high 8 bits + TIMx->CCR4 = Output_Config->Pulse; + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR2 |= (BIT10); // fast mode + } + TIMx->CCMR2 |= (BIT11); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT14); + } + else + { + TIMx->CR2 |= BIT14; + } + + } + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12); + break; + + default: + return 1; // error parameter + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIMER_Capture_Config +* Description : configure capture parameters +* Input : + TIMx: timer instance + Capture_Config: capture configuration parameter strcture + ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + ICSelection: TIM_ICSELECTION_DIRECTTI, TIM_ICSELECTION_INDIRECTTI + ICFilter: TIM_IC1_FILTER_LVL(x), TIM_IC2_FILTER_LVL(x), x:0-15 + ICPrescaler: TIM_IC1_PRESCALER_1, TIM_IC2_PRESCALER_1... + Channel: channel id, TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel) +{ + switch(Channel) + { + case TIM_CHANNEL_1: + TIMER_IC1_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (~BIT2|BIT3); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= Capture_Config->ICPrescaler; + break; + + case TIM_CHANNEL_2: + TIMER_IC2_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (~BIT10|BIT11); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= Capture_Config->ICPrescaler; + break; + + case TIM_CHANNEL_3: + TIMER_IC3_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (~BIT2|BIT3); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= Capture_Config->ICPrescaler; + + break; + + case TIM_CHANNEL_4: + TIMER_IC4_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (~BIT10|BIT11); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= Capture_Config->ICPrescaler; + break; + + default: + return 1; + } + + return 0; +} + + + +/********************************************************************************* +* Function : HAL_TIMER_SelectClockSource +* Description : select timer counter source, internal or external +* Input: + htim : timer handler + sClockSourceConfig: configuration parameters, includes following members: + ClockSource: TIM_CLOCKSOURCE_INT, TIM_CLOCKSOURCE_ETR... + ClockPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + ClockPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... + ClockFilter: TIM_ETR_FILTER_LVL(x), TIM_IC1_FILTER_LVL(x), TIM_IC2_FILTER_LVL(x) +* Output : HAL_ERROR:error, HAL_OK:OK +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +{ + htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2)); + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INT: + { + // do nothing here + break; + } + + case TIM_CLOCKSOURCE_ETR: + { + + /* Configure the ETR Clock source */ + TIMER_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= BIT14; // ECE=1,external clock mode 2 + break; + } + + case TIM_CLOCKSOURCE_TI1FP1: + { + + TIMER_TI1FP1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6)); // trigger selection + htim->Instance->SMCR |= (5 << 4); // Trigger select TI1FP1 + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); // select external clock mode 1 + break; + } + + case TIM_CLOCKSOURCE_TI2FP2: + { + TIMER_TI2FP2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6)); // trigger selection + htim->Instance->SMCR |= (6 << 4); // Trigger select TI2FP2 + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); // select external clock mode 1 + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6)); + htim->Instance->SMCR |= ( (sClockSourceConfig->ClockSource - TIM_CLOCKSOURCE_ITR0) << 4); + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); // select external clock mode 1 + break; + } + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_Init +* Description : timer base initiation +* Input : timer handler +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim) +{ + if (0 == IS_TIMER_INSTANCE(htim->Instance)) + { + return 1; //instance error + } + + htim->Instance->CR1 = BIT2; // CEN=0, URS=1, OPM = 0 + + if (htim->Init.ARRPreLoadEn) + { + htim->Instance->CR1 |= (BIT7); + } + else + { + htim->Instance->CR1 &= (~BIT7); + } + htim->Instance->ARR = htim->Init.Period; + htim->Instance->PSC = htim->Init.Prescaler; + if (IS_TIM_REPETITION_COUNTER_INSTANCE(htim->Instance)) + { + htim->Instance->RCR = htim->Init.RepetitionCounter; + } + htim->Instance->EGR = BIT0; // no UIF generated because URS=1 + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(htim->Instance)) + { + htim->Instance->CR1 = (htim->Instance->CR1 & (~(BIT8|BIT9))) | ((htim->Init.ClockDivision) & (BIT8|BIT9)); + } + //up/down/center mode + htim->Instance->CR1 = (htim->Instance->CR1 & (~(BIT4|BIT5|BIT6))) | ((htim->Init.CounterMode) & (BIT4|BIT5|BIT6)); + + htim->Instance->CR1 &= (~BIT2); //URS = 0 + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_DeInit +* Description : timer base deinitiation, disable Timer, turn off module clock and nvic +* Input : timer handler +* Output : HAL_OK: success; HAL_ERROR:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_Base_DeInit(TIM_HandleTypeDef *htim) +{ + htim->Instance->CR1 &= (~BIT0); + + HAL_TIMER_Base_MspDeInit(htim); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_Start +* Description : start timer +* Input : timer instance +* Output : none +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx) +{ + if (0 == IS_TIM_SLAVE_INSTANCE(TIMx) ) + { + TIMx->CR1 |= BIT0; + return; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + return; + } + + return; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_Stop +* Description : stop timer +* Input : timer handler +* Output : none +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_Base_Stop(TIM_TypeDef *TIMx) +{ + TIMx->CR1 &= (~BIT0); + HAL_TIM_DISABLE_IT_EX(TIMx, TIM_IT_UPDATE); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_OnePulse_Init +* Description : start timer with one pulse mode +* Input : + htim: timer handler + mode: 0 means normal mode, 1 means one pulse mode +* Output : HAL_OK, success; HAL_ERROR, fail +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t mode) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + HAL_TIMER_Base_Init(htim); + + /*reset the OPM Bit */ + htim->Instance->CR1 &= (~BIT3); + if (0 != mode) + { + /*set the OPM Bit */ + htim->Instance->CR1 |= BIT3; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIM_PWM_Output_Start +* Description : start timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} +/********************************************************************************* +* Function : HAL_TIM_PWM_Output_Stop +* Description : stop timer pwm output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return HAL_ERROR; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~(BIT0 | BIT2)); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~(BIT4 | BIT6)); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~(BIT8 | BIT10)); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~(BIT12)); + break; + + default: + return HAL_ERROR; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR &= (~BIT15); + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_OC_Start +* Description : start timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_OCxN_Start +* Description : start timer OCxN output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_OC_Stop +* Description : stop timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return HAL_ERROR; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~(BIT0 | BIT2)); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~(BIT4 | BIT6)); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~(BIT8 | BIT10)); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~(BIT12)); + break; + + default: + return HAL_ERROR; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR &= (~BIT15); + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIM_Capture_Start +* Description : start timer capture +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIM_Capture_Stop +* Description : stop timer capture +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~BIT0); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~BIT4); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~BIT8); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~BIT12); + break; + + default: + return 1; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIMEx_ETRSelection +* Description : select ETR signal, it can ben GPIO, COMP1_OUT, COMP2_OUT, ADC analog watchdog output +* Input : + htim: timer handler + ETRSelection: ETR_SELECT_GPIO, ETR_SELECT_COMP1_OUT... +* Output : HAL_OK, Success; HAL_ERROR:Fail +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ETRSelection(TIM_HandleTypeDef *htim, uint32_t ETRSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + + htim->Instance->AF1 &= (~ETR_SELECT_MASK); + htim->Instance->AF1 |= ETRSelection; + + return status; +} + +/********************************************************************************* +* Function : HAL_TIMER_ReadCapturedValue +* Description : read capture value as channel +* Input : + htim: timer handler + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : capture value +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t capture_data = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Return the capture 1 value */ + capture_data = htim->Instance->CCR1; + break; + } + case TIM_CHANNEL_2: + { + /* Return the capture 2 value */ + capture_data = htim->Instance->CCR2; + break; + } + case TIM_CHANNEL_3: + { + /* Return the capture 3 value */ + capture_data = htim->Instance->CCR3; + break; + } + case TIM_CHANNEL_4: + { + /* Return the capture 4 value */ + capture_data = htim->Instance->CCR4; + break; + } + default: + break; + } + + return capture_data; +} + +/********************************************************************************* +* Function : HAL_TIMER_GenerateEvent +* Description : Generate event by software +* Input: + htim : timer handler + EventSource: TIM_EVENTSOURCE_UPDATE, TIM_EVENTSOURCE_CC1... +* Output : HAL_ERROR:error, HAL_OK:OK +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + htim->Instance->EGR = EventSource; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Clear_Capture_Flag +* Description : clear capture flag as channel id +* Input : + htim: timer handler + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : capture value +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + switch (Channel) + { + case TIM_CHANNEL_1: + { + htim->Instance->SR &= (~(BIT1|BIT9)); + break; + } + case TIM_CHANNEL_2: + { + htim->Instance->SR &= (~(BIT2|BIT10)); + break; + } + case TIM_CHANNEL_3: + { + htim->Instance->SR &= (~(BIT3|BIT11)); + break; + } + case TIM_CHANNEL_4: + { + htim->Instance->SR &= (~(BIT4|BIT12)); + break; + } + default: + break; + } +} + +/********************************************************************************* +* Function : TIMER_ETR_SetConfig +* Description : configure ETR channel polarity, prescaler and filter +* Input: + TIMx : timer instance + TIM_ExtTRGPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... + TIM_ExtTRGPolarity: TIM_ETR_POLAIRTY_HIGH, TIM_ETR_POLAIRTY_LOW + ExtTRGFilter: TIM_ETR_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + /* Reset the ETR Bits */ + TIMx->SMCR &= (~0xFF00U); + + /* Set the Prescaler, the Filter value and the Polarity */ + TIMx->SMCR |= (TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | ExtTRGFilter); +} + +/********************************************************************************* +* Function : TIMER_TI1FP1_ConfigInputStage +* Description : configure TI1FP1 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI1_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_TI1FP1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t Filter) +{ + TIMx->CCER &= (~BIT0); //Disable the Channel 1: Reset the CC1E Bit + TIMx->CCMR1 = ((TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT0); // CH1 as input + + TIMx->CCMR1 &= (~0xF0U); // reset TI1 filter + TIMx->CCMR1 |= Filter; + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_FALLING; + } + else + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_BOTH; + } +} + +/********************************************************************************* +* Function : TIMER_TI2FP2_ConfigInputStage +* Description : configure TI2FP2 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI2_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_TI2FP2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t Filter) +{ + TIMx->CCER &= (~BIT4); //Disable the Channel 2: Reset the CC2E Bit + TIMx->CCMR1 = ((TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT8); // CH2 as input + + TIMx->CCMR1 &= (~0xF000U); // reset TI2 filter + TIMx->CCMR1 |= Filter; + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_FALLING; + } + else + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_BOTH; + } +} + +/********************************************************************************* +* Function : TIMER_IC1_SetConfig +* Description : configure TI1FP1 or TI2FP1 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI1_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +void TIMER_IC1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (~BIT0); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT0; + TIMx->CCMR1 &= (~0xF0U); + } + else + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT1; + TIMx->CCMR1 &= (~0xF000U); + } + + TIMx->CCMR1 |= Filter; + +} + +/********************************************************************************* +* Function : TIMER_IC2_SetConfig +* Description : configure TI1FP2 or TI2FP2 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI2_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 2, Reset the CC2E Bit */ + TIMx->CCER &= (~BIT4); + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT8; + TIMx->CCMR1 &= (~0xF000U); + } + else + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT9; + TIMx->CCMR1 &= (~0xF0U); + } + + TIMx->CCMR1 |= Filter; + +} + +/********************************************************************************* +* Function : TIMER_IC3_SetConfig +* Description : configure TI3FP3 or TI4FP3 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI3_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 3, Reset the CC3E Bit */ + TIMx->CCER &= (~BIT8); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT0|BIT1))) | BIT0; + TIMx->CCMR2 &= (~0xF0U); + } + else + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT0|BIT1))) | BIT1; + TIMx->CCMR2 &= (~0xF000U); + } + + + TIMx->CCMR2 |= Filter; +} + + +/********************************************************************************* +* Function : TIMER_IC4_SetConfig +* Description : configure TI3FP4 or TI4FP4 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI4_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 3, Reset the CC3E Bit */ + TIMx->CCER &= (~BIT12); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT8|BIT9))) | BIT8; + TIMx->CCMR2 &= (~0xF000U); + } + else + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT8|BIT9))) | BIT9; + TIMx->CCMR2 &= (~0xF0U); + } + + TIMx->CCMR2 |= Filter; + +} + + diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_TKEY.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_TKEY.c new file mode 100644 index 0000000000..c61c777186 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_TKEY.c @@ -0,0 +1,595 @@ +/* + ****************************************************************************** + * @file HAL_TKEY.c + * @version V1.0.0 + * @date 2020 + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * @ Initialization and de-initialization functions + * @ IO operation functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +__IO uint32_t u32Regbackup; + +/************************************************************************ + * function : TKEY_IRQHandler + * Description: tkey interrupt service routine. + * input : + * none + * return: none + ************************************************************************/ +void TKEY_IRQHandler(void) +{ + TKEY->ISR = 0xFFF; +} + +/************************************************************************ + * function : HAL_TKEY_MspInit + * Description: Init the hardware, GPIO and clock, etc. + * input : htkey : TKEY handle + * return : none + ************************************************************************/ +void HAL_TKEY_MspInit(TKEY_HandleTypeDef* htkey) +{ + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + uint8_t ucI; + + for(ucI = 0; htkey->ChannelData[ucI].ChannelId != 0xFFFF; ucI++) + { + /* TKEY0 GPIO inition*/ + if(htkey->ChannelData[ucI].ChannelId < 4) /*TKEY0-3 -> PA10-13*/ + { + GPIO_Handle.Pin = (uint16_t)(0x0001 << (htkey->ChannelData[ucI].ChannelId + 10)); + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + } + + if((htkey->ChannelData[ucI].ChannelId >= 4)&&(htkey->ChannelData[ucI].ChannelId <= 5)) /*TKEY4-5 -> PD6-7*/ + { + GPIO_Handle.Pin = (uint16_t)(0x0001 << (htkey->ChannelData[ucI].ChannelId + 2)); + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_Handle); + } + + if((htkey->ChannelData[ucI].ChannelId >= 6)&&(htkey->ChannelData[ucI].ChannelId <= 7)) /*TKEY6-7 -> PA14-15*/ + { + GPIO_Handle.Pin = (uint16_t)(0x0001 << (htkey->ChannelData[ucI].ChannelId + 8)); + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + } + + if((htkey->ChannelData[ucI].ChannelId >= 8)&&(htkey->ChannelData[ucI].ChannelId <= 10)) /*TKEY8-10 -> PC10-12*/ + { + GPIO_Handle.Pin = (uint16_t)(0x0001 << (htkey->ChannelData[ucI].ChannelId + 2)); + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_Handle); + } + + if(htkey->ChannelData[ucI].ChannelId == 11) /*TKEY11 -> PD2*/ + { + GPIO_Handle.Pin = (uint16_t)(0x0001 << (htkey->ChannelData[ucI].ChannelId - 9)); + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_Handle); + } + + if((htkey->ChannelData[ucI].ChannelId >= 12)&&(htkey->ChannelData[ucI].ChannelId <= 15)) /*TKEY12-15 -> PB3-6*/ + { + GPIO_Handle.Pin = (uint16_t)(0x0001 << (htkey->ChannelData[ucI].ChannelId - 9)); + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_Handle); + } + } + + if(htkey->Init.ShieldEn == TKEY_CR_SCAN_ENABLE) /*TKEY_SHIELD -> PB7*/ + { + GPIO_Handle.Pin = GPIO_PIN_7; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_Handle); + } + + /*Set the Cs(PB9) and Creg(PB8) pin to analog*/ + GPIO_Handle.Pin = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_Handle); + + SCU->RCHCR |= ((15 << 17) | SCU_RCHCR_RC4M_EN); //RC4M TRIM and Enable. + while((SCU->RCHCR & SCU_RCHCR_RC4MRDY) == 0x00); + SCU->CCR2 |= SCU_CCR2_TKSCLK_SEL; //TKEY use the RC4M as clock. + + System_Enable_RC32K(); //RC32K Enable. + + System_Module_Reset(RST_TKEY); + + /* Enable TKEY Clock */ + System_Module_Enable(EN_TKEY); + + /* Disable TKEY Interrupt */ + NVIC_ClearPendingIRQ(TKEY_IRQn); + NVIC_DisableIRQ(TKEY_IRQn); +} + +/************************************************************************ + * function : HAL_TKEY_Start + * Description: TKEY start to scan + * input : htkey : TKEY handle + * return : HAL_OK: success; HAL_ERROR: failed. +************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_Start(TKEY_HandleTypeDef* htkey) +{ + /* Check the parameters */ + if(!IS_TKEY_ALL_INSTANCE(htkey->Instance)) return HAL_ERROR; + /*Enable the Tkey scan*/ + SET_BIT(htkey->Instance->CR , TKEY_CR_SCAN); + + /*Start the Tkey scan*/ + SET_BIT(htkey->Instance->CR, TKEY_CR_START); + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_TKEY_Stop + * Description: TKEY stop the scan + * input : htkey : TKEY handle + * return : HAL_OK: success; HAL_ERROR: failed. + ************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_Stop(TKEY_HandleTypeDef* htkey) +{ + /* Check the parameters */ + if(!IS_TKEY_ALL_INSTANCE(htkey->Instance)) return HAL_ERROR; + + /*Check if the Tkey scan is busy*/ + while(READ_BIT(htkey->Instance->ISR , TKEY_ISR_BUSY)){} + + /*disable the Tkey scan*/ + CLEAR_BIT(htkey->Instance->CR, TKEY_CR_SCAN); + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_TKEY_Suspend + * Description: Set the sleep parameters. + * input : htkey : TKEY handle + * return : HAL_OK: success; HAL_ERROR: failed. + ************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_Suspend(TKEY_HandleTypeDef* htkey) +{ + uint8_t ucI; + __IO uint32_t *gu32RegTemp; + + /* Check the parameters */ + if(!IS_TKEY_ALL_INSTANCE(htkey->Instance)) return HAL_ERROR; + + /* Disable TKEY Interrupt */ + NVIC_ClearPendingIRQ(TKEY_IRQn); + NVIC_DisableIRQ(TKEY_IRQn); + + u32Regbackup = htkey->Instance->SMPR; + MODIFY_REG(htkey->Instance->SMPR, TKEY_SMPR_SWT_MASK, TKEY_SMPR_SWT(htkey->ScanPara.SleepScanWaitTime)); //Slow down the scan speed. + + SET_BIT(htkey->Instance->CR, TKEY_CR_SLEEP); //Enable the wakeup. + + SET_BIT(htkey->Instance->IER, TKEY_IER_WAKEUPIE); //Enable the wakeup interrupt. + + gu32RegTemp = &htkey->Instance->CH0; + for(ucI = 0; htkey->ChannelData[ucI].ChannelId != 0xFFFF; ucI++) + { + /* Write the base data and the wakeup threshold.*/ + *(gu32RegTemp + htkey->ChannelData[ucI].ChannelId) = htkey->ChannelData[ucI].Tkey_Data->Data; + *(gu32RegTemp - 16 + htkey->ChannelData[ucI].ChannelId) = htkey->ChannelData[ucI].Tkey_RefPara->RefDelta*htkey->ScanPara.WakeUpThRatio; + } + + /* Enable TKEY Interrupt */ + NVIC_ClearPendingIRQ(TKEY_IRQn); + NVIC_EnableIRQ(TKEY_IRQn); + + /*Start the Tkey scan*/ + SET_BIT(htkey->Instance->CR, TKEY_CR_START); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_TKEY_Resume + * Description: Resume the wakeup parameters. + * input : htkey : TKEY handle + * return : HAL_OK: success; HAL_ERROR: failed. + ************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_Resume(TKEY_HandleTypeDef* htkey) +{ + /* Disable TKEY Interrupt */ + NVIC_ClearPendingIRQ(TKEY_IRQn); + NVIC_DisableIRQ(TKEY_IRQn); + + CLEAR_BIT(htkey->Instance->IER, TKEY_IER_WAKEUPIE); //Disable the wakeup interrupt. + + htkey->Instance->SMPR = u32Regbackup; //Use the backup scan value. + CLEAR_BIT(htkey->Instance->CR, TKEY_CR_SLEEP); //Disable the wakeup. + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_TKEY_ReadNr + * Description: Read the count number of the Cr. + * input : htkey : TKEY handle + * return : HAL_OK: success; HAL_ERROR: failed. + ************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_ReadNr(TKEY_HandleTypeDef* htkey) +{ + HAL_StatusTypeDef Status = HAL_OK; + /* Check the parameters */ + if(!IS_TKEY_ALL_INSTANCE(htkey->Instance)) return HAL_ERROR; + + /*Check if the Tkey scan is busy*/ + while(READ_BIT(htkey->Instance->ISR , TKEY_ISR_BUSY)){} + + /*Set the CREN, enabel the internal channel scan*/ + SET_BIT(htkey->Instance->CR, TKEY_CR_CREN); + + /*Clear the SLEEP, use normal scan mode*/ + CLEAR_BIT(htkey->Instance->CR, TKEY_CR_SLEEP); + + /* Clear all flag */ + htkey->Instance->ISR = 0x07; + HAL_TKEY_Start(htkey); + + while(!READ_BIT(htkey->Instance->ISR, TKEY_ISR_EOC)) + { + if(!READ_BIT(htkey->Instance->ISR, TKEY_ISR_BUSY)) //Some times will stop.restart. + SET_BIT(htkey->Instance->CR, TKEY_CR_START); + + if(READ_BIT(htkey->Instance->ISR, TKEY_ISR_TIMEOUT)) + { + SET_BIT(htkey->Instance->ISR, TKEY_ISR_TIMEOUT); //Clear the timeout flag + Status = HAL_ERROR; + break; + } + } + + htkey->Instance->ISR = TKEY_ISR_EOC; + + htkey->NrData = htkey->Instance->DR; + + return Status; +} + +/************************************************************************ + * function : HAL_TKEY_ReadChannelData + * Description: Read the count number of the all channels. + * input : htkey : TKEY handle + * return : HAL_OK: success; HAL_ERROR: failed. + ************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_ReadChannelData(TKEY_HandleTypeDef* htkey) +{ + uint8_t ucI; + __IO uint32_t *gu32RegTemp; + + htkey->Instance->ISR = 0x07; + if(!(htkey->Instance->CR & TKEY_CR_CONT)) + { + /*Start the Tkey scan*/ + SET_BIT(htkey->Instance->CR, TKEY_CR_START); + } + + while(!READ_BIT(htkey->Instance->ISR, TKEY_ISR_EOC)) + { + if(!READ_BIT(htkey->Instance->ISR, TKEY_ISR_BUSY)) //Some times will stop.restart. + SET_BIT(htkey->Instance->CR, TKEY_CR_START); + + if(READ_BIT(htkey->Instance->ISR, TKEY_ISR_TIMEOUT)) + { + SET_BIT(htkey->Instance->ISR, TKEY_ISR_TIMEOUT); //Clear the timeout flag + return HAL_ERROR; + } + } + + htkey->Instance->ISR = TKEY_ISR_EOC; + + gu32RegTemp = &htkey->Instance->CH0; + for(ucI = 0; htkey->ChannelData[ucI].ChannelId != 0xFFFF; ucI++) + { + /* Read the data and calculate the delta.*/ + htkey->ChannelData[ucI].Tkey_Data->Data = *(gu32RegTemp + htkey->ChannelData[ucI].ChannelId); + htkey->ChannelData[ucI].Tkey_Data->Delta = (INT32)htkey->ChannelData[ucI].Tkey_Data->RefData - (INT32)htkey->ChannelData[ucI].Tkey_Data->Data; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_TKEY_ReadAllNx + * Description: Read the count number of the all channels first time, and start the scan. + * input : htkey : TKEY handle + * return : HAL_OK: success; HAL_ERROR: failed. + ************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_ReadAllNx(TKEY_HandleTypeDef* htkey) +{ + uint8_t ucI; + + /* Check the parameters */ + if(!IS_TKEY_ALL_INSTANCE(htkey->Instance)) return HAL_ERROR; + + /*Clear the CREN, disable the internal channel scan*/ + CLEAR_BIT(htkey->Instance->CR, TKEY_CR_CREN); + + for(ucI = 0; htkey->ChannelData[ucI].ChannelId != 0xFFFF; ucI++) + { + /*Enable the channels*/ + htkey->Instance->CXSELR |= (1<ChannelData[ucI].ChannelId); + /*If the channel need compensation*/ + if(htkey->ChannelData[ucI].Tkey_RefPara->CrSelect) + htkey->Instance->CRSELR |= (1<ChannelData[ucI].ChannelId); + } + /*Clear the SLEEP, use normal scan mode*/ + CLEAR_BIT(htkey->Instance->CR, TKEY_CR_SLEEP); + + HAL_TKEY_Start(htkey); + + HAL_TKEY_ReadChannelData(htkey); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_TKEY_StartUpStateProcess + * Description: Init the TKEY channel data. + * input : ChannelData : TKEY channel data handle point to TKEY_ChannelDataDef. + * return : None + ************************************************************************/ +void HAL_TKEY_StartUpStateProcess(const TKEY_ChannelDataDef *ChannelData) +{ + ChannelData->Tkey_Data->DebIn = ChannelData->Tkey_RefPara->DebIn; + ChannelData->Tkey_Data->DebOut = ChannelData->Tkey_RefPara->DebOut; + ChannelData->Tkey_Data->StateId = TKEY_STATEID_RELEASE; +} + +/************************************************************************ + * function : HAL_TKEY_DebDetectStateProcess + * Description: The TKEY detect action state process. + * input : ChannelData : TKEY channel data handle point to TKEY_ChannelDataDef. + * return : None + ************************************************************************/ +void HAL_TKEY_DebDetectStateProcess(const TKEY_ChannelDataDef *ChannelData) +{ + if (ChannelData->Tkey_Data->Delta >= ChannelData->Tkey_RefPara->DetectInTH) + { + if (ChannelData->Tkey_Data->DebIn > 0) + { + ChannelData->Tkey_Data->DebIn--; + } + if (ChannelData->Tkey_Data->DebIn == 0) + { + ChannelData->Tkey_Data->StateId = TKEY_STATEID_DETECT; + ChannelData->Tkey_Data->DebOut = ChannelData->Tkey_RefPara->DebOut; + } + // else stay in Debounce Detect + } + else + { + ChannelData->Tkey_Data->StateId = TKEY_STATEID_RELEASE; + ChannelData->Tkey_Data->DebIn = ChannelData->Tkey_RefPara->DebIn; + } +} + +/************************************************************************ + * function : HAL_TKEY_DebReleaseDetectStateProcess + * Description: The TKEY detect to release state process. + * input : ChannelData : TKEY channel data handle point to TKEY_ChannelDataDef. + * return : None + ************************************************************************/ +void HAL_TKEY_DebReleaseDetectStateProcess(const TKEY_ChannelDataDef *ChannelData) +{ + if (ChannelData->Tkey_Data->Delta >= ChannelData->Tkey_RefPara->DetectOutTH) + { + ChannelData->Tkey_Data->StateId = TKEY_STATEID_DETECT; + ChannelData->Tkey_Data->DebOut = ChannelData->Tkey_RefPara->DebOut; + } + else + { + if (ChannelData->Tkey_Data->DebOut > 0) + { + ChannelData->Tkey_Data->DebOut--; + } + if (ChannelData->Tkey_Data->DebOut == 0) + { + ChannelData->Tkey_Data->StateId = TKEY_STATEID_RELEASE; + ChannelData->Tkey_Data->DebIn = ChannelData->Tkey_RefPara->DebIn; + } + } +} + +/************************************************************************ + * function : HAL_TKEY_Init + * Description: Init the TKEY. + * input : htkey : TKEY handle + * return : HAL_OK: success; HAL_ERROR: failed. + ************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_Init(TKEY_HandleTypeDef* htkey) +{ + uint8_t ucI; + uint32_t u32RegTemp; + + /* Check the TKEY handle allocation */ + if (htkey == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_TKEY_ALL_INSTANCE(htkey->Instance)) return HAL_ERROR; + if(!IS_TKEY_ALL_VKEYSEL(htkey->Init.VkeySel)) return HAL_ERROR; + if(!IS_TKEY_ALL_VREFSEL(htkey->Init.VrefSel)) return HAL_ERROR; + if(!IS_TKEY_ALL_SHIELDEN(htkey->Init.ShieldEn)) return HAL_ERROR; + if(!IS_TKEY_ALL_SCANWAITTIME(htkey->Init.ScanWaitTime)) return HAL_ERROR; + if(!IS_TKEY_ALL_CSDISCHARGETIME(htkey->Init.CsDisChargeTime)) return HAL_ERROR; + if(!IS_TKEY_ALL_SW1(htkey->Init.Sw1H)) return HAL_ERROR; + if(!IS_TKEY_ALL_SW1(htkey->Init.Sw1L)) return HAL_ERROR; + + /* Init the low level hardware : GPIO, CLOCK, NVIC, DMA */ + HAL_TKEY_MspInit(htkey); + + /*Check if the Tkey scan is busy*/ + while(READ_BIT(htkey->Instance->ISR , TKEY_ISR_BUSY)){} + + HAL_TKEY_Stop(htkey); + + /*Config the Tkey control register*/ + u32RegTemp = ((TKEY_CR_CHARGESEL_LDO << 11)& TKEY_CR_CHARGESEL) | \ + (TKEY_CR_VKEYSEL(htkey->Init.VkeySel) & TKEY_CR_VKEYSEL_MASK) | \ + (TKEY_CR_VREFSEL(htkey->Init.VrefSel) & TKEY_CR_VREFSEL_MASK) | \ + ((TKEY_CR_SPREAD_DISABLE << 5)& TKEY_CR_SPREAD) | \ + ((TKEY_CR_CONT_ENABLE << 4)& TKEY_CR_CONT) | \ + ((htkey->Init.ShieldEn << 3)& TKEY_CR_SHIELDEN); + + WRITE_REG(htkey->Instance->CR,u32RegTemp); + + /*Config the Tkey TKEY_SMPR register*/ + u32RegTemp = (TKEY_SMPR_SWT(htkey->Init.ScanWaitTime) & TKEY_SMPR_SWT_MASK) | \ + (TKEY_SMPR_CST(htkey->Init.CsDisChargeTime) & TKEY_SMPR_CST_MASK); + + WRITE_REG(htkey->Instance->SMPR,u32RegTemp); + + /*Config the Tkey TKEY_SOFR register*/ + u32RegTemp = (TKEY_SOFR_SW1H(htkey->Init.Sw1H) & TKEY_SOFR_SW1H_MASK) | \ + (TKEY_SOFR_SW1L(htkey->Init.Sw1L) & TKEY_SOFR_SW1L_MASK); + + WRITE_REG(htkey->Instance->SOFR,u32RegTemp); + + HAL_TKEY_ReadNr(htkey); + + for(ucI = 0; htkey->ChannelData[ucI].ChannelId != 0xFFFF; ucI++) + { + /* if need calibrate , read the data to the reference data.*/ + htkey->ChannelData[ucI].Tkey_Data->StateId = TKEY_STATEID_STARTUP; + htkey->ChannelData[ucI].Tkey_Data->ReferenceFlag = 1; + + htkey->ChannelData[ucI].Tkey_RefPara->DetectInTH = htkey->ChannelData[ucI].Tkey_RefPara->RefDelta*htkey->ScanPara.DetectInThRatio; + htkey->ChannelData[ucI].Tkey_RefPara->DetectOutTH = htkey->ChannelData[ucI].Tkey_RefPara->RefDelta*htkey->ScanPara.DetectOutThRatio; + htkey->ChannelData[ucI].Tkey_RefPara->CalibratTH = htkey->ChannelData[ucI].Tkey_RefPara->RefDelta*htkey->ScanPara.CalibratThRatio; + } + + HAL_TKEY_ReadAllNx(htkey); + /* Clear all keys*/ + htkey->ChannelDetected = 0; + htkey->ChannelDetectedNum = 0; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_TKEY_DetectProcess + * Description: TKEY detect main process. + * input : htkey : TKEY handle + * return : None. + ************************************************************************/ +void HAL_TKEY_DetectProcess(TKEY_HandleTypeDef* htkey) +{ + uint8_t ucI; + const TKEY_ChannelDataDef *ChannelData; + + HAL_TKEY_ReadChannelData(htkey); + + for(ucI = 0; htkey->ChannelData[ucI].ChannelId != 0xFFFF; ucI++) + { + ChannelData = &htkey->ChannelData[ucI]; + switch(ChannelData->Tkey_Data->StateId) + { + case TKEY_STATEID_STARTUP : + HAL_TKEY_StartUpStateProcess(ChannelData); + break; + case TKEY_STATEID_RELEASE : + HAL_TKEY_DebDetectStateProcess(ChannelData); + break; + case TKEY_STATEID_DETECT : + if(htkey->ScanTimer >= htkey->ScanPara.DetectingTimeout) + htkey->ChannelDetecting |= (1 << ChannelData->ChannelId); + HAL_TKEY_DebReleaseDetectStateProcess(ChannelData); + if(ChannelData->Tkey_Data->StateId == TKEY_STATEID_RELEASE) + { + htkey->ChannelDetected |= (1 << ChannelData->ChannelId); + htkey->ChannelValue = ChannelData->ChannelId; + htkey->ChannelDetectedNum++; + htkey->ChannelDetecting &= ~(1 << ChannelData->ChannelId); + htkey->ScanTimer = 0; //Reset the timer when detect Key release. + } + break; + default : + break; + } + + if((htkey->ChannelData[ucI].Tkey_Data->Delta > htkey->ChannelData[ucI].Tkey_RefPara->CalibratTH) \ + ||(htkey->ChannelData[ucI].Tkey_Data->Delta < (-htkey->ChannelData[ucI].Tkey_RefPara->CalibratTH))) + { + htkey->ScanTimer++; + if(htkey->ScanTimer >= htkey->ScanPara.CalibratTimeout) + { + htkey->CalFlag = 1; //Need calibrate. + htkey->ScanTimer = 0; + htkey->ChannelDetected = 0; + htkey->ChannelDetecting = 0; + break; + } + } + if((htkey->ChannelData[ucI].Tkey_Data->Delta > 2*htkey->ChannelData[ucI].Tkey_RefPara->RefDelta) \ + ||(htkey->ChannelData[ucI].Tkey_Data->Delta < (-htkey->ChannelData[ucI].Tkey_RefPara->RefDelta))) + { + htkey->CalFlag = 1; //Need calibrate. + htkey->ScanTimer = 0; + htkey->ChannelDetected = 0; + htkey->ChannelDetecting = 0; + break; + } + + if(htkey->ChannelDetecting) //If don't need detecting. + { + htkey->ChannelDetecting = 0; + htkey->CalFlag = 1; //Need calibrate. + } + } +} + +/************************************************************************ + * function : HAL_TKEY_Calibrate_RefData + * Description: TKEY Calibrate the base Reference Data. + * input : htkey : TKEY handle + CalTimes: The calibrat times. + * return : None + ************************************************************************/ +void HAL_TKEY_Calibrate_RefData(TKEY_HandleTypeDef* htkey, uint8_t CalTimes) +{ + uint8_t ucI,ucJ; + uint32_t sum[16]; + + memset(sum,0,sizeof(sum)); + for(ucJ=0; ucJ < CalTimes; ucJ++) + { + HAL_TKEY_ReadChannelData(htkey); + for(ucI = 0; htkey->ChannelData[ucI].ChannelId != 0xFFFF; ucI++) + { + if(htkey->ChannelData[ucI].Tkey_Data->Data) + { + sum[ucI] += htkey->ChannelData[ucI].Tkey_Data->Data; + } + if(ucJ == (CalTimes-1)) + { + htkey->ChannelData[ucI].Tkey_Data->RefData = sum[ucI]/CalTimes; + } + } + } +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART.c new file mode 100644 index 0000000000..7634e6d7d4 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART.c @@ -0,0 +1,901 @@ +/* + ****************************************************************************** + * @file HAL_Uart.c + * @version V1.0.0 + * @date 2020 + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + + +/* If Use 'UART_MODE_TX_RX_DEBUG', Point to Debug Uart */ +UART_TypeDef *Uart_Debug = NULL; + +/* Private function prototypes -----------------------------------------------*/ +static void UART_Config_BaudRate(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef HAL_UART_Wait_Tx_Done(UART_HandleTypeDef *huart); +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); + +/********************************************************************************* +* Function : HAL_UART_IRQHandler +* Description : Handle UART interrupt request. +* Input : huart: UART handle. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t read_bytes_number; + uint32_t isrflags, ieits, errorflags; + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return; +#endif + + isrflags =READ_REG(huart->Instance->RIS); + ieits =READ_REG(huart->Instance->IE); + errorflags =0x00U; + errorflags =(isrflags & (uint32_t)(UART_ICR_PEI|UART_ICR_OEI|UART_ICR_FEI|UART_ICR_BEI)); + + /* Enable TXI */ + if (huart->Instance->IE & UART_IE_TXI) + { + if (huart->Instance->RIS & UART_RIS_TXI) + { + /* Clear TXI Status */ + SET_BIT(huart->Instance->ICR , UART_ICR_TXI); + + for(;;) + { + if(huart->lu32_TxCount == huart->lu32_TxSize) + { + huart->lu8_TxBusy = false; + + /* Disable TX interrupt */ + CLEAR_BIT(huart->Instance->IE, UART_IE_TXI); + + HAL_UART_TxCpltCallback(huart); + break; + } + + if (READ_BIT(huart->Instance->FR, UART_FR_TXFF)) + { + break; + } + + huart->Instance->DR = huart->lu8_TxData[huart->lu32_TxCount++]; + } + } + } + + /* RXI */ + if ((huart->Instance->IE & UART_IE_RXI || huart->Instance->IE& UART_IE_RTI) && errorflags == 0) + { + if (huart->Instance->RIS & UART_RIS_RXI) + { + read_bytes_number = 0; + /* Clear RXI Status */ + SET_BIT(huart->Instance->ICR, UART_ICR_RXI); + + /* Receive end */ + while(huart->lu32_RxCount lu32_RxSize ) + { + if(!READ_BIT(huart->Instance->FR, UART_FR_RXFE)) + { + /* Store Data in buffer */ + huart->lu8_RxData[huart->lu32_RxCount++] = huart->Instance->DR; + read_bytes_number++; + } + else + { + break; + } + if (read_bytes_number == huart->lu32_fifo_level_minus1) + { + break; + } + } + if(huart->lu32_RxCount ==huart->lu32_RxSize ) + { + huart->lu8_RxBusy = false; + + /* Disable RX and RTI interrupt */ + CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI|UART_IE_RTI)); + + /* clear error interrupt */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI); + + HAL_UART_RxCpltCallback(huart); + } + } + else if(huart->Instance->RIS & UART_RIS_RTI) + { + /*clear RTI Status */ + SET_BIT(huart->Instance->ICR ,UART_ICR_RTI); + + while(!READ_BIT(huart->Instance->FR, UART_FR_RXFE)) + { + huart->lu8_RxData[huart->lu32_RxCount++] = huart->Instance->DR; + } + + huart->lu8_RxBusy = false; + + /* Disable RX and RTI interrupt */ + CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI|UART_IE_RTI)); + + /* clear error interrupt */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI); + + HAL_UART_RxCpltCallback(huart); + } + } + /* if some errors occurred */ + if(errorflags != 0 &&(ieits & (UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI))) + { + /* UART parity error interrupt occurred */ + if (((isrflags & UART_RIS_PEI) != 0) && ((ieits & UART_IE_PEI) != 0)) + { + /* Clear parity error status */ + SET_BIT(huart->Instance->ICR, UART_ICR_PEI); + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART break error interrupt occurred */ + if (((isrflags & UART_RIS_BEI) != 0) && ((ieits & UART_IE_BEI) != 0)) + { + SET_BIT(huart->Instance->ICR, UART_RIS_BEI); + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred */ + if (((isrflags & UART_RIS_FEI) != 0) && ((ieits & UART_IE_FEI) != 0)) + { + SET_BIT(huart->Instance->ICR, UART_RIS_FEI); + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred */ + if (((isrflags & UART_RIS_OEI) != 0) && ((ieits & UART_IE_OEI) != 0)) + { + SET_BIT(huart->Instance->ICR, UART_RIS_OEI); + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* clear error interrupt */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI); + + HAL_UART_ErrorCallback(huart); + } +} + +/********************************************************************************* +* Function : HAL_UART_Wait_Tx_Done +* Description : wait Tx FIFO empty +* Input : huart: UART handle. +* Output : +**********************************************************************************/ +static HAL_StatusTypeDef HAL_UART_Wait_Tx_Done(UART_HandleTypeDef *huart) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + /* wait TX not busy*/ + while(READ_BIT(huart->Instance->FR, UART_FR_BUSY)); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_MspInit +* Description : Initialize the UART MSP. +* Input : huart: UART handle. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function should be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Uart1; + + if (huart->Instance == UART1) + { + /* Enable Clock */ + System_Module_Enable(EN_UART1); + + /* Initialization GPIO */ + /* A9:Tx A10:Rx */ + GPIO_Uart1.Pin = GPIO_PIN_9 | GPIO_PIN_10; + GPIO_Uart1.Mode = GPIO_MODE_AF_PP; + GPIO_Uart1.Pull = GPIO_PULLUP; + GPIO_Uart1.Alternate = GPIO_FUNCTION_2; + + HAL_GPIO_Init(GPIOA, &GPIO_Uart1); + + if (huart->Init.HwFlowCtl & UART_HWCONTROL_CTS) + { + /* A11:CTS */ + GPIO_Uart1.Pin = GPIO_PIN_11; + + HAL_GPIO_Init(GPIOA, &GPIO_Uart1); + } + + if (huart->Init.HwFlowCtl & UART_HWCONTROL_RTS) + { + /* A12:RTS */ + GPIO_Uart1.Pin = GPIO_PIN_12; + + HAL_GPIO_Init(GPIOA, &GPIO_Uart1); + } + + /* NVIC Config */ + NVIC_ClearPendingIRQ(UART1_IRQn); + NVIC_SetPriority(UART1_IRQn, 5); + NVIC_EnableIRQ(UART1_IRQn); + } +} + +/********************************************************************************* +* Function : HAL_UART_Init +* Description : Initialize the UART mode according to the specified parameters +* in the UART_InitTypeDef +* Input : huart: UART handle. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; + if (!IS_UART_WORDLENGTH(huart->Init.WordLength)) return HAL_ERROR; + if (!IS_UART_STOPBITS(huart->Init.StopBits)) return HAL_ERROR; + if (!IS_UART_PARITY(huart->Init.Parity)) return HAL_ERROR; + if (!IS_UART_MODE(huart->Init.Mode)) return HAL_ERROR; + if (!IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)) return HAL_ERROR; +#endif + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_UART_MspInit(huart); + + /* Config BaudRate */ + UART_Config_BaudRate(huart); + + /* Set the UART Communication parameters */ + huart->Instance->LCRH = huart->Init.WordLength | UART_LCRH_FEN | huart->Init.StopBits | huart->Init.Parity; + huart->Instance->CR = huart->Init.HwFlowCtl | huart->Init.Mode | UART_CR_UARTEN; + + if (huart->Init.Mode == UART_MODE_TX_RX_DEBUG) + { + Uart_Debug = huart->Instance; + } + else if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + huart->Instance->CR2 = UART_CR2_TXOE_SEL; + } + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_MspDeInit +* Description : DeInitialize the UART MSP. +* Input : huart: UART handle. +* Output : +**********************************************************************************/ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function should be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file. + */ + if (huart->Instance == UART1) + { + /* Disable Clock */ + System_Module_Disable(EN_UART1); + + /* DeInitialization GPIO */ + /* A9:Tx A10:Rx */ + HAL_GPIO_DeInit(GPIOA,GPIO_PIN_9 | GPIO_PIN_10); + + if (huart->Init.HwFlowCtl & UART_HWCONTROL_CTS) + { + /* A11:CTS */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11); + } + + if (huart->Init.HwFlowCtl & UART_HWCONTROL_RTS) + { + /* A12:RTS */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12); + } + + /* NVIC DeInit */ + NVIC_DisableIRQ(UART1_IRQn); + + } + else if(huart->Instance == UART2) + { + + } +} + +/********************************************************************************* +* Function : HAL_UART_Init +* Description : Initialize the UART mode according to the specified parameters +* in the UART_InitTypeDef +* Input : huart: UART handle. +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + /* DeInit the low level hardware : GPIO, CLOCK, NVIC */ + HAL_UART_MspDeInit(huart); + + return HAL_OK; + +} + + +/********************************************************************************* +* Function : HAL_UART_Transmit +* Description : Send an amount of data in blocking mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be sent. +* Input : fu32_Timeout: Timeout duration. +* Output : HAL status +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size, uint32_t fu32_Timeout) +{ + uint32_t lu32_Timeout; + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + huart->lu32_TxCount = 0; + + while (fu32_Size--) + { + huart->Instance->DR = *fu8_Data++; + + huart->lu32_TxCount++; + + /* have no timeout */ + if (fu32_Timeout == 0) + { + while (huart->Instance->FR & UART_FR_TXFF); + } + else + { + lu32_Timeout = fu32_Timeout *256; + + while (huart->Instance->FR & UART_FR_TXFF) + { + if (lu32_Timeout-- == 0) + { + return HAL_TIMEOUT; + } + } + } + } + + HAL_UART_Wait_Tx_Done(huart); + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Receive +* Description : Receive an amount of data in blocking mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be receive. +* Input : fu32_Timeout: Timeout duration. +* Output : HAL status +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size, uint32_t fu32_Timeout) +{ + uint32_t lu32_Timeout; + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + huart->lu32_RxCount = 0; + + /* Half duplex Use Tx GPIO Receive Data */ + if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + huart->Instance->CR2 |= UART_CR2_RX_SEL; + } + + while (fu32_Size--) + { + if (fu32_Timeout == 0) + { + while(huart->Instance->FR & UART_FR_RXFE); + + *fu8_Data++ = huart->Instance->DR; + + huart->lu32_RxCount++; + } + else + { + lu32_Timeout = fu32_Timeout * 256; + + while(huart->Instance->FR & UART_FR_RXFE) + { + if (lu32_Timeout-- == 0) + { + /* Clear Half duplex */ + huart->Instance->CR2 &= ~UART_CR2_RX_SEL; + + return HAL_TIMEOUT; + } + } + + *fu8_Data++ = huart->Instance->DR; + + huart->lu32_RxCount++; + } + } + + /* Clear Half duplex */ + huart->Instance->CR2 &= ~UART_CR2_RX_SEL; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Transmit_IT +* Description : Send an amount of data in interrupt mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be receive. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_TxBusy == true) + { + return HAL_BUSY; + } + + if (fu32_Size == 0 || fu8_Data == NULL) + { + return HAL_ERROR; + } + + huart->lu32_TxSize = fu32_Size; + huart->lu32_TxCount = 0; + huart->lu8_TxData = fu8_Data; + huart->lu8_TxBusy = true; + + /* Clear TXI Status */ + huart->Instance->ICR = UART_ICR_TXI; + /* FIFO Enable */ + SET_BIT(huart->Instance->LCRH, UART_LCRH_FEN); + /*FIFO Select*/ + SET_BIT(huart->Instance->IFLS,UART_TX_FIFO_1_2); + + for(;;) + { + /*Data Size less than 16Byte */ + if(fu32_Size == huart->lu32_TxCount) + { + huart->lu8_TxBusy = false; + + while ((huart->Instance->FR & UART_FR_BUSY)){} + + HAL_UART_TxCpltCallback(huart); + + return HAL_OK; + } + if(READ_BIT(huart->Instance->FR, UART_FR_TXFF)) + { + break; + } + huart->Instance->DR = huart->lu8_TxData[huart->lu32_TxCount++]; + } + + /* Enable TX interrupt */ + huart->Instance->IE |= UART_IE_TXI; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Receive_IT +* Description : Receive an amount of data in interrupt mode. +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_RxBusy == true) + { + return HAL_BUSY; + } + + if (fu32_Size == 0 || fu8_Data == NULL) + { + return HAL_ERROR; + } + + huart->lu32_RxSize = fu32_Size; + huart->lu32_RxCount = 0; + huart->lu8_RxData = fu8_Data; + huart->lu8_RxBusy = true; + + /* Clear RXI Status */ + huart->Instance->ICR = UART_ICR_RXI; + /* FIFO Enable */ + SET_BIT(huart->Instance->LCRH, UART_LCRH_FEN); + /*FIFO Select*/ + MODIFY_REG(huart->Instance->IFLS, UART_IFLS_RXIFLSEL, UART_RX_FIFO_1_2); + huart->lu32_fifo_level_minus1 = 8-1; // 16/2 - 1 + /* Enable the UART Errors interrupt */ + SET_BIT(huart->Instance->IE,UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI); + /* Enable RX and RTI interrupt */ + SET_BIT(huart->Instance->IE,UART_IE_RXI|UART_IE_RTI); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Transmit_DMA +* Description : Send an amount of data in DMA mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be Send. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_TxBusy == true) + { + return HAL_BUSY; + } + + if (fu32_Size == 0 || fu8_Data == NULL) + { + return HAL_ERROR; + } + + huart->Instance->DMACR |= UART_DMACR_TXDMAE; + + if (HAL_DMA_Start_IT(huart->HDMA_Tx, (uint32_t)fu8_Data, (uint32_t)(&huart->Instance->DR), fu32_Size)) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Receive_DMA +* Description : Receive an amount of data in DMA mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be receive. +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_RxBusy == true) + { + return HAL_BUSY; + } + + if (fu32_Size == 0 || fu8_Data == NULL) + { + return HAL_ERROR; + } + + huart->Instance->DMACR |= UART_DMACR_RXDMAE; + + if (HAL_DMA_Start_IT(huart->HDMA_Rx, (uint32_t)(&huart->Instance->DR), (uint32_t)fu8_Data, fu32_Size)) + { + return HAL_ERROR; + } + + return HAL_OK; +} + + + +/********************************************************************************* +* Function : HAL_UART_TxCpltCallback +* Description : Tx Transfer completed callbacks. +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file. + */ +} + +/********************************************************************************* +* Function : HAL_UART_RxCpltCallback +* Description : Rx Transfer completed callbacks. +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file. + */ +} + +/********************************************************************************* +* Function : HAL_UART_ErrorCallBack +* Description : Recv Error callbacks. +* Input : +* Output : +**********************************************************************************/ +__weak void HAL_UART_ErrorCallBack(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_ErrorCallBack could be implemented in the user file. + */ +} + +/********************************************************************************* +* Function : UART_Config_BaudRate +* Description : Config BaudRate +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +static void UART_Config_BaudRate(UART_HandleTypeDef *huart) +{ + uint32_t lu32_PCLK; + uint32_t lu32_IBAUD, lu32_FBAUD; + uint64_t lu64_TempValue; + + lu32_PCLK = System_Get_APBClock(); + + /* Integral part */ + lu32_IBAUD = lu32_PCLK / (huart->Init.BaudRate * 16); + + /* Fractional part */ + lu64_TempValue = lu32_PCLK % (huart->Init.BaudRate * 16); + lu64_TempValue = (lu64_TempValue * 1000000) / (huart->Init.BaudRate * 16); + lu32_FBAUD = (lu64_TempValue * 64 + 500000) / 1000000; + + if (lu32_FBAUD >= 64) + { + huart->Instance->IBRD = lu32_IBAUD + 1; + huart->Instance->FBRD = 0; + } + else + { + huart->Instance->IBRD = lu32_IBAUD; + huart->Instance->FBRD = lu32_FBAUD; + } +} + +/********************************************************************************* +* Function : HAL_UART_GetState +* Description : Return the uart State +* Input : +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if(huart->lu8_TxBusy || huart->lu8_RxBusy) + { + return HAL_BUSY; + } + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_UART_GetError +* Description : Return the uart Error +* Input : +* Output : +**********************************************************************************/ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/********************************************************************************* +* Function : HAL_UART_Abort +* Description : Abort ongoing transfers(blocking mode) +* Input : UART handle +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + /*disble all interrupt*/ + huart->Instance->IE =0x00; + + /* Disable the UART DMA Tx request if enable */ + if(READ_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE)) + { + CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE); + + /* Abort the UART Tx Channel */ + if(huart->HDMA_Tx) + { + /*Set the UART DMA Abort callback to Null */ + huart->HDMA_Tx->DMA_ITC_Callback =NULL; + + if(HAL_DMA_Abort(huart->HDMA_Tx)!=HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + /* Disable the UART DMA Rx request if enable */ + if(READ_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE)) + { + CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE); + + /* Abort the UART Rx Channel */ + if(huart->HDMA_Rx) + { + /*Set the UART DMA Abort callback to Null */ + huart->HDMA_Rx->DMA_ITC_Callback =NULL; + + if(HAL_DMA_Abort(huart->HDMA_Rx)!=HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + /*Reset Tx and Rx Transfer size*/ + huart->lu32_TxSize = 0; + huart->lu32_RxSize = 0; + + /* Restore huart->lu8_TxBusy and huart->lu8_RxBusy to Ready */ + huart->lu8_TxBusy = false; + huart->lu8_RxBusy = false; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_DMAPause +* Description : Pause the DMA Transfer +* Input : UART handle +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if(READ_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE)) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE); + } + + if (READ_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE)) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_FEI); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE); + } + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_UART_DMAResume +* Description : Resume the DMA Transfer +* Input : UART handle +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_TxBusy == false) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE); + } + + if (huart->lu8_RxBusy == false) + { + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_FEI); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE); + } + + return HAL_OK; +} + +#if 0 +/********************************************************************************* +* Function : fputc +* Description : +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +int fputc(int ch, FILE *f) +{ + if (Uart_Debug == NULL) + { + return 0; + } + + Uart_Debug->DR = ch; + + while ((Uart_Debug->FR & UART_FR_BUSY)); + + return ch; +} +#endif diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART_EX.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART_EX.c new file mode 100644 index 0000000000..5d5f2e2a70 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART_EX.c @@ -0,0 +1,244 @@ +/* + ****************************************************************************** + * @file HAL_UART_EX.c + * @version V1.0.0 + * @date 2021 + * @brief LIN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the extensional module: Local Interconnect Network Peripheral (LIN). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/************************************************************************ + * function : HAL_UART_LIN_Master_Transmit + * Description: Uart lin master transmit data + * input :none + * UART_HandleTypeDef *huart: Serial port number + * uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. + * uint8_t Lin_Id: LIN id + * uint8_t *pData: point to the transmit data buffer. + * uint8_t Size: Transmit buffer Size. + * return: none + ************************************************************************/ +void HAL_UART_LIN_Master_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size) +{ + uint8_t Lin_P0,Lin_P1,ucI; + uint16_t Lin_Check_Sum = 0; + + if((Size>8)||(pData == 0)) + return; + + CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI); + huart->Instance->CR = 0x0101; //disable uart_rx + + MODIFY_REG(huart->Instance->BCNT, UART_EX_BCNT_VALUE_MASK, (13)<Instance->BCNT, UART_EX_BCNT_START); + SET_BIT(huart->Instance->LCRH, UART_LCRH_BRK); + + while(!(READ_BIT(huart->Instance->RIS, UART_EX_RIS_BCNTI))){} //Check BCNTI. + CLEAR_BIT(huart->Instance->LCRH, UART_LCRH_BRK); + + HAL_UART_Transmit(huart, (uint8_t*)"\x55", 1, 0); //Transmit sync field + + Lin_Id &= 0x3F; //Lin address check, 0-63. + Lin_P0 = (Lin_Id^(Lin_Id>>1)^(Lin_Id>>2)^(Lin_Id>>4))&0x01; //P0 = ID0^ID1^ID2^ID4 + Lin_P1 = (~((Lin_Id>>1)^(Lin_Id>>3)^(Lin_Id>>4)^(Lin_Id>>5)))&0x01; //P1 = ~(ID1^ID3^ID4^ID5) + Lin_Id = Lin_Id | (Lin_P0<<6) | (Lin_P1<<7); + + HAL_UART_Transmit(huart, &Lin_Id, 1, 0); //Transmit pid field + + if((Lin_Version==UART_LIN_V2DX)&&(Lin_Id !=0x3C && Lin_Id!=0x3D)) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + if(Size) + { + for(ucI=0;ucI0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + + HAL_UART_Transmit(huart, pData, Size, 0); //Transmit data field + + HAL_UART_Transmit(huart, (uint8_t*)&Lin_Check_Sum, 1, 0); //Transmit Lin_Check_Sum field + } +} + +/************************************************************************ + * function : HAL_UART_LIN_Slave_Transmit + * Description: Uart lin slave transmit data + * input :none + * UART_HandleTypeDef *huart: Serial port number + * uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. + * uint8_t Lin_Id: LIN id + * uint8_t *pData: point to the transmit data buffer. + * uint8_t Size: Transmit buffer Size. + * return: none + ************************************************************************/ +void HAL_UART_LIN_Slave_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size) +{ + uint8_t ucI; + uint16_t Lin_Check_Sum = 0; + + if((Size>8)||(pData == 0)) + return; + + CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI);//disable LBDI int + huart->Instance->CR = 0x0101; //disable uart_rx + + if((Lin_Version==UART_LIN_V2DX)&&(Lin_Id !=0x3C && Lin_Id!=0x3D)) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + for(ucI=0;ucI0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + + HAL_UART_Transmit(huart, pData, Size, 0); //Transmit data field + + HAL_UART_Transmit(huart, (uint8_t*)&Lin_Check_Sum, 1, 0); //Transmit Lin_Check_Sum field +} + +/************************************************************************ + * function : HAL_UART_LIN_Master_Receive + * Description: Uart lin master receive data + * input :none + * UART_HandleTypeDef *huart: Serial port number + * uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. + * uint8_t Lin_Id: LIN id + * uint8_t *pData: point to the data buffer. + * return: uint8_t RxSize + ************************************************************************/ +uint8_t HAL_UART_LIN_Master_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint32_t Timeout) +{ + uint8_t ucI,RxSize; + uint8_t Lin_Rx_Buf[16]; + uint16_t Lin_Check_Sum = 0; + + if(pData == 0) + return 0; + + huart->Instance->CR = 0x0201; //disable uart_tx + huart->Instance->ICR = 0xfff; //clear int + huart->Instance->LCRH = 0x70; //8 data bit,1 stop bit,0 verify bit,enable FIFO + huart->Instance->IFLS = 0x12; //FIFO send and receive number is 8 + huart->Instance->IE = 0x00; //Disable all interrupt + + HAL_UART_Receive(huart, Lin_Rx_Buf, sizeof(Lin_Rx_Buf), Timeout); + + if((Lin_Version==UART_LIN_V2DX)&&(Lin_Id !=0x3C && Lin_Id!=0x3D)) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + if(huart->lu32_RxCount) + { + for(ucI=0;ucI<(huart->lu32_RxCount-1);ucI++) + { + Lin_Check_Sum += Lin_Rx_Buf[ucI]; + if(Lin_Check_Sum>0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + if((uint8_t)Lin_Check_Sum == Lin_Rx_Buf[ucI]) + { + RxSize = huart->lu32_RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0xFF; + } + else + RxSize = 0; + + return RxSize; +} + +/************************************************************************ + * function : HAL_UART_LIN_Slave_Receive + * Description: Uart lin slave receive head + * input :none + * UART_HandleTypeDef *huart: Serial port number + * uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. + * uint8_t *pData: point to the data buffer. + * return: uint8_t RxSize + ************************************************************************/ +uint8_t HAL_UART_LIN_Slave_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t *pData, uint32_t Timeout) +{ + uint8_t ucI,RxSize; + uint8_t Lin_Rx_Buf[16]; + uint16_t Lin_Check_Sum = 0; + uint32_t u32_Timeout; + + if(pData == 0) + return 0; + + huart->Instance->CR = 0x0201; //disable uart_tx + huart->Instance->ICR = 0xfff; //clear int + CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI); //Disable LBDI int + + if (Timeout == 0) + { + while(!READ_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI)); + } + else + { + u32_Timeout = Timeout * 0xFF; + + while(!READ_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI)) + { + if (u32_Timeout-- == 0) + { + return 0; + } + } + } + CLEAR_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI); + + huart->Instance->LCRH = 0x70; //8 data bit,1 stop bit,0 verify bit,enable FIFO + huart->Instance->IFLS = 0x12; //FIFO send and receive number is 8 + huart->Instance->IE = 0x00; //Disable all interrupt + + HAL_UART_Receive(huart, Lin_Rx_Buf, sizeof(Lin_Rx_Buf), Timeout); //waitting rx completed. + + if(huart->lu32_RxCount > 3) + { + if((Lin_Version==UART_LIN_V2DX)&&(Lin_Rx_Buf[2] !=0x3C && Lin_Rx_Buf[2]!=0x3D)) + Lin_Check_Sum = Lin_Rx_Buf[2]; //LIN 2.X check sum calc with PID. + + if(huart->lu32_RxCount) + { + for(ucI=3;ucI<(huart->lu32_RxCount-1);ucI++) + { + Lin_Check_Sum += Lin_Rx_Buf[ucI]; + if(Lin_Check_Sum>0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + if((uint8_t)Lin_Check_Sum == Lin_Rx_Buf[ucI]) + { + RxSize = huart->lu32_RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0xFF; + } + } + else if(huart->lu32_RxCount<=3) + { + RxSize = huart->lu32_RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0; + + return RxSize; +} diff --git a/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_WDT.c b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_WDT.c new file mode 100644 index 0000000000..d0a30d4ead --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_WDT.c @@ -0,0 +1,117 @@ +/*********************************************************************** + * Filename : HAL_WDT.c + * Description : HAL WDT driver source file + * Author(s) : CWT + * version : V1.0 + * Modify date : 2020-04-17 + ***********************************************************************/ +#include "ACM32Fxx_HAL.h" + +/************************************************************************ + * function : HAL_WDT_Feed + * Description: WDT feed. + * input : + * none + * return: none + ************************************************************************/ +void HAL_WDT_Feed(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->FEED = 0xAA55A55A; +} +/************************************************************************ + * function : HAL_WDT_IRQHandler + * Description: WDT interrupt service routine. + * input : + * none + * return: none + ************************************************************************/ +void HAL_WDT_IRQHandler(WDT_HandleTypeDef* hwdt) +{ +#ifdef __GNUC__ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wunused-but-set-variable" +#endif + volatile uint32_t wdt_ris = 0; + wdt_ris = hwdt->Instance->RIS; + HAL_WDT_Feed(hwdt); + NVIC_ClearPendingIRQ(WDT_IRQn); +#ifdef __GNUC__ + #pragma GCC diagnostic pop +#endif +} + +/************************************************************************ + * function : HAL_WDT_Init + * Description: WDT initiation. + * input : + * pinit initiation parameters + * return: none + ************************************************************************/ +void HAL_WDT_Init(WDT_HandleTypeDef* hwdt) +{ + System_Module_Enable(EN_WDT); + System_Delay(1); + System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE); + System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_WDT, FUNC_ENABLE); + + hwdt->Instance->LOAD = hwdt->Init.WDTLoad; + hwdt->Instance->CTRL = (hwdt->Instance->CTRL & ~0x47) | (hwdt->Init.WDTDivisor) | (hwdt->Init.WDTMode << 6); + + if (WDT_MODE_INT == hwdt->Init.WDTMode) + { + hwdt->Instance->INTCLRTIME = hwdt->Init.WDTINTCLRTIME; + HAL_WDT_Int_Enable(hwdt); + } +} + +/************************************************************************ + * function : HAL_WDT_Start + * Description: WDT start + * input : none + * + * return: none + ************************************************************************/ +void HAL_WDT_Start(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->CTRL |= WDT_ENABLE; +} + +/************************************************************************ + * function : WDT_Stop + * Description: WDT stop + * input : none + * + * return: none + ************************************************************************/ +void HAL_WDT_Stop(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->CTRL &= WDT_DISABLE; +} + +/************************************************************************ + * function : WDT_Int_Enable + * Description: WDT int enable + * input : none + * + * return: none + ************************************************************************/ +void HAL_WDT_Int_Enable(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->CTRL |= WDT_INT_ENABLE; + NVIC_ClearPendingIRQ(WDT_IRQn); + NVIC_EnableIRQ(WDT_IRQn); +} + +/************************************************************************ + * function : WDT_Int_Disable + * Description: WDT int disable + * input : none + * + * return: none + ************************************************************************/ +void HAL_WDT_Int_Disable(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->CTRL &= WDT_INT_DISABLE; +} + + diff --git a/bsp/acm32f0x0-nucleo/libraries/SConscript b/bsp/acm32f0x0-nucleo/libraries/SConscript new file mode 100644 index 0000000000..8f7a97ad30 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/libraries/SConscript @@ -0,0 +1,34 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +src = Split(""" +Device/System_ACM32F0x0.c +HAL_Driver/Src/HAL_DMA.c +HAL_Driver/Src/HAL_ADC.c +HAL_Driver/Src/HAL_GPIO.c +HAL_Driver/Src/HAL_WDT.c +HAL_Driver/Src/HAL_IWDT.c +HAL_Driver/Src/HAL_UART.c +HAL_Driver/Src/HAL_TIMER.c +HAL_Driver/Src/HAL_EXTI.c +""") + + +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['Device/Startup_ACM32F0x0_gcc.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['Device/Startup_ACM32F0x0.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['Device/Startup_ACM32F0x0_iar.s'] + +path = [cwd + '/HAL_Driver/Inc', + cwd + '/Device', + cwd + '/CMSIS'] + +group = DefineGroup('ACM32_HAL', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/acm32f0x0-nucleo/project.ewp b/bsp/acm32f0x0-nucleo/project.ewp new file mode 100644 index 0000000000..b5dd3214c4 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/project.ewp @@ -0,0 +1,2356 @@ + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + ACM32_HAL + + $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_IWDT.c + + + $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_Uart.c + + + $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_EXTI.c + + + $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_DMA.c + + + $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_TIMER.c + + + $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_ADC.c + + + $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_WDT.c + + + $PROJ_DIR$\libraries\Device\Startup_ACM32F0x0_iar.s + + + $PROJ_DIR$\libraries\HAL_Driver\Src\HAL_GPIO.c + + + $PROJ_DIR$\libraries\Device\System_ACM32F0x0.c + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + CPU + + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m0\cpuport.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m0\context_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\..\..\components\drivers\hwtimer\hwtimer.c + + + $PROJ_DIR$\..\..\components\drivers\misc\adc.c + + + $PROJ_DIR$\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\watchdog\watchdog.c + + + + Drivers + + $PROJ_DIR$\drivers\drv_uart.c + + + $PROJ_DIR$\drivers\drv_gpio.c + + + $PROJ_DIR$\drivers\led.c + + + $PROJ_DIR$\drivers\drv_wdt.c + + + $PROJ_DIR$\drivers\drv_adc.c + + + $PROJ_DIR$\drivers\drv_hwtimer.c + + + $PROJ_DIR$\drivers\board.c + + + + finsh + + $PROJ_DIR$\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_init.c + + + + Kernel + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\timer.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\components.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + + libc + + $PROJ_DIR$\..\..\components\libc\compilers\common\time.c + + + $PROJ_DIR$\..\..\components\libc\compilers\common\stdlib.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\stdio.c + + + + utestcases + + diff --git a/bsp/stm32/stm32f072-st-nucleo/project.eww b/bsp/acm32f0x0-nucleo/project.eww similarity index 100% rename from bsp/stm32/stm32f072-st-nucleo/project.eww rename to bsp/acm32f0x0-nucleo/project.eww diff --git a/bsp/acm32f0x0-nucleo/project.uvoptx b/bsp/acm32f0x0-nucleo/project.uvoptx new file mode 100644 index 0000000000..72665569be --- /dev/null +++ b/bsp/acm32f0x0-nucleo/project.uvoptx @@ -0,0 +1,1026 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ACM32F0x0 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F0x0 -FS00 -FL020000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + 0 + UL2V8M + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 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0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 3 + 15 + 2 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 4 + 17 + 1 + 0 + 0 + 0 + ..\..\components\drivers\hwtimer\hwtimer.c + hwtimer.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\..\components\drivers\misc\adc.c + adc.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + ..\..\components\drivers\watchdog\watchdog.c + watchdog.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 5 + 29 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + drivers\drv_wdt.c + drv_wdt.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + drivers\drv_hwtimer.c + drv_hwtimer.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + drivers\drv_adc.c + drv_adc.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_node.c + finsh_node.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_parser.c + finsh_parser.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_vm.c + finsh_vm.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_compiler.c + finsh_compiler.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_heap.c + finsh_heap.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_ops.c + finsh_ops.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_error.c + 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0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + ..\..\src\device.c + device.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 8 + 61 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 8 + 62 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\libc.c + libc.c + 0 + 0 + + + 8 + 63 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 8 + 64 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\time.c + time.c + 0 + 0 + + + 8 + 65 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\stdlib.c + stdlib.c + 0 + 0 + + + + diff --git a/bsp/acm32f0x0-nucleo/project.uvprojx b/bsp/acm32f0x0-nucleo/project.uvprojx new file mode 100644 index 0000000000..19b89df9c9 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/project.uvprojx @@ -0,0 +1,768 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ACM32F0x0 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + ACM32F0x0 + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output rtthread.bin ./build/keil/Obj/acm32f030.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + libraries\HAL_Driver\Inc;libraries\Device;libraries\CMSIS;applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + ACM32_HAL + + + HAL_IWDT.c + 1 + libraries\HAL_Driver\Src\HAL_IWDT.c + + + HAL_UART.c + 1 + libraries\HAL_Driver\Src\HAL_UART.c + + + HAL_EXTI.c + 1 + libraries\HAL_Driver\Src\HAL_EXTI.c + + + HAL_DMA.c + 1 + libraries\HAL_Driver\Src\HAL_DMA.c + + + HAL_TIMER.c + 1 + libraries\HAL_Driver\Src\HAL_TIMER.c + + + HAL_ADC.c + 1 + libraries\HAL_Driver\Src\HAL_ADC.c + + + Startup_ACM32F0x0.s + 2 + libraries\Device\Startup_ACM32F0x0.s + + + HAL_WDT.c + 1 + libraries\HAL_Driver\Src\HAL_WDT.c + + + HAL_GPIO.c + 1 + libraries\HAL_Driver\Src\HAL_GPIO.c + + + System_ACM32F0x0.c + 1 + libraries\Device\System_ACM32F0x0.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m0\cpuport.c + + + + + DeviceDrivers + + + hwtimer.c + 1 + ..\..\components\drivers\hwtimer\hwtimer.c + + + adc.c + 1 + ..\..\components\drivers\misc\adc.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + watchdog.c + 1 + ..\..\components\drivers\watchdog\watchdog.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_wdt.c + 1 + drivers\drv_wdt.c + + + drv_hwtimer.c + 1 + drivers\drv_hwtimer.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + drv_adc.c + 1 + drivers\drv_adc.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + + + finsh + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + Kernel + + + components.c + 1 + ..\..\src\components.c + + + timer.c + 1 + ..\..\src\timer.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + idle.c + 1 + ..\..\src\idle.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + thread.c + 1 + ..\..\src\thread.c + + + irq.c + 1 + ..\..\src\irq.c + + + object.c + 1 + ..\..\src\object.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + mem.c + 1 + ..\..\src\mem.c + + + clock.c + 1 + ..\..\src\clock.c + + + device.c + 1 + ..\..\src\device.c + + + + + libc + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/acm32f0x0-nucleo/rtconfig.h b/bsp/acm32f0x0-nucleo/rtconfig.h new file mode 100644 index 0000000000..0e4fdd245a --- /dev/null +++ b/bsp/acm32f0x0-nucleo/rtconfig.h @@ -0,0 +1,223 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40004 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_HWTIMER +#define RT_USING_PIN +#define RT_USING_ADC +#define RT_USING_WDT + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_SERIES_ACM32F0 + +/* Hardware Drivers Config */ + +#define SOC_ACM32F070RBT7 +#define SOC_SRAM_START_ADDR 0x20000000 +#define SOC_SRAM_SIZE 0x20 +#define SOC_FLASH_START_ADDR 0x00000000 +#define SOC_FLASH_SIZE 0x80 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +/* Hardware GPIO */ + +#define BSP_USING_GPIO1 +#define BSP_USING_GPIO2 +#define BSP_USING_ADC + +/* Hardware UART */ + +#define BSP_USING_UART1 +#define BSP_USING_UART2 +#define BSP_UART2_RX_USING_DMA +#define BSP_UART2_TX_USING_DMA +#define BSP_USING_UART3 +#define BSP_UART3_RX_USING_DMA +#define BSP_UART3_TX_USING_DMA + +/* Hardware I2C */ + + +/* Hardware CAN */ + + +/* Hardware TIMER */ + +#define BSP_USING_TIM1 +#define BSP_USING_TIM3 +#define BSP_USING_TIM6 +#define BSP_USING_TIM14 +#define BSP_USING_TIM15 +#define BSP_USING_TIM16 +#define BSP_USING_TIM17 + +/* Hardware WDT */ + +#define BSP_USING_WDT +#define BSP_USING_IWDT + +/* Hardware SPI */ + + +/* Hardware CRYPTO */ + + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/acm32f0x0-nucleo/rtconfig.py b/bsp/acm32f0x0-nucleo/rtconfig.py new file mode 100644 index 0000000000..e9814d2286 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'D:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'D:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -Os -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + CXXFLAGS = CFLAGS + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/acm32f0x0-nucleo/template.ewp b/bsp/acm32f0x0-nucleo/template.ewp new file mode 100644 index 0000000000..1ef0885c70 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/template.ewp @@ -0,0 +1,2074 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/acm32f0x0-nucleo/template.eww b/bsp/acm32f0x0-nucleo/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/acm32f0x0-nucleo/template.uvoptx b/bsp/acm32f0x0-nucleo/template.uvoptx new file mode 100644 index 0000000000..71abd8fd0d --- /dev/null +++ b/bsp/acm32f0x0-nucleo/template.uvoptx @@ -0,0 +1,182 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ACM32F0x0 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F0x0 -FS00 -FL020000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + 0 + UL2V8M + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/acm32f0x0-nucleo/template.uvprojx b/bsp/acm32f0x0-nucleo/template.uvprojx new file mode 100644 index 0000000000..b961bea0a4 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ACM32F0x0 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + ACM32F0x0 + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output rtthread.bin ./build/keil/Obj/acm32f030.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + RT_USING_ARM_LIBC + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c index 7c40ffbdad..dc98fe7c4d 100644 --- a/bsp/at91sam9260/platform/interrupt.c +++ b/bsp/at91sam9260/platform/interrupt.c @@ -413,7 +413,6 @@ void list_irq(void) } #include -FINSH_FUNCTION_EXPORT(list_irq, list system irq); #ifdef FINSH_USING_MSH int cmd_list_irq(int argc, char** argv) @@ -421,8 +420,7 @@ int cmd_list_irq(int argc, char** argv) list_irq(); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.); - +MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq); #endif #endif #endif diff --git a/bsp/at91sam9260/platform/reset.c b/bsp/at91sam9260/platform/reset.c index 4b5462a9e1..6679ab57fe 100644 --- a/bsp/at91sam9260/platform/reset.c +++ b/bsp/at91sam9260/platform/reset.c @@ -38,15 +38,14 @@ int cmd_reset(int argc, char** argv) rt_hw_cpu_reset(); return 0; } +MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system); int cmd_shutdown(int argc, char** argv) { rt_hw_cpu_shutdown(); return 0; } - -FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); -FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.); +MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system); #endif #endif diff --git a/bsp/at91sam9g45/platform/interrupt.c b/bsp/at91sam9g45/platform/interrupt.c index c8afc998f1..c3dd99e798 100644 --- a/bsp/at91sam9g45/platform/interrupt.c +++ b/bsp/at91sam9g45/platform/interrupt.c @@ -445,7 +445,6 @@ void list_irq(void) } #include -FINSH_FUNCTION_EXPORT(list_irq, list system irq); #ifdef FINSH_USING_MSH int cmd_list_irq(int argc, char** argv) @@ -453,8 +452,7 @@ int cmd_list_irq(int argc, char** argv) list_irq(); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.); - +MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq); #endif #endif #endif diff --git a/bsp/at91sam9g45/platform/reset.c b/bsp/at91sam9g45/platform/reset.c index 8abbf7a9fb..33d6f97283 100644 --- a/bsp/at91sam9g45/platform/reset.c +++ b/bsp/at91sam9g45/platform/reset.c @@ -30,7 +30,6 @@ void machine_shutdown(void) #ifdef RT_USING_FINSH #include -FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) @@ -38,15 +37,14 @@ int cmd_reset(int argc, char** argv) rt_hw_cpu_reset(); return 0; } +MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system); int cmd_shutdown(int argc, char** argv) { rt_hw_cpu_shutdown(); return 0; } - -FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); -FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.); +MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system); #endif #endif diff --git a/bsp/beaglebone/applications/board.c b/bsp/beaglebone/applications/board.c index ff25dd7dd7..e1e1f8cae2 100644 --- a/bsp/beaglebone/applications/board.c +++ b/bsp/beaglebone/applications/board.c @@ -163,5 +163,4 @@ void rt_hw_cpu_reset(void) REG32(PRM_DEVICE(prcm_base)) = 0x1; RT_ASSERT(0); } -FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu); -FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, __cmd_reboot, reboot the cpu); +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu); diff --git a/bsp/dm365/drivers/davinci_emac.c b/bsp/dm365/drivers/davinci_emac.c index 7ad539fb09..b164bf7aaa 100644 --- a/bsp/dm365/drivers/davinci_emac.c +++ b/bsp/dm365/drivers/davinci_emac.c @@ -1751,7 +1751,7 @@ int cmd_dump_emac_stats(int argc, char** argv) dump_emac_stats(); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_dump_emac_stats, __cmd_dump_emac_stats, dump emac statistics.); +MSH_CMD_EXPORT_ALIAS(cmd_dump_emac_stats, dump_emac_stats, dump emac statistics); #endif #endif diff --git a/bsp/dm365/platform/interrupt.c b/bsp/dm365/platform/interrupt.c index 6334072bcd..fb0d4d3d3e 100644 --- a/bsp/dm365/platform/interrupt.c +++ b/bsp/dm365/platform/interrupt.c @@ -286,8 +286,7 @@ int cmd_list_irq(int argc, char** argv) list_irq(); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.); - +MSH_CMD_EXPORT_ALIAS(cmd_list_irq, list_irq, list system irq); #endif #endif #endif diff --git a/bsp/dm365/platform/reset.c b/bsp/dm365/platform/reset.c index dc80fac76e..b706e5a4cc 100644 --- a/bsp/dm365/platform/reset.c +++ b/bsp/dm365/platform/reset.c @@ -39,7 +39,6 @@ void machine_shutdown() #ifdef RT_USING_FINSH #include -FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) @@ -47,15 +46,14 @@ int cmd_reset(int argc, char** argv) rt_hw_cpu_reset(); return 0; } +MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system); int cmd_shutdown(int argc, char** argv) { rt_hw_cpu_shutdown(); return 0; } - -FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); -FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.); +MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system); #endif #endif diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.c b/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.c index 9decb78d6d..27eb76cc84 100644 --- a/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.c +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.c @@ -22,7 +22,7 @@ static void reboot(uint8_t argc, char **argv) { rt_hw_cpu_reset(); } -FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System); +MSH_CMD_EXPORT(reboot, reboot system); #endif /* RT_USING_FINSH */ /* SysTick configuration */ diff --git a/bsp/gd32105c-eval/.config b/bsp/gd32105c-eval/.config new file mode 100644 index 0000000000..3642cdfa71 --- /dev/null +++ b/bsp/gd32105c-eval/.config @@ -0,0 +1,631 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +# CONFIG_RT_USING_I2C_BITOPS is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Hardware Drivers Config +# + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_SOC_SERIES_GD32F1=y +CONFIG_SOC_GD32105C=y +CONFIG_RT_USING_USART0=y +# CONFIG_RT_USING_USART1 is not set +# CONFIG_RT_USING_USART2 is not set +# CONFIG_RT_USING_UART3 is not set +CONFIG_RT_USING_SPI0=y +# CONFIG_RT_USING_SPI1 is not set +# CONFIG_RT_USING_SPI2 is not set +CONFIG_RT_USING_I2C0=y +# CONFIG_RT_USING_I2C1 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/gd32105c-eval/.ignore_format.yml b/bsp/gd32105c-eval/.ignore_format.yml new file mode 100644 index 0000000000..d570c52faf --- /dev/null +++ b/bsp/gd32105c-eval/.ignore_format.yml @@ -0,0 +1,8 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: + +dir_path: +- Libraries diff --git a/bsp/gd32105c-eval/Kconfig b/bsp/gd32105c-eval/Kconfig new file mode 100644 index 0000000000..3050d65e26 --- /dev/null +++ b/bsp/gd32105c-eval/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "drivers/Kconfig" + + + + + diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h new file mode 100644 index 0000000000..e525f3c0c6 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h @@ -0,0 +1,381 @@ +/*! + \file gd32f10x.h + \brief general definitions for GD32F10x + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_H +#define GD32F10X_H + +#ifdef cplusplus + extern "C" { +#endif + +/* define GD32F10x */ +#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) + /* #define GD32F10X_MD */ /*!< GD32F10X_MD: GD32 Medium density devices */ + /* #define GD32F10X_HD */ /*!< GD32F10X_HD: GD32 High density Value Line devices */ + /* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */ + /* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */ +#endif /* define GD32F10x */ + +#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) + #error "Please select the target GD32F10x device in gd32f10x.h file" +#endif /* undefine GD32F10x tip */ + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined HXTAL_VALUE +#ifdef GD32F10X_CL +#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ +#else +#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ +#endif /* HXTAL_VALUE */ +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* GD32F10x firmware library version number V2.0 */ +#define __GD32F10x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __GD32F10x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32F10x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F10x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F10x_STDPERIPH_VERSION ((__GD32F10x_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32F10x_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32F10x_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32F10x_STDPERIPH_VERSION_RC)) + +/* configuration of the Cortex-M3 processor and core peripherals */ +#define __MPU_PRESENT 0 /*!< GD32F10x do not provide MPU */ +#define __NVIC_PRIO_BITS 4 /*!< GD32F10x uses 4 bits for the priority levels */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ +/* define interrupt number */ +typedef enum IRQn +{ + /* Cortex-M3 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 system tick interrupt */ + + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ + RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ + FMC_IRQn = 4, /*!< FMC interrupt */ + RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ + ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ + +#ifdef GD32F10X_MD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ +#endif /* GD32F10X_MD */ + +#ifdef GD32F10X_HD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ + TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ + TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ + TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ + ADC2_IRQn = 47, /*!< ADC2 global interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + SDIO_IRQn = 49, /*!< SDIO global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ +#endif /* GD32F10X_HD */ + +#ifdef GD32F10X_XD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ + ADC2_IRQn = 47, /*!< ADC2 global interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + SDIO_IRQn = 49, /*!< SDIO global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */ +#endif /* GD32F10X_XD */ + +#ifdef GD32F10X_CL + CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */ + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ + TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ + TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ + ENET_IRQn = 61, /*!< ENET global interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS global interrupt */ +#endif /* GD32F10X_CL */ + +} IRQn_Type; + +/* includes */ +#include "core_cm3.h" +#include "system_gd32f10x.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ +#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ +#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ + +/* advanced peripheral bus 2 memory map */ +#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ + +/* advanced high performance bus 1 memory map */ +#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ +#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32f10x_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef cplusplus +} +#endif +#endif diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h new file mode 100644 index 0000000000..6bd00fb99d --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h @@ -0,0 +1,60 @@ +/*! + \file system_gd32f10x.h + \brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for + GD32F10x Device Series +*/ + +/* + Copyright (c) 2012 ARM LIMITED + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32F10X_H +#define SYSTEM_GD32F10X_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit(void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32F10X_H */ diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s new file mode 100644 index 0000000000..a3ffa4c752 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s @@ -0,0 +1,390 @@ +;/*! +; \file startup_gd32f10x_cl.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper Interrupt + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_IRQHandler ; 21:RCU + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break + DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line + DCD USBFS_WKUP_IRQHandler ; 58:USBFS WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt + DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt + DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; 64:EXMC + DCD 0 ; Reserved + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_IRQHandler [WEAK] + EXPORT TIMER0_UP_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_IRQHandler [WEAK] + EXPORT TIMER7_UP_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT ENET_WKUP_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_IRQHandler +TIMER0_UP_IRQHandler +TIMER0_TRG_CMT_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_IRQHandler +TIMER7_UP_IRQHandler +TIMER7_TRG_CMT_IRQHandler +TIMER7_Channel_IRQHandler +EXMC_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +ENET_IRQHandler +ENET_WKUP_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler + + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s new file mode 100644 index 0000000000..fe768cc3a9 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s @@ -0,0 +1,371 @@ +;/*! +; \file startup_gd32f10x_hd.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper Interrupt + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_IRQHandler ; 21:RCU + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break + DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt + DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt + DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD ADC2_IRQHandler ; 63:ADC2 + DCD EXMC_IRQHandler ; 64:EXMC + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] + EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_IRQHandler [WEAK] + EXPORT TIMER0_UP_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBD_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_IRQHandler [WEAK] + EXPORT TIMER7_UP_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_4_IRQHandler [WEAK] + + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +USBD_HP_CAN0_TX_IRQHandler +USBD_LP_CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_IRQHandler +TIMER0_UP_IRQHandler +TIMER0_TRG_CMT_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBD_WKUP_IRQHandler +TIMER7_BRK_IRQHandler +TIMER7_UP_IRQHandler +TIMER7_TRG_CMT_IRQHandler +TIMER7_Channel_IRQHandler +ADC2_IRQHandler +EXMC_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_4_IRQHandler + + + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s new file mode 100644 index 0000000000..c567fee5c1 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s @@ -0,0 +1,328 @@ +;/*! +; \file startup_gd32f10x_md.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper Interrupt + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_IRQHandler ; 21:RCU + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break + DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; 64:EXMC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] + EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_IRQHandler [WEAK] + EXPORT TIMER0_UP_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBD_WKUP_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +USBD_HP_CAN0_TX_IRQHandler +USBD_LP_CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_IRQHandler +TIMER0_UP_IRQHandler +TIMER0_TRG_CMT_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBD_WKUP_IRQHandler +EXMC_IRQHandler + + + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s new file mode 100644 index 0000000000..3db249b8e5 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s @@ -0,0 +1,371 @@ +;/*! +; \file startup_gd32f10x_xd.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper Interrupt + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_IRQHandler ; 21:RCU + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 global + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 global + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 global + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break Interrupt and TIMER11 global + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update Interrupt and TIMER12 global + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt and TIMER13 global + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD ADC2_IRQHandler ; 63:ADC2 + DCD EXMC_IRQHandler ; 64:EXMC + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] + EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBD_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_4_IRQHandler [WEAK] + + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +USBD_HP_CAN0_TX_IRQHandler +USBD_LP_CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBD_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +ADC2_IRQHandler +EXMC_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_4_IRQHandler + + + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s new file mode 100644 index 0000000000..8d614ecf3e --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s @@ -0,0 +1,529 @@ +;/*! +; \file startup_gd32f10x_cl.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt + DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 20,FMC + DCD RCU_IRQHandler ; Vector Number 21,RCU + DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 + DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 + DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 + DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 + DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; Vector Number 35,CAN0 TX + DCD CAN0_RX0_IRQHandler ; Vector Number 36,CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC + DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break + DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 + DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 + DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD SPI0_IRQHandler ; Vector Number 51,SPI0 + DCD SPI1_IRQHandler ; Vector Number 52,SPI1 + DCD USART0_IRQHandler ; Vector Number 53,USART0 + DCD USART1_IRQHandler ; Vector Number 54,USART1 + DCD USART2_IRQHandler ; Vector Number 55,USART2 + DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line + DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt + DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt + DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt + DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; Vector Number 64,EXMC + DCD 0 ; Reserved + DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 + DCD SPI2_IRQHandler ; Vector Number 67,SPI2 + DCD UART3_IRQHandler ; Vector Number 68,UART3 + DCD UART4_IRQHandler ; Vector Number 69,UART4 + DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 + DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 + DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; Vector Number 75,DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; Vector Number 76,DMA1 Channel4 + DCD ENET_IRQHandler ; Vector Number 77,Ethernet + DCD ENET_WKUP_IRQHandler ; Vector Number 78,Ethernet Wakeup through EXTI line + DCD CAN1_TX_IRQHandler ; Vector Number 79,CAN1 TX + DCD CAN1_RX0_IRQHandler ; Vector Number 80,CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; Vector Number 81,CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; Vector Number 82,CAN1 EWMC + DCD USBFS_IRQHandler ; Vector Number 83,USBFS +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, = SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_IRQHandler + B CAN0_TX_IRQHandler + + PUBWEAK CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_IRQHandler + B CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_IRQHandler + B TIMER0_BRK_IRQHandler + + PUBWEAK TIMER0_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_IRQHandler + B TIMER0_UP_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_IRQHandler + B TIMER0_TRG_CMT_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_IRQHandler + B TIMER7_BRK_IRQHandler + + PUBWEAK TIMER7_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_IRQHandler + B TIMER7_UP_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_IRQHandler + B TIMER7_TRG_CMT_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK ENET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_IRQHandler + B ENET_IRQHandler + + PUBWEAK ENET_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_WKUP_IRQHandler + B ENET_WKUP_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_EWMC_IRQHandler + B CAN1_EWMC_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + + + END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s new file mode 100644 index 0000000000..0cd9ade897 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s @@ -0,0 +1,491 @@ +;/*! +; \file startup_gd32f10x_hd.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt + DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 20,FMC + DCD RCU_IRQHandler ; Vector Number 21,RCU + DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 + DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 + DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 + DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 + DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC + DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break + DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 + DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 + DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD SPI0_IRQHandler ; Vector Number 51,SPI0 + DCD SPI1_IRQHandler ; Vector Number 52,SPI1 + DCD USART0_IRQHandler ; Vector Number 53,USART0 + DCD USART1_IRQHandler ; Vector Number 54,USART1 + DCD USART2_IRQHandler ; Vector Number 55,USART2 + DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt + DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt + DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt + DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare + DCD ADC2_IRQHandler ; Vector Number 63,ADC2 + DCD EXMC_IRQHandler ; Vector Number 64,EXMC + DCD SDIO_IRQHandler ; Vector Number 65,SDIO + DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 + DCD SPI2_IRQHandler ; Vector Number 67,SPI2 + DCD UART3_IRQHandler ; Vector Number 68,UART3 + DCD UART4_IRQHandler ; Vector Number 69,UART4 + DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 + DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 + DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 + DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, = SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK USBD_HP_CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_HP_CAN0_TX_IRQHandler + B USBD_HP_CAN0_TX_IRQHandler + + PUBWEAK USBD_LP_CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_LP_CAN0_RX0_IRQHandler + B USBD_LP_CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_IRQHandler + B TIMER0_BRK_IRQHandler + + PUBWEAK TIMER0_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_IRQHandler + B TIMER0_UP_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_IRQHandler + B TIMER0_TRG_CMT_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBD_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_WKUP_IRQHandler + B USBD_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_IRQHandler + B TIMER7_BRK_IRQHandler + + PUBWEAK TIMER7_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_IRQHandler + B TIMER7_UP_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_IRQHandler + B TIMER7_TRG_CMT_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_4_IRQHandler + B DMA1_Channel3_4_IRQHandler + + END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s new file mode 100644 index 0000000000..bc0d386613 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s @@ -0,0 +1,400 @@ +;/*! +; \file startup_gd32f10x_md.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt + DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 20,FMC + DCD RCU_IRQHandler ; Vector Number 21,RCU + DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 + DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 + DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 + DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 + DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC + DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break + DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 + DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 + DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD SPI0_IRQHandler ; Vector Number 51,SPI0 + DCD SPI1_IRQHandler ; Vector Number 52,SPI1 + DCD USART0_IRQHandler ; Vector Number 53,USART0 + DCD USART1_IRQHandler ; Vector Number 54,USART1 + DCD USART2_IRQHandler ; Vector Number 55,USART2 + DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; Vector Number 64,EXMC +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, = SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK USBD_HP_CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_HP_CAN0_TX_IRQHandler + B USBD_HP_CAN0_TX_IRQHandler + + PUBWEAK USBD_LP_CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_LP_CAN0_RX0_IRQHandler + B USBD_LP_CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_IRQHandler + B TIMER0_BRK_IRQHandler + + PUBWEAK TIMER0_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_IRQHandler + B TIMER0_UP_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_IRQHandler + B TIMER0_TRG_CMT_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBD_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_WKUP_IRQHandler + B USBD_WKUP_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s new file mode 100644 index 0000000000..4f52b7d5fa --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s @@ -0,0 +1,491 @@ +;/*! +; \file startup_gd32f10x_xd.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt + DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 20,FMC + DCD RCU_IRQHandler ; Vector Number 21,RCU + DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 + DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 + DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 + DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 + DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC + DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; Vector Number 40,TIMER0 Break and TIMER8 global + DCD TIMER0_UP_TIMER9_IRQHandler ; Vector Number 41,TIMER0 Update and TIMER9 global + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global + DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 + DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 + DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD SPI0_IRQHandler ; Vector Number 51,SPI0 + DCD SPI1_IRQHandler ; Vector Number 52,SPI1 + DCD USART0_IRQHandler ; Vector Number 53,USART0 + DCD USART1_IRQHandler ; Vector Number 54,USART1 + DCD USART2_IRQHandler ; Vector Number 55,USART2 + DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_TIMER11_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt and TIMER11 global + DCD TIMER7_UP_TIMER12_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt and TIMER12 global + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13 global + DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare + DCD ADC2_IRQHandler ; Vector Number 63,ADC2 + DCD EXMC_IRQHandler ; Vector Number 64,EXMC + DCD SDIO_IRQHandler ; Vector Number 65,SDIO + DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 + DCD SPI2_IRQHandler ; Vector Number 67,SPI2 + DCD UART3_IRQHandler ; Vector Number 68,UART3 + DCD UART4_IRQHandler ; Vector Number 69,UART4 + DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 + DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 + DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 + DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, = SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK USBD_HP_CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_HP_CAN0_TX_IRQHandler + B USBD_HP_CAN0_TX_IRQHandler + + PUBWEAK USBD_LP_CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_LP_CAN0_RX0_IRQHandler + B USBD_LP_CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_TIMER8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_TIMER8_IRQHandler + B TIMER0_BRK_TIMER8_IRQHandler + + PUBWEAK TIMER0_UP_TIMER9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_TIMER9_IRQHandler + B TIMER0_UP_TIMER9_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_TIMER10_IRQHandler + B TIMER0_TRG_CMT_TIMER10_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBD_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_WKUP_IRQHandler + B USBD_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_TIMER11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_TIMER11_IRQHandler + B TIMER7_BRK_TIMER11_IRQHandler + + PUBWEAK TIMER7_UP_TIMER12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_TIMER12_IRQHandler + B TIMER7_UP_TIMER12_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_TIMER13_IRQHandler + B TIMER7_TRG_CMT_TIMER13_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_4_IRQHandler + B DMA1_Channel3_4_IRQHandler + + END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c new file mode 100644 index 0000000000..699179711a --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c @@ -0,0 +1,1028 @@ +/*! + \file system_gd32f10x.c + \brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for + GD32F10x Device Series +*/ + +/* + Copyright (c) 2012 ARM LIMITED + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f10x.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/* use HXTAL (XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */ +//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + +#ifdef GD32F10X_CL + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + + RCU_CFG1 = 0x00000000U; +#else + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | + RCU_CFG0_USBDPSC | RCU_CFG0_PLLMF_4); +#endif /* GD32F10X_CL */ + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* reset HXTALEN, CKMEN and PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x009F0000U; +#elif defined(GD32F10X_CL) + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; +#endif + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; +#ifdef GD32F10X_CL + uint32_t predv0, predv1, pll1mf; +#endif /* GD32F10X_CL */ + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); + + /* PREDV0 input source clock divided by 2 */ + if(RCU_CFG0_PREDV0 == predv0sel){ + ck_src = HXTAL_VALUE / 2U; + } +#elif defined(GD32F10X_CL) + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + +#ifdef GD32F10X_CL + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } +#endif /* GD32F10X_CL */ + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL6; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL9; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL14; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL24; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/core_cm3.h b/bsp/gd32105c-eval/Libraries/CMSIS/core_cm3.h new file mode 100644 index 0000000000..1b661b4421 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/core_cm3.h @@ -0,0 +1,1638 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32105c-eval/Libraries/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..01089f1333 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32105c-eval/Libraries/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..856b4c3c61 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/CMSIS/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h new file mode 100644 index 0000000000..bb61cd73b5 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h @@ -0,0 +1,368 @@ +/*! + \file gd32f10x_adc.h + \brief definitions for the ADC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10x_ADC_H +#define GD32F10x_ADC_H + +#include "gd32f10x.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x400U) +#define ADC2 (ADC_BASE + 0x1800U) + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx x=0..2 */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ + +/* constants definitions */ +/* adc_stat register value */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +/* scan mode */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + +/* inserted channel group convert automatically */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ + +/* ADC sync mode */ +#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ +#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ +#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ +#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ + +/* adc_ctl1 register value */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* continuous mode */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* external trigger select for regular channel */ +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ +/* for ADC0 and ADC1 regular channel */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ +/* for ADC2 regular channel */ +#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */ +#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */ +#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */ +#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */ +#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */ +#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */ + +/* external trigger mode for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ +/* for ADC0 and ADC1 inserted channel */ +#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */ +#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ +/* for ADC2 inserted channel */ +#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */ +#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */ +#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */ +#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */ +#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ + +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ + +/* ADC interrupt */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* function declarations */ +/* initialization config */ +/* reset ADC */ +void adc_deinit(uint32_t adc_periph); +/* configure the ADC sync mode */ +void adc_mode_config(uint32_t mode); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); + +/* DMA config */ +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); + +/* regular group and inserted group config */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); + +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); + +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); +/* configure ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); + +/* get channel data */ +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); +/* read the last ADC0 and ADC1 conversion result data in sync mode */ +uint32_t adc_sync_mode_convert_value_read(void); + +/* watchdog config */ +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); + +/* interrupt & flag functions */ +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); +/* get the bit state of ADCx software start conversion */ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +/* get the bit state of ADCx software inserted channel start conversion */ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); + +#endif /* GD32F10x_ADC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h new file mode 100644 index 0000000000..73f93252fe --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h @@ -0,0 +1,230 @@ +/*! + \file gd32f10x_bkp.h + \brief definitions for the BKP + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_BKP_H +#define GD32F10X_BKP_H + +#include "gd32f10x.h" + +/* BKP definitions */ +#define BKP BKP_BASE /*!< BKP base address */ + +/* registers definitions */ +#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ +#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ +#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ +#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ +#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ +#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ +#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ +#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ +#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ +#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ +#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ +#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ +#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ +#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ +#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ +#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ +#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ +#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ +#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ +#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ +#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ +#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ +#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ +#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ +#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ +#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ +#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ +#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ +#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ +#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ +#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ +#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ +#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ +#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ +#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ +#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ +#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ +#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ +#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ +#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ +#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ +#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ +#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ +#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ +#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ + +/* bits definitions */ +/* BKP_DATA */ +#define BKP_DATA BITS(0,15) /*!< backup data */ + +/* BKP_OCTL */ +#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ +#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ +#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ +#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ + +/* BKP_TPCTL */ +#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ +#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ + +/* BKP_TPCS */ +#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ +#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ +#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ +#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ +#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ + +/* constants definitions */ +/* BKP data register number */ +typedef enum +{ + BKP_DATA_0 = 1, /*!< BKP data register 0 */ + BKP_DATA_1, /*!< BKP data register 1 */ + BKP_DATA_2, /*!< BKP data register 2 */ + BKP_DATA_3, /*!< BKP data register 3 */ + BKP_DATA_4, /*!< BKP data register 4 */ + BKP_DATA_5, /*!< BKP data register 5 */ + BKP_DATA_6, /*!< BKP data register 6 */ + BKP_DATA_7, /*!< BKP data register 7 */ + BKP_DATA_8, /*!< BKP data register 8 */ + BKP_DATA_9, /*!< BKP data register 9 */ + BKP_DATA_10, /*!< BKP data register 10 */ + BKP_DATA_11, /*!< BKP data register 11 */ + BKP_DATA_12, /*!< BKP data register 12 */ + BKP_DATA_13, /*!< BKP data register 13 */ + BKP_DATA_14, /*!< BKP data register 14 */ + BKP_DATA_15, /*!< BKP data register 15 */ + BKP_DATA_16, /*!< BKP data register 16 */ + BKP_DATA_17, /*!< BKP data register 17 */ + BKP_DATA_18, /*!< BKP data register 18 */ + BKP_DATA_19, /*!< BKP data register 19 */ + BKP_DATA_20, /*!< BKP data register 20 */ + BKP_DATA_21, /*!< BKP data register 21 */ + BKP_DATA_22, /*!< BKP data register 22 */ + BKP_DATA_23, /*!< BKP data register 23 */ + BKP_DATA_24, /*!< BKP data register 24 */ + BKP_DATA_25, /*!< BKP data register 25 */ + BKP_DATA_26, /*!< BKP data register 26 */ + BKP_DATA_27, /*!< BKP data register 27 */ + BKP_DATA_28, /*!< BKP data register 28 */ + BKP_DATA_29, /*!< BKP data register 29 */ + BKP_DATA_30, /*!< BKP data register 30 */ + BKP_DATA_31, /*!< BKP data register 31 */ + BKP_DATA_32, /*!< BKP data register 32 */ + BKP_DATA_33, /*!< BKP data register 33 */ + BKP_DATA_34, /*!< BKP data register 34 */ + BKP_DATA_35, /*!< BKP data register 35 */ + BKP_DATA_36, /*!< BKP data register 36 */ + BKP_DATA_37, /*!< BKP data register 37 */ + BKP_DATA_38, /*!< BKP data register 38 */ + BKP_DATA_39, /*!< BKP data register 39 */ + BKP_DATA_40, /*!< BKP data register 40 */ + BKP_DATA_41, /*!< BKP data register 41 */ +}bkp_data_register_enum; + +/* BKP register */ +#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) +#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) + +/* get data of BKP data register */ +#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + +/* RTC clock calibration value */ +#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/* RTC output selection */ +#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ +#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ + +/* tamper pin active level */ +#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ +#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ + +/* tamper flag */ +#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ + +/* tamper interrupt flag */ +#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ +/* function declarations */ +/* reset BKP registers */ +void bkp_deinit(void); +/* write BKP data register */ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); +/* read BKP data register */ +uint16_t bkp_data_read(bkp_data_register_enum register_number); + +/* RTC related functions */ +/* enable RTC clock calibration output */ +void bkp_rtc_calibration_output_enable(void); +/* disable RTC clock calibration output */ +void bkp_rtc_calibration_output_disable(void); +/* enable RTC alarm or second signal output */ +void bkp_rtc_signal_output_enable(void); +/* disable RTC alarm or second signal output */ +void bkp_rtc_signal_output_disable(void); +/* select RTC output */ +void bkp_rtc_output_select(uint16_t outputsel); +/* set RTC clock calibration value */ +void bkp_rtc_calibration_value_set(uint8_t value); + +/* tamper pin related functions */ +/* enable tamper pin detection */ +void bkp_tamper_detection_enable(void); +/* disable tamper pin detection */ +void bkp_tamper_detection_disable(void); +/* set tamper pin active level */ +void bkp_tamper_active_level_set(uint16_t level); + +/* interrupt & flag functions */ +/* enable tamper interrupt */ +void bkp_interrupt_enable(void); +/* disable tamper interrupt */ +void bkp_interrupt_disable(void); +/* get tamper flag state */ +FlagStatus bkp_flag_get(void); +/* clear tamper flag state */ +void bkp_flag_clear(void); +/* get tamper interrupt flag state */ +FlagStatus bkp_interrupt_flag_get(void); +/* clear tamper interrupt flag state */ +void bkp_interrupt_flag_clear(void); + +#endif /* GD32F10X_BKP_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h new file mode 100644 index 0000000000..0e5ae1f251 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h @@ -0,0 +1,725 @@ +/*! + \file gd32f10x_can.h + \brief definitions for the CAN + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10x_CAN_H +#define GD32F10x_CAN_H + +#include "gd32f10x.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ + +/* registers definitions */ +#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ + +/* CAN transmit mailbox bank */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ + +/* CAN filter bank */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ + +/* CAN receive fifo mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ + +/* bits definitions */ +/* CAN_CTL */ +#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ +#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ +#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ +#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ +#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ +#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ +#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ +#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ +#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ +#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ + +/* CAN_STAT */ +#define CAN_STAT_IWS BIT(0) /*!< initial working state */ +#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ +#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ +#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ +#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ +#define CAN_STAT_TS BIT(8) /*!< transmitting state */ +#define CAN_STAT_RS BIT(9) /*!< receiving state */ +#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ +#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ + +/* CAN_TSTAT */ +#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ +#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ +#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ +#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ +#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ +#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ +#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ +#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ +#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ +#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ +#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ +#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ +#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ +#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ +#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ +#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ +#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ +#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ +#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ +#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ +#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + +/* CAN_RFIFO0 */ +#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ +#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ +#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ +#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + +/* CAN_RFIFO1 */ +#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ +#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ +#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ +#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + +/* CAN_INTEN */ +#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ +#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ +#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ +#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ +#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ +#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ +#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ + +/* CAN_ERR */ +#define CAN_ERR_WERR BIT(0) /*!< warning error */ +#define CAN_ERR_PERR BIT(1) /*!< passive error */ +#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ + +/* CAN_BT */ +#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ +#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ +#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + +/* CAN_TMIx */ +#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ +#define CAN_TMI_FT BIT(1) /*!< frame type */ +#define CAN_TMI_FF BIT(2) /*!< frame format */ +#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_TMPx */ +#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ +#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_TMDATA0x */ +#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ + +/* CAN_TMDATA1x */ +#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ + +/* CAN_RFIFOMIx */ +#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ +#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_RFIFOMPx */ +#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_RFIFOMDATA0x */ +#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ + +/* CAN_RFIFOMDATA1x */ +#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ + +/* CAN_FCTL */ +#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ + +/* CAN_FMCFG */ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + +/* CAN_FSCFG */ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ + +/* CAN_FAFIFO */ +#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ + +/* CAN_FW */ +#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ + +/* CAN_FxDATAy */ +#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ + +/* consts definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ +#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ +#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ +#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ +#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ + +/* CAN flags */ +typedef enum +{ + /* flags in TSTAT register */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +}can_flag_enum; + +/* CAN interrupt flags */ +typedef enum +{ + /* interrupt flags in STAT register */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ +}can_interrupt_flag_enum; + +/* CAN initiliaze parameters struct */ +typedef struct +{ + uint8_t working_mode; /*!< CAN working mode */ + uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ + ControlStatus time_triggered; /*!< time triggered communication mode */ + ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ + ControlStatus auto_wake_up; /*!< automatic wake-up mode */ + ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ + ControlStatus trans_fifo_order; /*!< transmit FIFO order */ + uint16_t prescaler; /*!< baudrate prescaler */ +}can_parameter_struct; + +/* CAN transmit message struct */ +typedef struct +{ + uint32_t tx_sfid; /*!< standard format frame identifier */ + uint32_t tx_efid; /*!< extended format frame identifier */ + uint8_t tx_ff; /*!< format of frame, standard or extended format */ + uint8_t tx_ft; /*!< type of frame, data or remote */ + uint8_t tx_dlen; /*!< data length */ + uint8_t tx_data[8]; /*!< transmit data */ +}can_trasnmit_message_struct; + +/* CAN receive message struct */ +typedef struct +{ + uint32_t rx_sfid; /*!< standard format frame identifier */ + uint32_t rx_efid; /*!< extended format frame identifier */ + uint8_t rx_ff; /*!< format of frame, standard or extended format */ + uint8_t rx_ft; /*!< type of frame, data or remote */ + uint8_t rx_dlen; /*!< data length */ + uint8_t rx_data[8]; /*!< receive data */ + uint8_t rx_fi; /*!< filtering index */ +} can_receive_message_struct; + +/* CAN filter parameters struct */ +typedef struct +{ + uint16_t filter_list_high; /*!< filter list number high bits*/ + uint16_t filter_list_low; /*!< filter list number low bits */ + uint16_t filter_mask_high; /*!< filter mask number high bits */ + uint16_t filter_mask_low; /*!< filter mask number low bits */ + uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ + uint16_t filter_number; /*!< filter number */ + uint16_t filter_mode; /*!< filter mode, list or mask */ + uint16_t filter_bits; /*!< filter scale */ + ControlStatus filter_enable; /*!< filter work or not */ +}can_filter_parameter_struct; + +/* CAN errors */ +typedef enum +{ + CAN_ERROR_NONE = 0, /*!< no error */ + CAN_ERROR_FILL, /*!< fill error */ + CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_ACK, /*!< ACK error */ + CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ + CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_CRC, /*!< CRC error */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ +}can_error_enum; + +/* transmit states */ +typedef enum +{ + CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ +}can_transmit_state_enum; + +typedef enum +{ + CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_FILTER_STRUCT, /* CAN filter parameters struct */ + CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ + CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ +}can_struct_type_enum; + +/* CAN baudrate prescaler*/ +#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) + +/* CAN bit segment 1*/ +#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) + +/* CAN bit segment 2*/ +#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) + +/* CAN resynchronization jump width*/ +#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) + +/* CAN communication mode*/ +#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) + +/* CAN FDATA high 16 bits */ +#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) + +/* CAN FDATA low 16 bits */ +#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) + +/* CAN1 filter start bank_number*/ +#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) + +/* CAN transmit mailbox extended identifier*/ +#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) + +/* CAN transmit mailbox standard identifier*/ +#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) + +/* transmit data byte 0 */ +#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 1 */ +#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 2 */ +#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* receive mailbox extended identifier*/ +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) + +/* receive mailbox standrad identifier*/ +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) + +/* receive data length */ +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) + +/* the index of the filter by which the frame is passed */ +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 0 */ +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 1 */ +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 2 */ +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 3 */ +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* receive data byte 4 */ +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 5 */ +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 6 */ +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 7 */ +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* CAN errors */ +#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ +#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ + +#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ + +/* CAN communication mode */ +#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ +#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ +#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ +#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ + +/* CAN resynchronisation jump width */ +#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ + +/* CAN time segment 1 */ +#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ +#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ +#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ +#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ +#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ +#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ +#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ +#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ +#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ + +/* CAN time segment 2 */ +#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ + +/* CAN mailbox number */ +#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ +#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ +#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ +#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ + +/* CAN frame format */ +#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ +#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ + +/* CAN receive fifo */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ + +/* frame number of receive fifo */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ + +#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ +#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ + +/* CAN working mode */ +#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ +#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ +#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ + +/* filter bits */ +#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ +#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ + +/* filter mode */ +#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ +#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ + +/* filter 16 bits mask */ +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ + +/* frame type */ +#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ +#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ + +/* CAN timeout */ +#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ + +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + +/* function declarations */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* initialize CAN struct */ +void can_struct_para_init(can_struct_type_enum type, void* p_struct); +/* initialize CAN */ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); +/* CAN filter init */ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); +/* set can1 fliter start bank number */ +void can1_filter_start_bank(uint8_t start_bank); +/* enable functions */ +/* CAN debug freeze enable */ +void can_debug_freeze_enable(uint32_t can_periph); +/* CAN debug freeze disable */ +void can_debug_freeze_disable(uint32_t can_periph); +/* CAN time trigger mode enable */ +void can_time_trigger_mode_enable(uint32_t can_periph); +/* CAN time trigger mode disable */ +void can_time_trigger_mode_disable(uint32_t can_periph); + +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +/* CAN receive message */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); +/* CAN release fifo */ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); +/* CAN receive message length */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); +/* CAN working mode */ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); +/* CAN wakeup from sleep mode */ +ErrStatus can_wakeup(uint32_t can_periph); + +/* CAN get error */ +can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* CAN get flag state */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* CAN clear flag state */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN get interrupt flag state */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); +/* CAN clear interrupt flag state */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); + +#endif /* GD32F10x_CAN_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h new file mode 100644 index 0000000000..9f2781ff26 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h @@ -0,0 +1,81 @@ +/*! + \file gd32f10x_crc.h + \brief definitions for the CRC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_CRC_H +#define GD32F10X_CRC_H + +#include "gd32f10x.h" + +/* CRC definitions */ +#define CRC CRC_BASE + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* reset data register to the value of initializaiton data register */ +void crc_data_register_reset(void); +/* read the value of the data register */ +uint32_t crc_data_register_read(void); + +/* read the value of the free data register */ +uint8_t crc_free_data_register_read(void); +/* write data to the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* calculate the CRC value of a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* calculate the CRC value of an array of 32-bit values */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32F10X_CRC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h new file mode 100644 index 0000000000..aa9e70bbf8 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h @@ -0,0 +1,250 @@ +/*! + \file gd32f10x_dac.h + \brief definitions for the DAC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_DAC_H +#define GD32F10X_DAC_H + +#include "gd32f10x.h" + +/* DACx(x=0,1) definitions */ +#define DAC DAC_BASE +#define DAC0 0U +#define DAC1 1U + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + +/* DAC0_R12DH */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + +/* DAC0_L12DH */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + +/* DAC0_R8DH */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + +/* DAC1_R12DH */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + +/* DAC1_L12DH */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + +/* DAC1_R8DH */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + +/* DACC_R12DH */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + +/* DACC_L12DH */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + +/* DACC_R8DH */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + +/* DAC0_DO */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ + +/* DAC1_DO */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#elif defined(GD32F10X_CL) +#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(uint32_t dac_periph); +/* disable DAC */ +void dac_disable(uint32_t dac_periph); +/* enable DAC DMA */ +void dac_dma_enable(uint32_t dac_periph); +/* disable DAC DMA */ +void dac_dma_disable(uint32_t dac_periph); +/* enable DAC output buffer */ +void dac_output_buffer_enable(uint32_t dac_periph); +/* disable DAC output buffer */ +void dac_output_buffer_disable(uint32_t dac_periph); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ +/* enable DAC trigger */ +void dac_trigger_enable(uint32_t dac_periph); +/* disable DAC trigger */ +void dac_trigger_disable(uint32_t dac_periph); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* enable DAC software trigger */ +void dac_software_trigger_enable(uint32_t dac_periph); +/* disable DAC software trigger */ +void dac_software_trigger_disable(uint32_t dac_periph); + +/* DAC wave mode configuration */ +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); + +/* DAC concurrent mode configuration */ +/* enable DAC concurrent mode */ +void dac_concurrent_enable(void); +/* disable DAC concurrent mode */ +void dac_concurrent_disable(void); +/* enable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_enable(void); +/* disable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_disable(void); +/* enable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_enable(void); +/* disable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_disable(void); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); + +#endif /* GD32F10X_DAC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h new file mode 100644 index 0000000000..d9248414b8 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h @@ -0,0 +1,152 @@ +/*! + \file gd32f10x_dbg.h + \brief definitions for the DBG + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_DBG_H +#define GD32F10X_DBG_H + +#include "gd32f10x.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL */ +#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ +#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ +#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ +#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ +#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */ +#define DBG_CTL_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */ +#ifdef GD32F10x_CL +#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ +#endif /* GD32F10x_CL */ +#ifdef GD32F10X_XD +#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ +#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ +#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ +#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ +#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ +#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ +#endif /* GD32F10x_XD */ + +/* constants definitions */ +/* debug hold when core is halted */ +typedef enum +{ + DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ + DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ + DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ + DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ + DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */ +#ifdef GD32F10x_CL + DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ +#endif /* GD32F10x_CL */ +#if (defined(GD32F10x_XD) || defined(GD32F10x_CL)) + DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ + DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ +#endif /* GD32F10x_XD || GD32F10x_CL*/ +}dbg_periph_enum; + +/* DBG low power mode configurations */ +#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* DBG_CTL0_TRACE_MODE configurations */ +#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) +#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ +#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ +#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ +#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ + +/* function declarations */ +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* low power behavior configuration */ +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* peripheral behavior configuration */ +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +/* trace pin assignment configuration */ +/* enable trace pin assignment */ +void dbg_trace_pin_enable(void); +/* disable trace pin assignment */ +void dbg_trace_pin_disable(void); +/* set trace pin mode */ +void dbg_trace_pin_mode_set(uint32_t trace_mode); + +#endif /* GD32F10x_DBG_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h new file mode 100644 index 0000000000..3a90e8d690 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h @@ -0,0 +1,289 @@ +/*! + \file gd32f10x_dma.h + \brief definitions for the DMA + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_DMA_H +#define GD32F10X_DMA_H + +#include "gd32f10x.h" + +/* DMA definitions */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ + +/* registers definitions */ +#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ +#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL, x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT, x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR, x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR, x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA channel 0 */ + DMA_CH1, /*!< DMA channel 1 */ + DMA_CH2, /*!< DMA channel 2 */ + DMA_CH3, /*!< DMA channel 3 */ + DMA_CH4, /*!< DMA channel 4 */ + DMA_CH5, /*!< DMA channel 5 */ + DMA_CH6 /*!< DMA channel 6 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + +} dma_parameter_struct; + +#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_register address */ +#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ +/* circular mode */ +#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */ +#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ + +/* memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */ + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ + +/* function declarations */ +/* DMA deinitialization and initialization functions */ +/* deinitialize DMA a channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the parameters of DMA struct with the default values */ +void dma_struct_para_init(dma_parameter_struct* init_struct); +/* initialize DMA channel */ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* DMA configuration functions */ +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set DMA memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); + +/* flag and interrupt functions */ +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the flag of a DMA channel */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the interrupt flag of a DMA channel */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); + +#endif /* GD32F10X_DMA_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h new file mode 100644 index 0000000000..310fb2f8d8 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h @@ -0,0 +1,1498 @@ +/*! + \file gd32f10x_enet.h + \brief definitions for the ENET + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10x_ENET_H +#define GD32F10x_ENET_H + +#include "gd32f10x.h" +#include + +#define IF_USE_EXTERNPHY_LIB 0 +#if (1 == IF_USE_EXTERNPHY_LIB) +#include "phy.h" +#endif + +#ifndef ENET_RXBUF_NUM +#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ +#endif + +#ifndef ENET_TXBUF_NUM +#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ +#endif + +#ifndef ENET_RXBUF_SIZE +#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ +#endif + +#ifndef ENET_TXBUF_SIZE +#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ +#endif + +/* #define USE_DELAY */ + +#ifndef _PHY_H_ +#define DP83848 0 +#define LAN8700 1 +#define PHY_TYPE DP83848 + +#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ + +/* PHY read write timeouts */ +#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ +#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ + +/* PHY delay */ +#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ +#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ + +/* PHY register address */ +#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ +#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ + +/* PHY basic control register */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ + +/* PHY basic status register */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ + +#if(PHY_TYPE == LAN8700) +#define PHY_SR 31U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ +#elif(PHY_TYPE == DP83848) +#define PHY_SR 16U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ +#endif /* PHY_TYPE */ + +#endif /* _PHY_H_ */ + + +/* ENET definitions */ +#define ENET ENET_BASE + +/* registers definitions */ +#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ +#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ + +#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ + +#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ + +#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ +#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ +#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ +#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ +#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ +#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ +#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ +#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ +#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ + +/* bits definitions */ +/* ENET_MAC_CFG */ +#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ +#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ +#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ +#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ +#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ +#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ +#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ +#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ +#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ +#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ +#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ +#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ +#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ + +/* ENET_MAC_FRMF */ +#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ +#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + +/* ENET_MAC_HLH */ +#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ + +/* ENET_MAC_HLL */ +#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ + +/* ENET_MAC_PHY_CTL */ +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + +/* ENET_MAC_PHY_DATA */ +#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ + +/* ENET_MAC_FCTL */ +#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ +#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ +#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ +#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ +#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ + +/* ENET_MAC_FCTH */ +#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ +#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ + +/* ENET_MAC_VLT */ +#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ +#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ + +/* ENET_MAC_RWFF */ +#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ + +/* ENET_MAC_WUM */ +#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ +#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ +#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ +#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ +#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ +#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ +#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ + +/* ENET_MAC_INTF */ +#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ +#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ +#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ +#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ +#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ + +/* ENET_MAC_INTMSK */ +#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ +#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ + +/* ENET_MAC_ADDR0H */ +#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ +#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ + +/* ENET_MAC_ADDR0L */ +#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ + +/* ENET_MAC_ADDR1H */ +#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR1L */ +#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ + +/* ENET_MAC_ADDR2H */ +#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ +#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR2L */ +#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ + +/* ENET_MAC_ADDR3H */ +#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ +#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR3L */ +#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ + +/* ENET_MSC_CTL */ +#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ +#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ +#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ +#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ + +/* ENET_MSC_RINTF */ +#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ +#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ +#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ + +/* ENET_MSC_TINTF */ +#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ +#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ +#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ + +/* ENET_MSC_RINTMSK */ +#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ +#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ +#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ + +/* ENET_MSC_TINTMSK */ +#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ + +/* ENET_MSC_SCCNT */ +#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ + +/* ENET_MSC_MSCCNT */ +#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ + +/* ENET_MSC_TGFCNT */ +#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ + +/* ENET_MSC_RFCECNT */ +#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ + +/* ENET_MSC_RFAECNT */ +#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ + +/* ENET_MSC_RGUFCNT */ +#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ + +/* ENET_PTP_TSCTL */ +#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ +#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ +#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ +#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ +#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ +#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ + +/* ENET_PTP_SSINC */ +#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ + +/* ENET_PTP_TSH */ +#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ + +/* ENET_PTP_TSL */ +#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ +#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ + +/* ENET_PTP_TSUH */ +#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ + +/* ENET_PTP_TSUL */ +#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ +#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ + +/* ENET_PTP_TSADDEND */ +#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ + +/* ENET_PTP_ETH */ +#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ + +/* ENET_PTP_ETL */ +#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ + +/* ENET_DMA_BCTL */ +#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ +#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ +#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ +#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ +#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ +#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ +#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ +#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ +#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ +#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ + +/* ENET_DMA_TPEN */ +#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ + +/* ENET_DMA_RPEN */ +#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ + +/* ENET_DMA_RDTADDR */ +#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ + +/* ENET_DMA_TDTADDR */ +#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ + +/* ENET_DMA_STAT */ +#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ +#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ +#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ +#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ +#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ +#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ +#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ +#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ +#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ +#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ +#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ +#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ +#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ +#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ +#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ +#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ +#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ +#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ +#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ +#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ +#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ + +/* ENET_DMA_CTL */ +#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ +#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ +#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ +#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ +#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ +#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ +#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ +#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ +#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ +#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ +#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ +#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ + +/* ENET_DMA_INTEN */ +#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ +#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ +#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ +#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ +#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ +#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ +#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ +#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ +#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ +#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ +#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ +#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ +#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ + +/* ENET_DMA_MFBOCNT */ +#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ +#define ENET_DMA_MFBOCNT_OBMFC BIT(16) /* Overflow bit for missed frame counter */ +#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ +#define ENET_DMA_MFBOCNT_OBFOC BIT(28) /*!< Overflow bit for FIFO overflow counter */ + +/* ENET_DMA_CTDADDR */ +#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ + +/* ENET_DMA_CRDADDR */ +#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ + +/* ENET_DMA_CTBADDR */ +#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ + +/* ENET_DMA_CRBADDR */ +#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ + +/* ENET DMA Tx descriptor TDES0 */ +#define ENET_TDES0_DB BIT(0) /*!< deferred */ +#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ +#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ +#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ +#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ +#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ +#define ENET_TDES0_LCO BIT(9) /*!< late collision */ +#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ +#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ +#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ +#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ +#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ +#define ENET_TDES0_ES BIT(15) /*!< error summary */ +#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ +#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ +#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ +#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ +#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ +#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ +#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ +#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ +#define ENET_TDES0_FSG BIT(28) /*!< first segment */ +#define ENET_TDES0_LSG BIT(29) /*!< last segment */ +#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ +#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ + +/* ENET DMA Tx descriptor TDES1 */ +#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ +#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ + +/* ENET DMA Tx descriptor TDES2 */ +#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES3 */ +#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ + +/* ENET DMA Rx descriptor RDES0 */ +#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ +#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ +#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ +#define ENET_RDES0_RERR BIT(3) /*!< receive error */ +#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ +#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ +#define ENET_RDES0_LCO BIT(6) /*!< late collision */ +#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ +#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ +#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ +#define ENET_RDES0_LERR BIT(12) /*!< length error */ +#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ +#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ +#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ +#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ +#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ +#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ + +/* ENET DMA Rx descriptor RDES1 */ +#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ +#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ +#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ +#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ +#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ + +/* ENET DMA Rx descriptor RDES2 */ +#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ + +/* ENET DMA Rx descriptor RDES3 */ +#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ + +/* constants definitions */ +/* define bit position and its register index offset */ +#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) +#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* ENET clock range judgement */ +#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) + +/* define MAC address configuration and reference address */ +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) +#define ENET_ADDRH_BASE ((ENET) + 0x40U) +#define ENET_ADDRL_BASE ((ENET) + 0x44U) +#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) + +/* register offset */ +#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ + +#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ + +#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ + +/* ENET status flag get */ +typedef enum +{ + /* ENET_MAC_WUM register */ + ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + /* ENET_MAC_FCTL register */ + ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ + /* ENET_MAC_INTF register */ + ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ + ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ + ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ + ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_flag_enum; + +/* ENET stutus flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_flag_clear_enum; + +/* ENET interrupt enable/disable */ +typedef enum +{ + /* ENET_MAC_INTMSK register */ + ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ + ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ + /* ENET_MSC_RINTMSK register */ + ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ + ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ + ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ + /* ENET_MSC_TINTMSK register */ + ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ + ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ + ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ + /* ENET_DMA_INTEN register */ + ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ + ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ + ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ + ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ + ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ + ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ + ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ + ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ + ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ + ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ + ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ + ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ + ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ + ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ + ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ +}enet_int_enum; + +/* ENET interrupt flag get */ +typedef enum +{ + /* ENET_MAC_INTF register */ + ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_int_flag_enum; + +/* ENET interrupt flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_int_flag_clear_enum; + +/* current RX/TX descriptor/buffer/descriptor table address get */ +typedef enum +{ + ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ + ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ + ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ + ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ + ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ + ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ +}enet_desc_reg_enum; + +/* MAC statistics counter get */ +typedef enum +{ + ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ + ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ + ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ + ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ + ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ + ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ +}enet_msc_counter_enum; + +/* function option, used for ENET initialization */ +typedef enum +{ + FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ + DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ + DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ + DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ + STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ + DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ + VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ + FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ + HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ + HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ + FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ + HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ + TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ + INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ +}enet_option_enum; + +/* phy mode and mac loopback configurations */ +typedef enum +{ + ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ + ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ + ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ + ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ + ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ + ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ +}enet_mediamode_enum; + +/* IP frame checksum function */ +typedef enum +{ + ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ + ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ + ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped */ +}enet_chksumconf_enum; + +/* received frame filter function */ +typedef enum +{ + ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ + ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ + ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ + ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ +}enet_frmrecept_enum; + +/* register group value get */ +typedef enum +{ + ALL_MAC_REG = 0, /*!< MAC register group */ + ALL_MSC_REG = 22, /*!< MSC register group */ + ALL_PTP_REG = 33, /*!< PTP register group */ + ALL_DMA_REG = 44, /*!< DMA register group */ +}enet_registers_type_enum; + +/* dma direction select */ +typedef enum +{ + ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ + ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ +}enet_dmadirection_enum; + +/* PHY operation direction select */ +typedef enum +{ + ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ + ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ +}enet_phydirection_enum; + +/* register operation direction select */ +typedef enum +{ + ENET_REG_READ, /*!< read register */ + ENET_REG_WRITE /*!< write register */ +}enet_regdirection_enum; + +/* ENET MAC addresses */ +typedef enum +{ + ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ + ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ + ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ + ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ +}enet_macaddress_enum; + +/* descriptor information */ +typedef enum +{ + TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ + TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ + RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ + RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ + RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ + RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ +}enet_descstate_enum; + +/* structure for initialization of the ENET */ +typedef struct +{ + uint32_t option_enable; /*!< select which function to configure */ + uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ + uint32_t dma_maxburst; /*!< DMA max burst related parameters */ + uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ + uint32_t store_forward_mode; /*!< store forward mode related parameters */ + uint32_t dma_function; /*!< DMA control related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t flow_control; /*!< flow control related parameters */ + uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ + uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ + uint32_t framesfilter_mode; /*!< frame filter control related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t timer_config; /*!< frame timer related parameters */ + uint32_t interframegap; /*!< inter frame gap related parameters */ +}enet_initpara_struct; + +/* structure for ENET DMA desciptors */ +typedef struct +{ + uint32_t status; /*!< status */ + uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ + uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ + uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ +} enet_descriptors_struct; + +/* structure of PTP system time */ +typedef struct +{ + uint32_t second; /*!< second of system time */ + uint32_t nanosecond; /*!< nanosecond of system time */ + uint32_t sign; /*!< sign of system time */ +}enet_ptp_systime_struct; + +/* mac_cfg register value */ +#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ +#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ +#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ +#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ + +#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ +#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ +#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ +#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ + +#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ +#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ + +#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ +#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ + +#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ +#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ + +#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ +#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ + +#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ +#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ + +#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ +#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ + +#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ +#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ + +#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ +#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ + +#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ +#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ + +#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ +#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ +#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ + +#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ +#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ + +/* mac_frmf register value */ +#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ +#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ +#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ +#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ +#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ + +#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ +#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ + +#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ +#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ +#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ +#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ +#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ + +#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ +#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ + +#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ + +#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ +#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ + +#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ +#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ +#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ +#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ +#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ +#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ +#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ + +#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ +#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ +#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ +#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ + +/* mac_phy_ctl register value */ +#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ +#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ +#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ + +#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ + +#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ + +/* mac_phy_data register value */ +#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ + +/* mac_fctl register value */ +#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ +#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ +#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ +#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ + +#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ + +#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ +#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ + +#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ +#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ +#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ + +#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ + +#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ + +#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ +/* mac_vlt register value */ +#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ + +#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ +#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ + +/* mac_wum register value */ +#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ +#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ +#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ + +/* mac_addr0h register value */ +#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ + +/* mac_addrxh register value, x = 1,2,3 */ +#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ + +#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ +#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ +#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ +#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ + +#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ +#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ + +/* mac_fcth register value */ +#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ +#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ +#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ +#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ +#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ +#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ +#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ +#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ + +#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ +#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ +#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ +#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ + +/* msc_ctl register value */ +#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ +#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ +#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ + +/* ptp_tsctl register value */ +#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ +#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ + +/* ptp_ssinc register value */ +#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ + +/* ptp_tsl register value */ +#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ + +#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ +#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ + +#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ + +/* ptp_tsul register value */ +#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ + +#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ +#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ + +/* dma_bctl register value */ +#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ +#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ + +#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ +#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ +#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ +#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ +#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ + +#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ +#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ +#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ +#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ + +#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ +#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ + +#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ +#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ +#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ +#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ +#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ +#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ +#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ +#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ +#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ + +#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ +#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ + +#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ +#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ + +/* dma_stat register value */ +#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ +#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ +#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ +#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ +#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ +#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ +#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ + +#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ +#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ +#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ +#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ +#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ +#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ +#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ + +#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ +#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ +#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ +#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ + +/* dma_ctl register value */ +#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ +#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ +#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ +#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ + +#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ +#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ +#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ +#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ +#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ +#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ +#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ +#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ + +#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ +#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ + +#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ +#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ + +#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ +#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ +#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */ + +#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ +#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ + +#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ +#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ + +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ + +#define ENET_SECONDFRAME_OPT_ENABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode enable*/ +#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ +#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ + +/* dma_mfbocnt register value */ +#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ + +#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ + +/* dma tx descriptor tdes0 register value */ +#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ +#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ + +#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ + +/* dma tx descriptor tdes1 register value */ +#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ + +#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ + +/* dma rx descriptor rdes0 register value */ +#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ +#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ + +/* dma rx descriptor rdes1 register value */ +#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ +#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ + +#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ + +#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ + +/* dma rx descriptor rdes4 register value */ +#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ +#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ + +#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ +#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ + +/* ENET register mask value */ +#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ +#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ +#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ +#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ + +#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ + +typedef enum{ + ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ + ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ + ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ +}enet_ptp_function_enum; + + +/* ENET remote wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ + +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ + +/* ENET delay timeout */ +#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ +#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ + +/* function declarations */ +/* main function */ +/* deinitialize the ENET, and reset structure parameters for ENET initialization */ +void enet_deinit(void); +/* configure the parameters which are usually less cared for initialization */ +void enet_initpara_config(enet_option_enum option, uint32_t para); +/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); +/* reset all core internal registers located in CLK_TX and CLK_RX */ +ErrStatus enet_software_reset(void); +/* check receive frame valid and return frame size */ +uint32_t enet_rxframe_size_get(void); +/* initialize the dma tx/rx descriptors's parameters in chain mode */ +void enet_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma tx/rx descriptors's parameters in ring mode */ +void enet_descriptors_ring_init(enet_dmadirection_enum direction); +/* handle current received frame data to application buffer */ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); +/* handle current received frame but without data copy to application buffer */ +#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) +/* handle application buffer data to transmit it */ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); +/* handle current transmit frame but without data copy from application buffer */ +#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) +/* configure the transmit IP frame checksum offload calculation and insertion */ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); +/* ENET Tx and Rx function enable (include MAC and DMA module) */ +void enet_enable(void); +/* ENET Tx and Rx function disable (include MAC and DMA module) */ +void enet_disable(void); +/* configure MAC address */ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); +/* get MAC address */ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); + +/* get the ENET MAC/MSC/PTP/DMA status flag */ +FlagStatus enet_flag_get(enet_flag_enum enet_flag); +/* clear the ENET DMA status flag */ +void enet_flag_clear(enet_flag_clear_enum enet_flag); +/* enable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_enable(enet_int_enum enet_int); +/* disable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_disable(enet_int_enum enet_int); +/* get ENET MAC/MSC/DMA interrupt flag */ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); +/* clear ENET DMA interrupt flag */ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); + +/* MAC function */ +/* ENET Tx function enable (include MAC and DMA module) */ +void enet_tx_enable(void); +/* ENET Tx function disable (include MAC and DMA module) */ +void enet_tx_disable(void); +/* ENET Rx function enable (include MAC and DMA module) */ +void enet_rx_enable(void); +/* ENET Rx function disable (include MAC and DMA module) */ +void enet_rx_disable(void); +/* put registers value into the application buffer */ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); +/* enable the MAC address filter */ +void enet_address_filter_enable(enet_macaddress_enum mac_addr); +/* disable the MAC address filter */ +void enet_address_filter_disable(enet_macaddress_enum mac_addr); +/* configure the MAC address filter */ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); +/* PHY interface configuration (configure SMI clock and reset PHY chip) */ +ErrStatus enet_phy_config(void); +/* write to/read from a PHY register */ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); +/* enable the loopback function of phy chip */ +ErrStatus enet_phyloopback_enable(void); +/* disable the loopback function of phy chip */ +ErrStatus enet_phyloopback_disable(void); +/* enable ENET forward feature */ +void enet_forward_feature_enable(uint32_t feature); +/* disable ENET forward feature */ +void enet_forward_feature_disable(uint32_t feature); +/* enable ENET fliter feature */ +void enet_fliter_feature_enable(uint32_t feature); +/* disable ENET fliter feature */ +void enet_fliter_feature_disable(uint32_t feature); + +/* flow control function */ +/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ +ErrStatus enet_pauseframe_generate(void); +/* configure the pause frame detect type */ +void enet_pauseframe_detect_config(uint32_t detect); +/* configure the pause frame parameters */ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); +/* configure the threshold of the flow control(deactive and active threshold) */ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); +/* enable ENET flow control feature */ +void enet_flowcontrol_feature_enable(uint32_t feature); +/* disable ENET flow control feature */ +void enet_flowcontrol_feature_disable(uint32_t feature); + +/* DMA function */ +/* get the dma transmit/receive process state */ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +/* poll the dma transmission/reception enable */ +void enet_dmaprocess_resume(enet_dmadirection_enum direction); +/* check and recover the Rx process */ +void enet_rxprocess_check_recovery(void); +/* flush the ENET transmit fifo, and wait until the flush operation completes */ +ErrStatus enet_txfifo_flush(void); +/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); +/* get the Tx or Rx descriptor information */ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); +/* get the number of missed frames during receiving */ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); + +/* descriptor function */ +/* get the bit flag of ENET dma descriptor */ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); +/* set the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); +/* clear the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will set */ +void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will not set */ +void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc); +/* drop current receive frame */ +void enet_rxframe_drop(void); +/* enable DMA feature */ +void enet_dma_feature_enable(uint32_t feature); +/* disable DMA feature */ +void enet_dma_feature_disable(uint32_t feature); + +/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) + +/* WUM function */ +/* wakeup frame filter register pointer reset */ +void enet_wum_filter_register_pointer_reset(void); +/* set the remote wakeup frame registers */ +void enet_wum_filter_config(uint32_t pdata[]); +/* enable wakeup management features */ +void enet_wum_feature_enable(uint32_t feature); +/* disable wakeup management features */ +void enet_wum_feature_disable(uint32_t feature); + +/* MSC function */ +/* reset the MAC statistics counters */ +void enet_msc_counters_reset(void); +/* enable the MAC statistics counter features */ +void enet_msc_feature_enable(uint32_t feature); +/* disable the MAC statistics counter features */ +void enet_msc_feature_disable(uint32_t feature); +/* get MAC statistics counter */ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); + +/* PTP function */ +/* change subsecond to nanosecond */ +uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond); +/* change nanosecond to subsecond */ +uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond); +/* enable the PTP features */ +void enet_ptp_feature_enable(uint32_t feature); +/* disable the PTP features */ +void enet_ptp_feature_disable(uint32_t feature); +/* configure the PTP timestamp function */ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); +/* configure the PTP system time subsecond increment value */ +void enet_ptp_subsecond_increment_config(uint32_t subsecond); +/* adjusting the PTP clock frequency only in fine update mode */ +void enet_ptp_timestamp_addend_config(uint32_t add); +/* initializing or adding/subtracting to second of the PTP system time */ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); +/* configure the PTP expected target time */ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); +/* get the PTP current system time */ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); +/* configure and start PTP timestamp counter */ +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg); +/* adjust frequency in fine method by configure addend register */ +void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg); +/* update system time in coarse method */ +void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); +/* set system time in fine method */ +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct); +/* get the ptp flag status */ +FlagStatus enet_ptp_flag_get(uint32_t flag); + +/* internal function */ +/* reset the ENET initpara struct, call it before using enet_initpara_config() */ +void enet_initpara_reset(void); +/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ +static void enet_default_init(void); +#ifdef USE_DELAY +/* user can provide more timing precise _ENET_DELAY_ function */ +#define _ENET_DELAY_ delay_ms +#else +/* insert a delay time */ +static void enet_delay(uint32_t ncount); +/* default _ENET_DELAY_ function with less precise timing */ +#define _ENET_DELAY_ enet_delay +#endif + +#endif /* GD32F10X_ENET_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h new file mode 100644 index 0000000000..b9b1478a04 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h @@ -0,0 +1,432 @@ +/*! + \file gd32f10x_exmc.h + \brief definitions for the EXMC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_EXMC_H +#define GD32F10X_EXMC_H + +#include "gd32f10x.h" + +/* EXMC definitions */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ + +/* registers definitions */ +/* NOR/PSRAM */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ + +#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */ + +#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */ + +#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */ + +/* NAND/PC card */ +#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */ +#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */ + +#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */ +#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */ + +#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */ +#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */ +#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ + +/* bits definitions */ +/* NOR/PSRAM */ +/* EXMC_SNCTLx,x=0..3 */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ +#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ +#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ +#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ + +/* EXMC_SNTCFGx,x=0..3 */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ +#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_SNWTCFGx,x=0..3 */ +#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNWTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNWTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ +#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* NAND/PC card */ +/* EXMC_NPCTLx,x=1..3 */ +#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ +#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ +#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ +#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ + +/* EXMC_NPINTENx,x=1..3 */ +#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ +#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ +#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ +#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ +#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ +#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ +#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ + +/* EXMC_NPCTCFGx,x=1..3 */ +#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ + +/* EXMC_NPATCFGx,x=1..3 */ +#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ + +/* EXMC_PIOTCFG3 */ +#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ + +/* EXMC_NECCx,x=1,2 */ +#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ + +/* constants definitions */ +/* EXMC NOR/SRAM timing initialize struct */ +typedef struct +{ + uint32_t asyn_access_mode; /*!< asynchronous access mode */ + uint32_t syn_data_latency; /*!< configure the data latency */ + uint32_t syn_clk_division; /*!< configure the clock divide ratio */ + uint32_t bus_latency; /*!< configure the bus latency */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ +}exmc_norsram_timing_parameter_struct; + +/* EXMC NOR/SRAM initialize struct */ +typedef struct +{ + uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ + uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ + uint32_t extended_mode; /*!< enable or disable the extended mode */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ + uint32_t memory_write; /*!< enable or disable the write operation */ + uint32_t nwait_config; /*!< NWAIT signal configuration */ + uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ + uint32_t burst_mode; /*!< enable or disable the burst mode */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ + uint32_t memory_type; /*!< specifies the type of external memory */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing + parameters for read if the extended mode is used */ + exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ +}exmc_norsram_parameter_struct; + +/* EXMC NAND/PC card timing initialize struct */ +typedef struct +{ + uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ + uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ + uint32_t waittime; /*!< configure the minimum wait time */ + uint32_t setuptime; /*!< configure the address setup time */ +}exmc_nand_pccard_timing_parameter_struct; + +/* EXMC NAND initialize struct */ +typedef struct +{ + uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t ecc_size; /*!< the page size for the ECC calculation */ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ + uint32_t databus_width; /*!< the NAND flash databus width */ + uint32_t wait_feature; /*!< enables or disables the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +}exmc_nand_parameter_struct; + +/* EXMC PC card initialize struct */ +typedef struct +{ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t wait_feature; /*!< enables or disables the Wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ + exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */ +}exmc_pccard_parameter_struct;; + +/* EXMC register address */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ +#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */ + +#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */ +#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */ +#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */ +#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ +#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */ + +/* NOR bank memory data bus width */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ + +/* NOR bank memory type */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + +/* asynchronous access mode */ +#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ +#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ +#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ +#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ + +/* data latency for NOR flash */ +#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ +#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ +#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ +#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ +#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ +#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ +#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ +#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ +#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ +#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ +#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ +#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ +#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ +#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ +#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ +#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ + +/* synchronous clock divide ratio */ +#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ + +/* ECC size */ +#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ + +/* ALE to RE delay */ +#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ + +/* CLE to RE delay */ +#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ + +/* NAND bank memory data bus width */ +#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ +#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ + +/* EXMC NOR/SRAM bank region definition */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ +#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ +#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ +#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ + +/* EXMC NOR/SRAM write mode */ +#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ +#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */ + +/* EXMC NWAIT signal configuration */ +#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ +#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ + +/* EXMC NWAIT signal polarity configuration */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ + +/* EXMC NAND/PC card bank definition */ +#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ +#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ +#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ + +/* EXMC flag bits */ +#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ +#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ +#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ +#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ + +/* EXMC interrupt flag bits */ +#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ +#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ +#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ + +/* function declarations */ +/* deinitialize EXMC NOR/SRAM region */ +void exmc_norsram_deinit(uint32_t norsram_region); +/* exmc_norsram_parameter_struct parameter initialize */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* initialize EXMC NOR/SRAM region */ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* EXMC NOR/SRAM bank enable */ +void exmc_norsram_enable(uint32_t norsram_region); +/* EXMC NOR/SRAM bank disable */ +void exmc_norsram_disable(uint32_t norsram_region); + +/* deinitialize EXMC NAND bank */ +void exmc_nand_deinit(uint32_t nand_bank); +/* initialize EXMC NAND bank */ +void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* exmc_nand_init_struct parameter initialize */ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* EXMC NAND bank enable */ +void exmc_nand_enable(uint32_t nand_bank); +/* EXMC NAND bank disable */ +void exmc_nand_disable(uint32_t nand_bank); +/* enable or disable the EXMC NAND ECC function */ +void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue); +/* get the EXMC ECC value */ +uint32_t exmc_ecc_get(uint32_t nand_bank); + +/* deinitialize EXMC PC card bank */ +void exmc_pccard_deinit(void); +/* initialize EXMC PC card bank */ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* exmc_pccard_parameter_struct parameter initialize */ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* EXMC PC card bank enable */ +void exmc_pccard_enable(void); +/* EXMC PC card bank disable */ +void exmc_pccard_disable(void); + +/* enable EXMC interrupt */ +void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source); +/* disable EXMC interrupt */ +void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source); +/* check EXMC flag is set or not */ +FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag); +/* clear EXMC flag */ +void exmc_flag_clear(uint32_t bank, uint32_t flag); +/* check EXMC flag is set or not */ +FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source); +/* clear EXMC flag */ +void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source); + +#endif /* GD32F10X_EXMC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h new file mode 100644 index 0000000000..9822671976 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h @@ -0,0 +1,258 @@ +/*! + \file gd32f10x_exti.h + \brief definitions for the EXTI + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_EXTI_H +#define GD32F10X_EXTI_H + +#include "gd32f10x.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum +{ + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ +}exti_line_enum; + +/* external interrupt and event */ +typedef enum +{ + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +}exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum +{ + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH /*!< EXTI rising edge and falling edge trigger */ +}exti_trig_type_enum; + +/* function declarations */ +/* initialization, EXTI lines configuration functions */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* interrupt & flag functions */ +/* get EXTI lines pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI lines flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); +/* enable the EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); + +#endif /* GD32F10X_EXTI_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h new file mode 100644 index 0000000000..f5969b6436 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h @@ -0,0 +1,370 @@ +/*! + \file gd32f10x_fmc.h + \brief definitions for the FMC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_FMC_H +#define GD32F10X_FMC_H + +#include "gd32f10x.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option bytes base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ +#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ +#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ +#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ +#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ +#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ +#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ +#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ +#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ +#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ +#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ + +#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ +#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ +#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ +#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ +#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ + +/* FMC_KEY0 */ +#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT0 */ +#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL0 */ +#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ +#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ +#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ +#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ +#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR0 */ +#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash erase/program command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ +#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + +/* FMC_WP */ +#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ + +/* FMC_KEY1 */ +#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ + +/* FMC_STAT1 */ +#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL1 */ +#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */ +#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */ +#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */ +#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */ +#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR1 */ +#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash erase/program command address bits */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* define the FMC bit position and its register index offset */ +#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) +#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) +#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) + +/* configuration register */ +#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ +#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ +#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ +#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ +#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ + +/* fmc state */ +typedef enum +{ + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ +}fmc_state_enum; + +/* FMC interrupt enable */ +typedef enum +{ + FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ + FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ + FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ + FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ +}fmc_int_enum; + +/* FMC flags */ +typedef enum +{ + FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ + FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ + FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ + FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */ + FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ + FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ + FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ + FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ + FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ +}fmc_flag_enum; + +/* FMC interrupt flags */ +typedef enum +{ + FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ + FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ + FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ + FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ +}fmc_interrupt_flag_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* FMC wait state counter */ +#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ + +/* option bytes software/hardware free watch dog timer */ +#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ +#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ + +/* option bytes reset or not entering deep sleep mode */ +#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ + +/* option bytes reset or not entering standby mode */ +#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ + +/* option bytes boot bank value */ +#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ +#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ + +#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ + +/* OB_SPC */ +#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ +#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ + +/* OB_USER */ +#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ +#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ + +/* OB_WP0 */ +#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ + +/* OB_WP1 */ +#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ + +/* OB_WP2 */ +#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ + +/* OB_WP3 */ +#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ + +/* option bytes write protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ +#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ +#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ +#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ +#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ +#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ +#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ +#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ +#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ +#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ + +/* FMC timeout */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ + +/* FMC BANK address */ +#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ +#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ +#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* set the FMC wait state counter */ +void fmc_wscnt_set(uint32_t wscnt); +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* unlock the FMC bank0 operation */ +void fmc_bank0_unlock(void); +/* unlock the FMC bank1 operation */ +void fmc_bank1_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* lock the bank0 FMC operation */ +void fmc_bank0_lock(void); +/* lock the bank1 FMC operation */ +void fmc_bank1_lock(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC erase whole bank0 */ +fmc_state_enum fmc_bank0_erase(void); +/* FMC erase whole bank1 */ +fmc_state_enum fmc_bank1_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* erase the option byte */ +fmc_state_enum ob_erase(void); +/* enable write protect */ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); +/* configure the option byte security protection */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc); +/* write the FMC option byte */ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); +/* program option bytes data */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data); +/* get the FMC option byte user */ +uint8_t ob_user_get(void); +/* get OB_DATA in register FMC_OBSTAT */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint32_t ob_write_protection_get(void); +/* get option byte security protection code value */ +FlagStatus ob_spc_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* check flag is set or not */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC flag */ +void fmc_flag_clear(uint32_t flag); +/* get FMC interrupt flag state */ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); +/* clear FMC interrupt flag state */ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); +/* return the FMC bank0 state */ +fmc_state_enum fmc_bank0_state_get(void); +/* return the FMC bank1 state */ +fmc_state_enum fmc_bank1_state_get(void); +/* check FMC bank0 ready or not */ +fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); +/* check FMC bank1 ready or not */ +fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); + +#endif /* GD32F10X_FMC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h new file mode 100644 index 0000000000..2d22177e1e --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h @@ -0,0 +1,108 @@ +/*! + \file gd32f10x_fwdgt.h + \brief definitions for the FWDGT + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_FWDGT_H +#define GD32F10X_FWDGT_H + +#include "gd32f10x.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ + +/* constants definitions */ +/* psc register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + +/* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32F10X_FWDGT_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h new file mode 100644 index 0000000000..3b6b53a36d --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h @@ -0,0 +1,497 @@ +/*! + \file gd32f10x_gpio.h + \brief definitions for the GPIO + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10x_GPIO_H +#define GD32F10x_GPIO_H + +#include "gd32f10x.h" + +/* GPIOx(x=A,B,C,D,E,F,G) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOE (GPIO_BASE + 0x00001000U) +#define GPIOF (GPIO_BASE + 0x00001400U) +#define GPIOG (GPIO_BASE + 0x00001800U) + +/* AFIO definitions */ +#define AFIO AFIO_BASE + +/* registers definitions */ + +/* GPIO registers definitions */ +#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ +#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ + +/* AFIO registers definitions */ +#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ +#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ +#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ +#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ +#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ +#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ +#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ + +/* bits definitions */ +/* GPIO_CTL0 */ +#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ +#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ +#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ +#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ +#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ +#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ +#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ +#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ +#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ +#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ +#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ +#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ +#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ +#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ +#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ + +/* GPIO_CTL1 */ +#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ +#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ +#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ +#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ +#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ +#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ +#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ +#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ +#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ +#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ +#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ +#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ +#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ +#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ +#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* AFIO_EC */ +#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ +#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ +#define AFIO_EC_EOE BIT(7) /*!< event output enable */ + +/* AFIO_PCF0 */ +#ifdef GD32F10X_CL +/* memory map and bit definitions for GD32F10X_CL devices */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ +#define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ +#define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ +#define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ +#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ +#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ +#define AFIO_PCF0_TIMER1ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ +#define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ + +#else +/* memory map and bit definitions for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_REMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ +#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ +#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ +#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ +#endif /* GD32F10X_CL */ + +/* AFIO_EXTISS0 */ +#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ +#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ +#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ +#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ + +/* AFIO_EXTISS1 */ +#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ +#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ +#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ +#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ + +/* AFIO_EXTISS2 */ +#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ +#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ +#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ +#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ + +/* AFIO_EXTISS3 */ +#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ +#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ +#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ +#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ + +/* AFIO_PCF1 */ +#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ +#define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */ +#define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */ +#define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ +#define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ +#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* GPIO mode values set */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) +#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) + +/* GPIO mode definitions */ +#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ +#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ +#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ +#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ +#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ +#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ +#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ +#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ + +/* GPIO output max speed value */ +#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ + +/* GPIO event output port definitions */ +#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ +#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ +#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ +#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ +#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ + +/* GPIO output port source definitions */ +#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ +#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ +#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ +#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ +#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ +#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */ +#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */ + +/* GPIO event output pin definitions */ +#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ +#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ +#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ +#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ +#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ +#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ +#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ +#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ +#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ +#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ +#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ +#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ +#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ +#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ +#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ +#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ + +/* GPIO output pin source definitions */ +#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ +#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ +#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ +#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ +#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ +#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ +#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ +#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ +#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ +#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ +#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ +#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ +#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ +#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ +#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ +#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO remap definitions */ +#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ +#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ +#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ +#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ +#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ +#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ +#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ +#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ +#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ +#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ +#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ +#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN partial remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN full remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */ +#if (defined(GD32F10X_CL) || defined(GD32F10X_HD)) +#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) */ +#endif /* GD32F10X_CL||GD32F10X_HD */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U) /*!< ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U) /*!< ADC0 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U) /*!< ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U) /*!< ADC1 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */ +#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ +#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled and SW-DP enabled */ +#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U) /*!< JTAG-DP disabled and SW-DP disabled */ +#ifdef GD32F10X_CL +#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping(only for GD32F10X_CL devices) */ +#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping(only for GD32F10X_CL devices) */ +#define GPIO_ENET_REMAP ((uint32_t)0x00200020U) /*!< ENET remapping(only for GD32F10X_CL devices) */ +#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping(only for GD32F10X_CL devices) */ +#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping(only for GD32F10X_CL devices) */ +#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) */ +#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U) /*!< ethernet PTP PPS remapping(only for GD32F10X_CL devices) */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD +#define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U) /*!< TIMER8 remapping */ +#define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U) /*!< TIMER9 remapping */ +#define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U) /*!< TIMER10 remapping */ +#define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U) /*!< TIMER12 remapping */ +#define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U) /*!< TIMER13 remapping */ +#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ +#endif /* GD32F10X_XD */ + +#ifdef GD32F10X_CL +/* ethernet MII or RMII PHY selection */ +#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */ +#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */ +#endif /* GD32F10X_CL */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* reset alternate function I/O(AFIO) */ +void gpio_afio_deinit(void); +/* GPIO parameter initialization */ +void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* configure GPIO pin remap */ +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); + +/* select GPIO pin exti sources */ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); +/* configure GPIO pin event output */ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); +/* enable GPIO pin event output */ +void gpio_event_output_enable(void); +/* disable GPIO pin event output */ +void gpio_event_output_disable(void); + +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +#ifdef GD32F10X_CL +/* select ethernet MII or RMII PHY */ +void gpio_ethernet_phy_select(uint32_t gpio_enetsel); +#endif /* GD32F10X_CL */ + + +#endif /* GD32F10x_GPIO_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h new file mode 100644 index 0000000000..ab884837dc --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h @@ -0,0 +1,346 @@ +/*! + \file gd32f10x_i2c.h + \brief definitions for the I2C + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_I2C_H +#define GD32F10X_I2C_H + +#include "gd32f10x.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking register */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ + +/* I2C flags */ +typedef enum +{ + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +}i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ +}i2c_interrupt_flag_enum; + +/* I2C interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ +}i2c_interrupt_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ + +/* I2C dual-address mode switch */ +#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ +#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ + +/* PEC transfer */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ + +/* function declarations */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); +/* SMBus type selection */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* dual-address mode switch */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); + +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* enable I2C DMA mode */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); + +/* I2C PEC calculation on or off */ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); +/* I2C whether to transfer PEC value */ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* I2C issue alert through SMBA pin */ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* I2C ARP protocol in SMBus switch */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); + +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); + +#endif /* GD32E10X_I2C_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h new file mode 100644 index 0000000000..1c692733c8 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h @@ -0,0 +1,95 @@ +/*! + \file gd32f10x_misc.h + \brief definitions for the MISC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_MISC_H +#define GD32F10X_MISC_H + +#include "gd32f10x.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(uint8_t nvic_irq); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32F10X_MISC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h new file mode 100644 index 0000000000..3805d75ad5 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h @@ -0,0 +1,129 @@ +/*! + \file gd32f10x_pmu.h + \brief definitions for the PMU + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_PMU_H +#define GD32F10X_PMU_H + +#include "gd32f10x.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ + +/* constants definitions */ +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ + +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* set PMU mode */ +/* PMU work at sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work at deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); +/* PMU work at standby mode */ +void pmu_to_standbymode(uint8_t standbymodecmd); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(void); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(void); + +/* backup related functions */ +/* enable write access to the registers in backup domain */ +void pmu_backup_write_enable(void); +/* disable write access to the registers in backup domain */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag_reset); + +#endif /* GD32F10X_PMU_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h new file mode 100644 index 0000000000..7053c053f4 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h @@ -0,0 +1,924 @@ +/*! + \file gd32f10x_rcu.h + \brief definitions for the RCU + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_RCU_H +#define GD32F10X_RCU_H + +#include "gd32f10x.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ +#elif defined(GD32F10X_CL) +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* bits definitions */ +/* RCU_CTL */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#elif defined(GD32F10X_CL) +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ +#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ +#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ +#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* RCU_CFG0 */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#elif defined(GD32F10X_CL) +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* RCU_INT */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ +#elif defined(GD32F10X_CL) +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ +#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ +#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ +#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ +#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ +#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ +#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ +#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ +#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ +#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ +#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ +#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ +#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ +#ifndef GD32F10X_CL +#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD +#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ +#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ +#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ +#endif /* GD32F10X_XD */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ +#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ +#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ +#ifdef GD32F10X_XD +#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ +#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ +#endif /* GD32F10X_XD */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ +#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ +#ifdef GD32F10X_CL +#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ +#endif /* GD32F10X_CL */ +#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ +#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ +#elif defined(GD32F10X_CL) +#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ +#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ +#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ +#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ +#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ +#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ +#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ +#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ +#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ +#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ +#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ +#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ +#ifndef GD32F10X_CL +#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD +#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ +#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ +#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ +#endif /* GD32F10X_XD */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ +#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ +#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#ifdef GD32F10X_XD +#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ +#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ +#endif /* GD32F10X_XD */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ +#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ +#ifdef GD32F10X_CL +#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ +#endif /* GD32F10X_CL */ +#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +#ifdef GD32F10X_CL +/* RCU_AHBRST */ +#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ +#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ +#endif /* GD32F10X_CL */ + +#if defined(GD32F10X_CL) +/* RCU_CFG1 */ +#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ +#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ +#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ +#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ +#endif /* GD32F10X_CL */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +/* peripherals enable */ +#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ +#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ + +/* peripherals reset */ +#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ +#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ +#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ + +/* configuration register */ +#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ +#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum +{ + /* AHB peripherals */ + RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ + RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ + RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ +#elif defined(GD32F10X_CL) + RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ + RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ + RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ + RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ +#if defined(GD32F10X_XD) + RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ + RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ +#endif /* GD32F10X_XD */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ +#ifdef GD32F10X_CL + RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ +#endif /* GD32F10X_CL */ + RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ + + /* APB2 peripherals */ + RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ + RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ + RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ + RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ +#ifndef GD32F10X_CL + RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD + RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ + RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ + RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ +#endif /* GD32F10X_XD */ +}rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum +{ + /* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ +}rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum +{ + /* AHB peripherals */ +#ifdef GD32F10X_CL + RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ +#endif /* GD32F10X_CL */ + + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ + RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ + RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ +#ifdef GD32F10X_XD + RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ + RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ +#endif /* GD32F10X_XD */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ + RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ +#ifdef GD32F10X_CL + RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ +#endif /* GD32F10X_CL */ + RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ + + /* APB2 peripherals */ + RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ + RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ + RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ + RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ +#ifndef GD32F10X_CL + RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD + RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ + RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ + RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ +#endif /* GD32F10X_XD */ +}rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum +{ + /* clock stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ +#ifdef GD32F10X_CL + RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ + RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ +#endif /* GD32F10X_CL */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ + /* reset source flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ +}rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ +#ifdef GD32F10X_CL + RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ + RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ +#endif /* GD32F10X_CL */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ +}rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ +#ifdef GD32F10X_CL + RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ + RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ +#endif /* GD32F10X_CL */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ +}rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum +{ + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ +#ifdef GD32F10X_CL + RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ + RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ +#endif /* GD32F10X_CL */ +}rcu_int_enum; + +/* oscillator types */ +typedef enum +{ + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ + RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ +#ifdef GD32F10X_CL + RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ + RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ +#endif /* GD32F10X_CL */ +}rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum +{ + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ +}rcu_clock_freq_enum; + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC prescaler select */ +#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ +#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ +#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ +#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ +#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ +#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ +#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ + +/* PLL clock multiplication factor */ +#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ + +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ +#elif defined(GD32F10X_CL) +#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ + +/* USBD/USBFS prescaler select */ +#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) +#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ +#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ +#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ +#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */ + +/* CKOUT0 clock source selection */ +#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ +#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ +#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ +#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ +#ifdef GD32F10X_CL +#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ +#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ +#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ +#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ +#endif /* GD32F10X_CL */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ +#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + +/* PREDV0 division factor */ +#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ +#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ +#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ +#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ +#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ +#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ +#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ +#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ +#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ +#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ +#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ +#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ +#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ +#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ +#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ +#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + +/* PREDV1 division factor */ +#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ +#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ +#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ +#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ +#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ +#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ +#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ +#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ +#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ +#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ +#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ +#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ +#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ +#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ +#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ +#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + +/* PLL1 clock multiplication factor */ +#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ +#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ +#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ +#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ +#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ +#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ +#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ +#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ +#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ +#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ + +/* PLL2 clock multiplication factor */ +#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) +#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ +#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ +#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ +#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ +#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ +#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ +#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ +#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ +#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ +#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ + +#ifdef GD32F10X_CL +/* PREDV0 input clock source selection */ +#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ +#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ + +/* I2S1 clock source selection */ +#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ +#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ + +/* I2S2 clock source selection */ +#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ +#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ +#endif /* GD32F10X_CL */ + +/* deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ + +/* function declarations */ +/* initialization, peripheral clock enable/disable functions */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP domain */ +void rcu_bkp_reset_enable(void); +/* disable the BKP domain reset */ +void rcu_bkp_reset_disable(void); + +/* clock configuration functions */ +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT0 clock source and divider */ +void rcu_ckout0_config(uint32_t ckout0_src); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_div); +#elif defined(GD32F10X_CL) +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); +/* configure the PREDV1 division factor */ +void rcu_predv1_config(uint32_t predv1_div); +/* configure the PLL1 clock */ +void rcu_pll1_config(uint32_t pll_mul); +/* configure the PLL2 clock */ +void rcu_pll2_config(uint32_t pll_mul); +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* peripheral clock configuration functions */ +/* configure the ADC division factor */ +void rcu_adc_clock_config(uint32_t adc_psc); +/* configure the USBD/USBFS prescaler factor */ +void rcu_usb_clock_config(uint32_t usb_psc); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +#ifdef GD32F10X_CL +/* configure the I2S1 clock source selection */ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source); +/* configure the I2S2 clock source selection */ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source); +#endif /* GD32F10X_CL */ + +/* interrupt & flag functions */ +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +/* oscillator configuration functions */ +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +#endif /* GD32F10X_RCU_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h new file mode 100644 index 0000000000..580617014f --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h @@ -0,0 +1,152 @@ +/*! + \file gd32f10x_rtc.h + \brief definitions for the RTC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_RTC_H +#define GD32F10X_RTC_H + +#include "gd32f10x.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ +#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ +#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ +#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ +#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ +#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ +#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ +#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ +#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ +#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ + +/* bits definitions */ +/* RTC_INTEN */ +#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ +#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ +#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ + +/* RTC_CTL */ +#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ +#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ +#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ +#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ +#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ +#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + +/* RTC_PSCH */ +#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ + +/* RTC_PSCL */ +#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ + +/* RTC_DIVH */ +#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ + +/* RTC_DIVL */ +#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ + +/* RTC_CNTH */ +#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ + +/* RTC_CNTL */ +#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ + +/* RTC_ALRMH */ +#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ + +/* RTC_ALRML */ +#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ + +/* constants definitions */ +/* RTC interrupt enable or disable definitions */ +#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ +#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ +#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ + +/* RTC interrupt flag definitions */ +#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ + +/* RTC flag definitions */ +#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ +#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ + +/* function declarations */ +/* initialization functions */ +/* enter RTC configuration mode */ +void rtc_configuration_mode_enter(void); +/* exit RTC configuration mode */ +void rtc_configuration_mode_exit(void); +/* set RTC counter value */ +void rtc_counter_set(uint32_t cnt); +/* set RTC prescaler value */ +void rtc_prescaler_set(uint32_t psc); + +/* operation functions */ +/* wait RTC last write operation finished flag set */ +void rtc_lwoff_wait(void); +/* wait RTC registers synchronized flag set */ +void rtc_register_sync_wait(void); +/* set RTC alarm value */ +void rtc_alarm_config(uint32_t alarm); +/* get RTC counter value */ +uint32_t rtc_counter_get(void); +/* get RTC divider value */ +uint32_t rtc_divider_get(void); + +/* flag & interrupt functions */ +/* get RTC flag status */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear RTC flag status */ +void rtc_flag_clear(uint32_t flag); +/* get RTC interrupt flag status */ +FlagStatus rtc_interrupt_flag_get(uint32_t flag); +/* clear RTC interrupt flag status */ +void rtc_interrupt_flag_clear(uint32_t flag); +/* enable RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disable RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); + +#endif /* GD32F10X_RTC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h new file mode 100644 index 0000000000..c905e10200 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h @@ -0,0 +1,430 @@ +/*! + \file gd32f10x_sdio.h + \brief definitions for the SDIO + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_SDIO_H +#define GD32F10X_SDIO_H + +#include "gd32f10x.h" + +/* SDIO definitions */ +#define SDIO SDIO_BASE + +/* registers definitions */ +#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ +#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ +#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ +#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ +#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ +#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ +#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ +#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ +#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ +#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ +#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ +#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ +#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ +#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ +#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ +#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ +#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ +#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ + +/* bits definitions */ +/* SDIO_PWRCTL */ +#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ + +/* SDIO_CLKCTL */ +#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ +#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ +#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ +#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ +#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ +#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ + +/* SDIO_CMDAGMT */ +#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ + +/* SDIO_CMDCTL */ +#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ +#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ +#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ +#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ +#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ +#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ +#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ +#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ +#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ + +/* SDIO_DATATO */ +#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ + +/* SDIO_DATALEN */ +#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ + +/* SDIO_DATACTL */ +#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ +#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ +#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ +#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ +#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ +#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ +#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ +#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ +#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ + +/* SDIO_STAT */ +#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ +#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ +#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ +#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ +#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ +#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ +#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ +#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ +#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ +#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ +#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ +#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ +#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ +#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ +#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ +#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ +#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ +#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ +#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ +#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ +#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ +#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ +#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ +#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ + +/* SDIO_INTC */ +#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ +#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ +#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ +#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ +#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ +#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ +#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ +#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ +#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ +#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ +#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ +#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ +#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ + +/* SDIO_INTEN */ +#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ +#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ +#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ +#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ +#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ +#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ +#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ +#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ +#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ +#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ +#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ +#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ +#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ +#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ +#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ +#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ +#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ +#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ +#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ +#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ +#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ +#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ + +/* SDIO_FIFO */ +#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ + +/* constants definitions */ +/* SDIO flags */ +#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ +#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ +#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ +#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ +#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ +#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ +#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ +#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ +#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ +#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ +#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ +#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ +#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ +#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ +#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ +#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ +#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ +#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ +#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ +#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ +#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ +#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ +#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ +#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ + +/* SDIO interrupt enable or disable */ +#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO interrupt flags */ +#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO power control */ +#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ +#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ + +/* SDIO card bus mode control */ +#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ +#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ +#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ + +/* SDIO_CLK clock edge selection */ +#define SDIO_SDIOCLKEDGE_RISING ((uint32_t)0x00000000U)/*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ +#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ + +/* clock bypass enable or disable */ +#define SDIO_CLOCKBYPASS_DISABLE ((uint32_t)0x00000000U)/*!< no bypass */ +#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ + +/* SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000U)/*!< SDIO_CLK clock is always on */ +#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ + +/* SDIO command response type */ +#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ +#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ +#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ + +/* command state machine wait type */ +#define SDIO_WAITTYPE_NO ((uint32_t)0x00000000U)/*!< not wait interrupt */ +#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ +#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ + +#define SDIO_RESPONSE0 ((uint32_t)0x00000000U)/*!< card response[31:0]/card response[127:96] */ +#define SDIO_RESPONSE1 ((uint32_t)0x00000001U)/*!< card response[95:64] */ +#define SDIO_RESPONSE2 ((uint32_t)0x00000002U)/*!< card response[63:32] */ +#define SDIO_RESPONSE3 ((uint32_t)0x00000003U)/*!< card response[31:1], plus bit 0 */ + +/* SDIO data block size */ +#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ +#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ +#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ +#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ +#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ +#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ +#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ +#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ +#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ +#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ +#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ +#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ +#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ +#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ +#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ + +/* SDIO data transfer mode */ +#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000U)/*!< block transfer */ +#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ + +/* SDIO data transfer direction */ +#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000U)/*!< write data to card */ +#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ + +/* SDIO read wait type */ +#define SDIO_READWAITTYPE_DAT2 ((uint32_t)0x00000000U)/*!< read wait control using SDIO_DAT[2] */ +#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ + +/* function declarations */ +/* deinitialize the SDIO */ +void sdio_deinit(void); +/* configure the SDIO clock */ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); +/* enable hardware clock control */ +void sdio_hardware_clock_enable(void); +/* disable hardware clock control */ +void sdio_hardware_clock_disable(void); +/* set different SDIO card bus mode */ +void sdio_bus_mode_set(uint32_t bus_mode); +/* set the SDIO power state */ +void sdio_power_state_set(uint32_t power_state); +/* get the SDIO power state */ +uint32_t sdio_power_state_get(void); +/* enable SDIO_CLK clock output */ +void sdio_clock_enable(void); +/* disable SDIO_CLK clock output */ +void sdio_clock_disable(void); + +/* configure the command index, argument, response type, wait type and CSM to send command */ +/* configure the command and response */ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); +/* set the command state machine wait type */ +void sdio_wait_type_set(uint32_t wait_type); +/* enable the CSM(command state machine) */ +void sdio_csm_enable(void); +/* disable the CSM(command state machine) */ +void sdio_csm_disable(void); +/* get the last response command index */ +uint8_t sdio_command_index_get(void); +/* get the response for the last received command */ +uint32_t sdio_response_get(uint32_t responsex); + +/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ +/* configure the data timeout, data length and data block size */ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); +/* configure the data transfer mode and direction */ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); +/* enable the DSM(data state machine) for data transfer */ +void sdio_dsm_enable(void); +/* disable the DSM(data state machine) */ +void sdio_dsm_disable(void); +/* write data(one word) to the transmit FIFO */ +void sdio_data_write(uint32_t data); +/* read data(one word) from the receive FIFO */ +uint32_t sdio_data_read(void); +/* get the number of remaining data bytes to be transferred to card */ +uint32_t sdio_data_counter_get(void); +/* get the number of words remaining to be written or read from FIFO */ +uint32_t sdio_fifo_counter_get(void); +/* enable the DMA request for SDIO */ +void sdio_dma_enable(void); +/* disable the DMA request for SDIO */ +void sdio_dma_disable(void); + +/* get the flags state of SDIO */ +FlagStatus sdio_flag_get(uint32_t flag); +/* clear the pending flags of SDIO */ +void sdio_flag_clear(uint32_t flag); +/* enable the SDIO interrupt */ +void sdio_interrupt_enable(uint32_t int_flag); +/* disable the SDIO interrupt */ +void sdio_interrupt_disable(uint32_t int_flag); +/* get the interrupt flags state of SDIO */ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); +/* clear the interrupt pending flags of SDIO */ +void sdio_interrupt_flag_clear(uint32_t int_flag); + +/* enable the read wait mode(SD I/O only) */ +void sdio_readwait_enable(void); +/* disable the read wait mode(SD I/O only) */ +void sdio_readwait_disable(void); +/* enable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_enable(void); +/* disable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_disable(void); +/* set the read wait type(SD I/O only) */ +void sdio_readwait_type_set(uint32_t readwait_type); +/* enable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_enable(void); +/* disable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_disable(void); +/* enable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_enable(void); +/* disable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_disable(void); + +/* enable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_enable(void); +/* disable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_disable(void); +/* enable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_enable(void); +/* disable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_disable(void); +/* enable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_enable(void); +/* disable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_disable(void); + +#endif /* GD32F10X_SDIO_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h new file mode 100644 index 0000000000..0cd8c26786 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h @@ -0,0 +1,328 @@ +/*! + \file gd32f10x_spi.h + \brief definitions for the SPI + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_SPI_H +#define GD32F10X_SPI_H + +#include "gd32f10x.h" + +/* SPIx(x=0,1,2) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define SPI2 (SPI_BASE + 0x00000400U) + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial value */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC value */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC value */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct +{ + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +}spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ + +/* function declarations */ +/* SPI/I2S deinitialization and initialization functions */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI struct with the default values */ +void spi_struct_para_init(spi_parameter_struct* spi_struct); +/* initialize SPI parameter */ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph,uint32_t mode, uint32_t standard, uint32_t ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* NSS functions */ +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* DMA communication */ +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma); + +/* normal mode communication */ +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); + +/* flag and interrupt functions */ +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +#endif /* GD32F10X_SPI_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h new file mode 100644 index 0000000000..01af9b655c --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h @@ -0,0 +1,730 @@ +/*! + \file gd32f10x_timer.h + \brief definitions for the TIMER + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_TIMER_H +#define GD32F10X_TIMER_H + +#include "gd32f10x.h" + +/* TIMERx(x=0..13) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER3 (TIMER_BASE + 0x00000800U) +#define TIMER4 (TIMER_BASE + 0x00000C00U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER6 (TIMER_BASE + 0x00001400U) +#define TIMER7 (TIMER_BASE + 0x00013400U) +#define TIMER8 (TIMER_BASE + 0x00014C00U) +#define TIMER9 (TIMER_BASE + 0x00015000U) +#define TIMER10 (TIMER_BASE + 0x00015400U) +#define TIMER11 (TIMER_BASE + 0x00001800U) +#define TIMER12 (TIMER_BASE + 0x00001C00U) +#define TIMER13 (TIMER_BASE + 0x00002000U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* constants definitions */ +/* TIMER init parameter struct definitions */ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint32_t period; /*!< period value */ + uint16_t clockdivision; /*!< clock division value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint16_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ +#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ +#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ +#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ +#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ +#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ +#define TIMER_INT_FLAG_BRK TIMER_INT_BRK + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ + +/* channel enable state */ +#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ + +/* channel complementary output enable state */ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< frozen mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< set the channel output */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< clear the channel output */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle on match */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* timer input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ + +/* TIMERx(x=0..4,7..13) write CHxVAL register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* function declarations */ +/* TIMER timebase */ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint32_t update); + +/* timer DMA and event */ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); + +/* TIMER interrupt and flag */ +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER flag */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flag */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); + +#endif /* GD32E10X_TIMER_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h new file mode 100644 index 0000000000..b0af23732f --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h @@ -0,0 +1,378 @@ +/*! + \file gd32f10x_usart.h + \brief definitions for the USART + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.1, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_USART_H +#define GD32F10X_USART_H + +#include "gd32f10x.h" + +/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ +#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */ +#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */ +#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */ +#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */ + +/* registers definitions */ +#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ +#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ + +/* bits definitions */ +/* USARTx_STAT */ +#define USART_STAT_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT_TC BIT(6) /*!< transmission complete */ +#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ + +/* USARTx_DATA */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ + +/* USARTx_CTL0 */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< USART enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) + +/* register offset */ +#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ +#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ + +/* USART flags */ +typedef enum +{ + /* flags in STAT register */ + USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ +}usart_flag_enum; + +/* USART interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ +}usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ +}usart_interrupt_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ + +/* USART CK length */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART DMA request for receive configure */ +#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ + +/* USART DMA request for transmission configure */ +#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ + +/* USART RTS configure */ +#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ + +/* USART CTS configure */ +#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); + +/* USART normal mode communication */ +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* LIN mode enable */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* LIN mode disable */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); +/* send break frame */ +void usart_send_break(uint32_t usart_periph); + +/* half-duplex communication */ +/* half-duplex enable */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* half-duplex disable */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* clock enable */ +void usart_synchronous_clock_enable(uint32_t usart_periph); +/* clock disable */ +void usart_synchronous_clock_disable(uint32_t usart_periph); +/* configure usart synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* guard time value configure in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut); +/* smartcard mode enable */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* smartcard mode disable */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* NACK enable in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* NACK disable in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler */ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); + +/* flag functions */ +/* get flag in STAT register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); + +/* interrupt functions */ +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); +/* clear interrupt flag in STAT register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); +#endif /* GD32F10X_USART_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h new file mode 100644 index 0000000000..c548139baa --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h @@ -0,0 +1,90 @@ +/*! + \file gd32f10x_wwdgt.h + \brief definitions for the WWDGT + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_WWDGT_H +#define GD32F10X_WWDGT_H + +#include "gd32f10x.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); + +#endif /* GD32F10X_WWDGT_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c new file mode 100644 index 0000000000..ab628288bf --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c @@ -0,0 +1,933 @@ +/*! + \file gd32f10x_adc.c + \brief ADC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_adc.h" + +/* discontinuous mode macro*/ +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) + +/* ADC regular channel macro */ +#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) + +/* ADC sampling time macro */ +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) + +/* ADC inserted channel macro */ +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) + +/* ADC inserted channel offset macro */ +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) + +/*! + \brief reset ADC + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_deinit(uint32_t adc_periph) +{ + switch(adc_periph){ + case ADC0: + /* reset ADC0 */ + rcu_periph_reset_enable(RCU_ADC0RST); + rcu_periph_reset_disable(RCU_ADC0RST); + break; + case ADC1: + /* reset ADC1 */ + rcu_periph_reset_enable(RCU_ADC1RST); + rcu_periph_reset_disable(RCU_ADC1RST); + break; +#ifndef GD32F10X_CL + case ADC2: + rcu_periph_reset_enable(RCU_ADC2RST); + rcu_periph_reset_disable(RCU_ADC2RST); + break; +#endif /* GD32F10X_CL */ + default: + break; + } +} + +/*! + \brief configure the ADC sync mode + \param[in] mode: ADC mode + only one parameter can be selected which is shown as below: + \arg ADC_MODE_FREE: all the ADCs work independently + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only + \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only + \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only + \param[out] none + \retval none +*/ +void adc_mode_config(uint32_t mode) +{ + ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); + ADC_CTL0(ADC0) |= mode; +} + +/*! + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (function & ADC_SCAN_MODE)){ + /* enable scan mode */ + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* enable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* enable continuous mode */ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + }else{ + if(0U != (function & ADC_SCAN_MODE)){ + /* disable scan mode */ + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* disable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* disable continuous mode */ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment){ + /* MSB alignment */ + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + }else{ + /* LSB alignment */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + /* enable ADC */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + /* disable ADC */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC1 calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + } +} + +/*! + \brief enable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_enable(void) +{ + /* enable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; +} + +/*! + \brief disable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_disable(void) +{ + /* disable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + /* enable DMA request */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + /* disable DMA request */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel, the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) +{ + /* disable discontinuous mode of regular & inserted channel */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* config the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + /* enable regular channel group discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + /* enable inserted channel group discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + /* disable discontinuous mode of regular & inserted channel */ + default: + break; + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure the length of regular channel group */ + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + break; + case ADC_INSERTED_CHANNEL: + /* configure the length of inserted channel group */ + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint32_t rsq,sampt; + + /* ADC regular sequence config */ + if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ + /* the regular group sequence rank is smaller than six */ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); + ADC_RSQ2(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ + /* the regular group sequence rank is smaller than twelve */ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); + ADC_RSQ1(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ + /* the regular group sequence rank is smaller than sixteen */ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); + ADC_RSQ0(adc_periph) = rsq; + }else{ + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the regular group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the regular group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq,sampt; + /* get inserted channel group length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); + ADC_ISQ(adc_periph) = isq; + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the inserted group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the inserted group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] inserted_channel: insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset: the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); + + if(num <= ADC_OFFSET_LENGTH){ + /* calculate the offset of the register */ + num = num * ADC_OFFSET_SHIFT_LENGTH; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief configure ADC external trigger source + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected + for regular channel: + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select + \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 + \arg ADC2_EXTTRIG_REGULAR_T2_CH0: TIMER2 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T1_CH2: TIMER1 CH2 event select + \arg ADC2_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC2_EXTTRIG_REGULAR_T7_CH0: TIMER7 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH0: TIMER4 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH2: TIMER4 CH2 event select + \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select + \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T3_CH2: TIMER3 CH2 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH1: TIMER7 CH1 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: TIMER4 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T4_CH3: TIMER4 CH3 event select + \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure ADC regular group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief configure ADC external trigger + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected which are shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* enable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* enable ADC inserted channel group external trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; + } + }else{ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* disable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* disable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; + } + } +} + +/*! + \brief enable ADC software trigger + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected which are shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* enable ADC regular channel group software trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* enable ADC inserted channel group software trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted group data register + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] inserted_channel: insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel){ + case ADC_INSERTED_CHANNEL_0: + /* read the data of channel 0 */ + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + /* read the data of channel 1 */ + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + /* read the data of channel 2 */ + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + /* read the data of channel 3 */ + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief read the last ADC0 and ADC1 conversion result data in sync mode + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint32_t adc_sync_mode_convert_value_read(void) +{ + /* return conversion value */ + return ADC_RDATA(ADC0); +} + + +/*! + \brief configure ADC analog watchdog single channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); + /* analog watchdog channel select */ + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); + /* select the group */ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* regular channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + /* inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + /* regular and inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_watchdog_disable(uint32_t adc_periph) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] low_threshold: analog watchdog low threshold, 0..4095 + \param[in] high_threshold: analog watchdog high threshold, 0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) +{ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief get the ADC flag bits + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) +{ + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & adc_flag){ + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag bits + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_flag: the adc flag bits + one or more parameters can be selected which are shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); +} + +/*! + \brief get the bit state of ADCx software start conversion + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){ + reval = SET; + } + return reval; +} + +/*! + \brief get the bit state of ADCx software inserted channel start conversion + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){ + reval = SET; + } + return reval; +} + +/*! + \brief get the ADC interrupt bits + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_interrupt: the adc interrupt bits + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(adc_interrupt){ + case ADC_INT_FLAG_WDE: + /* get the ADC analog watchdog interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + /* get the ADC end of group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + /* get the ADC end of inserted group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear the ADC flag + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_interrupt: the adc status flag + one or more parameters can be selected which are shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); +} + +/*! + \brief enable ADC interrupt + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_interrupt: the adc interrupt + one or more parameters can be selected which are shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + /* enable ADC analog watchdog interrupt */ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; + } + /* enable ADC end of group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + } + /* enable ADC end of inserted group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOIC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; + } +} + +/*! + \brief disable ADC interrupt + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_interrupt: the adc interrupt flag + one or more parameters can be selected which are shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + /* disable ADC analog watchdog interrupt */ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; + } + /* disable ADC end of group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; + } + /* disable ADC end of inserted group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOIC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; + } +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c new file mode 100644 index 0000000000..69e0c6a93b --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c @@ -0,0 +1,296 @@ +/*! + \file gd32f10x_bkp.c + \brief BKP driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_bkp.h" + +/* BKP register bits offset */ +#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U) + +/*! + \brief reset BKP registers + \param[in] none + \param[out] none + \retval none +*/ +void bkp_deinit(void) +{ + /* reset BKP domain register*/ + rcu_bkp_reset_enable(); + rcu_bkp_reset_disable(); +} + +/*! + \brief write BKP data register + \param[in] register_number: refer to bkp_data_register_enum + only one parameter can be selected which is shown as below: + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[in] data: the data to be write in BKP data register + \param[out] none + \retval none +*/ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) +{ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + BKP_DATA10_41(register_number - 1U) = data; + }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + BKP_DATA0_9(register_number - 1U) = data; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief read BKP data register + \param[in] register_number: refer to bkp_data_register_enum + only one parameter can be selected which is shown as below: + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[out] none + \retval data of BKP data register +*/ +uint16_t bkp_data_read(bkp_data_register_enum register_number) +{ + uint16_t data = 0U; + + /* get the data from the BKP data register */ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + data = BKP_DATA10_41(register_number - 1U); + }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + data = BKP_DATA0_9(register_number - 1U); + }else{ + /* illegal parameters */ + } + return data; +} + +/*! + \brief enable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; +} + +/*! + \brief disable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; +} + +/*! + \brief enable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; +} + +/*! + \brief disable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; +} + +/*! + \brief select RTC output + \param[in] outputsel: RTC output selection + only one parameter can be selected which is shown as below: + \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output + \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output + \param[out] none + \retval none +*/ +void bkp_rtc_output_select(uint16_t outputsel) +{ + uint16_t ctl = 0U; + + /* configure BKP_OCTL_ROSEL with outputsel */ + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_ROSEL; + ctl |= outputsel; + BKP_OCTL = ctl; +} + +/*! + \brief set RTC clock calibration value + \param[in] value: RTC clock calibration value + \arg 0x00 - 0x7F + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_value_set(uint8_t value) +{ + uint16_t ctl; + + /* configure BKP_OCTL_RCCV with value */ + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_RCCV; + ctl |= (uint16_t)OCTL_RCCV(value); + BKP_OCTL = ctl; +} + +/*! + \brief enable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_enable(void) +{ + BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; +} + +/*! + \brief disable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_disable(void) +{ + BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; +} + +/*! + \brief set tamper pin active level + \param[in] level: tamper active level + only one parameter can be selected which is shown as below: + \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high + \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low + \param[out] none + \retval none +*/ +void bkp_tamper_active_level_set(uint16_t level) +{ + uint16_t ctl = 0U; + + /* configure BKP_TPCTL_TPAL with level */ + ctl = BKP_TPCTL; + ctl &= (uint16_t)~BKP_TPCTL_TPAL; + ctl |= level; + BKP_TPCTL = ctl; +} + +/*! + \brief enable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_enable(void) +{ + BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; +} + +/*! + \brief disable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_disable(void) +{ + BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; +} + +/*! + \brief get tamper flag state + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_flag_get(void) +{ + if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear tamper flag state + \param[in] none + \param[out] none + \retval none +*/ +void bkp_flag_clear(void) +{ + BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); +} + +/*! + \brief get tamper interrupt flag state + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_interrupt_flag_get(void) +{ + if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear tamper interrupt flag state + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_flag_clear(void) +{ + BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c new file mode 100644 index 0000000000..95ca2dd050 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c @@ -0,0 +1,993 @@ +/*! + \file gd32f10x_can.c + \brief CAN driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_can.h" + +#define CAN_ERROR_HANDLE(s) do{}while(1) + +/*! + \brief deinitialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_deinit(uint32_t can_periph) +{ +#ifdef GD32F10x_CL + if(CAN0 == can_periph){ + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + }else{ + rcu_periph_reset_enable(RCU_CAN1RST); + rcu_periph_reset_disable(RCU_CAN1RST); + } +#else + if(CAN0 == can_periph){ + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + } +#endif +} + +/*! + \brief initialize CAN parameter struct with a default value + \param[in] type: the type of CAN parameter struct + only one parameter can be selected which is shown as below: + \arg CAN_INIT_STRUCT: the CAN initial struct + \arg CAN_FILTER_STRUCT: the CAN filter struct + \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct + \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct + \param[in] p_struct: the pointer of the specific struct + \param[out] none + \retval none +*/ +void can_struct_para_init(can_struct_type_enum type, void* p_struct) +{ + uint8_t i; + + /* get type of the struct */ + switch(type){ + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE; + ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; + ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct*)p_struct)->rx_efid = 0U; + ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct*)p_struct)->rx_fi = 0U; + ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); + } +} + +/*! + \brief initialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0000 - 0x03FF + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) +{ + uint32_t timeout = CAN_TIMEOUT; + ErrStatus flag = ERROR; + + /* disable sleep mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + /* enable initialize mode */ + CAN_CTL(can_periph) |= CAN_CTL_IWMOD; + /* wait ACK */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + /* check initialize working success */ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = ERROR; + }else{ + /* set the bit timing register */ + CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ + BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ + BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ + BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ + BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + + /* time trigger communication mode */ + if(ENABLE == can_parameter_init->time_triggered){ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + } + /* automatic bus-off managment */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery){ + CAN_CTL(can_periph) |= CAN_CTL_ABOR; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; + } + /* automatic wakeup mode */ + if(ENABLE == can_parameter_init->auto_wake_up){ + CAN_CTL(can_periph) |= CAN_CTL_AWU; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_AWU; + } + /* automatic retransmission mode disable*/ + if(ENABLE == can_parameter_init->auto_retrans){ + CAN_CTL(can_periph) |= CAN_CTL_ARD; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } + /* receive fifo overwrite mode */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite){ + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } + /* transmit fifo order */ + if(ENABLE == can_parameter_init->trans_fifo_order){ + CAN_CTL(can_periph) |= CAN_CTL_TFO; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_TFO; + } + /* disable initialize mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; + timeout = CAN_TIMEOUT; + /* wait the ACK */ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + /* check exit initialize mode */ + if(0U != timeout){ + flag = SUCCESS; + } + } + return flag; +} + +/*! + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) +{ + uint32_t val = 0U; + + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* disable filter */ + CAN_FW(CAN0) &= ~(uint32_t)val; + + /* filter 16 bits */ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ + /* set filter 16 bits */ + CAN_FSCFG(CAN0) &= ~(uint32_t)val; + /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + } + /* filter 32 bits */ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ + /* set filter 32 bits */ + CAN_FSCFG(CAN0) |= (uint32_t)val; + /* 32 bits list or first 32 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* 32 bits mask or second 32 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + } + + /* filter mode */ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ + /* mask mode */ + CAN_FMCFG(CAN0) &= ~(uint32_t)val; + }else{ + /* list mode */ + CAN_FMCFG(CAN0) |= (uint32_t)val; + } + + /* filter FIFO */ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ + /* FIFO0 */ + CAN_FAFIFO(CAN0) &= ~(uint32_t)val; + }else{ + /* FIFO1 */ + CAN_FAFIFO(CAN0) |= (uint32_t)val; + } + + /* filter working */ + if(ENABLE == can_filter_parameter_init->filter_enable){ + + CAN_FW(CAN0) |= (uint32_t)val; + } + + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief set CAN1 fliter start bank number + \param[in] start_bank: CAN1 start bank number + only one parameter can be selected which is shown as below: + \arg (1..27) + \param[out] none + \retval none +*/ +void can1_filter_start_bank(uint8_t start_bank) +{ + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* set CAN1 filter start number */ + CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; + CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); + /* filter lock enaable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief enable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_debug_freeze_enable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; +#ifdef GD32F10x_CL + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + }else{ + dbg_periph_enable(DBG_CAN1_HOLD); + } +#else + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + } +#endif +} + +/*! + \brief disable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_debug_freeze_disable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; +#ifdef GD32F10x_CL + if(CAN0 == can_periph){ + dbg_periph_disable(DBG_CAN0_HOLD); + }else{ + dbg_periph_disable(DBG_CAN1_HOLD); + } +#else + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + } +#endif +} + +/*! + \brief enable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_time_trigger_mode_enable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* enable the tcc mode */ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + /* enable time stamp */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; + } +} + +/*! + \brief disable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_time_trigger_mode_disable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* disable the TCC mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + /* reset TSEN bits */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; + } +} + +/*! + \brief transmit CAN message + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlenc: 1 - 7 + \arg tx_data[]: 0x00 - 0xFF + \param[out] none + \retval mailbox_number +*/ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) +{ + uint8_t mailbox_number = CAN_MAILBOX0; + + /* select one empty mailbox */ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ + mailbox_number = CAN_MAILBOX0; + }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ + mailbox_number = CAN_MAILBOX1; + }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ + mailbox_number = CAN_MAILBOX2; + }else{ + mailbox_number = CAN_NOMAILBOX; + } + /* return no mailbox empty */ + if(CAN_NOMAILBOX == mailbox_number){ + return CAN_NOMAILBOX; + } + + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; + if(CAN_FF_STANDARD == transmit_message->tx_ff){ + /* set transmit mailbox standard identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ + transmit_message->tx_ft); + }else{ + /* set transmit mailbox extended identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ + transmit_message->tx_ff | \ + transmit_message->tx_ft); + } + /* set the data length */ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; + CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; + /* set the data */ + CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); + CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); + /* enable transmission */ + CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; + + return mailbox_number; +} + +/*! + \brief get CAN transmit state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOX(x=0,1,2) + \param[out] none + \retval can_transmit_state_enum +*/ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) +{ + can_transmit_state_enum state = CAN_TRANSMIT_FAILED; + uint32_t val = 0U; + + /* check selected mailbox state */ + switch(mailbox_number){ + /* mailbox0 */ + case CAN_MAILBOX0: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); + break; + /* mailbox1 */ + case CAN_MAILBOX1: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); + break; + /* mailbox2 */ + case CAN_MAILBOX2: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); + break; + default: + val = CAN_TRANSMIT_FAILED; + break; + } + + switch(val){ + /* transmit pending */ + case (CAN_STATE_PENDING): + state = CAN_TRANSMIT_PENDING; + break; + /* mailbox0 transmit succeeded */ + case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + state = CAN_TRANSMIT_OK; + break; + /* mailbox1 transmit succeeded */ + case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + state = CAN_TRANSMIT_OK; + break; + /* mailbox2 transmit succeeded */ + case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + state = CAN_TRANSMIT_OK; + break; + /* transmit failed */ + default: + state = CAN_TRANSMIT_FAILED; + break; + } + return state; +} + +/*! + \brief stop CAN transmission + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOXx(x=0,1,2) + \param[out] none + \retval none +*/ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) +{ + if(CAN_MAILBOX0 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + } + }else if(CAN_MAILBOX1 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + } + }else if(CAN_MAILBOX2 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + } + }else{ + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlenc: 1 - 7 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 + \retval none +*/ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) +{ + /* get the frame format */ + receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); + if(CAN_FF_STANDARD == receive_message->rx_ff){ + /* get standard identifier */ + receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + }else{ + /* get extended identifier */ + receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + } + + /* get frame type */ + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); + /* filtering index */ + receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + /* get recevie data length */ + receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + + /* receive data */ + receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + + /* release FIFO */ + if(CAN_FIFO0 == fifo_number){ + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + }else{ + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } +} + +/*! + \brief release FIFO0 + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval none +*/ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) +{ + if(CAN_FIFO0 == fifo_number){ + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + }else if(CAN_FIFO1 == fifo_number){ + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + }else{ + /* illegal parameters */ + CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); + } +} + +/*! + \brief CAN receive message length + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval message length +*/ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) +{ + uint8_t val = 0U; + + if(CAN_FIFO0 == fifo_number){ + /* FIFO0 */ + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + }else if(CAN_FIFO1 == fifo_number){ + /* FIFO1 */ + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); + }else{ + /* illegal parameters */ + } + return val; +} + +/*! + \brief set CAN working mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] can_working_mode + only one parameter can be selected which is shown as below: + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) +{ + ErrStatus flag = ERROR; + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + + if(CAN_MODE_INITIALIZE == working_mode){ + /* disable sleep mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); + /* set initialize mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; + /* wait the acknowledge */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else if(CAN_MODE_NORMAL == working_mode){ + /* enter normal mode */ + CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); + /* wait the acknowledge */ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ + timeout--; + } + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else if(CAN_MODE_SLEEP == working_mode){ + /* disable initialize mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); + /* set sleep mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; + /* wait the acknowledge */ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ + timeout--; + } + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else{ + flag = ERROR; + } + return flag; +} + +/*! + \brief wake up CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_wakeup(uint32_t can_periph) +{ + ErrStatus flag = ERROR; + uint32_t timeout = CAN_TIMEOUT; + + /* wakeup */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ + timeout--; + } + /* check state */ + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + return flag; +} + +/*! + \brief get CAN error type + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval can_error_enum + \arg CAN_ERROR_NONE: no error + \arg CAN_ERROR_FILL: fill error + \arg CAN_ERROR_FORMATE: format error + \arg CAN_ERROR_ACK: ACK error + \arg CAN_ERROR_BITRECESSIVE: bit recessive + \arg CAN_ERROR_BITDOMINANTER: bit dominant error + \arg CAN_ERROR_CRC: CRC error + \arg CAN_ERROR_SOFTWARECFG: software configure +*/ +can_error_enum can_error_get(uint32_t can_periph) +{ + can_error_enum error; + error = CAN_ERROR_NONE; + + /* get error type */ + error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); + return error; +} + +/*! + \brief get CAN receive error number + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval error number +*/ +uint8_t can_receive_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + /* get error count */ + val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief get CAN transmit error number + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval error number +*/ +uint8_t can_transmit_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + +/*! + \brief get CAN flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +{ + /* get flag and interrupt enable state */ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CAN flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \param[out] none + \retval none +*/ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag) +{ + CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); +} + +/*! + \brief get CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag))); + if(ret1 && ret2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval none +*/ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag)); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c new file mode 100644 index 0000000000..0173e9f507 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c @@ -0,0 +1,131 @@ +/*! + \file gd32f10x_crc.c + \brief CRC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_crc.h" + +#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) +#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_DATA = CRC_DATA_RESET_VALUE; + CRC_FDATA = CRC_FDATA_RESET_VALUE; + CRC_CTL = (uint32_t)CRC_CTL_RST; +} + +/*! + \brief reset data register to the value of initializaiton data register + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the value of the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the value of the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write data to the free data register + \param[in] free_data: specify 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief calculate the CRC value of a 32-bit data + \param[in] sdata: specified 32-bit data + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_single_data_calculate(uint32_t sdata) +{ + CRC_DATA = sdata; + return (CRC_DATA); +} + +/*! + \brief calculate the CRC value of an array of 32-bit values + \param[in] array: pointer to an array of 32-bit values + \param[in] size: size of the array + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) +{ + uint32_t index; + for(index = 0U; index < size; index++){ + CRC_DATA = array[index]; + } + return (CRC_DATA); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c new file mode 100644 index 0000000000..b5114a2739 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c @@ -0,0 +1,559 @@ +/*! + \file gd32f10x_dac.c + \brief DAC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_dac.h" + +/* DAC register bit offset */ +#define DAC1_REG_OFFSET ((uint32_t)16U) +#define DH_12BIT_OFFSET ((uint32_t)16U) +#define DH_8BIT_OFFSET ((uint32_t)8U) + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DEN0; + }else{ + DAC_CTL |= DAC_CTL_DEN1; + } +} + +/*! + \brief disable DAC + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DEN1; + } +} + +/*! + \brief enable DAC DMA function + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_dma_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DDMAEN0; + }else{ + DAC_CTL |= DAC_CTL_DDMAEN1; + } +} + +/*! + \brief disable DAC DMA function + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_dma_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DDMAEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DDMAEN1; + } +} + +/*! + \brief enable DAC output buffer + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DBOFF0; + }else{ + DAC_CTL &= ~DAC_CTL_DBOFF1; + } +} + +/*! + \brief disable DAC output buffer + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DBOFF0; + }else{ + DAC_CTL |= DAC_CTL_DBOFF1; + } +} + +/*! + \brief get DAC output value + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(uint32_t dac_periph) +{ + uint16_t data = 0U; + if(DAC0 == dac_periph){ + /* store the DAC0 output value */ + data = (uint16_t)DAC0_DO; + }else{ + /* store the DAC1 output value */ + data = (uint16_t)DAC1_DO; + } + return data; +} + +/*! + \brief set the DAC specified data holding register value + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] dac_align + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +{ + if(DAC0 == dac_periph){ + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } + }else{ + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } + } +} + +/*! + \brief enable DAC trigger + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DTEN0; + }else{ + DAC_CTL |= DAC_CTL_DTEN1; + } +} + +/*! + \brief disable DAC trigger + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DTEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DTEN1; + } +} + +/*! + \brief set DAC trigger source + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] triggersource: external triggers of DAC + only one parameter can be selected which is shown as below: + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F10X_CL) + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO + \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F10X_MD and GD32F10X_HD and GD32F10X_XD) + \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL0; + DAC_CTL |= triggersource; + }else{ + /* configure DAC1 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL1; + DAC_CTL |= (triggersource << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC software trigger + \param[in] dac_periph + \arg DACx(x=0,1) + \retval none +*/ +void dac_software_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT |= DAC_SWT_SWTR0; + }else{ + DAC_SWT |= DAC_SWT_SWTR1; + } +} + +/*! + \brief disable DAC software trigger + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT &= ~DAC_SWT_SWTR0; + }else{ + DAC_SWT &= ~DAC_SWT_SWTR1; + } +} + +/*! + \brief configure DAC wave mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] wave_mode + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM0; + DAC_CTL |= wave_mode; + }else{ + /* configure DAC1 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM1; + DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC wave bit width + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] bit_width + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= bit_width; + }else{ + /* configure DAC1 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (bit_width << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] unmask_bits + only one parameter can be selected which is shown as below: + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= unmask_bits; + }else{ + /* configure DAC1 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC triangle noise mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] amplitude + only one parameter can be selected which is shown as below: + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= amplitude; + }else{ + /* configure DAC1 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (amplitude << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL &= (~ctl); +} + +/*! + \brief enable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_enable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT |= (swt); +} + +/*! + \brief disable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_disable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT &= (~swt); +} + +/*! + \brief enable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL &= (~ctl); +} + +/*! + \brief disable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL |= (ctl); +} + +/*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c new file mode 100644 index 0000000000..f8b74c727f --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c @@ -0,0 +1,153 @@ +/*! + \file gd32f10x_dbg.c + \brief DBG driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_dbg.h" + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + one or more parameters can be selected which are shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_CTL |= (uint32_t)dbg_periph; +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + one or more parameters can be selected which are shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD and CL series): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_CTL &= ~(uint32_t)dbg_periph; +} + +/*! + \brief enable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_enable(void) +{ + DBG_CTL |= DBG_CTL_TRACE_IOEN; +} + +/*! + \brief disable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_disable(void) +{ + DBG_CTL &= ~DBG_CTL_TRACE_IOEN; +} + +/*! + \brief trace pin mode selection + \param[in] trace_mode: + only one parameter can be selected which is shown as below: + \arg TRACE_MODE_ASYNC: trace pin used for async mode + \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 + \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 + \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 + \param[out] none + \retval none +*/ +void dbg_trace_pin_mode_set(uint32_t trace_mode) +{ + DBG_CTL &= ~DBG_CTL_TRACE_MODE; + DBG_CTL |= trace_mode; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c new file mode 100644 index 0000000000..801d69130d --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c @@ -0,0 +1,737 @@ +/*! + \file gd32f10x_dma.c + \brief DMA driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_dma.h" + +#define DMA_WRONG_HANDLE while(1){} + + /* check whether peripheral matches channels or not */ +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); + +/*! + \brief deinitialize DMA a channel registers + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is deinitialized + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* disable DMA a channel */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize the parameters of DMA struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_struct_para_init(dma_parameter_struct* init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; + init_struct->number = 0U; + init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width,memory transfer width, */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + }else{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + }else{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + }else{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHPADDR(dma_periph, channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set memory base address + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHMADDR(dma_periph, channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] number: the number of remaining data to be transferred by the DMA + \arg 0x0000-0xFFFF + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + return (uint32_t)DMA_CHCNT(dma_periph, channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] priority: priority Level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] mwidth: transfer data width of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] pwidth: transfer data width of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + if(DMA_PERIPHERAL_TO_MEMORY == direction){ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + /* check whether the flag is set or not */ + if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ + reval = SET; + }else{ + reval = RESET; + } + + return reval; +} + +/*! + \brief clear the flag of a DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch(flag){ + case DMA_INT_FLAG_FTF: + /* check whether the full transfer finish interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + /* check whether the half transfer finish interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + /* check whether the error interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + default: + DMA_WRONG_HANDLE + } + + /* when the interrupt flag is set and enabled, return SET */ + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to enbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to disbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~source; +} + +/*! + \brief check whether peripheral and channels match + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) +{ + ErrStatus val = SUCCESS; + + if(DMA1 == dma_periph){ + /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ + if(channelx > DMA_CH4){ + val = ERROR; + } + } + + return val; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c new file mode 100644 index 0000000000..e614de1670 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c @@ -0,0 +1,3074 @@ +/*! + \file gd32f10x_enet.c + \brief ENET driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_enet.h" + +#ifdef GD32F10X_CL + +#if defined (__CC_ARM) /*!< ARM compiler */ +__align(4) +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +__align(4) +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +__align(4) +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +__align(4) +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined ( __ICCARM__ ) /*!< IAR compiler */ +#pragma data_alignment=4 +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +#pragma data_alignment=4 +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +#pragma data_alignment=4 +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +#pragma data_alignment=4 +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#endif /* __CC_ARM */ + +/* global transmit and receive descriptors pointers */ +enet_descriptors_struct *dma_current_txdesc; +enet_descriptors_struct *dma_current_rxdesc; + +/* structure pointer of ptp descriptor for normal mode */ +enet_descriptors_struct *dma_current_ptp_txdesc = NULL; +enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; + +/* init structure parameters for ENET initialization */ +static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + +static uint32_t enet_unknow_err = 0U; + +/* array of register offset for debug information get */ +static const uint16_t enet_reg_tab[] = { +0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C, +0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, + +0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + +0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, + +0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C, +0x1050, 0x1054}; + + +/*! + \brief deinitialize the ENET, and reset structure parameters for ENET initialization + \param[in] none + \param[out] none + \retval none +*/ +void enet_deinit(void) +{ + rcu_periph_reset_enable(RCU_ENETRST); + rcu_periph_reset_disable(RCU_ENETRST); + enet_initpara_reset(); +} + +/*! + \brief configure the parameters which are usually less cared for initialization + note -- this function must be called before enet_init(), otherwise + configuration will be no effect + \param[in] option: different function option, which is related to several parameters, + only one parameter can be selected which is shown as below, refer to enet_option_enum + \arg FORWARD_OPTION: choose to configure the frame forward related parameters + \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters + \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters + \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters + \arg STORE_OPTION: choose to configure the store forward mode related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg VLAN_OPTION: choose to configure vlan related parameters + \arg FLOWCTL_OPTION: choose to configure flow control related parameters + \arg HASHH_OPTION: choose to configure hash high + \arg HASHL_OPTION: choose to configure hash low + \arg FILTER_OPTION: choose to configure frame filter related parameters + \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters + \arg TIMER_OPTION: choose to configure time counter related parameters + \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters + \param[in] para: the related parameters according to the option + all the related parameters should be configured which are shown as below + FORWARD_OPTION related parameters: + - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; + - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; + - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . + DMABUS_OPTION related parameters: + - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; + - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; + DMA_MAXBURST_OPTION related parameters: + - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ + ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ + ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ + ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ + ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; + - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ + ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ + ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ + ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ + ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; + - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; + DMA_ARBITRATION_OPTION related parameters: + - ENET_ARBITRATION_RXPRIORTX / ENET_ARBITRATION_RXTX_1_1 + / ENET_ARBITRATION_RXTX_2_1/ ENET_ARBITRATION_RXTX_3_1 + / ENET_ARBITRATION_RXTX_4_1. + STORE_OPTION related parameters: + - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; + - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; + - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ + ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; + - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ + ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ + ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ + ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . + DMA_OPTION related parameters: + - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; + - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE . + VLAN_OPTION related parameters: + - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; + - MAC_VLT_VLTI(regval) . + FLOWCTL_OPTION related parameters: + - MAC_FCTL_PTM(regval) ; + - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; + - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; + - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; + - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . + HASHH_OPTION related parameters: + - 0x0~0xFFFF FFFFU + HASHL_OPTION related parameters: + - 0x0~0xFFFF FFFFU + FILTER_OPTION related parameters: + - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ + ENET_SRC_FILTER_DISABLE ; + - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; + - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ + ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; + - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ + ENET_UNICAST_FILTER_PERFECT ; + - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ + ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . + HALFDUPLEX_OPTION related parameters: + - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; + - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; + - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; + - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ + ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; + - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . + TIMER_OPTION related parameters: + - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; + - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; + INTERFRAMEGAP_OPTION related parameters: + - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ + ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ + ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ + ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . + \param[out] none + \retval none +*/ +void enet_initpara_config(enet_option_enum option, uint32_t para) +{ + switch(option){ + case FORWARD_OPTION: + /* choose to configure forward_frame, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; + enet_initpara.forward_frame = para; + break; + case DMABUS_OPTION: + /* choose to configure dmabus_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; + enet_initpara.dmabus_mode = para; + break; + case DMA_MAXBURST_OPTION: + /* choose to configure dma_maxburst, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; + enet_initpara.dma_maxburst = para; + break; + case DMA_ARBITRATION_OPTION: + /* choose to configure dma_arbitration, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; + enet_initpara.dma_arbitration = para; + break; + case STORE_OPTION: + /* choose to configure store_forward_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)STORE_OPTION; + enet_initpara.store_forward_mode = para; + break; + case DMA_OPTION: + /* choose to configure dma_function, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_OPTION; + enet_initpara.dma_function = para; + break; + case VLAN_OPTION: + /* choose to configure vlan_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; + enet_initpara.vlan_config = para; + break; + case FLOWCTL_OPTION: + /* choose to configure flow_control, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; + enet_initpara.flow_control = para; + break; + case HASHH_OPTION: + /* choose to configure hashtable_high, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; + enet_initpara.hashtable_high = para; + break; + case HASHL_OPTION: + /* choose to configure hashtable_low, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; + enet_initpara.hashtable_low = para; + break; + case FILTER_OPTION: + /* choose to configure framesfilter_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; + enet_initpara.framesfilter_mode = para; + break; + case HALFDUPLEX_OPTION: + /* choose to configure halfduplex_param, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; + enet_initpara.halfduplex_param = para; + break; + case TIMER_OPTION: + /* choose to configure timer_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; + enet_initpara.timer_config = para; + break; + case INTERFRAMEGAP_OPTION: + /* choose to configure interframegap, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; + enet_initpara.interframegap = para; + break; + default: + break; + } +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters and the less cared + parameters + \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected + which is shown as below, refer to enet_mediamode_enum + \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation + \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex + \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex + \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex + \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex + \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII + \param[in] checksum: IP frame checksum offload function, only one parameter can be selected + which is shown as below, refer to enet_mediamode_enum + \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function + \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function + \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped + \param[in] recept: frame filter function, only one parameter can be selected + which is shown as below, refer to enet_frmrecept_enum + \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled + \arg ENET_RECEIVEALL: all received frame are forwarded to application + \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames + \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) +{ + uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; + uint32_t media_temp = 0U; + uint32_t timeout = 0U; + uint16_t phy_value = 0U; + ErrStatus phy_state= ERROR, enet_state = ERROR; + + /* PHY interface configuration, configure SMI clock and reset PHY chip */ + if(ERROR == enet_phy_config()){ + _ENET_DELAY_(PHY_RESETDELAY); + if(ERROR == enet_phy_config()){ + return enet_state; + } + } + /* initialize ENET peripheral with generally concerned parameters */ + enet_default_init(); + + /* 1st, configure mediamode */ + media_temp = (uint32_t)mediamode; + /* if is PHY auto negotiation */ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ + /* wait for PHY_LINKED_STATUS bit be set */ + do{ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_LINKED_STATUS; + timeout++; + }while((RESET == phy_value) && (timeout < PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout){ + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* enable auto-negotiation */ + phy_value = PHY_AUTONEGOTIATION; + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state){ + /* return ERROR due to write timeout */ + return enet_state; + } + + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ + do{ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_AUTONEGO_COMPLETE; + timeout++; + }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout){ + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* read the result of the auto-negotiation */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + /* configure the duplex mode of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ + media_temp = ENET_MODE_FULLDUPLEX; + }else{ + media_temp = ENET_MODE_HALFDUPLEX; + } + /* configure the communication speed of MAC following the auto-negotiation result */ + if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ + media_temp |= ENET_SPEEDMODE_10M; + }else{ + media_temp |= ENET_SPEEDMODE_100M; + } + }else{ + phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); + phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state){ + /* return ERROR due to write timeout */ + return enet_state; + } + /* PHY configuration need some time */ + _ENET_DELAY_(PHY_CONFIGDELAY); + } + /* after configuring the PHY, use mediamode to configure registers */ + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); + reg_value |= media_temp; + ENET_MAC_CFG = reg_value; + + + /* 2st, configure checksum */ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ + ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~ENET_DMA_CTL_DTCERFD; + reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); + ENET_DMA_CTL = reg_value; + } + + /* 3rd, configure recept */ + ENET_MAC_FRMF |= (uint32_t)recept; + + /* 4th, configure different function options */ + /* configure forward_frame related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ + reg_temp = enet_initpara.forward_frame; + + reg_value = ENET_MAC_CFG; + temp = reg_temp; + /* configure ENET_MAC_CFG register */ + reg_value &= (~ENET_MAC_CFG_APCD); + temp &= ENET_MAC_CFG_APCD; + reg_value |= temp; + ENET_MAC_CFG = reg_value; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); + reg_value |= (temp >> 2); + ENET_DMA_CTL = reg_value; + } + + /* configure dmabus_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ + temp = enet_initpara.dmabus_mode; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ + |ENET_DMA_BCTL_FPBL); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_maxburst related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ + temp = enet_initpara.dma_maxburst; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_arbitration related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ + temp = enet_initpara.dma_arbitration; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure store_forward_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ + temp = enet_initpara.store_forward_mode; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + } + + /* configure dma_function related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ + reg_temp = enet_initpara.dma_function; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); + reg_value |= reg_temp; + ENET_DMA_CTL = reg_value; + } + + /* configure vlan_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ + reg_temp = enet_initpara.vlan_config; + + reg_value = ENET_MAC_VLT; + /* configure ENET_MAC_VLT register */ + reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); + reg_value |= reg_temp; + ENET_MAC_VLT = reg_value; + } + + /* configure flow_control related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ + reg_temp = enet_initpara.flow_control; + + reg_value = ENET_MAC_FCTL; + temp = reg_temp; + /* configure ENET_MAC_FCTL register */ + reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + reg_value |= temp; + ENET_MAC_FCTL = reg_value; + + reg_value = ENET_MAC_FCTH; + temp = reg_temp; + /* configure ENET_MAC_FCTH register */ + reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); + reg_value |= (temp >> 8); + ENET_MAC_FCTH = reg_value; + } + + /* configure hashtable_high related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ + ENET_MAC_HLH = enet_initpara.hashtable_high; + } + + /* configure hashtable_low related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ + ENET_MAC_HLL = enet_initpara.hashtable_low; + } + + /* configure framesfilter_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ + reg_temp = enet_initpara.framesfilter_mode; + + reg_value = ENET_MAC_FRMF; + /* configure ENET_MAC_FRMF register */ + reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + reg_value |= reg_temp; + ENET_MAC_FRMF = reg_value; + } + + /* configure halfduplex_param related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ + reg_temp = enet_initpara.halfduplex_param; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure timer_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ + reg_temp = enet_initpara.timer_config; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure interframegap related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ + reg_temp = enet_initpara.interframegap; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~ENET_MAC_CFG_IGBS; + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + enet_state = SUCCESS; + return enet_state; +} + +/*! + \brief reset all core internal registers located in CLK_TX and CLK_RX + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_software_reset(void) +{ + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + uint32_t dma_flag; + + /* reset all core internal registers located in CLK_TX and CLK_RX */ + ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; + + /* wait for reset operation complete */ + do{ + dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); + timeout++; + }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + + /* reset operation complete */ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief check receive frame valid and return frame size + \param[in] none + \param[out] none + \retval size of received frame: 0x0 - 0x3FFF +*/ +uint32_t enet_rxframe_size_get(void) +{ + uint32_t size = 0U; + uint32_t status; + + /* get rdes0 information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + + /* if the desciptor is owned by DMA */ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ + return 0U; + } + + /* if has any error, or the frame uses two or more descriptors */ + if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } + + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } + + /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ + if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ + /* get the size of the received data including CRC */ + size = GET_RDES0_FRML(status); + /* substract the CRC size */ + size = size - 4U; + }else{ + enet_unknow_err++; + enet_rxframe_drop(); + + return 1U; + } + + /* return packet size */ + return size; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode */ + desc_status = ENET_TDES0_TCHM; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num=0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)){ + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + }else{ + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num=0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)){ + if (ENET_DMA_TX == direction){ + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + }else{ + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief handle current received frame data to application buffer + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the received frame data + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + return ERROR; + } + + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer){ + /* if no error occurs, and the frame uses only one descriptor */ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status); + size = size - 4U; + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize){ + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offsetbuffer1_addr) + offset)); + } + + }else{ + /* return ERROR */ + return ERROR; + } + } + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief handle application buffer data to transmit it + \param[in] buffer: pointer to the frame data to be transmitted, + note -- if the input is NULL, user should handle the data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) +{ + uint32_t offset = 0U; + uint32_t dma_tbu_flag, dma_tu_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer){ + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++){ + (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief configure the transmit IP frame checksum offload calculation and insertion + \param[in] desc: the descriptor pointer which users want to configure + \param[in] checksum: IP frame checksum configuration + only one parameter can be selected which is shown as below + \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled + \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled + \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header + \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated + \param[out] none + \retval none +*/ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) +{ + desc->status &= ~ENET_TDES0_CM; + desc->status |= checksum; +} + +/*! + \brief ENET Tx and Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_enable(void) +{ + enet_tx_enable(); + enet_rx_enable(); +} + +/*! + \brief ENET Tx and Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_disable(void) +{ + enet_tx_disable(); + enet_rx_disable(); +} + +/*! + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: set MAC address 0 filter + \arg ENET_MAC_ADDRESS1: set MAC address 1 filter + \arg ENET_MAC_ADDRESS2: set MAC address 2 filter + \arg ENET_MAC_ADDRESS3: set MAC address 3 filter + \param[in] paddr: the buffer pointer which stores the MAC address + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \param[out] none + \retval none +*/ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); + REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); +} + +/*! + \brief get MAC address + \param[in] mac_addr: select which MAC address will be get, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: get MAC address 0 filter + \arg ENET_MAC_ADDRESS1: get MAC address 1 filter + \arg ENET_MAC_ADDRESS2: get MAC address 2 filter + \arg ENET_MAC_ADDRESS3: get MAC address 3 filter + \param[out] paddr: the buffer pointer which is stored the MAC address + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \retval none +*/ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); + paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); + paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); + paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); + paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); + paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); +} + +/*! + \brief get the ENET MAC/MSC/PTP/DMA status flag + \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, + only one parameter can be selected which is shown as below + \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_WUM: WUM status flag + \arg ENET_MAC_FLAG_MSC: MSC status flag + \arg ENET_MAC_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag + \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag + \arg ENET_PTP_FLAG_TTM: target time match flag + \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_FLAG_TS: transmit status flag + \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_FLAG_RO: receive overflow status flag + \arg ENET_DMA_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_FLAG_RS: receive status flag + \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_FLAG_ET: early transmit status flag + \arg ENET_DMA_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_FLAG_ER: early receive status flag + \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag + \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag + \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag + \arg ENET_DMA_FLAG_MSC: MSC status flag + \arg ENET_DMA_FLAG_WUM: WUM status flag + \arg ENET_DMA_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_flag_get(enet_flag_enum enet_flag) +{ + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the ENET DMA status flag + \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear + \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear + \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear + \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear + \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear + \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear + \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear + \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear + \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear + \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear + \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear + \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear + \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear + \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear + \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear + \param[out] none + \retval none +*/ +void enet_flag_clear(enet_flag_clear_enum enet_flag) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); +} + +/*! + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_enable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + }else{ + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_disable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + }else{ + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_FLAG_WUM: WUM status flag + \arg ENET_MAC_INT_FLAG_MSC: MSC status flag + \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag + \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_INT_FLAG_TS: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS: receive status flag + \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER: early receive status flag + \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_INT_FLAG_MSC: MSC status flag + \arg ENET_DMA_INT_FLAG_WUM: WUM status flag + \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) +{ + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag + \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag + \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag + \param[out] none + \retval none +*/ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); +} + +/*! + \brief ENET Tx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_TEN; + enet_txfifo_flush(); + ENET_DMA_CTL |= ENET_DMA_CTL_STE; +} + +/*! + \brief ENET Tx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; + enet_txfifo_flush(); + ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; +} + +/*! + \brief ENET Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_REN; + ENET_DMA_CTL |= ENET_DMA_CTL_SRE; +} + +/*! + \brief ENET Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; + ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; +} + +/*! + \brief put registers value into the application buffer + \param[in] type: register type which will be get, refer to enet_registers_type_enum, + only one parameter can be selected which is shown as below + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT + \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL + \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR + \param[in] num: the number of registers that the user want to get + \param[out] preg: the application buffer pointer for storing the register value + \retval none +*/ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) +{ + uint32_t offset = 0U, max = 0U, limit = 0U; + + offset = (uint32_t)type; + max = (uint32_t)type + num; + limit = sizeof(enet_reg_tab)/sizeof(uint16_t); + + /* prevent element in this array is out of range */ + if(max > limit){ + max = limit; + } + + for(; offset < max; offset++){ + /* get value of the corresponding register */ + *preg = REG32((ENET) + enet_reg_tab[offset]); + preg++; + } +} + +/*! + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable + \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_enable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief disable the MAC address filter + \param[in] mac_addr: select which MAC address will be disable, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_disable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief configure the MAC address filter + \param[in] mac_addr: select which MAC address will be configured, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter + \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter + \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter + \param[in] addr_mask: select which MAC address bytes will be mask, + one or more parameters can be selected which are shown as below + \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits + \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits + \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits + \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits + \param[in] filter_type: select which MAC address filter type will be selected, + only one parameter can be selected which is shown as below + \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame + \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame + \param[out] none + \retval none +*/ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) +{ + uint32_t reg; + + /* get the address filter register value which is to be configured */ + reg = REG32(ENET_ADDRH_BASE + mac_addr); + + /* clear and configure the address filter register */ + reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); + reg |= (addr_mask | filter_type); + REG32(ENET_ADDRH_BASE + mac_addr) = reg; +} + +/*! + \brief PHY interface configuration (configure SMI clock and reset PHY chip) + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_config(void) +{ + uint32_t ahbclk; + uint32_t reg; + uint16_t phy_value; + ErrStatus enet_state = ERROR; + + /* clear the previous MDC clock */ + reg = ENET_MAC_PHY_CTL; + reg &= ~ENET_MAC_PHY_CTL_CLR; + + /* get the HCLK frequency */ + ahbclk = rcu_clock_freq_get(CK_AHB); + + /* configure MDC clock according to HCLK frequency range */ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ + reg |= ENET_MDC_HCLK_DIV16; + }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ + reg |= ENET_MDC_HCLK_DIV26; + }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){ + reg |= ENET_MDC_HCLK_DIV42; + }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){ + reg |= ENET_MDC_HCLK_DIV62; + }else{ + return enet_state; + } + ENET_MAC_PHY_CTL = reg; + + /* reset PHY */ + phy_value = PHY_RESET; + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + return enet_state; + } + /* PHY reset need some time */ + _ENET_DELAY_(ENET_DELAY_TO); + + /* check whether PHY reset is complete */ + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + return enet_state; + } + + /* PHY reset complete */ + if(RESET == (phy_value & PHY_RESET)){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief write to / read from a PHY register + \param[in] direction: only one parameter can be selected which is shown as below + \arg ENET_PHY_WRITE: write data to phy register + \arg ENET_PHY_READ: read data from phy register + \param[in] phy_address: 0x0 - 0x1F + \param[in] phy_reg: 0x0 - 0x1F + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) +{ + uint32_t reg, phy_flag; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* configure ENET_MAC_PHY_CTL with write/read operation */ + reg = ENET_MAC_PHY_CTL; + reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + + /* if do the write operation, write value to the register */ + if(ENET_PHY_WRITE == direction){ + ENET_MAC_PHY_DATA = *pvalue; + } + + /* do PHY write/read operation, and wait the operation complete */ + ENET_MAC_PHY_CTL = reg; + do{ + phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); + timeout++; + } + while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + + /* write/read operation complete */ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ + enet_state = SUCCESS; + } + + /* if do the read operation, get value from the register */ + if(ENET_PHY_READ == direction){ + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + } + + return enet_state; +} + +/*! + \brief enable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_enable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* enable the PHY loopback mode */ + temp_phy |= PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief disable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_disable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* disable the PHY loopback mode */ + temp_phy &= (uint16_t)~PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief enable ENET forward feature + \param[in] feature: the feature of ENET forward mode, + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames + \param[out] none + \retval none +*/ +void enet_forward_feature_enable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG |= mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); + ENET_DMA_CTL |= (mask >> 2); +} + +/*! + \brief disable ENET forward feature + \param[in] feature: the feature of ENET forward mode, + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function + \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_forward_feature_disable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG &= ~mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); + ENET_DMA_CTL &= ~(mask >> 2); +} + +/*! + \brief enable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode, + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_enable(uint32_t feature) +{ + ENET_MAC_FRMF |= feature; +} + +/*! + \brief disable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode, + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_disable(uint32_t feature) +{ + ENET_MAC_FRMF &= ~feature; +} + +/*! + \brief generate the pause frame, ENET will send pause frame after enable transmit flow control + this function only use in full-dulex mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_pauseframe_generate(void) +{ + ErrStatus enet_state =ERROR; + uint32_t temp = 0U; + + /* in full-duplex mode, must make sure this bit is 0 before writing register */ + temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; + if(RESET == temp){ + ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; + enet_state = SUCCESS; + } + return enet_state; +} + +/*! + \brief configure the pause frame detect type + \param[in] detect: pause frame detect type, + only one parameter can be selected which is shown as below + \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also + use the MAC0 address to detecting pause frame + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + in IEEE802.3 can be detected + \param[out] none + \retval none +*/ +void enet_pauseframe_detect_config(uint32_t detect) +{ + ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; + ENET_MAC_FCTL |= detect; +} + +/*! + \brief configure the pause frame parameters + \param[in] pausetime: pause time in transmit pause control frame + \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, + this value must make sure to be less than configured pause time, only one parameter can be + selected which is shown as below + \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times + \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times + \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times + \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times + \param[out] none + \retval none +*/ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) +{ + ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); + ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); +} + +/*! + \brief configure the threshold of the flow control(deactive and active threshold) + \param[in] deactive: the threshold of the deactive flow control, this value + should always be less than active flow control value, only one + parameter can be selected which is shown as below + \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[in] active: the threshold of the active flow control, only one parameter + can be selected which is shown as below + \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[out] none + \retval none +*/ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) +{ + ENET_MAC_FCTH = ((deactive | active) >> 8); +} + +/*! + \brief enable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_enable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL |= feature; +} + +/*! + \brief disable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_disable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL &= ~feature; +} + +/*! + \brief get the dma transmit/receive process state + \param[in] direction: choose the direction of dma process which users want to check, + refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: dma transmit process + \arg ENET_DMA_RX: dma receive process + \param[out] none + \retval state of dma process, the value range shows below: + ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, + ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, + ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, + ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING +*/ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) +{ + uint32_t reval; + reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); + return reval; +} + +/*! + \brief poll the DMA transmission/reception enable by writing any value to the + ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception + \param[in] direction: choose the direction of DMA process which users want to resume, + refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA transmit process + \arg ENET_DMA_RX: DMA receive process + \param[out] none + \retval none +*/ +void enet_dmaprocess_resume(enet_dmadirection_enum direction) +{ + if(ENET_DMA_TX == direction){ + ENET_DMA_TPEN = 0U; + }else{ + ENET_DMA_RPEN = 0U; + } +} + +/*! + \brief check and recover the Rx process + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxprocess_check_recovery(void) +{ + uint32_t status; + + /* get DAV information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + status &= ENET_RDES0_DAV; + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with + receive descriptor address pointer updated by RxDMA controller */ + if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && + (ENET_RDES0_DAV == status)){ + dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; + } +} + +/*! + \brief flush the ENET transmit FIFO, and wait until the flush operation completes + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_txfifo_flush(void) +{ + uint32_t flush_state; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* set the FTF bit for flushing transmit FIFO */ + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + /* wait until the flush operation completes */ + do{ + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + timeout++; + }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(RESET == flush_state){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table + \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, + only one parameter can be selected which is shown as below + \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table + \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by + the RxDMA controller + \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller + \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table + \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by + the TxDMA controller + \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller + \param[out] none + \retval address value +*/ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) +{ + uint32_t reval = 0U; + + reval = REG32((ENET) +(uint32_t)addr_get); + return reval; +} + +/*! + \brief get the Tx or Rx descriptor information + \param[in] desc: the descriptor pointer which users want to get information + \param[in] info_get: the descriptor information type which is selected, + only one parameter can be selected which is shown as below + \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size + \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size + \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer + \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted + \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame + \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame + \param[out] none + \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter +*/ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch(info_get){ + case RXDESC_BUFFER_1_SIZE: + reval = GET_RDES1_RB1S(desc->control_buffer_size); + break; + case RXDESC_BUFFER_2_SIZE: + reval = GET_RDES1_RB2S(desc->control_buffer_size); + break; + case RXDESC_FRAME_LENGTH: + reval = GET_RDES0_FRML(desc->status); + if(reval > 4U){ + reval = reval - 4U; + }else{ + reval = 0U; + } + break; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_COLLISION_COUNT: + reval = GET_TDES0_COCNT(desc->status); + break; + default: + break; + } + return reval; +} + +/*! + \brief get the number of missed frames during receiving + \param[in] none + \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO + \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller + \retval none +*/ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) +{ + uint32_t temp_counter = 0U; + + temp_counter = ENET_DMA_MFBOCNT; + *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); + *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); +} + +/*! + \brief get the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_UFE: underflow error + \arg ENET_TDES0_EXD: excessive deferral + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_ECO: excessive collision + \arg ENET_TDES0_LCO: late collision + \arg ENET_TDES0_NCA: no carrier + \arg ENET_TDES0_LCA: loss of carrier + \arg ENET_TDES0_IPPE: IP payload error + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_JT: jabber timeout + \arg ENET_TDES0_ES: error summary + \arg ENET_TDES0_IPHE: IP header error + \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + + \arg ENET_RDES0_PCERR: payload checksum error + \arg ENET_RDES0_CERR: CRC error + \arg ENET_RDES0_DBERR: dribble bit error + \arg ENET_RDES0_RERR: receive error + \arg ENET_RDES0_RWDT: receive watchdog timeout + \arg ENET_RDES0_FRMT: frame type + \arg ENET_RDES0_LCO: late collision + \arg ENET_RDES0_IPHERR: IP frame header error + \arg ENET_RDES0_LDES: last descriptor + \arg ENET_RDES0_FDES: first descriptor + \arg ENET_RDES0_VTAG: VLAN tag + \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_LERR: length error + \arg ENET_RDES0_SAFF: SA filter fail + \arg ENET_RDES0_DERR: descriptor error + \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_DAFF: destination address filter fail + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + FlagStatus enet_flag = RESET; + + if ((uint32_t)RESET != (desc->status & desc_flag)){ + enet_flag = SET; + } + + return enet_flag; +} + +/*! + \brief set the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to set flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status |= desc_flag; +} + +/*! + \brief clear the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to clear flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status &= ~desc_flag; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will set + \param[in] desc: the descriptor pointer which users want to configure + \param[out] none + \retval none +*/ +void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc) +{ + desc->control_buffer_size &= ~ENET_RDES1_DINTC; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will not set + \param[in] desc: the descriptor pointer which users want to configure + \param[out] none + \retval none +*/ +void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc) +{ + desc->control_buffer_size |= ENET_RDES1_DINTC; +} + +/*! + \brief drop current receive frame + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxframe_drop(void) +{ + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + if(NULL != dma_current_ptp_rxdesc){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + }else{ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + } + + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc){ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + } + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc){ + dma_current_ptp_rxdesc++; + } + } + } +} + +/*! + \brief enable DMA feature + \param[in] feature: the feature of DMA mode, + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_enable(uint32_t feature) +{ + ENET_DMA_CTL |= feature; +} + +/*! + \brief disable DMA feature + \param[in] feature: the feature of DMA mode, + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_disable(uint32_t feature) +{ + ENET_DMA_CTL &= ~feature; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)){ + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + }else{ + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive ring mode and set buffer1 size */ + desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)){ + if (ENET_DMA_TX == direction){ + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + }else{ + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] timestamp: pointer to the table which stores the timestamp high and low + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer){ + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize){ + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++){ + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); + } + + }else{ + return ERROR; + } + } + /* copy timestamp value from Rx descriptor to application array */ + timestamp[0] = dma_current_rxdesc->buffer1_addr; + timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; + + dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; + dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with RxDMA descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_rxdesc ++; + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0U, timeout = 0U; + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer){ + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++){ + (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp){ + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do{ + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->buffer1_addr; + timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; + } + dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; + dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_txdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_txdesc++; + } + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with TxDMA descriptor */ + dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; + } + } + return SUCCESS; +} + +/*! + \brief wakeup frame filter register pointer reset + \param[in] none + \param[out] none + \retval none +*/ +void enet_wum_filter_register_pointer_reset(void) +{ + ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; +} + +/*! + \brief set the remote wakeup frame registers + \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) + \param[out] none + \retval none +*/ +void enet_wum_filter_config(uint32_t pdata[]) +{ + uint32_t num = 0U; + + /* configure ENET_MAC_RWFF register */ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ + ENET_MAC_RWFF = pdata[num]; + } +} + +/*! + \brief enable wakeup management features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_WUM_POWER_DOWN: power down mode + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_enable(uint32_t feature) +{ + ENET_MAC_WUM |= feature; +} + +/*! + \brief disable wakeup management features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_disable(uint32_t feature) +{ + ENET_MAC_WUM &= (~feature); +} + +/*! + \brief reset the MAC statistics counters + \param[in] none + \param[out] none + \retval none +*/ +void enet_msc_counters_reset(void) +{ + /* reset all counters */ + ENET_MSC_CTL |= ENET_MSC_CTL_CTR; +} + +/*! + \brief enable the MAC statistics counter features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_enable(uint32_t feature) +{ + ENET_MSC_CTL |= feature; +} + +/*! + \brief disable the MAC statistics counter features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_disable(uint32_t feature) +{ + ENET_MSC_CTL &= (~feature); +} + +/*! + \brief get MAC statistics counter + \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, + only one parameter can be selected which is shown as below + \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter + \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter + \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter + \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter + \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter + \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter + \param[out] none + \retval the MSC counter value +*/ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) +{ + uint32_t reval; + + reval = REG32((ENET + (uint32_t)counter)); + + return reval; +} + +/*! + \brief change subsecond to nanosecond + \param[in] subsecond: subsecond value + \param[out] none + \retval the nanosecond value +*/ +uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) +{ + uint64_t val = subsecond * 1000000000Ull; + val >>= 31; + return (uint32_t)val; +} + +/*! + \brief change nanosecond to subsecond + \param[in] nanosecond: nanosecond value + \param[out] none + \retval the subsecond value +*/ +uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond) +{ + uint64_t val = nanosecond * 0x80000000Ull; + val /= 1000000000U; + return (uint32_t)val; +} + +/*! + \brief enable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \param[out] none + \retval none +*/ +void enet_ptp_feature_enable(uint32_t feature) +{ + ENET_PTP_TSCTL |= feature; +} + +/*! + \brief disable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \param[out] none + \retval none +*/ +void enet_ptp_feature_disable(uint32_t feature) +{ + ENET_PTP_TSCTL &= ~feature; +} + +/*! + \brief configure the PTP timestamp function + \param[in] func: only one parameter can be selected which is shown as below + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating + \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ + +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) +{ + uint32_t temp_config = 0U, temp_state = 0U; + uint32_t timeout = 0U; + ErrStatus enet_state = SUCCESS; + + switch(func){ + case ENET_PTP_ADDEND_UPDATE: + /* this bit must be read as zero before application set it */ + do{ + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; + } + break; + case ENET_PTP_SYSTIME_UPDATE: + /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ + do{ + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; + } + break; + case ENET_PTP_SYSTIME_INIT: + /* this bit must be read as zero before application set it */ + do{ + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; + } + break; + default: + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))){ + ENET_PTP_TSCTL |= temp_config; + }else{ + ENET_PTP_TSCTL &= ~temp_config; + } + break; + } + + return enet_state; +} + +/*! + \brief configure system time subsecond increment value + \param[in] subsecond: the value will be added to the subsecond value of system time, + this value must be between 0 and 0xFF + \param[out] none + \retval none +*/ +void enet_ptp_subsecond_increment_config(uint32_t subsecond) +{ + ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); +} + +/*! + \brief adjusting the clock frequency only in fine update mode + \param[in] add: the value will be added to the accumulator register to achieve time synchronization + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_addend_config(uint32_t add) +{ + ENET_PTP_TSADDEND = add; +} + +/*! + \brief initialize or add/subtract to second of the system time + \param[in] sign: timestamp update positive or negative sign, + only one parameter can be selected which is shown as below + \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time + \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time + \param[in] second: initializing or adding/subtracting to second of the system time + \param[in] subsecond: the current subsecond of the system time + with 0.46 ns accuracy if required accuracy is 20 ns + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) +{ + ENET_PTP_TSUH = second; + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); +} + +/*! + \brief configure the expected target time + \param[in] second: the expected target second time + \param[in] nanosecond: the expected target nanosecond time (signed) + \param[out] none + \retval none +*/ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) +{ + ENET_PTP_ETH = second; + ENET_PTP_ETL = nanosecond; +} + +/*! + \brief get the current system time + \param[in] none + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \retval none +*/ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) +{ + uint32_t temp_sec = 0U, temp_subs = 0U; + + /* get the value of sysytem time registers */ + temp_sec = (uint32_t)ENET_PTP_TSH; + temp_subs = (uint32_t)ENET_PTP_TSL; + + /* get sysytem time and construct the enet_ptp_systime_struct structure */ + systime_struct->second = temp_sec; + systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); + systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); + systime_struct->sign = GET_PTP_TSL_STS(temp_subs); +} + +/*! + \brief configure and start PTP timestamp counter + \param[in] updatemethod: method for updating + \arg ENET_PTP_FINEMODE: fine correction method + \arg ENET_PTP_COARSEMODE: coarse correction method + \param[in] init_sec: second value for initializing system time + \param[in] init_subsec: subsecond value for initializing system time + \param[in] carry_cfg: the value to be added to the accumulator register (in fine method is used) + \param[in] accuracy_cfg: the value to be added to the subsecond value of system time + \param[out] none + \retval none +*/ +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg) +{ + /* mask the timestamp trigger interrupt */ + enet_interrupt_disable(ENET_MAC_INT_TMSTIM); + + /* enable timestamp */ + enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP); + + /* configure system time subsecond increment based on the PTP clock frequency */ + enet_ptp_subsecond_increment_config(accuracy_cfg); + + if(ENET_PTP_FINEMODE == updatemethod){ + /* fine correction method: configure the timestamp addend, then update */ + enet_ptp_timestamp_addend_config(carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); + /* wait until update is completed */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){ + } + } + + /* choose the fine correction method */ + enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod); + + /* initialize the system time */ + enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); +} + +/*! + \brief adjust frequency in fine method by configure addend register + \param[in] carry_cfg: the value to be added to the accumulator register + \param[out] none + \retval none +*/ +void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg) +{ + /* re-configure the timestamp addend, then update */ + enet_ptp_timestamp_addend_config((uint32_t)carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +/*! + \brief update system time in coarse method + \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \param[out] none + \retval none +*/ +void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct) +{ + uint32_t subsecond_val; + uint32_t carry_cfg; + + subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); + + /* save the carry_cfg value */ + carry_cfg = ENET_PTP_TSADDEND_TMSA; + + /* update the system time */ + enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); + + /* wait until the update is completed */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){ + } + + /* write back the carry_cfg value, then update */ + enet_ptp_timestamp_addend_config(carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +/*! + \brief set system time in fine method + \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \param[out] none + \retval none +*/ +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) +{ + uint32_t subsecond_val; + + subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); + + /* initialize the system time */ + enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); + + /* wait until the system time initialzation finished */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){ + } +} + +/*! + \brief get the ptp flag status + \param[in] flag: ptp flag status to be checked + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_ptp_flag_get(uint32_t flag) +{ + FlagStatus bitstatus = RESET; + + if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){ + bitstatus = SET; + } + + return bitstatus; +} + +/*! + \brief reset the ENET initpara struct, call it before using enet_initpara_config() + \param[in] none + \param[out] none + \retval none +*/ +void enet_initpara_reset(void) +{ + enet_initpara.option_enable = 0U; + enet_initpara.forward_frame = 0U; + enet_initpara.dmabus_mode = 0U; + enet_initpara.dma_maxburst = 0U; + enet_initpara.dma_arbitration = 0U; + enet_initpara.store_forward_mode = 0U; + enet_initpara.dma_function = 0U; + enet_initpara.vlan_config = 0U; + enet_initpara.flow_control = 0U; + enet_initpara.hashtable_high = 0U; + enet_initpara.hashtable_low = 0U; + enet_initpara.framesfilter_mode = 0U; + enet_initpara.halfduplex_param = 0U; + enet_initpara.timer_config = 0U; + enet_initpara.interframegap = 0U; +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \param[in] none + \param[out] none + \retval none +*/ +static void enet_default_init(void) +{ + uint32_t reg_value = 0U; + + /* MAC */ + /* configure ENET_MAC_CFG register */ + reg_value = ENET_MAC_CFG; + reg_value &= MAC_CFG_MASK; + reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ + | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; + ENET_MAC_CFG = reg_value; + + /* configure ENET_MAC_FRMF register */ + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ + |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ + |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ + |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; + + /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ + ENET_MAC_HLH = 0x0U; + + ENET_MAC_HLL = 0x0U; + + /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ + reg_value = ENET_MAC_FCTL; + reg_value &= MAC_FCTL_MASK; + reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ + |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ + |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; + ENET_MAC_FCTL = reg_value; + + ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; + + /* configure ENET_MAC_VLT register */ + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); + + /* DMA */ + /* configure ENET_DMA_CTL register */ + reg_value = ENET_DMA_CTL; + reg_value &= DMA_CTL_MASK; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ + |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ + |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ + |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ + |ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; + + /* configure ENET_DMA_BCTL register */ + reg_value = ENET_DMA_BCTL; + reg_value &= DMA_BCTL_MASK; + reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ + |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ + |ENET_FIXED_BURST_ENABLE; + ENET_DMA_BCTL = reg_value; +} + +#ifndef USE_DELAY +/*! + \brief insert a delay time + \param[in] ncount: specifies the delay time length + \param[out] none + \param[out] none +*/ +static void enet_delay(uint32_t ncount) +{ + uint32_t delay_time = 0U; + + for(delay_time = ncount; delay_time != 0U; delay_time--){ + } +} +#endif /* USE_DELAY */ + +#endif /* GD32F10X_CL */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c new file mode 100644 index 0000000000..641e716ca1 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c @@ -0,0 +1,646 @@ +/*! + \file gd32f10x_exmc.c + \brief EXMC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_exmc.h" + +/* EXMC bank0 register reset value */ +#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DBU) +#define BANK0_SNCTL1_2_3_REGION_RESET ((uint32_t)0x000030D2U) +#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) +#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) + +/* EXMC bank1/2 register reset mask*/ +#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) +#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) + +/* EXMC bank3 register reset mask*/ +#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) +#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) + +/* EXMC register bit offset */ +#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) +#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) +#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) +#define SNCTL_WREN_OFFSET ((uint32_t)12U) +#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) +#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) +#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) + +#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) +#define SNTCFG_DSET_OFFSET ((uint32_t)8U) +#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) + +#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U) +#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U) +#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U) + +#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) +#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) + +#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) +#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) +#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) + +#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) +#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) +#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) + +#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) +#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) +#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) + +#define INTEN_INTS_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize EXMC NOR/SRAM region + \param[in] norsram_region: select the region of bank0 + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_deinit(uint32_t norsram_region) +{ + /* reset the registers */ + if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){ + EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET; + }else{ + EXMC_SNCTL(norsram_region) = BANK0_SNCTL1_2_3_REGION_RESET; + } + + EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET; + EXMC_SNWTCFG(norsram_region) = BANK0_SNWTCFG_RESET; +} + +/*! + \brief initialize EXMC NOR/SRAM region + \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter + norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 + write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE + extended_mode: ENABLE or DISABLE + asyn_wait: ENABLE or DISABLE + nwait_signal: ENABLE or DISABLE + memory_write: ENABLE or DISABLE + nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING + wrap_burst_mode: ENABLE or DISABLE + nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH + burst_mode: ENABLE or DISABLE + databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR + address_data_mux: ENABLE or DISABLE + read_write_timing: struct exmc_norsram_timing_parameter_struct set the time + write_timing: struct exmc_norsram_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; + + /* get the register value */ + snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); + + /* clear relative bits */ + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX )); + + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| + (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | + (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | + (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )| + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* nor flash access enable */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ + snctl |= (uint32_t)EXMC_SNCTL_NREN; + } + + /* extended mode configure */ + if(ENABLE == exmc_norsram_init_struct->extended_mode){ + snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) | + (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)| + (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) | + exmc_norsram_init_struct->write_timing->asyn_access_mode); + }else{ + snwtcfg = BANK0_SNWTCFG_RESET; + } + + /* configure the registers */ + EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; + EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; + EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; +} + +/*! + \brief initialize the struct exmc_norsram_parameter_struct + \param[in] none + \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + /* configure the structure with default value */ + exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; + exmc_norsram_init_struct->address_data_mux = ENABLE; + exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; + exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; + exmc_norsram_init_struct->burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + exmc_norsram_init_struct->wrap_burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; + exmc_norsram_init_struct->memory_write = ENABLE; + exmc_norsram_init_struct->nwait_signal = ENABLE; + exmc_norsram_init_struct->extended_mode = DISABLE; + exmc_norsram_init_struct->asyn_wait = DISABLE; + exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; + + /* read/write timing configure */ + exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; + exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; + exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; + + /* write timing configure, when extended mode is used */ + exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; +} + +/*! + \brief enable EXMC NOR/PSRAM bank region + \param[in] norsram_region: specifie the region of NOR/PSRAM bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_enable(uint32_t norsram_region) +{ + EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief disable EXMC NOR/PSRAM bank region + \param[in] norsram_region: specifie the region of NOR/PSRAM Bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_disable(uint32_t norsram_region) +{ + EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief deinitialize EXMC NAND bank + \param[in] nand_bank: select the bank of NAND + \arg EXMC_BANKx_NAND(x=1..2) + \param[out] none + \retval none +*/ +void exmc_nand_deinit(uint32_t nand_bank) +{ + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + EXMC_NPCTL(nand_bank) = BANK1_2_NPCTL_RESET; + EXMC_NPINTEN(nand_bank) = BANK1_2_NPINTEN_RESET; + EXMC_NPCTCFG(nand_bank) = BANK1_2_NPCTCFG_RESET; + EXMC_NPATCFG(nand_bank) = BANK1_2_NPATCFG_RESET; +} + +/*! + \brief initialize EXMC NAND bank + \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter + nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND + ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + ecc_logic: ENABLE or DISABLE + databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +{ + uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; + + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; + + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | + (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); + + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ + EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; + EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; + EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; +} + +/*! + \brief initialize the struct exmc_nand_init_struct + \param[in] none + \param[out] the initialized struct exmc_nand_init_struct pointer + \retval none +*/ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +{ + /* configure the structure with default value */ + exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; + exmc_nand_init_struct->wait_feature = DISABLE; + exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; + exmc_nand_init_struct->ecc_logic = DISABLE; + exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; + exmc_nand_init_struct->ctr_latency = 0x0U; + exmc_nand_init_struct->atr_latency = 0x0U; + exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief enable NAND bank + \param[in] nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_enable(uint32_t nand_bank) +{ + EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable NAND bank + \param[in] nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_disable(uint32_t nand_bank) +{ + EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_NDBKEN; +} + +/*! + \brief enable or disable the EXMC NAND ECC function + \param[in] nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue) +{ + if (ENABLE == newvalue){ + /* enable the selected NAND bank ECC function */ + EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_ECCEN; + }else{ + /* disable the selected NAND bank ECC function */ + EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_ECCEN; + } +} + +/*! + \brief get the EXMC ECC value + \param[in] nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval the error correction code(ECC) value +*/ +uint32_t exmc_ecc_get(uint32_t nand_bank) +{ + return (EXMC_NECC(nand_bank)); +} + +/*! + \brief deinitialize EXMC PC card bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_deinit(void) +{ + /* EXMC_BANK3_PCCARD */ + EXMC_NPCTL3 = BANK3_NPCTL_RESET; + EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; + EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; + EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; + EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; +} + +/*! + \brief initialize EXMC PC card bank + \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +{ + /* configure the EXMC bank3 PC card control register */ + EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + + /* configure the EXMC bank3 PC card common space timing configuration register */ + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + + /* configure the EXMC bank3 PC card attribute space timing configuration register */ + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )| + (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); + + /* configure the EXMC bank3 PC card io space timing configuration register */ + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )| + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); +} + +/*! + \brief initialize the struct exmc_pccard_parameter_struct + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +{ + /* configure the structure with default value */ + exmc_pccard_init_struct->wait_feature = DISABLE; + exmc_pccard_init_struct->ctr_latency = 0x0U; + exmc_pccard_init_struct->atr_latency = 0x0U; + exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief enable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_enable(void) +{ + EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_disable(void) +{ + EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; +} + +/*! + \brief enable EXMC interrupt + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + one or more parameters can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source) +{ + /* NAND bank1, bank2 or PC card bank3 */ + EXMC_NPINTEN(bank) |= interrupt_source; +} + +/*! + \brief disable EXMC interrupt + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + one or more parameters can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(bank) &= ~interrupt_source; +} + +/*! + \brief check EXMC flag is set or not + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC Card bank + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag) +{ + uint32_t status = 0x00000000U; + + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(bank); + + if ((status & flag) != (uint32_t)flag ){ + /* flag is reset */ + return RESET; + }else{ + /* flag is set */ + return SET; + } +} + +/*! + \brief clear EXMC flag + \param[in] bank: specifie the NAND bank, PCCARD bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] flag: specify get which flag + one or more parameters can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \param[out] none + \retval none +*/ +void exmc_flag_clear(uint32_t bank, uint32_t flag) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(bank) &= ~flag; +} + +/*! + \brief check EXMC interrupt flag is set or not + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source) +{ + uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; + + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(bank); + interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET)); + + interrupt_enable = (status & interrupt_source); + + if ((interrupt_enable) && (interrupt_state)){ + /* interrupt flag is set */ + return SET; + }else{ + /* interrupt flag is reset */ + return RESET; + } +} + +/*! + \brief clear EXMC interrupt flag + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + one or more parameters can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source) +{ + /* NAND bank1, bank2 or PC card bank3 */ + EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c new file mode 100644 index 0000000000..dcda291314 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c @@ -0,0 +1,256 @@ +/*! + \file gd32f10x_exti.c + \brief EXTI driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_exti.h" + +#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = EXTI_REG_RESET_VALUE; + EXTI_EVEN = EXTI_REG_RESET_VALUE; + EXTI_RTEN = EXTI_REG_RESET_VALUE; + EXTI_FTEN = EXTI_REG_RESET_VALUE; + EXTI_SWIEV = EXTI_REG_RESET_VALUE; +} + +/*! + \brief initialize the EXTI + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling edge trigger + \arg EXTI_TRIG_BOTH: rising edge and falling edge trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode){ + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type){ + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI lines flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI lines flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c new file mode 100644 index 0000000000..83da3519e0 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c @@ -0,0 +1,965 @@ +/*! + \file gd32f10x_fmc.c + \brief FMC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_fmc.h" + +/*! + \brief set the wait state counter value + \param[in] wscnt£ºwait state counter value + \arg WS_WSCNT_0: FMC 0 wait state + \arg WS_WSCNT_1: FMC 1 wait state + \arg WS_WSCNT_2: FMC 2 wait state + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint32_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief unlock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ + /* write the FMC unlock key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } + + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* write the FMC unlock key */ + if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } + } +} + +/*! + \brief unlock the FMC bank0 operation + this function can be used for all GD32F10x devices. + for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. + for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_unlock(void) +{ + if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ + /* write the FMC unlock key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } +} + +/*! + \brief unlock the FMC bank1 operation + this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_unlock(void) +{ + if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){ + /* write the FMC unlock key */ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit */ + FMC_CTL0 |= FMC_CTL0_LK; + + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* set the LK bit */ + FMC_CTL1 |= FMC_CTL1_LK; + } +} + +/*! + \brief lock the FMC bank0 operation + this function can be used for all GD32F10X devices. + for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. + for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_lock(void) +{ + /* set the LK bit*/ + FMC_CTL0 |= FMC_CTL0_LK; +} + +/*! + \brief lock the FMC bank1 operation + this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_lock(void) +{ + /* set the LK bit*/ + FMC_CTL1 |= FMC_CTL1_LK; +} + +/*! + \brief erase page + \param[in] page_address: the page address to be erased. + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state; + + if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > page_address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + }else{ + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL1 |= FMC_CTL1_PER; + FMC_ADDR1 = page_address; + if(FMC_OBSTAT & FMC_OBSTAT_SPC){ + FMC_ADDR0 = page_address; + } + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL1 &= ~FMC_CTL1_PER; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase whole chip + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state; + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase bank0 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start FMC bank0 erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief erase bank1 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start FMC bank1 erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + }else{ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: halfword to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + if(FMC_BANK0_SIZE > FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + }else{ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief unlock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } + + /* wait until OBWEN bit is set by hardware */ + while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ + } +} + +/*! + \brief lock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OBWEN bit */ + FMC_CTL0 &= ~FMC_CTL0_OBWEN; +} + +/*! + \brief erase the FMC option byte + unlock the FMC_CTL0 and option byte before calling this function + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_erase(void) +{ + uint16_t temp_spc = FMC_NSPC; + + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* check the option byte security protection value */ + if(RESET != ob_spc_get()){ + temp_spc = FMC_USPC; + } + + if(FMC_READY == fmc_state){ + + /* start erase the option byte */ + FMC_CTL0 |= FMC_CTL0_OBER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + /* set the OBPG bit */ + FMC_CTL0 |= FMC_CTL0_OBPG; + /* no security protection */ + OB_SPC = (uint16_t)temp_spc; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable write protection + \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if + you want to protect the corresponding pages. meanwhile, sector + macro could used to set specific sector write protected. + one or more parameters can be selected which are shown as below: + \arg OB_WPx(x = 0..31): write protect specify sector + \arg OB_WP_ALL: write protect all sector + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) +{ + uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; + + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + ob_wp = (uint32_t)(~ob_wp); + temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); + temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U); + temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); + temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); + + if(FMC_READY == fmc_state){ + + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + if(0xFFU != temp_wp0){ + OB_WP0 = temp_wp0; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ + OB_WP1 = temp_wp1; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ + OB_WP2 = temp_wp2; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ + OB_WP3 = temp_wp3; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection + only one parameter can be selected which is shown as below: + \arg FMC_NSPC: no security protection + \arg FMC_USPC: under security protection + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_OBER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + + /* start the option byte program */ + FMC_CTL0 |= FMC_CTL0_OBPG; + + OB_SPC = (uint16_t)ob_spc; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option byte + \param[in] ob_fwdgt: option byte watchdog value + \arg OB_FWDGT_SW: software free watchdog + \arg OB_FWDGT_HW: hardware free watchdog + \param[in] ob_deepsleep: option byte deepsleep reset value + \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \param[in] ob_stdby:option byte standby reset value + \arg OB_STDBY_NRST: no reset when entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \param[in] ob_boot: specifies the option byte boot bank value + \arg OB_BOOT_B0: boot from bank0 + \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) +{ + fmc_state_enum fmc_state = FMC_READY; + uint8_t temp; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); + OB_USER = (uint16_t)temp; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program option bytes data + \param[in] address: the option bytes address to be programmed + \param[in] data: the byte to be programmed + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the OBPG bit */ + FMC_CTL0 |= FMC_CTL0_OBPG; + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the FMC user option byte + \param[in] none + \param[out] none + \retval the FMC user option byte values +*/ +uint8_t ob_user_get(void) +{ + /* return the FMC user option byte value */ + return (uint8_t)(FMC_OBSTAT >> 2U); +} + +/*! + \brief get OB_DATA in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_data +*/ +uint16_t ob_data_get(void) +{ + return (uint16_t)(FMC_OBSTAT >> 10U); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value +*/ +uint32_t ob_write_protection_get(void) +{ + /* return the FMC write protection option byte value */ + return FMC_WP; +} + +/*! + \brief get the FMC option byte security protection + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ob_spc_get(void) +{ + FlagStatus spc_state = RESET; + + if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ + spc_state = SET; + }else{ + spc_state = RESET; + } + return spc_state; +} + +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_BANK0_END: enable FMC end of program interrupt + \arg FMC_INT_BANK0_ERR: enable FMC error interrupt + \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_BANK0_END: enable FMC end of program interrupt + \arg FMC_INT_BANK0_ERR: enable FMC error interrupt + \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief check flag is set or not + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit + \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit + \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit + \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit + \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit + \arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit + \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit + \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit + \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t flag) +{ + if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the FMC flag + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit + \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit + \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit + \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit + \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit + \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t flag) +{ + FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); +} + +/*! + \brief get FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit + \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); + }else{ + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); + } + + if(ret1 && ret2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit + \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) +{ + FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); +} + +/*! + \brief get the FMC bank0 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ + fmc_state = FMC_BUSY; + }else{ + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ + fmc_state = FMC_WPERR; + }else{ + if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ + fmc_state = FMC_PGERR; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the FMC bank1 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){ + fmc_state = FMC_BUSY; + }else{ + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){ + fmc_state = FMC_WPERR; + }else{ + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ + fmc_state = FMC_PGERR; + } + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank0 is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do{ + /* get FMC state */ + fmc_state = fmc_bank0_state_get(); + timeout--; + }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state){ + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank1 is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do{ + /* get FMC state */ + fmc_state = fmc_bank1_state_get(); + timeout--; + }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state){ + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c new file mode 100644 index 0000000000..0025c9a572 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c @@ -0,0 +1,155 @@ +/*! + \file gd32f10x_fwdgt.c + \brief FWDGT driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_fwdgt.h" + +/* write value to FWDGT_CTL_CMD bit field */ +#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status){ + return ERROR; + } + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status){ + return ERROR; + } + FWDGT_RLD = RLD_RLD(reload_value); + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(FWDGT_STAT & flag){ + return SET; + } + + return RESET; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c new file mode 100644 index 0000000000..d8bdd709bb --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c @@ -0,0 +1,539 @@ +/*! + \file gd32f10x_gpio.c + \brief GPIO driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_gpio.h" + +#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ +#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ +#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ +#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ +#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ +#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ +#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ +#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ +#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/ + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph){ + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOE: + /* reset GPIOE */ + rcu_periph_reset_enable(RCU_GPIOERST); + rcu_periph_reset_disable(RCU_GPIOERST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + case GPIOG: + /* reset GPIOG */ + rcu_periph_reset_enable(RCU_GPIOGRST); + rcu_periph_reset_disable(RCU_GPIOGRST); + break; + default: + break; + } +} + +/*! + \brief reset alternate function I/O(AFIO) + \param[in] none + \param[out] none + \retval none +*/ +void gpio_afio_deinit(void) +{ + rcu_periph_reset_enable(RCU_AFRST); + rcu_periph_reset_disable(RCU_AFRST); +} + +/*! + \brief GPIO parameter initialization + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] mode: gpio pin mode + only one parameter can be selected which is shown as below: + \arg GPIO_MODE_AIN: analog input mode + \arg GPIO_MODE_IN_FLOATING: floating input mode + \arg GPIO_MODE_IPD: pull-down input mode + \arg GPIO_MODE_IPU: pull-up input mode + \arg GPIO_MODE_OUT_OD: GPIO output with open-drain + \arg GPIO_MODE_OUT_PP: GPIO output with push-pull + \arg GPIO_MODE_AF_OD: AFIO output with open-drain + \arg GPIO_MODE_AF_PP: AFIO output with push-pull + \param[in] speed: gpio output max speed value + only one parameter can be selected which is shown as below: + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + + \param[out] none + \retval none +*/ +void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) +{ + uint16_t i; + uint32_t temp_mode = 0U; + uint32_t reg = 0U; + + /* GPIO mode configuration */ + temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); + + /* GPIO speed configuration */ + if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ + /* output mode max speed:10MHz,2MHz,50MHz */ + temp_mode |= (uint32_t)speed; + } + + /* configure the eight low port pins with GPIO_CTL0 */ + for(i = 0U;i < 8U;i++){ + if((1U << i) & pin){ + reg = GPIO_CTL0(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i, temp_mode); + + /* set IPD or IPU */ + if(GPIO_MODE_IPD == mode){ + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); + }else{ + /* set the corresponding OCTL bit */ + if(GPIO_MODE_IPU == mode){ + GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); + } + } + /* set GPIO_CTL0 register */ + GPIO_CTL0(gpio_periph) = reg; + } + } + /* configure the eight high port pins with GPIO_CTL1 */ + for(i = 8U;i < 16U;i++){ + if((1U << i) & pin){ + reg = GPIO_CTL1(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i - 8U); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i - 8U, temp_mode); + + /* set IPD or IPU */ + if(GPIO_MODE_IPD == mode){ + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); + }else{ + /* set the corresponding OCTL bit */ + if(GPIO_MODE_IPU == mode){ + GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); + } + } + /* set GPIO_CTL1 register */ + GPIO_CTL1(gpio_periph) = reg; + } + } +} + +/*! + \brief set GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if(RESET != bit_value){ + GPIO_BOP(gpio_periph) = (uint32_t)pin; + }else{ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] data: specify the value to be written to the port output data register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph,uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + only one parameter can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval input status of gpio pin: SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO port input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval input status of gpio all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return (uint16_t)(GPIO_ISTAT(gpio_periph)); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + only one parameter can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval output status of gpio pin: SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO port output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval output status of gpio all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_OCTL(gpio_periph)); +} + +/*! + \brief configure GPIO pin remap + \param[in] gpio_remap: select the pin to remap + \arg GPIO_SPI0_REMAP: SPI0 remapping + \arg GPIO_I2C0_REMAP: I2C0 remapping + \arg GPIO_USART0_REMAP: USART0 remapping + \arg GPIO_USART1_REMAP: USART1 remapping + \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping + \arg GPIO_USART2_FULL_REMAP: USART2 full remapping + \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping + \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping + \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping + \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping + \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping + \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping + \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping + \arg GPIO_TIMER3_REMAP: TIMER3 remapping + \arg GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F10X_CL devices) + \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F10X_CL devices) + \arg GPIO_PD01_REMAP: PD01 remapping + \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) + \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices) + \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F10X_CL devices) + \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST + \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled + \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled + \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL devices) + \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) + \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices) + \arg GPIO_TIMER8_REMAP: TIMER8 remapping + \arg GPIO_TIMER9_REMAP: TIMER9 remapping + \arg GPIO_TIMER10_REMAP: TIMER10 remapping + \arg GPIO_TIMER12_REMAP: TIMER12 remapping + \arg GPIO_TIMER13_REMAP: TIMER13 remapping + \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) +{ + uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; + + if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ + /* get AFIO_PCF1 regiter value */ + temp_reg = AFIO_PCF1; + }else{ + /* get AFIO_PCF0 regiter value */ + temp_reg = AFIO_PCF0; + } + + temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; + remap1 = remap & LSB_16BIT_MASK; + + /* judge pin remap type */ + if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){ + temp_reg &= PCF_SWJCFG_MASK; + AFIO_PCF0 &= PCF_SWJCFG_MASK; + }else if(PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)){ + remap2 = ((uint32_t)0x03U) << temp_mask; + temp_reg &= ~remap2; + temp_reg |= ~PCF_SWJCFG_MASK; + }else{ + temp_reg &= ~(remap1 << ((remap >> 0x15U)*0x10U)); + temp_reg |= ~PCF_SWJCFG_MASK; + } + + /* set pin remap value */ + if(DISABLE != newvalue){ + temp_reg |= (remap1 << ((remap >> 0x15U)*0x10U)); + } + + if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ + /* set AFIO_PCF1 regiter value */ + AFIO_PCF1 = temp_reg; + }else{ + /* set AFIO_PCF0 regiter value */ + AFIO_PCF0 = temp_reg; + } +} + +/*! + \brief select GPIO pin exti sources + \param[in] gpio_outputport: gpio event output port + \arg GPIO_PORT_SOURCE_GPIOA: output port source A + \arg GPIO_PORT_SOURCE_GPIOB: output port source B + \arg GPIO_PORT_SOURCE_GPIOC: output port source C + \arg GPIO_PORT_SOURCE_GPIOD: output port source D + \arg GPIO_PORT_SOURCE_GPIOE: output port source E + \arg GPIO_PORT_SOURCE_GPIOF: output port source F + \arg GPIO_PORT_SOURCE_GPIOG: output port source G + \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15) + \param[out] none + \retval none +*/ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) +{ + uint32_t source = 0U; + source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); + + /* select EXTI sources */ + if(GPIO_PIN_SOURCE_4 > output_pin){ + /* select EXTI0/EXTI1/EXTI2/EXTI3 */ + AFIO_EXTISS0 &= ~source; + AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); + }else if(GPIO_PIN_SOURCE_8 > output_pin){ + /* select EXTI4/EXTI5/EXTI6/EXTI7 */ + AFIO_EXTISS1 &= ~source; + AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); + }else if(GPIO_PIN_SOURCE_12 > output_pin){ + /* select EXTI8/EXTI9/EXTI10/EXTI11 */ + AFIO_EXTISS2 &= ~source; + AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); + }else{ + /* select EXTI12/EXTI13/EXTI14/EXTI15 */ + AFIO_EXTISS3 &= ~source; + AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); + } +} + +/*! + \brief configure GPIO pin event output + \param[in] output_port: gpio event output port + only one parameter can be selected which are shown as below: + \arg GPIO_EVENT_PORT_GPIOA: event output port A + \arg GPIO_EVENT_PORT_GPIOB: event output port B + \arg GPIO_EVENT_PORT_GPIOC: event output port C + \arg GPIO_EVENT_PORT_GPIOD: event output port D + \arg GPIO_EVENT_PORT_GPIOE: event output port E + \arg GPIO_EVENT_PORT_GPIOE: event output port F + \arg GPIO_EVENT_PORT_GPIOE: event output port G + \param[in] output_pin: + only one parameter can be selected which are shown as below: + \arg GPIO_EVENT_PIN_x(x=0..15) + \param[out] none + \retval none +*/ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) +{ + uint32_t reg = 0U; + reg = AFIO_EC; + + /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ + reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); + + reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); + reg |= (uint32_t)output_pin; + + AFIO_EC = reg; +} + +/*! + \brief enable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_enable(void) +{ + AFIO_EC |= AFIO_EC_EOE; +} + +/*! + \brief disable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_disable(void) +{ + AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); +} + +/*! + \brief lock GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +#ifdef GD32F10X_CL +/*! + \brief select ethernet MII or RMII PHY + \param[in] gpio_enetsel: ethernet MII or RMII PHY selection + \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY + \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY + \param[out] none + \retval none +*/ +void gpio_ethernet_phy_select(uint32_t gpio_enetsel) +{ + /* clear AFIO_PCF0_ENET_PHY_SEL bit */ + AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); + + /* select MII or RMII PHY */ + AFIO_PCF0 |= (uint32_t)gpio_enetsel; +} +#endif diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c new file mode 100644 index 0000000000..fa1ae96d23 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c @@ -0,0 +1,707 @@ +/*! + \file gd32f10x_i2c.c + \brief I2C driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_i2c.h" + +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph){ + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + \param[in] dutycyc: duty cycle in fast mode + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high=2 + \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1/1000000U); + if(freq >= I2CCLK_MAX){ + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if(100000U >= clkspeed){ + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1/1000000U)+1U); + if(risetime >= I2CCLK_MAX){ + I2C_RT(i2c_periph) = I2CCLK_MAX; + }else if(risetime <= I2CCLK_MIN){ + I2C_RT(i2c_periph) = I2CCLK_MIN; + }else{ + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1/(clkspeed*2U)); + if(clkc < 0x04U){ + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + }else if(400000U >= clkspeed){ + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); + if(I2C_DTCY_2 == dutycyc){ + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1/(clkspeed*3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + }else{ + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1/(clkspeed*25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if(0U == (clkc & I2C_CKCFG_CLKC)){ + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + }else{ + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: 7bits + \arg I2C_ADDFORMAT_10BITS: 10bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief SMBus type selection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] type: + only one parameter can be selected which is shown as below: + \arg I2C_SMBUS_DEVICE: device + \arg I2C_SMBUS_HOST: host + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if(I2C_SMBUS_HOST == type){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + if(I2C_ACK_ENABLE == ack){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } +} + +/*! + \brief configure I2C POAP position + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + /* configure I2C POAP position */ + if(I2C_ACKPOS_NEXT == pos){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); + } +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection){ + addr = addr & I2C_TRANSMITTER; + }else{ + addr = addr | I2C_RECEIVER; + } + /* send slave address */ + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief dual-address mode switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dualaddr: + only one parameter can be selected which is shown as below: + \arg I2C_DUADEN_DISABLE: disable dual-address mode + \arg I2C_DUADEN_ENABLE: enable dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) +{ + if(I2C_DUADEN_ENABLE == dualaddr){ + I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; + }else{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); + } +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief enable I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable + \param[out] none + \retval none +*/ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure whether next DMA EOT is DMA last transfer or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmalast: + only one parameter can be selected which is shown as below: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] stretchpara: + only one parameter can be selected which is shown as below: + \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled + \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_DISSTRC); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] gcallpara: + only one parameter can be selected which is shown as below: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief software reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sreset: + only one parameter can be selected which is shown as below: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C PEC calculation on or off + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC + \param[out] none + \retval none +*/ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>STAT1_PECV_OFFSET); +} + +/*! + \brief I2C issue alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* issue alert through SMBA pin configure*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief enable or disable I2C ARP protocol in SMBus switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief check I2C flag is set or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear I2C flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(I2C_FLAG_ADDSEND == flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief check I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ + if(intenable && bufie){ + intenable = 1U; + }else{ + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + if(I2C_INT_FLAG_ADDSEND == int_flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c new file mode 100644 index 0000000000..1a96627b3a --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c @@ -0,0 +1,187 @@ +/*! + \file gd32f10x_misc.c + \brief MISC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, + uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + + /* use the priority group value to get the temp_pre and the temp_sub */ + switch ((SCB->AIRCR) & (uint32_t)0x700U) { + case NVIC_PRIGROUP_PRE0_SUB4: + temp_pre = 0U; + temp_sub = 0x4U; + break; + case NVIC_PRIGROUP_PRE1_SUB3: + temp_pre = 1U; + temp_sub = 0x3U; + break; + case NVIC_PRIGROUP_PRE2_SUB2: + temp_pre = 2U; + temp_sub = 0x2U; + break; + case NVIC_PRIGROUP_PRE3_SUB1: + temp_pre = 3U; + temp_sub = 0x1U; + break; + case NVIC_PRIGROUP_PRE4_SUB0: + temp_pre = 4U; + temp_sub = 0x0U; + break; + default: + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre = 2U; + temp_sub = 0x2U; + break; + } + + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(uint8_t nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + }else{ + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c new file mode 100644 index 0000000000..33052db8d1 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c @@ -0,0 +1,265 @@ +/*! + \file gd32f10x_pmu.c + \brief PMU driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_pmu.h" + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + only one parameter can be selected which is shown as below: + \arg PMU_LVDT_0: voltage threshold is 2.2V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.5V + \arg PMU_LVDT_4: voltage threshold is 2.6V + \arg PMU_LVDT_5: voltage threshold is 2.7V + \arg PMU_LVDT_6: voltage threshold is 2.8V + \arg PMU_LVDT_7: voltage threshold is 2.9V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief PMU work at sleep mode + \param[in] sleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd){ + __WFI(); + }else{ + __WFE(); + } +} + +/*! + \brief PMU work at deepsleep mode + \param[in] ldo: + only one parameter can be selected which is shown as below: + \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \param[in] deepsleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) +{ + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* set sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* select WFI or WFE command to enter deepsleep mode */ + if(WFI_CMD == deepsleepmodecmd){ + __WFI(); + }else{ + __SEV(); + __WFE(); + __WFE(); + } + /* reset sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work at standby mode + \param[in] standbymodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_standbymode(uint8_t standbymodecmd) +{ + /* set sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* select WFI or WFE command to enter standby mode */ + if(WFI_CMD == standbymodecmd){ + __WFI(); + }else{ + __WFE(); + } +} + +/*! + \brief enable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(void) +{ + PMU_CS |= PMU_CS_WUPEN; +} + +/*! + \brief disable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(void) +{ + PMU_CS &= ~PMU_CS_WUPEN; +} + +/*! + \brief enable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \param[out] none + \retval FlagStatus SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if(PMU_CS & flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear flag bit + \param[in] flag_reset: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag_reset) +{ + switch(flag_reset){ + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default : + break; + } +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c new file mode 100644 index 0000000000..579831ccaf --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c @@ -0,0 +1,1193 @@ +/*! + \file gd32f10x_rcu.c + \brief RCU driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_rcu.h" + +/* define clock source */ +#define SEL_IRC8M ((uint16_t)0U) +#define SEL_HXTAL ((uint16_t)1U) +#define SEL_PLL ((uint16_t)2U) + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + rcu_osci_stab_wait(RCU_IRC8M); + + /* reset CFG0 register */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | + RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2); +#elif defined(GD32F10X_CL) + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4); +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + RCU_CTL &= ~RCU_CTL_HXTALBPS; +#ifdef GD32F10X_CL + RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); +#endif /* GD32F10X_CL */ + + /* reset INT and CFG1 register */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_INT = 0x009f0000U; +#elif defined(GD32F10X_CL) + RCU_INT = 0x00ff0000U; + RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | + RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL); +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock + \arg RCU_AF : alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_ENET: ENET clock(CL series available) + \arg RCU_ENETTX: ENETTX clock(CL series available) + \arg RCU_ENETRX: ENETRX clock(CL series available) + \arg RCU_USBD: USBD clock(HD,XD series available) + \arg RCU_USBFS: USBFS clock(CL series available) + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock + \arg RCU_SDIO: SDIO clock(not available for CL series) + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock + \arg RCU_AF: alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_ENET: ENET clock(CL series available) + \arg RCU_ENETTX: ENETTX clock(CL series available) + \arg RCU_ENETRX: ENETRX clock(CL series available) + \arg RCU_USBD: USBD clock(HD,XD series available) + \arg RCU_USBFS: USBFS clock(CL series available) + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock + \arg RCU_SDIO: SDIO clock(not available for CL series) + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_ENETRST: reset ENET(CL series available) + \arg RCU_USBDRST: reset USBD(HD,XD series available) + \arg RCU_USBFSRST: reset USBFS(CL series available) + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_ENETRST: reset ENET(CL series available) + \arg RCU_USBDRST: reset USBD(HD,XD series available) + \arg RCU_USBFSRST: reset USBFS(CL series available) + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP domain + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP domain reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + reg &= ~RCU_CFG0_SCS; + RCU_CFG0 = (reg | ck_sys); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source + \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source + \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the AHBPSC bits and set according to ck_ahb */ + reg &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (reg | ck_ahb); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB1PSC and set according to ck_apb1 */ + reg &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (reg | ck_apb1); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB2PSC and set according to ck_apb2 */ + reg &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (reg | ck_apb2); +} + +/*! + \brief configure the CK_OUT0 clock source + \param[in] ckout0_src: CK_OUT0 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT0SRC_NONE: no clock selected + \arg RCU_CKOUT0SRC_CKSYS: system clock selected + \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected + \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected + \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected + \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected + \arg RCU_CKOUT0SRC_EXT1: EXT1 selected + \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected + \param[out] none + \retval none +*/ +void rcu_ckout0_config(uint32_t ckout0_src) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the CKOUT0SRC, set according to ckout0_src */ + reg &= ~RCU_CFG0_CKOUT0SEL; + RCU_CFG0 = (reg | ckout0_src); +} + +/*! + \brief configure the main PLL clock + \param[in] pll_src: PLL clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL + \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL_MULx (XD series x = 2..32, CL series x = 2..14, 6.5, 16..32) + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + + /* PLL clock source and multiplication factor configuration */ + reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + reg |= (pll_src | pll_mul); + + RCU_CFG0 = reg; +} + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +/*! + \brief configure the PREDV0 division factor + \param[in] predv0_div: PREDV0 division factor + only one parameter can be selected which is shown as below: + \arg RCU_PREDV0_DIVx, x = 1,2 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + /* reset PREDV0 bit */ + reg &= ~RCU_CFG0_PREDV0; + if(RCU_PREDV0_DIV2 == predv0_div){ + /* set the PREDV0 bit */ + reg |= RCU_CFG0_PREDV0; + } + + RCU_CFG0 = reg; +} +#elif defined(GD32F10X_CL) +/*! + \brief configure the PREDV0 division factor and clock source + \param[in] predv0_source: PREDV0 input clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock + \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock + \param[in] predv0_div: PREDV0 division factor + only one parameter can be selected which is shown as below: + \arg RCU_PREDV0_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset PREDV0SEL and PREDV0 bits */ + reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); + /* set the PREDV0SEL and PREDV0 division factor */ + reg |= (predv0_source | predv0_div); + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PREDV1 division factor + \param[in] predv1_div: PREDV1 division factor + only one parameter can be selected which is shown as below: + \arg RCU_PREDV1_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv1_config(uint32_t predv1_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset the PREDV1 bits */ + reg &= ~RCU_CFG1_PREDV1; + /* set the PREDV1 division factor */ + reg |= predv1_div; + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PLL1 clock + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL1_MULx (x = 8..16, 20) + \param[out] none + \retval none +*/ +void rcu_pll1_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL1MF; + RCU_CFG1 |= pll_mul; +} + +/*! + \brief configure the PLL2 clock + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL2_MULx (x = 8..16, 20) + \param[out] none + \retval none +*/ +void rcu_pll2_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL2MF; + RCU_CFG1 |= pll_mul; +} +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/*! + \brief configure the ADC prescaler factor + \param[in] adc_psc: ADC prescaler factor + only one parameter can be selected which is shown as below: + \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 + \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 + \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 + \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 + \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 + \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(uint32_t adc_psc) +{ + uint32_t reg0; + + /* reset the ADCPSC bits */ + reg0 = RCU_CFG0; + reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); + + /* set the ADC prescaler factor */ + switch(adc_psc){ + case RCU_CKADC_CKAPB2_DIV2: + case RCU_CKADC_CKAPB2_DIV4: + case RCU_CKADC_CKAPB2_DIV6: + case RCU_CKADC_CKAPB2_DIV8: + reg0 |= (adc_psc << 14); + break; + + case RCU_CKADC_CKAPB2_DIV12: + case RCU_CKADC_CKAPB2_DIV16: + adc_psc &= ~BIT(2); + reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); + break; + + default: + break; + } + + /* set the register */ + RCU_CFG0 = reg0; +} + +/*! + \brief configure the USBD/USBFS prescaler factor + \param[in] usb_psc: USB prescaler factor + only one parameter can be selected which is shown as below: + \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5 + \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1 + \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5 + \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2 + \param[out] none + \retval none +*/ +void rcu_usb_clock_config(uint32_t usb_psc) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* configure the USBD/USBFS prescaler factor */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + reg &= ~RCU_CFG0_USBDPSC; +#elif defined(GD32F10X_CL) + reg &= ~RCU_CFG0_USBFSPSC; +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + RCU_CFG0 = (reg | usb_psc); +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + uint32_t reg; + + reg = RCU_BDCTL; + /* reset the RTCSRC bits and set according to rtc_clock_source */ + reg &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL = (reg | rtc_clock_source); +} + +#ifdef GD32F10X_CL +/*! + \brief configure the I2S1 clock source selection + \param[in] i2s_clock_source: I2S1 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock + \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock + \param[out] none + \retval none +*/ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S1SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S1SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} + +/*! + \brief configure the I2S2 clock source selection + \param[in] i2s_clock_source: I2S2 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock + \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock + \param[out] none + \retval none +*/ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S2SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S2SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} +#endif /* GD32F10X_CL */ + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only) + \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only) + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only) + \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only) + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only) + \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only) + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +{ + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + + switch(osci){ + /* wait HXTAL stable */ + case RCU_HXTAL: + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC8M stable */ + case RCU_IRC8M: + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC40K stable */ + case RCU_IRC40K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ + reval = SUCCESS; + } + break; + + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ + reval = SUCCESS; + } + break; + +#ifdef GD32F10X_CL + /* wait PLL1 stable */ + case RCU_PLL1_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ + reval = SUCCESS; + } + break; + /* wait PLL2 stable */ + case RCU_PLL2_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ + reval = SUCCESS; + } + break; +#endif /* GD32F10X_CL */ + + default: + break; + } + + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci){ + /* enable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg | RCU_CTL_HXTALBPS); + break; + /* enable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC40K: + case RCU_PLL_CK: +#ifdef GD32F10X_CL + case RCU_PLL1_CK: + case RCU_PLL2_CK: +#endif /* GD32F10X_CL */ + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci){ + /* disable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); + break; + /* disable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC40K: + case RCU_PLL_CK: +#ifdef GD32F10X_CL + case RCU_PLL1_CK: + case RCU_PLL2_CK: +#endif /* GD32F10X_CL */ + break; + default: + break; + } +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) +{ + uint32_t reg; + + reg = RCU_CTL; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + reg &= ~RCU_CTL_IRC8MADJ; + RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V + \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V + \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V + \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2 +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws, ck_freq = 0U; + uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; + uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp; +#ifdef GD32F10X_CL + uint32_t predv0, predv1, pll1mf; +#endif /* GD32F10X_CL */ + + /* exponent of AHB, APB1 and APB2 clock divider */ + uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + if(RCU_PLLSRC_HXTAL == pllsel) { + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); + /* PREDV0 input source clock divided by 2 */ + if(RCU_CFG0_PREDV0 == predv0sel){ + ck_src = HXTAL_VALUE/2U; + } +#elif defined(GD32F10X_CL) + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; +#endif /* GD32F10X_HD and GD32F10X_XD */ + }else{ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE/2U; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + if(pllmf < 15U){ + pllmf += 2U; + }else{ + pllmf += 1U; + } + + cksys_freq = ck_src * pllmf; + + #ifdef GD32F10X_CL + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + cksys_freq = ck_src * 6U + ck_src / 2U; + } + #endif /* GD32F10X_CL */ + + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock){ + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + default: + break; + } + return ck_freq; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c new file mode 100644 index 0000000000..27fe2cfe70 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c @@ -0,0 +1,277 @@ +/*! + \file gd32f10x_rtc.c + \brief RTC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_rtc.h" + +/* RTC register high / low bits mask */ +#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */ +#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */ + +/* RTC register high bits offset */ +#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U) + +/*! + \brief enter RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_enter(void) +{ + RTC_CTL |= RTC_CTL_CMF; +} + +/*! + \brief exit RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_exit(void) +{ + RTC_CTL &= ~RTC_CTL_CMF; +} + +/*! + \brief set RTC counter value + \param[in] cnt: RTC counter value + \param[out] none + \retval none +*/ +void rtc_counter_set(uint32_t cnt) +{ + rtc_configuration_mode_enter(); + /* set the RTC counter high bits */ + RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET); + /* set the RTC counter low bits */ + RTC_CNTL = (cnt & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC prescaler value + \param[in] psc: RTC prescaler value + \param[out] none + \retval none +*/ +void rtc_prescaler_set(uint32_t psc) +{ + rtc_configuration_mode_enter(); + /* set the RTC prescaler high bits */ + RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET); + /* set the RTC prescaler low bits */ + RTC_PSCL = (psc & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief wait RTC last write operation finished flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_lwoff_wait(void) +{ + /* loop until LWOFF flag is set */ + while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){ + } +} + +/*! + \brief wait RTC registers synchronized flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_register_sync_wait(void) +{ + /* clear RSYNF flag */ + RTC_CTL &= ~RTC_CTL_RSYNF; + /* loop until RSYNF flag is set */ + while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){ + } +} + +/*! + \brief set RTC alarm value + \param[in] alarm: RTC alarm value + \param[out] none + \retval none +*/ +void rtc_alarm_config(uint32_t alarm) +{ + rtc_configuration_mode_enter(); + /* set the alarm high bits */ + RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET); + /* set the alarm low bits */ + RTC_ALRML = (alarm & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief get RTC counter value + \param[in] none + \param[out] none + \retval RTC counter value +*/ +uint32_t rtc_counter_get(void) +{ + uint32_t temp = 0x0U; + + temp = RTC_CNTL; + temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); + return temp; +} + +/*! + \brief get RTC divider value + \param[in] none + \param[out] none + \retval RTC divider value +*/ +uint32_t rtc_divider_get(void) +{ + uint32_t temp = 0x00U; + + temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); + temp |= RTC_DIVL; + return temp; +} + +/*! + \brief get RTC flag status + \param[in] flag: specify which flag status to get + only one parameter can be selected which is shown as below: + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \arg RTC_FLAG_LWOF: last write operation finished flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + if(RESET != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC flag status + \param[in] flag: specify which flag status to clear + one or more parameters can be selected which are shown as below: + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + /* clear RTC flag */ + RTC_CTL &= ~flag; +} + +/*! + \brief get RTC interrupt flag status + \param[in] flag: specify which flag status to get + only one parameter can be selected which is shown as below: + \arg RTC_INT_FLAG_SECOND: second interrupt flag + \arg RTC_INT_FLAG_ALARM: alarm interrupt flag + \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_interrupt_flag_get(uint32_t flag) +{ + if(RESET != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC interrupt flag status + \param[in] flag: specify which flag status to clear + one or more parameters can be selected which are shown as below: + \arg RTC_INT_FLAG_SECOND: second interrupt flag + \arg RTC_INT_FLAG_ALARM: alarm interrupt flag + \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \param[out] none + \retval none +*/ +void rtc_interrupt_flag_clear(uint32_t flag) +{ + /* clear RTC interrupt flag */ + RTC_CTL &= ~flag; +} + +/*! + \brief enable RTC interrupt + \param[in] interrupt: specify which interrupt to enbale + one or more parameters can be selected which are shown as below: + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + RTC_INTEN |= interrupt; +} + +/*! + \brief disable RTC interrupt + \param[in] interrupt: specify which interrupt to disbale + one or more parameters can be selected which are shown as below: + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + RTC_INTEN &= ~interrupt; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c new file mode 100644 index 0000000000..d609f282ed --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c @@ -0,0 +1,814 @@ +/*! + \file gd32f10x_sdio.c + \brief SDIO driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_sdio.h" + +#define DEFAULT_RESET_VALUE 0x00000000U + +/*! + \brief deinitialize the SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_deinit(void) +{ + SDIO_PWRCTL = DEFAULT_RESET_VALUE; + SDIO_CLKCTL = DEFAULT_RESET_VALUE; + SDIO_CMDAGMT = DEFAULT_RESET_VALUE; + SDIO_CMDCTL = DEFAULT_RESET_VALUE; + SDIO_DATATO = DEFAULT_RESET_VALUE; + SDIO_DATALEN = DEFAULT_RESET_VALUE; + SDIO_DATACTL = DEFAULT_RESET_VALUE; + SDIO_INTC = DEFAULT_RESET_VALUE; + SDIO_INTEN = DEFAULT_RESET_VALUE; +} + +/*! + \brief configure the SDIO clock + \param[in] clock_edge: SDIO_CLK clock edge + only one parameter can be selected which is shown as below: + \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK + \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK + \param[in] clock_bypass: clock bypass + only one parameter can be selected which is shown as below: + \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass + \arg SDIO_CLOCKBYPASS_DISABLE: no bypass + \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving + only one parameter can be selected which is shown as below: + \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle + \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on + \param[in] clock_division: clock division, less than 256 + \param[out] none + \retval none +*/ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) +{ + uint32_t clock_config = 0U; + clock_config = SDIO_CLKCTL; + /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ + clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV); + + /* configure the SDIO_CLKCTL according to the parameters */ + clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); + SDIO_CLKCTL = clock_config; +} + +/*! + \brief enable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief disable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief set different SDIO card bus mode + \param[in] bus_mode: SDIO card bus mode + only one parameter can be selected which is shown as below: + \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode + \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode + \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode + \param[out] none + \retval none +*/ +void sdio_bus_mode_set(uint32_t bus_mode) +{ + /* reset the SDIO card bus mode bits and set according to bus_mode */ + SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; + SDIO_CLKCTL |= bus_mode; +} + +/*! + \brief set the SDIO power state + \param[in] power_state: SDIO power state + only one parameter can be selected which is shown as below: + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off + \param[out] none + \retval none +*/ +void sdio_power_state_set(uint32_t power_state) +{ + SDIO_PWRCTL = power_state; +} + +/*! + \brief get the SDIO power state + \param[in] none + \param[out] none + \retval SDIO power state + only one parameter can be selected which is shown as below: + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off +*/ +uint32_t sdio_power_state_get(void) +{ + return SDIO_PWRCTL; +} + +/*! + \brief enable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; +} + +/*! + \brief disable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; +} + +/*! + \brief configure the command and response + \param[in] cmd_index: command index, refer to the related specifications + \param[in] cmd_argument: command argument, refer to the related specifications + \param[in] response_type: response type + only one parameter can be selected which is shown as below: + \arg SDIO_RESPONSETYPE_NO: no response + \arg SDIO_RESPONSETYPE_SHORT: short response + \arg SDIO_RESPONSETYPE_LONG: long response + \param[out] none + \retval none +*/ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) +{ + uint32_t cmd_config = 0U; + /* reset the command index, command argument and response type */ + SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; + SDIO_CMDAGMT = cmd_argument; + cmd_config = SDIO_CMDCTL; + cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); + /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ + cmd_config |= (cmd_index | response_type); + SDIO_CMDCTL = cmd_config; +} + +/*! + \brief set the command state machine wait type + \param[in] wait_type: wait type + only one parameter can be selected which is shown as below: + \arg SDIO_WAITTYPE_NO: not wait interrupt + \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt + \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer + \param[out] none + \retval none +*/ +void sdio_wait_type_set(uint32_t wait_type) +{ + /* reset INTWAIT and WAITDEND */ + SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); + /* set the wait type according to wait_type */ + SDIO_CMDCTL |= wait_type; +} + +/*! + \brief enable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; +} + +/*! + \brief disable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; +} + +/*! + \brief get the last response command index + \param[in] none + \param[out] none + \retval last response command index +*/ +uint8_t sdio_command_index_get(void) +{ + return (uint8_t)SDIO_RSPCMDIDX; +} + +/*! + \brief get the response for the last received command + \param[in] responsex: SDIO response + only one parameter can be selected which is shown as below: + \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] + \arg SDIO_RESPONSE1: card response[95:64] + \arg SDIO_RESPONSE2: card response[63:32] + \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 + \param[out] none + \retval response for the last received command +*/ +uint32_t sdio_response_get(uint32_t responsex) +{ + uint32_t resp_content = 0U; + switch(responsex){ + case SDIO_RESPONSE0: + resp_content = SDIO_RESP0; + break; + case SDIO_RESPONSE1: + resp_content = SDIO_RESP1; + break; + case SDIO_RESPONSE2: + resp_content = SDIO_RESP2; + break; + case SDIO_RESPONSE3: + resp_content = SDIO_RESP3; + break; + default: + break; + } + return resp_content; +} + +/*! + \brief configure the data timeout, data length and data block size + \param[in] data_timeout: data timeout period in card bus clock periods + \param[in] data_length: number of data bytes to be transferred + \param[in] data_blocksize: size of data block for block transfer + only one parameter can be selected which is shown as below: + \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte + \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes + \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes + \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes + \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes + \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes + \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes + \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes + \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes + \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes + \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes + \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes + \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes + \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes + \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes + \param[out] none + \retval none +*/ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) +{ + /* reset data timeout, data length and data block size */ + SDIO_DATATO &= ~SDIO_DATATO_DATATO; + SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; + SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; + /* configure the related parameters of data */ + SDIO_DATATO = data_timeout; + SDIO_DATALEN = data_length; + SDIO_DATACTL |= data_blocksize; +} + +/*! + \brief configure the data transfer mode and direction + \param[in] transfer_mode: mode of data transfer + only one parameter can be selected which is shown as below: + \arg SDIO_TRANSMODE_BLOCK: block transfer + \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer + \param[in] transfer_direction: data transfer direction, read or write + only one parameter can be selected which is shown as below: + \arg SDIO_TRANSDIRECTION_TOCARD: write data to card + \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card + \param[out] none + \retval none +*/ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) +{ + uint32_t data_trans = 0U; + /* reset the data transfer mode, transfer direction and set according to the parameters */ + data_trans = SDIO_DATACTL; + data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); + data_trans |= (transfer_mode | transfer_direction); + SDIO_DATACTL = data_trans; +} + +/*! + \brief enable the DSM(data state machine) for data transfer + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DATAEN; +} + +/*! + \brief disable the DSM(data state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; +} + +/*! + \brief write data(one word) to the transmit FIFO + \param[in] data: 32-bit data write to card + \param[out] none + \retval none +*/ +void sdio_data_write(uint32_t data) +{ + SDIO_FIFO = data; +} + +/*! + \brief read data(one word) from the receive FIFO + \param[in] none + \param[out] none + \retval received data +*/ +uint32_t sdio_data_read(void) +{ + return SDIO_FIFO; +} + +/*! + \brief get the number of remaining data bytes to be transferred to card + \param[in] none + \param[out] none + \retval number of remaining data bytes to be transferred +*/ +uint32_t sdio_data_counter_get(void) +{ + return SDIO_DATACNT; +} + +/*! + \brief get the number of words remaining to be written or read from FIFO + \param[in] none + \param[out] none + \retval remaining number of words +*/ +uint32_t sdio_fifo_counter_get(void) +{ + return SDIO_FIFOCNT; +} + +/*! + \brief enable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DMAEN; +} + +/*! + \brief disable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; +} + +/*! + \brief get the flags state of SDIO + \param[in] flag: flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_CMDRUN: command transmission in progress flag + \arg SDIO_FLAG_TXRUN: data transmission in progress flag + \arg SDIO_FLAG_RXRUN: data reception in progress flag + \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO + \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO + \arg SDIO_FLAG_TFF: transmit FIFO is full flag + \arg SDIO_FLAG_RFF: receive FIFO is full flag + \arg SDIO_FLAG_TFE: transmit FIFO is empty flag + \arg SDIO_FLAG_RFE: receive FIFO is empty flag + \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag + \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_flag_get(uint32_t flag) +{ + FlagStatus temp_flag = RESET; + if(RESET != (SDIO_STAT & flag)){ + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the pending flags of SDIO + \param[in] flag: flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_flag_clear(uint32_t flag) +{ + SDIO_INTC = flag; +} + +/*! + \brief enable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_enable(uint32_t int_flag) +{ + SDIO_INTEN |= int_flag; +} + +/*! + \brief disable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_disable(uint32_t int_flag) +{ + SDIO_INTEN &= ~int_flag; +} + +/*! + \brief get the interrupt flags state of SDIO + \param[in] int_flag: interrupt flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt + \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt + \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt + \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt + \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt + \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt + \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t state = 0U; + state = SDIO_STAT; + if(state & int_flag){ + state = SDIO_INTEN; + /* check whether the corresponding bit in SDIO_INTEN is set or not */ + if(state & int_flag){ + return SET; + } + } + return RESET; +} + +/*! + \brief clear the interrupt pending flags of SDIO + \param[in] int_flag: interrupt flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag + \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_interrupt_flag_clear(uint32_t int_flag) +{ + SDIO_INTC = int_flag; +} + +/*! + \brief enable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWEN; +} + +/*! + \brief disable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; +} + +/*! + \brief enable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; +} + +/*! + \brief disable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; +} + +/*! + \brief set the read wait type(SD I/O only) + \param[in] readwait_type: SD I/O read wait type + only one parameter can be selected which is shown as below: + \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK + \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] + \param[out] none + \retval none +*/ +void sdio_readwait_type_set(uint32_t readwait_type) +{ + if(SDIO_READWAITTYPE_CLK == readwait_type){ + SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; + }else{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; + } +} + +/*! + \brief enable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_IOEN; +} + +/*! + \brief disable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; +} + +/*! + \brief enable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief disable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief enable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; +} + +/*! + \brief disable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; +} + +/*! + \brief enable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_enable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; +} + +/*! + \brief disable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_disable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; +} + +/*! + \brief enable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; +} + +/*! + \brief disable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c new file mode 100644 index 0000000000..c0fb893ccc --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c @@ -0,0 +1,718 @@ +/*! + \file gd32f10x_spi.c + \brief SPI driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_spi.h" + +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ + +/* I2S clock source selection, multiplication and division mask */ +#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ +#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ +#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ +#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ + +/* default value and offset */ +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /* default value of SPI_I2SPSC register */ +#define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ +#define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph){ + case SPI0: + /* reset SPI0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 and I2S1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + case SPI2: + /* reset SPI2 and I2S2 */ + rcu_periph_reset_enable(RCU_SPI2RST); + rcu_periph_reset_disable(RCU_SPI2RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI struct with the default values + \param[in] spi_struct: SPI parameter stuct + \param[out] none + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct* spi_struct) +{ + /* set the SPI struct with the default values */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; +} + +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI NSS use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)mode; + /* select I2S standard */ + reg |= (uint32_t)standard; + /* select I2S polarity */ + reg |= (uint32_t)ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPIx(x=1,2) + \param[in] audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; + +#ifdef GD32F10X_CL + /* get the I2S clock source */ + if(SPI1 == ((uint32_t)spi_periph)){ + /* I2S1 clock source selection */ + clks = I2S1_CLOCK_SEL; + }else{ + /* I2S2 clock source selection */ + clks = I2S2_CLOCK_SEL; + } + + if(0U != (RCU_CFG1 & clks)){ + /* get RCU PLL2 clock multiplication factor */ + clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); + + if((clks > 5U) && (clks < 15U)){ + /* multiplier is between 8 and 14 */ + clks += 2U; + }else{ + if(15U == clks){ + /* multiplier is 20 */ + clks = 20U; + } + } + + /* get the PREDV1 value */ + i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); + /* calculate I2S clock based on PLL2 and PREDV1 */ + i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); + }else{ + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + } +#else + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); +#endif /* GD32F10X_CL */ + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == mckout){ + clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); + }else{ + if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ + clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); + }else{ + clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)){ + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI NSS pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI NSS pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + }else{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + }else{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* configure SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + }else{ + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief set CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc: SPI crc value + only one parameter can be selected which is shown as below: + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) +{ + if(SPI_CRC_TX == crc){ + return ((uint16_t)(SPI_TCRC(spi_periph))); + }else{ + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt flag status + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if((0U != reg1) && (0U != reg2)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] flag: SPI/I2S flag status + one or more parameters can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(RESET != (SPI_STAT(spi_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c new file mode 100644 index 0000000000..236eedf9be --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c @@ -0,0 +1,2004 @@ +/*! + \file gd32f10x_timer.c + \brief TIMER driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_timer.h" + +/* TIMER init parameter mask */ +#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ +#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ +#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph){ + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; + case TIMER3: + /* reset TIMER3 */ + rcu_periph_reset_enable(RCU_TIMER3RST); + rcu_periph_reset_disable(RCU_TIMER3RST); + break; + case TIMER4: + /* reset TIMER4 */ + rcu_periph_reset_enable(RCU_TIMER4RST); + rcu_periph_reset_disable(RCU_TIMER4RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER6: + /* reset TIMER6 */ + rcu_periph_reset_enable(RCU_TIMER6RST); + rcu_periph_reset_disable(RCU_TIMER6RST); + break; + case TIMER7: + /* reset TIMER7 */ + rcu_periph_reset_enable(RCU_TIMER7RST); + rcu_periph_reset_disable(RCU_TIMER7RST); + break; +#ifdef GD32F10X_XD + case TIMER8: + /* reset TIMER8 */ + rcu_periph_reset_enable(RCU_TIMER8RST); + rcu_periph_reset_disable(RCU_TIMER8RST); + break; + case TIMER9: + /* reset TIMER9 */ + rcu_periph_reset_enable(RCU_TIMER9RST); + rcu_periph_reset_disable(RCU_TIMER9RST); + break; + case TIMER10: + /* reset TIMER10 */ + rcu_periph_reset_enable(RCU_TIMER10RST); + rcu_periph_reset_disable(RCU_TIMER10RST); + break; + case TIMER11: + /* reset TIMER11 */ + rcu_periph_reset_enable(RCU_TIMER11RST); + rcu_periph_reset_disable(RCU_TIMER11RST); + break; + case TIMER12: + /* reset TIMER12 */ + rcu_periph_reset_enable(RCU_TIMER12RST); + rcu_periph_reset_disable(RCU_TIMER12RST); + break; + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; +#endif /* GD32F10X_XD */ + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct* initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP, + TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value,0~65535 + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || + (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || + (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){ + TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); + } + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..4,7..13) + \param[in] aligned: + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..4,7..13) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..4,7..13) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] prescaler: prescaler value + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload){ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] counter: the counter value + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..8,11) + \param[in] spmode: + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + }else if(TIMER_SP_MODE_REPETITIVE == spmode){ + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] update: + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, + or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint32_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + }else if(TIMER_UPDATE_SRC_GLOBAL == update){ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: timer DMA source enable + only one parameter can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: timer DMA source disable + only one parameter can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA disable,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA disable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA disable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA disable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA disable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request disable,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA disable,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: please refer to the following parameters + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) + \param[in] dma_lenth: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief enable or disable TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + }else{ + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + }else{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl){ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U); + } + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U); + } + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U); + } + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] pulse: channel output pulse value + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \arg TIMER_CH_2: TIMER channel2 + \arg TIMER_CH_3: TIMER channel3 + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \arg TIMER_CH_2: TIMER channel2 + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, + TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) + icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, + TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, + TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel){ + case TIMER_CH_0: + /* read TIMER channel 0 capture compare register value */ + count_value = TIMER_CH0CV(timer_periph); + break; + case TIMER_CH_1: + /* read TIMER channel 1 capture compare register value */ + count_value = TIMER_CH1CV(timer_periph); + break; + case TIMER_CH_2: + /* read TIMER channel 2 capture compare register value */ + count_value = TIMER_CH2CV(timer_periph); + break; + case TIMER_CH_3: + /* read TIMER channel 3 capture compare register value */ + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ + icpolarity = TIMER_IC_POLARITY_FALLING; + }else{ + icpolarity = TIMER_IC_POLARITY_RISING; + } + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ + icselection = TIMER_IC_SELECTION_INDIRECTTI; + }else{ + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel){ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); + }else{ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: please refer to the following parameters + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..7) + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable + \arg TIMER_ENCODER_MODE0: encoder mode 0 + \arg TIMER_ENCODER_MODE1: encoder mode 1 + \arg TIMER_ENCODER_MODE2: encoder mode 2 + \arg TIMER_SLAVE_MODE_RESTART: restart mode + \arg TIMER_SLAVE_MODE_PAUSE: pause mode + \arg TIMER_SLAVE_MODE_EVENT: event mode + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] masterslave: + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] decomode: + only one parameter can be selected which is shown as below: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) +{ + /* configure the quadrature decoder mode */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + /* configure input capture selection */ + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + /* configure channel input capture polarity */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph,intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] expolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + }else{ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph,extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source disable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)flag); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c new file mode 100644 index 0000000000..3e6c97ee6f --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c @@ -0,0 +1,767 @@ +/*! + \file gd32f10x_usart.c + \brief USART driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.1, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_usart.h" + +/*! + \brief reset USART/UART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph){ + case USART0: + /* reset USART0 */ + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + /* reset USART1 */ + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + case USART2: + /* reset USART2 */ + rcu_periph_reset_enable(RCU_USART2RST); + rcu_periph_reset_disable(RCU_USART2RST); + break; + case UART3: + /* reset UART3 */ + rcu_periph_reset_enable(RCU_UART3RST); + rcu_periph_reset_disable(RCU_UART3RST); + break; + case UART4: + /* reset UART4 */ + rcu_periph_reset_enable(RCU_UART4RST); + rcu_periph_reset_disable(RCU_UART4RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; + switch(usart_periph){ + /* get clock frequency */ + case USART0: + /* get USART0 clock */ + uclk=rcu_clock_freq_get(CK_APB2); + break; + case USART1: + /* get USART1 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case USART2: + /* get USART2 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case UART3: + /* get UART3 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case UART4: + /* get UART4 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk+baudval/2U)/baudval; + intdiv = udiv & (0x0000fff0U); + fradiv = udiv & (0x0000000fU); + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] paritycfg: configure USART parity + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg ; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + /* configure USART stop bits */ + USART_CTL1(usart_periph) |= stblen; +} +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_TEN; + ctl |= txconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_REN; + ctl |= rxconfig; + /* configure receiver mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_DATA(usart_periph) = USART_DATA_DATA & data; +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] addr: address of USART/UART + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); +} + +/*! + \brief receiver in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_RWU; +} + +/*! + \brief receiver in active mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wmethod: two methods be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mask + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure lin break frame length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] lblen: lin break frame length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits + \arg USART_LBLEN_11B: 11 bits + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); +} + +/*! + \brief send break frame + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_send_break(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; +} + +/*! + \brief enable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] clen: CK length + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + uint32_t ctl = 0U; + + /* read USART_CTL1 register */ + ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + /* set CK length, CK phase, CK polarity */ + ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); + + USART_CTL1(usart_periph) = ctl; +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] gaut: guard time value + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut) +{ + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] psc: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) +{ + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hardwareflow: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_RTSEN; + ctl |= rtsconfig; + /* configure RTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hardwareflow: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_CTSEN; + ctl |= ctsconfig; + /* configure CTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENR; + ctl |= dmacmd; + /* configure DMA reception */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENT; + ctl |= dmacmd; + /* configure DMA transmission */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief get flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_LBDF: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLEF: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_LBDF: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \param[out] none + \retval FlagStatus +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if(flagstatus && intenable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear USART interrupt flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART interrupt flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) +{ + USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c new file mode 100644 index 0000000000..633b50423b --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c @@ -0,0 +1,150 @@ +/*! + \file gd32f10x_wwdgt.c + \brief WWDGT driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_wwdgt.h" + +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + uint32_t reg = 0U; + + reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); + reg |= CTL_CNT(counter_value); + + WWDGT_CTL = reg; +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + uint32_t reg_cfg = 0U, reg_ctl = 0U; + + /* clear WIN and PSC bits, clear CNT bit */ + reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); + reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); + + /* configure WIN and PSC bits, configure CNT bit */ + reg_cfg |= CFG_WIN(window); + reg_cfg |= prescaler; + reg_ctl |= CTL_CNT(counter); + + WWDGT_CTL = reg_ctl; + WWDGT_CFG = reg_cfg; +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(WWDGT_STAT & WWDGT_STAT_EWIF){ + return SET; + } + + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT &= (~WWDGT_STAT_EWIF); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h new file mode 100644 index 0000000000..189be18bae --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h @@ -0,0 +1,217 @@ +/*! + \file usbd_core.h + \brief USB device driver core + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_CORE_H +#define USBD_CORE_H + +#include "usbd_conf.h" +#include "usbd_regs.h" + +/* interrupt flag mask which decide what event should be handled by application */ +#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ + | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE) + +#ifdef LPM_ENABLED +#undef IER_MASK + +#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ + | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE | CTL_L1REQIE) +#endif /* LPM_ENABLED */ + +/* USB device endpoint0 max packet size */ +#define USBD_EP0_MAX_SIZE 64U + +#define USBD_CONTRL_STATUS_TX() do \ +{ \ + pbuf_reg->tx_count = 0U; \ + USBD_ENDP_TX_STATUS_SET(EP0, EPTX_VALID); \ +} while(0) + +#define USBD_CONTRL_STATUS_RX() do \ +{ \ + USBD_STATUS_OUT_SET(EP0); \ + USBD_ENDP_RX_STATUS_SET(EP0, EPRX_VALID); \ +} while(0) + +#define ENDP_BUF_ADDR (sizeof(usbd_ep_buf_struct) * EP_COUNT) + +/* USB device endpoint type */ +typedef enum +{ + ENDP_CONTROL = 0, /*!< control endpoint type value */ + ENDP_ISOC, /*!< isochronous endpoint type value */ + ENDP_BULK, /*!< bulk endpoint type value */ + ENDP_INT /*!< interupt endpoint type value */ +}usbd_eptype_enum; + +/* USB device endpoint kind */ +typedef enum +{ + ENDP_SNG_BUF = 0, /*!< single buffer endpoint type value */ + ENDP_DBL_BUF /*!< double buffer endpoint type value */ +}usbd_epkind_enum; + +/* transfer direction */ +typedef enum +{ + USBD_RX = 0, /*!< receive direction type value */ + USBD_TX /*!< transmit direction type value */ +}usbd_dir_enum; + +/* USB device status */ +typedef enum +{ + USBD_UNCONNECTED = 0, /*!< USB device unconnected status */ + USBD_DEFAULT, /*!< USB device default status */ + USBD_ADDRESSED, /*!< USB device addressed status */ + USBD_CONFIGURED, /*!< USB device configured status */ + USBD_SUSPENDED, /*!< USB device suspended status */ + USBD_CONNECTED /*!< USB device connected status */ +}usbd_run_status_enum; + +/* USB device operation state */ +typedef enum +{ + USBD_OK = 0, /*!< USB device ok */ + USBD_BUSY, /*!< USB device busy */ + USBD_FAIL /*!< USB device fail */ +}usbd_status_enum; + +typedef struct +{ + uint16_t tx_addr; /*!< transmission address */ + uint16_t reserved0; + uint16_t tx_count; /*!< transmission count */ + uint16_t reserved1; + uint16_t rx_addr; /*!< reception address */ + uint16_t reserved2; + uint16_t rx_count; /*!< reception count */ + uint16_t reserved3; +}usbd_ep_buf_struct; + +/* USB endpoint structure */ +typedef struct +{ + /* basic parameters */ + uint8_t stall; /*!< endpoint stall status */ + uint32_t maxpacket; /*!< the maxpacket of the endpoint */ + + /* transaction level parameters */ + uint8_t *trs_buf; /*!< transaction buffer address */ + uint32_t trs_len; /*!< transaction buffer length */ + uint32_t trs_count; /*!< transaction data counts */ +}usb_ep_struct; + +/* USB standard device request structure */ +typedef struct +{ + uint8_t bmRequestType; /*!< the property of the request */ + uint8_t bRequest; /*!< the code of the request */ + uint16_t wValue; /*!< the value of the request which used to choose the different request in the same code request */ + uint16_t wIndex; /*!< USB standard device request index */ + uint16_t wLength; /*!< the return datas length that the host wants to get */ +}usb_device_req_struct; + +/* USB core driver struct */ +typedef struct +{ + /* basic parameters */ + uint8_t config_num; /*!< the number of the USB device configuration */ + __IO uint8_t status; /*!< USB device status */ + uint8_t prev_status; /*!< the previous USB device status */ + uint8_t remote_wakeup; /*!< the flag that point out the device whether support the remote wakeup function */ + + /* the parameters which needs in control transfer */ + uint8_t setup_packet[8]; /*!< the buffer used to store the setup packet */ + uint32_t ctl_count; /*!< the datas length of control transfer request */ + + /* device endpoints */ + usb_ep_struct in_ep[EP_COUNT]; /*!< the in direction endpoints */ + usb_ep_struct out_ep[EP_COUNT]; /*!< the out direction endpoints */ + +#ifdef LPM_ENABLED + uint8_t *bos_desc; /*!< BOS descriptor */ +#endif /* LPM_ENABLED */ + + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< configuration descriptor */ + void* const *strings; /*!< configuration strings */ + + /* device class handler */ + usbd_status_enum (*class_init) (void *pudev, uint8_t config_index); + usbd_status_enum (*class_deinit) (void *pudev, uint8_t config_index); + usbd_status_enum (*class_req_handler) (void *pudev, usb_device_req_struct *req); + usbd_status_enum (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num); +}usbd_core_handle_struct; + +extern uint32_t g_free_buf_addr; +extern usbd_ep_buf_struct *pbuf_reg; + +/* function declarations */ +/* device core register initialization */ +void usbd_core_init (usbd_core_handle_struct *pudev); +/* device core register configure when stop device */ +void usbd_core_deinit (void); + +/* free buffer used from application by toggling the SW_BUF byte */ +void user_buffer_free (uint8_t ep_num, uint8_t dir); + +/* endpoint initialization */ +void usbd_ep_init (usbd_core_handle_struct *pudev, usbd_epkind_enum buf_kind, void *pep_desc); +/* configure the endpoint when it is disabled */ +void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr); +/* endpoint prepare to transmit data */ +void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +/* endpoint prepare to receive data */ +void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +/* set an endpoint to stall status */ +void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); +/* clear endpoint stalled status */ +void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); +/* write datas from user fifo to USBRAM */ +void usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); +/* read datas from USBRAM to user fifo */ +void usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); + +/* get the endpoint status */ +uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr); + +/* get the received data length */ +uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num); + +#endif /* USBD_CORE_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h new file mode 100644 index 0000000000..a524ea615f --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h @@ -0,0 +1,62 @@ +/*! + \file usbd_int.h + \brief USB device interrupt handler header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_INT_H +#define USBD_INT_H + +#include "usbd_core.h" +#include "usbd_std.h" +#include "usbd_pwr.h" + +/* constants definitions */ +extern usbd_core_handle_struct usb_device_dev; + +typedef struct +{ + uint8_t (*SOF) (usbd_core_handle_struct *pudev); /*!< SOF ISR callback */ +}usbd_int_cb_struct; + +extern usbd_int_cb_struct *usbd_int_fops; + +/* function declarations */ +/* USB device interrupt service routine */ +void usbd_isr (void); +/* handle USB high priority successful transfer event */ +uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev); + +#endif /* USBD_INT_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h new file mode 100644 index 0000000000..c0e6a21a19 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h @@ -0,0 +1,52 @@ +/*! + \file usbd_pwr.h + \brief USB device power management functions prototype + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_PWR_H +#define USBD_PWR_H + +#include "usbd_core.h" + +/* function declarations */ +/* USB wakeup first operation is to wakeup mcu */ +void resume_mcu (void); +/* set USB device to suspend mode */ +void usbd_suspend (void); +/* start to remote wakeup */ +void usbd_remote_wakeup_active (void); + +#endif /* USBD_PWR_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h new file mode 100644 index 0000000000..ef3c5c8fcc --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h @@ -0,0 +1,297 @@ +/*! + \file usbd_regs.h + \brief USB device registers + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_REGS_H +#define USBD_REGS_H + +#include "usbd_conf.h" + +/* USB device registers base address */ +#define USBD USBD_BASE +#define USBD_RAM (APB1_BUS_BASE + 0x00006000U) + +/* registers definitions */ +/* common registers */ +#define USBD_CTL (REG32(USBD + 0x40U)) /*!< control register */ +#define USBD_INTF (REG32(USBD + 0x44U)) /*!< interrupt flag register */ +#define USBD_STAT (REG32(USBD + 0x48U)) /*!< status register */ +#define USBD_DADDR (REG32(USBD + 0x4CU)) /*!< device address register */ +#define USBD_BADDR (REG32(USBD + 0x50U)) /*!< buffer address register */ + +/* endpoint control and status register */ +#define USBD_EPxCS(ep_id) (REG32(USBD + (ep_id) * 4U)) /*!< endpoint x control and status register address */ + +/* LPM Registers */ +#define USBD_LPMCS (REG32(USBD + 0x54U)) /*!< USBD LPM control and status register */ + +/* bits definitions */ +/* USBD_CTL */ +#define CTL_STIE BIT(15) /*!< successful transfer interrupt enable mask */ +#define CTL_PMOUIE BIT(14) /*!< packet memory overrun/underrun interrupt enable mask */ +#define CTL_ERRIE BIT(13) /*!< error interrupt enable mask */ +#define CTL_WKUPIE BIT(12) /*!< wakeup interrupt enable mask */ +#define CTL_SPSIE BIT(11) /*!< suspend state interrupt enable mask */ +#define CTL_RSTIE BIT(10) /*!< reset interrupt enable mask */ +#define CTL_SOFIE BIT(9) /*!< start of frame interrupt enable mask */ +#define CTL_ESOFIE BIT(8) /*!< expected start of frame interrupt enable mask */ +#define CTL_L1REQIE BIT(7) /*!< LPM L1 state request interrupt enable */ +#define CTL_L1RSREQ BIT(5) /*!< LPM L1 resume request */ +#define CTL_RSREQ BIT(4) /*!< resume request */ +#define CTL_SETSPS BIT(3) /*!< set suspend state */ +#define CTL_LOWM BIT(2) /*!< low-power mode at suspend state */ +#define CTL_CLOSE BIT(1) /*!< goes to close state */ +#define CTL_SETRST BIT(0) /*!< set USB reset */ + +/* USBD_INTF */ +#define INTF_STIF BIT(15) /*!< successful transfer interrupt flag (read only bit) */ +#define INTF_PMOUIF BIT(14) /*!< packet memory overrun/underrun interrupt flag (clear-only bit) */ +#define INTF_ERRIF BIT(13) /*!< error interrupt flag (clear-only bit) */ +#define INTF_WKUPIF BIT(12) /*!< wakeup interrupt flag (clear-only bit) */ +#define INTF_SPSIF BIT(11) /*!< suspend state interrupt flag (clear-only bit) */ +#define INTF_RSTIF BIT(10) /*!< reset interrupt flag (clear-only bit) */ +#define INTF_SOFIF BIT(9) /*!< start of frame interrupt flag (clear-only bit) */ +#define INTF_ESOFIF BIT(8) /*!< expected start of frame interrupt flag(clear-only bit) */ +#define INTF_L1REQ BIT(7) /*!< LPM L1 transaction is successfully received and acknowledged */ +#define INTF_DIR BIT(4) /*!< direction of transaction (read-only bit) */ +#define INTF_EPNUM BITS(0, 3) /*!< endpoint number (read-only bit) */ + +/* USBD_STAT */ +#define STAT_RXDP BIT(15) /*!< data plus line status */ +#define STAT_RXDM BIT(14) /*!< data minus line status */ +#define STAT_LOCK BIT(13) /*!< locked the USB */ +#define STAT_SOFLN BITS(11, 12) /*!< SOF lost number */ +#define STAT_FCNT BITS(0, 10) /*!< frame number count */ + +/* USBD_DADDR */ +#define DADDR_USBEN BIT(7) /*!< USB module enable */ +#define DADDR_USBDAR BITS(0, 6) /*!< USB device address */ + +/* USBD_EPxCS */ +#define EPxCS_RX_ST BIT(15) /*!< endpoint reception successful transferred */ +#define EPxCS_RX_DTG BIT(14) /*!< endpoint reception data PID toggle */ +#define EPxCS_RX_STA BITS(12, 13) /*!< endpoint reception status bits */ +#define EPxCS_SETUP BIT(11) /*!< endpoint setup transaction completed */ +#define EPxCS_CTL BITS(9, 10) /*!< endpoint type control */ +#define EPxCS_KCTL BIT(8) /*!< endpoint kind control */ +#define EPxCS_TX_ST BIT(7) /*!< endpoint transmission successful transfer */ +#define EPxCS_TX_DTG BIT(6) /*!< endpoint transmission data toggle */ +#define EPxCS_TX_STA BITS(4, 5) /*!< endpoint transmission transfers status bits */ +#define EPxCS_ADDR BITS(0, 3) /*!< endpoint address */ + +/* USBD_LPMCS */ +#define LPMCS_BLSTAT BITS(4, 7) /*!< bLinkState value */ +#define LPMCS_REMWK BIT(3) /*!< bRemoteWake value */ +#define LPMCS_LPMACK BIT(1) /*!< LPM token acknowledge enable */ +#define LPMCS_LPMEN BIT(0) /*!< LPM support enable */ + +/* constants definitions */ +/* endpoint control and status register mask (no toggle fields) */ +#define EPCS_MASK (EPxCS_RX_ST|EPxCS_SETUP|EPxCS_CTL|EPxCS_KCTL|EPxCS_TX_ST|EPxCS_ADDR) + +/* EPxCS_CTL[1:0] endpoint type control */ +#define ENDP_TYPE(regval) (EPxCS_CTL & ((regval) << 9U)) + +#define EP_BULK ENDP_TYPE(0U) /* bulk transfers */ +#define EP_CONTROL ENDP_TYPE(1U) /* control transfers */ +#define EP_ISO ENDP_TYPE(2U) /* isochronous transfers */ +#define EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */ +#define EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK) + +/* endpoint kind control mask */ +#define EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK) + +/* EPxCS_TX_STA[1:0] status for tx transfer */ +#define ENDP_TXSTAT(regval) (EPxCS_TX_STA & ((regval) << 4U)) + +#define EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */ +#define EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */ +#define EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */ +#define EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */ +#define EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK) + +/* EPxCS_RX_STA[1:0] status for rx transfer */ +#define ENDP_RXSTAT(regval) (EPxCS_RX_STA & ((regval) << 12U)) + +#define EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */ +#define EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */ +#define EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */ +#define EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */ +#define EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK) + +/* endpoint receive/transmission counter register bit definitions */ +#define EPRCNT_BLKSIZ BIT(15) /* reception data block size */ +#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */ +#define EPRCNT_CNT BITS(0, 9) /* reception data count */ + +#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */ + +/* interrupt flag clear bits */ +#define CLR_STIF (~INTF_STIF) +#define CLR_PMOUIF (~INTF_PMOUIF) +#define CLR_ERRIF (~INTF_ERRIF) +#define CLR_WKUPIF (~INTF_WKUPIF) +#define CLR_SPSIF (~INTF_SPSIF) +#define CLR_RSTIF (~INTF_RSTIF) +#define CLR_SOFIF (~INTF_SOFIF) +#define CLR_ESOFIF (~INTF_ESOFIF) +#define CLR_L1REQ (~INTF_L1REQ) + +/* endpoint receive/transmission counter register bit offset */ +#define BLKSIZE_OFFSET (0x01U) +#define BLKNUM_OFFSET (0x05U) +#define RXCNT_OFFSET (0x0AU) + +#define TXCNT_OFFSET (0x0AU) + +#define BLKSIZE32_MASK (0x1fU) +#define BLKSIZE2_MASK (0x01U) + +#define BLKSIZE32_OFFSETMASK (0x05U) +#define BLKSIZE2_OFFSETMASK (0x01U) + +/* double buffer endpoint direction */ +typedef enum +{ + DBUF_EP_IN, /* double buffer IN direction */ + DBUF_EP_OUT, /* double buffer OUT direction */ + DBUF_EP_ERR, /* double buffer errer direction */ +}dbuf_ep_dir_enum; + +/* endpoints address */ +/* first bit is direction(0 for rx and 1 for tx) */ +#define EP0_OUT ((uint8_t)0x00) /* out endpoint 0 address */ +#define EP0_IN ((uint8_t)0x80) /* in endpoint 0 address */ +#define EP1_OUT ((uint8_t)0x01) /* out endpoint 1 address */ +#define EP1_IN ((uint8_t)0x81) /* in endpoint 1 address */ +#define EP2_OUT ((uint8_t)0x02) /* out endpoint 2 address */ +#define EP2_IN ((uint8_t)0x82) /* in endpoint 2 address */ +#define EP3_OUT ((uint8_t)0x03) /* out endpoint 3 address */ +#define EP3_IN ((uint8_t)0x83) /* in endpoint 3 address */ +#define EP4_OUT ((uint8_t)0x04) /* out endpoint 4 address */ +#define EP4_IN ((uint8_t)0x84) /* in endpoint 4 address */ +#define EP5_OUT ((uint8_t)0x05) /* out endpoint 5 address */ +#define EP5_IN ((uint8_t)0x85) /* in endpoint 5 address */ +#define EP6_OUT ((uint8_t)0x06) /* out endpoint 6 address */ +#define EP6_IN ((uint8_t)0x86) /* in endpoint 6 address */ +#define EP7_OUT ((uint8_t)0x07) /* out endpoint 7 address */ +#define EP7_IN ((uint8_t)0x87) /* in endpoint 7 address */ + +/* endpoints_identifier */ +#define EP0 ((uint8_t)0) /* endpoint 0 ID */ +#define EP1 ((uint8_t)1) /* endpoint 1 ID */ +#define EP2 ((uint8_t)2) /* endpoint 2 ID */ +#define EP3 ((uint8_t)3) /* endpoint 3 ID */ +#define EP4 ((uint8_t)4) /* endpoint 4 ID */ +#define EP5 ((uint8_t)5) /* endpoint 5 ID */ +#define EP6 ((uint8_t)6) /* endpoint 6 ID */ +#define EP7 ((uint8_t)7) /* endpoint 7 ID */ + +/* USBD operation macros */ + +/* set register value */ +#define USBD_REG_SET(reg, regvalue) ((reg) = (uint16_t)(regvalue)) + +/* get register value */ +#define USBD_REG_GET(reg) ((uint16_t)(reg)) + +#define _EP_ADDR_SET(ep_num, addr) USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK) | addr) + +/* tx or rx transfer status setting (bits EPTX_STA[1:0]) */ +#define USBD_ENDP_TX_STATUS_SET(ep_num, state) do {\ + register uint16_t _regval; \ + _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPTX_DTGMASK;\ + USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ +} while(0) + +#define USBD_ENDP_RX_STATUS_SET(ep_num, state) do {\ + register uint16_t _regval; \ + _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPRX_DTGMASK;\ + USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ +} while(0) + +/* tx or rx transfer status getting (bits EPxCS_RX_STA[1:0]) */ +#define USBD_ENDP_TX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_STA) +#define USBD_ENDP_RX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_STA) + +/* rx and tx transfer status setting (bits EPxCS_RX_STA[1:0] & EPxCS_TX_STA[1:0]) */ +#define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx) do {\ + register uint16_t _regval; \ + _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)(EPRX_DTGMASK | EPxCS_TX_STA) ;\ + USBD_REG_SET(USBD_EPxCS(ep_num), (((_regval) ^ (state_rx)) ^ (state_tx))); \ +} while(0) + +/* set and clear endpoint kind (bit EPxCS_KCTL) */ +#define USBD_ENDP_KIND_SET(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), ((USBD_REG_GET(USBD_EPxCS(ep_num)) | EPxCS_KCTL) & EPCS_MASK))) +#define USBD_ENDP_KIND_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPKCTL_MASK))) + +/* set and clear directly STATUS_OUT state of endpoint */ +#define USBD_STATUS_OUT_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) +#define USBD_STATUS_OUT_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) + +/* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */ +#define USBD_ENDP_RX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0x7FFFU & (uint16_t)EPCS_MASK)) +#define USBD_ENDP_TX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0xFF7FU & (uint16_t)EPCS_MASK)) + +/* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ +#define USBD_DTG_RX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_RX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) +#define USBD_DTG_TX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_TX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) + +/* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ +#define USBD_DTG_RX_CLEAR(ep_num) do {\ + if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_DTG) != 0U) {\ + USBD_DTG_RX_TOGGLE(ep_num);\ + } else {\ + }\ +} while(0) + +#define USBD_DTG_TX_CLEAR(ep_num) do {\ + if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_DTG) != 0U) {\ + USBD_DTG_TX_TOGGLE(ep_num);\ + } else {\ + }\ +} while(0) + +/* set and clear directly double buffered feature of endpoint */ +#define USBD_ENDP_DOUBLE_BUF_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) +#define USBD_ENDP_DOUBLE_BUF_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) + +/* toggle SW_BUF bit in the double buffered endpoint */ +#define USBD_SWBUF_TX_TOGGLE(ep_num) USBD_DTG_RX_TOGGLE(ep_num) +#define USBD_SWBUF_RX_TOGGLE(ep_num) USBD_DTG_TX_TOGGLE(ep_num) + +#endif /* USBD_REGS_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h new file mode 100644 index 0000000000..58a85d6cfc --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h @@ -0,0 +1,221 @@ +/*! + \file usbd_std.h + \brief USB standard definitions + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_STD_H +#define USBD_STD_H + +#include "usbd_core.h" +#include + +#ifndef NULL +#define NULL 0U +#endif + +/* constants definitions */ +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /* device qualifier descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /* configuration descriptor length */ + +#define USBD_LANGID_STR_IDX 0x00U /* language ID string index */ +#define USBD_MFC_STR_IDX 0x01U /* manufacturer string index */ +#define USBD_PRODUCT_STR_IDX 0x02U /* product string index */ +#define USBD_SERIAL_STR_IDX 0x03U /* serial string index */ +#define USBD_CONFIG_STR_IDX 0x04U /* configuration string index */ +#define USBD_INTERFACE_STR_IDX 0x05U /* interface string index */ + +#define USB_STANDARD_REQ 0x00U /* standard request */ +#define USB_CLASS_REQ 0x20U /* device class request */ +#define USB_VENDOR_REQ 0x40U /* vendor request */ +#define USB_REQ_MASK 0x60U /* request type mask */ + +#define USB_REQTYPE_DEVICE 0x00U /* request recipient is device */ +#define USB_REQTYPE_INTERFACE 0x01U /* request recipient is interface */ +#define USB_REQTYPE_ENDPOINT 0x02U /* request recipient is endpoint */ +#define USB_REQ_RECIPIENT_MASK 0x1fU /* request recipient mask */ + +#define USBREQ_GET_STATUS 0x00U /* Get_Status standard requeset */ +#define USBREQ_CLEAR_FEATURE 0x01U /* Clear_Feature standard requeset */ +#define USBREQ_SET_FEATURE 0x03U /* Set_Feature standard requeset */ +#define USBREQ_SET_ADDRESS 0x05U /* Set_Address standard requeset */ +#define USBREQ_GET_DESCRIPTOR 0x06U /* Get_Descriptor standard requeset */ +#define USBREQ_GET_CONFIGURATION 0x08U /* Get_Configuration standard requeset */ +#define USBREQ_SET_CONFIGURATION 0x09U /* Set_Configuration standard requeset */ +#define USBREQ_GET_INTERFACE 0x0AU /* Get_Interface standard requeset */ +#define USBREQ_SET_INTERFACE 0x0BU /* Set_Interface standard requeset */ + +#define USB_DESCTYPE_DEVICE 0x01U /* device descriptor type */ +#define USB_DESCTYPE_CONFIGURATION 0x02U /* configuration descriptor type */ +#define USB_DESCTYPE_STRING 0x03U /* string descriptor type */ +#define USB_DESCTYPE_INTERFACE 0x04U /* interface descriptor type */ +#define USB_DESCTYPE_ENDPOINT 0x05U /* endpoint descriptor type */ +#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /* device qualifier descriptor type */ +#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /* other speed configuration descriptor type */ +#define USB_DESCTYPE_BOS 0x0FU /* BOS descriptor type */ + +#define USB_STATUS_REMOTE_WAKEUP 2U /* USB is in remote wakeup status */ +#define USB_STATUS_SELF_POWERED 1U /* USB is in self powered status */ + +#define USB_FEATURE_ENDP_HALT 0U /* USB has endpoint halt feature */ +#define USB_FEATURE_REMOTE_WAKEUP 1U /* USB has endpoint remote wakeup feature */ +#define USB_FEATURE_TEST_MODE 2U /* USB has endpoint test mode feature */ + +#define ENG_LANGID 0x0409U /* english language ID */ +#define CHN_LANGID 0x0804U /* chinese language ID */ + +#define USB_EPTYPE_MASK 0x03U + +#define USB_DEVICE_DESC_SIZE 0x12U + +/* USB device exported macros */ +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) +#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) + +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) + +#define WIDE_STRING(string) _WIDE_STRING(string) +#define _WIDE_STRING(string) L##string + +#define USBD_STRING_DESC(string) \ + (void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(string)]; \ + }) { \ + sizeof(WIDE_STRING(string)) + 2U - 2U, \ + USB_DESCTYPE_STRING, \ + WIDE_STRING(string) \ + } + +typedef struct +{ + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_descriptor_header_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_descriptor_device_struct; + +#pragma pack(1) + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_descriptor_configuration_struct; + +#pragma pack() + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_descriptor_interface_struct; + +#pragma pack(1) + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ +} usb_descriptor_endpoint_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +}usb_descriptor_language_id_struct; + +#pragma pack() + +/* function declarations */ +/* USB setup transaction processing */ +uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev); +/* USB out transaction processing */ +uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); +/* USB in transaction processing */ +uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); + +/* handle USB standard device request */ +uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +/* handle device class request */ +uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +/* handle USB vendor request */ +uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); + +/* decode setup data packet */ +void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +/* handle USB enumeration error event */ +void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req); + +#endif /* USBD_STD_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c new file mode 100644 index 0000000000..4af7b03469 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c @@ -0,0 +1,455 @@ +/*! + \file usbd_core.c + \brief USB device driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_core.h" +#include "usbd_std.h" + +uint32_t g_interrupt_mask = 0U; +uint32_t g_free_buf_addr = ENDP_BUF_ADDR; + +usbd_ep_buf_struct *pbuf_reg = (usbd_ep_buf_struct *)USBD_RAM; + +/*! + \brief device core register initialization + \param[in] none + \param[out] none + \retval none +*/ +void usbd_core_init (usbd_core_handle_struct *pudev) +{ + /* disable remote wakeup feature */ + pudev->remote_wakeup = 0U; + + /* just reset the CLOSE bit */ + USBD_REG_SET(USBD_CTL, CTL_SETRST); + + /* may be need wait some time(tSTARTUP) ... */ + + /* clear SETRST bit in USBD_CTL register */ + USBD_REG_SET(USBD_CTL, 0U); + + /* clear all pending interrupts */ + USBD_REG_SET(USBD_INTF, 0U); + + /* set allocation buffer address */ + USBD_REG_SET(USBD_BADDR, BUFFER_ADDRESS & 0xFFF8U); + + g_interrupt_mask = IER_MASK; + +#ifdef LPM_ENABLED + /* enable L1REQ interrupt */ + USBD_REG_SET(USBD_LPMCS, LPMCS_LPMACK | LPMCS_LPMEN); +#endif /* LPM_ENABLED */ + + /* enable all interrupts mask bits */ + USBD_REG_SET(USBD_CTL, g_interrupt_mask); +} + +/*! + \brief free buffer used from application by toggling the SW_BUF byte + \param[in] ep_num: endpoint identifier (0..7) + \param[in] dir: endpoint direction which can be OUT(0) or IN(1) + \param[out] none + \retval None +*/ +void user_buffer_free (uint8_t ep_num, uint8_t dir) +{ + if (DBUF_EP_OUT == dir) { + USBD_SWBUF_RX_TOGGLE(ep_num); + } else if (DBUF_EP_IN == dir) { + USBD_SWBUF_TX_TOGGLE(ep_num); + } else { + /* no operation */ + } +} + +/*! + \brief device core register configure when stop device + \param[in] none + \param[out] none + \retval none +*/ +void usbd_core_deinit (void) +{ + /* disable all interrupts and set USB reset */ + USBD_REG_SET(USBD_CTL, CTL_SETRST); + + /* clear all interrupt flags */ + USBD_REG_SET(USBD_INTF, 0U); + + /* close device */ + USBD_REG_SET(USBD_CTL, CTL_SETRST | CTL_CLOSE); +} + +/*! + \brief endpoint initialization + \param[in] pudev: pointer to USB core instance + \param[in] buf_kind: kind of buffer + \param[in] pep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +void usbd_ep_init (usbd_core_handle_struct *pudev, usbd_epkind_enum buf_kind, void *ep_desc) +{ + usb_descriptor_endpoint_struct *desc_ep = (usb_descriptor_endpoint_struct *)ep_desc; + + uint8_t ep_num = desc_ep->bEndpointAddress & 0x0FU; + uint32_t reg_value = 0; + + /* set the endpoint type */ + switch (desc_ep->bmAttributes & USB_EPTYPE_MASK) { + case ENDP_CONTROL: + reg_value = EP_CONTROL; + break; + case ENDP_BULK: + reg_value = EP_BULK; + break; + case ENDP_INT: + reg_value = EP_INTERRUPT; + break; + case ENDP_ISOC: + reg_value = EP_ISO; + break; + default: + break; + } + + USBD_REG_SET(USBD_EPxCS(ep_num), reg_value | ep_num); + + reg_value = desc_ep->wMaxPacketSize; + + if (desc_ep->bEndpointAddress >> 7U) { + usb_ep_struct *ep = &pudev->in_ep[ep_num]; + + ep->maxpacket = reg_value; + + /* set the endpoint transmit buffer address */ + (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; + + reg_value = (reg_value + 1U) & ~1U; + + g_free_buf_addr += reg_value; + + if (ENDP_DBL_BUF == buf_kind) { + USBD_ENDP_DOUBLE_BUF_SET(ep_num); + + (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; + + g_free_buf_addr += reg_value; + + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); + } else { + /* configure the endpoint status as NAK status */ + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); + } + } else { + usb_ep_struct *ep = &pudev->out_ep[ep_num]; + + ep->maxpacket = reg_value; + + if (ENDP_DBL_BUF == buf_kind) { + USBD_ENDP_DOUBLE_BUF_SET(ep_num); + + USBD_DTG_TX_TOGGLE(ep_num); + + /* set the endpoint transmit buffer address */ + (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; + + if (reg_value > 62U) { + reg_value = (reg_value + 31U) & ~31U; + (pbuf_reg + ep_num)->tx_count = (uint16_t)(((reg_value << 5U) - 1U) | 0x8000U); + } else { + reg_value = (reg_value + 1U) & ~1U; + (pbuf_reg + ep_num)->tx_count = (uint16_t)(reg_value << 9U); + } + + g_free_buf_addr += reg_value; + } + + reg_value = desc_ep->wMaxPacketSize; + + /* set the endpoint receive buffer address */ + (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; + + if (reg_value > 62U) { + reg_value = (reg_value + 31U) & ~31U; + (pbuf_reg + ep_num)->rx_count = (uint16_t)(((reg_value << 5U) - 1U) | 0x8000U); + } else { + reg_value = (reg_value + 1U) & ~1U; + (pbuf_reg + ep_num)->rx_count = (uint16_t)(reg_value << 9U); + } + + if (ENDP_DBL_BUF == buf_kind) { + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); + } else { + /* configure the endpoint status as NAK status */ + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_NAK); + } + } +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] pudev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint8_t ep_num = ep_addr & 0x7F; + + if (ep_addr >> 7) { + USBD_DTG_TX_CLEAR(ep_num); + + /* configure the endpoint status as DISABLED */ + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_DISABLED); + } else { + USBD_DTG_RX_CLEAR(ep_num); + + /* configure the endpoint status as DISABLED */ + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); + } +} + +/*! + \brief endpoint prepare to receive data + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] buf_len: buffer length + \param[out] none + \retval none +*/ +void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + usb_ep_struct *ep; + uint8_t ep_num = ep_addr & 0x7FU; + + ep = &pudev->out_ep[ep_num]; + + /* configure the transaction level parameters */ + ep->trs_buf = pbuf; + ep->trs_len = buf_len; + + /* enable endpoint to receive */ + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); +} + +/*! + \brief endpoint prepare to transmit data + \param[in] pudev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] buf_len: buffer length + \param[out] none + \retval none +*/ +void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + __IO uint32_t len = 0U; + uint8_t ep_num = ep_addr & 0x7FU; + usb_ep_struct *ep = &pudev->in_ep[ep_num]; + + /* configure the transaction level parameters */ + ep->trs_buf = pbuf; + ep->trs_len = buf_len; + ep->trs_count = 0U; + + /* transmit length is more than one packet */ + if (ep->trs_len > ep->maxpacket) { + len = ep->maxpacket; + } else { + len = ep->trs_len; + } + + usbd_ep_data_write(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, (uint16_t)len); + (pbuf_reg + ep_num)->tx_count = (uint16_t)len; + + /* enable endpoint to transmit */ + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); +} + +/*! + \brief set an endpoint to stall status + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint8_t ep_num = ep_addr & 0x7FU; + usb_ep_struct *ep; + + if (ep_addr >> 7U) { + ep = &pudev->in_ep[ep_num]; + + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_STALL); + } else { + ep = &pudev->out_ep[ep_num]; + + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_STALL); + } + + ep->stall = 1U; + + if (0U == ep_num) { + /* control endpoint need to be stalled in two directions */ + USBD_ENDP_RX_TX_STATUS_SET(ep_num, EPRX_STALL, EPTX_STALL); + } +} + +/*! + \brief clear endpoint stalled status + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint8_t ep_num = ep_addr & 0x7FU; + usb_ep_struct *ep; + + if (ep_addr >> 7U) { + ep = &pudev->in_ep[ep_num]; + + /* clear endpoint data toggle bit */ + USBD_DTG_TX_CLEAR(ep_num); + + /* clear endpoint stall status */ + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); + } else { + ep = &pudev->out_ep[ep_num]; + + /* clear endpoint data toggle bit */ + USBD_DTG_RX_CLEAR(ep_num); + + /* clear endpoint stall status */ + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); + } + + ep->stall = 0U; +} + +/*! + \brief get the endpoint status + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval endpoint status +*/ +uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr) +{ + if (ep_addr >> 7U) { + return (uint8_t)USBD_ENDP_TX_STATUS_GET((ep_addr & 0x7FU)); + } else { + return (uint8_t)USBD_ENDP_RX_STATUS_GET(ep_addr); + } +} + +/*! + \brief write datas from user fifo to USBRAM + \param[in] user_fifo: pointer to user fifo + \param[in] usbram_addr: the allocation buffer address of the endpoint + \param[in] bytes: the bytes count of the write datas + \param[out] none + \retval none +*/ +void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) +{ + uint32_t n; + uint32_t *write_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); + + for (n = 0U; n < (bytes + 1U) / 2U; n++) { + *write_addr++ = *((__packed uint16_t*)user_fifo); + user_fifo += 2U; + } +} + +/*! + \brief read datas from USBRAM to user fifo + \param[in] user_fifo: pointer to user fifo + \param[in] usbram_addr: the allocation buffer address of the endpoint + \param[in] bytes: the bytes count of the read datas + \param[out] none + \retval none +*/ +void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) +{ + uint32_t n; + uint32_t *read_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); + + for (n = 0U; n < (bytes + 1U) / 2U; n++) { + *((__packed uint16_t*)user_fifo) = (uint16_t)*read_addr++; + user_fifo += 2U; + } +} + +/*! + \brief get the received data length + \param[in] pudev: pointer to USB core instance + \param[in] ep_num: endpoint identifier which is in (0..7) + \param[out] none + \retval received data length +*/ +uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num) +{ + return (uint16_t)pudev->out_ep[ep_num].trs_count; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c new file mode 100644 index 0000000000..f9e58fe3d9 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c @@ -0,0 +1,458 @@ +/*! + \file usbd_int.c + \brief USB device power interrupt routines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_int.h" + +extern uint32_t g_interrupt_mask; +extern __IO uint8_t g_suspend_enabled; +extern __IO uint8_t g_remote_wakeup_on; +extern __IO uint8_t g_ESOF_count; + +#ifdef LPM_ENABLED +__IO uint32_t L1_remote_wakeup = 0U; +__IO uint32_t L1_resume = 0U; +__IO uint32_t besl = 0U; +#endif /* LPM_ENABLED */ + +static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev); + +/*! + \brief USB interrupt events service routine + \param[in] none + \param[out] none + \retval none +*/ +void usbd_isr (void) +{ + __IO uint16_t interrupt_flag = 0U; + __IO uint16_t ctlr = 0U; + + interrupt_flag = USBD_REG_GET(USBD_INTF); + + if (g_interrupt_mask & INTF_STIF & interrupt_flag) { + /* the endpoint successful transfer interrupt service */ + usbd_intf_lpst(&usb_device_dev); + } + + if (g_interrupt_mask & INTF_WKUPIF & interrupt_flag) { + /* clear wakeup interrupt flag in INTF */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_WKUPIF); + + /* USB wakeup interrupt handle */ + usbd_intf_wakeup(&usb_device_dev); + +#ifdef LPM_ENABLED + /* clear L1 remote wakeup flag */ + L1_remote_wakeup = 0; +#endif /* LPM_ENABLED */ + } + + if (g_interrupt_mask & INTF_SPSIF & interrupt_flag) { + if(!(USBD_REG_GET(USBD_CTL) & CTL_RSREQ)) { + /* process library core layer suspend routine*/ + usbd_intf_suspend(&usb_device_dev); + + /* clear of suspend interrupt flag bit must be done after setting of CTLR_SETSPS */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SPSIF); + } + } + + if (g_interrupt_mask & INTF_SOFIF & interrupt_flag) { + /* clear SOF interrupt flag in INTF */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SOFIF); + + /* USB SOF interrupt handle */ + usbd_intf_sof(&usb_device_dev); + } + + if (g_interrupt_mask & INTF_ESOFIF & interrupt_flag) { + /* clear ESOF interrupt flag in INTF */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_ESOFIF); + + /* USB ESOF interrupt handle */ + usbd_intf_esof(&usb_device_dev); + } + + if (g_interrupt_mask & INTF_RSTIF & interrupt_flag) { + /* clear reset interrupt flag in INTF */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_RSTIF); + + /* USB reset interrupt handle */ + usbd_intf_reset(&usb_device_dev); + } + +#ifdef LPM_ENABLED + if (g_interrupt_mask & INTF_L1REQ & interrupt_flag) { + /* clear L1 ST bit in LPM INTF */ + USBD_REG_SET(USBD_INTF, CLR_L1REQ); + + /* read BESL field from subendpoint0 register which coressponds to HIRD parameter in LPM spec */ + besl = (USBD_REG_GET(USBD_LPMCS) & LPMCS_BLSTAT) >> 4; + + /* read BREMOTEWAKE bit from subendpoint0 register which corresponding to bRemoteWake bit in LPM request */ + L1_remote_wakeup = (USBD_REG_GET(USBD_LPMCS) & LPMCS_REMWK) >> 8; + + /* process USB device core layer suspend routine */ + /* enter USB model in suspend and system in low power mode (DEEP_SLEEP mode) */ + usbd_intf_suspend(&usb_device_dev); + } +#endif /* LPM_ENABLED */ +} + +/*! + \brief handle USB high priority successful transfer event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev) +{ + uint8_t ep_num = 0U; + + __IO uint16_t int_status = 0U; + __IO uint16_t ep_value = 0U; + + usb_ep_struct *ep = NULL; + + /* wait till interrupts are not pending */ + while (0U != ((int_status = USBD_INTF) & (uint16_t)INTF_STIF)) { + /* get endpoint number and the value of control and state register */ + ep_num = (uint8_t)(int_status & INTF_EPNUM); + ep_value = USBD_EPxCS(ep_num); + + if (0U == (int_status & INTF_DIR)) { + /* handle the in direction transaction */ + + ep = &(pudev->in_ep[ep_num]); + + if (0U != (ep_value & EPxCS_TX_ST)) { + /* clear successful transmit interrupt flag */ + USBD_ENDP_TX_STAT_CLEAR(ep_num); + + if (ep_value & EPxCS_TX_DTG) { + /* just handle single buffer situation */ + ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; + } + + /* maybe mutiple packets */ + ep->trs_buf += ep->trs_count; + + usbd_in_transaction(pudev, ep_num); + } + } else { + /* handle the out direction transaction */ + + uint16_t count = 0U; + + ep = &(pudev->out_ep[ep_num]); + + if (0U != (ep_value & EPxCS_RX_ST)) { + /* clear successful receive interrupt flag */ + USBD_ENDP_RX_STAT_CLEAR(ep_num); + + if (ep_value & EPxCS_TX_DTG) { + count = (pbuf_reg + ep_num)->tx_count & (uint16_t)EPRCNT_CNT; + + if (0U != count) { + usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, count); + } + } else { + count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; + + if (0U != count) { + usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); + } + } + + user_buffer_free(ep_num, DBUF_EP_OUT); + + /* maybe mutiple packets */ + ep->trs_count += count; + ep->trs_buf += count; + ep->trs_len -= count; + + if ((0U == ep->trs_len) || (count < ep->maxpacket)) { + USBD_ENDP_TX_STATUS_SET(ep_num, EPRX_NAK); + + /* enter data OUT status */ + usbd_out_transaction(pudev, ep_num); + + ep->trs_count = 0U; + } + } + } + } + + return USBD_OK; +} + +/*! + \brief handle USB low priority successful transfer event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev) +{ + uint8_t ep_num = 0U; + + __IO uint16_t int_status = 0U; + __IO uint16_t ep_value = 0U; + + usb_ep_struct *ep = NULL; + + /* wait till interrupts are not pending */ + while (0U != ((int_status = USBD_REG_GET(USBD_INTF)) & (uint16_t)INTF_STIF)) { + /* get endpoint number and the value of control and state register */ + ep_num = (uint8_t)(int_status & INTF_EPNUM); + ep_value = USBD_REG_GET(USBD_EPxCS(ep_num)); + + if (0U == (int_status & INTF_DIR)) { + /* handle the in direction transaction */ + + ep = &(pudev->in_ep[ep_num]); + + if (0U != (ep_value & EPxCS_TX_ST)) { + /* clear successful transmit interrupt flag */ + USBD_ENDP_TX_STAT_CLEAR(ep_num); + + /* just handle single buffer situation */ + ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; + + /* maybe mutiple packets */ + ep->trs_buf += ep->trs_count; + + usbd_in_transaction(pudev, ep_num); + } + } else { + /* handle the out direction transaction */ + + uint16_t count = 0U; + + ep = &(pudev->out_ep[ep_num]); + + if (0U != (ep_value & EPxCS_RX_ST)) { + /* clear successful receive interrupt flag */ + USBD_ENDP_RX_STAT_CLEAR(ep_num); + + count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; + + if (0U != count) { + if (0U != (ep_value & EPxCS_SETUP)) { + /* handle setup packet */ + usbd_ep_data_read(&(pudev->setup_packet[0]), pbuf_reg->rx_addr, count); + + /* enter setup status */ + usbd_setup_transaction(pudev); + + return USBD_OK; + } else { + usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); + } + } + + /* maybe mutiple packets */ + ep->trs_count += count; + ep->trs_buf += count; + ep->trs_len -= count; + + if ((0U == ep->trs_len) || (count < ep->maxpacket)) { + /* enter data OUT status */ + usbd_out_transaction(pudev, ep_num); + + ep->trs_count = 0U; + } else { + usbd_ep_rx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); + } + } + } + } + + return USBD_OK; +} + +/*! + \brief handle USB SOF event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev) +{ + /* if necessary, user can add code here */ + if (NULL != usbd_int_fops) { + usbd_int_fops->SOF(pudev); + } + + return USBD_OK; +} + +/*! + \brief handle USB expect SOF event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev) +{ + /* control resume time by ESOFs */ + if (g_ESOF_count > 0U) { + g_ESOF_count--; + + if (0U == g_ESOF_count) { + if (1U == g_remote_wakeup_on) { + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_RSREQ); + + g_remote_wakeup_on = 0U; + } else { + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); + + g_ESOF_count = 3U; + g_remote_wakeup_on = 1U; + } + } + } + + return USBD_OK; +} + +/*! + \brief handle USB reset event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev) +{ + uint8_t i; + + g_free_buf_addr = ENDP_BUF_ADDR; + + /* configure endpoint 0 buffer */ + pbuf_reg->tx_addr = (uint16_t)g_free_buf_addr; + g_free_buf_addr += USBD_EP0_MAX_SIZE; + + pbuf_reg->rx_addr = (uint16_t)g_free_buf_addr; + g_free_buf_addr += USBD_EP0_MAX_SIZE; + + /* configure endpoint 0 Rx count */ + if (USBD_EP0_MAX_SIZE > 62U) { + pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE << 5U) - 1U) | 0x8000U; + } else { + pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE + 1U) & ~1U) << 9U; + } + + pudev->in_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; + pudev->out_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; + + /* set endpoints address */ + for (i = 0U; i < EP_COUNT; i++) + { + _EP_ADDR_SET(i, i); + } + + /* set device address as default address 0 */ + USBD_REG_SET(USBD_DADDR, DADDR_USBEN); + + /* clear endpoint 0 register */ + USBD_REG_SET(USBD_EPxCS(EP0), USBD_EPxCS(EP0)); + + USBD_REG_SET(USBD_EPxCS(EP0), EP_CONTROL | EPRX_VALID | EPTX_NAK); + + pudev->status = USBD_DEFAULT; + + return USBD_OK; +} + +/*! + \brief handle USB suspend event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev) +{ + /* store the device current status */ + pudev->prev_status = pudev->status; + + /* set device in suspended state */ + pudev->status = USBD_SUSPENDED; + + /* enter USB in suspend and mcu system in low power mode */ + if (g_suspend_enabled) { + usbd_suspend(); + } else { + /* if not possible then resume after xx ms */ + g_ESOF_count = 3U; + } + + return USBD_OK; +} + +/*! + \brief handle USB wakeup event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev) +{ + /* restore the old status */ + pudev->status = pudev->prev_status; + +#ifdef LPM_ENABLED + if ((0U == g_remote_wakeup_on) && (0U == L1_resume)) { + resume_mcu(); + } else if (1U == g_remote_wakeup_on) { + /* no operation */ + } else { + L1_resume = 0U; + } +#else + if (0U == g_remote_wakeup_on) { + resume_mcu(); + } +#endif /* LPM_ENABLED */ + + return USBD_OK; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c new file mode 100644 index 0000000000..febdd765f4 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c @@ -0,0 +1,159 @@ +/*! + \file usbd_pwr.c + \brief USB device power management driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_pwr.h" + +#ifdef USBD_LOWPWR_MODE_ENABLE +static void lowpower_mode_exit (void); +#endif /* USBD_LOWPWR_MODE_ENABLE */ + +__IO uint8_t g_ESOF_count = 0U; +__IO uint8_t g_suspend_enabled = 1U; +__IO uint8_t g_remote_wakeup_on = 0U; + +#ifdef LPM_ENABLED +extern __IO uint32_t L1_resume; +#endif /* LPM_ENABLED */ + +/*! + \brief USB wakeup first operation is to wakeup mcu + \param[in] none + \param[out] none + \retval none +*/ +void resume_mcu (void) +{ + /* clear low_power mode bit in USBD_CTL */ + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM)); + +#ifdef USBD_LOWPWR_MODE_ENABLE + + /* restore normal operations */ + lowpower_mode_exit(); + +#endif /* USBD_LOWPWR_MODE_ENABLE */ + + /* clear SETSPS bit */ + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS)); +} + +#ifdef USBD_LOWPWR_MODE_ENABLE + +/*! + \brief restore system clocks and power while exiting suspend mode + \param[in] none + \param[out] none + \retval none +*/ +static void lowpower_mode_exit (void) +{ + /* restore system clock */ + + /* enable HSE */ + rcu_osci_on(RCU_HXTAL); + + /* wait till HSE is ready */ + while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB)); + + /* enable PLL */ + rcu_osci_on(RCU_PLL_CK); + + /* wait till PLL is ready */ + while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB)); + + /* select PLL as system clock source */ + rcu_system_clock_source_config(RCU_CKSYSSRC_PLL); + + /* wait till PLL is used as system clock source */ + while(0x08 != rcu_system_clock_source_get()); + + /* low power sleep on exit disabled */ + system_lowpower_reset(SCB_LPM_DEEPSLEEP); +} + +#endif /* USBD_LOWPWR_MODE_ENABLE */ + +/*! + \brief set USB device to suspend mode + \param[in] none + \param[out] none + \retval none +*/ +void usbd_suspend (void) +{ + /* set usb module to suspend and low-power mode */ + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM); + +#ifdef USBD_LOWPWR_MODE_ENABLE + + /* check wakeup flag is set */ + if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) { + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + } else { + /* clear wakeup interrupt flag */ + USBD_REG_SET(USBD_INTF, CLR_WKUPIF); + + /* clear set_suspend flag */ + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS); + } + +#endif /* USBD_LOWPWR_MODE_ENABLE */ +} + +/*! + \brief start to remote wakeup + \param[in] none + \param[out] none + \retval none +*/ +void usbd_remote_wakeup_active(void) +{ + resume_mcu(); + +#ifdef LPM_ENABLED + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ); + + L1_resume = 1U; +#else + g_remote_wakeup_on = 1U; + + g_ESOF_count = 15U; + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); +#endif /* LPM_ENABLED */ +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c new file mode 100644 index 0000000000..582d614fac --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c @@ -0,0 +1,868 @@ +/*! + \file usbd_std.c + \brief USB device stand routines + \note about USB standard, please refer to the USB2.0 protocol + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_std.h" + +uint8_t g_device_address = 0U; + +/* USB enumeration handle functions */ +static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req); + +static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, + uint8_t index, + uint16_t *pLen); + +static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, + uint8_t index, + uint16_t *pLen); + +static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, + uint8_t index, + uint16_t *pLen); + +#ifdef LPM_ENABLED +static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen); +#endif /* LPM_ENABLED */ + +/* standard device request handler */ +static void (*standard_device_request[])(usbd_core_handle_struct *pudev, usb_device_req_struct *req) = +{ + usbd_getstatus, + usbd_clearfeature, + usbd_reserved, + usbd_setfeature, + usbd_reserved, + usbd_setaddress, + usbd_getdescriptor, + usbd_setdescriptor, + usbd_getconfiguration, + usbd_setconfiguration, + usbd_getinterface, + usbd_setinterface, + usbd_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t* (*standard_descriptor_get[])(usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = +{ + usbd_device_descriptor_get, + usbd_configuration_descriptor_get, + usbd_string_descriptor_get +}; + +/*! + \brief USB setup stage processing + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev) +{ + usb_device_req_struct req; + + usbd_setup_request_parse (pudev, &req); + + switch (req.bmRequestType & USB_REQ_MASK) { + /* standard device request */ + case USB_STANDARD_REQ: + usbd_standard_request(pudev, &req); + break; + /* device class request */ + case USB_CLASS_REQ: + usbd_device_class_request(pudev, &req); + break; + /* vendor defined request */ + case USB_VENDOR_REQ: + usbd_vendor_request(pudev, &req); + break; + default: + usbd_ep_stall(pudev, 0x00U); + break; + } + return USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) +{ + usb_ep_struct *ep = &pudev->out_ep[ep_num]; + + if (0U == ep_num) { + if (0U != pudev->ctl_count) { + if (ep->trs_len > ep->maxpacket) { + /* one data packet has been received, update trs_len */ + ep->trs_len -= ep->maxpacket; + + /* continue to receive remain data */ + usbd_ep_rx(pudev, EP0_OUT, ep->trs_buf, (uint16_t)ep->trs_len); + } else { + if (USBD_CONFIGURED == pudev->status) { + /* device class handle */ + pudev->class_data_handler(pudev, USBD_RX, EP0); + } + + /* enter the control transaction status stage */ + USBD_CONTRL_STATUS_TX(); + + pudev->ctl_count = 0U; + } + } else { + /* clear endpoint status_out status */ + USBD_STATUS_OUT_CLEAR(EP0); + } + } else { + if (USBD_CONFIGURED == pudev->status) { + pudev->class_data_handler(pudev, USBD_RX, ep_num); + } + } + return USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) +{ + usb_ep_struct *ep = &pudev->in_ep[ep_num]; + + if (0U == ep_num) { + if (0U != pudev->ctl_count) { + if (ep->trs_len > ep->maxpacket) { + /* one data packet has been transmited, update trs_len */ + ep->trs_len -= ep->maxpacket; + + /* continue to transmit remain data */ + usbd_ep_tx (pudev, EP0_IN, ep->trs_buf, (uint16_t)ep->trs_len); + + usbd_ep_rx (pudev, 0U, NULL, 0U); + } else { +#ifndef USB_DFU + /* transmit length is maxpacket multiple, so send zero length packet */ + if ((0U == (ep->trs_len % ep->maxpacket)) && (ep->trs_len < pudev->ctl_count)) { + usbd_ep_tx (pudev, EP0_IN, NULL, 0U); + + pudev->ctl_count = 0U; + + usbd_ep_rx (pudev, 0U, NULL, 0U); + } else +#endif /* USB_DFU */ + { + ep->trs_len = 0U; + + if (USBD_CONFIGURED == pudev->status) { + pudev->class_data_handler(pudev, USBD_TX, EP0); + } + + USBD_CONTRL_STATUS_RX(); + + pudev->ctl_count = 0U; + } + } + } else { + if (0U != g_device_address) { + USBD_REG_SET(USBD_DADDR, DADDR_USBEN | g_device_address); + g_device_address = 0U; + } + } + } else { + ep->trs_len -= ep->trs_count; + + if (0U == ep->trs_len) { + if (USBD_CONFIGURED == pudev->status) { + pudev->class_data_handler(pudev, USBD_TX, ep_num); + } + } else { + usbd_ep_tx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); + } + } + + return USBD_OK; +} + +/*! + \brief handle USB standard device request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* call device request handle function */ + (*standard_device_request[req->bRequest])(pudev, req); + + return USBD_OK; +} + +/*! + \brief handle USB device class request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + usbd_status_enum ret; + + switch (pudev->status) { + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* call device class handle function */ + ret = (usbd_status_enum)(pudev->class_req_handler(pudev, req)); + + if ((0U == req->wLength) && (USBD_OK == ret)) { + /* no data stage */ + USBD_CONTRL_STATUS_TX(); + } + } else { + usbd_enum_error(pudev, req); + } + break; + default: + usbd_enum_error(pudev, req); + break; + } + + return USBD_OK; +} + +/*! + \brief handle USB vendor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* added by user */ + + return USBD_OK; +} + +/*! + \brief no operation, just for reserved + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no operation */ +} + +#ifdef LPM_ENABLED +/*! + \brief get BOS descriptor + \param[in] pudev: pointer to USB device instance + \param[in] pLen: data length pointer + \param[out] none + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen) +{ + *pLen = pudev->bos_desc[2] | ((uint16_t)pudev->bos_desc[3] << 8); + + return pudev->bos_desc; +} + +#endif /* LPM_ENABLED */ + +/*! + \brief get the device descriptor + \param[in] pudev: pointer to USB device instance + \param[in] index: no use + \param[out] pLen: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + *pLen = pudev->dev_desc[0]; + + return pudev->dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] pudev: pointer to USB device instance + \brief[in] index: no use + \param[out] pLen: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + *pLen = pudev->config_desc[2]; + + return pudev->config_desc; +} + +/*! + \brief get string descriptor + \param[in] pudev: pointer to USB device instance + \param[in] index: string descriptor index + \param[out] pLen: pointer to string length + \retval none +*/ +static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + uint8_t *desc = pudev->strings[index]; + + *pLen = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr; + uint16_t config_status = 0x0000U; + uint16_t endp_status = 0x0000U; + + switch(req->bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQTYPE_DEVICE: + switch (pudev->status) { + case USBD_ADDRESSED: + case USBD_CONFIGURED: + +#ifdef USBD_SELF_POWERED + config_status = USB_STATUS_SELF_POWERED; +#endif /* USBD_SELF_POWERED */ + + if (pudev->remote_wakeup) { + config_status |= USB_STATUS_REMOTE_WAKEUP; + } + + usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); + break; + default: + break; + } + break; + case USB_REQTYPE_INTERFACE: + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + case USB_REQTYPE_ENDPOINT: + /* get enndpoint address */ + ep_addr = LOWBYTE(req->wIndex); + + switch (pudev->status) { + case USBD_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_enum_error(pudev, req); + } + break; + case USBD_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) { + if(pudev->in_ep[ep_addr & 0x7FU].stall) { + endp_status = 0x0001U; + } + } else { + if (pudev->out_ep[ep_addr].stall) { + endp_status = 0x0001U; + } + } + usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&endp_status, 2U); + break; + + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Clear_Feature request + \param[in] pudev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval none +*/ +static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr = 0U; + + switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQTYPE_DEVICE: + switch (pudev->status) { + case USBD_ADDRESSED: + case USBD_CONFIGURED: + /* clear device remote wakeup feature */ + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + pudev->remote_wakeup = 0U; + pudev->class_req_handler(pudev, req); + USBD_CONTRL_STATUS_TX(); + } else if (USB_FEATURE_TEST_MODE == req->wValue) { + /* can not clear test_mode feature */ + usbd_enum_error(pudev, req); + } else { + /* no operation */ + } + break; + default: + break; + } + break; + case USB_REQTYPE_INTERFACE: + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error (pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* no operation */ + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + case USB_REQTYPE_ENDPOINT: + /* get endpoint address */ + ep_addr = LOWBYTE(req->wIndex); + + switch (pudev->status) { + case USBD_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_enum_error(pudev, req); + } + break; + case USBD_CONFIGURED: + /* clear endpoint halt feature */ + if (USB_FEATURE_ENDP_HALT == req->wValue) { + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_clear_stall(pudev, ep_addr); + } + } + + pudev->class_req_handler(pudev, req); + + USBD_CONTRL_STATUS_TX(); + break; + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Set_Feature request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr = 0U; + + switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQTYPE_DEVICE: + switch (pudev->status) { + case USBD_ADDRESSED: + case USBD_CONFIGURED: + /* set device remote wakeup feature */ + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + pudev->remote_wakeup = 1U; + + USBD_CONTRL_STATUS_TX(); + } + break; + default: + break; + } + break; + case USB_REQTYPE_INTERFACE: + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* no operation */ + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + case USB_REQTYPE_ENDPOINT: + /* get endpoint address */ + ep_addr = LOWBYTE(req->wIndex); + + switch (pudev->status) { + case USBD_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_enum_error(pudev, req); + } + break; + case USBD_CONFIGURED: + /* set endpoint halt feature */ + if (USB_FEATURE_ENDP_HALT == req->wValue) { + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_stall(pudev, ep_addr); + } + } + USBD_CONTRL_STATUS_TX(); + break; + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Set_Address request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + if ((0U == req->wIndex) && (0U == req->wLength)) { + g_device_address = (uint8_t)(req->wValue) & 0x7FU; + + if (USBD_CONFIGURED == pudev->status) { + usbd_enum_error(pudev, req); + } else { + USBD_CONTRL_STATUS_TX(); + + if (0U != g_device_address) { + pudev->status = USBD_ADDRESSED; + } else { + pudev->status = USBD_DEFAULT; + } + } + } else { + usbd_enum_error(pudev, req); + } +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { + uint8_t *pbuf = NULL; + uint8_t desc_type = (uint8_t)(req->wValue >> 8); + uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; + uint16_t len = 0U; + + if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { + /* call corresponding descriptor get function */ + pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); + } +#ifdef LPM_ENABLED + else if (USB_DESCTYPE_BOS == desc_type) { + pbuf = usbd_bos_descriptor_get(pudev, &len); + } +#endif /* LPM_ENABLED */ + else { + usbd_enum_error(pudev, req); + } + + if ((0U != len) && (0U != req->wLength)) { + len = MIN(len, req->wLength); + + usbd_ep_tx (pudev, EP0_IN, pbuf, len); + } + } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { + if (NULL != pudev->class_req_handler) { + /* get device class special descriptor */ + pudev->class_req_handler(pudev, req); + } + } else { + + } +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no handle */ +} + +/*! + \brief handle USB Get_Configuration request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint32_t usbd_default_config = 0U; + + if (req->wLength != 1U) { + usbd_enum_error(pudev, req); + } else { + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_ep_tx (pudev, EP0_IN, (uint8_t *)&usbd_default_config, 1U); + break; + case USBD_CONFIGURED: + usbd_ep_tx (pudev, EP0_IN, &pudev->config_num, 1U); + break; + default: + usbd_enum_error(pudev, req); + break; + } + } +} + +/*! + \brief handle USB Set_Configuration request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_CFG_MAX_NUM) { + usbd_enum_error(pudev, req); + } else { + switch (pudev->status) { + case USBD_ADDRESSED: + if (cfgidx){ + pudev->config_num = cfgidx; + pudev->status = USBD_CONFIGURED; + pudev->class_init(pudev, cfgidx); + USBD_CONTRL_STATUS_TX(); + } else { + USBD_CONTRL_STATUS_TX(); + } + break; + case USBD_CONFIGURED: + if (0U == cfgidx) { + pudev->status = USBD_ADDRESSED; + pudev->config_num = cfgidx; + pudev->class_deinit(pudev, cfgidx); + USBD_CONTRL_STATUS_TX(); + } else if (cfgidx != pudev->config_num) { + /* clear old configuration */ + pudev->class_deinit(pudev, pudev->config_num); + + /* set new configuration */ + pudev->config_num = cfgidx; + pudev->class_init(pudev, cfgidx); + USBD_CONTRL_STATUS_TX(); + } else { + USBD_CONTRL_STATUS_TX(); + } + break; + default: + break; + } + } +} + +/*! + \brief handle USB Get_Interface request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + if (NULL != pudev->class_req_handler) { + pudev->class_req_handler(pudev, req); + } + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } +} + +/*! + \brief handle USB Set_Interface request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + if (NULL != pudev->class_req_handler) { + pudev->class_req_handler(pudev, req); + } + + USBD_CONTRL_STATUS_TX(); + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } +} + +/*! + \brief handle USB SynchFrame request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no handle */ +} + +/*! + \brief decode setup data packet + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t *setup_data = pudev->setup_packet; + + req->bmRequestType = *setup_data; + req->bRequest = *(uint8_t *)(setup_data + 1U); + req->wValue = SWAPBYTE (setup_data + 2U); + req->wIndex = SWAPBYTE (setup_data + 4U); + req->wLength = SWAPBYTE (setup_data + 6U); + + pudev->ctl_count = req->wLength; +} + +/*! + \brief handle USB enumeration error event + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + usbd_ep_stall(pudev, EP0); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h new file mode 100644 index 0000000000..b50f903086 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h @@ -0,0 +1,304 @@ +/*! + \file usb_core.h + \brief USB core driver header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USB_CORE_H +#define USB_CORE_H + +#include "usb_conf.h" +#include "usb_regs.h" +#include "usb_defines.h" + +/* constants definitions */ +#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */ +#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */ +#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */ + +#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT +#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) + +/* USB core status */ +typedef enum +{ + USB_OK = 0, /* USB core OK status */ + USB_FAIL /* USB core fail status */ +}usb_status_enum; + +/* USB host channel status */ +typedef enum +{ + HC_IDLE = 0, /* USB host channel idle status */ + HC_XF, /* USB host channel transfer status */ + HC_HALTED, /* USB host channel halted status */ + HC_NAK, /* USB host channel nak status */ + HC_NYET, /* USB host channel nyet status */ + HC_STALL, /* USB host channel stall status */ + HC_TRACERR, /* USB host channel tracerr status */ + HC_BBERR, /* USB host channel bberr status */ + HC_DTGERR, /* USB host channel dtgerr status */ +}hc_status_enum; + +/* USB URB(USB request block) state */ +typedef enum +{ + URB_IDLE = 0, /* USB URB idle status */ + URB_DONE, /* USB URB done status */ + URB_NOTREADY, /* USB URB not ready status */ + URB_ERROR, /* USB URB error status */ + URB_STALL, /* USB URB stall status */ + URB_PING /* USB URB ping status */ +}urb_state_enum; + +/* USB core configuration */ +typedef struct +{ + uint8_t core_id; /* USB core id */ + uint8_t core_speed; /* USB core speed */ + uint8_t phy_interface; /* USB PHY interface */ + uint8_t host_channel_num; /* USB host channel number */ + uint8_t dev_endp_num; /* USB device endpoint number */ + uint8_t sof_output; /* USB SOF output */ + uint8_t low_power; /* USB low power */ + uint16_t max_packet_size; /* USB max packet size */ + uint16_t max_fifo_size; /* USB fifo size */ +}usb_core_cfgs_struct; + +typedef enum +{ + USBD_OK = 0, /* USB device ok status */ + USBD_BUSY, /* USB device busy status */ + USBD_FAIL, /* USB device fail stauts */ +}usbd_status_enum; + +/* USB control transfer state */ +typedef enum +{ + USB_CTRL_IDLE = 0, /* USB control transfer idle state */ + USB_CTRL_SETUP, /* USB control transfer setup state */ + USB_CTRL_DATA_IN, /* USB control transfer data in state */ + USB_CTRL_DATA_OUT, /* USB control transfer data out state */ + USB_CTRL_STATUS_IN, /* USB control transfer status in state*/ + USB_CTRL_STATUS_OUT, /* USB control transfer status out state */ + USB_CTRL_STALL /* USB control transfer stall state */ +}usbd_control_state_enum; + +/* USB transfer direction */ +typedef enum +{ + USB_RX = 0, /* receive direction type value */ + USB_TX /* transmit direction type value */ +}usb_dir_enum; + +/* USB endpoint in device mode */ +typedef struct +{ + uint8_t endp_type; /* USB endpoint type */ + uint8_t endp_frame; /* USB endpoint frame */ + uint32_t endp_mps; /* USB endpoint max packet size */ + + /* Transaction level variables */ + uint8_t *xfer_buff; /* USB transfer buffer */ + uint32_t xfer_len; /* USB transfer length */ + uint32_t xfer_count; /* USB transfer count */ + + uint32_t dma_addr; /* USBHS can use DMA */ +}usb_ep_struct; + +/* USB device standard request */ +typedef struct +{ + uint8_t bmRequestType; /* USB device request type */ + uint8_t bRequest; /* USB device request */ + uint16_t wValue; /* USB device request value */ + uint16_t wIndex; /* USB device request index */ + uint16_t wLength; /* USB device request length */ +}usb_device_req_struct; + +/* USB core device driver */ +typedef struct +{ + uint8_t config_num; /* USB configuration number */ + __IO uint8_t status; /* USB status */ + uint8_t ctl_status; /* USB control status */ + uint8_t prev_status; /* USB previous status */ + uint8_t connection_status; /* USB connection status */ + uint32_t remote_wakeup; /* USB remote wakeup */ + + /* transfer level variables */ + uint32_t remain_len; /* USB remain length */ + uint32_t sum_len; /* USB sum length */ + uint32_t ctl_len; /* USB control length */ + uint8_t setup_packet[8 * 3]; /* USB setup packet */ + + usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB in endpoint */ + usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB out endpoint */ + + uint8_t *dev_desc; /* device descriptor */ + uint8_t *config_desc; /* configuration descriptor */ + uint8_t* *strings; /* configuration strings */ + + /* device class handler */ + uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */ + uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */ + uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */ + uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */ +}dcd_dev_struct; + +/* USB core host mode channel */ +typedef struct +{ + uint8_t dev_addr; /* device address */ + uint8_t dev_speed; /* device speed */ + uint8_t DPID; /* endpoint transfer data pid */ + uint8_t endp_id; /* endpoint number */ + uint8_t endp_in; /* endpoint in */ + uint8_t endp_type; /* endpoint type */ + uint16_t endp_mps; /* endpoint max pactet size */ + uint16_t info; /* channel information */ + + uint8_t *xfer_buff; /* transfer buffer */ + uint32_t xfer_len; /* transfer length */ + uint32_t xfer_count; /* trasnfer count */ + + uint32_t err_count; /* USB transfer error count */ + + hc_status_enum status; /* channel status */ + urb_state_enum urb_state; /* URB state */ + + uint8_t data_tg_in; /* data in toggle */ + uint8_t data_tg_out; /* data out toggle */ +}usb_hostchannel_struct; + +/* USB core host driver */ +typedef struct +{ + uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */ + uint8_t connect_status; /* device connect status */ + usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */ + void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */ +}hcd_dev_struct; + +#ifdef USE_OTG_MODE + +/* USB core OTG-mode driver */ +typedef struct +{ + uint8_t OTG_State; /* OTG state */ + uint8_t OTG_PrevState; /* OTG previous state */ + uint8_t OTG_Mode; /* OTG mode */ +}otg_dev_struct; + +#endif /* USE_OTG_MODE */ + +/* USB core driver */ +typedef struct +{ + usb_core_cfgs_struct cfg; + +#ifdef USE_DEVICE_MODE + dcd_dev_struct dev; +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + hcd_dev_struct host; +#endif /* USE_HOST_MODE */ + +#ifdef USE_OTG_MODE + otg_dev_struct otg; +#endif /* USE_OTG_MODE */ + + void (*udelay) (const uint32_t usec); + void (*mdelay) (const uint32_t msec); +}usb_core_handle_struct; + +/* function declarations */ + +/* global APIs */ +/* initializes the USB controller registers and prepares the core device mode or host mode operation */ +usb_status_enum usb_core_init (usb_core_handle_struct *pudev); +/* initialize core parameters */ +usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id); +/* read a packet from the rx fifo associated with the endpoint */ +void* usb_fifo_read (uint8_t *dest, uint16_t len); +/* write a packet into the tx fifo associated with the endpoint */ +usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len); +/* flush a tx fifo or all tx fifos */ +usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num); +/* flush the entire rx fifo */ +usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev); +/* set operation mode (host or device) */ +usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode); + +/* host APIs */ +#ifdef USE_HOST_MODE + +/* initializes USB core for host mode */ +usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev); +/* enables the host mode interrupts */ +usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev); +/* initialize host channel */ +usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num); +/* halt channel */ +usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num); +/* prepare host channel for transferring packets */ +usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num); +/* reset host port */ +uint32_t usb_port_reset (usb_core_handle_struct *pudev); +/* control the VBUS to power */ +void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state); +/* stop the USB host and clean up fifos */ +void usb_host_stop (usb_core_handle_struct *pudev); + +#endif /* USE_HOST_MODE */ + +/* device APIs */ +#ifdef USE_DEVICE_MODE + +/* initialize USB core registers for device mode */ +usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev); +/* configures endpoint 0 to receive setup packets */ +void usb_ep0_startout (usb_core_handle_struct *pudev); +/* active remote wakeup signalling */ +void usb_remotewakeup_active (usb_core_handle_struct *pudev); +/* active USB core clock */ +void usb_clock_ungate (usb_core_handle_struct *pudev); +/* stop the device and clean up fifos */ +void usb_device_stop (usb_core_handle_struct *pudev); + +#endif /* USE_DEVICE_MODE */ + +#endif /* USB_CORE_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h new file mode 100644 index 0000000000..d9d1fd3c04 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h @@ -0,0 +1,128 @@ +/*! + \file usb_defines.h + \brief USB core defines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USB_DEFINES_H +#define USB_DEFINES_H + +#include "usb_conf.h" + +/* constants definitions */ +typedef enum +{ + USB_HS_CORE_ID = 0, + USB_FS_CORE_ID = 1 +}usb_core_id_enum; + +typedef enum +{ + USB_SPEED_UNKNOWN = 0, + USB_SPEED_LOW, + USB_SPEED_FULL, + USB_SPEED_HIGH +}usb_speed_enum; + +#ifndef NULL + #define NULL (void *)0 /*!< USB null marco value*/ +#endif /* NULL */ + +#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */ +#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */ + +#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */ +#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */ +#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */ +#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */ + +#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */ +#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */ +#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */ +#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */ + +#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */ +#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */ + +#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ +#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ + +#define GRSTATR_RPCKST_IN 2U /* in data packet received */ +#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* in transfer completed (generates an interrupt if poped) */ +#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */ +#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */ + +#define DEVICE_MODE 0U /* USB core in device mode */ +#define HOST_MODE 1U /* USB core in host mode */ +#define OTG_MODE 2U /* USB core in OTG mode */ + +#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */ +#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */ +#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */ +#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */ +#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */ + +#define RXSTAT_GOUT_NAK 1U /* global out NAK (triggers an interrupt) */ +#define RXSTAT_DATA_UPDT 2U /* out data packet received */ +#define RXSTAT_XFER_COMP 3U /* out transfer completed (triggers an interrupt) */ +#define RXSTAT_SETUP_COMP 4U /* setup transaction completed (triggers an interrupt) */ +#define RXSTAT_SETUP_UPDT 6U /* setup data packet received */ + +#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ +#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ +#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ +#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ + +#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */ +#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */ +#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */ +#define HC_PID_SETUP 3U /* host channel data PID is SETUP */ + +#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */ +#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */ +#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */ + +#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */ +#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */ +#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */ + +#define HCCHAR_CTRL 0U /* control channel type */ +#define HCCHAR_ISOC 1U /* synchronous channel type */ +#define HCCHAR_BULK 2U /* bulk channel type */ +#define HCCHAR_INTR 3U /* interrupt channel type */ + +#endif /* USB_DEFINES_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h new file mode 100644 index 0000000000..2e7d444381 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h @@ -0,0 +1,596 @@ +/*! + \file usb_regs.h + \brief USB FS cell registers definition and handle macros + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USB_REGS_H +#define USB_REGS_H + +#include "usb_conf.h" + +#define USBFS USBFS_BASE /*!< base address of USBFS registers */ + +/* registers location definitions */ +#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device in endpoint-x (x = 1..3) transfer length registers */ +#define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x)) /*!< locate host channel-x control registers */ +#define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x)) /*!< locate host channel-x interrupt flag registers */ +#define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x)) /*!< locate host channel-x interrupt enable registers */ +#define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x)) /*!< locate host channel-x transfer length registers */ +#define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x)) /*!< locate device in endpoint-x control registers */ +#define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x)) /*!< locate device out endpoint-x control registers */ +#define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x)) /*!< locate device in endpoint-x interrupt flag registers */ +#define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x)) /*!< locate device out endpoint-x interrupt flag registers */ +#define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x)) /*!< locate device in endpoint-x transfer length registers */ +#define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x)) /*!< locate device out endpoint-x transfer length registers */ +#define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x)) /*!< locate Device in endpoint-x transmit fifo status register */ +#define LOCATE_FIFO(x) (((x) + 1U) << 12U) /*!< locate FIFO-x memory */ + +/* registers definitions */ +#define USB_GOTGCS REG32(((USBFS) + 0x0000U)) /*!< global OTG control and status register */ +#define USB_GOTGINTF REG32(((USBFS) + 0x0004U)) /*!< global OTG interrupt flag register */ +#define USB_GAHBCS REG32(((USBFS) + 0x0008U)) /*!< global AHB control and status register */ +#define USB_GUSBCS REG32(((USBFS) + 0x000CU)) /*!< global USB control and status register */ +#define USB_GRSTCTL REG32(((USBFS) + 0x0010U)) /*!< global reset control register */ +#define USB_GINTF REG32(((USBFS) + 0x0014U)) /*!< global interrupt flag register */ +#define USB_GINTEN REG32(((USBFS) + 0x0018U)) /*!< global interrupt enable register */ +#define USB_GRSTATR REG32(((USBFS) + 0x001CU)) /*!< global receive status read register */ +#define USB_GRSTATP REG32(((USBFS) + 0x0020U)) /*!< global receive status read and pop register */ +#define USB_GRFLEN REG32(((USBFS) + 0x0024U)) /*!< global receive fifo length register */ +#define USB_HNPTFLEN REG32(((USBFS) + 0x0028U)) /*!< host non-periodic transmit fifo length register */ +#define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U)) /*!< device in endpoint 0 transmit fifo length register */ +#define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU)) /*!< host non-periodic transmint fifo/queue status register */ +#define USB_GCCFG REG32(((USBFS) + 0x0038U)) /*!< global core configuration register */ +#define USB_CID REG32(((USBFS) + 0x003CU)) /*!< core id register */ +#define USB_HPTFLEN REG32(((USBFS) + 0x0100U)) /*!< host periodic transmit fifo length register */ +#define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x))) /*!< device in endpoint transmit fifo length register */ + +#define USB_HCTL REG32(((USBFS) + 0x0400U)) /*!< host control register */ +#define USB_HFT REG32(((USBFS) + 0x0404U)) /*!< host frame interval register */ +#define USB_HFINFR REG32(((USBFS) + 0x0408U)) /*!< host frame information remaining register */ +#define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U)) /*!< host periodic transmit fifo/queue status register */ +#define USB_HACHINT REG32(((USBFS) + 0x0414U)) /*!< host all channels interrupt register */ +#define USB_HACHINTEN REG32(((USBFS) + 0x0418U)) /*!< host all channels interrupt enable register */ +#define USB_HPCS REG32(((USBFS) + 0x0440U)) /*!< host port control and status register */ +#define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ +#define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ +#define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ +#define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ + +#define USB_DCFG REG32(((USBFS) + 0x0800U)) /*!< device configuration register */ +#define USB_DCTL REG32(((USBFS) + 0x0804U)) /*!< device control register */ +#define USB_DSTAT REG32(((USBFS) + 0x0808U)) /*!< device status register */ +#define USB_DIEPINTEN REG32(((USBFS) + 0x0810U)) /*!< device in endpoint common interrupt enable register */ +#define USB_DOEPINTEN REG32(((USBFS) + 0x0814U)) /*!< device out endpoint common interrupt enable register */ +#define USB_DAEPINT REG32(((USBFS) + 0x0818U)) /*!< device all endpoints interrupt register */ +#define USB_DAEPINTEN REG32(((USBFS) + 0x081CU)) /*!< device all endpoints interrupt enable register */ +#define USB_DVBUSDT REG32(((USBFS) + 0x0828U)) /*!< device vbus discharge time register */ +#define USB_DVBUSPT REG32(((USBFS) + 0x082CU)) /*!< device vbus pulsing time register */ +#define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U)) /*!< device in endpoint fifo empty interrupt enable register */ +#define USB_DEP1INT REG32(((USBFS) + 0x0838U)) /*!< device endpoint 1 interrupt register */ +#define USB_DEP1INTEN REG32(((USBFS) + 0x083CU)) /*!< device endpoint 1 interrupt enable register */ +#define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U)) /*!< device in endpoint 1 interrupt enable register */ +#define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U)) /*!< device out endpoint 1 interrupt enable register */ +#define USB_DIEP0CTL REG32(((USBFS) + 0x0900U)) /*!< device in endpoint 0 control register */ +#define USB_DIEP0LEN REG32(((USBFS) + 0x0910U)) /*!< device in endpoint 0 transfer length register */ +#define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U)) /*!< device out endpoint 0 control register */ +#define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U)) /*!< device out endpoint 0 transfer length register */ +#define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x))) /*!< device in endpoint-x control register */ +#define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x))) /*!< device out endpoint-x control register */ +#define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x))) /*!< device in endpoint-x interrupt flag register */ +#define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x))) /*!< device out endpoint-x interrupt flag register */ +#define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x))) /*!< device in endpoint-x transfer length register */ +#define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x))) /*!< device out endpoint-x transfer length register */ +#define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x))) /*!< device in endpoint-x transmit fifo status register */ + +#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U)) /*!< power and clock register */ + +#define USB_FIFO(x) (®32(((USBFS) + LOCATE_FIFO(x)))) /*!< fifo memory */ + +/* global OTG control and status register bits definitions */ +#define GOTGCS_BSV BIT(19) /*!< B-Session valid */ +#define GOTGCS_ASV BIT(18) /*!< A-session valid */ +#define GOTGCS_DI BIT(17) /*!< debounce interval */ +#define GOTGCS_IDPS BIT(16) /*!< id pin status */ +#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ +#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ +#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ +#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ +#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ +#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ + +/* global OTG interrupt flag register bits definitions */ +#define GOTGINTF_DF BIT(19) /*!< debounce finish */ +#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ +#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ +#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ +#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ +#define GOTGINTF_SESEND BIT(2) /*!< session end */ + +/* global AHB control and status register bits definitions */ +#define GAHBCS_PTXFTH BIT(8) /*!< periodic tx fifo threshold */ +#define GAHBCS_TXFTH BIT(7) /*!< tx fifo threshold */ +#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + +/* global USB control and status register bits definitions */ +#define GUSBCS_FDM BIT(30) /*!< force device mode */ +#define GUSBCS_FHM BIT(29) /*!< force host mode */ +#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ +#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ +#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ + +/* global reset control register bits definitions */ +#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx fifo number */ +#define GRSTCTL_TXFF BIT(5) /*!< tx fifo flush */ +#define GRSTCTL_RXFF BIT(4) /*!< rx fifo flush */ +#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ +#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ +#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ + +/* global interrupt flag register bits definitions */ +#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ +#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ +#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ +#define GINTF_IDPSC BIT(28) /*!< id pin status change */ +#define GINTF_PTXFEIF BIT(26) /*!< periodic tx fifo empty interrupt flag */ +#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ +#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ +#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ +#define GINTF_ISOONCIF BIT(21) /*!< isochronous out transfer not complete interrupt flag */ +#define GINTF_ISOINCIF BIT(20) /*!< isochronous in transfer not complete interrupt flag */ +#define GINTF_OEPIF BIT(19) /*!< out endpoint interrupt flag */ +#define GINTF_IEPIF BIT(18) /*!< in endpoint interrupt flag */ +#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ +#define GINTF_ISOOPDIF BIT(14) /*!< isochronous out packet dropped interrupt flag */ +#define GINTF_ENUMF BIT(13) /*!< enumeration finished */ +#define GINTF_RST BIT(12) /*!< USB reset */ +#define GINTF_SP BIT(11) /*!< USB suspend */ +#define GINTF_ESP BIT(10) /*!< early suspend */ +#define GINTF_GONAK BIT(7) /*!< global out NAK effective */ +#define GINTF_GNPINAK BIT(6) /*!< global in non-periodic NAK effective */ +#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx fifo empty interrupt flag */ +#define GINTF_RXFNEIF BIT(4) /*!< rx fifo non-empty interrupt flag */ +#define GINTF_SOF BIT(3) /*!< start of frame */ +#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ +#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ +#define GINTF_COPM BIT(0) /*!< current operation mode */ + +/* global interrupt enable register bits definitions */ +#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ +#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ +#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ +#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ +#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx fifo empty interrupt enable */ +#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ +#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ +#define GINTEN_PXNCIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_ISOONCIE BIT(21) /*!< isochronous out transfer not complete interrupt enable */ +#define GINTEN_ISOINCIE BIT(20) /*!< isochronous in transfer not complete interrupt enable */ +#define GINTEN_OEPIE BIT(19) /*!< out endpoints interrupt enable */ +#define GINTEN_IEPIE BIT(18) /*!< in endpoints interrupt enable */ +#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ +#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous out packet dropped interrupt enable */ +#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ +#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ +#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ +#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ +#define GINTEN_GONAKIE BIT(7) /*!< global out NAK effective interrupt enable */ +#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic in NAK effective interrupt enable */ +#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic tx fifo empty interrupt enable */ +#define GINTEN_RXFNEIE BIT(4) /*!< receive fifo non-empty interrupt enable */ +#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ +#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ +#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ + +/* global receive fifo length register bits definitions */ +#define GRFLEN_RXFD BITS(0, 15) /*!< rx fifo depth */ + +/* host non-periodic transmit fifo length register bits definitions */ +#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic tx fifo depth */ +#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic tx RAM start address */ + +/* IN endpoint 0 transmit fifo length register bits definitions */ +#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< in endpoint 0 tx fifo depth */ +#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< in endpoint 0 tx RAM start address */ + +/* host non-periodic transmit fifo/queue status register bits definitions */ +#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic tx request queue */ +#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic tx request queue space */ +#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic tx fifo space */ +#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* global core configuration register bits definitions */ +#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ +#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ +#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ +#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ +#define GCCFG_PWRON BIT(16) /*!< power on */ + +/* core ID register bits definitions */ +#define CID_CID BITS(0, 31) /*!< core ID */ + +/* host periodic transmit fifo length register bits definitions */ +#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic tx fifo depth */ +#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic tx RAM start address */ + +/* device in endpoint transmit fifo length register bits definitions */ +#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< in endpoint tx fifo x depth */ +#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< in endpoint fifox tx x RAM start address */ + +/* host control register bits definitions */ +#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ + +/* host frame interval register bits definitions */ +#define HFT_FRI BITS(0, 15) /*!< frame interval */ + +/* host frame information remaining register bits definitions */ +#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ + +/* host periodic transmit fifo/queue status register bits definitions */ +#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic tx request queue */ +#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic tx request queue space */ +#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic tx fifo space */ +#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* host all channels interrupt register bits definitions */ +#define HACHINT_HACHINT BITS(0, 7) /*!< host all channel interrupts */ + +/* host all channels interrupt enable register bits definitions */ +#define HACHINTEN_CINTEN BITS(0, 7) /*!< channel interrupt enable */ + +/* host port control and status register bits definitions */ +#define HPCS_PS BITS(17, 18) /*!< port speed */ +#define HPCS_PP BIT(12) /*!< port power */ +#define HPCS_PLST BITS(10, 11) /*!< port line status */ +#define HPCS_PRST BIT(8) /*!< port reset */ +#define HPCS_PSP BIT(7) /*!< port suspend */ +#define HPCS_PREM BIT(6) /*!< port resume */ +#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ +#define HPCS_PE BIT(2) /*!< port enable */ +#define HPCS_PCD BIT(1) /*!< port connect detected */ +#define HPCS_PCST BIT(0) /*!< port connect status */ + +/* host channel-x control register bits definitions */ +#define HCHCTL_CEN BIT(31) /*!< channel enable */ +#define HCHCTL_CDIS BIT(30) /*!< channel disable */ +#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define HCHCTL_LSD BIT(17) /*!< low-speed device */ +#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* host channel-x interrupt flag register bits definitions */ +#define HCHINTF_DTER BIT(10) /*!< data toggle error */ +#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ +#define HCHINTF_BBER BIT(8) /*!< babble error */ +#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ +#define HCHINTF_NYET BIT(6) /*!< NYET */ +#define HCHINTF_ACK BIT(5) /*!< ACK */ +#define HCHINTF_NAK BIT(4) /*!< NAK */ +#define HCHINTF_STALL BIT(3) /*!< STALL */ +#define HCHINTF_CH BIT(1) /*!< channel halted */ +#define HCHINTF_TF BIT(0) /*!< transfer finished */ + +/* host channel-x interrupt enable register bits definitions */ +#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ +#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ +#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ +#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ +#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ +#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ +#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ +#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ +#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ +#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + +/* host channel-x transfer length register bits definitions */ +#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device control and status registers */ +/* device configuration registers bits definitions */ +#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +#define DCFG_DAR BITS(4, 10) /*!< device address */ +#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status out handshake */ +#define DCFG_DS BITS(0, 1) /*!< device speed */ + +/* device control registers bits definitions */ +#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ +#define DCTL_CGONAK BIT(10) /*!< clear global out NAK */ +#define DCTL_SGONAK BIT(9) /*!< set global out NAK */ +#define DCTL_CGINAK BIT(8) /*!< clear global in NAK */ +#define DCTL_SGINAK BIT(7) /*!< set global in NAK */ +#define DCTL_GONS BIT(3) /*!< global out NAK status */ +#define DCTL_GINS BIT(2) /*!< global in NAK status */ +#define DCTL_SD BIT(1) /*!< soft disconnect */ +#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + +/* device status registers bits definitions */ +#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ +#define DSTAT_SPST BIT(0) /*!< suspend status */ + +/* device in endpoint common interrupt enable registers bits definitions */ +#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit fifo empty interrupt enable bit */ +#define DIEPINTEN_IEPNEEN BIT(6) /*!< in endpoint NAK effective interrupt enable bit */ +#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint tx fifo underrun interrupt enable bit */ +#define DIEPINTEN_CITOEN BIT(3) /*!< control in timeout interrupt enable bit */ +#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device out endpoint common interrupt enable registers bits definitions */ +#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back setup packets interrupt enable bit */ +#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint rx fifo overrun interrupt enable bit */ +#define DOEPINTEN_STPFEN BIT(3) /*!< fifo phase finished interrupt enable bit */ +#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device all endpoints interrupt registers bits definitions */ +#define DAEPINT_OEPITB BITS(16, 21) /*!< device all out endpoint interrupt bits */ +#define DAEPINT_IEPITB BITS(0, 5) /*!< device all in endpoint interrupt bits */ + +/* device all endpoints interrupt enable registers bits definitions */ +#define DAEPINTEN_OEPIE BITS(16, 21) /*!< out endpoint interrupt enable */ +#define DAEPINTEN_IEPIE BITS(0, 3) /*!< in endpoint interrupt enable */ + +/* device Vbus discharge time registers bits definitions */ +#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ + +/* device Vbus pulsing time registers bits definitions */ +#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ + +/* device IN endpoint FIFO empty interrupt enable register bits definitions */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3) /*!< in endpoint tx FIFO empty interrupt enable bits */ + +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ + +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* device in endpoint-x interrupt flag register bits definitions */ +#define DIEPINTF_TXFE BIT(7) /*!< transmit fifo empty */ +#define DIEPINTF_IEPNE BIT(6) /*!< in endpoint NAK effective */ +#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint tx fifo underrun */ +#define DIEPINTF_CITO BIT(3) /*!< control in Timeout interrupt */ +#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DIEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device out endpoint-x interrupt flag register bits definitions */ +#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back setup packets */ +#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint rx fifo overrun */ +#define DOEPINTF_STPF BIT(3) /*!< setup phase finished */ +#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DOEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device in endpoint 0 transfer length register bits definitions */ +#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device out endpoint 0 transfer length register bits definitions */ +#define DOEP0LEN_STPCNT BITS(29, 30) /*!< setup packet count */ +#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device out endpoint-x transfer length register bits definitions */ +#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +#define DOEPLEN_STPCNT BITS(29, 30) /*!< setup packet count */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device in endpoint-x transmit fifo status register bits definitions */ +#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< in endpoint¡¯s tx fifo space remaining */ + +/* USB power and clock registers bits definition */ +#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ +#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ + +/* register options defines */ +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ + +#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ +#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ +#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ + +#define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */ + +#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U) /*!< tx fifo half empty */ +#define TXFIFO_EMPTY GAHBCS_TFEL(1U) /*!< tx fifo completely empty */ + +#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ + +#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ +#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ +#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ +#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ +#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ + +#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ + +#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ +#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ +#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ +#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ + +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ + +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ + +/* endpoints address */ + +/* first bit is direction(0 for Rx and 1 for Tx) */ +#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */ +#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */ +#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */ +#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */ +#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */ +#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */ +#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */ +#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */ + +/* enable global interrupt */ +#define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN) + +/* disable global interrupt */ +#define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN) + +/* get current operation mode */ +#define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM) + +/* read global interrupt flag */ +#define USB_CORE_INTR_READ(x) \ +do { \ + uint32_t global_intf = USB_GINTF; \ + (x) = global_intf & USB_GINTEN; \ +} while(0) + +/* read global interrupt flag */ +#define USB_DAOEP_INTR_READ(x) \ +do { \ + uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ + uint32_t dev_all_ep_int = USB_DAEPINT; \ + uint32_t out_ep_intb = DAEPINT_OEPITB; \ + (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ +} while(0) + +/* read out endpoint-x interrupt flag */ +#define USB_DOEP_INTR_READ(x, EpID) \ +do { \ + uint32_t out_epintf = USB_DOEPxINTF(EpID); \ + (x) = out_epintf & USB_DOEPINTEN; \ +} while(0) + +/* read all in endpoint interrupt flag */ +#define USB_DAIEP_INTR_READ(x) \ +do { \ + uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ + uint32_t dev_all_ep_int = USB_DAEPINT; \ + uint32_t in_ep_intb = DAEPINT_IEPITB; \ + (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ +} while(0) + + +/* read in endpoint-x interrupt flag */ +#define USB_DIEP_INTR_READ(x, EpID) \ +do { \ + uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \ + uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \ + uint32_t dev_inep_inten = USB_DIEPINTEN; \ + (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \ +} while(0) + +/* generate remote wakup signal */ +#define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP) + +/* no remote wakup signal generate */ +#define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP) + +/* generate soft disconnect */ +#define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD) + +/* no soft disconnect generate */ +#define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD) + +/* set device address */ +#define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U) + +/* check whether frame is even */ +#define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U)) + +/* read port status */ +#define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC)) + +/* usb clock initialize */ +#define USB_FSLSCLOCK_INIT(ClockFreq) \ +do { \ + USB_HCTL &= ~HCTL_CLKSEL; \ + USB_HCTL |= ClockFreq; \ +} while(0) + +/* get usb current speed */ +#define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17) + +/* get usb current frame */ +#define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU) + +#endif /* USB_REGS_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h new file mode 100644 index 0000000000..d82cb74f85 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h @@ -0,0 +1,216 @@ +/*! + \file usb_std.h + \brief USB 2.0 standard defines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USB_STD_H +#define USB_STD_H + +#include "usb_conf.h" + +/* constants definitions */ +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ +#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /*!< USB device configuration descriptor length */ +#define USB_IF_DESC_LEN 0x09U /*!< USB device interface descriptor length */ +#define USB_EP_DESC_LEN 0x07U /*!< USB device endpoint descriptor length */ +#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ + +/* bit 7 of bmRequestType: data phase transfer direction */ +#define USB_DIR_MASK 0x80U /*!< USB transfer direction mask */ +#define USB_DIR_OUT 0x00U /*!< USB transfer out direction */ +#define USB_DIR_IN 0x80U /*!< USB transfer in direction */ + +/* bit 6..5 of bmRequestType: request type */ +#define USB_STANDARD_REQ 0x00U /*!< USB standard request */ +#define USB_CLASS_REQ 0x20U /*!< USB class request */ +#define USB_VENDOR_REQ 0x40U /*!< USB vebdor request */ +#define USB_REQ_MASK 0x60U /*!< USB request mask */ + +/* bit 4..0 of bmRequestType: recipient type */ +#define USB_REQTYPE_DEVICE 0x00U /*!< USB device request type */ +#define USB_REQTYPE_INTERFACE 0x01U /*!< USB interface request type*/ +#define USB_REQTYPE_ENDPOINT 0x02U /*!< USB endpoint request type*/ +#define USB_REQTYPE_MASK 0x03U /*!< USB request type mask*/ + +/* bRequest value */ +#define USBREQ_GET_STATUS 0x00U /*!< USB get status request*/ +#define USBREQ_CLEAR_FEATURE 0x01U /*!< USB clear feature request*/ +#define USBREQ_SET_FEATURE 0x03U /*!< USB set feature request*/ +#define USBREQ_SET_ADDRESS 0x05U /*!< USB set address request*/ +#define USBREQ_GET_DESCRIPTOR 0x06U /*!< USB get descriptor request*/ +#define USBREQ_SET_DESCRIPTOR 0x07U /*!< USB set descriptor request*/ +#define USBREQ_GET_CONFIGURATION 0x08U /*!< USB get configuration request*/ +#define USBREQ_SET_CONFIGURATION 0x09U /*!< USB set configuration request*/ +#define USBREQ_GET_INTERFACE 0x0AU /*!< USB get interface request*/ +#define USBREQ_SET_INTERFACE 0x0BU /*!< USB set interface request*/ +#define USBREQ_SYNCH_FRAME 0x0CU /*!< USB synchronize frame request*/ + +/* descriptor types of usb specifications */ +#define USB_DESCTYPE_DEVICE 0x01U /*!< USB device descriptor type*/ +#define USB_DESCTYPE_CONFIGURATION 0x02U /*!< USB configuration descriptor type*/ +#define USB_DESCTYPE_STRING 0x03U /*!< USB string descriptor type*/ +#define USB_DESCTYPE_INTERFACE 0x04U /*!< USB interface descriptor type*/ +#define USB_DESCTYPE_ENDPOINT 0x05U /*!< USB endpoint descriptor type*/ +#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /*!< USB device qualtfier descriptor type*/ +#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /*!< USB other speed configuration descriptor type*/ +#define USB_DESCTYPE_INTERFACE_POWER 0x08U /*!< USB interface power descriptor type*/ + +#define USB_DESCTYPE_HID 0x21U /*!< USB HID descriptor type*/ +#define USB_DESCTYPE_HID_REPORT 0x22U /*!< USB HID report descriptor type*/ + +#define USB_DEVDESC_SIZE 18U /*!< USB device descriptor size*/ +#define USB_CFGDESC_SIZE 9U /*!< USB configure descriptor size*/ +#define USB_INTDESC_SIZE 9U /*!< USB interface descriptor size*/ +#define USB_EPDESC_SIZE 7U /*!< USB endpoint descriptor size*/ + +/* descriptor type and descriptor index */ +/* use the following values when USB host need to get descriptor */ +#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U) /*!< USB device operation marco */ +#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U) /*!< USB configuration operation marco */ +#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U) /*!< USB string operation marco */ +#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB interface operation marco */ +#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB endpoint operation marco */ +#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) /*!< USB device qualifier operation marco */ +#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) /*!< USB other speed configuration operation marco */ +#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U) /*!< USB interface power operation marco */ +#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U) /*!< USB HID report operation marco */ +#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U) /*!< USB HID operation marco */ + +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +/* supported classes */ +#define USB_MSC_CLASS 0x08U /*!< USB MSC class*/ +#define USB_HID_CLASS 0x03U /*!< USB HID class*/ + +/* interface descriptor field values for hid boot protocol */ +#define HID_BOOT_CODE 0x01U /*!< USB HID boot code*/ +#define HID_KEYBRD_BOOT_CODE 0x01U /*!< USB HID keyboard boot code*/ +#define HID_MOUSE_BOOT_CODE 0x02U /*!< USB HID mouse boot code*/ + +/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec + standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ +#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ + +#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \ + + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE)) /*!< USB host set configuration descriptor size */ + +#pragma pack(1) + +typedef union +{ + uint8_t data[8]; + + struct _setup_packet_struct + { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bRequest; /*!< request of setup packet */ + uint16_t wValue; /*!< value of setup packet */ + uint16_t wIndex; /*!< index of setup packet */ + uint16_t wLength; /*!< length of setup packet */ + } b; +}usb_setup_union; + +typedef struct +{ + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_descriptor_header_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_descriptor_device_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_descriptor_configuration_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_descriptor_interface_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an interrupt or isochrnous type */ +} usb_descriptor_endpoint_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +}usb_descriptor_language_id_struct; + +#pragma pack() + +#endif /* USB_STD_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h new file mode 100644 index 0000000000..637f1b5654 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h @@ -0,0 +1,81 @@ +/*! + \file usbd_core.h + \brief USB device mode core driver header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_CORE_H +#define USBD_CORE_H + +#include "usbd_conf.h" +#include "usb_core.h" +#include "usbd_std.h" + +/* constants definitions */ +/* device status */ +#define USB_STATUS_DEFAULT 1U /* default status */ +#define USB_STATUS_ADDRESSED 2U /* addressed status */ +#define USB_STATUS_CONFIGURED 3U /* configured status */ +#define USB_STATUS_SUSPENDED 4U /* suspended status */ + +/* function declarations */ +/* initailizes the USB device-mode handler stack */ +void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); +/* endpoint initialization */ +void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc); +/* endpoint deinitialize */ +void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* endpoint prepare to receive data */ +void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +/* endpoint prepare to transmit data */ +void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); +/* transmit data on the control channel */ +usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); +/* receive data on the control channel */ +usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); +/* transmit status on the control channel */ +usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev); +/* receive status on the control channel */ +usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev); +/* set an endpoint to stall status */ +void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* clear endpoint stalled status */ +void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* flushes the fifos */ +void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* get the received data length */ +uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num); + +#endif /* USBD_CORE_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h new file mode 100644 index 0000000000..89f791d8d8 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h @@ -0,0 +1,57 @@ +/*! + \file usbd_int.h + \brief USB device mode interrupt handler header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_INT_H +#define USBD_INT_H + +#include "usbd_core.h" + +/* constants definitions */ +typedef struct +{ + uint8_t (*SOF) (usb_core_handle_struct *pudev); +}usbd_int_cb_struct; + +extern usbd_int_cb_struct *usbd_int_fops; + +/* function declaration */ +/* USB device-mode interrupts global service routine handler */ +uint32_t usbd_isr (usb_core_handle_struct *pudev); + +#endif /* USBD_INT_H */ + diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h new file mode 100644 index 0000000000..d8ad1a61db --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h @@ -0,0 +1,98 @@ +/*! + \file usbd_std.h + \brief USB 2.0 standard defines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_STD_H +#define USBD_STD_H + +#include "usb_std.h" +#include "usbd_core.h" +#include "usbd_conf.h" +#include + +/* constants definitions */ +#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/ +#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/ +#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/ +#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/ +#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/ +#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/ + +#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/ +#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/ + +#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/ +#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/ +#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/ + +#define ENG_LANGID 0x0409U /*!< USB english language id*/ +#define CHN_LANGID 0x0804U /*!< USB chinese language id*/ + +#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/ + +#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/ +#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/ + +#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/ + +#define WIDE_STRING(string) _WIDE_STRING(string) +#define _WIDE_STRING(string) L##string + +#define USBD_STRING_DESC(string) \ + (uint8_t *)&(struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(string)]; \ + }) { \ + sizeof(WIDE_STRING(string)) + 2U - 2U, \ + USB_DESCTYPE_STRING, \ + WIDE_STRING(string) \ + } + +#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) + +/* function declarations */ +/* USB device setup transaction*/ +usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev); +/* USB device out transaction*/ +usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); +/* USB device in transaction*/ +usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); +/* USB device enum error handle*/ +void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req); + +#endif /* USBD_STD_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h new file mode 100644 index 0000000000..8137444b50 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h @@ -0,0 +1,310 @@ +/*! + \file usbh_core.h + \brief header file for usbh_core.c + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_CORE_H +#define USBH_CORE_H + +#include "usbh_conf.h" +#include "usb_std.h" +#include "usb_core.h" + +/* constants definitions */ +#define MSC_CLASS 0x08 /*!< the MSC class define */ +#define HID_CLASS 0x03 /*!< the HID class define */ +#define MSC_PROTOCOL 0x50 /*!< the MSC protocal define */ +#define CBI_PROTOCOL 0x01 /*!< the CBI protocal define */ + +#define USBH_DEVICE_ADDRESS_DEFAULT 0U /*!< the default device address define */ +#define USBH_DEVICE_ADDRESS 1U /*!< the device address define */ +#define USBH_MAX_ERROR_COUNT 2U /*!< the max error count define */ + +#define HOST_USER_SELECT_CONFIGURATION 1U /*!< the user select configuration define */ +#define HOST_USER_CLASS_ACTIVE 2U /*!< the user class active define */ +#define HOST_USER_CLASS_SELECTED 3U /*!< the user class selected define */ +#define HOST_USER_CONNECTION 4U /*!< the user connecttion define */ +#define HOST_USER_DISCONNECTION 5U /*!< the user disconnection define */ +#define HOST_USER_UNRECOVERED_ERROR 6U /*!< the user unrecovered error define */ + +#define MAX_USBH_STATE_STACK_DEEP 4 /*!< the max state stack deep define */ +#define MAX_USBH_STATE_TABLE_NUM 10U /*!< the max state table number */ + +#define HOST_FSM_ID 0U /*!< the host state table id */ +#define ENUM_FSM_ID 1U /*!< the enum state table id */ +#define CMD_FSM_ID 2U /*!< the cmd state table id */ +#define CTRL_FSM_ID 3U /*!< the ctrl state table id */ +#define CLASS_REQ_FSM_ID 4U /*!< the class req state table id */ +#define CLASS_FSM_ID 5U /*!< the class state table id */ + +#define UP_STATE 100U /*!< up state define */ +#define GO_TO_UP_STATE_EVENT 100U /*!< go to up state event define */ + +#define HOST_HANDLE_TABLE_SIZE 9U /*!< the host handle table size define */ +/* the enum of host state */ +typedef enum +{ + HOST_IDLE = 0, /* the host idle state definition */ + HOST_DEV_ATTACHED, /* the host device attached state definition */ + HOST_DEV_DETACHED, /* the host device detached state definition */ + HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */ + HOST_ENUMERATION, /* the host enumeration state definition */ + HOST_CLASS_REQUEST, /* the host class request state definition */ + HOST_CLASS, /* the host class state definition */ + HOST_USER_INPUT, /* the host user input state definition */ + HOST_SUSPENDED, /* the host suspended state definition */ + HOST_ERROR /* the host error state definition */ +}host_state_enum; + +/* the enum of host event */ +typedef enum +{ + HOST_EVENT_ATTACHED = 0, /* the host attached event */ + HOST_EVENT_ENUM, /* the host enum event */ + HOST_EVENT_USER_INPUT, /* the host user input event */ + HOST_EVENT_CLASS_REQ, /* the host class request event */ + HOST_EVENT_CLASS, /* the host class event */ + HOST_EVENT_ERROR, /* the host error event */ + HOST_EVENT_DEV_DETACHED, /* the host device detached event */ + HOST_EVENT_IDLE /* the host idle event */ +}host_event_enum; + +/* the enum of enum state */ +typedef enum +{ + ENUM_IDLE = 0, /* the enum idle state definition */ + ENUM_SET_ADDR, /* the enum set address state definition */ + ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */ + ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */ + ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */ + ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */ + ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */ + ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */ + ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */ + ENUM_DEV_CONFIGURED /* the enum device configuration state definition */ +}enum_state_enum; + +/* the enum of ctrl state */ +typedef enum +{ + CTRL_IDLE = 0, /* the ctrl idle state definition */ + CTRL_SETUP, /* the ctrl setup state definition */ + CTRL_DATA, /* the ctrl data state definition */ + CTRL_STATUS, /* the ctrl status state definition */ + CTRL_ERROR, /* the ctrl error state definition */ + CTRL_STALLED, /* the ctrl stalled state definition */ + CTRL_COMPLETE /* the ctrl complete state definition */ +}ctrl_state_enum; + +/* the enum of host status */ +typedef enum +{ + USBH_OK = 0, /* the usbh ok status definition */ + USBH_BUSY, /* the usbh busy status definition */ + USBH_FAIL, /* the usbh fail status definition */ + USBH_NOT_SUPPORTED, /* the usbh not supported status definition */ + USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */ + USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */ + USBH_APPLY_DEINIT /* the usbh apply deinit status definition */ +}usbh_status_enum; + +/* the state of user action */ +typedef enum +{ + USBH_USER_NO_RESP = 0, /* the user no response */ + USBH_USER_RESP_OK = 1, /* the user response ok */ +}usbh_user_status_enum; + +/* control transfer information */ +typedef struct +{ + uint8_t hc_in_num; /* the host in channel number */ + uint8_t hc_out_num; /* the host out channel number */ + uint8_t ep0_size; /* the endpoint 0 max packet size */ + uint8_t error_count; /* the error count */ + uint16_t length; /* the length */ + uint16_t timer; /* the timer */ + uint8_t *buff; /* the buffer */ + usb_setup_union setup; /* the setup packet */ +}usbh_ctrl_struct; + +/* device property */ +typedef struct +{ + uint8_t address; /* the device address */ + uint8_t speed; /* the device speed */ + usb_descriptor_device_struct dev_desc; /* the device descripter */ + usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */ + usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */ + usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */ +}usbh_device_struct; + +/* user callbacks */ +typedef struct +{ + void (*init) (void); /* the user callback init function */ + void (*deinit) (void); /* the user callback deinit function */ + void (*device_connected) (void); /* the user callback device connected function */ + void (*device_reset) (void); /* the user callback device reset function */ + void (*device_disconnected) (void); /* the user callback device disconnected function */ + void (*over_current_detected) (void); /* the user callback over current detected function */ + void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */ + void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */ + void (*device_address_set) (void); /* the user callback set device address function */ + + void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, + usb_descriptor_interface_struct *itf_desc, + usb_descriptor_endpoint_struct *ep_desc); + /* the configuration descripter available function */ + + void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */ + void (*product_string) (void *prod_string); /* the user callback product string function */ + void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */ + void (*enumeration_finish) (void); /* the user callback enumeration finish function */ + usbh_user_status_enum (*user_input) (void); /* the user callback user input function */ + int (*user_application) (usb_core_handle_struct *pudev, uint8_t id); + /* the user callback user appliction function */ + void (*device_not_supported) (void); /* the user callback device not supported function */ + void (*unrecovered_error) (void); /* the user callback unrecovered error function */ +}usbh_user_callback_struct; + +/* the backup state struct */ +typedef struct +{ + host_state_enum host_backup_state; /* the host backup state */ + enum_state_enum enum_backup_state; /* the enum backup state */ + ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */ + uint8_t class_req_backup_state; /* the class request backup state */ + uint8_t class_backup_state; /* the class backup state */ +} backup_state_struct; + +/* host information */ +typedef struct +{ + backup_state_struct usbh_backup_state; /* the usbh backup state variable */ + usbh_ctrl_struct control; /* the control struct variable */ + usbh_device_struct device; /* the device struct variable */ + usbh_user_callback_struct *usr_cb; /* the user callback function */ + usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */ + void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */ +}usbh_host_struct; + +/* the action function definition */ +typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate); + +/* the state table struct */ +typedef struct +{ + uint8_t cur_state; /* the current state */ + uint8_t cur_event; /* the current event */ + uint8_t next_state; /* the next state */ + ACT_FUN event_action_fun; /* the event action function entry */ +} state_table_struct; + +/* the state stack struct */ +typedef struct +{ + uint8_t state; /* the state in state stack */ + state_table_struct* table; /* the table in state stack */ + uint8_t table_size; /* the table size in state stack */ +} usbh_state_stack_struct; + +/* the state regist table struct */ +typedef struct +{ + uint8_t id; /* the id of the state table */ + state_table_struct* table; /* the table entry to regist */ + uint8_t table_size; /* the table size to regist */ +} usbh_state_regist_table_struct; + +/* the state handle struct */ +typedef struct +{ + uint8_t usbh_current_state; /* current state */ + uint8_t usbh_current_state_table_size; /* current state table size */ + state_table_struct* usbh_current_state_table; /* current state table */ + + usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */ + int8_t usbh_current_state_stack_top; /* the current state top */ + + usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */ + uint8_t usbh_regist_state_table_num; /* the number of regist state table */ +} usbh_state_handle_struct; + +/* function declarations */ +/* the host core driver function */ +usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* initialize the host portion of the driver */ +uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); +/* check if the device is connected */ +uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev); +/* this function returns the last URBstate */ +urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num); +/* this function returns the last URBstate */ +uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num); +/* de-initialize host */ +usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct* pustate); + +/* the state core driver function */ +/* state core driver init */ +void scd_init (usbh_state_handle_struct* pustate); +/* state core driver table regist */ +void scd_table_regist (usbh_state_handle_struct* pustate, + state_table_struct* pstate_table, + uint8_t table_id, + uint8_t current_table_size); +/* state core driver begin */ +void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id); +/* state core driver move state */ +void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state); +/* state core driver event handle */ +usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct* pustate, + uint8_t event, + uint8_t state); +/* state core driver table push */ +void scd_table_push (usbh_state_handle_struct* pustate); +/* state core driver table pop */ +void scd_table_pop (usbh_state_handle_struct* pustate); +/* the function is only used to state move */ +usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* the function to the up state */ +usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); + +#endif /* USBH_CORE_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h new file mode 100644 index 0000000000..b9cf7c5f97 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h @@ -0,0 +1,73 @@ +/*! + \file usbh_ctrl.h + \brief header file for usbh_ctrl.c + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_CTRL_H +#define USBH_CTRL_H + +#include "usbh_core.h" +#include "usbh_usr.h" + +/* constants definitions */ +/* the enum of CTRL event */ +typedef enum +{ + CTRL_EVENT_IDLE = 0, /* the ctrl idle event */ + CTRL_EVENT_SETUP, /* the ctrl setup event */ + CTRL_EVENT_DATA, /* the ctrl data event */ + CTRL_EVENT_STATUS, /* the ctrl status event */ + CTRL_EVENT_COMPLETE, /* the ctrl complete event */ + CTRL_EVENT_ERROR, /* the ctrl error event */ + CTRL_EVENT_STALLED, /* the ctrl stalled event */ +}ctrl_event_enum; + +#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */ + +extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]; +extern uint8_t ctrl_polling_handle_flag; + +/* function declarations */ +/* the polling function of control transfer state handle */ +usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* send datas from the host channel */ +usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len); +/* send the setup packet to the device */ +usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num); +/* this function prepare a hc and start a transfer */ +uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num); + +#endif /* USBH_CTRL_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h new file mode 100644 index 0000000000..d387f15b76 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h @@ -0,0 +1,73 @@ +/*! + \file usbh_hcs.h + \brief header file for usbh_hcs.c + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_HCS_H +#define USBH_HCS_H + +#include "usbh_core.h" + +/* constants definitions */ +#define HC_MAX 8U +#define HC_OK 0x0000U +#define HC_USED 0x8000U +#define HC_ERROR 0xFFFFU +#define HC_USED_MASK 0x7FFFU + +/* function declarations */ +/* allocate a new channel for the pipe */ +uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* free all usb host channel */ +uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev); +/* free the usb host channel */ +uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index); +/* open a channel */ +uint8_t usbh_channel_open (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps); +/* modify a channel */ +uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps); + +#endif /* USBH_HCS_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h new file mode 100644 index 0000000000..468ebc37d7 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h @@ -0,0 +1,58 @@ +/*! + \file usbh_int.h + \brief USB host mode interrupt handler header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_INT_H +#define USBH_INT_H + +#include "usb_core.h" + +/* constants definitions */ +typedef struct +{ + uint8_t (*sof) (usb_core_handle_struct *pudev); + uint8_t (*device_connected) (usb_core_handle_struct *pudev); + uint8_t (*device_disconnected) (usb_core_handle_struct *pudev); +}usbh_hcd_int_cb_struct; + +extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops; + +/* function declarations */ +/* handle global host interrupt */ +uint32_t usbh_isr (usb_core_handle_struct *pudev); + +#endif /* USBH_INT_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h new file mode 100644 index 0000000000..c4bc6cd91b --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h @@ -0,0 +1,101 @@ +/*! + \file usbh_std.h + \brief header file for usbh_std.c + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_STD_H +#define USBH_STD_H + +#include "usbh_core.h" +#include "usbh_usr.h" + +/* constants definitions */ +typedef enum +{ + ENUN_EVENT_IDLE = 0, /* the enum idle event */ + ENUM_EVENT_SET_ADDR, /* the enum set address event */ + ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */ + ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */ + ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */ + ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */ + ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */ + ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */ + ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */ + ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */ +}enum_event_enum; +/* standard feature selector for clear feature command */ +#define FEATURE_SELECTOR_ENDPOINT 0x00U +#define FEATURE_SELECTOR_DEVICE 0x01U + +#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */ +#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */ + +extern uint8_t usbh_cfg_desc[512]; +extern uint8_t enum_polling_handle_flag; +extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]; + +/* function declarations */ +/* the polling function of enumeration state */ +usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* get descriptor in usb host enumeration stage */ +void usbh_enum_desc_get (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + uint8_t *buf, + uint8_t req_type, + uint16_t value_idx, + uint16_t len); +/* set address in usb host enumeration stage */ +void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address); +/* set configuration in usb host enumeration stage */ +void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx); +/* parse the device descriptor */ +void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len); +/* parse the configuration descriptor */ +void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, + usb_descriptor_interface_struct *itf_desc, + usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], + uint8_t *buf, + uint16_t len); +/* parse the interface descriptor */ +void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf); +/* parse the endpoint descriptor */ +void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf); +/* parse the string descriptor */ +void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); +/* get the next descriptor header */ +usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr); + +#endif /* USBH_STD_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c new file mode 100644 index 0000000000..a2fa307efb --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c @@ -0,0 +1,974 @@ +/*! + \file usb_core.c + \brief USB core driver which can operate in host-mode and device-mode + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_core.h" + +static void usb_commonint_enable (usb_core_handle_struct *pudev); +static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev); + +/*! + \brief enable the commmon interrupts which are used in both device and host modes + \param[in] pudev: pointer to selected usb device + \param[out] none + \retval none +*/ +static void usb_commonint_enable (usb_core_handle_struct *pudev) +{ +#ifndef USE_OTG_MODE + + /* clear any pending USB interrupts */ + USB_GOTGINTF = 0xFFFFFFFFU; + +#endif /* USE_OTG_MODE */ + + USB_GINTF = 0xBFFFFFFF; + + /* enable the usb wakeup and suspend interrupts */ + USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + +#ifdef USE_OTG_MODE + + /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */ + USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ +} + +/*! + \brief soft reset of the OTG_FS core + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev) +{ + uint32_t count = 0U; + + /* enable core soft reset */ + USB_GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + do { + if (++count > 200000U) { + break; + } + } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST)); + + /* wait for addtional 3 PHY clocks */ + if (NULL != pudev->udelay) { + pudev->udelay(3U); + } + + return USB_OK; +} + +/*! + \brief write a packet into the tx fifo associated with the endpoint + \param[in] src: pointer to source buffer + \param[in] chep_num: channel or endpoint identifier which is in (0..3) + \param[in] len: packet length + \param[out] none + \retval operation status +*/ +usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len) +{ + uint32_t count32b = 0U, i = 0U; + __IO uint32_t *fifo = USB_FIFO(chep_num); + + count32b = (len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) { + *fifo = *((__packed uint32_t *)src); + + src += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the rx fifo associated with the endpoint + \param[in] dest: pointer to destination buffer + \param[in] len: packet length + \param[out] none + \retval void type pointer +*/ +void *usb_fifo_read (uint8_t *dest, uint16_t len) +{ + uint32_t i = 0U; + uint32_t count32b = (len + 3U) / 4U; + + __IO uint32_t *fifo = USB_FIFO(0U); + + for (i = 0U; i < count32b; i++) { + *(__packed uint32_t *)dest = *fifo; + + dest += 4U; + } + + return ((void *)dest); +} + +/*! + \brief initialize core parameters + \param[in] pudev: pointer to usb device + \param[in] core_id: USB core id + \param[out] none + \retval operation status +*/ +usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id) +{ + /* at startup the core is in FS mode */ + pudev->cfg.core_speed = USB_CORE_SPEED_FULL; + pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; + + /* initialize the core parameters */ + if (USB_FS_CORE_ID == core_id) { + + pudev->cfg.core_id = USB_FS_CORE_ID; + + /* set the host channel numbers */ + pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT; + + /* set the device endpoint numbers */ + pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT; + + /* fifo size is in terms of DWORD */ + pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN; + + /* OTG_FS core use embedded physical layer */ + pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; + + #ifdef USBFS_SOF_OUTPUT_ENABLED + pudev->cfg.sof_output = 1U; + #endif /* USBFS_SOF_OUTPUT_ENABLED */ + + #ifdef USBFS_LOW_PWR_MGMT_SUPPORT + pudev->cfg.low_power = 1U; + #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status_enum usb_core_init (usb_core_handle_struct *pudev) +{ + /* soft reset the core */ + usb_core_reset(pudev); + + /* active the transceiver and enable vbus sensing */ + USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + + /* set tx fifo empty level to half empty mode */ + USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; + +#ifndef VBUS_SENSING_ENABLED + USB_GCCFG |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + if(pudev->cfg.sof_output){ + USB_GCCFG |= GCCFG_SOFOEN; + } + + if (NULL != pudev->mdelay) { + pudev->mdelay(20U); + } + + +#ifdef USE_OTG_MODE + /* enable OTG features */ + USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; + USB_OTG_EnableCommonInt(pudev); + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief flush a tx fifo or all tx fifos + \param[in] pudev: pointer to usb device + \param[in] fifo_num: fifo number which is in (0..3) + \param[out] none + \retval operation status +*/ +usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num) +{ + uint32_t count = 0U; + + USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for tx fifo flush bit is set */ + do { + if (++count > 200000U) { + break; + } + } while (USB_GRSTCTL & GRSTCTL_TXFF); + + /* wait for 3 PHY clocks */ + if (NULL != pudev->udelay) { + pudev->udelay(3U); + } + + return USB_OK; +} + +/*! + \brief flush the entire rx fifo + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev) +{ + uint32_t count = 0U; + + USB_GRSTCTL = GRSTCTL_RXFF; + + /* wait for rx fifo flush bit is set */ + do { + if (++count > 200000U) { + break; + } + } while (USB_GRSTCTL & GRSTCTL_RXFF); + + /* wait for 3 PHY clocks */ + if (NULL != pudev->udelay) { + pudev->udelay(3U); + } + + return USB_OK; +} + +/*! + \brief set operation mode (host or device) + \param[in] pudev: pointer to usb device + \param[in] mode: operation mode which need to set + \arg HOST_MODE + \arg DEVICE_MODE + \param[out] none + \retval operation status +*/ +usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode) +{ + if (HOST_MODE == mode) { + USB_GUSBCS &= ~GUSBCS_FDM; + USB_GUSBCS |= GUSBCS_FHM; + } else if (DEVICE_MODE == mode) { + USB_GUSBCS &= ~GUSBCS_FHM; + USB_GUSBCS |= GUSBCS_FDM; + } else { + /* no operation */ + } + + if (NULL != pudev->mdelay) { + pudev->mdelay(50U); + } + + return USB_OK; +} + +#ifdef USE_HOST_MODE + +/*! + \brief initializes USB core for host mode + \param[in] pudev: pointer to selected usb host + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) +{ + uint32_t i = 0U; + __IO uint32_t nptxfifolen = 0U; + __IO uint32_t ptxfifolen = 0U; + +#ifdef USE_OTG_MODE + __IO uint32_t otgctl = 0; +#endif /* USE_OTG_MODE */ + + /* restart the PHY clock */ + USB_PWRCLKCTL = 0U; + + /* initialize host configuration register */ + if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { + USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ); + } else { + USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); + } + + /* reset USB port */ + usb_port_reset(pudev); + + /* configure data fifo sizes */ + if (USB_FS_CORE_ID == pudev->cfg.core_id) { + /* set rx fifo size */ + USB_GRFLEN = USBFS_RX_FIFO_SIZE; + + /* set non-periodic tx fifo size and address */ + nptxfifolen &= ~HNPTFLEN_HNPTXRSAR; + nptxfifolen |= USBFS_RX_FIFO_SIZE; + nptxfifolen &= ~HNPTFLEN_HNPTXFD; + nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16; + USB_HNPTFLEN = nptxfifolen; + + /* set periodic tx fifo size and address */ + ptxfifolen &= ~HPTFLEN_HPTXFSAR; + ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; + ptxfifolen &= ~HPTFLEN_HPTXFD; + ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16; + USB_HPTFLEN = ptxfifolen; + } + +#ifdef USE_OTG_MODE + + /* clear host set HNP enable bit in the USB OTG control register */ + otgctl |= GOTGCS_HHNPEN; + USB_GOTGCS &= ~otgctl; + USB_GOTGCS |= 0; + +#endif /* USE_OTG_MODE */ + + /* make sure the fifos are flushed */ + + /* flush all tx fifos in device or host mode */ + usb_txfifo_flush(pudev, 0x10U); + + /* flush the entire rx fifo */ + usb_rxfifo_flush(pudev); + + /* clear all pending host channel interrupts */ + USB_HACHINTEN &= ~HACHINTEN_CINTEN; + + for (i = 0U; i < pudev->cfg.host_channel_num; i++) { + USB_HCHxINTEN(i) = 0U; + USB_HCHxINTF(i) = 0xFFFFFFFFU; + } + +#ifndef USE_OTG_MODE + usb_vbus_drive(pudev, 1U); +#endif /* USE_OTG_MODE */ + + usb_hostint_enable(pudev); + + return USB_OK; +} + +/*! + \brief control the VBUS to power + \param[in] pudev: pointer to selected usb host + \param[in] state: VBUS state + \param[out] none + \retval none +*/ +void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state) +{ + __IO uint32_t host_port = 0U; + + /* enable or disable the external charge pump */ + if ((void *)0 != pudev->host.vbus_drive) { + pudev->host.vbus_drive(pudev, state); + } + + /* turn on the host port power. */ + host_port = USB_PORT_READ(); + + if ((0U == (host_port & HPCS_PP)) && (1U == state)) { + host_port |= HPCS_PP; + } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) { + host_port &= ~HPCS_PP; + } else { + /* no operation */ + } + + USB_HPCS = host_port; + + if (NULL != pudev->mdelay) { + pudev->mdelay(200U); + } +} + +/*! + \brief enables the host mode interrupts + \param[in] pudev: pointer to selected usb host + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) +{ + uint32_t gintf = 0U; + + /* disable all interrupts */ + USB_GINTEN = 0U; + + /* clear any pending interrupts */ + USB_GINTF = 0xFFFFFFFFU; + + /* enable the common interrupts */ + usb_commonint_enable(pudev); + + gintf |= GINTF_RXFNEIF; + + /* enable host_mode-related interrupts */ + gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF; + + USB_GINTEN &= ~gintf; + USB_GINTEN |= gintf; + + return USB_OK; +} + +/*! + \brief reset host port + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint32_t usb_port_reset (usb_core_handle_struct *pudev) +{ + __IO uint32_t hpcs; + + hpcs = USB_PORT_READ(); + + hpcs |= HPCS_PRST; + + USB_HPCS = hpcs; + + if (NULL != pudev->mdelay) { + pudev->mdelay(100U); + } + + hpcs &= ~HPCS_PRST; + + USB_HPCS = hpcs; + + if (NULL != pudev->mdelay) { + pudev->mdelay(20U); + } + + return USB_OK; +} + +/*! + \brief initialize host channel + \param[in] pudev: pointer to usb device + \param[in] hc_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num) +{ + uint8_t is_low_speed = 0U; + __IO uint32_t chinten = 0U; + __IO uint32_t chctl = 0U; + + usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; + + /* clear old interrupt conditions for this host channel */ + USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU; + + /* enable channel interrupts required for this transfer */ + switch (puhc->endp_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ + | HCHINTEN_DTERIE | HCHINTEN_NAKIE; + + if (puhc->endp_in) { + chinten |= HCHINTEN_BBERIE; + } else { + chinten |= HCHINTEN_NYETIE; + } + break; + + case USB_EPTYPE_INTR: + chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ + | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; + + if (puhc->endp_in) { + chinten |= HCHINTEN_BBERIE; + } + break; + + case USB_EPTYPE_ISOC: + chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; + + if (puhc->endp_in) { + chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; + } + break; + + default: + break; + } + + USB_HCHxINTEN((uint16_t)hc_num) = chinten; + + /* enable the top level host channel interrupt */ + USB_HACHINTEN |= 1U << hc_num; + + /* make sure host channel interrupts are enabled */ + USB_GINTEN |= GINTEN_HCIE; + + /* program the hcctlr register */ + chctl = 0U; + + if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) { + is_low_speed = 1U; + } + + chctl |= (uint32_t)puhc->dev_addr << 22U; + chctl |= (uint32_t)puhc->endp_type << 18U; + chctl |= (uint32_t)puhc->endp_id << 11U; + chctl |= (uint32_t)puhc->endp_in << 15U; + chctl |= (uint32_t)is_low_speed << 17U; + chctl |= puhc->endp_mps; + + if (HCCHAR_INTR == puhc->endp_type) { + chctl |= HCHCTL_ODDFRM; + } + + USB_HCHxCTL((uint16_t)hc_num) = chctl; + + return USB_OK; +} + +/*! + \brief prepare host channel for transferring packets + \param[in] pudev: pointer to usb device + \param[in] hc_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num) +{ + uint16_t dword_len = 0U; + uint16_t packet_num = 0U; + + __IO uint32_t chxlen = 0U; + __IO uint32_t chctl = 0U; + + usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; + + /* compute the expected number of packets associated to the transfer */ + if (puhc->xfer_len > 0U) { + packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps; + + if (packet_num > HC_MAX_PACKET_COUNT) { + packet_num = HC_MAX_PACKET_COUNT; + puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); + } + } else { + packet_num = 1U; + } + + if (puhc->endp_in) { + puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); + } + + /* initialize the host channel length register */ + chxlen &= ~HCHLEN_TLEN; + chxlen |= puhc->xfer_len; + chxlen &= ~HCHLEN_PCNT; + chxlen |= (uint32_t)packet_num << 19U; + chxlen &= ~HCHLEN_DPID; + chxlen |= (uint32_t)(puhc->DPID) << 29U; + USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen; + + /* set host channel enable */ + chctl = USB_HCHxCTL((uint16_t)hc_num); + + if (1U == USB_EVEN_FRAME()) { + chctl |= HCHCTL_ODDFRM; + } else { + chctl &= ~HCHCTL_ODDFRM; + } + + chctl |= HCHCTL_CEN; + chctl &= ~HCHCTL_CDIS; + USB_HCHxCTL((uint16_t)hc_num) = chctl; + + if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { + dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; + + switch (puhc->endp_type) { + /* non-periodic transfer */ + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + /* check if there is enough space in fifo space */ + if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + /* need to process data in non-periodic transfer fifo empty interrupt */ + USB_GINTEN |= GINTEN_NPTXFEIE; + } + break; + + /* periodic transfer */ + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + /* check if there is enough space in FIFO space */ + if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { + /* need to process data in periodic transfer fifo empty interrupt */ + USB_GINTEN |= GINTEN_PTXFEIE; + } + break; + + default: + break; + } + + /* write packet into the Tx FIFO. */ + usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); + } + + return USB_OK; +} + +/*! + \brief halt channel + \param[in] pudev: pointer to usb device + \param[in] hc_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num) +{ + uint8_t endp_type = 0U; + __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num); + + chctl |= HCHCTL_CEN | HCHCTL_CDIS; + + endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U); + + /* check for space in the request queue to issue the halt. */ + if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) { + if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + chctl &= ~HCHCTL_CEN; + } + } else { + if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { + chctl &= ~HCHCTL_CEN; + } + } + + USB_HCHxCTL((uint16_t)hc_num) = chctl; + + return USB_OK; +} + +/*! + \brief stop the USB host and clean up fifos + \param[in] none + \param[out] none + \retval none +*/ +void usb_host_stop(usb_core_handle_struct *pudev) +{ + uint32_t i; + + /* disable all host channel interrupt */ + USB_HACHINTEN = 0U; + USB_HACHINT = 0xFFFFFFFFU; + + /* flush out any leftover queued requests */ + for (i = 0U; i < pudev->cfg.host_channel_num; i++) { + USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR; + } + + /* flush the FIFO */ + usb_rxfifo_flush(pudev); + usb_txfifo_flush(pudev, 0x10U); +} + +#endif /* USE_HOST_MODE */ + + +#ifdef USE_DEVICE_MODE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = +{ + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); + +/*! + \brief initialize USB core registers for device mode + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) +{ + uint32_t i, ram_address = 0U; + __IO uint32_t devinep0intf = USB_DIEP0TFLEN; + __IO uint32_t devinepintf = 0U; + + /* restart the phy clock (maybe don't need to...) */ + USB_PWRCLKCTL = 0U; + + /* config periodic frmae interval to default */ + USB_DCFG &= ~DCFG_EOPFT; + USB_DCFG |= FRAME_INTERVAL_80; + + if (USB_FS_CORE_ID == pudev->cfg.core_id) { + /* set full speed PHY */ + USB_DCFG &= ~DCFG_DS; + USB_DCFG |= USB_SPEED_INP_FULL; + + /* set rx fifo size */ + USB_GRFLEN &= ~GRFLEN_RXFD; + USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE; + + /* set endpoint 0 tx fifo length and RAM address */ + devinep0intf &= ~DIEP0TFLEN_IEP0TXFD; + devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16; + devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR; + devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE; + + USB_DIEP0TFLEN = devinep0intf; + + ram_address = (uint32_t)RX_FIFO_FS_SIZE; + + /* set endpoint 1 to 3's tx fifo length and RAM address */ + for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) { + ram_address += USBFS_TX_FIFO_SIZE[i - 1U]; + + devinepintf &= ~DIEPTFLEN_IEPTXFD; + devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; + devinepintf &= ~DIEPTFLEN_IEPTXRSAR; + devinepintf |= ram_address; + + USB_DIEPxTFLEN(i) = devinepintf; + } + } + + /* make sure all fifos are flushed */ + + /* flush all tx fifos */ + usb_txfifo_flush(pudev, 0x10U); + + /* flush entire rx fifo */ + usb_rxfifo_flush(pudev); + + /* clear all pending device interrupts */ + USB_DIEPINTEN = 0U; + USB_DOEPINTEN = 0U; + USB_DAEPINT = 0xFFFFFFFFU; + USB_DAEPINTEN = 0U; + + /* configure all in/out endpoints */ + for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { + if (USB_DIEPxCTL(i) & DEPCTL_EPEN) { + USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + USB_DIEPxCTL(i) = 0U; + } + + if (USB_DOEPxCTL(i) & DEPCTL_EPEN) { + USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + USB_DOEPxCTL(i) = 0U; + } + + /* set in/out endpoint transfer length to 0 */ + USB_DIEPxLEN(i) = 0U; + USB_DOEPxLEN(i) = 0U; + + /* clear all pending in/out endpoints interrupts */ + USB_DIEPxINTF(i) = 0xFFU; + USB_DOEPxINTF(i) = 0xFFU; + } + + usb_devint_enable(pudev); + + return USB_OK; +} + +/*! + \brief enable the device mode interrupts + \param[in] pudev: pointer to usb device + \param[out] none + \retval status +*/ +static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) +{ + uint32_t int_mask = 0U; + + /* disable all interrupts */ + USB_GINTEN = 0U; + + /* clear any pending interrupts */ + USB_GINTF = 0xBFFFFFFFU; + + /* enable the common interrupts */ + usb_commonint_enable(pudev); + + int_mask = GINTEN_RXFNEIE; + + /* enable device_mode-related interrupts */ + int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \ + | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \ + | GINTEN_ISOINCIE; + +#ifdef VBUS_SENSING_ENABLED + int_mask |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + USB_GINTEN &= ~int_mask; + USB_GINTEN |= int_mask; + + return USB_OK; +} + +/*! + \brief configures endpoint 0 to receive setup packets + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_ep0_startout(usb_core_handle_struct *pudev) +{ + __IO uint32_t ep0len = 0U; + + /* set out endpoint 0 receive length to 24 bytes */ + ep0len &= ~DOEP0LEN_TLEN; + ep0len |= 8U * 3U; + + /* set out endpoint 0 receive length to 1 packet */ + ep0len &= ~DOEP0LEN_PCNT; + ep0len |= 1U << 19; + + /* set setup packet count to 3 */ + ep0len &= ~DOEP0LEN_STPCNT; + ep0len |= 3U << 29; + + USB_DOEPxLEN(0U) = ep0len; +} + +/*! + \brief active remote wakeup signalling + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_remotewakeup_active(usb_core_handle_struct *pudev) +{ + __IO uint32_t power_clock; + + if (pudev->dev.remote_wakeup) { + if (1U == (USB_DSTAT & DSTAT_SPST)) { + if (pudev->cfg.low_power) { + /* ungate USB core clock */ + power_clock = USB_PWRCLKCTL; + power_clock &= ~PWRCLKCTL_SHCLK; + power_clock &= ~PWRCLKCTL_SUCLK; + + USB_PWRCLKCTL = power_clock; + } + + /* active remote wakeup signaling */ + USB_DCTL |= DCTL_RWKUP; + + if (pudev->mdelay != (void *)0) { + pudev->mdelay(5U); + } + + USB_DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_clock_ungate(usb_core_handle_struct *pudev) +{ + if (pudev->cfg.low_power) { + __IO uint32_t power_clock; + + if (1U == (USB_DSTAT & DSTAT_SPST)) { + /* un-gate USB core clock */ + power_clock = USB_PWRCLKCTL; + power_clock &= ~PWRCLKCTL_SHCLK; + power_clock &= ~PWRCLKCTL_SUCLK; + + USB_PWRCLKCTL = power_clock; + } + } +} + +/*! + \brief stop the device and clean up fifos + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_device_stop (usb_core_handle_struct *pudev) +{ + uint32_t i; + + pudev->dev.status = 1U; + + for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { + USB_DIEPxINTF(i) = 0xFFU; + USB_DOEPxINTF(i) = 0xFFU; + } + + USB_DIEPINTEN = 0U; + USB_DOEPINTEN = 0U; + USB_DAEPINTEN = 0U; + USB_DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + usb_rxfifo_flush(pudev); + usb_txfifo_flush(pudev, 0x10U); +} +#endif /* USE_DEVICE_MODE */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c new file mode 100644 index 0000000000..366b1bbb3b --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c @@ -0,0 +1,503 @@ +/*! + \file usbd_core.c + \brief USB device mode core driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_core.h" +#include "usbd_std.h" + +/*! + \brief initailizes the USB device-mode handler stack + \param[in] pudev: pointer to usb device instance + \param[in] core_id: USB core ID + \param[out] none + \retval none +*/ +void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id) +{ + /* select USB core */ + usb_core_select (pudev, core_id); + + pudev->dev.status = USB_STATUS_DEFAULT; + + /* disable USB global interrupt */ + USB_GLOBAL_INT_DISABLE(); + + /* init the core (common init.) */ + usb_core_init(pudev); + + /* force device mode*/ + usb_mode_set(pudev, DEVICE_MODE); + + /* set device disconnect */ + USB_SOFT_DISCONNECT_ENABLE(); + + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(3U); + } + + /* init device */ + usb_devcore_init(pudev); + + /* set device Connect */ + USB_SOFT_DISCONNECT_DISABLE(); + + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(3U); + } + + /* enable USB global interrupt */ + USB_GLOBAL_INT_ENABLE(); +} + +/*! + \brief endpoint initialization + \param[in] pudev: pointer to usb device instance + \param[in] ep_desc: pointer to usb endpoint descriptor + \param[out] none + \retval none +*/ +void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc) +{ + usb_ep_struct *ep; + usb_dir_enum ep_dir; + + uint32_t devepinten = 0U; + uint32_t devepctl = 0U; + + uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU; + uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK; + uint16_t ep_mps = ep_desc->wMaxPacketSize; + + if (ep_desc->bEndpointAddress >> 7U) { + ep = &pudev->dev.in_ep[ep_num]; + + devepinten |= 1U << ep_num; + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + + ep_dir = USB_TX; + } else { + ep = &pudev->dev.out_ep[ep_num]; + + devepinten |= (1U << ep_num) << 16U; + devepctl = USB_DOEPxCTL((uint16_t)ep_num); + + ep_dir = USB_RX; + } + + /* if the endpoint is not active, need change the endpoint control register */ + if (!(devepctl & DEPCTL_EPACT)) { + devepctl &= ~DEPCTL_MPL; + devepctl |= ep_mps; + + devepctl &= ~DEPCTL_EPTYPE; + devepctl |= (uint32_t)ep_type << 18U; + + if (USB_TX == ep_dir) { + devepctl &= ~DIEPCTL_TXFNUM; + devepctl |= (uint32_t)ep_num << 22U; + } + + devepctl |= DEPCTL_SD0PID; + devepctl |= DEPCTL_EPACT; + } + + if (USB_TX == ep_dir) { + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + } else if (USB_RX == ep_dir) { + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; + } else { + /* no operation */ + } + + ep->endp_mps = ep_mps; + ep->endp_type = ep_type; + + /* enable the interrupts for this endpoint */ + USB_DAEPINTEN |= devepinten; +} + +/*! + \brief endpoint deinitialize + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval none +*/ +void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint32_t devepinten = 0U; + uint8_t ep_num = ep_addr & 0x7FU; + + if (ep_addr >> 7U) { + devepinten |= 1U << ep_num; + + USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; + } else { + devepinten |= (1U << ep_num) << 16U; + + USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; + } + + /* disable the interrupts for this endpoint */ + USB_DAEPINTEN &= ~devepinten; +} + +/*! + \brief endpoint prepare to receive data + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[in] pbuf: pointer to buffer + \param[in] buf_len: buffer length + \param[out] none + \retval none +*/ +void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + usb_ep_struct *ep; + uint8_t ep_num = ep_addr & 0x7FU; + uint32_t devepctl = 0U, devepxlen = 0U; + + ep = &pudev->dev.out_ep[ep_num]; + + /* setup and start the Xfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = buf_len; + ep->xfer_count = 0U; + + devepctl = USB_DOEPxCTL((uint16_t)ep_num); + devepxlen = USB_DOEPxLEN((uint16_t)ep_num); + + devepxlen &= ~DEPLEN_TLEN; + devepxlen &= ~DEPLEN_PCNT; + + /* zero length packet */ + if (0U == ep->xfer_len) { + /* set the transfer length to max packet size */ + devepxlen |= ep->endp_mps; + + /* set the transfer packet count to 1 */ + devepxlen |= 1U << 19U; + } else { + + if (0U == ep_num) { + /* set the transfer length to max packet size */ + devepxlen |= ep->endp_mps; + + /* set the transfer packet count to 1 */ + devepxlen |= 1U << 19U; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; + devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps; + } + } + + USB_DOEPxLEN((uint16_t)ep_num) = devepxlen; + + if (USB_EPTYPE_ISOC == ep->endp_type) { + if (ep->endp_frame) { + devepctl |= DEPCTL_SODDFRM; + } else { + devepctl |= DEPCTL_SEVNFRM; + } + } + + /* enable the endpoint and clear the NAK */ + devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[in] pbuf: pointer to buffer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) +{ + usb_ep_struct *ep; + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; + __IO uint32_t deveplen = 0U; + + ep = &pudev->dev.in_ep[ep_num]; + + /* setup and start the transfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = buf_len; + ep->xfer_count = 0U; + + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + deveplen = USB_DIEPxLEN((uint16_t)ep_num); + + /* clear transfer length to 0 */ + deveplen &= ~DEPLEN_TLEN; + + /* clear transfer packet to 0 */ + deveplen &= ~DEPLEN_PCNT; + + /* zero length packet */ + if (0U == ep->xfer_len) { + /* set transfer packet count to 1 */ + deveplen |= 1U << 19U; + } else { + if (0U == ep_num) { + if (ep->xfer_len > ep->endp_mps) { + ep->xfer_len = ep->endp_mps; + } + + deveplen |= 1U << 19U; + } else { + deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; + } + + /* configure the transfer size and packet count as follows: + * xfersize = N * maxpacket + short_packet + * pktcnt = N + (short_packet exist ? 1 : 0) + */ + deveplen |= ep->xfer_len; + + if (USB_EPTYPE_ISOC == ep->endp_type) { + deveplen |= DIEPLEN_MCNT & (1U << 29U); + } + } + + USB_DIEPxLEN((uint16_t)ep_num) = deveplen; + + if (USB_EPTYPE_ISOC == ep->endp_type) { + if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) { + devepctl |= DEPCTL_SODDFRM; + } else { + devepctl |= DEPCTL_SEVNFRM; + } + } + + /* enable the endpoint and clear the NAK */ + devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + + if (USB_EPTYPE_ISOC != ep->endp_type) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (ep->xfer_len > 0U) { + USB_DIEPFEINTEN |= 1U << ep_num; + } + } else { + usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len); + } +} + +/*! + \brief transmit data on the control channel + \param[in] pudev: pointer to usb device instance + \param[in] pbuf: pointer to buffer + \param[in] len: buffer length + \param[out] none + \retval usb device operation status +*/ +usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) +{ + usbd_status_enum ret = USBD_OK; + + pudev->dev.sum_len = len; + pudev->dev.remain_len = len; + pudev->dev.ctl_status = USB_CTRL_DATA_IN; + + usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len); + + return ret; +} + +/*! + \brief receive data on the control channel + \param[in] pudev: pointer to usb device instance + \param[in] pbuf: pointer to buffer + \param[in] len: buffer length + \param[out] none + \retval usb device operation status +*/ +usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) +{ + pudev->dev.sum_len = len; + pudev->dev.remain_len = len; + pudev->dev.ctl_status = USB_CTRL_DATA_OUT; + + usbd_ep_rx (pudev, 0U, pbuf, len); + + return USBD_OK; +} + +/*! + \brief transmit status on the control channel + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval usb device operation status +*/ +usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev) +{ + pudev->dev.ctl_status = USB_CTRL_STATUS_IN; + + usbd_ep_tx (pudev, 0U, NULL, 0U); + + usb_ep0_startout(pudev); + + return USBD_OK; +} + +/*! + \brief receive status on the control channel + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval usb device operation status +*/ +usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev) +{ + pudev->dev.ctl_status = USB_CTRL_STATUS_OUT; + + usbd_ep_rx (pudev, 0U, NULL, 0U); + + usb_ep0_startout(pudev); + + return USBD_OK; +} + +/*! + \brief set an endpoint to STALL status + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval none +*/ +void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; + + if (ep_addr >> 7U) { + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + + /* set the endpoint disable bit */ + if (devepctl & DEPCTL_EPEN) { + devepctl |= DEPCTL_EPD; + } + + /* set the endpoint stall bit */ + devepctl |= DEPCTL_STALL; + + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + } else { + /* set the endpoint stall bit */ + USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL; + } +} + +/*! + \brief clear endpoint stalled status + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval none +*/ +void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + usb_ep_struct *ep; + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; + + if(ep_addr >> 7U){ + ep = &pudev->dev.in_ep[ep_num]; + + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + + /* clear the in endpoint stall bits */ + devepctl &= ~DEPCTL_STALL; + + if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { + devepctl |= DEPCTL_SEVNFRM; + } + + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + } else { + ep = &pudev->dev.out_ep[ep_num]; + + devepctl = USB_DOEPxCTL((uint16_t)ep_num); + + /* clear the out endpoint stall bits */ + devepctl &= ~DEPCTL_STALL; + + if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { + devepctl |= DEPCTL_SEVNFRM; + } + + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; + } +} + +/*! + \brief flushes the fifos + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval none +*/ +void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + if (ep_addr >> 7U) { + usb_txfifo_flush(pudev, ep_addr & 0x7FU); + } else { + usb_rxfifo_flush(pudev); + } +} + +/*! + \brief get the received data length + \param[in] pudev: pointer to usb device instance + \param[in] ep_num: endpoint identifier which is in (0..3) + \param[out] none + \retval received data length +*/ +uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num) +{ + return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c new file mode 100644 index 0000000000..668ef35cd7 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c @@ -0,0 +1,663 @@ +/*! + \file usbd_int.c + \brief USB device mode interrupt routines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_int.h" +#include "usbd_std.h" + +/* interrupt handlers */ +static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev); + +static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num); + +#ifdef VBUS_SENSING_ENABLED + + static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev); + static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev); + +#endif /* VBUS_SENSING_ENABLED */ + +static usb_speed_enum USB_SPEED[4] = { + [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH, + [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL, + [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL, + [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW +}; + +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, + [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, + [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8 +}; + +/*! + \brief USB device-mode interrupts global service routine handler + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +uint32_t usbd_isr (usb_core_handle_struct *pudev) +{ + uint32_t retval = 0U; + uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN; + + /* ensure the core is in device mode */ + if (DEVICE_MODE == USB_CURRENT_MODE_GET()) { + int_status = gintf & ginten; + + /* there are no interrupts, avoid spurious interrupt */ + if (!int_status) { + return 0U; + } + + /* OUT endpoints interrupts */ + if (int_status & GINTF_OEPIF) { + retval |= usbd_intf_outep(pudev); + } + + /* IN endpoints interrupts */ + if (int_status & GINTF_IEPIF) { + retval |= usbd_intf_inep(pudev); + } + + /* mode mismatch interrupt */ + if (int_status & GINTF_MFIF) { + /* clear interrupt */ + USB_GINTF = GINTF_MFIF; + } + + /* early suspend interrupt */ + if (int_status & GINTF_ESP) { + retval |= usbd_intf_earlysuspend(pudev); + } + + /* suspend interrupt */ + if (int_status & GINTF_SP) { + retval |= usbd_intf_suspend(pudev); + } + + /* wakeup interrupt */ + if (int_status & GINTF_WKUPIF) { + retval |= usbd_intf_resume(pudev); + } + + /* start of frame interrupt */ + if (int_status & GINTF_SOF) { + retval |= usbd_intf_sof(pudev); + } + + /* reveive fifo not empty interrupt */ + if (int_status & GINTF_RXFNEIF) { + retval |= usbd_intf_rxfifo(pudev); + } + + /* USB reset interrupt */ + if (int_status & GINTF_RST) { + retval |= usbd_intf_reset(pudev); + } + + /* enumeration has been finished interrupt */ + if (int_status & GINTF_ENUMF) { + retval |= usbd_intf_enumfinish(pudev); + } + + /* incomplete synchronization in transfer interrupt*/ + if (int_status & GINTF_ISOINCIF) { + retval |= usbd_intf_isoinincomplete(pudev); + } + + /* incomplete synchronization out transfer interrupt*/ + if (int_status & GINTF_ISOONCIF) { + retval |= usbd_intf_isooutincomplete(pudev); + } + +#ifdef VBUS_SENSING_ENABLED + + /* session request interrupt */ + if (int_status & GINTF_SESIF) { + retval |= usbd_intf_sessionrequest(pudev); + } + + /* OTG mode interrupt */ + if (int_status & GINTF_OTGIF) { + retval |= usbd_intf_otg(pudev); + } +#endif /* VBUS_SENSING_ENABLED */ + } + + return retval; +} + +/*! + \brief indicates that an OUT endpoint has a pending interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev) +{ + uint8_t endp_num = 0U; + uint32_t endp_intr = 0U; + + __IO uint32_t out_endp_intr = 0U; + + /* read in the device interrupt bits */ + USB_DAOEP_INTR_READ(endp_intr); + + while (endp_intr) { + if (endp_intr & 0x1U) { + USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num); + + /* transfer complete interrupt */ + if (out_endp_intr & DOEPINTF_TF) { + USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF; + + /* data receive is completed */ + usbd_out_transaction(pudev, endp_num); + } + + /* endpoint disable interrupt */ + if (out_endp_intr & DOEPINTF_EPDIS) { + USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS; + } + + /* setup phase finished interrupt (just for control endpoints) */ + if (out_endp_intr & DOEPINTF_STPF) { + /* setup phase is completed */ + usbd_setup_transaction(pudev); + + USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF; + } + + /* back to back setup packets received */ + if (out_endp_intr & DOEPINTF_BTBSTP) { + USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP; + } + } + + endp_num ++; + endp_intr >>= 1; + } + + return 1U; +} + +/*! + \brief indicates that an in endpoint has a pending interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev) +{ + uint8_t endp_num = 0U; + uint32_t endp_intr = 0U; + + __IO uint32_t in_endp_intr = 0U; + + /* get all in endpoints which have interrupts */ + USB_DAIEP_INTR_READ(endp_intr); + + while (endp_intr) { + if (endp_intr & 0x1U) { + USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num); + + if (in_endp_intr & DIEPINTF_TF) { + /* disable the fifo empty interrupt for the endpoint */ + USB_DIEPFEINTEN &= ~(0x1U << endp_num); + + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF; + + /* data transmittion is completed */ + usbd_in_transaction(pudev, endp_num); + } + + if (in_endp_intr & DIEPINTF_CITO) { + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO; + } + + if (in_endp_intr & DIEPINTF_IEPNE) { + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE; + } + + if (in_endp_intr & DIEPINTF_EPDIS) { + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS; + } + + if (in_endp_intr & DIEPINTF_TXFE) { + usbd_emptytxfifo_write(pudev, endp_num); + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE; + } + } + + endp_num ++; + endp_intr >>= 1; + } + + return 1U; +} + +/*! + \brief indicates that early suspend state has been detected on the USB + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev) +{ + USB_GINTEN &= ~GINTEN_ESPIE; + USB_GINTF = GINTF_ESP; + + return 1U; +} + +/*! + \brief indicates that suspend state has been detected on the USB + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev) +{ + __IO uint8_t low_power = pudev->cfg.low_power; + __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST); + __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U; + + pudev->dev.prev_status = pudev->dev.status; + pudev->dev.status = USB_STATUS_SUSPENDED; + + if (low_power && suspend && is_configured) { + /* switch-off the otg clocks */ + USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + } + + /* clear interrupt */ + USB_GINTF = GINTF_SP; + + return 1U; +} + +/*! + \brief indicates that the USB controller has detected a resume or remote Wake-up sequence + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev) +{ + pudev->dev.status = pudev->dev.prev_status; + pudev->dev.status = USB_STATUS_CONFIGURED; + + /* clear interrupt */ + USB_GINTF = GINTF_WKUPIF; + + return 1U; +} + +/*! + \brief handle the SOF interrupts + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev) +{ + if (NULL != usbd_int_fops) { + usbd_int_fops->SOF(pudev); + } + + USB_GINTF = GINTF_SOF; + + return 1U; +} + +/*! + \brief handle the rx status queue level interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) +{ + usb_ep_struct *ep; + uint8_t data_pid = 0U, endp_num = 0U; + uint32_t bcount = 0U, packet_num = 0U; + + /* get the status from the top of the fifo (must be read to a variable) */ + __IO uint32_t rx_status = USB_GRSTATP; + + /* disable the rx fifo non-empty interrupt */ + USB_GINTEN &= ~GINTEN_RXFNEIE; + + endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM); + bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U; + data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U); + + /* ensure no-DMA mode can work */ + packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT; + if ((1U == endp_num) && (0U == packet_num)) { + uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num); + + devepctl |= DEPCTL_SNAK; + devepctl &= ~DEPCTL_EPEN; + devepctl &= ~DEPCTL_EPD; + + USB_DOEPxCTL((uint16_t)endp_num) = devepctl; + } + + ep = &pudev->dev.out_ep[endp_num]; + + switch ((rx_status & GRSTATRP_RPCKST) >> 17U) { + case RXSTAT_GOUT_NAK: + break; + case RXSTAT_DATA_UPDT: + if (bcount > 0U) { + usb_fifo_read(ep->xfer_buff, (uint16_t)bcount); + ep->xfer_buff += bcount; + ep->xfer_count += bcount; + } + break; + case RXSTAT_XFER_COMP: + break; + case RXSTAT_SETUP_COMP: + break; + case RXSTAT_SETUP_UPDT: + *(uint32_t *)0x5000081CU |= 0x00020000U; + if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) { + /* copy the setup packet received in fifo into the setup buffer in ram */ + usb_fifo_read(pudev->dev.setup_packet, 8U); + + ep->xfer_count += bcount; + } + break; + default: + break; + } + + /* enable the rx fifo non-empty interrupt */ + USB_GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle USB reset interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) +{ + uint8_t i = 0U; + usb_ep_struct *ep; + + /* clear the remote wakeup signaling */ + USB_DCTL &= ~DCTL_RWKUP; + + /* flush the tx fifo */ + usb_txfifo_flush(pudev, 0U); + + for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { + USB_DIEPxINTF((uint16_t)i) = 0xFFU; + USB_DOEPxINTF((uint16_t)i) = 0xFFU; + } + + /* clear all pending device endpoint interrupts */ + USB_DAEPINT = 0xFFFFFFFFU; + + /* enable endpoint 0 interrupts */ + USB_DAEPINTEN &= ~DAEPINTEN_OEPIE; + USB_DAEPINTEN &= ~DAEPINTEN_IEPIE; + USB_DAEPINTEN = (1U << 16) | 1U; + + /* enable out endpoint interrupts */ + USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; + + /* enable in endpoint interrupts */ + USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; + + /* reset device address */ + USB_DCFG &= ~DCFG_DAR; + USB_DCFG |= 0U << 4U; + + /* configure endpoint 0 to receive setup packets */ + usb_ep0_startout(pudev); + + /* clear usb reset interrupt */ + USB_GINTF = GINTF_RST; + + /* open EP0 IN */ + ep = &pudev->dev.in_ep[0]; + + USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL; + USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE; + USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM; + + if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) { + USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE; + USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); + USB_DIEPxCTL(0U) |= DEP0CTL_EPACT; + } + + ep->endp_mps = USB_MAX_EP0_SIZE; + ep->endp_type = USB_EPTYPE_CTRL; + + /* open EP0 OUT */ + ep = &pudev->dev.out_ep[0]; + + USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL; + USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE; + + if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) { + USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE; + USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); + USB_DOEPxCTL(0U) |= DEP0CTL_EPACT; + } + + ep->endp_mps = USB_MAX_EP0_SIZE; + ep->endp_type = USB_EPTYPE_CTRL; + + pudev->dev.status = USB_STATUS_DEFAULT; + + return 1U; +} + +/*! + \brief handle enumeration finish interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev) +{ + uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U); + + /* set the max packet size of devie in endpoint based on the enumeration speed */ + USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed]; + + /* clear global in NAK */ + USB_DCTL &= ~DCTL_CGINAK; + USB_DCTL |= DCTL_CGINAK; + + /* set USB turn-around time based on device speed and PHY interface */ + if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) { + pudev->cfg.core_speed = USB_CORE_SPEED_HIGH; + pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE; + + USB_GUSBCS &= ~GUSBCS_UTT; + USB_GUSBCS |= 0x09U << 10; + } else { + pudev->cfg.core_speed = USB_CORE_SPEED_FULL; + pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; + + USB_GUSBCS &= ~GUSBCS_UTT; + USB_GUSBCS |= 0x05U << 10; + } + + /* clear interrupt */ + USB_GINTF = GINTF_ENUMF; + + return 1U; +} + +/*! + \brief handle the ISO in incomplete interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev) +{ + + /* clear interrupt */ + USB_GINTF = GINTF_ISOINCIF; + + return 1U; +} + +/*! + \brief handle the ISO OUT incomplete interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev) +{ + /* clear interrupt */ + USB_GINTF = GINTF_ISOONCIF; + + return 1U; +} + +/*! + \brief check FIFO for the next packet to be loaded + \param[in] pudev: pointer to usb device instance + \param[in] ep_id: endpoint identifier which is in (0..3) + \param[out] none + \retval status +*/ +static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num) +{ + uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U; + usb_ep_struct *ep; + + ep = &pudev->dev.in_ep[ep_num]; + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->endp_mps) { + len = ep->endp_mps; + } + + word_len = (len + 3U) / 4U; + + while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) && + (ep->xfer_count < ep->xfer_len)) { + /* write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->endp_mps) { + len = ep->endp_mps; + } + + word_len = (len + 3U) / 4U; + + usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len); + + ep->xfer_buff += len; + ep->xfer_count += len; + + if(ep->xfer_len == ep->xfer_count) { + fifo_empty_mask = 0x1U << ep_num; + USB_DIEPFEINTEN &= ~fifo_empty_mask; + } + } + + return 1U; +} + +#ifdef VBUS_SENSING_ENABLED + +/*! + \brief indicates that the USB_OTG controller has detected a connection + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev) +{ + pudev->dev.connection_status = 1U; + + /* clear the interrupt bit */ + USB_GINTF = GINTF_SESIF; + + return 1; +} + +/*! + \brief indicates that the USB_OTG controller has detected an OTG event + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev) +{ + if (USB_GOTGINTF & GOTGINTF_SESEND) { + pudev->dev.class_deinit(pudev, 0); + pudev->dev.connection_status = 0; + } + + /* clear OTG interrupt */ + USB_GOTGINTF |= GOTGINTF_SESEND; + + return 1; +} + +#endif /* VBUS_SENSING_ENABLED */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c new file mode 100644 index 0000000000..33ad7a94b6 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c @@ -0,0 +1,727 @@ +/*! + \file usbd_std.c + \brief USB 2.0 standard handler driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_std.h" +#include "usb_core.h" + +static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); + +static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req); + +static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req); + +static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); +static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); +static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); + +static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) = +{ + usbd_getstatus, + usbd_clrfeature, + usbd_reserved, + usbd_setfeature, + usbd_reserved, + usbd_setaddress, + usbd_getdescriptor, + usbd_setdescriptor, + usbd_getconfig, + usbd_setconfig, + usbd_getinterface, + usbd_setinterface, + usbd_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = +{ + usbd_device_descriptor_get, + usbd_configuration_descriptor_get, + usbd_string_descriptor_get +}; + +/*! + \brief USB setup stage processing + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev) +{ + usb_device_req_struct req; + + usbd_setup_request_parse(pudev, &req); + + switch (req.bmRequestType & USB_REQ_MASK) { + /* standard device request */ + case USB_STANDARD_REQ: + usbd_standard_request(pudev, &req); + break; + /* device class request */ + case USB_CLASS_REQ: + usbd_device_class_request(pudev, &req); + break; + /* vendor defined request */ + case USB_VENDOR_REQ: + usbd_vendor_request(pudev, &req); + break; + default: + usbd_ep_stall(pudev, req.bmRequestType & 0x80U); + break; + } + + return USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] pudev: pointer to USB device instance + \param[in] ep_id: endpoint identifier(0..7) + \param[out] none + \retval USB device operation status +*/ +usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) +{ + usb_ep_struct *ep; + + if (0U == endp_num) { + ep = &pudev->dev.out_ep[0]; + + if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) { + if (pudev->dev.remain_len > ep->endp_mps) { + pudev->dev.remain_len -= ep->endp_mps; + + usbd_ep_rx (pudev, + 0U, + ep->xfer_buff, + (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps)); + } else { + if (USB_STATUS_CONFIGURED == pudev->dev.status) { + pudev->dev.class_data_handler(pudev, USB_RX, 0U); + } + + usbd_ctlstatus_tx(pudev); + } + } + } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { + pudev->dev.class_data_handler(pudev, USB_RX, endp_num); + } else { + /* no operation */ + } + + return USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] pudev: pointer to USB device instance + \param[in] ep_id: endpoint identifier(0..7) + \param[out] none + \retval USB device operation status +*/ +usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) +{ + usb_ep_struct *ep; + + if (0U == endp_num) { + ep = &pudev->dev.in_ep[0]; + + if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) { + if (pudev->dev.remain_len > ep->endp_mps) { + pudev->dev.remain_len -= ep->endp_mps; + + usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len); + + usbd_ep_rx (pudev, 0U, NULL, 0U); + } else { + /* last packet is MPS multiple, so send ZLP packet */ + if ((pudev->dev.sum_len % ep->endp_mps == 0U) && + (pudev->dev.sum_len >= ep->endp_mps) && + (pudev->dev.sum_len < pudev->dev.ctl_len)) { + usbd_ep_tx (pudev, 0U, NULL, 0U); + pudev->dev.ctl_len = 0U; + + usbd_ep_rx (pudev, 0U, NULL, 0U); + } else { + if (USB_STATUS_CONFIGURED == pudev->dev.status) { + pudev->dev.class_data_handler(pudev, USB_TX, 0U); + } + + usbd_ctlstatus_rx(pudev); + } + } + } + } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { + pudev->dev.class_data_handler(pudev, USB_TX, endp_num); + } else { + /* no operation */ + } + + return USBD_OK; +} + +/*! + \brief handle USB standard device request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device operation status +*/ +static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* call device request handle function */ + (*StandardDeviceRequest[req->bRequest])(pudev, req); + + return USBD_OK; +} + +/*! + \brief handle USB device class request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device operation status +*/ +static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + usbd_status_enum ret = USBD_OK; + + switch (pudev->dev.status) { + case USB_STATUS_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req)); + + if ((0U == req->wLength) && (USBD_OK == ret)) { + /* no data stage */ + usbd_ctlstatus_tx(pudev); + } + } else { + usbd_enum_error(pudev, req); + } + break; + + default: + usbd_enum_error(pudev, req); + break; + } + + return ret; +} + +/*! + \brief handle USB vendor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device operation status +*/ +static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* added by user... */ + + return USBD_OK; +} + +/*! + \brief no operation, just for reserved + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no operation... */ +} + +/*! + \brief get the device descriptor + \brief[in] index: no use + \param[in] none + \param[out] pLen: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + *pLen = pudev->dev.dev_desc[0]; + + return pudev->dev.dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] index: no use + \param[in] none + \param[out] pLen: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + *pLen = pudev->dev.config_desc[2]; + + return pudev->dev.config_desc; +} + +/*! + \brief get string descriptor + \param[in] index: string descriptor index + \param[in] pLen: pointer to string length + \param[out] none + \retval none +*/ +static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + uint8_t *desc = pudev->dev.strings[index]; + + *pLen = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ +} + +/*! + \brief handle USB Clear_Feature request + \param[in] pudev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval none +*/ +static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr = 0U; + + switch (req->bmRequestType & USB_REQTYPE_MASK) { + /* process device feature */ + case USB_REQTYPE_DEVICE: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + case USB_STATUS_CONFIGURED: + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + pudev->dev.remote_wakeup = 0U; + pudev->dev.class_req_handler(pudev, req); + + usbd_ctlstatus_tx(pudev); + } + break; + + default: + usbd_enum_error(pudev, req); + break; + } + break; + /* process interface feature */ + case USB_REQTYPE_INTERFACE: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USB_STATUS_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* no operation */ + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + /* process endpoint feature */ + case USB_REQTYPE_ENDPOINT: + ep_addr = LOWBYTE(req->wIndex); + + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_stall(pudev, ep_addr); + } + break; + case USB_STATUS_CONFIGURED: + if (USB_FEATURE_ENDP_HALT == req->wValue) { + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_clear_stall(pudev, ep_addr); + + pudev->dev.class_req_handler(pudev, req); + } + } + usbd_ctlstatus_tx(pudev); + break; + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Set_Feature request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr = 0U; + __IO uint32_t DctlrStatus; + + switch (req->bmRequestType & USB_REQ_MASK) { + /* process device feature */ + case USB_REQTYPE_DEVICE: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + case USB_STATUS_CONFIGURED: + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + pudev->dev.remote_wakeup = 1U; + pudev->dev.class_req_handler(pudev, req); + + usbd_ctlstatus_tx(pudev); + } else if ((req->wValue == USB_FEATURE_TEST_MODE) && + (0U == (req->wIndex & 0xFFU))) { + DctlrStatus = USB_DCTL; + + usbd_ctlstatus_tx(pudev); + } else { + /* no operation */ + } + break; + default: + break; + } + break; + /* process interface feature */ + case USB_REQTYPE_INTERFACE: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USB_STATUS_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* no operation */ + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + /* process endpoint feature */ + case USB_REQTYPE_ENDPOINT: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_stall(pudev, ep_addr); + } + break; + case USB_STATUS_CONFIGURED: + if (USB_FEATURE_ENDP_HALT == req->wValue) { + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_stall(pudev, ep_addr); + } + } + pudev->dev.class_req_handler(pudev, req); + + usbd_ctlstatus_tx(pudev); + break; + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Set_Address request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t DevAddr; + + if ((0U == req->wIndex) && (0U == req->wLength)) { + DevAddr = (uint8_t)(req->wValue) & 0x7FU; + + if (USB_STATUS_CONFIGURED == pudev->dev.status) { + usbd_enum_error(pudev, req); + } else { + USB_SET_DEVADDR((uint32_t)DevAddr); + + usbd_ctlstatus_tx(pudev); + + if (0U != DevAddr) { + pudev->dev.status = USB_STATUS_ADDRESSED; + } else { + pudev->dev.status = USB_STATUS_DEFAULT; + } + } + } else { + usbd_enum_error(pudev, req); + } +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) { + uint8_t desc_type = (uint8_t)(req->wValue >> 8); + uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; + + if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { + uint16_t len; + uint8_t *pbuf; + + /* call corresponding descriptor get function */ + pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); + + if ((0U != len) && (0U != req->wLength)) { + len = USB_MIN(len, req->wLength); + + if ((1U == desc_type) && (64U == req->wLength)) { + len = 8U; + } + + usbd_ctltx(pudev, pbuf, len); + } + } else { + usbd_enum_error(pudev, req); + } + } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) { + pudev->dev.class_req_handler(pudev, req); + } else { + /* no operation */ + } +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no handle... */ +} + +/*! + \brief handle USB Get_Configuration request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint32_t USBD_default_config = 0U; + + if (1U != req->wLength) { + usbd_enum_error(pudev, req); + } else { + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U); + break; + case USB_STATUS_CONFIGURED: + usbd_ctltx(pudev, &pudev->dev.config_num, 1U); + break; + default: + usbd_enum_error(pudev, req); + break; + } + } +} + +/*! + \brief handle USB Set_Configuration request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + /* if config index is more than configuration max number */ + if (cfgidx > USBD_CFG_MAX_NUM) { + usbd_enum_error(pudev, req); + } else { + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + if (cfgidx) { + pudev->dev.config_num = cfgidx; + pudev->dev.status = USB_STATUS_CONFIGURED; + pudev->dev.class_init(pudev, cfgidx); + } + + usbd_ctlstatus_tx(pudev); + break; + case USB_STATUS_CONFIGURED: + if (0U == cfgidx) { + pudev->dev.status = USB_STATUS_ADDRESSED; + pudev->dev.config_num = cfgidx; + pudev->dev.class_deinit(pudev, cfgidx); + } else if (cfgidx != pudev->dev.config_num) { + /* clear old configuration */ + pudev->dev.class_deinit(pudev, pudev->dev.config_num); + + /* set new configuration */ + pudev->dev.config_num = cfgidx; + pudev->dev.class_init(pudev, cfgidx); + } else { + /* no operation */ + } + + usbd_ctlstatus_tx(pudev); + break; + default: + usbd_enum_error(pudev, req); + break; + } + } +} + +/*! + \brief handle USB Get_Interface request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + pudev->dev.class_req_handler(pudev, req); +} + +/*! + \brief handle USB Set_Interface request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + pudev->dev.class_req_handler(pudev, req); +} + +/*! + \brief handle USB SynchFrame request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no handle... */ +} + +/*! + \brief decode setup data packet + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t *psetup = pudev->dev.setup_packet; + + req->bmRequestType = *psetup; + req->bRequest = *(uint8_t *)(psetup + 1U); + req->wValue = SWAPBYTE (psetup + 2U); + req->wIndex = SWAPBYTE (psetup + 4U); + req->wLength = SWAPBYTE (psetup + 6U); + + pudev->dev.ctl_len = req->wLength; +} + +/*! + \brief handle USB low level error event + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + usbd_ep_stall(pudev, 0x80U); + usbd_ep_stall(pudev, 0x00U); + usb_ep0_startout(pudev); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c new file mode 100644 index 0000000000..de41f72273 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c @@ -0,0 +1,737 @@ +/*! + \file usbh_core.c + \brief this file implements the functions for the core state machine process + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hcs.h" +#include "usbh_core.h" +#include "usbh_int.h" +#include "stdio.h" +#include "usbh_std.h" +#include "usbh_ctrl.h" +#include "usb_core.h" + +extern class_polling_fun_cb_struct class_polling_cb; + +uint8_t usbh_sof (usb_core_handle_struct *pudev); +uint8_t usbh_connected (usb_core_handle_struct *pudev); +uint8_t usbh_disconnected (usb_core_handle_struct *pudev); + +usbh_hcd_int_cb_struct usbh_hcd_int_cb = +{ + usbh_sof, + usbh_connected, + usbh_disconnected, +}; + +usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb; +extern usbh_state_handle_struct usbh_state_core; + +static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); + +static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); + +/* the host state handle function array */ +void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = +{ + host_idle_handle, + host_dev_attached_handle, + host_dev_detached_handle, + host_detect_dev_speed_handle, + host_enum_handle, + host_class_request_handle, + host_class_handle, + host_user_input_handle, + host_suspended_handle, + host_error_handle, +}; + +/* the host state handle table */ +state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] = +{ + /* the current state the current event the next state the event function */ + {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move }, + {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move }, + {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move }, + {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move }, + {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move }, + {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, + {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, + {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, + {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, +}; + +/*! + \brief the polling function of host state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + void *pustate) +{ + usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate; + + scd_begin(p_state, HOST_FSM_ID); + + if (-1 == p_state->usbh_current_state_stack_top) { + uint8_t cur_state = p_state->usbh_current_state; + + if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) { + if (HOST_DEV_DETACHED != cur_state) { + p_state->usbh_current_state = HOST_DEV_DETACHED; + cur_state = HOST_DEV_DETACHED; + } + } + + host_state_handle[cur_state](pudev, puhost, p_state); + } else { + uint8_t stack0_state = p_state->stack[0].state; + + if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) { + if (HOST_DEV_DETACHED != stack0_state) { + p_state->stack[0].state = HOST_DEV_DETACHED; + stack0_state = HOST_DEV_DETACHED; + p_state->usbh_current_state = HOST_DEV_DETACHED; + } + } + + host_state_handle[stack0_state](pudev, puhost, p_state); + } + + return USBH_OK; +} + +/*! + \brief the handle function of HOST_IDLE state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_idle_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + if (hcd_is_device_connected(pudev)) { + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state); + + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(100U); + } + } +} + +/*! + \brief the handle function of HOST_DEV_ATTACHED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_dev_attached_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usr_cb->device_connected(); + puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U); + puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U); + + /* reset usb device */ + if (0U == usb_port_reset(pudev)) { + puhost->usr_cb->device_reset(); + + /* wait for USB USBH_ISR_PrtEnDisableChange() + * host is now ready to start the enumeration + */ + puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET(); + puhost->usr_cb->device_speed_detected(puhost->device.speed); + + /* open in control pipes */ + usbh_channel_open (pudev, + puhost->control.hc_in_num, + puhost->device.address, + puhost->device.speed, + USB_EPTYPE_CTRL, + (uint16_t)puhost->control.ep0_size); + + /* open out control pipes */ + usbh_channel_open (pudev, + puhost->control.hc_out_num, + puhost->device.address, + puhost->device.speed, + USB_EPTYPE_CTRL, + (uint16_t)puhost->control.ep0_size); + + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of HOST_ENUMERATION state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_enum_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) { + puhost->usr_cb->enumeration_finish(); + scd_event_handle(pudev, + puhost, + pustate, + HOST_EVENT_USER_INPUT, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of HOST_USER_INPUT state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_user_input_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) { + if (USBH_OK == (puhost->class_init(pudev, puhost))) { + scd_event_handle(pudev, + puhost, + pustate, + HOST_EVENT_CLASS_REQ, + pustate->usbh_current_state); + } + } +} + +/*! + \brief the handle function of HOST_CLASS_REQUEST state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_class_request_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) { + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of HOST_CLASS state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_class_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + class_state_polling_fun(pudev, puhost, pustate); +} + +/*! + \brief the handle function of HOST_SUSPENDED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_suspended_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + /* no operation */ +} + +/*! + \brief the handle function of HOST_ERROR state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_error_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + /* re-initilaize host for new enumeration */ + usbh_deinit (pudev, puhost,&usbh_state_core); + puhost->usr_cb->deinit(); + puhost->class_deinit(pudev, &puhost->device); + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); +} + +/*! + \brief the handle function of HOST_DEV_DETACHED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_dev_detached_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + /* manage user disconnect operations*/ + puhost->usr_cb->device_disconnected(); + + /* re-initilaize host for new enumeration */ + usbh_deinit(pudev, puhost,&usbh_state_core); + puhost->usr_cb->deinit(); + puhost->class_deinit(pudev, &puhost->device); + usbh_allchannel_dealloc(pudev); + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); +} + +/*! + \brief the handle function of HOST_DETECT_DEV_SPEED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + /* no operation */ +} + +/*! + \brief usb connect callback function from the interrupt. + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_connected (usb_core_handle_struct *pudev) +{ + pudev->host.connect_status = 1U; + + return 0U; +} + +/*! + \brief usb disconnect callback function from the interrupt. + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_disconnected (usb_core_handle_struct *pudev) +{ + pudev->host.connect_status = 0U; + + return 0U; +} + +/*! + \brief usb sof callback function from the interrupt. + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_sof (usb_core_handle_struct *pudev) +{ + /* this callback could be used to implement a scheduler process */ + return 0U; +} + +/*! + \brief initialize the host portion of the driver. + \param[in] pudev: pointer to usb device + \param[in] core_id: usb otg core identifier(high-speed or full-speed) + \param[out] none + \retval operation status +*/ +uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id) +{ + pudev->host.connect_status = 0U; + + pudev->host.host_channel[0].endp_mps = 8U; + + usb_core_select(pudev, core_id); + +#ifndef DUAL_ROLE_MODE_ENABLED + + USB_GLOBAL_INT_DISABLE(); + + usb_core_init(pudev); + + /* force host mode*/ + usb_mode_set(pudev, HOST_MODE); + + usb_hostcore_init(pudev); + + USB_GLOBAL_INT_ENABLE(); + +#endif + + return 0U; +} + +/*! + \brief check if the device is connected. + \param[in] pudev: pointer to usb device + \param[out] none + \retval device connection status. 1 -> connected and 0 -> disconnected +*/ +uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev) +{ + return (uint32_t)(pudev->host.connect_status); +} + +/*! + \brief this function returns the last URBstate + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval urb_state_enum +*/ +urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + return pudev->host.host_channel[channel_num].urb_state; +} + +/*! + \brief this function returns the last URBstate + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval No. of data bytes transferred +*/ +uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + return pudev->host.host_channel[channel_num].xfer_count; +} + +/*! + \brief de-initialize host + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[out] none + \retval host status +*/ +usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct* pustate) +{ + /* software init */ + + puhost->control.ep0_size = USB_MAX_EP0_SIZE; + + puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT; + puhost->device.speed = HPRT_PRTSPD_FULL_SPEED; + + usbh_channel_free(pudev, puhost->control.hc_in_num); + usbh_channel_free(pudev, puhost->control.hc_out_num); + + scd_init(pustate); + scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE); + scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE); + scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE); + + scd_begin(pustate,HOST_FSM_ID); + scd_state_move(pustate, HOST_IDLE); + + return USBH_OK; +} + +/*! + \brief state core driver init + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +void scd_init(usbh_state_handle_struct* pustate) +{ + /* init the state core */ + pustate->usbh_current_state = 0U; + pustate->usbh_current_state_table = NULL; + pustate->usbh_current_state_table_size = 0U; + + pustate->usbh_current_state_stack_top = -1; + pustate->stack->state = 0U; + pustate->stack->table_size = 0U; + pustate->stack->table = NULL; + + pustate->usbh_regist_state_table_num = 0U; + pustate->usbh_regist_state_table->table = NULL; + pustate->usbh_regist_state_table->table_size = 0U; + pustate->usbh_regist_state_table->id = 0U; + + /* init the control and the enumeration polling handle flag */ + ctrl_polling_handle_flag = 0U; + enum_polling_handle_flag = 0U; +} + +/*! + \brief state core driver table regist + \param[in] pustate: pointer to usb state driver + \param[in] pstate_table: pointer to the table to regist + \param[in] table_id: the id of the table to regist + \param[in] current_table_size: the size of the current table to regist + \param[out] none + \retval none +*/ +void scd_table_regist (usbh_state_handle_struct* pustate, + state_table_struct* pstate_table, + uint8_t table_id, + uint8_t current_table_size) +{ + usbh_state_regist_table_struct *cur_state_reg_table; + + cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num]; + + cur_state_reg_table->id = table_id; + cur_state_reg_table->table = pstate_table; + cur_state_reg_table->table_size = current_table_size; + + pustate->usbh_regist_state_table_num++; +} + +/*! + \brief state core driver begin + \param[in] pustate: pointer to usb state driver + \param[in] table_id: the id of the table to begin + \param[out] none + \retval none +*/ +void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id) +{ + uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num; + usbh_state_regist_table_struct *cur_state_reg_table; + + for (i = 0U; i < table_num; i++) { + cur_state_reg_table = &pustate->usbh_regist_state_table[i]; + + if (table_id == cur_state_reg_table->id) { + pustate->usbh_current_state_table = cur_state_reg_table->table; + pustate->usbh_current_state_table_size = cur_state_reg_table->table_size; + break; + } + } +} + +/*! + \brief state core driver move state + \param[in] pustate: pointer to usb state driver + \param[in] state: the state to move + \param[out] none + \retval none +*/ +void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state) +{ + pustate->usbh_current_state = state; +} + +/*! + \brief state core driver event handle + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[in] event: the current event + \param[in] state: the current state + \param[out] none + \retval host status +*/ +usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct* pustate, + uint8_t event, + uint8_t state) +{ + uint8_t i = 0U; + ACT_FUN event_act_fun = NULL; + state_table_struct *backup_state_t = pustate->usbh_current_state_table; + state_table_struct *executive_state_table = pustate->usbh_current_state_table; + + /* look up the table to find the action function */ + for (i = 0U; i < pustate->usbh_current_state_table_size; i++) { + if (state == executive_state_table->cur_state) { + if (event == executive_state_table->cur_event) { + state = executive_state_table->next_state; + event_act_fun = executive_state_table->event_action_fun; + break; + } else { + executive_state_table++; + } + } else { + executive_state_table++; + } + } + + pustate->usbh_current_state_table = backup_state_t; + + /* if the action function is not NULL, execute the action function */ + if (event_act_fun) { + if (event_act_fun == &only_state_move) { + pustate->usbh_current_state = state; + } else { + return event_act_fun(pudev, puhost, pustate); + } + } + + return USBH_BUSY; +} + +/*! + \brief state core driver table push + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +void scd_table_push(usbh_state_handle_struct* pustate) +{ + usbh_state_stack_struct *top_state_element; + + if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) { + pustate->usbh_current_state_stack_top++; + + top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; + + /* put the current state table into the state stack */ + top_state_element->state = pustate->usbh_current_state; + top_state_element->table = pustate->usbh_current_state_table; + top_state_element->table_size = pustate->usbh_current_state_table_size; + } +} + +/*! + \brief state core driver table pop + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +void scd_table_pop (usbh_state_handle_struct* pustate) +{ + usbh_state_stack_struct *top_state_element; + + top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; + + if (pustate->usbh_current_state_stack_top > -1) { + /* get the current state table from the state stack */ + pustate->usbh_current_state = top_state_element->state; + pustate->usbh_current_state_table = top_state_element->table; + pustate->usbh_current_state_table_size = top_state_element->table_size; + pustate->usbh_current_state_stack_top--; + } +} +/*! + \brief the polling function of class req state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval host status +*/ +static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + return class_polling_cb.class_req_polling(pudev, puhost, pustate); +} + +/*! + \brief the polling function of class state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval host status +*/ +static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + return class_polling_cb.class_polling(pudev, puhost, pustate); +} + +/*! + \brief the function is only used to state move + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + return USBH_OK; +} + +/*! + \brief the function to the up state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + scd_table_pop((usbh_state_handle_struct *)pustate); + + return USBH_OK; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c new file mode 100644 index 0000000000..3f5277701f --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c @@ -0,0 +1,639 @@ +/*! + \file usbh_ctrl.c + \brief this file implements the functions for the control transmit process + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_core.h" +#include "usbh_std.h" +#include "usbh_ctrl.h" + +uint8_t ctrl_polling_handle_flag = 0U; +uint8_t ctrl_setup_wait_flag = 0U; +uint8_t ctrl_data_wait_flag = 0U; +uint8_t ctrl_status_wait_flag = 0U; + +static uint16_t timeout = 0U; + +static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); + +/* the ctrl state handle function array */ +void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) = +{ + ctrl_idle_handle, + ctrl_setup_handle, + ctrl_data_handle, + ctrl_status_handle, + ctrl_error_handle, + ctrl_stalled_handle, + ctrl_complete_handle, +}; + +/* the ctrl state handle table */ +state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] = +{ + /* the current state the current event the next state the event function */ + {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move }, + {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move }, + {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, + {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, + {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, + {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, + {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, + {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move }, + {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, + {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, + {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, + {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, + {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, +}; + +/*! + \brief the polling function of CTRL state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + void *pustate) +{ + usbh_status_enum exe_state = USBH_BUSY; + usbh_state_handle_struct *p_state; + + p_state = (usbh_state_handle_struct *)pustate; + + /* if first enter this function, begin the ctrl state */ + if (0U == ctrl_polling_handle_flag) { + ctrl_polling_handle_flag = 1U; + scd_table_push(p_state); + scd_state_move(p_state, CTRL_IDLE); + } + + /* base on the current state to handle the ctrl state */ + scd_begin(p_state, CTRL_FSM_ID); + ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); + + /* determine the control transfer whether to complete */ + switch (puhost->usbh_backup_state.ctrl_backup_state) { + case CTRL_COMPLETE: + ctrl_polling_handle_flag = 0U; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; + exe_state = USBH_OK; + break; + case CTRL_STALLED: + ctrl_polling_handle_flag = 0U; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; + exe_state = USBH_NOT_SUPPORTED; + break; + case CTRL_ERROR: + ctrl_polling_handle_flag = 0U; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; + exe_state = USBH_FAIL; + break; + default: + exe_state = USBH_BUSY; + break; + } + + return exe_state; +} + +/*! + \brief the handle function of CTRL_IDLE state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_idle_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; + scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); +} + +/*! + \brief the handle function of CTRL_SETUP state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_setup_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + urb_state_enum urb_status = URB_IDLE; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP; + + if (0U == ctrl_setup_wait_flag) { + ctrl_setup_wait_flag = 1U; + + /* send a setup packet */ + usbh_ctltx_setup (pudev, + puhost->control.setup.data, + puhost->control.hc_out_num); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); + + /* case setup packet sent successfully */ + if (URB_DONE == urb_status) { + /* check if there is a data stage */ + if (0U != puhost->control.setup.b.wLength) { + ctrl_setup_wait_flag = 0U; + timeout = DATA_STAGE_TIMEOUT; + scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state); + /* no data stage */ + } else { + timeout = NODATA_STAGE_TIMEOUT; + ctrl_setup_wait_flag = 0U; + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STATUS, + pustate->usbh_current_state); + } + + /* set the delay timer to enable timeout for data stage completion */ + puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET(); + } else if (URB_ERROR == urb_status) { + ctrl_setup_wait_flag = 0U; + scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state); + } else { + /* no operation */ + } + } +} + +/*! + \brief the handle function of CTRL_DATA state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_data_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + uint8_t direction; + urb_state_enum urb_status = URB_IDLE; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA; + + direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); + + if (USB_DIR_IN == direction) { + if (0U == ctrl_data_wait_flag) { + ctrl_data_wait_flag = 1U; + + /* issue an IN token */ + usbh_xfer(pudev, + puhost->control.buff, + puhost->control.hc_in_num, + puhost->control.length); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); + + /* check is data packet transfered successfully */ + switch (urb_status) { + case URB_DONE: + ctrl_data_wait_flag = 0U; + + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STATUS, + pustate->usbh_current_state); + break; + case URB_STALL: + ctrl_data_wait_flag = 0U; + + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STALLED, + pustate->usbh_current_state); + break; + case URB_ERROR: + ctrl_data_wait_flag = 0U; + + /* device error */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + break; + default: + if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { + ctrl_data_wait_flag = 0U; + + /* timeout for in transfer */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + } + break; + } + } + } else { + if (0U == ctrl_data_wait_flag) { + ctrl_data_wait_flag = 1U; + + /* start data out transfer (only one data packet)*/ + pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U; + + usbh_xfer(pudev, + puhost->control.buff, + puhost->control.hc_out_num, + puhost->control.length); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); + + switch (urb_status) { + case URB_DONE: + ctrl_data_wait_flag = 0U; + + /* if the setup pkt is sent successful, then change the state */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STATUS, + pustate->usbh_current_state); + break; + case URB_STALL: + ctrl_data_wait_flag = 0U; + + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STALLED, + pustate->usbh_current_state); + break; + case URB_NOTREADY: + /* nack received from device */ + ctrl_data_wait_flag = 0U; + break; + case URB_ERROR: + ctrl_data_wait_flag = 0U; + + /* device error */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + break; + default: + break; + } + } + } +} + +/*! + \brief the handle function of CTRL_STATUS state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_status_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + uint8_t direction; + urb_state_enum urb_status = URB_IDLE; + + puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS; + + /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */ + direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); + + if (USB_DIR_OUT == direction) { + /* handle status in */ + if (0U == ctrl_status_wait_flag) { + ctrl_status_wait_flag = 1U; + usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); + + switch (urb_status) { + case URB_DONE: + ctrl_status_wait_flag = 0U; + + /* handle URB_DONE status */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_COMPLETE, + pustate->usbh_current_state); + break; + case URB_ERROR: + ctrl_status_wait_flag = 0U; + + /* handle URB_STALL status*/ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + break; + case URB_STALL: + ctrl_status_wait_flag = 0U; + + /* handle URB_STALL status */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STALLED, + pustate->usbh_current_state); + break; + default: + if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { + ctrl_status_wait_flag = 0U; + + /* handle timeout */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + } + break; + } + } + } else { + /* handle status out */ + if (0U == ctrl_status_wait_flag) { + ctrl_status_wait_flag = 1U; + pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U; + usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); + + switch (urb_status) { + case URB_DONE: + ctrl_status_wait_flag = 0U; + + /* handle URB_DONE status */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_COMPLETE, + pustate->usbh_current_state); + break; + case URB_NOTREADY: + /* handle URB_NOTREADY status */ + ctrl_status_wait_flag = 0U; + break; + case URB_ERROR: + ctrl_status_wait_flag = 0U; + + /* handle URB_ERROR status */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + break; + default: + break; + } + } + } +} + +/*! + \brief the handle function of CTRL_ERROR state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_error_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR; + + if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { + /* do the transmission again, starting from setup packet */ + scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); + } else { + scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of CTRL_STALLED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_stalled_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED; + scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); +} + +/*! + \brief the handle function of CTRL_COMPLETE state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_complete_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE; + scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); +} + +/*! + \brief send datas from the host channel + \param[in] pudev: pointer to usb device + \param[in] buf: data buffer address to send datas + \param[in] hc_num: the number of the host channel + \param[in] len: length of the send data + \param[out] none + \retval host operation status +*/ +usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, + uint8_t *buf, + uint8_t hc_num, + uint16_t len) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; + + puhc->xfer_buff = buf; + puhc->xfer_len = len; + + switch (puhc->endp_type) { + case USB_EPTYPE_CTRL: + if (0U == puhc->endp_in) { + if (0U == len) { + /* for status out stage, length = 0, status out pid = 1 */ + puhc->data_tg_out = 1U; + } + + /* set the data toggle bit as per the flag */ + if (0U == puhc->data_tg_out) { + /* put the pid 0 */ + puhc->DPID = HC_PID_DATA0; + } else { + /* put the pid 1 */ + puhc->DPID = HC_PID_DATA1; + } + } else { + puhc->DPID = HC_PID_DATA1; + } + break; + + case USB_EPTYPE_ISOC: + puhc->DPID = HC_PID_DATA0; + break; + + case USB_EPTYPE_BULK: + if (0U == puhc->endp_in) { + /* set the data toggle bit as per the flag */ + if (0U == puhc->data_tg_out) { + /* put the pid 0 */ + puhc->DPID = HC_PID_DATA0; + } else { + /* put the pid 1 */ + puhc->DPID = HC_PID_DATA1; + } + } else { + if (0U == puhc->data_tg_in) { + puhc->DPID = HC_PID_DATA0; + } else { + puhc->DPID = HC_PID_DATA1; + } + } + break; + + case USB_EPTYPE_INTR: + if (0U == puhc->endp_in) { + if (0U == puhc->data_tg_out) { + puhc->DPID = HC_PID_DATA0; + } else { + puhc->DPID = HC_PID_DATA1; + } + + /* toggle data pid */ + puhc->data_tg_out ^= 1U; + } else { + if (0U == puhc->data_tg_in) { + puhc->DPID = HC_PID_DATA0; + } else { + puhc->DPID = HC_PID_DATA1; + } + + /* toggle data pid */ + puhc->data_tg_in ^= 1U; + } + break; + + default: + break; + } + + hcd_submit_request (pudev, hc_num); + + return USBH_OK; +} + +/*! + \brief send the setup packet to the device + \param[in] pudev: pointer to usb device + \param[in] buf: buffer pointer from which the data will be send to device + \param[in] hc_num: host channel number + \param[out] none + \retval host operation status +*/ +usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; + + puhc->DPID = HC_PID_SETUP; + puhc->xfer_buff = buf; + puhc->xfer_len = USBH_SETUP_PACKET_SIZE; + + return (usbh_status_enum)hcd_submit_request (pudev, hc_num); +} + +/*! + \brief this function prepare a hc and start a transfer + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval host operation status +*/ +uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + + puhc->urb_state = URB_IDLE; + puhc->xfer_count = 0U; + + return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num); +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c new file mode 100644 index 0000000000..33eecd62db --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c @@ -0,0 +1,185 @@ +/*! + \file usbh_hcs.c + \brief this file implements functions for opening and closing host channels + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hcs.h" + +static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev); + +/*! + \brief open a channel + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[in] dev_addr: USB device address allocated to attached device + \param[in] dev_speed: USB device speed (Full speed/Low speed) + \param[in] ep_type: endpoint type (bulk/int/ctl) + \param[in] ep_mps: max packet size + \param[out] none + \retval operation status +*/ +uint8_t usbh_channel_open (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + uint16_t channel_info = puhc->info; + + puhc->endp_id = (uint8_t)channel_info & 0x7FU; + puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7U; + puhc->endp_type = ep_type; + puhc->endp_mps = ep_mps; + puhc->dev_addr = dev_addr; + puhc->dev_speed = dev_speed; + + puhc->data_tg_in = 0U; + puhc->data_tg_out = 0U; + + usb_hostchannel_init(pudev, channel_num); + + return (uint8_t)HC_OK; +} + +/*! + \brief modify a channel + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[in] dev_addr: USB Device address allocated to attached device + \param[in] dev_speed: USB device speed (full speed / low speed) + \param[in] ep_type: endpoint type (bulk/int/ctl) + \param[in] ep_mps: max packet size + \param[out] none + \retval operation status +*/ +uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + + if (0U != dev_addr) { + puhc->dev_addr = dev_addr; + } + + if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) { + puhc->endp_mps = ep_mps; + } + + if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) { + puhc->dev_speed = dev_speed; + } + + usb_hostchannel_init(pudev, channel_num); + + return (uint8_t)HC_OK; +} + +/*! + \brief allocate a new channel for the pipe + \param[in] pudev: pointer to usb device + \param[in] ep_addr: endpoint for which the channel to be allocated + \param[out] none + \retval host channel number +*/ +uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint16_t hc_num = usbh_freechannel_get(pudev); + + if ((uint16_t)HC_ERROR != hc_num) { + pudev->host.host_channel[hc_num].info = HC_USED | ep_addr; + } + + return (uint8_t)hc_num; +} + +/*! + \brief free the usb host channel + \param[in] pudev: pointer to usb device + \param[in] index: channel number to be freed which is in (0..7) + \param[out] none + \retval host operation status +*/ +uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index) +{ + if (index < HC_MAX) { + pudev->host.host_channel[index].info &= HC_USED_MASK; + } + + return USBH_OK; +} + +/*! + \brief free all usb host channel + \param[in] pudev: pointer to usb device + \param[out] none + \retval host operation status +*/ +uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev) +{ + uint8_t index; + + for (index = 2U; index < HC_MAX; index ++) { + pudev->host.host_channel[index].info = 0U; + } + + return USBH_OK; +} + +/*! + \brief get a free channel number for allocation to a device endpoint + \param[in] pudev: pointer to usb device + \param[out] none + \retval free channel number +*/ +static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev) +{ + uint8_t index = 0U; + + for (index = 0U; index < HC_MAX; index++) { + if (0U == (pudev->host.host_channel[index].info & HC_USED)) { + return (uint16_t)index; + } + } + + return HC_ERROR; +} + diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c new file mode 100644 index 0000000000..5a652bcb88 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c @@ -0,0 +1,612 @@ +/*! + \file usbh_int.c + \brief USB host mode interrupt handler file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_core.h" +#include "usb_defines.h" +#include "usbh_int.h" + +static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_port (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num); +static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num); +static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev); + +/*! + \brief handle global host interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +uint32_t usbh_isr (usb_core_handle_struct *pudev) +{ + uint32_t retval = 0U; + __IO uint32_t int_flag = 0U; + + /* check if host mode */ + if (USB_CURRENT_MODE_GET() == HOST_MODE) { + USB_CORE_INTR_READ(int_flag); + + if (!int_flag) { + return 0U; + } + + /* start of frame interrupt handle */ + if (int_flag & GINTF_SOF) { + retval |= usbh_intf_sof (pudev); + } + + /* rx fifo non-empty interrupt handle */ + if (int_flag & GINTF_RXFNEIF) { + retval |= usbh_intf_rxfifo_noempty (pudev); + } + + /* non-periodic tx fifo empty interrupt hanlde */ + if (int_flag & GINTF_NPTXFEIF) { + retval |= usbh_intf_nptxfifo_empty (pudev); + } + + /* periodic tx fifo empty interrupt handle */ + if (int_flag & GINTF_PTXFEIF) { + retval |= usbh_intf_ptxfifo_empty (pudev); + } + + /* host channels interrupt handle */ + if (int_flag & GINTF_HCIF) { + retval |= usbh_intf_hc (pudev); + } + + /* host port interrupt handle */ + if (int_flag & GINTF_HPIF) { + retval |= usbh_intf_port (pudev); + } + + /* disconnect interrupt handle */ + if (int_flag & GINTF_DISCIF) { + retval |= usbh_intf_disconnect (pudev); + } + + /* isochronous in transfer not complete interrupt handle */ + if (int_flag & GINTF_ISOONCIF) { + retval |= usbh_intf_iso_incomplete_xfer (pudev); + } + } + + return retval; +} + +/*! + \brief handle the start-of-frame interrupt in host mode + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev) +{ + usbh_hcd_int_fops->sof(pudev); + + /* clear interrupt */ + USB_GINTF = GINTF_SOF; + + return 1U; +} + +/*! + \brief handle all host channels interrupt in host mode + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev) +{ + uint8_t i = 0U; + uint32_t retval = 0U; + + for (i = 0U; i < pudev->cfg.host_channel_num; i++) { + if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) { + if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) { + retval |= usbh_intf_hc_in (pudev, i); + } else { + retval |= usbh_intf_hc_out (pudev, i); + } + } + } + + return retval; +} + +/*! + \brief handle the disconnect interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev) +{ + usbh_hcd_int_fops->device_disconnected(pudev); + + /* clear interrupt */ + USB_GINTF = GINTF_DISCIF; + + return 1U; +} + +/*! + \brief handle the non-periodic tx fifo empty interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev) +{ + uint8_t channel_num = 0U; + uint32_t dword_len = 0U, len = 0U; + usb_hostchannel_struct *puhc; + + channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U); + puhc = &pudev->host.host_channel[channel_num]; + dword_len = (puhc->xfer_len + 3U) / 4U; + + while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) { + len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U; + + if (len > puhc->xfer_len) { + /* last packet */ + len = (uint16_t)puhc->xfer_len; + + USB_GINTEN &= ~GINTF_NPTXFEIF; + + } + + dword_len = (puhc->xfer_len + 3U) / 4U; + usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); + + puhc->xfer_buff += len; + puhc->xfer_len -= len; + puhc->xfer_count += len; + } + + return 1U; +} + +/*! + \brief handle the periodic tx fifo empty interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev) +{ + uint8_t channel_num = 0U; + uint32_t dword_len = 0U, len = 0U; + usb_hostchannel_struct *puhc; + + channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U); + puhc = &pudev->host.host_channel[channel_num]; + dword_len = (puhc->xfer_len + 3U) / 4U; + + while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) { + len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U; + + if (len > puhc->xfer_len) { + len = puhc->xfer_len; + + /* last packet */ + USB_GINTEN &= ~GINTF_PTXFEIF; + } + + dword_len = (puhc->xfer_len + 3U) / 4U; + usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); + + puhc->xfer_buff += len; + puhc->xfer_len -= len; + puhc->xfer_count += len; + } + + return 1U; +} + +/*! + \brief handle the host port interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_port (usb_core_handle_struct *pudev) +{ + uint8_t port_speed = 0U; + uint8_t port_reset = 0U; + uint32_t retval = 0U; + __IO uint32_t hostportdup = USB_HPCS; + + /* clear the interrupt bits in gintsts */ + hostportdup &= ~HPCS_PE; + hostportdup &= ~HPCS_PCD; + hostportdup &= ~HPCS_PEDC; + + /* port connect detected */ + if (USB_HPCS & HPCS_PCD) { + hostportdup |= HPCS_PCD; + usbh_hcd_int_fops->device_connected(pudev); + retval |= 1U; + } + + /* port enable changed */ + if (USB_HPCS & HPCS_PEDC) { + hostportdup |= HPCS_PEDC; + + if (USB_HPCS & HPCS_PE) { + port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U); + + if (HPRT_PRTSPD_LOW_SPEED == port_speed) { + USB_HFT = 6000U; + + if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) { + if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { + USB_FSLSCLOCK_INIT(HCTLR_6_MHZ); + } + port_reset = 1U; + } + } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) { + USB_HFT = 48000U; + + if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) { + if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { + USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); + } + port_reset = 1U; + } + } else { + /* for high speed device and others */ + port_reset = 1U; + } + } + } + + if (port_reset) { + usb_port_reset(pudev); + } + + /* clear port interrupts */ + USB_HPCS = hostportdup; + + return retval; +} + +/*! + \brief handle the out channel interrupt + \param[in] pudev: pointer to usb device instance + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num); + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + + channel_intr &= USB_HCHxINTEN((uint16_t)channel_num); + + if (channel_intr & HCHINTF_ACK) { + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; + } else if (channel_intr & HCHINTF_REQOVR) { + /* handle queue overrun interrupt */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; + } else if (channel_intr & HCHINTF_TF) { + /* handle transfer finished interrupt */ + puhc->err_count = 0U; + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; + puhc->status = HC_XF; + } else if (channel_intr & HCHINTF_STALL) { + /* handle stall */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; + usb_hostchannel_halt(pudev, channel_num); + puhc->status = HC_STALL; + } else if (channel_intr & HCHINTF_NAK) { + /* handle NAK */ + puhc->err_count = 0U; + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + puhc->status = HC_NAK; + } else if (channel_intr & HCHINTF_USBER) { + /* handle USB bus error */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + puhc->status = HC_TRACERR; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; + } else if (channel_intr & HCHINTF_NYET) { + /* handle NYET */ + puhc->err_count = 0U; + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + puhc->status = HC_NYET; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET; + } else if (channel_intr & HCHINTF_DTER) { + /* handle data toggle error */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + puhc->status= HC_DTGERR; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; + } else if (channel_intr & HCHINTF_CH) { + /* handle channel halted */ + USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; + + switch (puhc->status) { + case HC_XF: + puhc->urb_state = URB_DONE; + + if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18U)) { + puhc->data_tg_out ^= 1U; + } + break; + case HC_NAK: + puhc->urb_state = URB_NOTREADY; + break; + case HC_NYET: + puhc->urb_state = URB_NOTREADY; + break; + case HC_STALL: + puhc->urb_state = URB_STALL; + break; + case HC_TRACERR: + puhc->urb_state = URB_ERROR; + break; + default: + break; + } + + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the in channel interrupt + \param[in] pudev: pointer to usb device instance + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + uint8_t endp_type = 0U; + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + + uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num); + __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num); + + channle_intf &= USB_HCHxINTEN((uint16_t)channel_num); + + endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U); + + if (channle_intf & HCHINTF_ACK) { + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; + } else if (channle_intf & HCHINTF_STALL) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + puhc->status = HC_STALL; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; + + /* NOTE: When there is a 'stall', reset also nak, + else, the pudev->host.status = HC_STALL + will be overwritten by 'nak' in code below */ + channle_intf &= ~HCHINTF_NAK; + + usb_hostchannel_halt(pudev, channel_num); + } else if (channle_intf & HCHINTF_DTER) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + puhc->status = HC_DTGERR; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; + } else { + /* no operation */ + } + /* handle queue overrun interrupt */ + if (channle_intf & HCHINTF_REQOVR) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; + } else if (channle_intf & HCHINTF_TF) { + /* handle transfer finished interrupt */ + puhc->status = HC_XF; + puhc->err_count = 0U; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; + + if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + puhc->data_tg_in ^= 1U; + } else if (USB_EPTYPE_INTR == endp_type) { + channel_ctrl |= HCHCTL_ODDFRM; + USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; + puhc->urb_state = URB_DONE; + } else { + /* no operation */ + } + } else if (channle_intf & HCHINTF_CH) { + /* handle channel halted */ + USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; + + switch (puhc->status) { + case HC_XF: + puhc->urb_state = URB_DONE; + break; + case HC_TRACERR: + case HC_DTGERR: + puhc->err_count = 0U; + puhc->urb_state = URB_ERROR; + break; + case HC_STALL: + puhc->urb_state = URB_STALL; + break; + default: + if (USB_EPTYPE_INTR == endp_type) { + puhc->data_tg_in ^= 1U; + } + break; + } + + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; + } else if (channle_intf & HCHINTF_USBER) { + /* handle USB bus error */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + puhc->status = HC_TRACERR; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; + } else if (channle_intf & HCHINTF_NAK) { + /* handle NAK */ + if (USB_EPTYPE_INTR == endp_type) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + } + + puhc->status = HC_NAK; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + + if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { + /* re-activate the channel */ + channel_ctrl |= HCHCTL_CEN; + channel_ctrl &= ~HCHCTL_CDIS; + USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; + } + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the rx fifo non-empty interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) +{ + uint32_t count = 0U; + __IO uint8_t channel_num = 0U; + __IO uint32_t rx_status = 0U; + uint32_t usbh_ch_ctl_reg = 0U; + usb_hostchannel_struct *puhc; + + /* disable the rx status queue level interrupt */ + USB_GINTEN &= ~GINTF_RXFNEIF; + + rx_status = USB_GRSTATP; + channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM); + puhc = &pudev->host.host_channel[channel_num]; + + switch ((rx_status & GRSTATRP_RPCKST) >> 17) { + case GRSTATR_RPCKST_IN: + count = (rx_status & GRSTATRP_BCOUNT) >> 4; + + /* read the data into the host buffer. */ + if ((count > 0U) && (puhc->xfer_buff != (void *)0)) { + usb_fifo_read(puhc->xfer_buff, (uint16_t)count); + + /* manage multiple Xfer */ + puhc->xfer_buff += count; + puhc->xfer_count += count; + + if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) { + /* re-activate the channel when more packets are expected */ + usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num); + usbh_ch_ctl_reg |= HCHCTL_CEN; + usbh_ch_ctl_reg &= ~HCHCTL_CDIS; + USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg; + } + } + break; + case GRSTATR_RPCKST_IN_XFER_COMP: + break; + case GRSTATR_RPCKST_DATA_TOGGLE_ERR: + count = (rx_status & GRSTATRP_BCOUNT) >> 4; + while (count > 0) { + rx_status = USB_GRSTATP; + count--; + } + break; + case GRSTATR_RPCKST_CH_HALTED: + default: + break; + } + + /* enable the rx status queue level interrupt */ + USB_GINTEN |= GINTF_RXFNEIF; + + return 1U; +} + +/*! + \brief handle the incomplete periodic transfer interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev) +{ + __IO uint32_t gint_flag = 0U; + + gint_flag = USB_HCHxCTL(0U); + USB_HCHxCTL(0U) = 0U; + + gint_flag = 0U; + + /* clear interrupt */ + gint_flag |= GINTF_ISOONCIF; + USB_GINTF = gint_flag; + + return 1U; +} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c new file mode 100644 index 0000000000..6052b906e4 --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c @@ -0,0 +1,834 @@ +/*! + \file usbh_std.c + \brief USB 2.0 standard function definition + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_core.h" +#include "usbh_usr.h" +#include "usbh_std.h" +#include "usbh_ctrl.h" + +uint8_t local_buffer[64U]; +uint8_t usbh_cfg_desc[512U]; +uint8_t enum_polling_handle_flag = 0U; + +static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); + +/* the enumeration state handle function array */ +void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = +{ + enum_idle_handle, + enum_set_addr_handle, + enum_get_full_dev_desc_handle, + enum_get_cfg_desc_handle, + enum_get_full_cfg_desc_handle, + enum_get_mfc_string_desc_handle, + enum_get_product_string_desc_handle, + enum_get_serialnum_string_desc_handle, + enum_set_configuration_handle, + enum_dev_configured_handle, +}; + +/* the enumeration state handle table */ +state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] = +{ + /* the current state the current event the next state the event function */ + {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move }, + {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move }, + {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move }, + {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move }, + {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move }, + {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move }, + {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move }, + {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move }, + {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move }, + {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, +}; + +/*! + \brief the polling function of enumeration state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval usb host status +*/ +usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + usbh_status_enum exe_state = USBH_BUSY; + usbh_state_handle_struct *p_state; + p_state = (usbh_state_handle_struct *)pustate; + + if (0U == enum_polling_handle_flag) { + enum_polling_handle_flag = 1U; + scd_table_push(p_state); + scd_state_move(p_state, ENUM_IDLE); + } + + /* start the enumeration state handle */ + scd_begin(p_state,ENUM_FSM_ID); + + if (0U == p_state->usbh_current_state_stack_top) { + enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); + } else { + enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state); + } + + /* determine the enumeration whether to complete */ + if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) { + puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; + enum_polling_handle_flag = 0U; + exe_state = USBH_OK; + } + + return exe_state; +} + +/*! + \brief the handle function of ENUM_IDLE state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_DEVDESC, + 8U); + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(100U); + } + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U); + puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0; + + /* issue reset */ + usb_port_reset(pudev); + + /* modify control channels configuration for maxpacket size */ + usbh_channel_modify (pudev, + puhost->control.hc_out_num, + 0U, + 0U, + 0U, + (uint16_t)puhost->control.ep0_size); + + usbh_channel_modify (pudev, + puhost->control.hc_in_num, + 0U, + 0U, + 0U, + (uint16_t)puhost->control.ep0_size); + + scd_event_handle(pudev, + puhost, + pustate, + ENUM_EVENT_SET_ADDR, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_FULL_DEV_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_DEVDESC, + USB_DEVDESC_SIZE); + } + + if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ + usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE); + puhost->usr_cb->device_desc_available(&puhost->device.dev_desc); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_CFG_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_SET_ADDR state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_set_addr_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS); + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(100U); + } + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(2U); + } + puhost->device.address = USBH_DEVICE_ADDRESS; + + /* user callback for device address assigned */ + puhost->usr_cb->device_address_set(); + + /* modify control channels to update device address */ + usbh_channel_modify (pudev, + puhost->control.hc_in_num, + puhost->device.address, + 0U, + 0U, + 0U); + + usbh_channel_modify (pudev, + puhost->control.hc_out_num, + puhost->device.address, + 0U, + 0U, + 0U); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_FULL_DEV_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_CFG_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + uint16_t index = 0U; + + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_CFGDESC, + USB_CFGDESC_SIZE); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + /* save configuration descriptor for class parsing usage */ + for (; index < USB_CFGDESC_SIZE; index ++) { + usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; + } + + /* commands successfully sent and response received */ + usbh_cfg_desc_parse (&puhost->device.cfg_desc, + puhost->device.itf_desc, + puhost->device.ep_desc, + pudev->host.rx_buffer, + USB_CFGDESC_SIZE); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_FULL_CFG_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_FULL_CFG_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + + uint16_t index = 0U; + + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_CFGDESC, puhost->device.cfg_desc.wTotalLength); + } + + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + /* save configuration descriptor for class parsing usage */ + for (; index < puhost->device.cfg_desc.wTotalLength; index ++) { + usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; + } + + /* commands successfully sent and response received */ + usbh_cfg_desc_parse (&puhost->device.cfg_desc, + puhost->device.itf_desc, + puhost->device.ep_desc, + pudev->host.rx_buffer, + puhost->device.cfg_desc.wTotalLength); + + /* User callback for configuration descriptors available */ + puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc, + puhost->device.itf_desc, + puhost->device.ep_desc[0]); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_MFC_STRING_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_MFC_STRING_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC; + + if (0U != puhost->device.dev_desc.iManufacturer) { + if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_STRDESC | puhost->device.dev_desc.iManufacturer, + 0xffU); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); + puhost->usr_cb->manufacturer_string(local_buffer); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_PRODUCT_STRING_DESC, + pustate->usbh_current_state); + } + } else { + puhost->usr_cb->manufacturer_string("N/A"); + scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC); + } +} + +/*! + \brief the handle function of ENUM_GET_PRODUCT_STRING_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC; + + if (0U != puhost->device.dev_desc.iProduct) { + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_STRDESC | puhost->device.dev_desc.iProduct, + 0xffU); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); + + /* user callback for product string */ + puhost->usr_cb->product_string(local_buffer); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_SERIALNUM_STRING_DESC, + pustate->usbh_current_state); + } + } else { + puhost->usr_cb->product_string("N/A"); + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_SERIALNUM_STRING_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_SERIALNUM_STRING_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC; + + if (0U != puhost->device.dev_desc.iSerialNumber) { + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_STRDESC | puhost->device.dev_desc.iSerialNumber, + 0xffU); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ + usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); + + /* user callback for product string */ + puhost->usr_cb->serial_num_string(local_buffer); + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_SET_CONFIGURATION, + pustate->usbh_current_state); + } + } else { + puhost->usr_cb->serial_num_string("N/A"); + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_SET_CONFIGURATION, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_SET_CONFIGURATION state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_set_configuration_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) { + usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_DEV_CONFIGURED, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_DEV_CONFIGURED state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_dev_configured_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED; + scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); +} + +/*! + \brief get descriptor in usb host enumeration stage + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] buf: buffer to store the descriptor + \param[in] ReqType: descriptor type + \param[in] ValueIdx: wValue for the GetDescriptr request + \param[in] Len: length of the descriptor + \param[out] none + \retval none +*/ +void usbh_enum_desc_get(usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + uint8_t *buf, + uint8_t req_type, + uint16_t value_idx, + uint16_t len) +{ + usb_setup_union *pSetup = &(puhost->control.setup); + + pSetup->b.bmRequestType = USB_DIR_IN | req_type; + pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR; + pSetup->b.wValue = value_idx; + + if (USB_STRDESC == (value_idx & 0xff00U)){ + pSetup->b.wIndex = 0x0409U; + } else { + pSetup->b.wIndex = 0U; + } + + pSetup->b.wLength = len; + + puhost->control.buff = buf; + puhost->control.length = len; + +} + +/*! + \brief set address in usb host enumeration stage + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] device_address: the device address + \param[out] none + \retval none +*/ +void usbh_enum_addr_set(usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + uint8_t device_address) +{ + usb_setup_union *p_setup = &(puhost->control.setup); + + p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; + p_setup->b.bRequest = USBREQ_SET_ADDRESS; + p_setup->b.wValue = (uint16_t)device_address; + p_setup->b.wIndex = 0U; + p_setup->b.wLength = 0U; + puhost->control.buff = 0U; + puhost->control.length = 0U; +} + +/*! + \brief set configuration in usb host enumeration stage + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] cfg_idx: the index of the configuration + \param[out] none + \retval none +*/ +void usbh_enum_cfg_set(usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + uint16_t cfg_idx) +{ + usb_setup_union *p_setup = &(puhost->control.setup); + + p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; + p_setup->b.bRequest = USBREQ_SET_CONFIGURATION; + p_setup->b.wValue = cfg_idx; + p_setup->b.wIndex = 0U; + p_setup->b.wLength = 0U; + puhost->control.buff = 0; + puhost->control.length = 0U; +} + +/*! + \brief parse the device descriptor + \param[in] dev_desc: device_descriptor destinaton address + \param[in] buf: buffer where the source descriptor is available + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len) +{ + dev_desc->Header.bLength = *(uint8_t *)(buf + 0U); + dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); + dev_desc->bcdUSB = SWAPBYTE(buf + 2U); + dev_desc->bDeviceClass = *(uint8_t *)(buf + 4U); + dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5U); + dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6U); + dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7U); + + if (len > 8U){ + /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ + dev_desc->idVendor = SWAPBYTE(buf + 8U); + dev_desc->idProduct = SWAPBYTE(buf + 10U); + dev_desc->bcdDevice = SWAPBYTE(buf + 12U); + dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); + dev_desc->iProduct = *(uint8_t *)(buf + 15U); + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); + dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17U); + } +} + +/*! + \brief parse the configuration descriptor + \param[in] cfg_desc: configuration descriptor address + \param[in] itf_desc: interface descriptor address + \param[in] ep_desc: endpoint descriptor address + \param[in] buf: buffer where the source descriptor is available + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, + usb_descriptor_interface_struct *itf_desc, + usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], + uint8_t *buf, + uint16_t len) +{ + usb_descriptor_interface_struct *pitf = NULL; + usb_descriptor_interface_struct temp_pitf; + usb_descriptor_endpoint_struct *pep = NULL; + usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf; + + uint8_t itf_ix = 0U; + uint8_t ep_ix = 0U; + uint16_t ptr = 0U; + static uint8_t prev_itf = 0U; + static uint16_t prev_ep_size = 0U; + + /* parse configuration descriptor */ + cfg_desc->Header.bLength = *(uint8_t *)(buf + 0U); + cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); + cfg_desc->wTotalLength = SWAPBYTE(buf + 2U); + cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4U); + cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5U); + cfg_desc->iConfiguration = *(uint8_t *)(buf + 6U); + cfg_desc->bmAttributes = *(uint8_t *)(buf + 7U); + cfg_desc->bMaxPower = *(uint8_t *)(buf + 8U); + + if (len > USB_CFGDESC_SIZE) { + ptr = USB_CFG_DESC_LEN; + + if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) { + pitf = (usb_descriptor_interface_struct *)0U; + + for (; ptr < cfg_desc->wTotalLength; ) { + pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr); + + if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) { + itf_ix = *((uint8_t *)pdesc + 2U); + pitf = &itf_desc[itf_ix]; + + if (*((uint8_t *)pdesc + 3U) < 3U) { + usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc); + + /* parse endpoint descriptors relative to the current interface */ + if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) { + for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) { + pdesc = usbh_next_desc_get((void* )pdesc, &ptr); + + if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) { + pep = &ep_desc[itf_ix][ep_ix]; + + if (prev_itf != itf_ix) { + prev_itf = itf_ix; + usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); + } else { + if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) { + break; + } else { + usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); + } + } + + usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc); + prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4); + ep_ix++; + } + } + } + } + } + } + } + + prev_ep_size = 0U; + prev_itf = 0U; + } +} + +/*! + \brief parse the interface descriptor + \param[in] itf_desc: interface descriptor destination + \param[in] buf: buffer where the descriptor data is available + \param[out] none + \retval none +*/ +void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf) +{ + itf_desc->Header.bLength = *(uint8_t *)(buf + 0U); + itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); + itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2U); + itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3U); + itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4U); + itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5U); + itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6U); + itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7U); + itf_desc->iInterface = *(uint8_t *)(buf + 8U); +} + +/*! + \brief parse the endpoint descriptor + \param[in] ep_desc: endpoint descriptor destination address + \param[in] buf: buffer where the parsed descriptor stored + \param[out] none + \retval none +*/ +void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf) +{ + ep_desc->Header.bLength = *(uint8_t *)(buf + 0U); + ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); + ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2U); + ep_desc->bmAttributes = *(uint8_t *)(buf + 3U); + ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4U); + ep_desc->bInterval = *(uint8_t *)(buf + 6U); +} + +/*! + \brief parse the string descriptor + \param[in] psrc: source pointer containing the descriptor data + \param[in] pdest: destination address pointer + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len) +{ + uint16_t strlength; + uint16_t idx; + + /* the unicode string descriptor is not null-terminated. the string length is + computed by substracting two from the value of the first byte of the descriptor. + */ + + /* check which is lower size, the size of string or the length of bytes read from the device */ + + if (USB_DESCTYPE_STRING == psrc[1]){ + /* make sure the descriptor is string type */ + + /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ + strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len); + psrc += 2; /* adjust the offset ignoring the string len and descriptor type */ + + for (idx = 0U; idx < strlength; idx += 2U) { + /* copy only the string and ignore the unicode id, hence add the src */ + *pdest = psrc[idx]; + pdest++; + } + + *pdest = 0U; /* mark end of string */ + } +} + +/*! + \brief get the next descriptor header + \param[in] pbuf: pointer to buffer where the cfg descriptor is available + \param[in] ptr: data popinter inside the configuration descriptor + \param[out] none + \retval next descriptor header +*/ +usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr) +{ + uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength; + + usb_descriptor_header_struct *pnext; + + *ptr += len; + + pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len); + + return(pnext); +} + diff --git a/bsp/gd32105c-eval/Libraries/SConscript b/bsp/gd32105c-eval/Libraries/SConscript new file mode 100644 index 0000000000..bdfd09f67b --- /dev/null +++ b/bsp/gd32105c-eval/Libraries/SConscript @@ -0,0 +1,33 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Glob('GD32F10x_standard_peripheral/Source/*.c') +src += [cwd + '/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/CMSIS/GD/GD32F10x/Source/GCC/startup_gd32f10x_cl.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [cwd + '/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [cwd + '/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s'] + +path = [ + cwd + '/CMSIS/GD/GD32F10x/Include', + cwd + '/CMSIS', + cwd + '/GD32F10x_standard_peripheral/Include',] + +if GetDepend(['RT_USING_BSP_USB']): + path += [cwd + '/GD32F10x_usbfs_driver/Include'] + src += [cwd + '/GD32F10x_usbfs_driver/Source'] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F10X_CL'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/gd32105c-eval/README.md b/bsp/gd32105c-eval/README.md new file mode 100644 index 0000000000..3ae69f8226 --- /dev/null +++ b/bsp/gd32105c-eval/README.md @@ -0,0 +1,93 @@ +# GD32105C-EVAL # + +## 1. 简介 + +[GD32105C-EVAL](http://gd32mcu.21ic.com)是兆易科技提供的开发板，使用 GD32F105VCT6 作为主控制器。提供包括扩展引脚在内的及 SWD, Reset, Boot, User button key, LED, CAN, I2C, I2S, USART, RTC, LCD, SPI, ADC, DAC, EXMC, CTC, SDIO,USBD, GD-Link 等外设资源。 + +板载主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|CPU| Cortex-M3| +|主频| 120MHz | +|SRAM| 96KB | +|Flash| 256KB | + +## 2. 编译说明 + +GD32105C-EVAL板级包支持MDK5、IAR开发环境和GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| -- | -- | +| MDK5 | MDK5.25 | +| IAR | IAR8.20 | +| GCC | GCC 5.4.1 20160919 (release) | + +## 3. 烧写及执行 + +供电方式：开发板使用 Mini USB 接口或者 DC-005 连接器提供 5V 电源。 + +下载程序：下载程序到开发板需要一套 JLink 或者使用 GD-Link 工具。 + +解决IDE "Missing Device(s)"问题" +* MDK5: 安装GigaDevice.GD32F10x_DFP.2.0.1.pack，在 Folder Selection 中的 Destination Folder 那一栏选择 Keil uVision5 软件的安装目录，如 C:\Keil_v5，然后在 Option for Target 的 Device 选择对应的器件，同时在 Option forTarget 的 C/C++中添加路径 C:\Keil_v5\ARM\Pack\ARM\CMSIS\4.2.0\CMSIS\Include。 + +* IAR：安装 IAR_GD32F10x_ADDON.2.0.0.exe + +### 3.1 配置和仿真 + +工程已经默认使能了RT-Thread UART驱动、GPIO驱动、SPI驱动、I2C驱动。若想进一步配置工程请 +使用ENV工具。 + +### 3.2 运行结果 + +打开MDK或者IAR工程，进入仿真后全速运行，将会在串口0上看到RT-Thread的启动logo信息： + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Aug 23 2021 + 2006 - 2021 Copyright by rt-thread team +msh > + +``` + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0/1/2/3 | +| GPIO | 支持 | | +| SPI | 支持 | SPI0/1/2 | +| I2C | 支持 | I2C0/1| + +### 4.1 IO在板级支持包中的映射情况 + +| IO号 | 板级包中的定义 | +| -- | -- | +| PA9 | USART0 TX | +| PA10 | USART0 RX | +| PA2 | USART1 TX | +| PA3 | USART1 RX | +| PA5| SPI0 SCK | +| PA6 | SPI0 MISO | +| PA6 | SPI0 MOSI | +| PB13| SPI1 SCK | +| PB14 | SPI1 MISO | +| PB15 | SPI1 MOSI | +| PB6| I2C0 SCL | +| PB7 | I2C0 SDA | +| PB10| I2C1 SCL | +| PB11 | I2C1 SDA | + +## 5. 联系人信息 + +维护人： + +- [lianzhian](https://gitee.com/qidiyun) + +## 6. 参考 + +* [GD32105C-EVAL](http://gd32mcu.21ic.com/site) + + diff --git a/bsp/gd32105c-eval/SConscript b/bsp/gd32105c-eval/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/gd32105c-eval/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/gd32105c-eval/SConstruct b/bsp/gd32105c-eval/SConstruct new file mode 100644 index 0000000000..215861f94c --- /dev/null +++ b/bsp/gd32105c-eval/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread-gd32f30x.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/gd32105c-eval/applications/SConscript b/bsp/gd32105c-eval/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/gd32105c-eval/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/gd32105c-eval/applications/main.c b/bsp/gd32105c-eval/applications/main.c new file mode 100644 index 0000000000..83b68664a3 --- /dev/null +++ b/bsp/gd32105c-eval/applications/main.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-24 lianzhian first implementation + */ +#include +#include +#include + + +/* defined the LED0 pin: PF0 */ +#define LED0_PIN GET_PIN(C, 0) + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} + diff --git a/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf b/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf new file mode 100644 index 0000000000..d6665c3649 --- /dev/null +++ b/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807ffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +export symbol __ICFEDIT_region_RAM_end__; + +define symbol __region_RAM1_start__ = 0x10000000; +define symbol __region_RAM1_end__ = 0x1000FFFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; \ No newline at end of file diff --git a/bsp/gd32105c-eval/board/linker_script/gd32_rom.ld b/bsp/gd32105c-eval/board/linker_script/gd32_rom.ld new file mode 100644 index 0000000000..4af47d1dcb --- /dev/null +++ b/bsp/gd32105c-eval/board/linker_script/gd32_rom.ld @@ -0,0 +1,142 @@ +/* + * linker script for GD32F30x with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 512KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 64KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/gd32105c-eval/board/linker_script/gd32_rom.sct b/bsp/gd32105c-eval/board/linker_script/gd32_rom.sct new file mode 100644 index 0000000000..b3144a70e0 --- /dev/null +++ b/bsp/gd32105c-eval/board/linker_script/gd32_rom.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x000040000 { ; load region size_region + ER_IROM1 0x08000000 0x000040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00018000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/gd32105c-eval/drivers/Kconfig b/bsp/gd32105c-eval/drivers/Kconfig new file mode 100644 index 0000000000..e2f6367a08 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/Kconfig @@ -0,0 +1,69 @@ +menu "Hardware Drivers Config" + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config SOC_SERIES_GD32F1 + bool + default y + config SOC_GD32105C + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select SOC_SERIES_GD32F1 + default y + + config RT_USING_USART0 + bool "Using USART0" + select RT_USING_SERIAL + default y + + config RT_USING_USART1 + bool "Using USART1" + select RT_USING_SERIAL + default n + + config RT_USING_USART2 + bool "Using USART2" + select RT_USING_SERIAL + default n + + config RT_USING_UART3 + bool "Using UART3" + select RT_USING_SERIAL + default n + + config RT_USING_SPI0 + bool "Using SPI0" + select RT_USING_SPI + default y + + config RT_USING_SPI1 + bool "Using SPI1" + select RT_USING_SPI + default n + + config RT_USING_SPI2 + bool "Using SPI2" + select RT_USING_SPI + default n + + config RT_USING_I2C0 + bool "Using I2C0" + select RT_USING_I2C + default n + + config RT_USING_I2C1 + bool "Using I2C1" + select RT_USING_I2C + default n +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/gd32105c-eval/drivers/SConscript b/bsp/gd32105c-eval/drivers/SConscript new file mode 100644 index 0000000000..77badf9a32 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/SConscript @@ -0,0 +1,33 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'drivers') + +# add the general drivers. +src = Split(""" +board.c +drv_usart.c +""") + +CPPPATH = [cwd] + +# add spi drivers. +if GetDepend('RT_USING_SPI'): + src += ['drv_spi.c'] + +# add i2c drivers. +if GetDepend('RT_USING_I2C'): + src += ['drv_i2c.c'] + +# add pin drivers. +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +# add spi flash drivers. +if GetDepend('RT_USING_SFUD'): + src += ['drv_spi_flash.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/gd32105c-eval/drivers/board.c b/bsp/gd32105c-eval/drivers/board.c new file mode 100644 index 0000000000..6cfd569f1a --- /dev/null +++ b/bsp/gd32105c-eval/drivers/board.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ +#include +#include +#include +#include + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial GD32 board. + */ +void rt_hw_board_init() +{ + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); +#endif + + SystemClock_Config(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); +#endif +} + +/*@}*/ diff --git a/bsp/gd32105c-eval/drivers/board.h b/bsp/gd32105c-eval/drivers/board.h new file mode 100644 index 0000000000..7b791f25c9 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/board.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "drv_gpio.h" + +// Internal SRAM memory size[Kbytes] <8-64> +// Default: 64 +#ifdef __ICCARM__ +// Use *.icf ram symbal, to avoid hardcode. +extern char __ICFEDIT_region_RAM_end__; +#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ +#else +#define GD32_SRAM_SIZE 96 +#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) +#endif + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END GD32_SRAM_END + +#endif + +//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32105c-eval/drivers/drv_comm.h b/bsp/gd32105c-eval/drivers/drv_comm.h new file mode 100644 index 0000000000..0881776e60 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_comm.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef __DRV_COMM_H__ +#define __DRV_COMM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_HWTIMER_H__ */ + diff --git a/bsp/gd32105c-eval/drivers/drv_gpio.c b/bsp/gd32105c-eval/drivers/drv_gpio.c new file mode 100644 index 0000000000..40cd8df4b5 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_gpio.c @@ -0,0 +1,552 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ +#include +#include +#include "drv_gpio.h" +#include +#include +#include "gd32f10x.h" +#include "gd32f10x_exti.h" + +#ifdef RT_USING_PIN + +#define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \ + GPIO_PIN_##pin, GPIO_PORT_SOURCE_GPIO##port, GPIO_PIN_SOURCE_##pin} +#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} + +/* GD32 GPIO driver */ +struct pin_index +{ + rt_int16_t index; + rcu_periph_enum clk; + rt_uint32_t gpio_periph; + rt_uint32_t pin; + rt_uint8_t port_src; + rt_uint8_t pin_src; +}; + +static const struct pin_index pins[] = +{ + __GD32_PIN(0 , A, 0 ), + __GD32_PIN(1 , A, 1 ), + __GD32_PIN(2 , A, 2 ), + __GD32_PIN(3 , A, 3 ), + __GD32_PIN(4 , A, 4 ), + __GD32_PIN(5 , A, 5 ), + __GD32_PIN(6 , A, 6 ), + __GD32_PIN(7 , A, 7 ), + __GD32_PIN(8 , A, 8 ), + __GD32_PIN(9 , A, 9 ), + __GD32_PIN(10, A, 10), + __GD32_PIN(11, A, 11), + __GD32_PIN(12, A, 12), + __GD32_PIN(13, A, 13), + __GD32_PIN(14, A, 14), + __GD32_PIN(15, A, 15), + + __GD32_PIN(16, B, 0), + __GD32_PIN(17, B, 1), + __GD32_PIN(18, B, 2), + __GD32_PIN(19, B, 3), + __GD32_PIN(20, B, 4), + __GD32_PIN(21, B, 5), + __GD32_PIN(22, B, 6), + __GD32_PIN(23, B, 7), + __GD32_PIN(24, B, 8), + __GD32_PIN(25, B, 9), + __GD32_PIN(26, B, 10), + __GD32_PIN(27, B, 11), + __GD32_PIN(28, B, 12), + __GD32_PIN(29, B, 13), + __GD32_PIN(30, B, 14), + __GD32_PIN(31, B, 15), + + __GD32_PIN(32, C, 0), + __GD32_PIN(33, C, 1), + __GD32_PIN(34, C, 2), + __GD32_PIN(35, C, 3), + __GD32_PIN(36, C, 4), + __GD32_PIN(37, C, 5), + __GD32_PIN(38, C, 6), + __GD32_PIN(39, C, 7), + __GD32_PIN(40, C, 8), + __GD32_PIN(41, C, 9), + __GD32_PIN(42, C, 10), + __GD32_PIN(43, C, 11), + __GD32_PIN(44, C, 12), + __GD32_PIN(45, C, 13), + __GD32_PIN(46, C, 14), + __GD32_PIN(47, C, 15), + + __GD32_PIN(48, D, 0), + __GD32_PIN(49, D, 1), + __GD32_PIN(50, D, 2), + __GD32_PIN(51, D, 3), + __GD32_PIN(52, D, 4), + __GD32_PIN(53, D, 5), + __GD32_PIN(54, D, 6), + __GD32_PIN(55, D, 7), + __GD32_PIN(56, D, 8), + __GD32_PIN(57, D, 9), + __GD32_PIN(58, D, 10), + __GD32_PIN(59, D, 11), + __GD32_PIN(60, D, 12), + __GD32_PIN(61, D, 13), + __GD32_PIN(62, D, 14), + __GD32_PIN(63, D, 15), + + __GD32_PIN(64, E, 0), + __GD32_PIN(65, E, 1), + __GD32_PIN(66, E, 2), + __GD32_PIN(67, E, 3), + __GD32_PIN(68, E, 4), + __GD32_PIN(69, E, 5), + __GD32_PIN(70, E, 6), + __GD32_PIN(71, E, 7), + __GD32_PIN(72, E, 8), + __GD32_PIN(73, E, 9), + __GD32_PIN(74, E, 10), + __GD32_PIN(75, E, 11), + __GD32_PIN(76, E, 12), + __GD32_PIN(77, E, 13), + __GD32_PIN(78, E, 14), + __GD32_PIN(79, E, 15), + + __GD32_PIN(80, F, 0), + __GD32_PIN(81, F, 1), + __GD32_PIN(82, F, 2), + __GD32_PIN(83, F, 3), + __GD32_PIN(84, F, 4), + __GD32_PIN(85, F, 5), + __GD32_PIN(86, F, 6), + __GD32_PIN(87, F, 7), + __GD32_PIN(88, F, 8), + __GD32_PIN(89, F, 9), + __GD32_PIN(90, F, 10), + __GD32_PIN(91, F, 11), + __GD32_PIN(92, F, 12), + __GD32_PIN(93, F, 13), + __GD32_PIN(94, F, 14), + __GD32_PIN(95, F, 15), + + __GD32_PIN(96, G, 0), + __GD32_PIN(97, G, 1), + __GD32_PIN(98, G, 2), + __GD32_PIN(99, G, 3), + __GD32_PIN(100, G, 4), + __GD32_PIN(101, G, 5), + __GD32_PIN(102, G, 6), + __GD32_PIN(103, G, 7), + __GD32_PIN(104, G, 8), + __GD32_PIN(105, G, 9), + __GD32_PIN(106, G, 10), + __GD32_PIN(107, G, 11), + __GD32_PIN(108, G, 12), + __GD32_PIN(109, G, 13), + __GD32_PIN(110, G, 14), + __GD32_PIN(111, G, 15), + + +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_9_IRQn}, + {GPIO_PIN_6, EXTI5_9_IRQn}, + {GPIO_PIN_7, EXTI5_9_IRQn}, + {GPIO_PIN_8, EXTI5_9_IRQn}, + {GPIO_PIN_9, EXTI5_9_IRQn}, + {GPIO_PIN_10, EXTI10_15_IRQn}, + {GPIO_PIN_11, EXTI10_15_IRQn}, + {GPIO_PIN_12, EXTI10_15_IRQn}, + {GPIO_PIN_13, EXTI10_15_IRQn}, + {GPIO_PIN_14, EXTI10_15_IRQn}, + {GPIO_PIN_15, EXTI10_15_IRQn}, +}; +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(rt_uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + rt_uint32_t pin_mode; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* GPIO Periph clock enable */ + rcu_periph_clock_enable(index->clk); + pin_mode = GPIO_MODE_OUT_PP; + + switch(mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + pin_mode = GPIO_MODE_OUT_PP; + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + pin_mode = GPIO_MODE_OUT_OD; + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + pin_mode = GPIO_MODE_IN_FLOATING; + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + pin_mode = GPIO_MODE_IPU; + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + pin_mode = GPIO_MODE_IPD; + break; + default: + break; + } + + gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); +} + +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); +} + +static int _pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = gpio_input_bit_get(index->gpio_periph, index->pin); + + return value; +} + + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + rt_uint8_t i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; +static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == pin && + pin_irq_hdr_tab[hdr_index].hdr == hdr && + pin_irq_hdr_tab[hdr_index].mode == mode && + pin_irq_hdr_tab[hdr_index].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[hdr_index].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EFULL; + } + pin_irq_hdr_tab[hdr_index].pin = pin; + pin_irq_hdr_tab[hdr_index].hdr = hdr; + pin_irq_hdr_tab[hdr_index].mode = mode; + pin_irq_hdr_tab[hdr_index].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[hdr_index].pin = -1; + pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; + pin_irq_hdr_tab[hdr_index].mode = 0; + pin_irq_hdr_tab[hdr_index].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t hdr_index = -1; + exti_trig_type_enum trigger_mode; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + if (enabled == PIN_IRQ_ENABLE) + { + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + irqmap = &pin_irq_map[hdr_index]; + + switch (pin_irq_hdr_tab[hdr_index].mode) + { + case PIN_IRQ_MODE_RISING: + trigger_mode = EXTI_TRIG_RISING; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = EXTI_TRIG_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = EXTI_TRIG_BOTH; + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + rcu_periph_clock_enable(RCU_AF); + + /* enable and set interrupt priority */ + nvic_irq_enable(irqmap->irqno, 5U, 0U); + + /* connect EXTI line to GPIO pin */ + gpio_exti_source_select(index->port_src, index->pin_src); + + /* configure EXTI line */ + exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); + exti_interrupt_flag_clear((exti_line_enum)(index->pin)); + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_EINVAL; + } + nvic_irq_disable(irqmap->irqno); + } + else + { + return RT_EINVAL; + } + + return RT_EOK; +} +const static struct rt_pin_ops _gd32_pin_ops = +{ + _pin_mode, + _pin_write, + _pin_read, + _pin_attach_irq, + _pin_detach_irq, + _pin_irq_enable, + RT_NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) +{ + if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) + { + pin_irq_hdr(exti_line); + exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); + } +} +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(0); + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(1); + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(2); + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(3); + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(4); + rt_interrupt_leave(); +} +void EXTI5_9_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(5); + GD32_GPIO_EXTI_IRQHandler(6); + GD32_GPIO_EXTI_IRQHandler(7); + GD32_GPIO_EXTI_IRQHandler(8); + GD32_GPIO_EXTI_IRQHandler(9); + rt_interrupt_leave(); +} +void EXTI10_15_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(10); + GD32_GPIO_EXTI_IRQHandler(11); + GD32_GPIO_EXTI_IRQHandler(12); + GD32_GPIO_EXTI_IRQHandler(13); + GD32_GPIO_EXTI_IRQHandler(14); + GD32_GPIO_EXTI_IRQHandler(15); + rt_interrupt_leave(); +} + +#endif diff --git a/bsp/gd32105c-eval/drivers/drv_gpio.h b/bsp/gd32105c-eval/drivers/drv_gpio.h new file mode 100644 index 0000000000..0cdedb9acb --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_gpio.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __GD32_PORT(port) GPIO##port + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN) + +#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) + +#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/gd32105c-eval/drivers/drv_i2c.c b/bsp/gd32105c-eval/drivers/drv_i2c.c new file mode 100644 index 0000000000..6d3d2cedcc --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_i2c.c @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#include "drv_i2c.h" +#include +#include "gd32f10x.h" + +#ifdef RT_USING_I2C + +#include + +#define DBG_TAG "drv.I2C" +#ifdef RT_I2C_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif +#include + +#ifdef RT_USING_I2C_BITOPS + +/*user can change this*/ +#define I2C_BUS_NAME "i2c2" + +/*user should change this to adapt specific board*/ +#define I2C_SCL_PIN GPIO_PIN_4 +#define I2C_SCL_PORT GPIOE +#define I2C_SCL_CLK RCU_GPIOE +#define I2C_SDA_PIN GPIO_PIN_5 +#define I2C_SDA_PORT GPIOE +#define I2C_SDA_CLK RCU_GPIOE + +struct gd32_i2c_bit_data +{ + struct + { + rcu_periph_enum clk; + rt_uint32_t port; + rt_uint32_t pin; + }scl, sda; +}; + +static void gpio_set_sda(void *data, rt_int32_t state) +{ + struct gd32_i2c_bit_data* bd = data; + + if (state) + { + gpio_bit_set(bd->sda.port, bd->sda.pin); + } + else + { + gpio_bit_reset(bd->sda.port, bd->sda.pin); + } +} + +static void gpio_set_scl(void *data, rt_int32_t state) +{ + struct gd32_i2c_bit_data* bd = data; + if (state) + { + gpio_bit_set(bd->scl.port, bd->scl.pin); + } + else + { + gpio_bit_reset(bd->scl.port, bd->scl.pin); + } +} + +static rt_int32_t gpio_get_sda(void *data) +{ + struct gd32_i2c_bit_data* bd = data; + + return gpio_input_bit_get(bd->sda.port, bd->sda.pin); +} + +static rt_int32_t gpio_get_scl(void *data) +{ + struct gd32_i2c_bit_data* bd = data; + + return gpio_input_bit_get(bd->scl.port, bd->scl.pin); +} + +static void gpio_udelay(rt_uint32_t us) +{ + int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us); + while(i) + { + i--; + } +} + +static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd) +{ + rcu_periph_clock_enable(bd->sda.clk); + rcu_periph_clock_enable(bd->scl.clk); + gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin); + gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin); + + gpio_bit_set(bd->sda.port, bd->sda.pin); + gpio_bit_set(bd->scl.port, bd->scl.pin); +} + +#else /* use hardware i2c */ + +struct gd32_i2c_bus +{ + struct rt_i2c_bus_device parent; + rt_uint32_t i2c_periph; +}; + +static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte) +{ + /* wait until I2C bus is idle */ + while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); + + /* send a start condition to I2C bus */ + i2c_start_on_bus(i2c_periph); + + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); + + /* send slave address to I2C bus */ + i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER); + + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); + + /* clear the ADDSEND bit */ + i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); + + if(1 == data_byte){ + /* disable acknowledge */ + i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(i2c_periph); + } + + /* while there is data to be read */ + while(data_byte) + { + /* wait until the RBNE bit is set and clear it */ + if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)) + { + /* read a byte from the EEPROM */ + *p_buffer = i2c_data_receive(i2c_periph); + + /* point to the next location where the byte read will be saved */ + p_buffer++; + + /* decrement the read bytes counter */ + data_byte--; + if(1 == data_byte) + { + /* disable acknowledge */ + i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(i2c_periph); + } + } + } + + /* wait until the stop condition is finished */ + while(I2C_CTL0(i2c_periph)&0x0200); + + /* enable acknowledge */ + i2c_ack_config(i2c_periph,I2C_ACK_ENABLE); + + i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT); + + return 0; +} + +static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte) +{ + /* wait until I2C bus is idle */ + while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); + + /* send a start condition to I2C bus */ + i2c_start_on_bus(i2c_periph); + + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); + + /* send slave address to I2C bus */ + i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER); + + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); + + /* clear the ADDSEND bit */ + i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); + + /* wait until the transmit data buffer is empty */ + while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE)); + + /* while there is data to be read */ + while(data_byte) + { + i2c_data_transmit(i2c_periph, *p_buffer); + + /* point to the next byte to be written */ + p_buffer++; + + /* decrement the write bytes counter */ + data_byte --; + + /* wait until BTC bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC)); + } + + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(i2c_periph); + + /* wait until the stop condition is finished */ + while(I2C_CTL0(i2c_periph)&0x0200); + + return 0; +} + +static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + rt_err_t ret = RT_ERROR; + + struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_ADDR_10BIT) + { + i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0); + } + else + { + i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0); + } + if (msg->flags & RT_I2C_RD) + { + if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) + { + LOG_E("i2c bus write failed,i2c bus stop!"); + goto out; + } + } + else + { + if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) + { + LOG_E("i2c bus write failed,i2c bus stop!"); + goto out; + } + } + } + + ret = i; + +out: + LOG_E("send stop condition\n"); + + return ret; +} + +static const struct rt_i2c_bus_device_ops i2c_ops = +{ + gd32_i2c_xfer, + RT_NULL, + RT_NULL +}; + +#endif /* RT_USING_I2C_BITOPS */ + +int rt_hw_i2c_init(void) +{ +#ifdef RT_USING_I2C_BITOPS + { + static struct rt_i2c_bus_device i2c_device; + static const struct gd32_i2c_bit_data _i2c_bdata = + { + /* SCL */ + { I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN}, + /* SDA */ + { I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN}, + }; + + static const struct rt_i2c_bit_ops _i2c_bit_ops = + { + (void*)&_i2c_bdata, + gpio_set_sda, + gpio_set_scl, + gpio_get_sda, + gpio_get_scl, + gpio_udelay, + 1, + 100 + }; + + drv_i2c_gpio_init(&_i2c_bdata); + + i2c_device.priv = (void *)&_i2c_bit_ops; + rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); + } + +#else /* register hardware I2C */ + +#ifdef RT_USING_I2C0 +#define I2C0_SPEED 100000 + + static struct gd32_i2c_bus gd32_i2c0; + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + + /* connect PB6 to I2C0_SCL, PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); + + /* enable I2C clock */ + rcu_periph_clock_enable(RCU_I2C0); + /* configure I2C clock */ + i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2); + + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0,I2C_ACK_ENABLE); + + rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus)); + gd32_i2c0.parent.ops = &i2c_ops; + gd32_i2c0.i2c_periph = I2C0; + rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0"); +#endif + +#ifdef RT_USING_I2C1 +#define I2C1_SPEED 100000 + + static struct gd32_i2c_bus gd32_i2c1; + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + + /* connect PB10 to I2C1_SCL, PB11 to I2C1_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11); + + /* enable I2C clock */ + rcu_periph_clock_enable(RCU_I2C1); + /* configure I2C clock */ + i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2); + + i2c_enable(I2C1); + /* enable acknowledge */ + i2c_ack_config(I2C1,I2C_ACK_ENABLE); + + rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus)); + gd32_i2c1.parent.ops = &i2c_ops; + gd32_i2c1.i2c_periph = I2C1; + rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1"); +#endif + +#endif /* RT_USING_I2C_BITOPS */ + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif +/* end of i2c driver */ diff --git a/components/libc/compilers/common/none-gcc/fcntl.h b/bsp/gd32105c-eval/drivers/drv_i2c.h similarity index 61% rename from components/libc/compilers/common/none-gcc/fcntl.h rename to bsp/gd32105c-eval/drivers/drv_i2c.h index f247b926e9..fb34ff2b09 100644 --- a/components/libc/compilers/common/none-gcc/fcntl.h +++ b/bsp/gd32105c-eval/drivers/drv_i2c.h @@ -5,14 +5,11 @@ * * Change Logs: * Date Author Notes + * 2021-08-23 lianzhian first implementation. */ -#ifndef FCNTL_H__ -#define FCNTL_H__ -#include +#ifndef __DRV_I2C__ +#define __DRV_I2C__ -#ifdef RT_USING_DFS -#include -#endif #endif diff --git a/bsp/gd32105c-eval/drivers/drv_spi.c b/bsp/gd32105c-eval/drivers/drv_spi.c new file mode 100644 index 0000000000..3f9e86cb41 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_spi.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#include "drv_spi.h" +#include "gd32f10x.h" +#include + +#if defined(RT_USING_SPI) && defined(RT_USING_PIN) +#include + +#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \ + !defined(RT_USING_SPI2) +#error "Please define at least one SPIx" +#endif + +/* #define DEBUG */ +#ifdef DEBUG +#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) +#endif + +/* private rt-thread spi ops function */ +static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); +static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); + +static struct rt_spi_ops gd32_spi_ops = +{ + configure, + xfer +}; + +static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) +{ + spi_parameter_struct spi_init_struct; + + rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + if(configuration->data_width <= 8) + { + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + } + else if(configuration->data_width <= 16) + { + spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT; + } + else + { + return RT_EIO; + } + + { + rcu_clock_freq_enum spi_src; + rt_uint32_t spi_apb_clock; + rt_uint32_t max_hz; + + max_hz = configuration->max_hz; + + DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS)); + DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2)); + DEBUG_PRINTF("max freq: %d\n", max_hz); + + if (spi_periph == SPI1 || spi_periph == SPI2) + { + spi_src = CK_APB1; + } + else + { + spi_src = CK_APB2; + } + spi_apb_clock = rcu_clock_freq_get(spi_src); + + if(max_hz >= spi_apb_clock/2) + { + spi_init_struct.prescale = SPI_PSC_2; + } + else if (max_hz >= spi_apb_clock/4) + { + spi_init_struct.prescale = SPI_PSC_4; + } + else if (max_hz >= spi_apb_clock/8) + { + spi_init_struct.prescale = SPI_PSC_8; + } + else if (max_hz >= spi_apb_clock/16) + { + spi_init_struct.prescale = SPI_PSC_16; + } + else if (max_hz >= spi_apb_clock/32) + { + spi_init_struct.prescale = SPI_PSC_32; + } + else if (max_hz >= spi_apb_clock/64) + { + spi_init_struct.prescale = SPI_PSC_64; + } + else if (max_hz >= spi_apb_clock/128) + { + spi_init_struct.prescale = SPI_PSC_128; + } + else + { + /* min prescaler 256 */ + spi_init_struct.prescale = SPI_PSC_256; + } + } /* baudrate */ + + switch(configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + break; + case RT_SPI_MODE_1: + spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; + break; + case RT_SPI_MODE_2: + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; + break; + case RT_SPI_MODE_3: + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + break; + } + + /* MSB or LSB */ + if(configuration->mode & RT_SPI_MSB) + { + spi_init_struct.endian = SPI_ENDIAN_MSB; + } + else + { + spi_init_struct.endian = SPI_ENDIAN_LSB; + } + + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_MASTER; + spi_init_struct.nss = SPI_NSS_SOFT; + + spi_init(spi_periph, &spi_init_struct); + + spi_crc_off(spi_periph); + + spi_enable(spi_periph); + + return RT_EOK; +}; + +static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) +{ + rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data; + rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; + struct rt_spi_configuration * config = &device->config; + + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + + /* take CS */ + if(message->cs_take) + { + rt_pin_write(gd32_cs_pin, PIN_LOW); + DEBUG_PRINTF("spi take cs\n"); + } + + { + if(config->data_width <= 8) + { + const rt_uint8_t * send_ptr = message->send_buf; + rt_uint8_t * recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + DEBUG_PRINTF("spi poll transfer start: %d\n", size); + + while(size--) + { + rt_uint8_t data = 0xFF; + + if(send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /* Todo: replace register read/write by gd32f3 lib */ + /* Wait until the transmit buffer is empty */ + while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); + /* Send the byte */ + spi_i2s_data_transmit(spi_periph, data); + + /* Wait until a data is received */ + while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); + /* Get the received data */ + data = spi_i2s_data_receive(spi_periph); + + if(recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + DEBUG_PRINTF("spi poll transfer finsh\n"); + } + else if(config->data_width <= 16) + { + const rt_uint16_t * send_ptr = message->send_buf; + rt_uint16_t * recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + while(size--) + { + rt_uint16_t data = 0xFF; + + if(send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /*Wait until the transmit buffer is empty */ + while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); + /* Send the byte */ + spi_i2s_data_transmit(spi_periph, data); + + /*Wait until a data is received */ + while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); + /* Get the received data */ + data = spi_i2s_data_receive(spi_periph); + + if(recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + } + } + + /* release CS */ + if(message->cs_release) + { + rt_pin_write(gd32_cs_pin, PIN_HIGH); + DEBUG_PRINTF("spi release cs\n"); + } + + return message->length; +}; + +int gd32_hw_spi_init(void) +{ + int result = 0; +#ifdef RT_USING_SPI0 + static struct rt_spi_bus spi_bus0; + spi_bus0.parent.user_data = (void *)SPI0; + + result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops); + + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_SPI0); + /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + +#endif +#ifdef RT_USING_SPI1 + static struct rt_spi_bus spi_bus1; + spi_bus1.parent.user_data = (void *)SPI1; + + result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops); + + rcu_periph_clock_enable(RCU_SPI1); + rcu_periph_clock_enable(RCU_GPIOB); + + /* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15); + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14); +#endif +#ifdef RT_USING_SPI2 + static struct rt_spi_bus spi_bus2; + spi_bus2.parent.user_data = (void *)SPI2; + + result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); + + rcu_periph_clock_enable(RCU_SPI2); + rcu_periph_clock_enable(RCU_GPIOB); + + /* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5); + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4); +#endif + return result; +} +INIT_BOARD_EXPORT(gd32_hw_spi_init); +#endif diff --git a/bsp/gd32105c-eval/drivers/drv_spi.h b/bsp/gd32105c-eval/drivers/drv_spi.h new file mode 100644 index 0000000000..b4d768c5f5 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_spi.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef gd32F30X_SPI_H_INCLUDED +#define gd32F30X_SPI_H_INCLUDED + + +#endif /* gd32F30X_SPI_H_INCLUDED */ diff --git a/bsp/gd32105c-eval/drivers/drv_spi_flash.c b/bsp/gd32105c-eval/drivers/drv_spi_flash.c new file mode 100644 index 0000000000..d013c73ad0 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_spi_flash.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ +#include +#include +#include +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +#define SPI_BUS_NAME "spi0" +#define SPI_DEVICE_NAME "spi01" +#define SPI_FLASH_DEVICE_NAME "gd25q" +#define GD25Q_SPI_CS_PIN 67 /* PE3，在 drv_gpio.c 文件 pin_index pins[]中查到 PE3 编号为 67 */ + +static int rt_hw_gd25q40_init(void) +{ + rt_err_t res; + static struct rt_spi_device spi_dev_gd25q; /* SPI设备对象 */ + static rt_base_t gd25q_cs_pin; /* SPI设备CS片选引脚 */ + + gd25q_cs_pin = GD25Q_SPI_CS_PIN; + + rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP); + + res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin); + if (res != RT_EOK) + { + rt_kprintf("rt_spi_bus_attach_device() run failed!\n"); + return res; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_gd25q40_init); + +static int rt_hw_spi_flash_with_sfud_init(void) +{ + if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_DEVICE_NAME, SPI_DEVICE_NAME)) + { + return RT_ERROR; + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); + +#ifdef RT_USING_DFS +#include + +int mnt_init(void) +{ + if (dfs_mount(SPI_FLASH_DEVICE_NAME, "/", "elm", 0, 0) == 0) + { + rt_kprintf("spi flash mount success !\n"); + } + else + { + rt_kprintf("spi flash mount failed!\n"); + } + + return 0; +} +MSH_CMD_EXPORT(mnt_init, mount spi flash to file system); +#endif diff --git a/bsp/gd32105c-eval/drivers/drv_usart.c b/bsp/gd32105c-eval/drivers/drv_usart.c new file mode 100644 index 0000000000..6dbe467ab8 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_usart.c @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ +#include +#include +#include +#include + +#ifdef RT_USING_SERIAL + +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) && \ + !defined(RT_USING_USART2) && !defined(RT_USING_UART3) && \ + !defined(RT_USING_UART4) +#error "Please define at least one UARTx" + +#endif + +#include + +/* GD32 uart driver */ +/* Todo: compress uart info */ +struct gd32_uart +{ + uint32_t uart_periph; + IRQn_Type irqn; + rcu_periph_enum per_clk; + rcu_periph_enum tx_gpio_clk; + rcu_periph_enum rx_gpio_clk; + uint32_t tx_port; + uint16_t tx_pin; + uint32_t rx_port; + uint16_t rx_pin; + + struct rt_serial_device * serial; + char *device_name; +}; + +static void uart_isr(struct rt_serial_device *serial); + +#if defined(RT_USING_USART0) +struct rt_serial_device serial0; + +void USART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial0); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_USART0 */ + +#if defined(RT_USING_USART1) +struct rt_serial_device serial1; + +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_UART1 */ + +#if defined(RT_USING_USART2) +struct rt_serial_device serial2; + +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART3) +struct rt_serial_device serial3; + +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial3); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_UART3 */ + +#if defined(RT_USING_UART4) +struct rt_serial_device serial4; + +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial4); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_USING_UART4 */ + +static const struct gd32_uart uarts[] = { + #ifdef RT_USING_USART0 + { + USART0, /* uart peripheral index */ + USART0_IRQn, /* uart iqrn */ + RCU_USART0, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOA, GPIO_PIN_9, /* tx port, tx pin */ + GPIOA, GPIO_PIN_10, /* rx port, rx pin */ + &serial0, + "uart0", + }, + #endif + + #ifdef RT_USING_USART1 + { + USART1, /* uart peripheral index */ + USART1_IRQn, /* uart iqrn */ + RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOA, GPIO_PIN_2, /* tx port, tx pin */ + GPIOA, GPIO_PIN_3, /* rx port, rx pin */ + &serial1, + "uart1", + }, + #endif + + #ifdef RT_USING_USART2 + { + USART2, /* uart peripheral index */ + USART2_IRQn, /* uart iqrn */ + RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOB, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ + GPIOB, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ + &serial2, + "uart2", + }, + #endif + + #ifdef RT_USING_UART3 + { + UART3, /* uart peripheral index */ + UART3_IRQn, /* uart iqrn */ + RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOC, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ + GPIOC, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ + &serial3, + "uart3", + }, + #endif + + #ifdef RT_USING_UART4 + { + UART4, /* uart peripheral index */ + UART4_IRQn, /* uart iqrn */ + RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOC, GPIO_PIN_12, /* tx port, tx alternate, tx pin */ + GPIOD, GPIO_PIN_2, /* rx port, rx alternate, rx pin */ + &serial4, + "uart4", + }, + #endif +}; + + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example: +* - Peripheral's clock enable +* - Peripheral's GPIO Configuration +* - NVIC configuration for UART interrupt request enable +* @param uart: UART handle pointer +* @retval None +*/ +void gd32_uart_gpio_init(struct gd32_uart *uart) +{ + /* enable USART clock */ + rcu_periph_clock_enable(uart->tx_gpio_clk); + rcu_periph_clock_enable(uart->rx_gpio_clk); + rcu_periph_clock_enable(uart->per_clk); + + /* connect port to USARTx_Tx */ + gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); + + /* connect port to USARTx_Rx */ + gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); + + NVIC_SetPriority(uart->irqn, 0); + NVIC_EnableIRQ(uart->irqn); +} + +static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct gd32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = (struct gd32_uart *)serial->parent.user_data; + + gd32_uart_gpio_init(uart); + + usart_baudrate_set(uart->uart_periph, cfg->baud_rate); + + switch (cfg->data_bits) + { + case DATA_BITS_9: + usart_word_length_set(uart->uart_periph, USART_WL_9BIT); + break; + + default: + usart_word_length_set(uart->uart_periph, USART_WL_8BIT); + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT); + break; + default: + usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT); + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + usart_parity_config(uart->uart_periph, USART_PM_ODD); + break; + case PARITY_EVEN: + usart_parity_config(uart->uart_periph, USART_PM_EVEN); + break; + default: + usart_parity_config(uart->uart_periph, USART_PM_NONE); + break; + } + + usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE); + usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE); + usart_enable(uart->uart_periph); + + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct gd32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct gd32_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irqn); + /* disable interrupt */ + usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); + + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irqn); + /* enable interrupt */ + usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); + break; + } + + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial, char ch) +{ + struct gd32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct gd32_uart *)serial->parent.user_data; + + usart_data_transmit(uart->uart_periph, ch); + while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); + + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct gd32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct gd32_uart *)serial->parent.user_data; + + ch = -1; + if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET) + ch = usart_data_receive(uart->uart_periph); + return ch; +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data; + + RT_ASSERT(uart != RT_NULL); + + /* UART in mode Receiver */ + if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && + (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + /* Clear RXNE interrupt flag */ + usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE); + } +} + +static const struct rt_uart_ops gd32_uart_ops = +{ + _uart_configure, + _uart_control, + _uart_putc, + _uart_getc +}; + +int gd32_hw_usart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + int i; + + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) + { + uarts[i].serial->ops = &gd32_uart_ops; + uarts[i].serial->config = config; + + /* register UART device */ + rt_hw_serial_register(uarts[i].serial, + uarts[i].device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + (void *)&uarts[i]); + } + + return 0; +} +INIT_BOARD_EXPORT(gd32_hw_usart_init); +#endif diff --git a/bsp/gd32105c-eval/drivers/drv_usart.h b/bsp/gd32105c-eval/drivers/drv_usart.h new file mode 100644 index 0000000000..f575ad3810 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/drv_usart.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef __USART_H__ +#define __USART_H__ + + +#endif diff --git a/bsp/gd32105c-eval/drivers/gd32f10x_libopt.h b/bsp/gd32105c-eval/drivers/gd32f10x_libopt.h new file mode 100644 index 0000000000..a4dd11b017 --- /dev/null +++ b/bsp/gd32105c-eval/drivers/gd32f10x_libopt.h @@ -0,0 +1,67 @@ +/*! + \file gd32f10x_libopt.h + \brief library optional for gd32f10x + \version 2014-12-26, V1.0.0, demo for GD32F10x + \version 2017-06-30, V2.0.0, demo for GD32F10x + \version 2018-07-31, V2.1.0, demo for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_LIBOPT_H +#define GD32F10X_LIBOPT_H + +#include "gd32f10x_rcu.h" +#include "gd32f10x_adc.h" +#include "gd32f10x_can.h" +#include "gd32f10x_crc.h" +#include "gd32f10x_dac.h" +#include "gd32f10x_dbg.h" +#include "gd32f10x_dma.h" +#include "gd32f10x_exti.h" +#include "gd32f10x_fmc.h" +#include "gd32f10x_fwdgt.h" +#include "gd32f10x_gpio.h" +#include "gd32f10x_i2c.h" +#include "gd32f10x_pmu.h" +#include "gd32f10x_bkp.h" +#include "gd32f10x_rtc.h" +#include "gd32f10x_sdio.h" +#include "gd32f10x_spi.h" +#include "gd32f10x_timer.h" +#include "gd32f10x_usart.h" +#include "gd32f10x_wwdgt.h" +#include "gd32f10x_misc.h" +#include "gd32f10x_exmc.h" +#ifdef GD32F10X_CL +#include "gd32f10x_enet.h" +#endif /* GD32F10X_CL */ + +#endif /* GD32F10X_LIBOPT_H */ diff --git a/bsp/gd32105c-eval/list/context_rvds.lst b/bsp/gd32105c-eval/list/context_rvds.lst new file mode 100644 index 0000000000..0049e2543b --- /dev/null +++ b/bsp/gd32105c-eval/list/context_rvds.lst @@ -0,0 +1,515 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;/* + 2 00000000 ; * Copyright (c) 2006-2018, RT-Thread Development Team + 3 00000000 ; * + 4 00000000 ; * SPDX-License-Identifier: Apache-2.0 + 5 00000000 ; * + 6 00000000 ; * Change Logs: + 7 00000000 ; * Date Author Notes + 8 00000000 ; * 2009-01-17 Bernard first version + 9 00000000 ; * 2013-06-18 aozima add restore MSP feature. + + 10 00000000 ; * 2013-07-09 aozima enhancement hard fault e + xception handler. + 11 00000000 ; */ + 12 00000000 + 13 00000000 ;/** + 14 00000000 ; * @addtogroup CORTEX-M3 + 15 00000000 ; */ + 16 00000000 ;/*@{*/ + 17 00000000 + 18 00000000 E000ED08 + SCB_VTOR + EQU 0xE000ED08 ; Vector Table Offs + et Register + 19 00000000 E000ED04 + NVIC_INT_CTRL + EQU 0xE000ED04 ; interrupt control + state register + 20 00000000 E000ED20 + NVIC_SYSPRI2 + EQU 0xE000ED20 ; system priority r + egister (2) + 21 00000000 FFFF0000 + NVIC_PENDSV_PRI + EQU 0xFFFF0000 ; PendSV and SysTic + k priority value (l + owest) + 22 00000000 10000000 + NVIC_PENDSVSET + EQU 0x10000000 ; value to trigger + PendSV exception + 23 00000000 + 24 00000000 AREA |.text|, CODE, READONLY, ALIGN= +2 + 25 00000000 THUMB + 26 00000000 REQUIRE8 + 27 00000000 PRESERVE8 + 28 00000000 + 29 00000000 IMPORT rt_thread_switch_interrupt_flag + 30 00000000 IMPORT rt_interrupt_from_thread + 31 00000000 IMPORT rt_interrupt_to_thread + 32 00000000 + 33 00000000 ;/* + 34 00000000 ; * rt_base_t rt_hw_interrupt_disable(); + 35 00000000 ; */ + 36 00000000 rt_hw_interrupt_disable + PROC + 37 00000000 EXPORT rt_hw_interrupt_disable + 38 00000000 F3EF 8010 MRS r0, PRIMASK + 39 00000004 B672 CPSID I + + + +ARM Macro Assembler Page 2 + + + 40 00000006 4770 BX LR + 41 00000008 ENDP + 42 00000008 + 43 00000008 ;/* + 44 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level); + 45 00000008 ; */ + 46 00000008 rt_hw_interrupt_enable + PROC + 47 00000008 EXPORT rt_hw_interrupt_enable + 48 00000008 F380 8810 MSR PRIMASK, r0 + 49 0000000C 4770 BX LR + 50 0000000E ENDP + 51 0000000E + 52 0000000E ;/* + 53 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 + to); + 54 0000000E ; * r0 --> from + 55 0000000E ; * r1 --> to + 56 0000000E ; */ + 57 0000000E rt_hw_context_switch_interrupt + 58 0000000E EXPORT rt_hw_context_switch_interrupt + 59 0000000E rt_hw_context_switch + PROC + 60 0000000E EXPORT rt_hw_context_switch + 61 0000000E + 62 0000000E ; set rt_thread_switch_interrupt_flag to 1 + 63 0000000E 4A32 LDR r2, =rt_thread_switch_interrupt +_flag + 64 00000010 6813 LDR r3, [r2] + 65 00000012 2B01 CMP r3, #1 + 66 00000014 D004 BEQ _reswitch + 67 00000016 F04F 0301 MOV r3, #1 + 68 0000001A 6013 STR r3, [r2] + 69 0000001C + 70 0000001C 4A2F LDR r2, =rt_interrupt_from_thread ; + set rt_interrupt_f + rom_thread + 71 0000001E 6010 STR r0, [r2] + 72 00000020 + 73 00000020 _reswitch + 74 00000020 4A2F LDR r2, =rt_interrupt_to_thread ; s + et rt_interrupt_to_ + thread + 75 00000022 6011 STR r1, [r2] + 76 00000024 + 77 00000024 482F LDR r0, =NVIC_INT_CTRL ; trigger th + e PendSV exception + (causes context swi + tch) + 78 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET + 79 0000002A 6001 STR r1, [r0] + 80 0000002C 4770 BX LR + 81 0000002E ENDP + 82 0000002E + 83 0000002E ; r0 --> switch from thread stack + 84 0000002E ; r1 --> switch to thread stack + 85 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from + ] stack + 86 0000002E PendSV_Handler + + + +ARM Macro Assembler Page 3 + + + PROC + 87 0000002E EXPORT PendSV_Handler + 88 0000002E + 89 0000002E ; disable interrupt to protect context switch + 90 0000002E F3EF 8210 MRS r2, PRIMASK + 91 00000032 B672 CPSID I + 92 00000034 + 93 00000034 ; get rt_thread_switch_interrupt_flag + 94 00000034 4828 LDR r0, =rt_thread_switch_interrupt +_flag + 95 00000036 6801 LDR r1, [r0] + 96 00000038 B191 CBZ r1, pendsv_exit ; pendsv alread + y handled + 97 0000003A + 98 0000003A ; clear rt_thread_switch_interrupt_flag to 0 + 99 0000003A F04F 0100 MOV r1, #0x00 + 100 0000003E 6001 STR r1, [r0] + 101 00000040 + 102 00000040 4826 LDR r0, =rt_interrupt_from_thread + 103 00000042 6801 LDR r1, [r0] + 104 00000044 B129 CBZ r1, switch_to_thread ; skip reg + ister save at the f + irst time + 105 00000046 + 106 00000046 F3EF 8109 MRS r1, psp ; get from thread s + tack pointer + 107 0000004A E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11 + register + 108 0000004E 6800 LDR r0, [r0] + 109 00000050 6001 STR r1, [r0] ; update from threa + d stack pointer + 110 00000052 + 111 00000052 switch_to_thread + 112 00000052 4923 LDR r1, =rt_interrupt_to_thread + 113 00000054 6809 LDR r1, [r1] + 114 00000056 6809 LDR r1, [r1] ; load thread stack + pointer + 115 00000058 + 116 00000058 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11 + register + 117 0000005C F381 8809 MSR psp, r1 ; update stack poin + ter + 118 00000060 + 119 00000060 pendsv_exit + 120 00000060 ; restore interrupt + 121 00000060 F382 8810 MSR PRIMASK, r2 + 122 00000064 + 123 00000064 F04E 0E04 ORR lr, lr, #0x04 + 124 00000068 4770 BX lr + 125 0000006A ENDP + 126 0000006A + 127 0000006A ;/* + 128 0000006A ; * void rt_hw_context_switch_to(rt_uint32 to); + 129 0000006A ; * r0 --> to + 130 0000006A ; * this fucntion is used to perform the first thread sw + itch + 131 0000006A ; */ + 132 0000006A rt_hw_context_switch_to + PROC + + + +ARM Macro Assembler Page 4 + + + 133 0000006A EXPORT rt_hw_context_switch_to + 134 0000006A ; set to thread + 135 0000006A 491D LDR r1, =rt_interrupt_to_thread + 136 0000006C 6008 STR r0, [r1] + 137 0000006E + 138 0000006E ; set from thread to 0 + 139 0000006E 491B LDR r1, =rt_interrupt_from_thread + 140 00000070 F04F 0000 MOV r0, #0x0 + 141 00000074 6008 STR r0, [r1] + 142 00000076 + 143 00000076 ; set interrupt flag to 1 + 144 00000076 4918 LDR r1, =rt_thread_switch_interrupt +_flag + 145 00000078 F04F 0001 MOV r0, #1 + 146 0000007C 6008 STR r0, [r1] + 147 0000007E + 148 0000007E ; set the PendSV and SysTick exception priority + 149 0000007E 481A LDR r0, =NVIC_SYSPRI2 + 150 00000080 491A LDR r1, =NVIC_PENDSV_PRI + 151 00000082 F8D0 2000 LDR.W r2, [r0,#0x00] ; read + 152 00000086 EA41 0102 ORR r1,r1,r2 ; modify + 153 0000008A 6001 STR r1, [r0] ; write-back + 154 0000008C + 155 0000008C ; trigger the PendSV exception (causes context switch) + 156 0000008C 4815 LDR r0, =NVIC_INT_CTRL + 157 0000008E F04F 5180 LDR r1, =NVIC_PENDSVSET + 158 00000092 6001 STR r1, [r0] + 159 00000094 + 160 00000094 ; restore MSP + 161 00000094 4816 LDR r0, =SCB_VTOR + 162 00000096 6800 LDR r0, [r0] + 163 00000098 6800 LDR r0, [r0] + 164 0000009A F380 8808 MSR msp, r0 + 165 0000009E + 166 0000009E ; enable interrupts at processor level + 167 0000009E B661 CPSIE F + 168 000000A0 B662 CPSIE I + 169 000000A2 + 170 000000A2 ; never reach here! + 171 000000A2 ENDP + 172 000000A2 + 173 000000A2 ; compatible with old version + 174 000000A2 rt_hw_interrupt_thread_switch + PROC + 175 000000A2 EXPORT rt_hw_interrupt_thread_switch + 176 000000A2 4770 BX lr + 177 000000A4 ENDP + 178 000000A4 + 179 000000A4 IMPORT rt_hw_hard_fault_exception + 180 000000A4 EXPORT HardFault_Handler + 181 000000A4 HardFault_Handler + PROC + 182 000000A4 + 183 000000A4 ; get current context + 184 000000A4 F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] + ) + 185 000000A8 BF0C ITE EQ + 186 000000AA F3EF 8008 MRSEQ r0, msp ; [2]=0 ==> Z=1, ge + t fault context fro + + + +ARM Macro Assembler Page 5 + + + m handler. + 187 000000AE F3EF 8009 MRSNE r0, psp ; [2]=1 ==> Z=0, ge + t fault context fro + m thread. + 188 000000B2 + 189 000000B2 E920 0FF0 STMFD r0!, {r4 - r11} ; push r4 - r11 + register + 190 000000B6 F840 ED04 STMFD r0!, {lr} ; push exec_return + register + 191 000000BA + 192 000000BA F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] + ) + 193 000000BE BF0C ITE EQ + 194 000000C0 F380 8808 MSREQ msp, r0 ; [2]=0 ==> Z=1, up + date stack pointer + to MSP. + 195 000000C4 F380 8809 MSRNE psp, r0 ; [2]=1 ==> Z=0, up + date stack pointer + to PSP. + 196 000000C8 + 197 000000C8 B500 PUSH {lr} + 198 000000CA F7FF FFFE BL rt_hw_hard_fault_exception + 199 000000CE F85D EB04 POP {lr} + 200 000000D2 + 201 000000D2 F04E 0E04 ORR lr, lr, #0x04 + 202 000000D6 4770 BX lr + 203 000000D8 ENDP + 204 000000D8 + 205 000000D8 ALIGN 4 + 206 000000D8 + 207 000000D8 END + 00000000 + 00000000 + 00000000 + E000ED04 + E000ED20 + FFFF0000 + E000ED08 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=.\output\context_rvds.d -o.\output\context_rvds.o -IE:\code\rtt\rt +-thread\bsp\gd32105c-eval\RTE -ID:\Keil_v5\ARM\PACK\GigaDevice\GD32F10x_DFP\2.0 +.1\Device\Include -ID:\Keil_v5\ARM\CMSIS\Include --predefine="__MICROLIB SETA 1 +" --predefine="__UVISION_VERSION SETA 514" --predefine="GD32F10X_CL SETA 1" --p +redefine="USE_STDPERIPH_DRIVER SETA 1" --list=.\list\context_rvds.lst ..\..\lib +cpu\arm\cortex-m3\context_rvds.S + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 24 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + None +Comment: .text unused +HardFault_Handler 000000A4 + +Symbol: HardFault_Handler + Definitions + At line 181 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 180 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: HardFault_Handler used once +PendSV_Handler 0000002E + +Symbol: PendSV_Handler + Definitions + At line 86 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 87 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: PendSV_Handler used once +_reswitch 00000020 + +Symbol: _reswitch + Definitions + At line 73 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 66 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: _reswitch used once +pendsv_exit 00000060 + +Symbol: pendsv_exit + Definitions + At line 119 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 96 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: pendsv_exit used once +rt_hw_context_switch 0000000E + +Symbol: rt_hw_context_switch + Definitions + At line 59 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 60 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_context_switch used once +rt_hw_context_switch_interrupt 0000000E + +Symbol: rt_hw_context_switch_interrupt + Definitions + At line 57 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 58 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_context_switch_interrupt used once +rt_hw_context_switch_to 0000006A + +Symbol: rt_hw_context_switch_to + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 132 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 133 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_context_switch_to used once +rt_hw_interrupt_disable 00000000 + +Symbol: rt_hw_interrupt_disable + Definitions + At line 36 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 37 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_interrupt_disable used once +rt_hw_interrupt_enable 00000008 + +Symbol: rt_hw_interrupt_enable + Definitions + At line 46 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 47 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_interrupt_enable used once +rt_hw_interrupt_thread_switch 000000A2 + +Symbol: rt_hw_interrupt_thread_switch + Definitions + At line 174 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 175 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_interrupt_thread_switch used once +switch_to_thread 00000052 + +Symbol: switch_to_thread + Definitions + At line 111 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 104 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: switch_to_thread used once +12 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +NVIC_INT_CTRL E000ED04 + +Symbol: NVIC_INT_CTRL + Definitions + At line 19 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 77 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 156 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +NVIC_PENDSVSET 10000000 + +Symbol: NVIC_PENDSVSET + Definitions + At line 22 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 78 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 157 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +NVIC_PENDSV_PRI FFFF0000 + +Symbol: NVIC_PENDSV_PRI + Definitions + At line 21 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 150 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: NVIC_PENDSV_PRI used once +NVIC_SYSPRI2 E000ED20 + +Symbol: NVIC_SYSPRI2 + Definitions + At line 20 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 149 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: NVIC_SYSPRI2 used once +SCB_VTOR E000ED08 + +Symbol: SCB_VTOR + Definitions + At line 18 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 161 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: SCB_VTOR used once +5 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +rt_hw_hard_fault_exception 00000000 + +Symbol: rt_hw_hard_fault_exception + Definitions + At line 179 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 198 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_hard_fault_exception used once +rt_interrupt_from_thread 00000000 + +Symbol: rt_interrupt_from_thread + Definitions + At line 30 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 70 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 102 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 139 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +rt_interrupt_to_thread 00000000 + +Symbol: rt_interrupt_to_thread + Definitions + At line 31 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 74 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 112 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 135 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +rt_thread_switch_interrupt_flag 00000000 + +Symbol: rt_thread_switch_interrupt_flag + Definitions + At line 29 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 63 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 94 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 144 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +4 symbols +357 symbols in table diff --git a/bsp/gd32105c-eval/list/startup_gd32f10x_cl.lst b/bsp/gd32105c-eval/list/startup_gd32f10x_cl.lst new file mode 100644 index 0000000000..0944b6bb38 --- /dev/null +++ b/bsp/gd32105c-eval/list/startup_gd32f10x_cl.lst @@ -0,0 +1,1850 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;/*! + 2 00000000 ; \file startup_gd32f10x_cl.s + 3 00000000 ; \brief start up file + 4 00000000 ; + 5 00000000 ; \version 2014-12-26, V1.0.0, firmware for GD32F10x + 6 00000000 ; \version 2017-06-20, V2.0.0, firmware for GD32F10x + 7 00000000 ; \version 2018-07-31, V2.1.0, firmware for GD32F10x + 8 00000000 ;*/ + 9 00000000 ; + 10 00000000 ;/* + 11 00000000 ; Copyright (c) 2018, GigaDevice Semiconductor Inc. + 12 00000000 ; + 13 00000000 ; All rights reserved. + 14 00000000 ; + 15 00000000 ; Redistribution and use in source and binary forms, + with or without modification, + 16 00000000 ;are permitted provided that the following conditions ar + e met: + 17 00000000 ; + 18 00000000 ; 1. Redistributions of source code must retain the a + bove copyright notice, this + 19 00000000 ; list of conditions and the following disclaimer. + + 20 00000000 ; 2. Redistributions in binary form must reproduce th + e above copyright notice, + 21 00000000 ; this list of conditions and the following discla + imer in the documentation + 22 00000000 ; and/or other materials provided with the distrib + ution. + 23 00000000 ; 3. Neither the name of the copyright holder nor the + names of its contributors + 24 00000000 ; may be used to endorse or promote products deriv + ed from this software without + 25 00000000 ; specific prior written permission. + 26 00000000 ; + 27 00000000 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS + AND CONTRIBUTORS "AS IS" + 28 00000000 ;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT N + OT LIMITED TO, THE IMPLIED + 29 00000000 ;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU + LAR PURPOSE ARE DISCLAIMED. + 30 00000000 ;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS + BE LIABLE FOR ANY DIRECT, + 31 00000000 ;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENT + IAL DAMAGES (INCLUDING, BUT + 32 00000000 ;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV + ICES; LOSS OF USE, DATA, OR + 33 00000000 ;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND O + N ANY THEORY OF LIABILITY, + 34 00000000 ;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDI + NG NEGLIGENCE OR OTHERWISE) + 35 00000000 ;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVE + N IF ADVISED OF THE POSSIBILITY + 36 00000000 ;OF SUCH DAMAGE. + 37 00000000 ;*/ + 38 00000000 + 39 00000000 ; Stack Configuration + 40 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 41 00000000 ; + + + +ARM Macro Assembler Page 2 + + + 42 00000000 + 43 00000000 00002000 + Stack_Size + EQU 0x00002000 + 44 00000000 + 45 00000000 AREA STACK, NOINIT, READWRITE, ALIGN + = 3 + 46 00000000 Stack_Mem + SPACE Stack_Size + 47 00002000 __initial_sp + 48 00002000 + 49 00002000 + 50 00002000 ; Heap Configuration + 51 00002000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 52 00002000 ; + 53 00002000 + 54 00002000 00002000 + Heap_Size + EQU 0x00002000 + 55 00002000 + 56 00002000 AREA HEAP, NOINIT, READWRITE, ALIGN += 3 + 57 00000000 __heap_base + 58 00000000 Heap_Mem + SPACE Heap_Size + 59 00002000 __heap_limit + 60 00002000 + 61 00002000 + 62 00002000 PRESERVE8 + 63 00002000 THUMB + 64 00002000 + 65 00002000 ; /* reset Vector Mapped to at Address + 0 */ + 66 00002000 AREA RESET, DATA, READONLY + 67 00000000 EXPORT __Vectors + 68 00000000 EXPORT __Vectors_End + 69 00000000 EXPORT __Vectors_Size + 70 00000000 + 71 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 72 00000004 00000000 DCD Reset_Handler ; Reset Handler + 73 00000008 00000000 DCD NMI_Handler ; NMI Handler + 74 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 75 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 76 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 77 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 78 0000001C 00000000 DCD 0 ; Reserved + 79 00000020 00000000 DCD 0 ; Reserved + 80 00000024 00000000 DCD 0 ; Reserved + 81 00000028 00000000 DCD 0 ; Reserved + 82 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 83 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + + + +ARM Macro Assembler Page 3 + + + r Handler + 84 00000034 00000000 DCD 0 ; Reserved + 85 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 86 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 87 00000040 + 88 00000040 ; /* external interrupts handler */ + 89 00000040 00000000 DCD WWDGT_IRQHandler ; 16:Window Wa + tchdog Timer + 90 00000044 00000000 DCD LVD_IRQHandler ; 17:LVD through + EXTI Line detect + 91 00000048 00000000 DCD TAMPER_IRQHandler ; 18:Tamper I + nterrupt + 92 0000004C 00000000 DCD RTC_IRQHandler ; 19:RTC through + EXTI Line + 93 00000050 00000000 DCD FMC_IRQHandler ; 20:FMC + 94 00000054 00000000 DCD RCU_IRQHandler ; 21:RCU + 95 00000058 00000000 DCD EXTI0_IRQHandler + ; 22:EXTI Line 0 + 96 0000005C 00000000 DCD EXTI1_IRQHandler + ; 23:EXTI Line 1 + 97 00000060 00000000 DCD EXTI2_IRQHandler + ; 24:EXTI Line 2 + 98 00000064 00000000 DCD EXTI3_IRQHandler + ; 25:EXTI Line 3 + 99 00000068 00000000 DCD EXTI4_IRQHandler + ; 26:EXTI Line 4 + 100 0000006C 00000000 DCD DMA0_Channel0_IRQHandler + ; 27:DMA0 Channel 0 + + 101 00000070 00000000 DCD DMA0_Channel1_IRQHandler + ; 28:DMA0 Channel 1 + + 102 00000074 00000000 DCD DMA0_Channel2_IRQHandler + ; 29:DMA0 Channel 2 + + 103 00000078 00000000 DCD DMA0_Channel3_IRQHandler + ; 30:DMA0 Channel 3 + + 104 0000007C 00000000 DCD DMA0_Channel4_IRQHandler + ; 31:DMA0 Channel 4 + + 105 00000080 00000000 DCD DMA0_Channel5_IRQHandler ; 32:D + MA0 Channel 5 + 106 00000084 00000000 DCD DMA0_Channel6_IRQHandler + ; 33:DMA0 Channel 6 + + 107 00000088 00000000 DCD ADC0_1_IRQHandler + ; 34:ADC0 and ADC1 + 108 0000008C 00000000 DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + + 109 00000090 00000000 DCD CAN0_RX0_IRQHandler + ; 36:CAN0 RX0 + 110 00000094 00000000 DCD CAN0_RX1_IRQHandler + ; 37:CAN0 RX1 + 111 00000098 00000000 DCD CAN0_EWMC_IRQHandler + ; 38:CAN0 EWMC + 112 0000009C 00000000 DCD EXTI5_9_IRQHandler ; 39:EXTI Li + + + +ARM Macro Assembler Page 4 + + + ne 5 to EXTI Line 9 + + 113 000000A0 00000000 DCD TIMER0_BRK_IRQHandler + ; 40:TIMER0 Break + 114 000000A4 00000000 DCD TIMER0_UP_IRQHandler + ; 41:TIMER0 Update + 115 000000A8 00000000 DCD TIMER0_TRG_CMT_IRQHandler ; 42: + TIMER0 Trigger and + Commutation + 116 000000AC 00000000 DCD TIMER0_Channel_IRQHandler ; 43: + TIMER0 Channel Capt + ure Compare + 117 000000B0 00000000 DCD TIMER1_IRQHandler ; 44:TIMER1 + 118 000000B4 00000000 DCD TIMER2_IRQHandler ; 45:TIMER2 + 119 000000B8 00000000 DCD TIMER3_IRQHandler ; 46:TIMER3 + 120 000000BC 00000000 DCD I2C0_EV_IRQHandler + ; 47:I2C0 Event + 121 000000C0 00000000 DCD I2C0_ER_IRQHandler + ; 48:I2C0 Error + 122 000000C4 00000000 DCD I2C1_EV_IRQHandler + ; 49:I2C1 Event + 123 000000C8 00000000 DCD I2C1_ER_IRQHandler + ; 50:I2C1 Error + 124 000000CC 00000000 DCD SPI0_IRQHandler ; 51:SPI0 + 125 000000D0 00000000 DCD SPI1_IRQHandler ; 52:SPI1 + 126 000000D4 00000000 DCD USART0_IRQHandler ; 53:USART0 + 127 000000D8 00000000 DCD USART1_IRQHandler ; 54:USART1 + 128 000000DC 00000000 DCD USART2_IRQHandler ; 55:USART2 + 129 000000E0 00000000 DCD EXTI10_15_IRQHandler ; 56:EXTI + Line 10 to EXTI Lin + e 15 + 130 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; 57:RTC A + larm through EXTI L + ine + 131 000000E8 00000000 DCD USBFS_WKUP_IRQHandler ; 58:USBF + S WakeUp from suspe + nd through EXTI Lin + e + 132 000000EC 00000000 DCD TIMER7_BRK_IRQHandler ; 59:TIME + R7 Break Interrupt + 133 000000F0 00000000 DCD TIMER7_UP_IRQHandler ; 60:TIMER + 7 Update Interrupt + 134 000000F4 00000000 DCD TIMER7_TRG_CMT_IRQHandler + ; 61:TIMER7 Trigger + + 135 000000F8 00000000 DCD TIMER7_Channel_IRQHandler ; 62: + TIMER7 Channel Capt + ure Compare + 136 000000FC 00000000 DCD 0 ; Reserved + 137 00000100 00000000 DCD EXMC_IRQHandler ; 64:EXMC + 138 00000104 00000000 DCD 0 ; Reserved + 139 00000108 00000000 DCD TIMER4_IRQHandler ; 66:TIMER4 + 140 0000010C 00000000 DCD SPI2_IRQHandler ; 67:SPI2 + 141 00000110 00000000 DCD UART3_IRQHandler ; 68:UART3 + 142 00000114 00000000 DCD UART4_IRQHandler ; 69:UART4 + 143 00000118 00000000 DCD TIMER5_IRQHandler ; 70:TIMER5 + 144 0000011C 00000000 DCD TIMER6_IRQHandler ; 71:TIMER6 + 145 00000120 00000000 DCD DMA1_Channel0_IRQHandler + ; 72:DMA1 Channel0 + + + +ARM Macro Assembler Page 5 + + + 146 00000124 00000000 DCD DMA1_Channel1_IRQHandler + ; 73:DMA1 Channel1 + 147 00000128 00000000 DCD DMA1_Channel2_IRQHandler + ; 74:DMA1 Channel2 + 148 0000012C 00000000 DCD DMA1_Channel3_IRQHandler + ; 75:DMA1 Channel3 + 149 00000130 00000000 DCD DMA1_Channel4_IRQHandler + ; 76:DMA1 Channel4 + 150 00000134 00000000 DCD ENET_IRQHandler ; 77:Ethernet + 151 00000138 00000000 DCD ENET_WKUP_IRQHandler ; 78:Ether + net Wakeup through + EXTI line + 152 0000013C 00000000 DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + + 153 00000140 00000000 DCD CAN1_RX0_IRQHandler + ; 80:CAN1 RX0 + 154 00000144 00000000 DCD CAN1_RX1_IRQHandler + ; 81:CAN1 RX1 + 155 00000148 00000000 DCD CAN1_EWMC_IRQHandler + ; 82:CAN1 EWMC + 156 0000014C 00000000 DCD USBFS_IRQHandler ; 83:USBFS + 157 00000150 + 158 00000150 __Vectors_End + 159 00000150 + 160 00000150 00000150 + __Vectors_Size + EQU __Vectors_End - __Vectors + 161 00000150 + 162 00000150 AREA |.text|, CODE, READONLY + 163 00000000 + 164 00000000 ;/* reset Handler */ + 165 00000000 Reset_Handler + PROC + 166 00000000 EXPORT Reset_Handler + [WEAK] + 167 00000000 IMPORT __main + 168 00000000 IMPORT SystemInit + 169 00000000 4806 LDR R0, =SystemInit + 170 00000002 4780 BLX R0 + 171 00000004 4806 LDR R0, =__main + 172 00000006 4700 BX R0 + 173 00000008 ENDP + 174 00000008 + 175 00000008 ;/* dummy Exception Handlers */ + 176 00000008 NMI_Handler + PROC + 177 00000008 EXPORT NMI_Handler + [WEAK] + 178 00000008 E7FE B . + 179 0000000A ENDP + 180 0000000A + 181 0000000A HardFault_Handler + PROC + 182 0000000A EXPORT HardFault_Handler + [WEAK] + 183 0000000A E7FE B . + 184 0000000C ENDP + 185 0000000C + 186 0000000C MemManage_Handler + + + +ARM Macro Assembler Page 6 + + + PROC + 187 0000000C EXPORT MemManage_Handler + [WEAK] + 188 0000000C E7FE B . + 189 0000000E ENDP + 190 0000000E + 191 0000000E BusFault_Handler + PROC + 192 0000000E EXPORT BusFault_Handler + [WEAK] + 193 0000000E E7FE B . + 194 00000010 ENDP + 195 00000010 + 196 00000010 UsageFault_Handler + PROC + 197 00000010 EXPORT UsageFault_Handler + [WEAK] + 198 00000010 E7FE B . + 199 00000012 ENDP + 200 00000012 + 201 00000012 SVC_Handler + PROC + 202 00000012 EXPORT SVC_Handler + [WEAK] + 203 00000012 E7FE B . + 204 00000014 ENDP + 205 00000014 + 206 00000014 DebugMon_Handler + PROC + 207 00000014 EXPORT DebugMon_Handler + [WEAK] + 208 00000014 E7FE B . + 209 00000016 ENDP + 210 00000016 + 211 00000016 PendSV_Handler + PROC + 212 00000016 EXPORT PendSV_Handler + [WEAK] + 213 00000016 E7FE B . + 214 00000018 ENDP + 215 00000018 + 216 00000018 SysTick_Handler + PROC + 217 00000018 EXPORT SysTick_Handler + [WEAK] + 218 00000018 E7FE B . + 219 0000001A ENDP + 220 0000001A + 221 0000001A Default_Handler + PROC + 222 0000001A ; /* external interrupts handler */ + + 223 0000001A EXPORT WWDGT_IRQHandler + [WEAK] + 224 0000001A EXPORT LVD_IRQHandler + [WEAK] + 225 0000001A EXPORT TAMPER_IRQHandler + [WEAK] + 226 0000001A EXPORT RTC_IRQHandler + + + +ARM Macro Assembler Page 7 + + + [WEAK] + 227 0000001A EXPORT FMC_IRQHandler + [WEAK] + 228 0000001A EXPORT RCU_IRQHandler + [WEAK] + 229 0000001A EXPORT EXTI0_IRQHandler + [WEAK] + 230 0000001A EXPORT EXTI1_IRQHandler + [WEAK] + 231 0000001A EXPORT EXTI2_IRQHandler + [WEAK] + 232 0000001A EXPORT EXTI3_IRQHandler + [WEAK] + 233 0000001A EXPORT EXTI4_IRQHandler + [WEAK] + 234 0000001A EXPORT DMA0_Channel0_IRQHandler + [WEAK] + 235 0000001A EXPORT DMA0_Channel1_IRQHandler + [WEAK] + 236 0000001A EXPORT DMA0_Channel2_IRQHandler + [WEAK] + 237 0000001A EXPORT DMA0_Channel3_IRQHandler + [WEAK] + 238 0000001A EXPORT DMA0_Channel4_IRQHandler + [WEAK] + 239 0000001A EXPORT DMA0_Channel5_IRQHandler + [WEAK] + 240 0000001A EXPORT DMA0_Channel6_IRQHandler + [WEAK] + 241 0000001A EXPORT ADC0_1_IRQHandler + [WEAK] + 242 0000001A EXPORT CAN0_TX_IRQHandler + [WEAK] + 243 0000001A EXPORT CAN0_RX0_IRQHandler + [WEAK] + 244 0000001A EXPORT CAN0_RX1_IRQHandler + [WEAK] + 245 0000001A EXPORT CAN0_EWMC_IRQHandler + [WEAK] + 246 0000001A EXPORT EXTI5_9_IRQHandler + [WEAK] + 247 0000001A EXPORT TIMER0_BRK_IRQHandler + [WEAK] + 248 0000001A EXPORT TIMER0_UP_IRQHandler + [WEAK] + 249 0000001A EXPORT TIMER0_TRG_CMT_IRQHandler + [WEAK] + 250 0000001A EXPORT TIMER0_Channel_IRQHandler + [WEAK] + 251 0000001A EXPORT TIMER1_IRQHandler + [WEAK] + 252 0000001A EXPORT TIMER2_IRQHandler + [WEAK] + 253 0000001A EXPORT TIMER3_IRQHandler + [WEAK] + 254 0000001A EXPORT I2C0_EV_IRQHandler + [WEAK] + 255 0000001A EXPORT I2C0_ER_IRQHandler + [WEAK] + + + +ARM Macro Assembler Page 8 + + + 256 0000001A EXPORT I2C1_EV_IRQHandler + [WEAK] + 257 0000001A EXPORT I2C1_ER_IRQHandler + [WEAK] + 258 0000001A EXPORT SPI0_IRQHandler + [WEAK] + 259 0000001A EXPORT SPI1_IRQHandler + [WEAK] + 260 0000001A EXPORT USART0_IRQHandler + [WEAK] + 261 0000001A EXPORT USART1_IRQHandler + [WEAK] + 262 0000001A EXPORT USART2_IRQHandler + [WEAK] + 263 0000001A EXPORT EXTI10_15_IRQHandler + [WEAK] + 264 0000001A EXPORT RTC_Alarm_IRQHandler + [WEAK] + 265 0000001A EXPORT USBFS_WKUP_IRQHandler + [WEAK] + 266 0000001A EXPORT TIMER7_BRK_IRQHandler + [WEAK] + 267 0000001A EXPORT TIMER7_UP_IRQHandler + [WEAK] + 268 0000001A EXPORT TIMER7_TRG_CMT_IRQHandler + [WEAK] + 269 0000001A EXPORT TIMER7_Channel_IRQHandler + [WEAK] + 270 0000001A EXPORT EXMC_IRQHandler + [WEAK] + 271 0000001A EXPORT TIMER4_IRQHandler + [WEAK] + 272 0000001A EXPORT SPI2_IRQHandler + [WEAK] + 273 0000001A EXPORT UART3_IRQHandler + [WEAK] + 274 0000001A EXPORT UART4_IRQHandler + [WEAK] + 275 0000001A EXPORT TIMER5_IRQHandler + [WEAK] + 276 0000001A EXPORT TIMER6_IRQHandler + [WEAK] + 277 0000001A EXPORT DMA1_Channel0_IRQHandler + [WEAK] + 278 0000001A EXPORT DMA1_Channel1_IRQHandler + [WEAK] + 279 0000001A EXPORT DMA1_Channel2_IRQHandler + [WEAK] + 280 0000001A EXPORT DMA1_Channel3_IRQHandler + [WEAK] + 281 0000001A EXPORT DMA1_Channel4_IRQHandler + [WEAK] + 282 0000001A EXPORT ENET_IRQHandler + [WEAK] + 283 0000001A EXPORT ENET_WKUP_IRQHandler + [WEAK] + 284 0000001A EXPORT CAN1_TX_IRQHandler + [WEAK] + 285 0000001A EXPORT CAN1_RX0_IRQHandler + + + +ARM Macro Assembler Page 9 + + + [WEAK] + 286 0000001A EXPORT CAN1_RX1_IRQHandler + [WEAK] + 287 0000001A EXPORT CAN1_EWMC_IRQHandler + [WEAK] + 288 0000001A EXPORT USBFS_IRQHandler + [WEAK] + 289 0000001A + 290 0000001A + 291 0000001A ;/* external interrupts handler */ + 292 0000001A WWDGT_IRQHandler + 293 0000001A LVD_IRQHandler + 294 0000001A TAMPER_IRQHandler + 295 0000001A RTC_IRQHandler + 296 0000001A FMC_IRQHandler + 297 0000001A RCU_IRQHandler + 298 0000001A EXTI0_IRQHandler + 299 0000001A EXTI1_IRQHandler + 300 0000001A EXTI2_IRQHandler + 301 0000001A EXTI3_IRQHandler + 302 0000001A EXTI4_IRQHandler + 303 0000001A DMA0_Channel0_IRQHandler + 304 0000001A DMA0_Channel1_IRQHandler + 305 0000001A DMA0_Channel2_IRQHandler + 306 0000001A DMA0_Channel3_IRQHandler + 307 0000001A DMA0_Channel4_IRQHandler + 308 0000001A DMA0_Channel5_IRQHandler + 309 0000001A DMA0_Channel6_IRQHandler + 310 0000001A ADC0_1_IRQHandler + 311 0000001A CAN0_TX_IRQHandler + 312 0000001A CAN0_RX0_IRQHandler + 313 0000001A CAN0_RX1_IRQHandler + 314 0000001A CAN0_EWMC_IRQHandler + 315 0000001A EXTI5_9_IRQHandler + 316 0000001A TIMER0_BRK_IRQHandler + 317 0000001A TIMER0_UP_IRQHandler + 318 0000001A TIMER0_TRG_CMT_IRQHandler + 319 0000001A TIMER0_Channel_IRQHandler + 320 0000001A TIMER1_IRQHandler + 321 0000001A TIMER2_IRQHandler + 322 0000001A TIMER3_IRQHandler + 323 0000001A I2C0_EV_IRQHandler + 324 0000001A I2C0_ER_IRQHandler + 325 0000001A I2C1_EV_IRQHandler + 326 0000001A I2C1_ER_IRQHandler + 327 0000001A SPI0_IRQHandler + 328 0000001A SPI1_IRQHandler + 329 0000001A USART0_IRQHandler + 330 0000001A USART1_IRQHandler + 331 0000001A USART2_IRQHandler + 332 0000001A EXTI10_15_IRQHandler + 333 0000001A RTC_Alarm_IRQHandler + 334 0000001A USBFS_WKUP_IRQHandler + 335 0000001A TIMER7_BRK_IRQHandler + 336 0000001A TIMER7_UP_IRQHandler + 337 0000001A TIMER7_TRG_CMT_IRQHandler + 338 0000001A TIMER7_Channel_IRQHandler + 339 0000001A EXMC_IRQHandler + 340 0000001A TIMER4_IRQHandler + + + +ARM Macro Assembler Page 10 + + + 341 0000001A SPI2_IRQHandler + 342 0000001A UART3_IRQHandler + 343 0000001A UART4_IRQHandler + 344 0000001A TIMER5_IRQHandler + 345 0000001A TIMER6_IRQHandler + 346 0000001A DMA1_Channel0_IRQHandler + 347 0000001A DMA1_Channel1_IRQHandler + 348 0000001A DMA1_Channel2_IRQHandler + 349 0000001A DMA1_Channel3_IRQHandler + 350 0000001A DMA1_Channel4_IRQHandler + 351 0000001A ENET_IRQHandler + 352 0000001A ENET_WKUP_IRQHandler + 353 0000001A CAN1_TX_IRQHandler + 354 0000001A CAN1_RX0_IRQHandler + 355 0000001A CAN1_RX1_IRQHandler + 356 0000001A CAN1_EWMC_IRQHandler + 357 0000001A USBFS_IRQHandler + 358 0000001A + 359 0000001A + 360 0000001A E7FE B . + 361 0000001C ENDP + 362 0000001C + 363 0000001C ALIGN + 364 0000001C + 365 0000001C ; user Initial Stack & Heap + 366 0000001C + 367 0000001C IF :DEF:__MICROLIB + 368 0000001C + 369 0000001C EXPORT __initial_sp + 370 0000001C EXPORT __heap_base + 371 0000001C EXPORT __heap_limit + 372 0000001C + 373 0000001C ELSE + 388 ENDIF + 389 0000001C + 390 0000001C END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=.\output\startup_gd32f10x_cl.d -o.\output\startup_gd32f10x_cl.o -I +E:\code\rtt\rt-thread\bsp\gd32105c-eval\RTE -ID:\Keil_v5\ARM\PACK\GigaDevice\GD +32F10x_DFP\2.0.1\Device\Include -ID:\Keil_v5\ARM\CMSIS\Include --predefine="__M +ICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 514" --predefine="GD32F10X_ +CL SETA 1" --predefine="USE_STDPERIPH_DRIVER SETA 1" --list=.\list\startup_gd32 +f10x_cl.lst Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 45 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 46 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00002000 + +Symbol: __initial_sp + Definitions + At line 47 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 71 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 369 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 56 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 58 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 57 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 370 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s +Comment: __heap_base used once +__heap_limit 00002000 + +Symbol: __heap_limit + Definitions + At line 59 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 371 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 66 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 71 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 67 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +__Vectors_End 00000150 + +Symbol: __Vectors_End + Definitions + At line 158 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 68 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 162 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + None +Comment: .text unused +ADC0_1_IRQHandler 0000001A + +Symbol: ADC0_1_IRQHandler + Definitions + At line 310 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 107 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 241 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 191 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 76 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 192 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN0_EWMC_IRQHandler 0000001A + +Symbol: CAN0_EWMC_IRQHandler + Definitions + At line 314 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 111 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 245 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN0_RX0_IRQHandler 0000001A + +Symbol: CAN0_RX0_IRQHandler + Definitions + At line 312 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 109 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 243 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN0_RX1_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + +Symbol: CAN0_RX1_IRQHandler + Definitions + At line 313 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 110 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 244 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN0_TX_IRQHandler 0000001A + +Symbol: CAN0_TX_IRQHandler + Definitions + At line 311 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 108 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 242 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN1_EWMC_IRQHandler 0000001A + +Symbol: CAN1_EWMC_IRQHandler + Definitions + At line 356 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 155 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 287 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN1_RX0_IRQHandler 0000001A + +Symbol: CAN1_RX0_IRQHandler + Definitions + At line 354 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 153 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 285 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 355 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 154 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 286 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN1_TX_IRQHandler 0000001A + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: CAN1_TX_IRQHandler + Definitions + At line 353 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 152 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 284 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel0_IRQHandler 0000001A + +Symbol: DMA0_Channel0_IRQHandler + Definitions + At line 303 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 100 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 234 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel1_IRQHandler 0000001A + +Symbol: DMA0_Channel1_IRQHandler + Definitions + At line 304 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 101 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 235 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel2_IRQHandler 0000001A + +Symbol: DMA0_Channel2_IRQHandler + Definitions + At line 305 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 102 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 236 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel3_IRQHandler 0000001A + +Symbol: DMA0_Channel3_IRQHandler + Definitions + At line 306 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 103 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 237 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + +DMA0_Channel4_IRQHandler 0000001A + +Symbol: DMA0_Channel4_IRQHandler + Definitions + At line 307 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 104 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 238 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel5_IRQHandler 0000001A + +Symbol: DMA0_Channel5_IRQHandler + Definitions + At line 308 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 105 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 239 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel6_IRQHandler 0000001A + +Symbol: DMA0_Channel6_IRQHandler + Definitions + At line 309 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 106 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 240 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA1_Channel0_IRQHandler 0000001A + +Symbol: DMA1_Channel0_IRQHandler + Definitions + At line 346 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 145 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 277 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA1_Channel1_IRQHandler 0000001A + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 347 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 146 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 278 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + +DMA1_Channel2_IRQHandler 0000001A + +Symbol: DMA1_Channel2_IRQHandler + Definitions + At line 348 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 147 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 279 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA1_Channel3_IRQHandler 0000001A + +Symbol: DMA1_Channel3_IRQHandler + Definitions + At line 349 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 148 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 280 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA1_Channel4_IRQHandler 0000001A + +Symbol: DMA1_Channel4_IRQHandler + Definitions + At line 350 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 149 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 281 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 206 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 83 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 207 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 221 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + None +Comment: Default_Handler unused +ENET_IRQHandler 0000001A + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: ENET_IRQHandler + Definitions + At line 351 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 150 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 282 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +ENET_WKUP_IRQHandler 0000001A + +Symbol: ENET_WKUP_IRQHandler + Definitions + At line 352 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 151 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 283 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXMC_IRQHandler 0000001A + +Symbol: EXMC_IRQHandler + Definitions + At line 339 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 137 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 270 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 298 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 95 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 229 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI10_15_IRQHandler 0000001A + +Symbol: EXTI10_15_IRQHandler + Definitions + At line 332 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 129 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 263 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 299 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 96 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 230 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 300 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 97 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 231 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 301 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 98 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 232 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 302 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 99 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 233 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI5_9_IRQHandler 0000001A + +Symbol: EXTI5_9_IRQHandler + Definitions + At line 315 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 112 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 246 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +FMC_IRQHandler 0000001A + +Symbol: FMC_IRQHandler + Definitions + At line 296 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 93 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 227 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 181 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 74 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 182 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +I2C0_ER_IRQHandler 0000001A + +Symbol: I2C0_ER_IRQHandler + Definitions + At line 324 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 121 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 255 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +I2C0_EV_IRQHandler 0000001A + +Symbol: I2C0_EV_IRQHandler + Definitions + At line 323 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 120 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 254 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 326 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 123 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 257 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + +0x_cl.s + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 325 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 122 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 256 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +LVD_IRQHandler 0000001A + +Symbol: LVD_IRQHandler + Definitions + At line 293 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 90 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 224 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 186 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 75 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 187 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 176 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 73 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 177 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 211 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 85 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + + At line 212 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +RCU_IRQHandler 0000001A + +Symbol: RCU_IRQHandler + Definitions + At line 297 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 94 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 228 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +RTC_Alarm_IRQHandler 0000001A + +Symbol: RTC_Alarm_IRQHandler + Definitions + At line 333 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 130 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 264 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 295 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 92 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 226 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 165 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 72 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 166 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SPI0_IRQHandler 0000001A + +Symbol: SPI0_IRQHandler + Definitions + At line 327 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 124 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + +0x_cl.s + At line 258 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 328 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 125 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 259 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 341 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 140 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 272 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 201 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 82 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 202 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 216 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 86 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 217 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TAMPER_IRQHandler 0000001A + +Symbol: TAMPER_IRQHandler + Definitions + At line 294 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + At line 91 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 225 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER0_BRK_IRQHandler 0000001A + +Symbol: TIMER0_BRK_IRQHandler + Definitions + At line 316 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 113 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 247 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER0_Channel_IRQHandler 0000001A + +Symbol: TIMER0_Channel_IRQHandler + Definitions + At line 319 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 116 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 250 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER0_TRG_CMT_IRQHandler 0000001A + +Symbol: TIMER0_TRG_CMT_IRQHandler + Definitions + At line 318 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 115 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 249 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER0_UP_IRQHandler 0000001A + +Symbol: TIMER0_UP_IRQHandler + Definitions + At line 317 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 114 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 248 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER1_IRQHandler 0000001A + +Symbol: TIMER1_IRQHandler + Definitions + At line 320 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + +ARM Macro Assembler Page 13 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 117 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 251 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER2_IRQHandler 0000001A + +Symbol: TIMER2_IRQHandler + Definitions + At line 321 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 118 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 252 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER3_IRQHandler 0000001A + +Symbol: TIMER3_IRQHandler + Definitions + At line 322 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 119 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 253 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER4_IRQHandler 0000001A + +Symbol: TIMER4_IRQHandler + Definitions + At line 340 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 139 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 271 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER5_IRQHandler 0000001A + +Symbol: TIMER5_IRQHandler + Definitions + At line 344 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 143 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 275 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER6_IRQHandler 0000001A + +Symbol: TIMER6_IRQHandler + Definitions + At line 345 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 + + + +ARM Macro Assembler Page 14 Alphabetic symbol ordering +Relocatable symbols + +0x_cl.s + Uses + At line 144 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 276 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER7_BRK_IRQHandler 0000001A + +Symbol: TIMER7_BRK_IRQHandler + Definitions + At line 335 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 132 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 266 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER7_Channel_IRQHandler 0000001A + +Symbol: TIMER7_Channel_IRQHandler + Definitions + At line 338 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 135 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 269 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER7_TRG_CMT_IRQHandler 0000001A + +Symbol: TIMER7_TRG_CMT_IRQHandler + Definitions + At line 337 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 134 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 268 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER7_UP_IRQHandler 0000001A + +Symbol: TIMER7_UP_IRQHandler + Definitions + At line 336 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 133 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 267 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +UART3_IRQHandler 0000001A + +Symbol: UART3_IRQHandler + Definitions + + + +ARM Macro Assembler Page 15 Alphabetic symbol ordering +Relocatable symbols + + At line 342 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 141 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 273 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +UART4_IRQHandler 0000001A + +Symbol: UART4_IRQHandler + Definitions + At line 343 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 142 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 274 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USART0_IRQHandler 0000001A + +Symbol: USART0_IRQHandler + Definitions + At line 329 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 126 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 260 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 330 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 127 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 261 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 331 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 128 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 262 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USBFS_IRQHandler 0000001A + +Symbol: USBFS_IRQHandler + + + +ARM Macro Assembler Page 16 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 357 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 156 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 288 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USBFS_WKUP_IRQHandler 0000001A + +Symbol: USBFS_WKUP_IRQHandler + Definitions + At line 334 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 131 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 265 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 196 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 77 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 197 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +WWDGT_IRQHandler 0000001A + +Symbol: WWDGT_IRQHandler + Definitions + At line 292 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 89 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 223 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +78 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00002000 + +Symbol: Heap_Size + Definitions + At line 54 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 58 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s +Comment: Heap_Size used once +Stack_Size 00002000 + +Symbol: Stack_Size + Definitions + At line 43 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 46 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s +Comment: Stack_Size used once +__Vectors_Size 00000150 + +Symbol: __Vectors_Size + Definitions + At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 69 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 168 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 169 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 167 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 171 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s +Comment: __main used once +2 symbols +429 symbols in table diff --git a/bsp/gd32105c-eval/project.ewd b/bsp/gd32105c-eval/project.ewd new file mode 100644 index 0000000000..5f99340356 --- /dev/null +++ b/bsp/gd32105c-eval/project.ewd @@ -0,0 +1,2834 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + 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Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_bkp.c + gd32f10x_bkp.c + 0 + 0 + + + 9 + 78 + 1 + 0 + 0 + 0 + 0 + Libraries\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c + system_gd32f10x.c + 0 + 0 + + + + diff --git a/bsp/gd32105c-eval/project.uvprojx b/bsp/gd32105c-eval/project.uvprojx new file mode 100644 index 0000000000..ddaca36aca --- /dev/null +++ b/bsp/gd32105c-eval/project.uvprojx @@ -0,0 +1,907 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread_gd32f105 + 0x4 + ARM-ADS + + + GD32F105VC + GigaDevice + GigaDevice.GD32F10x_DFP.2.0.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM)) + 0 + $$Device:GD32F105VC$Device\Include\gd32f10x.h + + + + + + + + + + $$Device:GD32F105VC$SVD\GD32F10x\GD32F10x_CL.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\ + Project + 1 + 0 + 1 + 1 + 1 + .\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + GD32F10X_CL, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;Libraries\CMSIS\GD\GD32F10x\Include;Libraries\CMSIS;Libraries\GD32F10x_standard_peripheral\Include;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m3\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m3\cpuport.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + i2c_core.c + 1 + ..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\components\drivers\i2c\i2c_dev.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + sfud.c + 1 + ..\..\components\drivers\spi\sfud\src\sfud.c + + + spi_flash_sfud.c + 1 + ..\..\components\drivers\spi\spi_flash_sfud.c + + + sfud_sfdp.c + 1 + ..\..\components\drivers\spi\sfud\src\sfud_sfdp.c + + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + 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..\..\components\libc\compilers\common\time.c + + + + + Libraries + + + gd32f10x_crc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_crc.c + + + gd32f10x_rtc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rtc.c + + + gd32f10x_dbg.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dbg.c + + + gd32f10x_pmu.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_pmu.c + + + gd32f10x_fmc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_fmc.c + + + gd32f10x_gpio.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c + + + gd32f10x_i2c.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_i2c.c + + + gd32f10x_exmc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_exmc.c + + + gd32f10x_fwdgt.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_fwdgt.c + + + gd32f10x_misc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c + + + gd32f10x_dma.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dma.c + + + gd32f10x_sdio.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_sdio.c + + + gd32f10x_dac.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dac.c + + + gd32f10x_usart.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c + + + gd32f10x_can.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_can.c + + + gd32f10x_timer.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_timer.c + + + gd32f10x_rcu.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c + + + gd32f10x_adc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_adc.c + + + gd32f10x_spi.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c + + + startup_gd32f10x_cl.s + 2 + Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s + + + gd32f10x_enet.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_enet.c + + + gd32f10x_exti.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c + + + gd32f10x_wwdgt.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_wwdgt.c + + + gd32f10x_bkp.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_bkp.c + + + system_gd32f10x.c + 1 + Libraries\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c + + + + + + + + diff --git a/bsp/gd32105c-eval/rtconfig.h b/bsp/gd32105c-eval/rtconfig.h new file mode 100644 index 0000000000..0d8737cd9e --- /dev/null +++ b/bsp/gd32105c-eval/rtconfig.h @@ -0,0 +1,207 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_PIN +#define RT_USING_SPI +#define RT_USING_SFUD +#define RT_SFUD_USING_SFDP +#define RT_SFUD_USING_FLASH_INFO_TABLE +#define RT_SFUD_SPI_MAX_HZ 50000000 + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define SOC_SERIES_GD32F1 +#define SOC_GD32105C +#define RT_USING_USART0 +#define RT_USING_SPI0 +#define RT_USING_I2C0 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/gd32105c-eval/rtconfig.py b/bsp/gd32105c-eval/rtconfig.py new file mode 100644 index 0000000000..7a845afd38 --- /dev/null +++ b/bsp/gd32105c-eval/rtconfig.py @@ -0,0 +1,126 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # tool-chains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + EXEC_PATH += '/ARM/ARMCC/bin' + print(EXEC_PATH) + + CFLAGS += ' --c99' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config gd32_rom.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH += '/arm/bin/' + POST_ACTION = '' + diff --git a/bsp/gd32105c-eval/template.ewp b/bsp/gd32105c-eval/template.ewp new file mode 100644 index 0000000000..716042958e --- /dev/null +++ b/bsp/gd32105c-eval/template.ewp @@ -0,0 +1,1889 @@ + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/gd32105c-eval/template.uvoptx b/bsp/gd32105c-eval/template.uvoptx new file mode 100644 index 0000000000..f9ac66a05a --- /dev/null +++ b/bsp/gd32105c-eval/template.uvoptx @@ -0,0 +1,163 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread_gd32f105 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U58001139 -O14 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(790007A3) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL0300000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/gd32105c-eval/template.uvprojx b/bsp/gd32105c-eval/template.uvprojx new file mode 100644 index 0000000000..88f1e75220 --- /dev/null +++ b/bsp/gd32105c-eval/template.uvprojx @@ -0,0 +1,410 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread_gd32f105 + 0x4 + ARM-ADS + + + GD32F105VC + GigaDevice + GigaDevice.GD32F10x_DFP.2.0.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM)) + 0 + $$Device:GD32F105VC$Device\Include\gd32f10x.h + + + + + + + + + + $$Device:GD32F105VC$SVD\GD32F10x\GD32F10x_CL.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\ + Project + 1 + 0 + 1 + 1 + 1 + .\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\GD32F10x_Firmware_Library\CMSIS;..\..\..\..\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\..\..\..\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\Utilities;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + + diff --git a/bsp/gd32107c-eval/.config b/bsp/gd32107c-eval/.config new file mode 100644 index 0000000000..3642cdfa71 --- /dev/null +++ b/bsp/gd32107c-eval/.config @@ -0,0 +1,631 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +# CONFIG_RT_USING_I2C_BITOPS is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Hardware Drivers Config +# + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_SOC_SERIES_GD32F1=y +CONFIG_SOC_GD32105C=y +CONFIG_RT_USING_USART0=y +# CONFIG_RT_USING_USART1 is not set +# CONFIG_RT_USING_USART2 is not set +# CONFIG_RT_USING_UART3 is not set +CONFIG_RT_USING_SPI0=y +# CONFIG_RT_USING_SPI1 is not set +# CONFIG_RT_USING_SPI2 is not set +CONFIG_RT_USING_I2C0=y +# CONFIG_RT_USING_I2C1 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/gd32107c-eval/.ignore_format.yml b/bsp/gd32107c-eval/.ignore_format.yml new file mode 100644 index 0000000000..d570c52faf --- /dev/null +++ b/bsp/gd32107c-eval/.ignore_format.yml @@ -0,0 +1,8 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: + +dir_path: +- Libraries diff --git a/bsp/gd32107c-eval/Kconfig b/bsp/gd32107c-eval/Kconfig new file mode 100644 index 0000000000..3050d65e26 --- /dev/null +++ b/bsp/gd32107c-eval/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "drivers/Kconfig" + + + + + diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h new file mode 100644 index 0000000000..e525f3c0c6 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h @@ -0,0 +1,381 @@ +/*! + \file gd32f10x.h + \brief general definitions for GD32F10x + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_H +#define GD32F10X_H + +#ifdef cplusplus + extern "C" { +#endif + +/* define GD32F10x */ +#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) + /* #define GD32F10X_MD */ /*!< GD32F10X_MD: GD32 Medium density devices */ + /* #define GD32F10X_HD */ /*!< GD32F10X_HD: GD32 High density Value Line devices */ + /* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */ + /* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */ +#endif /* define GD32F10x */ + +#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) + #error "Please select the target GD32F10x device in gd32f10x.h file" +#endif /* undefine GD32F10x tip */ + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined HXTAL_VALUE +#ifdef GD32F10X_CL +#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ +#else +#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ +#endif /* HXTAL_VALUE */ +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* GD32F10x firmware library version number V2.0 */ +#define __GD32F10x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __GD32F10x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32F10x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F10x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F10x_STDPERIPH_VERSION ((__GD32F10x_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32F10x_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32F10x_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32F10x_STDPERIPH_VERSION_RC)) + +/* configuration of the Cortex-M3 processor and core peripherals */ +#define __MPU_PRESENT 0 /*!< GD32F10x do not provide MPU */ +#define __NVIC_PRIO_BITS 4 /*!< GD32F10x uses 4 bits for the priority levels */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ +/* define interrupt number */ +typedef enum IRQn +{ + /* Cortex-M3 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 system tick interrupt */ + + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ + RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ + FMC_IRQn = 4, /*!< FMC interrupt */ + RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ + ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ + +#ifdef GD32F10X_MD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ +#endif /* GD32F10X_MD */ + +#ifdef GD32F10X_HD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ + TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ + TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ + TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ + ADC2_IRQn = 47, /*!< ADC2 global interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + SDIO_IRQn = 49, /*!< SDIO global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ +#endif /* GD32F10X_HD */ + +#ifdef GD32F10X_XD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ + ADC2_IRQn = 47, /*!< ADC2 global interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + SDIO_IRQn = 49, /*!< SDIO global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */ +#endif /* GD32F10X_XD */ + +#ifdef GD32F10X_CL + CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */ + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ + TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ + TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ + ENET_IRQn = 61, /*!< ENET global interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS global interrupt */ +#endif /* GD32F10X_CL */ + +} IRQn_Type; + +/* includes */ +#include "core_cm3.h" +#include "system_gd32f10x.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ +#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ +#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ + +/* advanced peripheral bus 2 memory map */ +#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ + +/* advanced high performance bus 1 memory map */ +#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ +#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32f10x_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef cplusplus +} +#endif +#endif diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h new file mode 100644 index 0000000000..6bd00fb99d --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h @@ -0,0 +1,60 @@ +/*! + \file system_gd32f10x.h + \brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for + GD32F10x Device Series +*/ + +/* + Copyright (c) 2012 ARM LIMITED + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32F10X_H +#define SYSTEM_GD32F10X_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit(void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32F10X_H */ diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s new file mode 100644 index 0000000000..a3ffa4c752 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s @@ -0,0 +1,390 @@ +;/*! +; \file startup_gd32f10x_cl.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper Interrupt + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_IRQHandler ; 21:RCU + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break + DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line + DCD USBFS_WKUP_IRQHandler ; 58:USBFS WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt + DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt + DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; 64:EXMC + DCD 0 ; Reserved + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_IRQHandler [WEAK] + EXPORT TIMER0_UP_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_IRQHandler [WEAK] + EXPORT TIMER7_UP_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT ENET_WKUP_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_IRQHandler +TIMER0_UP_IRQHandler +TIMER0_TRG_CMT_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_IRQHandler +TIMER7_UP_IRQHandler +TIMER7_TRG_CMT_IRQHandler +TIMER7_Channel_IRQHandler +EXMC_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +ENET_IRQHandler +ENET_WKUP_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler + + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s new file mode 100644 index 0000000000..fe768cc3a9 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s @@ -0,0 +1,371 @@ +;/*! +; \file startup_gd32f10x_hd.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper Interrupt + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_IRQHandler ; 21:RCU + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break + DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt + DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt + DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD ADC2_IRQHandler ; 63:ADC2 + DCD EXMC_IRQHandler ; 64:EXMC + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] + EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_IRQHandler [WEAK] + EXPORT TIMER0_UP_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBD_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_IRQHandler [WEAK] + EXPORT TIMER7_UP_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_4_IRQHandler [WEAK] + + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +USBD_HP_CAN0_TX_IRQHandler +USBD_LP_CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_IRQHandler +TIMER0_UP_IRQHandler +TIMER0_TRG_CMT_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBD_WKUP_IRQHandler +TIMER7_BRK_IRQHandler +TIMER7_UP_IRQHandler +TIMER7_TRG_CMT_IRQHandler +TIMER7_Channel_IRQHandler +ADC2_IRQHandler +EXMC_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_4_IRQHandler + + + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s new file mode 100644 index 0000000000..c567fee5c1 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s @@ -0,0 +1,328 @@ +;/*! +; \file startup_gd32f10x_md.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper Interrupt + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_IRQHandler ; 21:RCU + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break + DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; 64:EXMC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] + EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_IRQHandler [WEAK] + EXPORT TIMER0_UP_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBD_WKUP_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +USBD_HP_CAN0_TX_IRQHandler +USBD_LP_CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_IRQHandler +TIMER0_UP_IRQHandler +TIMER0_TRG_CMT_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBD_WKUP_IRQHandler +EXMC_IRQHandler + + + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s new file mode 100644 index 0000000000..3db249b8e5 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s @@ -0,0 +1,371 @@ +;/*! +; \file startup_gd32f10x_xd.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper Interrupt + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_IRQHandler ; 21:RCU + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 global + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 global + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 global + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break Interrupt and TIMER11 global + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update Interrupt and TIMER12 global + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt and TIMER13 global + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD ADC2_IRQHandler ; 63:ADC2 + DCD EXMC_IRQHandler ; 64:EXMC + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] + EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBD_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_4_IRQHandler [WEAK] + + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +USBD_HP_CAN0_TX_IRQHandler +USBD_LP_CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBD_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +ADC2_IRQHandler +EXMC_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_4_IRQHandler + + + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s new file mode 100644 index 0000000000..8d614ecf3e --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s @@ -0,0 +1,529 @@ +;/*! +; \file startup_gd32f10x_cl.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt + DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 20,FMC + DCD RCU_IRQHandler ; Vector Number 21,RCU + DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 + DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 + DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 + DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 + DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; Vector Number 35,CAN0 TX + DCD CAN0_RX0_IRQHandler ; Vector Number 36,CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC + DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break + DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 + DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 + DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD SPI0_IRQHandler ; Vector Number 51,SPI0 + DCD SPI1_IRQHandler ; Vector Number 52,SPI1 + DCD USART0_IRQHandler ; Vector Number 53,USART0 + DCD USART1_IRQHandler ; Vector Number 54,USART1 + DCD USART2_IRQHandler ; Vector Number 55,USART2 + DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line + DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt + DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt + DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt + DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; Vector Number 64,EXMC + DCD 0 ; Reserved + DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 + DCD SPI2_IRQHandler ; Vector Number 67,SPI2 + DCD UART3_IRQHandler ; Vector Number 68,UART3 + DCD UART4_IRQHandler ; Vector Number 69,UART4 + DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 + DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 + DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; Vector Number 75,DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; Vector Number 76,DMA1 Channel4 + DCD ENET_IRQHandler ; Vector Number 77,Ethernet + DCD ENET_WKUP_IRQHandler ; Vector Number 78,Ethernet Wakeup through EXTI line + DCD CAN1_TX_IRQHandler ; Vector Number 79,CAN1 TX + DCD CAN1_RX0_IRQHandler ; Vector Number 80,CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; Vector Number 81,CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; Vector Number 82,CAN1 EWMC + DCD USBFS_IRQHandler ; Vector Number 83,USBFS +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, = SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_IRQHandler + B CAN0_TX_IRQHandler + + PUBWEAK CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_IRQHandler + B CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_IRQHandler + B TIMER0_BRK_IRQHandler + + PUBWEAK TIMER0_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_IRQHandler + B TIMER0_UP_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_IRQHandler + B TIMER0_TRG_CMT_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_IRQHandler + B TIMER7_BRK_IRQHandler + + PUBWEAK TIMER7_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_IRQHandler + B TIMER7_UP_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_IRQHandler + B TIMER7_TRG_CMT_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK ENET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_IRQHandler + B ENET_IRQHandler + + PUBWEAK ENET_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_WKUP_IRQHandler + B ENET_WKUP_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_EWMC_IRQHandler + B CAN1_EWMC_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + + + END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s new file mode 100644 index 0000000000..0cd9ade897 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s @@ -0,0 +1,491 @@ +;/*! +; \file startup_gd32f10x_hd.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt + DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 20,FMC + DCD RCU_IRQHandler ; Vector Number 21,RCU + DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 + DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 + DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 + DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 + DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC + DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break + DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 + DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 + DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD SPI0_IRQHandler ; Vector Number 51,SPI0 + DCD SPI1_IRQHandler ; Vector Number 52,SPI1 + DCD USART0_IRQHandler ; Vector Number 53,USART0 + DCD USART1_IRQHandler ; Vector Number 54,USART1 + DCD USART2_IRQHandler ; Vector Number 55,USART2 + DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt + DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt + DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt + DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare + DCD ADC2_IRQHandler ; Vector Number 63,ADC2 + DCD EXMC_IRQHandler ; Vector Number 64,EXMC + DCD SDIO_IRQHandler ; Vector Number 65,SDIO + DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 + DCD SPI2_IRQHandler ; Vector Number 67,SPI2 + DCD UART3_IRQHandler ; Vector Number 68,UART3 + DCD UART4_IRQHandler ; Vector Number 69,UART4 + DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 + DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 + DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 + DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, = SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK USBD_HP_CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_HP_CAN0_TX_IRQHandler + B USBD_HP_CAN0_TX_IRQHandler + + PUBWEAK USBD_LP_CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_LP_CAN0_RX0_IRQHandler + B USBD_LP_CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_IRQHandler + B TIMER0_BRK_IRQHandler + + PUBWEAK TIMER0_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_IRQHandler + B TIMER0_UP_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_IRQHandler + B TIMER0_TRG_CMT_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBD_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_WKUP_IRQHandler + B USBD_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_IRQHandler + B TIMER7_BRK_IRQHandler + + PUBWEAK TIMER7_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_IRQHandler + B TIMER7_UP_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_IRQHandler + B TIMER7_TRG_CMT_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_4_IRQHandler + B DMA1_Channel3_4_IRQHandler + + END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s new file mode 100644 index 0000000000..bc0d386613 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s @@ -0,0 +1,400 @@ +;/*! +; \file startup_gd32f10x_md.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt + DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 20,FMC + DCD RCU_IRQHandler ; Vector Number 21,RCU + DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 + DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 + DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 + DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 + DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC + DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break + DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update + DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 + DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 + DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD SPI0_IRQHandler ; Vector Number 51,SPI0 + DCD SPI1_IRQHandler ; Vector Number 52,SPI1 + DCD USART0_IRQHandler ; Vector Number 53,USART0 + DCD USART1_IRQHandler ; Vector Number 54,USART1 + DCD USART2_IRQHandler ; Vector Number 55,USART2 + DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; Vector Number 64,EXMC +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, = SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK USBD_HP_CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_HP_CAN0_TX_IRQHandler + B USBD_HP_CAN0_TX_IRQHandler + + PUBWEAK USBD_LP_CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_LP_CAN0_RX0_IRQHandler + B USBD_LP_CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_IRQHandler + B TIMER0_BRK_IRQHandler + + PUBWEAK TIMER0_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_IRQHandler + B TIMER0_UP_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_IRQHandler + B TIMER0_TRG_CMT_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBD_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_WKUP_IRQHandler + B USBD_WKUP_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s new file mode 100644 index 0000000000..4f52b7d5fa --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s @@ -0,0 +1,491 @@ +;/*! +; \file startup_gd32f10x_xd.s +; \brief start up file +; +; \version 2014-12-26, V1.0.0, firmware for GD32F10x +; \version 2017-06-20, V2.0.0, firmware for GD32F10x +; \version 2018-07-31, V2.1.0, firmware for GD32F10x +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt + DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 20,FMC + DCD RCU_IRQHandler ; Vector Number 21,RCU + DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 + DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 + DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 + DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 + DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 + DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 + DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 + DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 + DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 + DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 + DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 + DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 + DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX + DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC + DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; Vector Number 40,TIMER0 Break and TIMER8 global + DCD TIMER0_UP_TIMER9_IRQHandler ; Vector Number 41,TIMER0 Update and TIMER9 global + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global + DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 + DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 + DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD SPI0_IRQHandler ; Vector Number 51,SPI0 + DCD SPI1_IRQHandler ; Vector Number 52,SPI1 + DCD USART0_IRQHandler ; Vector Number 53,USART0 + DCD USART1_IRQHandler ; Vector Number 54,USART1 + DCD USART2_IRQHandler ; Vector Number 55,USART2 + DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 + DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line + DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line + DCD TIMER7_BRK_TIMER11_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt and TIMER11 global + DCD TIMER7_UP_TIMER12_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt and TIMER12 global + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13 global + DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare + DCD ADC2_IRQHandler ; Vector Number 63,ADC2 + DCD EXMC_IRQHandler ; Vector Number 64,EXMC + DCD SDIO_IRQHandler ; Vector Number 65,SDIO + DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 + DCD SPI2_IRQHandler ; Vector Number 67,SPI2 + DCD UART3_IRQHandler ; Vector Number 68,UART3 + DCD UART4_IRQHandler ; Vector Number 69,UART4 + DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 + DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 + DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 + DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, = SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK USBD_HP_CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_HP_CAN0_TX_IRQHandler + B USBD_HP_CAN0_TX_IRQHandler + + PUBWEAK USBD_LP_CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_LP_CAN0_RX0_IRQHandler + B USBD_LP_CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_TIMER8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_TIMER8_IRQHandler + B TIMER0_BRK_TIMER8_IRQHandler + + PUBWEAK TIMER0_UP_TIMER9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_TIMER9_IRQHandler + B TIMER0_UP_TIMER9_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_TIMER10_IRQHandler + B TIMER0_TRG_CMT_TIMER10_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBD_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_WKUP_IRQHandler + B USBD_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_TIMER11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_TIMER11_IRQHandler + B TIMER7_BRK_TIMER11_IRQHandler + + PUBWEAK TIMER7_UP_TIMER12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_TIMER12_IRQHandler + B TIMER7_UP_TIMER12_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_TIMER13_IRQHandler + B TIMER7_TRG_CMT_TIMER13_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_4_IRQHandler + B DMA1_Channel3_4_IRQHandler + + END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c new file mode 100644 index 0000000000..699179711a --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c @@ -0,0 +1,1028 @@ +/*! + \file system_gd32f10x.c + \brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for + GD32F10x Device Series +*/ + +/* + Copyright (c) 2012 ARM LIMITED + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f10x.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/* use HXTAL (XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */ +//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + +#ifdef GD32F10X_CL + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + + RCU_CFG1 = 0x00000000U; +#else + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | + RCU_CFG0_USBDPSC | RCU_CFG0_PLLMF_4); +#endif /* GD32F10X_CL */ + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* reset HXTALEN, CKMEN and PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x009F0000U; +#elif defined(GD32F10X_CL) + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; +#endif + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; +#ifdef GD32F10X_CL + uint32_t predv0, predv1, pll1mf; +#endif /* GD32F10X_CL */ + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); + + /* PREDV0 input source clock divided by 2 */ + if(RCU_CFG0_PREDV0 == predv0sel){ + ck_src = HXTAL_VALUE / 2U; + } +#elif defined(GD32F10X_CL) + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + +#ifdef GD32F10X_CL + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } +#endif /* GD32F10X_CL */ + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL6; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL9; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL14; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL24; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + +#elif defined(GD32F10X_CL) + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/core_cm3.h b/bsp/gd32107c-eval/Libraries/CMSIS/core_cm3.h new file mode 100644 index 0000000000..1b661b4421 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/core_cm3.h @@ -0,0 +1,1638 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32107c-eval/Libraries/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..01089f1333 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32107c-eval/Libraries/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..856b4c3c61 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/CMSIS/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h new file mode 100644 index 0000000000..bb61cd73b5 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h @@ -0,0 +1,368 @@ +/*! + \file gd32f10x_adc.h + \brief definitions for the ADC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10x_ADC_H +#define GD32F10x_ADC_H + +#include "gd32f10x.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x400U) +#define ADC2 (ADC_BASE + 0x1800U) + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx x=0..2 */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ + +/* constants definitions */ +/* adc_stat register value */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +/* scan mode */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + +/* inserted channel group convert automatically */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ + +/* ADC sync mode */ +#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ +#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ +#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ +#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ + +/* adc_ctl1 register value */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* continuous mode */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* external trigger select for regular channel */ +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ +/* for ADC0 and ADC1 regular channel */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ +/* for ADC2 regular channel */ +#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */ +#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */ +#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */ +#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */ +#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */ +#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */ + +/* external trigger mode for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ +/* for ADC0 and ADC1 inserted channel */ +#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */ +#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ +/* for ADC2 inserted channel */ +#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */ +#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */ +#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */ +#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */ +#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ + +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ + +/* ADC interrupt */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* function declarations */ +/* initialization config */ +/* reset ADC */ +void adc_deinit(uint32_t adc_periph); +/* configure the ADC sync mode */ +void adc_mode_config(uint32_t mode); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); + +/* DMA config */ +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); + +/* regular group and inserted group config */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); + +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); + +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); +/* configure ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); + +/* get channel data */ +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); +/* read the last ADC0 and ADC1 conversion result data in sync mode */ +uint32_t adc_sync_mode_convert_value_read(void); + +/* watchdog config */ +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); + +/* interrupt & flag functions */ +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); +/* get the bit state of ADCx software start conversion */ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +/* get the bit state of ADCx software inserted channel start conversion */ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); + +#endif /* GD32F10x_ADC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h new file mode 100644 index 0000000000..73f93252fe --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h @@ -0,0 +1,230 @@ +/*! + \file gd32f10x_bkp.h + \brief definitions for the BKP + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_BKP_H +#define GD32F10X_BKP_H + +#include "gd32f10x.h" + +/* BKP definitions */ +#define BKP BKP_BASE /*!< BKP base address */ + +/* registers definitions */ +#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ +#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ +#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ +#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ +#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ +#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ +#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ +#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ +#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ +#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ +#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ +#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ +#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ +#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ +#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ +#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ +#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ +#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ +#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ +#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ +#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ +#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ +#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ +#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ +#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ +#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ +#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ +#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ +#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ +#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ +#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ +#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ +#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ +#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ +#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ +#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ +#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ +#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ +#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ +#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ +#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ +#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ +#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ +#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ +#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ + +/* bits definitions */ +/* BKP_DATA */ +#define BKP_DATA BITS(0,15) /*!< backup data */ + +/* BKP_OCTL */ +#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ +#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ +#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ +#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ + +/* BKP_TPCTL */ +#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ +#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ + +/* BKP_TPCS */ +#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ +#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ +#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ +#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ +#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ + +/* constants definitions */ +/* BKP data register number */ +typedef enum +{ + BKP_DATA_0 = 1, /*!< BKP data register 0 */ + BKP_DATA_1, /*!< BKP data register 1 */ + BKP_DATA_2, /*!< BKP data register 2 */ + BKP_DATA_3, /*!< BKP data register 3 */ + BKP_DATA_4, /*!< BKP data register 4 */ + BKP_DATA_5, /*!< BKP data register 5 */ + BKP_DATA_6, /*!< BKP data register 6 */ + BKP_DATA_7, /*!< BKP data register 7 */ + BKP_DATA_8, /*!< BKP data register 8 */ + BKP_DATA_9, /*!< BKP data register 9 */ + BKP_DATA_10, /*!< BKP data register 10 */ + BKP_DATA_11, /*!< BKP data register 11 */ + BKP_DATA_12, /*!< BKP data register 12 */ + BKP_DATA_13, /*!< BKP data register 13 */ + BKP_DATA_14, /*!< BKP data register 14 */ + BKP_DATA_15, /*!< BKP data register 15 */ + BKP_DATA_16, /*!< BKP data register 16 */ + BKP_DATA_17, /*!< BKP data register 17 */ + BKP_DATA_18, /*!< BKP data register 18 */ + BKP_DATA_19, /*!< BKP data register 19 */ + BKP_DATA_20, /*!< BKP data register 20 */ + BKP_DATA_21, /*!< BKP data register 21 */ + BKP_DATA_22, /*!< BKP data register 22 */ + BKP_DATA_23, /*!< BKP data register 23 */ + BKP_DATA_24, /*!< BKP data register 24 */ + BKP_DATA_25, /*!< BKP data register 25 */ + BKP_DATA_26, /*!< BKP data register 26 */ + BKP_DATA_27, /*!< BKP data register 27 */ + BKP_DATA_28, /*!< BKP data register 28 */ + BKP_DATA_29, /*!< BKP data register 29 */ + BKP_DATA_30, /*!< BKP data register 30 */ + BKP_DATA_31, /*!< BKP data register 31 */ + BKP_DATA_32, /*!< BKP data register 32 */ + BKP_DATA_33, /*!< BKP data register 33 */ + BKP_DATA_34, /*!< BKP data register 34 */ + BKP_DATA_35, /*!< BKP data register 35 */ + BKP_DATA_36, /*!< BKP data register 36 */ + BKP_DATA_37, /*!< BKP data register 37 */ + BKP_DATA_38, /*!< BKP data register 38 */ + BKP_DATA_39, /*!< BKP data register 39 */ + BKP_DATA_40, /*!< BKP data register 40 */ + BKP_DATA_41, /*!< BKP data register 41 */ +}bkp_data_register_enum; + +/* BKP register */ +#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) +#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) + +/* get data of BKP data register */ +#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + +/* RTC clock calibration value */ +#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/* RTC output selection */ +#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ +#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ + +/* tamper pin active level */ +#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ +#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ + +/* tamper flag */ +#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ + +/* tamper interrupt flag */ +#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ +/* function declarations */ +/* reset BKP registers */ +void bkp_deinit(void); +/* write BKP data register */ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); +/* read BKP data register */ +uint16_t bkp_data_read(bkp_data_register_enum register_number); + +/* RTC related functions */ +/* enable RTC clock calibration output */ +void bkp_rtc_calibration_output_enable(void); +/* disable RTC clock calibration output */ +void bkp_rtc_calibration_output_disable(void); +/* enable RTC alarm or second signal output */ +void bkp_rtc_signal_output_enable(void); +/* disable RTC alarm or second signal output */ +void bkp_rtc_signal_output_disable(void); +/* select RTC output */ +void bkp_rtc_output_select(uint16_t outputsel); +/* set RTC clock calibration value */ +void bkp_rtc_calibration_value_set(uint8_t value); + +/* tamper pin related functions */ +/* enable tamper pin detection */ +void bkp_tamper_detection_enable(void); +/* disable tamper pin detection */ +void bkp_tamper_detection_disable(void); +/* set tamper pin active level */ +void bkp_tamper_active_level_set(uint16_t level); + +/* interrupt & flag functions */ +/* enable tamper interrupt */ +void bkp_interrupt_enable(void); +/* disable tamper interrupt */ +void bkp_interrupt_disable(void); +/* get tamper flag state */ +FlagStatus bkp_flag_get(void); +/* clear tamper flag state */ +void bkp_flag_clear(void); +/* get tamper interrupt flag state */ +FlagStatus bkp_interrupt_flag_get(void); +/* clear tamper interrupt flag state */ +void bkp_interrupt_flag_clear(void); + +#endif /* GD32F10X_BKP_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h new file mode 100644 index 0000000000..0e5ae1f251 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h @@ -0,0 +1,725 @@ +/*! + \file gd32f10x_can.h + \brief definitions for the CAN + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10x_CAN_H +#define GD32F10x_CAN_H + +#include "gd32f10x.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ + +/* registers definitions */ +#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ + +/* CAN transmit mailbox bank */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ + +/* CAN filter bank */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ + +/* CAN receive fifo mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ + +/* bits definitions */ +/* CAN_CTL */ +#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ +#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ +#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ +#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ +#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ +#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ +#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ +#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ +#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ +#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ + +/* CAN_STAT */ +#define CAN_STAT_IWS BIT(0) /*!< initial working state */ +#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ +#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ +#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ +#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ +#define CAN_STAT_TS BIT(8) /*!< transmitting state */ +#define CAN_STAT_RS BIT(9) /*!< receiving state */ +#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ +#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ + +/* CAN_TSTAT */ +#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ +#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ +#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ +#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ +#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ +#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ +#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ +#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ +#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ +#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ +#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ +#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ +#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ +#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ +#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ +#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ +#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ +#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ +#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ +#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ +#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + +/* CAN_RFIFO0 */ +#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ +#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ +#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ +#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + +/* CAN_RFIFO1 */ +#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ +#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ +#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ +#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + +/* CAN_INTEN */ +#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ +#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ +#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ +#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ +#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ +#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ +#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ + +/* CAN_ERR */ +#define CAN_ERR_WERR BIT(0) /*!< warning error */ +#define CAN_ERR_PERR BIT(1) /*!< passive error */ +#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ + +/* CAN_BT */ +#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ +#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ +#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + +/* CAN_TMIx */ +#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ +#define CAN_TMI_FT BIT(1) /*!< frame type */ +#define CAN_TMI_FF BIT(2) /*!< frame format */ +#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_TMPx */ +#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ +#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_TMDATA0x */ +#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ + +/* CAN_TMDATA1x */ +#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ + +/* CAN_RFIFOMIx */ +#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ +#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_RFIFOMPx */ +#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_RFIFOMDATA0x */ +#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ + +/* CAN_RFIFOMDATA1x */ +#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ + +/* CAN_FCTL */ +#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ + +/* CAN_FMCFG */ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + +/* CAN_FSCFG */ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ + +/* CAN_FAFIFO */ +#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ + +/* CAN_FW */ +#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ + +/* CAN_FxDATAy */ +#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ + +/* consts definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ +#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ +#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ +#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ +#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ + +/* CAN flags */ +typedef enum +{ + /* flags in TSTAT register */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +}can_flag_enum; + +/* CAN interrupt flags */ +typedef enum +{ + /* interrupt flags in STAT register */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ +}can_interrupt_flag_enum; + +/* CAN initiliaze parameters struct */ +typedef struct +{ + uint8_t working_mode; /*!< CAN working mode */ + uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ + ControlStatus time_triggered; /*!< time triggered communication mode */ + ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ + ControlStatus auto_wake_up; /*!< automatic wake-up mode */ + ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ + ControlStatus trans_fifo_order; /*!< transmit FIFO order */ + uint16_t prescaler; /*!< baudrate prescaler */ +}can_parameter_struct; + +/* CAN transmit message struct */ +typedef struct +{ + uint32_t tx_sfid; /*!< standard format frame identifier */ + uint32_t tx_efid; /*!< extended format frame identifier */ + uint8_t tx_ff; /*!< format of frame, standard or extended format */ + uint8_t tx_ft; /*!< type of frame, data or remote */ + uint8_t tx_dlen; /*!< data length */ + uint8_t tx_data[8]; /*!< transmit data */ +}can_trasnmit_message_struct; + +/* CAN receive message struct */ +typedef struct +{ + uint32_t rx_sfid; /*!< standard format frame identifier */ + uint32_t rx_efid; /*!< extended format frame identifier */ + uint8_t rx_ff; /*!< format of frame, standard or extended format */ + uint8_t rx_ft; /*!< type of frame, data or remote */ + uint8_t rx_dlen; /*!< data length */ + uint8_t rx_data[8]; /*!< receive data */ + uint8_t rx_fi; /*!< filtering index */ +} can_receive_message_struct; + +/* CAN filter parameters struct */ +typedef struct +{ + uint16_t filter_list_high; /*!< filter list number high bits*/ + uint16_t filter_list_low; /*!< filter list number low bits */ + uint16_t filter_mask_high; /*!< filter mask number high bits */ + uint16_t filter_mask_low; /*!< filter mask number low bits */ + uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ + uint16_t filter_number; /*!< filter number */ + uint16_t filter_mode; /*!< filter mode, list or mask */ + uint16_t filter_bits; /*!< filter scale */ + ControlStatus filter_enable; /*!< filter work or not */ +}can_filter_parameter_struct; + +/* CAN errors */ +typedef enum +{ + CAN_ERROR_NONE = 0, /*!< no error */ + CAN_ERROR_FILL, /*!< fill error */ + CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_ACK, /*!< ACK error */ + CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ + CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_CRC, /*!< CRC error */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ +}can_error_enum; + +/* transmit states */ +typedef enum +{ + CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ +}can_transmit_state_enum; + +typedef enum +{ + CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_FILTER_STRUCT, /* CAN filter parameters struct */ + CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ + CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ +}can_struct_type_enum; + +/* CAN baudrate prescaler*/ +#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) + +/* CAN bit segment 1*/ +#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) + +/* CAN bit segment 2*/ +#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) + +/* CAN resynchronization jump width*/ +#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) + +/* CAN communication mode*/ +#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) + +/* CAN FDATA high 16 bits */ +#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) + +/* CAN FDATA low 16 bits */ +#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) + +/* CAN1 filter start bank_number*/ +#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) + +/* CAN transmit mailbox extended identifier*/ +#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) + +/* CAN transmit mailbox standard identifier*/ +#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) + +/* transmit data byte 0 */ +#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 1 */ +#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 2 */ +#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* receive mailbox extended identifier*/ +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) + +/* receive mailbox standrad identifier*/ +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) + +/* receive data length */ +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) + +/* the index of the filter by which the frame is passed */ +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 0 */ +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 1 */ +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 2 */ +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 3 */ +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* receive data byte 4 */ +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 5 */ +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 6 */ +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 7 */ +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* CAN errors */ +#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ +#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ + +#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ + +/* CAN communication mode */ +#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ +#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ +#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ +#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ + +/* CAN resynchronisation jump width */ +#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ + +/* CAN time segment 1 */ +#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ +#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ +#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ +#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ +#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ +#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ +#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ +#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ +#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ + +/* CAN time segment 2 */ +#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ + +/* CAN mailbox number */ +#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ +#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ +#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ +#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ + +/* CAN frame format */ +#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ +#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ + +/* CAN receive fifo */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ + +/* frame number of receive fifo */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ + +#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ +#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ + +/* CAN working mode */ +#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ +#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ +#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ + +/* filter bits */ +#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ +#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ + +/* filter mode */ +#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ +#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ + +/* filter 16 bits mask */ +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ + +/* frame type */ +#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ +#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ + +/* CAN timeout */ +#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ + +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + +/* function declarations */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* initialize CAN struct */ +void can_struct_para_init(can_struct_type_enum type, void* p_struct); +/* initialize CAN */ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); +/* CAN filter init */ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); +/* set can1 fliter start bank number */ +void can1_filter_start_bank(uint8_t start_bank); +/* enable functions */ +/* CAN debug freeze enable */ +void can_debug_freeze_enable(uint32_t can_periph); +/* CAN debug freeze disable */ +void can_debug_freeze_disable(uint32_t can_periph); +/* CAN time trigger mode enable */ +void can_time_trigger_mode_enable(uint32_t can_periph); +/* CAN time trigger mode disable */ +void can_time_trigger_mode_disable(uint32_t can_periph); + +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +/* CAN receive message */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); +/* CAN release fifo */ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); +/* CAN receive message length */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); +/* CAN working mode */ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); +/* CAN wakeup from sleep mode */ +ErrStatus can_wakeup(uint32_t can_periph); + +/* CAN get error */ +can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* CAN get flag state */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* CAN clear flag state */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN get interrupt flag state */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); +/* CAN clear interrupt flag state */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); + +#endif /* GD32F10x_CAN_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h new file mode 100644 index 0000000000..9f2781ff26 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h @@ -0,0 +1,81 @@ +/*! + \file gd32f10x_crc.h + \brief definitions for the CRC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_CRC_H +#define GD32F10X_CRC_H + +#include "gd32f10x.h" + +/* CRC definitions */ +#define CRC CRC_BASE + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* reset data register to the value of initializaiton data register */ +void crc_data_register_reset(void); +/* read the value of the data register */ +uint32_t crc_data_register_read(void); + +/* read the value of the free data register */ +uint8_t crc_free_data_register_read(void); +/* write data to the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* calculate the CRC value of a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* calculate the CRC value of an array of 32-bit values */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32F10X_CRC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h new file mode 100644 index 0000000000..aa9e70bbf8 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h @@ -0,0 +1,250 @@ +/*! + \file gd32f10x_dac.h + \brief definitions for the DAC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_DAC_H +#define GD32F10X_DAC_H + +#include "gd32f10x.h" + +/* DACx(x=0,1) definitions */ +#define DAC DAC_BASE +#define DAC0 0U +#define DAC1 1U + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + +/* DAC0_R12DH */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + +/* DAC0_L12DH */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + +/* DAC0_R8DH */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + +/* DAC1_R12DH */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + +/* DAC1_L12DH */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + +/* DAC1_R8DH */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + +/* DACC_R12DH */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + +/* DACC_L12DH */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + +/* DACC_R8DH */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + +/* DAC0_DO */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ + +/* DAC1_DO */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#elif defined(GD32F10X_CL) +#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(uint32_t dac_periph); +/* disable DAC */ +void dac_disable(uint32_t dac_periph); +/* enable DAC DMA */ +void dac_dma_enable(uint32_t dac_periph); +/* disable DAC DMA */ +void dac_dma_disable(uint32_t dac_periph); +/* enable DAC output buffer */ +void dac_output_buffer_enable(uint32_t dac_periph); +/* disable DAC output buffer */ +void dac_output_buffer_disable(uint32_t dac_periph); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ +/* enable DAC trigger */ +void dac_trigger_enable(uint32_t dac_periph); +/* disable DAC trigger */ +void dac_trigger_disable(uint32_t dac_periph); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* enable DAC software trigger */ +void dac_software_trigger_enable(uint32_t dac_periph); +/* disable DAC software trigger */ +void dac_software_trigger_disable(uint32_t dac_periph); + +/* DAC wave mode configuration */ +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); + +/* DAC concurrent mode configuration */ +/* enable DAC concurrent mode */ +void dac_concurrent_enable(void); +/* disable DAC concurrent mode */ +void dac_concurrent_disable(void); +/* enable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_enable(void); +/* disable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_disable(void); +/* enable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_enable(void); +/* disable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_disable(void); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); + +#endif /* GD32F10X_DAC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h new file mode 100644 index 0000000000..d9248414b8 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h @@ -0,0 +1,152 @@ +/*! + \file gd32f10x_dbg.h + \brief definitions for the DBG + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_DBG_H +#define GD32F10X_DBG_H + +#include "gd32f10x.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL */ +#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ +#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ +#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ +#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ +#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */ +#define DBG_CTL_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */ +#ifdef GD32F10x_CL +#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ +#endif /* GD32F10x_CL */ +#ifdef GD32F10X_XD +#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ +#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ +#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ +#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ +#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ +#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ +#endif /* GD32F10x_XD */ + +/* constants definitions */ +/* debug hold when core is halted */ +typedef enum +{ + DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ + DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ + DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ + DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ + DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */ +#ifdef GD32F10x_CL + DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ +#endif /* GD32F10x_CL */ +#if (defined(GD32F10x_XD) || defined(GD32F10x_CL)) + DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ + DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ +#endif /* GD32F10x_XD || GD32F10x_CL*/ +}dbg_periph_enum; + +/* DBG low power mode configurations */ +#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* DBG_CTL0_TRACE_MODE configurations */ +#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) +#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ +#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ +#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ +#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ + +/* function declarations */ +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* low power behavior configuration */ +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* peripheral behavior configuration */ +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +/* trace pin assignment configuration */ +/* enable trace pin assignment */ +void dbg_trace_pin_enable(void); +/* disable trace pin assignment */ +void dbg_trace_pin_disable(void); +/* set trace pin mode */ +void dbg_trace_pin_mode_set(uint32_t trace_mode); + +#endif /* GD32F10x_DBG_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h new file mode 100644 index 0000000000..3a90e8d690 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h @@ -0,0 +1,289 @@ +/*! + \file gd32f10x_dma.h + \brief definitions for the DMA + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_DMA_H +#define GD32F10X_DMA_H + +#include "gd32f10x.h" + +/* DMA definitions */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ + +/* registers definitions */ +#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ +#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL, x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT, x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR, x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR, x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA channel 0 */ + DMA_CH1, /*!< DMA channel 1 */ + DMA_CH2, /*!< DMA channel 2 */ + DMA_CH3, /*!< DMA channel 3 */ + DMA_CH4, /*!< DMA channel 4 */ + DMA_CH5, /*!< DMA channel 5 */ + DMA_CH6 /*!< DMA channel 6 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + +} dma_parameter_struct; + +#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_register address */ +#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ +/* circular mode */ +#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */ +#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ + +/* memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */ + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ + +/* function declarations */ +/* DMA deinitialization and initialization functions */ +/* deinitialize DMA a channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the parameters of DMA struct with the default values */ +void dma_struct_para_init(dma_parameter_struct* init_struct); +/* initialize DMA channel */ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* DMA configuration functions */ +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set DMA memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); + +/* flag and interrupt functions */ +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the flag of a DMA channel */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the interrupt flag of a DMA channel */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); + +#endif /* GD32F10X_DMA_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h new file mode 100644 index 0000000000..310fb2f8d8 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h @@ -0,0 +1,1498 @@ +/*! + \file gd32f10x_enet.h + \brief definitions for the ENET + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10x_ENET_H +#define GD32F10x_ENET_H + +#include "gd32f10x.h" +#include + +#define IF_USE_EXTERNPHY_LIB 0 +#if (1 == IF_USE_EXTERNPHY_LIB) +#include "phy.h" +#endif + +#ifndef ENET_RXBUF_NUM +#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ +#endif + +#ifndef ENET_TXBUF_NUM +#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ +#endif + +#ifndef ENET_RXBUF_SIZE +#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ +#endif + +#ifndef ENET_TXBUF_SIZE +#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ +#endif + +/* #define USE_DELAY */ + +#ifndef _PHY_H_ +#define DP83848 0 +#define LAN8700 1 +#define PHY_TYPE DP83848 + +#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ + +/* PHY read write timeouts */ +#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ +#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ + +/* PHY delay */ +#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ +#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ + +/* PHY register address */ +#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ +#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ + +/* PHY basic control register */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ + +/* PHY basic status register */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ + +#if(PHY_TYPE == LAN8700) +#define PHY_SR 31U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ +#elif(PHY_TYPE == DP83848) +#define PHY_SR 16U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ +#endif /* PHY_TYPE */ + +#endif /* _PHY_H_ */ + + +/* ENET definitions */ +#define ENET ENET_BASE + +/* registers definitions */ +#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ +#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ + +#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ + +#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ + +#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ +#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ +#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ +#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ +#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ +#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ +#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ +#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ +#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ + +/* bits definitions */ +/* ENET_MAC_CFG */ +#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ +#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ +#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ +#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ +#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ +#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ +#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ +#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ +#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ +#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ +#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ +#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ +#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ + +/* ENET_MAC_FRMF */ +#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ +#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + +/* ENET_MAC_HLH */ +#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ + +/* ENET_MAC_HLL */ +#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ + +/* ENET_MAC_PHY_CTL */ +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + +/* ENET_MAC_PHY_DATA */ +#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ + +/* ENET_MAC_FCTL */ +#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ +#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ +#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ +#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ +#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ + +/* ENET_MAC_FCTH */ +#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ +#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ + +/* ENET_MAC_VLT */ +#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ +#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ + +/* ENET_MAC_RWFF */ +#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ + +/* ENET_MAC_WUM */ +#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ +#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ +#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ +#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ +#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ +#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ +#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ + +/* ENET_MAC_INTF */ +#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ +#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ +#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ +#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ +#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ + +/* ENET_MAC_INTMSK */ +#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ +#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ + +/* ENET_MAC_ADDR0H */ +#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ +#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ + +/* ENET_MAC_ADDR0L */ +#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ + +/* ENET_MAC_ADDR1H */ +#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR1L */ +#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ + +/* ENET_MAC_ADDR2H */ +#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ +#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR2L */ +#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ + +/* ENET_MAC_ADDR3H */ +#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ +#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR3L */ +#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ + +/* ENET_MSC_CTL */ +#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ +#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ +#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ +#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ + +/* ENET_MSC_RINTF */ +#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ +#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ +#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ + +/* ENET_MSC_TINTF */ +#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ +#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ +#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ + +/* ENET_MSC_RINTMSK */ +#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ +#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ +#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ + +/* ENET_MSC_TINTMSK */ +#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ + +/* ENET_MSC_SCCNT */ +#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ + +/* ENET_MSC_MSCCNT */ +#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ + +/* ENET_MSC_TGFCNT */ +#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ + +/* ENET_MSC_RFCECNT */ +#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ + +/* ENET_MSC_RFAECNT */ +#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ + +/* ENET_MSC_RGUFCNT */ +#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ + +/* ENET_PTP_TSCTL */ +#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ +#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ +#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ +#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ +#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ +#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ + +/* ENET_PTP_SSINC */ +#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ + +/* ENET_PTP_TSH */ +#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ + +/* ENET_PTP_TSL */ +#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ +#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ + +/* ENET_PTP_TSUH */ +#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ + +/* ENET_PTP_TSUL */ +#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ +#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ + +/* ENET_PTP_TSADDEND */ +#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ + +/* ENET_PTP_ETH */ +#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ + +/* ENET_PTP_ETL */ +#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ + +/* ENET_DMA_BCTL */ +#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ +#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ +#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ +#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ +#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ +#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ +#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ +#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ +#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ +#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ + +/* ENET_DMA_TPEN */ +#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ + +/* ENET_DMA_RPEN */ +#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ + +/* ENET_DMA_RDTADDR */ +#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ + +/* ENET_DMA_TDTADDR */ +#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ + +/* ENET_DMA_STAT */ +#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ +#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ +#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ +#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ +#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ +#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ +#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ +#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ +#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ +#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ +#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ +#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ +#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ +#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ +#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ +#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ +#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ +#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ +#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ +#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ +#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ + +/* ENET_DMA_CTL */ +#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ +#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ +#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ +#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ +#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ +#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ +#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ +#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ +#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ +#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ +#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ +#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ + +/* ENET_DMA_INTEN */ +#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ +#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ +#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ +#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ +#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ +#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ +#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ +#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ +#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ +#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ +#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ +#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ +#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ + +/* ENET_DMA_MFBOCNT */ +#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ +#define ENET_DMA_MFBOCNT_OBMFC BIT(16) /* Overflow bit for missed frame counter */ +#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ +#define ENET_DMA_MFBOCNT_OBFOC BIT(28) /*!< Overflow bit for FIFO overflow counter */ + +/* ENET_DMA_CTDADDR */ +#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ + +/* ENET_DMA_CRDADDR */ +#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ + +/* ENET_DMA_CTBADDR */ +#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ + +/* ENET_DMA_CRBADDR */ +#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ + +/* ENET DMA Tx descriptor TDES0 */ +#define ENET_TDES0_DB BIT(0) /*!< deferred */ +#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ +#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ +#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ +#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ +#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ +#define ENET_TDES0_LCO BIT(9) /*!< late collision */ +#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ +#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ +#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ +#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ +#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ +#define ENET_TDES0_ES BIT(15) /*!< error summary */ +#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ +#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ +#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ +#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ +#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ +#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ +#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ +#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ +#define ENET_TDES0_FSG BIT(28) /*!< first segment */ +#define ENET_TDES0_LSG BIT(29) /*!< last segment */ +#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ +#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ + +/* ENET DMA Tx descriptor TDES1 */ +#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ +#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ + +/* ENET DMA Tx descriptor TDES2 */ +#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES3 */ +#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ + +/* ENET DMA Rx descriptor RDES0 */ +#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ +#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ +#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ +#define ENET_RDES0_RERR BIT(3) /*!< receive error */ +#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ +#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ +#define ENET_RDES0_LCO BIT(6) /*!< late collision */ +#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ +#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ +#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ +#define ENET_RDES0_LERR BIT(12) /*!< length error */ +#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ +#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ +#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ +#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ +#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ +#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ + +/* ENET DMA Rx descriptor RDES1 */ +#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ +#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ +#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ +#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ +#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ + +/* ENET DMA Rx descriptor RDES2 */ +#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ + +/* ENET DMA Rx descriptor RDES3 */ +#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ + +/* constants definitions */ +/* define bit position and its register index offset */ +#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) +#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* ENET clock range judgement */ +#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) + +/* define MAC address configuration and reference address */ +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) +#define ENET_ADDRH_BASE ((ENET) + 0x40U) +#define ENET_ADDRL_BASE ((ENET) + 0x44U) +#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) + +/* register offset */ +#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ + +#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ + +#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ + +/* ENET status flag get */ +typedef enum +{ + /* ENET_MAC_WUM register */ + ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + /* ENET_MAC_FCTL register */ + ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ + /* ENET_MAC_INTF register */ + ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ + ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ + ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ + ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_flag_enum; + +/* ENET stutus flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_flag_clear_enum; + +/* ENET interrupt enable/disable */ +typedef enum +{ + /* ENET_MAC_INTMSK register */ + ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ + ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ + /* ENET_MSC_RINTMSK register */ + ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ + ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ + ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ + /* ENET_MSC_TINTMSK register */ + ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ + ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ + ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ + /* ENET_DMA_INTEN register */ + ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ + ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ + ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ + ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ + ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ + ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ + ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ + ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ + ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ + ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ + ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ + ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ + ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ + ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ + ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ +}enet_int_enum; + +/* ENET interrupt flag get */ +typedef enum +{ + /* ENET_MAC_INTF register */ + ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_int_flag_enum; + +/* ENET interrupt flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_int_flag_clear_enum; + +/* current RX/TX descriptor/buffer/descriptor table address get */ +typedef enum +{ + ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ + ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ + ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ + ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ + ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ + ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ +}enet_desc_reg_enum; + +/* MAC statistics counter get */ +typedef enum +{ + ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ + ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ + ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ + ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ + ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ + ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ +}enet_msc_counter_enum; + +/* function option, used for ENET initialization */ +typedef enum +{ + FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ + DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ + DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ + DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ + STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ + DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ + VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ + FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ + HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ + HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ + FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ + HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ + TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ + INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ +}enet_option_enum; + +/* phy mode and mac loopback configurations */ +typedef enum +{ + ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ + ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ + ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ + ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ + ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ + ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ +}enet_mediamode_enum; + +/* IP frame checksum function */ +typedef enum +{ + ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ + ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ + ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped */ +}enet_chksumconf_enum; + +/* received frame filter function */ +typedef enum +{ + ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ + ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ + ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ + ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ +}enet_frmrecept_enum; + +/* register group value get */ +typedef enum +{ + ALL_MAC_REG = 0, /*!< MAC register group */ + ALL_MSC_REG = 22, /*!< MSC register group */ + ALL_PTP_REG = 33, /*!< PTP register group */ + ALL_DMA_REG = 44, /*!< DMA register group */ +}enet_registers_type_enum; + +/* dma direction select */ +typedef enum +{ + ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ + ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ +}enet_dmadirection_enum; + +/* PHY operation direction select */ +typedef enum +{ + ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ + ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ +}enet_phydirection_enum; + +/* register operation direction select */ +typedef enum +{ + ENET_REG_READ, /*!< read register */ + ENET_REG_WRITE /*!< write register */ +}enet_regdirection_enum; + +/* ENET MAC addresses */ +typedef enum +{ + ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ + ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ + ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ + ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ +}enet_macaddress_enum; + +/* descriptor information */ +typedef enum +{ + TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ + TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ + RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ + RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ + RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ + RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ +}enet_descstate_enum; + +/* structure for initialization of the ENET */ +typedef struct +{ + uint32_t option_enable; /*!< select which function to configure */ + uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ + uint32_t dma_maxburst; /*!< DMA max burst related parameters */ + uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ + uint32_t store_forward_mode; /*!< store forward mode related parameters */ + uint32_t dma_function; /*!< DMA control related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t flow_control; /*!< flow control related parameters */ + uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ + uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ + uint32_t framesfilter_mode; /*!< frame filter control related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t timer_config; /*!< frame timer related parameters */ + uint32_t interframegap; /*!< inter frame gap related parameters */ +}enet_initpara_struct; + +/* structure for ENET DMA desciptors */ +typedef struct +{ + uint32_t status; /*!< status */ + uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ + uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ + uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ +} enet_descriptors_struct; + +/* structure of PTP system time */ +typedef struct +{ + uint32_t second; /*!< second of system time */ + uint32_t nanosecond; /*!< nanosecond of system time */ + uint32_t sign; /*!< sign of system time */ +}enet_ptp_systime_struct; + +/* mac_cfg register value */ +#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ +#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ +#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ +#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ + +#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ +#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ +#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ +#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ + +#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ +#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ + +#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ +#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ + +#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ +#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ + +#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ +#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ + +#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ +#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ + +#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ +#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ + +#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ +#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ + +#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ +#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ + +#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ +#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ + +#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ +#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ +#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ + +#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ +#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ + +/* mac_frmf register value */ +#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ +#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ +#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ +#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ +#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ + +#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ +#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ + +#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ +#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ +#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ +#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ +#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ + +#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ +#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ + +#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ + +#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ +#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ + +#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ +#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ +#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ +#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ +#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ +#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ +#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ + +#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ +#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ +#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ +#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ + +/* mac_phy_ctl register value */ +#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ +#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ +#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ + +#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ + +#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ + +/* mac_phy_data register value */ +#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ + +/* mac_fctl register value */ +#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ +#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ +#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ +#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ + +#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ + +#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ +#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ + +#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ +#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ +#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ + +#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ + +#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ + +#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ +/* mac_vlt register value */ +#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ + +#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ +#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ + +/* mac_wum register value */ +#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ +#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ +#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ + +/* mac_addr0h register value */ +#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ + +/* mac_addrxh register value, x = 1,2,3 */ +#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ + +#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ +#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ +#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ +#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ + +#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ +#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ + +/* mac_fcth register value */ +#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ +#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ +#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ +#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ +#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ +#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ +#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ +#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ + +#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ +#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ +#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ +#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ + +/* msc_ctl register value */ +#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ +#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ +#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ + +/* ptp_tsctl register value */ +#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ +#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ + +/* ptp_ssinc register value */ +#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ + +/* ptp_tsl register value */ +#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ + +#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ +#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ + +#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ + +/* ptp_tsul register value */ +#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ + +#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ +#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ + +/* dma_bctl register value */ +#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ +#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ + +#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ +#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ +#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ +#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ +#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ + +#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ +#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ +#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ +#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ + +#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ +#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ + +#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ +#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ +#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ +#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ +#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ +#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ +#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ +#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ +#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ + +#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ +#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ + +#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ +#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ + +/* dma_stat register value */ +#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ +#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ +#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ +#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ +#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ +#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ +#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ + +#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ +#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ +#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ +#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ +#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ +#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ +#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ + +#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ +#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ +#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ +#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ + +/* dma_ctl register value */ +#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ +#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ +#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ +#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ + +#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ +#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ +#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ +#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ +#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ +#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ +#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ +#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ + +#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ +#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ + +#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ +#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ + +#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ +#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ +#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */ + +#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ +#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ + +#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ +#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ + +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ + +#define ENET_SECONDFRAME_OPT_ENABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode enable*/ +#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ +#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ + +/* dma_mfbocnt register value */ +#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ + +#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ + +/* dma tx descriptor tdes0 register value */ +#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ +#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ + +#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ + +/* dma tx descriptor tdes1 register value */ +#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ + +#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ + +/* dma rx descriptor rdes0 register value */ +#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ +#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ + +/* dma rx descriptor rdes1 register value */ +#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ +#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ + +#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ + +#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ + +/* dma rx descriptor rdes4 register value */ +#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ +#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ + +#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ +#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ + +/* ENET register mask value */ +#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ +#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ +#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ +#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ + +#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ + +typedef enum{ + ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ + ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ + ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ +}enet_ptp_function_enum; + + +/* ENET remote wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ + +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ + +/* ENET delay timeout */ +#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ +#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ + +/* function declarations */ +/* main function */ +/* deinitialize the ENET, and reset structure parameters for ENET initialization */ +void enet_deinit(void); +/* configure the parameters which are usually less cared for initialization */ +void enet_initpara_config(enet_option_enum option, uint32_t para); +/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); +/* reset all core internal registers located in CLK_TX and CLK_RX */ +ErrStatus enet_software_reset(void); +/* check receive frame valid and return frame size */ +uint32_t enet_rxframe_size_get(void); +/* initialize the dma tx/rx descriptors's parameters in chain mode */ +void enet_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma tx/rx descriptors's parameters in ring mode */ +void enet_descriptors_ring_init(enet_dmadirection_enum direction); +/* handle current received frame data to application buffer */ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); +/* handle current received frame but without data copy to application buffer */ +#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) +/* handle application buffer data to transmit it */ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); +/* handle current transmit frame but without data copy from application buffer */ +#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) +/* configure the transmit IP frame checksum offload calculation and insertion */ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); +/* ENET Tx and Rx function enable (include MAC and DMA module) */ +void enet_enable(void); +/* ENET Tx and Rx function disable (include MAC and DMA module) */ +void enet_disable(void); +/* configure MAC address */ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); +/* get MAC address */ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); + +/* get the ENET MAC/MSC/PTP/DMA status flag */ +FlagStatus enet_flag_get(enet_flag_enum enet_flag); +/* clear the ENET DMA status flag */ +void enet_flag_clear(enet_flag_clear_enum enet_flag); +/* enable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_enable(enet_int_enum enet_int); +/* disable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_disable(enet_int_enum enet_int); +/* get ENET MAC/MSC/DMA interrupt flag */ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); +/* clear ENET DMA interrupt flag */ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); + +/* MAC function */ +/* ENET Tx function enable (include MAC and DMA module) */ +void enet_tx_enable(void); +/* ENET Tx function disable (include MAC and DMA module) */ +void enet_tx_disable(void); +/* ENET Rx function enable (include MAC and DMA module) */ +void enet_rx_enable(void); +/* ENET Rx function disable (include MAC and DMA module) */ +void enet_rx_disable(void); +/* put registers value into the application buffer */ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); +/* enable the MAC address filter */ +void enet_address_filter_enable(enet_macaddress_enum mac_addr); +/* disable the MAC address filter */ +void enet_address_filter_disable(enet_macaddress_enum mac_addr); +/* configure the MAC address filter */ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); +/* PHY interface configuration (configure SMI clock and reset PHY chip) */ +ErrStatus enet_phy_config(void); +/* write to/read from a PHY register */ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); +/* enable the loopback function of phy chip */ +ErrStatus enet_phyloopback_enable(void); +/* disable the loopback function of phy chip */ +ErrStatus enet_phyloopback_disable(void); +/* enable ENET forward feature */ +void enet_forward_feature_enable(uint32_t feature); +/* disable ENET forward feature */ +void enet_forward_feature_disable(uint32_t feature); +/* enable ENET fliter feature */ +void enet_fliter_feature_enable(uint32_t feature); +/* disable ENET fliter feature */ +void enet_fliter_feature_disable(uint32_t feature); + +/* flow control function */ +/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ +ErrStatus enet_pauseframe_generate(void); +/* configure the pause frame detect type */ +void enet_pauseframe_detect_config(uint32_t detect); +/* configure the pause frame parameters */ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); +/* configure the threshold of the flow control(deactive and active threshold) */ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); +/* enable ENET flow control feature */ +void enet_flowcontrol_feature_enable(uint32_t feature); +/* disable ENET flow control feature */ +void enet_flowcontrol_feature_disable(uint32_t feature); + +/* DMA function */ +/* get the dma transmit/receive process state */ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +/* poll the dma transmission/reception enable */ +void enet_dmaprocess_resume(enet_dmadirection_enum direction); +/* check and recover the Rx process */ +void enet_rxprocess_check_recovery(void); +/* flush the ENET transmit fifo, and wait until the flush operation completes */ +ErrStatus enet_txfifo_flush(void); +/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); +/* get the Tx or Rx descriptor information */ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); +/* get the number of missed frames during receiving */ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); + +/* descriptor function */ +/* get the bit flag of ENET dma descriptor */ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); +/* set the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); +/* clear the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will set */ +void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will not set */ +void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc); +/* drop current receive frame */ +void enet_rxframe_drop(void); +/* enable DMA feature */ +void enet_dma_feature_enable(uint32_t feature); +/* disable DMA feature */ +void enet_dma_feature_disable(uint32_t feature); + +/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) + +/* WUM function */ +/* wakeup frame filter register pointer reset */ +void enet_wum_filter_register_pointer_reset(void); +/* set the remote wakeup frame registers */ +void enet_wum_filter_config(uint32_t pdata[]); +/* enable wakeup management features */ +void enet_wum_feature_enable(uint32_t feature); +/* disable wakeup management features */ +void enet_wum_feature_disable(uint32_t feature); + +/* MSC function */ +/* reset the MAC statistics counters */ +void enet_msc_counters_reset(void); +/* enable the MAC statistics counter features */ +void enet_msc_feature_enable(uint32_t feature); +/* disable the MAC statistics counter features */ +void enet_msc_feature_disable(uint32_t feature); +/* get MAC statistics counter */ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); + +/* PTP function */ +/* change subsecond to nanosecond */ +uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond); +/* change nanosecond to subsecond */ +uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond); +/* enable the PTP features */ +void enet_ptp_feature_enable(uint32_t feature); +/* disable the PTP features */ +void enet_ptp_feature_disable(uint32_t feature); +/* configure the PTP timestamp function */ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); +/* configure the PTP system time subsecond increment value */ +void enet_ptp_subsecond_increment_config(uint32_t subsecond); +/* adjusting the PTP clock frequency only in fine update mode */ +void enet_ptp_timestamp_addend_config(uint32_t add); +/* initializing or adding/subtracting to second of the PTP system time */ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); +/* configure the PTP expected target time */ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); +/* get the PTP current system time */ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); +/* configure and start PTP timestamp counter */ +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg); +/* adjust frequency in fine method by configure addend register */ +void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg); +/* update system time in coarse method */ +void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); +/* set system time in fine method */ +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct); +/* get the ptp flag status */ +FlagStatus enet_ptp_flag_get(uint32_t flag); + +/* internal function */ +/* reset the ENET initpara struct, call it before using enet_initpara_config() */ +void enet_initpara_reset(void); +/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ +static void enet_default_init(void); +#ifdef USE_DELAY +/* user can provide more timing precise _ENET_DELAY_ function */ +#define _ENET_DELAY_ delay_ms +#else +/* insert a delay time */ +static void enet_delay(uint32_t ncount); +/* default _ENET_DELAY_ function with less precise timing */ +#define _ENET_DELAY_ enet_delay +#endif + +#endif /* GD32F10X_ENET_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h new file mode 100644 index 0000000000..b9b1478a04 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h @@ -0,0 +1,432 @@ +/*! + \file gd32f10x_exmc.h + \brief definitions for the EXMC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_EXMC_H +#define GD32F10X_EXMC_H + +#include "gd32f10x.h" + +/* EXMC definitions */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ + +/* registers definitions */ +/* NOR/PSRAM */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ + +#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */ + +#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */ + +#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */ + +/* NAND/PC card */ +#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */ +#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */ + +#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */ +#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */ + +#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */ +#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */ +#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ + +/* bits definitions */ +/* NOR/PSRAM */ +/* EXMC_SNCTLx,x=0..3 */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ +#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ +#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ +#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ + +/* EXMC_SNTCFGx,x=0..3 */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ +#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_SNWTCFGx,x=0..3 */ +#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNWTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNWTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ +#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* NAND/PC card */ +/* EXMC_NPCTLx,x=1..3 */ +#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ +#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ +#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ +#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ + +/* EXMC_NPINTENx,x=1..3 */ +#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ +#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ +#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ +#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ +#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ +#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ +#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ + +/* EXMC_NPCTCFGx,x=1..3 */ +#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ + +/* EXMC_NPATCFGx,x=1..3 */ +#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ + +/* EXMC_PIOTCFG3 */ +#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ + +/* EXMC_NECCx,x=1,2 */ +#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ + +/* constants definitions */ +/* EXMC NOR/SRAM timing initialize struct */ +typedef struct +{ + uint32_t asyn_access_mode; /*!< asynchronous access mode */ + uint32_t syn_data_latency; /*!< configure the data latency */ + uint32_t syn_clk_division; /*!< configure the clock divide ratio */ + uint32_t bus_latency; /*!< configure the bus latency */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ +}exmc_norsram_timing_parameter_struct; + +/* EXMC NOR/SRAM initialize struct */ +typedef struct +{ + uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ + uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ + uint32_t extended_mode; /*!< enable or disable the extended mode */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ + uint32_t memory_write; /*!< enable or disable the write operation */ + uint32_t nwait_config; /*!< NWAIT signal configuration */ + uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ + uint32_t burst_mode; /*!< enable or disable the burst mode */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ + uint32_t memory_type; /*!< specifies the type of external memory */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing + parameters for read if the extended mode is used */ + exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ +}exmc_norsram_parameter_struct; + +/* EXMC NAND/PC card timing initialize struct */ +typedef struct +{ + uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ + uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ + uint32_t waittime; /*!< configure the minimum wait time */ + uint32_t setuptime; /*!< configure the address setup time */ +}exmc_nand_pccard_timing_parameter_struct; + +/* EXMC NAND initialize struct */ +typedef struct +{ + uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t ecc_size; /*!< the page size for the ECC calculation */ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ + uint32_t databus_width; /*!< the NAND flash databus width */ + uint32_t wait_feature; /*!< enables or disables the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +}exmc_nand_parameter_struct; + +/* EXMC PC card initialize struct */ +typedef struct +{ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t wait_feature; /*!< enables or disables the Wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ + exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */ +}exmc_pccard_parameter_struct;; + +/* EXMC register address */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ +#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */ + +#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */ +#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */ +#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */ +#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ +#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */ + +/* NOR bank memory data bus width */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ + +/* NOR bank memory type */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + +/* asynchronous access mode */ +#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ +#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ +#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ +#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ + +/* data latency for NOR flash */ +#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ +#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ +#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ +#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ +#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ +#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ +#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ +#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ +#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ +#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ +#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ +#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ +#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ +#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ +#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ +#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ + +/* synchronous clock divide ratio */ +#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ + +/* ECC size */ +#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ + +/* ALE to RE delay */ +#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ + +/* CLE to RE delay */ +#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ + +/* NAND bank memory data bus width */ +#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ +#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ + +/* EXMC NOR/SRAM bank region definition */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ +#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ +#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ +#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ + +/* EXMC NOR/SRAM write mode */ +#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ +#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */ + +/* EXMC NWAIT signal configuration */ +#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ +#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ + +/* EXMC NWAIT signal polarity configuration */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ + +/* EXMC NAND/PC card bank definition */ +#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ +#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ +#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ + +/* EXMC flag bits */ +#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ +#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ +#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ +#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ + +/* EXMC interrupt flag bits */ +#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ +#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ +#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ + +/* function declarations */ +/* deinitialize EXMC NOR/SRAM region */ +void exmc_norsram_deinit(uint32_t norsram_region); +/* exmc_norsram_parameter_struct parameter initialize */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* initialize EXMC NOR/SRAM region */ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* EXMC NOR/SRAM bank enable */ +void exmc_norsram_enable(uint32_t norsram_region); +/* EXMC NOR/SRAM bank disable */ +void exmc_norsram_disable(uint32_t norsram_region); + +/* deinitialize EXMC NAND bank */ +void exmc_nand_deinit(uint32_t nand_bank); +/* initialize EXMC NAND bank */ +void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* exmc_nand_init_struct parameter initialize */ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* EXMC NAND bank enable */ +void exmc_nand_enable(uint32_t nand_bank); +/* EXMC NAND bank disable */ +void exmc_nand_disable(uint32_t nand_bank); +/* enable or disable the EXMC NAND ECC function */ +void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue); +/* get the EXMC ECC value */ +uint32_t exmc_ecc_get(uint32_t nand_bank); + +/* deinitialize EXMC PC card bank */ +void exmc_pccard_deinit(void); +/* initialize EXMC PC card bank */ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* exmc_pccard_parameter_struct parameter initialize */ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* EXMC PC card bank enable */ +void exmc_pccard_enable(void); +/* EXMC PC card bank disable */ +void exmc_pccard_disable(void); + +/* enable EXMC interrupt */ +void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source); +/* disable EXMC interrupt */ +void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source); +/* check EXMC flag is set or not */ +FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag); +/* clear EXMC flag */ +void exmc_flag_clear(uint32_t bank, uint32_t flag); +/* check EXMC flag is set or not */ +FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source); +/* clear EXMC flag */ +void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source); + +#endif /* GD32F10X_EXMC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h new file mode 100644 index 0000000000..9822671976 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h @@ -0,0 +1,258 @@ +/*! + \file gd32f10x_exti.h + \brief definitions for the EXTI + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_EXTI_H +#define GD32F10X_EXTI_H + +#include "gd32f10x.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum +{ + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ +}exti_line_enum; + +/* external interrupt and event */ +typedef enum +{ + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +}exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum +{ + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH /*!< EXTI rising edge and falling edge trigger */ +}exti_trig_type_enum; + +/* function declarations */ +/* initialization, EXTI lines configuration functions */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* interrupt & flag functions */ +/* get EXTI lines pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI lines flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); +/* enable the EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); + +#endif /* GD32F10X_EXTI_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h new file mode 100644 index 0000000000..f5969b6436 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h @@ -0,0 +1,370 @@ +/*! + \file gd32f10x_fmc.h + \brief definitions for the FMC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_FMC_H +#define GD32F10X_FMC_H + +#include "gd32f10x.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option bytes base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ +#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ +#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ +#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ +#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ +#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ +#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ +#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ +#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ +#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ +#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ + +#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ +#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ +#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ +#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ +#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ + +/* FMC_KEY0 */ +#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT0 */ +#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL0 */ +#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ +#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ +#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ +#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ +#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR0 */ +#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash erase/program command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ +#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + +/* FMC_WP */ +#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ + +/* FMC_KEY1 */ +#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ + +/* FMC_STAT1 */ +#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL1 */ +#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */ +#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */ +#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */ +#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */ +#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR1 */ +#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash erase/program command address bits */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* define the FMC bit position and its register index offset */ +#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) +#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) +#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) + +/* configuration register */ +#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ +#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ +#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ +#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ +#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ + +/* fmc state */ +typedef enum +{ + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ +}fmc_state_enum; + +/* FMC interrupt enable */ +typedef enum +{ + FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ + FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ + FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ + FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ +}fmc_int_enum; + +/* FMC flags */ +typedef enum +{ + FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ + FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ + FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ + FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */ + FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ + FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ + FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ + FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ + FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ +}fmc_flag_enum; + +/* FMC interrupt flags */ +typedef enum +{ + FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ + FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ + FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ + FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ +}fmc_interrupt_flag_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* FMC wait state counter */ +#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ + +/* option bytes software/hardware free watch dog timer */ +#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ +#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ + +/* option bytes reset or not entering deep sleep mode */ +#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ + +/* option bytes reset or not entering standby mode */ +#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ + +/* option bytes boot bank value */ +#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ +#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ + +#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ + +/* OB_SPC */ +#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ +#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ + +/* OB_USER */ +#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ +#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ + +/* OB_WP0 */ +#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ + +/* OB_WP1 */ +#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ + +/* OB_WP2 */ +#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ + +/* OB_WP3 */ +#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ + +/* option bytes write protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ +#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ +#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ +#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ +#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ +#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ +#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ +#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ +#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ +#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ + +/* FMC timeout */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ + +/* FMC BANK address */ +#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ +#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ +#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* set the FMC wait state counter */ +void fmc_wscnt_set(uint32_t wscnt); +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* unlock the FMC bank0 operation */ +void fmc_bank0_unlock(void); +/* unlock the FMC bank1 operation */ +void fmc_bank1_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* lock the bank0 FMC operation */ +void fmc_bank0_lock(void); +/* lock the bank1 FMC operation */ +void fmc_bank1_lock(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC erase whole bank0 */ +fmc_state_enum fmc_bank0_erase(void); +/* FMC erase whole bank1 */ +fmc_state_enum fmc_bank1_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* erase the option byte */ +fmc_state_enum ob_erase(void); +/* enable write protect */ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); +/* configure the option byte security protection */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc); +/* write the FMC option byte */ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); +/* program option bytes data */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data); +/* get the FMC option byte user */ +uint8_t ob_user_get(void); +/* get OB_DATA in register FMC_OBSTAT */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint32_t ob_write_protection_get(void); +/* get option byte security protection code value */ +FlagStatus ob_spc_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* check flag is set or not */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC flag */ +void fmc_flag_clear(uint32_t flag); +/* get FMC interrupt flag state */ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); +/* clear FMC interrupt flag state */ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); +/* return the FMC bank0 state */ +fmc_state_enum fmc_bank0_state_get(void); +/* return the FMC bank1 state */ +fmc_state_enum fmc_bank1_state_get(void); +/* check FMC bank0 ready or not */ +fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); +/* check FMC bank1 ready or not */ +fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); + +#endif /* GD32F10X_FMC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h new file mode 100644 index 0000000000..2d22177e1e --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h @@ -0,0 +1,108 @@ +/*! + \file gd32f10x_fwdgt.h + \brief definitions for the FWDGT + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_FWDGT_H +#define GD32F10X_FWDGT_H + +#include "gd32f10x.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ + +/* constants definitions */ +/* psc register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + +/* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32F10X_FWDGT_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h new file mode 100644 index 0000000000..3b6b53a36d --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h @@ -0,0 +1,497 @@ +/*! + \file gd32f10x_gpio.h + \brief definitions for the GPIO + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10x_GPIO_H +#define GD32F10x_GPIO_H + +#include "gd32f10x.h" + +/* GPIOx(x=A,B,C,D,E,F,G) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOE (GPIO_BASE + 0x00001000U) +#define GPIOF (GPIO_BASE + 0x00001400U) +#define GPIOG (GPIO_BASE + 0x00001800U) + +/* AFIO definitions */ +#define AFIO AFIO_BASE + +/* registers definitions */ + +/* GPIO registers definitions */ +#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ +#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ + +/* AFIO registers definitions */ +#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ +#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ +#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ +#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ +#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ +#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ +#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ + +/* bits definitions */ +/* GPIO_CTL0 */ +#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ +#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ +#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ +#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ +#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ +#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ +#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ +#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ +#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ +#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ +#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ +#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ +#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ +#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ +#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ + +/* GPIO_CTL1 */ +#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ +#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ +#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ +#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ +#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ +#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ +#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ +#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ +#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ +#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ +#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ +#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ +#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ +#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ +#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* AFIO_EC */ +#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ +#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ +#define AFIO_EC_EOE BIT(7) /*!< event output enable */ + +/* AFIO_PCF0 */ +#ifdef GD32F10X_CL +/* memory map and bit definitions for GD32F10X_CL devices */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ +#define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ +#define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ +#define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ +#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ +#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ +#define AFIO_PCF0_TIMER1ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ +#define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ + +#else +/* memory map and bit definitions for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_REMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ +#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ +#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ +#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ +#endif /* GD32F10X_CL */ + +/* AFIO_EXTISS0 */ +#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ +#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ +#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ +#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ + +/* AFIO_EXTISS1 */ +#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ +#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ +#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ +#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ + +/* AFIO_EXTISS2 */ +#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ +#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ +#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ +#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ + +/* AFIO_EXTISS3 */ +#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ +#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ +#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ +#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ + +/* AFIO_PCF1 */ +#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ +#define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */ +#define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */ +#define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ +#define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ +#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* GPIO mode values set */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) +#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) + +/* GPIO mode definitions */ +#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ +#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ +#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ +#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ +#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ +#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ +#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ +#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ + +/* GPIO output max speed value */ +#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ + +/* GPIO event output port definitions */ +#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ +#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ +#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ +#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ +#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ + +/* GPIO output port source definitions */ +#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ +#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ +#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ +#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ +#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ +#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */ +#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */ + +/* GPIO event output pin definitions */ +#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ +#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ +#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ +#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ +#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ +#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ +#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ +#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ +#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ +#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ +#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ +#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ +#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ +#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ +#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ +#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ + +/* GPIO output pin source definitions */ +#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ +#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ +#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ +#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ +#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ +#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ +#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ +#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ +#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ +#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ +#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ +#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ +#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ +#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ +#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ +#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO remap definitions */ +#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ +#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ +#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ +#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ +#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ +#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ +#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ +#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ +#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ +#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ +#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ +#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN partial remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN full remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */ +#if (defined(GD32F10X_CL) || defined(GD32F10X_HD)) +#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) */ +#endif /* GD32F10X_CL||GD32F10X_HD */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U) /*!< ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U) /*!< ADC0 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U) /*!< ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U) /*!< ADC1 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ +#endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */ +#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ +#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled and SW-DP enabled */ +#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U) /*!< JTAG-DP disabled and SW-DP disabled */ +#ifdef GD32F10X_CL +#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping(only for GD32F10X_CL devices) */ +#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping(only for GD32F10X_CL devices) */ +#define GPIO_ENET_REMAP ((uint32_t)0x00200020U) /*!< ENET remapping(only for GD32F10X_CL devices) */ +#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping(only for GD32F10X_CL devices) */ +#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping(only for GD32F10X_CL devices) */ +#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) */ +#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U) /*!< ethernet PTP PPS remapping(only for GD32F10X_CL devices) */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD +#define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U) /*!< TIMER8 remapping */ +#define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U) /*!< TIMER9 remapping */ +#define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U) /*!< TIMER10 remapping */ +#define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U) /*!< TIMER12 remapping */ +#define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U) /*!< TIMER13 remapping */ +#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ +#endif /* GD32F10X_XD */ + +#ifdef GD32F10X_CL +/* ethernet MII or RMII PHY selection */ +#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */ +#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */ +#endif /* GD32F10X_CL */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* reset alternate function I/O(AFIO) */ +void gpio_afio_deinit(void); +/* GPIO parameter initialization */ +void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* configure GPIO pin remap */ +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); + +/* select GPIO pin exti sources */ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); +/* configure GPIO pin event output */ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); +/* enable GPIO pin event output */ +void gpio_event_output_enable(void); +/* disable GPIO pin event output */ +void gpio_event_output_disable(void); + +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +#ifdef GD32F10X_CL +/* select ethernet MII or RMII PHY */ +void gpio_ethernet_phy_select(uint32_t gpio_enetsel); +#endif /* GD32F10X_CL */ + + +#endif /* GD32F10x_GPIO_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h new file mode 100644 index 0000000000..ab884837dc --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h @@ -0,0 +1,346 @@ +/*! + \file gd32f10x_i2c.h + \brief definitions for the I2C + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_I2C_H +#define GD32F10X_I2C_H + +#include "gd32f10x.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking register */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ + +/* I2C flags */ +typedef enum +{ + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +}i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ +}i2c_interrupt_flag_enum; + +/* I2C interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ +}i2c_interrupt_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ + +/* I2C dual-address mode switch */ +#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ +#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ + +/* PEC transfer */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ + +/* function declarations */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); +/* SMBus type selection */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* dual-address mode switch */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); + +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* enable I2C DMA mode */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); + +/* I2C PEC calculation on or off */ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); +/* I2C whether to transfer PEC value */ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* I2C issue alert through SMBA pin */ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* I2C ARP protocol in SMBus switch */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); + +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); + +#endif /* GD32E10X_I2C_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h new file mode 100644 index 0000000000..1c692733c8 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h @@ -0,0 +1,95 @@ +/*! + \file gd32f10x_misc.h + \brief definitions for the MISC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_MISC_H +#define GD32F10X_MISC_H + +#include "gd32f10x.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(uint8_t nvic_irq); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32F10X_MISC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h new file mode 100644 index 0000000000..3805d75ad5 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h @@ -0,0 +1,129 @@ +/*! + \file gd32f10x_pmu.h + \brief definitions for the PMU + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_PMU_H +#define GD32F10X_PMU_H + +#include "gd32f10x.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ + +/* constants definitions */ +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ + +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* set PMU mode */ +/* PMU work at sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work at deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); +/* PMU work at standby mode */ +void pmu_to_standbymode(uint8_t standbymodecmd); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(void); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(void); + +/* backup related functions */ +/* enable write access to the registers in backup domain */ +void pmu_backup_write_enable(void); +/* disable write access to the registers in backup domain */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag_reset); + +#endif /* GD32F10X_PMU_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h new file mode 100644 index 0000000000..7053c053f4 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h @@ -0,0 +1,924 @@ +/*! + \file gd32f10x_rcu.h + \brief definitions for the RCU + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_RCU_H +#define GD32F10X_RCU_H + +#include "gd32f10x.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ +#elif defined(GD32F10X_CL) +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* bits definitions */ +/* RCU_CTL */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#elif defined(GD32F10X_CL) +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ +#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ +#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ +#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* RCU_CFG0 */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#elif defined(GD32F10X_CL) +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* RCU_INT */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ +#elif defined(GD32F10X_CL) +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ +#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ +#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ +#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ +#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ +#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ +#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ +#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ +#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ +#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ +#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ +#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ +#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ +#ifndef GD32F10X_CL +#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD +#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ +#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ +#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ +#endif /* GD32F10X_XD */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ +#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ +#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ +#ifdef GD32F10X_XD +#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ +#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ +#endif /* GD32F10X_XD */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ +#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ +#ifdef GD32F10X_CL +#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ +#endif /* GD32F10X_CL */ +#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ +#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ +#elif defined(GD32F10X_CL) +#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ +#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ +#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ +#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ +#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ +#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ +#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ +#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ +#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ +#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ +#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ +#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ +#ifndef GD32F10X_CL +#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD +#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ +#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ +#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ +#endif /* GD32F10X_XD */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ +#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ +#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#ifdef GD32F10X_XD +#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ +#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ +#endif /* GD32F10X_XD */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ +#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ +#ifdef GD32F10X_CL +#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ +#endif /* GD32F10X_CL */ +#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +#ifdef GD32F10X_CL +/* RCU_AHBRST */ +#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ +#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ +#endif /* GD32F10X_CL */ + +#if defined(GD32F10X_CL) +/* RCU_CFG1 */ +#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ +#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ +#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ +#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ +#endif /* GD32F10X_CL */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +/* peripherals enable */ +#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ +#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ + +/* peripherals reset */ +#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ +#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ +#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ + +/* configuration register */ +#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ +#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum +{ + /* AHB peripherals */ + RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ + RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ + RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ +#elif defined(GD32F10X_CL) + RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ + RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ + RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ + RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ +#if defined(GD32F10X_XD) + RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ + RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ +#endif /* GD32F10X_XD */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ +#ifdef GD32F10X_CL + RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ +#endif /* GD32F10X_CL */ + RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ + + /* APB2 peripherals */ + RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ + RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ + RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ + RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ +#ifndef GD32F10X_CL + RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD + RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ + RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ + RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ +#endif /* GD32F10X_XD */ +}rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum +{ + /* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ +}rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum +{ + /* AHB peripherals */ +#ifdef GD32F10X_CL + RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ +#endif /* GD32F10X_CL */ + + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ + RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ + RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ +#ifdef GD32F10X_XD + RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ + RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ +#endif /* GD32F10X_XD */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ + RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ +#ifdef GD32F10X_CL + RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ +#endif /* GD32F10X_CL */ + RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ + + /* APB2 peripherals */ + RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ + RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ + RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ + RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ +#ifndef GD32F10X_CL + RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ +#endif /* GD32F10X_CL */ +#ifdef GD32F10X_XD + RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ + RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ + RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ +#endif /* GD32F10X_XD */ +}rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum +{ + /* clock stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ +#ifdef GD32F10X_CL + RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ + RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ +#endif /* GD32F10X_CL */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ + /* reset source flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ +}rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ +#ifdef GD32F10X_CL + RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ + RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ +#endif /* GD32F10X_CL */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ +}rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ +#ifdef GD32F10X_CL + RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ + RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ +#endif /* GD32F10X_CL */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ +}rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum +{ + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ +#ifdef GD32F10X_CL + RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ + RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ +#endif /* GD32F10X_CL */ +}rcu_int_enum; + +/* oscillator types */ +typedef enum +{ + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ + RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ +#ifdef GD32F10X_CL + RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ + RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ +#endif /* GD32F10X_CL */ +}rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum +{ + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ +}rcu_clock_freq_enum; + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC prescaler select */ +#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ +#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ +#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ +#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ +#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ +#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ +#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ + +/* PLL clock multiplication factor */ +#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ + +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ +#elif defined(GD32F10X_CL) +#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ + +/* USBD/USBFS prescaler select */ +#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) +#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ +#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ +#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ +#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */ + +/* CKOUT0 clock source selection */ +#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ +#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ +#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ +#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ +#ifdef GD32F10X_CL +#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ +#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ +#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ +#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ +#endif /* GD32F10X_CL */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ +#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + +/* PREDV0 division factor */ +#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ +#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ +#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ +#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ +#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ +#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ +#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ +#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ +#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ +#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ +#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ +#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ +#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ +#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ +#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ +#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + +/* PREDV1 division factor */ +#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ +#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ +#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ +#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ +#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ +#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ +#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ +#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ +#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ +#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ +#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ +#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ +#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ +#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ +#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ +#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + +/* PLL1 clock multiplication factor */ +#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ +#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ +#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ +#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ +#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ +#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ +#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ +#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ +#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ +#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ + +/* PLL2 clock multiplication factor */ +#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) +#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ +#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ +#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ +#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ +#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ +#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ +#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ +#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ +#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ +#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ + +#ifdef GD32F10X_CL +/* PREDV0 input clock source selection */ +#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ +#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ + +/* I2S1 clock source selection */ +#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ +#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ + +/* I2S2 clock source selection */ +#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ +#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ +#endif /* GD32F10X_CL */ + +/* deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ + +/* function declarations */ +/* initialization, peripheral clock enable/disable functions */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP domain */ +void rcu_bkp_reset_enable(void); +/* disable the BKP domain reset */ +void rcu_bkp_reset_disable(void); + +/* clock configuration functions */ +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT0 clock source and divider */ +void rcu_ckout0_config(uint32_t ckout0_src); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_div); +#elif defined(GD32F10X_CL) +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); +/* configure the PREDV1 division factor */ +void rcu_predv1_config(uint32_t predv1_div); +/* configure the PLL1 clock */ +void rcu_pll1_config(uint32_t pll_mul); +/* configure the PLL2 clock */ +void rcu_pll2_config(uint32_t pll_mul); +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/* peripheral clock configuration functions */ +/* configure the ADC division factor */ +void rcu_adc_clock_config(uint32_t adc_psc); +/* configure the USBD/USBFS prescaler factor */ +void rcu_usb_clock_config(uint32_t usb_psc); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +#ifdef GD32F10X_CL +/* configure the I2S1 clock source selection */ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source); +/* configure the I2S2 clock source selection */ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source); +#endif /* GD32F10X_CL */ + +/* interrupt & flag functions */ +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +/* oscillator configuration functions */ +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +#endif /* GD32F10X_RCU_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h new file mode 100644 index 0000000000..580617014f --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h @@ -0,0 +1,152 @@ +/*! + \file gd32f10x_rtc.h + \brief definitions for the RTC + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_RTC_H +#define GD32F10X_RTC_H + +#include "gd32f10x.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ +#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ +#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ +#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ +#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ +#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ +#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ +#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ +#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ +#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ + +/* bits definitions */ +/* RTC_INTEN */ +#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ +#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ +#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ + +/* RTC_CTL */ +#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ +#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ +#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ +#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ +#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ +#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + +/* RTC_PSCH */ +#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ + +/* RTC_PSCL */ +#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ + +/* RTC_DIVH */ +#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ + +/* RTC_DIVL */ +#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ + +/* RTC_CNTH */ +#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ + +/* RTC_CNTL */ +#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ + +/* RTC_ALRMH */ +#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ + +/* RTC_ALRML */ +#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ + +/* constants definitions */ +/* RTC interrupt enable or disable definitions */ +#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ +#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ +#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ + +/* RTC interrupt flag definitions */ +#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ + +/* RTC flag definitions */ +#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ +#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ + +/* function declarations */ +/* initialization functions */ +/* enter RTC configuration mode */ +void rtc_configuration_mode_enter(void); +/* exit RTC configuration mode */ +void rtc_configuration_mode_exit(void); +/* set RTC counter value */ +void rtc_counter_set(uint32_t cnt); +/* set RTC prescaler value */ +void rtc_prescaler_set(uint32_t psc); + +/* operation functions */ +/* wait RTC last write operation finished flag set */ +void rtc_lwoff_wait(void); +/* wait RTC registers synchronized flag set */ +void rtc_register_sync_wait(void); +/* set RTC alarm value */ +void rtc_alarm_config(uint32_t alarm); +/* get RTC counter value */ +uint32_t rtc_counter_get(void); +/* get RTC divider value */ +uint32_t rtc_divider_get(void); + +/* flag & interrupt functions */ +/* get RTC flag status */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear RTC flag status */ +void rtc_flag_clear(uint32_t flag); +/* get RTC interrupt flag status */ +FlagStatus rtc_interrupt_flag_get(uint32_t flag); +/* clear RTC interrupt flag status */ +void rtc_interrupt_flag_clear(uint32_t flag); +/* enable RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disable RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); + +#endif /* GD32F10X_RTC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h new file mode 100644 index 0000000000..c905e10200 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h @@ -0,0 +1,430 @@ +/*! + \file gd32f10x_sdio.h + \brief definitions for the SDIO + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_SDIO_H +#define GD32F10X_SDIO_H + +#include "gd32f10x.h" + +/* SDIO definitions */ +#define SDIO SDIO_BASE + +/* registers definitions */ +#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ +#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ +#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ +#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ +#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ +#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ +#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ +#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ +#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ +#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ +#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ +#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ +#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ +#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ +#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ +#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ +#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ +#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ + +/* bits definitions */ +/* SDIO_PWRCTL */ +#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ + +/* SDIO_CLKCTL */ +#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ +#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ +#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ +#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ +#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ +#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ + +/* SDIO_CMDAGMT */ +#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ + +/* SDIO_CMDCTL */ +#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ +#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ +#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ +#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ +#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ +#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ +#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ +#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ +#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ + +/* SDIO_DATATO */ +#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ + +/* SDIO_DATALEN */ +#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ + +/* SDIO_DATACTL */ +#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ +#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ +#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ +#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ +#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ +#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ +#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ +#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ +#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ + +/* SDIO_STAT */ +#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ +#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ +#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ +#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ +#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ +#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ +#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ +#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ +#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ +#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ +#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ +#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ +#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ +#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ +#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ +#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ +#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ +#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ +#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ +#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ +#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ +#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ +#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ +#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ + +/* SDIO_INTC */ +#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ +#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ +#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ +#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ +#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ +#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ +#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ +#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ +#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ +#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ +#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ +#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ +#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ + +/* SDIO_INTEN */ +#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ +#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ +#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ +#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ +#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ +#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ +#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ +#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ +#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ +#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ +#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ +#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ +#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ +#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ +#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ +#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ +#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ +#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ +#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ +#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ +#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ +#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ + +/* SDIO_FIFO */ +#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ + +/* constants definitions */ +/* SDIO flags */ +#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ +#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ +#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ +#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ +#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ +#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ +#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ +#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ +#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ +#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ +#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ +#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ +#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ +#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ +#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ +#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ +#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ +#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ +#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ +#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ +#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ +#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ +#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ +#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ + +/* SDIO interrupt enable or disable */ +#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO interrupt flags */ +#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO power control */ +#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ +#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ + +/* SDIO card bus mode control */ +#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ +#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ +#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ + +/* SDIO_CLK clock edge selection */ +#define SDIO_SDIOCLKEDGE_RISING ((uint32_t)0x00000000U)/*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ +#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ + +/* clock bypass enable or disable */ +#define SDIO_CLOCKBYPASS_DISABLE ((uint32_t)0x00000000U)/*!< no bypass */ +#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ + +/* SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000U)/*!< SDIO_CLK clock is always on */ +#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ + +/* SDIO command response type */ +#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ +#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ +#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ + +/* command state machine wait type */ +#define SDIO_WAITTYPE_NO ((uint32_t)0x00000000U)/*!< not wait interrupt */ +#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ +#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ + +#define SDIO_RESPONSE0 ((uint32_t)0x00000000U)/*!< card response[31:0]/card response[127:96] */ +#define SDIO_RESPONSE1 ((uint32_t)0x00000001U)/*!< card response[95:64] */ +#define SDIO_RESPONSE2 ((uint32_t)0x00000002U)/*!< card response[63:32] */ +#define SDIO_RESPONSE3 ((uint32_t)0x00000003U)/*!< card response[31:1], plus bit 0 */ + +/* SDIO data block size */ +#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ +#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ +#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ +#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ +#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ +#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ +#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ +#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ +#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ +#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ +#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ +#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ +#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ +#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ +#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ + +/* SDIO data transfer mode */ +#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000U)/*!< block transfer */ +#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ + +/* SDIO data transfer direction */ +#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000U)/*!< write data to card */ +#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ + +/* SDIO read wait type */ +#define SDIO_READWAITTYPE_DAT2 ((uint32_t)0x00000000U)/*!< read wait control using SDIO_DAT[2] */ +#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ + +/* function declarations */ +/* deinitialize the SDIO */ +void sdio_deinit(void); +/* configure the SDIO clock */ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); +/* enable hardware clock control */ +void sdio_hardware_clock_enable(void); +/* disable hardware clock control */ +void sdio_hardware_clock_disable(void); +/* set different SDIO card bus mode */ +void sdio_bus_mode_set(uint32_t bus_mode); +/* set the SDIO power state */ +void sdio_power_state_set(uint32_t power_state); +/* get the SDIO power state */ +uint32_t sdio_power_state_get(void); +/* enable SDIO_CLK clock output */ +void sdio_clock_enable(void); +/* disable SDIO_CLK clock output */ +void sdio_clock_disable(void); + +/* configure the command index, argument, response type, wait type and CSM to send command */ +/* configure the command and response */ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); +/* set the command state machine wait type */ +void sdio_wait_type_set(uint32_t wait_type); +/* enable the CSM(command state machine) */ +void sdio_csm_enable(void); +/* disable the CSM(command state machine) */ +void sdio_csm_disable(void); +/* get the last response command index */ +uint8_t sdio_command_index_get(void); +/* get the response for the last received command */ +uint32_t sdio_response_get(uint32_t responsex); + +/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ +/* configure the data timeout, data length and data block size */ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); +/* configure the data transfer mode and direction */ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); +/* enable the DSM(data state machine) for data transfer */ +void sdio_dsm_enable(void); +/* disable the DSM(data state machine) */ +void sdio_dsm_disable(void); +/* write data(one word) to the transmit FIFO */ +void sdio_data_write(uint32_t data); +/* read data(one word) from the receive FIFO */ +uint32_t sdio_data_read(void); +/* get the number of remaining data bytes to be transferred to card */ +uint32_t sdio_data_counter_get(void); +/* get the number of words remaining to be written or read from FIFO */ +uint32_t sdio_fifo_counter_get(void); +/* enable the DMA request for SDIO */ +void sdio_dma_enable(void); +/* disable the DMA request for SDIO */ +void sdio_dma_disable(void); + +/* get the flags state of SDIO */ +FlagStatus sdio_flag_get(uint32_t flag); +/* clear the pending flags of SDIO */ +void sdio_flag_clear(uint32_t flag); +/* enable the SDIO interrupt */ +void sdio_interrupt_enable(uint32_t int_flag); +/* disable the SDIO interrupt */ +void sdio_interrupt_disable(uint32_t int_flag); +/* get the interrupt flags state of SDIO */ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); +/* clear the interrupt pending flags of SDIO */ +void sdio_interrupt_flag_clear(uint32_t int_flag); + +/* enable the read wait mode(SD I/O only) */ +void sdio_readwait_enable(void); +/* disable the read wait mode(SD I/O only) */ +void sdio_readwait_disable(void); +/* enable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_enable(void); +/* disable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_disable(void); +/* set the read wait type(SD I/O only) */ +void sdio_readwait_type_set(uint32_t readwait_type); +/* enable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_enable(void); +/* disable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_disable(void); +/* enable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_enable(void); +/* disable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_disable(void); + +/* enable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_enable(void); +/* disable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_disable(void); +/* enable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_enable(void); +/* disable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_disable(void); +/* enable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_enable(void); +/* disable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_disable(void); + +#endif /* GD32F10X_SDIO_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h new file mode 100644 index 0000000000..0cd8c26786 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h @@ -0,0 +1,328 @@ +/*! + \file gd32f10x_spi.h + \brief definitions for the SPI + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_SPI_H +#define GD32F10X_SPI_H + +#include "gd32f10x.h" + +/* SPIx(x=0,1,2) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define SPI2 (SPI_BASE + 0x00000400U) + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial value */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC value */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC value */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct +{ + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +}spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ + +/* function declarations */ +/* SPI/I2S deinitialization and initialization functions */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI struct with the default values */ +void spi_struct_para_init(spi_parameter_struct* spi_struct); +/* initialize SPI parameter */ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph,uint32_t mode, uint32_t standard, uint32_t ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* NSS functions */ +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* DMA communication */ +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma); + +/* normal mode communication */ +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); + +/* flag and interrupt functions */ +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +#endif /* GD32F10X_SPI_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h new file mode 100644 index 0000000000..01af9b655c --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h @@ -0,0 +1,730 @@ +/*! + \file gd32f10x_timer.h + \brief definitions for the TIMER + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_TIMER_H +#define GD32F10X_TIMER_H + +#include "gd32f10x.h" + +/* TIMERx(x=0..13) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER3 (TIMER_BASE + 0x00000800U) +#define TIMER4 (TIMER_BASE + 0x00000C00U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER6 (TIMER_BASE + 0x00001400U) +#define TIMER7 (TIMER_BASE + 0x00013400U) +#define TIMER8 (TIMER_BASE + 0x00014C00U) +#define TIMER9 (TIMER_BASE + 0x00015000U) +#define TIMER10 (TIMER_BASE + 0x00015400U) +#define TIMER11 (TIMER_BASE + 0x00001800U) +#define TIMER12 (TIMER_BASE + 0x00001C00U) +#define TIMER13 (TIMER_BASE + 0x00002000U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* constants definitions */ +/* TIMER init parameter struct definitions */ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint32_t period; /*!< period value */ + uint16_t clockdivision; /*!< clock division value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint16_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ +#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ +#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ +#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ +#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ +#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ +#define TIMER_INT_FLAG_BRK TIMER_INT_BRK + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ + +/* channel enable state */ +#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ + +/* channel complementary output enable state */ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< frozen mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< set the channel output */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< clear the channel output */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle on match */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* timer input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ + +/* TIMERx(x=0..4,7..13) write CHxVAL register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* function declarations */ +/* TIMER timebase */ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint32_t update); + +/* timer DMA and event */ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); + +/* TIMER interrupt and flag */ +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER flag */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flag */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); + +#endif /* GD32E10X_TIMER_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h new file mode 100644 index 0000000000..b0af23732f --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h @@ -0,0 +1,378 @@ +/*! + \file gd32f10x_usart.h + \brief definitions for the USART + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.1, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_USART_H +#define GD32F10X_USART_H + +#include "gd32f10x.h" + +/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ +#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */ +#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */ +#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */ +#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */ + +/* registers definitions */ +#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ +#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ + +/* bits definitions */ +/* USARTx_STAT */ +#define USART_STAT_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT_TC BIT(6) /*!< transmission complete */ +#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ + +/* USARTx_DATA */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ + +/* USARTx_CTL0 */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< USART enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) + +/* register offset */ +#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ +#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ + +/* USART flags */ +typedef enum +{ + /* flags in STAT register */ + USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ +}usart_flag_enum; + +/* USART interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ +}usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ +}usart_interrupt_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ + +/* USART CK length */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART DMA request for receive configure */ +#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ + +/* USART DMA request for transmission configure */ +#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ + +/* USART RTS configure */ +#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ + +/* USART CTS configure */ +#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); + +/* USART normal mode communication */ +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* LIN mode enable */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* LIN mode disable */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); +/* send break frame */ +void usart_send_break(uint32_t usart_periph); + +/* half-duplex communication */ +/* half-duplex enable */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* half-duplex disable */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* clock enable */ +void usart_synchronous_clock_enable(uint32_t usart_periph); +/* clock disable */ +void usart_synchronous_clock_disable(uint32_t usart_periph); +/* configure usart synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* guard time value configure in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut); +/* smartcard mode enable */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* smartcard mode disable */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* NACK enable in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* NACK disable in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler */ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); + +/* flag functions */ +/* get flag in STAT register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); + +/* interrupt functions */ +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); +/* clear interrupt flag in STAT register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); +#endif /* GD32F10X_USART_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h new file mode 100644 index 0000000000..c548139baa --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h @@ -0,0 +1,90 @@ +/*! + \file gd32f10x_wwdgt.h + \brief definitions for the WWDGT + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_WWDGT_H +#define GD32F10X_WWDGT_H + +#include "gd32f10x.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); + +#endif /* GD32F10X_WWDGT_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c new file mode 100644 index 0000000000..ab628288bf --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c @@ -0,0 +1,933 @@ +/*! + \file gd32f10x_adc.c + \brief ADC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_adc.h" + +/* discontinuous mode macro*/ +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) + +/* ADC regular channel macro */ +#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) + +/* ADC sampling time macro */ +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) + +/* ADC inserted channel macro */ +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) + +/* ADC inserted channel offset macro */ +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) + +/*! + \brief reset ADC + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_deinit(uint32_t adc_periph) +{ + switch(adc_periph){ + case ADC0: + /* reset ADC0 */ + rcu_periph_reset_enable(RCU_ADC0RST); + rcu_periph_reset_disable(RCU_ADC0RST); + break; + case ADC1: + /* reset ADC1 */ + rcu_periph_reset_enable(RCU_ADC1RST); + rcu_periph_reset_disable(RCU_ADC1RST); + break; +#ifndef GD32F10X_CL + case ADC2: + rcu_periph_reset_enable(RCU_ADC2RST); + rcu_periph_reset_disable(RCU_ADC2RST); + break; +#endif /* GD32F10X_CL */ + default: + break; + } +} + +/*! + \brief configure the ADC sync mode + \param[in] mode: ADC mode + only one parameter can be selected which is shown as below: + \arg ADC_MODE_FREE: all the ADCs work independently + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only + \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only + \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only + \param[out] none + \retval none +*/ +void adc_mode_config(uint32_t mode) +{ + ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); + ADC_CTL0(ADC0) |= mode; +} + +/*! + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (function & ADC_SCAN_MODE)){ + /* enable scan mode */ + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* enable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* enable continuous mode */ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + }else{ + if(0U != (function & ADC_SCAN_MODE)){ + /* disable scan mode */ + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* disable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* disable continuous mode */ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment){ + /* MSB alignment */ + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + }else{ + /* LSB alignment */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + /* enable ADC */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + /* disable ADC */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC1 calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + } +} + +/*! + \brief enable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_enable(void) +{ + /* enable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; +} + +/*! + \brief disable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_disable(void) +{ + /* disable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + /* enable DMA request */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + /* disable DMA request */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel, the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) +{ + /* disable discontinuous mode of regular & inserted channel */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* config the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + /* enable regular channel group discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + /* enable inserted channel group discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + /* disable discontinuous mode of regular & inserted channel */ + default: + break; + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure the length of regular channel group */ + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + break; + case ADC_INSERTED_CHANNEL: + /* configure the length of inserted channel group */ + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint32_t rsq,sampt; + + /* ADC regular sequence config */ + if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ + /* the regular group sequence rank is smaller than six */ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); + ADC_RSQ2(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ + /* the regular group sequence rank is smaller than twelve */ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); + ADC_RSQ1(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ + /* the regular group sequence rank is smaller than sixteen */ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); + ADC_RSQ0(adc_periph) = rsq; + }else{ + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the regular group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the regular group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq,sampt; + /* get inserted channel group length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); + ADC_ISQ(adc_periph) = isq; + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the inserted group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the inserted group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] inserted_channel: insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset: the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); + + if(num <= ADC_OFFSET_LENGTH){ + /* calculate the offset of the register */ + num = num * ADC_OFFSET_SHIFT_LENGTH; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief configure ADC external trigger source + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected + for regular channel: + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select + \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 + \arg ADC2_EXTTRIG_REGULAR_T2_CH0: TIMER2 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T1_CH2: TIMER1 CH2 event select + \arg ADC2_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC2_EXTTRIG_REGULAR_T7_CH0: TIMER7 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH0: TIMER4 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH2: TIMER4 CH2 event select + \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select + \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T3_CH2: TIMER3 CH2 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH1: TIMER7 CH1 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: TIMER4 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T4_CH3: TIMER4 CH3 event select + \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure ADC regular group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief configure ADC external trigger + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected which are shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* enable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* enable ADC inserted channel group external trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; + } + }else{ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* disable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* disable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; + } + } +} + +/*! + \brief enable ADC software trigger + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected which are shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* enable ADC regular channel group software trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* enable ADC inserted channel group software trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted group data register + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] inserted_channel: insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel){ + case ADC_INSERTED_CHANNEL_0: + /* read the data of channel 0 */ + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + /* read the data of channel 1 */ + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + /* read the data of channel 2 */ + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + /* read the data of channel 3 */ + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief read the last ADC0 and ADC1 conversion result data in sync mode + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint32_t adc_sync_mode_convert_value_read(void) +{ + /* return conversion value */ + return ADC_RDATA(ADC0); +} + + +/*! + \brief configure ADC analog watchdog single channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); + /* analog watchdog channel select */ + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); + /* select the group */ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* regular channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + /* inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + /* regular and inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] adc_periph: ADCx, x=0,1,2 + \param[out] none + \retval none +*/ +void adc_watchdog_disable(uint32_t adc_periph) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] low_threshold: analog watchdog low threshold, 0..4095 + \param[in] high_threshold: analog watchdog high threshold, 0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) +{ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief get the ADC flag bits + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) +{ + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & adc_flag){ + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag bits + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_flag: the adc flag bits + one or more parameters can be selected which are shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); +} + +/*! + \brief get the bit state of ADCx software start conversion + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){ + reval = SET; + } + return reval; +} + +/*! + \brief get the bit state of ADCx software inserted channel start conversion + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){ + reval = SET; + } + return reval; +} + +/*! + \brief get the ADC interrupt bits + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_interrupt: the adc interrupt bits + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(adc_interrupt){ + case ADC_INT_FLAG_WDE: + /* get the ADC analog watchdog interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + /* get the ADC end of group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + /* get the ADC end of inserted group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear the ADC flag + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_interrupt: the adc status flag + one or more parameters can be selected which are shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); +} + +/*! + \brief enable ADC interrupt + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_interrupt: the adc interrupt + one or more parameters can be selected which are shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + /* enable ADC analog watchdog interrupt */ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; + } + /* enable ADC end of group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + } + /* enable ADC end of inserted group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOIC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; + } +} + +/*! + \brief disable ADC interrupt + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_interrupt: the adc interrupt flag + one or more parameters can be selected which are shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + /* disable ADC analog watchdog interrupt */ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; + } + /* disable ADC end of group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; + } + /* disable ADC end of inserted group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOIC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; + } +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c new file mode 100644 index 0000000000..69e0c6a93b --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c @@ -0,0 +1,296 @@ +/*! + \file gd32f10x_bkp.c + \brief BKP driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_bkp.h" + +/* BKP register bits offset */ +#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U) + +/*! + \brief reset BKP registers + \param[in] none + \param[out] none + \retval none +*/ +void bkp_deinit(void) +{ + /* reset BKP domain register*/ + rcu_bkp_reset_enable(); + rcu_bkp_reset_disable(); +} + +/*! + \brief write BKP data register + \param[in] register_number: refer to bkp_data_register_enum + only one parameter can be selected which is shown as below: + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[in] data: the data to be write in BKP data register + \param[out] none + \retval none +*/ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) +{ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + BKP_DATA10_41(register_number - 1U) = data; + }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + BKP_DATA0_9(register_number - 1U) = data; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief read BKP data register + \param[in] register_number: refer to bkp_data_register_enum + only one parameter can be selected which is shown as below: + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[out] none + \retval data of BKP data register +*/ +uint16_t bkp_data_read(bkp_data_register_enum register_number) +{ + uint16_t data = 0U; + + /* get the data from the BKP data register */ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + data = BKP_DATA10_41(register_number - 1U); + }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + data = BKP_DATA0_9(register_number - 1U); + }else{ + /* illegal parameters */ + } + return data; +} + +/*! + \brief enable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; +} + +/*! + \brief disable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; +} + +/*! + \brief enable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; +} + +/*! + \brief disable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; +} + +/*! + \brief select RTC output + \param[in] outputsel: RTC output selection + only one parameter can be selected which is shown as below: + \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output + \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output + \param[out] none + \retval none +*/ +void bkp_rtc_output_select(uint16_t outputsel) +{ + uint16_t ctl = 0U; + + /* configure BKP_OCTL_ROSEL with outputsel */ + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_ROSEL; + ctl |= outputsel; + BKP_OCTL = ctl; +} + +/*! + \brief set RTC clock calibration value + \param[in] value: RTC clock calibration value + \arg 0x00 - 0x7F + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_value_set(uint8_t value) +{ + uint16_t ctl; + + /* configure BKP_OCTL_RCCV with value */ + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_RCCV; + ctl |= (uint16_t)OCTL_RCCV(value); + BKP_OCTL = ctl; +} + +/*! + \brief enable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_enable(void) +{ + BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; +} + +/*! + \brief disable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_disable(void) +{ + BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; +} + +/*! + \brief set tamper pin active level + \param[in] level: tamper active level + only one parameter can be selected which is shown as below: + \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high + \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low + \param[out] none + \retval none +*/ +void bkp_tamper_active_level_set(uint16_t level) +{ + uint16_t ctl = 0U; + + /* configure BKP_TPCTL_TPAL with level */ + ctl = BKP_TPCTL; + ctl &= (uint16_t)~BKP_TPCTL_TPAL; + ctl |= level; + BKP_TPCTL = ctl; +} + +/*! + \brief enable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_enable(void) +{ + BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; +} + +/*! + \brief disable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_disable(void) +{ + BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; +} + +/*! + \brief get tamper flag state + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_flag_get(void) +{ + if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear tamper flag state + \param[in] none + \param[out] none + \retval none +*/ +void bkp_flag_clear(void) +{ + BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); +} + +/*! + \brief get tamper interrupt flag state + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_interrupt_flag_get(void) +{ + if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear tamper interrupt flag state + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_flag_clear(void) +{ + BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c new file mode 100644 index 0000000000..95ca2dd050 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c @@ -0,0 +1,993 @@ +/*! + \file gd32f10x_can.c + \brief CAN driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_can.h" + +#define CAN_ERROR_HANDLE(s) do{}while(1) + +/*! + \brief deinitialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_deinit(uint32_t can_periph) +{ +#ifdef GD32F10x_CL + if(CAN0 == can_periph){ + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + }else{ + rcu_periph_reset_enable(RCU_CAN1RST); + rcu_periph_reset_disable(RCU_CAN1RST); + } +#else + if(CAN0 == can_periph){ + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + } +#endif +} + +/*! + \brief initialize CAN parameter struct with a default value + \param[in] type: the type of CAN parameter struct + only one parameter can be selected which is shown as below: + \arg CAN_INIT_STRUCT: the CAN initial struct + \arg CAN_FILTER_STRUCT: the CAN filter struct + \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct + \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct + \param[in] p_struct: the pointer of the specific struct + \param[out] none + \retval none +*/ +void can_struct_para_init(can_struct_type_enum type, void* p_struct) +{ + uint8_t i; + + /* get type of the struct */ + switch(type){ + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE; + ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; + ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct*)p_struct)->rx_efid = 0U; + ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct*)p_struct)->rx_fi = 0U; + ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); + } +} + +/*! + \brief initialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0000 - 0x03FF + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) +{ + uint32_t timeout = CAN_TIMEOUT; + ErrStatus flag = ERROR; + + /* disable sleep mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + /* enable initialize mode */ + CAN_CTL(can_periph) |= CAN_CTL_IWMOD; + /* wait ACK */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + /* check initialize working success */ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = ERROR; + }else{ + /* set the bit timing register */ + CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ + BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ + BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ + BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ + BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + + /* time trigger communication mode */ + if(ENABLE == can_parameter_init->time_triggered){ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + } + /* automatic bus-off managment */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery){ + CAN_CTL(can_periph) |= CAN_CTL_ABOR; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; + } + /* automatic wakeup mode */ + if(ENABLE == can_parameter_init->auto_wake_up){ + CAN_CTL(can_periph) |= CAN_CTL_AWU; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_AWU; + } + /* automatic retransmission mode disable*/ + if(ENABLE == can_parameter_init->auto_retrans){ + CAN_CTL(can_periph) |= CAN_CTL_ARD; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } + /* receive fifo overwrite mode */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite){ + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } + /* transmit fifo order */ + if(ENABLE == can_parameter_init->trans_fifo_order){ + CAN_CTL(can_periph) |= CAN_CTL_TFO; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_TFO; + } + /* disable initialize mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; + timeout = CAN_TIMEOUT; + /* wait the ACK */ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + /* check exit initialize mode */ + if(0U != timeout){ + flag = SUCCESS; + } + } + return flag; +} + +/*! + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) +{ + uint32_t val = 0U; + + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* disable filter */ + CAN_FW(CAN0) &= ~(uint32_t)val; + + /* filter 16 bits */ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ + /* set filter 16 bits */ + CAN_FSCFG(CAN0) &= ~(uint32_t)val; + /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + } + /* filter 32 bits */ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ + /* set filter 32 bits */ + CAN_FSCFG(CAN0) |= (uint32_t)val; + /* 32 bits list or first 32 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* 32 bits mask or second 32 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + } + + /* filter mode */ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ + /* mask mode */ + CAN_FMCFG(CAN0) &= ~(uint32_t)val; + }else{ + /* list mode */ + CAN_FMCFG(CAN0) |= (uint32_t)val; + } + + /* filter FIFO */ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ + /* FIFO0 */ + CAN_FAFIFO(CAN0) &= ~(uint32_t)val; + }else{ + /* FIFO1 */ + CAN_FAFIFO(CAN0) |= (uint32_t)val; + } + + /* filter working */ + if(ENABLE == can_filter_parameter_init->filter_enable){ + + CAN_FW(CAN0) |= (uint32_t)val; + } + + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief set CAN1 fliter start bank number + \param[in] start_bank: CAN1 start bank number + only one parameter can be selected which is shown as below: + \arg (1..27) + \param[out] none + \retval none +*/ +void can1_filter_start_bank(uint8_t start_bank) +{ + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* set CAN1 filter start number */ + CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; + CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); + /* filter lock enaable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief enable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_debug_freeze_enable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; +#ifdef GD32F10x_CL + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + }else{ + dbg_periph_enable(DBG_CAN1_HOLD); + } +#else + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + } +#endif +} + +/*! + \brief disable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_debug_freeze_disable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; +#ifdef GD32F10x_CL + if(CAN0 == can_periph){ + dbg_periph_disable(DBG_CAN0_HOLD); + }else{ + dbg_periph_disable(DBG_CAN1_HOLD); + } +#else + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + } +#endif +} + +/*! + \brief enable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_time_trigger_mode_enable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* enable the tcc mode */ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + /* enable time stamp */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; + } +} + +/*! + \brief disable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval none +*/ +void can_time_trigger_mode_disable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* disable the TCC mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + /* reset TSEN bits */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; + } +} + +/*! + \brief transmit CAN message + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlenc: 1 - 7 + \arg tx_data[]: 0x00 - 0xFF + \param[out] none + \retval mailbox_number +*/ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) +{ + uint8_t mailbox_number = CAN_MAILBOX0; + + /* select one empty mailbox */ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ + mailbox_number = CAN_MAILBOX0; + }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ + mailbox_number = CAN_MAILBOX1; + }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ + mailbox_number = CAN_MAILBOX2; + }else{ + mailbox_number = CAN_NOMAILBOX; + } + /* return no mailbox empty */ + if(CAN_NOMAILBOX == mailbox_number){ + return CAN_NOMAILBOX; + } + + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; + if(CAN_FF_STANDARD == transmit_message->tx_ff){ + /* set transmit mailbox standard identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ + transmit_message->tx_ft); + }else{ + /* set transmit mailbox extended identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ + transmit_message->tx_ff | \ + transmit_message->tx_ft); + } + /* set the data length */ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; + CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; + /* set the data */ + CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); + CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); + /* enable transmission */ + CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; + + return mailbox_number; +} + +/*! + \brief get CAN transmit state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOX(x=0,1,2) + \param[out] none + \retval can_transmit_state_enum +*/ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) +{ + can_transmit_state_enum state = CAN_TRANSMIT_FAILED; + uint32_t val = 0U; + + /* check selected mailbox state */ + switch(mailbox_number){ + /* mailbox0 */ + case CAN_MAILBOX0: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); + break; + /* mailbox1 */ + case CAN_MAILBOX1: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); + break; + /* mailbox2 */ + case CAN_MAILBOX2: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); + break; + default: + val = CAN_TRANSMIT_FAILED; + break; + } + + switch(val){ + /* transmit pending */ + case (CAN_STATE_PENDING): + state = CAN_TRANSMIT_PENDING; + break; + /* mailbox0 transmit succeeded */ + case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + state = CAN_TRANSMIT_OK; + break; + /* mailbox1 transmit succeeded */ + case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + state = CAN_TRANSMIT_OK; + break; + /* mailbox2 transmit succeeded */ + case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + state = CAN_TRANSMIT_OK; + break; + /* transmit failed */ + default: + state = CAN_TRANSMIT_FAILED; + break; + } + return state; +} + +/*! + \brief stop CAN transmission + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOXx(x=0,1,2) + \param[out] none + \retval none +*/ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) +{ + if(CAN_MAILBOX0 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + } + }else if(CAN_MAILBOX1 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + } + }else if(CAN_MAILBOX2 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + } + }else{ + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlenc: 1 - 7 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 + \retval none +*/ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) +{ + /* get the frame format */ + receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); + if(CAN_FF_STANDARD == receive_message->rx_ff){ + /* get standard identifier */ + receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + }else{ + /* get extended identifier */ + receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + } + + /* get frame type */ + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); + /* filtering index */ + receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + /* get recevie data length */ + receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + + /* receive data */ + receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + + /* release FIFO */ + if(CAN_FIFO0 == fifo_number){ + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + }else{ + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } +} + +/*! + \brief release FIFO0 + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval none +*/ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) +{ + if(CAN_FIFO0 == fifo_number){ + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + }else if(CAN_FIFO1 == fifo_number){ + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + }else{ + /* illegal parameters */ + CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); + } +} + +/*! + \brief CAN receive message length + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval message length +*/ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) +{ + uint8_t val = 0U; + + if(CAN_FIFO0 == fifo_number){ + /* FIFO0 */ + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + }else if(CAN_FIFO1 == fifo_number){ + /* FIFO1 */ + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); + }else{ + /* illegal parameters */ + } + return val; +} + +/*! + \brief set CAN working mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] can_working_mode + only one parameter can be selected which is shown as below: + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) +{ + ErrStatus flag = ERROR; + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + + if(CAN_MODE_INITIALIZE == working_mode){ + /* disable sleep mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); + /* set initialize mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; + /* wait the acknowledge */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else if(CAN_MODE_NORMAL == working_mode){ + /* enter normal mode */ + CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); + /* wait the acknowledge */ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ + timeout--; + } + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else if(CAN_MODE_SLEEP == working_mode){ + /* disable initialize mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); + /* set sleep mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; + /* wait the acknowledge */ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ + timeout--; + } + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else{ + flag = ERROR; + } + return flag; +} + +/*! + \brief wake up CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_wakeup(uint32_t can_periph) +{ + ErrStatus flag = ERROR; + uint32_t timeout = CAN_TIMEOUT; + + /* wakeup */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ + timeout--; + } + /* check state */ + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + return flag; +} + +/*! + \brief get CAN error type + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval can_error_enum + \arg CAN_ERROR_NONE: no error + \arg CAN_ERROR_FILL: fill error + \arg CAN_ERROR_FORMATE: format error + \arg CAN_ERROR_ACK: ACK error + \arg CAN_ERROR_BITRECESSIVE: bit recessive + \arg CAN_ERROR_BITDOMINANTER: bit dominant error + \arg CAN_ERROR_CRC: CRC error + \arg CAN_ERROR_SOFTWARECFG: software configure +*/ +can_error_enum can_error_get(uint32_t can_periph) +{ + can_error_enum error; + error = CAN_ERROR_NONE; + + /* get error type */ + error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); + return error; +} + +/*! + \brief get CAN receive error number + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval error number +*/ +uint8_t can_receive_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + /* get error count */ + val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief get CAN transmit error number + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[out] none + \retval error number +*/ +uint8_t can_transmit_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + +/*! + \brief get CAN flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +{ + /* get flag and interrupt enable state */ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CAN flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \param[out] none + \retval none +*/ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag) +{ + CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); +} + +/*! + \brief get CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag))); + if(ret1 && ret2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval none +*/ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag)); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c new file mode 100644 index 0000000000..0173e9f507 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c @@ -0,0 +1,131 @@ +/*! + \file gd32f10x_crc.c + \brief CRC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_crc.h" + +#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) +#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_DATA = CRC_DATA_RESET_VALUE; + CRC_FDATA = CRC_FDATA_RESET_VALUE; + CRC_CTL = (uint32_t)CRC_CTL_RST; +} + +/*! + \brief reset data register to the value of initializaiton data register + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the value of the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the value of the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write data to the free data register + \param[in] free_data: specify 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief calculate the CRC value of a 32-bit data + \param[in] sdata: specified 32-bit data + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_single_data_calculate(uint32_t sdata) +{ + CRC_DATA = sdata; + return (CRC_DATA); +} + +/*! + \brief calculate the CRC value of an array of 32-bit values + \param[in] array: pointer to an array of 32-bit values + \param[in] size: size of the array + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) +{ + uint32_t index; + for(index = 0U; index < size; index++){ + CRC_DATA = array[index]; + } + return (CRC_DATA); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c new file mode 100644 index 0000000000..b5114a2739 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c @@ -0,0 +1,559 @@ +/*! + \file gd32f10x_dac.c + \brief DAC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_dac.h" + +/* DAC register bit offset */ +#define DAC1_REG_OFFSET ((uint32_t)16U) +#define DH_12BIT_OFFSET ((uint32_t)16U) +#define DH_8BIT_OFFSET ((uint32_t)8U) + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DEN0; + }else{ + DAC_CTL |= DAC_CTL_DEN1; + } +} + +/*! + \brief disable DAC + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DEN1; + } +} + +/*! + \brief enable DAC DMA function + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_dma_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DDMAEN0; + }else{ + DAC_CTL |= DAC_CTL_DDMAEN1; + } +} + +/*! + \brief disable DAC DMA function + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_dma_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DDMAEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DDMAEN1; + } +} + +/*! + \brief enable DAC output buffer + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DBOFF0; + }else{ + DAC_CTL &= ~DAC_CTL_DBOFF1; + } +} + +/*! + \brief disable DAC output buffer + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DBOFF0; + }else{ + DAC_CTL |= DAC_CTL_DBOFF1; + } +} + +/*! + \brief get DAC output value + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(uint32_t dac_periph) +{ + uint16_t data = 0U; + if(DAC0 == dac_periph){ + /* store the DAC0 output value */ + data = (uint16_t)DAC0_DO; + }else{ + /* store the DAC1 output value */ + data = (uint16_t)DAC1_DO; + } + return data; +} + +/*! + \brief set the DAC specified data holding register value + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] dac_align + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +{ + if(DAC0 == dac_periph){ + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } + }else{ + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } + } +} + +/*! + \brief enable DAC trigger + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DTEN0; + }else{ + DAC_CTL |= DAC_CTL_DTEN1; + } +} + +/*! + \brief disable DAC trigger + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DTEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DTEN1; + } +} + +/*! + \brief set DAC trigger source + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] triggersource: external triggers of DAC + only one parameter can be selected which is shown as below: + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F10X_CL) + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO + \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F10X_MD and GD32F10X_HD and GD32F10X_XD) + \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL0; + DAC_CTL |= triggersource; + }else{ + /* configure DAC1 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL1; + DAC_CTL |= (triggersource << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC software trigger + \param[in] dac_periph + \arg DACx(x=0,1) + \retval none +*/ +void dac_software_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT |= DAC_SWT_SWTR0; + }else{ + DAC_SWT |= DAC_SWT_SWTR1; + } +} + +/*! + \brief disable DAC software trigger + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT &= ~DAC_SWT_SWTR0; + }else{ + DAC_SWT &= ~DAC_SWT_SWTR1; + } +} + +/*! + \brief configure DAC wave mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] wave_mode + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM0; + DAC_CTL |= wave_mode; + }else{ + /* configure DAC1 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM1; + DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC wave bit width + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] bit_width + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= bit_width; + }else{ + /* configure DAC1 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (bit_width << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] unmask_bits + only one parameter can be selected which is shown as below: + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= unmask_bits; + }else{ + /* configure DAC1 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC triangle noise mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] amplitude + only one parameter can be selected which is shown as below: + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= amplitude; + }else{ + /* configure DAC1 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (amplitude << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL &= (~ctl); +} + +/*! + \brief enable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_enable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT |= (swt); +} + +/*! + \brief disable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_disable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT &= (~swt); +} + +/*! + \brief enable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL &= (~ctl); +} + +/*! + \brief disable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL |= (ctl); +} + +/*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c new file mode 100644 index 0000000000..f8b74c727f --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c @@ -0,0 +1,153 @@ +/*! + \file gd32f10x_dbg.c + \brief DBG driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_dbg.h" + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + one or more parameters can be selected which are shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_CTL |= (uint32_t)dbg_periph; +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + one or more parameters can be selected which are shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD and CL series): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_CTL &= ~(uint32_t)dbg_periph; +} + +/*! + \brief enable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_enable(void) +{ + DBG_CTL |= DBG_CTL_TRACE_IOEN; +} + +/*! + \brief disable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_disable(void) +{ + DBG_CTL &= ~DBG_CTL_TRACE_IOEN; +} + +/*! + \brief trace pin mode selection + \param[in] trace_mode: + only one parameter can be selected which is shown as below: + \arg TRACE_MODE_ASYNC: trace pin used for async mode + \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 + \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 + \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 + \param[out] none + \retval none +*/ +void dbg_trace_pin_mode_set(uint32_t trace_mode) +{ + DBG_CTL &= ~DBG_CTL_TRACE_MODE; + DBG_CTL |= trace_mode; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c new file mode 100644 index 0000000000..801d69130d --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c @@ -0,0 +1,737 @@ +/*! + \file gd32f10x_dma.c + \brief DMA driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_dma.h" + +#define DMA_WRONG_HANDLE while(1){} + + /* check whether peripheral matches channels or not */ +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); + +/*! + \brief deinitialize DMA a channel registers + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is deinitialized + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* disable DMA a channel */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize the parameters of DMA struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_struct_para_init(dma_parameter_struct* init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; + init_struct->number = 0U; + init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width,memory transfer width, */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + }else{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + }else{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + }else{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHPADDR(dma_periph, channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set memory base address + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHMADDR(dma_periph, channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] number: the number of remaining data to be transferred by the DMA + \arg 0x0000-0xFFFF + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + return (uint32_t)DMA_CHCNT(dma_periph, channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] priority: priority Level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] mwidth: transfer data width of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] pwidth: transfer data width of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + if(DMA_PERIPHERAL_TO_MEMORY == direction){ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + /* check whether the flag is set or not */ + if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ + reval = SET; + }else{ + reval = RESET; + } + + return reval; +} + +/*! + \brief clear the flag of a DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch(flag){ + case DMA_INT_FLAG_FTF: + /* check whether the full transfer finish interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + /* check whether the half transfer finish interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + /* check whether the error interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + default: + DMA_WRONG_HANDLE + } + + /* when the interrupt flag is set and enabled, return SET */ + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to enbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to disbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~source; +} + +/*! + \brief check whether peripheral and channels match + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) +{ + ErrStatus val = SUCCESS; + + if(DMA1 == dma_periph){ + /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ + if(channelx > DMA_CH4){ + val = ERROR; + } + } + + return val; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c new file mode 100644 index 0000000000..e614de1670 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c @@ -0,0 +1,3074 @@ +/*! + \file gd32f10x_enet.c + \brief ENET driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_enet.h" + +#ifdef GD32F10X_CL + +#if defined (__CC_ARM) /*!< ARM compiler */ +__align(4) +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +__align(4) +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +__align(4) +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +__align(4) +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined ( __ICCARM__ ) /*!< IAR compiler */ +#pragma data_alignment=4 +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +#pragma data_alignment=4 +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +#pragma data_alignment=4 +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +#pragma data_alignment=4 +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#endif /* __CC_ARM */ + +/* global transmit and receive descriptors pointers */ +enet_descriptors_struct *dma_current_txdesc; +enet_descriptors_struct *dma_current_rxdesc; + +/* structure pointer of ptp descriptor for normal mode */ +enet_descriptors_struct *dma_current_ptp_txdesc = NULL; +enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; + +/* init structure parameters for ENET initialization */ +static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + +static uint32_t enet_unknow_err = 0U; + +/* array of register offset for debug information get */ +static const uint16_t enet_reg_tab[] = { +0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C, +0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, + +0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + +0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, + +0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C, +0x1050, 0x1054}; + + +/*! + \brief deinitialize the ENET, and reset structure parameters for ENET initialization + \param[in] none + \param[out] none + \retval none +*/ +void enet_deinit(void) +{ + rcu_periph_reset_enable(RCU_ENETRST); + rcu_periph_reset_disable(RCU_ENETRST); + enet_initpara_reset(); +} + +/*! + \brief configure the parameters which are usually less cared for initialization + note -- this function must be called before enet_init(), otherwise + configuration will be no effect + \param[in] option: different function option, which is related to several parameters, + only one parameter can be selected which is shown as below, refer to enet_option_enum + \arg FORWARD_OPTION: choose to configure the frame forward related parameters + \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters + \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters + \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters + \arg STORE_OPTION: choose to configure the store forward mode related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg VLAN_OPTION: choose to configure vlan related parameters + \arg FLOWCTL_OPTION: choose to configure flow control related parameters + \arg HASHH_OPTION: choose to configure hash high + \arg HASHL_OPTION: choose to configure hash low + \arg FILTER_OPTION: choose to configure frame filter related parameters + \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters + \arg TIMER_OPTION: choose to configure time counter related parameters + \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters + \param[in] para: the related parameters according to the option + all the related parameters should be configured which are shown as below + FORWARD_OPTION related parameters: + - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; + - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; + - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . + DMABUS_OPTION related parameters: + - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; + - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; + DMA_MAXBURST_OPTION related parameters: + - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ + ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ + ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ + ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ + ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; + - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ + ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ + ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ + ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ + ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; + - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; + DMA_ARBITRATION_OPTION related parameters: + - ENET_ARBITRATION_RXPRIORTX / ENET_ARBITRATION_RXTX_1_1 + / ENET_ARBITRATION_RXTX_2_1/ ENET_ARBITRATION_RXTX_3_1 + / ENET_ARBITRATION_RXTX_4_1. + STORE_OPTION related parameters: + - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; + - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; + - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ + ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; + - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ + ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ + ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ + ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . + DMA_OPTION related parameters: + - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; + - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE . + VLAN_OPTION related parameters: + - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; + - MAC_VLT_VLTI(regval) . + FLOWCTL_OPTION related parameters: + - MAC_FCTL_PTM(regval) ; + - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; + - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; + - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; + - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . + HASHH_OPTION related parameters: + - 0x0~0xFFFF FFFFU + HASHL_OPTION related parameters: + - 0x0~0xFFFF FFFFU + FILTER_OPTION related parameters: + - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ + ENET_SRC_FILTER_DISABLE ; + - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; + - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ + ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; + - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ + ENET_UNICAST_FILTER_PERFECT ; + - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ + ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . + HALFDUPLEX_OPTION related parameters: + - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; + - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; + - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; + - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ + ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; + - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . + TIMER_OPTION related parameters: + - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; + - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; + INTERFRAMEGAP_OPTION related parameters: + - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ + ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ + ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ + ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . + \param[out] none + \retval none +*/ +void enet_initpara_config(enet_option_enum option, uint32_t para) +{ + switch(option){ + case FORWARD_OPTION: + /* choose to configure forward_frame, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; + enet_initpara.forward_frame = para; + break; + case DMABUS_OPTION: + /* choose to configure dmabus_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; + enet_initpara.dmabus_mode = para; + break; + case DMA_MAXBURST_OPTION: + /* choose to configure dma_maxburst, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; + enet_initpara.dma_maxburst = para; + break; + case DMA_ARBITRATION_OPTION: + /* choose to configure dma_arbitration, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; + enet_initpara.dma_arbitration = para; + break; + case STORE_OPTION: + /* choose to configure store_forward_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)STORE_OPTION; + enet_initpara.store_forward_mode = para; + break; + case DMA_OPTION: + /* choose to configure dma_function, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_OPTION; + enet_initpara.dma_function = para; + break; + case VLAN_OPTION: + /* choose to configure vlan_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; + enet_initpara.vlan_config = para; + break; + case FLOWCTL_OPTION: + /* choose to configure flow_control, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; + enet_initpara.flow_control = para; + break; + case HASHH_OPTION: + /* choose to configure hashtable_high, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; + enet_initpara.hashtable_high = para; + break; + case HASHL_OPTION: + /* choose to configure hashtable_low, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; + enet_initpara.hashtable_low = para; + break; + case FILTER_OPTION: + /* choose to configure framesfilter_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; + enet_initpara.framesfilter_mode = para; + break; + case HALFDUPLEX_OPTION: + /* choose to configure halfduplex_param, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; + enet_initpara.halfduplex_param = para; + break; + case TIMER_OPTION: + /* choose to configure timer_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; + enet_initpara.timer_config = para; + break; + case INTERFRAMEGAP_OPTION: + /* choose to configure interframegap, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; + enet_initpara.interframegap = para; + break; + default: + break; + } +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters and the less cared + parameters + \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected + which is shown as below, refer to enet_mediamode_enum + \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation + \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex + \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex + \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex + \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex + \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII + \param[in] checksum: IP frame checksum offload function, only one parameter can be selected + which is shown as below, refer to enet_mediamode_enum + \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function + \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function + \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped + \param[in] recept: frame filter function, only one parameter can be selected + which is shown as below, refer to enet_frmrecept_enum + \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled + \arg ENET_RECEIVEALL: all received frame are forwarded to application + \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames + \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) +{ + uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; + uint32_t media_temp = 0U; + uint32_t timeout = 0U; + uint16_t phy_value = 0U; + ErrStatus phy_state= ERROR, enet_state = ERROR; + + /* PHY interface configuration, configure SMI clock and reset PHY chip */ + if(ERROR == enet_phy_config()){ + _ENET_DELAY_(PHY_RESETDELAY); + if(ERROR == enet_phy_config()){ + return enet_state; + } + } + /* initialize ENET peripheral with generally concerned parameters */ + enet_default_init(); + + /* 1st, configure mediamode */ + media_temp = (uint32_t)mediamode; + /* if is PHY auto negotiation */ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ + /* wait for PHY_LINKED_STATUS bit be set */ + do{ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_LINKED_STATUS; + timeout++; + }while((RESET == phy_value) && (timeout < PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout){ + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* enable auto-negotiation */ + phy_value = PHY_AUTONEGOTIATION; + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state){ + /* return ERROR due to write timeout */ + return enet_state; + } + + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ + do{ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_AUTONEGO_COMPLETE; + timeout++; + }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout){ + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* read the result of the auto-negotiation */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + /* configure the duplex mode of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ + media_temp = ENET_MODE_FULLDUPLEX; + }else{ + media_temp = ENET_MODE_HALFDUPLEX; + } + /* configure the communication speed of MAC following the auto-negotiation result */ + if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ + media_temp |= ENET_SPEEDMODE_10M; + }else{ + media_temp |= ENET_SPEEDMODE_100M; + } + }else{ + phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); + phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state){ + /* return ERROR due to write timeout */ + return enet_state; + } + /* PHY configuration need some time */ + _ENET_DELAY_(PHY_CONFIGDELAY); + } + /* after configuring the PHY, use mediamode to configure registers */ + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); + reg_value |= media_temp; + ENET_MAC_CFG = reg_value; + + + /* 2st, configure checksum */ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ + ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~ENET_DMA_CTL_DTCERFD; + reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); + ENET_DMA_CTL = reg_value; + } + + /* 3rd, configure recept */ + ENET_MAC_FRMF |= (uint32_t)recept; + + /* 4th, configure different function options */ + /* configure forward_frame related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ + reg_temp = enet_initpara.forward_frame; + + reg_value = ENET_MAC_CFG; + temp = reg_temp; + /* configure ENET_MAC_CFG register */ + reg_value &= (~ENET_MAC_CFG_APCD); + temp &= ENET_MAC_CFG_APCD; + reg_value |= temp; + ENET_MAC_CFG = reg_value; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); + reg_value |= (temp >> 2); + ENET_DMA_CTL = reg_value; + } + + /* configure dmabus_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ + temp = enet_initpara.dmabus_mode; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ + |ENET_DMA_BCTL_FPBL); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_maxburst related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ + temp = enet_initpara.dma_maxburst; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_arbitration related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ + temp = enet_initpara.dma_arbitration; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure store_forward_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ + temp = enet_initpara.store_forward_mode; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + } + + /* configure dma_function related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ + reg_temp = enet_initpara.dma_function; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); + reg_value |= reg_temp; + ENET_DMA_CTL = reg_value; + } + + /* configure vlan_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ + reg_temp = enet_initpara.vlan_config; + + reg_value = ENET_MAC_VLT; + /* configure ENET_MAC_VLT register */ + reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); + reg_value |= reg_temp; + ENET_MAC_VLT = reg_value; + } + + /* configure flow_control related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ + reg_temp = enet_initpara.flow_control; + + reg_value = ENET_MAC_FCTL; + temp = reg_temp; + /* configure ENET_MAC_FCTL register */ + reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + reg_value |= temp; + ENET_MAC_FCTL = reg_value; + + reg_value = ENET_MAC_FCTH; + temp = reg_temp; + /* configure ENET_MAC_FCTH register */ + reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); + reg_value |= (temp >> 8); + ENET_MAC_FCTH = reg_value; + } + + /* configure hashtable_high related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ + ENET_MAC_HLH = enet_initpara.hashtable_high; + } + + /* configure hashtable_low related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ + ENET_MAC_HLL = enet_initpara.hashtable_low; + } + + /* configure framesfilter_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ + reg_temp = enet_initpara.framesfilter_mode; + + reg_value = ENET_MAC_FRMF; + /* configure ENET_MAC_FRMF register */ + reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + reg_value |= reg_temp; + ENET_MAC_FRMF = reg_value; + } + + /* configure halfduplex_param related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ + reg_temp = enet_initpara.halfduplex_param; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure timer_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ + reg_temp = enet_initpara.timer_config; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure interframegap related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ + reg_temp = enet_initpara.interframegap; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~ENET_MAC_CFG_IGBS; + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + enet_state = SUCCESS; + return enet_state; +} + +/*! + \brief reset all core internal registers located in CLK_TX and CLK_RX + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_software_reset(void) +{ + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + uint32_t dma_flag; + + /* reset all core internal registers located in CLK_TX and CLK_RX */ + ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; + + /* wait for reset operation complete */ + do{ + dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); + timeout++; + }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + + /* reset operation complete */ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief check receive frame valid and return frame size + \param[in] none + \param[out] none + \retval size of received frame: 0x0 - 0x3FFF +*/ +uint32_t enet_rxframe_size_get(void) +{ + uint32_t size = 0U; + uint32_t status; + + /* get rdes0 information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + + /* if the desciptor is owned by DMA */ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ + return 0U; + } + + /* if has any error, or the frame uses two or more descriptors */ + if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } + + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } + + /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ + if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ + /* get the size of the received data including CRC */ + size = GET_RDES0_FRML(status); + /* substract the CRC size */ + size = size - 4U; + }else{ + enet_unknow_err++; + enet_rxframe_drop(); + + return 1U; + } + + /* return packet size */ + return size; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode */ + desc_status = ENET_TDES0_TCHM; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num=0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)){ + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + }else{ + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num=0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)){ + if (ENET_DMA_TX == direction){ + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + }else{ + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief handle current received frame data to application buffer + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the received frame data + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + return ERROR; + } + + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer){ + /* if no error occurs, and the frame uses only one descriptor */ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status); + size = size - 4U; + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize){ + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offsetbuffer1_addr) + offset)); + } + + }else{ + /* return ERROR */ + return ERROR; + } + } + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief handle application buffer data to transmit it + \param[in] buffer: pointer to the frame data to be transmitted, + note -- if the input is NULL, user should handle the data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) +{ + uint32_t offset = 0U; + uint32_t dma_tbu_flag, dma_tu_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer){ + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++){ + (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief configure the transmit IP frame checksum offload calculation and insertion + \param[in] desc: the descriptor pointer which users want to configure + \param[in] checksum: IP frame checksum configuration + only one parameter can be selected which is shown as below + \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled + \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled + \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header + \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated + \param[out] none + \retval none +*/ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) +{ + desc->status &= ~ENET_TDES0_CM; + desc->status |= checksum; +} + +/*! + \brief ENET Tx and Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_enable(void) +{ + enet_tx_enable(); + enet_rx_enable(); +} + +/*! + \brief ENET Tx and Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_disable(void) +{ + enet_tx_disable(); + enet_rx_disable(); +} + +/*! + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: set MAC address 0 filter + \arg ENET_MAC_ADDRESS1: set MAC address 1 filter + \arg ENET_MAC_ADDRESS2: set MAC address 2 filter + \arg ENET_MAC_ADDRESS3: set MAC address 3 filter + \param[in] paddr: the buffer pointer which stores the MAC address + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \param[out] none + \retval none +*/ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); + REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); +} + +/*! + \brief get MAC address + \param[in] mac_addr: select which MAC address will be get, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: get MAC address 0 filter + \arg ENET_MAC_ADDRESS1: get MAC address 1 filter + \arg ENET_MAC_ADDRESS2: get MAC address 2 filter + \arg ENET_MAC_ADDRESS3: get MAC address 3 filter + \param[out] paddr: the buffer pointer which is stored the MAC address + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \retval none +*/ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); + paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); + paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); + paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); + paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); + paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); +} + +/*! + \brief get the ENET MAC/MSC/PTP/DMA status flag + \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, + only one parameter can be selected which is shown as below + \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_WUM: WUM status flag + \arg ENET_MAC_FLAG_MSC: MSC status flag + \arg ENET_MAC_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag + \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag + \arg ENET_PTP_FLAG_TTM: target time match flag + \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_FLAG_TS: transmit status flag + \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_FLAG_RO: receive overflow status flag + \arg ENET_DMA_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_FLAG_RS: receive status flag + \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_FLAG_ET: early transmit status flag + \arg ENET_DMA_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_FLAG_ER: early receive status flag + \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag + \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag + \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag + \arg ENET_DMA_FLAG_MSC: MSC status flag + \arg ENET_DMA_FLAG_WUM: WUM status flag + \arg ENET_DMA_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_flag_get(enet_flag_enum enet_flag) +{ + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the ENET DMA status flag + \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear + \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear + \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear + \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear + \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear + \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear + \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear + \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear + \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear + \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear + \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear + \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear + \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear + \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear + \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear + \param[out] none + \retval none +*/ +void enet_flag_clear(enet_flag_clear_enum enet_flag) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); +} + +/*! + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_enable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + }else{ + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_disable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + }else{ + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_FLAG_WUM: WUM status flag + \arg ENET_MAC_INT_FLAG_MSC: MSC status flag + \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag + \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_INT_FLAG_TS: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS: receive status flag + \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER: early receive status flag + \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_INT_FLAG_MSC: MSC status flag + \arg ENET_DMA_INT_FLAG_WUM: WUM status flag + \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) +{ + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag + \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag + \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag + \param[out] none + \retval none +*/ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); +} + +/*! + \brief ENET Tx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_TEN; + enet_txfifo_flush(); + ENET_DMA_CTL |= ENET_DMA_CTL_STE; +} + +/*! + \brief ENET Tx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; + enet_txfifo_flush(); + ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; +} + +/*! + \brief ENET Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_REN; + ENET_DMA_CTL |= ENET_DMA_CTL_SRE; +} + +/*! + \brief ENET Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; + ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; +} + +/*! + \brief put registers value into the application buffer + \param[in] type: register type which will be get, refer to enet_registers_type_enum, + only one parameter can be selected which is shown as below + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT + \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL + \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR + \param[in] num: the number of registers that the user want to get + \param[out] preg: the application buffer pointer for storing the register value + \retval none +*/ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) +{ + uint32_t offset = 0U, max = 0U, limit = 0U; + + offset = (uint32_t)type; + max = (uint32_t)type + num; + limit = sizeof(enet_reg_tab)/sizeof(uint16_t); + + /* prevent element in this array is out of range */ + if(max > limit){ + max = limit; + } + + for(; offset < max; offset++){ + /* get value of the corresponding register */ + *preg = REG32((ENET) + enet_reg_tab[offset]); + preg++; + } +} + +/*! + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable + \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_enable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief disable the MAC address filter + \param[in] mac_addr: select which MAC address will be disable, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_disable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief configure the MAC address filter + \param[in] mac_addr: select which MAC address will be configured, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter + \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter + \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter + \param[in] addr_mask: select which MAC address bytes will be mask, + one or more parameters can be selected which are shown as below + \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits + \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits + \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits + \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits + \param[in] filter_type: select which MAC address filter type will be selected, + only one parameter can be selected which is shown as below + \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame + \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame + \param[out] none + \retval none +*/ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) +{ + uint32_t reg; + + /* get the address filter register value which is to be configured */ + reg = REG32(ENET_ADDRH_BASE + mac_addr); + + /* clear and configure the address filter register */ + reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); + reg |= (addr_mask | filter_type); + REG32(ENET_ADDRH_BASE + mac_addr) = reg; +} + +/*! + \brief PHY interface configuration (configure SMI clock and reset PHY chip) + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_config(void) +{ + uint32_t ahbclk; + uint32_t reg; + uint16_t phy_value; + ErrStatus enet_state = ERROR; + + /* clear the previous MDC clock */ + reg = ENET_MAC_PHY_CTL; + reg &= ~ENET_MAC_PHY_CTL_CLR; + + /* get the HCLK frequency */ + ahbclk = rcu_clock_freq_get(CK_AHB); + + /* configure MDC clock according to HCLK frequency range */ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ + reg |= ENET_MDC_HCLK_DIV16; + }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ + reg |= ENET_MDC_HCLK_DIV26; + }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){ + reg |= ENET_MDC_HCLK_DIV42; + }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){ + reg |= ENET_MDC_HCLK_DIV62; + }else{ + return enet_state; + } + ENET_MAC_PHY_CTL = reg; + + /* reset PHY */ + phy_value = PHY_RESET; + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + return enet_state; + } + /* PHY reset need some time */ + _ENET_DELAY_(ENET_DELAY_TO); + + /* check whether PHY reset is complete */ + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + return enet_state; + } + + /* PHY reset complete */ + if(RESET == (phy_value & PHY_RESET)){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief write to / read from a PHY register + \param[in] direction: only one parameter can be selected which is shown as below + \arg ENET_PHY_WRITE: write data to phy register + \arg ENET_PHY_READ: read data from phy register + \param[in] phy_address: 0x0 - 0x1F + \param[in] phy_reg: 0x0 - 0x1F + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) +{ + uint32_t reg, phy_flag; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* configure ENET_MAC_PHY_CTL with write/read operation */ + reg = ENET_MAC_PHY_CTL; + reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + + /* if do the write operation, write value to the register */ + if(ENET_PHY_WRITE == direction){ + ENET_MAC_PHY_DATA = *pvalue; + } + + /* do PHY write/read operation, and wait the operation complete */ + ENET_MAC_PHY_CTL = reg; + do{ + phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); + timeout++; + } + while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + + /* write/read operation complete */ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ + enet_state = SUCCESS; + } + + /* if do the read operation, get value from the register */ + if(ENET_PHY_READ == direction){ + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + } + + return enet_state; +} + +/*! + \brief enable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_enable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* enable the PHY loopback mode */ + temp_phy |= PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief disable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_disable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* disable the PHY loopback mode */ + temp_phy &= (uint16_t)~PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief enable ENET forward feature + \param[in] feature: the feature of ENET forward mode, + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames + \param[out] none + \retval none +*/ +void enet_forward_feature_enable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG |= mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); + ENET_DMA_CTL |= (mask >> 2); +} + +/*! + \brief disable ENET forward feature + \param[in] feature: the feature of ENET forward mode, + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function + \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_forward_feature_disable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG &= ~mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); + ENET_DMA_CTL &= ~(mask >> 2); +} + +/*! + \brief enable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode, + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_enable(uint32_t feature) +{ + ENET_MAC_FRMF |= feature; +} + +/*! + \brief disable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode, + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_disable(uint32_t feature) +{ + ENET_MAC_FRMF &= ~feature; +} + +/*! + \brief generate the pause frame, ENET will send pause frame after enable transmit flow control + this function only use in full-dulex mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_pauseframe_generate(void) +{ + ErrStatus enet_state =ERROR; + uint32_t temp = 0U; + + /* in full-duplex mode, must make sure this bit is 0 before writing register */ + temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; + if(RESET == temp){ + ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; + enet_state = SUCCESS; + } + return enet_state; +} + +/*! + \brief configure the pause frame detect type + \param[in] detect: pause frame detect type, + only one parameter can be selected which is shown as below + \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also + use the MAC0 address to detecting pause frame + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + in IEEE802.3 can be detected + \param[out] none + \retval none +*/ +void enet_pauseframe_detect_config(uint32_t detect) +{ + ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; + ENET_MAC_FCTL |= detect; +} + +/*! + \brief configure the pause frame parameters + \param[in] pausetime: pause time in transmit pause control frame + \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, + this value must make sure to be less than configured pause time, only one parameter can be + selected which is shown as below + \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times + \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times + \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times + \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times + \param[out] none + \retval none +*/ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) +{ + ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); + ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); +} + +/*! + \brief configure the threshold of the flow control(deactive and active threshold) + \param[in] deactive: the threshold of the deactive flow control, this value + should always be less than active flow control value, only one + parameter can be selected which is shown as below + \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[in] active: the threshold of the active flow control, only one parameter + can be selected which is shown as below + \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[out] none + \retval none +*/ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) +{ + ENET_MAC_FCTH = ((deactive | active) >> 8); +} + +/*! + \brief enable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_enable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL |= feature; +} + +/*! + \brief disable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_disable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL &= ~feature; +} + +/*! + \brief get the dma transmit/receive process state + \param[in] direction: choose the direction of dma process which users want to check, + refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: dma transmit process + \arg ENET_DMA_RX: dma receive process + \param[out] none + \retval state of dma process, the value range shows below: + ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, + ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, + ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, + ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING +*/ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) +{ + uint32_t reval; + reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); + return reval; +} + +/*! + \brief poll the DMA transmission/reception enable by writing any value to the + ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception + \param[in] direction: choose the direction of DMA process which users want to resume, + refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA transmit process + \arg ENET_DMA_RX: DMA receive process + \param[out] none + \retval none +*/ +void enet_dmaprocess_resume(enet_dmadirection_enum direction) +{ + if(ENET_DMA_TX == direction){ + ENET_DMA_TPEN = 0U; + }else{ + ENET_DMA_RPEN = 0U; + } +} + +/*! + \brief check and recover the Rx process + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxprocess_check_recovery(void) +{ + uint32_t status; + + /* get DAV information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + status &= ENET_RDES0_DAV; + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with + receive descriptor address pointer updated by RxDMA controller */ + if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && + (ENET_RDES0_DAV == status)){ + dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; + } +} + +/*! + \brief flush the ENET transmit FIFO, and wait until the flush operation completes + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_txfifo_flush(void) +{ + uint32_t flush_state; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* set the FTF bit for flushing transmit FIFO */ + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + /* wait until the flush operation completes */ + do{ + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + timeout++; + }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(RESET == flush_state){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table + \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, + only one parameter can be selected which is shown as below + \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table + \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by + the RxDMA controller + \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller + \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table + \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by + the TxDMA controller + \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller + \param[out] none + \retval address value +*/ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) +{ + uint32_t reval = 0U; + + reval = REG32((ENET) +(uint32_t)addr_get); + return reval; +} + +/*! + \brief get the Tx or Rx descriptor information + \param[in] desc: the descriptor pointer which users want to get information + \param[in] info_get: the descriptor information type which is selected, + only one parameter can be selected which is shown as below + \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size + \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size + \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer + \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted + \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame + \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame + \param[out] none + \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter +*/ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch(info_get){ + case RXDESC_BUFFER_1_SIZE: + reval = GET_RDES1_RB1S(desc->control_buffer_size); + break; + case RXDESC_BUFFER_2_SIZE: + reval = GET_RDES1_RB2S(desc->control_buffer_size); + break; + case RXDESC_FRAME_LENGTH: + reval = GET_RDES0_FRML(desc->status); + if(reval > 4U){ + reval = reval - 4U; + }else{ + reval = 0U; + } + break; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_COLLISION_COUNT: + reval = GET_TDES0_COCNT(desc->status); + break; + default: + break; + } + return reval; +} + +/*! + \brief get the number of missed frames during receiving + \param[in] none + \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO + \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller + \retval none +*/ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) +{ + uint32_t temp_counter = 0U; + + temp_counter = ENET_DMA_MFBOCNT; + *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); + *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); +} + +/*! + \brief get the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_UFE: underflow error + \arg ENET_TDES0_EXD: excessive deferral + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_ECO: excessive collision + \arg ENET_TDES0_LCO: late collision + \arg ENET_TDES0_NCA: no carrier + \arg ENET_TDES0_LCA: loss of carrier + \arg ENET_TDES0_IPPE: IP payload error + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_JT: jabber timeout + \arg ENET_TDES0_ES: error summary + \arg ENET_TDES0_IPHE: IP header error + \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + + \arg ENET_RDES0_PCERR: payload checksum error + \arg ENET_RDES0_CERR: CRC error + \arg ENET_RDES0_DBERR: dribble bit error + \arg ENET_RDES0_RERR: receive error + \arg ENET_RDES0_RWDT: receive watchdog timeout + \arg ENET_RDES0_FRMT: frame type + \arg ENET_RDES0_LCO: late collision + \arg ENET_RDES0_IPHERR: IP frame header error + \arg ENET_RDES0_LDES: last descriptor + \arg ENET_RDES0_FDES: first descriptor + \arg ENET_RDES0_VTAG: VLAN tag + \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_LERR: length error + \arg ENET_RDES0_SAFF: SA filter fail + \arg ENET_RDES0_DERR: descriptor error + \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_DAFF: destination address filter fail + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + FlagStatus enet_flag = RESET; + + if ((uint32_t)RESET != (desc->status & desc_flag)){ + enet_flag = SET; + } + + return enet_flag; +} + +/*! + \brief set the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to set flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status |= desc_flag; +} + +/*! + \brief clear the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to clear flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status &= ~desc_flag; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will set + \param[in] desc: the descriptor pointer which users want to configure + \param[out] none + \retval none +*/ +void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc) +{ + desc->control_buffer_size &= ~ENET_RDES1_DINTC; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will not set + \param[in] desc: the descriptor pointer which users want to configure + \param[out] none + \retval none +*/ +void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc) +{ + desc->control_buffer_size |= ENET_RDES1_DINTC; +} + +/*! + \brief drop current receive frame + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxframe_drop(void) +{ + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + if(NULL != dma_current_ptp_rxdesc){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + }else{ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + } + + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc){ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + } + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc){ + dma_current_ptp_rxdesc++; + } + } + } +} + +/*! + \brief enable DMA feature + \param[in] feature: the feature of DMA mode, + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_enable(uint32_t feature) +{ + ENET_DMA_CTL |= feature; +} + +/*! + \brief disable DMA feature + \param[in] feature: the feature of DMA mode, + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_disable(uint32_t feature) +{ + ENET_DMA_CTL &= ~feature; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)){ + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + }else{ + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive ring mode and set buffer1 size */ + desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)){ + if (ENET_DMA_TX == direction){ + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + }else{ + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] timestamp: pointer to the table which stores the timestamp high and low + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer){ + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize){ + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++){ + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); + } + + }else{ + return ERROR; + } + } + /* copy timestamp value from Rx descriptor to application array */ + timestamp[0] = dma_current_rxdesc->buffer1_addr; + timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; + + dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; + dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with RxDMA descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_rxdesc ++; + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0U, timeout = 0U; + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer){ + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++){ + (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp){ + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do{ + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->buffer1_addr; + timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; + } + dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; + dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_txdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_txdesc++; + } + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with TxDMA descriptor */ + dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; + } + } + return SUCCESS; +} + +/*! + \brief wakeup frame filter register pointer reset + \param[in] none + \param[out] none + \retval none +*/ +void enet_wum_filter_register_pointer_reset(void) +{ + ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; +} + +/*! + \brief set the remote wakeup frame registers + \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) + \param[out] none + \retval none +*/ +void enet_wum_filter_config(uint32_t pdata[]) +{ + uint32_t num = 0U; + + /* configure ENET_MAC_RWFF register */ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ + ENET_MAC_RWFF = pdata[num]; + } +} + +/*! + \brief enable wakeup management features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_WUM_POWER_DOWN: power down mode + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_enable(uint32_t feature) +{ + ENET_MAC_WUM |= feature; +} + +/*! + \brief disable wakeup management features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_disable(uint32_t feature) +{ + ENET_MAC_WUM &= (~feature); +} + +/*! + \brief reset the MAC statistics counters + \param[in] none + \param[out] none + \retval none +*/ +void enet_msc_counters_reset(void) +{ + /* reset all counters */ + ENET_MSC_CTL |= ENET_MSC_CTL_CTR; +} + +/*! + \brief enable the MAC statistics counter features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_enable(uint32_t feature) +{ + ENET_MSC_CTL |= feature; +} + +/*! + \brief disable the MAC statistics counter features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_disable(uint32_t feature) +{ + ENET_MSC_CTL &= (~feature); +} + +/*! + \brief get MAC statistics counter + \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, + only one parameter can be selected which is shown as below + \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter + \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter + \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter + \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter + \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter + \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter + \param[out] none + \retval the MSC counter value +*/ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) +{ + uint32_t reval; + + reval = REG32((ENET + (uint32_t)counter)); + + return reval; +} + +/*! + \brief change subsecond to nanosecond + \param[in] subsecond: subsecond value + \param[out] none + \retval the nanosecond value +*/ +uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) +{ + uint64_t val = subsecond * 1000000000Ull; + val >>= 31; + return (uint32_t)val; +} + +/*! + \brief change nanosecond to subsecond + \param[in] nanosecond: nanosecond value + \param[out] none + \retval the subsecond value +*/ +uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond) +{ + uint64_t val = nanosecond * 0x80000000Ull; + val /= 1000000000U; + return (uint32_t)val; +} + +/*! + \brief enable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \param[out] none + \retval none +*/ +void enet_ptp_feature_enable(uint32_t feature) +{ + ENET_PTP_TSCTL |= feature; +} + +/*! + \brief disable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \param[out] none + \retval none +*/ +void enet_ptp_feature_disable(uint32_t feature) +{ + ENET_PTP_TSCTL &= ~feature; +} + +/*! + \brief configure the PTP timestamp function + \param[in] func: only one parameter can be selected which is shown as below + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating + \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ + +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) +{ + uint32_t temp_config = 0U, temp_state = 0U; + uint32_t timeout = 0U; + ErrStatus enet_state = SUCCESS; + + switch(func){ + case ENET_PTP_ADDEND_UPDATE: + /* this bit must be read as zero before application set it */ + do{ + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; + } + break; + case ENET_PTP_SYSTIME_UPDATE: + /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ + do{ + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; + } + break; + case ENET_PTP_SYSTIME_INIT: + /* this bit must be read as zero before application set it */ + do{ + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; + } + break; + default: + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))){ + ENET_PTP_TSCTL |= temp_config; + }else{ + ENET_PTP_TSCTL &= ~temp_config; + } + break; + } + + return enet_state; +} + +/*! + \brief configure system time subsecond increment value + \param[in] subsecond: the value will be added to the subsecond value of system time, + this value must be between 0 and 0xFF + \param[out] none + \retval none +*/ +void enet_ptp_subsecond_increment_config(uint32_t subsecond) +{ + ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); +} + +/*! + \brief adjusting the clock frequency only in fine update mode + \param[in] add: the value will be added to the accumulator register to achieve time synchronization + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_addend_config(uint32_t add) +{ + ENET_PTP_TSADDEND = add; +} + +/*! + \brief initialize or add/subtract to second of the system time + \param[in] sign: timestamp update positive or negative sign, + only one parameter can be selected which is shown as below + \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time + \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time + \param[in] second: initializing or adding/subtracting to second of the system time + \param[in] subsecond: the current subsecond of the system time + with 0.46 ns accuracy if required accuracy is 20 ns + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) +{ + ENET_PTP_TSUH = second; + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); +} + +/*! + \brief configure the expected target time + \param[in] second: the expected target second time + \param[in] nanosecond: the expected target nanosecond time (signed) + \param[out] none + \retval none +*/ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) +{ + ENET_PTP_ETH = second; + ENET_PTP_ETL = nanosecond; +} + +/*! + \brief get the current system time + \param[in] none + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \retval none +*/ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) +{ + uint32_t temp_sec = 0U, temp_subs = 0U; + + /* get the value of sysytem time registers */ + temp_sec = (uint32_t)ENET_PTP_TSH; + temp_subs = (uint32_t)ENET_PTP_TSL; + + /* get sysytem time and construct the enet_ptp_systime_struct structure */ + systime_struct->second = temp_sec; + systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); + systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); + systime_struct->sign = GET_PTP_TSL_STS(temp_subs); +} + +/*! + \brief configure and start PTP timestamp counter + \param[in] updatemethod: method for updating + \arg ENET_PTP_FINEMODE: fine correction method + \arg ENET_PTP_COARSEMODE: coarse correction method + \param[in] init_sec: second value for initializing system time + \param[in] init_subsec: subsecond value for initializing system time + \param[in] carry_cfg: the value to be added to the accumulator register (in fine method is used) + \param[in] accuracy_cfg: the value to be added to the subsecond value of system time + \param[out] none + \retval none +*/ +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg) +{ + /* mask the timestamp trigger interrupt */ + enet_interrupt_disable(ENET_MAC_INT_TMSTIM); + + /* enable timestamp */ + enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP); + + /* configure system time subsecond increment based on the PTP clock frequency */ + enet_ptp_subsecond_increment_config(accuracy_cfg); + + if(ENET_PTP_FINEMODE == updatemethod){ + /* fine correction method: configure the timestamp addend, then update */ + enet_ptp_timestamp_addend_config(carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); + /* wait until update is completed */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){ + } + } + + /* choose the fine correction method */ + enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod); + + /* initialize the system time */ + enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); +} + +/*! + \brief adjust frequency in fine method by configure addend register + \param[in] carry_cfg: the value to be added to the accumulator register + \param[out] none + \retval none +*/ +void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg) +{ + /* re-configure the timestamp addend, then update */ + enet_ptp_timestamp_addend_config((uint32_t)carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +/*! + \brief update system time in coarse method + \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \param[out] none + \retval none +*/ +void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct) +{ + uint32_t subsecond_val; + uint32_t carry_cfg; + + subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); + + /* save the carry_cfg value */ + carry_cfg = ENET_PTP_TSADDEND_TMSA; + + /* update the system time */ + enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); + + /* wait until the update is completed */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){ + } + + /* write back the carry_cfg value, then update */ + enet_ptp_timestamp_addend_config(carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +/*! + \brief set system time in fine method + \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \param[out] none + \retval none +*/ +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) +{ + uint32_t subsecond_val; + + subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); + + /* initialize the system time */ + enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); + + /* wait until the system time initialzation finished */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){ + } +} + +/*! + \brief get the ptp flag status + \param[in] flag: ptp flag status to be checked + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_ptp_flag_get(uint32_t flag) +{ + FlagStatus bitstatus = RESET; + + if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){ + bitstatus = SET; + } + + return bitstatus; +} + +/*! + \brief reset the ENET initpara struct, call it before using enet_initpara_config() + \param[in] none + \param[out] none + \retval none +*/ +void enet_initpara_reset(void) +{ + enet_initpara.option_enable = 0U; + enet_initpara.forward_frame = 0U; + enet_initpara.dmabus_mode = 0U; + enet_initpara.dma_maxburst = 0U; + enet_initpara.dma_arbitration = 0U; + enet_initpara.store_forward_mode = 0U; + enet_initpara.dma_function = 0U; + enet_initpara.vlan_config = 0U; + enet_initpara.flow_control = 0U; + enet_initpara.hashtable_high = 0U; + enet_initpara.hashtable_low = 0U; + enet_initpara.framesfilter_mode = 0U; + enet_initpara.halfduplex_param = 0U; + enet_initpara.timer_config = 0U; + enet_initpara.interframegap = 0U; +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \param[in] none + \param[out] none + \retval none +*/ +static void enet_default_init(void) +{ + uint32_t reg_value = 0U; + + /* MAC */ + /* configure ENET_MAC_CFG register */ + reg_value = ENET_MAC_CFG; + reg_value &= MAC_CFG_MASK; + reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ + | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; + ENET_MAC_CFG = reg_value; + + /* configure ENET_MAC_FRMF register */ + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ + |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ + |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ + |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; + + /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ + ENET_MAC_HLH = 0x0U; + + ENET_MAC_HLL = 0x0U; + + /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ + reg_value = ENET_MAC_FCTL; + reg_value &= MAC_FCTL_MASK; + reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ + |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ + |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; + ENET_MAC_FCTL = reg_value; + + ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; + + /* configure ENET_MAC_VLT register */ + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); + + /* DMA */ + /* configure ENET_DMA_CTL register */ + reg_value = ENET_DMA_CTL; + reg_value &= DMA_CTL_MASK; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ + |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ + |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ + |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ + |ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; + + /* configure ENET_DMA_BCTL register */ + reg_value = ENET_DMA_BCTL; + reg_value &= DMA_BCTL_MASK; + reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ + |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ + |ENET_FIXED_BURST_ENABLE; + ENET_DMA_BCTL = reg_value; +} + +#ifndef USE_DELAY +/*! + \brief insert a delay time + \param[in] ncount: specifies the delay time length + \param[out] none + \param[out] none +*/ +static void enet_delay(uint32_t ncount) +{ + uint32_t delay_time = 0U; + + for(delay_time = ncount; delay_time != 0U; delay_time--){ + } +} +#endif /* USE_DELAY */ + +#endif /* GD32F10X_CL */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c new file mode 100644 index 0000000000..641e716ca1 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c @@ -0,0 +1,646 @@ +/*! + \file gd32f10x_exmc.c + \brief EXMC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_exmc.h" + +/* EXMC bank0 register reset value */ +#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DBU) +#define BANK0_SNCTL1_2_3_REGION_RESET ((uint32_t)0x000030D2U) +#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) +#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) + +/* EXMC bank1/2 register reset mask*/ +#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) +#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) + +/* EXMC bank3 register reset mask*/ +#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) +#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) + +/* EXMC register bit offset */ +#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) +#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) +#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) +#define SNCTL_WREN_OFFSET ((uint32_t)12U) +#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) +#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) +#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) + +#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) +#define SNTCFG_DSET_OFFSET ((uint32_t)8U) +#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) + +#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U) +#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U) +#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U) + +#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) +#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) + +#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) +#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) +#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) + +#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) +#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) +#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) + +#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) +#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) +#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) + +#define INTEN_INTS_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize EXMC NOR/SRAM region + \param[in] norsram_region: select the region of bank0 + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_deinit(uint32_t norsram_region) +{ + /* reset the registers */ + if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){ + EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET; + }else{ + EXMC_SNCTL(norsram_region) = BANK0_SNCTL1_2_3_REGION_RESET; + } + + EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET; + EXMC_SNWTCFG(norsram_region) = BANK0_SNWTCFG_RESET; +} + +/*! + \brief initialize EXMC NOR/SRAM region + \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter + norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 + write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE + extended_mode: ENABLE or DISABLE + asyn_wait: ENABLE or DISABLE + nwait_signal: ENABLE or DISABLE + memory_write: ENABLE or DISABLE + nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING + wrap_burst_mode: ENABLE or DISABLE + nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH + burst_mode: ENABLE or DISABLE + databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR + address_data_mux: ENABLE or DISABLE + read_write_timing: struct exmc_norsram_timing_parameter_struct set the time + write_timing: struct exmc_norsram_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; + + /* get the register value */ + snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); + + /* clear relative bits */ + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX )); + + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| + (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | + (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | + (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )| + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* nor flash access enable */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ + snctl |= (uint32_t)EXMC_SNCTL_NREN; + } + + /* extended mode configure */ + if(ENABLE == exmc_norsram_init_struct->extended_mode){ + snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) | + (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)| + (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) | + exmc_norsram_init_struct->write_timing->asyn_access_mode); + }else{ + snwtcfg = BANK0_SNWTCFG_RESET; + } + + /* configure the registers */ + EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; + EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; + EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; +} + +/*! + \brief initialize the struct exmc_norsram_parameter_struct + \param[in] none + \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + /* configure the structure with default value */ + exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; + exmc_norsram_init_struct->address_data_mux = ENABLE; + exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; + exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; + exmc_norsram_init_struct->burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + exmc_norsram_init_struct->wrap_burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; + exmc_norsram_init_struct->memory_write = ENABLE; + exmc_norsram_init_struct->nwait_signal = ENABLE; + exmc_norsram_init_struct->extended_mode = DISABLE; + exmc_norsram_init_struct->asyn_wait = DISABLE; + exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; + + /* read/write timing configure */ + exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; + exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; + exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; + + /* write timing configure, when extended mode is used */ + exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; +} + +/*! + \brief enable EXMC NOR/PSRAM bank region + \param[in] norsram_region: specifie the region of NOR/PSRAM bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_enable(uint32_t norsram_region) +{ + EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief disable EXMC NOR/PSRAM bank region + \param[in] norsram_region: specifie the region of NOR/PSRAM Bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_disable(uint32_t norsram_region) +{ + EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief deinitialize EXMC NAND bank + \param[in] nand_bank: select the bank of NAND + \arg EXMC_BANKx_NAND(x=1..2) + \param[out] none + \retval none +*/ +void exmc_nand_deinit(uint32_t nand_bank) +{ + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + EXMC_NPCTL(nand_bank) = BANK1_2_NPCTL_RESET; + EXMC_NPINTEN(nand_bank) = BANK1_2_NPINTEN_RESET; + EXMC_NPCTCFG(nand_bank) = BANK1_2_NPCTCFG_RESET; + EXMC_NPATCFG(nand_bank) = BANK1_2_NPATCFG_RESET; +} + +/*! + \brief initialize EXMC NAND bank + \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter + nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND + ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + ecc_logic: ENABLE or DISABLE + databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +{ + uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; + + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; + + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | + (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); + + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ + EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; + EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; + EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; +} + +/*! + \brief initialize the struct exmc_nand_init_struct + \param[in] none + \param[out] the initialized struct exmc_nand_init_struct pointer + \retval none +*/ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +{ + /* configure the structure with default value */ + exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; + exmc_nand_init_struct->wait_feature = DISABLE; + exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; + exmc_nand_init_struct->ecc_logic = DISABLE; + exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; + exmc_nand_init_struct->ctr_latency = 0x0U; + exmc_nand_init_struct->atr_latency = 0x0U; + exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief enable NAND bank + \param[in] nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_enable(uint32_t nand_bank) +{ + EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable NAND bank + \param[in] nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_disable(uint32_t nand_bank) +{ + EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_NDBKEN; +} + +/*! + \brief enable or disable the EXMC NAND ECC function + \param[in] nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue) +{ + if (ENABLE == newvalue){ + /* enable the selected NAND bank ECC function */ + EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_ECCEN; + }else{ + /* disable the selected NAND bank ECC function */ + EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_ECCEN; + } +} + +/*! + \brief get the EXMC ECC value + \param[in] nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval the error correction code(ECC) value +*/ +uint32_t exmc_ecc_get(uint32_t nand_bank) +{ + return (EXMC_NECC(nand_bank)); +} + +/*! + \brief deinitialize EXMC PC card bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_deinit(void) +{ + /* EXMC_BANK3_PCCARD */ + EXMC_NPCTL3 = BANK3_NPCTL_RESET; + EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; + EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; + EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; + EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; +} + +/*! + \brief initialize EXMC PC card bank + \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +{ + /* configure the EXMC bank3 PC card control register */ + EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + + /* configure the EXMC bank3 PC card common space timing configuration register */ + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + + /* configure the EXMC bank3 PC card attribute space timing configuration register */ + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )| + (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); + + /* configure the EXMC bank3 PC card io space timing configuration register */ + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )| + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); +} + +/*! + \brief initialize the struct exmc_pccard_parameter_struct + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +{ + /* configure the structure with default value */ + exmc_pccard_init_struct->wait_feature = DISABLE; + exmc_pccard_init_struct->ctr_latency = 0x0U; + exmc_pccard_init_struct->atr_latency = 0x0U; + exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief enable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_enable(void) +{ + EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_disable(void) +{ + EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; +} + +/*! + \brief enable EXMC interrupt + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + one or more parameters can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source) +{ + /* NAND bank1, bank2 or PC card bank3 */ + EXMC_NPINTEN(bank) |= interrupt_source; +} + +/*! + \brief disable EXMC interrupt + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + one or more parameters can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(bank) &= ~interrupt_source; +} + +/*! + \brief check EXMC flag is set or not + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC Card bank + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag) +{ + uint32_t status = 0x00000000U; + + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(bank); + + if ((status & flag) != (uint32_t)flag ){ + /* flag is reset */ + return RESET; + }else{ + /* flag is set */ + return SET; + } +} + +/*! + \brief clear EXMC flag + \param[in] bank: specifie the NAND bank, PCCARD bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] flag: specify get which flag + one or more parameters can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \param[out] none + \retval none +*/ +void exmc_flag_clear(uint32_t bank, uint32_t flag) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(bank) &= ~flag; +} + +/*! + \brief check EXMC interrupt flag is set or not + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source) +{ + uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; + + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(bank); + interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET)); + + interrupt_enable = (status & interrupt_source); + + if ((interrupt_enable) && (interrupt_state)){ + /* interrupt flag is set */ + return SET; + }else{ + /* interrupt flag is reset */ + return RESET; + } +} + +/*! + \brief clear EXMC interrupt flag + \param[in] bank: specifies the NAND bank, PC card bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + one or more parameters can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source) +{ + /* NAND bank1, bank2 or PC card bank3 */ + EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c new file mode 100644 index 0000000000..dcda291314 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c @@ -0,0 +1,256 @@ +/*! + \file gd32f10x_exti.c + \brief EXTI driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_exti.h" + +#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = EXTI_REG_RESET_VALUE; + EXTI_EVEN = EXTI_REG_RESET_VALUE; + EXTI_RTEN = EXTI_REG_RESET_VALUE; + EXTI_FTEN = EXTI_REG_RESET_VALUE; + EXTI_SWIEV = EXTI_REG_RESET_VALUE; +} + +/*! + \brief initialize the EXTI + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling edge trigger + \arg EXTI_TRIG_BOTH: rising edge and falling edge trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode){ + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type){ + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI lines flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI lines flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c new file mode 100644 index 0000000000..83da3519e0 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c @@ -0,0 +1,965 @@ +/*! + \file gd32f10x_fmc.c + \brief FMC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_fmc.h" + +/*! + \brief set the wait state counter value + \param[in] wscnt£ºwait state counter value + \arg WS_WSCNT_0: FMC 0 wait state + \arg WS_WSCNT_1: FMC 1 wait state + \arg WS_WSCNT_2: FMC 2 wait state + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint32_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief unlock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ + /* write the FMC unlock key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } + + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* write the FMC unlock key */ + if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } + } +} + +/*! + \brief unlock the FMC bank0 operation + this function can be used for all GD32F10x devices. + for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. + for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_unlock(void) +{ + if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ + /* write the FMC unlock key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } +} + +/*! + \brief unlock the FMC bank1 operation + this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_unlock(void) +{ + if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){ + /* write the FMC unlock key */ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit */ + FMC_CTL0 |= FMC_CTL0_LK; + + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* set the LK bit */ + FMC_CTL1 |= FMC_CTL1_LK; + } +} + +/*! + \brief lock the FMC bank0 operation + this function can be used for all GD32F10X devices. + for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. + for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_lock(void) +{ + /* set the LK bit*/ + FMC_CTL0 |= FMC_CTL0_LK; +} + +/*! + \brief lock the FMC bank1 operation + this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_lock(void) +{ + /* set the LK bit*/ + FMC_CTL1 |= FMC_CTL1_LK; +} + +/*! + \brief erase page + \param[in] page_address: the page address to be erased. + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state; + + if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > page_address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + }else{ + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL1 |= FMC_CTL1_PER; + FMC_ADDR1 = page_address; + if(FMC_OBSTAT & FMC_OBSTAT_SPC){ + FMC_ADDR0 = page_address; + } + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL1 &= ~FMC_CTL1_PER; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase whole chip + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state; + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase bank0 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start FMC bank0 erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief erase bank1 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start FMC bank1 erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + }else{ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: halfword to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + if(FMC_BANK0_SIZE > FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + }else{ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief unlock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } + + /* wait until OBWEN bit is set by hardware */ + while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ + } +} + +/*! + \brief lock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OBWEN bit */ + FMC_CTL0 &= ~FMC_CTL0_OBWEN; +} + +/*! + \brief erase the FMC option byte + unlock the FMC_CTL0 and option byte before calling this function + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_erase(void) +{ + uint16_t temp_spc = FMC_NSPC; + + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* check the option byte security protection value */ + if(RESET != ob_spc_get()){ + temp_spc = FMC_USPC; + } + + if(FMC_READY == fmc_state){ + + /* start erase the option byte */ + FMC_CTL0 |= FMC_CTL0_OBER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + /* set the OBPG bit */ + FMC_CTL0 |= FMC_CTL0_OBPG; + /* no security protection */ + OB_SPC = (uint16_t)temp_spc; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable write protection + \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if + you want to protect the corresponding pages. meanwhile, sector + macro could used to set specific sector write protected. + one or more parameters can be selected which are shown as below: + \arg OB_WPx(x = 0..31): write protect specify sector + \arg OB_WP_ALL: write protect all sector + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) +{ + uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; + + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + ob_wp = (uint32_t)(~ob_wp); + temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); + temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U); + temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); + temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); + + if(FMC_READY == fmc_state){ + + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + if(0xFFU != temp_wp0){ + OB_WP0 = temp_wp0; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ + OB_WP1 = temp_wp1; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ + OB_WP2 = temp_wp2; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ + OB_WP3 = temp_wp3; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection + only one parameter can be selected which is shown as below: + \arg FMC_NSPC: no security protection + \arg FMC_USPC: under security protection + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_OBER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + + /* start the option byte program */ + FMC_CTL0 |= FMC_CTL0_OBPG; + + OB_SPC = (uint16_t)ob_spc; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option byte + \param[in] ob_fwdgt: option byte watchdog value + \arg OB_FWDGT_SW: software free watchdog + \arg OB_FWDGT_HW: hardware free watchdog + \param[in] ob_deepsleep: option byte deepsleep reset value + \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \param[in] ob_stdby:option byte standby reset value + \arg OB_STDBY_NRST: no reset when entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \param[in] ob_boot: specifies the option byte boot bank value + \arg OB_BOOT_B0: boot from bank0 + \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) +{ + fmc_state_enum fmc_state = FMC_READY; + uint8_t temp; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); + OB_USER = (uint16_t)temp; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program option bytes data + \param[in] address: the option bytes address to be programmed + \param[in] data: the byte to be programmed + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the OBPG bit */ + FMC_CTL0 |= FMC_CTL0_OBPG; + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the FMC user option byte + \param[in] none + \param[out] none + \retval the FMC user option byte values +*/ +uint8_t ob_user_get(void) +{ + /* return the FMC user option byte value */ + return (uint8_t)(FMC_OBSTAT >> 2U); +} + +/*! + \brief get OB_DATA in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_data +*/ +uint16_t ob_data_get(void) +{ + return (uint16_t)(FMC_OBSTAT >> 10U); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value +*/ +uint32_t ob_write_protection_get(void) +{ + /* return the FMC write protection option byte value */ + return FMC_WP; +} + +/*! + \brief get the FMC option byte security protection + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ob_spc_get(void) +{ + FlagStatus spc_state = RESET; + + if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ + spc_state = SET; + }else{ + spc_state = RESET; + } + return spc_state; +} + +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_BANK0_END: enable FMC end of program interrupt + \arg FMC_INT_BANK0_ERR: enable FMC error interrupt + \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_BANK0_END: enable FMC end of program interrupt + \arg FMC_INT_BANK0_ERR: enable FMC error interrupt + \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief check flag is set or not + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit + \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit + \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit + \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit + \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit + \arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit + \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit + \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit + \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t flag) +{ + if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the FMC flag + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit + \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit + \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit + \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit + \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit + \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t flag) +{ + FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); +} + +/*! + \brief get FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit + \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); + }else{ + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); + } + + if(ret1 && ret2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit + \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) +{ + FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); +} + +/*! + \brief get the FMC bank0 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ + fmc_state = FMC_BUSY; + }else{ + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ + fmc_state = FMC_WPERR; + }else{ + if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ + fmc_state = FMC_PGERR; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the FMC bank1 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){ + fmc_state = FMC_BUSY; + }else{ + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){ + fmc_state = FMC_WPERR; + }else{ + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ + fmc_state = FMC_PGERR; + } + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank0 is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do{ + /* get FMC state */ + fmc_state = fmc_bank0_state_get(); + timeout--; + }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state){ + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank1 is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do{ + /* get FMC state */ + fmc_state = fmc_bank1_state_get(); + timeout--; + }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state){ + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c new file mode 100644 index 0000000000..0025c9a572 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c @@ -0,0 +1,155 @@ +/*! + \file gd32f10x_fwdgt.c + \brief FWDGT driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_fwdgt.h" + +/* write value to FWDGT_CTL_CMD bit field */ +#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status){ + return ERROR; + } + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status){ + return ERROR; + } + FWDGT_RLD = RLD_RLD(reload_value); + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(FWDGT_STAT & flag){ + return SET; + } + + return RESET; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c new file mode 100644 index 0000000000..d8bdd709bb --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c @@ -0,0 +1,539 @@ +/*! + \file gd32f10x_gpio.c + \brief GPIO driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_gpio.h" + +#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ +#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ +#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ +#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ +#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ +#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ +#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ +#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ +#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/ + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph){ + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOE: + /* reset GPIOE */ + rcu_periph_reset_enable(RCU_GPIOERST); + rcu_periph_reset_disable(RCU_GPIOERST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + case GPIOG: + /* reset GPIOG */ + rcu_periph_reset_enable(RCU_GPIOGRST); + rcu_periph_reset_disable(RCU_GPIOGRST); + break; + default: + break; + } +} + +/*! + \brief reset alternate function I/O(AFIO) + \param[in] none + \param[out] none + \retval none +*/ +void gpio_afio_deinit(void) +{ + rcu_periph_reset_enable(RCU_AFRST); + rcu_periph_reset_disable(RCU_AFRST); +} + +/*! + \brief GPIO parameter initialization + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] mode: gpio pin mode + only one parameter can be selected which is shown as below: + \arg GPIO_MODE_AIN: analog input mode + \arg GPIO_MODE_IN_FLOATING: floating input mode + \arg GPIO_MODE_IPD: pull-down input mode + \arg GPIO_MODE_IPU: pull-up input mode + \arg GPIO_MODE_OUT_OD: GPIO output with open-drain + \arg GPIO_MODE_OUT_PP: GPIO output with push-pull + \arg GPIO_MODE_AF_OD: AFIO output with open-drain + \arg GPIO_MODE_AF_PP: AFIO output with push-pull + \param[in] speed: gpio output max speed value + only one parameter can be selected which is shown as below: + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + + \param[out] none + \retval none +*/ +void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) +{ + uint16_t i; + uint32_t temp_mode = 0U; + uint32_t reg = 0U; + + /* GPIO mode configuration */ + temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); + + /* GPIO speed configuration */ + if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ + /* output mode max speed:10MHz,2MHz,50MHz */ + temp_mode |= (uint32_t)speed; + } + + /* configure the eight low port pins with GPIO_CTL0 */ + for(i = 0U;i < 8U;i++){ + if((1U << i) & pin){ + reg = GPIO_CTL0(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i, temp_mode); + + /* set IPD or IPU */ + if(GPIO_MODE_IPD == mode){ + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); + }else{ + /* set the corresponding OCTL bit */ + if(GPIO_MODE_IPU == mode){ + GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); + } + } + /* set GPIO_CTL0 register */ + GPIO_CTL0(gpio_periph) = reg; + } + } + /* configure the eight high port pins with GPIO_CTL1 */ + for(i = 8U;i < 16U;i++){ + if((1U << i) & pin){ + reg = GPIO_CTL1(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i - 8U); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i - 8U, temp_mode); + + /* set IPD or IPU */ + if(GPIO_MODE_IPD == mode){ + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); + }else{ + /* set the corresponding OCTL bit */ + if(GPIO_MODE_IPU == mode){ + GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); + } + } + /* set GPIO_CTL1 register */ + GPIO_CTL1(gpio_periph) = reg; + } + } +} + +/*! + \brief set GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if(RESET != bit_value){ + GPIO_BOP(gpio_periph) = (uint32_t)pin; + }else{ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] data: specify the value to be written to the port output data register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph,uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + only one parameter can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval input status of gpio pin: SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO port input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval input status of gpio all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return (uint16_t)(GPIO_ISTAT(gpio_periph)); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + only one parameter can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval output status of gpio pin: SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO port output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval output status of gpio all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_OCTL(gpio_periph)); +} + +/*! + \brief configure GPIO pin remap + \param[in] gpio_remap: select the pin to remap + \arg GPIO_SPI0_REMAP: SPI0 remapping + \arg GPIO_I2C0_REMAP: I2C0 remapping + \arg GPIO_USART0_REMAP: USART0 remapping + \arg GPIO_USART1_REMAP: USART1 remapping + \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping + \arg GPIO_USART2_FULL_REMAP: USART2 full remapping + \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping + \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping + \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping + \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping + \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping + \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping + \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping + \arg GPIO_TIMER3_REMAP: TIMER3 remapping + \arg GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F10X_CL devices) + \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F10X_CL devices) + \arg GPIO_PD01_REMAP: PD01 remapping + \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) + \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) + \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices) + \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F10X_CL devices) + \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST + \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled + \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled + \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL devices) + \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) + \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices) + \arg GPIO_TIMER8_REMAP: TIMER8 remapping + \arg GPIO_TIMER9_REMAP: TIMER9 remapping + \arg GPIO_TIMER10_REMAP: TIMER10 remapping + \arg GPIO_TIMER12_REMAP: TIMER12 remapping + \arg GPIO_TIMER13_REMAP: TIMER13 remapping + \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) +{ + uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; + + if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ + /* get AFIO_PCF1 regiter value */ + temp_reg = AFIO_PCF1; + }else{ + /* get AFIO_PCF0 regiter value */ + temp_reg = AFIO_PCF0; + } + + temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; + remap1 = remap & LSB_16BIT_MASK; + + /* judge pin remap type */ + if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){ + temp_reg &= PCF_SWJCFG_MASK; + AFIO_PCF0 &= PCF_SWJCFG_MASK; + }else if(PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)){ + remap2 = ((uint32_t)0x03U) << temp_mask; + temp_reg &= ~remap2; + temp_reg |= ~PCF_SWJCFG_MASK; + }else{ + temp_reg &= ~(remap1 << ((remap >> 0x15U)*0x10U)); + temp_reg |= ~PCF_SWJCFG_MASK; + } + + /* set pin remap value */ + if(DISABLE != newvalue){ + temp_reg |= (remap1 << ((remap >> 0x15U)*0x10U)); + } + + if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ + /* set AFIO_PCF1 regiter value */ + AFIO_PCF1 = temp_reg; + }else{ + /* set AFIO_PCF0 regiter value */ + AFIO_PCF0 = temp_reg; + } +} + +/*! + \brief select GPIO pin exti sources + \param[in] gpio_outputport: gpio event output port + \arg GPIO_PORT_SOURCE_GPIOA: output port source A + \arg GPIO_PORT_SOURCE_GPIOB: output port source B + \arg GPIO_PORT_SOURCE_GPIOC: output port source C + \arg GPIO_PORT_SOURCE_GPIOD: output port source D + \arg GPIO_PORT_SOURCE_GPIOE: output port source E + \arg GPIO_PORT_SOURCE_GPIOF: output port source F + \arg GPIO_PORT_SOURCE_GPIOG: output port source G + \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15) + \param[out] none + \retval none +*/ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) +{ + uint32_t source = 0U; + source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); + + /* select EXTI sources */ + if(GPIO_PIN_SOURCE_4 > output_pin){ + /* select EXTI0/EXTI1/EXTI2/EXTI3 */ + AFIO_EXTISS0 &= ~source; + AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); + }else if(GPIO_PIN_SOURCE_8 > output_pin){ + /* select EXTI4/EXTI5/EXTI6/EXTI7 */ + AFIO_EXTISS1 &= ~source; + AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); + }else if(GPIO_PIN_SOURCE_12 > output_pin){ + /* select EXTI8/EXTI9/EXTI10/EXTI11 */ + AFIO_EXTISS2 &= ~source; + AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); + }else{ + /* select EXTI12/EXTI13/EXTI14/EXTI15 */ + AFIO_EXTISS3 &= ~source; + AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); + } +} + +/*! + \brief configure GPIO pin event output + \param[in] output_port: gpio event output port + only one parameter can be selected which are shown as below: + \arg GPIO_EVENT_PORT_GPIOA: event output port A + \arg GPIO_EVENT_PORT_GPIOB: event output port B + \arg GPIO_EVENT_PORT_GPIOC: event output port C + \arg GPIO_EVENT_PORT_GPIOD: event output port D + \arg GPIO_EVENT_PORT_GPIOE: event output port E + \arg GPIO_EVENT_PORT_GPIOE: event output port F + \arg GPIO_EVENT_PORT_GPIOE: event output port G + \param[in] output_pin: + only one parameter can be selected which are shown as below: + \arg GPIO_EVENT_PIN_x(x=0..15) + \param[out] none + \retval none +*/ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) +{ + uint32_t reg = 0U; + reg = AFIO_EC; + + /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ + reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); + + reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); + reg |= (uint32_t)output_pin; + + AFIO_EC = reg; +} + +/*! + \brief enable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_enable(void) +{ + AFIO_EC |= AFIO_EC_EOE; +} + +/*! + \brief disable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_disable(void) +{ + AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); +} + +/*! + \brief lock GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +#ifdef GD32F10X_CL +/*! + \brief select ethernet MII or RMII PHY + \param[in] gpio_enetsel: ethernet MII or RMII PHY selection + \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY + \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY + \param[out] none + \retval none +*/ +void gpio_ethernet_phy_select(uint32_t gpio_enetsel) +{ + /* clear AFIO_PCF0_ENET_PHY_SEL bit */ + AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); + + /* select MII or RMII PHY */ + AFIO_PCF0 |= (uint32_t)gpio_enetsel; +} +#endif diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c new file mode 100644 index 0000000000..fa1ae96d23 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c @@ -0,0 +1,707 @@ +/*! + \file gd32f10x_i2c.c + \brief I2C driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_i2c.h" + +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph){ + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + \param[in] dutycyc: duty cycle in fast mode + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high=2 + \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1/1000000U); + if(freq >= I2CCLK_MAX){ + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if(100000U >= clkspeed){ + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1/1000000U)+1U); + if(risetime >= I2CCLK_MAX){ + I2C_RT(i2c_periph) = I2CCLK_MAX; + }else if(risetime <= I2CCLK_MIN){ + I2C_RT(i2c_periph) = I2CCLK_MIN; + }else{ + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1/(clkspeed*2U)); + if(clkc < 0x04U){ + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + }else if(400000U >= clkspeed){ + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); + if(I2C_DTCY_2 == dutycyc){ + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1/(clkspeed*3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + }else{ + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1/(clkspeed*25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if(0U == (clkc & I2C_CKCFG_CLKC)){ + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + }else{ + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: 7bits + \arg I2C_ADDFORMAT_10BITS: 10bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief SMBus type selection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] type: + only one parameter can be selected which is shown as below: + \arg I2C_SMBUS_DEVICE: device + \arg I2C_SMBUS_HOST: host + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if(I2C_SMBUS_HOST == type){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + if(I2C_ACK_ENABLE == ack){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } +} + +/*! + \brief configure I2C POAP position + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + /* configure I2C POAP position */ + if(I2C_ACKPOS_NEXT == pos){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); + } +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection){ + addr = addr & I2C_TRANSMITTER; + }else{ + addr = addr | I2C_RECEIVER; + } + /* send slave address */ + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief dual-address mode switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dualaddr: + only one parameter can be selected which is shown as below: + \arg I2C_DUADEN_DISABLE: disable dual-address mode + \arg I2C_DUADEN_ENABLE: enable dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) +{ + if(I2C_DUADEN_ENABLE == dualaddr){ + I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; + }else{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); + } +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief enable I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable + \param[out] none + \retval none +*/ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure whether next DMA EOT is DMA last transfer or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmalast: + only one parameter can be selected which is shown as below: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] stretchpara: + only one parameter can be selected which is shown as below: + \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled + \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_DISSTRC); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] gcallpara: + only one parameter can be selected which is shown as below: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief software reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sreset: + only one parameter can be selected which is shown as below: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C PEC calculation on or off + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC + \param[out] none + \retval none +*/ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>STAT1_PECV_OFFSET); +} + +/*! + \brief I2C issue alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* issue alert through SMBA pin configure*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief enable or disable I2C ARP protocol in SMBus switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief check I2C flag is set or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear I2C flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(I2C_FLAG_ADDSEND == flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief check I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ + if(intenable && bufie){ + intenable = 1U; + }else{ + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + if(I2C_INT_FLAG_ADDSEND == int_flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c new file mode 100644 index 0000000000..1a96627b3a --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c @@ -0,0 +1,187 @@ +/*! + \file gd32f10x_misc.c + \brief MISC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, + uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + + /* use the priority group value to get the temp_pre and the temp_sub */ + switch ((SCB->AIRCR) & (uint32_t)0x700U) { + case NVIC_PRIGROUP_PRE0_SUB4: + temp_pre = 0U; + temp_sub = 0x4U; + break; + case NVIC_PRIGROUP_PRE1_SUB3: + temp_pre = 1U; + temp_sub = 0x3U; + break; + case NVIC_PRIGROUP_PRE2_SUB2: + temp_pre = 2U; + temp_sub = 0x2U; + break; + case NVIC_PRIGROUP_PRE3_SUB1: + temp_pre = 3U; + temp_sub = 0x1U; + break; + case NVIC_PRIGROUP_PRE4_SUB0: + temp_pre = 4U; + temp_sub = 0x0U; + break; + default: + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre = 2U; + temp_sub = 0x2U; + break; + } + + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(uint8_t nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + }else{ + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c new file mode 100644 index 0000000000..33052db8d1 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c @@ -0,0 +1,265 @@ +/*! + \file gd32f10x_pmu.c + \brief PMU driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_pmu.h" + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + only one parameter can be selected which is shown as below: + \arg PMU_LVDT_0: voltage threshold is 2.2V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.5V + \arg PMU_LVDT_4: voltage threshold is 2.6V + \arg PMU_LVDT_5: voltage threshold is 2.7V + \arg PMU_LVDT_6: voltage threshold is 2.8V + \arg PMU_LVDT_7: voltage threshold is 2.9V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief PMU work at sleep mode + \param[in] sleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd){ + __WFI(); + }else{ + __WFE(); + } +} + +/*! + \brief PMU work at deepsleep mode + \param[in] ldo: + only one parameter can be selected which is shown as below: + \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \param[in] deepsleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) +{ + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* set sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* select WFI or WFE command to enter deepsleep mode */ + if(WFI_CMD == deepsleepmodecmd){ + __WFI(); + }else{ + __SEV(); + __WFE(); + __WFE(); + } + /* reset sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work at standby mode + \param[in] standbymodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_standbymode(uint8_t standbymodecmd) +{ + /* set sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* select WFI or WFE command to enter standby mode */ + if(WFI_CMD == standbymodecmd){ + __WFI(); + }else{ + __WFE(); + } +} + +/*! + \brief enable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(void) +{ + PMU_CS |= PMU_CS_WUPEN; +} + +/*! + \brief disable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(void) +{ + PMU_CS &= ~PMU_CS_WUPEN; +} + +/*! + \brief enable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \param[out] none + \retval FlagStatus SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if(PMU_CS & flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear flag bit + \param[in] flag_reset: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag_reset) +{ + switch(flag_reset){ + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default : + break; + } +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c new file mode 100644 index 0000000000..579831ccaf --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c @@ -0,0 +1,1193 @@ +/*! + \file gd32f10x_rcu.c + \brief RCU driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_rcu.h" + +/* define clock source */ +#define SEL_IRC8M ((uint16_t)0U) +#define SEL_HXTAL ((uint16_t)1U) +#define SEL_PLL ((uint16_t)2U) + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + rcu_osci_stab_wait(RCU_IRC8M); + + /* reset CFG0 register */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | + RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2); +#elif defined(GD32F10X_CL) + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4); +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + RCU_CTL &= ~RCU_CTL_HXTALBPS; +#ifdef GD32F10X_CL + RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); +#endif /* GD32F10X_CL */ + + /* reset INT and CFG1 register */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + RCU_INT = 0x009f0000U; +#elif defined(GD32F10X_CL) + RCU_INT = 0x00ff0000U; + RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | + RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL); +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock + \arg RCU_AF : alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_ENET: ENET clock(CL series available) + \arg RCU_ENETTX: ENETTX clock(CL series available) + \arg RCU_ENETRX: ENETRX clock(CL series available) + \arg RCU_USBD: USBD clock(HD,XD series available) + \arg RCU_USBFS: USBFS clock(CL series available) + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock + \arg RCU_SDIO: SDIO clock(not available for CL series) + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock + \arg RCU_AF: alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_ENET: ENET clock(CL series available) + \arg RCU_ENETTX: ENETTX clock(CL series available) + \arg RCU_ENETRX: ENETRX clock(CL series available) + \arg RCU_USBD: USBD clock(HD,XD series available) + \arg RCU_USBFS: USBFS clock(CL series available) + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock + \arg RCU_SDIO: SDIO clock(not available for CL series) + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_ENETRST: reset ENET(CL series available) + \arg RCU_USBDRST: reset USBD(HD,XD series available) + \arg RCU_USBFSRST: reset USBFS(CL series available) + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_ENETRST: reset ENET(CL series available) + \arg RCU_USBDRST: reset USBD(HD,XD series available) + \arg RCU_USBFSRST: reset USBFS(CL series available) + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP domain + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP domain reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + reg &= ~RCU_CFG0_SCS; + RCU_CFG0 = (reg | ck_sys); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source + \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source + \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the AHBPSC bits and set according to ck_ahb */ + reg &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (reg | ck_ahb); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB1PSC and set according to ck_apb1 */ + reg &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (reg | ck_apb1); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB2PSC and set according to ck_apb2 */ + reg &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (reg | ck_apb2); +} + +/*! + \brief configure the CK_OUT0 clock source + \param[in] ckout0_src: CK_OUT0 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT0SRC_NONE: no clock selected + \arg RCU_CKOUT0SRC_CKSYS: system clock selected + \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected + \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected + \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected + \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected + \arg RCU_CKOUT0SRC_EXT1: EXT1 selected + \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected + \param[out] none + \retval none +*/ +void rcu_ckout0_config(uint32_t ckout0_src) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the CKOUT0SRC, set according to ckout0_src */ + reg &= ~RCU_CFG0_CKOUT0SEL; + RCU_CFG0 = (reg | ckout0_src); +} + +/*! + \brief configure the main PLL clock + \param[in] pll_src: PLL clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL + \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL_MULx (XD series x = 2..32, CL series x = 2..14, 6.5, 16..32) + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + + /* PLL clock source and multiplication factor configuration */ + reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + reg |= (pll_src | pll_mul); + + RCU_CFG0 = reg; +} + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) +/*! + \brief configure the PREDV0 division factor + \param[in] predv0_div: PREDV0 division factor + only one parameter can be selected which is shown as below: + \arg RCU_PREDV0_DIVx, x = 1,2 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + /* reset PREDV0 bit */ + reg &= ~RCU_CFG0_PREDV0; + if(RCU_PREDV0_DIV2 == predv0_div){ + /* set the PREDV0 bit */ + reg |= RCU_CFG0_PREDV0; + } + + RCU_CFG0 = reg; +} +#elif defined(GD32F10X_CL) +/*! + \brief configure the PREDV0 division factor and clock source + \param[in] predv0_source: PREDV0 input clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock + \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock + \param[in] predv0_div: PREDV0 division factor + only one parameter can be selected which is shown as below: + \arg RCU_PREDV0_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset PREDV0SEL and PREDV0 bits */ + reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); + /* set the PREDV0SEL and PREDV0 division factor */ + reg |= (predv0_source | predv0_div); + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PREDV1 division factor + \param[in] predv1_div: PREDV1 division factor + only one parameter can be selected which is shown as below: + \arg RCU_PREDV1_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv1_config(uint32_t predv1_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset the PREDV1 bits */ + reg &= ~RCU_CFG1_PREDV1; + /* set the PREDV1 division factor */ + reg |= predv1_div; + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PLL1 clock + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL1_MULx (x = 8..16, 20) + \param[out] none + \retval none +*/ +void rcu_pll1_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL1MF; + RCU_CFG1 |= pll_mul; +} + +/*! + \brief configure the PLL2 clock + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL2_MULx (x = 8..16, 20) + \param[out] none + \retval none +*/ +void rcu_pll2_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL2MF; + RCU_CFG1 |= pll_mul; +} +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + +/*! + \brief configure the ADC prescaler factor + \param[in] adc_psc: ADC prescaler factor + only one parameter can be selected which is shown as below: + \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 + \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 + \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 + \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 + \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 + \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(uint32_t adc_psc) +{ + uint32_t reg0; + + /* reset the ADCPSC bits */ + reg0 = RCU_CFG0; + reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); + + /* set the ADC prescaler factor */ + switch(adc_psc){ + case RCU_CKADC_CKAPB2_DIV2: + case RCU_CKADC_CKAPB2_DIV4: + case RCU_CKADC_CKAPB2_DIV6: + case RCU_CKADC_CKAPB2_DIV8: + reg0 |= (adc_psc << 14); + break; + + case RCU_CKADC_CKAPB2_DIV12: + case RCU_CKADC_CKAPB2_DIV16: + adc_psc &= ~BIT(2); + reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); + break; + + default: + break; + } + + /* set the register */ + RCU_CFG0 = reg0; +} + +/*! + \brief configure the USBD/USBFS prescaler factor + \param[in] usb_psc: USB prescaler factor + only one parameter can be selected which is shown as below: + \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5 + \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1 + \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5 + \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2 + \param[out] none + \retval none +*/ +void rcu_usb_clock_config(uint32_t usb_psc) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* configure the USBD/USBFS prescaler factor */ +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + reg &= ~RCU_CFG0_USBDPSC; +#elif defined(GD32F10X_CL) + reg &= ~RCU_CFG0_USBFSPSC; +#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ + + RCU_CFG0 = (reg | usb_psc); +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + uint32_t reg; + + reg = RCU_BDCTL; + /* reset the RTCSRC bits and set according to rtc_clock_source */ + reg &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL = (reg | rtc_clock_source); +} + +#ifdef GD32F10X_CL +/*! + \brief configure the I2S1 clock source selection + \param[in] i2s_clock_source: I2S1 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock + \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock + \param[out] none + \retval none +*/ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S1SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S1SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} + +/*! + \brief configure the I2S2 clock source selection + \param[in] i2s_clock_source: I2S2 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock + \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock + \param[out] none + \retval none +*/ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S2SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S2SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} +#endif /* GD32F10X_CL */ + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only) + \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only) + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only) + \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only) + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only) + \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only) + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +{ + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + + switch(osci){ + /* wait HXTAL stable */ + case RCU_HXTAL: + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC8M stable */ + case RCU_IRC8M: + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC40K stable */ + case RCU_IRC40K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ + reval = SUCCESS; + } + break; + + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ + reval = SUCCESS; + } + break; + +#ifdef GD32F10X_CL + /* wait PLL1 stable */ + case RCU_PLL1_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ + reval = SUCCESS; + } + break; + /* wait PLL2 stable */ + case RCU_PLL2_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ + reval = SUCCESS; + } + break; +#endif /* GD32F10X_CL */ + + default: + break; + } + + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci){ + /* enable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg | RCU_CTL_HXTALBPS); + break; + /* enable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC40K: + case RCU_PLL_CK: +#ifdef GD32F10X_CL + case RCU_PLL1_CK: + case RCU_PLL2_CK: +#endif /* GD32F10X_CL */ + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci){ + /* disable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); + break; + /* disable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC40K: + case RCU_PLL_CK: +#ifdef GD32F10X_CL + case RCU_PLL1_CK: + case RCU_PLL2_CK: +#endif /* GD32F10X_CL */ + break; + default: + break; + } +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) +{ + uint32_t reg; + + reg = RCU_CTL; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + reg &= ~RCU_CTL_IRC8MADJ; + RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V + \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V + \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V + \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2 +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws, ck_freq = 0U; + uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; + uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp; +#ifdef GD32F10X_CL + uint32_t predv0, predv1, pll1mf; +#endif /* GD32F10X_CL */ + + /* exponent of AHB, APB1 and APB2 clock divider */ + uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + if(RCU_PLLSRC_HXTAL == pllsel) { + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + +#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) + predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); + /* PREDV0 input source clock divided by 2 */ + if(RCU_CFG0_PREDV0 == predv0sel){ + ck_src = HXTAL_VALUE/2U; + } +#elif defined(GD32F10X_CL) + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; +#endif /* GD32F10X_HD and GD32F10X_XD */ + }else{ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE/2U; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + if(pllmf < 15U){ + pllmf += 2U; + }else{ + pllmf += 1U; + } + + cksys_freq = ck_src * pllmf; + + #ifdef GD32F10X_CL + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + cksys_freq = ck_src * 6U + ck_src / 2U; + } + #endif /* GD32F10X_CL */ + + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock){ + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + default: + break; + } + return ck_freq; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c new file mode 100644 index 0000000000..27fe2cfe70 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c @@ -0,0 +1,277 @@ +/*! + \file gd32f10x_rtc.c + \brief RTC driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_rtc.h" + +/* RTC register high / low bits mask */ +#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */ +#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */ + +/* RTC register high bits offset */ +#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U) + +/*! + \brief enter RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_enter(void) +{ + RTC_CTL |= RTC_CTL_CMF; +} + +/*! + \brief exit RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_exit(void) +{ + RTC_CTL &= ~RTC_CTL_CMF; +} + +/*! + \brief set RTC counter value + \param[in] cnt: RTC counter value + \param[out] none + \retval none +*/ +void rtc_counter_set(uint32_t cnt) +{ + rtc_configuration_mode_enter(); + /* set the RTC counter high bits */ + RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET); + /* set the RTC counter low bits */ + RTC_CNTL = (cnt & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC prescaler value + \param[in] psc: RTC prescaler value + \param[out] none + \retval none +*/ +void rtc_prescaler_set(uint32_t psc) +{ + rtc_configuration_mode_enter(); + /* set the RTC prescaler high bits */ + RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET); + /* set the RTC prescaler low bits */ + RTC_PSCL = (psc & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief wait RTC last write operation finished flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_lwoff_wait(void) +{ + /* loop until LWOFF flag is set */ + while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){ + } +} + +/*! + \brief wait RTC registers synchronized flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_register_sync_wait(void) +{ + /* clear RSYNF flag */ + RTC_CTL &= ~RTC_CTL_RSYNF; + /* loop until RSYNF flag is set */ + while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){ + } +} + +/*! + \brief set RTC alarm value + \param[in] alarm: RTC alarm value + \param[out] none + \retval none +*/ +void rtc_alarm_config(uint32_t alarm) +{ + rtc_configuration_mode_enter(); + /* set the alarm high bits */ + RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET); + /* set the alarm low bits */ + RTC_ALRML = (alarm & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief get RTC counter value + \param[in] none + \param[out] none + \retval RTC counter value +*/ +uint32_t rtc_counter_get(void) +{ + uint32_t temp = 0x0U; + + temp = RTC_CNTL; + temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); + return temp; +} + +/*! + \brief get RTC divider value + \param[in] none + \param[out] none + \retval RTC divider value +*/ +uint32_t rtc_divider_get(void) +{ + uint32_t temp = 0x00U; + + temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); + temp |= RTC_DIVL; + return temp; +} + +/*! + \brief get RTC flag status + \param[in] flag: specify which flag status to get + only one parameter can be selected which is shown as below: + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \arg RTC_FLAG_LWOF: last write operation finished flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + if(RESET != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC flag status + \param[in] flag: specify which flag status to clear + one or more parameters can be selected which are shown as below: + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + /* clear RTC flag */ + RTC_CTL &= ~flag; +} + +/*! + \brief get RTC interrupt flag status + \param[in] flag: specify which flag status to get + only one parameter can be selected which is shown as below: + \arg RTC_INT_FLAG_SECOND: second interrupt flag + \arg RTC_INT_FLAG_ALARM: alarm interrupt flag + \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_interrupt_flag_get(uint32_t flag) +{ + if(RESET != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC interrupt flag status + \param[in] flag: specify which flag status to clear + one or more parameters can be selected which are shown as below: + \arg RTC_INT_FLAG_SECOND: second interrupt flag + \arg RTC_INT_FLAG_ALARM: alarm interrupt flag + \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \param[out] none + \retval none +*/ +void rtc_interrupt_flag_clear(uint32_t flag) +{ + /* clear RTC interrupt flag */ + RTC_CTL &= ~flag; +} + +/*! + \brief enable RTC interrupt + \param[in] interrupt: specify which interrupt to enbale + one or more parameters can be selected which are shown as below: + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + RTC_INTEN |= interrupt; +} + +/*! + \brief disable RTC interrupt + \param[in] interrupt: specify which interrupt to disbale + one or more parameters can be selected which are shown as below: + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + RTC_INTEN &= ~interrupt; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c new file mode 100644 index 0000000000..d609f282ed --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c @@ -0,0 +1,814 @@ +/*! + \file gd32f10x_sdio.c + \brief SDIO driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_sdio.h" + +#define DEFAULT_RESET_VALUE 0x00000000U + +/*! + \brief deinitialize the SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_deinit(void) +{ + SDIO_PWRCTL = DEFAULT_RESET_VALUE; + SDIO_CLKCTL = DEFAULT_RESET_VALUE; + SDIO_CMDAGMT = DEFAULT_RESET_VALUE; + SDIO_CMDCTL = DEFAULT_RESET_VALUE; + SDIO_DATATO = DEFAULT_RESET_VALUE; + SDIO_DATALEN = DEFAULT_RESET_VALUE; + SDIO_DATACTL = DEFAULT_RESET_VALUE; + SDIO_INTC = DEFAULT_RESET_VALUE; + SDIO_INTEN = DEFAULT_RESET_VALUE; +} + +/*! + \brief configure the SDIO clock + \param[in] clock_edge: SDIO_CLK clock edge + only one parameter can be selected which is shown as below: + \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK + \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK + \param[in] clock_bypass: clock bypass + only one parameter can be selected which is shown as below: + \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass + \arg SDIO_CLOCKBYPASS_DISABLE: no bypass + \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving + only one parameter can be selected which is shown as below: + \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle + \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on + \param[in] clock_division: clock division, less than 256 + \param[out] none + \retval none +*/ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) +{ + uint32_t clock_config = 0U; + clock_config = SDIO_CLKCTL; + /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ + clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV); + + /* configure the SDIO_CLKCTL according to the parameters */ + clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); + SDIO_CLKCTL = clock_config; +} + +/*! + \brief enable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief disable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief set different SDIO card bus mode + \param[in] bus_mode: SDIO card bus mode + only one parameter can be selected which is shown as below: + \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode + \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode + \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode + \param[out] none + \retval none +*/ +void sdio_bus_mode_set(uint32_t bus_mode) +{ + /* reset the SDIO card bus mode bits and set according to bus_mode */ + SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; + SDIO_CLKCTL |= bus_mode; +} + +/*! + \brief set the SDIO power state + \param[in] power_state: SDIO power state + only one parameter can be selected which is shown as below: + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off + \param[out] none + \retval none +*/ +void sdio_power_state_set(uint32_t power_state) +{ + SDIO_PWRCTL = power_state; +} + +/*! + \brief get the SDIO power state + \param[in] none + \param[out] none + \retval SDIO power state + only one parameter can be selected which is shown as below: + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off +*/ +uint32_t sdio_power_state_get(void) +{ + return SDIO_PWRCTL; +} + +/*! + \brief enable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; +} + +/*! + \brief disable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; +} + +/*! + \brief configure the command and response + \param[in] cmd_index: command index, refer to the related specifications + \param[in] cmd_argument: command argument, refer to the related specifications + \param[in] response_type: response type + only one parameter can be selected which is shown as below: + \arg SDIO_RESPONSETYPE_NO: no response + \arg SDIO_RESPONSETYPE_SHORT: short response + \arg SDIO_RESPONSETYPE_LONG: long response + \param[out] none + \retval none +*/ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) +{ + uint32_t cmd_config = 0U; + /* reset the command index, command argument and response type */ + SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; + SDIO_CMDAGMT = cmd_argument; + cmd_config = SDIO_CMDCTL; + cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); + /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ + cmd_config |= (cmd_index | response_type); + SDIO_CMDCTL = cmd_config; +} + +/*! + \brief set the command state machine wait type + \param[in] wait_type: wait type + only one parameter can be selected which is shown as below: + \arg SDIO_WAITTYPE_NO: not wait interrupt + \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt + \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer + \param[out] none + \retval none +*/ +void sdio_wait_type_set(uint32_t wait_type) +{ + /* reset INTWAIT and WAITDEND */ + SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); + /* set the wait type according to wait_type */ + SDIO_CMDCTL |= wait_type; +} + +/*! + \brief enable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; +} + +/*! + \brief disable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; +} + +/*! + \brief get the last response command index + \param[in] none + \param[out] none + \retval last response command index +*/ +uint8_t sdio_command_index_get(void) +{ + return (uint8_t)SDIO_RSPCMDIDX; +} + +/*! + \brief get the response for the last received command + \param[in] responsex: SDIO response + only one parameter can be selected which is shown as below: + \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] + \arg SDIO_RESPONSE1: card response[95:64] + \arg SDIO_RESPONSE2: card response[63:32] + \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 + \param[out] none + \retval response for the last received command +*/ +uint32_t sdio_response_get(uint32_t responsex) +{ + uint32_t resp_content = 0U; + switch(responsex){ + case SDIO_RESPONSE0: + resp_content = SDIO_RESP0; + break; + case SDIO_RESPONSE1: + resp_content = SDIO_RESP1; + break; + case SDIO_RESPONSE2: + resp_content = SDIO_RESP2; + break; + case SDIO_RESPONSE3: + resp_content = SDIO_RESP3; + break; + default: + break; + } + return resp_content; +} + +/*! + \brief configure the data timeout, data length and data block size + \param[in] data_timeout: data timeout period in card bus clock periods + \param[in] data_length: number of data bytes to be transferred + \param[in] data_blocksize: size of data block for block transfer + only one parameter can be selected which is shown as below: + \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte + \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes + \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes + \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes + \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes + \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes + \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes + \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes + \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes + \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes + \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes + \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes + \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes + \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes + \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes + \param[out] none + \retval none +*/ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) +{ + /* reset data timeout, data length and data block size */ + SDIO_DATATO &= ~SDIO_DATATO_DATATO; + SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; + SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; + /* configure the related parameters of data */ + SDIO_DATATO = data_timeout; + SDIO_DATALEN = data_length; + SDIO_DATACTL |= data_blocksize; +} + +/*! + \brief configure the data transfer mode and direction + \param[in] transfer_mode: mode of data transfer + only one parameter can be selected which is shown as below: + \arg SDIO_TRANSMODE_BLOCK: block transfer + \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer + \param[in] transfer_direction: data transfer direction, read or write + only one parameter can be selected which is shown as below: + \arg SDIO_TRANSDIRECTION_TOCARD: write data to card + \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card + \param[out] none + \retval none +*/ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) +{ + uint32_t data_trans = 0U; + /* reset the data transfer mode, transfer direction and set according to the parameters */ + data_trans = SDIO_DATACTL; + data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); + data_trans |= (transfer_mode | transfer_direction); + SDIO_DATACTL = data_trans; +} + +/*! + \brief enable the DSM(data state machine) for data transfer + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DATAEN; +} + +/*! + \brief disable the DSM(data state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; +} + +/*! + \brief write data(one word) to the transmit FIFO + \param[in] data: 32-bit data write to card + \param[out] none + \retval none +*/ +void sdio_data_write(uint32_t data) +{ + SDIO_FIFO = data; +} + +/*! + \brief read data(one word) from the receive FIFO + \param[in] none + \param[out] none + \retval received data +*/ +uint32_t sdio_data_read(void) +{ + return SDIO_FIFO; +} + +/*! + \brief get the number of remaining data bytes to be transferred to card + \param[in] none + \param[out] none + \retval number of remaining data bytes to be transferred +*/ +uint32_t sdio_data_counter_get(void) +{ + return SDIO_DATACNT; +} + +/*! + \brief get the number of words remaining to be written or read from FIFO + \param[in] none + \param[out] none + \retval remaining number of words +*/ +uint32_t sdio_fifo_counter_get(void) +{ + return SDIO_FIFOCNT; +} + +/*! + \brief enable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DMAEN; +} + +/*! + \brief disable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; +} + +/*! + \brief get the flags state of SDIO + \param[in] flag: flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_CMDRUN: command transmission in progress flag + \arg SDIO_FLAG_TXRUN: data transmission in progress flag + \arg SDIO_FLAG_RXRUN: data reception in progress flag + \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO + \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO + \arg SDIO_FLAG_TFF: transmit FIFO is full flag + \arg SDIO_FLAG_RFF: receive FIFO is full flag + \arg SDIO_FLAG_TFE: transmit FIFO is empty flag + \arg SDIO_FLAG_RFE: receive FIFO is empty flag + \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag + \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_flag_get(uint32_t flag) +{ + FlagStatus temp_flag = RESET; + if(RESET != (SDIO_STAT & flag)){ + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the pending flags of SDIO + \param[in] flag: flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_flag_clear(uint32_t flag) +{ + SDIO_INTC = flag; +} + +/*! + \brief enable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_enable(uint32_t int_flag) +{ + SDIO_INTEN |= int_flag; +} + +/*! + \brief disable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_disable(uint32_t int_flag) +{ + SDIO_INTEN &= ~int_flag; +} + +/*! + \brief get the interrupt flags state of SDIO + \param[in] int_flag: interrupt flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt + \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt + \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt + \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt + \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt + \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt + \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t state = 0U; + state = SDIO_STAT; + if(state & int_flag){ + state = SDIO_INTEN; + /* check whether the corresponding bit in SDIO_INTEN is set or not */ + if(state & int_flag){ + return SET; + } + } + return RESET; +} + +/*! + \brief clear the interrupt pending flags of SDIO + \param[in] int_flag: interrupt flags state of SDIO + only one parameter can be selected which is shown as below: + \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag + \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_interrupt_flag_clear(uint32_t int_flag) +{ + SDIO_INTC = int_flag; +} + +/*! + \brief enable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWEN; +} + +/*! + \brief disable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; +} + +/*! + \brief enable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; +} + +/*! + \brief disable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; +} + +/*! + \brief set the read wait type(SD I/O only) + \param[in] readwait_type: SD I/O read wait type + only one parameter can be selected which is shown as below: + \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK + \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] + \param[out] none + \retval none +*/ +void sdio_readwait_type_set(uint32_t readwait_type) +{ + if(SDIO_READWAITTYPE_CLK == readwait_type){ + SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; + }else{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; + } +} + +/*! + \brief enable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_IOEN; +} + +/*! + \brief disable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; +} + +/*! + \brief enable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief disable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief enable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; +} + +/*! + \brief disable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; +} + +/*! + \brief enable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_enable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; +} + +/*! + \brief disable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_disable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; +} + +/*! + \brief enable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; +} + +/*! + \brief disable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c new file mode 100644 index 0000000000..c0fb893ccc --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c @@ -0,0 +1,718 @@ +/*! + \file gd32f10x_spi.c + \brief SPI driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_spi.h" + +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ + +/* I2S clock source selection, multiplication and division mask */ +#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ +#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ +#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ +#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ + +/* default value and offset */ +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /* default value of SPI_I2SPSC register */ +#define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ +#define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph){ + case SPI0: + /* reset SPI0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 and I2S1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + case SPI2: + /* reset SPI2 and I2S2 */ + rcu_periph_reset_enable(RCU_SPI2RST); + rcu_periph_reset_disable(RCU_SPI2RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI struct with the default values + \param[in] spi_struct: SPI parameter stuct + \param[out] none + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct* spi_struct) +{ + /* set the SPI struct with the default values */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; +} + +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI NSS use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)mode; + /* select I2S standard */ + reg |= (uint32_t)standard; + /* select I2S polarity */ + reg |= (uint32_t)ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPIx(x=1,2) + \param[in] audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; + +#ifdef GD32F10X_CL + /* get the I2S clock source */ + if(SPI1 == ((uint32_t)spi_periph)){ + /* I2S1 clock source selection */ + clks = I2S1_CLOCK_SEL; + }else{ + /* I2S2 clock source selection */ + clks = I2S2_CLOCK_SEL; + } + + if(0U != (RCU_CFG1 & clks)){ + /* get RCU PLL2 clock multiplication factor */ + clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); + + if((clks > 5U) && (clks < 15U)){ + /* multiplier is between 8 and 14 */ + clks += 2U; + }else{ + if(15U == clks){ + /* multiplier is 20 */ + clks = 20U; + } + } + + /* get the PREDV1 value */ + i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); + /* calculate I2S clock based on PLL2 and PREDV1 */ + i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); + }else{ + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + } +#else + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); +#endif /* GD32F10X_CL */ + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == mckout){ + clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); + }else{ + if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ + clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); + }else{ + clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)){ + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI NSS pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI NSS pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + }else{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + }else{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* configure SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + }else{ + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief set CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc: SPI crc value + only one parameter can be selected which is shown as below: + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) +{ + if(SPI_CRC_TX == crc){ + return ((uint16_t)(SPI_TCRC(spi_periph))); + }else{ + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt flag status + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if((0U != reg1) && (0U != reg2)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] flag: SPI/I2S flag status + one or more parameters can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(RESET != (SPI_STAT(spi_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c new file mode 100644 index 0000000000..236eedf9be --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c @@ -0,0 +1,2004 @@ +/*! + \file gd32f10x_timer.c + \brief TIMER driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_timer.h" + +/* TIMER init parameter mask */ +#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ +#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ +#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph){ + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; + case TIMER3: + /* reset TIMER3 */ + rcu_periph_reset_enable(RCU_TIMER3RST); + rcu_periph_reset_disable(RCU_TIMER3RST); + break; + case TIMER4: + /* reset TIMER4 */ + rcu_periph_reset_enable(RCU_TIMER4RST); + rcu_periph_reset_disable(RCU_TIMER4RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER6: + /* reset TIMER6 */ + rcu_periph_reset_enable(RCU_TIMER6RST); + rcu_periph_reset_disable(RCU_TIMER6RST); + break; + case TIMER7: + /* reset TIMER7 */ + rcu_periph_reset_enable(RCU_TIMER7RST); + rcu_periph_reset_disable(RCU_TIMER7RST); + break; +#ifdef GD32F10X_XD + case TIMER8: + /* reset TIMER8 */ + rcu_periph_reset_enable(RCU_TIMER8RST); + rcu_periph_reset_disable(RCU_TIMER8RST); + break; + case TIMER9: + /* reset TIMER9 */ + rcu_periph_reset_enable(RCU_TIMER9RST); + rcu_periph_reset_disable(RCU_TIMER9RST); + break; + case TIMER10: + /* reset TIMER10 */ + rcu_periph_reset_enable(RCU_TIMER10RST); + rcu_periph_reset_disable(RCU_TIMER10RST); + break; + case TIMER11: + /* reset TIMER11 */ + rcu_periph_reset_enable(RCU_TIMER11RST); + rcu_periph_reset_disable(RCU_TIMER11RST); + break; + case TIMER12: + /* reset TIMER12 */ + rcu_periph_reset_enable(RCU_TIMER12RST); + rcu_periph_reset_disable(RCU_TIMER12RST); + break; + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; +#endif /* GD32F10X_XD */ + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct* initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP, + TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value,0~65535 + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || + (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || + (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){ + TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); + } + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..4,7..13) + \param[in] aligned: + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..4,7..13) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..4,7..13) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] prescaler: prescaler value + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload){ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] counter: the counter value + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..8,11) + \param[in] spmode: + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + }else if(TIMER_SP_MODE_REPETITIVE == spmode){ + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] update: + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, + or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint32_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + }else if(TIMER_UPDATE_SRC_GLOBAL == update){ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: timer DMA source enable + only one parameter can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: timer DMA source disable + only one parameter can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA disable,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA disable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA disable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA disable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA disable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request disable,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA disable,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: please refer to the following parameters + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) + \param[in] dma_lenth: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief enable or disable TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + }else{ + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + }else{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl){ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U); + } + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U); + } + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U); + } + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] pulse: channel output pulse value + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \arg TIMER_CH_2: TIMER channel2 + \arg TIMER_CH_3: TIMER channel3 + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \arg TIMER_CH_2: TIMER channel2 + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, + TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) + icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, + TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, + TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel){ + case TIMER_CH_0: + /* read TIMER channel 0 capture compare register value */ + count_value = TIMER_CH0CV(timer_periph); + break; + case TIMER_CH_1: + /* read TIMER channel 1 capture compare register value */ + count_value = TIMER_CH1CV(timer_periph); + break; + case TIMER_CH_2: + /* read TIMER channel 2 capture compare register value */ + count_value = TIMER_CH2CV(timer_periph); + break; + case TIMER_CH_3: + /* read TIMER channel 3 capture compare register value */ + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ + icpolarity = TIMER_IC_POLARITY_FALLING; + }else{ + icpolarity = TIMER_IC_POLARITY_RISING; + } + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ + icselection = TIMER_IC_SELECTION_INDIRECTTI; + }else{ + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel){ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); + }else{ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: please refer to the following parameters + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..7) + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable + \arg TIMER_ENCODER_MODE0: encoder mode 0 + \arg TIMER_ENCODER_MODE1: encoder mode 1 + \arg TIMER_ENCODER_MODE2: encoder mode 2 + \arg TIMER_SLAVE_MODE_RESTART: restart mode + \arg TIMER_SLAVE_MODE_PAUSE: pause mode + \arg TIMER_SLAVE_MODE_EVENT: event mode + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] masterslave: + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] decomode: + only one parameter can be selected which is shown as below: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) +{ + /* configure the quadrature decoder mode */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + /* configure input capture selection */ + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + /* configure channel input capture polarity */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph,intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] expolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + }else{ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph,extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source disable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)flag); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c new file mode 100644 index 0000000000..3e6c97ee6f --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c @@ -0,0 +1,767 @@ +/*! + \file gd32f10x_usart.c + \brief USART driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.1, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_usart.h" + +/*! + \brief reset USART/UART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph){ + case USART0: + /* reset USART0 */ + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + /* reset USART1 */ + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + case USART2: + /* reset USART2 */ + rcu_periph_reset_enable(RCU_USART2RST); + rcu_periph_reset_disable(RCU_USART2RST); + break; + case UART3: + /* reset UART3 */ + rcu_periph_reset_enable(RCU_UART3RST); + rcu_periph_reset_disable(RCU_UART3RST); + break; + case UART4: + /* reset UART4 */ + rcu_periph_reset_enable(RCU_UART4RST); + rcu_periph_reset_disable(RCU_UART4RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; + switch(usart_periph){ + /* get clock frequency */ + case USART0: + /* get USART0 clock */ + uclk=rcu_clock_freq_get(CK_APB2); + break; + case USART1: + /* get USART1 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case USART2: + /* get USART2 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case UART3: + /* get UART3 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case UART4: + /* get UART4 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk+baudval/2U)/baudval; + intdiv = udiv & (0x0000fff0U); + fradiv = udiv & (0x0000000fU); + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] paritycfg: configure USART parity + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg ; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + /* configure USART stop bits */ + USART_CTL1(usart_periph) |= stblen; +} +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_TEN; + ctl |= txconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_REN; + ctl |= rxconfig; + /* configure receiver mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_DATA(usart_periph) = USART_DATA_DATA & data; +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] addr: address of USART/UART + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); +} + +/*! + \brief receiver in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_RWU; +} + +/*! + \brief receiver in active mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wmethod: two methods be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mask + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure lin break frame length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] lblen: lin break frame length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits + \arg USART_LBLEN_11B: 11 bits + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); +} + +/*! + \brief send break frame + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_send_break(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; +} + +/*! + \brief enable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] clen: CK length + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + uint32_t ctl = 0U; + + /* read USART_CTL1 register */ + ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + /* set CK length, CK phase, CK polarity */ + ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); + + USART_CTL1(usart_periph) = ctl; +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] gaut: guard time value + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut) +{ + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] psc: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) +{ + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hardwareflow: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_RTSEN; + ctl |= rtsconfig; + /* configure RTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hardwareflow: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_CTSEN; + ctl |= ctsconfig; + /* configure CTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENR; + ctl |= dmacmd; + /* configure DMA reception */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENT; + ctl |= dmacmd; + /* configure DMA transmission */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief get flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_LBDF: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLEF: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_LBDF: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \param[out] none + \retval FlagStatus +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if(flagstatus && intenable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear USART interrupt flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART interrupt flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) +{ + USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c new file mode 100644 index 0000000000..633b50423b --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c @@ -0,0 +1,150 @@ +/*! + \file gd32f10x_wwdgt.c + \brief WWDGT driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f10x_wwdgt.h" + +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + uint32_t reg = 0U; + + reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); + reg |= CTL_CNT(counter_value); + + WWDGT_CTL = reg; +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + uint32_t reg_cfg = 0U, reg_ctl = 0U; + + /* clear WIN and PSC bits, clear CNT bit */ + reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); + reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); + + /* configure WIN and PSC bits, configure CNT bit */ + reg_cfg |= CFG_WIN(window); + reg_cfg |= prescaler; + reg_ctl |= CTL_CNT(counter); + + WWDGT_CTL = reg_ctl; + WWDGT_CFG = reg_cfg; +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(WWDGT_STAT & WWDGT_STAT_EWIF){ + return SET; + } + + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT &= (~WWDGT_STAT_EWIF); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h new file mode 100644 index 0000000000..189be18bae --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h @@ -0,0 +1,217 @@ +/*! + \file usbd_core.h + \brief USB device driver core + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_CORE_H +#define USBD_CORE_H + +#include "usbd_conf.h" +#include "usbd_regs.h" + +/* interrupt flag mask which decide what event should be handled by application */ +#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ + | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE) + +#ifdef LPM_ENABLED +#undef IER_MASK + +#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ + | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE | CTL_L1REQIE) +#endif /* LPM_ENABLED */ + +/* USB device endpoint0 max packet size */ +#define USBD_EP0_MAX_SIZE 64U + +#define USBD_CONTRL_STATUS_TX() do \ +{ \ + pbuf_reg->tx_count = 0U; \ + USBD_ENDP_TX_STATUS_SET(EP0, EPTX_VALID); \ +} while(0) + +#define USBD_CONTRL_STATUS_RX() do \ +{ \ + USBD_STATUS_OUT_SET(EP0); \ + USBD_ENDP_RX_STATUS_SET(EP0, EPRX_VALID); \ +} while(0) + +#define ENDP_BUF_ADDR (sizeof(usbd_ep_buf_struct) * EP_COUNT) + +/* USB device endpoint type */ +typedef enum +{ + ENDP_CONTROL = 0, /*!< control endpoint type value */ + ENDP_ISOC, /*!< isochronous endpoint type value */ + ENDP_BULK, /*!< bulk endpoint type value */ + ENDP_INT /*!< interupt endpoint type value */ +}usbd_eptype_enum; + +/* USB device endpoint kind */ +typedef enum +{ + ENDP_SNG_BUF = 0, /*!< single buffer endpoint type value */ + ENDP_DBL_BUF /*!< double buffer endpoint type value */ +}usbd_epkind_enum; + +/* transfer direction */ +typedef enum +{ + USBD_RX = 0, /*!< receive direction type value */ + USBD_TX /*!< transmit direction type value */ +}usbd_dir_enum; + +/* USB device status */ +typedef enum +{ + USBD_UNCONNECTED = 0, /*!< USB device unconnected status */ + USBD_DEFAULT, /*!< USB device default status */ + USBD_ADDRESSED, /*!< USB device addressed status */ + USBD_CONFIGURED, /*!< USB device configured status */ + USBD_SUSPENDED, /*!< USB device suspended status */ + USBD_CONNECTED /*!< USB device connected status */ +}usbd_run_status_enum; + +/* USB device operation state */ +typedef enum +{ + USBD_OK = 0, /*!< USB device ok */ + USBD_BUSY, /*!< USB device busy */ + USBD_FAIL /*!< USB device fail */ +}usbd_status_enum; + +typedef struct +{ + uint16_t tx_addr; /*!< transmission address */ + uint16_t reserved0; + uint16_t tx_count; /*!< transmission count */ + uint16_t reserved1; + uint16_t rx_addr; /*!< reception address */ + uint16_t reserved2; + uint16_t rx_count; /*!< reception count */ + uint16_t reserved3; +}usbd_ep_buf_struct; + +/* USB endpoint structure */ +typedef struct +{ + /* basic parameters */ + uint8_t stall; /*!< endpoint stall status */ + uint32_t maxpacket; /*!< the maxpacket of the endpoint */ + + /* transaction level parameters */ + uint8_t *trs_buf; /*!< transaction buffer address */ + uint32_t trs_len; /*!< transaction buffer length */ + uint32_t trs_count; /*!< transaction data counts */ +}usb_ep_struct; + +/* USB standard device request structure */ +typedef struct +{ + uint8_t bmRequestType; /*!< the property of the request */ + uint8_t bRequest; /*!< the code of the request */ + uint16_t wValue; /*!< the value of the request which used to choose the different request in the same code request */ + uint16_t wIndex; /*!< USB standard device request index */ + uint16_t wLength; /*!< the return datas length that the host wants to get */ +}usb_device_req_struct; + +/* USB core driver struct */ +typedef struct +{ + /* basic parameters */ + uint8_t config_num; /*!< the number of the USB device configuration */ + __IO uint8_t status; /*!< USB device status */ + uint8_t prev_status; /*!< the previous USB device status */ + uint8_t remote_wakeup; /*!< the flag that point out the device whether support the remote wakeup function */ + + /* the parameters which needs in control transfer */ + uint8_t setup_packet[8]; /*!< the buffer used to store the setup packet */ + uint32_t ctl_count; /*!< the datas length of control transfer request */ + + /* device endpoints */ + usb_ep_struct in_ep[EP_COUNT]; /*!< the in direction endpoints */ + usb_ep_struct out_ep[EP_COUNT]; /*!< the out direction endpoints */ + +#ifdef LPM_ENABLED + uint8_t *bos_desc; /*!< BOS descriptor */ +#endif /* LPM_ENABLED */ + + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< configuration descriptor */ + void* const *strings; /*!< configuration strings */ + + /* device class handler */ + usbd_status_enum (*class_init) (void *pudev, uint8_t config_index); + usbd_status_enum (*class_deinit) (void *pudev, uint8_t config_index); + usbd_status_enum (*class_req_handler) (void *pudev, usb_device_req_struct *req); + usbd_status_enum (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num); +}usbd_core_handle_struct; + +extern uint32_t g_free_buf_addr; +extern usbd_ep_buf_struct *pbuf_reg; + +/* function declarations */ +/* device core register initialization */ +void usbd_core_init (usbd_core_handle_struct *pudev); +/* device core register configure when stop device */ +void usbd_core_deinit (void); + +/* free buffer used from application by toggling the SW_BUF byte */ +void user_buffer_free (uint8_t ep_num, uint8_t dir); + +/* endpoint initialization */ +void usbd_ep_init (usbd_core_handle_struct *pudev, usbd_epkind_enum buf_kind, void *pep_desc); +/* configure the endpoint when it is disabled */ +void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr); +/* endpoint prepare to transmit data */ +void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +/* endpoint prepare to receive data */ +void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +/* set an endpoint to stall status */ +void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); +/* clear endpoint stalled status */ +void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); +/* write datas from user fifo to USBRAM */ +void usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); +/* read datas from USBRAM to user fifo */ +void usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); + +/* get the endpoint status */ +uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr); + +/* get the received data length */ +uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num); + +#endif /* USBD_CORE_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h new file mode 100644 index 0000000000..a524ea615f --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h @@ -0,0 +1,62 @@ +/*! + \file usbd_int.h + \brief USB device interrupt handler header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_INT_H +#define USBD_INT_H + +#include "usbd_core.h" +#include "usbd_std.h" +#include "usbd_pwr.h" + +/* constants definitions */ +extern usbd_core_handle_struct usb_device_dev; + +typedef struct +{ + uint8_t (*SOF) (usbd_core_handle_struct *pudev); /*!< SOF ISR callback */ +}usbd_int_cb_struct; + +extern usbd_int_cb_struct *usbd_int_fops; + +/* function declarations */ +/* USB device interrupt service routine */ +void usbd_isr (void); +/* handle USB high priority successful transfer event */ +uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev); + +#endif /* USBD_INT_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h new file mode 100644 index 0000000000..c0e6a21a19 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h @@ -0,0 +1,52 @@ +/*! + \file usbd_pwr.h + \brief USB device power management functions prototype + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_PWR_H +#define USBD_PWR_H + +#include "usbd_core.h" + +/* function declarations */ +/* USB wakeup first operation is to wakeup mcu */ +void resume_mcu (void); +/* set USB device to suspend mode */ +void usbd_suspend (void); +/* start to remote wakeup */ +void usbd_remote_wakeup_active (void); + +#endif /* USBD_PWR_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h new file mode 100644 index 0000000000..ef3c5c8fcc --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h @@ -0,0 +1,297 @@ +/*! + \file usbd_regs.h + \brief USB device registers + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_REGS_H +#define USBD_REGS_H + +#include "usbd_conf.h" + +/* USB device registers base address */ +#define USBD USBD_BASE +#define USBD_RAM (APB1_BUS_BASE + 0x00006000U) + +/* registers definitions */ +/* common registers */ +#define USBD_CTL (REG32(USBD + 0x40U)) /*!< control register */ +#define USBD_INTF (REG32(USBD + 0x44U)) /*!< interrupt flag register */ +#define USBD_STAT (REG32(USBD + 0x48U)) /*!< status register */ +#define USBD_DADDR (REG32(USBD + 0x4CU)) /*!< device address register */ +#define USBD_BADDR (REG32(USBD + 0x50U)) /*!< buffer address register */ + +/* endpoint control and status register */ +#define USBD_EPxCS(ep_id) (REG32(USBD + (ep_id) * 4U)) /*!< endpoint x control and status register address */ + +/* LPM Registers */ +#define USBD_LPMCS (REG32(USBD + 0x54U)) /*!< USBD LPM control and status register */ + +/* bits definitions */ +/* USBD_CTL */ +#define CTL_STIE BIT(15) /*!< successful transfer interrupt enable mask */ +#define CTL_PMOUIE BIT(14) /*!< packet memory overrun/underrun interrupt enable mask */ +#define CTL_ERRIE BIT(13) /*!< error interrupt enable mask */ +#define CTL_WKUPIE BIT(12) /*!< wakeup interrupt enable mask */ +#define CTL_SPSIE BIT(11) /*!< suspend state interrupt enable mask */ +#define CTL_RSTIE BIT(10) /*!< reset interrupt enable mask */ +#define CTL_SOFIE BIT(9) /*!< start of frame interrupt enable mask */ +#define CTL_ESOFIE BIT(8) /*!< expected start of frame interrupt enable mask */ +#define CTL_L1REQIE BIT(7) /*!< LPM L1 state request interrupt enable */ +#define CTL_L1RSREQ BIT(5) /*!< LPM L1 resume request */ +#define CTL_RSREQ BIT(4) /*!< resume request */ +#define CTL_SETSPS BIT(3) /*!< set suspend state */ +#define CTL_LOWM BIT(2) /*!< low-power mode at suspend state */ +#define CTL_CLOSE BIT(1) /*!< goes to close state */ +#define CTL_SETRST BIT(0) /*!< set USB reset */ + +/* USBD_INTF */ +#define INTF_STIF BIT(15) /*!< successful transfer interrupt flag (read only bit) */ +#define INTF_PMOUIF BIT(14) /*!< packet memory overrun/underrun interrupt flag (clear-only bit) */ +#define INTF_ERRIF BIT(13) /*!< error interrupt flag (clear-only bit) */ +#define INTF_WKUPIF BIT(12) /*!< wakeup interrupt flag (clear-only bit) */ +#define INTF_SPSIF BIT(11) /*!< suspend state interrupt flag (clear-only bit) */ +#define INTF_RSTIF BIT(10) /*!< reset interrupt flag (clear-only bit) */ +#define INTF_SOFIF BIT(9) /*!< start of frame interrupt flag (clear-only bit) */ +#define INTF_ESOFIF BIT(8) /*!< expected start of frame interrupt flag(clear-only bit) */ +#define INTF_L1REQ BIT(7) /*!< LPM L1 transaction is successfully received and acknowledged */ +#define INTF_DIR BIT(4) /*!< direction of transaction (read-only bit) */ +#define INTF_EPNUM BITS(0, 3) /*!< endpoint number (read-only bit) */ + +/* USBD_STAT */ +#define STAT_RXDP BIT(15) /*!< data plus line status */ +#define STAT_RXDM BIT(14) /*!< data minus line status */ +#define STAT_LOCK BIT(13) /*!< locked the USB */ +#define STAT_SOFLN BITS(11, 12) /*!< SOF lost number */ +#define STAT_FCNT BITS(0, 10) /*!< frame number count */ + +/* USBD_DADDR */ +#define DADDR_USBEN BIT(7) /*!< USB module enable */ +#define DADDR_USBDAR BITS(0, 6) /*!< USB device address */ + +/* USBD_EPxCS */ +#define EPxCS_RX_ST BIT(15) /*!< endpoint reception successful transferred */ +#define EPxCS_RX_DTG BIT(14) /*!< endpoint reception data PID toggle */ +#define EPxCS_RX_STA BITS(12, 13) /*!< endpoint reception status bits */ +#define EPxCS_SETUP BIT(11) /*!< endpoint setup transaction completed */ +#define EPxCS_CTL BITS(9, 10) /*!< endpoint type control */ +#define EPxCS_KCTL BIT(8) /*!< endpoint kind control */ +#define EPxCS_TX_ST BIT(7) /*!< endpoint transmission successful transfer */ +#define EPxCS_TX_DTG BIT(6) /*!< endpoint transmission data toggle */ +#define EPxCS_TX_STA BITS(4, 5) /*!< endpoint transmission transfers status bits */ +#define EPxCS_ADDR BITS(0, 3) /*!< endpoint address */ + +/* USBD_LPMCS */ +#define LPMCS_BLSTAT BITS(4, 7) /*!< bLinkState value */ +#define LPMCS_REMWK BIT(3) /*!< bRemoteWake value */ +#define LPMCS_LPMACK BIT(1) /*!< LPM token acknowledge enable */ +#define LPMCS_LPMEN BIT(0) /*!< LPM support enable */ + +/* constants definitions */ +/* endpoint control and status register mask (no toggle fields) */ +#define EPCS_MASK (EPxCS_RX_ST|EPxCS_SETUP|EPxCS_CTL|EPxCS_KCTL|EPxCS_TX_ST|EPxCS_ADDR) + +/* EPxCS_CTL[1:0] endpoint type control */ +#define ENDP_TYPE(regval) (EPxCS_CTL & ((regval) << 9U)) + +#define EP_BULK ENDP_TYPE(0U) /* bulk transfers */ +#define EP_CONTROL ENDP_TYPE(1U) /* control transfers */ +#define EP_ISO ENDP_TYPE(2U) /* isochronous transfers */ +#define EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */ +#define EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK) + +/* endpoint kind control mask */ +#define EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK) + +/* EPxCS_TX_STA[1:0] status for tx transfer */ +#define ENDP_TXSTAT(regval) (EPxCS_TX_STA & ((regval) << 4U)) + +#define EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */ +#define EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */ +#define EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */ +#define EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */ +#define EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK) + +/* EPxCS_RX_STA[1:0] status for rx transfer */ +#define ENDP_RXSTAT(regval) (EPxCS_RX_STA & ((regval) << 12U)) + +#define EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */ +#define EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */ +#define EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */ +#define EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */ +#define EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK) + +/* endpoint receive/transmission counter register bit definitions */ +#define EPRCNT_BLKSIZ BIT(15) /* reception data block size */ +#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */ +#define EPRCNT_CNT BITS(0, 9) /* reception data count */ + +#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */ + +/* interrupt flag clear bits */ +#define CLR_STIF (~INTF_STIF) +#define CLR_PMOUIF (~INTF_PMOUIF) +#define CLR_ERRIF (~INTF_ERRIF) +#define CLR_WKUPIF (~INTF_WKUPIF) +#define CLR_SPSIF (~INTF_SPSIF) +#define CLR_RSTIF (~INTF_RSTIF) +#define CLR_SOFIF (~INTF_SOFIF) +#define CLR_ESOFIF (~INTF_ESOFIF) +#define CLR_L1REQ (~INTF_L1REQ) + +/* endpoint receive/transmission counter register bit offset */ +#define BLKSIZE_OFFSET (0x01U) +#define BLKNUM_OFFSET (0x05U) +#define RXCNT_OFFSET (0x0AU) + +#define TXCNT_OFFSET (0x0AU) + +#define BLKSIZE32_MASK (0x1fU) +#define BLKSIZE2_MASK (0x01U) + +#define BLKSIZE32_OFFSETMASK (0x05U) +#define BLKSIZE2_OFFSETMASK (0x01U) + +/* double buffer endpoint direction */ +typedef enum +{ + DBUF_EP_IN, /* double buffer IN direction */ + DBUF_EP_OUT, /* double buffer OUT direction */ + DBUF_EP_ERR, /* double buffer errer direction */ +}dbuf_ep_dir_enum; + +/* endpoints address */ +/* first bit is direction(0 for rx and 1 for tx) */ +#define EP0_OUT ((uint8_t)0x00) /* out endpoint 0 address */ +#define EP0_IN ((uint8_t)0x80) /* in endpoint 0 address */ +#define EP1_OUT ((uint8_t)0x01) /* out endpoint 1 address */ +#define EP1_IN ((uint8_t)0x81) /* in endpoint 1 address */ +#define EP2_OUT ((uint8_t)0x02) /* out endpoint 2 address */ +#define EP2_IN ((uint8_t)0x82) /* in endpoint 2 address */ +#define EP3_OUT ((uint8_t)0x03) /* out endpoint 3 address */ +#define EP3_IN ((uint8_t)0x83) /* in endpoint 3 address */ +#define EP4_OUT ((uint8_t)0x04) /* out endpoint 4 address */ +#define EP4_IN ((uint8_t)0x84) /* in endpoint 4 address */ +#define EP5_OUT ((uint8_t)0x05) /* out endpoint 5 address */ +#define EP5_IN ((uint8_t)0x85) /* in endpoint 5 address */ +#define EP6_OUT ((uint8_t)0x06) /* out endpoint 6 address */ +#define EP6_IN ((uint8_t)0x86) /* in endpoint 6 address */ +#define EP7_OUT ((uint8_t)0x07) /* out endpoint 7 address */ +#define EP7_IN ((uint8_t)0x87) /* in endpoint 7 address */ + +/* endpoints_identifier */ +#define EP0 ((uint8_t)0) /* endpoint 0 ID */ +#define EP1 ((uint8_t)1) /* endpoint 1 ID */ +#define EP2 ((uint8_t)2) /* endpoint 2 ID */ +#define EP3 ((uint8_t)3) /* endpoint 3 ID */ +#define EP4 ((uint8_t)4) /* endpoint 4 ID */ +#define EP5 ((uint8_t)5) /* endpoint 5 ID */ +#define EP6 ((uint8_t)6) /* endpoint 6 ID */ +#define EP7 ((uint8_t)7) /* endpoint 7 ID */ + +/* USBD operation macros */ + +/* set register value */ +#define USBD_REG_SET(reg, regvalue) ((reg) = (uint16_t)(regvalue)) + +/* get register value */ +#define USBD_REG_GET(reg) ((uint16_t)(reg)) + +#define _EP_ADDR_SET(ep_num, addr) USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK) | addr) + +/* tx or rx transfer status setting (bits EPTX_STA[1:0]) */ +#define USBD_ENDP_TX_STATUS_SET(ep_num, state) do {\ + register uint16_t _regval; \ + _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPTX_DTGMASK;\ + USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ +} while(0) + +#define USBD_ENDP_RX_STATUS_SET(ep_num, state) do {\ + register uint16_t _regval; \ + _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPRX_DTGMASK;\ + USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ +} while(0) + +/* tx or rx transfer status getting (bits EPxCS_RX_STA[1:0]) */ +#define USBD_ENDP_TX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_STA) +#define USBD_ENDP_RX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_STA) + +/* rx and tx transfer status setting (bits EPxCS_RX_STA[1:0] & EPxCS_TX_STA[1:0]) */ +#define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx) do {\ + register uint16_t _regval; \ + _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)(EPRX_DTGMASK | EPxCS_TX_STA) ;\ + USBD_REG_SET(USBD_EPxCS(ep_num), (((_regval) ^ (state_rx)) ^ (state_tx))); \ +} while(0) + +/* set and clear endpoint kind (bit EPxCS_KCTL) */ +#define USBD_ENDP_KIND_SET(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), ((USBD_REG_GET(USBD_EPxCS(ep_num)) | EPxCS_KCTL) & EPCS_MASK))) +#define USBD_ENDP_KIND_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPKCTL_MASK))) + +/* set and clear directly STATUS_OUT state of endpoint */ +#define USBD_STATUS_OUT_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) +#define USBD_STATUS_OUT_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) + +/* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */ +#define USBD_ENDP_RX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0x7FFFU & (uint16_t)EPCS_MASK)) +#define USBD_ENDP_TX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0xFF7FU & (uint16_t)EPCS_MASK)) + +/* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ +#define USBD_DTG_RX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_RX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) +#define USBD_DTG_TX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_TX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) + +/* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ +#define USBD_DTG_RX_CLEAR(ep_num) do {\ + if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_DTG) != 0U) {\ + USBD_DTG_RX_TOGGLE(ep_num);\ + } else {\ + }\ +} while(0) + +#define USBD_DTG_TX_CLEAR(ep_num) do {\ + if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_DTG) != 0U) {\ + USBD_DTG_TX_TOGGLE(ep_num);\ + } else {\ + }\ +} while(0) + +/* set and clear directly double buffered feature of endpoint */ +#define USBD_ENDP_DOUBLE_BUF_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) +#define USBD_ENDP_DOUBLE_BUF_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) + +/* toggle SW_BUF bit in the double buffered endpoint */ +#define USBD_SWBUF_TX_TOGGLE(ep_num) USBD_DTG_RX_TOGGLE(ep_num) +#define USBD_SWBUF_RX_TOGGLE(ep_num) USBD_DTG_TX_TOGGLE(ep_num) + +#endif /* USBD_REGS_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h new file mode 100644 index 0000000000..58a85d6cfc --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h @@ -0,0 +1,221 @@ +/*! + \file usbd_std.h + \brief USB standard definitions + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_STD_H +#define USBD_STD_H + +#include "usbd_core.h" +#include + +#ifndef NULL +#define NULL 0U +#endif + +/* constants definitions */ +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /* device qualifier descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /* configuration descriptor length */ + +#define USBD_LANGID_STR_IDX 0x00U /* language ID string index */ +#define USBD_MFC_STR_IDX 0x01U /* manufacturer string index */ +#define USBD_PRODUCT_STR_IDX 0x02U /* product string index */ +#define USBD_SERIAL_STR_IDX 0x03U /* serial string index */ +#define USBD_CONFIG_STR_IDX 0x04U /* configuration string index */ +#define USBD_INTERFACE_STR_IDX 0x05U /* interface string index */ + +#define USB_STANDARD_REQ 0x00U /* standard request */ +#define USB_CLASS_REQ 0x20U /* device class request */ +#define USB_VENDOR_REQ 0x40U /* vendor request */ +#define USB_REQ_MASK 0x60U /* request type mask */ + +#define USB_REQTYPE_DEVICE 0x00U /* request recipient is device */ +#define USB_REQTYPE_INTERFACE 0x01U /* request recipient is interface */ +#define USB_REQTYPE_ENDPOINT 0x02U /* request recipient is endpoint */ +#define USB_REQ_RECIPIENT_MASK 0x1fU /* request recipient mask */ + +#define USBREQ_GET_STATUS 0x00U /* Get_Status standard requeset */ +#define USBREQ_CLEAR_FEATURE 0x01U /* Clear_Feature standard requeset */ +#define USBREQ_SET_FEATURE 0x03U /* Set_Feature standard requeset */ +#define USBREQ_SET_ADDRESS 0x05U /* Set_Address standard requeset */ +#define USBREQ_GET_DESCRIPTOR 0x06U /* Get_Descriptor standard requeset */ +#define USBREQ_GET_CONFIGURATION 0x08U /* Get_Configuration standard requeset */ +#define USBREQ_SET_CONFIGURATION 0x09U /* Set_Configuration standard requeset */ +#define USBREQ_GET_INTERFACE 0x0AU /* Get_Interface standard requeset */ +#define USBREQ_SET_INTERFACE 0x0BU /* Set_Interface standard requeset */ + +#define USB_DESCTYPE_DEVICE 0x01U /* device descriptor type */ +#define USB_DESCTYPE_CONFIGURATION 0x02U /* configuration descriptor type */ +#define USB_DESCTYPE_STRING 0x03U /* string descriptor type */ +#define USB_DESCTYPE_INTERFACE 0x04U /* interface descriptor type */ +#define USB_DESCTYPE_ENDPOINT 0x05U /* endpoint descriptor type */ +#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /* device qualifier descriptor type */ +#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /* other speed configuration descriptor type */ +#define USB_DESCTYPE_BOS 0x0FU /* BOS descriptor type */ + +#define USB_STATUS_REMOTE_WAKEUP 2U /* USB is in remote wakeup status */ +#define USB_STATUS_SELF_POWERED 1U /* USB is in self powered status */ + +#define USB_FEATURE_ENDP_HALT 0U /* USB has endpoint halt feature */ +#define USB_FEATURE_REMOTE_WAKEUP 1U /* USB has endpoint remote wakeup feature */ +#define USB_FEATURE_TEST_MODE 2U /* USB has endpoint test mode feature */ + +#define ENG_LANGID 0x0409U /* english language ID */ +#define CHN_LANGID 0x0804U /* chinese language ID */ + +#define USB_EPTYPE_MASK 0x03U + +#define USB_DEVICE_DESC_SIZE 0x12U + +/* USB device exported macros */ +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) +#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) + +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) + +#define WIDE_STRING(string) _WIDE_STRING(string) +#define _WIDE_STRING(string) L##string + +#define USBD_STRING_DESC(string) \ + (void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(string)]; \ + }) { \ + sizeof(WIDE_STRING(string)) + 2U - 2U, \ + USB_DESCTYPE_STRING, \ + WIDE_STRING(string) \ + } + +typedef struct +{ + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_descriptor_header_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_descriptor_device_struct; + +#pragma pack(1) + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_descriptor_configuration_struct; + +#pragma pack() + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_descriptor_interface_struct; + +#pragma pack(1) + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ +} usb_descriptor_endpoint_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +}usb_descriptor_language_id_struct; + +#pragma pack() + +/* function declarations */ +/* USB setup transaction processing */ +uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev); +/* USB out transaction processing */ +uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); +/* USB in transaction processing */ +uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); + +/* handle USB standard device request */ +uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +/* handle device class request */ +uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +/* handle USB vendor request */ +uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); + +/* decode setup data packet */ +void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +/* handle USB enumeration error event */ +void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req); + +#endif /* USBD_STD_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c new file mode 100644 index 0000000000..4af7b03469 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c @@ -0,0 +1,455 @@ +/*! + \file usbd_core.c + \brief USB device driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_core.h" +#include "usbd_std.h" + +uint32_t g_interrupt_mask = 0U; +uint32_t g_free_buf_addr = ENDP_BUF_ADDR; + +usbd_ep_buf_struct *pbuf_reg = (usbd_ep_buf_struct *)USBD_RAM; + +/*! + \brief device core register initialization + \param[in] none + \param[out] none + \retval none +*/ +void usbd_core_init (usbd_core_handle_struct *pudev) +{ + /* disable remote wakeup feature */ + pudev->remote_wakeup = 0U; + + /* just reset the CLOSE bit */ + USBD_REG_SET(USBD_CTL, CTL_SETRST); + + /* may be need wait some time(tSTARTUP) ... */ + + /* clear SETRST bit in USBD_CTL register */ + USBD_REG_SET(USBD_CTL, 0U); + + /* clear all pending interrupts */ + USBD_REG_SET(USBD_INTF, 0U); + + /* set allocation buffer address */ + USBD_REG_SET(USBD_BADDR, BUFFER_ADDRESS & 0xFFF8U); + + g_interrupt_mask = IER_MASK; + +#ifdef LPM_ENABLED + /* enable L1REQ interrupt */ + USBD_REG_SET(USBD_LPMCS, LPMCS_LPMACK | LPMCS_LPMEN); +#endif /* LPM_ENABLED */ + + /* enable all interrupts mask bits */ + USBD_REG_SET(USBD_CTL, g_interrupt_mask); +} + +/*! + \brief free buffer used from application by toggling the SW_BUF byte + \param[in] ep_num: endpoint identifier (0..7) + \param[in] dir: endpoint direction which can be OUT(0) or IN(1) + \param[out] none + \retval None +*/ +void user_buffer_free (uint8_t ep_num, uint8_t dir) +{ + if (DBUF_EP_OUT == dir) { + USBD_SWBUF_RX_TOGGLE(ep_num); + } else if (DBUF_EP_IN == dir) { + USBD_SWBUF_TX_TOGGLE(ep_num); + } else { + /* no operation */ + } +} + +/*! + \brief device core register configure when stop device + \param[in] none + \param[out] none + \retval none +*/ +void usbd_core_deinit (void) +{ + /* disable all interrupts and set USB reset */ + USBD_REG_SET(USBD_CTL, CTL_SETRST); + + /* clear all interrupt flags */ + USBD_REG_SET(USBD_INTF, 0U); + + /* close device */ + USBD_REG_SET(USBD_CTL, CTL_SETRST | CTL_CLOSE); +} + +/*! + \brief endpoint initialization + \param[in] pudev: pointer to USB core instance + \param[in] buf_kind: kind of buffer + \param[in] pep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +void usbd_ep_init (usbd_core_handle_struct *pudev, usbd_epkind_enum buf_kind, void *ep_desc) +{ + usb_descriptor_endpoint_struct *desc_ep = (usb_descriptor_endpoint_struct *)ep_desc; + + uint8_t ep_num = desc_ep->bEndpointAddress & 0x0FU; + uint32_t reg_value = 0; + + /* set the endpoint type */ + switch (desc_ep->bmAttributes & USB_EPTYPE_MASK) { + case ENDP_CONTROL: + reg_value = EP_CONTROL; + break; + case ENDP_BULK: + reg_value = EP_BULK; + break; + case ENDP_INT: + reg_value = EP_INTERRUPT; + break; + case ENDP_ISOC: + reg_value = EP_ISO; + break; + default: + break; + } + + USBD_REG_SET(USBD_EPxCS(ep_num), reg_value | ep_num); + + reg_value = desc_ep->wMaxPacketSize; + + if (desc_ep->bEndpointAddress >> 7U) { + usb_ep_struct *ep = &pudev->in_ep[ep_num]; + + ep->maxpacket = reg_value; + + /* set the endpoint transmit buffer address */ + (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; + + reg_value = (reg_value + 1U) & ~1U; + + g_free_buf_addr += reg_value; + + if (ENDP_DBL_BUF == buf_kind) { + USBD_ENDP_DOUBLE_BUF_SET(ep_num); + + (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; + + g_free_buf_addr += reg_value; + + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); + } else { + /* configure the endpoint status as NAK status */ + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); + } + } else { + usb_ep_struct *ep = &pudev->out_ep[ep_num]; + + ep->maxpacket = reg_value; + + if (ENDP_DBL_BUF == buf_kind) { + USBD_ENDP_DOUBLE_BUF_SET(ep_num); + + USBD_DTG_TX_TOGGLE(ep_num); + + /* set the endpoint transmit buffer address */ + (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; + + if (reg_value > 62U) { + reg_value = (reg_value + 31U) & ~31U; + (pbuf_reg + ep_num)->tx_count = (uint16_t)(((reg_value << 5U) - 1U) | 0x8000U); + } else { + reg_value = (reg_value + 1U) & ~1U; + (pbuf_reg + ep_num)->tx_count = (uint16_t)(reg_value << 9U); + } + + g_free_buf_addr += reg_value; + } + + reg_value = desc_ep->wMaxPacketSize; + + /* set the endpoint receive buffer address */ + (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; + + if (reg_value > 62U) { + reg_value = (reg_value + 31U) & ~31U; + (pbuf_reg + ep_num)->rx_count = (uint16_t)(((reg_value << 5U) - 1U) | 0x8000U); + } else { + reg_value = (reg_value + 1U) & ~1U; + (pbuf_reg + ep_num)->rx_count = (uint16_t)(reg_value << 9U); + } + + if (ENDP_DBL_BUF == buf_kind) { + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); + } else { + /* configure the endpoint status as NAK status */ + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_NAK); + } + } +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] pudev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint8_t ep_num = ep_addr & 0x7F; + + if (ep_addr >> 7) { + USBD_DTG_TX_CLEAR(ep_num); + + /* configure the endpoint status as DISABLED */ + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_DISABLED); + } else { + USBD_DTG_RX_CLEAR(ep_num); + + /* configure the endpoint status as DISABLED */ + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); + } +} + +/*! + \brief endpoint prepare to receive data + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] buf_len: buffer length + \param[out] none + \retval none +*/ +void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + usb_ep_struct *ep; + uint8_t ep_num = ep_addr & 0x7FU; + + ep = &pudev->out_ep[ep_num]; + + /* configure the transaction level parameters */ + ep->trs_buf = pbuf; + ep->trs_len = buf_len; + + /* enable endpoint to receive */ + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); +} + +/*! + \brief endpoint prepare to transmit data + \param[in] pudev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] buf_len: buffer length + \param[out] none + \retval none +*/ +void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + __IO uint32_t len = 0U; + uint8_t ep_num = ep_addr & 0x7FU; + usb_ep_struct *ep = &pudev->in_ep[ep_num]; + + /* configure the transaction level parameters */ + ep->trs_buf = pbuf; + ep->trs_len = buf_len; + ep->trs_count = 0U; + + /* transmit length is more than one packet */ + if (ep->trs_len > ep->maxpacket) { + len = ep->maxpacket; + } else { + len = ep->trs_len; + } + + usbd_ep_data_write(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, (uint16_t)len); + (pbuf_reg + ep_num)->tx_count = (uint16_t)len; + + /* enable endpoint to transmit */ + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); +} + +/*! + \brief set an endpoint to stall status + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint8_t ep_num = ep_addr & 0x7FU; + usb_ep_struct *ep; + + if (ep_addr >> 7U) { + ep = &pudev->in_ep[ep_num]; + + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_STALL); + } else { + ep = &pudev->out_ep[ep_num]; + + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_STALL); + } + + ep->stall = 1U; + + if (0U == ep_num) { + /* control endpoint need to be stalled in two directions */ + USBD_ENDP_RX_TX_STATUS_SET(ep_num, EPRX_STALL, EPTX_STALL); + } +} + +/*! + \brief clear endpoint stalled status + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint8_t ep_num = ep_addr & 0x7FU; + usb_ep_struct *ep; + + if (ep_addr >> 7U) { + ep = &pudev->in_ep[ep_num]; + + /* clear endpoint data toggle bit */ + USBD_DTG_TX_CLEAR(ep_num); + + /* clear endpoint stall status */ + USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); + } else { + ep = &pudev->out_ep[ep_num]; + + /* clear endpoint data toggle bit */ + USBD_DTG_RX_CLEAR(ep_num); + + /* clear endpoint stall status */ + USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); + } + + ep->stall = 0U; +} + +/*! + \brief get the endpoint status + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval endpoint status +*/ +uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr) +{ + if (ep_addr >> 7U) { + return (uint8_t)USBD_ENDP_TX_STATUS_GET((ep_addr & 0x7FU)); + } else { + return (uint8_t)USBD_ENDP_RX_STATUS_GET(ep_addr); + } +} + +/*! + \brief write datas from user fifo to USBRAM + \param[in] user_fifo: pointer to user fifo + \param[in] usbram_addr: the allocation buffer address of the endpoint + \param[in] bytes: the bytes count of the write datas + \param[out] none + \retval none +*/ +void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) +{ + uint32_t n; + uint32_t *write_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); + + for (n = 0U; n < (bytes + 1U) / 2U; n++) { + *write_addr++ = *((__packed uint16_t*)user_fifo); + user_fifo += 2U; + } +} + +/*! + \brief read datas from USBRAM to user fifo + \param[in] user_fifo: pointer to user fifo + \param[in] usbram_addr: the allocation buffer address of the endpoint + \param[in] bytes: the bytes count of the read datas + \param[out] none + \retval none +*/ +void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) +{ + uint32_t n; + uint32_t *read_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); + + for (n = 0U; n < (bytes + 1U) / 2U; n++) { + *((__packed uint16_t*)user_fifo) = (uint16_t)*read_addr++; + user_fifo += 2U; + } +} + +/*! + \brief get the received data length + \param[in] pudev: pointer to USB core instance + \param[in] ep_num: endpoint identifier which is in (0..7) + \param[out] none + \retval received data length +*/ +uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num) +{ + return (uint16_t)pudev->out_ep[ep_num].trs_count; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c new file mode 100644 index 0000000000..f9e58fe3d9 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c @@ -0,0 +1,458 @@ +/*! + \file usbd_int.c + \brief USB device power interrupt routines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_int.h" + +extern uint32_t g_interrupt_mask; +extern __IO uint8_t g_suspend_enabled; +extern __IO uint8_t g_remote_wakeup_on; +extern __IO uint8_t g_ESOF_count; + +#ifdef LPM_ENABLED +__IO uint32_t L1_remote_wakeup = 0U; +__IO uint32_t L1_resume = 0U; +__IO uint32_t besl = 0U; +#endif /* LPM_ENABLED */ + +static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev); +static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev); + +/*! + \brief USB interrupt events service routine + \param[in] none + \param[out] none + \retval none +*/ +void usbd_isr (void) +{ + __IO uint16_t interrupt_flag = 0U; + __IO uint16_t ctlr = 0U; + + interrupt_flag = USBD_REG_GET(USBD_INTF); + + if (g_interrupt_mask & INTF_STIF & interrupt_flag) { + /* the endpoint successful transfer interrupt service */ + usbd_intf_lpst(&usb_device_dev); + } + + if (g_interrupt_mask & INTF_WKUPIF & interrupt_flag) { + /* clear wakeup interrupt flag in INTF */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_WKUPIF); + + /* USB wakeup interrupt handle */ + usbd_intf_wakeup(&usb_device_dev); + +#ifdef LPM_ENABLED + /* clear L1 remote wakeup flag */ + L1_remote_wakeup = 0; +#endif /* LPM_ENABLED */ + } + + if (g_interrupt_mask & INTF_SPSIF & interrupt_flag) { + if(!(USBD_REG_GET(USBD_CTL) & CTL_RSREQ)) { + /* process library core layer suspend routine*/ + usbd_intf_suspend(&usb_device_dev); + + /* clear of suspend interrupt flag bit must be done after setting of CTLR_SETSPS */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SPSIF); + } + } + + if (g_interrupt_mask & INTF_SOFIF & interrupt_flag) { + /* clear SOF interrupt flag in INTF */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SOFIF); + + /* USB SOF interrupt handle */ + usbd_intf_sof(&usb_device_dev); + } + + if (g_interrupt_mask & INTF_ESOFIF & interrupt_flag) { + /* clear ESOF interrupt flag in INTF */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_ESOFIF); + + /* USB ESOF interrupt handle */ + usbd_intf_esof(&usb_device_dev); + } + + if (g_interrupt_mask & INTF_RSTIF & interrupt_flag) { + /* clear reset interrupt flag in INTF */ + USBD_REG_SET(USBD_INTF, (uint16_t)CLR_RSTIF); + + /* USB reset interrupt handle */ + usbd_intf_reset(&usb_device_dev); + } + +#ifdef LPM_ENABLED + if (g_interrupt_mask & INTF_L1REQ & interrupt_flag) { + /* clear L1 ST bit in LPM INTF */ + USBD_REG_SET(USBD_INTF, CLR_L1REQ); + + /* read BESL field from subendpoint0 register which coressponds to HIRD parameter in LPM spec */ + besl = (USBD_REG_GET(USBD_LPMCS) & LPMCS_BLSTAT) >> 4; + + /* read BREMOTEWAKE bit from subendpoint0 register which corresponding to bRemoteWake bit in LPM request */ + L1_remote_wakeup = (USBD_REG_GET(USBD_LPMCS) & LPMCS_REMWK) >> 8; + + /* process USB device core layer suspend routine */ + /* enter USB model in suspend and system in low power mode (DEEP_SLEEP mode) */ + usbd_intf_suspend(&usb_device_dev); + } +#endif /* LPM_ENABLED */ +} + +/*! + \brief handle USB high priority successful transfer event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev) +{ + uint8_t ep_num = 0U; + + __IO uint16_t int_status = 0U; + __IO uint16_t ep_value = 0U; + + usb_ep_struct *ep = NULL; + + /* wait till interrupts are not pending */ + while (0U != ((int_status = USBD_INTF) & (uint16_t)INTF_STIF)) { + /* get endpoint number and the value of control and state register */ + ep_num = (uint8_t)(int_status & INTF_EPNUM); + ep_value = USBD_EPxCS(ep_num); + + if (0U == (int_status & INTF_DIR)) { + /* handle the in direction transaction */ + + ep = &(pudev->in_ep[ep_num]); + + if (0U != (ep_value & EPxCS_TX_ST)) { + /* clear successful transmit interrupt flag */ + USBD_ENDP_TX_STAT_CLEAR(ep_num); + + if (ep_value & EPxCS_TX_DTG) { + /* just handle single buffer situation */ + ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; + } + + /* maybe mutiple packets */ + ep->trs_buf += ep->trs_count; + + usbd_in_transaction(pudev, ep_num); + } + } else { + /* handle the out direction transaction */ + + uint16_t count = 0U; + + ep = &(pudev->out_ep[ep_num]); + + if (0U != (ep_value & EPxCS_RX_ST)) { + /* clear successful receive interrupt flag */ + USBD_ENDP_RX_STAT_CLEAR(ep_num); + + if (ep_value & EPxCS_TX_DTG) { + count = (pbuf_reg + ep_num)->tx_count & (uint16_t)EPRCNT_CNT; + + if (0U != count) { + usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, count); + } + } else { + count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; + + if (0U != count) { + usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); + } + } + + user_buffer_free(ep_num, DBUF_EP_OUT); + + /* maybe mutiple packets */ + ep->trs_count += count; + ep->trs_buf += count; + ep->trs_len -= count; + + if ((0U == ep->trs_len) || (count < ep->maxpacket)) { + USBD_ENDP_TX_STATUS_SET(ep_num, EPRX_NAK); + + /* enter data OUT status */ + usbd_out_transaction(pudev, ep_num); + + ep->trs_count = 0U; + } + } + } + } + + return USBD_OK; +} + +/*! + \brief handle USB low priority successful transfer event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev) +{ + uint8_t ep_num = 0U; + + __IO uint16_t int_status = 0U; + __IO uint16_t ep_value = 0U; + + usb_ep_struct *ep = NULL; + + /* wait till interrupts are not pending */ + while (0U != ((int_status = USBD_REG_GET(USBD_INTF)) & (uint16_t)INTF_STIF)) { + /* get endpoint number and the value of control and state register */ + ep_num = (uint8_t)(int_status & INTF_EPNUM); + ep_value = USBD_REG_GET(USBD_EPxCS(ep_num)); + + if (0U == (int_status & INTF_DIR)) { + /* handle the in direction transaction */ + + ep = &(pudev->in_ep[ep_num]); + + if (0U != (ep_value & EPxCS_TX_ST)) { + /* clear successful transmit interrupt flag */ + USBD_ENDP_TX_STAT_CLEAR(ep_num); + + /* just handle single buffer situation */ + ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; + + /* maybe mutiple packets */ + ep->trs_buf += ep->trs_count; + + usbd_in_transaction(pudev, ep_num); + } + } else { + /* handle the out direction transaction */ + + uint16_t count = 0U; + + ep = &(pudev->out_ep[ep_num]); + + if (0U != (ep_value & EPxCS_RX_ST)) { + /* clear successful receive interrupt flag */ + USBD_ENDP_RX_STAT_CLEAR(ep_num); + + count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; + + if (0U != count) { + if (0U != (ep_value & EPxCS_SETUP)) { + /* handle setup packet */ + usbd_ep_data_read(&(pudev->setup_packet[0]), pbuf_reg->rx_addr, count); + + /* enter setup status */ + usbd_setup_transaction(pudev); + + return USBD_OK; + } else { + usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); + } + } + + /* maybe mutiple packets */ + ep->trs_count += count; + ep->trs_buf += count; + ep->trs_len -= count; + + if ((0U == ep->trs_len) || (count < ep->maxpacket)) { + /* enter data OUT status */ + usbd_out_transaction(pudev, ep_num); + + ep->trs_count = 0U; + } else { + usbd_ep_rx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); + } + } + } + } + + return USBD_OK; +} + +/*! + \brief handle USB SOF event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev) +{ + /* if necessary, user can add code here */ + if (NULL != usbd_int_fops) { + usbd_int_fops->SOF(pudev); + } + + return USBD_OK; +} + +/*! + \brief handle USB expect SOF event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev) +{ + /* control resume time by ESOFs */ + if (g_ESOF_count > 0U) { + g_ESOF_count--; + + if (0U == g_ESOF_count) { + if (1U == g_remote_wakeup_on) { + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_RSREQ); + + g_remote_wakeup_on = 0U; + } else { + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); + + g_ESOF_count = 3U; + g_remote_wakeup_on = 1U; + } + } + } + + return USBD_OK; +} + +/*! + \brief handle USB reset event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev) +{ + uint8_t i; + + g_free_buf_addr = ENDP_BUF_ADDR; + + /* configure endpoint 0 buffer */ + pbuf_reg->tx_addr = (uint16_t)g_free_buf_addr; + g_free_buf_addr += USBD_EP0_MAX_SIZE; + + pbuf_reg->rx_addr = (uint16_t)g_free_buf_addr; + g_free_buf_addr += USBD_EP0_MAX_SIZE; + + /* configure endpoint 0 Rx count */ + if (USBD_EP0_MAX_SIZE > 62U) { + pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE << 5U) - 1U) | 0x8000U; + } else { + pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE + 1U) & ~1U) << 9U; + } + + pudev->in_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; + pudev->out_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; + + /* set endpoints address */ + for (i = 0U; i < EP_COUNT; i++) + { + _EP_ADDR_SET(i, i); + } + + /* set device address as default address 0 */ + USBD_REG_SET(USBD_DADDR, DADDR_USBEN); + + /* clear endpoint 0 register */ + USBD_REG_SET(USBD_EPxCS(EP0), USBD_EPxCS(EP0)); + + USBD_REG_SET(USBD_EPxCS(EP0), EP_CONTROL | EPRX_VALID | EPTX_NAK); + + pudev->status = USBD_DEFAULT; + + return USBD_OK; +} + +/*! + \brief handle USB suspend event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev) +{ + /* store the device current status */ + pudev->prev_status = pudev->status; + + /* set device in suspended state */ + pudev->status = USBD_SUSPENDED; + + /* enter USB in suspend and mcu system in low power mode */ + if (g_suspend_enabled) { + usbd_suspend(); + } else { + /* if not possible then resume after xx ms */ + g_ESOF_count = 3U; + } + + return USBD_OK; +} + +/*! + \brief handle USB wakeup event + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev) +{ + /* restore the old status */ + pudev->status = pudev->prev_status; + +#ifdef LPM_ENABLED + if ((0U == g_remote_wakeup_on) && (0U == L1_resume)) { + resume_mcu(); + } else if (1U == g_remote_wakeup_on) { + /* no operation */ + } else { + L1_resume = 0U; + } +#else + if (0U == g_remote_wakeup_on) { + resume_mcu(); + } +#endif /* LPM_ENABLED */ + + return USBD_OK; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c new file mode 100644 index 0000000000..febdd765f4 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c @@ -0,0 +1,159 @@ +/*! + \file usbd_pwr.c + \brief USB device power management driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_pwr.h" + +#ifdef USBD_LOWPWR_MODE_ENABLE +static void lowpower_mode_exit (void); +#endif /* USBD_LOWPWR_MODE_ENABLE */ + +__IO uint8_t g_ESOF_count = 0U; +__IO uint8_t g_suspend_enabled = 1U; +__IO uint8_t g_remote_wakeup_on = 0U; + +#ifdef LPM_ENABLED +extern __IO uint32_t L1_resume; +#endif /* LPM_ENABLED */ + +/*! + \brief USB wakeup first operation is to wakeup mcu + \param[in] none + \param[out] none + \retval none +*/ +void resume_mcu (void) +{ + /* clear low_power mode bit in USBD_CTL */ + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM)); + +#ifdef USBD_LOWPWR_MODE_ENABLE + + /* restore normal operations */ + lowpower_mode_exit(); + +#endif /* USBD_LOWPWR_MODE_ENABLE */ + + /* clear SETSPS bit */ + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS)); +} + +#ifdef USBD_LOWPWR_MODE_ENABLE + +/*! + \brief restore system clocks and power while exiting suspend mode + \param[in] none + \param[out] none + \retval none +*/ +static void lowpower_mode_exit (void) +{ + /* restore system clock */ + + /* enable HSE */ + rcu_osci_on(RCU_HXTAL); + + /* wait till HSE is ready */ + while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB)); + + /* enable PLL */ + rcu_osci_on(RCU_PLL_CK); + + /* wait till PLL is ready */ + while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB)); + + /* select PLL as system clock source */ + rcu_system_clock_source_config(RCU_CKSYSSRC_PLL); + + /* wait till PLL is used as system clock source */ + while(0x08 != rcu_system_clock_source_get()); + + /* low power sleep on exit disabled */ + system_lowpower_reset(SCB_LPM_DEEPSLEEP); +} + +#endif /* USBD_LOWPWR_MODE_ENABLE */ + +/*! + \brief set USB device to suspend mode + \param[in] none + \param[out] none + \retval none +*/ +void usbd_suspend (void) +{ + /* set usb module to suspend and low-power mode */ + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM); + +#ifdef USBD_LOWPWR_MODE_ENABLE + + /* check wakeup flag is set */ + if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) { + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + } else { + /* clear wakeup interrupt flag */ + USBD_REG_SET(USBD_INTF, CLR_WKUPIF); + + /* clear set_suspend flag */ + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS); + } + +#endif /* USBD_LOWPWR_MODE_ENABLE */ +} + +/*! + \brief start to remote wakeup + \param[in] none + \param[out] none + \retval none +*/ +void usbd_remote_wakeup_active(void) +{ + resume_mcu(); + +#ifdef LPM_ENABLED + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ); + + L1_resume = 1U; +#else + g_remote_wakeup_on = 1U; + + g_ESOF_count = 15U; + USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); +#endif /* LPM_ENABLED */ +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c new file mode 100644 index 0000000000..582d614fac --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c @@ -0,0 +1,868 @@ +/*! + \file usbd_std.c + \brief USB device stand routines + \note about USB standard, please refer to the USB2.0 protocol + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_std.h" + +uint8_t g_device_address = 0U; + +/* USB enumeration handle functions */ +static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req); + +static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, + uint8_t index, + uint16_t *pLen); + +static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, + uint8_t index, + uint16_t *pLen); + +static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, + uint8_t index, + uint16_t *pLen); + +#ifdef LPM_ENABLED +static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen); +#endif /* LPM_ENABLED */ + +/* standard device request handler */ +static void (*standard_device_request[])(usbd_core_handle_struct *pudev, usb_device_req_struct *req) = +{ + usbd_getstatus, + usbd_clearfeature, + usbd_reserved, + usbd_setfeature, + usbd_reserved, + usbd_setaddress, + usbd_getdescriptor, + usbd_setdescriptor, + usbd_getconfiguration, + usbd_setconfiguration, + usbd_getinterface, + usbd_setinterface, + usbd_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t* (*standard_descriptor_get[])(usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = +{ + usbd_device_descriptor_get, + usbd_configuration_descriptor_get, + usbd_string_descriptor_get +}; + +/*! + \brief USB setup stage processing + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev) +{ + usb_device_req_struct req; + + usbd_setup_request_parse (pudev, &req); + + switch (req.bmRequestType & USB_REQ_MASK) { + /* standard device request */ + case USB_STANDARD_REQ: + usbd_standard_request(pudev, &req); + break; + /* device class request */ + case USB_CLASS_REQ: + usbd_device_class_request(pudev, &req); + break; + /* vendor defined request */ + case USB_VENDOR_REQ: + usbd_vendor_request(pudev, &req); + break; + default: + usbd_ep_stall(pudev, 0x00U); + break; + } + return USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) +{ + usb_ep_struct *ep = &pudev->out_ep[ep_num]; + + if (0U == ep_num) { + if (0U != pudev->ctl_count) { + if (ep->trs_len > ep->maxpacket) { + /* one data packet has been received, update trs_len */ + ep->trs_len -= ep->maxpacket; + + /* continue to receive remain data */ + usbd_ep_rx(pudev, EP0_OUT, ep->trs_buf, (uint16_t)ep->trs_len); + } else { + if (USBD_CONFIGURED == pudev->status) { + /* device class handle */ + pudev->class_data_handler(pudev, USBD_RX, EP0); + } + + /* enter the control transaction status stage */ + USBD_CONTRL_STATUS_TX(); + + pudev->ctl_count = 0U; + } + } else { + /* clear endpoint status_out status */ + USBD_STATUS_OUT_CLEAR(EP0); + } + } else { + if (USBD_CONFIGURED == pudev->status) { + pudev->class_data_handler(pudev, USBD_RX, ep_num); + } + } + return USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) +{ + usb_ep_struct *ep = &pudev->in_ep[ep_num]; + + if (0U == ep_num) { + if (0U != pudev->ctl_count) { + if (ep->trs_len > ep->maxpacket) { + /* one data packet has been transmited, update trs_len */ + ep->trs_len -= ep->maxpacket; + + /* continue to transmit remain data */ + usbd_ep_tx (pudev, EP0_IN, ep->trs_buf, (uint16_t)ep->trs_len); + + usbd_ep_rx (pudev, 0U, NULL, 0U); + } else { +#ifndef USB_DFU + /* transmit length is maxpacket multiple, so send zero length packet */ + if ((0U == (ep->trs_len % ep->maxpacket)) && (ep->trs_len < pudev->ctl_count)) { + usbd_ep_tx (pudev, EP0_IN, NULL, 0U); + + pudev->ctl_count = 0U; + + usbd_ep_rx (pudev, 0U, NULL, 0U); + } else +#endif /* USB_DFU */ + { + ep->trs_len = 0U; + + if (USBD_CONFIGURED == pudev->status) { + pudev->class_data_handler(pudev, USBD_TX, EP0); + } + + USBD_CONTRL_STATUS_RX(); + + pudev->ctl_count = 0U; + } + } + } else { + if (0U != g_device_address) { + USBD_REG_SET(USBD_DADDR, DADDR_USBEN | g_device_address); + g_device_address = 0U; + } + } + } else { + ep->trs_len -= ep->trs_count; + + if (0U == ep->trs_len) { + if (USBD_CONFIGURED == pudev->status) { + pudev->class_data_handler(pudev, USBD_TX, ep_num); + } + } else { + usbd_ep_tx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); + } + } + + return USBD_OK; +} + +/*! + \brief handle USB standard device request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* call device request handle function */ + (*standard_device_request[req->bRequest])(pudev, req); + + return USBD_OK; +} + +/*! + \brief handle USB device class request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + usbd_status_enum ret; + + switch (pudev->status) { + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* call device class handle function */ + ret = (usbd_status_enum)(pudev->class_req_handler(pudev, req)); + + if ((0U == req->wLength) && (USBD_OK == ret)) { + /* no data stage */ + USBD_CONTRL_STATUS_TX(); + } + } else { + usbd_enum_error(pudev, req); + } + break; + default: + usbd_enum_error(pudev, req); + break; + } + + return USBD_OK; +} + +/*! + \brief handle USB vendor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device operation status +*/ +uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* added by user */ + + return USBD_OK; +} + +/*! + \brief no operation, just for reserved + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no operation */ +} + +#ifdef LPM_ENABLED +/*! + \brief get BOS descriptor + \param[in] pudev: pointer to USB device instance + \param[in] pLen: data length pointer + \param[out] none + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen) +{ + *pLen = pudev->bos_desc[2] | ((uint16_t)pudev->bos_desc[3] << 8); + + return pudev->bos_desc; +} + +#endif /* LPM_ENABLED */ + +/*! + \brief get the device descriptor + \param[in] pudev: pointer to USB device instance + \param[in] index: no use + \param[out] pLen: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + *pLen = pudev->dev_desc[0]; + + return pudev->dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] pudev: pointer to USB device instance + \brief[in] index: no use + \param[out] pLen: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + *pLen = pudev->config_desc[2]; + + return pudev->config_desc; +} + +/*! + \brief get string descriptor + \param[in] pudev: pointer to USB device instance + \param[in] index: string descriptor index + \param[out] pLen: pointer to string length + \retval none +*/ +static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + uint8_t *desc = pudev->strings[index]; + + *pLen = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr; + uint16_t config_status = 0x0000U; + uint16_t endp_status = 0x0000U; + + switch(req->bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQTYPE_DEVICE: + switch (pudev->status) { + case USBD_ADDRESSED: + case USBD_CONFIGURED: + +#ifdef USBD_SELF_POWERED + config_status = USB_STATUS_SELF_POWERED; +#endif /* USBD_SELF_POWERED */ + + if (pudev->remote_wakeup) { + config_status |= USB_STATUS_REMOTE_WAKEUP; + } + + usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); + break; + default: + break; + } + break; + case USB_REQTYPE_INTERFACE: + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + case USB_REQTYPE_ENDPOINT: + /* get enndpoint address */ + ep_addr = LOWBYTE(req->wIndex); + + switch (pudev->status) { + case USBD_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_enum_error(pudev, req); + } + break; + case USBD_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) { + if(pudev->in_ep[ep_addr & 0x7FU].stall) { + endp_status = 0x0001U; + } + } else { + if (pudev->out_ep[ep_addr].stall) { + endp_status = 0x0001U; + } + } + usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&endp_status, 2U); + break; + + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Clear_Feature request + \param[in] pudev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval none +*/ +static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr = 0U; + + switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQTYPE_DEVICE: + switch (pudev->status) { + case USBD_ADDRESSED: + case USBD_CONFIGURED: + /* clear device remote wakeup feature */ + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + pudev->remote_wakeup = 0U; + pudev->class_req_handler(pudev, req); + USBD_CONTRL_STATUS_TX(); + } else if (USB_FEATURE_TEST_MODE == req->wValue) { + /* can not clear test_mode feature */ + usbd_enum_error(pudev, req); + } else { + /* no operation */ + } + break; + default: + break; + } + break; + case USB_REQTYPE_INTERFACE: + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error (pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* no operation */ + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + case USB_REQTYPE_ENDPOINT: + /* get endpoint address */ + ep_addr = LOWBYTE(req->wIndex); + + switch (pudev->status) { + case USBD_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_enum_error(pudev, req); + } + break; + case USBD_CONFIGURED: + /* clear endpoint halt feature */ + if (USB_FEATURE_ENDP_HALT == req->wValue) { + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_clear_stall(pudev, ep_addr); + } + } + + pudev->class_req_handler(pudev, req); + + USBD_CONTRL_STATUS_TX(); + break; + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Set_Feature request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr = 0U; + + switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQTYPE_DEVICE: + switch (pudev->status) { + case USBD_ADDRESSED: + case USBD_CONFIGURED: + /* set device remote wakeup feature */ + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + pudev->remote_wakeup = 1U; + + USBD_CONTRL_STATUS_TX(); + } + break; + default: + break; + } + break; + case USB_REQTYPE_INTERFACE: + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* no operation */ + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + case USB_REQTYPE_ENDPOINT: + /* get endpoint address */ + ep_addr = LOWBYTE(req->wIndex); + + switch (pudev->status) { + case USBD_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_enum_error(pudev, req); + } + break; + case USBD_CONFIGURED: + /* set endpoint halt feature */ + if (USB_FEATURE_ENDP_HALT == req->wValue) { + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_stall(pudev, ep_addr); + } + } + USBD_CONTRL_STATUS_TX(); + break; + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Set_Address request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + if ((0U == req->wIndex) && (0U == req->wLength)) { + g_device_address = (uint8_t)(req->wValue) & 0x7FU; + + if (USBD_CONFIGURED == pudev->status) { + usbd_enum_error(pudev, req); + } else { + USBD_CONTRL_STATUS_TX(); + + if (0U != g_device_address) { + pudev->status = USBD_ADDRESSED; + } else { + pudev->status = USBD_DEFAULT; + } + } + } else { + usbd_enum_error(pudev, req); + } +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { + uint8_t *pbuf = NULL; + uint8_t desc_type = (uint8_t)(req->wValue >> 8); + uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; + uint16_t len = 0U; + + if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { + /* call corresponding descriptor get function */ + pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); + } +#ifdef LPM_ENABLED + else if (USB_DESCTYPE_BOS == desc_type) { + pbuf = usbd_bos_descriptor_get(pudev, &len); + } +#endif /* LPM_ENABLED */ + else { + usbd_enum_error(pudev, req); + } + + if ((0U != len) && (0U != req->wLength)) { + len = MIN(len, req->wLength); + + usbd_ep_tx (pudev, EP0_IN, pbuf, len); + } + } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { + if (NULL != pudev->class_req_handler) { + /* get device class special descriptor */ + pudev->class_req_handler(pudev, req); + } + } else { + + } +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no handle */ +} + +/*! + \brief handle USB Get_Configuration request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint32_t usbd_default_config = 0U; + + if (req->wLength != 1U) { + usbd_enum_error(pudev, req); + } else { + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_ep_tx (pudev, EP0_IN, (uint8_t *)&usbd_default_config, 1U); + break; + case USBD_CONFIGURED: + usbd_ep_tx (pudev, EP0_IN, &pudev->config_num, 1U); + break; + default: + usbd_enum_error(pudev, req); + break; + } + } +} + +/*! + \brief handle USB Set_Configuration request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_CFG_MAX_NUM) { + usbd_enum_error(pudev, req); + } else { + switch (pudev->status) { + case USBD_ADDRESSED: + if (cfgidx){ + pudev->config_num = cfgidx; + pudev->status = USBD_CONFIGURED; + pudev->class_init(pudev, cfgidx); + USBD_CONTRL_STATUS_TX(); + } else { + USBD_CONTRL_STATUS_TX(); + } + break; + case USBD_CONFIGURED: + if (0U == cfgidx) { + pudev->status = USBD_ADDRESSED; + pudev->config_num = cfgidx; + pudev->class_deinit(pudev, cfgidx); + USBD_CONTRL_STATUS_TX(); + } else if (cfgidx != pudev->config_num) { + /* clear old configuration */ + pudev->class_deinit(pudev, pudev->config_num); + + /* set new configuration */ + pudev->config_num = cfgidx; + pudev->class_init(pudev, cfgidx); + USBD_CONTRL_STATUS_TX(); + } else { + USBD_CONTRL_STATUS_TX(); + } + break; + default: + break; + } + } +} + +/*! + \brief handle USB Get_Interface request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + if (NULL != pudev->class_req_handler) { + pudev->class_req_handler(pudev, req); + } + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } +} + +/*! + \brief handle USB Set_Interface request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + switch (pudev->status) { + case USBD_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USBD_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + if (NULL != pudev->class_req_handler) { + pudev->class_req_handler(pudev, req); + } + + USBD_CONTRL_STATUS_TX(); + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } +} + +/*! + \brief handle USB SynchFrame request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no handle */ +} + +/*! + \brief decode setup data packet + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t *setup_data = pudev->setup_packet; + + req->bmRequestType = *setup_data; + req->bRequest = *(uint8_t *)(setup_data + 1U); + req->wValue = SWAPBYTE (setup_data + 2U); + req->wIndex = SWAPBYTE (setup_data + 4U); + req->wLength = SWAPBYTE (setup_data + 6U); + + pudev->ctl_count = req->wLength; +} + +/*! + \brief handle USB enumeration error event + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req) +{ + usbd_ep_stall(pudev, EP0); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h new file mode 100644 index 0000000000..b50f903086 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h @@ -0,0 +1,304 @@ +/*! + \file usb_core.h + \brief USB core driver header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USB_CORE_H +#define USB_CORE_H + +#include "usb_conf.h" +#include "usb_regs.h" +#include "usb_defines.h" + +/* constants definitions */ +#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */ +#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */ +#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */ + +#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT +#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) + +/* USB core status */ +typedef enum +{ + USB_OK = 0, /* USB core OK status */ + USB_FAIL /* USB core fail status */ +}usb_status_enum; + +/* USB host channel status */ +typedef enum +{ + HC_IDLE = 0, /* USB host channel idle status */ + HC_XF, /* USB host channel transfer status */ + HC_HALTED, /* USB host channel halted status */ + HC_NAK, /* USB host channel nak status */ + HC_NYET, /* USB host channel nyet status */ + HC_STALL, /* USB host channel stall status */ + HC_TRACERR, /* USB host channel tracerr status */ + HC_BBERR, /* USB host channel bberr status */ + HC_DTGERR, /* USB host channel dtgerr status */ +}hc_status_enum; + +/* USB URB(USB request block) state */ +typedef enum +{ + URB_IDLE = 0, /* USB URB idle status */ + URB_DONE, /* USB URB done status */ + URB_NOTREADY, /* USB URB not ready status */ + URB_ERROR, /* USB URB error status */ + URB_STALL, /* USB URB stall status */ + URB_PING /* USB URB ping status */ +}urb_state_enum; + +/* USB core configuration */ +typedef struct +{ + uint8_t core_id; /* USB core id */ + uint8_t core_speed; /* USB core speed */ + uint8_t phy_interface; /* USB PHY interface */ + uint8_t host_channel_num; /* USB host channel number */ + uint8_t dev_endp_num; /* USB device endpoint number */ + uint8_t sof_output; /* USB SOF output */ + uint8_t low_power; /* USB low power */ + uint16_t max_packet_size; /* USB max packet size */ + uint16_t max_fifo_size; /* USB fifo size */ +}usb_core_cfgs_struct; + +typedef enum +{ + USBD_OK = 0, /* USB device ok status */ + USBD_BUSY, /* USB device busy status */ + USBD_FAIL, /* USB device fail stauts */ +}usbd_status_enum; + +/* USB control transfer state */ +typedef enum +{ + USB_CTRL_IDLE = 0, /* USB control transfer idle state */ + USB_CTRL_SETUP, /* USB control transfer setup state */ + USB_CTRL_DATA_IN, /* USB control transfer data in state */ + USB_CTRL_DATA_OUT, /* USB control transfer data out state */ + USB_CTRL_STATUS_IN, /* USB control transfer status in state*/ + USB_CTRL_STATUS_OUT, /* USB control transfer status out state */ + USB_CTRL_STALL /* USB control transfer stall state */ +}usbd_control_state_enum; + +/* USB transfer direction */ +typedef enum +{ + USB_RX = 0, /* receive direction type value */ + USB_TX /* transmit direction type value */ +}usb_dir_enum; + +/* USB endpoint in device mode */ +typedef struct +{ + uint8_t endp_type; /* USB endpoint type */ + uint8_t endp_frame; /* USB endpoint frame */ + uint32_t endp_mps; /* USB endpoint max packet size */ + + /* Transaction level variables */ + uint8_t *xfer_buff; /* USB transfer buffer */ + uint32_t xfer_len; /* USB transfer length */ + uint32_t xfer_count; /* USB transfer count */ + + uint32_t dma_addr; /* USBHS can use DMA */ +}usb_ep_struct; + +/* USB device standard request */ +typedef struct +{ + uint8_t bmRequestType; /* USB device request type */ + uint8_t bRequest; /* USB device request */ + uint16_t wValue; /* USB device request value */ + uint16_t wIndex; /* USB device request index */ + uint16_t wLength; /* USB device request length */ +}usb_device_req_struct; + +/* USB core device driver */ +typedef struct +{ + uint8_t config_num; /* USB configuration number */ + __IO uint8_t status; /* USB status */ + uint8_t ctl_status; /* USB control status */ + uint8_t prev_status; /* USB previous status */ + uint8_t connection_status; /* USB connection status */ + uint32_t remote_wakeup; /* USB remote wakeup */ + + /* transfer level variables */ + uint32_t remain_len; /* USB remain length */ + uint32_t sum_len; /* USB sum length */ + uint32_t ctl_len; /* USB control length */ + uint8_t setup_packet[8 * 3]; /* USB setup packet */ + + usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB in endpoint */ + usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB out endpoint */ + + uint8_t *dev_desc; /* device descriptor */ + uint8_t *config_desc; /* configuration descriptor */ + uint8_t* *strings; /* configuration strings */ + + /* device class handler */ + uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */ + uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */ + uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */ + uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */ +}dcd_dev_struct; + +/* USB core host mode channel */ +typedef struct +{ + uint8_t dev_addr; /* device address */ + uint8_t dev_speed; /* device speed */ + uint8_t DPID; /* endpoint transfer data pid */ + uint8_t endp_id; /* endpoint number */ + uint8_t endp_in; /* endpoint in */ + uint8_t endp_type; /* endpoint type */ + uint16_t endp_mps; /* endpoint max pactet size */ + uint16_t info; /* channel information */ + + uint8_t *xfer_buff; /* transfer buffer */ + uint32_t xfer_len; /* transfer length */ + uint32_t xfer_count; /* trasnfer count */ + + uint32_t err_count; /* USB transfer error count */ + + hc_status_enum status; /* channel status */ + urb_state_enum urb_state; /* URB state */ + + uint8_t data_tg_in; /* data in toggle */ + uint8_t data_tg_out; /* data out toggle */ +}usb_hostchannel_struct; + +/* USB core host driver */ +typedef struct +{ + uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */ + uint8_t connect_status; /* device connect status */ + usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */ + void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */ +}hcd_dev_struct; + +#ifdef USE_OTG_MODE + +/* USB core OTG-mode driver */ +typedef struct +{ + uint8_t OTG_State; /* OTG state */ + uint8_t OTG_PrevState; /* OTG previous state */ + uint8_t OTG_Mode; /* OTG mode */ +}otg_dev_struct; + +#endif /* USE_OTG_MODE */ + +/* USB core driver */ +typedef struct +{ + usb_core_cfgs_struct cfg; + +#ifdef USE_DEVICE_MODE + dcd_dev_struct dev; +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + hcd_dev_struct host; +#endif /* USE_HOST_MODE */ + +#ifdef USE_OTG_MODE + otg_dev_struct otg; +#endif /* USE_OTG_MODE */ + + void (*udelay) (const uint32_t usec); + void (*mdelay) (const uint32_t msec); +}usb_core_handle_struct; + +/* function declarations */ + +/* global APIs */ +/* initializes the USB controller registers and prepares the core device mode or host mode operation */ +usb_status_enum usb_core_init (usb_core_handle_struct *pudev); +/* initialize core parameters */ +usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id); +/* read a packet from the rx fifo associated with the endpoint */ +void* usb_fifo_read (uint8_t *dest, uint16_t len); +/* write a packet into the tx fifo associated with the endpoint */ +usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len); +/* flush a tx fifo or all tx fifos */ +usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num); +/* flush the entire rx fifo */ +usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev); +/* set operation mode (host or device) */ +usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode); + +/* host APIs */ +#ifdef USE_HOST_MODE + +/* initializes USB core for host mode */ +usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev); +/* enables the host mode interrupts */ +usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev); +/* initialize host channel */ +usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num); +/* halt channel */ +usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num); +/* prepare host channel for transferring packets */ +usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num); +/* reset host port */ +uint32_t usb_port_reset (usb_core_handle_struct *pudev); +/* control the VBUS to power */ +void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state); +/* stop the USB host and clean up fifos */ +void usb_host_stop (usb_core_handle_struct *pudev); + +#endif /* USE_HOST_MODE */ + +/* device APIs */ +#ifdef USE_DEVICE_MODE + +/* initialize USB core registers for device mode */ +usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev); +/* configures endpoint 0 to receive setup packets */ +void usb_ep0_startout (usb_core_handle_struct *pudev); +/* active remote wakeup signalling */ +void usb_remotewakeup_active (usb_core_handle_struct *pudev); +/* active USB core clock */ +void usb_clock_ungate (usb_core_handle_struct *pudev); +/* stop the device and clean up fifos */ +void usb_device_stop (usb_core_handle_struct *pudev); + +#endif /* USE_DEVICE_MODE */ + +#endif /* USB_CORE_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h new file mode 100644 index 0000000000..d9d1fd3c04 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h @@ -0,0 +1,128 @@ +/*! + \file usb_defines.h + \brief USB core defines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USB_DEFINES_H +#define USB_DEFINES_H + +#include "usb_conf.h" + +/* constants definitions */ +typedef enum +{ + USB_HS_CORE_ID = 0, + USB_FS_CORE_ID = 1 +}usb_core_id_enum; + +typedef enum +{ + USB_SPEED_UNKNOWN = 0, + USB_SPEED_LOW, + USB_SPEED_FULL, + USB_SPEED_HIGH +}usb_speed_enum; + +#ifndef NULL + #define NULL (void *)0 /*!< USB null marco value*/ +#endif /* NULL */ + +#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */ +#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */ + +#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */ +#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */ +#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */ +#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */ + +#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */ +#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */ +#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */ +#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */ + +#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */ +#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */ + +#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ +#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ + +#define GRSTATR_RPCKST_IN 2U /* in data packet received */ +#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* in transfer completed (generates an interrupt if poped) */ +#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */ +#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */ + +#define DEVICE_MODE 0U /* USB core in device mode */ +#define HOST_MODE 1U /* USB core in host mode */ +#define OTG_MODE 2U /* USB core in OTG mode */ + +#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */ +#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */ +#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */ +#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */ +#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */ + +#define RXSTAT_GOUT_NAK 1U /* global out NAK (triggers an interrupt) */ +#define RXSTAT_DATA_UPDT 2U /* out data packet received */ +#define RXSTAT_XFER_COMP 3U /* out transfer completed (triggers an interrupt) */ +#define RXSTAT_SETUP_COMP 4U /* setup transaction completed (triggers an interrupt) */ +#define RXSTAT_SETUP_UPDT 6U /* setup data packet received */ + +#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ +#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ +#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ +#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ + +#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */ +#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */ +#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */ +#define HC_PID_SETUP 3U /* host channel data PID is SETUP */ + +#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */ +#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */ +#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */ + +#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */ +#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */ +#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */ + +#define HCCHAR_CTRL 0U /* control channel type */ +#define HCCHAR_ISOC 1U /* synchronous channel type */ +#define HCCHAR_BULK 2U /* bulk channel type */ +#define HCCHAR_INTR 3U /* interrupt channel type */ + +#endif /* USB_DEFINES_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h new file mode 100644 index 0000000000..2e7d444381 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h @@ -0,0 +1,596 @@ +/*! + \file usb_regs.h + \brief USB FS cell registers definition and handle macros + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USB_REGS_H +#define USB_REGS_H + +#include "usb_conf.h" + +#define USBFS USBFS_BASE /*!< base address of USBFS registers */ + +/* registers location definitions */ +#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device in endpoint-x (x = 1..3) transfer length registers */ +#define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x)) /*!< locate host channel-x control registers */ +#define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x)) /*!< locate host channel-x interrupt flag registers */ +#define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x)) /*!< locate host channel-x interrupt enable registers */ +#define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x)) /*!< locate host channel-x transfer length registers */ +#define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x)) /*!< locate device in endpoint-x control registers */ +#define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x)) /*!< locate device out endpoint-x control registers */ +#define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x)) /*!< locate device in endpoint-x interrupt flag registers */ +#define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x)) /*!< locate device out endpoint-x interrupt flag registers */ +#define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x)) /*!< locate device in endpoint-x transfer length registers */ +#define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x)) /*!< locate device out endpoint-x transfer length registers */ +#define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x)) /*!< locate Device in endpoint-x transmit fifo status register */ +#define LOCATE_FIFO(x) (((x) + 1U) << 12U) /*!< locate FIFO-x memory */ + +/* registers definitions */ +#define USB_GOTGCS REG32(((USBFS) + 0x0000U)) /*!< global OTG control and status register */ +#define USB_GOTGINTF REG32(((USBFS) + 0x0004U)) /*!< global OTG interrupt flag register */ +#define USB_GAHBCS REG32(((USBFS) + 0x0008U)) /*!< global AHB control and status register */ +#define USB_GUSBCS REG32(((USBFS) + 0x000CU)) /*!< global USB control and status register */ +#define USB_GRSTCTL REG32(((USBFS) + 0x0010U)) /*!< global reset control register */ +#define USB_GINTF REG32(((USBFS) + 0x0014U)) /*!< global interrupt flag register */ +#define USB_GINTEN REG32(((USBFS) + 0x0018U)) /*!< global interrupt enable register */ +#define USB_GRSTATR REG32(((USBFS) + 0x001CU)) /*!< global receive status read register */ +#define USB_GRSTATP REG32(((USBFS) + 0x0020U)) /*!< global receive status read and pop register */ +#define USB_GRFLEN REG32(((USBFS) + 0x0024U)) /*!< global receive fifo length register */ +#define USB_HNPTFLEN REG32(((USBFS) + 0x0028U)) /*!< host non-periodic transmit fifo length register */ +#define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U)) /*!< device in endpoint 0 transmit fifo length register */ +#define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU)) /*!< host non-periodic transmint fifo/queue status register */ +#define USB_GCCFG REG32(((USBFS) + 0x0038U)) /*!< global core configuration register */ +#define USB_CID REG32(((USBFS) + 0x003CU)) /*!< core id register */ +#define USB_HPTFLEN REG32(((USBFS) + 0x0100U)) /*!< host periodic transmit fifo length register */ +#define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x))) /*!< device in endpoint transmit fifo length register */ + +#define USB_HCTL REG32(((USBFS) + 0x0400U)) /*!< host control register */ +#define USB_HFT REG32(((USBFS) + 0x0404U)) /*!< host frame interval register */ +#define USB_HFINFR REG32(((USBFS) + 0x0408U)) /*!< host frame information remaining register */ +#define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U)) /*!< host periodic transmit fifo/queue status register */ +#define USB_HACHINT REG32(((USBFS) + 0x0414U)) /*!< host all channels interrupt register */ +#define USB_HACHINTEN REG32(((USBFS) + 0x0418U)) /*!< host all channels interrupt enable register */ +#define USB_HPCS REG32(((USBFS) + 0x0440U)) /*!< host port control and status register */ +#define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ +#define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ +#define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ +#define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ + +#define USB_DCFG REG32(((USBFS) + 0x0800U)) /*!< device configuration register */ +#define USB_DCTL REG32(((USBFS) + 0x0804U)) /*!< device control register */ +#define USB_DSTAT REG32(((USBFS) + 0x0808U)) /*!< device status register */ +#define USB_DIEPINTEN REG32(((USBFS) + 0x0810U)) /*!< device in endpoint common interrupt enable register */ +#define USB_DOEPINTEN REG32(((USBFS) + 0x0814U)) /*!< device out endpoint common interrupt enable register */ +#define USB_DAEPINT REG32(((USBFS) + 0x0818U)) /*!< device all endpoints interrupt register */ +#define USB_DAEPINTEN REG32(((USBFS) + 0x081CU)) /*!< device all endpoints interrupt enable register */ +#define USB_DVBUSDT REG32(((USBFS) + 0x0828U)) /*!< device vbus discharge time register */ +#define USB_DVBUSPT REG32(((USBFS) + 0x082CU)) /*!< device vbus pulsing time register */ +#define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U)) /*!< device in endpoint fifo empty interrupt enable register */ +#define USB_DEP1INT REG32(((USBFS) + 0x0838U)) /*!< device endpoint 1 interrupt register */ +#define USB_DEP1INTEN REG32(((USBFS) + 0x083CU)) /*!< device endpoint 1 interrupt enable register */ +#define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U)) /*!< device in endpoint 1 interrupt enable register */ +#define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U)) /*!< device out endpoint 1 interrupt enable register */ +#define USB_DIEP0CTL REG32(((USBFS) + 0x0900U)) /*!< device in endpoint 0 control register */ +#define USB_DIEP0LEN REG32(((USBFS) + 0x0910U)) /*!< device in endpoint 0 transfer length register */ +#define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U)) /*!< device out endpoint 0 control register */ +#define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U)) /*!< device out endpoint 0 transfer length register */ +#define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x))) /*!< device in endpoint-x control register */ +#define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x))) /*!< device out endpoint-x control register */ +#define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x))) /*!< device in endpoint-x interrupt flag register */ +#define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x))) /*!< device out endpoint-x interrupt flag register */ +#define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x))) /*!< device in endpoint-x transfer length register */ +#define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x))) /*!< device out endpoint-x transfer length register */ +#define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x))) /*!< device in endpoint-x transmit fifo status register */ + +#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U)) /*!< power and clock register */ + +#define USB_FIFO(x) (®32(((USBFS) + LOCATE_FIFO(x)))) /*!< fifo memory */ + +/* global OTG control and status register bits definitions */ +#define GOTGCS_BSV BIT(19) /*!< B-Session valid */ +#define GOTGCS_ASV BIT(18) /*!< A-session valid */ +#define GOTGCS_DI BIT(17) /*!< debounce interval */ +#define GOTGCS_IDPS BIT(16) /*!< id pin status */ +#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ +#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ +#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ +#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ +#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ +#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ + +/* global OTG interrupt flag register bits definitions */ +#define GOTGINTF_DF BIT(19) /*!< debounce finish */ +#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ +#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ +#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ +#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ +#define GOTGINTF_SESEND BIT(2) /*!< session end */ + +/* global AHB control and status register bits definitions */ +#define GAHBCS_PTXFTH BIT(8) /*!< periodic tx fifo threshold */ +#define GAHBCS_TXFTH BIT(7) /*!< tx fifo threshold */ +#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + +/* global USB control and status register bits definitions */ +#define GUSBCS_FDM BIT(30) /*!< force device mode */ +#define GUSBCS_FHM BIT(29) /*!< force host mode */ +#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ +#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ +#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ + +/* global reset control register bits definitions */ +#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx fifo number */ +#define GRSTCTL_TXFF BIT(5) /*!< tx fifo flush */ +#define GRSTCTL_RXFF BIT(4) /*!< rx fifo flush */ +#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ +#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ +#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ + +/* global interrupt flag register bits definitions */ +#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ +#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ +#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ +#define GINTF_IDPSC BIT(28) /*!< id pin status change */ +#define GINTF_PTXFEIF BIT(26) /*!< periodic tx fifo empty interrupt flag */ +#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ +#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ +#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ +#define GINTF_ISOONCIF BIT(21) /*!< isochronous out transfer not complete interrupt flag */ +#define GINTF_ISOINCIF BIT(20) /*!< isochronous in transfer not complete interrupt flag */ +#define GINTF_OEPIF BIT(19) /*!< out endpoint interrupt flag */ +#define GINTF_IEPIF BIT(18) /*!< in endpoint interrupt flag */ +#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ +#define GINTF_ISOOPDIF BIT(14) /*!< isochronous out packet dropped interrupt flag */ +#define GINTF_ENUMF BIT(13) /*!< enumeration finished */ +#define GINTF_RST BIT(12) /*!< USB reset */ +#define GINTF_SP BIT(11) /*!< USB suspend */ +#define GINTF_ESP BIT(10) /*!< early suspend */ +#define GINTF_GONAK BIT(7) /*!< global out NAK effective */ +#define GINTF_GNPINAK BIT(6) /*!< global in non-periodic NAK effective */ +#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx fifo empty interrupt flag */ +#define GINTF_RXFNEIF BIT(4) /*!< rx fifo non-empty interrupt flag */ +#define GINTF_SOF BIT(3) /*!< start of frame */ +#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ +#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ +#define GINTF_COPM BIT(0) /*!< current operation mode */ + +/* global interrupt enable register bits definitions */ +#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ +#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ +#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ +#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ +#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx fifo empty interrupt enable */ +#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ +#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ +#define GINTEN_PXNCIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_ISOONCIE BIT(21) /*!< isochronous out transfer not complete interrupt enable */ +#define GINTEN_ISOINCIE BIT(20) /*!< isochronous in transfer not complete interrupt enable */ +#define GINTEN_OEPIE BIT(19) /*!< out endpoints interrupt enable */ +#define GINTEN_IEPIE BIT(18) /*!< in endpoints interrupt enable */ +#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ +#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous out packet dropped interrupt enable */ +#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ +#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ +#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ +#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ +#define GINTEN_GONAKIE BIT(7) /*!< global out NAK effective interrupt enable */ +#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic in NAK effective interrupt enable */ +#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic tx fifo empty interrupt enable */ +#define GINTEN_RXFNEIE BIT(4) /*!< receive fifo non-empty interrupt enable */ +#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ +#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ +#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ + +/* global receive fifo length register bits definitions */ +#define GRFLEN_RXFD BITS(0, 15) /*!< rx fifo depth */ + +/* host non-periodic transmit fifo length register bits definitions */ +#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic tx fifo depth */ +#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic tx RAM start address */ + +/* IN endpoint 0 transmit fifo length register bits definitions */ +#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< in endpoint 0 tx fifo depth */ +#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< in endpoint 0 tx RAM start address */ + +/* host non-periodic transmit fifo/queue status register bits definitions */ +#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic tx request queue */ +#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic tx request queue space */ +#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic tx fifo space */ +#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* global core configuration register bits definitions */ +#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ +#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ +#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ +#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ +#define GCCFG_PWRON BIT(16) /*!< power on */ + +/* core ID register bits definitions */ +#define CID_CID BITS(0, 31) /*!< core ID */ + +/* host periodic transmit fifo length register bits definitions */ +#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic tx fifo depth */ +#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic tx RAM start address */ + +/* device in endpoint transmit fifo length register bits definitions */ +#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< in endpoint tx fifo x depth */ +#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< in endpoint fifox tx x RAM start address */ + +/* host control register bits definitions */ +#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ + +/* host frame interval register bits definitions */ +#define HFT_FRI BITS(0, 15) /*!< frame interval */ + +/* host frame information remaining register bits definitions */ +#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ + +/* host periodic transmit fifo/queue status register bits definitions */ +#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic tx request queue */ +#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic tx request queue space */ +#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic tx fifo space */ +#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* host all channels interrupt register bits definitions */ +#define HACHINT_HACHINT BITS(0, 7) /*!< host all channel interrupts */ + +/* host all channels interrupt enable register bits definitions */ +#define HACHINTEN_CINTEN BITS(0, 7) /*!< channel interrupt enable */ + +/* host port control and status register bits definitions */ +#define HPCS_PS BITS(17, 18) /*!< port speed */ +#define HPCS_PP BIT(12) /*!< port power */ +#define HPCS_PLST BITS(10, 11) /*!< port line status */ +#define HPCS_PRST BIT(8) /*!< port reset */ +#define HPCS_PSP BIT(7) /*!< port suspend */ +#define HPCS_PREM BIT(6) /*!< port resume */ +#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ +#define HPCS_PE BIT(2) /*!< port enable */ +#define HPCS_PCD BIT(1) /*!< port connect detected */ +#define HPCS_PCST BIT(0) /*!< port connect status */ + +/* host channel-x control register bits definitions */ +#define HCHCTL_CEN BIT(31) /*!< channel enable */ +#define HCHCTL_CDIS BIT(30) /*!< channel disable */ +#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define HCHCTL_LSD BIT(17) /*!< low-speed device */ +#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* host channel-x interrupt flag register bits definitions */ +#define HCHINTF_DTER BIT(10) /*!< data toggle error */ +#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ +#define HCHINTF_BBER BIT(8) /*!< babble error */ +#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ +#define HCHINTF_NYET BIT(6) /*!< NYET */ +#define HCHINTF_ACK BIT(5) /*!< ACK */ +#define HCHINTF_NAK BIT(4) /*!< NAK */ +#define HCHINTF_STALL BIT(3) /*!< STALL */ +#define HCHINTF_CH BIT(1) /*!< channel halted */ +#define HCHINTF_TF BIT(0) /*!< transfer finished */ + +/* host channel-x interrupt enable register bits definitions */ +#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ +#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ +#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ +#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ +#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ +#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ +#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ +#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ +#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ +#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + +/* host channel-x transfer length register bits definitions */ +#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device control and status registers */ +/* device configuration registers bits definitions */ +#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +#define DCFG_DAR BITS(4, 10) /*!< device address */ +#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status out handshake */ +#define DCFG_DS BITS(0, 1) /*!< device speed */ + +/* device control registers bits definitions */ +#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ +#define DCTL_CGONAK BIT(10) /*!< clear global out NAK */ +#define DCTL_SGONAK BIT(9) /*!< set global out NAK */ +#define DCTL_CGINAK BIT(8) /*!< clear global in NAK */ +#define DCTL_SGINAK BIT(7) /*!< set global in NAK */ +#define DCTL_GONS BIT(3) /*!< global out NAK status */ +#define DCTL_GINS BIT(2) /*!< global in NAK status */ +#define DCTL_SD BIT(1) /*!< soft disconnect */ +#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + +/* device status registers bits definitions */ +#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ +#define DSTAT_SPST BIT(0) /*!< suspend status */ + +/* device in endpoint common interrupt enable registers bits definitions */ +#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit fifo empty interrupt enable bit */ +#define DIEPINTEN_IEPNEEN BIT(6) /*!< in endpoint NAK effective interrupt enable bit */ +#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint tx fifo underrun interrupt enable bit */ +#define DIEPINTEN_CITOEN BIT(3) /*!< control in timeout interrupt enable bit */ +#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device out endpoint common interrupt enable registers bits definitions */ +#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back setup packets interrupt enable bit */ +#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint rx fifo overrun interrupt enable bit */ +#define DOEPINTEN_STPFEN BIT(3) /*!< fifo phase finished interrupt enable bit */ +#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device all endpoints interrupt registers bits definitions */ +#define DAEPINT_OEPITB BITS(16, 21) /*!< device all out endpoint interrupt bits */ +#define DAEPINT_IEPITB BITS(0, 5) /*!< device all in endpoint interrupt bits */ + +/* device all endpoints interrupt enable registers bits definitions */ +#define DAEPINTEN_OEPIE BITS(16, 21) /*!< out endpoint interrupt enable */ +#define DAEPINTEN_IEPIE BITS(0, 3) /*!< in endpoint interrupt enable */ + +/* device Vbus discharge time registers bits definitions */ +#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ + +/* device Vbus pulsing time registers bits definitions */ +#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ + +/* device IN endpoint FIFO empty interrupt enable register bits definitions */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3) /*!< in endpoint tx FIFO empty interrupt enable bits */ + +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ + +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* device in endpoint-x interrupt flag register bits definitions */ +#define DIEPINTF_TXFE BIT(7) /*!< transmit fifo empty */ +#define DIEPINTF_IEPNE BIT(6) /*!< in endpoint NAK effective */ +#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint tx fifo underrun */ +#define DIEPINTF_CITO BIT(3) /*!< control in Timeout interrupt */ +#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DIEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device out endpoint-x interrupt flag register bits definitions */ +#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back setup packets */ +#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint rx fifo overrun */ +#define DOEPINTF_STPF BIT(3) /*!< setup phase finished */ +#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DOEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device in endpoint 0 transfer length register bits definitions */ +#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device out endpoint 0 transfer length register bits definitions */ +#define DOEP0LEN_STPCNT BITS(29, 30) /*!< setup packet count */ +#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device out endpoint-x transfer length register bits definitions */ +#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +#define DOEPLEN_STPCNT BITS(29, 30) /*!< setup packet count */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device in endpoint-x transmit fifo status register bits definitions */ +#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< in endpoint¡¯s tx fifo space remaining */ + +/* USB power and clock registers bits definition */ +#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ +#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ + +/* register options defines */ +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ + +#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ +#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ +#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ + +#define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */ + +#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U) /*!< tx fifo half empty */ +#define TXFIFO_EMPTY GAHBCS_TFEL(1U) /*!< tx fifo completely empty */ + +#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ + +#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ +#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ +#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ +#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ +#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ + +#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ + +#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ +#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ +#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ +#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ + +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ + +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ + +/* endpoints address */ + +/* first bit is direction(0 for Rx and 1 for Tx) */ +#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */ +#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */ +#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */ +#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */ +#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */ +#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */ +#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */ +#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */ + +/* enable global interrupt */ +#define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN) + +/* disable global interrupt */ +#define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN) + +/* get current operation mode */ +#define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM) + +/* read global interrupt flag */ +#define USB_CORE_INTR_READ(x) \ +do { \ + uint32_t global_intf = USB_GINTF; \ + (x) = global_intf & USB_GINTEN; \ +} while(0) + +/* read global interrupt flag */ +#define USB_DAOEP_INTR_READ(x) \ +do { \ + uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ + uint32_t dev_all_ep_int = USB_DAEPINT; \ + uint32_t out_ep_intb = DAEPINT_OEPITB; \ + (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ +} while(0) + +/* read out endpoint-x interrupt flag */ +#define USB_DOEP_INTR_READ(x, EpID) \ +do { \ + uint32_t out_epintf = USB_DOEPxINTF(EpID); \ + (x) = out_epintf & USB_DOEPINTEN; \ +} while(0) + +/* read all in endpoint interrupt flag */ +#define USB_DAIEP_INTR_READ(x) \ +do { \ + uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ + uint32_t dev_all_ep_int = USB_DAEPINT; \ + uint32_t in_ep_intb = DAEPINT_IEPITB; \ + (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ +} while(0) + + +/* read in endpoint-x interrupt flag */ +#define USB_DIEP_INTR_READ(x, EpID) \ +do { \ + uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \ + uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \ + uint32_t dev_inep_inten = USB_DIEPINTEN; \ + (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \ +} while(0) + +/* generate remote wakup signal */ +#define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP) + +/* no remote wakup signal generate */ +#define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP) + +/* generate soft disconnect */ +#define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD) + +/* no soft disconnect generate */ +#define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD) + +/* set device address */ +#define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U) + +/* check whether frame is even */ +#define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U)) + +/* read port status */ +#define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC)) + +/* usb clock initialize */ +#define USB_FSLSCLOCK_INIT(ClockFreq) \ +do { \ + USB_HCTL &= ~HCTL_CLKSEL; \ + USB_HCTL |= ClockFreq; \ +} while(0) + +/* get usb current speed */ +#define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17) + +/* get usb current frame */ +#define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU) + +#endif /* USB_REGS_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h new file mode 100644 index 0000000000..d82cb74f85 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h @@ -0,0 +1,216 @@ +/*! + \file usb_std.h + \brief USB 2.0 standard defines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USB_STD_H +#define USB_STD_H + +#include "usb_conf.h" + +/* constants definitions */ +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ +#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /*!< USB device configuration descriptor length */ +#define USB_IF_DESC_LEN 0x09U /*!< USB device interface descriptor length */ +#define USB_EP_DESC_LEN 0x07U /*!< USB device endpoint descriptor length */ +#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ + +/* bit 7 of bmRequestType: data phase transfer direction */ +#define USB_DIR_MASK 0x80U /*!< USB transfer direction mask */ +#define USB_DIR_OUT 0x00U /*!< USB transfer out direction */ +#define USB_DIR_IN 0x80U /*!< USB transfer in direction */ + +/* bit 6..5 of bmRequestType: request type */ +#define USB_STANDARD_REQ 0x00U /*!< USB standard request */ +#define USB_CLASS_REQ 0x20U /*!< USB class request */ +#define USB_VENDOR_REQ 0x40U /*!< USB vebdor request */ +#define USB_REQ_MASK 0x60U /*!< USB request mask */ + +/* bit 4..0 of bmRequestType: recipient type */ +#define USB_REQTYPE_DEVICE 0x00U /*!< USB device request type */ +#define USB_REQTYPE_INTERFACE 0x01U /*!< USB interface request type*/ +#define USB_REQTYPE_ENDPOINT 0x02U /*!< USB endpoint request type*/ +#define USB_REQTYPE_MASK 0x03U /*!< USB request type mask*/ + +/* bRequest value */ +#define USBREQ_GET_STATUS 0x00U /*!< USB get status request*/ +#define USBREQ_CLEAR_FEATURE 0x01U /*!< USB clear feature request*/ +#define USBREQ_SET_FEATURE 0x03U /*!< USB set feature request*/ +#define USBREQ_SET_ADDRESS 0x05U /*!< USB set address request*/ +#define USBREQ_GET_DESCRIPTOR 0x06U /*!< USB get descriptor request*/ +#define USBREQ_SET_DESCRIPTOR 0x07U /*!< USB set descriptor request*/ +#define USBREQ_GET_CONFIGURATION 0x08U /*!< USB get configuration request*/ +#define USBREQ_SET_CONFIGURATION 0x09U /*!< USB set configuration request*/ +#define USBREQ_GET_INTERFACE 0x0AU /*!< USB get interface request*/ +#define USBREQ_SET_INTERFACE 0x0BU /*!< USB set interface request*/ +#define USBREQ_SYNCH_FRAME 0x0CU /*!< USB synchronize frame request*/ + +/* descriptor types of usb specifications */ +#define USB_DESCTYPE_DEVICE 0x01U /*!< USB device descriptor type*/ +#define USB_DESCTYPE_CONFIGURATION 0x02U /*!< USB configuration descriptor type*/ +#define USB_DESCTYPE_STRING 0x03U /*!< USB string descriptor type*/ +#define USB_DESCTYPE_INTERFACE 0x04U /*!< USB interface descriptor type*/ +#define USB_DESCTYPE_ENDPOINT 0x05U /*!< USB endpoint descriptor type*/ +#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /*!< USB device qualtfier descriptor type*/ +#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /*!< USB other speed configuration descriptor type*/ +#define USB_DESCTYPE_INTERFACE_POWER 0x08U /*!< USB interface power descriptor type*/ + +#define USB_DESCTYPE_HID 0x21U /*!< USB HID descriptor type*/ +#define USB_DESCTYPE_HID_REPORT 0x22U /*!< USB HID report descriptor type*/ + +#define USB_DEVDESC_SIZE 18U /*!< USB device descriptor size*/ +#define USB_CFGDESC_SIZE 9U /*!< USB configure descriptor size*/ +#define USB_INTDESC_SIZE 9U /*!< USB interface descriptor size*/ +#define USB_EPDESC_SIZE 7U /*!< USB endpoint descriptor size*/ + +/* descriptor type and descriptor index */ +/* use the following values when USB host need to get descriptor */ +#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U) /*!< USB device operation marco */ +#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U) /*!< USB configuration operation marco */ +#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U) /*!< USB string operation marco */ +#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB interface operation marco */ +#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB endpoint operation marco */ +#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) /*!< USB device qualifier operation marco */ +#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) /*!< USB other speed configuration operation marco */ +#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U) /*!< USB interface power operation marco */ +#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U) /*!< USB HID report operation marco */ +#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U) /*!< USB HID operation marco */ + +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +/* supported classes */ +#define USB_MSC_CLASS 0x08U /*!< USB MSC class*/ +#define USB_HID_CLASS 0x03U /*!< USB HID class*/ + +/* interface descriptor field values for hid boot protocol */ +#define HID_BOOT_CODE 0x01U /*!< USB HID boot code*/ +#define HID_KEYBRD_BOOT_CODE 0x01U /*!< USB HID keyboard boot code*/ +#define HID_MOUSE_BOOT_CODE 0x02U /*!< USB HID mouse boot code*/ + +/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec + standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ +#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ + +#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \ + + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE)) /*!< USB host set configuration descriptor size */ + +#pragma pack(1) + +typedef union +{ + uint8_t data[8]; + + struct _setup_packet_struct + { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bRequest; /*!< request of setup packet */ + uint16_t wValue; /*!< value of setup packet */ + uint16_t wIndex; /*!< index of setup packet */ + uint16_t wLength; /*!< length of setup packet */ + } b; +}usb_setup_union; + +typedef struct +{ + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_descriptor_header_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_descriptor_device_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_descriptor_configuration_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_descriptor_interface_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an interrupt or isochrnous type */ +} usb_descriptor_endpoint_struct; + +typedef struct +{ + usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +}usb_descriptor_language_id_struct; + +#pragma pack() + +#endif /* USB_STD_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h new file mode 100644 index 0000000000..637f1b5654 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h @@ -0,0 +1,81 @@ +/*! + \file usbd_core.h + \brief USB device mode core driver header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_CORE_H +#define USBD_CORE_H + +#include "usbd_conf.h" +#include "usb_core.h" +#include "usbd_std.h" + +/* constants definitions */ +/* device status */ +#define USB_STATUS_DEFAULT 1U /* default status */ +#define USB_STATUS_ADDRESSED 2U /* addressed status */ +#define USB_STATUS_CONFIGURED 3U /* configured status */ +#define USB_STATUS_SUSPENDED 4U /* suspended status */ + +/* function declarations */ +/* initailizes the USB device-mode handler stack */ +void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); +/* endpoint initialization */ +void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc); +/* endpoint deinitialize */ +void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* endpoint prepare to receive data */ +void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +/* endpoint prepare to transmit data */ +void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); +/* transmit data on the control channel */ +usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); +/* receive data on the control channel */ +usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); +/* transmit status on the control channel */ +usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev); +/* receive status on the control channel */ +usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev); +/* set an endpoint to stall status */ +void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* clear endpoint stalled status */ +void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* flushes the fifos */ +void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* get the received data length */ +uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num); + +#endif /* USBD_CORE_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h new file mode 100644 index 0000000000..89f791d8d8 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h @@ -0,0 +1,57 @@ +/*! + \file usbd_int.h + \brief USB device mode interrupt handler header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_INT_H +#define USBD_INT_H + +#include "usbd_core.h" + +/* constants definitions */ +typedef struct +{ + uint8_t (*SOF) (usb_core_handle_struct *pudev); +}usbd_int_cb_struct; + +extern usbd_int_cb_struct *usbd_int_fops; + +/* function declaration */ +/* USB device-mode interrupts global service routine handler */ +uint32_t usbd_isr (usb_core_handle_struct *pudev); + +#endif /* USBD_INT_H */ + diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h new file mode 100644 index 0000000000..d8ad1a61db --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h @@ -0,0 +1,98 @@ +/*! + \file usbd_std.h + \brief USB 2.0 standard defines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_STD_H +#define USBD_STD_H + +#include "usb_std.h" +#include "usbd_core.h" +#include "usbd_conf.h" +#include + +/* constants definitions */ +#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/ +#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/ +#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/ +#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/ +#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/ +#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/ + +#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/ +#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/ + +#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/ +#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/ +#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/ + +#define ENG_LANGID 0x0409U /*!< USB english language id*/ +#define CHN_LANGID 0x0804U /*!< USB chinese language id*/ + +#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/ + +#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/ +#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/ + +#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/ + +#define WIDE_STRING(string) _WIDE_STRING(string) +#define _WIDE_STRING(string) L##string + +#define USBD_STRING_DESC(string) \ + (uint8_t *)&(struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(string)]; \ + }) { \ + sizeof(WIDE_STRING(string)) + 2U - 2U, \ + USB_DESCTYPE_STRING, \ + WIDE_STRING(string) \ + } + +#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) + +/* function declarations */ +/* USB device setup transaction*/ +usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev); +/* USB device out transaction*/ +usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); +/* USB device in transaction*/ +usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); +/* USB device enum error handle*/ +void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req); + +#endif /* USBD_STD_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h new file mode 100644 index 0000000000..8137444b50 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h @@ -0,0 +1,310 @@ +/*! + \file usbh_core.h + \brief header file for usbh_core.c + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_CORE_H +#define USBH_CORE_H + +#include "usbh_conf.h" +#include "usb_std.h" +#include "usb_core.h" + +/* constants definitions */ +#define MSC_CLASS 0x08 /*!< the MSC class define */ +#define HID_CLASS 0x03 /*!< the HID class define */ +#define MSC_PROTOCOL 0x50 /*!< the MSC protocal define */ +#define CBI_PROTOCOL 0x01 /*!< the CBI protocal define */ + +#define USBH_DEVICE_ADDRESS_DEFAULT 0U /*!< the default device address define */ +#define USBH_DEVICE_ADDRESS 1U /*!< the device address define */ +#define USBH_MAX_ERROR_COUNT 2U /*!< the max error count define */ + +#define HOST_USER_SELECT_CONFIGURATION 1U /*!< the user select configuration define */ +#define HOST_USER_CLASS_ACTIVE 2U /*!< the user class active define */ +#define HOST_USER_CLASS_SELECTED 3U /*!< the user class selected define */ +#define HOST_USER_CONNECTION 4U /*!< the user connecttion define */ +#define HOST_USER_DISCONNECTION 5U /*!< the user disconnection define */ +#define HOST_USER_UNRECOVERED_ERROR 6U /*!< the user unrecovered error define */ + +#define MAX_USBH_STATE_STACK_DEEP 4 /*!< the max state stack deep define */ +#define MAX_USBH_STATE_TABLE_NUM 10U /*!< the max state table number */ + +#define HOST_FSM_ID 0U /*!< the host state table id */ +#define ENUM_FSM_ID 1U /*!< the enum state table id */ +#define CMD_FSM_ID 2U /*!< the cmd state table id */ +#define CTRL_FSM_ID 3U /*!< the ctrl state table id */ +#define CLASS_REQ_FSM_ID 4U /*!< the class req state table id */ +#define CLASS_FSM_ID 5U /*!< the class state table id */ + +#define UP_STATE 100U /*!< up state define */ +#define GO_TO_UP_STATE_EVENT 100U /*!< go to up state event define */ + +#define HOST_HANDLE_TABLE_SIZE 9U /*!< the host handle table size define */ +/* the enum of host state */ +typedef enum +{ + HOST_IDLE = 0, /* the host idle state definition */ + HOST_DEV_ATTACHED, /* the host device attached state definition */ + HOST_DEV_DETACHED, /* the host device detached state definition */ + HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */ + HOST_ENUMERATION, /* the host enumeration state definition */ + HOST_CLASS_REQUEST, /* the host class request state definition */ + HOST_CLASS, /* the host class state definition */ + HOST_USER_INPUT, /* the host user input state definition */ + HOST_SUSPENDED, /* the host suspended state definition */ + HOST_ERROR /* the host error state definition */ +}host_state_enum; + +/* the enum of host event */ +typedef enum +{ + HOST_EVENT_ATTACHED = 0, /* the host attached event */ + HOST_EVENT_ENUM, /* the host enum event */ + HOST_EVENT_USER_INPUT, /* the host user input event */ + HOST_EVENT_CLASS_REQ, /* the host class request event */ + HOST_EVENT_CLASS, /* the host class event */ + HOST_EVENT_ERROR, /* the host error event */ + HOST_EVENT_DEV_DETACHED, /* the host device detached event */ + HOST_EVENT_IDLE /* the host idle event */ +}host_event_enum; + +/* the enum of enum state */ +typedef enum +{ + ENUM_IDLE = 0, /* the enum idle state definition */ + ENUM_SET_ADDR, /* the enum set address state definition */ + ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */ + ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */ + ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */ + ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */ + ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */ + ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */ + ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */ + ENUM_DEV_CONFIGURED /* the enum device configuration state definition */ +}enum_state_enum; + +/* the enum of ctrl state */ +typedef enum +{ + CTRL_IDLE = 0, /* the ctrl idle state definition */ + CTRL_SETUP, /* the ctrl setup state definition */ + CTRL_DATA, /* the ctrl data state definition */ + CTRL_STATUS, /* the ctrl status state definition */ + CTRL_ERROR, /* the ctrl error state definition */ + CTRL_STALLED, /* the ctrl stalled state definition */ + CTRL_COMPLETE /* the ctrl complete state definition */ +}ctrl_state_enum; + +/* the enum of host status */ +typedef enum +{ + USBH_OK = 0, /* the usbh ok status definition */ + USBH_BUSY, /* the usbh busy status definition */ + USBH_FAIL, /* the usbh fail status definition */ + USBH_NOT_SUPPORTED, /* the usbh not supported status definition */ + USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */ + USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */ + USBH_APPLY_DEINIT /* the usbh apply deinit status definition */ +}usbh_status_enum; + +/* the state of user action */ +typedef enum +{ + USBH_USER_NO_RESP = 0, /* the user no response */ + USBH_USER_RESP_OK = 1, /* the user response ok */ +}usbh_user_status_enum; + +/* control transfer information */ +typedef struct +{ + uint8_t hc_in_num; /* the host in channel number */ + uint8_t hc_out_num; /* the host out channel number */ + uint8_t ep0_size; /* the endpoint 0 max packet size */ + uint8_t error_count; /* the error count */ + uint16_t length; /* the length */ + uint16_t timer; /* the timer */ + uint8_t *buff; /* the buffer */ + usb_setup_union setup; /* the setup packet */ +}usbh_ctrl_struct; + +/* device property */ +typedef struct +{ + uint8_t address; /* the device address */ + uint8_t speed; /* the device speed */ + usb_descriptor_device_struct dev_desc; /* the device descripter */ + usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */ + usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */ + usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */ +}usbh_device_struct; + +/* user callbacks */ +typedef struct +{ + void (*init) (void); /* the user callback init function */ + void (*deinit) (void); /* the user callback deinit function */ + void (*device_connected) (void); /* the user callback device connected function */ + void (*device_reset) (void); /* the user callback device reset function */ + void (*device_disconnected) (void); /* the user callback device disconnected function */ + void (*over_current_detected) (void); /* the user callback over current detected function */ + void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */ + void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */ + void (*device_address_set) (void); /* the user callback set device address function */ + + void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, + usb_descriptor_interface_struct *itf_desc, + usb_descriptor_endpoint_struct *ep_desc); + /* the configuration descripter available function */ + + void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */ + void (*product_string) (void *prod_string); /* the user callback product string function */ + void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */ + void (*enumeration_finish) (void); /* the user callback enumeration finish function */ + usbh_user_status_enum (*user_input) (void); /* the user callback user input function */ + int (*user_application) (usb_core_handle_struct *pudev, uint8_t id); + /* the user callback user appliction function */ + void (*device_not_supported) (void); /* the user callback device not supported function */ + void (*unrecovered_error) (void); /* the user callback unrecovered error function */ +}usbh_user_callback_struct; + +/* the backup state struct */ +typedef struct +{ + host_state_enum host_backup_state; /* the host backup state */ + enum_state_enum enum_backup_state; /* the enum backup state */ + ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */ + uint8_t class_req_backup_state; /* the class request backup state */ + uint8_t class_backup_state; /* the class backup state */ +} backup_state_struct; + +/* host information */ +typedef struct +{ + backup_state_struct usbh_backup_state; /* the usbh backup state variable */ + usbh_ctrl_struct control; /* the control struct variable */ + usbh_device_struct device; /* the device struct variable */ + usbh_user_callback_struct *usr_cb; /* the user callback function */ + usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */ + void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */ +}usbh_host_struct; + +/* the action function definition */ +typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate); + +/* the state table struct */ +typedef struct +{ + uint8_t cur_state; /* the current state */ + uint8_t cur_event; /* the current event */ + uint8_t next_state; /* the next state */ + ACT_FUN event_action_fun; /* the event action function entry */ +} state_table_struct; + +/* the state stack struct */ +typedef struct +{ + uint8_t state; /* the state in state stack */ + state_table_struct* table; /* the table in state stack */ + uint8_t table_size; /* the table size in state stack */ +} usbh_state_stack_struct; + +/* the state regist table struct */ +typedef struct +{ + uint8_t id; /* the id of the state table */ + state_table_struct* table; /* the table entry to regist */ + uint8_t table_size; /* the table size to regist */ +} usbh_state_regist_table_struct; + +/* the state handle struct */ +typedef struct +{ + uint8_t usbh_current_state; /* current state */ + uint8_t usbh_current_state_table_size; /* current state table size */ + state_table_struct* usbh_current_state_table; /* current state table */ + + usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */ + int8_t usbh_current_state_stack_top; /* the current state top */ + + usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */ + uint8_t usbh_regist_state_table_num; /* the number of regist state table */ +} usbh_state_handle_struct; + +/* function declarations */ +/* the host core driver function */ +usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* initialize the host portion of the driver */ +uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); +/* check if the device is connected */ +uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev); +/* this function returns the last URBstate */ +urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num); +/* this function returns the last URBstate */ +uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num); +/* de-initialize host */ +usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct* pustate); + +/* the state core driver function */ +/* state core driver init */ +void scd_init (usbh_state_handle_struct* pustate); +/* state core driver table regist */ +void scd_table_regist (usbh_state_handle_struct* pustate, + state_table_struct* pstate_table, + uint8_t table_id, + uint8_t current_table_size); +/* state core driver begin */ +void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id); +/* state core driver move state */ +void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state); +/* state core driver event handle */ +usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct* pustate, + uint8_t event, + uint8_t state); +/* state core driver table push */ +void scd_table_push (usbh_state_handle_struct* pustate); +/* state core driver table pop */ +void scd_table_pop (usbh_state_handle_struct* pustate); +/* the function is only used to state move */ +usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* the function to the up state */ +usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); + +#endif /* USBH_CORE_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h new file mode 100644 index 0000000000..b9cf7c5f97 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h @@ -0,0 +1,73 @@ +/*! + \file usbh_ctrl.h + \brief header file for usbh_ctrl.c + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_CTRL_H +#define USBH_CTRL_H + +#include "usbh_core.h" +#include "usbh_usr.h" + +/* constants definitions */ +/* the enum of CTRL event */ +typedef enum +{ + CTRL_EVENT_IDLE = 0, /* the ctrl idle event */ + CTRL_EVENT_SETUP, /* the ctrl setup event */ + CTRL_EVENT_DATA, /* the ctrl data event */ + CTRL_EVENT_STATUS, /* the ctrl status event */ + CTRL_EVENT_COMPLETE, /* the ctrl complete event */ + CTRL_EVENT_ERROR, /* the ctrl error event */ + CTRL_EVENT_STALLED, /* the ctrl stalled event */ +}ctrl_event_enum; + +#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */ + +extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]; +extern uint8_t ctrl_polling_handle_flag; + +/* function declarations */ +/* the polling function of control transfer state handle */ +usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* send datas from the host channel */ +usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len); +/* send the setup packet to the device */ +usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num); +/* this function prepare a hc and start a transfer */ +uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num); + +#endif /* USBH_CTRL_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h new file mode 100644 index 0000000000..d387f15b76 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h @@ -0,0 +1,73 @@ +/*! + \file usbh_hcs.h + \brief header file for usbh_hcs.c + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_HCS_H +#define USBH_HCS_H + +#include "usbh_core.h" + +/* constants definitions */ +#define HC_MAX 8U +#define HC_OK 0x0000U +#define HC_USED 0x8000U +#define HC_ERROR 0xFFFFU +#define HC_USED_MASK 0x7FFFU + +/* function declarations */ +/* allocate a new channel for the pipe */ +uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr); +/* free all usb host channel */ +uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev); +/* free the usb host channel */ +uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index); +/* open a channel */ +uint8_t usbh_channel_open (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps); +/* modify a channel */ +uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps); + +#endif /* USBH_HCS_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h new file mode 100644 index 0000000000..468ebc37d7 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h @@ -0,0 +1,58 @@ +/*! + \file usbh_int.h + \brief USB host mode interrupt handler header file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_INT_H +#define USBH_INT_H + +#include "usb_core.h" + +/* constants definitions */ +typedef struct +{ + uint8_t (*sof) (usb_core_handle_struct *pudev); + uint8_t (*device_connected) (usb_core_handle_struct *pudev); + uint8_t (*device_disconnected) (usb_core_handle_struct *pudev); +}usbh_hcd_int_cb_struct; + +extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops; + +/* function declarations */ +/* handle global host interrupt */ +uint32_t usbh_isr (usb_core_handle_struct *pudev); + +#endif /* USBH_INT_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h new file mode 100644 index 0000000000..c4bc6cd91b --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h @@ -0,0 +1,101 @@ +/*! + \file usbh_std.h + \brief header file for usbh_std.c + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_STD_H +#define USBH_STD_H + +#include "usbh_core.h" +#include "usbh_usr.h" + +/* constants definitions */ +typedef enum +{ + ENUN_EVENT_IDLE = 0, /* the enum idle event */ + ENUM_EVENT_SET_ADDR, /* the enum set address event */ + ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */ + ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */ + ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */ + ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */ + ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */ + ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */ + ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */ + ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */ +}enum_event_enum; +/* standard feature selector for clear feature command */ +#define FEATURE_SELECTOR_ENDPOINT 0x00U +#define FEATURE_SELECTOR_DEVICE 0x01U + +#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */ +#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */ + +extern uint8_t usbh_cfg_desc[512]; +extern uint8_t enum_polling_handle_flag; +extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]; + +/* function declarations */ +/* the polling function of enumeration state */ +usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +/* get descriptor in usb host enumeration stage */ +void usbh_enum_desc_get (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + uint8_t *buf, + uint8_t req_type, + uint16_t value_idx, + uint16_t len); +/* set address in usb host enumeration stage */ +void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address); +/* set configuration in usb host enumeration stage */ +void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx); +/* parse the device descriptor */ +void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len); +/* parse the configuration descriptor */ +void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, + usb_descriptor_interface_struct *itf_desc, + usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], + uint8_t *buf, + uint16_t len); +/* parse the interface descriptor */ +void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf); +/* parse the endpoint descriptor */ +void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf); +/* parse the string descriptor */ +void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); +/* get the next descriptor header */ +usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr); + +#endif /* USBH_STD_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c new file mode 100644 index 0000000000..a2fa307efb --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c @@ -0,0 +1,974 @@ +/*! + \file usb_core.c + \brief USB core driver which can operate in host-mode and device-mode + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_core.h" + +static void usb_commonint_enable (usb_core_handle_struct *pudev); +static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev); + +/*! + \brief enable the commmon interrupts which are used in both device and host modes + \param[in] pudev: pointer to selected usb device + \param[out] none + \retval none +*/ +static void usb_commonint_enable (usb_core_handle_struct *pudev) +{ +#ifndef USE_OTG_MODE + + /* clear any pending USB interrupts */ + USB_GOTGINTF = 0xFFFFFFFFU; + +#endif /* USE_OTG_MODE */ + + USB_GINTF = 0xBFFFFFFF; + + /* enable the usb wakeup and suspend interrupts */ + USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + +#ifdef USE_OTG_MODE + + /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */ + USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ +} + +/*! + \brief soft reset of the OTG_FS core + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev) +{ + uint32_t count = 0U; + + /* enable core soft reset */ + USB_GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + do { + if (++count > 200000U) { + break; + } + } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST)); + + /* wait for addtional 3 PHY clocks */ + if (NULL != pudev->udelay) { + pudev->udelay(3U); + } + + return USB_OK; +} + +/*! + \brief write a packet into the tx fifo associated with the endpoint + \param[in] src: pointer to source buffer + \param[in] chep_num: channel or endpoint identifier which is in (0..3) + \param[in] len: packet length + \param[out] none + \retval operation status +*/ +usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len) +{ + uint32_t count32b = 0U, i = 0U; + __IO uint32_t *fifo = USB_FIFO(chep_num); + + count32b = (len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) { + *fifo = *((__packed uint32_t *)src); + + src += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the rx fifo associated with the endpoint + \param[in] dest: pointer to destination buffer + \param[in] len: packet length + \param[out] none + \retval void type pointer +*/ +void *usb_fifo_read (uint8_t *dest, uint16_t len) +{ + uint32_t i = 0U; + uint32_t count32b = (len + 3U) / 4U; + + __IO uint32_t *fifo = USB_FIFO(0U); + + for (i = 0U; i < count32b; i++) { + *(__packed uint32_t *)dest = *fifo; + + dest += 4U; + } + + return ((void *)dest); +} + +/*! + \brief initialize core parameters + \param[in] pudev: pointer to usb device + \param[in] core_id: USB core id + \param[out] none + \retval operation status +*/ +usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id) +{ + /* at startup the core is in FS mode */ + pudev->cfg.core_speed = USB_CORE_SPEED_FULL; + pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; + + /* initialize the core parameters */ + if (USB_FS_CORE_ID == core_id) { + + pudev->cfg.core_id = USB_FS_CORE_ID; + + /* set the host channel numbers */ + pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT; + + /* set the device endpoint numbers */ + pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT; + + /* fifo size is in terms of DWORD */ + pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN; + + /* OTG_FS core use embedded physical layer */ + pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; + + #ifdef USBFS_SOF_OUTPUT_ENABLED + pudev->cfg.sof_output = 1U; + #endif /* USBFS_SOF_OUTPUT_ENABLED */ + + #ifdef USBFS_LOW_PWR_MGMT_SUPPORT + pudev->cfg.low_power = 1U; + #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status_enum usb_core_init (usb_core_handle_struct *pudev) +{ + /* soft reset the core */ + usb_core_reset(pudev); + + /* active the transceiver and enable vbus sensing */ + USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + + /* set tx fifo empty level to half empty mode */ + USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; + +#ifndef VBUS_SENSING_ENABLED + USB_GCCFG |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + if(pudev->cfg.sof_output){ + USB_GCCFG |= GCCFG_SOFOEN; + } + + if (NULL != pudev->mdelay) { + pudev->mdelay(20U); + } + + +#ifdef USE_OTG_MODE + /* enable OTG features */ + USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; + USB_OTG_EnableCommonInt(pudev); + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief flush a tx fifo or all tx fifos + \param[in] pudev: pointer to usb device + \param[in] fifo_num: fifo number which is in (0..3) + \param[out] none + \retval operation status +*/ +usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num) +{ + uint32_t count = 0U; + + USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for tx fifo flush bit is set */ + do { + if (++count > 200000U) { + break; + } + } while (USB_GRSTCTL & GRSTCTL_TXFF); + + /* wait for 3 PHY clocks */ + if (NULL != pudev->udelay) { + pudev->udelay(3U); + } + + return USB_OK; +} + +/*! + \brief flush the entire rx fifo + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev) +{ + uint32_t count = 0U; + + USB_GRSTCTL = GRSTCTL_RXFF; + + /* wait for rx fifo flush bit is set */ + do { + if (++count > 200000U) { + break; + } + } while (USB_GRSTCTL & GRSTCTL_RXFF); + + /* wait for 3 PHY clocks */ + if (NULL != pudev->udelay) { + pudev->udelay(3U); + } + + return USB_OK; +} + +/*! + \brief set operation mode (host or device) + \param[in] pudev: pointer to usb device + \param[in] mode: operation mode which need to set + \arg HOST_MODE + \arg DEVICE_MODE + \param[out] none + \retval operation status +*/ +usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode) +{ + if (HOST_MODE == mode) { + USB_GUSBCS &= ~GUSBCS_FDM; + USB_GUSBCS |= GUSBCS_FHM; + } else if (DEVICE_MODE == mode) { + USB_GUSBCS &= ~GUSBCS_FHM; + USB_GUSBCS |= GUSBCS_FDM; + } else { + /* no operation */ + } + + if (NULL != pudev->mdelay) { + pudev->mdelay(50U); + } + + return USB_OK; +} + +#ifdef USE_HOST_MODE + +/*! + \brief initializes USB core for host mode + \param[in] pudev: pointer to selected usb host + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) +{ + uint32_t i = 0U; + __IO uint32_t nptxfifolen = 0U; + __IO uint32_t ptxfifolen = 0U; + +#ifdef USE_OTG_MODE + __IO uint32_t otgctl = 0; +#endif /* USE_OTG_MODE */ + + /* restart the PHY clock */ + USB_PWRCLKCTL = 0U; + + /* initialize host configuration register */ + if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { + USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ); + } else { + USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); + } + + /* reset USB port */ + usb_port_reset(pudev); + + /* configure data fifo sizes */ + if (USB_FS_CORE_ID == pudev->cfg.core_id) { + /* set rx fifo size */ + USB_GRFLEN = USBFS_RX_FIFO_SIZE; + + /* set non-periodic tx fifo size and address */ + nptxfifolen &= ~HNPTFLEN_HNPTXRSAR; + nptxfifolen |= USBFS_RX_FIFO_SIZE; + nptxfifolen &= ~HNPTFLEN_HNPTXFD; + nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16; + USB_HNPTFLEN = nptxfifolen; + + /* set periodic tx fifo size and address */ + ptxfifolen &= ~HPTFLEN_HPTXFSAR; + ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; + ptxfifolen &= ~HPTFLEN_HPTXFD; + ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16; + USB_HPTFLEN = ptxfifolen; + } + +#ifdef USE_OTG_MODE + + /* clear host set HNP enable bit in the USB OTG control register */ + otgctl |= GOTGCS_HHNPEN; + USB_GOTGCS &= ~otgctl; + USB_GOTGCS |= 0; + +#endif /* USE_OTG_MODE */ + + /* make sure the fifos are flushed */ + + /* flush all tx fifos in device or host mode */ + usb_txfifo_flush(pudev, 0x10U); + + /* flush the entire rx fifo */ + usb_rxfifo_flush(pudev); + + /* clear all pending host channel interrupts */ + USB_HACHINTEN &= ~HACHINTEN_CINTEN; + + for (i = 0U; i < pudev->cfg.host_channel_num; i++) { + USB_HCHxINTEN(i) = 0U; + USB_HCHxINTF(i) = 0xFFFFFFFFU; + } + +#ifndef USE_OTG_MODE + usb_vbus_drive(pudev, 1U); +#endif /* USE_OTG_MODE */ + + usb_hostint_enable(pudev); + + return USB_OK; +} + +/*! + \brief control the VBUS to power + \param[in] pudev: pointer to selected usb host + \param[in] state: VBUS state + \param[out] none + \retval none +*/ +void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state) +{ + __IO uint32_t host_port = 0U; + + /* enable or disable the external charge pump */ + if ((void *)0 != pudev->host.vbus_drive) { + pudev->host.vbus_drive(pudev, state); + } + + /* turn on the host port power. */ + host_port = USB_PORT_READ(); + + if ((0U == (host_port & HPCS_PP)) && (1U == state)) { + host_port |= HPCS_PP; + } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) { + host_port &= ~HPCS_PP; + } else { + /* no operation */ + } + + USB_HPCS = host_port; + + if (NULL != pudev->mdelay) { + pudev->mdelay(200U); + } +} + +/*! + \brief enables the host mode interrupts + \param[in] pudev: pointer to selected usb host + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) +{ + uint32_t gintf = 0U; + + /* disable all interrupts */ + USB_GINTEN = 0U; + + /* clear any pending interrupts */ + USB_GINTF = 0xFFFFFFFFU; + + /* enable the common interrupts */ + usb_commonint_enable(pudev); + + gintf |= GINTF_RXFNEIF; + + /* enable host_mode-related interrupts */ + gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF; + + USB_GINTEN &= ~gintf; + USB_GINTEN |= gintf; + + return USB_OK; +} + +/*! + \brief reset host port + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint32_t usb_port_reset (usb_core_handle_struct *pudev) +{ + __IO uint32_t hpcs; + + hpcs = USB_PORT_READ(); + + hpcs |= HPCS_PRST; + + USB_HPCS = hpcs; + + if (NULL != pudev->mdelay) { + pudev->mdelay(100U); + } + + hpcs &= ~HPCS_PRST; + + USB_HPCS = hpcs; + + if (NULL != pudev->mdelay) { + pudev->mdelay(20U); + } + + return USB_OK; +} + +/*! + \brief initialize host channel + \param[in] pudev: pointer to usb device + \param[in] hc_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num) +{ + uint8_t is_low_speed = 0U; + __IO uint32_t chinten = 0U; + __IO uint32_t chctl = 0U; + + usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; + + /* clear old interrupt conditions for this host channel */ + USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU; + + /* enable channel interrupts required for this transfer */ + switch (puhc->endp_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ + | HCHINTEN_DTERIE | HCHINTEN_NAKIE; + + if (puhc->endp_in) { + chinten |= HCHINTEN_BBERIE; + } else { + chinten |= HCHINTEN_NYETIE; + } + break; + + case USB_EPTYPE_INTR: + chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ + | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; + + if (puhc->endp_in) { + chinten |= HCHINTEN_BBERIE; + } + break; + + case USB_EPTYPE_ISOC: + chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; + + if (puhc->endp_in) { + chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; + } + break; + + default: + break; + } + + USB_HCHxINTEN((uint16_t)hc_num) = chinten; + + /* enable the top level host channel interrupt */ + USB_HACHINTEN |= 1U << hc_num; + + /* make sure host channel interrupts are enabled */ + USB_GINTEN |= GINTEN_HCIE; + + /* program the hcctlr register */ + chctl = 0U; + + if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) { + is_low_speed = 1U; + } + + chctl |= (uint32_t)puhc->dev_addr << 22U; + chctl |= (uint32_t)puhc->endp_type << 18U; + chctl |= (uint32_t)puhc->endp_id << 11U; + chctl |= (uint32_t)puhc->endp_in << 15U; + chctl |= (uint32_t)is_low_speed << 17U; + chctl |= puhc->endp_mps; + + if (HCCHAR_INTR == puhc->endp_type) { + chctl |= HCHCTL_ODDFRM; + } + + USB_HCHxCTL((uint16_t)hc_num) = chctl; + + return USB_OK; +} + +/*! + \brief prepare host channel for transferring packets + \param[in] pudev: pointer to usb device + \param[in] hc_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num) +{ + uint16_t dword_len = 0U; + uint16_t packet_num = 0U; + + __IO uint32_t chxlen = 0U; + __IO uint32_t chctl = 0U; + + usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; + + /* compute the expected number of packets associated to the transfer */ + if (puhc->xfer_len > 0U) { + packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps; + + if (packet_num > HC_MAX_PACKET_COUNT) { + packet_num = HC_MAX_PACKET_COUNT; + puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); + } + } else { + packet_num = 1U; + } + + if (puhc->endp_in) { + puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); + } + + /* initialize the host channel length register */ + chxlen &= ~HCHLEN_TLEN; + chxlen |= puhc->xfer_len; + chxlen &= ~HCHLEN_PCNT; + chxlen |= (uint32_t)packet_num << 19U; + chxlen &= ~HCHLEN_DPID; + chxlen |= (uint32_t)(puhc->DPID) << 29U; + USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen; + + /* set host channel enable */ + chctl = USB_HCHxCTL((uint16_t)hc_num); + + if (1U == USB_EVEN_FRAME()) { + chctl |= HCHCTL_ODDFRM; + } else { + chctl &= ~HCHCTL_ODDFRM; + } + + chctl |= HCHCTL_CEN; + chctl &= ~HCHCTL_CDIS; + USB_HCHxCTL((uint16_t)hc_num) = chctl; + + if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { + dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; + + switch (puhc->endp_type) { + /* non-periodic transfer */ + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + /* check if there is enough space in fifo space */ + if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + /* need to process data in non-periodic transfer fifo empty interrupt */ + USB_GINTEN |= GINTEN_NPTXFEIE; + } + break; + + /* periodic transfer */ + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + /* check if there is enough space in FIFO space */ + if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { + /* need to process data in periodic transfer fifo empty interrupt */ + USB_GINTEN |= GINTEN_PTXFEIE; + } + break; + + default: + break; + } + + /* write packet into the Tx FIFO. */ + usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); + } + + return USB_OK; +} + +/*! + \brief halt channel + \param[in] pudev: pointer to usb device + \param[in] hc_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num) +{ + uint8_t endp_type = 0U; + __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num); + + chctl |= HCHCTL_CEN | HCHCTL_CDIS; + + endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U); + + /* check for space in the request queue to issue the halt. */ + if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) { + if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + chctl &= ~HCHCTL_CEN; + } + } else { + if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { + chctl &= ~HCHCTL_CEN; + } + } + + USB_HCHxCTL((uint16_t)hc_num) = chctl; + + return USB_OK; +} + +/*! + \brief stop the USB host and clean up fifos + \param[in] none + \param[out] none + \retval none +*/ +void usb_host_stop(usb_core_handle_struct *pudev) +{ + uint32_t i; + + /* disable all host channel interrupt */ + USB_HACHINTEN = 0U; + USB_HACHINT = 0xFFFFFFFFU; + + /* flush out any leftover queued requests */ + for (i = 0U; i < pudev->cfg.host_channel_num; i++) { + USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR; + } + + /* flush the FIFO */ + usb_rxfifo_flush(pudev); + usb_txfifo_flush(pudev, 0x10U); +} + +#endif /* USE_HOST_MODE */ + + +#ifdef USE_DEVICE_MODE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = +{ + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); + +/*! + \brief initialize USB core registers for device mode + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) +{ + uint32_t i, ram_address = 0U; + __IO uint32_t devinep0intf = USB_DIEP0TFLEN; + __IO uint32_t devinepintf = 0U; + + /* restart the phy clock (maybe don't need to...) */ + USB_PWRCLKCTL = 0U; + + /* config periodic frmae interval to default */ + USB_DCFG &= ~DCFG_EOPFT; + USB_DCFG |= FRAME_INTERVAL_80; + + if (USB_FS_CORE_ID == pudev->cfg.core_id) { + /* set full speed PHY */ + USB_DCFG &= ~DCFG_DS; + USB_DCFG |= USB_SPEED_INP_FULL; + + /* set rx fifo size */ + USB_GRFLEN &= ~GRFLEN_RXFD; + USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE; + + /* set endpoint 0 tx fifo length and RAM address */ + devinep0intf &= ~DIEP0TFLEN_IEP0TXFD; + devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16; + devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR; + devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE; + + USB_DIEP0TFLEN = devinep0intf; + + ram_address = (uint32_t)RX_FIFO_FS_SIZE; + + /* set endpoint 1 to 3's tx fifo length and RAM address */ + for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) { + ram_address += USBFS_TX_FIFO_SIZE[i - 1U]; + + devinepintf &= ~DIEPTFLEN_IEPTXFD; + devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; + devinepintf &= ~DIEPTFLEN_IEPTXRSAR; + devinepintf |= ram_address; + + USB_DIEPxTFLEN(i) = devinepintf; + } + } + + /* make sure all fifos are flushed */ + + /* flush all tx fifos */ + usb_txfifo_flush(pudev, 0x10U); + + /* flush entire rx fifo */ + usb_rxfifo_flush(pudev); + + /* clear all pending device interrupts */ + USB_DIEPINTEN = 0U; + USB_DOEPINTEN = 0U; + USB_DAEPINT = 0xFFFFFFFFU; + USB_DAEPINTEN = 0U; + + /* configure all in/out endpoints */ + for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { + if (USB_DIEPxCTL(i) & DEPCTL_EPEN) { + USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + USB_DIEPxCTL(i) = 0U; + } + + if (USB_DOEPxCTL(i) & DEPCTL_EPEN) { + USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + USB_DOEPxCTL(i) = 0U; + } + + /* set in/out endpoint transfer length to 0 */ + USB_DIEPxLEN(i) = 0U; + USB_DOEPxLEN(i) = 0U; + + /* clear all pending in/out endpoints interrupts */ + USB_DIEPxINTF(i) = 0xFFU; + USB_DOEPxINTF(i) = 0xFFU; + } + + usb_devint_enable(pudev); + + return USB_OK; +} + +/*! + \brief enable the device mode interrupts + \param[in] pudev: pointer to usb device + \param[out] none + \retval status +*/ +static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) +{ + uint32_t int_mask = 0U; + + /* disable all interrupts */ + USB_GINTEN = 0U; + + /* clear any pending interrupts */ + USB_GINTF = 0xBFFFFFFFU; + + /* enable the common interrupts */ + usb_commonint_enable(pudev); + + int_mask = GINTEN_RXFNEIE; + + /* enable device_mode-related interrupts */ + int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \ + | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \ + | GINTEN_ISOINCIE; + +#ifdef VBUS_SENSING_ENABLED + int_mask |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + USB_GINTEN &= ~int_mask; + USB_GINTEN |= int_mask; + + return USB_OK; +} + +/*! + \brief configures endpoint 0 to receive setup packets + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_ep0_startout(usb_core_handle_struct *pudev) +{ + __IO uint32_t ep0len = 0U; + + /* set out endpoint 0 receive length to 24 bytes */ + ep0len &= ~DOEP0LEN_TLEN; + ep0len |= 8U * 3U; + + /* set out endpoint 0 receive length to 1 packet */ + ep0len &= ~DOEP0LEN_PCNT; + ep0len |= 1U << 19; + + /* set setup packet count to 3 */ + ep0len &= ~DOEP0LEN_STPCNT; + ep0len |= 3U << 29; + + USB_DOEPxLEN(0U) = ep0len; +} + +/*! + \brief active remote wakeup signalling + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_remotewakeup_active(usb_core_handle_struct *pudev) +{ + __IO uint32_t power_clock; + + if (pudev->dev.remote_wakeup) { + if (1U == (USB_DSTAT & DSTAT_SPST)) { + if (pudev->cfg.low_power) { + /* ungate USB core clock */ + power_clock = USB_PWRCLKCTL; + power_clock &= ~PWRCLKCTL_SHCLK; + power_clock &= ~PWRCLKCTL_SUCLK; + + USB_PWRCLKCTL = power_clock; + } + + /* active remote wakeup signaling */ + USB_DCTL |= DCTL_RWKUP; + + if (pudev->mdelay != (void *)0) { + pudev->mdelay(5U); + } + + USB_DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_clock_ungate(usb_core_handle_struct *pudev) +{ + if (pudev->cfg.low_power) { + __IO uint32_t power_clock; + + if (1U == (USB_DSTAT & DSTAT_SPST)) { + /* un-gate USB core clock */ + power_clock = USB_PWRCLKCTL; + power_clock &= ~PWRCLKCTL_SHCLK; + power_clock &= ~PWRCLKCTL_SUCLK; + + USB_PWRCLKCTL = power_clock; + } + } +} + +/*! + \brief stop the device and clean up fifos + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_device_stop (usb_core_handle_struct *pudev) +{ + uint32_t i; + + pudev->dev.status = 1U; + + for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { + USB_DIEPxINTF(i) = 0xFFU; + USB_DOEPxINTF(i) = 0xFFU; + } + + USB_DIEPINTEN = 0U; + USB_DOEPINTEN = 0U; + USB_DAEPINTEN = 0U; + USB_DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + usb_rxfifo_flush(pudev); + usb_txfifo_flush(pudev, 0x10U); +} +#endif /* USE_DEVICE_MODE */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c new file mode 100644 index 0000000000..366b1bbb3b --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c @@ -0,0 +1,503 @@ +/*! + \file usbd_core.c + \brief USB device mode core driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_core.h" +#include "usbd_std.h" + +/*! + \brief initailizes the USB device-mode handler stack + \param[in] pudev: pointer to usb device instance + \param[in] core_id: USB core ID + \param[out] none + \retval none +*/ +void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id) +{ + /* select USB core */ + usb_core_select (pudev, core_id); + + pudev->dev.status = USB_STATUS_DEFAULT; + + /* disable USB global interrupt */ + USB_GLOBAL_INT_DISABLE(); + + /* init the core (common init.) */ + usb_core_init(pudev); + + /* force device mode*/ + usb_mode_set(pudev, DEVICE_MODE); + + /* set device disconnect */ + USB_SOFT_DISCONNECT_ENABLE(); + + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(3U); + } + + /* init device */ + usb_devcore_init(pudev); + + /* set device Connect */ + USB_SOFT_DISCONNECT_DISABLE(); + + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(3U); + } + + /* enable USB global interrupt */ + USB_GLOBAL_INT_ENABLE(); +} + +/*! + \brief endpoint initialization + \param[in] pudev: pointer to usb device instance + \param[in] ep_desc: pointer to usb endpoint descriptor + \param[out] none + \retval none +*/ +void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc) +{ + usb_ep_struct *ep; + usb_dir_enum ep_dir; + + uint32_t devepinten = 0U; + uint32_t devepctl = 0U; + + uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU; + uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK; + uint16_t ep_mps = ep_desc->wMaxPacketSize; + + if (ep_desc->bEndpointAddress >> 7U) { + ep = &pudev->dev.in_ep[ep_num]; + + devepinten |= 1U << ep_num; + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + + ep_dir = USB_TX; + } else { + ep = &pudev->dev.out_ep[ep_num]; + + devepinten |= (1U << ep_num) << 16U; + devepctl = USB_DOEPxCTL((uint16_t)ep_num); + + ep_dir = USB_RX; + } + + /* if the endpoint is not active, need change the endpoint control register */ + if (!(devepctl & DEPCTL_EPACT)) { + devepctl &= ~DEPCTL_MPL; + devepctl |= ep_mps; + + devepctl &= ~DEPCTL_EPTYPE; + devepctl |= (uint32_t)ep_type << 18U; + + if (USB_TX == ep_dir) { + devepctl &= ~DIEPCTL_TXFNUM; + devepctl |= (uint32_t)ep_num << 22U; + } + + devepctl |= DEPCTL_SD0PID; + devepctl |= DEPCTL_EPACT; + } + + if (USB_TX == ep_dir) { + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + } else if (USB_RX == ep_dir) { + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; + } else { + /* no operation */ + } + + ep->endp_mps = ep_mps; + ep->endp_type = ep_type; + + /* enable the interrupts for this endpoint */ + USB_DAEPINTEN |= devepinten; +} + +/*! + \brief endpoint deinitialize + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval none +*/ +void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint32_t devepinten = 0U; + uint8_t ep_num = ep_addr & 0x7FU; + + if (ep_addr >> 7U) { + devepinten |= 1U << ep_num; + + USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; + } else { + devepinten |= (1U << ep_num) << 16U; + + USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; + } + + /* disable the interrupts for this endpoint */ + USB_DAEPINTEN &= ~devepinten; +} + +/*! + \brief endpoint prepare to receive data + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[in] pbuf: pointer to buffer + \param[in] buf_len: buffer length + \param[out] none + \retval none +*/ +void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + usb_ep_struct *ep; + uint8_t ep_num = ep_addr & 0x7FU; + uint32_t devepctl = 0U, devepxlen = 0U; + + ep = &pudev->dev.out_ep[ep_num]; + + /* setup and start the Xfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = buf_len; + ep->xfer_count = 0U; + + devepctl = USB_DOEPxCTL((uint16_t)ep_num); + devepxlen = USB_DOEPxLEN((uint16_t)ep_num); + + devepxlen &= ~DEPLEN_TLEN; + devepxlen &= ~DEPLEN_PCNT; + + /* zero length packet */ + if (0U == ep->xfer_len) { + /* set the transfer length to max packet size */ + devepxlen |= ep->endp_mps; + + /* set the transfer packet count to 1 */ + devepxlen |= 1U << 19U; + } else { + + if (0U == ep_num) { + /* set the transfer length to max packet size */ + devepxlen |= ep->endp_mps; + + /* set the transfer packet count to 1 */ + devepxlen |= 1U << 19U; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; + devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps; + } + } + + USB_DOEPxLEN((uint16_t)ep_num) = devepxlen; + + if (USB_EPTYPE_ISOC == ep->endp_type) { + if (ep->endp_frame) { + devepctl |= DEPCTL_SODDFRM; + } else { + devepctl |= DEPCTL_SEVNFRM; + } + } + + /* enable the endpoint and clear the NAK */ + devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[in] pbuf: pointer to buffer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) +{ + usb_ep_struct *ep; + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; + __IO uint32_t deveplen = 0U; + + ep = &pudev->dev.in_ep[ep_num]; + + /* setup and start the transfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = buf_len; + ep->xfer_count = 0U; + + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + deveplen = USB_DIEPxLEN((uint16_t)ep_num); + + /* clear transfer length to 0 */ + deveplen &= ~DEPLEN_TLEN; + + /* clear transfer packet to 0 */ + deveplen &= ~DEPLEN_PCNT; + + /* zero length packet */ + if (0U == ep->xfer_len) { + /* set transfer packet count to 1 */ + deveplen |= 1U << 19U; + } else { + if (0U == ep_num) { + if (ep->xfer_len > ep->endp_mps) { + ep->xfer_len = ep->endp_mps; + } + + deveplen |= 1U << 19U; + } else { + deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; + } + + /* configure the transfer size and packet count as follows: + * xfersize = N * maxpacket + short_packet + * pktcnt = N + (short_packet exist ? 1 : 0) + */ + deveplen |= ep->xfer_len; + + if (USB_EPTYPE_ISOC == ep->endp_type) { + deveplen |= DIEPLEN_MCNT & (1U << 29U); + } + } + + USB_DIEPxLEN((uint16_t)ep_num) = deveplen; + + if (USB_EPTYPE_ISOC == ep->endp_type) { + if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) { + devepctl |= DEPCTL_SODDFRM; + } else { + devepctl |= DEPCTL_SEVNFRM; + } + } + + /* enable the endpoint and clear the NAK */ + devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + + if (USB_EPTYPE_ISOC != ep->endp_type) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (ep->xfer_len > 0U) { + USB_DIEPFEINTEN |= 1U << ep_num; + } + } else { + usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len); + } +} + +/*! + \brief transmit data on the control channel + \param[in] pudev: pointer to usb device instance + \param[in] pbuf: pointer to buffer + \param[in] len: buffer length + \param[out] none + \retval usb device operation status +*/ +usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) +{ + usbd_status_enum ret = USBD_OK; + + pudev->dev.sum_len = len; + pudev->dev.remain_len = len; + pudev->dev.ctl_status = USB_CTRL_DATA_IN; + + usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len); + + return ret; +} + +/*! + \brief receive data on the control channel + \param[in] pudev: pointer to usb device instance + \param[in] pbuf: pointer to buffer + \param[in] len: buffer length + \param[out] none + \retval usb device operation status +*/ +usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) +{ + pudev->dev.sum_len = len; + pudev->dev.remain_len = len; + pudev->dev.ctl_status = USB_CTRL_DATA_OUT; + + usbd_ep_rx (pudev, 0U, pbuf, len); + + return USBD_OK; +} + +/*! + \brief transmit status on the control channel + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval usb device operation status +*/ +usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev) +{ + pudev->dev.ctl_status = USB_CTRL_STATUS_IN; + + usbd_ep_tx (pudev, 0U, NULL, 0U); + + usb_ep0_startout(pudev); + + return USBD_OK; +} + +/*! + \brief receive status on the control channel + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval usb device operation status +*/ +usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev) +{ + pudev->dev.ctl_status = USB_CTRL_STATUS_OUT; + + usbd_ep_rx (pudev, 0U, NULL, 0U); + + usb_ep0_startout(pudev); + + return USBD_OK; +} + +/*! + \brief set an endpoint to STALL status + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval none +*/ +void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; + + if (ep_addr >> 7U) { + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + + /* set the endpoint disable bit */ + if (devepctl & DEPCTL_EPEN) { + devepctl |= DEPCTL_EPD; + } + + /* set the endpoint stall bit */ + devepctl |= DEPCTL_STALL; + + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + } else { + /* set the endpoint stall bit */ + USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL; + } +} + +/*! + \brief clear endpoint stalled status + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval none +*/ +void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + usb_ep_struct *ep; + uint8_t ep_num = ep_addr & 0x7FU; + __IO uint32_t devepctl = 0U; + + if(ep_addr >> 7U){ + ep = &pudev->dev.in_ep[ep_num]; + + devepctl = USB_DIEPxCTL((uint16_t)ep_num); + + /* clear the in endpoint stall bits */ + devepctl &= ~DEPCTL_STALL; + + if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { + devepctl |= DEPCTL_SEVNFRM; + } + + USB_DIEPxCTL((uint16_t)ep_num) = devepctl; + } else { + ep = &pudev->dev.out_ep[ep_num]; + + devepctl = USB_DOEPxCTL((uint16_t)ep_num); + + /* clear the out endpoint stall bits */ + devepctl &= ~DEPCTL_STALL; + + if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { + devepctl |= DEPCTL_SEVNFRM; + } + + USB_DOEPxCTL((uint16_t)ep_num) = devepctl; + } +} + +/*! + \brief flushes the fifos + \param[in] pudev: pointer to usb device instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval none +*/ +void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + if (ep_addr >> 7U) { + usb_txfifo_flush(pudev, ep_addr & 0x7FU); + } else { + usb_rxfifo_flush(pudev); + } +} + +/*! + \brief get the received data length + \param[in] pudev: pointer to usb device instance + \param[in] ep_num: endpoint identifier which is in (0..3) + \param[out] none + \retval received data length +*/ +uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num) +{ + return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c new file mode 100644 index 0000000000..668ef35cd7 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c @@ -0,0 +1,663 @@ +/*! + \file usbd_int.c + \brief USB device mode interrupt routines + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_int.h" +#include "usbd_std.h" + +/* interrupt handlers */ +static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev); +static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev); + +static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num); + +#ifdef VBUS_SENSING_ENABLED + + static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev); + static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev); + +#endif /* VBUS_SENSING_ENABLED */ + +static usb_speed_enum USB_SPEED[4] = { + [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH, + [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL, + [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL, + [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW +}; + +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, + [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, + [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8 +}; + +/*! + \brief USB device-mode interrupts global service routine handler + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +uint32_t usbd_isr (usb_core_handle_struct *pudev) +{ + uint32_t retval = 0U; + uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN; + + /* ensure the core is in device mode */ + if (DEVICE_MODE == USB_CURRENT_MODE_GET()) { + int_status = gintf & ginten; + + /* there are no interrupts, avoid spurious interrupt */ + if (!int_status) { + return 0U; + } + + /* OUT endpoints interrupts */ + if (int_status & GINTF_OEPIF) { + retval |= usbd_intf_outep(pudev); + } + + /* IN endpoints interrupts */ + if (int_status & GINTF_IEPIF) { + retval |= usbd_intf_inep(pudev); + } + + /* mode mismatch interrupt */ + if (int_status & GINTF_MFIF) { + /* clear interrupt */ + USB_GINTF = GINTF_MFIF; + } + + /* early suspend interrupt */ + if (int_status & GINTF_ESP) { + retval |= usbd_intf_earlysuspend(pudev); + } + + /* suspend interrupt */ + if (int_status & GINTF_SP) { + retval |= usbd_intf_suspend(pudev); + } + + /* wakeup interrupt */ + if (int_status & GINTF_WKUPIF) { + retval |= usbd_intf_resume(pudev); + } + + /* start of frame interrupt */ + if (int_status & GINTF_SOF) { + retval |= usbd_intf_sof(pudev); + } + + /* reveive fifo not empty interrupt */ + if (int_status & GINTF_RXFNEIF) { + retval |= usbd_intf_rxfifo(pudev); + } + + /* USB reset interrupt */ + if (int_status & GINTF_RST) { + retval |= usbd_intf_reset(pudev); + } + + /* enumeration has been finished interrupt */ + if (int_status & GINTF_ENUMF) { + retval |= usbd_intf_enumfinish(pudev); + } + + /* incomplete synchronization in transfer interrupt*/ + if (int_status & GINTF_ISOINCIF) { + retval |= usbd_intf_isoinincomplete(pudev); + } + + /* incomplete synchronization out transfer interrupt*/ + if (int_status & GINTF_ISOONCIF) { + retval |= usbd_intf_isooutincomplete(pudev); + } + +#ifdef VBUS_SENSING_ENABLED + + /* session request interrupt */ + if (int_status & GINTF_SESIF) { + retval |= usbd_intf_sessionrequest(pudev); + } + + /* OTG mode interrupt */ + if (int_status & GINTF_OTGIF) { + retval |= usbd_intf_otg(pudev); + } +#endif /* VBUS_SENSING_ENABLED */ + } + + return retval; +} + +/*! + \brief indicates that an OUT endpoint has a pending interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev) +{ + uint8_t endp_num = 0U; + uint32_t endp_intr = 0U; + + __IO uint32_t out_endp_intr = 0U; + + /* read in the device interrupt bits */ + USB_DAOEP_INTR_READ(endp_intr); + + while (endp_intr) { + if (endp_intr & 0x1U) { + USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num); + + /* transfer complete interrupt */ + if (out_endp_intr & DOEPINTF_TF) { + USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF; + + /* data receive is completed */ + usbd_out_transaction(pudev, endp_num); + } + + /* endpoint disable interrupt */ + if (out_endp_intr & DOEPINTF_EPDIS) { + USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS; + } + + /* setup phase finished interrupt (just for control endpoints) */ + if (out_endp_intr & DOEPINTF_STPF) { + /* setup phase is completed */ + usbd_setup_transaction(pudev); + + USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF; + } + + /* back to back setup packets received */ + if (out_endp_intr & DOEPINTF_BTBSTP) { + USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP; + } + } + + endp_num ++; + endp_intr >>= 1; + } + + return 1U; +} + +/*! + \brief indicates that an in endpoint has a pending interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev) +{ + uint8_t endp_num = 0U; + uint32_t endp_intr = 0U; + + __IO uint32_t in_endp_intr = 0U; + + /* get all in endpoints which have interrupts */ + USB_DAIEP_INTR_READ(endp_intr); + + while (endp_intr) { + if (endp_intr & 0x1U) { + USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num); + + if (in_endp_intr & DIEPINTF_TF) { + /* disable the fifo empty interrupt for the endpoint */ + USB_DIEPFEINTEN &= ~(0x1U << endp_num); + + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF; + + /* data transmittion is completed */ + usbd_in_transaction(pudev, endp_num); + } + + if (in_endp_intr & DIEPINTF_CITO) { + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO; + } + + if (in_endp_intr & DIEPINTF_IEPNE) { + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE; + } + + if (in_endp_intr & DIEPINTF_EPDIS) { + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS; + } + + if (in_endp_intr & DIEPINTF_TXFE) { + usbd_emptytxfifo_write(pudev, endp_num); + USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE; + } + } + + endp_num ++; + endp_intr >>= 1; + } + + return 1U; +} + +/*! + \brief indicates that early suspend state has been detected on the USB + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev) +{ + USB_GINTEN &= ~GINTEN_ESPIE; + USB_GINTF = GINTF_ESP; + + return 1U; +} + +/*! + \brief indicates that suspend state has been detected on the USB + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev) +{ + __IO uint8_t low_power = pudev->cfg.low_power; + __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST); + __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U; + + pudev->dev.prev_status = pudev->dev.status; + pudev->dev.status = USB_STATUS_SUSPENDED; + + if (low_power && suspend && is_configured) { + /* switch-off the otg clocks */ + USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + } + + /* clear interrupt */ + USB_GINTF = GINTF_SP; + + return 1U; +} + +/*! + \brief indicates that the USB controller has detected a resume or remote Wake-up sequence + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev) +{ + pudev->dev.status = pudev->dev.prev_status; + pudev->dev.status = USB_STATUS_CONFIGURED; + + /* clear interrupt */ + USB_GINTF = GINTF_WKUPIF; + + return 1U; +} + +/*! + \brief handle the SOF interrupts + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev) +{ + if (NULL != usbd_int_fops) { + usbd_int_fops->SOF(pudev); + } + + USB_GINTF = GINTF_SOF; + + return 1U; +} + +/*! + \brief handle the rx status queue level interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) +{ + usb_ep_struct *ep; + uint8_t data_pid = 0U, endp_num = 0U; + uint32_t bcount = 0U, packet_num = 0U; + + /* get the status from the top of the fifo (must be read to a variable) */ + __IO uint32_t rx_status = USB_GRSTATP; + + /* disable the rx fifo non-empty interrupt */ + USB_GINTEN &= ~GINTEN_RXFNEIE; + + endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM); + bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U; + data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U); + + /* ensure no-DMA mode can work */ + packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT; + if ((1U == endp_num) && (0U == packet_num)) { + uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num); + + devepctl |= DEPCTL_SNAK; + devepctl &= ~DEPCTL_EPEN; + devepctl &= ~DEPCTL_EPD; + + USB_DOEPxCTL((uint16_t)endp_num) = devepctl; + } + + ep = &pudev->dev.out_ep[endp_num]; + + switch ((rx_status & GRSTATRP_RPCKST) >> 17U) { + case RXSTAT_GOUT_NAK: + break; + case RXSTAT_DATA_UPDT: + if (bcount > 0U) { + usb_fifo_read(ep->xfer_buff, (uint16_t)bcount); + ep->xfer_buff += bcount; + ep->xfer_count += bcount; + } + break; + case RXSTAT_XFER_COMP: + break; + case RXSTAT_SETUP_COMP: + break; + case RXSTAT_SETUP_UPDT: + *(uint32_t *)0x5000081CU |= 0x00020000U; + if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) { + /* copy the setup packet received in fifo into the setup buffer in ram */ + usb_fifo_read(pudev->dev.setup_packet, 8U); + + ep->xfer_count += bcount; + } + break; + default: + break; + } + + /* enable the rx fifo non-empty interrupt */ + USB_GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle USB reset interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) +{ + uint8_t i = 0U; + usb_ep_struct *ep; + + /* clear the remote wakeup signaling */ + USB_DCTL &= ~DCTL_RWKUP; + + /* flush the tx fifo */ + usb_txfifo_flush(pudev, 0U); + + for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { + USB_DIEPxINTF((uint16_t)i) = 0xFFU; + USB_DOEPxINTF((uint16_t)i) = 0xFFU; + } + + /* clear all pending device endpoint interrupts */ + USB_DAEPINT = 0xFFFFFFFFU; + + /* enable endpoint 0 interrupts */ + USB_DAEPINTEN &= ~DAEPINTEN_OEPIE; + USB_DAEPINTEN &= ~DAEPINTEN_IEPIE; + USB_DAEPINTEN = (1U << 16) | 1U; + + /* enable out endpoint interrupts */ + USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; + + /* enable in endpoint interrupts */ + USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; + + /* reset device address */ + USB_DCFG &= ~DCFG_DAR; + USB_DCFG |= 0U << 4U; + + /* configure endpoint 0 to receive setup packets */ + usb_ep0_startout(pudev); + + /* clear usb reset interrupt */ + USB_GINTF = GINTF_RST; + + /* open EP0 IN */ + ep = &pudev->dev.in_ep[0]; + + USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL; + USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE; + USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM; + + if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) { + USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE; + USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); + USB_DIEPxCTL(0U) |= DEP0CTL_EPACT; + } + + ep->endp_mps = USB_MAX_EP0_SIZE; + ep->endp_type = USB_EPTYPE_CTRL; + + /* open EP0 OUT */ + ep = &pudev->dev.out_ep[0]; + + USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL; + USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE; + + if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) { + USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE; + USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); + USB_DOEPxCTL(0U) |= DEP0CTL_EPACT; + } + + ep->endp_mps = USB_MAX_EP0_SIZE; + ep->endp_type = USB_EPTYPE_CTRL; + + pudev->dev.status = USB_STATUS_DEFAULT; + + return 1U; +} + +/*! + \brief handle enumeration finish interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev) +{ + uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U); + + /* set the max packet size of devie in endpoint based on the enumeration speed */ + USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed]; + + /* clear global in NAK */ + USB_DCTL &= ~DCTL_CGINAK; + USB_DCTL |= DCTL_CGINAK; + + /* set USB turn-around time based on device speed and PHY interface */ + if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) { + pudev->cfg.core_speed = USB_CORE_SPEED_HIGH; + pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE; + + USB_GUSBCS &= ~GUSBCS_UTT; + USB_GUSBCS |= 0x09U << 10; + } else { + pudev->cfg.core_speed = USB_CORE_SPEED_FULL; + pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; + + USB_GUSBCS &= ~GUSBCS_UTT; + USB_GUSBCS |= 0x05U << 10; + } + + /* clear interrupt */ + USB_GINTF = GINTF_ENUMF; + + return 1U; +} + +/*! + \brief handle the ISO in incomplete interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev) +{ + + /* clear interrupt */ + USB_GINTF = GINTF_ISOINCIF; + + return 1U; +} + +/*! + \brief handle the ISO OUT incomplete interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev) +{ + /* clear interrupt */ + USB_GINTF = GINTF_ISOONCIF; + + return 1U; +} + +/*! + \brief check FIFO for the next packet to be loaded + \param[in] pudev: pointer to usb device instance + \param[in] ep_id: endpoint identifier which is in (0..3) + \param[out] none + \retval status +*/ +static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num) +{ + uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U; + usb_ep_struct *ep; + + ep = &pudev->dev.in_ep[ep_num]; + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->endp_mps) { + len = ep->endp_mps; + } + + word_len = (len + 3U) / 4U; + + while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) && + (ep->xfer_count < ep->xfer_len)) { + /* write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->endp_mps) { + len = ep->endp_mps; + } + + word_len = (len + 3U) / 4U; + + usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len); + + ep->xfer_buff += len; + ep->xfer_count += len; + + if(ep->xfer_len == ep->xfer_count) { + fifo_empty_mask = 0x1U << ep_num; + USB_DIEPFEINTEN &= ~fifo_empty_mask; + } + } + + return 1U; +} + +#ifdef VBUS_SENSING_ENABLED + +/*! + \brief indicates that the USB_OTG controller has detected a connection + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev) +{ + pudev->dev.connection_status = 1U; + + /* clear the interrupt bit */ + USB_GINTF = GINTF_SESIF; + + return 1; +} + +/*! + \brief indicates that the USB_OTG controller has detected an OTG event + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev) +{ + if (USB_GOTGINTF & GOTGINTF_SESEND) { + pudev->dev.class_deinit(pudev, 0); + pudev->dev.connection_status = 0; + } + + /* clear OTG interrupt */ + USB_GOTGINTF |= GOTGINTF_SESEND; + + return 1; +} + +#endif /* VBUS_SENSING_ENABLED */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c new file mode 100644 index 0000000000..33ad7a94b6 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c @@ -0,0 +1,727 @@ +/*! + \file usbd_std.c + \brief USB 2.0 standard handler driver + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_std.h" +#include "usb_core.h" + +static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); + +static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req); + +static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); +static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req); + +static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); +static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); +static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); + +static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) = +{ + usbd_getstatus, + usbd_clrfeature, + usbd_reserved, + usbd_setfeature, + usbd_reserved, + usbd_setaddress, + usbd_getdescriptor, + usbd_setdescriptor, + usbd_getconfig, + usbd_setconfig, + usbd_getinterface, + usbd_setinterface, + usbd_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = +{ + usbd_device_descriptor_get, + usbd_configuration_descriptor_get, + usbd_string_descriptor_get +}; + +/*! + \brief USB setup stage processing + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev) +{ + usb_device_req_struct req; + + usbd_setup_request_parse(pudev, &req); + + switch (req.bmRequestType & USB_REQ_MASK) { + /* standard device request */ + case USB_STANDARD_REQ: + usbd_standard_request(pudev, &req); + break; + /* device class request */ + case USB_CLASS_REQ: + usbd_device_class_request(pudev, &req); + break; + /* vendor defined request */ + case USB_VENDOR_REQ: + usbd_vendor_request(pudev, &req); + break; + default: + usbd_ep_stall(pudev, req.bmRequestType & 0x80U); + break; + } + + return USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] pudev: pointer to USB device instance + \param[in] ep_id: endpoint identifier(0..7) + \param[out] none + \retval USB device operation status +*/ +usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) +{ + usb_ep_struct *ep; + + if (0U == endp_num) { + ep = &pudev->dev.out_ep[0]; + + if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) { + if (pudev->dev.remain_len > ep->endp_mps) { + pudev->dev.remain_len -= ep->endp_mps; + + usbd_ep_rx (pudev, + 0U, + ep->xfer_buff, + (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps)); + } else { + if (USB_STATUS_CONFIGURED == pudev->dev.status) { + pudev->dev.class_data_handler(pudev, USB_RX, 0U); + } + + usbd_ctlstatus_tx(pudev); + } + } + } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { + pudev->dev.class_data_handler(pudev, USB_RX, endp_num); + } else { + /* no operation */ + } + + return USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] pudev: pointer to USB device instance + \param[in] ep_id: endpoint identifier(0..7) + \param[out] none + \retval USB device operation status +*/ +usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) +{ + usb_ep_struct *ep; + + if (0U == endp_num) { + ep = &pudev->dev.in_ep[0]; + + if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) { + if (pudev->dev.remain_len > ep->endp_mps) { + pudev->dev.remain_len -= ep->endp_mps; + + usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len); + + usbd_ep_rx (pudev, 0U, NULL, 0U); + } else { + /* last packet is MPS multiple, so send ZLP packet */ + if ((pudev->dev.sum_len % ep->endp_mps == 0U) && + (pudev->dev.sum_len >= ep->endp_mps) && + (pudev->dev.sum_len < pudev->dev.ctl_len)) { + usbd_ep_tx (pudev, 0U, NULL, 0U); + pudev->dev.ctl_len = 0U; + + usbd_ep_rx (pudev, 0U, NULL, 0U); + } else { + if (USB_STATUS_CONFIGURED == pudev->dev.status) { + pudev->dev.class_data_handler(pudev, USB_TX, 0U); + } + + usbd_ctlstatus_rx(pudev); + } + } + } + } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { + pudev->dev.class_data_handler(pudev, USB_TX, endp_num); + } else { + /* no operation */ + } + + return USBD_OK; +} + +/*! + \brief handle USB standard device request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device operation status +*/ +static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* call device request handle function */ + (*StandardDeviceRequest[req->bRequest])(pudev, req); + + return USBD_OK; +} + +/*! + \brief handle USB device class request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device operation status +*/ +static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + usbd_status_enum ret = USBD_OK; + + switch (pudev->dev.status) { + case USB_STATUS_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req)); + + if ((0U == req->wLength) && (USBD_OK == ret)) { + /* no data stage */ + usbd_ctlstatus_tx(pudev); + } + } else { + usbd_enum_error(pudev, req); + } + break; + + default: + usbd_enum_error(pudev, req); + break; + } + + return ret; +} + +/*! + \brief handle USB vendor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device operation status +*/ +static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* added by user... */ + + return USBD_OK; +} + +/*! + \brief no operation, just for reserved + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no operation... */ +} + +/*! + \brief get the device descriptor + \brief[in] index: no use + \param[in] none + \param[out] pLen: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + *pLen = pudev->dev.dev_desc[0]; + + return pudev->dev.dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] index: no use + \param[in] none + \param[out] pLen: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + *pLen = pudev->dev.config_desc[2]; + + return pudev->dev.config_desc; +} + +/*! + \brief get string descriptor + \param[in] index: string descriptor index + \param[in] pLen: pointer to string length + \param[out] none + \retval none +*/ +static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) +{ + uint8_t *desc = pudev->dev.strings[index]; + + *pLen = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ +} + +/*! + \brief handle USB Clear_Feature request + \param[in] pudev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval none +*/ +static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr = 0U; + + switch (req->bmRequestType & USB_REQTYPE_MASK) { + /* process device feature */ + case USB_REQTYPE_DEVICE: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + case USB_STATUS_CONFIGURED: + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + pudev->dev.remote_wakeup = 0U; + pudev->dev.class_req_handler(pudev, req); + + usbd_ctlstatus_tx(pudev); + } + break; + + default: + usbd_enum_error(pudev, req); + break; + } + break; + /* process interface feature */ + case USB_REQTYPE_INTERFACE: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USB_STATUS_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* no operation */ + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + /* process endpoint feature */ + case USB_REQTYPE_ENDPOINT: + ep_addr = LOWBYTE(req->wIndex); + + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_stall(pudev, ep_addr); + } + break; + case USB_STATUS_CONFIGURED: + if (USB_FEATURE_ENDP_HALT == req->wValue) { + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_clear_stall(pudev, ep_addr); + + pudev->dev.class_req_handler(pudev, req); + } + } + usbd_ctlstatus_tx(pudev); + break; + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Set_Feature request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t ep_addr = 0U; + __IO uint32_t DctlrStatus; + + switch (req->bmRequestType & USB_REQ_MASK) { + /* process device feature */ + case USB_REQTYPE_DEVICE: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + case USB_STATUS_CONFIGURED: + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + pudev->dev.remote_wakeup = 1U; + pudev->dev.class_req_handler(pudev, req); + + usbd_ctlstatus_tx(pudev); + } else if ((req->wValue == USB_FEATURE_TEST_MODE) && + (0U == (req->wIndex & 0xFFU))) { + DctlrStatus = USB_DCTL; + + usbd_ctlstatus_tx(pudev); + } else { + /* no operation */ + } + break; + default: + break; + } + break; + /* process interface feature */ + case USB_REQTYPE_INTERFACE: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + usbd_enum_error(pudev, req); + break; + case USB_STATUS_CONFIGURED: + if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* no operation */ + } else { + usbd_enum_error(pudev, req); + } + break; + default: + break; + } + break; + /* process endpoint feature */ + case USB_REQTYPE_ENDPOINT: + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_stall(pudev, ep_addr); + } + break; + case USB_STATUS_CONFIGURED: + if (USB_FEATURE_ENDP_HALT == req->wValue) { + if (IS_NOT_EP0(ep_addr)) { + usbd_ep_stall(pudev, ep_addr); + } + } + pudev->dev.class_req_handler(pudev, req); + + usbd_ctlstatus_tx(pudev); + break; + default: + break; + } + break; + default: + usbd_enum_error(pudev, req); + break; + } +} + +/*! + \brief handle USB Set_Address request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t DevAddr; + + if ((0U == req->wIndex) && (0U == req->wLength)) { + DevAddr = (uint8_t)(req->wValue) & 0x7FU; + + if (USB_STATUS_CONFIGURED == pudev->dev.status) { + usbd_enum_error(pudev, req); + } else { + USB_SET_DEVADDR((uint32_t)DevAddr); + + usbd_ctlstatus_tx(pudev); + + if (0U != DevAddr) { + pudev->dev.status = USB_STATUS_ADDRESSED; + } else { + pudev->dev.status = USB_STATUS_DEFAULT; + } + } + } else { + usbd_enum_error(pudev, req); + } +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) { + uint8_t desc_type = (uint8_t)(req->wValue >> 8); + uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; + + if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { + uint16_t len; + uint8_t *pbuf; + + /* call corresponding descriptor get function */ + pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); + + if ((0U != len) && (0U != req->wLength)) { + len = USB_MIN(len, req->wLength); + + if ((1U == desc_type) && (64U == req->wLength)) { + len = 8U; + } + + usbd_ctltx(pudev, pbuf, len); + } + } else { + usbd_enum_error(pudev, req); + } + } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) { + pudev->dev.class_req_handler(pudev, req); + } else { + /* no operation */ + } +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no handle... */ +} + +/*! + \brief handle USB Get_Configuration request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint32_t USBD_default_config = 0U; + + if (1U != req->wLength) { + usbd_enum_error(pudev, req); + } else { + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U); + break; + case USB_STATUS_CONFIGURED: + usbd_ctltx(pudev, &pudev->dev.config_num, 1U); + break; + default: + usbd_enum_error(pudev, req); + break; + } + } +} + +/*! + \brief handle USB Set_Configuration request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + /* if config index is more than configuration max number */ + if (cfgidx > USBD_CFG_MAX_NUM) { + usbd_enum_error(pudev, req); + } else { + switch (pudev->dev.status) { + case USB_STATUS_ADDRESSED: + if (cfgidx) { + pudev->dev.config_num = cfgidx; + pudev->dev.status = USB_STATUS_CONFIGURED; + pudev->dev.class_init(pudev, cfgidx); + } + + usbd_ctlstatus_tx(pudev); + break; + case USB_STATUS_CONFIGURED: + if (0U == cfgidx) { + pudev->dev.status = USB_STATUS_ADDRESSED; + pudev->dev.config_num = cfgidx; + pudev->dev.class_deinit(pudev, cfgidx); + } else if (cfgidx != pudev->dev.config_num) { + /* clear old configuration */ + pudev->dev.class_deinit(pudev, pudev->dev.config_num); + + /* set new configuration */ + pudev->dev.config_num = cfgidx; + pudev->dev.class_init(pudev, cfgidx); + } else { + /* no operation */ + } + + usbd_ctlstatus_tx(pudev); + break; + default: + usbd_enum_error(pudev, req); + break; + } + } +} + +/*! + \brief handle USB Get_Interface request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + pudev->dev.class_req_handler(pudev, req); +} + +/*! + \brief handle USB Set_Interface request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + pudev->dev.class_req_handler(pudev, req); +} + +/*! + \brief handle USB SynchFrame request + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + /* no handle... */ +} + +/*! + \brief decode setup data packet + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + uint8_t *psetup = pudev->dev.setup_packet; + + req->bmRequestType = *psetup; + req->bRequest = *(uint8_t *)(psetup + 1U); + req->wValue = SWAPBYTE (psetup + 2U); + req->wIndex = SWAPBYTE (psetup + 4U); + req->wLength = SWAPBYTE (psetup + 6U); + + pudev->dev.ctl_len = req->wLength; +} + +/*! + \brief handle USB low level error event + \param[in] pudev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req) +{ + usbd_ep_stall(pudev, 0x80U); + usbd_ep_stall(pudev, 0x00U); + usb_ep0_startout(pudev); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c new file mode 100644 index 0000000000..de41f72273 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c @@ -0,0 +1,737 @@ +/*! + \file usbh_core.c + \brief this file implements the functions for the core state machine process + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hcs.h" +#include "usbh_core.h" +#include "usbh_int.h" +#include "stdio.h" +#include "usbh_std.h" +#include "usbh_ctrl.h" +#include "usb_core.h" + +extern class_polling_fun_cb_struct class_polling_cb; + +uint8_t usbh_sof (usb_core_handle_struct *pudev); +uint8_t usbh_connected (usb_core_handle_struct *pudev); +uint8_t usbh_disconnected (usb_core_handle_struct *pudev); + +usbh_hcd_int_cb_struct usbh_hcd_int_cb = +{ + usbh_sof, + usbh_connected, + usbh_disconnected, +}; + +usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb; +extern usbh_state_handle_struct usbh_state_core; + +static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); + +static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); +static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); + +/* the host state handle function array */ +void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = +{ + host_idle_handle, + host_dev_attached_handle, + host_dev_detached_handle, + host_detect_dev_speed_handle, + host_enum_handle, + host_class_request_handle, + host_class_handle, + host_user_input_handle, + host_suspended_handle, + host_error_handle, +}; + +/* the host state handle table */ +state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] = +{ + /* the current state the current event the next state the event function */ + {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move }, + {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move }, + {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move }, + {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move }, + {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move }, + {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, + {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, + {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, + {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, +}; + +/*! + \brief the polling function of host state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + void *pustate) +{ + usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate; + + scd_begin(p_state, HOST_FSM_ID); + + if (-1 == p_state->usbh_current_state_stack_top) { + uint8_t cur_state = p_state->usbh_current_state; + + if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) { + if (HOST_DEV_DETACHED != cur_state) { + p_state->usbh_current_state = HOST_DEV_DETACHED; + cur_state = HOST_DEV_DETACHED; + } + } + + host_state_handle[cur_state](pudev, puhost, p_state); + } else { + uint8_t stack0_state = p_state->stack[0].state; + + if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) { + if (HOST_DEV_DETACHED != stack0_state) { + p_state->stack[0].state = HOST_DEV_DETACHED; + stack0_state = HOST_DEV_DETACHED; + p_state->usbh_current_state = HOST_DEV_DETACHED; + } + } + + host_state_handle[stack0_state](pudev, puhost, p_state); + } + + return USBH_OK; +} + +/*! + \brief the handle function of HOST_IDLE state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_idle_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + if (hcd_is_device_connected(pudev)) { + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state); + + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(100U); + } + } +} + +/*! + \brief the handle function of HOST_DEV_ATTACHED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_dev_attached_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usr_cb->device_connected(); + puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U); + puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U); + + /* reset usb device */ + if (0U == usb_port_reset(pudev)) { + puhost->usr_cb->device_reset(); + + /* wait for USB USBH_ISR_PrtEnDisableChange() + * host is now ready to start the enumeration + */ + puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET(); + puhost->usr_cb->device_speed_detected(puhost->device.speed); + + /* open in control pipes */ + usbh_channel_open (pudev, + puhost->control.hc_in_num, + puhost->device.address, + puhost->device.speed, + USB_EPTYPE_CTRL, + (uint16_t)puhost->control.ep0_size); + + /* open out control pipes */ + usbh_channel_open (pudev, + puhost->control.hc_out_num, + puhost->device.address, + puhost->device.speed, + USB_EPTYPE_CTRL, + (uint16_t)puhost->control.ep0_size); + + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of HOST_ENUMERATION state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_enum_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) { + puhost->usr_cb->enumeration_finish(); + scd_event_handle(pudev, + puhost, + pustate, + HOST_EVENT_USER_INPUT, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of HOST_USER_INPUT state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_user_input_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) { + if (USBH_OK == (puhost->class_init(pudev, puhost))) { + scd_event_handle(pudev, + puhost, + pustate, + HOST_EVENT_CLASS_REQ, + pustate->usbh_current_state); + } + } +} + +/*! + \brief the handle function of HOST_CLASS_REQUEST state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_class_request_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) { + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of HOST_CLASS state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_class_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + class_state_polling_fun(pudev, puhost, pustate); +} + +/*! + \brief the handle function of HOST_SUSPENDED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_suspended_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + /* no operation */ +} + +/*! + \brief the handle function of HOST_ERROR state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_error_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + /* re-initilaize host for new enumeration */ + usbh_deinit (pudev, puhost,&usbh_state_core); + puhost->usr_cb->deinit(); + puhost->class_deinit(pudev, &puhost->device); + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); +} + +/*! + \brief the handle function of HOST_DEV_DETACHED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_dev_detached_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + /* manage user disconnect operations*/ + puhost->usr_cb->device_disconnected(); + + /* re-initilaize host for new enumeration */ + usbh_deinit(pudev, puhost,&usbh_state_core); + puhost->usr_cb->deinit(); + puhost->class_deinit(pudev, &puhost->device); + usbh_allchannel_dealloc(pudev); + scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); +} + +/*! + \brief the handle function of HOST_DETECT_DEV_SPEED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + /* no operation */ +} + +/*! + \brief usb connect callback function from the interrupt. + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_connected (usb_core_handle_struct *pudev) +{ + pudev->host.connect_status = 1U; + + return 0U; +} + +/*! + \brief usb disconnect callback function from the interrupt. + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_disconnected (usb_core_handle_struct *pudev) +{ + pudev->host.connect_status = 0U; + + return 0U; +} + +/*! + \brief usb sof callback function from the interrupt. + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_sof (usb_core_handle_struct *pudev) +{ + /* this callback could be used to implement a scheduler process */ + return 0U; +} + +/*! + \brief initialize the host portion of the driver. + \param[in] pudev: pointer to usb device + \param[in] core_id: usb otg core identifier(high-speed or full-speed) + \param[out] none + \retval operation status +*/ +uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id) +{ + pudev->host.connect_status = 0U; + + pudev->host.host_channel[0].endp_mps = 8U; + + usb_core_select(pudev, core_id); + +#ifndef DUAL_ROLE_MODE_ENABLED + + USB_GLOBAL_INT_DISABLE(); + + usb_core_init(pudev); + + /* force host mode*/ + usb_mode_set(pudev, HOST_MODE); + + usb_hostcore_init(pudev); + + USB_GLOBAL_INT_ENABLE(); + +#endif + + return 0U; +} + +/*! + \brief check if the device is connected. + \param[in] pudev: pointer to usb device + \param[out] none + \retval device connection status. 1 -> connected and 0 -> disconnected +*/ +uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev) +{ + return (uint32_t)(pudev->host.connect_status); +} + +/*! + \brief this function returns the last URBstate + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval urb_state_enum +*/ +urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + return pudev->host.host_channel[channel_num].urb_state; +} + +/*! + \brief this function returns the last URBstate + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval No. of data bytes transferred +*/ +uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + return pudev->host.host_channel[channel_num].xfer_count; +} + +/*! + \brief de-initialize host + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[out] none + \retval host status +*/ +usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct* pustate) +{ + /* software init */ + + puhost->control.ep0_size = USB_MAX_EP0_SIZE; + + puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT; + puhost->device.speed = HPRT_PRTSPD_FULL_SPEED; + + usbh_channel_free(pudev, puhost->control.hc_in_num); + usbh_channel_free(pudev, puhost->control.hc_out_num); + + scd_init(pustate); + scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE); + scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE); + scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE); + + scd_begin(pustate,HOST_FSM_ID); + scd_state_move(pustate, HOST_IDLE); + + return USBH_OK; +} + +/*! + \brief state core driver init + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +void scd_init(usbh_state_handle_struct* pustate) +{ + /* init the state core */ + pustate->usbh_current_state = 0U; + pustate->usbh_current_state_table = NULL; + pustate->usbh_current_state_table_size = 0U; + + pustate->usbh_current_state_stack_top = -1; + pustate->stack->state = 0U; + pustate->stack->table_size = 0U; + pustate->stack->table = NULL; + + pustate->usbh_regist_state_table_num = 0U; + pustate->usbh_regist_state_table->table = NULL; + pustate->usbh_regist_state_table->table_size = 0U; + pustate->usbh_regist_state_table->id = 0U; + + /* init the control and the enumeration polling handle flag */ + ctrl_polling_handle_flag = 0U; + enum_polling_handle_flag = 0U; +} + +/*! + \brief state core driver table regist + \param[in] pustate: pointer to usb state driver + \param[in] pstate_table: pointer to the table to regist + \param[in] table_id: the id of the table to regist + \param[in] current_table_size: the size of the current table to regist + \param[out] none + \retval none +*/ +void scd_table_regist (usbh_state_handle_struct* pustate, + state_table_struct* pstate_table, + uint8_t table_id, + uint8_t current_table_size) +{ + usbh_state_regist_table_struct *cur_state_reg_table; + + cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num]; + + cur_state_reg_table->id = table_id; + cur_state_reg_table->table = pstate_table; + cur_state_reg_table->table_size = current_table_size; + + pustate->usbh_regist_state_table_num++; +} + +/*! + \brief state core driver begin + \param[in] pustate: pointer to usb state driver + \param[in] table_id: the id of the table to begin + \param[out] none + \retval none +*/ +void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id) +{ + uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num; + usbh_state_regist_table_struct *cur_state_reg_table; + + for (i = 0U; i < table_num; i++) { + cur_state_reg_table = &pustate->usbh_regist_state_table[i]; + + if (table_id == cur_state_reg_table->id) { + pustate->usbh_current_state_table = cur_state_reg_table->table; + pustate->usbh_current_state_table_size = cur_state_reg_table->table_size; + break; + } + } +} + +/*! + \brief state core driver move state + \param[in] pustate: pointer to usb state driver + \param[in] state: the state to move + \param[out] none + \retval none +*/ +void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state) +{ + pustate->usbh_current_state = state; +} + +/*! + \brief state core driver event handle + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[in] event: the current event + \param[in] state: the current state + \param[out] none + \retval host status +*/ +usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct* pustate, + uint8_t event, + uint8_t state) +{ + uint8_t i = 0U; + ACT_FUN event_act_fun = NULL; + state_table_struct *backup_state_t = pustate->usbh_current_state_table; + state_table_struct *executive_state_table = pustate->usbh_current_state_table; + + /* look up the table to find the action function */ + for (i = 0U; i < pustate->usbh_current_state_table_size; i++) { + if (state == executive_state_table->cur_state) { + if (event == executive_state_table->cur_event) { + state = executive_state_table->next_state; + event_act_fun = executive_state_table->event_action_fun; + break; + } else { + executive_state_table++; + } + } else { + executive_state_table++; + } + } + + pustate->usbh_current_state_table = backup_state_t; + + /* if the action function is not NULL, execute the action function */ + if (event_act_fun) { + if (event_act_fun == &only_state_move) { + pustate->usbh_current_state = state; + } else { + return event_act_fun(pudev, puhost, pustate); + } + } + + return USBH_BUSY; +} + +/*! + \brief state core driver table push + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +void scd_table_push(usbh_state_handle_struct* pustate) +{ + usbh_state_stack_struct *top_state_element; + + if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) { + pustate->usbh_current_state_stack_top++; + + top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; + + /* put the current state table into the state stack */ + top_state_element->state = pustate->usbh_current_state; + top_state_element->table = pustate->usbh_current_state_table; + top_state_element->table_size = pustate->usbh_current_state_table_size; + } +} + +/*! + \brief state core driver table pop + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +void scd_table_pop (usbh_state_handle_struct* pustate) +{ + usbh_state_stack_struct *top_state_element; + + top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; + + if (pustate->usbh_current_state_stack_top > -1) { + /* get the current state table from the state stack */ + pustate->usbh_current_state = top_state_element->state; + pustate->usbh_current_state_table = top_state_element->table; + pustate->usbh_current_state_table_size = top_state_element->table_size; + pustate->usbh_current_state_stack_top--; + } +} +/*! + \brief the polling function of class req state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval host status +*/ +static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + return class_polling_cb.class_req_polling(pudev, puhost, pustate); +} + +/*! + \brief the polling function of class state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval host status +*/ +static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + return class_polling_cb.class_polling(pudev, puhost, pustate); +} + +/*! + \brief the function is only used to state move + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + return USBH_OK; +} + +/*! + \brief the function to the up state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + scd_table_pop((usbh_state_handle_struct *)pustate); + + return USBH_OK; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c new file mode 100644 index 0000000000..3f5277701f --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c @@ -0,0 +1,639 @@ +/*! + \file usbh_ctrl.c + \brief this file implements the functions for the control transmit process + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_core.h" +#include "usbh_std.h" +#include "usbh_ctrl.h" + +uint8_t ctrl_polling_handle_flag = 0U; +uint8_t ctrl_setup_wait_flag = 0U; +uint8_t ctrl_data_wait_flag = 0U; +uint8_t ctrl_status_wait_flag = 0U; + +static uint16_t timeout = 0U; + +static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); + +/* the ctrl state handle function array */ +void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) = +{ + ctrl_idle_handle, + ctrl_setup_handle, + ctrl_data_handle, + ctrl_status_handle, + ctrl_error_handle, + ctrl_stalled_handle, + ctrl_complete_handle, +}; + +/* the ctrl state handle table */ +state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] = +{ + /* the current state the current event the next state the event function */ + {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move }, + {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move }, + {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, + {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, + {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, + {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, + {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, + {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move }, + {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, + {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, + {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, + {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, + {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, +}; + +/*! + \brief the polling function of CTRL state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + void *pustate) +{ + usbh_status_enum exe_state = USBH_BUSY; + usbh_state_handle_struct *p_state; + + p_state = (usbh_state_handle_struct *)pustate; + + /* if first enter this function, begin the ctrl state */ + if (0U == ctrl_polling_handle_flag) { + ctrl_polling_handle_flag = 1U; + scd_table_push(p_state); + scd_state_move(p_state, CTRL_IDLE); + } + + /* base on the current state to handle the ctrl state */ + scd_begin(p_state, CTRL_FSM_ID); + ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); + + /* determine the control transfer whether to complete */ + switch (puhost->usbh_backup_state.ctrl_backup_state) { + case CTRL_COMPLETE: + ctrl_polling_handle_flag = 0U; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; + exe_state = USBH_OK; + break; + case CTRL_STALLED: + ctrl_polling_handle_flag = 0U; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; + exe_state = USBH_NOT_SUPPORTED; + break; + case CTRL_ERROR: + ctrl_polling_handle_flag = 0U; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; + exe_state = USBH_FAIL; + break; + default: + exe_state = USBH_BUSY; + break; + } + + return exe_state; +} + +/*! + \brief the handle function of CTRL_IDLE state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_idle_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; + scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); +} + +/*! + \brief the handle function of CTRL_SETUP state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_setup_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + urb_state_enum urb_status = URB_IDLE; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP; + + if (0U == ctrl_setup_wait_flag) { + ctrl_setup_wait_flag = 1U; + + /* send a setup packet */ + usbh_ctltx_setup (pudev, + puhost->control.setup.data, + puhost->control.hc_out_num); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); + + /* case setup packet sent successfully */ + if (URB_DONE == urb_status) { + /* check if there is a data stage */ + if (0U != puhost->control.setup.b.wLength) { + ctrl_setup_wait_flag = 0U; + timeout = DATA_STAGE_TIMEOUT; + scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state); + /* no data stage */ + } else { + timeout = NODATA_STAGE_TIMEOUT; + ctrl_setup_wait_flag = 0U; + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STATUS, + pustate->usbh_current_state); + } + + /* set the delay timer to enable timeout for data stage completion */ + puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET(); + } else if (URB_ERROR == urb_status) { + ctrl_setup_wait_flag = 0U; + scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state); + } else { + /* no operation */ + } + } +} + +/*! + \brief the handle function of CTRL_DATA state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_data_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + uint8_t direction; + urb_state_enum urb_status = URB_IDLE; + puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA; + + direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); + + if (USB_DIR_IN == direction) { + if (0U == ctrl_data_wait_flag) { + ctrl_data_wait_flag = 1U; + + /* issue an IN token */ + usbh_xfer(pudev, + puhost->control.buff, + puhost->control.hc_in_num, + puhost->control.length); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); + + /* check is data packet transfered successfully */ + switch (urb_status) { + case URB_DONE: + ctrl_data_wait_flag = 0U; + + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STATUS, + pustate->usbh_current_state); + break; + case URB_STALL: + ctrl_data_wait_flag = 0U; + + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STALLED, + pustate->usbh_current_state); + break; + case URB_ERROR: + ctrl_data_wait_flag = 0U; + + /* device error */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + break; + default: + if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { + ctrl_data_wait_flag = 0U; + + /* timeout for in transfer */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + } + break; + } + } + } else { + if (0U == ctrl_data_wait_flag) { + ctrl_data_wait_flag = 1U; + + /* start data out transfer (only one data packet)*/ + pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U; + + usbh_xfer(pudev, + puhost->control.buff, + puhost->control.hc_out_num, + puhost->control.length); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); + + switch (urb_status) { + case URB_DONE: + ctrl_data_wait_flag = 0U; + + /* if the setup pkt is sent successful, then change the state */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STATUS, + pustate->usbh_current_state); + break; + case URB_STALL: + ctrl_data_wait_flag = 0U; + + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STALLED, + pustate->usbh_current_state); + break; + case URB_NOTREADY: + /* nack received from device */ + ctrl_data_wait_flag = 0U; + break; + case URB_ERROR: + ctrl_data_wait_flag = 0U; + + /* device error */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + break; + default: + break; + } + } + } +} + +/*! + \brief the handle function of CTRL_STATUS state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_status_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + uint8_t direction; + urb_state_enum urb_status = URB_IDLE; + + puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS; + + /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */ + direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); + + if (USB_DIR_OUT == direction) { + /* handle status in */ + if (0U == ctrl_status_wait_flag) { + ctrl_status_wait_flag = 1U; + usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); + + switch (urb_status) { + case URB_DONE: + ctrl_status_wait_flag = 0U; + + /* handle URB_DONE status */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_COMPLETE, + pustate->usbh_current_state); + break; + case URB_ERROR: + ctrl_status_wait_flag = 0U; + + /* handle URB_STALL status*/ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + break; + case URB_STALL: + ctrl_status_wait_flag = 0U; + + /* handle URB_STALL status */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_STALLED, + pustate->usbh_current_state); + break; + default: + if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { + ctrl_status_wait_flag = 0U; + + /* handle timeout */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + } + break; + } + } + } else { + /* handle status out */ + if (0U == ctrl_status_wait_flag) { + ctrl_status_wait_flag = 1U; + pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U; + usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U); + } else { + urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); + + switch (urb_status) { + case URB_DONE: + ctrl_status_wait_flag = 0U; + + /* handle URB_DONE status */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_COMPLETE, + pustate->usbh_current_state); + break; + case URB_NOTREADY: + /* handle URB_NOTREADY status */ + ctrl_status_wait_flag = 0U; + break; + case URB_ERROR: + ctrl_status_wait_flag = 0U; + + /* handle URB_ERROR status */ + scd_event_handle(pudev, + puhost, + pustate, + CTRL_EVENT_ERROR, + pustate->usbh_current_state); + break; + default: + break; + } + } + } +} + +/*! + \brief the handle function of CTRL_ERROR state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_error_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR; + + if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { + /* do the transmission again, starting from setup packet */ + scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); + } else { + scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of CTRL_STALLED state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_stalled_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED; + scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); +} + +/*! + \brief the handle function of CTRL_COMPLETE state + \param[in] pudev: pointer to usb device + \param[in] puhost: pointer to usb host + \param[in] pustate: pointer to usb state driver + \param[out] none + \retval none +*/ +static void ctrl_complete_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE; + scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); +} + +/*! + \brief send datas from the host channel + \param[in] pudev: pointer to usb device + \param[in] buf: data buffer address to send datas + \param[in] hc_num: the number of the host channel + \param[in] len: length of the send data + \param[out] none + \retval host operation status +*/ +usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, + uint8_t *buf, + uint8_t hc_num, + uint16_t len) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; + + puhc->xfer_buff = buf; + puhc->xfer_len = len; + + switch (puhc->endp_type) { + case USB_EPTYPE_CTRL: + if (0U == puhc->endp_in) { + if (0U == len) { + /* for status out stage, length = 0, status out pid = 1 */ + puhc->data_tg_out = 1U; + } + + /* set the data toggle bit as per the flag */ + if (0U == puhc->data_tg_out) { + /* put the pid 0 */ + puhc->DPID = HC_PID_DATA0; + } else { + /* put the pid 1 */ + puhc->DPID = HC_PID_DATA1; + } + } else { + puhc->DPID = HC_PID_DATA1; + } + break; + + case USB_EPTYPE_ISOC: + puhc->DPID = HC_PID_DATA0; + break; + + case USB_EPTYPE_BULK: + if (0U == puhc->endp_in) { + /* set the data toggle bit as per the flag */ + if (0U == puhc->data_tg_out) { + /* put the pid 0 */ + puhc->DPID = HC_PID_DATA0; + } else { + /* put the pid 1 */ + puhc->DPID = HC_PID_DATA1; + } + } else { + if (0U == puhc->data_tg_in) { + puhc->DPID = HC_PID_DATA0; + } else { + puhc->DPID = HC_PID_DATA1; + } + } + break; + + case USB_EPTYPE_INTR: + if (0U == puhc->endp_in) { + if (0U == puhc->data_tg_out) { + puhc->DPID = HC_PID_DATA0; + } else { + puhc->DPID = HC_PID_DATA1; + } + + /* toggle data pid */ + puhc->data_tg_out ^= 1U; + } else { + if (0U == puhc->data_tg_in) { + puhc->DPID = HC_PID_DATA0; + } else { + puhc->DPID = HC_PID_DATA1; + } + + /* toggle data pid */ + puhc->data_tg_in ^= 1U; + } + break; + + default: + break; + } + + hcd_submit_request (pudev, hc_num); + + return USBH_OK; +} + +/*! + \brief send the setup packet to the device + \param[in] pudev: pointer to usb device + \param[in] buf: buffer pointer from which the data will be send to device + \param[in] hc_num: host channel number + \param[out] none + \retval host operation status +*/ +usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; + + puhc->DPID = HC_PID_SETUP; + puhc->xfer_buff = buf; + puhc->xfer_len = USBH_SETUP_PACKET_SIZE; + + return (usbh_status_enum)hcd_submit_request (pudev, hc_num); +} + +/*! + \brief this function prepare a hc and start a transfer + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval host operation status +*/ +uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + + puhc->urb_state = URB_IDLE; + puhc->xfer_count = 0U; + + return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num); +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c new file mode 100644 index 0000000000..33eecd62db --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c @@ -0,0 +1,185 @@ +/*! + \file usbh_hcs.c + \brief this file implements functions for opening and closing host channels + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hcs.h" + +static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev); + +/*! + \brief open a channel + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[in] dev_addr: USB device address allocated to attached device + \param[in] dev_speed: USB device speed (Full speed/Low speed) + \param[in] ep_type: endpoint type (bulk/int/ctl) + \param[in] ep_mps: max packet size + \param[out] none + \retval operation status +*/ +uint8_t usbh_channel_open (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + uint16_t channel_info = puhc->info; + + puhc->endp_id = (uint8_t)channel_info & 0x7FU; + puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7U; + puhc->endp_type = ep_type; + puhc->endp_mps = ep_mps; + puhc->dev_addr = dev_addr; + puhc->dev_speed = dev_speed; + + puhc->data_tg_in = 0U; + puhc->data_tg_out = 0U; + + usb_hostchannel_init(pudev, channel_num); + + return (uint8_t)HC_OK; +} + +/*! + \brief modify a channel + \param[in] pudev: pointer to usb device + \param[in] channel_num: host channel number which is in (0..7) + \param[in] dev_addr: USB Device address allocated to attached device + \param[in] dev_speed: USB device speed (full speed / low speed) + \param[in] ep_type: endpoint type (bulk/int/ctl) + \param[in] ep_mps: max packet size + \param[out] none + \retval operation status +*/ +uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, + uint8_t channel_num, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t ep_type, + uint16_t ep_mps) +{ + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + + if (0U != dev_addr) { + puhc->dev_addr = dev_addr; + } + + if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) { + puhc->endp_mps = ep_mps; + } + + if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) { + puhc->dev_speed = dev_speed; + } + + usb_hostchannel_init(pudev, channel_num); + + return (uint8_t)HC_OK; +} + +/*! + \brief allocate a new channel for the pipe + \param[in] pudev: pointer to usb device + \param[in] ep_addr: endpoint for which the channel to be allocated + \param[out] none + \retval host channel number +*/ +uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr) +{ + uint16_t hc_num = usbh_freechannel_get(pudev); + + if ((uint16_t)HC_ERROR != hc_num) { + pudev->host.host_channel[hc_num].info = HC_USED | ep_addr; + } + + return (uint8_t)hc_num; +} + +/*! + \brief free the usb host channel + \param[in] pudev: pointer to usb device + \param[in] index: channel number to be freed which is in (0..7) + \param[out] none + \retval host operation status +*/ +uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index) +{ + if (index < HC_MAX) { + pudev->host.host_channel[index].info &= HC_USED_MASK; + } + + return USBH_OK; +} + +/*! + \brief free all usb host channel + \param[in] pudev: pointer to usb device + \param[out] none + \retval host operation status +*/ +uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev) +{ + uint8_t index; + + for (index = 2U; index < HC_MAX; index ++) { + pudev->host.host_channel[index].info = 0U; + } + + return USBH_OK; +} + +/*! + \brief get a free channel number for allocation to a device endpoint + \param[in] pudev: pointer to usb device + \param[out] none + \retval free channel number +*/ +static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev) +{ + uint8_t index = 0U; + + for (index = 0U; index < HC_MAX; index++) { + if (0U == (pudev->host.host_channel[index].info & HC_USED)) { + return (uint16_t)index; + } + } + + return HC_ERROR; +} + diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c new file mode 100644 index 0000000000..5a652bcb88 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c @@ -0,0 +1,612 @@ +/*! + \file usbh_int.c + \brief USB host mode interrupt handler file + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_core.h" +#include "usb_defines.h" +#include "usbh_int.h" + +static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_port (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num); +static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num); +static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev); +static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev); + +/*! + \brief handle global host interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +uint32_t usbh_isr (usb_core_handle_struct *pudev) +{ + uint32_t retval = 0U; + __IO uint32_t int_flag = 0U; + + /* check if host mode */ + if (USB_CURRENT_MODE_GET() == HOST_MODE) { + USB_CORE_INTR_READ(int_flag); + + if (!int_flag) { + return 0U; + } + + /* start of frame interrupt handle */ + if (int_flag & GINTF_SOF) { + retval |= usbh_intf_sof (pudev); + } + + /* rx fifo non-empty interrupt handle */ + if (int_flag & GINTF_RXFNEIF) { + retval |= usbh_intf_rxfifo_noempty (pudev); + } + + /* non-periodic tx fifo empty interrupt hanlde */ + if (int_flag & GINTF_NPTXFEIF) { + retval |= usbh_intf_nptxfifo_empty (pudev); + } + + /* periodic tx fifo empty interrupt handle */ + if (int_flag & GINTF_PTXFEIF) { + retval |= usbh_intf_ptxfifo_empty (pudev); + } + + /* host channels interrupt handle */ + if (int_flag & GINTF_HCIF) { + retval |= usbh_intf_hc (pudev); + } + + /* host port interrupt handle */ + if (int_flag & GINTF_HPIF) { + retval |= usbh_intf_port (pudev); + } + + /* disconnect interrupt handle */ + if (int_flag & GINTF_DISCIF) { + retval |= usbh_intf_disconnect (pudev); + } + + /* isochronous in transfer not complete interrupt handle */ + if (int_flag & GINTF_ISOONCIF) { + retval |= usbh_intf_iso_incomplete_xfer (pudev); + } + } + + return retval; +} + +/*! + \brief handle the start-of-frame interrupt in host mode + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev) +{ + usbh_hcd_int_fops->sof(pudev); + + /* clear interrupt */ + USB_GINTF = GINTF_SOF; + + return 1U; +} + +/*! + \brief handle all host channels interrupt in host mode + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev) +{ + uint8_t i = 0U; + uint32_t retval = 0U; + + for (i = 0U; i < pudev->cfg.host_channel_num; i++) { + if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) { + if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) { + retval |= usbh_intf_hc_in (pudev, i); + } else { + retval |= usbh_intf_hc_out (pudev, i); + } + } + } + + return retval; +} + +/*! + \brief handle the disconnect interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev) +{ + usbh_hcd_int_fops->device_disconnected(pudev); + + /* clear interrupt */ + USB_GINTF = GINTF_DISCIF; + + return 1U; +} + +/*! + \brief handle the non-periodic tx fifo empty interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev) +{ + uint8_t channel_num = 0U; + uint32_t dword_len = 0U, len = 0U; + usb_hostchannel_struct *puhc; + + channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U); + puhc = &pudev->host.host_channel[channel_num]; + dword_len = (puhc->xfer_len + 3U) / 4U; + + while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) { + len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U; + + if (len > puhc->xfer_len) { + /* last packet */ + len = (uint16_t)puhc->xfer_len; + + USB_GINTEN &= ~GINTF_NPTXFEIF; + + } + + dword_len = (puhc->xfer_len + 3U) / 4U; + usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); + + puhc->xfer_buff += len; + puhc->xfer_len -= len; + puhc->xfer_count += len; + } + + return 1U; +} + +/*! + \brief handle the periodic tx fifo empty interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev) +{ + uint8_t channel_num = 0U; + uint32_t dword_len = 0U, len = 0U; + usb_hostchannel_struct *puhc; + + channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U); + puhc = &pudev->host.host_channel[channel_num]; + dword_len = (puhc->xfer_len + 3U) / 4U; + + while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) { + len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U; + + if (len > puhc->xfer_len) { + len = puhc->xfer_len; + + /* last packet */ + USB_GINTEN &= ~GINTF_PTXFEIF; + } + + dword_len = (puhc->xfer_len + 3U) / 4U; + usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); + + puhc->xfer_buff += len; + puhc->xfer_len -= len; + puhc->xfer_count += len; + } + + return 1U; +} + +/*! + \brief handle the host port interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_port (usb_core_handle_struct *pudev) +{ + uint8_t port_speed = 0U; + uint8_t port_reset = 0U; + uint32_t retval = 0U; + __IO uint32_t hostportdup = USB_HPCS; + + /* clear the interrupt bits in gintsts */ + hostportdup &= ~HPCS_PE; + hostportdup &= ~HPCS_PCD; + hostportdup &= ~HPCS_PEDC; + + /* port connect detected */ + if (USB_HPCS & HPCS_PCD) { + hostportdup |= HPCS_PCD; + usbh_hcd_int_fops->device_connected(pudev); + retval |= 1U; + } + + /* port enable changed */ + if (USB_HPCS & HPCS_PEDC) { + hostportdup |= HPCS_PEDC; + + if (USB_HPCS & HPCS_PE) { + port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U); + + if (HPRT_PRTSPD_LOW_SPEED == port_speed) { + USB_HFT = 6000U; + + if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) { + if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { + USB_FSLSCLOCK_INIT(HCTLR_6_MHZ); + } + port_reset = 1U; + } + } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) { + USB_HFT = 48000U; + + if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) { + if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { + USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); + } + port_reset = 1U; + } + } else { + /* for high speed device and others */ + port_reset = 1U; + } + } + } + + if (port_reset) { + usb_port_reset(pudev); + } + + /* clear port interrupts */ + USB_HPCS = hostportdup; + + return retval; +} + +/*! + \brief handle the out channel interrupt + \param[in] pudev: pointer to usb device instance + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num); + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + + channel_intr &= USB_HCHxINTEN((uint16_t)channel_num); + + if (channel_intr & HCHINTF_ACK) { + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; + } else if (channel_intr & HCHINTF_REQOVR) { + /* handle queue overrun interrupt */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; + } else if (channel_intr & HCHINTF_TF) { + /* handle transfer finished interrupt */ + puhc->err_count = 0U; + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; + puhc->status = HC_XF; + } else if (channel_intr & HCHINTF_STALL) { + /* handle stall */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; + usb_hostchannel_halt(pudev, channel_num); + puhc->status = HC_STALL; + } else if (channel_intr & HCHINTF_NAK) { + /* handle NAK */ + puhc->err_count = 0U; + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + puhc->status = HC_NAK; + } else if (channel_intr & HCHINTF_USBER) { + /* handle USB bus error */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + puhc->status = HC_TRACERR; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; + } else if (channel_intr & HCHINTF_NYET) { + /* handle NYET */ + puhc->err_count = 0U; + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + puhc->status = HC_NYET; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET; + } else if (channel_intr & HCHINTF_DTER) { + /* handle data toggle error */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + puhc->status= HC_DTGERR; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; + } else if (channel_intr & HCHINTF_CH) { + /* handle channel halted */ + USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; + + switch (puhc->status) { + case HC_XF: + puhc->urb_state = URB_DONE; + + if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18U)) { + puhc->data_tg_out ^= 1U; + } + break; + case HC_NAK: + puhc->urb_state = URB_NOTREADY; + break; + case HC_NYET: + puhc->urb_state = URB_NOTREADY; + break; + case HC_STALL: + puhc->urb_state = URB_STALL; + break; + case HC_TRACERR: + puhc->urb_state = URB_ERROR; + break; + default: + break; + } + + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the in channel interrupt + \param[in] pudev: pointer to usb device instance + \param[in] channel_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num) +{ + uint8_t endp_type = 0U; + usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; + + uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num); + __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num); + + channle_intf &= USB_HCHxINTEN((uint16_t)channel_num); + + endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U); + + if (channle_intf & HCHINTF_ACK) { + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; + } else if (channle_intf & HCHINTF_STALL) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + puhc->status = HC_STALL; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; + + /* NOTE: When there is a 'stall', reset also nak, + else, the pudev->host.status = HC_STALL + will be overwritten by 'nak' in code below */ + channle_intf &= ~HCHINTF_NAK; + + usb_hostchannel_halt(pudev, channel_num); + } else if (channle_intf & HCHINTF_DTER) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + puhc->status = HC_DTGERR; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; + } else { + /* no operation */ + } + /* handle queue overrun interrupt */ + if (channle_intf & HCHINTF_REQOVR) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; + } else if (channle_intf & HCHINTF_TF) { + /* handle transfer finished interrupt */ + puhc->status = HC_XF; + puhc->err_count = 0U; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; + + if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + puhc->data_tg_in ^= 1U; + } else if (USB_EPTYPE_INTR == endp_type) { + channel_ctrl |= HCHCTL_ODDFRM; + USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; + puhc->urb_state = URB_DONE; + } else { + /* no operation */ + } + } else if (channle_intf & HCHINTF_CH) { + /* handle channel halted */ + USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; + + switch (puhc->status) { + case HC_XF: + puhc->urb_state = URB_DONE; + break; + case HC_TRACERR: + case HC_DTGERR: + puhc->err_count = 0U; + puhc->urb_state = URB_ERROR; + break; + case HC_STALL: + puhc->urb_state = URB_STALL; + break; + default: + if (USB_EPTYPE_INTR == endp_type) { + puhc->data_tg_in ^= 1U; + } + break; + } + + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; + } else if (channle_intf & HCHINTF_USBER) { + /* handle USB bus error */ + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + puhc->status = HC_TRACERR; + usb_hostchannel_halt(pudev, channel_num); + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; + } else if (channle_intf & HCHINTF_NAK) { + /* handle NAK */ + if (USB_EPTYPE_INTR == endp_type) { + USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; + usb_hostchannel_halt(pudev, channel_num); + } + + puhc->status = HC_NAK; + USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; + + if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { + /* re-activate the channel */ + channel_ctrl |= HCHCTL_CEN; + channel_ctrl &= ~HCHCTL_CDIS; + USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; + } + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the rx fifo non-empty interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) +{ + uint32_t count = 0U; + __IO uint8_t channel_num = 0U; + __IO uint32_t rx_status = 0U; + uint32_t usbh_ch_ctl_reg = 0U; + usb_hostchannel_struct *puhc; + + /* disable the rx status queue level interrupt */ + USB_GINTEN &= ~GINTF_RXFNEIF; + + rx_status = USB_GRSTATP; + channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM); + puhc = &pudev->host.host_channel[channel_num]; + + switch ((rx_status & GRSTATRP_RPCKST) >> 17) { + case GRSTATR_RPCKST_IN: + count = (rx_status & GRSTATRP_BCOUNT) >> 4; + + /* read the data into the host buffer. */ + if ((count > 0U) && (puhc->xfer_buff != (void *)0)) { + usb_fifo_read(puhc->xfer_buff, (uint16_t)count); + + /* manage multiple Xfer */ + puhc->xfer_buff += count; + puhc->xfer_count += count; + + if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) { + /* re-activate the channel when more packets are expected */ + usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num); + usbh_ch_ctl_reg |= HCHCTL_CEN; + usbh_ch_ctl_reg &= ~HCHCTL_CDIS; + USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg; + } + } + break; + case GRSTATR_RPCKST_IN_XFER_COMP: + break; + case GRSTATR_RPCKST_DATA_TOGGLE_ERR: + count = (rx_status & GRSTATRP_BCOUNT) >> 4; + while (count > 0) { + rx_status = USB_GRSTATP; + count--; + } + break; + case GRSTATR_RPCKST_CH_HALTED: + default: + break; + } + + /* enable the rx status queue level interrupt */ + USB_GINTEN |= GINTF_RXFNEIF; + + return 1U; +} + +/*! + \brief handle the incomplete periodic transfer interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev) +{ + __IO uint32_t gint_flag = 0U; + + gint_flag = USB_HCHxCTL(0U); + USB_HCHxCTL(0U) = 0U; + + gint_flag = 0U; + + /* clear interrupt */ + gint_flag |= GINTF_ISOONCIF; + USB_GINTF = gint_flag; + + return 1U; +} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c new file mode 100644 index 0000000000..6052b906e4 --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c @@ -0,0 +1,834 @@ +/*! + \file usbh_std.c + \brief USB 2.0 standard function definition + + \version 2014-12-26, V1.0.0, firmware for GD32F10x + \version 2017-06-20, V2.0.0, firmware for GD32F10x + \version 2018-07-31, V2.1.0, firmware for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_core.h" +#include "usbh_usr.h" +#include "usbh_std.h" +#include "usbh_ctrl.h" + +uint8_t local_buffer[64U]; +uint8_t usbh_cfg_desc[512U]; +uint8_t enum_polling_handle_flag = 0U; + +static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); +static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); + +/* the enumeration state handle function array */ +void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = +{ + enum_idle_handle, + enum_set_addr_handle, + enum_get_full_dev_desc_handle, + enum_get_cfg_desc_handle, + enum_get_full_cfg_desc_handle, + enum_get_mfc_string_desc_handle, + enum_get_product_string_desc_handle, + enum_get_serialnum_string_desc_handle, + enum_set_configuration_handle, + enum_dev_configured_handle, +}; + +/* the enumeration state handle table */ +state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] = +{ + /* the current state the current event the next state the event function */ + {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move }, + {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move }, + {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move }, + {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move }, + {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move }, + {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move }, + {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move }, + {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move }, + {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move }, + {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, +}; + +/*! + \brief the polling function of enumeration state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval usb host status +*/ +usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) +{ + usbh_status_enum exe_state = USBH_BUSY; + usbh_state_handle_struct *p_state; + p_state = (usbh_state_handle_struct *)pustate; + + if (0U == enum_polling_handle_flag) { + enum_polling_handle_flag = 1U; + scd_table_push(p_state); + scd_state_move(p_state, ENUM_IDLE); + } + + /* start the enumeration state handle */ + scd_begin(p_state,ENUM_FSM_ID); + + if (0U == p_state->usbh_current_state_stack_top) { + enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); + } else { + enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state); + } + + /* determine the enumeration whether to complete */ + if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) { + puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; + enum_polling_handle_flag = 0U; + exe_state = USBH_OK; + } + + return exe_state; +} + +/*! + \brief the handle function of ENUM_IDLE state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_DEVDESC, + 8U); + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(100U); + } + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U); + puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0; + + /* issue reset */ + usb_port_reset(pudev); + + /* modify control channels configuration for maxpacket size */ + usbh_channel_modify (pudev, + puhost->control.hc_out_num, + 0U, + 0U, + 0U, + (uint16_t)puhost->control.ep0_size); + + usbh_channel_modify (pudev, + puhost->control.hc_in_num, + 0U, + 0U, + 0U, + (uint16_t)puhost->control.ep0_size); + + scd_event_handle(pudev, + puhost, + pustate, + ENUM_EVENT_SET_ADDR, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_FULL_DEV_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_DEVDESC, + USB_DEVDESC_SIZE); + } + + if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ + usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE); + puhost->usr_cb->device_desc_available(&puhost->device.dev_desc); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_CFG_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_SET_ADDR state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_set_addr_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS); + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(100U); + } + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + if ((void *)0 != pudev->mdelay) { + pudev->mdelay(2U); + } + puhost->device.address = USBH_DEVICE_ADDRESS; + + /* user callback for device address assigned */ + puhost->usr_cb->device_address_set(); + + /* modify control channels to update device address */ + usbh_channel_modify (pudev, + puhost->control.hc_in_num, + puhost->device.address, + 0U, + 0U, + 0U); + + usbh_channel_modify (pudev, + puhost->control.hc_out_num, + puhost->device.address, + 0U, + 0U, + 0U); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_FULL_DEV_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_CFG_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + uint16_t index = 0U; + + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_CFGDESC, + USB_CFGDESC_SIZE); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + /* save configuration descriptor for class parsing usage */ + for (; index < USB_CFGDESC_SIZE; index ++) { + usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; + } + + /* commands successfully sent and response received */ + usbh_cfg_desc_parse (&puhost->device.cfg_desc, + puhost->device.itf_desc, + puhost->device.ep_desc, + pudev->host.rx_buffer, + USB_CFGDESC_SIZE); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_FULL_CFG_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_FULL_CFG_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + + uint16_t index = 0U; + + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_CFGDESC, puhost->device.cfg_desc.wTotalLength); + } + + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + /* save configuration descriptor for class parsing usage */ + for (; index < puhost->device.cfg_desc.wTotalLength; index ++) { + usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; + } + + /* commands successfully sent and response received */ + usbh_cfg_desc_parse (&puhost->device.cfg_desc, + puhost->device.itf_desc, + puhost->device.ep_desc, + pudev->host.rx_buffer, + puhost->device.cfg_desc.wTotalLength); + + /* User callback for configuration descriptors available */ + puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc, + puhost->device.itf_desc, + puhost->device.ep_desc[0]); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_MFC_STRING_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_MFC_STRING_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC; + + if (0U != puhost->device.dev_desc.iManufacturer) { + if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_STRDESC | puhost->device.dev_desc.iManufacturer, + 0xffU); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); + puhost->usr_cb->manufacturer_string(local_buffer); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_PRODUCT_STRING_DESC, + pustate->usbh_current_state); + } + } else { + puhost->usr_cb->manufacturer_string("N/A"); + scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC); + } +} + +/*! + \brief the handle function of ENUM_GET_PRODUCT_STRING_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC; + + if (0U != puhost->device.dev_desc.iProduct) { + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_STRDESC | puhost->device.dev_desc.iProduct, + 0xffU); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); + + /* user callback for product string */ + puhost->usr_cb->product_string(local_buffer); + + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_SERIALNUM_STRING_DESC, + pustate->usbh_current_state); + } + } else { + puhost->usr_cb->product_string("N/A"); + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_GET_SERIALNUM_STRING_DESC, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_GET_SERIALNUM_STRING_DESC state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC; + + if (0U != puhost->device.dev_desc.iSerialNumber) { + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { + usbh_enum_desc_get(pudev, + puhost, + pudev->host.rx_buffer, + USB_REQTYPE_DEVICE | USB_STANDARD_REQ, + USB_STRDESC | puhost->device.dev_desc.iSerialNumber, + 0xffU); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ + usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); + + /* user callback for product string */ + puhost->usr_cb->serial_num_string(local_buffer); + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_SET_CONFIGURATION, + pustate->usbh_current_state); + } + } else { + puhost->usr_cb->serial_num_string("N/A"); + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_SET_CONFIGURATION, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_SET_CONFIGURATION state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_set_configuration_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION; + + if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) { + usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue); + } + + if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { + scd_event_handle(pudev, + puhost, + pustate, + ENUN_EVENT_DEV_CONFIGURED, + pustate->usbh_current_state); + } +} + +/*! + \brief the handle function of ENUM_DEV_CONFIGURED state + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] pustate: pointer to USB state driver + \param[out] none + \retval none +*/ +static void enum_dev_configured_handle (usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + usbh_state_handle_struct *pustate) +{ + puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED; + scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); +} + +/*! + \brief get descriptor in usb host enumeration stage + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] buf: buffer to store the descriptor + \param[in] ReqType: descriptor type + \param[in] ValueIdx: wValue for the GetDescriptr request + \param[in] Len: length of the descriptor + \param[out] none + \retval none +*/ +void usbh_enum_desc_get(usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + uint8_t *buf, + uint8_t req_type, + uint16_t value_idx, + uint16_t len) +{ + usb_setup_union *pSetup = &(puhost->control.setup); + + pSetup->b.bmRequestType = USB_DIR_IN | req_type; + pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR; + pSetup->b.wValue = value_idx; + + if (USB_STRDESC == (value_idx & 0xff00U)){ + pSetup->b.wIndex = 0x0409U; + } else { + pSetup->b.wIndex = 0U; + } + + pSetup->b.wLength = len; + + puhost->control.buff = buf; + puhost->control.length = len; + +} + +/*! + \brief set address in usb host enumeration stage + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] device_address: the device address + \param[out] none + \retval none +*/ +void usbh_enum_addr_set(usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + uint8_t device_address) +{ + usb_setup_union *p_setup = &(puhost->control.setup); + + p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; + p_setup->b.bRequest = USBREQ_SET_ADDRESS; + p_setup->b.wValue = (uint16_t)device_address; + p_setup->b.wIndex = 0U; + p_setup->b.wLength = 0U; + puhost->control.buff = 0U; + puhost->control.length = 0U; +} + +/*! + \brief set configuration in usb host enumeration stage + \param[in] pudev: pointer to USB device + \param[in] puhost: pointer to USB host + \param[in] cfg_idx: the index of the configuration + \param[out] none + \retval none +*/ +void usbh_enum_cfg_set(usb_core_handle_struct *pudev, + usbh_host_struct *puhost, + uint16_t cfg_idx) +{ + usb_setup_union *p_setup = &(puhost->control.setup); + + p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; + p_setup->b.bRequest = USBREQ_SET_CONFIGURATION; + p_setup->b.wValue = cfg_idx; + p_setup->b.wIndex = 0U; + p_setup->b.wLength = 0U; + puhost->control.buff = 0; + puhost->control.length = 0U; +} + +/*! + \brief parse the device descriptor + \param[in] dev_desc: device_descriptor destinaton address + \param[in] buf: buffer where the source descriptor is available + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len) +{ + dev_desc->Header.bLength = *(uint8_t *)(buf + 0U); + dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); + dev_desc->bcdUSB = SWAPBYTE(buf + 2U); + dev_desc->bDeviceClass = *(uint8_t *)(buf + 4U); + dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5U); + dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6U); + dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7U); + + if (len > 8U){ + /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ + dev_desc->idVendor = SWAPBYTE(buf + 8U); + dev_desc->idProduct = SWAPBYTE(buf + 10U); + dev_desc->bcdDevice = SWAPBYTE(buf + 12U); + dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); + dev_desc->iProduct = *(uint8_t *)(buf + 15U); + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); + dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17U); + } +} + +/*! + \brief parse the configuration descriptor + \param[in] cfg_desc: configuration descriptor address + \param[in] itf_desc: interface descriptor address + \param[in] ep_desc: endpoint descriptor address + \param[in] buf: buffer where the source descriptor is available + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, + usb_descriptor_interface_struct *itf_desc, + usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], + uint8_t *buf, + uint16_t len) +{ + usb_descriptor_interface_struct *pitf = NULL; + usb_descriptor_interface_struct temp_pitf; + usb_descriptor_endpoint_struct *pep = NULL; + usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf; + + uint8_t itf_ix = 0U; + uint8_t ep_ix = 0U; + uint16_t ptr = 0U; + static uint8_t prev_itf = 0U; + static uint16_t prev_ep_size = 0U; + + /* parse configuration descriptor */ + cfg_desc->Header.bLength = *(uint8_t *)(buf + 0U); + cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); + cfg_desc->wTotalLength = SWAPBYTE(buf + 2U); + cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4U); + cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5U); + cfg_desc->iConfiguration = *(uint8_t *)(buf + 6U); + cfg_desc->bmAttributes = *(uint8_t *)(buf + 7U); + cfg_desc->bMaxPower = *(uint8_t *)(buf + 8U); + + if (len > USB_CFGDESC_SIZE) { + ptr = USB_CFG_DESC_LEN; + + if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) { + pitf = (usb_descriptor_interface_struct *)0U; + + for (; ptr < cfg_desc->wTotalLength; ) { + pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr); + + if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) { + itf_ix = *((uint8_t *)pdesc + 2U); + pitf = &itf_desc[itf_ix]; + + if (*((uint8_t *)pdesc + 3U) < 3U) { + usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc); + + /* parse endpoint descriptors relative to the current interface */ + if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) { + for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) { + pdesc = usbh_next_desc_get((void* )pdesc, &ptr); + + if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) { + pep = &ep_desc[itf_ix][ep_ix]; + + if (prev_itf != itf_ix) { + prev_itf = itf_ix; + usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); + } else { + if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) { + break; + } else { + usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); + } + } + + usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc); + prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4); + ep_ix++; + } + } + } + } + } + } + } + + prev_ep_size = 0U; + prev_itf = 0U; + } +} + +/*! + \brief parse the interface descriptor + \param[in] itf_desc: interface descriptor destination + \param[in] buf: buffer where the descriptor data is available + \param[out] none + \retval none +*/ +void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf) +{ + itf_desc->Header.bLength = *(uint8_t *)(buf + 0U); + itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); + itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2U); + itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3U); + itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4U); + itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5U); + itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6U); + itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7U); + itf_desc->iInterface = *(uint8_t *)(buf + 8U); +} + +/*! + \brief parse the endpoint descriptor + \param[in] ep_desc: endpoint descriptor destination address + \param[in] buf: buffer where the parsed descriptor stored + \param[out] none + \retval none +*/ +void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf) +{ + ep_desc->Header.bLength = *(uint8_t *)(buf + 0U); + ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); + ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2U); + ep_desc->bmAttributes = *(uint8_t *)(buf + 3U); + ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4U); + ep_desc->bInterval = *(uint8_t *)(buf + 6U); +} + +/*! + \brief parse the string descriptor + \param[in] psrc: source pointer containing the descriptor data + \param[in] pdest: destination address pointer + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len) +{ + uint16_t strlength; + uint16_t idx; + + /* the unicode string descriptor is not null-terminated. the string length is + computed by substracting two from the value of the first byte of the descriptor. + */ + + /* check which is lower size, the size of string or the length of bytes read from the device */ + + if (USB_DESCTYPE_STRING == psrc[1]){ + /* make sure the descriptor is string type */ + + /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ + strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len); + psrc += 2; /* adjust the offset ignoring the string len and descriptor type */ + + for (idx = 0U; idx < strlength; idx += 2U) { + /* copy only the string and ignore the unicode id, hence add the src */ + *pdest = psrc[idx]; + pdest++; + } + + *pdest = 0U; /* mark end of string */ + } +} + +/*! + \brief get the next descriptor header + \param[in] pbuf: pointer to buffer where the cfg descriptor is available + \param[in] ptr: data popinter inside the configuration descriptor + \param[out] none + \retval next descriptor header +*/ +usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr) +{ + uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength; + + usb_descriptor_header_struct *pnext; + + *ptr += len; + + pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len); + + return(pnext); +} + diff --git a/bsp/gd32107c-eval/Libraries/SConscript b/bsp/gd32107c-eval/Libraries/SConscript new file mode 100644 index 0000000000..bdfd09f67b --- /dev/null +++ b/bsp/gd32107c-eval/Libraries/SConscript @@ -0,0 +1,33 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Glob('GD32F10x_standard_peripheral/Source/*.c') +src += [cwd + '/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/CMSIS/GD/GD32F10x/Source/GCC/startup_gd32f10x_cl.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [cwd + '/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [cwd + '/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s'] + +path = [ + cwd + '/CMSIS/GD/GD32F10x/Include', + cwd + '/CMSIS', + cwd + '/GD32F10x_standard_peripheral/Include',] + +if GetDepend(['RT_USING_BSP_USB']): + path += [cwd + '/GD32F10x_usbfs_driver/Include'] + src += [cwd + '/GD32F10x_usbfs_driver/Source'] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F10X_CL'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/gd32107c-eval/README.md b/bsp/gd32107c-eval/README.md new file mode 100644 index 0000000000..3ae69f8226 --- /dev/null +++ b/bsp/gd32107c-eval/README.md @@ -0,0 +1,93 @@ +# GD32105C-EVAL # + +## 1. 简介 + +[GD32105C-EVAL](http://gd32mcu.21ic.com)是兆易科技提供的开发板，使用 GD32F105VCT6 作为主控制器。提供包括扩展引脚在内的及 SWD, Reset, Boot, User button key, LED, CAN, I2C, I2S, USART, RTC, LCD, SPI, ADC, DAC, EXMC, CTC, SDIO,USBD, GD-Link 等外设资源。 + +板载主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|CPU| Cortex-M3| +|主频| 120MHz | +|SRAM| 96KB | +|Flash| 256KB | + +## 2. 编译说明 + +GD32105C-EVAL板级包支持MDK5、IAR开发环境和GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| -- | -- | +| MDK5 | MDK5.25 | +| IAR | IAR8.20 | +| GCC | GCC 5.4.1 20160919 (release) | + +## 3. 烧写及执行 + +供电方式：开发板使用 Mini USB 接口或者 DC-005 连接器提供 5V 电源。 + +下载程序：下载程序到开发板需要一套 JLink 或者使用 GD-Link 工具。 + +解决IDE "Missing Device(s)"问题" +* MDK5: 安装GigaDevice.GD32F10x_DFP.2.0.1.pack，在 Folder Selection 中的 Destination Folder 那一栏选择 Keil uVision5 软件的安装目录，如 C:\Keil_v5，然后在 Option for Target 的 Device 选择对应的器件，同时在 Option forTarget 的 C/C++中添加路径 C:\Keil_v5\ARM\Pack\ARM\CMSIS\4.2.0\CMSIS\Include。 + +* IAR：安装 IAR_GD32F10x_ADDON.2.0.0.exe + +### 3.1 配置和仿真 + +工程已经默认使能了RT-Thread UART驱动、GPIO驱动、SPI驱动、I2C驱动。若想进一步配置工程请 +使用ENV工具。 + +### 3.2 运行结果 + +打开MDK或者IAR工程，进入仿真后全速运行，将会在串口0上看到RT-Thread的启动logo信息： + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Aug 23 2021 + 2006 - 2021 Copyright by rt-thread team +msh > + +``` + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0/1/2/3 | +| GPIO | 支持 | | +| SPI | 支持 | SPI0/1/2 | +| I2C | 支持 | I2C0/1| + +### 4.1 IO在板级支持包中的映射情况 + +| IO号 | 板级包中的定义 | +| -- | -- | +| PA9 | USART0 TX | +| PA10 | USART0 RX | +| PA2 | USART1 TX | +| PA3 | USART1 RX | +| PA5| SPI0 SCK | +| PA6 | SPI0 MISO | +| PA6 | SPI0 MOSI | +| PB13| SPI1 SCK | +| PB14 | SPI1 MISO | +| PB15 | SPI1 MOSI | +| PB6| I2C0 SCL | +| PB7 | I2C0 SDA | +| PB10| I2C1 SCL | +| PB11 | I2C1 SDA | + +## 5. 联系人信息 + +维护人： + +- [lianzhian](https://gitee.com/qidiyun) + +## 6. 参考 + +* [GD32105C-EVAL](http://gd32mcu.21ic.com/site) + + diff --git a/bsp/gd32107c-eval/SConscript b/bsp/gd32107c-eval/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/gd32107c-eval/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/gd32107c-eval/SConstruct b/bsp/gd32107c-eval/SConstruct new file mode 100644 index 0000000000..215861f94c --- /dev/null +++ b/bsp/gd32107c-eval/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread-gd32f30x.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/gd32107c-eval/applications/SConscript b/bsp/gd32107c-eval/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/gd32107c-eval/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/gd32107c-eval/applications/main.c b/bsp/gd32107c-eval/applications/main.c new file mode 100644 index 0000000000..83b68664a3 --- /dev/null +++ b/bsp/gd32107c-eval/applications/main.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-24 lianzhian first implementation + */ +#include +#include +#include + + +/* defined the LED0 pin: PF0 */ +#define LED0_PIN GET_PIN(C, 0) + +int main(void) +{ + int count = 1; + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} + diff --git a/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf b/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf new file mode 100644 index 0000000000..d6665c3649 --- /dev/null +++ b/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807ffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +export symbol __ICFEDIT_region_RAM_end__; + +define symbol __region_RAM1_start__ = 0x10000000; +define symbol __region_RAM1_end__ = 0x1000FFFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; \ No newline at end of file diff --git a/bsp/gd32107c-eval/board/linker_script/gd32_rom.ld b/bsp/gd32107c-eval/board/linker_script/gd32_rom.ld new file mode 100644 index 0000000000..4af47d1dcb --- /dev/null +++ b/bsp/gd32107c-eval/board/linker_script/gd32_rom.ld @@ -0,0 +1,142 @@ +/* + * linker script for GD32F30x with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 512KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 64KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/gd32107c-eval/board/linker_script/gd32_rom.sct b/bsp/gd32107c-eval/board/linker_script/gd32_rom.sct new file mode 100644 index 0000000000..b3144a70e0 --- /dev/null +++ b/bsp/gd32107c-eval/board/linker_script/gd32_rom.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x000040000 { ; load region size_region + ER_IROM1 0x08000000 0x000040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00018000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/gd32107c-eval/drivers/Kconfig b/bsp/gd32107c-eval/drivers/Kconfig new file mode 100644 index 0000000000..ad63f6f612 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/Kconfig @@ -0,0 +1,69 @@ +menu "Hardware Drivers Config" + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config SOC_SERIES_GD32F1 + bool + default y + config SOC_GD32107C + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select SOC_SERIES_GD32F1 + default y + + config RT_USING_USART0 + bool "Using USART0" + select RT_USING_SERIAL + default y + + config RT_USING_USART1 + bool "Using USART1" + select RT_USING_SERIAL + default n + + config RT_USING_USART2 + bool "Using USART2" + select RT_USING_SERIAL + default n + + config RT_USING_UART3 + bool "Using UART3" + select RT_USING_SERIAL + default n + + config RT_USING_SPI0 + bool "Using SPI0" + select RT_USING_SPI + default y + + config RT_USING_SPI1 + bool "Using SPI1" + select RT_USING_SPI + default n + + config RT_USING_SPI2 + bool "Using SPI2" + select RT_USING_SPI + default n + + config RT_USING_I2C0 + bool "Using I2C0" + select RT_USING_I2C + default n + + config RT_USING_I2C1 + bool "Using I2C1" + select RT_USING_I2C + default n +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/gd32107c-eval/drivers/SConscript b/bsp/gd32107c-eval/drivers/SConscript new file mode 100644 index 0000000000..77badf9a32 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/SConscript @@ -0,0 +1,33 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'drivers') + +# add the general drivers. +src = Split(""" +board.c +drv_usart.c +""") + +CPPPATH = [cwd] + +# add spi drivers. +if GetDepend('RT_USING_SPI'): + src += ['drv_spi.c'] + +# add i2c drivers. +if GetDepend('RT_USING_I2C'): + src += ['drv_i2c.c'] + +# add pin drivers. +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +# add spi flash drivers. +if GetDepend('RT_USING_SFUD'): + src += ['drv_spi_flash.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/gd32107c-eval/drivers/board.c b/bsp/gd32107c-eval/drivers/board.c new file mode 100644 index 0000000000..6cfd569f1a --- /dev/null +++ b/bsp/gd32107c-eval/drivers/board.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ +#include +#include +#include +#include + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial GD32 board. + */ +void rt_hw_board_init() +{ + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); +#endif + + SystemClock_Config(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); +#endif +} + +/*@}*/ diff --git a/bsp/gd32107c-eval/drivers/board.h b/bsp/gd32107c-eval/drivers/board.h new file mode 100644 index 0000000000..7b791f25c9 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/board.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "drv_gpio.h" + +// Internal SRAM memory size[Kbytes] <8-64> +// Default: 64 +#ifdef __ICCARM__ +// Use *.icf ram symbal, to avoid hardcode. +extern char __ICFEDIT_region_RAM_end__; +#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ +#else +#define GD32_SRAM_SIZE 96 +#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) +#endif + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END GD32_SRAM_END + +#endif + +//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32107c-eval/drivers/drv_comm.h b/bsp/gd32107c-eval/drivers/drv_comm.h new file mode 100644 index 0000000000..0881776e60 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_comm.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef __DRV_COMM_H__ +#define __DRV_COMM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_HWTIMER_H__ */ + diff --git a/bsp/gd32107c-eval/drivers/drv_gpio.c b/bsp/gd32107c-eval/drivers/drv_gpio.c new file mode 100644 index 0000000000..40cd8df4b5 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_gpio.c @@ -0,0 +1,552 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ +#include +#include +#include "drv_gpio.h" +#include +#include +#include "gd32f10x.h" +#include "gd32f10x_exti.h" + +#ifdef RT_USING_PIN + +#define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \ + GPIO_PIN_##pin, GPIO_PORT_SOURCE_GPIO##port, GPIO_PIN_SOURCE_##pin} +#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} + +/* GD32 GPIO driver */ +struct pin_index +{ + rt_int16_t index; + rcu_periph_enum clk; + rt_uint32_t gpio_periph; + rt_uint32_t pin; + rt_uint8_t port_src; + rt_uint8_t pin_src; +}; + +static const struct pin_index pins[] = +{ + __GD32_PIN(0 , A, 0 ), + __GD32_PIN(1 , A, 1 ), + __GD32_PIN(2 , A, 2 ), + __GD32_PIN(3 , A, 3 ), + __GD32_PIN(4 , A, 4 ), + __GD32_PIN(5 , A, 5 ), + __GD32_PIN(6 , A, 6 ), + __GD32_PIN(7 , A, 7 ), + __GD32_PIN(8 , A, 8 ), + __GD32_PIN(9 , A, 9 ), + __GD32_PIN(10, A, 10), + __GD32_PIN(11, A, 11), + __GD32_PIN(12, A, 12), + __GD32_PIN(13, A, 13), + __GD32_PIN(14, A, 14), + __GD32_PIN(15, A, 15), + + __GD32_PIN(16, B, 0), + __GD32_PIN(17, B, 1), + __GD32_PIN(18, B, 2), + __GD32_PIN(19, B, 3), + __GD32_PIN(20, B, 4), + __GD32_PIN(21, B, 5), + __GD32_PIN(22, B, 6), + __GD32_PIN(23, B, 7), + __GD32_PIN(24, B, 8), + __GD32_PIN(25, B, 9), + __GD32_PIN(26, B, 10), + __GD32_PIN(27, B, 11), + __GD32_PIN(28, B, 12), + __GD32_PIN(29, B, 13), + __GD32_PIN(30, B, 14), + __GD32_PIN(31, B, 15), + + __GD32_PIN(32, C, 0), + __GD32_PIN(33, C, 1), + __GD32_PIN(34, C, 2), + __GD32_PIN(35, C, 3), + __GD32_PIN(36, C, 4), + __GD32_PIN(37, C, 5), + __GD32_PIN(38, C, 6), + __GD32_PIN(39, C, 7), + __GD32_PIN(40, C, 8), + __GD32_PIN(41, C, 9), + __GD32_PIN(42, C, 10), + __GD32_PIN(43, C, 11), + __GD32_PIN(44, C, 12), + __GD32_PIN(45, C, 13), + __GD32_PIN(46, C, 14), + __GD32_PIN(47, C, 15), + + __GD32_PIN(48, D, 0), + __GD32_PIN(49, D, 1), + __GD32_PIN(50, D, 2), + __GD32_PIN(51, D, 3), + __GD32_PIN(52, D, 4), + __GD32_PIN(53, D, 5), + __GD32_PIN(54, D, 6), + __GD32_PIN(55, D, 7), + __GD32_PIN(56, D, 8), + __GD32_PIN(57, D, 9), + __GD32_PIN(58, D, 10), + __GD32_PIN(59, D, 11), + __GD32_PIN(60, D, 12), + __GD32_PIN(61, D, 13), + __GD32_PIN(62, D, 14), + __GD32_PIN(63, D, 15), + + __GD32_PIN(64, E, 0), + __GD32_PIN(65, E, 1), + __GD32_PIN(66, E, 2), + __GD32_PIN(67, E, 3), + __GD32_PIN(68, E, 4), + __GD32_PIN(69, E, 5), + __GD32_PIN(70, E, 6), + __GD32_PIN(71, E, 7), + __GD32_PIN(72, E, 8), + __GD32_PIN(73, E, 9), + __GD32_PIN(74, E, 10), + __GD32_PIN(75, E, 11), + __GD32_PIN(76, E, 12), + __GD32_PIN(77, E, 13), + __GD32_PIN(78, E, 14), + __GD32_PIN(79, E, 15), + + __GD32_PIN(80, F, 0), + __GD32_PIN(81, F, 1), + __GD32_PIN(82, F, 2), + __GD32_PIN(83, F, 3), + __GD32_PIN(84, F, 4), + __GD32_PIN(85, F, 5), + __GD32_PIN(86, F, 6), + __GD32_PIN(87, F, 7), + __GD32_PIN(88, F, 8), + __GD32_PIN(89, F, 9), + __GD32_PIN(90, F, 10), + __GD32_PIN(91, F, 11), + __GD32_PIN(92, F, 12), + __GD32_PIN(93, F, 13), + __GD32_PIN(94, F, 14), + __GD32_PIN(95, F, 15), + + __GD32_PIN(96, G, 0), + __GD32_PIN(97, G, 1), + __GD32_PIN(98, G, 2), + __GD32_PIN(99, G, 3), + __GD32_PIN(100, G, 4), + __GD32_PIN(101, G, 5), + __GD32_PIN(102, G, 6), + __GD32_PIN(103, G, 7), + __GD32_PIN(104, G, 8), + __GD32_PIN(105, G, 9), + __GD32_PIN(106, G, 10), + __GD32_PIN(107, G, 11), + __GD32_PIN(108, G, 12), + __GD32_PIN(109, G, 13), + __GD32_PIN(110, G, 14), + __GD32_PIN(111, G, 15), + + +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_9_IRQn}, + {GPIO_PIN_6, EXTI5_9_IRQn}, + {GPIO_PIN_7, EXTI5_9_IRQn}, + {GPIO_PIN_8, EXTI5_9_IRQn}, + {GPIO_PIN_9, EXTI5_9_IRQn}, + {GPIO_PIN_10, EXTI10_15_IRQn}, + {GPIO_PIN_11, EXTI10_15_IRQn}, + {GPIO_PIN_12, EXTI10_15_IRQn}, + {GPIO_PIN_13, EXTI10_15_IRQn}, + {GPIO_PIN_14, EXTI10_15_IRQn}, + {GPIO_PIN_15, EXTI10_15_IRQn}, +}; +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(rt_uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + rt_uint32_t pin_mode; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* GPIO Periph clock enable */ + rcu_periph_clock_enable(index->clk); + pin_mode = GPIO_MODE_OUT_PP; + + switch(mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + pin_mode = GPIO_MODE_OUT_PP; + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + pin_mode = GPIO_MODE_OUT_OD; + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + pin_mode = GPIO_MODE_IN_FLOATING; + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + pin_mode = GPIO_MODE_IPU; + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + pin_mode = GPIO_MODE_IPD; + break; + default: + break; + } + + gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); +} + +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); +} + +static int _pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = gpio_input_bit_get(index->gpio_periph, index->pin); + + return value; +} + + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + rt_uint8_t i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; +static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == pin && + pin_irq_hdr_tab[hdr_index].hdr == hdr && + pin_irq_hdr_tab[hdr_index].mode == mode && + pin_irq_hdr_tab[hdr_index].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[hdr_index].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EFULL; + } + pin_irq_hdr_tab[hdr_index].pin = pin; + pin_irq_hdr_tab[hdr_index].hdr = hdr; + pin_irq_hdr_tab[hdr_index].mode = mode; + pin_irq_hdr_tab[hdr_index].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[hdr_index].pin = -1; + pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; + pin_irq_hdr_tab[hdr_index].mode = 0; + pin_irq_hdr_tab[hdr_index].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t hdr_index = -1; + exti_trig_type_enum trigger_mode; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + if (enabled == PIN_IRQ_ENABLE) + { + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_EINVAL; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + irqmap = &pin_irq_map[hdr_index]; + + switch (pin_irq_hdr_tab[hdr_index].mode) + { + case PIN_IRQ_MODE_RISING: + trigger_mode = EXTI_TRIG_RISING; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = EXTI_TRIG_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = EXTI_TRIG_BOTH; + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + rcu_periph_clock_enable(RCU_AF); + + /* enable and set interrupt priority */ + nvic_irq_enable(irqmap->irqno, 5U, 0U); + + /* connect EXTI line to GPIO pin */ + gpio_exti_source_select(index->port_src, index->pin_src); + + /* configure EXTI line */ + exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); + exti_interrupt_flag_clear((exti_line_enum)(index->pin)); + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_EINVAL; + } + nvic_irq_disable(irqmap->irqno); + } + else + { + return RT_EINVAL; + } + + return RT_EOK; +} +const static struct rt_pin_ops _gd32_pin_ops = +{ + _pin_mode, + _pin_write, + _pin_read, + _pin_attach_irq, + _pin_detach_irq, + _pin_irq_enable, + RT_NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) +{ + if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) + { + pin_irq_hdr(exti_line); + exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); + } +} +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(0); + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(1); + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(2); + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(3); + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(4); + rt_interrupt_leave(); +} +void EXTI5_9_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(5); + GD32_GPIO_EXTI_IRQHandler(6); + GD32_GPIO_EXTI_IRQHandler(7); + GD32_GPIO_EXTI_IRQHandler(8); + GD32_GPIO_EXTI_IRQHandler(9); + rt_interrupt_leave(); +} +void EXTI10_15_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(10); + GD32_GPIO_EXTI_IRQHandler(11); + GD32_GPIO_EXTI_IRQHandler(12); + GD32_GPIO_EXTI_IRQHandler(13); + GD32_GPIO_EXTI_IRQHandler(14); + GD32_GPIO_EXTI_IRQHandler(15); + rt_interrupt_leave(); +} + +#endif diff --git a/bsp/gd32107c-eval/drivers/drv_gpio.h b/bsp/gd32107c-eval/drivers/drv_gpio.h new file mode 100644 index 0000000000..0cdedb9acb --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_gpio.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __GD32_PORT(port) GPIO##port + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN) + +#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) + +#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/gd32107c-eval/drivers/drv_i2c.c b/bsp/gd32107c-eval/drivers/drv_i2c.c new file mode 100644 index 0000000000..6d3d2cedcc --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_i2c.c @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#include "drv_i2c.h" +#include +#include "gd32f10x.h" + +#ifdef RT_USING_I2C + +#include + +#define DBG_TAG "drv.I2C" +#ifdef RT_I2C_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif +#include + +#ifdef RT_USING_I2C_BITOPS + +/*user can change this*/ +#define I2C_BUS_NAME "i2c2" + +/*user should change this to adapt specific board*/ +#define I2C_SCL_PIN GPIO_PIN_4 +#define I2C_SCL_PORT GPIOE +#define I2C_SCL_CLK RCU_GPIOE +#define I2C_SDA_PIN GPIO_PIN_5 +#define I2C_SDA_PORT GPIOE +#define I2C_SDA_CLK RCU_GPIOE + +struct gd32_i2c_bit_data +{ + struct + { + rcu_periph_enum clk; + rt_uint32_t port; + rt_uint32_t pin; + }scl, sda; +}; + +static void gpio_set_sda(void *data, rt_int32_t state) +{ + struct gd32_i2c_bit_data* bd = data; + + if (state) + { + gpio_bit_set(bd->sda.port, bd->sda.pin); + } + else + { + gpio_bit_reset(bd->sda.port, bd->sda.pin); + } +} + +static void gpio_set_scl(void *data, rt_int32_t state) +{ + struct gd32_i2c_bit_data* bd = data; + if (state) + { + gpio_bit_set(bd->scl.port, bd->scl.pin); + } + else + { + gpio_bit_reset(bd->scl.port, bd->scl.pin); + } +} + +static rt_int32_t gpio_get_sda(void *data) +{ + struct gd32_i2c_bit_data* bd = data; + + return gpio_input_bit_get(bd->sda.port, bd->sda.pin); +} + +static rt_int32_t gpio_get_scl(void *data) +{ + struct gd32_i2c_bit_data* bd = data; + + return gpio_input_bit_get(bd->scl.port, bd->scl.pin); +} + +static void gpio_udelay(rt_uint32_t us) +{ + int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us); + while(i) + { + i--; + } +} + +static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd) +{ + rcu_periph_clock_enable(bd->sda.clk); + rcu_periph_clock_enable(bd->scl.clk); + gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin); + gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin); + + gpio_bit_set(bd->sda.port, bd->sda.pin); + gpio_bit_set(bd->scl.port, bd->scl.pin); +} + +#else /* use hardware i2c */ + +struct gd32_i2c_bus +{ + struct rt_i2c_bus_device parent; + rt_uint32_t i2c_periph; +}; + +static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte) +{ + /* wait until I2C bus is idle */ + while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); + + /* send a start condition to I2C bus */ + i2c_start_on_bus(i2c_periph); + + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); + + /* send slave address to I2C bus */ + i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER); + + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); + + /* clear the ADDSEND bit */ + i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); + + if(1 == data_byte){ + /* disable acknowledge */ + i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(i2c_periph); + } + + /* while there is data to be read */ + while(data_byte) + { + /* wait until the RBNE bit is set and clear it */ + if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)) + { + /* read a byte from the EEPROM */ + *p_buffer = i2c_data_receive(i2c_periph); + + /* point to the next location where the byte read will be saved */ + p_buffer++; + + /* decrement the read bytes counter */ + data_byte--; + if(1 == data_byte) + { + /* disable acknowledge */ + i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(i2c_periph); + } + } + } + + /* wait until the stop condition is finished */ + while(I2C_CTL0(i2c_periph)&0x0200); + + /* enable acknowledge */ + i2c_ack_config(i2c_periph,I2C_ACK_ENABLE); + + i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT); + + return 0; +} + +static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte) +{ + /* wait until I2C bus is idle */ + while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); + + /* send a start condition to I2C bus */ + i2c_start_on_bus(i2c_periph); + + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); + + /* send slave address to I2C bus */ + i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER); + + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); + + /* clear the ADDSEND bit */ + i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); + + /* wait until the transmit data buffer is empty */ + while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE)); + + /* while there is data to be read */ + while(data_byte) + { + i2c_data_transmit(i2c_periph, *p_buffer); + + /* point to the next byte to be written */ + p_buffer++; + + /* decrement the write bytes counter */ + data_byte --; + + /* wait until BTC bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC)); + } + + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(i2c_periph); + + /* wait until the stop condition is finished */ + while(I2C_CTL0(i2c_periph)&0x0200); + + return 0; +} + +static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + rt_err_t ret = RT_ERROR; + + struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_ADDR_10BIT) + { + i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0); + } + else + { + i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0); + } + if (msg->flags & RT_I2C_RD) + { + if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) + { + LOG_E("i2c bus write failed,i2c bus stop!"); + goto out; + } + } + else + { + if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) + { + LOG_E("i2c bus write failed,i2c bus stop!"); + goto out; + } + } + } + + ret = i; + +out: + LOG_E("send stop condition\n"); + + return ret; +} + +static const struct rt_i2c_bus_device_ops i2c_ops = +{ + gd32_i2c_xfer, + RT_NULL, + RT_NULL +}; + +#endif /* RT_USING_I2C_BITOPS */ + +int rt_hw_i2c_init(void) +{ +#ifdef RT_USING_I2C_BITOPS + { + static struct rt_i2c_bus_device i2c_device; + static const struct gd32_i2c_bit_data _i2c_bdata = + { + /* SCL */ + { I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN}, + /* SDA */ + { I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN}, + }; + + static const struct rt_i2c_bit_ops _i2c_bit_ops = + { + (void*)&_i2c_bdata, + gpio_set_sda, + gpio_set_scl, + gpio_get_sda, + gpio_get_scl, + gpio_udelay, + 1, + 100 + }; + + drv_i2c_gpio_init(&_i2c_bdata); + + i2c_device.priv = (void *)&_i2c_bit_ops; + rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); + } + +#else /* register hardware I2C */ + +#ifdef RT_USING_I2C0 +#define I2C0_SPEED 100000 + + static struct gd32_i2c_bus gd32_i2c0; + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + + /* connect PB6 to I2C0_SCL, PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); + + /* enable I2C clock */ + rcu_periph_clock_enable(RCU_I2C0); + /* configure I2C clock */ + i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2); + + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0,I2C_ACK_ENABLE); + + rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus)); + gd32_i2c0.parent.ops = &i2c_ops; + gd32_i2c0.i2c_periph = I2C0; + rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0"); +#endif + +#ifdef RT_USING_I2C1 +#define I2C1_SPEED 100000 + + static struct gd32_i2c_bus gd32_i2c1; + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + + /* connect PB10 to I2C1_SCL, PB11 to I2C1_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11); + + /* enable I2C clock */ + rcu_periph_clock_enable(RCU_I2C1); + /* configure I2C clock */ + i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2); + + i2c_enable(I2C1); + /* enable acknowledge */ + i2c_ack_config(I2C1,I2C_ACK_ENABLE); + + rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus)); + gd32_i2c1.parent.ops = &i2c_ops; + gd32_i2c1.i2c_periph = I2C1; + rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1"); +#endif + +#endif /* RT_USING_I2C_BITOPS */ + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif +/* end of i2c driver */ diff --git a/bsp/gd32107c-eval/drivers/drv_i2c.h b/bsp/gd32107c-eval/drivers/drv_i2c.h new file mode 100644 index 0000000000..fb34ff2b09 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_i2c.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef __DRV_I2C__ +#define __DRV_I2C__ + + +#endif diff --git a/bsp/gd32107c-eval/drivers/drv_spi.c b/bsp/gd32107c-eval/drivers/drv_spi.c new file mode 100644 index 0000000000..3f9e86cb41 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_spi.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#include "drv_spi.h" +#include "gd32f10x.h" +#include + +#if defined(RT_USING_SPI) && defined(RT_USING_PIN) +#include + +#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \ + !defined(RT_USING_SPI2) +#error "Please define at least one SPIx" +#endif + +/* #define DEBUG */ +#ifdef DEBUG +#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) +#endif + +/* private rt-thread spi ops function */ +static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); +static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); + +static struct rt_spi_ops gd32_spi_ops = +{ + configure, + xfer +}; + +static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) +{ + spi_parameter_struct spi_init_struct; + + rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + if(configuration->data_width <= 8) + { + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + } + else if(configuration->data_width <= 16) + { + spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT; + } + else + { + return RT_EIO; + } + + { + rcu_clock_freq_enum spi_src; + rt_uint32_t spi_apb_clock; + rt_uint32_t max_hz; + + max_hz = configuration->max_hz; + + DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS)); + DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2)); + DEBUG_PRINTF("max freq: %d\n", max_hz); + + if (spi_periph == SPI1 || spi_periph == SPI2) + { + spi_src = CK_APB1; + } + else + { + spi_src = CK_APB2; + } + spi_apb_clock = rcu_clock_freq_get(spi_src); + + if(max_hz >= spi_apb_clock/2) + { + spi_init_struct.prescale = SPI_PSC_2; + } + else if (max_hz >= spi_apb_clock/4) + { + spi_init_struct.prescale = SPI_PSC_4; + } + else if (max_hz >= spi_apb_clock/8) + { + spi_init_struct.prescale = SPI_PSC_8; + } + else if (max_hz >= spi_apb_clock/16) + { + spi_init_struct.prescale = SPI_PSC_16; + } + else if (max_hz >= spi_apb_clock/32) + { + spi_init_struct.prescale = SPI_PSC_32; + } + else if (max_hz >= spi_apb_clock/64) + { + spi_init_struct.prescale = SPI_PSC_64; + } + else if (max_hz >= spi_apb_clock/128) + { + spi_init_struct.prescale = SPI_PSC_128; + } + else + { + /* min prescaler 256 */ + spi_init_struct.prescale = SPI_PSC_256; + } + } /* baudrate */ + + switch(configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + break; + case RT_SPI_MODE_1: + spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; + break; + case RT_SPI_MODE_2: + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; + break; + case RT_SPI_MODE_3: + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + break; + } + + /* MSB or LSB */ + if(configuration->mode & RT_SPI_MSB) + { + spi_init_struct.endian = SPI_ENDIAN_MSB; + } + else + { + spi_init_struct.endian = SPI_ENDIAN_LSB; + } + + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_MASTER; + spi_init_struct.nss = SPI_NSS_SOFT; + + spi_init(spi_periph, &spi_init_struct); + + spi_crc_off(spi_periph); + + spi_enable(spi_periph); + + return RT_EOK; +}; + +static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) +{ + rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data; + rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; + struct rt_spi_configuration * config = &device->config; + + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + + /* take CS */ + if(message->cs_take) + { + rt_pin_write(gd32_cs_pin, PIN_LOW); + DEBUG_PRINTF("spi take cs\n"); + } + + { + if(config->data_width <= 8) + { + const rt_uint8_t * send_ptr = message->send_buf; + rt_uint8_t * recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + DEBUG_PRINTF("spi poll transfer start: %d\n", size); + + while(size--) + { + rt_uint8_t data = 0xFF; + + if(send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /* Todo: replace register read/write by gd32f3 lib */ + /* Wait until the transmit buffer is empty */ + while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); + /* Send the byte */ + spi_i2s_data_transmit(spi_periph, data); + + /* Wait until a data is received */ + while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); + /* Get the received data */ + data = spi_i2s_data_receive(spi_periph); + + if(recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + DEBUG_PRINTF("spi poll transfer finsh\n"); + } + else if(config->data_width <= 16) + { + const rt_uint16_t * send_ptr = message->send_buf; + rt_uint16_t * recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + while(size--) + { + rt_uint16_t data = 0xFF; + + if(send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /*Wait until the transmit buffer is empty */ + while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); + /* Send the byte */ + spi_i2s_data_transmit(spi_periph, data); + + /*Wait until a data is received */ + while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); + /* Get the received data */ + data = spi_i2s_data_receive(spi_periph); + + if(recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + } + } + + /* release CS */ + if(message->cs_release) + { + rt_pin_write(gd32_cs_pin, PIN_HIGH); + DEBUG_PRINTF("spi release cs\n"); + } + + return message->length; +}; + +int gd32_hw_spi_init(void) +{ + int result = 0; +#ifdef RT_USING_SPI0 + static struct rt_spi_bus spi_bus0; + spi_bus0.parent.user_data = (void *)SPI0; + + result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops); + + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_SPI0); + /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + +#endif +#ifdef RT_USING_SPI1 + static struct rt_spi_bus spi_bus1; + spi_bus1.parent.user_data = (void *)SPI1; + + result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops); + + rcu_periph_clock_enable(RCU_SPI1); + rcu_periph_clock_enable(RCU_GPIOB); + + /* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15); + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14); +#endif +#ifdef RT_USING_SPI2 + static struct rt_spi_bus spi_bus2; + spi_bus2.parent.user_data = (void *)SPI2; + + result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); + + rcu_periph_clock_enable(RCU_SPI2); + rcu_periph_clock_enable(RCU_GPIOB); + + /* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5); + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4); +#endif + return result; +} +INIT_BOARD_EXPORT(gd32_hw_spi_init); +#endif diff --git a/bsp/gd32107c-eval/drivers/drv_spi.h b/bsp/gd32107c-eval/drivers/drv_spi.h new file mode 100644 index 0000000000..6616fd88eb --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_spi.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + + +#endif /* __DRV_SPI_H__ */ diff --git a/bsp/gd32107c-eval/drivers/drv_spi_flash.c b/bsp/gd32107c-eval/drivers/drv_spi_flash.c new file mode 100644 index 0000000000..d013c73ad0 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_spi_flash.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ +#include +#include +#include +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +#define SPI_BUS_NAME "spi0" +#define SPI_DEVICE_NAME "spi01" +#define SPI_FLASH_DEVICE_NAME "gd25q" +#define GD25Q_SPI_CS_PIN 67 /* PE3，在 drv_gpio.c 文件 pin_index pins[]中查到 PE3 编号为 67 */ + +static int rt_hw_gd25q40_init(void) +{ + rt_err_t res; + static struct rt_spi_device spi_dev_gd25q; /* SPI设备对象 */ + static rt_base_t gd25q_cs_pin; /* SPI设备CS片选引脚 */ + + gd25q_cs_pin = GD25Q_SPI_CS_PIN; + + rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP); + + res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin); + if (res != RT_EOK) + { + rt_kprintf("rt_spi_bus_attach_device() run failed!\n"); + return res; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_gd25q40_init); + +static int rt_hw_spi_flash_with_sfud_init(void) +{ + if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_DEVICE_NAME, SPI_DEVICE_NAME)) + { + return RT_ERROR; + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); + +#ifdef RT_USING_DFS +#include + +int mnt_init(void) +{ + if (dfs_mount(SPI_FLASH_DEVICE_NAME, "/", "elm", 0, 0) == 0) + { + rt_kprintf("spi flash mount success !\n"); + } + else + { + rt_kprintf("spi flash mount failed!\n"); + } + + return 0; +} +MSH_CMD_EXPORT(mnt_init, mount spi flash to file system); +#endif diff --git a/bsp/gd32107c-eval/drivers/drv_usart.c b/bsp/gd32107c-eval/drivers/drv_usart.c new file mode 100644 index 0000000000..6dbe467ab8 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_usart.c @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ +#include +#include +#include +#include + +#ifdef RT_USING_SERIAL + +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) && \ + !defined(RT_USING_USART2) && !defined(RT_USING_UART3) && \ + !defined(RT_USING_UART4) +#error "Please define at least one UARTx" + +#endif + +#include + +/* GD32 uart driver */ +/* Todo: compress uart info */ +struct gd32_uart +{ + uint32_t uart_periph; + IRQn_Type irqn; + rcu_periph_enum per_clk; + rcu_periph_enum tx_gpio_clk; + rcu_periph_enum rx_gpio_clk; + uint32_t tx_port; + uint16_t tx_pin; + uint32_t rx_port; + uint16_t rx_pin; + + struct rt_serial_device * serial; + char *device_name; +}; + +static void uart_isr(struct rt_serial_device *serial); + +#if defined(RT_USING_USART0) +struct rt_serial_device serial0; + +void USART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial0); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_USART0 */ + +#if defined(RT_USING_USART1) +struct rt_serial_device serial1; + +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_UART1 */ + +#if defined(RT_USING_USART2) +struct rt_serial_device serial2; + +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART3) +struct rt_serial_device serial3; + +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial3); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_UART3 */ + +#if defined(RT_USING_UART4) +struct rt_serial_device serial4; + +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial4); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_USING_UART4 */ + +static const struct gd32_uart uarts[] = { + #ifdef RT_USING_USART0 + { + USART0, /* uart peripheral index */ + USART0_IRQn, /* uart iqrn */ + RCU_USART0, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOA, GPIO_PIN_9, /* tx port, tx pin */ + GPIOA, GPIO_PIN_10, /* rx port, rx pin */ + &serial0, + "uart0", + }, + #endif + + #ifdef RT_USING_USART1 + { + USART1, /* uart peripheral index */ + USART1_IRQn, /* uart iqrn */ + RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOA, GPIO_PIN_2, /* tx port, tx pin */ + GPIOA, GPIO_PIN_3, /* rx port, rx pin */ + &serial1, + "uart1", + }, + #endif + + #ifdef RT_USING_USART2 + { + USART2, /* uart peripheral index */ + USART2_IRQn, /* uart iqrn */ + RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOB, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ + GPIOB, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ + &serial2, + "uart2", + }, + #endif + + #ifdef RT_USING_UART3 + { + UART3, /* uart peripheral index */ + UART3_IRQn, /* uart iqrn */ + RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOC, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ + GPIOC, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ + &serial3, + "uart3", + }, + #endif + + #ifdef RT_USING_UART4 + { + UART4, /* uart peripheral index */ + UART4_IRQn, /* uart iqrn */ + RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOC, GPIO_PIN_12, /* tx port, tx alternate, tx pin */ + GPIOD, GPIO_PIN_2, /* rx port, rx alternate, rx pin */ + &serial4, + "uart4", + }, + #endif +}; + + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example: +* - Peripheral's clock enable +* - Peripheral's GPIO Configuration +* - NVIC configuration for UART interrupt request enable +* @param uart: UART handle pointer +* @retval None +*/ +void gd32_uart_gpio_init(struct gd32_uart *uart) +{ + /* enable USART clock */ + rcu_periph_clock_enable(uart->tx_gpio_clk); + rcu_periph_clock_enable(uart->rx_gpio_clk); + rcu_periph_clock_enable(uart->per_clk); + + /* connect port to USARTx_Tx */ + gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); + + /* connect port to USARTx_Rx */ + gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); + + NVIC_SetPriority(uart->irqn, 0); + NVIC_EnableIRQ(uart->irqn); +} + +static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct gd32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = (struct gd32_uart *)serial->parent.user_data; + + gd32_uart_gpio_init(uart); + + usart_baudrate_set(uart->uart_periph, cfg->baud_rate); + + switch (cfg->data_bits) + { + case DATA_BITS_9: + usart_word_length_set(uart->uart_periph, USART_WL_9BIT); + break; + + default: + usart_word_length_set(uart->uart_periph, USART_WL_8BIT); + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT); + break; + default: + usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT); + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + usart_parity_config(uart->uart_periph, USART_PM_ODD); + break; + case PARITY_EVEN: + usart_parity_config(uart->uart_periph, USART_PM_EVEN); + break; + default: + usart_parity_config(uart->uart_periph, USART_PM_NONE); + break; + } + + usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE); + usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE); + usart_enable(uart->uart_periph); + + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct gd32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct gd32_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irqn); + /* disable interrupt */ + usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); + + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irqn); + /* enable interrupt */ + usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); + break; + } + + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial, char ch) +{ + struct gd32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct gd32_uart *)serial->parent.user_data; + + usart_data_transmit(uart->uart_periph, ch); + while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); + + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct gd32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct gd32_uart *)serial->parent.user_data; + + ch = -1; + if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET) + ch = usart_data_receive(uart->uart_periph); + return ch; +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data; + + RT_ASSERT(uart != RT_NULL); + + /* UART in mode Receiver */ + if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && + (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + /* Clear RXNE interrupt flag */ + usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE); + } +} + +static const struct rt_uart_ops gd32_uart_ops = +{ + _uart_configure, + _uart_control, + _uart_putc, + _uart_getc +}; + +int gd32_hw_usart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + int i; + + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) + { + uarts[i].serial->ops = &gd32_uart_ops; + uarts[i].serial->config = config; + + /* register UART device */ + rt_hw_serial_register(uarts[i].serial, + uarts[i].device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + (void *)&uarts[i]); + } + + return 0; +} +INIT_BOARD_EXPORT(gd32_hw_usart_init); +#endif diff --git a/bsp/gd32107c-eval/drivers/drv_usart.h b/bsp/gd32107c-eval/drivers/drv_usart.h new file mode 100644 index 0000000000..f575ad3810 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/drv_usart.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 lianzhian first implementation. + */ + +#ifndef __USART_H__ +#define __USART_H__ + + +#endif diff --git a/bsp/gd32107c-eval/drivers/gd32f10x_libopt.h b/bsp/gd32107c-eval/drivers/gd32f10x_libopt.h new file mode 100644 index 0000000000..a4dd11b017 --- /dev/null +++ b/bsp/gd32107c-eval/drivers/gd32f10x_libopt.h @@ -0,0 +1,67 @@ +/*! + \file gd32f10x_libopt.h + \brief library optional for gd32f10x + \version 2014-12-26, V1.0.0, demo for GD32F10x + \version 2017-06-30, V2.0.0, demo for GD32F10x + \version 2018-07-31, V2.1.0, demo for GD32F10x +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F10X_LIBOPT_H +#define GD32F10X_LIBOPT_H + +#include "gd32f10x_rcu.h" +#include "gd32f10x_adc.h" +#include "gd32f10x_can.h" +#include "gd32f10x_crc.h" +#include "gd32f10x_dac.h" +#include "gd32f10x_dbg.h" +#include "gd32f10x_dma.h" +#include "gd32f10x_exti.h" +#include "gd32f10x_fmc.h" +#include "gd32f10x_fwdgt.h" +#include "gd32f10x_gpio.h" +#include "gd32f10x_i2c.h" +#include "gd32f10x_pmu.h" +#include "gd32f10x_bkp.h" +#include "gd32f10x_rtc.h" +#include "gd32f10x_sdio.h" +#include "gd32f10x_spi.h" +#include "gd32f10x_timer.h" +#include "gd32f10x_usart.h" +#include "gd32f10x_wwdgt.h" +#include "gd32f10x_misc.h" +#include "gd32f10x_exmc.h" +#ifdef GD32F10X_CL +#include "gd32f10x_enet.h" +#endif /* GD32F10X_CL */ + +#endif /* GD32F10X_LIBOPT_H */ diff --git a/bsp/gd32107c-eval/list/context_rvds.lst b/bsp/gd32107c-eval/list/context_rvds.lst new file mode 100644 index 0000000000..27d7ece457 --- /dev/null +++ b/bsp/gd32107c-eval/list/context_rvds.lst @@ -0,0 +1,515 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;/* + 2 00000000 ; * Copyright (c) 2006-2018, RT-Thread Development Team + 3 00000000 ; * + 4 00000000 ; * SPDX-License-Identifier: Apache-2.0 + 5 00000000 ; * + 6 00000000 ; * Change Logs: + 7 00000000 ; * Date Author Notes + 8 00000000 ; * 2009-01-17 Bernard first version + 9 00000000 ; * 2013-06-18 aozima add restore MSP feature. + + 10 00000000 ; * 2013-07-09 aozima enhancement hard fault e + xception handler. + 11 00000000 ; */ + 12 00000000 + 13 00000000 ;/** + 14 00000000 ; * @addtogroup CORTEX-M3 + 15 00000000 ; */ + 16 00000000 ;/*@{*/ + 17 00000000 + 18 00000000 E000ED08 + SCB_VTOR + EQU 0xE000ED08 ; Vector Table Offs + et Register + 19 00000000 E000ED04 + NVIC_INT_CTRL + EQU 0xE000ED04 ; interrupt control + state register + 20 00000000 E000ED20 + NVIC_SYSPRI2 + EQU 0xE000ED20 ; system priority r + egister (2) + 21 00000000 FFFF0000 + NVIC_PENDSV_PRI + EQU 0xFFFF0000 ; PendSV and SysTic + k priority value (l + owest) + 22 00000000 10000000 + NVIC_PENDSVSET + EQU 0x10000000 ; value to trigger + PendSV exception + 23 00000000 + 24 00000000 AREA |.text|, CODE, READONLY, ALIGN= +2 + 25 00000000 THUMB + 26 00000000 REQUIRE8 + 27 00000000 PRESERVE8 + 28 00000000 + 29 00000000 IMPORT rt_thread_switch_interrupt_flag + 30 00000000 IMPORT rt_interrupt_from_thread + 31 00000000 IMPORT rt_interrupt_to_thread + 32 00000000 + 33 00000000 ;/* + 34 00000000 ; * rt_base_t rt_hw_interrupt_disable(); + 35 00000000 ; */ + 36 00000000 rt_hw_interrupt_disable + PROC + 37 00000000 EXPORT rt_hw_interrupt_disable + 38 00000000 F3EF 8010 MRS r0, PRIMASK + 39 00000004 B672 CPSID I + + + +ARM Macro Assembler Page 2 + + + 40 00000006 4770 BX LR + 41 00000008 ENDP + 42 00000008 + 43 00000008 ;/* + 44 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level); + 45 00000008 ; */ + 46 00000008 rt_hw_interrupt_enable + PROC + 47 00000008 EXPORT rt_hw_interrupt_enable + 48 00000008 F380 8810 MSR PRIMASK, r0 + 49 0000000C 4770 BX LR + 50 0000000E ENDP + 51 0000000E + 52 0000000E ;/* + 53 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 + to); + 54 0000000E ; * r0 --> from + 55 0000000E ; * r1 --> to + 56 0000000E ; */ + 57 0000000E rt_hw_context_switch_interrupt + 58 0000000E EXPORT rt_hw_context_switch_interrupt + 59 0000000E rt_hw_context_switch + PROC + 60 0000000E EXPORT rt_hw_context_switch + 61 0000000E + 62 0000000E ; set rt_thread_switch_interrupt_flag to 1 + 63 0000000E 4A32 LDR r2, =rt_thread_switch_interrupt +_flag + 64 00000010 6813 LDR r3, [r2] + 65 00000012 2B01 CMP r3, #1 + 66 00000014 D004 BEQ _reswitch + 67 00000016 F04F 0301 MOV r3, #1 + 68 0000001A 6013 STR r3, [r2] + 69 0000001C + 70 0000001C 4A2F LDR r2, =rt_interrupt_from_thread ; + set rt_interrupt_f + rom_thread + 71 0000001E 6010 STR r0, [r2] + 72 00000020 + 73 00000020 _reswitch + 74 00000020 4A2F LDR r2, =rt_interrupt_to_thread ; s + et rt_interrupt_to_ + thread + 75 00000022 6011 STR r1, [r2] + 76 00000024 + 77 00000024 482F LDR r0, =NVIC_INT_CTRL ; trigger th + e PendSV exception + (causes context swi + tch) + 78 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET + 79 0000002A 6001 STR r1, [r0] + 80 0000002C 4770 BX LR + 81 0000002E ENDP + 82 0000002E + 83 0000002E ; r0 --> switch from thread stack + 84 0000002E ; r1 --> switch to thread stack + 85 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from + ] stack + 86 0000002E PendSV_Handler + + + +ARM Macro Assembler Page 3 + + + PROC + 87 0000002E EXPORT PendSV_Handler + 88 0000002E + 89 0000002E ; disable interrupt to protect context switch + 90 0000002E F3EF 8210 MRS r2, PRIMASK + 91 00000032 B672 CPSID I + 92 00000034 + 93 00000034 ; get rt_thread_switch_interrupt_flag + 94 00000034 4828 LDR r0, =rt_thread_switch_interrupt +_flag + 95 00000036 6801 LDR r1, [r0] + 96 00000038 B191 CBZ r1, pendsv_exit ; pendsv alread + y handled + 97 0000003A + 98 0000003A ; clear rt_thread_switch_interrupt_flag to 0 + 99 0000003A F04F 0100 MOV r1, #0x00 + 100 0000003E 6001 STR r1, [r0] + 101 00000040 + 102 00000040 4826 LDR r0, =rt_interrupt_from_thread + 103 00000042 6801 LDR r1, [r0] + 104 00000044 B129 CBZ r1, switch_to_thread ; skip reg + ister save at the f + irst time + 105 00000046 + 106 00000046 F3EF 8109 MRS r1, psp ; get from thread s + tack pointer + 107 0000004A E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11 + register + 108 0000004E 6800 LDR r0, [r0] + 109 00000050 6001 STR r1, [r0] ; update from threa + d stack pointer + 110 00000052 + 111 00000052 switch_to_thread + 112 00000052 4923 LDR r1, =rt_interrupt_to_thread + 113 00000054 6809 LDR r1, [r1] + 114 00000056 6809 LDR r1, [r1] ; load thread stack + pointer + 115 00000058 + 116 00000058 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11 + register + 117 0000005C F381 8809 MSR psp, r1 ; update stack poin + ter + 118 00000060 + 119 00000060 pendsv_exit + 120 00000060 ; restore interrupt + 121 00000060 F382 8810 MSR PRIMASK, r2 + 122 00000064 + 123 00000064 F04E 0E04 ORR lr, lr, #0x04 + 124 00000068 4770 BX lr + 125 0000006A ENDP + 126 0000006A + 127 0000006A ;/* + 128 0000006A ; * void rt_hw_context_switch_to(rt_uint32 to); + 129 0000006A ; * r0 --> to + 130 0000006A ; * this fucntion is used to perform the first thread sw + itch + 131 0000006A ; */ + 132 0000006A rt_hw_context_switch_to + PROC + + + +ARM Macro Assembler Page 4 + + + 133 0000006A EXPORT rt_hw_context_switch_to + 134 0000006A ; set to thread + 135 0000006A 491D LDR r1, =rt_interrupt_to_thread + 136 0000006C 6008 STR r0, [r1] + 137 0000006E + 138 0000006E ; set from thread to 0 + 139 0000006E 491B LDR r1, =rt_interrupt_from_thread + 140 00000070 F04F 0000 MOV r0, #0x0 + 141 00000074 6008 STR r0, [r1] + 142 00000076 + 143 00000076 ; set interrupt flag to 1 + 144 00000076 4918 LDR r1, =rt_thread_switch_interrupt +_flag + 145 00000078 F04F 0001 MOV r0, #1 + 146 0000007C 6008 STR r0, [r1] + 147 0000007E + 148 0000007E ; set the PendSV and SysTick exception priority + 149 0000007E 481A LDR r0, =NVIC_SYSPRI2 + 150 00000080 491A LDR r1, =NVIC_PENDSV_PRI + 151 00000082 F8D0 2000 LDR.W r2, [r0,#0x00] ; read + 152 00000086 EA41 0102 ORR r1,r1,r2 ; modify + 153 0000008A 6001 STR r1, [r0] ; write-back + 154 0000008C + 155 0000008C ; trigger the PendSV exception (causes context switch) + 156 0000008C 4815 LDR r0, =NVIC_INT_CTRL + 157 0000008E F04F 5180 LDR r1, =NVIC_PENDSVSET + 158 00000092 6001 STR r1, [r0] + 159 00000094 + 160 00000094 ; restore MSP + 161 00000094 4816 LDR r0, =SCB_VTOR + 162 00000096 6800 LDR r0, [r0] + 163 00000098 6800 LDR r0, [r0] + 164 0000009A F380 8808 MSR msp, r0 + 165 0000009E + 166 0000009E ; enable interrupts at processor level + 167 0000009E B661 CPSIE F + 168 000000A0 B662 CPSIE I + 169 000000A2 + 170 000000A2 ; never reach here! + 171 000000A2 ENDP + 172 000000A2 + 173 000000A2 ; compatible with old version + 174 000000A2 rt_hw_interrupt_thread_switch + PROC + 175 000000A2 EXPORT rt_hw_interrupt_thread_switch + 176 000000A2 4770 BX lr + 177 000000A4 ENDP + 178 000000A4 + 179 000000A4 IMPORT rt_hw_hard_fault_exception + 180 000000A4 EXPORT HardFault_Handler + 181 000000A4 HardFault_Handler + PROC + 182 000000A4 + 183 000000A4 ; get current context + 184 000000A4 F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] + ) + 185 000000A8 BF0C ITE EQ + 186 000000AA F3EF 8008 MRSEQ r0, msp ; [2]=0 ==> Z=1, ge + t fault context fro + + + +ARM Macro Assembler Page 5 + + + m handler. + 187 000000AE F3EF 8009 MRSNE r0, psp ; [2]=1 ==> Z=0, ge + t fault context fro + m thread. + 188 000000B2 + 189 000000B2 E920 0FF0 STMFD r0!, {r4 - r11} ; push r4 - r11 + register + 190 000000B6 F840 ED04 STMFD r0!, {lr} ; push exec_return + register + 191 000000BA + 192 000000BA F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] + ) + 193 000000BE BF0C ITE EQ + 194 000000C0 F380 8808 MSREQ msp, r0 ; [2]=0 ==> Z=1, up + date stack pointer + to MSP. + 195 000000C4 F380 8809 MSRNE psp, r0 ; [2]=1 ==> Z=0, up + date stack pointer + to PSP. + 196 000000C8 + 197 000000C8 B500 PUSH {lr} + 198 000000CA F7FF FFFE BL rt_hw_hard_fault_exception + 199 000000CE F85D EB04 POP {lr} + 200 000000D2 + 201 000000D2 F04E 0E04 ORR lr, lr, #0x04 + 202 000000D6 4770 BX lr + 203 000000D8 ENDP + 204 000000D8 + 205 000000D8 ALIGN 4 + 206 000000D8 + 207 000000D8 END + 00000000 + 00000000 + 00000000 + E000ED04 + E000ED20 + FFFF0000 + E000ED08 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=.\output\context_rvds.d -o.\output\context_rvds.o -IE:\code\rtt\rt +-thread\bsp\gd32107c-eval\RTE -ID:\Keil_v5\ARM\PACK\GigaDevice\GD32F10x_DFP\2.0 +.1\Device\Include -ID:\Keil_v5\ARM\CMSIS\Include --predefine="__MICROLIB SETA 1 +" --predefine="__UVISION_VERSION SETA 514" --predefine="GD32F10X_CL SETA 1" --p +redefine="USE_STDPERIPH_DRIVER SETA 1" --list=.\list\context_rvds.lst ..\..\lib +cpu\arm\cortex-m3\context_rvds.S + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 24 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + None +Comment: .text unused +HardFault_Handler 000000A4 + +Symbol: HardFault_Handler + Definitions + At line 181 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 180 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: HardFault_Handler used once +PendSV_Handler 0000002E + +Symbol: PendSV_Handler + Definitions + At line 86 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 87 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: PendSV_Handler used once +_reswitch 00000020 + +Symbol: _reswitch + Definitions + At line 73 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 66 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: _reswitch used once +pendsv_exit 00000060 + +Symbol: pendsv_exit + Definitions + At line 119 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 96 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: pendsv_exit used once +rt_hw_context_switch 0000000E + +Symbol: rt_hw_context_switch + Definitions + At line 59 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 60 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_context_switch used once +rt_hw_context_switch_interrupt 0000000E + +Symbol: rt_hw_context_switch_interrupt + Definitions + At line 57 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 58 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_context_switch_interrupt used once +rt_hw_context_switch_to 0000006A + +Symbol: rt_hw_context_switch_to + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 132 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 133 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_context_switch_to used once +rt_hw_interrupt_disable 00000000 + +Symbol: rt_hw_interrupt_disable + Definitions + At line 36 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 37 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_interrupt_disable used once +rt_hw_interrupt_enable 00000008 + +Symbol: rt_hw_interrupt_enable + Definitions + At line 46 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 47 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_interrupt_enable used once +rt_hw_interrupt_thread_switch 000000A2 + +Symbol: rt_hw_interrupt_thread_switch + Definitions + At line 174 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 175 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_interrupt_thread_switch used once +switch_to_thread 00000052 + +Symbol: switch_to_thread + Definitions + At line 111 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 104 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: switch_to_thread used once +12 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +NVIC_INT_CTRL E000ED04 + +Symbol: NVIC_INT_CTRL + Definitions + At line 19 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 77 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 156 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +NVIC_PENDSVSET 10000000 + +Symbol: NVIC_PENDSVSET + Definitions + At line 22 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 78 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 157 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +NVIC_PENDSV_PRI FFFF0000 + +Symbol: NVIC_PENDSV_PRI + Definitions + At line 21 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 150 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: NVIC_PENDSV_PRI used once +NVIC_SYSPRI2 E000ED20 + +Symbol: NVIC_SYSPRI2 + Definitions + At line 20 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 149 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: NVIC_SYSPRI2 used once +SCB_VTOR E000ED08 + +Symbol: SCB_VTOR + Definitions + At line 18 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 161 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: SCB_VTOR used once +5 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +rt_hw_hard_fault_exception 00000000 + +Symbol: rt_hw_hard_fault_exception + Definitions + At line 179 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 198 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S +Comment: rt_hw_hard_fault_exception used once +rt_interrupt_from_thread 00000000 + +Symbol: rt_interrupt_from_thread + Definitions + At line 30 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 70 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 102 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 139 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +rt_interrupt_to_thread 00000000 + +Symbol: rt_interrupt_to_thread + Definitions + At line 31 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 74 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 112 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 135 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +rt_thread_switch_interrupt_flag 00000000 + +Symbol: rt_thread_switch_interrupt_flag + Definitions + At line 29 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + Uses + At line 63 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 94 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + At line 144 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S + +4 symbols +357 symbols in table diff --git a/bsp/gd32107c-eval/list/startup_gd32f10x_cl.lst b/bsp/gd32107c-eval/list/startup_gd32f10x_cl.lst new file mode 100644 index 0000000000..ca9e6f53ad --- /dev/null +++ b/bsp/gd32107c-eval/list/startup_gd32f10x_cl.lst @@ -0,0 +1,1850 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;/*! + 2 00000000 ; \file startup_gd32f10x_cl.s + 3 00000000 ; \brief start up file + 4 00000000 ; + 5 00000000 ; \version 2014-12-26, V1.0.0, firmware for GD32F10x + 6 00000000 ; \version 2017-06-20, V2.0.0, firmware for GD32F10x + 7 00000000 ; \version 2018-07-31, V2.1.0, firmware for GD32F10x + 8 00000000 ;*/ + 9 00000000 ; + 10 00000000 ;/* + 11 00000000 ; Copyright (c) 2018, GigaDevice Semiconductor Inc. + 12 00000000 ; + 13 00000000 ; All rights reserved. + 14 00000000 ; + 15 00000000 ; Redistribution and use in source and binary forms, + with or without modification, + 16 00000000 ;are permitted provided that the following conditions ar + e met: + 17 00000000 ; + 18 00000000 ; 1. Redistributions of source code must retain the a + bove copyright notice, this + 19 00000000 ; list of conditions and the following disclaimer. + + 20 00000000 ; 2. Redistributions in binary form must reproduce th + e above copyright notice, + 21 00000000 ; this list of conditions and the following discla + imer in the documentation + 22 00000000 ; and/or other materials provided with the distrib + ution. + 23 00000000 ; 3. Neither the name of the copyright holder nor the + names of its contributors + 24 00000000 ; may be used to endorse or promote products deriv + ed from this software without + 25 00000000 ; specific prior written permission. + 26 00000000 ; + 27 00000000 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS + AND CONTRIBUTORS "AS IS" + 28 00000000 ;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT N + OT LIMITED TO, THE IMPLIED + 29 00000000 ;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU + LAR PURPOSE ARE DISCLAIMED. + 30 00000000 ;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS + BE LIABLE FOR ANY DIRECT, + 31 00000000 ;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENT + IAL DAMAGES (INCLUDING, BUT + 32 00000000 ;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV + ICES; LOSS OF USE, DATA, OR + 33 00000000 ;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND O + N ANY THEORY OF LIABILITY, + 34 00000000 ;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDI + NG NEGLIGENCE OR OTHERWISE) + 35 00000000 ;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVE + N IF ADVISED OF THE POSSIBILITY + 36 00000000 ;OF SUCH DAMAGE. + 37 00000000 ;*/ + 38 00000000 + 39 00000000 ; Stack Configuration + 40 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 41 00000000 ; + + + +ARM Macro Assembler Page 2 + + + 42 00000000 + 43 00000000 00002000 + Stack_Size + EQU 0x00002000 + 44 00000000 + 45 00000000 AREA STACK, NOINIT, READWRITE, ALIGN + = 3 + 46 00000000 Stack_Mem + SPACE Stack_Size + 47 00002000 __initial_sp + 48 00002000 + 49 00002000 + 50 00002000 ; Heap Configuration + 51 00002000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 52 00002000 ; + 53 00002000 + 54 00002000 00002000 + Heap_Size + EQU 0x00002000 + 55 00002000 + 56 00002000 AREA HEAP, NOINIT, READWRITE, ALIGN += 3 + 57 00000000 __heap_base + 58 00000000 Heap_Mem + SPACE Heap_Size + 59 00002000 __heap_limit + 60 00002000 + 61 00002000 + 62 00002000 PRESERVE8 + 63 00002000 THUMB + 64 00002000 + 65 00002000 ; /* reset Vector Mapped to at Address + 0 */ + 66 00002000 AREA RESET, DATA, READONLY + 67 00000000 EXPORT __Vectors + 68 00000000 EXPORT __Vectors_End + 69 00000000 EXPORT __Vectors_Size + 70 00000000 + 71 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 72 00000004 00000000 DCD Reset_Handler ; Reset Handler + 73 00000008 00000000 DCD NMI_Handler ; NMI Handler + 74 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 75 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 76 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 77 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 78 0000001C 00000000 DCD 0 ; Reserved + 79 00000020 00000000 DCD 0 ; Reserved + 80 00000024 00000000 DCD 0 ; Reserved + 81 00000028 00000000 DCD 0 ; Reserved + 82 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 83 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + + + +ARM Macro Assembler Page 3 + + + r Handler + 84 00000034 00000000 DCD 0 ; Reserved + 85 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 86 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 87 00000040 + 88 00000040 ; /* external interrupts handler */ + 89 00000040 00000000 DCD WWDGT_IRQHandler ; 16:Window Wa + tchdog Timer + 90 00000044 00000000 DCD LVD_IRQHandler ; 17:LVD through + EXTI Line detect + 91 00000048 00000000 DCD TAMPER_IRQHandler ; 18:Tamper I + nterrupt + 92 0000004C 00000000 DCD RTC_IRQHandler ; 19:RTC through + EXTI Line + 93 00000050 00000000 DCD FMC_IRQHandler ; 20:FMC + 94 00000054 00000000 DCD RCU_IRQHandler ; 21:RCU + 95 00000058 00000000 DCD EXTI0_IRQHandler + ; 22:EXTI Line 0 + 96 0000005C 00000000 DCD EXTI1_IRQHandler + ; 23:EXTI Line 1 + 97 00000060 00000000 DCD EXTI2_IRQHandler + ; 24:EXTI Line 2 + 98 00000064 00000000 DCD EXTI3_IRQHandler + ; 25:EXTI Line 3 + 99 00000068 00000000 DCD EXTI4_IRQHandler + ; 26:EXTI Line 4 + 100 0000006C 00000000 DCD DMA0_Channel0_IRQHandler + ; 27:DMA0 Channel 0 + + 101 00000070 00000000 DCD DMA0_Channel1_IRQHandler + ; 28:DMA0 Channel 1 + + 102 00000074 00000000 DCD DMA0_Channel2_IRQHandler + ; 29:DMA0 Channel 2 + + 103 00000078 00000000 DCD DMA0_Channel3_IRQHandler + ; 30:DMA0 Channel 3 + + 104 0000007C 00000000 DCD DMA0_Channel4_IRQHandler + ; 31:DMA0 Channel 4 + + 105 00000080 00000000 DCD DMA0_Channel5_IRQHandler ; 32:D + MA0 Channel 5 + 106 00000084 00000000 DCD DMA0_Channel6_IRQHandler + ; 33:DMA0 Channel 6 + + 107 00000088 00000000 DCD ADC0_1_IRQHandler + ; 34:ADC0 and ADC1 + 108 0000008C 00000000 DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + + 109 00000090 00000000 DCD CAN0_RX0_IRQHandler + ; 36:CAN0 RX0 + 110 00000094 00000000 DCD CAN0_RX1_IRQHandler + ; 37:CAN0 RX1 + 111 00000098 00000000 DCD CAN0_EWMC_IRQHandler + ; 38:CAN0 EWMC + 112 0000009C 00000000 DCD EXTI5_9_IRQHandler ; 39:EXTI Li + + + +ARM Macro Assembler Page 4 + + + ne 5 to EXTI Line 9 + + 113 000000A0 00000000 DCD TIMER0_BRK_IRQHandler + ; 40:TIMER0 Break + 114 000000A4 00000000 DCD TIMER0_UP_IRQHandler + ; 41:TIMER0 Update + 115 000000A8 00000000 DCD TIMER0_TRG_CMT_IRQHandler ; 42: + TIMER0 Trigger and + Commutation + 116 000000AC 00000000 DCD TIMER0_Channel_IRQHandler ; 43: + TIMER0 Channel Capt + ure Compare + 117 000000B0 00000000 DCD TIMER1_IRQHandler ; 44:TIMER1 + 118 000000B4 00000000 DCD TIMER2_IRQHandler ; 45:TIMER2 + 119 000000B8 00000000 DCD TIMER3_IRQHandler ; 46:TIMER3 + 120 000000BC 00000000 DCD I2C0_EV_IRQHandler + ; 47:I2C0 Event + 121 000000C0 00000000 DCD I2C0_ER_IRQHandler + ; 48:I2C0 Error + 122 000000C4 00000000 DCD I2C1_EV_IRQHandler + ; 49:I2C1 Event + 123 000000C8 00000000 DCD I2C1_ER_IRQHandler + ; 50:I2C1 Error + 124 000000CC 00000000 DCD SPI0_IRQHandler ; 51:SPI0 + 125 000000D0 00000000 DCD SPI1_IRQHandler ; 52:SPI1 + 126 000000D4 00000000 DCD USART0_IRQHandler ; 53:USART0 + 127 000000D8 00000000 DCD USART1_IRQHandler ; 54:USART1 + 128 000000DC 00000000 DCD USART2_IRQHandler ; 55:USART2 + 129 000000E0 00000000 DCD EXTI10_15_IRQHandler ; 56:EXTI + Line 10 to EXTI Lin + e 15 + 130 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; 57:RTC A + larm through EXTI L + ine + 131 000000E8 00000000 DCD USBFS_WKUP_IRQHandler ; 58:USBF + S WakeUp from suspe + nd through EXTI Lin + e + 132 000000EC 00000000 DCD TIMER7_BRK_IRQHandler ; 59:TIME + R7 Break Interrupt + 133 000000F0 00000000 DCD TIMER7_UP_IRQHandler ; 60:TIMER + 7 Update Interrupt + 134 000000F4 00000000 DCD TIMER7_TRG_CMT_IRQHandler + ; 61:TIMER7 Trigger + + 135 000000F8 00000000 DCD TIMER7_Channel_IRQHandler ; 62: + TIMER7 Channel Capt + ure Compare + 136 000000FC 00000000 DCD 0 ; Reserved + 137 00000100 00000000 DCD EXMC_IRQHandler ; 64:EXMC + 138 00000104 00000000 DCD 0 ; Reserved + 139 00000108 00000000 DCD TIMER4_IRQHandler ; 66:TIMER4 + 140 0000010C 00000000 DCD SPI2_IRQHandler ; 67:SPI2 + 141 00000110 00000000 DCD UART3_IRQHandler ; 68:UART3 + 142 00000114 00000000 DCD UART4_IRQHandler ; 69:UART4 + 143 00000118 00000000 DCD TIMER5_IRQHandler ; 70:TIMER5 + 144 0000011C 00000000 DCD TIMER6_IRQHandler ; 71:TIMER6 + 145 00000120 00000000 DCD DMA1_Channel0_IRQHandler + ; 72:DMA1 Channel0 + + + +ARM Macro Assembler Page 5 + + + 146 00000124 00000000 DCD DMA1_Channel1_IRQHandler + ; 73:DMA1 Channel1 + 147 00000128 00000000 DCD DMA1_Channel2_IRQHandler + ; 74:DMA1 Channel2 + 148 0000012C 00000000 DCD DMA1_Channel3_IRQHandler + ; 75:DMA1 Channel3 + 149 00000130 00000000 DCD DMA1_Channel4_IRQHandler + ; 76:DMA1 Channel4 + 150 00000134 00000000 DCD ENET_IRQHandler ; 77:Ethernet + 151 00000138 00000000 DCD ENET_WKUP_IRQHandler ; 78:Ether + net Wakeup through + EXTI line + 152 0000013C 00000000 DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + + 153 00000140 00000000 DCD CAN1_RX0_IRQHandler + ; 80:CAN1 RX0 + 154 00000144 00000000 DCD CAN1_RX1_IRQHandler + ; 81:CAN1 RX1 + 155 00000148 00000000 DCD CAN1_EWMC_IRQHandler + ; 82:CAN1 EWMC + 156 0000014C 00000000 DCD USBFS_IRQHandler ; 83:USBFS + 157 00000150 + 158 00000150 __Vectors_End + 159 00000150 + 160 00000150 00000150 + __Vectors_Size + EQU __Vectors_End - __Vectors + 161 00000150 + 162 00000150 AREA |.text|, CODE, READONLY + 163 00000000 + 164 00000000 ;/* reset Handler */ + 165 00000000 Reset_Handler + PROC + 166 00000000 EXPORT Reset_Handler + [WEAK] + 167 00000000 IMPORT __main + 168 00000000 IMPORT SystemInit + 169 00000000 4806 LDR R0, =SystemInit + 170 00000002 4780 BLX R0 + 171 00000004 4806 LDR R0, =__main + 172 00000006 4700 BX R0 + 173 00000008 ENDP + 174 00000008 + 175 00000008 ;/* dummy Exception Handlers */ + 176 00000008 NMI_Handler + PROC + 177 00000008 EXPORT NMI_Handler + [WEAK] + 178 00000008 E7FE B . + 179 0000000A ENDP + 180 0000000A + 181 0000000A HardFault_Handler + PROC + 182 0000000A EXPORT HardFault_Handler + [WEAK] + 183 0000000A E7FE B . + 184 0000000C ENDP + 185 0000000C + 186 0000000C MemManage_Handler + + + +ARM Macro Assembler Page 6 + + + PROC + 187 0000000C EXPORT MemManage_Handler + [WEAK] + 188 0000000C E7FE B . + 189 0000000E ENDP + 190 0000000E + 191 0000000E BusFault_Handler + PROC + 192 0000000E EXPORT BusFault_Handler + [WEAK] + 193 0000000E E7FE B . + 194 00000010 ENDP + 195 00000010 + 196 00000010 UsageFault_Handler + PROC + 197 00000010 EXPORT UsageFault_Handler + [WEAK] + 198 00000010 E7FE B . + 199 00000012 ENDP + 200 00000012 + 201 00000012 SVC_Handler + PROC + 202 00000012 EXPORT SVC_Handler + [WEAK] + 203 00000012 E7FE B . + 204 00000014 ENDP + 205 00000014 + 206 00000014 DebugMon_Handler + PROC + 207 00000014 EXPORT DebugMon_Handler + [WEAK] + 208 00000014 E7FE B . + 209 00000016 ENDP + 210 00000016 + 211 00000016 PendSV_Handler + PROC + 212 00000016 EXPORT PendSV_Handler + [WEAK] + 213 00000016 E7FE B . + 214 00000018 ENDP + 215 00000018 + 216 00000018 SysTick_Handler + PROC + 217 00000018 EXPORT SysTick_Handler + [WEAK] + 218 00000018 E7FE B . + 219 0000001A ENDP + 220 0000001A + 221 0000001A Default_Handler + PROC + 222 0000001A ; /* external interrupts handler */ + + 223 0000001A EXPORT WWDGT_IRQHandler + [WEAK] + 224 0000001A EXPORT LVD_IRQHandler + [WEAK] + 225 0000001A EXPORT TAMPER_IRQHandler + [WEAK] + 226 0000001A EXPORT RTC_IRQHandler + + + +ARM Macro Assembler Page 7 + + + [WEAK] + 227 0000001A EXPORT FMC_IRQHandler + [WEAK] + 228 0000001A EXPORT RCU_IRQHandler + [WEAK] + 229 0000001A EXPORT EXTI0_IRQHandler + [WEAK] + 230 0000001A EXPORT EXTI1_IRQHandler + [WEAK] + 231 0000001A EXPORT EXTI2_IRQHandler + [WEAK] + 232 0000001A EXPORT EXTI3_IRQHandler + [WEAK] + 233 0000001A EXPORT EXTI4_IRQHandler + [WEAK] + 234 0000001A EXPORT DMA0_Channel0_IRQHandler + [WEAK] + 235 0000001A EXPORT DMA0_Channel1_IRQHandler + [WEAK] + 236 0000001A EXPORT DMA0_Channel2_IRQHandler + [WEAK] + 237 0000001A EXPORT DMA0_Channel3_IRQHandler + [WEAK] + 238 0000001A EXPORT DMA0_Channel4_IRQHandler + [WEAK] + 239 0000001A EXPORT DMA0_Channel5_IRQHandler + [WEAK] + 240 0000001A EXPORT DMA0_Channel6_IRQHandler + [WEAK] + 241 0000001A EXPORT ADC0_1_IRQHandler + [WEAK] + 242 0000001A EXPORT CAN0_TX_IRQHandler + [WEAK] + 243 0000001A EXPORT CAN0_RX0_IRQHandler + [WEAK] + 244 0000001A EXPORT CAN0_RX1_IRQHandler + [WEAK] + 245 0000001A EXPORT CAN0_EWMC_IRQHandler + [WEAK] + 246 0000001A EXPORT EXTI5_9_IRQHandler + [WEAK] + 247 0000001A EXPORT TIMER0_BRK_IRQHandler + [WEAK] + 248 0000001A EXPORT TIMER0_UP_IRQHandler + [WEAK] + 249 0000001A EXPORT TIMER0_TRG_CMT_IRQHandler + [WEAK] + 250 0000001A EXPORT TIMER0_Channel_IRQHandler + [WEAK] + 251 0000001A EXPORT TIMER1_IRQHandler + [WEAK] + 252 0000001A EXPORT TIMER2_IRQHandler + [WEAK] + 253 0000001A EXPORT TIMER3_IRQHandler + [WEAK] + 254 0000001A EXPORT I2C0_EV_IRQHandler + [WEAK] + 255 0000001A EXPORT I2C0_ER_IRQHandler + [WEAK] + + + +ARM Macro Assembler Page 8 + + + 256 0000001A EXPORT I2C1_EV_IRQHandler + [WEAK] + 257 0000001A EXPORT I2C1_ER_IRQHandler + [WEAK] + 258 0000001A EXPORT SPI0_IRQHandler + [WEAK] + 259 0000001A EXPORT SPI1_IRQHandler + [WEAK] + 260 0000001A EXPORT USART0_IRQHandler + [WEAK] + 261 0000001A EXPORT USART1_IRQHandler + [WEAK] + 262 0000001A EXPORT USART2_IRQHandler + [WEAK] + 263 0000001A EXPORT EXTI10_15_IRQHandler + [WEAK] + 264 0000001A EXPORT RTC_Alarm_IRQHandler + [WEAK] + 265 0000001A EXPORT USBFS_WKUP_IRQHandler + [WEAK] + 266 0000001A EXPORT TIMER7_BRK_IRQHandler + [WEAK] + 267 0000001A EXPORT TIMER7_UP_IRQHandler + [WEAK] + 268 0000001A EXPORT TIMER7_TRG_CMT_IRQHandler + [WEAK] + 269 0000001A EXPORT TIMER7_Channel_IRQHandler + [WEAK] + 270 0000001A EXPORT EXMC_IRQHandler + [WEAK] + 271 0000001A EXPORT TIMER4_IRQHandler + [WEAK] + 272 0000001A EXPORT SPI2_IRQHandler + [WEAK] + 273 0000001A EXPORT UART3_IRQHandler + [WEAK] + 274 0000001A EXPORT UART4_IRQHandler + [WEAK] + 275 0000001A EXPORT TIMER5_IRQHandler + [WEAK] + 276 0000001A EXPORT TIMER6_IRQHandler + [WEAK] + 277 0000001A EXPORT DMA1_Channel0_IRQHandler + [WEAK] + 278 0000001A EXPORT DMA1_Channel1_IRQHandler + [WEAK] + 279 0000001A EXPORT DMA1_Channel2_IRQHandler + [WEAK] + 280 0000001A EXPORT DMA1_Channel3_IRQHandler + [WEAK] + 281 0000001A EXPORT DMA1_Channel4_IRQHandler + [WEAK] + 282 0000001A EXPORT ENET_IRQHandler + [WEAK] + 283 0000001A EXPORT ENET_WKUP_IRQHandler + [WEAK] + 284 0000001A EXPORT CAN1_TX_IRQHandler + [WEAK] + 285 0000001A EXPORT CAN1_RX0_IRQHandler + + + +ARM Macro Assembler Page 9 + + + [WEAK] + 286 0000001A EXPORT CAN1_RX1_IRQHandler + [WEAK] + 287 0000001A EXPORT CAN1_EWMC_IRQHandler + [WEAK] + 288 0000001A EXPORT USBFS_IRQHandler + [WEAK] + 289 0000001A + 290 0000001A + 291 0000001A ;/* external interrupts handler */ + 292 0000001A WWDGT_IRQHandler + 293 0000001A LVD_IRQHandler + 294 0000001A TAMPER_IRQHandler + 295 0000001A RTC_IRQHandler + 296 0000001A FMC_IRQHandler + 297 0000001A RCU_IRQHandler + 298 0000001A EXTI0_IRQHandler + 299 0000001A EXTI1_IRQHandler + 300 0000001A EXTI2_IRQHandler + 301 0000001A EXTI3_IRQHandler + 302 0000001A EXTI4_IRQHandler + 303 0000001A DMA0_Channel0_IRQHandler + 304 0000001A DMA0_Channel1_IRQHandler + 305 0000001A DMA0_Channel2_IRQHandler + 306 0000001A DMA0_Channel3_IRQHandler + 307 0000001A DMA0_Channel4_IRQHandler + 308 0000001A DMA0_Channel5_IRQHandler + 309 0000001A DMA0_Channel6_IRQHandler + 310 0000001A ADC0_1_IRQHandler + 311 0000001A CAN0_TX_IRQHandler + 312 0000001A CAN0_RX0_IRQHandler + 313 0000001A CAN0_RX1_IRQHandler + 314 0000001A CAN0_EWMC_IRQHandler + 315 0000001A EXTI5_9_IRQHandler + 316 0000001A TIMER0_BRK_IRQHandler + 317 0000001A TIMER0_UP_IRQHandler + 318 0000001A TIMER0_TRG_CMT_IRQHandler + 319 0000001A TIMER0_Channel_IRQHandler + 320 0000001A TIMER1_IRQHandler + 321 0000001A TIMER2_IRQHandler + 322 0000001A TIMER3_IRQHandler + 323 0000001A I2C0_EV_IRQHandler + 324 0000001A I2C0_ER_IRQHandler + 325 0000001A I2C1_EV_IRQHandler + 326 0000001A I2C1_ER_IRQHandler + 327 0000001A SPI0_IRQHandler + 328 0000001A SPI1_IRQHandler + 329 0000001A USART0_IRQHandler + 330 0000001A USART1_IRQHandler + 331 0000001A USART2_IRQHandler + 332 0000001A EXTI10_15_IRQHandler + 333 0000001A RTC_Alarm_IRQHandler + 334 0000001A USBFS_WKUP_IRQHandler + 335 0000001A TIMER7_BRK_IRQHandler + 336 0000001A TIMER7_UP_IRQHandler + 337 0000001A TIMER7_TRG_CMT_IRQHandler + 338 0000001A TIMER7_Channel_IRQHandler + 339 0000001A EXMC_IRQHandler + 340 0000001A TIMER4_IRQHandler + + + +ARM Macro Assembler Page 10 + + + 341 0000001A SPI2_IRQHandler + 342 0000001A UART3_IRQHandler + 343 0000001A UART4_IRQHandler + 344 0000001A TIMER5_IRQHandler + 345 0000001A TIMER6_IRQHandler + 346 0000001A DMA1_Channel0_IRQHandler + 347 0000001A DMA1_Channel1_IRQHandler + 348 0000001A DMA1_Channel2_IRQHandler + 349 0000001A DMA1_Channel3_IRQHandler + 350 0000001A DMA1_Channel4_IRQHandler + 351 0000001A ENET_IRQHandler + 352 0000001A ENET_WKUP_IRQHandler + 353 0000001A CAN1_TX_IRQHandler + 354 0000001A CAN1_RX0_IRQHandler + 355 0000001A CAN1_RX1_IRQHandler + 356 0000001A CAN1_EWMC_IRQHandler + 357 0000001A USBFS_IRQHandler + 358 0000001A + 359 0000001A + 360 0000001A E7FE B . + 361 0000001C ENDP + 362 0000001C + 363 0000001C ALIGN + 364 0000001C + 365 0000001C ; user Initial Stack & Heap + 366 0000001C + 367 0000001C IF :DEF:__MICROLIB + 368 0000001C + 369 0000001C EXPORT __initial_sp + 370 0000001C EXPORT __heap_base + 371 0000001C EXPORT __heap_limit + 372 0000001C + 373 0000001C ELSE + 388 ENDIF + 389 0000001C + 390 0000001C END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=.\output\startup_gd32f10x_cl.d -o.\output\startup_gd32f10x_cl.o -I +E:\code\rtt\rt-thread\bsp\gd32107c-eval\RTE -ID:\Keil_v5\ARM\PACK\GigaDevice\GD +32F10x_DFP\2.0.1\Device\Include -ID:\Keil_v5\ARM\CMSIS\Include --predefine="__M +ICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 514" --predefine="GD32F10X_ +CL SETA 1" --predefine="USE_STDPERIPH_DRIVER SETA 1" --list=.\list\startup_gd32 +f10x_cl.lst Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 45 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 46 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00002000 + +Symbol: __initial_sp + Definitions + At line 47 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 71 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 369 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 56 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 58 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 57 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 370 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s +Comment: __heap_base used once +__heap_limit 00002000 + +Symbol: __heap_limit + Definitions + At line 59 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 371 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 66 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 71 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 67 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +__Vectors_End 00000150 + +Symbol: __Vectors_End + Definitions + At line 158 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 68 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 162 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + None +Comment: .text unused +ADC0_1_IRQHandler 0000001A + +Symbol: ADC0_1_IRQHandler + Definitions + At line 310 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 107 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 241 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 191 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 76 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 192 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN0_EWMC_IRQHandler 0000001A + +Symbol: CAN0_EWMC_IRQHandler + Definitions + At line 314 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 111 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 245 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN0_RX0_IRQHandler 0000001A + +Symbol: CAN0_RX0_IRQHandler + Definitions + At line 312 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 109 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 243 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN0_RX1_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + +Symbol: CAN0_RX1_IRQHandler + Definitions + At line 313 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 110 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 244 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN0_TX_IRQHandler 0000001A + +Symbol: CAN0_TX_IRQHandler + Definitions + At line 311 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 108 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 242 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN1_EWMC_IRQHandler 0000001A + +Symbol: CAN1_EWMC_IRQHandler + Definitions + At line 356 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 155 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 287 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN1_RX0_IRQHandler 0000001A + +Symbol: CAN1_RX0_IRQHandler + Definitions + At line 354 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 153 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 285 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 355 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 154 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 286 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +CAN1_TX_IRQHandler 0000001A + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: CAN1_TX_IRQHandler + Definitions + At line 353 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 152 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 284 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel0_IRQHandler 0000001A + +Symbol: DMA0_Channel0_IRQHandler + Definitions + At line 303 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 100 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 234 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel1_IRQHandler 0000001A + +Symbol: DMA0_Channel1_IRQHandler + Definitions + At line 304 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 101 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 235 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel2_IRQHandler 0000001A + +Symbol: DMA0_Channel2_IRQHandler + Definitions + At line 305 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 102 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 236 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel3_IRQHandler 0000001A + +Symbol: DMA0_Channel3_IRQHandler + Definitions + At line 306 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 103 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 237 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + +DMA0_Channel4_IRQHandler 0000001A + +Symbol: DMA0_Channel4_IRQHandler + Definitions + At line 307 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 104 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 238 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel5_IRQHandler 0000001A + +Symbol: DMA0_Channel5_IRQHandler + Definitions + At line 308 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 105 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 239 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA0_Channel6_IRQHandler 0000001A + +Symbol: DMA0_Channel6_IRQHandler + Definitions + At line 309 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 106 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 240 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA1_Channel0_IRQHandler 0000001A + +Symbol: DMA1_Channel0_IRQHandler + Definitions + At line 346 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 145 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 277 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA1_Channel1_IRQHandler 0000001A + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 347 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 146 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 278 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + +DMA1_Channel2_IRQHandler 0000001A + +Symbol: DMA1_Channel2_IRQHandler + Definitions + At line 348 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 147 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 279 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA1_Channel3_IRQHandler 0000001A + +Symbol: DMA1_Channel3_IRQHandler + Definitions + At line 349 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 148 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 280 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DMA1_Channel4_IRQHandler 0000001A + +Symbol: DMA1_Channel4_IRQHandler + Definitions + At line 350 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 149 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 281 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 206 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 83 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 207 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 221 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + None +Comment: Default_Handler unused +ENET_IRQHandler 0000001A + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: ENET_IRQHandler + Definitions + At line 351 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 150 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 282 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +ENET_WKUP_IRQHandler 0000001A + +Symbol: ENET_WKUP_IRQHandler + Definitions + At line 352 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 151 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 283 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXMC_IRQHandler 0000001A + +Symbol: EXMC_IRQHandler + Definitions + At line 339 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 137 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 270 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 298 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 95 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 229 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI10_15_IRQHandler 0000001A + +Symbol: EXTI10_15_IRQHandler + Definitions + At line 332 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 129 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 263 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 299 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 96 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 230 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 300 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 97 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 231 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 301 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 98 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 232 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 302 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 99 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 233 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +EXTI5_9_IRQHandler 0000001A + +Symbol: EXTI5_9_IRQHandler + Definitions + At line 315 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 112 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 246 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +FMC_IRQHandler 0000001A + +Symbol: FMC_IRQHandler + Definitions + At line 296 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 93 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 227 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 181 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 74 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 182 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +I2C0_ER_IRQHandler 0000001A + +Symbol: I2C0_ER_IRQHandler + Definitions + At line 324 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 121 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 255 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +I2C0_EV_IRQHandler 0000001A + +Symbol: I2C0_EV_IRQHandler + Definitions + At line 323 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 120 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 254 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 326 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 123 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 257 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + +0x_cl.s + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 325 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 122 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 256 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +LVD_IRQHandler 0000001A + +Symbol: LVD_IRQHandler + Definitions + At line 293 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 90 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 224 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 186 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 75 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 187 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 176 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 73 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 177 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 211 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 85 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + + At line 212 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +RCU_IRQHandler 0000001A + +Symbol: RCU_IRQHandler + Definitions + At line 297 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 94 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 228 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +RTC_Alarm_IRQHandler 0000001A + +Symbol: RTC_Alarm_IRQHandler + Definitions + At line 333 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 130 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 264 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 295 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 92 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 226 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 165 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 72 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 166 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SPI0_IRQHandler 0000001A + +Symbol: SPI0_IRQHandler + Definitions + At line 327 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 124 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + +0x_cl.s + At line 258 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 328 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 125 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 259 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 341 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 140 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 272 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 201 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 82 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 202 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 216 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 86 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 217 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TAMPER_IRQHandler 0000001A + +Symbol: TAMPER_IRQHandler + Definitions + At line 294 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + At line 91 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 225 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER0_BRK_IRQHandler 0000001A + +Symbol: TIMER0_BRK_IRQHandler + Definitions + At line 316 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 113 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 247 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER0_Channel_IRQHandler 0000001A + +Symbol: TIMER0_Channel_IRQHandler + Definitions + At line 319 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 116 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 250 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER0_TRG_CMT_IRQHandler 0000001A + +Symbol: TIMER0_TRG_CMT_IRQHandler + Definitions + At line 318 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 115 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 249 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER0_UP_IRQHandler 0000001A + +Symbol: TIMER0_UP_IRQHandler + Definitions + At line 317 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 114 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 248 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER1_IRQHandler 0000001A + +Symbol: TIMER1_IRQHandler + Definitions + At line 320 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + + + +ARM Macro Assembler Page 13 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 117 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 251 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER2_IRQHandler 0000001A + +Symbol: TIMER2_IRQHandler + Definitions + At line 321 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 118 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 252 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER3_IRQHandler 0000001A + +Symbol: TIMER3_IRQHandler + Definitions + At line 322 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 119 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 253 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER4_IRQHandler 0000001A + +Symbol: TIMER4_IRQHandler + Definitions + At line 340 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 139 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 271 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER5_IRQHandler 0000001A + +Symbol: TIMER5_IRQHandler + Definitions + At line 344 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 143 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 275 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER6_IRQHandler 0000001A + +Symbol: TIMER6_IRQHandler + Definitions + At line 345 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 + + + +ARM Macro Assembler Page 14 Alphabetic symbol ordering +Relocatable symbols + +0x_cl.s + Uses + At line 144 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 276 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER7_BRK_IRQHandler 0000001A + +Symbol: TIMER7_BRK_IRQHandler + Definitions + At line 335 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 132 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 266 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER7_Channel_IRQHandler 0000001A + +Symbol: TIMER7_Channel_IRQHandler + Definitions + At line 338 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 135 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 269 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER7_TRG_CMT_IRQHandler 0000001A + +Symbol: TIMER7_TRG_CMT_IRQHandler + Definitions + At line 337 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 134 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 268 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +TIMER7_UP_IRQHandler 0000001A + +Symbol: TIMER7_UP_IRQHandler + Definitions + At line 336 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 133 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 267 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +UART3_IRQHandler 0000001A + +Symbol: UART3_IRQHandler + Definitions + + + +ARM Macro Assembler Page 15 Alphabetic symbol ordering +Relocatable symbols + + At line 342 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 141 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 273 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +UART4_IRQHandler 0000001A + +Symbol: UART4_IRQHandler + Definitions + At line 343 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 142 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 274 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USART0_IRQHandler 0000001A + +Symbol: USART0_IRQHandler + Definitions + At line 329 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 126 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 260 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 330 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 127 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 261 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 331 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 128 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 262 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USBFS_IRQHandler 0000001A + +Symbol: USBFS_IRQHandler + + + +ARM Macro Assembler Page 16 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 357 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 156 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 288 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +USBFS_WKUP_IRQHandler 0000001A + +Symbol: USBFS_WKUP_IRQHandler + Definitions + At line 334 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 131 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + At line 265 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 196 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 77 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 197 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +WWDGT_IRQHandler 0000001A + +Symbol: WWDGT_IRQHandler + Definitions + At line 292 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 89 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + At line 223 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + +78 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00002000 + +Symbol: Heap_Size + Definitions + At line 54 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 58 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s +Comment: Heap_Size used once +Stack_Size 00002000 + +Symbol: Stack_Size + Definitions + At line 43 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s + Uses + At line 46 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s +Comment: Stack_Size used once +__Vectors_Size 00000150 + +Symbol: __Vectors_Size + Definitions + At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 69 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 +x_cl.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 168 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 169 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 167 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s + Uses + At line 171 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 +0x_cl.s +Comment: __main used once +2 symbols +429 symbols in table diff --git a/bsp/gd32107c-eval/project.ewd b/bsp/gd32107c-eval/project.ewd new file mode 100644 index 0000000000..5f99340356 --- /dev/null +++ b/bsp/gd32107c-eval/project.ewd @@ -0,0 +1,2834 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + 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Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c + gd32f10x_rcu.c + 0 + 0 + + + 9 + 78 + 2 + 0 + 0 + 0 + 0 + Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s + startup_gd32f10x_cl.s + 0 + 0 + + + + diff --git a/bsp/gd32107c-eval/project.uvprojx b/bsp/gd32107c-eval/project.uvprojx new file mode 100644 index 0000000000..5cb9c7672c --- /dev/null +++ b/bsp/gd32107c-eval/project.uvprojx @@ -0,0 +1,907 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread_gd32f107 + 0x4 + ARM-ADS + + + GD32F107VC + GigaDevice + GigaDevice.GD32F10x_DFP.2.0.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM)) + 0 + $$Device:GD32F107VC$Device\Include\gd32f10x.h + + + + + + + + + + $$Device:GD32F107VC$SVD\GD32F10x\GD32F10x_CL.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\ + Project + 1 + 0 + 1 + 1 + 1 + .\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + GD32F10X_CL, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;Libraries\CMSIS\GD\GD32F10x\Include;Libraries\CMSIS;Libraries\GD32F10x_standard_peripheral\Include;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m3\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m3\cpuport.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + i2c_core.c + 1 + ..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\components\drivers\i2c\i2c_dev.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + sfud.c + 1 + ..\..\components\drivers\spi\sfud\src\sfud.c + + + spi_flash_sfud.c + 1 + ..\..\components\drivers\spi\spi_flash_sfud.c + + + sfud_sfdp.c + 1 + ..\..\components\drivers\spi\sfud\src\sfud_sfdp.c + + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_spi.c + 1 + drivers\drv_spi.c + + + drv_i2c.c + 1 + drivers\drv_i2c.c + + + drv_spi_flash.c + 1 + drivers\drv_spi_flash.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + board.c + 1 + drivers\board.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + devfs.c + 1 + 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..\..\components\libc\compilers\common\time.c + + + + + Libraries + + + gd32f10x_enet.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_enet.c + + + gd32f10x_sdio.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_sdio.c + + + gd32f10x_can.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_can.c + + + gd32f10x_fmc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_fmc.c + + + gd32f10x_exti.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c + + + gd32f10x_dbg.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dbg.c + + + gd32f10x_misc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c + + + gd32f10x_gpio.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c + + + gd32f10x_timer.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_timer.c + + + gd32f10x_dac.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dac.c + + + gd32f10x_wwdgt.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_wwdgt.c + + + gd32f10x_adc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_adc.c + + + gd32f10x_pmu.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_pmu.c + + + gd32f10x_crc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_crc.c + + + gd32f10x_dma.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dma.c + + + gd32f10x_rtc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rtc.c + + + gd32f10x_usart.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c + + + gd32f10x_fwdgt.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_fwdgt.c + + + system_gd32f10x.c + 1 + Libraries\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c + + + gd32f10x_bkp.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_bkp.c + + + gd32f10x_i2c.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_i2c.c + + + gd32f10x_spi.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c + + + gd32f10x_exmc.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_exmc.c + + + gd32f10x_rcu.c + 1 + Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c + + + startup_gd32f10x_cl.s + 2 + Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s + + + + + + + + diff --git a/bsp/gd32107c-eval/rtconfig.h b/bsp/gd32107c-eval/rtconfig.h new file mode 100644 index 0000000000..0d8737cd9e --- /dev/null +++ b/bsp/gd32107c-eval/rtconfig.h @@ -0,0 +1,207 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_PIN +#define RT_USING_SPI +#define RT_USING_SFUD +#define RT_SFUD_USING_SFDP +#define RT_SFUD_USING_FLASH_INFO_TABLE +#define RT_SFUD_SPI_MAX_HZ 50000000 + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define SOC_SERIES_GD32F1 +#define SOC_GD32105C +#define RT_USING_USART0 +#define RT_USING_SPI0 +#define RT_USING_I2C0 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/gd32107c-eval/rtconfig.py b/bsp/gd32107c-eval/rtconfig.py new file mode 100644 index 0000000000..7a845afd38 --- /dev/null +++ b/bsp/gd32107c-eval/rtconfig.py @@ -0,0 +1,126 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # tool-chains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + EXEC_PATH += '/ARM/ARMCC/bin' + print(EXEC_PATH) + + CFLAGS += ' --c99' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config gd32_rom.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH += '/arm/bin/' + POST_ACTION = '' + diff --git a/bsp/gd32107c-eval/template.ewp b/bsp/gd32107c-eval/template.ewp new file mode 100644 index 0000000000..716042958e --- /dev/null +++ b/bsp/gd32107c-eval/template.ewp @@ -0,0 +1,1889 @@ + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/gd32107c-eval/template.uvoptx b/bsp/gd32107c-eval/template.uvoptx new file mode 100644 index 0000000000..954746e570 --- /dev/null +++ b/bsp/gd32107c-eval/template.uvoptx @@ -0,0 +1,163 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread_gd32f107 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\list\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U58001139 -O14 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(790007A3) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL0300000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/gd32107c-eval/template.uvprojx b/bsp/gd32107c-eval/template.uvprojx new file mode 100644 index 0000000000..85b169ee0f --- /dev/null +++ b/bsp/gd32107c-eval/template.uvprojx @@ -0,0 +1,410 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread_gd32f107 + 0x4 + ARM-ADS + + + GD32F107VC + GigaDevice + GigaDevice.GD32F10x_DFP.2.0.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM)) + 0 + $$Device:GD32F107VC$Device\Include\gd32f10x.h + + + + + + + + + + $$Device:GD32F107VC$SVD\GD32F10x\GD32F10x_CL.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\output\ + Project + 1 + 0 + 1 + 1 + 1 + .\list\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + + + ..\..\..\..\GD32F10x_Firmware_Library\CMSIS;..\..\..\..\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\..\..\..\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\Utilities;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + + diff --git a/bsp/gd32vf103v-eval/board/board.c b/bsp/gd32vf103v-eval/board/board.c index 5df6fa722f..3c03e3fc83 100644 --- a/bsp/gd32vf103v-eval/board/board.c +++ b/bsp/gd32vf103v-eval/board/board.c @@ -8,7 +8,7 @@ * 2019-07-23 tyustli first version * */ - +#include #include #include #include "board.h" diff --git a/bsp/gd32vf103v-eval/libraries/SConscript b/bsp/gd32vf103v-eval/libraries/SConscript index e7a4f5c3eb..932d0eef17 100644 --- a/bsp/gd32vf103v-eval/libraries/SConscript +++ b/bsp/gd32vf103v-eval/libraries/SConscript @@ -8,7 +8,6 @@ cwd = GetCurrentDir() src = Glob('GD32VF103_standard_peripheral/Source/*.c') src += Glob('n22/env_Eclipse/*.c') -src += Glob('n22/stubs/*.c') src += ['GD32VF103_standard_peripheral/system_gd32vf103.c', 'n22/drivers/n22_func.c', 'n22/env_Eclipse/start.S', diff --git a/bsp/hc32f460/.config b/bsp/hc32f460/.config new file mode 100644 index 0000000000..e9037464ea --- /dev/null +++ b/bsp/hc32f460/.config @@ -0,0 +1,600 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set + +# +# Hardware Drivers Config +# +CONFIG_MCU_HC32F460=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_UART4=y diff --git a/bsp/hc32f460/.gitignore b/bsp/hc32f460/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/hc32f460/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32f460/.ignore_format.yml b/bsp/hc32f460/.ignore_format.yml new file mode 100644 index 0000000000..d570c52faf --- /dev/null +++ b/bsp/hc32f460/.ignore_format.yml @@ -0,0 +1,8 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: + +dir_path: +- Libraries diff --git a/bsp/hc32f460/EventRecorderStub.scvd b/bsp/hc32f460/EventRecorderStub.scvd new file mode 100644 index 0000000000..2956b29683 --- /dev/null +++ b/bsp/hc32f460/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/bsp/hc32f460/Kconfig b/bsp/hc32f460/Kconfig new file mode 100644 index 0000000000..f4ed99b3fa --- /dev/null +++ b/bsp/hc32f460/Kconfig @@ -0,0 +1,23 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + + + diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/ddl_config.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/ddl_config.h new file mode 100644 index 0000000000..7bddac1a11 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/ddl_config.h @@ -0,0 +1,159 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file ddl_config.h + ** + ** A detailed description is available at + ** @link DdlConfigGroup Ddl Config description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library config. + ** + ******************************************************************************/ +#ifndef __DDL_CONFIG_H__ +#define __DDL_CONFIG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Chip module on-off define */ +#define DDL_ON (1u) +#define DDL_OFF (0u) + +/** + ******************************************************************************* + ** \brief This is the list of modules to be used in the device driver library + ** Select the modules you need to use to DDL_ON. + ** + ** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + ** properly. + ** + ** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + ** Library. + ** + ** \note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + ******************************************************************************/ +#define DDL_ICG_ENABLE (DDL_ON) +#define DDL_UTILITY_ENABLE (DDL_ON) +#define DDL_PRINT_ENABLE (DDL_ON) + +#define DDL_ADC_ENABLE (DDL_OFF) +#define DDL_AES_ENABLE (DDL_OFF) +#define DDL_CAN_ENABLE (DDL_OFF) +#define DDL_CLK_ENABLE (DDL_ON) +#define DDL_CMP_ENABLE (DDL_OFF) +#define DDL_CRC_ENABLE (DDL_OFF) +#define DDL_DCU_ENABLE (DDL_OFF) +#define DDL_DMAC_ENABLE (DDL_ON) +#define DDL_EFM_ENABLE (DDL_ON) +#define DDL_EMB_ENABLE (DDL_OFF) +#define DDL_EVENT_PORT_ENABLE (DDL_OFF) +#define DDL_EXINT_NMI_SWI_ENABLE (DDL_ON) +#define DDL_GPIO_ENABLE (DDL_ON) +#define DDL_HASH_ENABLE (DDL_OFF) +#define DDL_I2C_ENABLE (DDL_OFF) +#define DDL_I2S_ENABLE (DDL_OFF) +#define DDL_INTERRUPTS_ENABLE (DDL_ON) +#define DDL_KEYSCAN_ENABLE (DDL_OFF) +#define DDL_MPU_ENABLE (DDL_OFF) +#define DDL_OTS_ENABLE (DDL_OFF) +#define DDL_PWC_ENABLE (DDL_ON) +#define DDL_QSPI_ENABLE (DDL_OFF) +#define DDL_RMU_ENABLE (DDL_OFF) +#define DDL_RTC_ENABLE (DDL_OFF) +#define DDL_SDIOC_ENABLE (DDL_OFF) +#define DDL_SPI_ENABLE (DDL_OFF) +#define DDL_SRAM_ENABLE (DDL_ON) +#define DDL_SWDT_ENABLE (DDL_OFF) +#define DDL_TIMER0_ENABLE (DDL_ON) +#define DDL_TIMER4_CNT_ENABLE (DDL_OFF) +#define DDL_TIMER4_EMB_ENABLE (DDL_OFF) +#define DDL_TIMER4_OCO_ENABLE (DDL_OFF) +#define DDL_TIMER4_PWM_ENABLE (DDL_OFF) +#define DDL_TIMER4_SEVT_ENABLE (DDL_OFF) +#define DDL_TIMER6_ENABLE (DDL_OFF) +#define DDL_TIMERA_ENABLE (DDL_OFF) +#define DDL_TRNG_ENABLE (DDL_OFF) +#define DDL_USART_ENABLE (DDL_ON) +#define DDL_USBFS_ENABLE (DDL_OFF) +#define DDL_WDT_ENABLE (DDL_OFF) + + +/*! Midware module on-off define */ +#define MW_ON (1u) +#define MW_OFF (0u) + +/** + ******************************************************************************* + ** \brief This is the list of Midware modules to use + ** Select the modules you need to use to MW_ON. + ******************************************************************************/ +#define MW_SD_CARD_ENABLE (MW_OFF) +#define MW_FS_ENABLE (MW_OFF) +#define MW_W25QXX_ENABLE (MW_OFF) +#define MW_WM8731_ENABLE (MW_OFF) + +/* BSP on-off define */ +#define BSP_ON (1u) +#define BSP_OFF (0u) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F460_LQFP100_V1 (1u) +#define BSP_EV_HC32F460_LQFP100_V2 (2u) + +/** + * @brief The macro BSP_EV_HC32F460 is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to BSP_EV_HC32F460. + */ +#define BSP_EV_HC32F460 (BSP_EV_HC32F460) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // DdlConfigGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_CONFIG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_common.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_common.h new file mode 100644 index 0000000000..6de31bc856 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_common.h @@ -0,0 +1,234 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32_common.h + ** + ** A detailed description is available at + ** @link Hc32CommonGroup Hc32 Series Comm Part description @endlink + ** + ** - 2018-10-18 CDT First version for Hc32 Series of common part. + ** + ******************************************************************************/ +#ifndef __HC32_COMMON_H__ +#define __HC32_COMMON_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include +#include +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32CommonGroup Hc32 Series Common Part(HC32COMMON) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief single precision floating point number (4 byte) + ******************************************************************************/ +typedef float float32_t; + +/** + ******************************************************************************* + ** \brief double precision floating point number (8 byte) + ******************************************************************************/ +typedef double float64_t; + +/** + ******************************************************************************* + ** \brief function pointer type to void/void function + ******************************************************************************/ +typedef void (*func_ptr_t)(void); + +/** + ******************************************************************************* + ** \brief function pointer type to void/uint8_t function + ******************************************************************************/ +typedef void (*func_ptr_arg1_t)(uint8_t); + +/** + ******************************************************************************* + ** \brief functional state + ******************************************************************************/ +typedef enum en_functional_state +{ + Disable = 0u, + Enable = 1u, +} en_functional_state_t; + +/** + ******************************************************************************* + ** \brief flag status + ******************************************************************************/ +typedef enum en_flag_status +{ + Reset = 0u, + Set = 1u, +} en_flag_status_t, en_int_status_t; + +/** + ******************************************************************************* + ** \brief generic error codes + ******************************************************************************/ +typedef enum en_result +{ + Ok = 0u, ///< No error + Error = 1u, ///< Non-specific error code + ErrorAddressAlignment = 2u, ///< Address alignment does not match + ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4u, ///< Provided parameter is not valid + ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6u, ///< Operation not allowed in current mode + ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10u, ///< A requested final state is not reached + OperationInProgress = 11u, ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) +} en_result_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Device include + ******************************************************************************/ +#if defined(HC32F460) +#include "hc32f460.h" +#include "system_hc32f460.h" +#elif defined(HC32xxxx) +#include "hc32xxxx.h" +#include "system_hc32xxxx.h" +#else +#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)" +#endif + +/*! Weak and Align compiler definition */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __WEAKDEF + #define __WEAKDEF __attribute__((weak)) + #endif /* __WEAKDEF */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN __attribute__((aligned (4))) + #endif /* __ALIGN_BEGIN */ + #ifndef __NOINLINE + #define __NOINLINE __attribute__((noinline)) + #endif /* __NOINLINE */ + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif /* __UNUSED */ + #ifndef __RAM_FUNC + #define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) + /* Usage: void __RAM_FUNC foo(void) */ + #endif /* __RAM_FUNC */ +#elif defined (__ICCARM__) ///< IAR Compiler +#define __WEAKDEF __weak +#define __ALIGN_BEGIN _Pragma("data_alignment=4") +#define __NOINLINE _Pragma("optimize = no_inline") +#define __UNUSED __attribute__((unused)) +#define __RAM_FUNC __ramfunc +#elif defined (__CC_ARM) ///< ARM Compiler +#define __WEAKDEF __attribute__((weak)) +#define __ALIGN_BEGIN __align(4) +#define __NOINLINE __attribute__((noinline)) +#define __UNUSED __attribute__((unused)) +/* RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. */ +#define __RAM_FUNC +#else +#error "unsupported compiler!!" +#endif /* __GNUC__ */ + +/*! Pointer correspond to zero value */ +#if !defined (NULL) +#define NULL (0) +#endif + +/*! Memory clear */ +#define MEM_ZERO_STRUCT(x) do { \ + memset((void*)&(x), 0l, (sizeof(x))); \ + }while(0) + +/*! Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10u) << 4u) + ((x) % 10u)) + +/*! BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4u) * 10u) + ((x) & 0x0Fu)) + +/*! Returns the minimum value out of two values */ +#define MIN(x, y) ((x) < (y) ? (x) : (y)) + +/*! Returns the maximum value out of two values */ +#define MAX(x, y) ((x) > (y) ? (x) : (y)) + +/*! Returns the dimension of an array */ +#define ARRAY_SZ(X) (sizeof((X)) / sizeof((X)[0])) + +/*! Check if it is a functional state */ +#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable)) + +#define BIT_SET(value,bit) ((value) |= (bit)) + +#define BIT_CLEAR(value,bit) ((value) &= ~(bit)) + +#define BIT_READ(value,bit) ((value) & (bit)) + +#define BIT_VALUE(index) (1ul << (index)) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT))) +#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT))) +#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT))) + +#define READ_REG8(REG) (REG) +#define READ_REG16(REG) (REG) +#define READ_REG32(REG) (REG) + +#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL))) +#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL))) +#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL))) + +#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK))))) +#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK))))) +#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK))))) + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // Hc32CommonGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_COMMON_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_ddl.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_ddl.h new file mode 100644 index 0000000000..4a9a1228f9 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32_ddl.h @@ -0,0 +1,262 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32_ddl.h + ** + ** A detailed description is available at + ** @link Hc32DdlGroup Hc32 Series Ddl description @endlink + ** + ** - 2018-9-28 CDT First version for Hc32 Series Device Driver + ** Library. + ** + ******************************************************************************/ +#ifndef __HC32_DDL_H__ +#define __HC32_DDL_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32DdlGroup Hc32 Series Device Driver Library(HC32DDL) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Defined use device driver library */ +#if !defined (USE_DEVICE_DRIVER_LIB) +/** + ******************************************************************************* + ** \brief Comment the line below if you will not use the device driver library. + ** In this case, the application code will be based on direct access to + ** peripherals registers. + ******************************************************************************/ + /* #define USE_DEVICE_DRIVER_LIB */ +#endif /* USE_DEVICE_DRIVER_LIB */ + +/** + ******************************************************************************* + ** \brief Hc32 Series device driver library version number v1.0.0 + ******************************************************************************/ +#define HC32_DDL_VERSION_MAIN 0x01u ///< [31:24] main version +#define HC32_DDL_VERSION_SUB1 0x00u ///< [23:16] sub1 version +#define HC32_DDL_VERSION_SUB2 0x00u ///< [15:8] sub2 version +#define HC32_DDL_VERSION_RC 0x00u ///< [7:0] release candidate +#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \ + (HC32_DDL_VERSION_SUB1 << 16) | \ + (HC32_DDL_VERSION_SUB2 << 8 ) | \ + (HC32_DDL_VERSION_RC)) + +/*! Use device driver library */ +#if defined (USE_DEVICE_DRIVER_LIB) +/** + ******************************************************************************* + ** \brief Include module's header file + ******************************************************************************/ +#if (DDL_ADC_ENABLE == DDL_ON) +#include "hc32f460_adc.h" +#endif /* DDL_ADC_ENABLE */ + +#if (DDL_AES_ENABLE == DDL_ON) +#include "hc32f460_aes.h" +#endif /* DDL_AES_ENABLE */ + +#if (DDL_CAN_ENABLE == DDL_ON) +#include "hc32f460_can.h" +#endif /* DDL_CAN_ENABLE */ + +#if (DDL_CMP_ENABLE == DDL_ON) +#include "hc32f460_cmp.h" +#endif /* DDL_CMP_ENABLE */ + +#if (DDL_CLK_ENABLE == DDL_ON) +#include "hc32f460_clk.h" +#endif /* DDL_CLK_ENABLE */ + +#if (DDL_DCU_ENABLE == DDL_ON) +#include "hc32f460_dcu.h" +#endif /* DDL_DCU_ENABLE */ + +#if (DDL_DMAC_ENABLE == DDL_ON) +#include "hc32f460_dmac.h" +#endif /* DDL_DMAC_ENABLE */ + +#if (DDL_EFM_ENABLE == DDL_ON) +#include "hc32f460_efm.h" +#endif /* DDL_EFM_ENABLE */ + +#if (DDL_EMB_ENABLE == DDL_ON) +#include "hc32f460_emb.h" +#endif /* DDL_EMB_ENABLE */ + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) +#include "hc32f460_exint_nmi_swi.h" +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +#if (DDL_GPIO_ENABLE == DDL_ON) +#include "hc32f460_gpio.h" +#endif /* DDL_GPIO_ENABLE */ + +#if (DDL_HASH_ENABLE == DDL_ON) +#include "hc32f460_hash.h" +#endif /* DDL_HASH_ENABLE */ + +#if (DDL_I2C_ENABLE == DDL_ON) +#include "hc32f460_i2c.h" +#endif /* DDL_I2C_ENABLE */ + +#if (DDL_I2S_ENABLE == DDL_ON) +#include "hc32f460_i2s.h" +#endif /* DDL_I2S_ENABLE */ + +#if (DDL_ICG_ENABLE == DDL_ON) +#include "hc32f460_icg.h" +#endif /* DDL_ICG_ENABLE */ + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) +#include "hc32f460_interrupts.h" +#endif /* DDL_INTERRUPTS_ENABLE */ + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) +#include "hc32f460_keyscan.h" +#endif /* DDL_KEYSCAN_ENABLE */ + +#if (DDL_MPU_ENABLE == DDL_ON) +#include "hc32f460_mpu.h" +#endif /* DDL_MPU_ENABLE */ + +#if (DDL_OTS_ENABLE == DDL_ON) +#include "hc32f460_ots.h" +#endif /* DDL_OTS_ENABLE */ + +#if (DDL_PGA_ENABLE == DDL_ON) +#include "hc32f460_pga.h" +#endif /* DDL_PGA_ENABLE */ + +#if (DDL_PWC_ENABLE == DDL_ON) +#include "hc32f460_pwc.h" +#endif /* DDL_PWC_ENABLE */ + +#if (DDL_QSPI_ENABLE == DDL_ON) +#include "hc32f460_qspi.h" +#endif /* DDL_QSPI_ENABLE */ + +#if (DDL_RMU_ENABLE == DDL_ON) +#include "hc32f460_rmu.h" +#endif /* DDL_RMU_ENABLE */ + +#if (DDL_RTC_ENABLE == DDL_ON) +#include "hc32f460_rtc.h" +#endif /* DDL_RTC_ENABLE */ + +#if (DDL_SDIOC_ENABLE == DDL_ON) +#include "hc32f460_sdioc.h" +#endif /* DDL_SDIOC_ENABLE */ + +#if (DDL_SPI_ENABLE == DDL_ON) +#include "hc32f460_spi.h" +#endif /* DDL_SPI_ENABLE */ + +#if (DDL_SRAM_ENABLE == DDL_ON) +#include "hc32f460_sram.h" +#endif /* DDL_SRAM_ENABLE */ + +#if (DDL_SWDT_ENABLE == DDL_ON) +#include "hc32f460_swdt.h" +#endif /* DDL_SWDT_ENABLE */ + +#if (DDL_TIMER0_ENABLE == DDL_ON) +#include "hc32f460_timer0.h" +#endif /* DDL_TIMER0_ENABLE */ + +#if (DDL_TIMER4_CNT_ENABLE == DDL_ON) +#include "hc32f460_timer4_cnt.h" +#endif /* DDL_TIMER4_CNT_ENABLE */ + +#if (DDL_TIMER4_EMB_ENABLE == DDL_ON) +#include "hc32f460_timer4_emb.h" +#endif /* DDL_TIMER4_EMB_ENABLE */ + +#if (DDL_TIMER4_OCO_ENABLE == DDL_ON) +#include "hc32f460_timer4_oco.h" +#endif /* DDL_TIMER4_OCO_ENABLE */ + +#if (DDL_TIMER4_PWM_ENABLE == DDL_ON) +#include "hc32f460_timer4_pwm.h" +#endif /* DDL_TIMER4_PWM_ENABLE */ + +#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON) +#include "hc32f460_timer4_sevt.h" +#endif /* DDL_TIMER4_SEVT_ENABLE */ + +#if (DDL_TIMER6_ENABLE == DDL_ON) +#include "hc32f460_timer6.h" +#endif /* DDL_TIMER6_ENABLE */ + +#if (DDL_TIMERA_ENABLE == DDL_ON) +#include "hc32f460_timera.h" +#endif /* DDL_TIMERA_ENABLE */ + +#if (DDL_TRNG_ENABLE == DDL_ON) +#include "hc32f460_trng.h" +#endif /* DDL_TRNG_ENABLE */ + +#if (DDL_USART_ENABLE == DDL_ON) +#include "hc32f460_usart.h" +#endif /* DDL_USART_ENABLE */ + +#if (DDL_USBFS_ENABLE == DDL_ON) +#include "hc32f460_usbfs.h" +#endif /* DDL_USBFS_ENABLE */ + +#if (DDL_UTILITY_ENABLE == DDL_ON) +#include "hc32f460_utility.h" +#endif /* DDL_UTILITY_ENABLE */ + +#if (DDL_WDT_ENABLE == DDL_ON) +#include "hc32f460_wdt.h" +#endif /* DDL_WDT_ENABLE */ + +#endif /* USE_DEVICE_DRIVER_LIB */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // Hc32DdlGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_DDL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32f460.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32f460.h new file mode 100644 index 0000000000..a62c8418e5 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/hc32f460.h @@ -0,0 +1,30601 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file HC32F460.h + ** + ** Auto generate. + ** Headerfile for HC32F460 series MCU + ** + ** History: + ** + ** - 2020-12-16 1.03 First version for Device Driver Library of HC32F460 series MCU. + ** + ******************************************************************************/ + +#ifndef __HC32F460_H__ +#define __HC32F460_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< HC32F460 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F460 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManageFault_IRQn = -12, /* 4 MemManage Fault */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DM_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + Int000_IRQn = 0, + Int001_IRQn = 1, + Int002_IRQn = 2, + Int003_IRQn = 3, + Int004_IRQn = 4, + Int005_IRQn = 5, + Int006_IRQn = 6, + Int007_IRQn = 7, + Int008_IRQn = 8, + Int009_IRQn = 9, + Int010_IRQn = 10, + Int011_IRQn = 11, + Int012_IRQn = 12, + Int013_IRQn = 13, + Int014_IRQn = 14, + Int015_IRQn = 15, + Int016_IRQn = 16, + Int017_IRQn = 17, + Int018_IRQn = 18, + Int019_IRQn = 19, + Int020_IRQn = 20, + Int021_IRQn = 21, + Int022_IRQn = 22, + Int023_IRQn = 23, + Int024_IRQn = 24, + Int025_IRQn = 25, + Int026_IRQn = 26, + Int027_IRQn = 27, + Int028_IRQn = 28, + Int029_IRQn = 29, + Int030_IRQn = 30, + Int031_IRQn = 31, + Int032_IRQn = 32, + Int033_IRQn = 33, + Int034_IRQn = 34, + Int035_IRQn = 35, + Int036_IRQn = 36, + Int037_IRQn = 37, + Int038_IRQn = 38, + Int039_IRQn = 39, + Int040_IRQn = 40, + Int041_IRQn = 41, + Int042_IRQn = 42, + Int043_IRQn = 43, + Int044_IRQn = 44, + Int045_IRQn = 45, + Int046_IRQn = 46, + Int047_IRQn = 47, + Int048_IRQn = 48, + Int049_IRQn = 49, + Int050_IRQn = 50, + Int051_IRQn = 51, + Int052_IRQn = 52, + Int053_IRQn = 53, + Int054_IRQn = 54, + Int055_IRQn = 55, + Int056_IRQn = 56, + Int057_IRQn = 57, + Int058_IRQn = 58, + Int059_IRQn = 59, + Int060_IRQn = 60, + Int061_IRQn = 61, + Int062_IRQn = 62, + Int063_IRQn = 63, + Int064_IRQn = 64, + Int065_IRQn = 65, + Int066_IRQn = 66, + Int067_IRQn = 67, + Int068_IRQn = 68, + Int069_IRQn = 69, + Int070_IRQn = 70, + Int071_IRQn = 71, + Int072_IRQn = 72, + Int073_IRQn = 73, + Int074_IRQn = 74, + Int075_IRQn = 75, + Int076_IRQn = 76, + Int077_IRQn = 77, + Int078_IRQn = 78, + Int079_IRQn = 79, + Int080_IRQn = 80, + Int081_IRQn = 81, + Int082_IRQn = 82, + Int083_IRQn = 83, + Int084_IRQn = 84, + Int085_IRQn = 85, + Int086_IRQn = 86, + Int087_IRQn = 87, + Int088_IRQn = 88, + Int089_IRQn = 89, + Int090_IRQn = 90, + Int091_IRQn = 91, + Int092_IRQn = 92, + Int093_IRQn = 93, + Int094_IRQn = 94, + Int095_IRQn = 95, + Int096_IRQn = 96, + Int097_IRQn = 97, + Int098_IRQn = 98, + Int099_IRQn = 99, + Int100_IRQn = 100, + Int101_IRQn = 101, + Int102_IRQn = 102, + Int103_IRQn = 103, + Int104_IRQn = 104, + Int105_IRQn = 105, + Int106_IRQn = 106, + Int107_IRQn = 107, + Int108_IRQn = 108, + Int109_IRQn = 109, + Int110_IRQn = 110, + Int111_IRQn = 111, + Int112_IRQn = 112, + Int113_IRQn = 113, + Int114_IRQn = 114, + Int115_IRQn = 115, + Int116_IRQn = 116, + Int117_IRQn = 117, + Int118_IRQn = 118, + Int119_IRQn = 119, + Int120_IRQn = 120, + Int121_IRQn = 121, + Int122_IRQn = 122, + Int123_IRQn = 123, + Int124_IRQn = 124, + Int125_IRQn = 125, + Int126_IRQn = 126, + Int127_IRQn = 127, + Int128_IRQn = 128, + Int129_IRQn = 129, + Int130_IRQn = 130, + Int131_IRQn = 131, + Int132_IRQn = 132, + Int133_IRQn = 133, + Int134_IRQn = 134, + Int135_IRQn = 135, + Int136_IRQn = 136, + Int137_IRQn = 137, + Int138_IRQn = 138, + Int139_IRQn = 139, + Int140_IRQn = 140, + Int141_IRQn = 141, + Int142_IRQn = 142, + Int143_IRQn = 143, + +}IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum en_event_src +{ + EVT_SWI_IRQ0 = 0u, + EVT_SWI_IRQ1 = 1u, + EVT_SWI_IRQ2 = 2u, + EVT_SWI_IRQ3 = 3u, + EVT_SWI_IRQ4 = 4u, + EVT_SWI_IRQ5 = 5u, + EVT_SWI_IRQ6 = 6u, + EVT_SWI_IRQ7 = 7u, + EVT_SWI_IRQ8 = 8u, + EVT_SWI_IRQ9 = 9u, + EVT_SWI_IRQ10 = 10u, + EVT_SWI_IRQ11 = 11u, + EVT_SWI_IRQ12 = 12u, + EVT_SWI_IRQ13 = 13u, + EVT_SWI_IRQ14 = 14u, + EVT_SWI_IRQ15 = 15u, + EVT_SWI_IRQ16 = 16u, + EVT_SWI_IRQ17 = 17u, + EVT_SWI_IRQ18 = 18u, + EVT_SWI_IRQ19 = 19u, + EVT_SWI_IRQ20 = 20u, + EVT_SWI_IRQ21 = 21u, + EVT_SWI_IRQ22 = 22u, + EVT_SWI_IRQ23 = 23u, + EVT_SWI_IRQ24 = 24u, + EVT_SWI_IRQ25 = 25u, + EVT_SWI_IRQ26 = 26u, + EVT_SWI_IRQ27 = 27u, + EVT_SWI_IRQ28 = 28u, + EVT_SWI_IRQ29 = 29u, + EVT_SWI_IRQ30 = 30u, + EVT_SWI_IRQ31 = 31u, + + /* External Interrupt. */ + EVT_PORT_EIRQ0 = 0u, + EVT_PORT_EIRQ1 = 1u, + EVT_PORT_EIRQ2 = 2u, + EVT_PORT_EIRQ3 = 3u, + EVT_PORT_EIRQ4 = 4u, + EVT_PORT_EIRQ5 = 5u, + EVT_PORT_EIRQ6 = 6u, + EVT_PORT_EIRQ7 = 7u, + EVT_PORT_EIRQ8 = 8u, + EVT_PORT_EIRQ9 = 9u, + EVT_PORT_EIRQ10 = 10u, + EVT_PORT_EIRQ11 = 11u, + EVT_PORT_EIRQ12 = 12u, + EVT_PORT_EIRQ13 = 13u, + EVT_PORT_EIRQ14 = 14u, + EVT_PORT_EIRQ15 = 15u, + + /* DMAC */ + EVT_DMA1_TC0 = 32u, + EVT_DMA1_TC1 = 33u, + EVT_DMA1_TC2 = 34u, + EVT_DMA1_TC3 = 35u, + EVT_DMA2_TC0 = 36u, + EVT_DMA2_TC1 = 37u, + EVT_DMA2_TC2 = 38u, + EVT_DMA2_TC3 = 39u, + EVT_DMA1_BTC0 = 40u, + EVT_DMA1_BTC1 = 41u, + EVT_DMA1_BTC2 = 42u, + EVT_DMA1_BTC3 = 43u, + EVT_DMA2_BTC0 = 44u, + EVT_DMA2_BTC1 = 45u, + EVT_DMA2_BTC2 = 46u, + EVT_DMA2_BTC3 = 47u, + + /* EFM */ + EVT_EFM_OPTEND = 52u, + + /* USB SOF */ + EVT_USBFS_SOF = 53u, + + /* DCU */ + EVT_DCU1 = 55u, + EVT_DCU2 = 56u, + EVT_DCU3 = 57u, + EVT_DCU4 = 58u, + + /* TIMER 0 */ + EVT_TMR01_GCMA = 64u, + EVT_TMR01_GCMB = 65u, + EVT_TMR02_GCMA = 66u, + EVT_TMR02_GCMB = 67u, + + /* RTC */ + EVT_RTC_ALM = 81u, + EVT_RTC_PRD = 82u, + + /* TIMER 6 */ + EVT_TMR61_GCMA = 96u, + EVT_TMR61_GCMB = 97u, + EVT_TMR61_GCMC = 98u, + EVT_TMR61_GCMD = 99u, + EVT_TMR61_GCME = 100u, + EVT_TMR61_GCMF = 101u, + EVT_TMR61_GOVF = 102u, + EVT_TMR61_GUDF = 103u, + EVT_TMR61_SCMA = 107u, + EVT_TMR61_SCMB = 108u, + EVT_TMR62_GCMA = 112u, + EVT_TMR62_GCMB = 113u, + EVT_TMR62_GCMC = 114u, + EVT_TMR62_GCMD = 115u, + EVT_TMR62_GCME = 116u, + EVT_TMR62_GCMF = 117u, + EVT_TMR62_GOVF = 118u, + EVT_TMR62_GUDF = 119u, + EVT_TMR62_SCMA = 123u, + EVT_TMR62_SCMB = 124u, + EVT_TMR63_GCMA = 128u, + EVT_TMR63_GCMB = 129u, + EVT_TMR63_GCMC = 130u, + EVT_TMR63_GCMD = 131u, + EVT_TMR63_GCME = 132u, + EVT_TMR63_GCMF = 133u, + EVT_TMR63_GOVF = 134u, + EVT_TMR63_GUDF = 135u, + EVT_TMR63_SCMA = 139u, + EVT_TMR63_SCMB = 140u, + + /* TIMER A */ + EVT_TMRA1_OVF = 256u, + EVT_TMRA1_UDF = 257u, + EVT_TMRA1_CMP = 258u, + EVT_TMRA2_OVF = 259u, + EVT_TMRA2_UDF = 260u, + EVT_TMRA2_CMP = 261u, + EVT_TMRA3_OVF = 262u, + EVT_TMRA3_UDF = 263u, + EVT_TMRA3_CMP = 264u, + EVT_TMRA4_OVF = 265u, + EVT_TMRA4_UDF = 266u, + EVT_TMRA4_CMP = 267u, + EVT_TMRA5_OVF = 268u, + EVT_TMRA5_UDF = 269u, + EVT_TMRA5_CMP = 270u, + EVT_TMRA6_OVF = 272u, + EVT_TMRA6_UDF = 273u, + EVT_TMRA6_CMP = 274u, + + /* USART */ + EVT_USART1_EI = 278u, + EVT_USART1_RI = 279u, + EVT_USART1_TI = 280u, + EVT_USART1_TCI = 281u, + EVT_USART1_RTO = 282u, + EVT_USART2_EI = 283u, + EVT_USART2_RI = 284u, + EVT_USART2_TI = 285u, + EVT_USART2_TCI = 286u, + EVT_USART2_RTO = 287u, + EVT_USART3_EI = 288u, + EVT_USART3_RI = 289u, + EVT_USART3_TI = 290u, + EVT_USART3_TCI = 291u, + EVT_USART3_RTO = 292u, + EVT_USART4_EI = 293u, + EVT_USART4_RI = 294u, + EVT_USART4_TI = 295u, + EVT_USART4_TCI = 296u, + EVT_USART4_RTO = 297u, + + /* SPI */ + EVT_SPI1_SPRI = 299u, + EVT_SPI1_SPTI = 300u, + EVT_SPI1_SPII = 301u, + EVT_SPI1_SPEI = 302u, + EVT_SPI1_SPTEND = 303u, + EVT_SPI2_SPRI = 304u, + EVT_SPI2_SPTI = 305u, + EVT_SPI2_SPII = 306u, + EVT_SPI2_SPEI = 307u, + EVT_SPI2_SPTEND = 308u, + EVT_SPI3_SPRI = 309u, + EVT_SPI3_SPTI = 310u, + EVT_SPI3_SPII = 311u, + EVT_SPI3_SPEI = 312u, + EVT_SPI3_SPTEND = 313u, + EVT_SPI4_SPRI = 314u, + EVT_SPI4_SPTI = 315u, + EVT_SPI4_SPII = 316u, + EVT_SPI4_SPEI = 317u, + EVT_SPI4_SPTEND = 318u, + + /* AOS */ + EVT_AOS_STRG = 319u, + + /* TIMER 4 */ + EVT_TMR41_SCMUH = 368u, + EVT_TMR41_SCMUL = 369u, + EVT_TMR41_SCMVH = 370u, + EVT_TMR41_SCMVL = 371u, + EVT_TMR41_SCMWH = 372u, + EVT_TMR41_SCMWL = 373u, + EVT_TMR42_SCMUH = 374u, + EVT_TMR42_SCMUL = 375u, + EVT_TMR42_SCMVH = 376u, + EVT_TMR42_SCMVL = 377u, + EVT_TMR42_SCMWH = 378u, + EVT_TMR42_SCMWL = 379u, + EVT_TMR43_SCMUH = 384u, + EVT_TMR43_SCMUL = 385u, + EVT_TMR43_SCMVH = 386u, + EVT_TMR43_SCMVL = 387u, + EVT_TMR43_SCMWH = 388u, + EVT_TMR43_SCMWL = 389u, + + /* EVENT PORT */ + EVT_EVENT_PORT1 = 394u, + EVT_EVENT_PORT2 = 395u, + EVT_EVENT_PORT3 = 396u, + EVT_EVENT_PORT4 = 397u, + + /* I2S */ + EVT_I2S1_TXIRQOUT = 400u, + EVT_I2S1_RXIRQOUT = 401u, + EVT_I2S2_TXIRQOUT = 403u, + EVT_I2S2_RXIRQOUT = 404u, + EVT_I2S3_TXIRQOUT = 406u, + EVT_I2S3_RXIRQOUT = 407u, + EVT_I2S4_TXIRQOUT = 409u, + EVT_I2S4_RXIRQOUT = 410u, + + /* COMPARATOR */ + EVT_ACMP1 = 416u, + EVT_ACMP2 = 417u, + EVT_ACMP3 = 418u, + + /* I2C */ + EVT_I2C1_RXI = 420u, + EVT_I2C1_TXI = 421u, + EVT_I2C1_TEI = 422u, + EVT_I2C1_EEI = 423u, + EVT_I2C2_RXI = 424u, + EVT_I2C2_TXI = 425u, + EVT_I2C2_TEI = 426u, + EVT_I2C2_EEI = 427u, + EVT_I2C3_RXI = 428u, + EVT_I2C3_TXI = 429u, + EVT_I2C3_TEI = 430u, + EVT_I2C3_EEI = 431u, + + /* PVD */ + EVT_PVD_PVD1 = 433u, + EVT_PVD_PVD2 = 434u, + + /* OTS */ + EVT_OTS = 435u, + + /* WDT */ + EVT_WDT_REFUDF = 439u, + + /* ADC */ + EVT_ADC1_EOCA = 448u, + EVT_ADC1_EOCB = 449u, + EVT_ADC1_CHCMP = 450u, + EVT_ADC1_SEQCMP = 451u, + EVT_ADC2_EOCA = 452u, + EVT_ADC2_EOCB = 453u, + EVT_ADC2_CHCMP = 454u, + EVT_ADC2_SEQCMP = 455u, + + /* TRNG */ + EVT_TRNG_END = 456u, + + /* SDIO */ + EVT_SDIOC1_DMAR = 480u, + EVT_SDIOC1_DMAW = 481u, + EVT_SDIOC2_DMAR = 483u, + EVT_SDIOC2_DMAW = 484u, + EVT_MAX = 511u, +}en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum en_int_src +{ + INT_SWI_IRQ0 = 0u, + INT_SWI_IRQ1 = 1u, + INT_SWI_IRQ2 = 2u, + INT_SWI_IRQ3 = 3u, + INT_SWI_IRQ4 = 4u, + INT_SWI_IRQ5 = 5u, + INT_SWI_IRQ6 = 6u, + INT_SWI_IRQ7 = 7u, + INT_SWI_IRQ8 = 8u, + INT_SWI_IRQ9 = 9u, + INT_SWI_IRQ10 = 10u, + INT_SWI_IRQ11 = 11u, + INT_SWI_IRQ12 = 12u, + INT_SWI_IRQ13 = 13u, + INT_SWI_IRQ14 = 14u, + INT_SWI_IRQ15 = 15u, + INT_SWI_IRQ16 = 16u, + INT_SWI_IRQ17 = 17u, + INT_SWI_IRQ18 = 18u, + INT_SWI_IRQ19 = 19u, + INT_SWI_IRQ20 = 20u, + INT_SWI_IRQ21 = 21u, + INT_SWI_IRQ22 = 22u, + INT_SWI_IRQ23 = 23u, + INT_SWI_IRQ24 = 24u, + INT_SWI_IRQ25 = 25u, + INT_SWI_IRQ26 = 26u, + INT_SWI_IRQ27 = 27u, + INT_SWI_IRQ28 = 28u, + INT_SWI_IRQ29 = 29u, + INT_SWI_IRQ30 = 30u, + INT_SWI_IRQ31 = 31u, + + /* External Interrupt. */ + INT_PORT_EIRQ0 = 0u, + INT_PORT_EIRQ1 = 1u, + INT_PORT_EIRQ2 = 2u, + INT_PORT_EIRQ3 = 3u, + INT_PORT_EIRQ4 = 4u, + INT_PORT_EIRQ5 = 5u, + INT_PORT_EIRQ6 = 6u, + INT_PORT_EIRQ7 = 7u, + INT_PORT_EIRQ8 = 8u, + INT_PORT_EIRQ9 = 9u, + INT_PORT_EIRQ10 = 10u, + INT_PORT_EIRQ11 = 11u, + INT_PORT_EIRQ12 = 12u, + INT_PORT_EIRQ13 = 13u, + INT_PORT_EIRQ14 = 14u, + INT_PORT_EIRQ15 = 15u, + + /* DMAC */ + INT_DMA1_TC0 = 32u, + INT_DMA1_TC1 = 33u, + INT_DMA1_TC2 = 34u, + INT_DMA1_TC3 = 35u, + INT_DMA2_TC0 = 36u, + INT_DMA2_TC1 = 37u, + INT_DMA2_TC2 = 38u, + INT_DMA2_TC3 = 39u, + INT_DMA1_BTC0 = 40u, + INT_DMA1_BTC1 = 41u, + INT_DMA1_BTC2 = 42u, + INT_DMA1_BTC3 = 43u, + INT_DMA2_BTC0 = 44u, + INT_DMA2_BTC1 = 45u, + INT_DMA2_BTC2 = 46u, + INT_DMA2_BTC3 = 47u, + INT_DMA1_ERR = 48u, + INT_DMA2_ERR = 49u, + + /* EFM */ + INT_EFM_PEERR = 50u, + INT_EFM_COLERR = 51u, + INT_EFM_OPTEND = 52u, + + /* QSPI */ + INT_QSPI_INTR = 54u, + + /* DCU */ + INT_DCU1 = 55u, + INT_DCU2 = 56u, + INT_DCU3 = 57u, + INT_DCU4 = 58u, + + /* TIMER 0 */ + INT_TMR01_GCMA = 64u, + INT_TMR01_GCMB = 65u, + INT_TMR02_GCMA = 66u, + INT_TMR02_GCMB = 67u, + + /* RTC */ + INT_RTC_ALM = 81u, + INT_RTC_PRD = 82u, + + /* XTAL32 stop */ + INT_XTAL32_STOP = 84u, + + /* XTAL stop */ + INT_XTAL_STOP = 85u, + + /* wake-up timer */ + INT_WKTM_PRD = 86u, + + /* SWDT */ + INT_SWDT_REFUDF = 87u, + + /* TIMER 6 */ + INT_TMR61_GCMA = 96u, + INT_TMR61_GCMB = 97u, + INT_TMR61_GCMC = 98u, + INT_TMR61_GCMD = 99u, + INT_TMR61_GCME = 100u, + INT_TMR61_GCMF = 101u, + INT_TMR61_GOVF = 102u, + INT_TMR61_GUDF = 103u, + INT_TMR61_GDTE = 104u, + INT_TMR61_SCMA = 107u, + INT_TMR61_SCMB = 108u, + INT_TMR62_GCMA = 112u, + INT_TMR62_GCMB = 113u, + INT_TMR62_GCMC = 114u, + INT_TMR62_GCMD = 115u, + INT_TMR62_GCME = 116u, + INT_TMR62_GCMF = 117u, + INT_TMR62_GOVF = 118u, + INT_TMR62_GUDF = 119u, + INT_TMR62_GDTE = 120u, + INT_TMR62_SCMA = 123u, + INT_TMR62_SCMB = 124u, + INT_TMR63_GCMA = 128u, + INT_TMR63_GCMB = 129u, + INT_TMR63_GCMC = 130u, + INT_TMR63_GCMD = 131u, + INT_TMR63_GCME = 132u, + INT_TMR63_GCMF = 133u, + INT_TMR63_GOVF = 134u, + INT_TMR63_GUDF = 135u, + INT_TMR63_GDTE = 136u, + INT_TMR63_SCMA = 139u, + INT_TMR63_SCMB = 140u, + + /* TIMER A */ + INT_TMRA1_OVF = 256u, + INT_TMRA1_UDF = 257u, + INT_TMRA1_CMP = 258u, + INT_TMRA2_OVF = 259u, + INT_TMRA2_UDF = 260u, + INT_TMRA2_CMP = 261u, + INT_TMRA3_OVF = 262u, + INT_TMRA3_UDF = 263u, + INT_TMRA3_CMP = 264u, + INT_TMRA4_OVF = 265u, + INT_TMRA4_UDF = 266u, + INT_TMRA4_CMP = 267u, + INT_TMRA5_OVF = 268u, + INT_TMRA5_UDF = 269u, + INT_TMRA5_CMP = 270u, + INT_TMRA6_OVF = 272u, + INT_TMRA6_UDF = 273u, + INT_TMRA6_CMP = 274u, + + /* USB FS */ + INT_USBFS_GLB = 275u, + + /* USRAT */ + INT_USART1_EI = 278u, + INT_USART1_RI = 279u, + INT_USART1_TI = 280u, + INT_USART1_TCI = 281u, + INT_USART1_RTO = 282u, + INT_USART1_WUPI = 432u, + INT_USART2_EI = 283u, + INT_USART2_RI = 284u, + INT_USART2_TI = 285u, + INT_USART2_TCI = 286u, + INT_USART2_RTO = 287u, + INT_USART3_EI = 288u, + INT_USART3_RI = 289u, + INT_USART3_TI = 290u, + INT_USART3_TCI = 291u, + INT_USART3_RTO = 292u, + INT_USART4_EI = 293u, + INT_USART4_RI = 294u, + INT_USART4_TI = 295u, + INT_USART4_TCI = 296u, + INT_USART4_RTO = 297u, + + /* SPI */ + INT_SPI1_SPRI = 299u, + INT_SPI1_SPTI = 300u, + INT_SPI1_SPII = 301u, + INT_SPI1_SPEI = 302u, + INT_SPI2_SPRI = 304u, + INT_SPI2_SPTI = 305u, + INT_SPI2_SPII = 306u, + INT_SPI2_SPEI = 307u, + INT_SPI3_SPRI = 309u, + INT_SPI3_SPTI = 310u, + INT_SPI3_SPII = 311u, + INT_SPI3_SPEI = 312u, + INT_SPI4_SPRI = 314u, + INT_SPI4_SPTI = 315u, + INT_SPI4_SPII = 316u, + INT_SPI4_SPEI = 317u, + + /* TIMER 4 */ + INT_TMR41_GCMUH = 320u, + INT_TMR41_GCMUL = 321u, + INT_TMR41_GCMVH = 322u, + INT_TMR41_GCMVL = 323u, + INT_TMR41_GCMWH = 324u, + INT_TMR41_GCMWL = 325u, + INT_TMR41_GOVF = 326u, + INT_TMR41_GUDF = 327u, + INT_TMR41_RLOU = 328u, + INT_TMR41_RLOV = 329u, + INT_TMR41_RLOW = 330u, + INT_TMR42_GCMUH = 336u, + INT_TMR42_GCMUL = 337u, + INT_TMR42_GCMVH = 338u, + INT_TMR42_GCMVL = 339u, + INT_TMR42_GCMWH = 340u, + INT_TMR42_GCMWL = 341u, + INT_TMR42_GOVF = 342u, + INT_TMR42_GUDF = 343u, + INT_TMR42_RLOU = 344u, + INT_TMR42_RLOV = 345u, + INT_TMR42_RLOW = 346u, + INT_TMR43_GCMUH = 352u, + INT_TMR43_GCMUL = 353u, + INT_TMR43_GCMVH = 354u, + INT_TMR43_GCMVL = 355u, + INT_TMR43_GCMWH = 356u, + INT_TMR43_GCMWL = 357u, + INT_TMR43_GOVF = 358u, + INT_TMR43_GUDF = 359u, + INT_TMR43_RLOU = 360u, + INT_TMR43_RLOV = 361u, + INT_TMR43_RLOW = 362u, + + /* EMB */ + INT_EMB_GR0 = 390u, + INT_EMB_GR1 = 391u, + INT_EMB_GR2 = 392u, + INT_EMB_GR3 = 393u, + + /* EVENT PORT */ + INT_EVENT_PORT1 = 394u, + INT_EVENT_PORT2 = 395u, + INT_EVENT_PORT3 = 396u, + INT_EVENT_PORT4 = 397u, + + /* I2S */ + INT_I2S1_TXIRQOUT = 400u, + INT_I2S1_RXIRQOUT = 401u, + INT_I2S1_ERRIRQOUT = 402u, + INT_I2S2_TXIRQOUT = 403u, + INT_I2S2_RXIRQOUT = 404u, + INT_I2S2_ERRIRQOUT = 405u, + INT_I2S3_TXIRQOUT = 406u, + INT_I2S3_RXIRQOUT = 407u, + INT_I2S3_ERRIRQOUT = 408u, + INT_I2S4_TXIRQOUT = 409u, + INT_I2S4_RXIRQOUT = 410u, + INT_I2S4_ERRIRQOUT = 411u, + + /* COMPARATOR */ + INT_ACMP1 = 416u, + INT_ACMP2 = 417u, + INT_ACMP3 = 418u, + + /* I2C */ + INT_I2C1_RXI = 420u, + INT_I2C1_TXI = 421u, + INT_I2C1_TEI = 422u, + INT_I2C1_EEI = 423u, + INT_I2C2_RXI = 424u, + INT_I2C2_TXI = 425u, + INT_I2C2_TEI = 426u, + INT_I2C2_EEI = 427u, + INT_I2C3_RXI = 428u, + INT_I2C3_TXI = 429u, + INT_I2C3_TEI = 430u, + INT_I2C3_EEI = 431u, + + /* PVD */ + INT_PVD_PVD1 = 433u, + INT_PVD_PVD2 = 434u, + + /* Temp. sensor */ + INT_OTS = 435u, + + /* FCM */ + INT_FCMFERRI = 436u, + INT_FCMMENDI = 437u, + INT_FCMCOVFI = 438u, + + /* WDT */ + INT_WDT_REFUDF = 439u, + + /* ADC */ + INT_ADC1_EOCA = 448u, + INT_ADC1_EOCB = 449u, + INT_ADC1_CHCMP = 450u, + INT_ADC1_SEQCMP = 451u, + INT_ADC2_EOCA = 452u, + INT_ADC2_EOCB = 453u, + INT_ADC2_CHCMP = 454u, + INT_ADC2_SEQCMP = 455u, + + /* TRNG */ + INT_TRNG_END = 456u, + + /* SDIOC */ + INT_SDIOC1_SD = 482u, + INT_SDIOC2_SD = 485u, + + /* CAN */ + INT_CAN_INT = 486u, + + INT_MAX = 511u, +}en_int_src_t; + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +typedef struct +{ + __IO uint8_t STRT : 1; + uint8_t RESERVED1 : 7; +} stc_adc_str_field_t; + +typedef struct +{ + __IO uint16_t MS : 2; + uint16_t RESERVED2 : 2; + __IO uint16_t ACCSEL : 2; + __IO uint16_t CLREN : 1; + __IO uint16_t DFMT : 1; + __IO uint16_t AVCNT : 3; + uint16_t RESERVED11 : 5; +} stc_adc_cr0_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 2; + __IO uint16_t RSCHSEL : 1; + uint16_t RESERVED3 :13; +} stc_adc_cr1_field_t; + +typedef struct +{ + __IO uint16_t TRGSELA : 3; + uint16_t RESERVED3 : 4; + __IO uint16_t TRGENA : 1; + __IO uint16_t TRGSELB : 3; + uint16_t RESERVED11 : 4; + __IO uint16_t TRGENB : 1; +} stc_adc_trgsr_field_t; + +typedef struct +{ + __IO uint16_t CHSELA16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_chselra1_field_t; + +typedef struct +{ + __IO uint16_t CHSELB16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_chselrb1_field_t; + +typedef struct +{ + __IO uint16_t AVCHSEL16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_avchselr1_field_t; + +typedef struct +{ + __IO uint16_t CH00MUX : 4; + __IO uint16_t CH01MUX : 4; + __IO uint16_t CH02MUX : 4; + __IO uint16_t CH03MUX : 4; +} stc_adc_chmuxr0_field_t; + +typedef struct +{ + __IO uint16_t CH04MUX : 4; + __IO uint16_t CH05MUX : 4; + __IO uint16_t CH06MUX : 4; + __IO uint16_t CH07MUX : 4; +} stc_adc_chmuxr1_field_t; + +typedef struct +{ + __IO uint16_t CH08MUX : 4; + __IO uint16_t CH09MUX : 4; + __IO uint16_t CH10MUX : 4; + __IO uint16_t CH11MUX : 4; +} stc_adc_chmuxr2_field_t; + +typedef struct +{ + __IO uint16_t CH12MUX : 4; + __IO uint16_t CH13MUX : 4; + __IO uint16_t CH14MUX : 4; + __IO uint16_t CH15MUX : 4; +} stc_adc_chmuxr3_field_t; + +typedef struct +{ + __IO uint8_t EOCAF : 1; + __IO uint8_t EOCBF : 1; + uint8_t RESERVED2 : 6; +} stc_adc_isr_field_t; + +typedef struct +{ + __IO uint8_t EOCAIEN : 1; + __IO uint8_t EOCBIEN : 1; + uint8_t RESERVED2 : 6; +} stc_adc_icr_field_t; + +typedef struct +{ + __IO uint16_t SYNCEN : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t SYNCMD : 3; + uint16_t RESERVED7 : 1; + __IO uint16_t SYNCDLY : 8; +} stc_adc_synccr_field_t; + +typedef struct +{ + __IO uint16_t AWDEN : 1; + uint16_t RESERVED1 : 3; + __IO uint16_t AWDMD : 1; + uint16_t RESERVED5 : 1; + __IO uint16_t AWDSS : 2; + __IO uint16_t AWDIEN : 1; + uint16_t RESERVED9 : 7; +} stc_adc_awdcr_field_t; + +typedef struct +{ + __IO uint16_t AWDCH16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_awdchsr1_field_t; + +typedef struct +{ + __IO uint16_t AWDF16 : 1; + uint16_t RESERVED1 :15; +} stc_adc_awdsr1_field_t; + +typedef struct +{ + __IO uint16_t PGACTL : 4; + uint16_t RESERVED4 :12; +} stc_adc_pgacr_field_t; + +typedef struct +{ + __IO uint16_t GAIN : 4; + uint16_t RESERVED4 :12; +} stc_adc_pgagsr_field_t; + +typedef struct +{ + __IO uint16_t PGAINSEL : 9; + uint16_t RESERVED9 : 7; +} stc_adc_pgainsr0_field_t; + +typedef struct +{ + __IO uint16_t PGAVSSEN : 1; + uint16_t RESERVED1 :15; +} stc_adc_pgainsr1_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 1; + uint32_t RESERVED2 :30; +} stc_aes_cr_field_t; + +typedef struct +{ + __IO uint32_t STRG : 1; + uint32_t RESERVED1 :31; +} stc_aos_int_sfttrg_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu1_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu2_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu3_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dcu4_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma1_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma1_trgsel3_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma2_trgsel_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_dma_trgselrc_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmr6_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmr0_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_port_pevnttrgsr12_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_port_pevnttrgsr34_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_tmra_htssr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_ots_trg_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_adc1_itrgselr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :21; + __IO uint32_t COMTRG_EN : 2; +} stc_aos_adc2_itrgselr_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :23; +} stc_aos_comtrg1_field_t; + +typedef struct +{ + __IO uint32_t TRGSEL : 9; + uint32_t RESERVED9 :23; +} stc_aos_comtrg2_field_t; + +typedef struct +{ + __IO uint32_t PDIR00 : 1; + __IO uint32_t PDIR01 : 1; + __IO uint32_t PDIR02 : 1; + __IO uint32_t PDIR03 : 1; + __IO uint32_t PDIR04 : 1; + __IO uint32_t PDIR05 : 1; + __IO uint32_t PDIR06 : 1; + __IO uint32_t PDIR07 : 1; + __IO uint32_t PDIR08 : 1; + __IO uint32_t PDIR09 : 1; + __IO uint32_t PDIR10 : 1; + __IO uint32_t PDIR11 : 1; + __IO uint32_t PDIR12 : 1; + __IO uint32_t PDIR13 : 1; + __IO uint32_t PDIR14 : 1; + __IO uint32_t PDIR15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntdirr_field_t; + +typedef struct +{ + __IO uint32_t PIN00 : 1; + __IO uint32_t PIN01 : 1; + __IO uint32_t PIN02 : 1; + __IO uint32_t PIN03 : 1; + __IO uint32_t PIN04 : 1; + __IO uint32_t PIN05 : 1; + __IO uint32_t PIN06 : 1; + __IO uint32_t PIN07 : 1; + __IO uint32_t PIN08 : 1; + __IO uint32_t PIN09 : 1; + __IO uint32_t PIN10 : 1; + __IO uint32_t PIN11 : 1; + __IO uint32_t PIN12 : 1; + __IO uint32_t PIN13 : 1; + __IO uint32_t PIN14 : 1; + __IO uint32_t PIN15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntidr_field_t; + +typedef struct +{ + __IO uint32_t POUT00 : 1; + __IO uint32_t POUT01 : 1; + __IO uint32_t POUT02 : 1; + __IO uint32_t POUT03 : 1; + __IO uint32_t POUT04 : 1; + __IO uint32_t POUT05 : 1; + __IO uint32_t POUT06 : 1; + __IO uint32_t POUT07 : 1; + __IO uint32_t POUT08 : 1; + __IO uint32_t POUT09 : 1; + __IO uint32_t POUT10 : 1; + __IO uint32_t POUT11 : 1; + __IO uint32_t POUT12 : 1; + __IO uint32_t POUT13 : 1; + __IO uint32_t POUT14 : 1; + __IO uint32_t POUT15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntodr_field_t; + +typedef struct +{ + __IO uint32_t POR00 : 1; + __IO uint32_t POR01 : 1; + __IO uint32_t POR02 : 1; + __IO uint32_t POR03 : 1; + __IO uint32_t POR04 : 1; + __IO uint32_t POR05 : 1; + __IO uint32_t POR06 : 1; + __IO uint32_t POR07 : 1; + __IO uint32_t POR08 : 1; + __IO uint32_t POR09 : 1; + __IO uint32_t POR10 : 1; + __IO uint32_t POR11 : 1; + __IO uint32_t POR12 : 1; + __IO uint32_t POR13 : 1; + __IO uint32_t POR14 : 1; + __IO uint32_t POR15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntorr_field_t; + +typedef struct +{ + __IO uint32_t POS00 : 1; + __IO uint32_t POS01 : 1; + __IO uint32_t POS02 : 1; + __IO uint32_t POS03 : 1; + __IO uint32_t POS04 : 1; + __IO uint32_t POS05 : 1; + __IO uint32_t POS06 : 1; + __IO uint32_t POS07 : 1; + __IO uint32_t POS08 : 1; + __IO uint32_t POS09 : 1; + __IO uint32_t POS10 : 1; + __IO uint32_t POS11 : 1; + __IO uint32_t POS12 : 1; + __IO uint32_t POS13 : 1; + __IO uint32_t POS14 : 1; + __IO uint32_t POS15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntosr_field_t; + +typedef struct +{ + __IO uint32_t RIS00 : 1; + __IO uint32_t RIS01 : 1; + __IO uint32_t RIS02 : 1; + __IO uint32_t RIS03 : 1; + __IO uint32_t RIS04 : 1; + __IO uint32_t RIS05 : 1; + __IO uint32_t RIS06 : 1; + __IO uint32_t RIS07 : 1; + __IO uint32_t RIS08 : 1; + __IO uint32_t RIS09 : 1; + __IO uint32_t RIS10 : 1; + __IO uint32_t RIS11 : 1; + __IO uint32_t RIS12 : 1; + __IO uint32_t RIS13 : 1; + __IO uint32_t RIS14 : 1; + __IO uint32_t RIS15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntrisr_field_t; + +typedef struct +{ + __IO uint32_t FAL00 : 1; + __IO uint32_t FAL01 : 1; + __IO uint32_t FAL02 : 1; + __IO uint32_t FAL03 : 1; + __IO uint32_t FAL04 : 1; + __IO uint32_t FAL05 : 1; + __IO uint32_t FAL06 : 1; + __IO uint32_t FAL07 : 1; + __IO uint32_t FAL08 : 1; + __IO uint32_t FAL09 : 1; + __IO uint32_t FAL10 : 1; + __IO uint32_t FAL11 : 1; + __IO uint32_t FAL12 : 1; + __IO uint32_t FAL13 : 1; + __IO uint32_t FAL14 : 1; + __IO uint32_t FAL15 : 1; + uint32_t RESERVED16 :16; +} stc_aos_pevntfal_field_t; + +typedef struct +{ + __IO uint32_t NFEN1 : 1; + __IO uint32_t DIVS1 : 2; + uint32_t RESERVED3 : 5; + __IO uint32_t NFEN2 : 1; + __IO uint32_t DIVS2 : 2; + uint32_t RESERVED11 : 5; + __IO uint32_t NFEN3 : 1; + __IO uint32_t DIVS3 : 2; + uint32_t RESERVED19 : 5; + __IO uint32_t NFEN4 : 1; + __IO uint32_t DIVS4 : 2; + uint32_t RESERVED27 : 5; +} stc_aos_pevntnfcr_field_t; + +typedef struct +{ + __IO uint8_t BUSOFF : 1; + __IO uint8_t TACTIVE : 1; + __IO uint8_t RACTIVE : 1; + __IO uint8_t TSSS : 1; + __IO uint8_t TPSS : 1; + __IO uint8_t LBMI : 1; + __IO uint8_t LBME : 1; + __IO uint8_t RESET : 1; +} stc_can_cfg_stat_field_t; + +typedef struct +{ + __IO uint8_t TSA : 1; + __IO uint8_t TSALL : 1; + __IO uint8_t TSONE : 1; + __IO uint8_t TPA : 1; + __IO uint8_t TPE : 1; + __IO uint8_t STBY : 1; + __IO uint8_t LOM : 1; + __IO uint8_t TBSEL : 1; +} stc_can_tcmd_field_t; + +typedef struct +{ + __IO uint8_t TSSTAT : 2; + uint8_t RESERVED2 : 2; + __IO uint8_t TTBM : 1; + __IO uint8_t TSMODE : 1; + __IO uint8_t TSNEXT : 1; + uint8_t RESERVED7 : 1; +} stc_can_tctrl_field_t; + +typedef struct +{ + __IO uint8_t RSSTAT : 2; + uint8_t RESERVED2 : 1; + __IO uint8_t RBALL : 1; + __IO uint8_t RREL : 1; + __IO uint8_t ROV : 1; + __IO uint8_t ROM : 1; + __IO uint8_t SACK : 1; +} stc_can_rctrl_field_t; + +typedef struct +{ + __IO uint8_t TSFF : 1; + __IO uint8_t EIE : 1; + __IO uint8_t TSIE : 1; + __IO uint8_t TPIE : 1; + __IO uint8_t RAFIE : 1; + __IO uint8_t RFIE : 1; + __IO uint8_t ROIE : 1; + __IO uint8_t RIE : 1; +} stc_can_rtie_field_t; + +typedef struct +{ + __IO uint8_t AIF : 1; + __IO uint8_t EIF : 1; + __IO uint8_t TSIF : 1; + __IO uint8_t TPIF : 1; + __IO uint8_t RAFIF : 1; + __IO uint8_t RFIF : 1; + __IO uint8_t ROIF : 1; + __IO uint8_t RIF : 1; +} stc_can_rtif_field_t; + +typedef struct +{ + __IO uint8_t BEIF : 1; + __IO uint8_t BEIE : 1; + __IO uint8_t ALIF : 1; + __IO uint8_t ALIE : 1; + __IO uint8_t EPIF : 1; + __IO uint8_t EPIE : 1; + __IO uint8_t EPASS : 1; + __IO uint8_t EWARN : 1; +} stc_can_errint_field_t; + +typedef struct +{ + __IO uint8_t EWL : 4; + __IO uint8_t AFWL : 4; +} stc_can_limit_field_t; + +typedef struct +{ + __IO uint32_t SEG_1 : 8; + __IO uint32_t SEG_2 : 7; + uint32_t RESERVED15 : 1; + __IO uint32_t SJW : 7; + uint32_t RESERVED23 : 1; + __IO uint32_t PRESC : 8; +} stc_can_bt_field_t; + +typedef struct +{ + __IO uint8_t ALC : 5; + __IO uint8_t KOER : 3; +} stc_can_ealcap_field_t; + +typedef struct +{ + __IO uint8_t ACFADR : 4; + uint8_t RESERVED4 : 1; + __IO uint8_t SELMASK : 1; + uint8_t RESERVED6 : 2; +} stc_can_acfctrl_field_t; + +typedef struct +{ + __IO uint8_t AE_1 : 1; + __IO uint8_t AE_2 : 1; + __IO uint8_t AE_3 : 1; + __IO uint8_t AE_4 : 1; + __IO uint8_t AE_5 : 1; + __IO uint8_t AE_6 : 1; + __IO uint8_t AE_7 : 1; + __IO uint8_t AE_8 : 1; +} stc_can_acfen_field_t; + +typedef struct +{ + __IO uint32_t ACODEORAMASK :29; + __IO uint32_t AIDE : 1; + __IO uint32_t AIDEE : 1; + uint32_t RESERVED31 : 1; +} stc_can_acf_field_t; + +typedef struct +{ + __IO uint8_t TBPTR : 6; + __IO uint8_t TBF : 1; + __IO uint8_t TBE : 1; +} stc_can_tbslot_field_t; + +typedef struct +{ + __IO uint8_t TTEN : 1; + __IO uint8_t T_PRESC : 2; + __IO uint8_t TTIF : 1; + __IO uint8_t TTIE : 1; + __IO uint8_t TEIF : 1; + __IO uint8_t WTIF : 1; + __IO uint8_t WTIE : 1; +} stc_can_ttcfg_field_t; + +typedef struct +{ + __IO uint32_t REF_ID :29; + uint32_t RESERVED29 : 2; + __IO uint32_t REF_IDE : 1; +} stc_can_ref_msg_field_t; + +typedef struct +{ + __IO uint16_t TTPTR : 6; + uint16_t RESERVED6 : 2; + __IO uint16_t TTYPE : 3; + uint16_t RESERVED11 : 1; + __IO uint16_t TEW : 4; +} stc_can_trg_cfg_field_t; + +typedef struct +{ + __IO uint16_t FLTSL : 3; + uint16_t RESERVED3 : 2; + __IO uint16_t EDGSL : 2; + __IO uint16_t IEN : 1; + __IO uint16_t CVSEN : 1; + uint16_t RESERVED9 : 3; + __IO uint16_t OUTEN : 1; + __IO uint16_t INV : 1; + __IO uint16_t CMPOE : 1; + __IO uint16_t CMPON : 1; +} stc_cmp_ctrl_field_t; + +typedef struct +{ + __IO uint16_t RVSL : 4; + uint16_t RESERVED4 : 4; + __IO uint16_t CVSL : 4; + __IO uint16_t C4SL : 3; + uint16_t RESERVED15 : 1; +} stc_cmp_vltsel_field_t; + +typedef struct +{ + __IO uint16_t OMON : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t CVST : 4; + uint16_t RESERVED12 : 4; +} stc_cmp_mon_field_t; + +typedef struct +{ + __IO uint16_t STB : 4; + uint16_t RESERVED4 :12; +} stc_cmp_cvsstb_field_t; + +typedef struct +{ + __IO uint16_t PRD : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cvsprd_field_t; + +typedef struct +{ + __IO uint16_t DATA : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cr_dadr1_field_t; + +typedef struct +{ + __IO uint16_t DATA : 8; + uint16_t RESERVED8 : 8; +} stc_cmp_cr_dadr2_field_t; + +typedef struct +{ + __IO uint16_t DA1EN : 1; + __IO uint16_t DA2EN : 1; + uint16_t RESERVED2 :14; +} stc_cmp_cr_dacr_field_t; + +typedef struct +{ + __IO uint16_t DA1SW : 1; + __IO uint16_t DA2SW : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t VREFSW : 1; + uint16_t RESERVED5 : 3; + __IO uint16_t WPRT : 8; +} stc_cmp_cr_rvadc_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t CRC_SEL : 1; + __IO uint32_t REFIN : 1; + __IO uint32_t REFOUT : 1; + __IO uint32_t XOROUT : 1; + uint32_t RESERVED5 :27; +} stc_crc_cr_field_t; + +typedef struct +{ + __IO uint32_t FLAG : 1; + uint32_t RESERVED1 :31; +} stc_crc_flg_field_t; + +typedef struct +{ + __IO uint32_t AUTH : 1; + __IO uint32_t REMVLOCK : 1; + __IO uint32_t SAFTYLOCK1 : 1; + __IO uint32_t SAFTYLOCK2 : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t CPUSTOP : 1; + __IO uint32_t CPUSLEEP : 1; + uint32_t RESERVED10 :22; +} stc_dbgc_mcustat_field_t; + +typedef struct +{ + __IO uint32_t EDBGRQ : 1; + __IO uint32_t RESTART : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t DIRQ : 1; + uint32_t RESERVED9 :23; +} stc_dbgc_mcuctl_field_t; + +typedef struct +{ + __IO uint32_t ERASEREQ : 1; + __IO uint32_t ERASEACK : 1; + __IO uint32_t ERASEERR : 1; + uint32_t RESERVED3 :29; +} stc_dbgc_fmcctl_field_t; + +typedef struct +{ + __IO uint32_t CDBGPWRUPREQ : 1; + __IO uint32_t CDBGPWRUPACK : 1; + uint32_t RESERVED2 :30; +} stc_dbgc_mcudbgstat_field_t; + +typedef struct +{ + __IO uint32_t SWDTSTP : 1; + __IO uint32_t WDTSTP : 1; + __IO uint32_t RTCSTP : 1; + __IO uint32_t PVD0STP : 1; + __IO uint32_t PVD1STP : 1; + __IO uint32_t PVD2STP : 1; + uint32_t RESERVED6 : 8; + __IO uint32_t TMR01STP : 1; + __IO uint32_t TMR02STP : 1; + uint32_t RESERVED16 : 4; + __IO uint32_t TMR41STP : 1; + __IO uint32_t TMR42STP : 1; + __IO uint32_t TMR43STP : 1; + __IO uint32_t TM61STP : 1; + __IO uint32_t TM62STP : 1; + __IO uint32_t TMR63STP : 1; + __IO uint32_t TMRA1STP : 1; + __IO uint32_t TMRA2STP : 1; + __IO uint32_t TMRA3STP : 1; + __IO uint32_t TMRA4STP : 1; + __IO uint32_t TMRA5STP : 1; + __IO uint32_t TMRA6STP : 1; +} stc_dbgc_mcustpctl_field_t; + +typedef struct +{ + __IO uint32_t TRACEMODE : 2; + __IO uint32_t TRACEIOEN : 1; + uint32_t RESERVED3 :29; +} stc_dbgc_mcutracectl_field_t; + +typedef struct +{ + __IO uint32_t MODE : 3; + __IO uint32_t DATASIZE : 2; + uint32_t RESERVED5 : 3; + __IO uint32_t COMP_TRG : 1; + uint32_t RESERVED9 :22; + __IO uint32_t INTEN : 1; +} stc_dcu_ctl_field_t; + +typedef struct +{ + __IO uint32_t FLAG_OP : 1; + __IO uint32_t FLAG_LS2 : 1; + __IO uint32_t FLAG_EQ2 : 1; + __IO uint32_t FLAG_GT2 : 1; + __IO uint32_t FLAG_LS1 : 1; + __IO uint32_t FLAG_EQ1 : 1; + __IO uint32_t FLAG_GT1 : 1; + uint32_t RESERVED7 :25; +} stc_dcu_flag_field_t; + +typedef struct +{ + __IO uint32_t CLR_OP : 1; + __IO uint32_t CLR_LS2 : 1; + __IO uint32_t CLR_EQ2 : 1; + __IO uint32_t CLR_GT2 : 1; + __IO uint32_t CLR_LS1 : 1; + __IO uint32_t CLR_EQ1 : 1; + __IO uint32_t CLR_GT1 : 1; + uint32_t RESERVED7 :25; +} stc_dcu_flagclr_field_t; + +typedef struct +{ + __IO uint32_t INT_OP : 1; + __IO uint32_t INT_LS2 : 1; + __IO uint32_t INT_EQ2 : 1; + __IO uint32_t INT_GT2 : 1; + __IO uint32_t INT_LS1 : 1; + __IO uint32_t INT_EQ1 : 1; + __IO uint32_t INT_GT1 : 1; + __IO uint32_t INT_WIN : 2; + uint32_t RESERVED9 :23; +} stc_dcu_intsel_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + uint32_t RESERVED1 :31; +} stc_dma_en_field_t; + +typedef struct +{ + __IO uint32_t TRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t REQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intstat0_field_t; + +typedef struct +{ + __IO uint32_t TC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t BTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intstat1_field_t; + +typedef struct +{ + __IO uint32_t MSKTRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t MSKREQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intmask0_field_t; + +typedef struct +{ + __IO uint32_t MSKTC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t MSKBTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intmask1_field_t; + +typedef struct +{ + __IO uint32_t CLRTRNERR : 4; + uint32_t RESERVED4 :12; + __IO uint32_t CLRREQERR : 4; + uint32_t RESERVED20 :12; +} stc_dma_intclr0_field_t; + +typedef struct +{ + __IO uint32_t CLRTC : 4; + uint32_t RESERVED4 :12; + __IO uint32_t CLRBTC : 4; + uint32_t RESERVED20 :12; +} stc_dma_intclr1_field_t; + +typedef struct +{ + __IO uint32_t CHEN : 4; + uint32_t RESERVED4 :28; +} stc_dma_chen_field_t; + +typedef struct +{ + __IO uint32_t DMAACT : 1; + __IO uint32_t RCFGACT : 1; + uint32_t RESERVED2 :14; + __IO uint32_t CHACT : 4; + uint32_t RESERVED20 :12; +} stc_dma_chstat_field_t; + +typedef struct +{ + __IO uint32_t RCFGEN : 1; + __IO uint32_t RCFGLLP : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t RCFGCHS : 4; + uint32_t RESERVED12 : 4; + __IO uint32_t SARMD : 2; + __IO uint32_t DARMD : 2; + __IO uint32_t CNTMD : 2; + uint32_t RESERVED22 :10; +} stc_dma_rcfgctl_field_t; + +typedef struct +{ + __IO uint32_t BLKSIZE :10; + uint32_t RESERVED10 : 6; + __IO uint32_t CNT :16; +} stc_dma_dtctl_field_t; + +typedef struct +{ + __IO uint32_t SRPT :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPT :10; + uint32_t RESERVED26 : 6; +} stc_dma_rpt_field_t; + +typedef struct +{ + __IO uint32_t SRPTB :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPTB :10; + uint32_t RESERVED26 : 6; +} stc_dma_rptb_field_t; + +typedef struct +{ + __IO uint32_t SOFFSET :20; + __IO uint32_t SNSCNT :12; +} stc_dma_snseqctl_field_t; + +typedef struct +{ + __IO uint32_t SNSDIST :20; + __IO uint32_t SNSCNTB :12; +} stc_dma_snseqctlb_field_t; + +typedef struct +{ + __IO uint32_t DOFFSET :20; + __IO uint32_t DNSCNT :12; +} stc_dma_dnseqctl_field_t; + +typedef struct +{ + __IO uint32_t DNSDIST :20; + __IO uint32_t DNSCNTB :12; +} stc_dma_dnseqctlb_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t LLP :30; +} stc_dma_llp_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch0ctl_field_t; + +typedef struct +{ + __IO uint32_t BLKSIZE :10; + uint32_t RESERVED10 : 6; + __IO uint32_t CNT :16; +} stc_dma_mondtctl_field_t; + +typedef struct +{ + __IO uint32_t SRPT :10; + uint32_t RESERVED10 : 6; + __IO uint32_t DRPT :10; + uint32_t RESERVED26 : 6; +} stc_dma_monrpt_field_t; + +typedef struct +{ + __IO uint32_t SOFFSET :20; + __IO uint32_t SNSCNT :12; +} stc_dma_monsnseqctl_field_t; + +typedef struct +{ + __IO uint32_t DOFFSET :20; + __IO uint32_t DNSCNT :12; +} stc_dma_mondnseqctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch1ctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch2ctl_field_t; + +typedef struct +{ + __IO uint32_t SINC : 2; + __IO uint32_t DINC : 2; + __IO uint32_t SRPTEN : 1; + __IO uint32_t DRPTEN : 1; + __IO uint32_t SNSEQEN : 1; + __IO uint32_t DNSEQEN : 1; + __IO uint32_t HSIZE : 2; + __IO uint32_t LLPEN : 1; + __IO uint32_t LLPRUN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED13 :19; +} stc_dma_ch3ctl_field_t; + +typedef struct +{ + __IO uint32_t FAPRT :16; + uint32_t RESERVED16 :16; +} stc_efm_faprt_field_t; + +typedef struct +{ + __IO uint32_t FSTP : 1; + uint32_t RESERVED1 :31; +} stc_efm_fstp_field_t; + +typedef struct +{ + __IO uint32_t SLPMD : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t FLWT : 4; + __IO uint32_t LVM : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t CACHE : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t CRST : 1; + uint32_t RESERVED25 : 7; +} stc_efm_frmc_field_t; + +typedef struct +{ + __IO uint32_t PEMODE : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t PEMOD : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t BUSHLDCTL : 1; + uint32_t RESERVED9 :23; +} stc_efm_fwmc_field_t; + +typedef struct +{ + __IO uint32_t PEWERR : 1; + __IO uint32_t PEPRTERR : 1; + __IO uint32_t PGSZERR : 1; + __IO uint32_t PGMISMTCH : 1; + __IO uint32_t OPTEND : 1; + __IO uint32_t COLERR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t RDY : 1; + uint32_t RESERVED9 :23; +} stc_efm_fsr_field_t; + +typedef struct +{ + __IO uint32_t PEWERRCLR : 1; + __IO uint32_t PEPRTERRCLR : 1; + __IO uint32_t PGSZERRCLR : 1; + __IO uint32_t PGMISMTCHCLR : 1; + __IO uint32_t OPTENDCLR : 1; + __IO uint32_t COLERRCLR : 1; + uint32_t RESERVED6 :26; +} stc_efm_fsclr_field_t; + +typedef struct +{ + __IO uint32_t PEERRITE : 1; + __IO uint32_t OPTENDITE : 1; + __IO uint32_t COLERRITE : 1; + uint32_t RESERVED3 :29; +} stc_efm_fite_field_t; + +typedef struct +{ + __IO uint32_t FSWP : 1; + uint32_t RESERVED1 :31; +} stc_efm_fswp_field_t; + +typedef struct +{ + __IO uint32_t FPMTSW :19; + uint32_t RESERVED19 :13; +} stc_efm_fpmtsw_field_t; + +typedef struct +{ + __IO uint32_t FPMTEW :19; + uint32_t RESERVED19 :13; +} stc_efm_fpmtew_field_t; + +typedef struct +{ + __IO uint32_t REMPRT :16; + uint32_t RESERVED16 :16; +} stc_efm_mmf_remprt_field_t; + +typedef struct +{ + __IO uint32_t RM0SIZE : 5; + uint32_t RESERVED5 : 7; + __IO uint32_t RM0TADDR :17; + uint32_t RESERVED29 : 2; + __IO uint32_t EN0 : 1; +} stc_efm_mmf_remcr0_field_t; + +typedef struct +{ + __IO uint32_t RM1SIZE : 5; + uint32_t RESERVED5 : 7; + __IO uint32_t RM1TADDR :17; + uint32_t RESERVED29 : 2; + __IO uint32_t EN1 : 1; +} stc_efm_mmf_remcr1_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t FRANDS :14; + uint32_t RESERVED15 : 1; + __IO uint32_t FRANDFG : 1; + uint32_t RESERVED17 :15; +} stc_efm_efm_frands_field_t; + +typedef struct +{ + __IO uint32_t PORTINEN : 1; + __IO uint32_t CMPEN : 3; + uint32_t RESERVED4 : 1; + __IO uint32_t OSCSTPEN : 1; + __IO uint32_t PWMSEN : 3; + uint32_t RESERVED9 :19; + __IO uint32_t NFSEL : 2; + __IO uint32_t NFEN : 1; + __IO uint32_t INVSEL : 1; +} stc_emb_ctl_field_t; + +typedef struct +{ + __IO uint32_t PWMLV : 3; + uint32_t RESERVED3 :29; +} stc_emb_pwmlv_field_t; + +typedef struct +{ + __IO uint32_t SOE : 1; + uint32_t RESERVED1 :31; +} stc_emb_soe_field_t; + +typedef struct +{ + __IO uint32_t PORTINF : 1; + __IO uint32_t PWMSF : 1; + __IO uint32_t CMPF : 1; + __IO uint32_t OSF : 1; + __IO uint32_t PORTINST : 1; + __IO uint32_t PWMST : 1; + uint32_t RESERVED6 :26; +} stc_emb_stat_field_t; + +typedef struct +{ + __IO uint32_t PORTINFCLR : 1; + __IO uint32_t PWMSFCLR : 1; + __IO uint32_t CMPFCLR : 1; + __IO uint32_t OSFCLR : 1; + uint32_t RESERVED4 :28; +} stc_emb_statclr_field_t; + +typedef struct +{ + __IO uint32_t PORTINTEN : 1; + __IO uint32_t PWMINTEN : 1; + __IO uint32_t CMPINTEN : 1; + __IO uint32_t OSINTEN : 1; + uint32_t RESERVED4 :28; +} stc_emb_inten_field_t; + +typedef struct +{ + __IO uint32_t LVR :16; + uint32_t RESERVED16 :16; +} stc_fcm_lvr_field_t; + +typedef struct +{ + __IO uint32_t UVR :16; + uint32_t RESERVED16 :16; +} stc_fcm_uvr_field_t; + +typedef struct +{ + __IO uint32_t CNTR :16; + uint32_t RESERVED16 :16; +} stc_fcm_cntr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :31; +} stc_fcm_str_field_t; + +typedef struct +{ + __IO uint32_t MDIVS : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t MCKS : 4; + uint32_t RESERVED8 :24; +} stc_fcm_mccr_field_t; + +typedef struct +{ + __IO uint32_t RDIVS : 2; + uint32_t RESERVED2 : 1; + __IO uint32_t RCKS : 4; + __IO uint32_t INEXS : 1; + __IO uint32_t DNFS : 2; + uint32_t RESERVED10 : 2; + __IO uint32_t EDGES : 2; + uint32_t RESERVED14 : 1; + __IO uint32_t EXREFE : 1; + uint32_t RESERVED16 :16; +} stc_fcm_rccr_field_t; + +typedef struct +{ + __IO uint32_t ERRIE : 1; + __IO uint32_t MENDIE : 1; + __IO uint32_t OVFIE : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t ERRINTRS : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ERRE : 1; + uint32_t RESERVED8 :24; +} stc_fcm_rier_field_t; + +typedef struct +{ + __IO uint32_t ERRF : 1; + __IO uint32_t MENDF : 1; + __IO uint32_t OVF : 1; + uint32_t RESERVED3 :29; +} stc_fcm_sr_field_t; + +typedef struct +{ + __IO uint32_t ERRFCLR : 1; + __IO uint32_t MENDFCLR : 1; + __IO uint32_t OVFCLR : 1; + uint32_t RESERVED3 :29; +} stc_fcm_clr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t FST_GRP : 1; + uint32_t RESERVED2 :30; +} stc_hash_cr_field_t; + +typedef struct +{ + __IO uint32_t PE : 1; + __IO uint32_t SMBUS : 1; + __IO uint32_t SMBALRTEN : 1; + __IO uint32_t SMBDEFAULTEN : 1; + __IO uint32_t SMBHOSTEN : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t ENGC : 1; + __IO uint32_t RESTART : 1; + __IO uint32_t START : 1; + __IO uint32_t STOP : 1; + __IO uint32_t ACK : 1; + uint32_t RESERVED11 : 4; + __IO uint32_t SWRST : 1; + uint32_t RESERVED16 :16; +} stc_i2c_cr1_field_t; + +typedef struct +{ + __IO uint32_t STARTIE : 1; + __IO uint32_t SLADDR0IE : 1; + __IO uint32_t SLADDR1IE : 1; + __IO uint32_t TENDIE : 1; + __IO uint32_t STOPIE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLIE : 1; + __IO uint32_t TEMPTYIE : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOIE : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NACKIE : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTIE : 1; + uint32_t RESERVED15 : 5; + __IO uint32_t GENCALLIE : 1; + __IO uint32_t SMBDEFAULTIE : 1; + __IO uint32_t SMBHOSTIE : 1; + __IO uint32_t SMBALRTIE : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_cr2_field_t; + +typedef struct +{ + __IO uint32_t TMOUTEN : 1; + __IO uint32_t LTMOUT : 1; + __IO uint32_t HTMOUT : 1; + uint32_t RESERVED3 : 4; + __IO uint32_t FACKEN : 1; + uint32_t RESERVED8 :24; +} stc_i2c_cr3_field_t; + +typedef struct +{ + __IO uint32_t SLADDR0 :10; + uint32_t RESERVED10 : 2; + __IO uint32_t SLADDR0EN : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t ADDRMOD0 : 1; + uint32_t RESERVED16 :16; +} stc_i2c_slr0_field_t; + +typedef struct +{ + __IO uint32_t SLADDR1 :10; + uint32_t RESERVED10 : 2; + __IO uint32_t SLADDR1EN : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t ADDRMOD1 : 1; + uint32_t RESERVED16 :16; +} stc_i2c_slr1_field_t; + +typedef struct +{ + __IO uint32_t TOUTLOW :16; + __IO uint32_t TOUTHIGH :16; +} stc_i2c_sltr_field_t; + +typedef struct +{ + __IO uint32_t STARTF : 1; + __IO uint32_t SLADDR0F : 1; + __IO uint32_t SLADDR1F : 1; + __IO uint32_t TENDF : 1; + __IO uint32_t STOPF : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLF : 1; + __IO uint32_t TEMPTYF : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOF : 1; + __IO uint32_t ACKRF : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t NACKF : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTF : 1; + uint32_t RESERVED15 : 1; + __IO uint32_t MSL : 1; + __IO uint32_t BUSY : 1; + __IO uint32_t TRA : 1; + uint32_t RESERVED19 : 1; + __IO uint32_t GENCALLF : 1; + __IO uint32_t SMBDEFAULTF : 1; + __IO uint32_t SMBHOSTF : 1; + __IO uint32_t SMBALRTF : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_sr_field_t; + +typedef struct +{ + __IO uint32_t STARTFCLR : 1; + __IO uint32_t SLADDR0FCLR : 1; + __IO uint32_t SLADDR1FCLR : 1; + __IO uint32_t TENDFCLR : 1; + __IO uint32_t STOPFCLR : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t RFULLFCLR : 1; + __IO uint32_t TEMPTYFCLR : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t ARLOFCLR : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NACKFCLR : 1; + uint32_t RESERVED13 : 1; + __IO uint32_t TMOUTFCLR : 1; + uint32_t RESERVED15 : 5; + __IO uint32_t GENCALLFCLR : 1; + __IO uint32_t SMBDEFAULTFCLR : 1; + __IO uint32_t SMBHOSTFCLR : 1; + __IO uint32_t SMBALRTFCLR : 1; + uint32_t RESERVED24 : 8; +} stc_i2c_clr_field_t; + +typedef struct +{ + __IO uint8_t DT : 8; +} stc_i2c_dtr_field_t; + +typedef struct +{ + __IO uint8_t DR : 8; +} stc_i2c_drr_field_t; + +typedef struct +{ + __IO uint32_t SLOWW : 5; + uint32_t RESERVED5 : 3; + __IO uint32_t SHIGHW : 5; + uint32_t RESERVED13 : 3; + __IO uint32_t FREQ : 3; + uint32_t RESERVED19 :13; +} stc_i2c_ccr_field_t; + +typedef struct +{ + __IO uint32_t DNF : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t DNFEN : 1; + __IO uint32_t ANFEN : 1; + uint32_t RESERVED6 :26; +} stc_i2c_fltr_field_t; + +typedef struct +{ + __IO uint32_t TXE : 1; + __IO uint32_t TXIE : 1; + __IO uint32_t RXE : 1; + __IO uint32_t RXIE : 1; + __IO uint32_t EIE : 1; + __IO uint32_t WMS : 1; + __IO uint32_t ODD : 1; + __IO uint32_t MCKOE : 1; + __IO uint32_t TXBIRQWL : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t RXBIRQWL : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t FIFOR : 1; + __IO uint32_t CODECRC : 1; + __IO uint32_t I2SPLLSEL : 1; + __IO uint32_t SDOE : 1; + __IO uint32_t LRCKOE : 1; + __IO uint32_t CKOE : 1; + __IO uint32_t DUPLEX : 1; + __IO uint32_t CLKSEL : 1; + uint32_t RESERVED24 : 8; +} stc_i2s_ctrl_field_t; + +typedef struct +{ + __IO uint32_t TXBA : 1; + __IO uint32_t RXBA : 1; + __IO uint32_t TXBE : 1; + __IO uint32_t TXBF : 1; + __IO uint32_t RXBE : 1; + __IO uint32_t RXBF : 1; + uint32_t RESERVED6 :26; +} stc_i2s_sr_field_t; + +typedef struct +{ + __IO uint32_t TXERR : 1; + __IO uint32_t RXERR : 1; + uint32_t RESERVED2 :30; +} stc_i2s_er_field_t; + +typedef struct +{ + __IO uint32_t I2SSTD : 2; + __IO uint32_t DATLEN : 2; + __IO uint32_t CHLEN : 1; + __IO uint32_t PCMSYNC : 1; + uint32_t RESERVED6 :26; +} stc_i2s_cfgr_field_t; + +typedef struct +{ + __IO uint32_t I2SDIV : 8; + uint32_t RESERVED8 :24; +} stc_i2s_pr_field_t; + +typedef struct +{ + __IO uint32_t SWDTAUTS : 1; + __IO uint32_t SWDTITS : 1; + __IO uint32_t SWDTPERI : 2; + __IO uint32_t SWDTCKS : 4; + __IO uint32_t SWDTWDPT : 4; + __IO uint32_t SWDTSLPOFF : 1; + uint32_t RESERVED13 : 3; + __IO uint32_t WDTAUTS : 1; + __IO uint32_t WDTITS : 1; + __IO uint32_t WDTPERI : 2; + __IO uint32_t WDTCKS : 4; + __IO uint32_t WDTWDPT : 4; + __IO uint32_t WDTSLPOFF : 1; + uint32_t RESERVED29 : 3; +} stc_icg_icg0_field_t; + +typedef struct +{ + __IO uint32_t HRCFREQSEL : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t HRCSTOP : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t BOR_LEV : 2; + __IO uint32_t BORDIS : 1; + uint32_t RESERVED19 : 7; + __IO uint32_t SMPCLK : 2; + __IO uint32_t NMITRG : 1; + __IO uint32_t NMIENR : 1; + __IO uint32_t NFEN : 1; + __IO uint32_t NMIICGENA : 1; +} stc_icg_icg1_field_t; + +typedef struct +{ + __IO uint32_t NMITRG : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t NSMPCLK : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t NFEN : 1; + uint32_t RESERVED8 :24; +} stc_intc_nmicr_field_t; + +typedef struct +{ + __IO uint32_t NMIENR : 1; + __IO uint32_t SWDTENR : 1; + __IO uint32_t PVD1ENR : 1; + __IO uint32_t PVD2ENR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPENR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPENR : 1; + __IO uint32_t RECCENR : 1; + __IO uint32_t BUSMENR : 1; + __IO uint32_t WDTENR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmienr_field_t; + +typedef struct +{ + __IO uint32_t NMIFR : 1; + __IO uint32_t SWDTFR : 1; + __IO uint32_t PVD1FR : 1; + __IO uint32_t PVD2FR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPFR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPFR : 1; + __IO uint32_t RECCFR : 1; + __IO uint32_t BUSMFR : 1; + __IO uint32_t WDTFR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmifr_field_t; + +typedef struct +{ + __IO uint32_t NMICFR : 1; + __IO uint32_t SWDTCFR : 1; + __IO uint32_t PVD1CFR : 1; + __IO uint32_t PVD2CFR : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t XTALSTPCFR : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t REPCFR : 1; + __IO uint32_t RECCCFR : 1; + __IO uint32_t BUSMCFR : 1; + __IO uint32_t WDTCFR : 1; + uint32_t RESERVED12 :20; +} stc_intc_nmicfr_field_t; + +typedef struct +{ + __IO uint32_t EIRQTRG : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t EISMPCLK : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t EFEN : 1; + uint32_t RESERVED8 :24; +} stc_intc_eirqcr_field_t; + +typedef struct +{ + __IO uint32_t EIRQWUEN :16; + __IO uint32_t SWDTWUEN : 1; + __IO uint32_t PVD1WUEN : 1; + __IO uint32_t PVD2WUEN : 1; + __IO uint32_t CMPI0WUEN : 1; + __IO uint32_t WKTMWUEN : 1; + __IO uint32_t RTCALMWUEN : 1; + __IO uint32_t RTCPRDWUEN : 1; + __IO uint32_t TMR0WUEN : 1; + uint32_t RESERVED24 : 1; + __IO uint32_t RXWUEN : 1; + uint32_t RESERVED26 : 6; +} stc_intc_wupen_field_t; + +typedef struct +{ + __IO uint32_t EIFR0 : 1; + __IO uint32_t EIFR1 : 1; + __IO uint32_t EIFR2 : 1; + __IO uint32_t EIFR3 : 1; + __IO uint32_t EIFR4 : 1; + __IO uint32_t EIFR5 : 1; + __IO uint32_t EIFR6 : 1; + __IO uint32_t EIFR7 : 1; + __IO uint32_t EIFR8 : 1; + __IO uint32_t EIFR9 : 1; + __IO uint32_t EIFR10 : 1; + __IO uint32_t EIFR11 : 1; + __IO uint32_t EIFR12 : 1; + __IO uint32_t EIFR13 : 1; + __IO uint32_t EIFR14 : 1; + __IO uint32_t EIFR15 : 1; + uint32_t RESERVED16 :16; +} stc_intc_eifr_field_t; + +typedef struct +{ + __IO uint32_t EICFR0 : 1; + __IO uint32_t EICFR1 : 1; + __IO uint32_t EICFR2 : 1; + __IO uint32_t EICFR3 : 1; + __IO uint32_t EICFR4 : 1; + __IO uint32_t EICFR5 : 1; + __IO uint32_t EICFR6 : 1; + __IO uint32_t EICFR7 : 1; + __IO uint32_t EICFR8 : 1; + __IO uint32_t EICFR9 : 1; + __IO uint32_t EICFR10 : 1; + __IO uint32_t EICFR11 : 1; + __IO uint32_t EICFR12 : 1; + __IO uint32_t EICFR13 : 1; + __IO uint32_t EICFR14 : 1; + __IO uint32_t EICFR15 : 1; + uint32_t RESERVED16 :16; +} stc_intc_eicfr_field_t; + +typedef struct +{ + __IO uint32_t INTSEL : 9; + uint32_t RESERVED9 :23; +} stc_intc_sel_field_t; + +typedef struct +{ + __IO uint32_t VSEL0 : 1; + __IO uint32_t VSEL1 : 1; + __IO uint32_t VSEL2 : 1; + __IO uint32_t VSEL3 : 1; + __IO uint32_t VSEL4 : 1; + __IO uint32_t VSEL5 : 1; + __IO uint32_t VSEL6 : 1; + __IO uint32_t VSEL7 : 1; + __IO uint32_t VSEL8 : 1; + __IO uint32_t VSEL9 : 1; + __IO uint32_t VSEL10 : 1; + __IO uint32_t VSEL11 : 1; + __IO uint32_t VSEL12 : 1; + __IO uint32_t VSEL13 : 1; + __IO uint32_t VSEL14 : 1; + __IO uint32_t VSEL15 : 1; + __IO uint32_t VSEL16 : 1; + __IO uint32_t VSEL17 : 1; + __IO uint32_t VSEL18 : 1; + __IO uint32_t VSEL19 : 1; + __IO uint32_t VSEL20 : 1; + __IO uint32_t VSEL21 : 1; + __IO uint32_t VSEL22 : 1; + __IO uint32_t VSEL23 : 1; + __IO uint32_t VSEL24 : 1; + __IO uint32_t VSEL25 : 1; + __IO uint32_t VSEL26 : 1; + __IO uint32_t VSEL27 : 1; + __IO uint32_t VSEL28 : 1; + __IO uint32_t VSEL29 : 1; + __IO uint32_t VSEL30 : 1; + __IO uint32_t VSEL31 : 1; +} stc_intc_vssel_field_t; + +typedef struct +{ + __IO uint32_t SWIE0 : 1; + __IO uint32_t SWIE1 : 1; + __IO uint32_t SWIE2 : 1; + __IO uint32_t SWIE3 : 1; + __IO uint32_t SWIE4 : 1; + __IO uint32_t SWIE5 : 1; + __IO uint32_t SWIE6 : 1; + __IO uint32_t SWIE7 : 1; + __IO uint32_t SWIE8 : 1; + __IO uint32_t SWIE9 : 1; + __IO uint32_t SWIE10 : 1; + __IO uint32_t SWIE11 : 1; + __IO uint32_t SWIE12 : 1; + __IO uint32_t SWIE13 : 1; + __IO uint32_t SWIE14 : 1; + __IO uint32_t SWIE15 : 1; + __IO uint32_t SWIE16 : 1; + __IO uint32_t SWIE17 : 1; + __IO uint32_t SWIE18 : 1; + __IO uint32_t SWIE19 : 1; + __IO uint32_t SWIE20 : 1; + __IO uint32_t SWIE21 : 1; + __IO uint32_t SWIE22 : 1; + __IO uint32_t SWIE23 : 1; + __IO uint32_t SWIE24 : 1; + __IO uint32_t SWIE25 : 1; + __IO uint32_t SWIE26 : 1; + __IO uint32_t SWIE27 : 1; + __IO uint32_t SWIE28 : 1; + __IO uint32_t SWIE29 : 1; + __IO uint32_t SWIE30 : 1; + __IO uint32_t SWIE31 : 1; +} stc_intc_swier_field_t; + +typedef struct +{ + __IO uint32_t EVTE0 : 1; + __IO uint32_t EVTE1 : 1; + __IO uint32_t EVTE2 : 1; + __IO uint32_t EVTE3 : 1; + __IO uint32_t EVTE4 : 1; + __IO uint32_t EVTE5 : 1; + __IO uint32_t EVTE6 : 1; + __IO uint32_t EVTE7 : 1; + __IO uint32_t EVTE8 : 1; + __IO uint32_t EVTE9 : 1; + __IO uint32_t EVTE10 : 1; + __IO uint32_t EVTE11 : 1; + __IO uint32_t EVTE12 : 1; + __IO uint32_t EVTE13 : 1; + __IO uint32_t EVTE14 : 1; + __IO uint32_t EVTE15 : 1; + __IO uint32_t EVTE16 : 1; + __IO uint32_t EVTE17 : 1; + __IO uint32_t EVTE18 : 1; + __IO uint32_t EVTE19 : 1; + __IO uint32_t EVTE20 : 1; + __IO uint32_t EVTE21 : 1; + __IO uint32_t EVTE22 : 1; + __IO uint32_t EVTE23 : 1; + __IO uint32_t EVTE24 : 1; + __IO uint32_t EVTE25 : 1; + __IO uint32_t EVTE26 : 1; + __IO uint32_t EVTE27 : 1; + __IO uint32_t EVTE28 : 1; + __IO uint32_t EVTE29 : 1; + __IO uint32_t EVTE30 : 1; + __IO uint32_t EVTE31 : 1; +} stc_intc_evter_field_t; + +typedef struct +{ + __IO uint32_t IER0 : 1; + __IO uint32_t IER1 : 1; + __IO uint32_t IER2 : 1; + __IO uint32_t IER3 : 1; + __IO uint32_t IER4 : 1; + __IO uint32_t IER5 : 1; + __IO uint32_t IER6 : 1; + __IO uint32_t IER7 : 1; + __IO uint32_t IER8 : 1; + __IO uint32_t IER9 : 1; + __IO uint32_t IER10 : 1; + __IO uint32_t IER11 : 1; + __IO uint32_t IER12 : 1; + __IO uint32_t IER13 : 1; + __IO uint32_t IER14 : 1; + __IO uint32_t IER15 : 1; + __IO uint32_t IER16 : 1; + __IO uint32_t IER17 : 1; + __IO uint32_t IER18 : 1; + __IO uint32_t IER19 : 1; + __IO uint32_t IER20 : 1; + __IO uint32_t IER21 : 1; + __IO uint32_t IER22 : 1; + __IO uint32_t IER23 : 1; + __IO uint32_t IER24 : 1; + __IO uint32_t IER25 : 1; + __IO uint32_t IER26 : 1; + __IO uint32_t IER27 : 1; + __IO uint32_t IER28 : 1; + __IO uint32_t IER29 : 1; + __IO uint32_t IER30 : 1; + __IO uint32_t IER31 : 1; +} stc_intc_ier_field_t; + +typedef struct +{ + __IO uint32_t KEYINSEL :16; + __IO uint32_t KEYOUTSEL : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t CKSEL : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t T_LLEVEL : 5; + __IO uint32_t T_HIZ : 3; +} stc_keyscan_scr_field_t; + +typedef struct +{ + __IO uint32_t SEN : 1; + uint32_t RESERVED1 :31; +} stc_keyscan_ser_field_t; + +typedef struct +{ + __IO uint32_t INDEX : 3; + uint32_t RESERVED3 :29; +} stc_keyscan_ssr_field_t; + +typedef struct +{ + __IO uint32_t MPURG0SIZE : 5; + __IO uint32_t MPURG0ADDR :27; +} stc_mpu_rgd0_field_t; + +typedef struct +{ + __IO uint32_t MPURG1SIZE : 5; + __IO uint32_t MPURG1ADDR :27; +} stc_mpu_rgd1_field_t; + +typedef struct +{ + __IO uint32_t MPURG2SIZE : 5; + __IO uint32_t MPURG2ADDR :27; +} stc_mpu_rgd2_field_t; + +typedef struct +{ + __IO uint32_t MPURG3SIZE : 5; + __IO uint32_t MPURG3ADDR :27; +} stc_mpu_rgd3_field_t; + +typedef struct +{ + __IO uint32_t MPURG4SIZE : 5; + __IO uint32_t MPURG4ADDR :27; +} stc_mpu_rgd4_field_t; + +typedef struct +{ + __IO uint32_t MPURG5SIZE : 5; + __IO uint32_t MPURG5ADDR :27; +} stc_mpu_rgd5_field_t; + +typedef struct +{ + __IO uint32_t MPURG6SIZE : 5; + __IO uint32_t MPURG6ADDR :27; +} stc_mpu_rgd6_field_t; + +typedef struct +{ + __IO uint32_t MPURG7SIZE : 5; + __IO uint32_t MPURG7ADDR :27; +} stc_mpu_rgd7_field_t; + +typedef struct +{ + __IO uint32_t MPURG8SIZE : 5; + __IO uint32_t MPURG8ADDR :27; +} stc_mpu_rgd8_field_t; + +typedef struct +{ + __IO uint32_t MPURG9SIZE : 5; + __IO uint32_t MPURG9ADDR :27; +} stc_mpu_rgd9_field_t; + +typedef struct +{ + __IO uint32_t MPURG10SIZE : 5; + __IO uint32_t MPURG10ADDR :27; +} stc_mpu_rgd10_field_t; + +typedef struct +{ + __IO uint32_t MPURG11SIZE : 5; + __IO uint32_t MPURG11ADDR :27; +} stc_mpu_rgd11_field_t; + +typedef struct +{ + __IO uint32_t MPURG12SIZE : 5; + __IO uint32_t MPURG12ADDR :27; +} stc_mpu_rgd12_field_t; + +typedef struct +{ + __IO uint32_t MPURG13SIZE : 5; + __IO uint32_t MPURG13ADDR :27; +} stc_mpu_rgd13_field_t; + +typedef struct +{ + __IO uint32_t MPURG14SIZE : 5; + __IO uint32_t MPURG14ADDR :27; +} stc_mpu_rgd14_field_t; + +typedef struct +{ + __IO uint32_t MPURG15SIZE : 5; + __IO uint32_t MPURG15ADDR :27; +} stc_mpu_rgd15_field_t; + +typedef struct +{ + __IO uint32_t S2RG0RP : 1; + __IO uint32_t S2RG0WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG0E : 1; + __IO uint32_t S1RG0RP : 1; + __IO uint32_t S1RG0WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG0E : 1; + __IO uint32_t FRG0RP : 1; + __IO uint32_t FRG0WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG0E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr0_field_t; + +typedef struct +{ + __IO uint32_t S2RG1RP : 1; + __IO uint32_t S2RG1WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG1E : 1; + __IO uint32_t S1RG1RP : 1; + __IO uint32_t S1RG1WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG1E : 1; + __IO uint32_t FRG1RP : 1; + __IO uint32_t FRG1WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG1E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr1_field_t; + +typedef struct +{ + __IO uint32_t S2RG2RP : 1; + __IO uint32_t S2RG2WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG2E : 1; + __IO uint32_t S1RG2RP : 1; + __IO uint32_t S1RG2WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG2E : 1; + __IO uint32_t FRG2RP : 1; + __IO uint32_t FRG2WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG2E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr2_field_t; + +typedef struct +{ + __IO uint32_t S2RG3RP : 1; + __IO uint32_t S2RG3WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG3E : 1; + __IO uint32_t S1RG3RP : 1; + __IO uint32_t S1RG3WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG3E : 1; + __IO uint32_t FRG3RP : 1; + __IO uint32_t FRG3WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG3E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr3_field_t; + +typedef struct +{ + __IO uint32_t S2RG4RP : 1; + __IO uint32_t S2RG4WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG4E : 1; + __IO uint32_t S1RG4RP : 1; + __IO uint32_t S1RG4WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG4E : 1; + __IO uint32_t FRG4RP : 1; + __IO uint32_t FRG4WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG4E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr4_field_t; + +typedef struct +{ + __IO uint32_t S2RG5RP : 1; + __IO uint32_t S2RG5WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG5E : 1; + __IO uint32_t S1RG5RP : 1; + __IO uint32_t S1RG5WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG5E : 1; + __IO uint32_t FRG5RP : 1; + __IO uint32_t FRG5WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG5E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr5_field_t; + +typedef struct +{ + __IO uint32_t S2RG6RP : 1; + __IO uint32_t S2RG6WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG6E : 1; + __IO uint32_t S1RG6RP : 1; + __IO uint32_t S1RG6WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG6E : 1; + __IO uint32_t FRG6RP : 1; + __IO uint32_t FRG6WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG6E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr6_field_t; + +typedef struct +{ + __IO uint32_t S2RG7RP : 1; + __IO uint32_t S2RG7WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG7E : 1; + __IO uint32_t S1RG7RP : 1; + __IO uint32_t S1RG7WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG7E : 1; + __IO uint32_t FRG7RP : 1; + __IO uint32_t FRG7WP : 1; + uint32_t RESERVED18 : 5; + __IO uint32_t FRG7E : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_rgcr7_field_t; + +typedef struct +{ + __IO uint32_t S2RG8RP : 1; + __IO uint32_t S2RG8WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG8E : 1; + __IO uint32_t S1RG8RP : 1; + __IO uint32_t S1RG8WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG8E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr8_field_t; + +typedef struct +{ + __IO uint32_t S2RG9RP : 1; + __IO uint32_t S2RG9WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG9E : 1; + __IO uint32_t S1RG9RP : 1; + __IO uint32_t S1RG9WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG9E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr9_field_t; + +typedef struct +{ + __IO uint32_t S2RG10RP : 1; + __IO uint32_t S2RG10WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG10E : 1; + __IO uint32_t S1RG10RP : 1; + __IO uint32_t S1RG10WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG10E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr10_field_t; + +typedef struct +{ + __IO uint32_t S2RG11RP : 1; + __IO uint32_t S2RG11WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG11E : 1; + __IO uint32_t S1RG11RP : 1; + __IO uint32_t S1RG11WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG11E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr11_field_t; + +typedef struct +{ + __IO uint32_t S2RG12RP : 1; + __IO uint32_t S2RG12WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG12E : 1; + __IO uint32_t S1RG12RP : 1; + __IO uint32_t S1RG12WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG12E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr12_field_t; + +typedef struct +{ + __IO uint32_t S2RG13RP : 1; + __IO uint32_t S2RG13WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG13E : 1; + __IO uint32_t S1RG13RP : 1; + __IO uint32_t S1RG13WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG13E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr13_field_t; + +typedef struct +{ + __IO uint32_t S2RG14RP : 1; + __IO uint32_t S2RG14WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG14E : 1; + __IO uint32_t S1RG14RP : 1; + __IO uint32_t S1RG14WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG14E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr14_field_t; + +typedef struct +{ + __IO uint32_t S2RG15RP : 1; + __IO uint32_t S2RG15WP : 1; + uint32_t RESERVED2 : 5; + __IO uint32_t S2RG15E : 1; + __IO uint32_t S1RG15RP : 1; + __IO uint32_t S1RG15WP : 1; + uint32_t RESERVED10 : 5; + __IO uint32_t S1RG15E : 1; + uint32_t RESERVED16 :16; +} stc_mpu_rgcr15_field_t; + +typedef struct +{ + __IO uint32_t SMPU2BRP : 1; + __IO uint32_t SMPU2BWP : 1; + __IO uint32_t SMPU2ACT : 2; + uint32_t RESERVED4 : 3; + __IO uint32_t SMPU2E : 1; + __IO uint32_t SMPU1BRP : 1; + __IO uint32_t SMPU1BWP : 1; + __IO uint32_t SMPU1ACT : 2; + uint32_t RESERVED12 : 3; + __IO uint32_t SMPU1E : 1; + __IO uint32_t FMPUBRP : 1; + __IO uint32_t FMPUBWP : 1; + __IO uint32_t FMPUACT : 2; + uint32_t RESERVED20 : 3; + __IO uint32_t FMPUE : 1; + uint32_t RESERVED24 : 8; +} stc_mpu_cr_field_t; + +typedef struct +{ + __IO uint32_t SMPU2EAF : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SMPU1EAF : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t FMPUEAF : 1; + uint32_t RESERVED17 :15; +} stc_mpu_sr_field_t; + +typedef struct +{ + __IO uint32_t SMPU2ECLR : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SMPU1ECLR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t FMPUECLR : 1; + uint32_t RESERVED17 :15; +} stc_mpu_eclr_field_t; + +typedef struct +{ + __IO uint32_t MPUWE : 1; + __IO uint32_t WKEY :15; + uint32_t RESERVED16 :16; +} stc_mpu_wp_field_t; + +typedef struct +{ + __IO uint32_t SRAMH : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t SRAM12 : 1; + uint32_t RESERVED5 : 3; + __IO uint32_t SRAM3 : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t SRAMRET : 1; + uint32_t RESERVED11 : 3; + __IO uint32_t DMA1 : 1; + __IO uint32_t DMA2 : 1; + __IO uint32_t FCM : 1; + __IO uint32_t AOS : 1; + uint32_t RESERVED18 : 2; + __IO uint32_t AES : 1; + __IO uint32_t HASH : 1; + __IO uint32_t TRNG : 1; + __IO uint32_t CRC : 1; + __IO uint32_t DCU1 : 1; + __IO uint32_t DCU2 : 1; + __IO uint32_t DCU3 : 1; + __IO uint32_t DCU4 : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t KEY : 1; +} stc_mstp_fcg0_field_t; + +typedef struct +{ + __IO uint32_t CAN : 1; + uint32_t RESERVED1 : 2; + __IO uint32_t QSPI : 1; + __IO uint32_t IIC1 : 1; + __IO uint32_t IIC2 : 1; + __IO uint32_t IIC3 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t USBFS : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t SDIOC1 : 1; + __IO uint32_t SDIOC2 : 1; + __IO uint32_t I2S1 : 1; + __IO uint32_t I2S2 : 1; + __IO uint32_t I2S3 : 1; + __IO uint32_t I2S4 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t SPI2 : 1; + __IO uint32_t SPI3 : 1; + __IO uint32_t SPI4 : 1; + uint32_t RESERVED20 : 4; + __IO uint32_t USART1 : 1; + __IO uint32_t USART2 : 1; + __IO uint32_t USART3 : 1; + __IO uint32_t USART4 : 1; + uint32_t RESERVED28 : 4; +} stc_mstp_fcg1_field_t; + +typedef struct +{ + __IO uint32_t TIMER0_1 : 1; + __IO uint32_t TIMER0_2 : 1; + __IO uint32_t TIMERA_1 : 1; + __IO uint32_t TIMERA_2 : 1; + __IO uint32_t TIMERA_3 : 1; + __IO uint32_t TIMERA_4 : 1; + __IO uint32_t TIMERA_5 : 1; + __IO uint32_t TIMERA_6 : 1; + __IO uint32_t TIMER4_1 : 1; + __IO uint32_t TIMER4_2 : 1; + __IO uint32_t TIMER4_3 : 1; + uint32_t RESERVED11 : 4; + __IO uint32_t EMB : 1; + __IO uint32_t TIMER6_1 : 1; + __IO uint32_t TIMER6_2 : 1; + __IO uint32_t TIMER6_3 : 1; + uint32_t RESERVED19 :13; +} stc_mstp_fcg2_field_t; + +typedef struct +{ + __IO uint32_t ADC1 : 1; + __IO uint32_t ADC2 : 1; + uint32_t RESERVED2 : 6; + __IO uint32_t CMP : 1; + uint32_t RESERVED9 : 3; + __IO uint32_t OTS : 1; + uint32_t RESERVED13 :19; +} stc_mstp_fcg3_field_t; + +typedef struct +{ + __IO uint32_t PRT0 : 1; + uint32_t RESERVED1 :15; + __IO uint32_t FCG0PCWE :16; +} stc_mstp_fcg0pc_field_t; + +typedef struct +{ + __IO uint16_t OTSST : 1; + __IO uint16_t OTSCK : 1; + __IO uint16_t OTSIE : 1; + __IO uint16_t TSSTP : 1; + uint16_t RESERVED4 :12; +} stc_ots_ctl_field_t; + +typedef struct +{ + __IO uint32_t TSOFS : 8; + __IO uint32_t TSSLP :24; +} stc_ots_lpr_field_t; + +typedef struct +{ + __IO uint32_t DFB : 1; + __IO uint32_t SOFEN : 1; + uint32_t RESERVED2 :30; +} stc_peric_usbfs_syctlreg_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t SELMMC1 : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SELMMC2 : 1; + uint32_t RESERVED4 :28; +} stc_peric_sdioc_syctlreg_field_t; + +typedef struct +{ + __IO uint16_t PIN00 : 1; + __IO uint16_t PIN01 : 1; + __IO uint16_t PIN02 : 1; + __IO uint16_t PIN03 : 1; + __IO uint16_t PIN04 : 1; + __IO uint16_t PIN05 : 1; + __IO uint16_t PIN06 : 1; + __IO uint16_t PIN07 : 1; + __IO uint16_t PIN08 : 1; + __IO uint16_t PIN09 : 1; + __IO uint16_t PIN10 : 1; + __IO uint16_t PIN11 : 1; + __IO uint16_t PIN12 : 1; + __IO uint16_t PIN13 : 1; + __IO uint16_t PIN14 : 1; + __IO uint16_t PIN15 : 1; +} stc_port_pidr_field_t; + +typedef struct +{ + __IO uint16_t POUT00 : 1; + __IO uint16_t POUT01 : 1; + __IO uint16_t POUT02 : 1; + __IO uint16_t POUT03 : 1; + __IO uint16_t POUT04 : 1; + __IO uint16_t POUT05 : 1; + __IO uint16_t POUT06 : 1; + __IO uint16_t POUT07 : 1; + __IO uint16_t POUT08 : 1; + __IO uint16_t POUT09 : 1; + __IO uint16_t POUT10 : 1; + __IO uint16_t POUT11 : 1; + __IO uint16_t POUT12 : 1; + __IO uint16_t POUT13 : 1; + __IO uint16_t POUT14 : 1; + __IO uint16_t POUT15 : 1; +} stc_port_podr_field_t; + +typedef struct +{ + __IO uint16_t POUTE00 : 1; + __IO uint16_t POUTE01 : 1; + __IO uint16_t POUTE02 : 1; + __IO uint16_t POUTE03 : 1; + __IO uint16_t POUTE04 : 1; + __IO uint16_t POUTE05 : 1; + __IO uint16_t POUTE06 : 1; + __IO uint16_t POUTE07 : 1; + __IO uint16_t POUTE08 : 1; + __IO uint16_t POUTE09 : 1; + __IO uint16_t POUTE10 : 1; + __IO uint16_t POUTE11 : 1; + __IO uint16_t POUTE12 : 1; + __IO uint16_t POUTE13 : 1; + __IO uint16_t POUTE14 : 1; + __IO uint16_t POUTE15 : 1; +} stc_port_poer_field_t; + +typedef struct +{ + __IO uint16_t POS00 : 1; + __IO uint16_t POS01 : 1; + __IO uint16_t POS02 : 1; + __IO uint16_t POS03 : 1; + __IO uint16_t POS04 : 1; + __IO uint16_t POS05 : 1; + __IO uint16_t POS06 : 1; + __IO uint16_t POS07 : 1; + __IO uint16_t POS08 : 1; + __IO uint16_t POS09 : 1; + __IO uint16_t POS10 : 1; + __IO uint16_t POS11 : 1; + __IO uint16_t POS12 : 1; + __IO uint16_t POS13 : 1; + __IO uint16_t POS14 : 1; + __IO uint16_t POS15 : 1; +} stc_port_posr_field_t; + +typedef struct +{ + __IO uint16_t POR00 : 1; + __IO uint16_t POR01 : 1; + __IO uint16_t POR02 : 1; + __IO uint16_t POR03 : 1; + __IO uint16_t POR04 : 1; + __IO uint16_t POR05 : 1; + __IO uint16_t POR06 : 1; + __IO uint16_t POR07 : 1; + __IO uint16_t POR08 : 1; + __IO uint16_t POR09 : 1; + __IO uint16_t POR10 : 1; + __IO uint16_t POR11 : 1; + __IO uint16_t POR12 : 1; + __IO uint16_t POR13 : 1; + __IO uint16_t POR14 : 1; + __IO uint16_t POR15 : 1; +} stc_port_porr_field_t; + +typedef struct +{ + __IO uint16_t POT00 : 1; + __IO uint16_t POT01 : 1; + __IO uint16_t POT02 : 1; + __IO uint16_t POT03 : 1; + __IO uint16_t POT04 : 1; + __IO uint16_t POT05 : 1; + __IO uint16_t POT06 : 1; + __IO uint16_t POT07 : 1; + __IO uint16_t POT08 : 1; + __IO uint16_t POT09 : 1; + __IO uint16_t POT10 : 1; + __IO uint16_t POT11 : 1; + __IO uint16_t POT12 : 1; + __IO uint16_t POT13 : 1; + __IO uint16_t POT14 : 1; + __IO uint16_t POT15 : 1; +} stc_port_potr_field_t; + +typedef struct +{ + __IO uint16_t PIN00 : 1; + __IO uint16_t PIN01 : 1; + __IO uint16_t PIN02 : 1; + uint16_t RESERVED3 :13; +} stc_port_pidrh_field_t; + +typedef struct +{ + __IO uint16_t POUT00 : 1; + __IO uint16_t POUT01 : 1; + __IO uint16_t POUT02 : 1; + uint16_t RESERVED3 :13; +} stc_port_podrh_field_t; + +typedef struct +{ + __IO uint16_t POUTE00 : 1; + __IO uint16_t POUTE01 : 1; + __IO uint16_t POUTE02 : 1; + uint16_t RESERVED3 :13; +} stc_port_poerh_field_t; + +typedef struct +{ + __IO uint16_t POS00 : 1; + __IO uint16_t POS01 : 1; + __IO uint16_t POS02 : 1; + uint16_t RESERVED3 :13; +} stc_port_posrh_field_t; + +typedef struct +{ + __IO uint16_t POR00 : 1; + __IO uint16_t POR01 : 1; + __IO uint16_t POR02 : 1; + uint16_t RESERVED3 :13; +} stc_port_porrh_field_t; + +typedef struct +{ + __IO uint16_t POT00 : 1; + __IO uint16_t POT01 : 1; + __IO uint16_t POT02 : 1; + uint16_t RESERVED3 :13; +} stc_port_potrh_field_t; + +typedef struct +{ + __IO uint16_t SPFE : 5; + uint16_t RESERVED5 :11; +} stc_port_pspcr_field_t; + +typedef struct +{ + __IO uint16_t BFSEL : 4; + uint16_t RESERVED4 :10; + __IO uint16_t RDWT : 2; +} stc_port_pccr_field_t; + +typedef struct +{ + __IO uint16_t PINAE : 6; + uint16_t RESERVED6 :10; +} stc_port_pinaer_field_t; + +typedef struct +{ + __IO uint16_t WE : 1; + uint16_t RESERVED1 : 7; + __IO uint16_t WP : 8; +} stc_port_pwpr_field_t; + +typedef struct +{ + __IO uint16_t POUT : 1; + __IO uint16_t POUTE : 1; + __IO uint16_t NOD : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t DRV : 2; + __IO uint16_t PUU : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t PIN : 1; + __IO uint16_t INVE : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t INTE : 1; + uint16_t RESERVED13 : 1; + __IO uint16_t LTE : 1; + __IO uint16_t DDIS : 1; +} stc_port_pcr_field_t; + +typedef struct +{ + __IO uint16_t FSEL : 6; + uint16_t RESERVED6 : 2; + __IO uint16_t BFE : 1; + uint16_t RESERVED9 : 7; +} stc_port_pfsr_field_t; + +typedef struct +{ + __IO uint32_t MDSEL : 3; + __IO uint32_t PFE : 1; + __IO uint32_t PFSAE : 1; + __IO uint32_t DCOME : 1; + __IO uint32_t XIPE : 1; + __IO uint32_t SPIMD3 : 1; + __IO uint32_t IPRSL : 2; + __IO uint32_t APRSL : 2; + __IO uint32_t DPRSL : 2; + uint32_t RESERVED14 : 2; + __IO uint32_t DIV : 6; + uint32_t RESERVED22 :10; +} stc_qspi_cr_field_t; + +typedef struct +{ + __IO uint32_t SSHW : 4; + __IO uint32_t SSNW : 2; + uint32_t RESERVED6 :26; +} stc_qspi_cscr_field_t; + +typedef struct +{ + __IO uint32_t AWSL : 2; + __IO uint32_t FOUR_BIC : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t SSNHD : 1; + __IO uint32_t SSNLD : 1; + __IO uint32_t WPOL : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t DMCYCN : 4; + uint32_t RESERVED12 : 3; + __IO uint32_t DUTY : 1; + uint32_t RESERVED16 :16; +} stc_qspi_fcr_field_t; + +typedef struct +{ + __IO uint32_t BUSY : 1; + uint32_t RESERVED1 : 5; + __IO uint32_t XIPF : 1; + __IO uint32_t RAER : 1; + __IO uint32_t PFNUM : 5; + uint32_t RESERVED13 : 1; + __IO uint32_t PFFUL : 1; + __IO uint32_t PFAN : 1; + uint32_t RESERVED16 :16; +} stc_qspi_sr_field_t; + +typedef struct +{ + __IO uint32_t DCOM : 8; + uint32_t RESERVED8 :24; +} stc_qspi_dcom_field_t; + +typedef struct +{ + __IO uint32_t RIC : 8; + uint32_t RESERVED8 :24; +} stc_qspi_ccmd_field_t; + +typedef struct +{ + __IO uint32_t XIPMC : 8; + uint32_t RESERVED8 :24; +} stc_qspi_xcmd_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 7; + __IO uint32_t RAERCLR : 1; + uint32_t RESERVED8 :24; +} stc_qspi_sr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 :26; + __IO uint32_t EXADR : 6; +} stc_qspi_exar_field_t; + +typedef struct +{ + __IO uint32_t RESET : 1; + uint32_t RESERVED1 :31; +} stc_rtc_cr0_field_t; + +typedef struct +{ + __IO uint32_t PRDS : 3; + __IO uint32_t AMPM : 1; + __IO uint32_t ALMFCLR : 1; + __IO uint32_t ONEHZOE : 1; + __IO uint32_t ONEHZSEL : 1; + __IO uint32_t START : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr1_field_t; + +typedef struct +{ + __IO uint32_t RWREQ : 1; + __IO uint32_t RWEN : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t ALMF : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t PRDIE : 1; + __IO uint32_t ALMIE : 1; + __IO uint32_t ALME : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 4; + __IO uint32_t LRCEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t RCKSEL : 1; + uint32_t RESERVED8 :24; +} stc_rtc_cr3_field_t; + +typedef struct +{ + __IO uint32_t SECU : 4; + __IO uint32_t SECD : 3; + uint32_t RESERVED7 :25; +} stc_rtc_sec_field_t; + +typedef struct +{ + __IO uint32_t MINU : 4; + __IO uint32_t MIND : 3; + uint32_t RESERVED7 :25; +} stc_rtc_min_field_t; + +typedef struct +{ + __IO uint32_t HOURU : 4; + __IO uint32_t HOURD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_hour_field_t; + +typedef struct +{ + __IO uint32_t WEEK : 3; + uint32_t RESERVED3 :29; +} stc_rtc_week_field_t; + +typedef struct +{ + __IO uint32_t DAYU : 4; + __IO uint32_t DAYD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_day_field_t; + +typedef struct +{ + __IO uint32_t MON : 5; + uint32_t RESERVED5 :27; +} stc_rtc_mon_field_t; + +typedef struct +{ + __IO uint32_t YEARU : 4; + __IO uint32_t YEARD : 4; + uint32_t RESERVED8 :24; +} stc_rtc_year_field_t; + +typedef struct +{ + __IO uint32_t ALMMINU : 4; + __IO uint32_t ALMMIND : 3; + uint32_t RESERVED7 :25; +} stc_rtc_almmin_field_t; + +typedef struct +{ + __IO uint32_t ALMHOURU : 4; + __IO uint32_t ALMHOURD : 2; + uint32_t RESERVED6 :26; +} stc_rtc_almhour_field_t; + +typedef struct +{ + __IO uint32_t ALMWEEK : 7; + uint32_t RESERVED7 :25; +} stc_rtc_almweek_field_t; + +typedef struct +{ + __IO uint32_t COMP8 : 1; + uint32_t RESERVED1 : 6; + __IO uint32_t COMPEN : 1; + uint32_t RESERVED8 :24; +} stc_rtc_errcrh_field_t; + +typedef struct +{ + __IO uint32_t COMP : 8; + uint32_t RESERVED8 :24; +} stc_rtc_errcrl_field_t; + +typedef struct +{ + __IO uint16_t TBS :12; + uint16_t RESERVED12 : 4; +} stc_sdioc_blksize_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 1; + __IO uint16_t BCE : 1; + __IO uint16_t ATCEN : 2; + __IO uint16_t DDIR : 1; + __IO uint16_t MULB : 1; + uint16_t RESERVED6 :10; +} stc_sdioc_transmode_field_t; + +typedef struct +{ + __IO uint16_t RESTYP : 2; + uint16_t RESERVED2 : 1; + __IO uint16_t CCE : 1; + __IO uint16_t ICE : 1; + __IO uint16_t DAT : 1; + __IO uint16_t TYP : 2; + __IO uint16_t IDX : 6; + uint16_t RESERVED14 : 2; +} stc_sdioc_cmd_field_t; + +typedef struct +{ + __IO uint32_t CIC : 1; + __IO uint32_t CID : 1; + __IO uint32_t DA : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t WTA : 1; + __IO uint32_t RTA : 1; + __IO uint32_t BWE : 1; + __IO uint32_t BRE : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t CIN : 1; + __IO uint32_t CSS : 1; + __IO uint32_t CDL : 1; + __IO uint32_t WPL : 1; + __IO uint32_t DATL : 4; + __IO uint32_t CMDL : 1; + uint32_t RESERVED25 : 7; +} stc_sdioc_pstat_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 1; + __IO uint8_t DW : 1; + __IO uint8_t HSEN : 1; + uint8_t RESERVED3 : 2; + __IO uint8_t EXDW : 1; + __IO uint8_t CDTL : 1; + __IO uint8_t CDSS : 1; +} stc_sdioc_hostcon_field_t; + +typedef struct +{ + __IO uint8_t PWON : 1; + uint8_t RESERVED1 : 7; +} stc_sdioc_pwrcon_field_t; + +typedef struct +{ + __IO uint8_t SABGR : 1; + __IO uint8_t CR : 1; + __IO uint8_t RWC : 1; + __IO uint8_t IABG : 1; + uint8_t RESERVED4 : 4; +} stc_sdioc_blkgpcon_field_t; + +typedef struct +{ + __IO uint16_t ICE : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t CE : 1; + uint16_t RESERVED3 : 5; + __IO uint16_t FS : 8; +} stc_sdioc_clkcon_field_t; + +typedef struct +{ + __IO uint8_t DTO : 4; + uint8_t RESERVED4 : 4; +} stc_sdioc_toutcon_field_t; + +typedef struct +{ + __IO uint8_t RSTA : 1; + __IO uint8_t RSTC : 1; + __IO uint8_t RSTD : 1; + uint8_t RESERVED3 : 5; +} stc_sdioc_sftrst_field_t; + +typedef struct +{ + __IO uint16_t CC : 1; + __IO uint16_t TC : 1; + __IO uint16_t BGE : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWR : 1; + __IO uint16_t BRR : 1; + __IO uint16_t CIST : 1; + __IO uint16_t CRM : 1; + __IO uint16_t CINT : 1; + uint16_t RESERVED9 : 6; + __IO uint16_t EI : 1; +} stc_sdioc_norintst_field_t; + +typedef struct +{ + __IO uint16_t CTOE : 1; + __IO uint16_t CCE : 1; + __IO uint16_t CEBE : 1; + __IO uint16_t CIE : 1; + __IO uint16_t DTOE : 1; + __IO uint16_t DCE : 1; + __IO uint16_t DEBE : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACE : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintst_field_t; + +typedef struct +{ + __IO uint16_t CCEN : 1; + __IO uint16_t TCEN : 1; + __IO uint16_t BGEEN : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWREN : 1; + __IO uint16_t BRREN : 1; + __IO uint16_t CISTEN : 1; + __IO uint16_t CRMEN : 1; + __IO uint16_t CINTEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_norintsten_field_t; + +typedef struct +{ + __IO uint16_t CTOEEN : 1; + __IO uint16_t CCEEN : 1; + __IO uint16_t CEBEEN : 1; + __IO uint16_t CIEEN : 1; + __IO uint16_t DTOEEN : 1; + __IO uint16_t DCEEN : 1; + __IO uint16_t DEBEEN : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACEEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintsten_field_t; + +typedef struct +{ + __IO uint16_t CCSEN : 1; + __IO uint16_t TCSEN : 1; + __IO uint16_t BGESEN : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t BWRSEN : 1; + __IO uint16_t BRRSEN : 1; + __IO uint16_t CISTSEN : 1; + __IO uint16_t CRMSEN : 1; + __IO uint16_t CINTSEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_norintsgen_field_t; + +typedef struct +{ + __IO uint16_t CTOESEN : 1; + __IO uint16_t CCESEN : 1; + __IO uint16_t CEBESEN : 1; + __IO uint16_t CIESEN : 1; + __IO uint16_t DTOESEN : 1; + __IO uint16_t DCESEN : 1; + __IO uint16_t DEBESEN : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t ACESEN : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_errintsgen_field_t; + +typedef struct +{ + __IO uint16_t NE : 1; + __IO uint16_t TOE : 1; + __IO uint16_t CE : 1; + __IO uint16_t EBE : 1; + __IO uint16_t IE : 1; + uint16_t RESERVED5 : 2; + __IO uint16_t CMDE : 1; + uint16_t RESERVED8 : 8; +} stc_sdioc_atcerrst_field_t; + +typedef struct +{ + __IO uint16_t FNE : 1; + __IO uint16_t FTOE : 1; + __IO uint16_t FCE : 1; + __IO uint16_t FEBE : 1; + __IO uint16_t FIE : 1; + uint16_t RESERVED5 : 2; + __IO uint16_t FCMDE : 1; + uint16_t RESERVED8 : 8; +} stc_sdioc_fea_field_t; + +typedef struct +{ + __IO uint16_t FCTOE : 1; + __IO uint16_t FCCE : 1; + __IO uint16_t FCEBE : 1; + __IO uint16_t FCIE : 1; + __IO uint16_t FDTOE : 1; + __IO uint16_t FDCE : 1; + __IO uint16_t FDEBE : 1; + uint16_t RESERVED7 : 1; + __IO uint16_t FACE : 1; + uint16_t RESERVED9 : 7; +} stc_sdioc_fee_field_t; + +typedef struct +{ + __IO uint32_t SPIMDS : 1; + __IO uint32_t TXMDS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t MSTR : 1; + __IO uint32_t SPLPBK : 1; + __IO uint32_t SPLPBK2 : 1; + __IO uint32_t SPE : 1; + __IO uint32_t CSUSPE : 1; + __IO uint32_t EIE : 1; + __IO uint32_t TXIE : 1; + __IO uint32_t RXIE : 1; + __IO uint32_t IDIE : 1; + __IO uint32_t MODFE : 1; + __IO uint32_t PATE : 1; + __IO uint32_t PAOE : 1; + __IO uint32_t PAE : 1; + uint32_t RESERVED16 :16; +} stc_spi_cr1_field_t; + +typedef struct +{ + __IO uint32_t FTHLV : 2; + uint32_t RESERVED2 : 4; + __IO uint32_t SPRDTD : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t SS0PV : 1; + __IO uint32_t SS1PV : 1; + __IO uint32_t SS2PV : 1; + __IO uint32_t SS3PV : 1; + uint32_t RESERVED12 : 8; + __IO uint32_t MSSI : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t MSSDL : 3; + uint32_t RESERVED27 : 1; + __IO uint32_t MIDI : 3; + uint32_t RESERVED31 : 1; +} stc_spi_cfg1_field_t; + +typedef struct +{ + __IO uint32_t OVRERF : 1; + __IO uint32_t IDLNF : 1; + __IO uint32_t MODFERF : 1; + __IO uint32_t PERF : 1; + __IO uint32_t UDRERF : 1; + __IO uint32_t TDEF : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t RDFF : 1; + uint32_t RESERVED8 :24; +} stc_spi_sr_field_t; + +typedef struct +{ + __IO uint32_t CPHA : 1; + __IO uint32_t CPOL : 1; + __IO uint32_t MBR : 3; + __IO uint32_t SSA : 3; + __IO uint32_t DSIZE : 4; + __IO uint32_t LSBF : 1; + __IO uint32_t MIDIE : 1; + __IO uint32_t MSSDLE : 1; + __IO uint32_t MSSIE : 1; + uint32_t RESERVED16 :16; +} stc_spi_cfg2_field_t; + +typedef struct +{ + __IO uint32_t SRAM12_RWT : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t SRAM12_WWT : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t SRAM3_RWT : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t SRAM3_WWT : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t SRAMH_RWT : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t SRAMH_WWT : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t SRAMR_RWT : 3; + uint32_t RESERVED27 : 1; + __IO uint32_t SRAMR_WWT : 3; + uint32_t RESERVED31 : 1; +} stc_sramc_wtcr_field_t; + +typedef struct +{ + __IO uint32_t WTPRC : 1; + __IO uint32_t WTPRKW : 7; + uint32_t RESERVED8 :24; +} stc_sramc_wtpr_field_t; + +typedef struct +{ + __IO uint32_t PYOAD : 1; + uint32_t RESERVED1 :15; + __IO uint32_t ECCOAD : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t ECCMOD : 2; + uint32_t RESERVED26 : 6; +} stc_sramc_ckcr_field_t; + +typedef struct +{ + __IO uint32_t CKPRC : 1; + __IO uint32_t CKPRKW : 7; + uint32_t RESERVED8 :24; +} stc_sramc_ckpr_field_t; + +typedef struct +{ + __IO uint32_t SRAM3_1ERR : 1; + __IO uint32_t SRAM3_2ERR : 1; + __IO uint32_t SRAM12_PYERR : 1; + __IO uint32_t SRAMH_PYERR : 1; + __IO uint32_t SRAMR_PYERR : 1; + uint32_t RESERVED5 :27; +} stc_sramc_cksr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + __IO uint32_t UDF : 1; + __IO uint32_t REF : 1; + uint32_t RESERVED18 :14; +} stc_swdt_sr_field_t; + +typedef struct +{ + __IO uint32_t RF :16; + uint32_t RESERVED16 :16; +} stc_swdt_rr_field_t; + +typedef struct +{ + __IO uint16_t FLNWT : 1; + __IO uint16_t CKSMRC : 1; + uint16_t RESERVED2 :13; + __IO uint16_t STOP : 1; +} stc_sysreg_pwr_stpmcr_field_t; + +typedef struct +{ + __IO uint16_t PERICKSEL : 4; + uint16_t RESERVED4 :12; +} stc_sysreg_cmu_pericksel_field_t; + +typedef struct +{ + __IO uint16_t I2S1CKSEL : 4; + __IO uint16_t I2S2CKSEL : 4; + __IO uint16_t I2S3CKSEL : 4; + __IO uint16_t I2S4CKSEL : 4; +} stc_sysreg_cmu_i2scksel_field_t; + +typedef struct +{ + __IO uint32_t RAMPDC0 : 1; + __IO uint32_t RAMPDC1 : 1; + __IO uint32_t RAMPDC2 : 1; + __IO uint32_t RAMPDC3 : 1; + __IO uint32_t RAMPDC4 : 1; + __IO uint32_t RAMPDC5 : 1; + __IO uint32_t RAMPDC6 : 1; + __IO uint32_t RAMPDC7 : 1; + __IO uint32_t RAMPDC8 : 1; + uint32_t RESERVED9 :23; +} stc_sysreg_pwr_rampc0_field_t; + +typedef struct +{ + __IO uint32_t AESRDP : 1; + __IO uint32_t AESWRP : 1; + __IO uint32_t HASHRDP : 1; + __IO uint32_t HASHWRP : 1; + __IO uint32_t TRNGRDP : 1; + __IO uint32_t TRNGWRP : 1; + __IO uint32_t CRCRDP : 1; + __IO uint32_t CRCWRP : 1; + __IO uint32_t FMCRDP : 1; + __IO uint32_t FMCWRP : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t WDTRDP : 1; + __IO uint32_t WDTWRP : 1; + __IO uint32_t SWDTRDP : 1; + __IO uint32_t SWDTWRP : 1; + __IO uint32_t BKSRAMRDP : 1; + __IO uint32_t BKSRAMWRP : 1; + __IO uint32_t RTCRDP : 1; + __IO uint32_t RTCWRP : 1; + __IO uint32_t DMPURDP : 1; + __IO uint32_t DMPUWRP : 1; + __IO uint32_t SRAMCRDP : 1; + __IO uint32_t SRAMCWRP : 1; + __IO uint32_t INTCRDP : 1; + __IO uint32_t INTCWRP : 1; + __IO uint32_t SYSCRDP : 1; + __IO uint32_t SYSCWRP : 1; + __IO uint32_t MSTPRDP : 1; + __IO uint32_t MSTPWRP : 1; + uint32_t RESERVED30 : 1; + __IO uint32_t BUSERRE : 1; +} stc_sysreg_mpu_ippr_field_t; + +typedef struct +{ + __IO uint32_t PCLK0S : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t PCLK1S : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t PCLK2S : 3; + uint32_t RESERVED11 : 1; + __IO uint32_t PCLK3S : 3; + uint32_t RESERVED15 : 1; + __IO uint32_t PCLK4S : 3; + uint32_t RESERVED19 : 1; + __IO uint32_t EXCKS : 3; + uint32_t RESERVED23 : 1; + __IO uint32_t HCLKS : 3; + uint32_t RESERVED27 : 5; +} stc_sysreg_cmu_scfgr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t USBCKS : 4; +} stc_sysreg_cmu_ufsckcfgr_field_t; + +typedef struct +{ + __IO uint8_t CKSW : 3; + uint8_t RESERVED3 : 5; +} stc_sysreg_cmu_ckswr_field_t; + +typedef struct +{ + __IO uint8_t MPLLOFF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_pllcr_field_t; + +typedef struct +{ + __IO uint8_t UPLLOFF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_upllcr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtalcr_field_t; + +typedef struct +{ + __IO uint8_t HRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_hrccr_field_t; + +typedef struct +{ + __IO uint8_t MRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_mrccr_field_t; + +typedef struct +{ + __IO uint8_t HRCSTBF : 1; + uint8_t RESERVED1 : 2; + __IO uint8_t XTALSTBF : 1; + uint8_t RESERVED4 : 1; + __IO uint8_t MPLLSTBF : 1; + __IO uint8_t UPLLSTBF : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_cmu_oscstbsr_field_t; + +typedef struct +{ + __IO uint8_t MCO1SEL : 4; + __IO uint8_t MCO1DIV : 3; + __IO uint8_t MCO1EN : 1; +} stc_sysreg_cmu_mco1cfgr_field_t; + +typedef struct +{ + __IO uint8_t MCO2SEL : 4; + __IO uint8_t MCO2DIV : 3; + __IO uint8_t MCO2EN : 1; +} stc_sysreg_cmu_mco2cfgr_field_t; + +typedef struct +{ + __IO uint8_t TPIUCKS : 2; + uint8_t RESERVED2 : 5; + __IO uint8_t TPIUCKOE : 1; +} stc_sysreg_cmu_tpiuckcfgr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTDIE : 1; + __IO uint8_t XTALSTDRE : 1; + __IO uint8_t XTALSTDRIS : 1; + uint8_t RESERVED3 : 4; + __IO uint8_t XTALSTDE : 1; +} stc_sysreg_cmu_xtalstdcr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTDF : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtalstdsr_field_t; + +typedef struct +{ + __IO uint8_t XTALSTB : 4; + uint8_t RESERVED4 : 4; +} stc_sysreg_cmu_xtalstbcr_field_t; + +typedef struct +{ + __IO uint16_t PORF : 1; + __IO uint16_t PINRF : 1; + __IO uint16_t BORF : 1; + __IO uint16_t PVD1RF : 1; + __IO uint16_t PVD2RF : 1; + __IO uint16_t WDRF : 1; + __IO uint16_t SWDRF : 1; + __IO uint16_t PDRF : 1; + __IO uint16_t SWRF : 1; + __IO uint16_t MPUERF : 1; + __IO uint16_t RAPERF : 1; + __IO uint16_t RAECRF : 1; + __IO uint16_t CKFERF : 1; + __IO uint16_t XTALERF : 1; + __IO uint16_t MULTIRF : 1; + __IO uint16_t CLRF : 1; +} stc_sysreg_rmu_rstf0_field_t; + +typedef struct +{ + __IO uint8_t PVD1NMIS : 1; + uint8_t RESERVED1 : 3; + __IO uint8_t PVD2NMIS : 1; + uint8_t RESERVED5 : 3; +} stc_sysreg_pwr_pvdicr_field_t; + +typedef struct +{ + __IO uint8_t PVD1MON : 1; + __IO uint8_t PVD1DETFLG : 1; + uint8_t RESERVED2 : 2; + __IO uint8_t PVD2MON : 1; + __IO uint8_t PVD2DETFLG : 1; + uint8_t RESERVED6 : 2; +} stc_sysreg_pwr_pvddsr_field_t; + +typedef struct +{ + __IO uint32_t MPLLM : 5; + uint32_t RESERVED5 : 2; + __IO uint32_t PLLSRC : 1; + __IO uint32_t MPLLN : 9; + uint32_t RESERVED17 : 3; + __IO uint32_t MPLLR : 4; + __IO uint32_t MPLLQ : 4; + __IO uint32_t MPLLP : 4; +} stc_sysreg_cmu_pllcfgr_field_t; + +typedef struct +{ + __IO uint32_t UPLLM : 5; + uint32_t RESERVED5 : 3; + __IO uint32_t UPLLN : 9; + uint32_t RESERVED17 : 3; + __IO uint32_t UPLLR : 4; + __IO uint32_t UPLLQ : 4; + __IO uint32_t UPLLP : 4; +} stc_sysreg_cmu_upllcfgr_field_t; + +typedef struct +{ + __IO uint16_t FPRCB0 : 1; + __IO uint16_t FPRCB1 : 1; + __IO uint16_t FPRCB2 : 1; + __IO uint16_t FPRCB3 : 1; + uint16_t RESERVED4 : 4; + __IO uint16_t FPRCWE : 8; +} stc_sysreg_pwr_fprc_field_t; + +typedef struct +{ + __IO uint8_t PDMDS : 2; + __IO uint8_t VVDRSD : 1; + __IO uint8_t RETRAMSD : 1; + __IO uint8_t IORTN : 2; + uint8_t RESERVED6 : 1; + __IO uint8_t PWDN : 1; +} stc_sysreg_pwr_pwrc0_field_t; + +typedef struct +{ + __IO uint8_t VPLLSD : 1; + __IO uint8_t VHRCSD : 1; + uint8_t RESERVED2 : 4; + __IO uint8_t STPDAS : 2; +} stc_sysreg_pwr_pwrc1_field_t; + +typedef struct +{ + __IO uint8_t DDAS : 4; + __IO uint8_t DVS : 2; + uint8_t RESERVED6 : 2; +} stc_sysreg_pwr_pwrc2_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 2; + __IO uint8_t PDTS : 1; + uint8_t RESERVED3 : 5; +} stc_sysreg_pwr_pwrc3_field_t; + +typedef struct +{ + __IO uint8_t WKE00 : 1; + __IO uint8_t WKE01 : 1; + __IO uint8_t WKE02 : 1; + __IO uint8_t WKE03 : 1; + __IO uint8_t WKE10 : 1; + __IO uint8_t WKE11 : 1; + __IO uint8_t WKE12 : 1; + __IO uint8_t WKE13 : 1; +} stc_sysreg_pwr_pdwke0_field_t; + +typedef struct +{ + __IO uint8_t WKE20 : 1; + __IO uint8_t WKE21 : 1; + __IO uint8_t WKE22 : 1; + __IO uint8_t WKE23 : 1; + __IO uint8_t WKE30 : 1; + __IO uint8_t WKE31 : 1; + __IO uint8_t WKE32 : 1; + __IO uint8_t WKE33 : 1; +} stc_sysreg_pwr_pdwke1_field_t; + +typedef struct +{ + __IO uint8_t VD1WKE : 1; + __IO uint8_t VD2WKE : 1; + __IO uint8_t NMIWKE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t RTCPRDWKE : 1; + __IO uint8_t RTCALMWKE : 1; + uint8_t RESERVED6 : 1; + __IO uint8_t WKTMWKE : 1; +} stc_sysreg_pwr_pdwke2_field_t; + +typedef struct +{ + __IO uint8_t WK0EGS : 1; + __IO uint8_t WK1EGS : 1; + __IO uint8_t WK2EGS : 1; + __IO uint8_t WK3EGS : 1; + __IO uint8_t VD1EGS : 1; + __IO uint8_t VD2EGS : 1; + __IO uint8_t NMIEGS : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pdwkes_field_t; + +typedef struct +{ + __IO uint8_t PTWK0F : 1; + __IO uint8_t PTWK1F : 1; + __IO uint8_t PTWK2F : 1; + __IO uint8_t PTWK3F : 1; + __IO uint8_t VD1WKF : 1; + __IO uint8_t VD2WKF : 1; + __IO uint8_t NMIWKF : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pdwkf0_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t RTCPRDWKF : 1; + __IO uint8_t RTCALMWKF : 1; + uint8_t RESERVED6 : 1; + __IO uint8_t WKTMWKF : 1; +} stc_sysreg_pwr_pdwkf1_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 7; + __IO uint8_t ADBUFE : 1; +} stc_sysreg_pwr_pwcmr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 4; + __IO uint8_t XTALDRV : 2; + __IO uint8_t XTALMS : 1; + __IO uint8_t SUPDRV : 1; +} stc_sysreg_cmu_xtalcfgr_field_t; + +typedef struct +{ + __IO uint8_t EXVCCINEN : 1; + uint8_t RESERVED1 : 4; + __IO uint8_t PVD1EN : 1; + __IO uint8_t PVD2EN : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdcr0_field_t; + +typedef struct +{ + __IO uint8_t PVD1IRE : 1; + __IO uint8_t PVD1IRS : 1; + __IO uint8_t PVD1CMPOE : 1; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2IRE : 1; + __IO uint8_t PVD2IRS : 1; + __IO uint8_t PVD2CMPOE : 1; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdcr1_field_t; + +typedef struct +{ + __IO uint8_t PVD1NFDIS : 1; + __IO uint8_t PVD1NFCKS : 2; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2NFDIS : 1; + __IO uint8_t PVD2NFCKS : 2; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdfcr_field_t; + +typedef struct +{ + __IO uint8_t PVD1LVL : 3; + uint8_t RESERVED3 : 1; + __IO uint8_t PVD2LVL : 3; + uint8_t RESERVED7 : 1; +} stc_sysreg_pwr_pvdlcr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32STP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_xtal32cr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32DRV : 3; + uint8_t RESERVED3 : 5; +} stc_sysreg_cmu_xtal32cfgr_field_t; + +typedef struct +{ + __IO uint8_t XTAL32NF : 2; + uint8_t RESERVED2 : 6; +} stc_sysreg_cmu_xtal32nfr_field_t; + +typedef struct +{ + __IO uint8_t LRCSTP : 1; + uint8_t RESERVED1 : 7; +} stc_sysreg_cmu_lrccr_field_t; + +typedef struct +{ + uint8_t RESERVED0 : 7; + __IO uint8_t CSDIS : 1; +} stc_sysreg_pwr_xtal32cs_field_t; + +typedef struct +{ + __IO uint32_t CNTA :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cntar_field_t; + +typedef struct +{ + __IO uint32_t CNTB :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cntbr_field_t; + +typedef struct +{ + __IO uint32_t CMPA :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cmpar_field_t; + +typedef struct +{ + __IO uint32_t CMPB :16; + uint32_t RESERVED16 :16; +} stc_tmr0_cmpbr_field_t; + +typedef struct +{ + __IO uint32_t CSTA : 1; + __IO uint32_t CAPMDA : 1; + __IO uint32_t INTENA : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t CKDIVA : 4; + __IO uint32_t SYNSA : 1; + __IO uint32_t SYNCLKA : 1; + __IO uint32_t ASYNCLKA : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t HSTAA : 1; + __IO uint32_t HSTPA : 1; + __IO uint32_t HCLEA : 1; + __IO uint32_t HICPA : 1; + __IO uint32_t CSTB : 1; + __IO uint32_t CAPMDB : 1; + __IO uint32_t INTENB : 1; + uint32_t RESERVED19 : 1; + __IO uint32_t CKDIVB : 4; + __IO uint32_t SYNSB : 1; + __IO uint32_t SYNCLKB : 1; + __IO uint32_t ASYNCLKB : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t HSTAB : 1; + __IO uint32_t HSTPB : 1; + __IO uint32_t HCLEB : 1; + __IO uint32_t HICPB : 1; +} stc_tmr0_bconr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + uint32_t RESERVED1 :15; + __IO uint32_t CMBF : 1; + uint32_t RESERVED17 :15; +} stc_tmr0_stflr_field_t; + +typedef struct +{ + __IO uint16_t OCEH : 1; + __IO uint16_t OCEL : 1; + __IO uint16_t OCPH : 1; + __IO uint16_t OCPL : 1; + __IO uint16_t OCIEH : 1; + __IO uint16_t OCIEL : 1; + __IO uint16_t OCFH : 1; + __IO uint16_t OCFL : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_ocsr_field_t; + +typedef struct +{ + __IO uint16_t CHBUFEN : 2; + __IO uint16_t CLBUFEN : 2; + __IO uint16_t MHBUFEN : 2; + __IO uint16_t MLBUFEN : 2; + __IO uint16_t LMCH : 1; + __IO uint16_t LMCL : 1; + __IO uint16_t LMMH : 1; + __IO uint16_t LMML : 1; + __IO uint16_t MCECH : 1; + __IO uint16_t MCECL : 1; + uint16_t RESERVED14 : 2; +} stc_tmr4_ocer_field_t; + +typedef struct +{ + __IO uint16_t OCFDCH : 1; + __IO uint16_t OCFPKH : 1; + __IO uint16_t OCFUCH : 1; + __IO uint16_t OCFZRH : 1; + __IO uint16_t OPDCH : 2; + __IO uint16_t OPPKH : 2; + __IO uint16_t OPUCH : 2; + __IO uint16_t OPZRH : 2; + __IO uint16_t OPNPKH : 2; + __IO uint16_t OPNZRH : 2; +} stc_tmr4_ocmrh_field_t; + +typedef struct +{ + __IO uint32_t OCFDCL : 1; + __IO uint32_t OCFPKL : 1; + __IO uint32_t OCFUCL : 1; + __IO uint32_t OCFZRL : 1; + __IO uint32_t OPDCL : 2; + __IO uint32_t OPPKL : 2; + __IO uint32_t OPUCL : 2; + __IO uint32_t OPZRL : 2; + __IO uint32_t OPNPKL : 2; + __IO uint32_t OPNZRL : 2; + __IO uint32_t EOPNDCL : 2; + __IO uint32_t EOPNUCL : 2; + __IO uint32_t EOPDCL : 2; + __IO uint32_t EOPPKL : 2; + __IO uint32_t EOPUCL : 2; + __IO uint32_t EOPZRL : 2; + __IO uint32_t EOPNPKL : 2; + __IO uint32_t EOPNZRL : 2; +} stc_tmr4_ocmrl_field_t; + +typedef struct +{ + __IO uint16_t CKDIV : 4; + __IO uint16_t CLEAR : 1; + __IO uint16_t MODE : 1; + __IO uint16_t STOP : 1; + __IO uint16_t BUFEN : 1; + __IO uint16_t IRQPEN : 1; + __IO uint16_t IRQPF : 1; + uint16_t RESERVED10 : 3; + __IO uint16_t IRQZEN : 1; + __IO uint16_t IRQZF : 1; + __IO uint16_t ECKEN : 1; +} stc_tmr4_ccsr_field_t; + +typedef struct +{ + __IO uint16_t ZIM : 4; + __IO uint16_t PIM : 4; + __IO uint16_t ZIC : 4; + __IO uint16_t PIC : 4; +} stc_tmr4_cvpr_field_t; + +typedef struct +{ + __IO uint16_t DIVCK : 4; + __IO uint16_t PWMMD : 2; + __IO uint16_t LVLS : 2; + uint16_t RESERVED8 : 8; +} stc_tmr4_pocr_field_t; + +typedef struct +{ + __IO uint16_t RTIDU : 1; + __IO uint16_t RTIDV : 1; + __IO uint16_t RTIDW : 1; + uint16_t RESERVED3 : 1; + __IO uint16_t RTIFU : 1; + __IO uint16_t RTICU : 1; + __IO uint16_t RTEU : 1; + __IO uint16_t RTSU : 1; + __IO uint16_t RTIFV : 1; + __IO uint16_t RTICV : 1; + __IO uint16_t RTEV : 1; + __IO uint16_t RTSV : 1; + __IO uint16_t RTIFW : 1; + __IO uint16_t RTICW : 1; + __IO uint16_t RTEW : 1; + __IO uint16_t RTSW : 1; +} stc_tmr4_rcsr_field_t; + +typedef struct +{ + __IO uint16_t BUFEN : 2; + __IO uint16_t EVTOS : 3; + __IO uint16_t LMC : 1; + uint16_t RESERVED6 : 2; + __IO uint16_t EVTMS : 1; + __IO uint16_t EVTDS : 1; + uint16_t RESERVED10 : 2; + __IO uint16_t DEN : 1; + __IO uint16_t PEN : 1; + __IO uint16_t UEN : 1; + __IO uint16_t ZEN : 1; +} stc_tmr4_scsr_field_t; + +typedef struct +{ + __IO uint16_t AMC : 4; + uint16_t RESERVED4 : 2; + __IO uint16_t MZCE : 1; + __IO uint16_t MPCE : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_scmr_field_t; + +typedef struct +{ + uint16_t RESERVED0 : 7; + __IO uint16_t HOLD : 1; + uint16_t RESERVED8 : 8; +} stc_tmr4_ecsr_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer1_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer2_field_t; + +typedef struct +{ + __IO uint16_t EMBVAL : 2; + uint16_t RESERVED2 :14; +} stc_tmr4_cr_ecer3_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :16; +} stc_tmr6_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_perbr_field_t; + +typedef struct +{ + __IO uint32_t PERC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_percr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t GCME :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmer_field_t; + +typedef struct +{ + __IO uint32_t GCMF :16; + uint32_t RESERVED16 :16; +} stc_tmr6_gcmfr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmbr_field_t; + +typedef struct +{ + __IO uint32_t SCMC :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmcr_field_t; + +typedef struct +{ + __IO uint32_t SCMD :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmdr_field_t; + +typedef struct +{ + __IO uint32_t SCME :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmer_field_t; + +typedef struct +{ + __IO uint32_t SCMF :16; + uint32_t RESERVED16 :16; +} stc_tmr6_scmfr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtdar_field_t; + +typedef struct +{ + __IO uint32_t DTUB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtubr_field_t; + +typedef struct +{ + __IO uint32_t DTDB :16; + uint32_t RESERVED16 :16; +} stc_tmr6_dtdbr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSKVAL : 2; + uint32_t RESERVED20 :12; +} stc_tmr6_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + __IO uint32_t INTENE : 1; + __IO uint32_t INTENF : 1; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDTE : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; + uint32_t RESERVED20 :12; +} stc_tmr6_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPMDA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t EMBVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPMDB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + uint32_t RESERVED25 : 2; + __IO uint32_t EMBVALB : 2; + uint32_t RESERVED29 : 3; +} stc_tmr6_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + __IO uint32_t BSEA : 1; + __IO uint32_t BENB : 1; + __IO uint32_t BSEB : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t BENP : 1; + __IO uint32_t BSEP : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t BENSPA : 1; + __IO uint32_t BSESPA : 1; + uint32_t RESERVED18 : 2; + __IO uint32_t BTRSPA : 2; + uint32_t RESERVED22 : 2; + __IO uint32_t BENSPB : 1; + __IO uint32_t BSESPB : 1; + uint32_t RESERVED26 : 2; + __IO uint32_t BTRSPB : 2; + uint32_t RESERVED30 : 2; +} stc_tmr6_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t DTBENU : 1; + __IO uint32_t DTBEND : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t SEPA : 1; + uint32_t RESERVED9 :23; +} stc_tmr6_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 9; +} stc_tmr6_fconr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t SPPERIA : 1; + __IO uint32_t SPPERIB : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; + uint32_t RESERVED21 :11; +} stc_tmr6_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + __IO uint32_t CMEF : 1; + __IO uint32_t CMFF : 1; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tmr6_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t STARTS : 1; +} stc_tmr6_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t STOPS : 1; +} stc_tmr6_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCLE0 : 1; + __IO uint32_t HCLE1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCLE4 : 1; + __IO uint32_t HCLE5 : 1; + __IO uint32_t HCLE6 : 1; + __IO uint32_t HCLE7 : 1; + __IO uint32_t HCLE8 : 1; + __IO uint32_t HCLE9 : 1; + __IO uint32_t HCLE10 : 1; + __IO uint32_t HCLE11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t CLEARS : 1; +} stc_tmr6_hclrr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + uint32_t RESERVED12 :20; +} stc_tmr6_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + uint32_t RESERVED12 :20; +} stc_tmr6_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + uint32_t RESERVED18 :14; +} stc_tmr6_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + uint32_t RESERVED12 : 4; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + uint32_t RESERVED18 :14; +} stc_tmr6_hcdor_field_t; + +typedef struct +{ + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; + __IO uint32_t SSTA3 : 1; + uint32_t RESERVED3 :13; + __IO uint32_t RESV0 : 1; + uint32_t RESERVED17 : 7; + __IO uint32_t RESV : 1; + uint32_t RESERVED25 : 7; +} stc_tmr6_cr_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; + __IO uint32_t SSTP3 : 1; + uint32_t RESERVED3 :29; +} stc_tmr6_cr_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLE1 : 1; + __IO uint32_t SCLE2 : 1; + __IO uint32_t SCLE3 : 1; + uint32_t RESERVED3 :29; +} stc_tmr6_cr_sclrr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :16; +} stc_tmra_cnter_field_t; + +typedef struct +{ + __IO uint32_t PER :16; + uint32_t RESERVED16 :16; +} stc_tmra_perar_field_t; + +typedef struct +{ + __IO uint32_t CMP :16; + uint32_t RESERVED16 :16; +} stc_tmra_cmpar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t DIR : 1; + __IO uint32_t MODE : 1; + __IO uint32_t SYNST : 1; + __IO uint32_t CKDIV : 4; + uint32_t RESERVED8 : 4; + __IO uint32_t ITENOVF : 1; + __IO uint32_t ITENUDF : 1; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + uint32_t RESERVED16 :16; +} stc_tmra_bcstr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t HCLE0 : 1; + __IO uint32_t HCLE1 : 1; + __IO uint32_t HCLE2 : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t HCLE3 : 1; + __IO uint32_t HCLE4 : 1; + __IO uint32_t HCLE5 : 1; + __IO uint32_t HCLE6 : 1; + uint32_t RESERVED16 :16; +} stc_tmra_hconr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + uint32_t RESERVED13 :19; +} stc_tmra_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + uint32_t RESERVED13 :19; +} stc_tmra_hcdor_field_t; + +typedef struct +{ + __IO uint32_t ITEN1 : 1; + __IO uint32_t ITEN2 : 1; + __IO uint32_t ITEN3 : 1; + __IO uint32_t ITEN4 : 1; + __IO uint32_t ITEN5 : 1; + __IO uint32_t ITEN6 : 1; + __IO uint32_t ITEN7 : 1; + __IO uint32_t ITEN8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_iconr_field_t; + +typedef struct +{ + __IO uint32_t ETEN1 : 1; + __IO uint32_t ETEN2 : 1; + __IO uint32_t ETEN3 : 1; + __IO uint32_t ETEN4 : 1; + __IO uint32_t ETEN5 : 1; + __IO uint32_t ETEN6 : 1; + __IO uint32_t ETEN7 : 1; + __IO uint32_t ETEN8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_econr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENTG : 1; + __IO uint32_t NOFICKTG : 2; + uint32_t RESERVED3 : 5; + __IO uint32_t NOFIENCA : 1; + __IO uint32_t NOFICKCA : 2; + uint32_t RESERVED11 : 1; + __IO uint32_t NOFIENCB : 1; + __IO uint32_t NOFICKCB : 2; + uint32_t RESERVED15 :17; +} stc_tmra_fconr_field_t; + +typedef struct +{ + __IO uint32_t CMPF1 : 1; + __IO uint32_t CMPF2 : 1; + __IO uint32_t CMPF3 : 1; + __IO uint32_t CMPF4 : 1; + __IO uint32_t CMPF5 : 1; + __IO uint32_t CMPF6 : 1; + __IO uint32_t CMPF7 : 1; + __IO uint32_t CMPF8 : 1; + uint32_t RESERVED8 :24; +} stc_tmra_stflr_field_t; + +typedef struct +{ + __IO uint32_t BEN : 1; + __IO uint32_t BSE0 : 1; + __IO uint32_t BSE1 : 1; + uint32_t RESERVED3 :29; +} stc_tmra_bconr_field_t; + +typedef struct +{ + __IO uint32_t CAPMD : 1; + uint32_t RESERVED1 : 3; + __IO uint32_t HICP0 : 1; + __IO uint32_t HICP1 : 1; + __IO uint32_t HICP2 : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t HICP3 : 1; + __IO uint32_t HICP4 : 1; + uint32_t RESERVED10 : 2; + __IO uint32_t NOFIENCP : 1; + __IO uint32_t NOFICKCP : 2; + uint32_t RESERVED15 :17; +} stc_tmra_cconr_field_t; + +typedef struct +{ + __IO uint32_t STAC : 2; + __IO uint32_t STPC : 2; + __IO uint32_t CMPC : 2; + __IO uint32_t PERC : 2; + __IO uint32_t FORC : 2; + uint32_t RESERVED10 : 2; + __IO uint32_t OUTEN : 1; + uint32_t RESERVED13 :19; +} stc_tmra_pconr_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t RUN : 1; + uint32_t RESERVED2 :30; +} stc_trng_cr_field_t; + +typedef struct +{ + __IO uint32_t LOAD : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CNT : 3; + uint32_t RESERVED5 :27; +} stc_trng_mr_field_t; + +typedef struct +{ + __IO uint32_t PE : 1; + __IO uint32_t FE : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t ORE : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t RXNE : 1; + __IO uint32_t TC : 1; + __IO uint32_t TXE : 1; + __IO uint32_t RTOF : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t MPB : 1; + uint32_t RESERVED17 :15; +} stc_usart_sr_field_t; + +typedef struct +{ + __IO uint32_t TDR : 9; + __IO uint32_t MPID : 1; + uint32_t RESERVED10 : 6; + __IO uint32_t RDR : 9; + uint32_t RESERVED25 : 7; +} stc_usart_dr_field_t; + +typedef struct +{ + __IO uint32_t DIV_FRACTION : 7; + uint32_t RESERVED7 : 1; + __IO uint32_t DIV_INTEGER : 8; + uint32_t RESERVED16 :16; +} stc_usart_brr_field_t; + +typedef struct +{ + __IO uint32_t RTOE : 1; + __IO uint32_t RTOIE : 1; + __IO uint32_t RE : 1; + __IO uint32_t TE : 1; + __IO uint32_t SLME : 1; + __IO uint32_t RIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t TXEIE : 1; + uint32_t RESERVED8 : 1; + __IO uint32_t PS : 1; + __IO uint32_t PCE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t M : 1; + uint32_t RESERVED13 : 2; + __IO uint32_t OVER8 : 1; + __IO uint32_t CPE : 1; + __IO uint32_t CFE : 1; + uint32_t RESERVED18 : 1; + __IO uint32_t CORE : 1; + __IO uint32_t CRTOF : 1; + uint32_t RESERVED21 : 3; + __IO uint32_t MS : 1; + uint32_t RESERVED25 : 3; + __IO uint32_t ML : 1; + __IO uint32_t FBME : 1; + __IO uint32_t NFE : 1; + __IO uint32_t SBS : 1; +} stc_usart_cr1_field_t; + +typedef struct +{ + __IO uint32_t MPE : 1; + uint32_t RESERVED1 :10; + __IO uint32_t CLKC : 2; + __IO uint32_t STOP : 1; + uint32_t RESERVED14 :18; +} stc_usart_cr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t SCEN : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t CTSE : 1; + uint32_t RESERVED10 :11; + __IO uint32_t BCN : 3; + uint32_t RESERVED24 : 8; +} stc_usart_cr3_field_t; + +typedef struct +{ + __IO uint32_t PSC : 2; + uint32_t RESERVED2 :30; +} stc_usart_pr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 6; + __IO uint32_t VBUSOVEN : 1; + __IO uint32_t VBUSVAL : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_usbfs_gvbuscfg_field_t; + +typedef struct +{ + __IO uint32_t GINTMSK : 1; + __IO uint32_t HBSTLEN : 4; + __IO uint32_t DMAEN : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXFELVL : 1; + __IO uint32_t PTXFELVL : 1; + uint32_t RESERVED9 :23; +} stc_usbfs_gahbcfg_field_t; + +typedef struct +{ + __IO uint32_t TOCAL : 3; + uint32_t RESERVED3 : 3; + __IO uint32_t PHYSEL : 1; + uint32_t RESERVED7 : 3; + __IO uint32_t TRDT : 4; + uint32_t RESERVED14 :15; + __IO uint32_t FHMOD : 1; + __IO uint32_t FDMOD : 1; + uint32_t RESERVED31 : 1; +} stc_usbfs_gusbcfg_field_t; + +typedef struct +{ + __IO uint32_t CSRST : 1; + __IO uint32_t HSRST : 1; + __IO uint32_t FCRST : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t RXFFLSH : 1; + __IO uint32_t TXFFLSH : 1; + __IO uint32_t TXFNUM : 5; + uint32_t RESERVED11 :19; + __IO uint32_t DMAREQ : 1; + __IO uint32_t AHBIDL : 1; +} stc_usbfs_grstctl_field_t; + +typedef struct +{ + __IO uint32_t CMOD : 1; + __IO uint32_t MMIS : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SOF : 1; + __IO uint32_t RXFNE : 1; + __IO uint32_t NPTXFE : 1; + __IO uint32_t GINAKEFF : 1; + __IO uint32_t GONAKEFF : 1; + uint32_t RESERVED8 : 2; + __IO uint32_t ESUSP : 1; + __IO uint32_t USBSUSP : 1; + __IO uint32_t USBRST : 1; + __IO uint32_t ENUMDNE : 1; + __IO uint32_t ISOODRP : 1; + __IO uint32_t EOPF : 1; + uint32_t RESERVED16 : 2; + __IO uint32_t IEPINT : 1; + __IO uint32_t OEPINT : 1; + __IO uint32_t IISOIXFR : 1; + __IO uint32_t IPXFR_INCOMPISOOUT : 1; + __IO uint32_t DATAFSUSP : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t HPRTINT : 1; + __IO uint32_t HCINT : 1; + __IO uint32_t PTXFE : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t CIDSCHG : 1; + __IO uint32_t DISCINT : 1; + __IO uint32_t VBUSVINT : 1; + __IO uint32_t WKUINT : 1; +} stc_usbfs_gintsts_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t MMISM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t SOFM : 1; + __IO uint32_t RXFNEM : 1; + __IO uint32_t NPTXFEM : 1; + __IO uint32_t GINAKEFFM : 1; + __IO uint32_t GONAKEFFM : 1; + uint32_t RESERVED8 : 2; + __IO uint32_t ESUSPM : 1; + __IO uint32_t USBSUSPM : 1; + __IO uint32_t USBRSTM : 1; + __IO uint32_t ENUMDNEM : 1; + __IO uint32_t ISOODRPM : 1; + __IO uint32_t EOPFM : 1; + uint32_t RESERVED16 : 2; + __IO uint32_t IEPIM : 1; + __IO uint32_t OEPIM : 1; + __IO uint32_t IISOIXFRM : 1; + __IO uint32_t IPXFRM_INCOMPISOOUTM : 1; + __IO uint32_t DATAFSUSPM : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t HPRTIM : 1; + __IO uint32_t HCIM : 1; + __IO uint32_t PTXFEM : 1; + uint32_t RESERVED27 : 1; + __IO uint32_t CIDSCHGM : 1; + __IO uint32_t DISCIM : 1; + __IO uint32_t VBUSVIM : 1; + __IO uint32_t WKUIM : 1; +} stc_usbfs_gintmsk_field_t; + +typedef struct +{ + __IO uint32_t CHNUM_EPNUM : 4; + __IO uint32_t BCNT :11; + __IO uint32_t DPID : 2; + __IO uint32_t PKTSTS : 4; + uint32_t RESERVED21 :11; +} stc_usbfs_grxstsr_field_t; + +typedef struct +{ + __IO uint32_t CHNUM_EPNUM : 4; + __IO uint32_t BCNT :11; + __IO uint32_t DPID : 2; + __IO uint32_t PKTSTS : 4; + uint32_t RESERVED21 :11; +} stc_usbfs_grxstsp_field_t; + +typedef struct +{ + __IO uint32_t RXFD :11; + uint32_t RESERVED11 :21; +} stc_usbfs_grxfsiz_field_t; + +typedef struct +{ + __IO uint32_t NPTXFSA :16; + __IO uint32_t NPTXFD :16; +} stc_usbfs_hnptxfsiz_field_t; + +typedef struct +{ + __IO uint32_t NPTXFSAV :16; + __IO uint32_t NPTQXSAV : 8; + __IO uint32_t NPTXQTOP : 7; + uint32_t RESERVED31 : 1; +} stc_usbfs_hnptxsts_field_t; + +typedef struct +{ + __IO uint32_t PTXSA :12; + uint32_t RESERVED12 : 4; + __IO uint32_t PTXFD :11; + uint32_t RESERVED27 : 5; +} stc_usbfs_hptxfsiz_field_t; + +typedef struct +{ + __IO uint32_t INEPTXSA :12; + uint32_t RESERVED12 : 4; + __IO uint32_t INEPTXFD :10; + uint32_t RESERVED26 : 6; +} stc_usbfs_dieptxf_field_t; + +typedef struct +{ + __IO uint32_t FSLSPCS : 2; + __IO uint32_t FSLSS : 1; + uint32_t RESERVED3 :29; +} stc_usbfs_hcfg_field_t; + +typedef struct +{ + __IO uint32_t FRIVL :16; + uint32_t RESERVED16 :16; +} stc_usbfs_hfir_field_t; + +typedef struct +{ + __IO uint32_t FRNUM :16; + __IO uint32_t FTREM :16; +} stc_usbfs_hfnum_field_t; + +typedef struct +{ + __IO uint32_t PTXFSAVL :16; + __IO uint32_t PTXQSAV : 8; + __IO uint32_t PTXQTOP : 8; +} stc_usbfs_hptxsts_field_t; + +typedef struct +{ + __IO uint32_t HAINT :12; + uint32_t RESERVED12 :20; +} stc_usbfs_haint_field_t; + +typedef struct +{ + __IO uint32_t HAINTM :12; + uint32_t RESERVED12 :20; +} stc_usbfs_haintmsk_field_t; + +typedef struct +{ + __IO uint32_t PCSTS : 1; + __IO uint32_t PCDET : 1; + __IO uint32_t PENA : 1; + __IO uint32_t PENCHNG : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t PRES : 1; + __IO uint32_t PSUSP : 1; + __IO uint32_t PRST : 1; + uint32_t RESERVED9 : 1; + __IO uint32_t PLSTS : 2; + __IO uint32_t PWPR : 1; + uint32_t RESERVED13 : 4; + __IO uint32_t PSPD : 2; + uint32_t RESERVED19 :13; +} stc_usbfs_hprt_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + __IO uint32_t EPNUM : 4; + __IO uint32_t EPDIR : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t LSDEV : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 2; + __IO uint32_t DAD : 7; + __IO uint32_t ODDFRM : 1; + __IO uint32_t CHDIS : 1; + __IO uint32_t CHENA : 1; +} stc_usbfs_hcchar_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t CHH : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t NAK : 1; + __IO uint32_t ACK : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXERR : 1; + __IO uint32_t BBERR : 1; + __IO uint32_t FRMOR : 1; + __IO uint32_t DTERR : 1; + uint32_t RESERVED11 :21; +} stc_usbfs_hcint_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t CHHM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STALLM : 1; + __IO uint32_t NAKM : 1; + __IO uint32_t ACKM : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t TXERRM : 1; + __IO uint32_t BBERRM : 1; + __IO uint32_t FRMORM : 1; + __IO uint32_t DTERRM : 1; + uint32_t RESERVED11 :21; +} stc_usbfs_hcintmsk_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + __IO uint32_t DPID : 2; + uint32_t RESERVED31 : 1; +} stc_usbfs_hctsiz_field_t; + +typedef struct +{ + __IO uint32_t DSPD : 2; + __IO uint32_t NZLSOHSK : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t DAD : 7; + __IO uint32_t PFIVL : 2; + uint32_t RESERVED13 :19; +} stc_usbfs_dcfg_field_t; + +typedef struct +{ + __IO uint32_t RWUSIG : 1; + __IO uint32_t SDIS : 1; + __IO uint32_t GINSTS : 1; + __IO uint32_t GONSTS : 1; + uint32_t RESERVED4 : 3; + __IO uint32_t SGINAK : 1; + __IO uint32_t CGINAK : 1; + __IO uint32_t SGONAK : 1; + __IO uint32_t CGONAK : 1; + __IO uint32_t POPRGDNE : 1; + uint32_t RESERVED12 :20; +} stc_usbfs_dctl_field_t; + +typedef struct +{ + __IO uint32_t SUSPSTS : 1; + __IO uint32_t ENUMSPD : 2; + __IO uint32_t EERR : 1; + uint32_t RESERVED4 : 4; + __IO uint32_t FNSOF :14; + uint32_t RESERVED22 :10; +} stc_usbfs_dsts_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t EPDM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOM : 1; + __IO uint32_t ITTXFEMSK : 1; + __IO uint32_t INEPNMM : 1; + __IO uint32_t INEPNEM : 1; + uint32_t RESERVED7 :25; +} stc_usbfs_diepmsk_field_t; + +typedef struct +{ + __IO uint32_t XFRCM : 1; + __IO uint32_t EPDM : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STUPM : 1; + __IO uint32_t OTEPDM : 1; + uint32_t RESERVED5 :27; +} stc_usbfs_doepmsk_field_t; + +typedef struct +{ + __IO uint32_t IEPINT : 6; + uint32_t RESERVED6 :10; + __IO uint32_t OEPINT : 6; + uint32_t RESERVED22 :10; +} stc_usbfs_daint_field_t; + +typedef struct +{ + __IO uint32_t IEPINTM : 6; + uint32_t RESERVED6 :10; + __IO uint32_t OEPINTM : 6; + uint32_t RESERVED22 :10; +} stc_usbfs_daintmsk_field_t; + +typedef struct +{ + __IO uint32_t INEPTXFEM : 6; + uint32_t RESERVED6 :26; +} stc_usbfs_diepempmsk_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ : 2; + uint32_t RESERVED2 :13; + __IO uint32_t USBAEP : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t TXFNUM : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + uint32_t RESERVED28 : 2; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_diepctl0_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOC : 1; + __IO uint32_t TTXFE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t INEPNE : 1; + __IO uint32_t TXFE : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_diepint0_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ : 7; + uint32_t RESERVED7 :12; + __IO uint32_t PKTCNT : 2; + uint32_t RESERVED21 :11; +} stc_usbfs_dieptsiz0_field_t; + +typedef struct +{ + __IO uint32_t INEPTFSAV :16; + uint32_t RESERVED16 :16; +} stc_usbfs_dtxfsts0_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + uint32_t RESERVED11 : 4; + __IO uint32_t USBAEP : 1; + __IO uint32_t EONUM_DPID : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + uint32_t RESERVED20 : 1; + __IO uint32_t STALL : 1; + __IO uint32_t TXFNUM : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + __IO uint32_t SD0PID_SEVNFRM : 1; + __IO uint32_t SODDFRM : 1; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_diepctl_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t TOC : 1; + __IO uint32_t TTXFE : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t INEPNE : 1; + __IO uint32_t TXFE : 1; + uint32_t RESERVED8 :24; +} stc_usbfs_diepint_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + uint32_t RESERVED29 : 3; +} stc_usbfs_dieptsiz_field_t; + +typedef struct +{ + __IO uint32_t INEPTFSAV :16; + uint32_t RESERVED16 :16; +} stc_usbfs_dtxfsts_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ : 2; + uint32_t RESERVED2 :13; + __IO uint32_t USBAEP : 1; + uint32_t RESERVED16 : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + __IO uint32_t SNPM : 1; + __IO uint32_t STALL : 1; + uint32_t RESERVED22 : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + uint32_t RESERVED28 : 2; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_doepctl0_field_t; + +typedef struct +{ + __IO uint32_t XFRC : 1; + __IO uint32_t EPDISD : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t STUP : 1; + __IO uint32_t OTEPDIS : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t B2BSTUP : 1; + uint32_t RESERVED7 :25; +} stc_usbfs_doepint_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ : 7; + uint32_t RESERVED7 :12; + __IO uint32_t PKTCNT : 1; + uint32_t RESERVED20 : 9; + __IO uint32_t STUPCNT : 2; + uint32_t RESERVED31 : 1; +} stc_usbfs_doeptsiz0_field_t; + +typedef struct +{ + __IO uint32_t MPSIZ :11; + uint32_t RESERVED11 : 4; + __IO uint32_t USBAEP : 1; + __IO uint32_t DPID : 1; + __IO uint32_t NAKSTS : 1; + __IO uint32_t EPTYP : 2; + __IO uint32_t SNPM : 1; + __IO uint32_t STALL : 1; + uint32_t RESERVED22 : 4; + __IO uint32_t CNAK : 1; + __IO uint32_t SNAK : 1; + __IO uint32_t SD0PID : 1; + __IO uint32_t SD1PID : 1; + __IO uint32_t EPDIS : 1; + __IO uint32_t EPENA : 1; +} stc_usbfs_doepctl_field_t; + +typedef struct +{ + __IO uint32_t XFRSIZ :19; + __IO uint32_t PKTCNT :10; + uint32_t RESERVED29 : 3; +} stc_usbfs_doeptsiz_field_t; + +typedef struct +{ + __IO uint32_t STPPCLK : 1; + __IO uint32_t GATEHCLK : 1; + uint32_t RESERVED2 :30; +} stc_usbfs_pcgcctl_field_t; + +typedef struct +{ + __IO uint32_t PERI : 2; + uint32_t RESERVED2 : 2; + __IO uint32_t CKS : 4; + __IO uint32_t WDPT : 4; + uint32_t RESERVED12 : 4; + __IO uint32_t SLPOFF : 1; + uint32_t RESERVED17 :14; + __IO uint32_t ITS : 1; +} stc_wdt_cr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + __IO uint32_t UDF : 1; + __IO uint32_t REF : 1; + uint32_t RESERVED18 :14; +} stc_wdt_sr_field_t; + +typedef struct +{ + __IO uint32_t RF :16; + uint32_t RESERVED16 :16; +} stc_wdt_rr_field_t; + +typedef struct +{ + __IO uint16_t WKTMCMP :12; + __IO uint16_t WKOVF : 1; + __IO uint16_t WKCKS : 2; + __IO uint16_t WKTCE : 1; +} stc_wktm_cr_field_t; + + +typedef struct +{ + union + { + __IO uint8_t STR; + stc_adc_str_field_t STR_f; + }; + uint8_t RESERVED1[1]; + union + { + __IO uint16_t CR0; + stc_adc_cr0_field_t CR0_f; + }; + union + { + __IO uint16_t CR1; + stc_adc_cr1_field_t CR1_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint16_t TRGSR; + stc_adc_trgsr_field_t TRGSR_f; + }; + __IO uint16_t CHSELRA0; + union + { + __IO uint16_t CHSELRA1; + stc_adc_chselra1_field_t CHSELRA1_f; + }; + __IO uint16_t CHSELRB0; + union + { + __IO uint16_t CHSELRB1; + stc_adc_chselrb1_field_t CHSELRB1_f; + }; + __IO uint16_t AVCHSELR0; + union + { + __IO uint16_t AVCHSELR1; + stc_adc_avchselr1_field_t AVCHSELR1_f; + }; + uint8_t RESERVED10[8]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED27[7]; + union + { + __IO uint16_t CHMUXR0; + stc_adc_chmuxr0_field_t CHMUXR0_f; + }; + union + { + __IO uint16_t CHMUXR1; + stc_adc_chmuxr1_field_t CHMUXR1_f; + }; + union + { + __IO uint16_t CHMUXR2; + stc_adc_chmuxr2_field_t CHMUXR2_f; + }; + union + { + __IO uint16_t CHMUXR3; + stc_adc_chmuxr3_field_t CHMUXR3_f; + }; + uint8_t RESERVED31[6]; + union + { + __IO uint8_t ISR; + stc_adc_isr_field_t ISR_f; + }; + union + { + __IO uint8_t ICR; + stc_adc_icr_field_t ICR_f; + }; + uint8_t RESERVED33[4]; + union + { + __IO uint16_t SYNCCR; + stc_adc_synccr_field_t SYNCCR_f; + }; + uint8_t RESERVED34[2]; + __IO uint16_t DR0; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t DR3; + __IO uint16_t DR4; + __IO uint16_t DR5; + __IO uint16_t DR6; + __IO uint16_t DR7; + __IO uint16_t DR8; + __IO uint16_t DR9; + __IO uint16_t DR10; + __IO uint16_t DR11; + __IO uint16_t DR12; + __IO uint16_t DR13; + __IO uint16_t DR14; + __IO uint16_t DR15; + __IO uint16_t DR16; + uint8_t RESERVED51[46]; + union + { + __IO uint16_t AWDCR; + stc_adc_awdcr_field_t AWDCR_f; + }; + uint8_t RESERVED52[2]; + __IO uint16_t AWDDR0; + __IO uint16_t AWDDR1; + uint8_t RESERVED54[4]; + __IO uint16_t AWDCHSR0; + union + { + __IO uint16_t AWDCHSR1; + stc_adc_awdchsr1_field_t AWDCHSR1_f; + }; + __IO uint16_t AWDSR0; + union + { + __IO uint16_t AWDSR1; + stc_adc_awdsr1_field_t AWDSR1_f; + }; + uint8_t RESERVED58[12]; + union + { + __IO uint16_t PGACR; + stc_adc_pgacr_field_t PGACR_f; + }; + union + { + __IO uint16_t PGAGSR; + stc_adc_pgagsr_field_t PGAGSR_f; + }; + uint8_t RESERVED60[8]; + union + { + __IO uint16_t PGAINSR0; + stc_adc_pgainsr0_field_t PGAINSR0_f; + }; + union + { + __IO uint16_t PGAINSR1; + stc_adc_pgainsr1_field_t PGAINSR1_f; + }; +}M4_ADC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_aes_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; +}M4_AES_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t INT_SFTTRG; + stc_aos_int_sfttrg_field_t INT_SFTTRG_f; + }; + union + { + __IO uint32_t DCU1_TRGSEL; + stc_aos_dcu1_trgsel_field_t DCU1_TRGSEL_f; + }; + union + { + __IO uint32_t DCU2_TRGSEL; + stc_aos_dcu2_trgsel_field_t DCU2_TRGSEL_f; + }; + union + { + __IO uint32_t DCU3_TRGSEL; + stc_aos_dcu3_trgsel_field_t DCU3_TRGSEL_f; + }; + union + { + __IO uint32_t DCU4_TRGSEL; + stc_aos_dcu4_trgsel_field_t DCU4_TRGSEL_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL0; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL0_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL1; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL1_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL2; + stc_aos_dma1_trgsel_field_t DMA1_TRGSEL2_f; + }; + union + { + __IO uint32_t DMA1_TRGSEL3; + stc_aos_dma1_trgsel3_field_t DMA1_TRGSEL3_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL0; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL0_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL1; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL1_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL2; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL2_f; + }; + union + { + __IO uint32_t DMA2_TRGSEL3; + stc_aos_dma2_trgsel_field_t DMA2_TRGSEL3_f; + }; + union + { + __IO uint32_t DMA_TRGSELRC; + stc_aos_dma_trgselrc_field_t DMA_TRGSELRC_f; + }; + union + { + __IO uint32_t TMR6_HTSSR1; + stc_aos_tmr6_htssr_field_t TMR6_HTSSR1_f; + }; + union + { + __IO uint32_t TMR6_HTSSR2; + stc_aos_tmr6_htssr_field_t TMR6_HTSSR2_f; + }; + union + { + __IO uint32_t TMR0_HTSSR; + stc_aos_tmr0_htssr_field_t TMR0_HTSSR_f; + }; + union + { + __IO uint32_t PORT_PEVNTTRGSR12; + stc_aos_port_pevnttrgsr12_field_t PORT_PEVNTTRGSR12_f; + }; + union + { + __IO uint32_t PORT_PEVNTTRGSR34; + stc_aos_port_pevnttrgsr34_field_t PORT_PEVNTTRGSR34_f; + }; + union + { + __IO uint32_t TMRA_HTSSR0; + stc_aos_tmra_htssr_field_t TMRA_HTSSR0_f; + }; + union + { + __IO uint32_t TMRA_HTSSR1; + stc_aos_tmra_htssr_field_t TMRA_HTSSR1_f; + }; + union + { + __IO uint32_t OTS_TRG; + stc_aos_ots_trg_field_t OTS_TRG_f; + }; + union + { + __IO uint32_t ADC1_ITRGSELR0; + stc_aos_adc1_itrgselr_field_t ADC1_ITRGSELR0_f; + }; + union + { + __IO uint32_t ADC1_ITRGSELR1; + stc_aos_adc1_itrgselr_field_t ADC1_ITRGSELR1_f; + }; + union + { + __IO uint32_t ADC2_ITRGSELR0; + stc_aos_adc2_itrgselr_field_t ADC2_ITRGSELR0_f; + }; + union + { + __IO uint32_t ADC2_ITRGSELR1; + stc_aos_adc2_itrgselr_field_t ADC2_ITRGSELR1_f; + }; + union + { + __IO uint32_t COMTRG1; + stc_aos_comtrg1_field_t COMTRG1_f; + }; + union + { + __IO uint32_t COMTRG2; + stc_aos_comtrg2_field_t COMTRG2_f; + }; + uint8_t RESERVED28[144]; + union + { + __IO uint32_t PEVNTDIRR1; + stc_aos_pevntdirr_field_t PEVNTDIRR1_f; + }; + union + { + __IO uint32_t PEVNTIDR1; + stc_aos_pevntidr_field_t PEVNTIDR1_f; + }; + union + { + __IO uint32_t PEVNTODR1; + stc_aos_pevntodr_field_t PEVNTODR1_f; + }; + union + { + __IO uint32_t PEVNTORR1; + stc_aos_pevntorr_field_t PEVNTORR1_f; + }; + union + { + __IO uint32_t PEVNTOSR1; + stc_aos_pevntosr_field_t PEVNTOSR1_f; + }; + union + { + __IO uint32_t PEVNTRISR1; + stc_aos_pevntrisr_field_t PEVNTRISR1_f; + }; + union + { + __IO uint32_t PEVNTFAL1; + stc_aos_pevntfal_field_t PEVNTFAL1_f; + }; + union + { + __IO uint32_t PEVNTDIRR2; + stc_aos_pevntdirr_field_t PEVNTDIRR2_f; + }; + union + { + __IO uint32_t PEVNTIDR2; + stc_aos_pevntidr_field_t PEVNTIDR2_f; + }; + union + { + __IO uint32_t PEVNTODR2; + stc_aos_pevntodr_field_t PEVNTODR2_f; + }; + union + { + __IO uint32_t PEVNTORR2; + stc_aos_pevntorr_field_t PEVNTORR2_f; + }; + union + { + __IO uint32_t PEVNTOSR2; + stc_aos_pevntosr_field_t PEVNTOSR2_f; + }; + union + { + __IO uint32_t PEVNTRISR2; + stc_aos_pevntrisr_field_t PEVNTRISR2_f; + }; + union + { + __IO uint32_t PEVNTFAL2; + stc_aos_pevntfal_field_t PEVNTFAL2_f; + }; + union + { + __IO uint32_t PEVNTDIRR3; + stc_aos_pevntdirr_field_t PEVNTDIRR3_f; + }; + union + { + __IO uint32_t PEVNTIDR3; + stc_aos_pevntidr_field_t PEVNTIDR3_f; + }; + union + { + __IO uint32_t PEVNTODR3; + stc_aos_pevntodr_field_t PEVNTODR3_f; + }; + union + { + __IO uint32_t PEVNTORR3; + stc_aos_pevntorr_field_t PEVNTORR3_f; + }; + union + { + __IO uint32_t PEVNTOSR3; + stc_aos_pevntosr_field_t PEVNTOSR3_f; + }; + union + { + __IO uint32_t PEVNTRISR3; + stc_aos_pevntrisr_field_t PEVNTRISR3_f; + }; + union + { + __IO uint32_t PEVNTFAL3; + stc_aos_pevntfal_field_t PEVNTFAL3_f; + }; + union + { + __IO uint32_t PEVNTDIRR4; + stc_aos_pevntdirr_field_t PEVNTDIRR4_f; + }; + union + { + __IO uint32_t PEVNTIDR4; + stc_aos_pevntidr_field_t PEVNTIDR4_f; + }; + union + { + __IO uint32_t PEVNTODR4; + stc_aos_pevntodr_field_t PEVNTODR4_f; + }; + union + { + __IO uint32_t PEVNTORR4; + stc_aos_pevntorr_field_t PEVNTORR4_f; + }; + union + { + __IO uint32_t PEVNTOSR4; + stc_aos_pevntosr_field_t PEVNTOSR4_f; + }; + union + { + __IO uint32_t PEVNTRISR4; + stc_aos_pevntrisr_field_t PEVNTRISR4_f; + }; + union + { + __IO uint32_t PEVNTFAL4; + stc_aos_pevntfal_field_t PEVNTFAL4_f; + }; + union + { + __IO uint32_t PEVNTNFCR; + stc_aos_pevntnfcr_field_t PEVNTNFCR_f; + }; +}M4_AOS_TypeDef; + +typedef struct +{ + __IO uint32_t RBUF; + uint8_t RESERVED1[76]; + __IO uint32_t TBUF; + uint8_t RESERVED2[76]; + union + { + __IO uint8_t CFG_STAT; + stc_can_cfg_stat_field_t CFG_STAT_f; + }; + union + { + __IO uint8_t TCMD; + stc_can_tcmd_field_t TCMD_f; + }; + union + { + __IO uint8_t TCTRL; + stc_can_tctrl_field_t TCTRL_f; + }; + union + { + __IO uint8_t RCTRL; + stc_can_rctrl_field_t RCTRL_f; + }; + union + { + __IO uint8_t RTIE; + stc_can_rtie_field_t RTIE_f; + }; + union + { + __IO uint8_t RTIF; + stc_can_rtif_field_t RTIF_f; + }; + union + { + __IO uint8_t ERRINT; + stc_can_errint_field_t ERRINT_f; + }; + union + { + __IO uint8_t LIMIT; + stc_can_limit_field_t LIMIT_f; + }; + union + { + __IO uint32_t BT; + stc_can_bt_field_t BT_f; + }; + uint8_t RESERVED11[4]; + union + { + __IO uint8_t EALCAP; + stc_can_ealcap_field_t EALCAP_f; + }; + uint8_t RESERVED12[1]; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + union + { + __IO uint8_t ACFCTRL; + stc_can_acfctrl_field_t ACFCTRL_f; + }; + uint8_t RESERVED15[1]; + union + { + __IO uint8_t ACFEN; + stc_can_acfen_field_t ACFEN_f; + }; + uint8_t RESERVED16[1]; + union + { + __IO uint32_t ACF; + stc_can_acf_field_t ACF_f; + }; + uint8_t RESERVED17[2]; + union + { + __IO uint8_t TBSLOT; + stc_can_tbslot_field_t TBSLOT_f; + }; + union + { + __IO uint8_t TTCFG; + stc_can_ttcfg_field_t TTCFG_f; + }; + union + { + __IO uint32_t REF_MSG; + stc_can_ref_msg_field_t REF_MSG_f; + }; + union + { + __IO uint16_t TRG_CFG; + stc_can_trg_cfg_field_t TRG_CFG_f; + }; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +}M4_CAN_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CTRL; + stc_cmp_ctrl_field_t CTRL_f; + }; + union + { + __IO uint16_t VLTSEL; + stc_cmp_vltsel_field_t VLTSEL_f; + }; + union + { + __IO uint16_t MON; + stc_cmp_mon_field_t MON_f; + }; + union + { + __IO uint16_t CVSSTB; + stc_cmp_cvsstb_field_t CVSSTB_f; + }; + union + { + __IO uint16_t CVSPRD; + stc_cmp_cvsprd_field_t CVSPRD_f; + }; +}M4_CMP_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[256]; + union + { + __IO uint16_t DADR1; + stc_cmp_cr_dadr1_field_t DADR1_f; + }; + union + { + __IO uint16_t DADR2; + stc_cmp_cr_dadr2_field_t DADR2_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint16_t DACR; + stc_cmp_cr_dacr_field_t DACR_f; + }; + uint8_t RESERVED3[2]; + union + { + __IO uint16_t RVADC; + stc_cmp_cr_rvadc_field_t RVADC_f; + }; +}M4_CMP_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_crc_cr_field_t CR_f; + }; + __IO uint32_t RESLT; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t FLG; + stc_crc_flg_field_t FLG_f; + }; + uint8_t RESERVED3[112]; + __IO uint32_t DAT0; + __IO uint32_t DAT1; + __IO uint32_t DAT2; + __IO uint32_t DAT3; + __IO uint32_t DAT4; + __IO uint32_t DAT5; + __IO uint32_t DAT6; + __IO uint32_t DAT7; + __IO uint32_t DAT8; + __IO uint32_t DAT9; + __IO uint32_t DAT10; + __IO uint32_t DAT11; + __IO uint32_t DAT12; + __IO uint32_t DAT13; + __IO uint32_t DAT14; + __IO uint32_t DAT15; + __IO uint32_t DAT16; + __IO uint32_t DAT17; + __IO uint32_t DAT18; + __IO uint32_t DAT19; + __IO uint32_t DAT20; + __IO uint32_t DAT21; + __IO uint32_t DAT22; + __IO uint32_t DAT23; + __IO uint32_t DAT24; + __IO uint32_t DAT25; + __IO uint32_t DAT26; + __IO uint32_t DAT27; + __IO uint32_t DAT28; + __IO uint32_t DAT29; + __IO uint32_t DAT30; + __IO uint32_t DAT31; +}M4_CRC_TypeDef; + +typedef struct +{ + __IO uint32_t AUTHID0; + __IO uint32_t AUTHID1; + __IO uint32_t AUTHID2; + __IO uint32_t RESV0; + union + { + __IO uint32_t MCUSTAT; + stc_dbgc_mcustat_field_t MCUSTAT_f; + }; + union + { + __IO uint32_t MCUCTL; + stc_dbgc_mcuctl_field_t MCUCTL_f; + }; + union + { + __IO uint32_t FMCCTL; + stc_dbgc_fmcctl_field_t FMCCTL_f; + }; + union + { + __IO uint32_t MCUDBGSTAT; + stc_dbgc_mcudbgstat_field_t MCUDBGSTAT_f; + }; + union + { + __IO uint32_t MCUSTPCTL; + stc_dbgc_mcustpctl_field_t MCUSTPCTL_f; + }; + union + { + __IO uint32_t MCUTRACECTL; + stc_dbgc_mcutracectl_field_t MCUTRACECTL_f; + }; +}M4_DBGC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTL; + stc_dcu_ctl_field_t CTL_f; + }; + union + { + __IO uint32_t FLAG; + stc_dcu_flag_field_t FLAG_f; + }; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + union + { + __IO uint32_t FLAGCLR; + stc_dcu_flagclr_field_t FLAGCLR_f; + }; + union + { + __IO uint32_t INTSEL; + stc_dcu_intsel_field_t INTSEL_f; + }; +}M4_DCU_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t EN; + stc_dma_en_field_t EN_f; + }; + union + { + __IO uint32_t INTSTAT0; + stc_dma_intstat0_field_t INTSTAT0_f; + }; + union + { + __IO uint32_t INTSTAT1; + stc_dma_intstat1_field_t INTSTAT1_f; + }; + union + { + __IO uint32_t INTMASK0; + stc_dma_intmask0_field_t INTMASK0_f; + }; + union + { + __IO uint32_t INTMASK1; + stc_dma_intmask1_field_t INTMASK1_f; + }; + union + { + __IO uint32_t INTCLR0; + stc_dma_intclr0_field_t INTCLR0_f; + }; + union + { + __IO uint32_t INTCLR1; + stc_dma_intclr1_field_t INTCLR1_f; + }; + union + { + __IO uint32_t CHEN; + stc_dma_chen_field_t CHEN_f; + }; + uint8_t RESERVED8[4]; + union + { + __IO uint32_t CHSTAT; + stc_dma_chstat_field_t CHSTAT_f; + }; + uint8_t RESERVED9[4]; + union + { + __IO uint32_t RCFGCTL; + stc_dma_rcfgctl_field_t RCFGCTL_f; + }; + uint8_t RESERVED10[16]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + union + { + __IO uint32_t DTCTL0; + stc_dma_dtctl_field_t DTCTL0_f; + }; + union + { + __IO uint32_t RPT0; + stc_dma_rpt_field_t RPT0_f; + __IO uint32_t RPTB0; + stc_dma_rptb_field_t RPTB0_f; + }; + union + { + __IO uint32_t SNSEQCTL0; + stc_dma_snseqctl_field_t SNSEQCTL0_f; + __IO uint32_t SNSEQCTLB0; + stc_dma_snseqctlb_field_t SNSEQCTLB0_f; + }; + union + { + __IO uint32_t DNSEQCTL0; + stc_dma_dnseqctl_field_t DNSEQCTL0_f; + __IO uint32_t DNSEQCTLB0; + stc_dma_dnseqctlb_field_t DNSEQCTLB0_f; + }; + union + { + __IO uint32_t LLP0; + stc_dma_llp_field_t LLP0_f; + }; + union + { + __IO uint32_t CH0CTL; + stc_dma_ch0ctl_field_t CH0CTL_f; + }; + __IO uint32_t MONSAR0; + __IO uint32_t MONDAR0; + union + { + __IO uint32_t MONDTCTL0; + stc_dma_mondtctl_field_t MONDTCTL0_f; + }; + union + { + __IO uint32_t MONRPT0; + stc_dma_monrpt_field_t MONRPT0_f; + }; + union + { + __IO uint32_t MONSNSEQCTL0; + stc_dma_monsnseqctl_field_t MONSNSEQCTL0_f; + }; + union + { + __IO uint32_t MONDNSEQCTL0; + stc_dma_mondnseqctl_field_t MONDNSEQCTL0_f; + }; + uint8_t RESERVED27[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + union + { + __IO uint32_t DTCTL1; + stc_dma_dtctl_field_t DTCTL1_f; + }; + union + { + __IO uint32_t RPT1; + stc_dma_rpt_field_t RPT1_f; + __IO uint32_t RPTB1; + stc_dma_rptb_field_t RPTB1_f; + }; + union + { + __IO uint32_t SNSEQCTL1; + stc_dma_snseqctl_field_t SNSEQCTL1_f; + __IO uint32_t SNSEQCTLB1; + stc_dma_snseqctlb_field_t SNSEQCTLB1_f; + }; + union + { + __IO uint32_t DNSEQCTL1; + stc_dma_dnseqctl_field_t DNSEQCTL1_f; + __IO uint32_t DNSEQCTLB1; + stc_dma_dnseqctlb_field_t DNSEQCTLB1_f; + }; + union + { + __IO uint32_t LLP1; + stc_dma_llp_field_t LLP1_f; + }; + union + { + __IO uint32_t CH1CTL; + stc_dma_ch1ctl_field_t CH1CTL_f; + }; + __IO uint32_t MONSAR1; + __IO uint32_t MONDAR1; + union + { + __IO uint32_t MONDTCTL1; + stc_dma_mondtctl_field_t MONDTCTL1_f; + }; + union + { + __IO uint32_t MONRPT1; + stc_dma_monrpt_field_t MONRPT1_f; + }; + union + { + __IO uint32_t MONSNSEQCTL1; + stc_dma_monsnseqctl_field_t MONSNSEQCTL1_f; + }; + union + { + __IO uint32_t MONDNSEQCTL1; + stc_dma_mondnseqctl_field_t MONDNSEQCTL1_f; + }; + uint8_t RESERVED44[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + union + { + __IO uint32_t DTCTL2; + stc_dma_dtctl_field_t DTCTL2_f; + }; + union + { + __IO uint32_t RPT2; + stc_dma_rpt_field_t RPT2_f; + __IO uint32_t RPTB2; + stc_dma_rptb_field_t RPTB2_f; + }; + union + { + __IO uint32_t SNSEQCTL2; + stc_dma_snseqctl_field_t SNSEQCTL2_f; + __IO uint32_t SNSEQCTLB2; + stc_dma_snseqctlb_field_t SNSEQCTLB2_f; + }; + union + { + __IO uint32_t DNSEQCTL2; + stc_dma_dnseqctl_field_t DNSEQCTL2_f; + __IO uint32_t DNSEQCTLB2; + stc_dma_dnseqctlb_field_t DNSEQCTLB2_f; + }; + union + { + __IO uint32_t LLP2; + stc_dma_llp_field_t LLP2_f; + }; + union + { + __IO uint32_t CH2CTL; + stc_dma_ch2ctl_field_t CH2CTL_f; + }; + __IO uint32_t MONSAR2; + __IO uint32_t MONDAR2; + union + { + __IO uint32_t MONDTCTL2; + stc_dma_mondtctl_field_t MONDTCTL2_f; + }; + union + { + __IO uint32_t MONRPT2; + stc_dma_monrpt_field_t MONRPT2_f; + }; + union + { + __IO uint32_t MONSNSEQCTL2; + stc_dma_monsnseqctl_field_t MONSNSEQCTL2_f; + }; + union + { + __IO uint32_t MONDNSEQCTL2; + stc_dma_mondnseqctl_field_t MONDNSEQCTL2_f; + }; + uint8_t RESERVED61[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + union + { + __IO uint32_t DTCTL3; + stc_dma_dtctl_field_t DTCTL3_f; + }; + union + { + __IO uint32_t RPT3; + stc_dma_rpt_field_t RPT3_f; + __IO uint32_t RPTB3; + stc_dma_rptb_field_t RPTB3_f; + }; + union + { + __IO uint32_t SNSEQCTL3; + stc_dma_snseqctl_field_t SNSEQCTL3_f; + __IO uint32_t SNSEQCTLB3; + stc_dma_snseqctlb_field_t SNSEQCTLB3_f; + }; + union + { + __IO uint32_t DNSEQCTL3; + stc_dma_dnseqctl_field_t DNSEQCTL3_f; + __IO uint32_t DNSEQCTLB3; + stc_dma_dnseqctlb_field_t DNSEQCTLB3_f; + }; + union + { + __IO uint32_t LLP3; + stc_dma_llp_field_t LLP3_f; + }; + union + { + __IO uint32_t CH3CTL; + stc_dma_ch3ctl_field_t CH3CTL_f; + }; + __IO uint32_t MONSAR3; + __IO uint32_t MONDAR3; + union + { + __IO uint32_t MONDTCTL3; + stc_dma_mondtctl_field_t MONDTCTL3_f; + }; + union + { + __IO uint32_t MONRPT3; + stc_dma_monrpt_field_t MONRPT3_f; + }; + union + { + __IO uint32_t MONSNSEQCTL3; + stc_dma_monsnseqctl_field_t MONSNSEQCTL3_f; + }; + union + { + __IO uint32_t MONDNSEQCTL3; + stc_dma_mondnseqctl_field_t MONDNSEQCTL3_f; + }; +}M4_DMA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t FAPRT; + stc_efm_faprt_field_t FAPRT_f; + }; + union + { + __IO uint32_t FSTP; + stc_efm_fstp_field_t FSTP_f; + }; + union + { + __IO uint32_t FRMC; + stc_efm_frmc_field_t FRMC_f; + }; + union + { + __IO uint32_t FWMC; + stc_efm_fwmc_field_t FWMC_f; + }; + union + { + __IO uint32_t FSR; + stc_efm_fsr_field_t FSR_f; + }; + union + { + __IO uint32_t FSCLR; + stc_efm_fsclr_field_t FSCLR_f; + }; + union + { + __IO uint32_t FITE; + stc_efm_fite_field_t FITE_f; + }; + union + { + __IO uint32_t FSWP; + stc_efm_fswp_field_t FSWP_f; + }; + union + { + __IO uint32_t FPMTSW; + stc_efm_fpmtsw_field_t FPMTSW_f; + }; + union + { + __IO uint32_t FPMTEW; + stc_efm_fpmtew_field_t FPMTEW_f; + }; + uint8_t RESERVED10[40]; + __IO uint32_t UQID1; + __IO uint32_t UQID2; + __IO uint32_t UQID3; + uint8_t RESERVED13[164]; + union + { + __IO uint32_t MMF_REMPRT; + stc_efm_mmf_remprt_field_t MMF_REMPRT_f; + }; + union + { + __IO uint32_t MMF_REMCR0; + stc_efm_mmf_remcr0_field_t MMF_REMCR0_f; + }; + union + { + __IO uint32_t MMF_REMCR1; + stc_efm_mmf_remcr1_field_t MMF_REMCR1_f; + }; + uint8_t RESERVED16[248]; + union + { + __IO uint32_t EFM_FRANDS; + stc_efm_efm_frands_field_t EFM_FRANDS_f; + }; +}M4_EFM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTL; + stc_emb_ctl_field_t CTL_f; + }; + union + { + __IO uint32_t PWMLV; + stc_emb_pwmlv_field_t PWMLV_f; + }; + union + { + __IO uint32_t SOE; + stc_emb_soe_field_t SOE_f; + }; + union + { + __IO uint32_t STAT; + stc_emb_stat_field_t STAT_f; + }; + union + { + __IO uint32_t STATCLR; + stc_emb_statclr_field_t STATCLR_f; + }; + union + { + __IO uint32_t INTEN; + stc_emb_inten_field_t INTEN_f; + }; +}M4_EMB_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t LVR; + stc_fcm_lvr_field_t LVR_f; + }; + union + { + __IO uint32_t UVR; + stc_fcm_uvr_field_t UVR_f; + }; + union + { + __IO uint32_t CNTR; + stc_fcm_cntr_field_t CNTR_f; + }; + union + { + __IO uint32_t STR; + stc_fcm_str_field_t STR_f; + }; + union + { + __IO uint32_t MCCR; + stc_fcm_mccr_field_t MCCR_f; + }; + union + { + __IO uint32_t RCCR; + stc_fcm_rccr_field_t RCCR_f; + }; + union + { + __IO uint32_t RIER; + stc_fcm_rier_field_t RIER_f; + }; + union + { + __IO uint32_t SR; + stc_fcm_sr_field_t SR_f; + }; + union + { + __IO uint32_t CLR; + stc_fcm_clr_field_t CLR_f; + }; +}M4_FCM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_hash_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED9[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +}M4_HASH_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR1; + stc_i2c_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_i2c_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_i2c_cr3_field_t CR3_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t SLR0; + stc_i2c_slr0_field_t SLR0_f; + }; + union + { + __IO uint32_t SLR1; + stc_i2c_slr1_field_t SLR1_f; + }; + union + { + __IO uint32_t SLTR; + stc_i2c_sltr_field_t SLTR_f; + }; + union + { + __IO uint32_t SR; + stc_i2c_sr_field_t SR_f; + }; + union + { + __IO uint32_t CLR; + stc_i2c_clr_field_t CLR_f; + }; + union + { + __IO uint8_t DTR; + stc_i2c_dtr_field_t DTR_f; + }; + uint8_t RESERVED9[3]; + union + { + __IO uint8_t DRR; + stc_i2c_drr_field_t DRR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint32_t CCR; + stc_i2c_ccr_field_t CCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_i2c_fltr_field_t FLTR_f; + }; +}M4_I2C_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CTRL; + stc_i2s_ctrl_field_t CTRL_f; + }; + union + { + __IO uint32_t SR; + stc_i2s_sr_field_t SR_f; + }; + union + { + __IO uint32_t ER; + stc_i2s_er_field_t ER_f; + }; + union + { + __IO uint32_t CFGR; + stc_i2s_cfgr_field_t CFGR_f; + }; + __IO uint32_t TXBUF; + __IO uint32_t RXBUF; + union + { + __IO uint32_t PR; + stc_i2s_pr_field_t PR_f; + }; +}M4_I2S_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ICG0; + stc_icg_icg0_field_t ICG0_f; + }; + union + { + __IO uint32_t ICG1; + stc_icg_icg1_field_t ICG1_f; + }; + __IO uint32_t ICG2; + __IO uint32_t ICG3; + __IO uint32_t ICG4; + __IO uint32_t ICG5; + __IO uint32_t ICG6; + __IO uint32_t ICG7; +}M4_ICG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t NMICR; + stc_intc_nmicr_field_t NMICR_f; + }; + union + { + __IO uint32_t NMIENR; + stc_intc_nmienr_field_t NMIENR_f; + }; + union + { + __IO uint32_t NMIFR; + stc_intc_nmifr_field_t NMIFR_f; + }; + union + { + __IO uint32_t NMICFR; + stc_intc_nmicfr_field_t NMICFR_f; + }; + union + { + __IO uint32_t EIRQCR0; + stc_intc_eirqcr_field_t EIRQCR0_f; + }; + union + { + __IO uint32_t EIRQCR1; + stc_intc_eirqcr_field_t EIRQCR1_f; + }; + union + { + __IO uint32_t EIRQCR2; + stc_intc_eirqcr_field_t EIRQCR2_f; + }; + union + { + __IO uint32_t EIRQCR3; + stc_intc_eirqcr_field_t EIRQCR3_f; + }; + union + { + __IO uint32_t EIRQCR4; + stc_intc_eirqcr_field_t EIRQCR4_f; + }; + union + { + __IO uint32_t EIRQCR5; + stc_intc_eirqcr_field_t EIRQCR5_f; + }; + union + { + __IO uint32_t EIRQCR6; + stc_intc_eirqcr_field_t EIRQCR6_f; + }; + union + { + __IO uint32_t EIRQCR7; + stc_intc_eirqcr_field_t EIRQCR7_f; + }; + union + { + __IO uint32_t EIRQCR8; + stc_intc_eirqcr_field_t EIRQCR8_f; + }; + union + { + __IO uint32_t EIRQCR9; + stc_intc_eirqcr_field_t EIRQCR9_f; + }; + union + { + __IO uint32_t EIRQCR10; + stc_intc_eirqcr_field_t EIRQCR10_f; + }; + union + { + __IO uint32_t EIRQCR11; + stc_intc_eirqcr_field_t EIRQCR11_f; + }; + union + { + __IO uint32_t EIRQCR12; + stc_intc_eirqcr_field_t EIRQCR12_f; + }; + union + { + __IO uint32_t EIRQCR13; + stc_intc_eirqcr_field_t EIRQCR13_f; + }; + union + { + __IO uint32_t EIRQCR14; + stc_intc_eirqcr_field_t EIRQCR14_f; + }; + union + { + __IO uint32_t EIRQCR15; + stc_intc_eirqcr_field_t EIRQCR15_f; + }; + union + { + __IO uint32_t WUPEN; + stc_intc_wupen_field_t WUPEN_f; + }; + union + { + __IO uint32_t EIFR; + stc_intc_eifr_field_t EIFR_f; + }; + union + { + __IO uint32_t EICFR; + stc_intc_eicfr_field_t EICFR_f; + }; + union + { + __IO uint32_t SEL0; + stc_intc_sel_field_t SEL0_f; + }; + union + { + __IO uint32_t SEL1; + stc_intc_sel_field_t SEL1_f; + }; + union + { + __IO uint32_t SEL2; + stc_intc_sel_field_t SEL2_f; + }; + union + { + __IO uint32_t SEL3; + stc_intc_sel_field_t SEL3_f; + }; + union + { + __IO uint32_t SEL4; + stc_intc_sel_field_t SEL4_f; + }; + union + { + __IO uint32_t SEL5; + stc_intc_sel_field_t SEL5_f; + }; + union + { + __IO uint32_t SEL6; + stc_intc_sel_field_t SEL6_f; + }; + union + { + __IO uint32_t SEL7; + stc_intc_sel_field_t SEL7_f; + }; + union + { + __IO uint32_t SEL8; + stc_intc_sel_field_t SEL8_f; + }; + union + { + __IO uint32_t SEL9; + stc_intc_sel_field_t SEL9_f; + }; + union + { + __IO uint32_t SEL10; + stc_intc_sel_field_t SEL10_f; + }; + union + { + __IO uint32_t SEL11; + stc_intc_sel_field_t SEL11_f; + }; + union + { + __IO uint32_t SEL12; + stc_intc_sel_field_t SEL12_f; + }; + union + { + __IO uint32_t SEL13; + stc_intc_sel_field_t SEL13_f; + }; + union + { + __IO uint32_t SEL14; + stc_intc_sel_field_t SEL14_f; + }; + union + { + __IO uint32_t SEL15; + stc_intc_sel_field_t SEL15_f; + }; + union + { + __IO uint32_t SEL16; + stc_intc_sel_field_t SEL16_f; + }; + union + { + __IO uint32_t SEL17; + stc_intc_sel_field_t SEL17_f; + }; + union + { + __IO uint32_t SEL18; + stc_intc_sel_field_t SEL18_f; + }; + union + { + __IO uint32_t SEL19; + stc_intc_sel_field_t SEL19_f; + }; + union + { + __IO uint32_t SEL20; + stc_intc_sel_field_t SEL20_f; + }; + union + { + __IO uint32_t SEL21; + stc_intc_sel_field_t SEL21_f; + }; + union + { + __IO uint32_t SEL22; + stc_intc_sel_field_t SEL22_f; + }; + union + { + __IO uint32_t SEL23; + stc_intc_sel_field_t SEL23_f; + }; + union + { + __IO uint32_t SEL24; + stc_intc_sel_field_t SEL24_f; + }; + union + { + __IO uint32_t SEL25; + stc_intc_sel_field_t SEL25_f; + }; + union + { + __IO uint32_t SEL26; + stc_intc_sel_field_t SEL26_f; + }; + union + { + __IO uint32_t SEL27; + stc_intc_sel_field_t SEL27_f; + }; + union + { + __IO uint32_t SEL28; + stc_intc_sel_field_t SEL28_f; + }; + union + { + __IO uint32_t SEL29; + stc_intc_sel_field_t SEL29_f; + }; + union + { + __IO uint32_t SEL30; + stc_intc_sel_field_t SEL30_f; + }; + union + { + __IO uint32_t SEL31; + stc_intc_sel_field_t SEL31_f; + }; + union + { + __IO uint32_t SEL32; + stc_intc_sel_field_t SEL32_f; + }; + union + { + __IO uint32_t SEL33; + stc_intc_sel_field_t SEL33_f; + }; + union + { + __IO uint32_t SEL34; + stc_intc_sel_field_t SEL34_f; + }; + union + { + __IO uint32_t SEL35; + stc_intc_sel_field_t SEL35_f; + }; + union + { + __IO uint32_t SEL36; + stc_intc_sel_field_t SEL36_f; + }; + union + { + __IO uint32_t SEL37; + stc_intc_sel_field_t SEL37_f; + }; + union + { + __IO uint32_t SEL38; + stc_intc_sel_field_t SEL38_f; + }; + union + { + __IO uint32_t SEL39; + stc_intc_sel_field_t SEL39_f; + }; + union + { + __IO uint32_t SEL40; + stc_intc_sel_field_t SEL40_f; + }; + union + { + __IO uint32_t SEL41; + stc_intc_sel_field_t SEL41_f; + }; + union + { + __IO uint32_t SEL42; + stc_intc_sel_field_t SEL42_f; + }; + union + { + __IO uint32_t SEL43; + stc_intc_sel_field_t SEL43_f; + }; + union + { + __IO uint32_t SEL44; + stc_intc_sel_field_t SEL44_f; + }; + union + { + __IO uint32_t SEL45; + stc_intc_sel_field_t SEL45_f; + }; + union + { + __IO uint32_t SEL46; + stc_intc_sel_field_t SEL46_f; + }; + union + { + __IO uint32_t SEL47; + stc_intc_sel_field_t SEL47_f; + }; + union + { + __IO uint32_t SEL48; + stc_intc_sel_field_t SEL48_f; + }; + union + { + __IO uint32_t SEL49; + stc_intc_sel_field_t SEL49_f; + }; + union + { + __IO uint32_t SEL50; + stc_intc_sel_field_t SEL50_f; + }; + union + { + __IO uint32_t SEL51; + stc_intc_sel_field_t SEL51_f; + }; + union + { + __IO uint32_t SEL52; + stc_intc_sel_field_t SEL52_f; + }; + union + { + __IO uint32_t SEL53; + stc_intc_sel_field_t SEL53_f; + }; + union + { + __IO uint32_t SEL54; + stc_intc_sel_field_t SEL54_f; + }; + union + { + __IO uint32_t SEL55; + stc_intc_sel_field_t SEL55_f; + }; + union + { + __IO uint32_t SEL56; + stc_intc_sel_field_t SEL56_f; + }; + union + { + __IO uint32_t SEL57; + stc_intc_sel_field_t SEL57_f; + }; + union + { + __IO uint32_t SEL58; + stc_intc_sel_field_t SEL58_f; + }; + union + { + __IO uint32_t SEL59; + stc_intc_sel_field_t SEL59_f; + }; + union + { + __IO uint32_t SEL60; + stc_intc_sel_field_t SEL60_f; + }; + union + { + __IO uint32_t SEL61; + stc_intc_sel_field_t SEL61_f; + }; + union + { + __IO uint32_t SEL62; + stc_intc_sel_field_t SEL62_f; + }; + union + { + __IO uint32_t SEL63; + stc_intc_sel_field_t SEL63_f; + }; + union + { + __IO uint32_t SEL64; + stc_intc_sel_field_t SEL64_f; + }; + union + { + __IO uint32_t SEL65; + stc_intc_sel_field_t SEL65_f; + }; + union + { + __IO uint32_t SEL66; + stc_intc_sel_field_t SEL66_f; + }; + union + { + __IO uint32_t SEL67; + stc_intc_sel_field_t SEL67_f; + }; + union + { + __IO uint32_t SEL68; + stc_intc_sel_field_t SEL68_f; + }; + union + { + __IO uint32_t SEL69; + stc_intc_sel_field_t SEL69_f; + }; + union + { + __IO uint32_t SEL70; + stc_intc_sel_field_t SEL70_f; + }; + union + { + __IO uint32_t SEL71; + stc_intc_sel_field_t SEL71_f; + }; + union + { + __IO uint32_t SEL72; + stc_intc_sel_field_t SEL72_f; + }; + union + { + __IO uint32_t SEL73; + stc_intc_sel_field_t SEL73_f; + }; + union + { + __IO uint32_t SEL74; + stc_intc_sel_field_t SEL74_f; + }; + union + { + __IO uint32_t SEL75; + stc_intc_sel_field_t SEL75_f; + }; + union + { + __IO uint32_t SEL76; + stc_intc_sel_field_t SEL76_f; + }; + union + { + __IO uint32_t SEL77; + stc_intc_sel_field_t SEL77_f; + }; + union + { + __IO uint32_t SEL78; + stc_intc_sel_field_t SEL78_f; + }; + union + { + __IO uint32_t SEL79; + stc_intc_sel_field_t SEL79_f; + }; + union + { + __IO uint32_t SEL80; + stc_intc_sel_field_t SEL80_f; + }; + union + { + __IO uint32_t SEL81; + stc_intc_sel_field_t SEL81_f; + }; + union + { + __IO uint32_t SEL82; + stc_intc_sel_field_t SEL82_f; + }; + union + { + __IO uint32_t SEL83; + stc_intc_sel_field_t SEL83_f; + }; + union + { + __IO uint32_t SEL84; + stc_intc_sel_field_t SEL84_f; + }; + union + { + __IO uint32_t SEL85; + stc_intc_sel_field_t SEL85_f; + }; + union + { + __IO uint32_t SEL86; + stc_intc_sel_field_t SEL86_f; + }; + union + { + __IO uint32_t SEL87; + stc_intc_sel_field_t SEL87_f; + }; + union + { + __IO uint32_t SEL88; + stc_intc_sel_field_t SEL88_f; + }; + union + { + __IO uint32_t SEL89; + stc_intc_sel_field_t SEL89_f; + }; + union + { + __IO uint32_t SEL90; + stc_intc_sel_field_t SEL90_f; + }; + union + { + __IO uint32_t SEL91; + stc_intc_sel_field_t SEL91_f; + }; + union + { + __IO uint32_t SEL92; + stc_intc_sel_field_t SEL92_f; + }; + union + { + __IO uint32_t SEL93; + stc_intc_sel_field_t SEL93_f; + }; + union + { + __IO uint32_t SEL94; + stc_intc_sel_field_t SEL94_f; + }; + union + { + __IO uint32_t SEL95; + stc_intc_sel_field_t SEL95_f; + }; + union + { + __IO uint32_t SEL96; + stc_intc_sel_field_t SEL96_f; + }; + union + { + __IO uint32_t SEL97; + stc_intc_sel_field_t SEL97_f; + }; + union + { + __IO uint32_t SEL98; + stc_intc_sel_field_t SEL98_f; + }; + union + { + __IO uint32_t SEL99; + stc_intc_sel_field_t SEL99_f; + }; + union + { + __IO uint32_t SEL100; + stc_intc_sel_field_t SEL100_f; + }; + union + { + __IO uint32_t SEL101; + stc_intc_sel_field_t SEL101_f; + }; + union + { + __IO uint32_t SEL102; + stc_intc_sel_field_t SEL102_f; + }; + union + { + __IO uint32_t SEL103; + stc_intc_sel_field_t SEL103_f; + }; + union + { + __IO uint32_t SEL104; + stc_intc_sel_field_t SEL104_f; + }; + union + { + __IO uint32_t SEL105; + stc_intc_sel_field_t SEL105_f; + }; + union + { + __IO uint32_t SEL106; + stc_intc_sel_field_t SEL106_f; + }; + union + { + __IO uint32_t SEL107; + stc_intc_sel_field_t SEL107_f; + }; + union + { + __IO uint32_t SEL108; + stc_intc_sel_field_t SEL108_f; + }; + union + { + __IO uint32_t SEL109; + stc_intc_sel_field_t SEL109_f; + }; + union + { + __IO uint32_t SEL110; + stc_intc_sel_field_t SEL110_f; + }; + union + { + __IO uint32_t SEL111; + stc_intc_sel_field_t SEL111_f; + }; + union + { + __IO uint32_t SEL112; + stc_intc_sel_field_t SEL112_f; + }; + union + { + __IO uint32_t SEL113; + stc_intc_sel_field_t SEL113_f; + }; + union + { + __IO uint32_t SEL114; + stc_intc_sel_field_t SEL114_f; + }; + union + { + __IO uint32_t SEL115; + stc_intc_sel_field_t SEL115_f; + }; + union + { + __IO uint32_t SEL116; + stc_intc_sel_field_t SEL116_f; + }; + union + { + __IO uint32_t SEL117; + stc_intc_sel_field_t SEL117_f; + }; + union + { + __IO uint32_t SEL118; + stc_intc_sel_field_t SEL118_f; + }; + union + { + __IO uint32_t SEL119; + stc_intc_sel_field_t SEL119_f; + }; + union + { + __IO uint32_t SEL120; + stc_intc_sel_field_t SEL120_f; + }; + union + { + __IO uint32_t SEL121; + stc_intc_sel_field_t SEL121_f; + }; + union + { + __IO uint32_t SEL122; + stc_intc_sel_field_t SEL122_f; + }; + union + { + __IO uint32_t SEL123; + stc_intc_sel_field_t SEL123_f; + }; + union + { + __IO uint32_t SEL124; + stc_intc_sel_field_t SEL124_f; + }; + union + { + __IO uint32_t SEL125; + stc_intc_sel_field_t SEL125_f; + }; + union + { + __IO uint32_t SEL126; + stc_intc_sel_field_t SEL126_f; + }; + union + { + __IO uint32_t SEL127; + stc_intc_sel_field_t SEL127_f; + }; + union + { + __IO uint32_t VSSEL128; + stc_intc_vssel_field_t VSSEL128_f; + }; + union + { + __IO uint32_t VSSEL129; + stc_intc_vssel_field_t VSSEL129_f; + }; + union + { + __IO uint32_t VSSEL130; + stc_intc_vssel_field_t VSSEL130_f; + }; + union + { + __IO uint32_t VSSEL131; + stc_intc_vssel_field_t VSSEL131_f; + }; + union + { + __IO uint32_t VSSEL132; + stc_intc_vssel_field_t VSSEL132_f; + }; + union + { + __IO uint32_t VSSEL133; + stc_intc_vssel_field_t VSSEL133_f; + }; + union + { + __IO uint32_t VSSEL134; + stc_intc_vssel_field_t VSSEL134_f; + }; + union + { + __IO uint32_t VSSEL135; + stc_intc_vssel_field_t VSSEL135_f; + }; + union + { + __IO uint32_t VSSEL136; + stc_intc_vssel_field_t VSSEL136_f; + }; + union + { + __IO uint32_t VSSEL137; + stc_intc_vssel_field_t VSSEL137_f; + }; + union + { + __IO uint32_t VSSEL138; + stc_intc_vssel_field_t VSSEL138_f; + }; + union + { + __IO uint32_t VSSEL139; + stc_intc_vssel_field_t VSSEL139_f; + }; + union + { + __IO uint32_t VSSEL140; + stc_intc_vssel_field_t VSSEL140_f; + }; + union + { + __IO uint32_t VSSEL141; + stc_intc_vssel_field_t VSSEL141_f; + }; + union + { + __IO uint32_t VSSEL142; + stc_intc_vssel_field_t VSSEL142_f; + }; + union + { + __IO uint32_t VSSEL143; + stc_intc_vssel_field_t VSSEL143_f; + }; + union + { + __IO uint32_t SWIER; + stc_intc_swier_field_t SWIER_f; + }; + union + { + __IO uint32_t EVTER; + stc_intc_evter_field_t EVTER_f; + }; + union + { + __IO uint32_t IER; + stc_intc_ier_field_t IER_f; + }; +}M4_INTC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SCR; + stc_keyscan_scr_field_t SCR_f; + }; + union + { + __IO uint32_t SER; + stc_keyscan_ser_field_t SER_f; + }; + union + { + __IO uint32_t SSR; + stc_keyscan_ssr_field_t SSR_f; + }; +}M4_KEYSCAN_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RGD0; + stc_mpu_rgd0_field_t RGD0_f; + }; + union + { + __IO uint32_t RGD1; + stc_mpu_rgd1_field_t RGD1_f; + }; + union + { + __IO uint32_t RGD2; + stc_mpu_rgd2_field_t RGD2_f; + }; + union + { + __IO uint32_t RGD3; + stc_mpu_rgd3_field_t RGD3_f; + }; + union + { + __IO uint32_t RGD4; + stc_mpu_rgd4_field_t RGD4_f; + }; + union + { + __IO uint32_t RGD5; + stc_mpu_rgd5_field_t RGD5_f; + }; + union + { + __IO uint32_t RGD6; + stc_mpu_rgd6_field_t RGD6_f; + }; + union + { + __IO uint32_t RGD7; + stc_mpu_rgd7_field_t RGD7_f; + }; + union + { + __IO uint32_t RGD8; + stc_mpu_rgd8_field_t RGD8_f; + }; + union + { + __IO uint32_t RGD9; + stc_mpu_rgd9_field_t RGD9_f; + }; + union + { + __IO uint32_t RGD10; + stc_mpu_rgd10_field_t RGD10_f; + }; + union + { + __IO uint32_t RGD11; + stc_mpu_rgd11_field_t RGD11_f; + }; + union + { + __IO uint32_t RGD12; + stc_mpu_rgd12_field_t RGD12_f; + }; + union + { + __IO uint32_t RGD13; + stc_mpu_rgd13_field_t RGD13_f; + }; + union + { + __IO uint32_t RGD14; + stc_mpu_rgd14_field_t RGD14_f; + }; + union + { + __IO uint32_t RGD15; + stc_mpu_rgd15_field_t RGD15_f; + }; + union + { + __IO uint32_t RGCR0; + stc_mpu_rgcr0_field_t RGCR0_f; + }; + union + { + __IO uint32_t RGCR1; + stc_mpu_rgcr1_field_t RGCR1_f; + }; + union + { + __IO uint32_t RGCR2; + stc_mpu_rgcr2_field_t RGCR2_f; + }; + union + { + __IO uint32_t RGCR3; + stc_mpu_rgcr3_field_t RGCR3_f; + }; + union + { + __IO uint32_t RGCR4; + stc_mpu_rgcr4_field_t RGCR4_f; + }; + union + { + __IO uint32_t RGCR5; + stc_mpu_rgcr5_field_t RGCR5_f; + }; + union + { + __IO uint32_t RGCR6; + stc_mpu_rgcr6_field_t RGCR6_f; + }; + union + { + __IO uint32_t RGCR7; + stc_mpu_rgcr7_field_t RGCR7_f; + }; + union + { + __IO uint32_t RGCR8; + stc_mpu_rgcr8_field_t RGCR8_f; + }; + union + { + __IO uint32_t RGCR9; + stc_mpu_rgcr9_field_t RGCR9_f; + }; + union + { + __IO uint32_t RGCR10; + stc_mpu_rgcr10_field_t RGCR10_f; + }; + union + { + __IO uint32_t RGCR11; + stc_mpu_rgcr11_field_t RGCR11_f; + }; + union + { + __IO uint32_t RGCR12; + stc_mpu_rgcr12_field_t RGCR12_f; + }; + union + { + __IO uint32_t RGCR13; + stc_mpu_rgcr13_field_t RGCR13_f; + }; + union + { + __IO uint32_t RGCR14; + stc_mpu_rgcr14_field_t RGCR14_f; + }; + union + { + __IO uint32_t RGCR15; + stc_mpu_rgcr15_field_t RGCR15_f; + }; + union + { + __IO uint32_t CR; + stc_mpu_cr_field_t CR_f; + }; + union + { + __IO uint32_t SR; + stc_mpu_sr_field_t SR_f; + }; + union + { + __IO uint32_t ECLR; + stc_mpu_eclr_field_t ECLR_f; + }; + union + { + __IO uint32_t WP; + stc_mpu_wp_field_t WP_f; + }; +}M4_MPU_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t FCG0; + stc_mstp_fcg0_field_t FCG0_f; + }; + union + { + __IO uint32_t FCG1; + stc_mstp_fcg1_field_t FCG1_f; + }; + union + { + __IO uint32_t FCG2; + stc_mstp_fcg2_field_t FCG2_f; + }; + union + { + __IO uint32_t FCG3; + stc_mstp_fcg3_field_t FCG3_f; + }; + union + { + __IO uint32_t FCG0PC; + stc_mstp_fcg0pc_field_t FCG0PC_f; + }; +}M4_MSTP_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CTL; + stc_ots_ctl_field_t CTL_f; + }; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; + union + { + __IO uint32_t LPR; + stc_ots_lpr_field_t LPR_f; + }; +}M4_OTS_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t USBFS_SYCTLREG; + stc_peric_usbfs_syctlreg_field_t USBFS_SYCTLREG_f; + }; + union + { + __IO uint32_t SDIOC_SYCTLREG; + stc_peric_sdioc_syctlreg_field_t SDIOC_SYCTLREG_f; + }; +}M4_PERIC_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t PIDRA; + stc_port_pidr_field_t PIDRA_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t PODRA; + stc_port_podr_field_t PODRA_f; + }; + union + { + __IO uint16_t POERA; + stc_port_poer_field_t POERA_f; + }; + union + { + __IO uint16_t POSRA; + stc_port_posr_field_t POSRA_f; + }; + union + { + __IO uint16_t PORRA; + stc_port_porr_field_t PORRA_f; + }; + union + { + __IO uint16_t POTRA; + stc_port_potr_field_t POTRA_f; + }; + uint8_t RESERVED6[2]; + union + { + __IO uint16_t PIDRB; + stc_port_pidr_field_t PIDRB_f; + }; + uint8_t RESERVED7[2]; + union + { + __IO uint16_t PODRB; + stc_port_podr_field_t PODRB_f; + }; + union + { + __IO uint16_t POERB; + stc_port_poer_field_t POERB_f; + }; + union + { + __IO uint16_t POSRB; + stc_port_posr_field_t POSRB_f; + }; + union + { + __IO uint16_t PORRB; + stc_port_porr_field_t PORRB_f; + }; + union + { + __IO uint16_t POTRB; + stc_port_potr_field_t POTRB_f; + }; + uint8_t RESERVED12[2]; + union + { + __IO uint16_t PIDRC; + stc_port_pidr_field_t PIDRC_f; + }; + uint8_t RESERVED13[2]; + union + { + __IO uint16_t PODRC; + stc_port_podr_field_t PODRC_f; + }; + union + { + __IO uint16_t POERC; + stc_port_poer_field_t POERC_f; + }; + union + { + __IO uint16_t POSRC; + stc_port_posr_field_t POSRC_f; + }; + union + { + __IO uint16_t PORRC; + stc_port_porr_field_t PORRC_f; + }; + union + { + __IO uint16_t POTRC; + stc_port_potr_field_t POTRC_f; + }; + uint8_t RESERVED18[2]; + union + { + __IO uint16_t PIDRD; + stc_port_pidr_field_t PIDRD_f; + }; + uint8_t RESERVED19[2]; + union + { + __IO uint16_t PODRD; + stc_port_podr_field_t PODRD_f; + }; + union + { + __IO uint16_t POERD; + stc_port_poer_field_t POERD_f; + }; + union + { + __IO uint16_t POSRD; + stc_port_posr_field_t POSRD_f; + }; + union + { + __IO uint16_t PORRD; + stc_port_porr_field_t PORRD_f; + }; + union + { + __IO uint16_t POTRD; + stc_port_potr_field_t POTRD_f; + }; + uint8_t RESERVED24[2]; + union + { + __IO uint16_t PIDRE; + stc_port_pidr_field_t PIDRE_f; + }; + uint8_t RESERVED25[2]; + union + { + __IO uint16_t PODRE; + stc_port_podr_field_t PODRE_f; + }; + union + { + __IO uint16_t POERE; + stc_port_poer_field_t POERE_f; + }; + union + { + __IO uint16_t POSRE; + stc_port_posr_field_t POSRE_f; + }; + union + { + __IO uint16_t PORRE; + stc_port_porr_field_t PORRE_f; + }; + union + { + __IO uint16_t POTRE; + stc_port_potr_field_t POTRE_f; + }; + uint8_t RESERVED30[2]; + union + { + __IO uint16_t PIDRH; + stc_port_pidrh_field_t PIDRH_f; + }; + uint8_t RESERVED31[2]; + union + { + __IO uint16_t PODRH; + stc_port_podrh_field_t PODRH_f; + }; + union + { + __IO uint16_t POERH; + stc_port_poerh_field_t POERH_f; + }; + union + { + __IO uint16_t POSRH; + stc_port_posrh_field_t POSRH_f; + }; + union + { + __IO uint16_t PORRH; + stc_port_porrh_field_t PORRH_f; + }; + union + { + __IO uint16_t POTRH; + stc_port_potrh_field_t POTRH_f; + }; + uint8_t RESERVED36[918]; + union + { + __IO uint16_t PSPCR; + stc_port_pspcr_field_t PSPCR_f; + }; + uint8_t RESERVED37[2]; + union + { + __IO uint16_t PCCR; + stc_port_pccr_field_t PCCR_f; + }; + union + { + __IO uint16_t PINAER; + stc_port_pinaer_field_t PINAER_f; + }; + union + { + __IO uint16_t PWPR; + stc_port_pwpr_field_t PWPR_f; + }; + uint8_t RESERVED40[2]; + union + { + __IO uint16_t PCRA0; + stc_port_pcr_field_t PCRA0_f; + }; + union + { + __IO uint16_t PFSRA0; + stc_port_pfsr_field_t PFSRA0_f; + }; + union + { + __IO uint16_t PCRA1; + stc_port_pcr_field_t PCRA1_f; + }; + union + { + __IO uint16_t PFSRA1; + stc_port_pfsr_field_t PFSRA1_f; + }; + union + { + __IO uint16_t PCRA2; + stc_port_pcr_field_t PCRA2_f; + }; + union + { + __IO uint16_t PFSRA2; + stc_port_pfsr_field_t PFSRA2_f; + }; + union + { + __IO uint16_t PCRA3; + stc_port_pcr_field_t PCRA3_f; + }; + union + { + __IO uint16_t PFSRA3; + stc_port_pfsr_field_t PFSRA3_f; + }; + union + { + __IO uint16_t PCRA4; + stc_port_pcr_field_t PCRA4_f; + }; + union + { + __IO uint16_t PFSRA4; + stc_port_pfsr_field_t PFSRA4_f; + }; + union + { + __IO uint16_t PCRA5; + stc_port_pcr_field_t PCRA5_f; + }; + union + { + __IO uint16_t PFSRA5; + stc_port_pfsr_field_t PFSRA5_f; + }; + union + { + __IO uint16_t PCRA6; + stc_port_pcr_field_t PCRA6_f; + }; + union + { + __IO uint16_t PFSRA6; + stc_port_pfsr_field_t PFSRA6_f; + }; + union + { + __IO uint16_t PCRA7; + stc_port_pcr_field_t PCRA7_f; + }; + union + { + __IO uint16_t PFSRA7; + stc_port_pfsr_field_t PFSRA7_f; + }; + union + { + __IO uint16_t PCRA8; + stc_port_pcr_field_t PCRA8_f; + }; + union + { + __IO uint16_t PFSRA8; + stc_port_pfsr_field_t PFSRA8_f; + }; + union + { + __IO uint16_t PCRA9; + stc_port_pcr_field_t PCRA9_f; + }; + union + { + __IO uint16_t PFSRA9; + stc_port_pfsr_field_t PFSRA9_f; + }; + union + { + __IO uint16_t PCRA10; + stc_port_pcr_field_t PCRA10_f; + }; + union + { + __IO uint16_t PFSRA10; + stc_port_pfsr_field_t PFSRA10_f; + }; + union + { + __IO uint16_t PCRA11; + stc_port_pcr_field_t PCRA11_f; + }; + union + { + __IO uint16_t PFSRA11; + stc_port_pfsr_field_t PFSRA11_f; + }; + union + { + __IO uint16_t PCRA12; + stc_port_pcr_field_t PCRA12_f; + }; + union + { + __IO uint16_t PFSRA12; + stc_port_pfsr_field_t PFSRA12_f; + }; + union + { + __IO uint16_t PCRA13; + stc_port_pcr_field_t PCRA13_f; + }; + union + { + __IO uint16_t PFSRA13; + stc_port_pfsr_field_t PFSRA13_f; + }; + union + { + __IO uint16_t PCRA14; + stc_port_pcr_field_t PCRA14_f; + }; + union + { + __IO uint16_t PFSRA14; + stc_port_pfsr_field_t PFSRA14_f; + }; + union + { + __IO uint16_t PCRA15; + stc_port_pcr_field_t PCRA15_f; + }; + union + { + __IO uint16_t PFSRA15; + stc_port_pfsr_field_t PFSRA15_f; + }; + union + { + __IO uint16_t PCRB0; + stc_port_pcr_field_t PCRB0_f; + }; + union + { + __IO uint16_t PFSRB0; + stc_port_pfsr_field_t PFSRB0_f; + }; + union + { + __IO uint16_t PCRB1; + stc_port_pcr_field_t PCRB1_f; + }; + union + { + __IO uint16_t PFSRB1; + stc_port_pfsr_field_t PFSRB1_f; + }; + union + { + __IO uint16_t PCRB2; + stc_port_pcr_field_t PCRB2_f; + }; + union + { + __IO uint16_t PFSRB2; + stc_port_pfsr_field_t PFSRB2_f; + }; + union + { + __IO uint16_t PCRB3; + stc_port_pcr_field_t PCRB3_f; + }; + union + { + __IO uint16_t PFSRB3; + stc_port_pfsr_field_t PFSRB3_f; + }; + union + { + __IO uint16_t PCRB4; + stc_port_pcr_field_t PCRB4_f; + }; + union + { + __IO uint16_t PFSRB4; + stc_port_pfsr_field_t PFSRB4_f; + }; + union + { + __IO uint16_t PCRB5; + stc_port_pcr_field_t PCRB5_f; + }; + union + { + __IO uint16_t PFSRB5; + stc_port_pfsr_field_t PFSRB5_f; + }; + union + { + __IO uint16_t PCRB6; + stc_port_pcr_field_t PCRB6_f; + }; + union + { + __IO uint16_t PFSRB6; + stc_port_pfsr_field_t PFSRB6_f; + }; + union + { + __IO uint16_t PCRB7; + stc_port_pcr_field_t PCRB7_f; + }; + union + { + __IO uint16_t PFSRB7; + stc_port_pfsr_field_t PFSRB7_f; + }; + union + { + __IO uint16_t PCRB8; + stc_port_pcr_field_t PCRB8_f; + }; + union + { + __IO uint16_t PFSRB8; + stc_port_pfsr_field_t PFSRB8_f; + }; + union + { + __IO uint16_t PCRB9; + stc_port_pcr_field_t PCRB9_f; + }; + union + { + __IO uint16_t PFSRB9; + stc_port_pfsr_field_t PFSRB9_f; + }; + union + { + __IO uint16_t PCRB10; + stc_port_pcr_field_t PCRB10_f; + }; + union + { + __IO uint16_t PFSRB10; + stc_port_pfsr_field_t PFSRB10_f; + }; + union + { + __IO uint16_t PCRB11; + stc_port_pcr_field_t PCRB11_f; + }; + union + { + __IO uint16_t PFSRB11; + stc_port_pfsr_field_t PFSRB11_f; + }; + union + { + __IO uint16_t PCRB12; + stc_port_pcr_field_t PCRB12_f; + }; + union + { + __IO uint16_t PFSRB12; + stc_port_pfsr_field_t PFSRB12_f; + }; + union + { + __IO uint16_t PCRB13; + stc_port_pcr_field_t PCRB13_f; + }; + union + { + __IO uint16_t PFSRB13; + stc_port_pfsr_field_t PFSRB13_f; + }; + union + { + __IO uint16_t PCRB14; + stc_port_pcr_field_t PCRB14_f; + }; + union + { + __IO uint16_t PFSRB14; + stc_port_pfsr_field_t PFSRB14_f; + }; + union + { + __IO uint16_t PCRB15; + stc_port_pcr_field_t PCRB15_f; + }; + union + { + __IO uint16_t PFSRB15; + stc_port_pfsr_field_t PFSRB15_f; + }; + union + { + __IO uint16_t PCRC0; + stc_port_pcr_field_t PCRC0_f; + }; + union + { + __IO uint16_t PFSRC0; + stc_port_pfsr_field_t PFSRC0_f; + }; + union + { + __IO uint16_t PCRC1; + stc_port_pcr_field_t PCRC1_f; + }; + union + { + __IO uint16_t PFSRC1; + stc_port_pfsr_field_t PFSRC1_f; + }; + union + { + __IO uint16_t PCRC2; + stc_port_pcr_field_t PCRC2_f; + }; + union + { + __IO uint16_t PFSRC2; + stc_port_pfsr_field_t PFSRC2_f; + }; + union + { + __IO uint16_t PCRC3; + stc_port_pcr_field_t PCRC3_f; + }; + union + { + __IO uint16_t PFSRC3; + stc_port_pfsr_field_t PFSRC3_f; + }; + union + { + __IO uint16_t PCRC4; + stc_port_pcr_field_t PCRC4_f; + }; + union + { + __IO uint16_t PFSRC4; + stc_port_pfsr_field_t PFSRC4_f; + }; + union + { + __IO uint16_t PCRC5; + stc_port_pcr_field_t PCRC5_f; + }; + union + { + __IO uint16_t PFSRC5; + stc_port_pfsr_field_t PFSRC5_f; + }; + union + { + __IO uint16_t PCRC6; + stc_port_pcr_field_t PCRC6_f; + }; + union + { + __IO uint16_t PFSRC6; + stc_port_pfsr_field_t PFSRC6_f; + }; + union + { + __IO uint16_t PCRC7; + stc_port_pcr_field_t PCRC7_f; + }; + union + { + __IO uint16_t PFSRC7; + stc_port_pfsr_field_t PFSRC7_f; + }; + union + { + __IO uint16_t PCRC8; + stc_port_pcr_field_t PCRC8_f; + }; + union + { + __IO uint16_t PFSRC8; + stc_port_pfsr_field_t PFSRC8_f; + }; + union + { + __IO uint16_t PCRC9; + stc_port_pcr_field_t PCRC9_f; + }; + union + { + __IO uint16_t PFSRC9; + stc_port_pfsr_field_t PFSRC9_f; + }; + union + { + __IO uint16_t PCRC10; + stc_port_pcr_field_t PCRC10_f; + }; + union + { + __IO uint16_t PFSRC10; + stc_port_pfsr_field_t PFSRC10_f; + }; + union + { + __IO uint16_t PCRC11; + stc_port_pcr_field_t PCRC11_f; + }; + union + { + __IO uint16_t PFSRC11; + stc_port_pfsr_field_t PFSRC11_f; + }; + union + { + __IO uint16_t PCRC12; + stc_port_pcr_field_t PCRC12_f; + }; + union + { + __IO uint16_t PFSRC12; + stc_port_pfsr_field_t PFSRC12_f; + }; + union + { + __IO uint16_t PCRC13; + stc_port_pcr_field_t PCRC13_f; + }; + union + { + __IO uint16_t PFSRC13; + stc_port_pfsr_field_t PFSRC13_f; + }; + union + { + __IO uint16_t PCRC14; + stc_port_pcr_field_t PCRC14_f; + }; + union + { + __IO uint16_t PFSRC14; + stc_port_pfsr_field_t PFSRC14_f; + }; + union + { + __IO uint16_t PCRC15; + stc_port_pcr_field_t PCRC15_f; + }; + union + { + __IO uint16_t PFSRC15; + stc_port_pfsr_field_t PFSRC15_f; + }; + union + { + __IO uint16_t PCRD0; + stc_port_pcr_field_t PCRD0_f; + }; + union + { + __IO uint16_t PFSRD0; + stc_port_pfsr_field_t PFSRD0_f; + }; + union + { + __IO uint16_t PCRD1; + stc_port_pcr_field_t PCRD1_f; + }; + union + { + __IO uint16_t PFSRD1; + stc_port_pfsr_field_t PFSRD1_f; + }; + union + { + __IO uint16_t PCRD2; + stc_port_pcr_field_t PCRD2_f; + }; + union + { + __IO uint16_t PFSRD2; + stc_port_pfsr_field_t PFSRD2_f; + }; + union + { + __IO uint16_t PCRD3; + stc_port_pcr_field_t PCRD3_f; + }; + union + { + __IO uint16_t PFSRD3; + stc_port_pfsr_field_t PFSRD3_f; + }; + union + { + __IO uint16_t PCRD4; + stc_port_pcr_field_t PCRD4_f; + }; + union + { + __IO uint16_t PFSRD4; + stc_port_pfsr_field_t PFSRD4_f; + }; + union + { + __IO uint16_t PCRD5; + stc_port_pcr_field_t PCRD5_f; + }; + union + { + __IO uint16_t PFSRD5; + stc_port_pfsr_field_t PFSRD5_f; + }; + union + { + __IO uint16_t PCRD6; + stc_port_pcr_field_t PCRD6_f; + }; + union + { + __IO uint16_t PFSRD6; + stc_port_pfsr_field_t PFSRD6_f; + }; + union + { + __IO uint16_t PCRD7; + stc_port_pcr_field_t PCRD7_f; + }; + union + { + __IO uint16_t PFSRD7; + stc_port_pfsr_field_t PFSRD7_f; + }; + union + { + __IO uint16_t PCRD8; + stc_port_pcr_field_t PCRD8_f; + }; + union + { + __IO uint16_t PFSRD8; + stc_port_pfsr_field_t PFSRD8_f; + }; + union + { + __IO uint16_t PCRD9; + stc_port_pcr_field_t PCRD9_f; + }; + union + { + __IO uint16_t PFSRD9; + stc_port_pfsr_field_t PFSRD9_f; + }; + union + { + __IO uint16_t PCRD10; + stc_port_pcr_field_t PCRD10_f; + }; + union + { + __IO uint16_t PFSRD10; + stc_port_pfsr_field_t PFSRD10_f; + }; + union + { + __IO uint16_t PCRD11; + stc_port_pcr_field_t PCRD11_f; + }; + union + { + __IO uint16_t PFSRD11; + stc_port_pfsr_field_t PFSRD11_f; + }; + union + { + __IO uint16_t PCRD12; + stc_port_pcr_field_t PCRD12_f; + }; + union + { + __IO uint16_t PFSRD12; + stc_port_pfsr_field_t PFSRD12_f; + }; + union + { + __IO uint16_t PCRD13; + stc_port_pcr_field_t PCRD13_f; + }; + union + { + __IO uint16_t PFSRD13; + stc_port_pfsr_field_t PFSRD13_f; + }; + union + { + __IO uint16_t PCRD14; + stc_port_pcr_field_t PCRD14_f; + }; + union + { + __IO uint16_t PFSRD14; + stc_port_pfsr_field_t PFSRD14_f; + }; + union + { + __IO uint16_t PCRD15; + stc_port_pcr_field_t PCRD15_f; + }; + union + { + __IO uint16_t PFSRD15; + stc_port_pfsr_field_t PFSRD15_f; + }; + union + { + __IO uint16_t PCRE0; + stc_port_pcr_field_t PCRE0_f; + }; + union + { + __IO uint16_t PFSRE0; + stc_port_pfsr_field_t PFSRE0_f; + }; + union + { + __IO uint16_t PCRE1; + stc_port_pcr_field_t PCRE1_f; + }; + union + { + __IO uint16_t PFSRE1; + stc_port_pfsr_field_t PFSRE1_f; + }; + union + { + __IO uint16_t PCRE2; + stc_port_pcr_field_t PCRE2_f; + }; + union + { + __IO uint16_t PFSRE2; + stc_port_pfsr_field_t PFSRE2_f; + }; + union + { + __IO uint16_t PCRE3; + stc_port_pcr_field_t PCRE3_f; + }; + union + { + __IO uint16_t PFSRE3; + stc_port_pfsr_field_t PFSRE3_f; + }; + union + { + __IO uint16_t PCRE4; + stc_port_pcr_field_t PCRE4_f; + }; + union + { + __IO uint16_t PFSRE4; + stc_port_pfsr_field_t PFSRE4_f; + }; + union + { + __IO uint16_t PCRE5; + stc_port_pcr_field_t PCRE5_f; + }; + union + { + __IO uint16_t PFSRE5; + stc_port_pfsr_field_t PFSRE5_f; + }; + union + { + __IO uint16_t PCRE6; + stc_port_pcr_field_t PCRE6_f; + }; + union + { + __IO uint16_t PFSRE6; + stc_port_pfsr_field_t PFSRE6_f; + }; + union + { + __IO uint16_t PCRE7; + stc_port_pcr_field_t PCRE7_f; + }; + union + { + __IO uint16_t PFSRE7; + stc_port_pfsr_field_t PFSRE7_f; + }; + union + { + __IO uint16_t PCRE8; + stc_port_pcr_field_t PCRE8_f; + }; + union + { + __IO uint16_t PFSRE8; + stc_port_pfsr_field_t PFSRE8_f; + }; + union + { + __IO uint16_t PCRE9; + stc_port_pcr_field_t PCRE9_f; + }; + union + { + __IO uint16_t PFSRE9; + stc_port_pfsr_field_t PFSRE9_f; + }; + union + { + __IO uint16_t PCRE10; + stc_port_pcr_field_t PCRE10_f; + }; + union + { + __IO uint16_t PFSRE10; + stc_port_pfsr_field_t PFSRE10_f; + }; + union + { + __IO uint16_t PCRE11; + stc_port_pcr_field_t PCRE11_f; + }; + union + { + __IO uint16_t PFSRE11; + stc_port_pfsr_field_t PFSRE11_f; + }; + union + { + __IO uint16_t PCRE12; + stc_port_pcr_field_t PCRE12_f; + }; + union + { + __IO uint16_t PFSRE12; + stc_port_pfsr_field_t PFSRE12_f; + }; + union + { + __IO uint16_t PCRE13; + stc_port_pcr_field_t PCRE13_f; + }; + union + { + __IO uint16_t PFSRE13; + stc_port_pfsr_field_t PFSRE13_f; + }; + union + { + __IO uint16_t PCRE14; + stc_port_pcr_field_t PCRE14_f; + }; + union + { + __IO uint16_t PFSRE14; + stc_port_pfsr_field_t PFSRE14_f; + }; + union + { + __IO uint16_t PCRE15; + stc_port_pcr_field_t PCRE15_f; + }; + union + { + __IO uint16_t PFSRE15; + stc_port_pfsr_field_t PFSRE15_f; + }; + union + { + __IO uint16_t PCRH0; + stc_port_pcr_field_t PCRH0_f; + }; + union + { + __IO uint16_t PFSRH0; + stc_port_pfsr_field_t PFSRH0_f; + }; + union + { + __IO uint16_t PCRH1; + stc_port_pcr_field_t PCRH1_f; + }; + union + { + __IO uint16_t PFSRH1; + stc_port_pfsr_field_t PFSRH1_f; + }; + union + { + __IO uint16_t PCRH2; + stc_port_pcr_field_t PCRH2_f; + }; + union + { + __IO uint16_t PFSRH2; + stc_port_pfsr_field_t PFSRH2_f; + }; +}M4_PORT_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_qspi_cr_field_t CR_f; + }; + union + { + __IO uint32_t CSCR; + stc_qspi_cscr_field_t CSCR_f; + }; + union + { + __IO uint32_t FCR; + stc_qspi_fcr_field_t FCR_f; + }; + union + { + __IO uint32_t SR; + stc_qspi_sr_field_t SR_f; + }; + union + { + __IO uint32_t DCOM; + stc_qspi_dcom_field_t DCOM_f; + }; + union + { + __IO uint32_t CCMD; + stc_qspi_ccmd_field_t CCMD_f; + }; + union + { + __IO uint32_t XCMD; + stc_qspi_xcmd_field_t XCMD_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SR2; + stc_qspi_sr2_field_t SR2_f; + }; + uint8_t RESERVED8[2012]; + union + { + __IO uint32_t EXAR; + stc_qspi_exar_field_t EXAR_f; + }; +}M4_QSPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_rtc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_rtc_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_rtc_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_rtc_cr3_field_t CR3_f; + }; + union + { + __IO uint32_t SEC; + stc_rtc_sec_field_t SEC_f; + }; + union + { + __IO uint32_t MIN; + stc_rtc_min_field_t MIN_f; + }; + union + { + __IO uint32_t HOUR; + stc_rtc_hour_field_t HOUR_f; + }; + union + { + __IO uint32_t WEEK; + stc_rtc_week_field_t WEEK_f; + }; + union + { + __IO uint32_t DAY; + stc_rtc_day_field_t DAY_f; + }; + union + { + __IO uint32_t MON; + stc_rtc_mon_field_t MON_f; + }; + union + { + __IO uint32_t YEAR; + stc_rtc_year_field_t YEAR_f; + }; + union + { + __IO uint32_t ALMMIN; + stc_rtc_almmin_field_t ALMMIN_f; + }; + union + { + __IO uint32_t ALMHOUR; + stc_rtc_almhour_field_t ALMHOUR_f; + }; + union + { + __IO uint32_t ALMWEEK; + stc_rtc_almweek_field_t ALMWEEK_f; + }; + union + { + __IO uint32_t ERRCRH; + stc_rtc_errcrh_field_t ERRCRH_f; + }; + union + { + __IO uint32_t ERRCRL; + stc_rtc_errcrl_field_t ERRCRL_f; + }; +}M4_RTC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint16_t BLKSIZE; + stc_sdioc_blksize_field_t BLKSIZE_f; + }; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + union + { + __IO uint16_t TRANSMODE; + stc_sdioc_transmode_field_t TRANSMODE_f; + }; + union + { + __IO uint16_t CMD; + stc_sdioc_cmd_field_t CMD_f; + }; + __IO uint16_t RESP0; + __IO uint16_t RESP1; + __IO uint16_t RESP2; + __IO uint16_t RESP3; + __IO uint16_t RESP4; + __IO uint16_t RESP5; + __IO uint16_t RESP6; + __IO uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + union + { + __IO uint32_t PSTAT; + stc_sdioc_pstat_field_t PSTAT_f; + }; + union + { + __IO uint8_t HOSTCON; + stc_sdioc_hostcon_field_t HOSTCON_f; + }; + union + { + __IO uint8_t PWRCON; + stc_sdioc_pwrcon_field_t PWRCON_f; + }; + union + { + __IO uint8_t BLKGPCON; + stc_sdioc_blkgpcon_field_t BLKGPCON_f; + }; + uint8_t RESERVED20[1]; + union + { + __IO uint16_t CLKCON; + stc_sdioc_clkcon_field_t CLKCON_f; + }; + union + { + __IO uint8_t TOUTCON; + stc_sdioc_toutcon_field_t TOUTCON_f; + }; + union + { + __IO uint8_t SFTRST; + stc_sdioc_sftrst_field_t SFTRST_f; + }; + union + { + __IO uint16_t NORINTST; + stc_sdioc_norintst_field_t NORINTST_f; + }; + union + { + __IO uint16_t ERRINTST; + stc_sdioc_errintst_field_t ERRINTST_f; + }; + union + { + __IO uint16_t NORINTSTEN; + stc_sdioc_norintsten_field_t NORINTSTEN_f; + }; + union + { + __IO uint16_t ERRINTSTEN; + stc_sdioc_errintsten_field_t ERRINTSTEN_f; + }; + union + { + __IO uint16_t NORINTSGEN; + stc_sdioc_norintsgen_field_t NORINTSGEN_f; + }; + union + { + __IO uint16_t ERRINTSGEN; + stc_sdioc_errintsgen_field_t ERRINTSGEN_f; + }; + union + { + __IO uint16_t ATCERRST; + stc_sdioc_atcerrst_field_t ATCERRST_f; + }; + uint8_t RESERVED30[18]; + union + { + __IO uint16_t FEA; + stc_sdioc_fea_field_t FEA_f; + }; + union + { + __IO uint16_t FEE; + stc_sdioc_fee_field_t FEE_f; + }; +}M4_SDIOC_TypeDef; + +typedef struct +{ + __IO uint32_t DR; + union + { + __IO uint32_t CR1; + stc_spi_cr1_field_t CR1_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t CFG1; + stc_spi_cfg1_field_t CFG1_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t SR; + stc_spi_sr_field_t SR_f; + }; + union + { + __IO uint32_t CFG2; + stc_spi_cfg2_field_t CFG2_f; + }; +}M4_SPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t WTCR; + stc_sramc_wtcr_field_t WTCR_f; + }; + union + { + __IO uint32_t WTPR; + stc_sramc_wtpr_field_t WTPR_f; + }; + union + { + __IO uint32_t CKCR; + stc_sramc_ckcr_field_t CKCR_f; + }; + union + { + __IO uint32_t CKPR; + stc_sramc_ckpr_field_t CKPR_f; + }; + union + { + __IO uint32_t CKSR; + stc_sramc_cksr_field_t CKSR_f; + }; +}M4_SRAMC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t SR; + stc_swdt_sr_field_t SR_f; + }; + union + { + __IO uint32_t RR; + stc_swdt_rr_field_t RR_f; + }; +}M4_SWDT_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[12]; + union + { + __IO uint16_t PWR_STPMCR; + stc_sysreg_pwr_stpmcr_field_t PWR_STPMCR_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t CMU_PERICKSEL; + stc_sysreg_cmu_pericksel_field_t CMU_PERICKSEL_f; + }; + union + { + __IO uint16_t CMU_I2SCKSEL; + stc_sysreg_cmu_i2scksel_field_t CMU_I2SCKSEL_f; + }; + union + { + __IO uint32_t PWR_RAMPC0; + stc_sysreg_pwr_rampc0_field_t PWR_RAMPC0_f; + }; + __IO uint16_t PWR_RAMOPM; + uint8_t RESERVED5[2]; + union + { + __IO uint32_t MPU_IPPR; + stc_sysreg_mpu_ippr_field_t MPU_IPPR_f; + }; + union + { + __IO uint32_t CMU_SCFGR; + stc_sysreg_cmu_scfgr_field_t CMU_SCFGR_f; + }; + union + { + __IO uint8_t CMU_UFSCKCFGR; + stc_sysreg_cmu_ufsckcfgr_field_t CMU_UFSCKCFGR_f; + }; + uint8_t RESERVED8[1]; + union + { + __IO uint8_t CMU_CKSWR; + stc_sysreg_cmu_ckswr_field_t CMU_CKSWR_f; + }; + uint8_t RESERVED9[3]; + union + { + __IO uint8_t CMU_PLLCR; + stc_sysreg_cmu_pllcr_field_t CMU_PLLCR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint8_t CMU_UPLLCR; + stc_sysreg_cmu_upllcr_field_t CMU_UPLLCR_f; + }; + uint8_t RESERVED11[3]; + union + { + __IO uint8_t CMU_XTALCR; + stc_sysreg_cmu_xtalcr_field_t CMU_XTALCR_f; + }; + uint8_t RESERVED12[3]; + union + { + __IO uint8_t CMU_HRCCR; + stc_sysreg_cmu_hrccr_field_t CMU_HRCCR_f; + }; + uint8_t RESERVED13[1]; + union + { + __IO uint8_t CMU_MRCCR; + stc_sysreg_cmu_mrccr_field_t CMU_MRCCR_f; + }; + uint8_t RESERVED14[3]; + union + { + __IO uint8_t CMU_OSCSTBSR; + stc_sysreg_cmu_oscstbsr_field_t CMU_OSCSTBSR_f; + }; + union + { + __IO uint8_t CMU_MCO1CFGR; + stc_sysreg_cmu_mco1cfgr_field_t CMU_MCO1CFGR_f; + }; + union + { + __IO uint8_t CMU_MCO2CFGR; + stc_sysreg_cmu_mco2cfgr_field_t CMU_MCO2CFGR_f; + }; + union + { + __IO uint8_t CMU_TPIUCKCFGR; + stc_sysreg_cmu_tpiuckcfgr_field_t CMU_TPIUCKCFGR_f; + }; + union + { + __IO uint8_t CMU_XTALSTDCR; + stc_sysreg_cmu_xtalstdcr_field_t CMU_XTALSTDCR_f; + }; + union + { + __IO uint8_t CMU_XTALSTDSR; + stc_sysreg_cmu_xtalstdsr_field_t CMU_XTALSTDSR_f; + }; + uint8_t RESERVED20[31]; + __IO uint8_t CMU_MRCTRM; + __IO uint8_t CMU_HRCTRM; + uint8_t RESERVED22[63]; + union + { + __IO uint8_t CMU_XTALSTBCR; + stc_sysreg_cmu_xtalstbcr_field_t CMU_XTALSTBCR_f; + }; + uint8_t RESERVED23[29]; + union + { + __IO uint16_t RMU_RSTF0; + stc_sysreg_rmu_rstf0_field_t RMU_RSTF0_f; + }; + uint8_t RESERVED24[30]; + union + { + __IO uint8_t PWR_PVDICR; + stc_sysreg_pwr_pvdicr_field_t PWR_PVDICR_f; + }; + union + { + __IO uint8_t PWR_PVDDSR; + stc_sysreg_pwr_pvddsr_field_t PWR_PVDDSR_f; + }; + uint8_t RESERVED26[30]; + union + { + __IO uint32_t CMU_PLLCFGR; + stc_sysreg_cmu_pllcfgr_field_t CMU_PLLCFGR_f; + }; + union + { + __IO uint32_t CMU_UPLLCFGR; + stc_sysreg_cmu_upllcfgr_field_t CMU_UPLLCFGR_f; + }; + uint8_t RESERVED28[758]; + union + { + __IO uint16_t PWR_FPRC; + stc_sysreg_pwr_fprc_field_t PWR_FPRC_f; + }; + union + { + __IO uint8_t PWR_PWRC0; + stc_sysreg_pwr_pwrc0_field_t PWR_PWRC0_f; + }; + union + { + __IO uint8_t PWR_PWRC1; + stc_sysreg_pwr_pwrc1_field_t PWR_PWRC1_f; + }; + union + { + __IO uint8_t PWR_PWRC2; + stc_sysreg_pwr_pwrc2_field_t PWR_PWRC2_f; + }; + union + { + __IO uint8_t PWR_PWRC3; + stc_sysreg_pwr_pwrc3_field_t PWR_PWRC3_f; + }; + union + { + __IO uint8_t PWR_PDWKE0; + stc_sysreg_pwr_pdwke0_field_t PWR_PDWKE0_f; + }; + union + { + __IO uint8_t PWR_PDWKE1; + stc_sysreg_pwr_pdwke1_field_t PWR_PDWKE1_f; + }; + union + { + __IO uint8_t PWR_PDWKE2; + stc_sysreg_pwr_pdwke2_field_t PWR_PDWKE2_f; + }; + union + { + __IO uint8_t PWR_PDWKES; + stc_sysreg_pwr_pdwkes_field_t PWR_PDWKES_f; + }; + union + { + __IO uint8_t PWR_PDWKF0; + stc_sysreg_pwr_pdwkf0_field_t PWR_PDWKF0_f; + }; + union + { + __IO uint8_t PWR_PDWKF1; + stc_sysreg_pwr_pdwkf1_field_t PWR_PDWKF1_f; + }; + union + { + __IO uint8_t PWR_PWCMR; + stc_sysreg_pwr_pwcmr_field_t PWR_PWCMR_f; + }; + uint8_t RESERVED40[4]; + __IO uint8_t PWR_MDSWCR; + union + { + __IO uint8_t CMU_XTALCFGR; + stc_sysreg_cmu_xtalcfgr_field_t CMU_XTALCFGR_f; + }; + uint8_t RESERVED42[1]; + union + { + __IO uint8_t PWR_PVDCR0; + stc_sysreg_pwr_pvdcr0_field_t PWR_PVDCR0_f; + }; + union + { + __IO uint8_t PWR_PVDCR1; + stc_sysreg_pwr_pvdcr1_field_t PWR_PVDCR1_f; + }; + union + { + __IO uint8_t PWR_PVDFCR; + stc_sysreg_pwr_pvdfcr_field_t PWR_PVDFCR_f; + }; + union + { + __IO uint8_t PWR_PVDLCR; + stc_sysreg_pwr_pvdlcr_field_t PWR_PVDLCR_f; + }; + uint8_t RESERVED46[10]; + union + { + __IO uint8_t CMU_XTAL32CR; + stc_sysreg_cmu_xtal32cr_field_t CMU_XTAL32CR_f; + }; + union + { + __IO uint8_t CMU_XTAL32CFGR; + stc_sysreg_cmu_xtal32cfgr_field_t CMU_XTAL32CFGR_f; + }; + uint8_t RESERVED48[3]; + union + { + __IO uint8_t CMU_XTAL32NFR; + stc_sysreg_cmu_xtal32nfr_field_t CMU_XTAL32NFR_f; + }; + uint8_t RESERVED49[1]; + union + { + __IO uint8_t CMU_LRCCR; + stc_sysreg_cmu_lrccr_field_t CMU_LRCCR_f; + }; + uint8_t RESERVED50[1]; + __IO uint8_t CMU_LRCTRM; + uint8_t RESERVED51[1]; + union + { + __IO uint8_t PWR_XTAL32CS; + stc_sysreg_pwr_xtal32cs_field_t PWR_XTAL32CS_f; + }; +}M4_SYSREG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTAR; + stc_tmr0_cntar_field_t CNTAR_f; + }; + union + { + __IO uint32_t CNTBR; + stc_tmr0_cntbr_field_t CNTBR_f; + }; + union + { + __IO uint32_t CMPAR; + stc_tmr0_cmpar_field_t CMPAR_f; + }; + union + { + __IO uint32_t CMPBR; + stc_tmr0_cmpbr_field_t CMPBR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tmr0_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmr0_stflr_field_t STFLR_f; + }; +}M4_TMR0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + union + { + __IO uint16_t OCSRU; + stc_tmr4_ocsr_field_t OCSRU_f; + }; + union + { + __IO uint16_t OCERU; + stc_tmr4_ocer_field_t OCERU_f; + }; + union + { + __IO uint16_t OCSRV; + stc_tmr4_ocsr_field_t OCSRV_f; + }; + union + { + __IO uint16_t OCERV; + stc_tmr4_ocer_field_t OCERV_f; + }; + union + { + __IO uint16_t OCSRW; + stc_tmr4_ocsr_field_t OCSRW_f; + }; + union + { + __IO uint16_t OCERW; + stc_tmr4_ocer_field_t OCERW_f; + }; + union + { + __IO uint16_t OCMRHUH; + stc_tmr4_ocmrh_field_t OCMRHUH_f; + }; + uint8_t RESERVED13[2]; + union + { + __IO uint32_t OCMRLUL; + stc_tmr4_ocmrl_field_t OCMRLUL_f; + }; + union + { + __IO uint16_t OCMRHVH; + stc_tmr4_ocmrh_field_t OCMRHVH_f; + }; + uint8_t RESERVED15[2]; + union + { + __IO uint32_t OCMRLVL; + stc_tmr4_ocmrl_field_t OCMRLVL_f; + }; + union + { + __IO uint16_t OCMRHWH; + stc_tmr4_ocmrh_field_t OCMRHWH_f; + }; + uint8_t RESERVED17[2]; + union + { + __IO uint32_t OCMRLWL; + stc_tmr4_ocmrl_field_t OCMRLWL_f; + }; + uint8_t RESERVED18[6]; + __IO uint16_t CPSR; + uint8_t RESERVED19[2]; + __IO uint16_t CNTR; + union + { + __IO uint16_t CCSR; + stc_tmr4_ccsr_field_t CCSR_f; + }; + union + { + __IO uint16_t CVPR; + stc_tmr4_cvpr_field_t CVPR_f; + }; + uint8_t RESERVED22[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED25[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED28[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + union + { + __IO uint16_t POCRU; + stc_tmr4_pocr_field_t POCRU_f; + }; + uint8_t RESERVED32[2]; + union + { + __IO uint16_t POCRV; + stc_tmr4_pocr_field_t POCRV_f; + }; + uint8_t RESERVED33[2]; + union + { + __IO uint16_t POCRW; + stc_tmr4_pocr_field_t POCRW_f; + }; + uint8_t RESERVED34[2]; + union + { + __IO uint16_t RCSR; + stc_tmr4_rcsr_field_t RCSR_f; + }; + uint8_t RESERVED35[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED36[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED37[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED38[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED39[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED40[2]; + __IO uint16_t SCCRWL; + union + { + __IO uint16_t SCSRUH; + stc_tmr4_scsr_field_t SCSRUH_f; + }; + union + { + __IO uint16_t SCMRUH; + stc_tmr4_scmr_field_t SCMRUH_f; + }; + union + { + __IO uint16_t SCSRUL; + stc_tmr4_scsr_field_t SCSRUL_f; + }; + union + { + __IO uint16_t SCMRUL; + stc_tmr4_scmr_field_t SCMRUL_f; + }; + union + { + __IO uint16_t SCSRVH; + stc_tmr4_scsr_field_t SCSRVH_f; + }; + union + { + __IO uint16_t SCMRVH; + stc_tmr4_scmr_field_t SCMRVH_f; + }; + union + { + __IO uint16_t SCSRVL; + stc_tmr4_scsr_field_t SCSRVL_f; + }; + union + { + __IO uint16_t SCMRVL; + stc_tmr4_scmr_field_t SCMRVL_f; + }; + union + { + __IO uint16_t SCSRWH; + stc_tmr4_scsr_field_t SCSRWH_f; + }; + union + { + __IO uint16_t SCMRWH; + stc_tmr4_scmr_field_t SCMRWH_f; + }; + union + { + __IO uint16_t SCSRWL; + stc_tmr4_scsr_field_t SCSRWL_f; + }; + union + { + __IO uint16_t SCMRWL; + stc_tmr4_scmr_field_t SCMRWL_f; + }; + uint8_t RESERVED53[16]; + union + { + __IO uint16_t ECSR; + stc_tmr4_ecsr_field_t ECSR_f; + }; +}M4_TMR4_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t ECER1; + stc_tmr4_cr_ecer1_field_t ECER1_f; + }; + uint8_t RESERVED1[2]; + union + { + __IO uint16_t ECER2; + stc_tmr4_cr_ecer2_field_t ECER2_f; + }; + uint8_t RESERVED2[2]; + union + { + __IO uint16_t ECER3; + stc_tmr4_cr_ecer3_field_t ECER3_f; + }; +}M4_TMR4_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tmr6_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tmr6_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tmr6_perbr_field_t PERBR_f; + }; + union + { + __IO uint32_t PERCR; + stc_tmr6_percr_field_t PERCR_f; + }; + union + { + __IO uint32_t GCMAR; + stc_tmr6_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tmr6_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tmr6_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tmr6_gcmdr_field_t GCMDR_f; + }; + union + { + __IO uint32_t GCMER; + stc_tmr6_gcmer_field_t GCMER_f; + }; + union + { + __IO uint32_t GCMFR; + stc_tmr6_gcmfr_field_t GCMFR_f; + }; + union + { + __IO uint32_t SCMAR; + stc_tmr6_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tmr6_scmbr_field_t SCMBR_f; + }; + union + { + __IO uint32_t SCMCR; + stc_tmr6_scmcr_field_t SCMCR_f; + }; + union + { + __IO uint32_t SCMDR; + stc_tmr6_scmdr_field_t SCMDR_f; + }; + union + { + __IO uint32_t SCMER; + stc_tmr6_scmer_field_t SCMER_f; + }; + union + { + __IO uint32_t SCMFR; + stc_tmr6_scmfr_field_t SCMFR_f; + }; + union + { + __IO uint32_t DTUAR; + stc_tmr6_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tmr6_dtdar_field_t DTDAR_f; + }; + union + { + __IO uint32_t DTUBR; + stc_tmr6_dtubr_field_t DTUBR_f; + }; + union + { + __IO uint32_t DTDBR; + stc_tmr6_dtdbr_field_t DTDBR_f; + }; + union + { + __IO uint32_t GCONR; + stc_tmr6_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tmr6_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tmr6_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tmr6_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tmr6_dconr_field_t DCONR_f; + }; + uint8_t RESERVED25[4]; + union + { + __IO uint32_t FCONR; + stc_tmr6_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tmr6_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmr6_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tmr6_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tmr6_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCLRR; + stc_tmr6_hclrr_field_t HCLRR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tmr6_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tmr6_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tmr6_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tmr6_hcdor_field_t HCDOR_f; + }; +}M4_TMR6_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[1012]; + union + { + __IO uint32_t SSTAR; + stc_tmr6_cr_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tmr6_cr_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tmr6_cr_sclrr_field_t SCLRR_f; + }; +}M4_TMR6_CR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tmra_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tmra_perar_field_t PERAR_f; + }; + uint8_t RESERVED2[56]; + union + { + __IO uint32_t CMPAR1; + stc_tmra_cmpar_field_t CMPAR1_f; + }; + union + { + __IO uint32_t CMPAR2; + stc_tmra_cmpar_field_t CMPAR2_f; + }; + union + { + __IO uint32_t CMPAR3; + stc_tmra_cmpar_field_t CMPAR3_f; + }; + union + { + __IO uint32_t CMPAR4; + stc_tmra_cmpar_field_t CMPAR4_f; + }; + union + { + __IO uint32_t CMPAR5; + stc_tmra_cmpar_field_t CMPAR5_f; + }; + union + { + __IO uint32_t CMPAR6; + stc_tmra_cmpar_field_t CMPAR6_f; + }; + union + { + __IO uint32_t CMPAR7; + stc_tmra_cmpar_field_t CMPAR7_f; + }; + union + { + __IO uint32_t CMPAR8; + stc_tmra_cmpar_field_t CMPAR8_f; + }; + uint8_t RESERVED10[32]; + union + { + __IO uint32_t BCSTR; + stc_tmra_bcstr_field_t BCSTR_f; + }; + union + { + __IO uint32_t HCONR; + stc_tmra_hconr_field_t HCONR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tmra_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tmra_hcdor_field_t HCDOR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tmra_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t ECONR; + stc_tmra_econr_field_t ECONR_f; + }; + union + { + __IO uint32_t FCONR; + stc_tmra_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tmra_stflr_field_t STFLR_f; + }; + uint8_t RESERVED18[32]; + union + { + __IO uint32_t BCONR1; + stc_tmra_bconr_field_t BCONR1_f; + }; + uint8_t RESERVED19[4]; + union + { + __IO uint32_t BCONR2; + stc_tmra_bconr_field_t BCONR2_f; + }; + uint8_t RESERVED20[4]; + union + { + __IO uint32_t BCONR3; + stc_tmra_bconr_field_t BCONR3_f; + }; + uint8_t RESERVED21[4]; + union + { + __IO uint32_t BCONR4; + stc_tmra_bconr_field_t BCONR4_f; + }; + uint8_t RESERVED22[36]; + union + { + __IO uint32_t CCONR1; + stc_tmra_cconr_field_t CCONR1_f; + }; + union + { + __IO uint32_t CCONR2; + stc_tmra_cconr_field_t CCONR2_f; + }; + union + { + __IO uint32_t CCONR3; + stc_tmra_cconr_field_t CCONR3_f; + }; + union + { + __IO uint32_t CCONR4; + stc_tmra_cconr_field_t CCONR4_f; + }; + union + { + __IO uint32_t CCONR5; + stc_tmra_cconr_field_t CCONR5_f; + }; + union + { + __IO uint32_t CCONR6; + stc_tmra_cconr_field_t CCONR6_f; + }; + union + { + __IO uint32_t CCONR7; + stc_tmra_cconr_field_t CCONR7_f; + }; + union + { + __IO uint32_t CCONR8; + stc_tmra_cconr_field_t CCONR8_f; + }; + uint8_t RESERVED30[32]; + union + { + __IO uint32_t PCONR1; + stc_tmra_pconr_field_t PCONR1_f; + }; + union + { + __IO uint32_t PCONR2; + stc_tmra_pconr_field_t PCONR2_f; + }; + union + { + __IO uint32_t PCONR3; + stc_tmra_pconr_field_t PCONR3_f; + }; + union + { + __IO uint32_t PCONR4; + stc_tmra_pconr_field_t PCONR4_f; + }; + union + { + __IO uint32_t PCONR5; + stc_tmra_pconr_field_t PCONR5_f; + }; + union + { + __IO uint32_t PCONR6; + stc_tmra_pconr_field_t PCONR6_f; + }; + union + { + __IO uint32_t PCONR7; + stc_tmra_pconr_field_t PCONR7_f; + }; + union + { + __IO uint32_t PCONR8; + stc_tmra_pconr_field_t PCONR8_f; + }; +}M4_TMRA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_trng_cr_field_t CR_f; + }; + union + { + __IO uint32_t MR; + stc_trng_mr_field_t MR_f; + }; + uint8_t RESERVED2[4]; + __IO uint32_t DR0; + __IO uint32_t DR1; +}M4_TRNG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SR; + stc_usart_sr_field_t SR_f; + }; + union + { + __IO uint32_t DR; + stc_usart_dr_field_t DR_f; + }; + union + { + __IO uint32_t BRR; + stc_usart_brr_field_t BRR_f; + }; + union + { + __IO uint32_t CR1; + stc_usart_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_usart_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t CR3; + stc_usart_cr3_field_t CR3_f; + }; + union + { + __IO uint32_t PR; + stc_usart_pr_field_t PR_f; + }; +}M4_USART_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t USBFS_GVBUSCFG; + stc_usbfs_usbfs_gvbuscfg_field_t USBFS_GVBUSCFG_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t GAHBCFG; + stc_usbfs_gahbcfg_field_t GAHBCFG_f; + }; + union + { + __IO uint32_t GUSBCFG; + stc_usbfs_gusbcfg_field_t GUSBCFG_f; + }; + union + { + __IO uint32_t GRSTCTL; + stc_usbfs_grstctl_field_t GRSTCTL_f; + }; + union + { + __IO uint32_t GINTSTS; + stc_usbfs_gintsts_field_t GINTSTS_f; + }; + union + { + __IO uint32_t GINTMSK; + stc_usbfs_gintmsk_field_t GINTMSK_f; + }; + union + { + __IO uint32_t GRXSTSR; + stc_usbfs_grxstsr_field_t GRXSTSR_f; + }; + union + { + __IO uint32_t GRXSTSP; + stc_usbfs_grxstsp_field_t GRXSTSP_f; + }; + union + { + __IO uint32_t GRXFSIZ; + stc_usbfs_grxfsiz_field_t GRXFSIZ_f; + }; + union + { + __IO uint32_t HNPTXFSIZ; + stc_usbfs_hnptxfsiz_field_t HNPTXFSIZ_f; + }; + union + { + __IO uint32_t HNPTXSTS; + stc_usbfs_hnptxsts_field_t HNPTXSTS_f; + }; + uint8_t RESERVED11[12]; + __IO uint32_t CID; + uint8_t RESERVED12[192]; + union + { + __IO uint32_t HPTXFSIZ; + stc_usbfs_hptxfsiz_field_t HPTXFSIZ_f; + }; + union + { + __IO uint32_t DIEPTXF1; + stc_usbfs_dieptxf_field_t DIEPTXF1_f; + }; + union + { + __IO uint32_t DIEPTXF2; + stc_usbfs_dieptxf_field_t DIEPTXF2_f; + }; + union + { + __IO uint32_t DIEPTXF3; + stc_usbfs_dieptxf_field_t DIEPTXF3_f; + }; + union + { + __IO uint32_t DIEPTXF4; + stc_usbfs_dieptxf_field_t DIEPTXF4_f; + }; + union + { + __IO uint32_t DIEPTXF5; + stc_usbfs_dieptxf_field_t DIEPTXF5_f; + }; + uint8_t RESERVED18[744]; + union + { + __IO uint32_t HCFG; + stc_usbfs_hcfg_field_t HCFG_f; + }; + union + { + __IO uint32_t HFIR; + stc_usbfs_hfir_field_t HFIR_f; + }; + union + { + __IO uint32_t HFNUM; + stc_usbfs_hfnum_field_t HFNUM_f; + }; + uint8_t RESERVED21[4]; + union + { + __IO uint32_t HPTXSTS; + stc_usbfs_hptxsts_field_t HPTXSTS_f; + }; + union + { + __IO uint32_t HAINT; + stc_usbfs_haint_field_t HAINT_f; + }; + union + { + __IO uint32_t HAINTMSK; + stc_usbfs_haintmsk_field_t HAINTMSK_f; + }; + uint8_t RESERVED24[36]; + union + { + __IO uint32_t HPRT; + stc_usbfs_hprt_field_t HPRT_f; + }; + uint8_t RESERVED25[188]; + union + { + __IO uint32_t HCCHAR0; + stc_usbfs_hcchar_field_t HCCHAR0_f; + }; + uint8_t RESERVED26[4]; + union + { + __IO uint32_t HCINT0; + stc_usbfs_hcint_field_t HCINT0_f; + }; + union + { + __IO uint32_t HCINTMSK0; + stc_usbfs_hcintmsk_field_t HCINTMSK0_f; + }; + union + { + __IO uint32_t HCTSIZ0; + stc_usbfs_hctsiz_field_t HCTSIZ0_f; + }; + __IO uint32_t HCDMA0; + uint8_t RESERVED30[8]; + union + { + __IO uint32_t HCCHAR1; + stc_usbfs_hcchar_field_t HCCHAR1_f; + }; + uint8_t RESERVED31[4]; + union + { + __IO uint32_t HCINT1; + stc_usbfs_hcint_field_t HCINT1_f; + }; + union + { + __IO uint32_t HCINTMSK1; + stc_usbfs_hcintmsk_field_t HCINTMSK1_f; + }; + union + { + __IO uint32_t HCTSIZ1; + stc_usbfs_hctsiz_field_t HCTSIZ1_f; + }; + __IO uint32_t HCDMA1; + uint8_t RESERVED35[8]; + union + { + __IO uint32_t HCCHAR2; + stc_usbfs_hcchar_field_t HCCHAR2_f; + }; + uint8_t RESERVED36[4]; + union + { + __IO uint32_t HCINT2; + stc_usbfs_hcint_field_t HCINT2_f; + }; + union + { + __IO uint32_t HCINTMSK2; + stc_usbfs_hcintmsk_field_t HCINTMSK2_f; + }; + union + { + __IO uint32_t HCTSIZ2; + stc_usbfs_hctsiz_field_t HCTSIZ2_f; + }; + __IO uint32_t HCDMA2; + uint8_t RESERVED40[8]; + union + { + __IO uint32_t HCCHAR3; + stc_usbfs_hcchar_field_t HCCHAR3_f; + }; + uint8_t RESERVED41[4]; + union + { + __IO uint32_t HCINT3; + stc_usbfs_hcint_field_t HCINT3_f; + }; + union + { + __IO uint32_t HCINTMSK3; + stc_usbfs_hcintmsk_field_t HCINTMSK3_f; + }; + union + { + __IO uint32_t HCTSIZ3; + stc_usbfs_hctsiz_field_t HCTSIZ3_f; + }; + __IO uint32_t HCDMA3; + uint8_t RESERVED45[8]; + union + { + __IO uint32_t HCCHAR4; + stc_usbfs_hcchar_field_t HCCHAR4_f; + }; + uint8_t RESERVED46[4]; + union + { + __IO uint32_t HCINT4; + stc_usbfs_hcint_field_t HCINT4_f; + }; + union + { + __IO uint32_t HCINTMSK4; + stc_usbfs_hcintmsk_field_t HCINTMSK4_f; + }; + union + { + __IO uint32_t HCTSIZ4; + stc_usbfs_hctsiz_field_t HCTSIZ4_f; + }; + __IO uint32_t HCDMA4; + uint8_t RESERVED50[8]; + union + { + __IO uint32_t HCCHAR5; + stc_usbfs_hcchar_field_t HCCHAR5_f; + }; + uint8_t RESERVED51[4]; + union + { + __IO uint32_t HCINT5; + stc_usbfs_hcint_field_t HCINT5_f; + }; + union + { + __IO uint32_t HCINTMSK5; + stc_usbfs_hcintmsk_field_t HCINTMSK5_f; + }; + union + { + __IO uint32_t HCTSIZ5; + stc_usbfs_hctsiz_field_t HCTSIZ5_f; + }; + __IO uint32_t HCDMA5; + uint8_t RESERVED55[8]; + union + { + __IO uint32_t HCCHAR6; + stc_usbfs_hcchar_field_t HCCHAR6_f; + }; + uint8_t RESERVED56[4]; + union + { + __IO uint32_t HCINT6; + stc_usbfs_hcint_field_t HCINT6_f; + }; + union + { + __IO uint32_t HCINTMSK6; + stc_usbfs_hcintmsk_field_t HCINTMSK6_f; + }; + union + { + __IO uint32_t HCTSIZ6; + stc_usbfs_hctsiz_field_t HCTSIZ6_f; + }; + __IO uint32_t HCDMA6; + uint8_t RESERVED60[8]; + union + { + __IO uint32_t HCCHAR7; + stc_usbfs_hcchar_field_t HCCHAR7_f; + }; + uint8_t RESERVED61[4]; + union + { + __IO uint32_t HCINT7; + stc_usbfs_hcint_field_t HCINT7_f; + }; + union + { + __IO uint32_t HCINTMSK7; + stc_usbfs_hcintmsk_field_t HCINTMSK7_f; + }; + union + { + __IO uint32_t HCTSIZ7; + stc_usbfs_hctsiz_field_t HCTSIZ7_f; + }; + __IO uint32_t HCDMA7; + uint8_t RESERVED65[8]; + union + { + __IO uint32_t HCCHAR8; + stc_usbfs_hcchar_field_t HCCHAR8_f; + }; + uint8_t RESERVED66[4]; + union + { + __IO uint32_t HCINT8; + stc_usbfs_hcint_field_t HCINT8_f; + }; + union + { + __IO uint32_t HCINTMSK8; + stc_usbfs_hcintmsk_field_t HCINTMSK8_f; + }; + union + { + __IO uint32_t HCTSIZ8; + stc_usbfs_hctsiz_field_t HCTSIZ8_f; + }; + __IO uint32_t HCDMA8; + uint8_t RESERVED70[8]; + union + { + __IO uint32_t HCCHAR9; + stc_usbfs_hcchar_field_t HCCHAR9_f; + }; + uint8_t RESERVED71[4]; + union + { + __IO uint32_t HCINT9; + stc_usbfs_hcint_field_t HCINT9_f; + }; + union + { + __IO uint32_t HCINTMSK9; + stc_usbfs_hcintmsk_field_t HCINTMSK9_f; + }; + union + { + __IO uint32_t HCTSIZ9; + stc_usbfs_hctsiz_field_t HCTSIZ9_f; + }; + __IO uint32_t HCDMA9; + uint8_t RESERVED75[8]; + union + { + __IO uint32_t HCCHAR10; + stc_usbfs_hcchar_field_t HCCHAR10_f; + }; + uint8_t RESERVED76[4]; + union + { + __IO uint32_t HCINT10; + stc_usbfs_hcint_field_t HCINT10_f; + }; + union + { + __IO uint32_t HCINTMSK10; + stc_usbfs_hcintmsk_field_t HCINTMSK10_f; + }; + union + { + __IO uint32_t HCTSIZ10; + stc_usbfs_hctsiz_field_t HCTSIZ10_f; + }; + __IO uint32_t HCDMA10; + uint8_t RESERVED80[8]; + union + { + __IO uint32_t HCCHAR11; + stc_usbfs_hcchar_field_t HCCHAR11_f; + }; + uint8_t RESERVED81[4]; + union + { + __IO uint32_t HCINT11; + stc_usbfs_hcint_field_t HCINT11_f; + }; + union + { + __IO uint32_t HCINTMSK11; + stc_usbfs_hcintmsk_field_t HCINTMSK11_f; + }; + union + { + __IO uint32_t HCTSIZ11; + stc_usbfs_hctsiz_field_t HCTSIZ11_f; + }; + __IO uint32_t HCDMA11; + uint8_t RESERVED85[392]; + union + { + __IO uint32_t DCFG; + stc_usbfs_dcfg_field_t DCFG_f; + }; + union + { + __IO uint32_t DCTL; + stc_usbfs_dctl_field_t DCTL_f; + }; + union + { + __IO uint32_t DSTS; + stc_usbfs_dsts_field_t DSTS_f; + }; + uint8_t RESERVED88[4]; + union + { + __IO uint32_t DIEPMSK; + stc_usbfs_diepmsk_field_t DIEPMSK_f; + }; + union + { + __IO uint32_t DOEPMSK; + stc_usbfs_doepmsk_field_t DOEPMSK_f; + }; + union + { + __IO uint32_t DAINT; + stc_usbfs_daint_field_t DAINT_f; + }; + union + { + __IO uint32_t DAINTMSK; + stc_usbfs_daintmsk_field_t DAINTMSK_f; + }; + uint8_t RESERVED92[20]; + union + { + __IO uint32_t DIEPEMPMSK; + stc_usbfs_diepempmsk_field_t DIEPEMPMSK_f; + }; + uint8_t RESERVED93[200]; + union + { + __IO uint32_t DIEPCTL0; + stc_usbfs_diepctl0_field_t DIEPCTL0_f; + }; + uint8_t RESERVED94[4]; + union + { + __IO uint32_t DIEPINT0; + stc_usbfs_diepint0_field_t DIEPINT0_f; + }; + uint8_t RESERVED95[4]; + union + { + __IO uint32_t DIEPTSIZ0; + stc_usbfs_dieptsiz0_field_t DIEPTSIZ0_f; + }; + __IO uint32_t DIEPDMA0; + union + { + __IO uint32_t DTXFSTS0; + stc_usbfs_dtxfsts0_field_t DTXFSTS0_f; + }; + uint8_t RESERVED98[4]; + union + { + __IO uint32_t DIEPCTL1; + stc_usbfs_diepctl_field_t DIEPCTL1_f; + }; + uint8_t RESERVED99[4]; + union + { + __IO uint32_t DIEPINT1; + stc_usbfs_diepint_field_t DIEPINT1_f; + }; + uint8_t RESERVED100[4]; + union + { + __IO uint32_t DIEPTSIZ1; + stc_usbfs_dieptsiz_field_t DIEPTSIZ1_f; + }; + __IO uint32_t DIEPDMA1; + union + { + __IO uint32_t DTXFSTS1; + stc_usbfs_dtxfsts_field_t DTXFSTS1_f; + }; + uint8_t RESERVED103[4]; + union + { + __IO uint32_t DIEPCTL2; + stc_usbfs_diepctl_field_t DIEPCTL2_f; + }; + uint8_t RESERVED104[4]; + union + { + __IO uint32_t DIEPINT2; + stc_usbfs_diepint_field_t DIEPINT2_f; + }; + uint8_t RESERVED105[4]; + union + { + __IO uint32_t DIEPTSIZ2; + stc_usbfs_dieptsiz_field_t DIEPTSIZ2_f; + }; + __IO uint32_t DIEPDMA2; + union + { + __IO uint32_t DTXFSTS2; + stc_usbfs_dtxfsts_field_t DTXFSTS2_f; + }; + uint8_t RESERVED108[4]; + union + { + __IO uint32_t DIEPCTL3; + stc_usbfs_diepctl_field_t DIEPCTL3_f; + }; + uint8_t RESERVED109[4]; + union + { + __IO uint32_t DIEPINT3; + stc_usbfs_diepint_field_t DIEPINT3_f; + }; + uint8_t RESERVED110[4]; + union + { + __IO uint32_t DIEPTSIZ3; + stc_usbfs_dieptsiz_field_t DIEPTSIZ3_f; + }; + __IO uint32_t DIEPDMA3; + union + { + __IO uint32_t DTXFSTS3; + stc_usbfs_dtxfsts_field_t DTXFSTS3_f; + }; + uint8_t RESERVED113[4]; + union + { + __IO uint32_t DIEPCTL4; + stc_usbfs_diepctl_field_t DIEPCTL4_f; + }; + uint8_t RESERVED114[4]; + union + { + __IO uint32_t DIEPINT4; + stc_usbfs_diepint_field_t DIEPINT4_f; + }; + uint8_t RESERVED115[4]; + union + { + __IO uint32_t DIEPTSIZ4; + stc_usbfs_dieptsiz_field_t DIEPTSIZ4_f; + }; + __IO uint32_t DIEPDMA4; + union + { + __IO uint32_t DTXFSTS4; + stc_usbfs_dtxfsts_field_t DTXFSTS4_f; + }; + uint8_t RESERVED118[4]; + union + { + __IO uint32_t DIEPCTL5; + stc_usbfs_diepctl_field_t DIEPCTL5_f; + }; + uint8_t RESERVED119[4]; + union + { + __IO uint32_t DIEPINT5; + stc_usbfs_diepint_field_t DIEPINT5_f; + }; + uint8_t RESERVED120[4]; + union + { + __IO uint32_t DIEPTSIZ5; + stc_usbfs_dieptsiz_field_t DIEPTSIZ5_f; + }; + __IO uint32_t DIEPDMA5; + union + { + __IO uint32_t DTXFSTS5; + stc_usbfs_dtxfsts_field_t DTXFSTS5_f; + }; + uint8_t RESERVED123[324]; + union + { + __IO uint32_t DOEPCTL0; + stc_usbfs_doepctl0_field_t DOEPCTL0_f; + }; + uint8_t RESERVED124[4]; + union + { + __IO uint32_t DOEPINT0; + stc_usbfs_doepint_field_t DOEPINT0_f; + }; + uint8_t RESERVED125[4]; + union + { + __IO uint32_t DOEPTSIZ0; + stc_usbfs_doeptsiz0_field_t DOEPTSIZ0_f; + }; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED127[8]; + union + { + __IO uint32_t DOEPCTL1; + stc_usbfs_doepctl_field_t DOEPCTL1_f; + }; + uint8_t RESERVED128[4]; + union + { + __IO uint32_t DOEPINT1; + stc_usbfs_doepint_field_t DOEPINT1_f; + }; + uint8_t RESERVED129[4]; + union + { + __IO uint32_t DOEPTSIZ1; + stc_usbfs_doeptsiz_field_t DOEPTSIZ1_f; + }; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED131[8]; + union + { + __IO uint32_t DOEPCTL2; + stc_usbfs_doepctl_field_t DOEPCTL2_f; + }; + uint8_t RESERVED132[4]; + union + { + __IO uint32_t DOEPINT2; + stc_usbfs_doepint_field_t DOEPINT2_f; + }; + uint8_t RESERVED133[4]; + union + { + __IO uint32_t DOEPTSIZ2; + stc_usbfs_doeptsiz_field_t DOEPTSIZ2_f; + }; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED135[8]; + union + { + __IO uint32_t DOEPCTL3; + stc_usbfs_doepctl_field_t DOEPCTL3_f; + }; + uint8_t RESERVED136[4]; + union + { + __IO uint32_t DOEPINT3; + stc_usbfs_doepint_field_t DOEPINT3_f; + }; + uint8_t RESERVED137[4]; + union + { + __IO uint32_t DOEPTSIZ3; + stc_usbfs_doeptsiz_field_t DOEPTSIZ3_f; + }; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED139[8]; + union + { + __IO uint32_t DOEPCTL4; + stc_usbfs_doepctl_field_t DOEPCTL4_f; + }; + uint8_t RESERVED140[4]; + union + { + __IO uint32_t DOEPINT4; + stc_usbfs_doepint_field_t DOEPINT4_f; + }; + uint8_t RESERVED141[4]; + union + { + __IO uint32_t DOEPTSIZ4; + stc_usbfs_doeptsiz_field_t DOEPTSIZ4_f; + }; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED143[8]; + union + { + __IO uint32_t DOEPCTL5; + stc_usbfs_doepctl_field_t DOEPCTL5_f; + }; + uint8_t RESERVED144[4]; + union + { + __IO uint32_t DOEPINT5; + stc_usbfs_doepint_field_t DOEPINT5_f; + }; + uint8_t RESERVED145[4]; + union + { + __IO uint32_t DOEPTSIZ5; + stc_usbfs_doeptsiz_field_t DOEPTSIZ5_f; + }; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED147[584]; + union + { + __IO uint32_t PCGCCTL; + stc_usbfs_pcgcctl_field_t PCGCCTL_f; + }; +}M4_USBFS_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_wdt_cr_field_t CR_f; + }; + union + { + __IO uint32_t SR; + stc_wdt_sr_field_t SR_f; + }; + union + { + __IO uint32_t RR; + stc_wdt_rr_field_t RR_f; + }; +}M4_WDT_TypeDef; + +typedef struct +{ + union + { + __IO uint16_t CR; + stc_wktm_cr_field_t CR_f; + }; +}M4_WKTM_TypeDef; + + + +#define M4_ADC1 ((M4_ADC_TypeDef *)0x40040000UL) +#define M4_ADC2 ((M4_ADC_TypeDef *)0x40040400UL) +#define M4_AES ((M4_AES_TypeDef *)0x40008000UL) +#define M4_AOS ((M4_AOS_TypeDef *)0x40010800UL) +#define M4_CAN ((M4_CAN_TypeDef *)0x40070400UL) +#define M4_CMP1 ((M4_CMP_TypeDef *)0x4004A000UL) +#define M4_CMP2 ((M4_CMP_TypeDef *)0x4004A010UL) +#define M4_CMP3 ((M4_CMP_TypeDef *)0x4004A020UL) +#define M4_CMP_CR ((M4_CMP_CR_TypeDef *)0x4004A000UL) +#define M4_CRC ((M4_CRC_TypeDef *)0x40008C00UL) +#define M4_DBGC ((M4_DBGC_TypeDef *)0xE0042000UL) +#define M4_DCU1 ((M4_DCU_TypeDef *)0x40052000UL) +#define M4_DCU2 ((M4_DCU_TypeDef *)0x40052400UL) +#define M4_DCU3 ((M4_DCU_TypeDef *)0x40052800UL) +#define M4_DCU4 ((M4_DCU_TypeDef *)0x40052C00UL) +#define M4_DMA1 ((M4_DMA_TypeDef *)0x40053000UL) +#define M4_DMA2 ((M4_DMA_TypeDef *)0x40053400UL) +#define M4_EFM ((M4_EFM_TypeDef *)0x40010400UL) +#define M4_EMB1 ((M4_EMB_TypeDef *)0x40017C00UL) +#define M4_EMB2 ((M4_EMB_TypeDef *)0x40017C20UL) +#define M4_EMB3 ((M4_EMB_TypeDef *)0x40017C40UL) +#define M4_EMB4 ((M4_EMB_TypeDef *)0x40017C60UL) +#define M4_FCM ((M4_FCM_TypeDef *)0x40048400UL) +#define M4_HASH ((M4_HASH_TypeDef *)0x40008400UL) +#define M4_I2C1 ((M4_I2C_TypeDef *)0x4004E000UL) +#define M4_I2C2 ((M4_I2C_TypeDef *)0x4004E400UL) +#define M4_I2C3 ((M4_I2C_TypeDef *)0x4004E800UL) +#define M4_I2S1 ((M4_I2S_TypeDef *)0x4001E000UL) +#define M4_I2S2 ((M4_I2S_TypeDef *)0x4001E400UL) +#define M4_I2S3 ((M4_I2S_TypeDef *)0x40022000UL) +#define M4_I2S4 ((M4_I2S_TypeDef *)0x40022400UL) +#define M4_ICG ((M4_ICG_TypeDef *)0x00000400UL) +#define M4_INTC ((M4_INTC_TypeDef *)0x40051000UL) +#define M4_KEYSCAN ((M4_KEYSCAN_TypeDef *)0x40050C00UL) +#define M4_MPU ((M4_MPU_TypeDef *)0x40050000UL) +#define M4_MSTP ((M4_MSTP_TypeDef *)0x40048000UL) +#define M4_OTS ((M4_OTS_TypeDef *)0x4004A400UL) +#define M4_PERIC ((M4_PERIC_TypeDef *)0x40055400UL) +#define M4_PORT ((M4_PORT_TypeDef *)0x40053800UL) +#define M4_QSPI ((M4_QSPI_TypeDef *)0x9C000000UL) +#define M4_RTC ((M4_RTC_TypeDef *)0x4004C000UL) +#define M4_SDIOC1 ((M4_SDIOC_TypeDef *)0x4006FC00UL) +#define M4_SDIOC2 ((M4_SDIOC_TypeDef *)0x40070000UL) +#define M4_SPI1 ((M4_SPI_TypeDef *)0x4001C000UL) +#define M4_SPI2 ((M4_SPI_TypeDef *)0x4001C400UL) +#define M4_SPI3 ((M4_SPI_TypeDef *)0x40020000UL) +#define M4_SPI4 ((M4_SPI_TypeDef *)0x40020400UL) +#define M4_SRAMC ((M4_SRAMC_TypeDef *)0x40050800UL) +#define M4_SWDT ((M4_SWDT_TypeDef *)0x40049400UL) +#define M4_SYSREG ((M4_SYSREG_TypeDef *)0x40054000UL) +#define M4_TMR01 ((M4_TMR0_TypeDef *)0x40024000UL) +#define M4_TMR02 ((M4_TMR0_TypeDef *)0x40024400UL) +#define M4_TMR41 ((M4_TMR4_TypeDef *)0x40017000UL) +#define M4_TMR42 ((M4_TMR4_TypeDef *)0x40024800UL) +#define M4_TMR43 ((M4_TMR4_TypeDef *)0x40024C00UL) +#define M4_TMR4_CR ((M4_TMR4_CR_TypeDef *)0x40055408UL) +#define M4_TMR61 ((M4_TMR6_TypeDef *)0x40018000UL) +#define M4_TMR62 ((M4_TMR6_TypeDef *)0x40018400UL) +#define M4_TMR63 ((M4_TMR6_TypeDef *)0x40018800UL) +#define M4_TMR6_CR ((M4_TMR6_CR_TypeDef *)0x40018000UL) +#define M4_TMRA1 ((M4_TMRA_TypeDef *)0x40015000UL) +#define M4_TMRA2 ((M4_TMRA_TypeDef *)0x40015400UL) +#define M4_TMRA3 ((M4_TMRA_TypeDef *)0x40015800UL) +#define M4_TMRA4 ((M4_TMRA_TypeDef *)0x40015C00UL) +#define M4_TMRA5 ((M4_TMRA_TypeDef *)0x40016000UL) +#define M4_TMRA6 ((M4_TMRA_TypeDef *)0x40016400UL) +#define M4_TRNG ((M4_TRNG_TypeDef *)0x40041000UL) +#define M4_USART1 ((M4_USART_TypeDef *)0x4001D000UL) +#define M4_USART2 ((M4_USART_TypeDef *)0x4001D400UL) +#define M4_USART3 ((M4_USART_TypeDef *)0x40021000UL) +#define M4_USART4 ((M4_USART_TypeDef *)0x40021400UL) +#define M4_USBFS ((M4_USBFS_TypeDef *)0x400C0000UL) +#define M4_WDT ((M4_WDT_TypeDef *)0x40049000UL) +#define M4_WKTM ((M4_WKTM_TypeDef *)0x4004C400UL) + + +#define bM4_ADC1_STR_STRT (*((volatile unsigned int*)(0x42800000UL))) +#define bM4_ADC1_CR0_MS0 (*((volatile unsigned int*)(0x42800040UL))) +#define bM4_ADC1_CR0_MS1 (*((volatile unsigned int*)(0x42800044UL))) +#define bM4_ADC1_CR0_ACCSEL0 (*((volatile unsigned int*)(0x42800050UL))) +#define bM4_ADC1_CR0_ACCSEL1 (*((volatile unsigned int*)(0x42800054UL))) +#define bM4_ADC1_CR0_CLREN (*((volatile unsigned int*)(0x42800058UL))) +#define bM4_ADC1_CR0_DFMT (*((volatile unsigned int*)(0x4280005CUL))) +#define bM4_ADC1_CR0_AVCNT0 (*((volatile unsigned int*)(0x42800060UL))) +#define bM4_ADC1_CR0_AVCNT1 (*((volatile unsigned int*)(0x42800064UL))) +#define bM4_ADC1_CR0_AVCNT2 (*((volatile unsigned int*)(0x42800068UL))) +#define bM4_ADC1_CR1_RSCHSEL (*((volatile unsigned int*)(0x42800088UL))) +#define bM4_ADC1_TRGSR_TRGSELA0 (*((volatile unsigned int*)(0x42800140UL))) +#define bM4_ADC1_TRGSR_TRGSELA1 (*((volatile unsigned int*)(0x42800144UL))) +#define bM4_ADC1_TRGSR_TRGSELA2 (*((volatile unsigned int*)(0x42800148UL))) +#define bM4_ADC1_TRGSR_TRGENA (*((volatile unsigned int*)(0x4280015CUL))) +#define bM4_ADC1_TRGSR_TRGSELB0 (*((volatile unsigned int*)(0x42800160UL))) +#define bM4_ADC1_TRGSR_TRGSELB1 (*((volatile unsigned int*)(0x42800164UL))) +#define bM4_ADC1_TRGSR_TRGSELB2 (*((volatile unsigned int*)(0x42800168UL))) +#define bM4_ADC1_TRGSR_TRGENB (*((volatile unsigned int*)(0x4280017CUL))) +#define bM4_ADC1_CHSELRA1_CHSELA16 (*((volatile unsigned int*)(0x428001C0UL))) +#define bM4_ADC1_CHSELRB1_CHSELB16 (*((volatile unsigned int*)(0x42800240UL))) +#define bM4_ADC1_AVCHSELR1_AVCHSEL16 (*((volatile unsigned int*)(0x428002C0UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX0 (*((volatile unsigned int*)(0x42800700UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX1 (*((volatile unsigned int*)(0x42800704UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX2 (*((volatile unsigned int*)(0x42800708UL))) +#define bM4_ADC1_CHMUXR0_CH00MUX3 (*((volatile unsigned int*)(0x4280070CUL))) +#define bM4_ADC1_CHMUXR0_CH01MUX0 (*((volatile unsigned int*)(0x42800710UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX1 (*((volatile unsigned int*)(0x42800714UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX2 (*((volatile unsigned int*)(0x42800718UL))) +#define bM4_ADC1_CHMUXR0_CH01MUX3 (*((volatile unsigned int*)(0x4280071CUL))) +#define bM4_ADC1_CHMUXR0_CH02MUX0 (*((volatile unsigned int*)(0x42800720UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX1 (*((volatile unsigned int*)(0x42800724UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX2 (*((volatile unsigned int*)(0x42800728UL))) +#define bM4_ADC1_CHMUXR0_CH02MUX3 (*((volatile unsigned int*)(0x4280072CUL))) +#define bM4_ADC1_CHMUXR0_CH03MUX0 (*((volatile unsigned int*)(0x42800730UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX1 (*((volatile unsigned int*)(0x42800734UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX2 (*((volatile unsigned int*)(0x42800738UL))) +#define bM4_ADC1_CHMUXR0_CH03MUX3 (*((volatile unsigned int*)(0x4280073CUL))) +#define bM4_ADC1_CHMUXR1_CH04MUX0 (*((volatile unsigned int*)(0x42800740UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX1 (*((volatile unsigned int*)(0x42800744UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX2 (*((volatile unsigned int*)(0x42800748UL))) +#define bM4_ADC1_CHMUXR1_CH04MUX3 (*((volatile unsigned int*)(0x4280074CUL))) +#define bM4_ADC1_CHMUXR1_CH05MUX0 (*((volatile unsigned int*)(0x42800750UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX1 (*((volatile unsigned int*)(0x42800754UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX2 (*((volatile unsigned int*)(0x42800758UL))) +#define bM4_ADC1_CHMUXR1_CH05MUX3 (*((volatile unsigned int*)(0x4280075CUL))) +#define bM4_ADC1_CHMUXR1_CH06MUX0 (*((volatile unsigned int*)(0x42800760UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX1 (*((volatile unsigned int*)(0x42800764UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX2 (*((volatile unsigned int*)(0x42800768UL))) +#define bM4_ADC1_CHMUXR1_CH06MUX3 (*((volatile unsigned int*)(0x4280076CUL))) +#define bM4_ADC1_CHMUXR1_CH07MUX0 (*((volatile unsigned int*)(0x42800770UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX1 (*((volatile unsigned int*)(0x42800774UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX2 (*((volatile unsigned int*)(0x42800778UL))) +#define bM4_ADC1_CHMUXR1_CH07MUX3 (*((volatile unsigned int*)(0x4280077CUL))) +#define bM4_ADC1_CHMUXR2_CH08MUX0 (*((volatile unsigned int*)(0x42800780UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX1 (*((volatile unsigned int*)(0x42800784UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX2 (*((volatile unsigned int*)(0x42800788UL))) +#define bM4_ADC1_CHMUXR2_CH08MUX3 (*((volatile unsigned int*)(0x4280078CUL))) +#define bM4_ADC1_CHMUXR2_CH09MUX0 (*((volatile unsigned int*)(0x42800790UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX1 (*((volatile unsigned int*)(0x42800794UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX2 (*((volatile unsigned int*)(0x42800798UL))) +#define bM4_ADC1_CHMUXR2_CH09MUX3 (*((volatile unsigned int*)(0x4280079CUL))) +#define bM4_ADC1_CHMUXR2_CH10MUX0 (*((volatile unsigned int*)(0x428007A0UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX1 (*((volatile unsigned int*)(0x428007A4UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX2 (*((volatile unsigned int*)(0x428007A8UL))) +#define bM4_ADC1_CHMUXR2_CH10MUX3 (*((volatile unsigned int*)(0x428007ACUL))) +#define bM4_ADC1_CHMUXR2_CH11MUX0 (*((volatile unsigned int*)(0x428007B0UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX1 (*((volatile unsigned int*)(0x428007B4UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX2 (*((volatile unsigned int*)(0x428007B8UL))) +#define bM4_ADC1_CHMUXR2_CH11MUX3 (*((volatile unsigned int*)(0x428007BCUL))) +#define bM4_ADC1_CHMUXR3_CH12MUX0 (*((volatile unsigned int*)(0x428007C0UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX1 (*((volatile unsigned int*)(0x428007C4UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX2 (*((volatile unsigned int*)(0x428007C8UL))) +#define bM4_ADC1_CHMUXR3_CH12MUX3 (*((volatile unsigned int*)(0x428007CCUL))) +#define bM4_ADC1_CHMUXR3_CH13MUX0 (*((volatile unsigned int*)(0x428007D0UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX1 (*((volatile unsigned int*)(0x428007D4UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX2 (*((volatile unsigned int*)(0x428007D8UL))) +#define bM4_ADC1_CHMUXR3_CH13MUX3 (*((volatile unsigned int*)(0x428007DCUL))) +#define bM4_ADC1_CHMUXR3_CH14MUX0 (*((volatile unsigned int*)(0x428007E0UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX1 (*((volatile unsigned int*)(0x428007E4UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX2 (*((volatile unsigned int*)(0x428007E8UL))) +#define bM4_ADC1_CHMUXR3_CH14MUX3 (*((volatile unsigned int*)(0x428007ECUL))) +#define bM4_ADC1_CHMUXR3_CH15MUX0 (*((volatile unsigned int*)(0x428007F0UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX1 (*((volatile unsigned int*)(0x428007F4UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX2 (*((volatile unsigned int*)(0x428007F8UL))) +#define bM4_ADC1_CHMUXR3_CH15MUX3 (*((volatile unsigned int*)(0x428007FCUL))) +#define bM4_ADC1_ISR_EOCAF (*((volatile unsigned int*)(0x428008C0UL))) +#define bM4_ADC1_ISR_EOCBF (*((volatile unsigned int*)(0x428008C4UL))) +#define bM4_ADC1_ICR_EOCAIEN (*((volatile unsigned int*)(0x428008E0UL))) +#define bM4_ADC1_ICR_EOCBIEN (*((volatile unsigned int*)(0x428008E4UL))) +#define bM4_ADC1_SYNCCR_SYNCEN (*((volatile unsigned int*)(0x42800980UL))) +#define bM4_ADC1_SYNCCR_SYNCMD0 (*((volatile unsigned int*)(0x42800990UL))) +#define bM4_ADC1_SYNCCR_SYNCMD1 (*((volatile unsigned int*)(0x42800994UL))) +#define bM4_ADC1_SYNCCR_SYNCMD2 (*((volatile unsigned int*)(0x42800998UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY0 (*((volatile unsigned int*)(0x428009A0UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY1 (*((volatile unsigned int*)(0x428009A4UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY2 (*((volatile unsigned int*)(0x428009A8UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY3 (*((volatile unsigned int*)(0x428009ACUL))) +#define bM4_ADC1_SYNCCR_SYNCDLY4 (*((volatile unsigned int*)(0x428009B0UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY5 (*((volatile unsigned int*)(0x428009B4UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY6 (*((volatile unsigned int*)(0x428009B8UL))) +#define bM4_ADC1_SYNCCR_SYNCDLY7 (*((volatile unsigned int*)(0x428009BCUL))) +#define bM4_ADC1_AWDCR_AWDEN (*((volatile unsigned int*)(0x42801400UL))) +#define bM4_ADC1_AWDCR_AWDMD (*((volatile unsigned int*)(0x42801410UL))) +#define bM4_ADC1_AWDCR_AWDSS0 (*((volatile unsigned int*)(0x42801418UL))) +#define bM4_ADC1_AWDCR_AWDSS1 (*((volatile unsigned int*)(0x4280141CUL))) +#define bM4_ADC1_AWDCR_AWDIEN (*((volatile unsigned int*)(0x42801420UL))) +#define bM4_ADC1_AWDCHSR1_AWDCH16 (*((volatile unsigned int*)(0x428015C0UL))) +#define bM4_ADC1_AWDSR1_AWDF16 (*((volatile unsigned int*)(0x42801640UL))) +#define bM4_ADC1_PGACR_PGACTL0 (*((volatile unsigned int*)(0x42801800UL))) +#define bM4_ADC1_PGACR_PGACTL1 (*((volatile unsigned int*)(0x42801804UL))) +#define bM4_ADC1_PGACR_PGACTL2 (*((volatile unsigned int*)(0x42801808UL))) +#define bM4_ADC1_PGACR_PGACTL3 (*((volatile unsigned int*)(0x4280180CUL))) +#define bM4_ADC1_PGAGSR_GAIN0 (*((volatile unsigned int*)(0x42801840UL))) +#define bM4_ADC1_PGAGSR_GAIN1 (*((volatile unsigned int*)(0x42801844UL))) +#define bM4_ADC1_PGAGSR_GAIN2 (*((volatile unsigned int*)(0x42801848UL))) +#define bM4_ADC1_PGAGSR_GAIN3 (*((volatile unsigned int*)(0x4280184CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL0 (*((volatile unsigned int*)(0x42801980UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL1 (*((volatile unsigned int*)(0x42801984UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL2 (*((volatile unsigned int*)(0x42801988UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL3 (*((volatile unsigned int*)(0x4280198CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL4 (*((volatile unsigned int*)(0x42801990UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL5 (*((volatile unsigned int*)(0x42801994UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL6 (*((volatile unsigned int*)(0x42801998UL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL7 (*((volatile unsigned int*)(0x4280199CUL))) +#define bM4_ADC1_PGAINSR0_PGAINSEL8 (*((volatile unsigned int*)(0x428019A0UL))) +#define bM4_ADC1_PGAINSR1_PGAVSSEN (*((volatile unsigned int*)(0x428019C0UL))) +#define bM4_ADC2_STR_STRT (*((volatile unsigned int*)(0x42808000UL))) +#define bM4_ADC2_CR0_MS0 (*((volatile unsigned int*)(0x42808040UL))) +#define bM4_ADC2_CR0_MS1 (*((volatile unsigned int*)(0x42808044UL))) +#define bM4_ADC2_CR0_ACCSEL0 (*((volatile unsigned int*)(0x42808050UL))) +#define bM4_ADC2_CR0_ACCSEL1 (*((volatile unsigned int*)(0x42808054UL))) +#define bM4_ADC2_CR0_CLREN (*((volatile unsigned int*)(0x42808058UL))) +#define bM4_ADC2_CR0_DFMT (*((volatile unsigned int*)(0x4280805CUL))) +#define bM4_ADC2_CR0_AVCNT0 (*((volatile unsigned int*)(0x42808060UL))) +#define bM4_ADC2_CR0_AVCNT1 (*((volatile unsigned int*)(0x42808064UL))) +#define bM4_ADC2_CR0_AVCNT2 (*((volatile unsigned int*)(0x42808068UL))) +#define bM4_ADC2_CR1_RSCHSEL (*((volatile unsigned int*)(0x42808088UL))) +#define bM4_ADC2_TRGSR_TRGSELA0 (*((volatile unsigned int*)(0x42808140UL))) +#define bM4_ADC2_TRGSR_TRGSELA1 (*((volatile unsigned int*)(0x42808144UL))) +#define bM4_ADC2_TRGSR_TRGSELA2 (*((volatile unsigned int*)(0x42808148UL))) +#define bM4_ADC2_TRGSR_TRGENA (*((volatile unsigned int*)(0x4280815CUL))) +#define bM4_ADC2_TRGSR_TRGSELB0 (*((volatile unsigned int*)(0x42808160UL))) +#define bM4_ADC2_TRGSR_TRGSELB1 (*((volatile unsigned int*)(0x42808164UL))) +#define bM4_ADC2_TRGSR_TRGSELB2 (*((volatile unsigned int*)(0x42808168UL))) +#define bM4_ADC2_TRGSR_TRGENB (*((volatile unsigned int*)(0x4280817CUL))) +#define bM4_ADC2_CHSELRA1_CHSELA16 (*((volatile unsigned int*)(0x428081C0UL))) +#define bM4_ADC2_CHSELRB1_CHSELB16 (*((volatile unsigned int*)(0x42808240UL))) +#define bM4_ADC2_AVCHSELR1_AVCHSEL16 (*((volatile unsigned int*)(0x428082C0UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX0 (*((volatile unsigned int*)(0x42808700UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX1 (*((volatile unsigned int*)(0x42808704UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX2 (*((volatile unsigned int*)(0x42808708UL))) +#define bM4_ADC2_CHMUXR0_CH00MUX3 (*((volatile unsigned int*)(0x4280870CUL))) +#define bM4_ADC2_CHMUXR0_CH01MUX0 (*((volatile unsigned int*)(0x42808710UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX1 (*((volatile unsigned int*)(0x42808714UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX2 (*((volatile unsigned int*)(0x42808718UL))) +#define bM4_ADC2_CHMUXR0_CH01MUX3 (*((volatile unsigned int*)(0x4280871CUL))) +#define bM4_ADC2_CHMUXR0_CH02MUX0 (*((volatile unsigned int*)(0x42808720UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX1 (*((volatile unsigned int*)(0x42808724UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX2 (*((volatile unsigned int*)(0x42808728UL))) +#define bM4_ADC2_CHMUXR0_CH02MUX3 (*((volatile unsigned int*)(0x4280872CUL))) +#define bM4_ADC2_CHMUXR0_CH03MUX0 (*((volatile unsigned int*)(0x42808730UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX1 (*((volatile unsigned int*)(0x42808734UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX2 (*((volatile unsigned int*)(0x42808738UL))) +#define bM4_ADC2_CHMUXR0_CH03MUX3 (*((volatile unsigned int*)(0x4280873CUL))) +#define bM4_ADC2_CHMUXR1_CH04MUX0 (*((volatile unsigned int*)(0x42808740UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX1 (*((volatile unsigned int*)(0x42808744UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX2 (*((volatile unsigned int*)(0x42808748UL))) +#define bM4_ADC2_CHMUXR1_CH04MUX3 (*((volatile unsigned int*)(0x4280874CUL))) +#define bM4_ADC2_CHMUXR1_CH05MUX0 (*((volatile unsigned int*)(0x42808750UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX1 (*((volatile unsigned int*)(0x42808754UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX2 (*((volatile unsigned int*)(0x42808758UL))) +#define bM4_ADC2_CHMUXR1_CH05MUX3 (*((volatile unsigned int*)(0x4280875CUL))) +#define bM4_ADC2_CHMUXR1_CH06MUX0 (*((volatile unsigned int*)(0x42808760UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX1 (*((volatile unsigned int*)(0x42808764UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX2 (*((volatile unsigned int*)(0x42808768UL))) +#define bM4_ADC2_CHMUXR1_CH06MUX3 (*((volatile unsigned int*)(0x4280876CUL))) +#define bM4_ADC2_CHMUXR1_CH07MUX0 (*((volatile unsigned int*)(0x42808770UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX1 (*((volatile unsigned int*)(0x42808774UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX2 (*((volatile unsigned int*)(0x42808778UL))) +#define bM4_ADC2_CHMUXR1_CH07MUX3 (*((volatile unsigned int*)(0x4280877CUL))) +#define bM4_ADC2_CHMUXR2_CH08MUX0 (*((volatile unsigned int*)(0x42808780UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX1 (*((volatile unsigned int*)(0x42808784UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX2 (*((volatile unsigned int*)(0x42808788UL))) +#define bM4_ADC2_CHMUXR2_CH08MUX3 (*((volatile unsigned int*)(0x4280878CUL))) +#define bM4_ADC2_CHMUXR2_CH09MUX0 (*((volatile unsigned int*)(0x42808790UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX1 (*((volatile unsigned int*)(0x42808794UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX2 (*((volatile unsigned int*)(0x42808798UL))) +#define bM4_ADC2_CHMUXR2_CH09MUX3 (*((volatile unsigned int*)(0x4280879CUL))) +#define bM4_ADC2_CHMUXR2_CH10MUX0 (*((volatile unsigned int*)(0x428087A0UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX1 (*((volatile unsigned int*)(0x428087A4UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX2 (*((volatile unsigned int*)(0x428087A8UL))) +#define bM4_ADC2_CHMUXR2_CH10MUX3 (*((volatile unsigned int*)(0x428087ACUL))) +#define bM4_ADC2_CHMUXR2_CH11MUX0 (*((volatile unsigned int*)(0x428087B0UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX1 (*((volatile unsigned int*)(0x428087B4UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX2 (*((volatile unsigned int*)(0x428087B8UL))) +#define bM4_ADC2_CHMUXR2_CH11MUX3 (*((volatile unsigned int*)(0x428087BCUL))) +#define bM4_ADC2_CHMUXR3_CH12MUX0 (*((volatile unsigned int*)(0x428087C0UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX1 (*((volatile unsigned int*)(0x428087C4UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX2 (*((volatile unsigned int*)(0x428087C8UL))) +#define bM4_ADC2_CHMUXR3_CH12MUX3 (*((volatile unsigned int*)(0x428087CCUL))) +#define bM4_ADC2_CHMUXR3_CH13MUX0 (*((volatile unsigned int*)(0x428087D0UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX1 (*((volatile unsigned int*)(0x428087D4UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX2 (*((volatile unsigned int*)(0x428087D8UL))) +#define bM4_ADC2_CHMUXR3_CH13MUX3 (*((volatile unsigned int*)(0x428087DCUL))) +#define bM4_ADC2_CHMUXR3_CH14MUX0 (*((volatile unsigned int*)(0x428087E0UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX1 (*((volatile unsigned int*)(0x428087E4UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX2 (*((volatile unsigned int*)(0x428087E8UL))) +#define bM4_ADC2_CHMUXR3_CH14MUX3 (*((volatile unsigned int*)(0x428087ECUL))) +#define bM4_ADC2_CHMUXR3_CH15MUX0 (*((volatile unsigned int*)(0x428087F0UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX1 (*((volatile unsigned int*)(0x428087F4UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX2 (*((volatile unsigned int*)(0x428087F8UL))) +#define bM4_ADC2_CHMUXR3_CH15MUX3 (*((volatile unsigned int*)(0x428087FCUL))) +#define bM4_ADC2_ISR_EOCAF (*((volatile unsigned int*)(0x428088C0UL))) +#define bM4_ADC2_ISR_EOCBF (*((volatile unsigned int*)(0x428088C4UL))) +#define bM4_ADC2_ICR_EOCAIEN (*((volatile unsigned int*)(0x428088E0UL))) +#define bM4_ADC2_ICR_EOCBIEN (*((volatile unsigned int*)(0x428088E4UL))) +#define bM4_ADC2_SYNCCR_SYNCEN (*((volatile unsigned int*)(0x42808980UL))) +#define bM4_ADC2_SYNCCR_SYNCMD0 (*((volatile unsigned int*)(0x42808990UL))) +#define bM4_ADC2_SYNCCR_SYNCMD1 (*((volatile unsigned int*)(0x42808994UL))) +#define bM4_ADC2_SYNCCR_SYNCMD2 (*((volatile unsigned int*)(0x42808998UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY0 (*((volatile unsigned int*)(0x428089A0UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY1 (*((volatile unsigned int*)(0x428089A4UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY2 (*((volatile unsigned int*)(0x428089A8UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY3 (*((volatile unsigned int*)(0x428089ACUL))) +#define bM4_ADC2_SYNCCR_SYNCDLY4 (*((volatile unsigned int*)(0x428089B0UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY5 (*((volatile unsigned int*)(0x428089B4UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY6 (*((volatile unsigned int*)(0x428089B8UL))) +#define bM4_ADC2_SYNCCR_SYNCDLY7 (*((volatile unsigned int*)(0x428089BCUL))) +#define bM4_ADC2_AWDCR_AWDEN (*((volatile unsigned int*)(0x42809400UL))) +#define bM4_ADC2_AWDCR_AWDMD (*((volatile unsigned int*)(0x42809410UL))) +#define bM4_ADC2_AWDCR_AWDSS0 (*((volatile unsigned int*)(0x42809418UL))) +#define bM4_ADC2_AWDCR_AWDSS1 (*((volatile unsigned int*)(0x4280941CUL))) +#define bM4_ADC2_AWDCR_AWDIEN (*((volatile unsigned int*)(0x42809420UL))) +#define bM4_ADC2_AWDCHSR1_AWDCH16 (*((volatile unsigned int*)(0x428095C0UL))) +#define bM4_ADC2_AWDSR1_AWDF16 (*((volatile unsigned int*)(0x42809640UL))) +#define bM4_ADC2_PGACR_PGACTL0 (*((volatile unsigned int*)(0x42809800UL))) +#define bM4_ADC2_PGACR_PGACTL1 (*((volatile unsigned int*)(0x42809804UL))) +#define bM4_ADC2_PGACR_PGACTL2 (*((volatile unsigned int*)(0x42809808UL))) +#define bM4_ADC2_PGACR_PGACTL3 (*((volatile unsigned int*)(0x4280980CUL))) +#define bM4_ADC2_PGAGSR_GAIN0 (*((volatile unsigned int*)(0x42809840UL))) +#define bM4_ADC2_PGAGSR_GAIN1 (*((volatile unsigned int*)(0x42809844UL))) +#define bM4_ADC2_PGAGSR_GAIN2 (*((volatile unsigned int*)(0x42809848UL))) +#define bM4_ADC2_PGAGSR_GAIN3 (*((volatile unsigned int*)(0x4280984CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL0 (*((volatile unsigned int*)(0x42809980UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL1 (*((volatile unsigned int*)(0x42809984UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL2 (*((volatile unsigned int*)(0x42809988UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL3 (*((volatile unsigned int*)(0x4280998CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL4 (*((volatile unsigned int*)(0x42809990UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL5 (*((volatile unsigned int*)(0x42809994UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL6 (*((volatile unsigned int*)(0x42809998UL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL7 (*((volatile unsigned int*)(0x4280999CUL))) +#define bM4_ADC2_PGAINSR0_PGAINSEL8 (*((volatile unsigned int*)(0x428099A0UL))) +#define bM4_ADC2_PGAINSR1_PGAVSSEN (*((volatile unsigned int*)(0x428099C0UL))) +#define bM4_AES_CR_START (*((volatile unsigned int*)(0x42100000UL))) +#define bM4_AES_CR_MODE (*((volatile unsigned int*)(0x42100004UL))) +#define bM4_AOS_INT_SFTTRG_STRG (*((volatile unsigned int*)(0x42210000UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210080UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210084UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210088UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221008CUL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210090UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210094UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210098UL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221009CUL))) +#define bM4_AOS_DCU1_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x422100A0UL))) +#define bM4_AOS_DCU1_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x422100F8UL))) +#define bM4_AOS_DCU1_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x422100FCUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210100UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210104UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210108UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221010CUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210110UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210114UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210118UL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221011CUL))) +#define bM4_AOS_DCU2_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x42210120UL))) +#define bM4_AOS_DCU2_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x42210178UL))) +#define bM4_AOS_DCU2_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x4221017CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210180UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210184UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210188UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221018CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210190UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210194UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210198UL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221019CUL))) +#define bM4_AOS_DCU3_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x422101A0UL))) +#define bM4_AOS_DCU3_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x422101F8UL))) +#define bM4_AOS_DCU3_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x422101FCUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL0 (*((volatile unsigned int*)(0x42210200UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL1 (*((volatile unsigned int*)(0x42210204UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL2 (*((volatile unsigned int*)(0x42210208UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL3 (*((volatile unsigned int*)(0x4221020CUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL4 (*((volatile unsigned int*)(0x42210210UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL5 (*((volatile unsigned int*)(0x42210214UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL6 (*((volatile unsigned int*)(0x42210218UL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL7 (*((volatile unsigned int*)(0x4221021CUL))) +#define bM4_AOS_DCU4_TRGSEL_TRGSEL8 (*((volatile unsigned int*)(0x42210220UL))) +#define bM4_AOS_DCU4_TRGSEL_COMTRG_EN0 (*((volatile unsigned int*)(0x42210278UL))) +#define bM4_AOS_DCU4_TRGSEL_COMTRG_EN1 (*((volatile unsigned int*)(0x4221027CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL0 (*((volatile unsigned int*)(0x42210280UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL1 (*((volatile unsigned int*)(0x42210284UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL2 (*((volatile unsigned int*)(0x42210288UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL3 (*((volatile unsigned int*)(0x4221028CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL4 (*((volatile unsigned int*)(0x42210290UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL5 (*((volatile unsigned int*)(0x42210294UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL6 (*((volatile unsigned int*)(0x42210298UL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL7 (*((volatile unsigned int*)(0x4221029CUL))) +#define bM4_AOS_DMA1_TRGSEL0_TRGSEL8 (*((volatile unsigned int*)(0x422102A0UL))) +#define bM4_AOS_DMA1_TRGSEL0_COMTRG_EN0 (*((volatile unsigned int*)(0x422102F8UL))) +#define bM4_AOS_DMA1_TRGSEL0_COMTRG_EN1 (*((volatile unsigned int*)(0x422102FCUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL0 (*((volatile unsigned int*)(0x42210300UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL1 (*((volatile unsigned int*)(0x42210304UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL2 (*((volatile unsigned int*)(0x42210308UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL3 (*((volatile unsigned int*)(0x4221030CUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL4 (*((volatile unsigned int*)(0x42210310UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL5 (*((volatile unsigned int*)(0x42210314UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL6 (*((volatile unsigned int*)(0x42210318UL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL7 (*((volatile unsigned int*)(0x4221031CUL))) +#define bM4_AOS_DMA1_TRGSEL1_TRGSEL8 (*((volatile unsigned int*)(0x42210320UL))) +#define bM4_AOS_DMA1_TRGSEL1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210378UL))) +#define bM4_AOS_DMA1_TRGSEL1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221037CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL0 (*((volatile unsigned int*)(0x42210380UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL1 (*((volatile unsigned int*)(0x42210384UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL2 (*((volatile unsigned int*)(0x42210388UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL3 (*((volatile unsigned int*)(0x4221038CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL4 (*((volatile unsigned int*)(0x42210390UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL5 (*((volatile unsigned int*)(0x42210394UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL6 (*((volatile unsigned int*)(0x42210398UL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL7 (*((volatile unsigned int*)(0x4221039CUL))) +#define bM4_AOS_DMA1_TRGSEL2_TRGSEL8 (*((volatile unsigned int*)(0x422103A0UL))) +#define bM4_AOS_DMA1_TRGSEL2_COMTRG_EN0 (*((volatile unsigned int*)(0x422103F8UL))) +#define bM4_AOS_DMA1_TRGSEL2_COMTRG_EN1 (*((volatile unsigned int*)(0x422103FCUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL0 (*((volatile unsigned int*)(0x42210400UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL1 (*((volatile unsigned int*)(0x42210404UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL2 (*((volatile unsigned int*)(0x42210408UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL3 (*((volatile unsigned int*)(0x4221040CUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL4 (*((volatile unsigned int*)(0x42210410UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL5 (*((volatile unsigned int*)(0x42210414UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL6 (*((volatile unsigned int*)(0x42210418UL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL7 (*((volatile unsigned int*)(0x4221041CUL))) +#define bM4_AOS_DMA1_TRGSEL3_TRGSEL8 (*((volatile unsigned int*)(0x42210420UL))) +#define bM4_AOS_DMA1_TRGSEL3_COMTRG_EN0 (*((volatile unsigned int*)(0x42210478UL))) +#define bM4_AOS_DMA1_TRGSEL3_COMTRG_EN1 (*((volatile unsigned int*)(0x4221047CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL0 (*((volatile unsigned int*)(0x42210480UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL1 (*((volatile unsigned int*)(0x42210484UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL2 (*((volatile unsigned int*)(0x42210488UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL3 (*((volatile unsigned int*)(0x4221048CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL4 (*((volatile unsigned int*)(0x42210490UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL5 (*((volatile unsigned int*)(0x42210494UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL6 (*((volatile unsigned int*)(0x42210498UL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL7 (*((volatile unsigned int*)(0x4221049CUL))) +#define bM4_AOS_DMA2_TRGSEL0_TRGSEL8 (*((volatile unsigned int*)(0x422104A0UL))) +#define bM4_AOS_DMA2_TRGSEL0_COMTRG_EN0 (*((volatile unsigned int*)(0x422104F8UL))) +#define bM4_AOS_DMA2_TRGSEL0_COMTRG_EN1 (*((volatile unsigned int*)(0x422104FCUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL0 (*((volatile unsigned int*)(0x42210500UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL1 (*((volatile unsigned int*)(0x42210504UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL2 (*((volatile unsigned int*)(0x42210508UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL3 (*((volatile unsigned int*)(0x4221050CUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL4 (*((volatile unsigned int*)(0x42210510UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL5 (*((volatile unsigned int*)(0x42210514UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL6 (*((volatile unsigned int*)(0x42210518UL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL7 (*((volatile unsigned int*)(0x4221051CUL))) +#define bM4_AOS_DMA2_TRGSEL1_TRGSEL8 (*((volatile unsigned int*)(0x42210520UL))) +#define bM4_AOS_DMA2_TRGSEL1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210578UL))) +#define bM4_AOS_DMA2_TRGSEL1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221057CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL0 (*((volatile unsigned int*)(0x42210580UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL1 (*((volatile unsigned int*)(0x42210584UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL2 (*((volatile unsigned int*)(0x42210588UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL3 (*((volatile unsigned int*)(0x4221058CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL4 (*((volatile unsigned int*)(0x42210590UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL5 (*((volatile unsigned int*)(0x42210594UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL6 (*((volatile unsigned int*)(0x42210598UL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL7 (*((volatile unsigned int*)(0x4221059CUL))) +#define bM4_AOS_DMA2_TRGSEL2_TRGSEL8 (*((volatile unsigned int*)(0x422105A0UL))) +#define bM4_AOS_DMA2_TRGSEL2_COMTRG_EN0 (*((volatile unsigned int*)(0x422105F8UL))) +#define bM4_AOS_DMA2_TRGSEL2_COMTRG_EN1 (*((volatile unsigned int*)(0x422105FCUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL0 (*((volatile unsigned int*)(0x42210600UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL1 (*((volatile unsigned int*)(0x42210604UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL2 (*((volatile unsigned int*)(0x42210608UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL3 (*((volatile unsigned int*)(0x4221060CUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL4 (*((volatile unsigned int*)(0x42210610UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL5 (*((volatile unsigned int*)(0x42210614UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL6 (*((volatile unsigned int*)(0x42210618UL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL7 (*((volatile unsigned int*)(0x4221061CUL))) +#define bM4_AOS_DMA2_TRGSEL3_TRGSEL8 (*((volatile unsigned int*)(0x42210620UL))) +#define bM4_AOS_DMA2_TRGSEL3_COMTRG_EN0 (*((volatile unsigned int*)(0x42210678UL))) +#define bM4_AOS_DMA2_TRGSEL3_COMTRG_EN1 (*((volatile unsigned int*)(0x4221067CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL0 (*((volatile unsigned int*)(0x42210680UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL1 (*((volatile unsigned int*)(0x42210684UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL2 (*((volatile unsigned int*)(0x42210688UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL3 (*((volatile unsigned int*)(0x4221068CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL4 (*((volatile unsigned int*)(0x42210690UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL5 (*((volatile unsigned int*)(0x42210694UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL6 (*((volatile unsigned int*)(0x42210698UL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL7 (*((volatile unsigned int*)(0x4221069CUL))) +#define bM4_AOS_DMA_TRGSELRC_TRGSEL8 (*((volatile unsigned int*)(0x422106A0UL))) +#define bM4_AOS_DMA_TRGSELRC_COMTRG_EN0 (*((volatile unsigned int*)(0x422106F8UL))) +#define bM4_AOS_DMA_TRGSELRC_COMTRG_EN1 (*((volatile unsigned int*)(0x422106FCUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL0 (*((volatile unsigned int*)(0x42210700UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL1 (*((volatile unsigned int*)(0x42210704UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL2 (*((volatile unsigned int*)(0x42210708UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL3 (*((volatile unsigned int*)(0x4221070CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL4 (*((volatile unsigned int*)(0x42210710UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL5 (*((volatile unsigned int*)(0x42210714UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL6 (*((volatile unsigned int*)(0x42210718UL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL7 (*((volatile unsigned int*)(0x4221071CUL))) +#define bM4_AOS_TMR6_HTSSR1_TRGSEL8 (*((volatile unsigned int*)(0x42210720UL))) +#define bM4_AOS_TMR6_HTSSR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210778UL))) +#define bM4_AOS_TMR6_HTSSR1_COMTRG_EN1 (*((volatile unsigned int*)(0x4221077CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL0 (*((volatile unsigned int*)(0x42210780UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL1 (*((volatile unsigned int*)(0x42210784UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL2 (*((volatile unsigned int*)(0x42210788UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL3 (*((volatile unsigned int*)(0x4221078CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL4 (*((volatile unsigned int*)(0x42210790UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL5 (*((volatile unsigned int*)(0x42210794UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL6 (*((volatile unsigned int*)(0x42210798UL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL7 (*((volatile unsigned int*)(0x4221079CUL))) +#define bM4_AOS_TMR6_HTSSR2_TRGSEL8 (*((volatile unsigned int*)(0x422107A0UL))) +#define bM4_AOS_TMR6_HTSSR2_COMTRG_EN0 (*((volatile unsigned int*)(0x422107F8UL))) +#define bM4_AOS_TMR6_HTSSR2_COMTRG_EN1 (*((volatile unsigned int*)(0x422107FCUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL0 (*((volatile unsigned int*)(0x42210800UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL1 (*((volatile unsigned int*)(0x42210804UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL2 (*((volatile unsigned int*)(0x42210808UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL3 (*((volatile unsigned int*)(0x4221080CUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL4 (*((volatile unsigned int*)(0x42210810UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL5 (*((volatile unsigned int*)(0x42210814UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL6 (*((volatile unsigned int*)(0x42210818UL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL7 (*((volatile unsigned int*)(0x4221081CUL))) +#define bM4_AOS_TMR0_HTSSR_TRGSEL8 (*((volatile unsigned int*)(0x42210820UL))) +#define bM4_AOS_TMR0_HTSSR_COMTRG_EN0 (*((volatile unsigned int*)(0x42210878UL))) +#define bM4_AOS_TMR0_HTSSR_COMTRG_EN1 (*((volatile unsigned int*)(0x4221087CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL0 (*((volatile unsigned int*)(0x42210880UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL1 (*((volatile unsigned int*)(0x42210884UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL2 (*((volatile unsigned int*)(0x42210888UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL3 (*((volatile unsigned int*)(0x4221088CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL4 (*((volatile unsigned int*)(0x42210890UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL5 (*((volatile unsigned int*)(0x42210894UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL6 (*((volatile unsigned int*)(0x42210898UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL7 (*((volatile unsigned int*)(0x4221089CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_TRGSEL8 (*((volatile unsigned int*)(0x422108A0UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_COMTRG_EN0 (*((volatile unsigned int*)(0x422108F8UL))) +#define bM4_AOS_PORT_PEVNTTRGSR12_COMTRG_EN1 (*((volatile unsigned int*)(0x422108FCUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL0 (*((volatile unsigned int*)(0x42210900UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL1 (*((volatile unsigned int*)(0x42210904UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL2 (*((volatile unsigned int*)(0x42210908UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL3 (*((volatile unsigned int*)(0x4221090CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL4 (*((volatile unsigned int*)(0x42210910UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL5 (*((volatile unsigned int*)(0x42210914UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL6 (*((volatile unsigned int*)(0x42210918UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL7 (*((volatile unsigned int*)(0x4221091CUL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_TRGSEL8 (*((volatile unsigned int*)(0x42210920UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_COMTRG_EN0 (*((volatile unsigned int*)(0x42210978UL))) +#define bM4_AOS_PORT_PEVNTTRGSR34_COMTRG_EN1 (*((volatile unsigned int*)(0x4221097CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL0 (*((volatile unsigned int*)(0x42210980UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL1 (*((volatile unsigned int*)(0x42210984UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL2 (*((volatile unsigned int*)(0x42210988UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL3 (*((volatile unsigned int*)(0x4221098CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL4 (*((volatile unsigned int*)(0x42210990UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL5 (*((volatile unsigned int*)(0x42210994UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL6 (*((volatile unsigned int*)(0x42210998UL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL7 (*((volatile unsigned int*)(0x4221099CUL))) +#define bM4_AOS_TMRA_HTSSR0_TRGSEL8 (*((volatile unsigned int*)(0x422109A0UL))) +#define bM4_AOS_TMRA_HTSSR0_COMTRG_EN0 (*((volatile unsigned int*)(0x422109F8UL))) +#define bM4_AOS_TMRA_HTSSR0_COMTRG_EN1 (*((volatile unsigned int*)(0x422109FCUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL0 (*((volatile unsigned int*)(0x42210A00UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL1 (*((volatile unsigned int*)(0x42210A04UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL2 (*((volatile unsigned int*)(0x42210A08UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL3 (*((volatile unsigned int*)(0x42210A0CUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL4 (*((volatile unsigned int*)(0x42210A10UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL5 (*((volatile unsigned int*)(0x42210A14UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL6 (*((volatile unsigned int*)(0x42210A18UL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL7 (*((volatile unsigned int*)(0x42210A1CUL))) +#define bM4_AOS_TMRA_HTSSR1_TRGSEL8 (*((volatile unsigned int*)(0x42210A20UL))) +#define bM4_AOS_TMRA_HTSSR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210A78UL))) +#define bM4_AOS_TMRA_HTSSR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210A7CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL0 (*((volatile unsigned int*)(0x42210A80UL))) +#define bM4_AOS_OTS_TRG_TRGSEL1 (*((volatile unsigned int*)(0x42210A84UL))) +#define bM4_AOS_OTS_TRG_TRGSEL2 (*((volatile unsigned int*)(0x42210A88UL))) +#define bM4_AOS_OTS_TRG_TRGSEL3 (*((volatile unsigned int*)(0x42210A8CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL4 (*((volatile unsigned int*)(0x42210A90UL))) +#define bM4_AOS_OTS_TRG_TRGSEL5 (*((volatile unsigned int*)(0x42210A94UL))) +#define bM4_AOS_OTS_TRG_TRGSEL6 (*((volatile unsigned int*)(0x42210A98UL))) +#define bM4_AOS_OTS_TRG_TRGSEL7 (*((volatile unsigned int*)(0x42210A9CUL))) +#define bM4_AOS_OTS_TRG_TRGSEL8 (*((volatile unsigned int*)(0x42210AA0UL))) +#define bM4_AOS_OTS_TRG_COMTRG_EN0 (*((volatile unsigned int*)(0x42210AF8UL))) +#define bM4_AOS_OTS_TRG_COMTRG_EN1 (*((volatile unsigned int*)(0x42210AFCUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL0 (*((volatile unsigned int*)(0x42210B00UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL1 (*((volatile unsigned int*)(0x42210B04UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL2 (*((volatile unsigned int*)(0x42210B08UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL3 (*((volatile unsigned int*)(0x42210B0CUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL4 (*((volatile unsigned int*)(0x42210B10UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL5 (*((volatile unsigned int*)(0x42210B14UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL6 (*((volatile unsigned int*)(0x42210B18UL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL7 (*((volatile unsigned int*)(0x42210B1CUL))) +#define bM4_AOS_ADC1_ITRGSELR0_TRGSEL8 (*((volatile unsigned int*)(0x42210B20UL))) +#define bM4_AOS_ADC1_ITRGSELR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210B78UL))) +#define bM4_AOS_ADC1_ITRGSELR0_COMTRG_EN1 (*((volatile unsigned int*)(0x42210B7CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL0 (*((volatile unsigned int*)(0x42210B80UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL1 (*((volatile unsigned int*)(0x42210B84UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL2 (*((volatile unsigned int*)(0x42210B88UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL3 (*((volatile unsigned int*)(0x42210B8CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL4 (*((volatile unsigned int*)(0x42210B90UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL5 (*((volatile unsigned int*)(0x42210B94UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL6 (*((volatile unsigned int*)(0x42210B98UL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL7 (*((volatile unsigned int*)(0x42210B9CUL))) +#define bM4_AOS_ADC1_ITRGSELR1_TRGSEL8 (*((volatile unsigned int*)(0x42210BA0UL))) +#define bM4_AOS_ADC1_ITRGSELR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210BF8UL))) +#define bM4_AOS_ADC1_ITRGSELR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210BFCUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL0 (*((volatile unsigned int*)(0x42210C00UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL1 (*((volatile unsigned int*)(0x42210C04UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL2 (*((volatile unsigned int*)(0x42210C08UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL3 (*((volatile unsigned int*)(0x42210C0CUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL4 (*((volatile unsigned int*)(0x42210C10UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL5 (*((volatile unsigned int*)(0x42210C14UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL6 (*((volatile unsigned int*)(0x42210C18UL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL7 (*((volatile unsigned int*)(0x42210C1CUL))) +#define bM4_AOS_ADC2_ITRGSELR0_TRGSEL8 (*((volatile unsigned int*)(0x42210C20UL))) +#define bM4_AOS_ADC2_ITRGSELR0_COMTRG_EN0 (*((volatile unsigned int*)(0x42210C78UL))) +#define bM4_AOS_ADC2_ITRGSELR0_COMTRG_EN1 (*((volatile unsigned int*)(0x42210C7CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL0 (*((volatile unsigned int*)(0x42210C80UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL1 (*((volatile unsigned int*)(0x42210C84UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL2 (*((volatile unsigned int*)(0x42210C88UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL3 (*((volatile unsigned int*)(0x42210C8CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL4 (*((volatile unsigned int*)(0x42210C90UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL5 (*((volatile unsigned int*)(0x42210C94UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL6 (*((volatile unsigned int*)(0x42210C98UL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL7 (*((volatile unsigned int*)(0x42210C9CUL))) +#define bM4_AOS_ADC2_ITRGSELR1_TRGSEL8 (*((volatile unsigned int*)(0x42210CA0UL))) +#define bM4_AOS_ADC2_ITRGSELR1_COMTRG_EN0 (*((volatile unsigned int*)(0x42210CF8UL))) +#define bM4_AOS_ADC2_ITRGSELR1_COMTRG_EN1 (*((volatile unsigned int*)(0x42210CFCUL))) +#define bM4_AOS_COMTRG1_TRGSEL0 (*((volatile unsigned int*)(0x42210D00UL))) +#define bM4_AOS_COMTRG1_TRGSEL1 (*((volatile unsigned int*)(0x42210D04UL))) +#define bM4_AOS_COMTRG1_TRGSEL2 (*((volatile unsigned int*)(0x42210D08UL))) +#define bM4_AOS_COMTRG1_TRGSEL3 (*((volatile unsigned int*)(0x42210D0CUL))) +#define bM4_AOS_COMTRG1_TRGSEL4 (*((volatile unsigned int*)(0x42210D10UL))) +#define bM4_AOS_COMTRG1_TRGSEL5 (*((volatile unsigned int*)(0x42210D14UL))) +#define bM4_AOS_COMTRG1_TRGSEL6 (*((volatile unsigned int*)(0x42210D18UL))) +#define bM4_AOS_COMTRG1_TRGSEL7 (*((volatile unsigned int*)(0x42210D1CUL))) +#define bM4_AOS_COMTRG1_TRGSEL8 (*((volatile unsigned int*)(0x42210D20UL))) +#define bM4_AOS_COMTRG2_TRGSEL0 (*((volatile unsigned int*)(0x42210D80UL))) +#define bM4_AOS_COMTRG2_TRGSEL1 (*((volatile unsigned int*)(0x42210D84UL))) +#define bM4_AOS_COMTRG2_TRGSEL2 (*((volatile unsigned int*)(0x42210D88UL))) +#define bM4_AOS_COMTRG2_TRGSEL3 (*((volatile unsigned int*)(0x42210D8CUL))) +#define bM4_AOS_COMTRG2_TRGSEL4 (*((volatile unsigned int*)(0x42210D90UL))) +#define bM4_AOS_COMTRG2_TRGSEL5 (*((volatile unsigned int*)(0x42210D94UL))) +#define bM4_AOS_COMTRG2_TRGSEL6 (*((volatile unsigned int*)(0x42210D98UL))) +#define bM4_AOS_COMTRG2_TRGSEL7 (*((volatile unsigned int*)(0x42210D9CUL))) +#define bM4_AOS_COMTRG2_TRGSEL8 (*((volatile unsigned int*)(0x42210DA0UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR00 (*((volatile unsigned int*)(0x42212000UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR01 (*((volatile unsigned int*)(0x42212004UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR02 (*((volatile unsigned int*)(0x42212008UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR03 (*((volatile unsigned int*)(0x4221200CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR04 (*((volatile unsigned int*)(0x42212010UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR05 (*((volatile unsigned int*)(0x42212014UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR06 (*((volatile unsigned int*)(0x42212018UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR07 (*((volatile unsigned int*)(0x4221201CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR08 (*((volatile unsigned int*)(0x42212020UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR09 (*((volatile unsigned int*)(0x42212024UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR10 (*((volatile unsigned int*)(0x42212028UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR11 (*((volatile unsigned int*)(0x4221202CUL))) +#define bM4_AOS_PEVNTDIRR1_PDIR12 (*((volatile unsigned int*)(0x42212030UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR13 (*((volatile unsigned int*)(0x42212034UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR14 (*((volatile unsigned int*)(0x42212038UL))) +#define bM4_AOS_PEVNTDIRR1_PDIR15 (*((volatile unsigned int*)(0x4221203CUL))) +#define bM4_AOS_PEVNTIDR1_PIN00 (*((volatile unsigned int*)(0x42212080UL))) +#define bM4_AOS_PEVNTIDR1_PIN01 (*((volatile unsigned int*)(0x42212084UL))) +#define bM4_AOS_PEVNTIDR1_PIN02 (*((volatile unsigned int*)(0x42212088UL))) +#define bM4_AOS_PEVNTIDR1_PIN03 (*((volatile unsigned int*)(0x4221208CUL))) +#define bM4_AOS_PEVNTIDR1_PIN04 (*((volatile unsigned int*)(0x42212090UL))) +#define bM4_AOS_PEVNTIDR1_PIN05 (*((volatile unsigned int*)(0x42212094UL))) +#define bM4_AOS_PEVNTIDR1_PIN06 (*((volatile unsigned int*)(0x42212098UL))) +#define bM4_AOS_PEVNTIDR1_PIN07 (*((volatile unsigned int*)(0x4221209CUL))) +#define bM4_AOS_PEVNTIDR1_PIN08 (*((volatile unsigned int*)(0x422120A0UL))) +#define bM4_AOS_PEVNTIDR1_PIN09 (*((volatile unsigned int*)(0x422120A4UL))) +#define bM4_AOS_PEVNTIDR1_PIN10 (*((volatile unsigned int*)(0x422120A8UL))) +#define bM4_AOS_PEVNTIDR1_PIN11 (*((volatile unsigned int*)(0x422120ACUL))) +#define bM4_AOS_PEVNTIDR1_PIN12 (*((volatile unsigned int*)(0x422120B0UL))) +#define bM4_AOS_PEVNTIDR1_PIN13 (*((volatile unsigned int*)(0x422120B4UL))) +#define bM4_AOS_PEVNTIDR1_PIN14 (*((volatile unsigned int*)(0x422120B8UL))) +#define bM4_AOS_PEVNTIDR1_PIN15 (*((volatile unsigned int*)(0x422120BCUL))) +#define bM4_AOS_PEVNTODR1_POUT00 (*((volatile unsigned int*)(0x42212100UL))) +#define bM4_AOS_PEVNTODR1_POUT01 (*((volatile unsigned int*)(0x42212104UL))) +#define bM4_AOS_PEVNTODR1_POUT02 (*((volatile unsigned int*)(0x42212108UL))) +#define bM4_AOS_PEVNTODR1_POUT03 (*((volatile unsigned int*)(0x4221210CUL))) +#define bM4_AOS_PEVNTODR1_POUT04 (*((volatile unsigned int*)(0x42212110UL))) +#define bM4_AOS_PEVNTODR1_POUT05 (*((volatile unsigned int*)(0x42212114UL))) +#define bM4_AOS_PEVNTODR1_POUT06 (*((volatile unsigned int*)(0x42212118UL))) +#define bM4_AOS_PEVNTODR1_POUT07 (*((volatile unsigned int*)(0x4221211CUL))) +#define bM4_AOS_PEVNTODR1_POUT08 (*((volatile unsigned int*)(0x42212120UL))) +#define bM4_AOS_PEVNTODR1_POUT09 (*((volatile unsigned int*)(0x42212124UL))) +#define bM4_AOS_PEVNTODR1_POUT10 (*((volatile unsigned int*)(0x42212128UL))) +#define bM4_AOS_PEVNTODR1_POUT11 (*((volatile unsigned int*)(0x4221212CUL))) +#define bM4_AOS_PEVNTODR1_POUT12 (*((volatile unsigned int*)(0x42212130UL))) +#define bM4_AOS_PEVNTODR1_POUT13 (*((volatile unsigned int*)(0x42212134UL))) +#define bM4_AOS_PEVNTODR1_POUT14 (*((volatile unsigned int*)(0x42212138UL))) +#define bM4_AOS_PEVNTODR1_POUT15 (*((volatile unsigned int*)(0x4221213CUL))) +#define bM4_AOS_PEVNTORR1_POR00 (*((volatile unsigned int*)(0x42212180UL))) +#define bM4_AOS_PEVNTORR1_POR01 (*((volatile unsigned int*)(0x42212184UL))) +#define bM4_AOS_PEVNTORR1_POR02 (*((volatile unsigned int*)(0x42212188UL))) +#define bM4_AOS_PEVNTORR1_POR03 (*((volatile unsigned int*)(0x4221218CUL))) +#define bM4_AOS_PEVNTORR1_POR04 (*((volatile unsigned int*)(0x42212190UL))) +#define bM4_AOS_PEVNTORR1_POR05 (*((volatile unsigned int*)(0x42212194UL))) +#define bM4_AOS_PEVNTORR1_POR06 (*((volatile unsigned int*)(0x42212198UL))) +#define bM4_AOS_PEVNTORR1_POR07 (*((volatile unsigned int*)(0x4221219CUL))) +#define bM4_AOS_PEVNTORR1_POR08 (*((volatile unsigned int*)(0x422121A0UL))) +#define bM4_AOS_PEVNTORR1_POR09 (*((volatile unsigned int*)(0x422121A4UL))) +#define bM4_AOS_PEVNTORR1_POR10 (*((volatile unsigned int*)(0x422121A8UL))) +#define bM4_AOS_PEVNTORR1_POR11 (*((volatile unsigned int*)(0x422121ACUL))) +#define bM4_AOS_PEVNTORR1_POR12 (*((volatile unsigned int*)(0x422121B0UL))) +#define bM4_AOS_PEVNTORR1_POR13 (*((volatile unsigned int*)(0x422121B4UL))) +#define bM4_AOS_PEVNTORR1_POR14 (*((volatile unsigned int*)(0x422121B8UL))) +#define bM4_AOS_PEVNTORR1_POR15 (*((volatile unsigned int*)(0x422121BCUL))) +#define bM4_AOS_PEVNTOSR1_POS00 (*((volatile unsigned int*)(0x42212200UL))) +#define bM4_AOS_PEVNTOSR1_POS01 (*((volatile unsigned int*)(0x42212204UL))) +#define bM4_AOS_PEVNTOSR1_POS02 (*((volatile unsigned int*)(0x42212208UL))) +#define bM4_AOS_PEVNTOSR1_POS03 (*((volatile unsigned int*)(0x4221220CUL))) +#define bM4_AOS_PEVNTOSR1_POS04 (*((volatile unsigned int*)(0x42212210UL))) +#define bM4_AOS_PEVNTOSR1_POS05 (*((volatile unsigned int*)(0x42212214UL))) +#define bM4_AOS_PEVNTOSR1_POS06 (*((volatile unsigned int*)(0x42212218UL))) +#define bM4_AOS_PEVNTOSR1_POS07 (*((volatile unsigned int*)(0x4221221CUL))) +#define bM4_AOS_PEVNTOSR1_POS08 (*((volatile unsigned int*)(0x42212220UL))) +#define bM4_AOS_PEVNTOSR1_POS09 (*((volatile unsigned int*)(0x42212224UL))) +#define bM4_AOS_PEVNTOSR1_POS10 (*((volatile unsigned int*)(0x42212228UL))) +#define bM4_AOS_PEVNTOSR1_POS11 (*((volatile unsigned int*)(0x4221222CUL))) +#define bM4_AOS_PEVNTOSR1_POS12 (*((volatile unsigned int*)(0x42212230UL))) +#define bM4_AOS_PEVNTOSR1_POS13 (*((volatile unsigned int*)(0x42212234UL))) +#define bM4_AOS_PEVNTOSR1_POS14 (*((volatile unsigned int*)(0x42212238UL))) +#define bM4_AOS_PEVNTOSR1_POS15 (*((volatile unsigned int*)(0x4221223CUL))) +#define bM4_AOS_PEVNTRISR1_RIS00 (*((volatile unsigned int*)(0x42212280UL))) +#define bM4_AOS_PEVNTRISR1_RIS01 (*((volatile unsigned int*)(0x42212284UL))) +#define bM4_AOS_PEVNTRISR1_RIS02 (*((volatile unsigned int*)(0x42212288UL))) +#define bM4_AOS_PEVNTRISR1_RIS03 (*((volatile unsigned int*)(0x4221228CUL))) +#define bM4_AOS_PEVNTRISR1_RIS04 (*((volatile unsigned int*)(0x42212290UL))) +#define bM4_AOS_PEVNTRISR1_RIS05 (*((volatile unsigned int*)(0x42212294UL))) +#define bM4_AOS_PEVNTRISR1_RIS06 (*((volatile unsigned int*)(0x42212298UL))) +#define bM4_AOS_PEVNTRISR1_RIS07 (*((volatile unsigned int*)(0x4221229CUL))) +#define bM4_AOS_PEVNTRISR1_RIS08 (*((volatile unsigned int*)(0x422122A0UL))) +#define bM4_AOS_PEVNTRISR1_RIS09 (*((volatile unsigned int*)(0x422122A4UL))) +#define bM4_AOS_PEVNTRISR1_RIS10 (*((volatile unsigned int*)(0x422122A8UL))) +#define bM4_AOS_PEVNTRISR1_RIS11 (*((volatile unsigned int*)(0x422122ACUL))) +#define bM4_AOS_PEVNTRISR1_RIS12 (*((volatile unsigned int*)(0x422122B0UL))) +#define bM4_AOS_PEVNTRISR1_RIS13 (*((volatile unsigned int*)(0x422122B4UL))) +#define bM4_AOS_PEVNTRISR1_RIS14 (*((volatile unsigned int*)(0x422122B8UL))) +#define bM4_AOS_PEVNTRISR1_RIS15 (*((volatile unsigned int*)(0x422122BCUL))) +#define bM4_AOS_PEVNTFAL1_FAL00 (*((volatile unsigned int*)(0x42212300UL))) +#define bM4_AOS_PEVNTFAL1_FAL01 (*((volatile unsigned int*)(0x42212304UL))) +#define bM4_AOS_PEVNTFAL1_FAL02 (*((volatile unsigned int*)(0x42212308UL))) +#define bM4_AOS_PEVNTFAL1_FAL03 (*((volatile unsigned int*)(0x4221230CUL))) +#define bM4_AOS_PEVNTFAL1_FAL04 (*((volatile unsigned int*)(0x42212310UL))) +#define bM4_AOS_PEVNTFAL1_FAL05 (*((volatile unsigned int*)(0x42212314UL))) +#define bM4_AOS_PEVNTFAL1_FAL06 (*((volatile unsigned int*)(0x42212318UL))) +#define bM4_AOS_PEVNTFAL1_FAL07 (*((volatile unsigned int*)(0x4221231CUL))) +#define bM4_AOS_PEVNTFAL1_FAL08 (*((volatile unsigned int*)(0x42212320UL))) +#define bM4_AOS_PEVNTFAL1_FAL09 (*((volatile unsigned int*)(0x42212324UL))) +#define bM4_AOS_PEVNTFAL1_FAL10 (*((volatile unsigned int*)(0x42212328UL))) +#define bM4_AOS_PEVNTFAL1_FAL11 (*((volatile unsigned int*)(0x4221232CUL))) +#define bM4_AOS_PEVNTFAL1_FAL12 (*((volatile unsigned int*)(0x42212330UL))) +#define bM4_AOS_PEVNTFAL1_FAL13 (*((volatile unsigned int*)(0x42212334UL))) +#define bM4_AOS_PEVNTFAL1_FAL14 (*((volatile unsigned int*)(0x42212338UL))) +#define bM4_AOS_PEVNTFAL1_FAL15 (*((volatile unsigned int*)(0x4221233CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR00 (*((volatile unsigned int*)(0x42212380UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR01 (*((volatile unsigned int*)(0x42212384UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR02 (*((volatile unsigned int*)(0x42212388UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR03 (*((volatile unsigned int*)(0x4221238CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR04 (*((volatile unsigned int*)(0x42212390UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR05 (*((volatile unsigned int*)(0x42212394UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR06 (*((volatile unsigned int*)(0x42212398UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR07 (*((volatile unsigned int*)(0x4221239CUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR08 (*((volatile unsigned int*)(0x422123A0UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR09 (*((volatile unsigned int*)(0x422123A4UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR10 (*((volatile unsigned int*)(0x422123A8UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR11 (*((volatile unsigned int*)(0x422123ACUL))) +#define bM4_AOS_PEVNTDIRR2_PDIR12 (*((volatile unsigned int*)(0x422123B0UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR13 (*((volatile unsigned int*)(0x422123B4UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR14 (*((volatile unsigned int*)(0x422123B8UL))) +#define bM4_AOS_PEVNTDIRR2_PDIR15 (*((volatile unsigned int*)(0x422123BCUL))) +#define bM4_AOS_PEVNTIDR2_PIN00 (*((volatile unsigned int*)(0x42212400UL))) +#define bM4_AOS_PEVNTIDR2_PIN01 (*((volatile unsigned int*)(0x42212404UL))) +#define bM4_AOS_PEVNTIDR2_PIN02 (*((volatile unsigned int*)(0x42212408UL))) +#define bM4_AOS_PEVNTIDR2_PIN03 (*((volatile unsigned int*)(0x4221240CUL))) +#define bM4_AOS_PEVNTIDR2_PIN04 (*((volatile unsigned int*)(0x42212410UL))) +#define bM4_AOS_PEVNTIDR2_PIN05 (*((volatile unsigned int*)(0x42212414UL))) +#define bM4_AOS_PEVNTIDR2_PIN06 (*((volatile unsigned int*)(0x42212418UL))) +#define bM4_AOS_PEVNTIDR2_PIN07 (*((volatile unsigned int*)(0x4221241CUL))) +#define bM4_AOS_PEVNTIDR2_PIN08 (*((volatile unsigned int*)(0x42212420UL))) +#define bM4_AOS_PEVNTIDR2_PIN09 (*((volatile unsigned int*)(0x42212424UL))) +#define bM4_AOS_PEVNTIDR2_PIN10 (*((volatile unsigned int*)(0x42212428UL))) +#define bM4_AOS_PEVNTIDR2_PIN11 (*((volatile unsigned int*)(0x4221242CUL))) +#define bM4_AOS_PEVNTIDR2_PIN12 (*((volatile unsigned int*)(0x42212430UL))) +#define bM4_AOS_PEVNTIDR2_PIN13 (*((volatile unsigned int*)(0x42212434UL))) +#define bM4_AOS_PEVNTIDR2_PIN14 (*((volatile unsigned int*)(0x42212438UL))) +#define bM4_AOS_PEVNTIDR2_PIN15 (*((volatile unsigned int*)(0x4221243CUL))) +#define bM4_AOS_PEVNTODR2_POUT00 (*((volatile unsigned int*)(0x42212480UL))) +#define bM4_AOS_PEVNTODR2_POUT01 (*((volatile unsigned int*)(0x42212484UL))) +#define bM4_AOS_PEVNTODR2_POUT02 (*((volatile unsigned int*)(0x42212488UL))) +#define bM4_AOS_PEVNTODR2_POUT03 (*((volatile unsigned int*)(0x4221248CUL))) +#define bM4_AOS_PEVNTODR2_POUT04 (*((volatile unsigned int*)(0x42212490UL))) +#define bM4_AOS_PEVNTODR2_POUT05 (*((volatile unsigned int*)(0x42212494UL))) +#define bM4_AOS_PEVNTODR2_POUT06 (*((volatile unsigned int*)(0x42212498UL))) +#define bM4_AOS_PEVNTODR2_POUT07 (*((volatile unsigned int*)(0x4221249CUL))) +#define bM4_AOS_PEVNTODR2_POUT08 (*((volatile unsigned int*)(0x422124A0UL))) +#define bM4_AOS_PEVNTODR2_POUT09 (*((volatile unsigned int*)(0x422124A4UL))) +#define bM4_AOS_PEVNTODR2_POUT10 (*((volatile unsigned int*)(0x422124A8UL))) +#define bM4_AOS_PEVNTODR2_POUT11 (*((volatile unsigned int*)(0x422124ACUL))) +#define bM4_AOS_PEVNTODR2_POUT12 (*((volatile unsigned int*)(0x422124B0UL))) +#define bM4_AOS_PEVNTODR2_POUT13 (*((volatile unsigned int*)(0x422124B4UL))) +#define bM4_AOS_PEVNTODR2_POUT14 (*((volatile unsigned int*)(0x422124B8UL))) +#define bM4_AOS_PEVNTODR2_POUT15 (*((volatile unsigned int*)(0x422124BCUL))) +#define bM4_AOS_PEVNTORR2_POR00 (*((volatile unsigned int*)(0x42212500UL))) +#define bM4_AOS_PEVNTORR2_POR01 (*((volatile unsigned int*)(0x42212504UL))) +#define bM4_AOS_PEVNTORR2_POR02 (*((volatile unsigned int*)(0x42212508UL))) +#define bM4_AOS_PEVNTORR2_POR03 (*((volatile unsigned int*)(0x4221250CUL))) +#define bM4_AOS_PEVNTORR2_POR04 (*((volatile unsigned int*)(0x42212510UL))) +#define bM4_AOS_PEVNTORR2_POR05 (*((volatile unsigned int*)(0x42212514UL))) +#define bM4_AOS_PEVNTORR2_POR06 (*((volatile unsigned int*)(0x42212518UL))) +#define bM4_AOS_PEVNTORR2_POR07 (*((volatile unsigned int*)(0x4221251CUL))) +#define bM4_AOS_PEVNTORR2_POR08 (*((volatile unsigned int*)(0x42212520UL))) +#define bM4_AOS_PEVNTORR2_POR09 (*((volatile unsigned int*)(0x42212524UL))) +#define bM4_AOS_PEVNTORR2_POR10 (*((volatile unsigned int*)(0x42212528UL))) +#define bM4_AOS_PEVNTORR2_POR11 (*((volatile unsigned int*)(0x4221252CUL))) +#define bM4_AOS_PEVNTORR2_POR12 (*((volatile unsigned int*)(0x42212530UL))) +#define bM4_AOS_PEVNTORR2_POR13 (*((volatile unsigned int*)(0x42212534UL))) +#define bM4_AOS_PEVNTORR2_POR14 (*((volatile unsigned int*)(0x42212538UL))) +#define bM4_AOS_PEVNTORR2_POR15 (*((volatile unsigned int*)(0x4221253CUL))) +#define bM4_AOS_PEVNTOSR2_POS00 (*((volatile unsigned int*)(0x42212580UL))) +#define bM4_AOS_PEVNTOSR2_POS01 (*((volatile unsigned int*)(0x42212584UL))) +#define bM4_AOS_PEVNTOSR2_POS02 (*((volatile unsigned int*)(0x42212588UL))) +#define bM4_AOS_PEVNTOSR2_POS03 (*((volatile unsigned int*)(0x4221258CUL))) +#define bM4_AOS_PEVNTOSR2_POS04 (*((volatile unsigned int*)(0x42212590UL))) +#define bM4_AOS_PEVNTOSR2_POS05 (*((volatile unsigned int*)(0x42212594UL))) +#define bM4_AOS_PEVNTOSR2_POS06 (*((volatile unsigned int*)(0x42212598UL))) +#define bM4_AOS_PEVNTOSR2_POS07 (*((volatile unsigned int*)(0x4221259CUL))) +#define bM4_AOS_PEVNTOSR2_POS08 (*((volatile unsigned int*)(0x422125A0UL))) +#define bM4_AOS_PEVNTOSR2_POS09 (*((volatile unsigned int*)(0x422125A4UL))) +#define bM4_AOS_PEVNTOSR2_POS10 (*((volatile unsigned int*)(0x422125A8UL))) +#define bM4_AOS_PEVNTOSR2_POS11 (*((volatile unsigned int*)(0x422125ACUL))) +#define bM4_AOS_PEVNTOSR2_POS12 (*((volatile unsigned int*)(0x422125B0UL))) +#define bM4_AOS_PEVNTOSR2_POS13 (*((volatile unsigned int*)(0x422125B4UL))) +#define bM4_AOS_PEVNTOSR2_POS14 (*((volatile unsigned int*)(0x422125B8UL))) +#define bM4_AOS_PEVNTOSR2_POS15 (*((volatile unsigned int*)(0x422125BCUL))) +#define bM4_AOS_PEVNTRISR2_RIS00 (*((volatile unsigned int*)(0x42212600UL))) +#define bM4_AOS_PEVNTRISR2_RIS01 (*((volatile unsigned int*)(0x42212604UL))) +#define bM4_AOS_PEVNTRISR2_RIS02 (*((volatile unsigned int*)(0x42212608UL))) +#define bM4_AOS_PEVNTRISR2_RIS03 (*((volatile unsigned int*)(0x4221260CUL))) +#define bM4_AOS_PEVNTRISR2_RIS04 (*((volatile unsigned int*)(0x42212610UL))) +#define bM4_AOS_PEVNTRISR2_RIS05 (*((volatile unsigned int*)(0x42212614UL))) +#define bM4_AOS_PEVNTRISR2_RIS06 (*((volatile unsigned int*)(0x42212618UL))) +#define bM4_AOS_PEVNTRISR2_RIS07 (*((volatile unsigned int*)(0x4221261CUL))) +#define bM4_AOS_PEVNTRISR2_RIS08 (*((volatile unsigned int*)(0x42212620UL))) +#define bM4_AOS_PEVNTRISR2_RIS09 (*((volatile unsigned int*)(0x42212624UL))) +#define bM4_AOS_PEVNTRISR2_RIS10 (*((volatile unsigned int*)(0x42212628UL))) +#define bM4_AOS_PEVNTRISR2_RIS11 (*((volatile unsigned int*)(0x4221262CUL))) +#define bM4_AOS_PEVNTRISR2_RIS12 (*((volatile unsigned int*)(0x42212630UL))) +#define bM4_AOS_PEVNTRISR2_RIS13 (*((volatile unsigned int*)(0x42212634UL))) +#define bM4_AOS_PEVNTRISR2_RIS14 (*((volatile unsigned int*)(0x42212638UL))) +#define bM4_AOS_PEVNTRISR2_RIS15 (*((volatile unsigned int*)(0x4221263CUL))) +#define bM4_AOS_PEVNTFAL2_FAL00 (*((volatile unsigned int*)(0x42212680UL))) +#define bM4_AOS_PEVNTFAL2_FAL01 (*((volatile unsigned int*)(0x42212684UL))) +#define bM4_AOS_PEVNTFAL2_FAL02 (*((volatile unsigned int*)(0x42212688UL))) +#define bM4_AOS_PEVNTFAL2_FAL03 (*((volatile unsigned int*)(0x4221268CUL))) +#define bM4_AOS_PEVNTFAL2_FAL04 (*((volatile unsigned int*)(0x42212690UL))) +#define bM4_AOS_PEVNTFAL2_FAL05 (*((volatile unsigned int*)(0x42212694UL))) +#define bM4_AOS_PEVNTFAL2_FAL06 (*((volatile unsigned int*)(0x42212698UL))) +#define bM4_AOS_PEVNTFAL2_FAL07 (*((volatile unsigned int*)(0x4221269CUL))) +#define bM4_AOS_PEVNTFAL2_FAL08 (*((volatile unsigned int*)(0x422126A0UL))) +#define bM4_AOS_PEVNTFAL2_FAL09 (*((volatile unsigned int*)(0x422126A4UL))) +#define bM4_AOS_PEVNTFAL2_FAL10 (*((volatile unsigned int*)(0x422126A8UL))) +#define bM4_AOS_PEVNTFAL2_FAL11 (*((volatile unsigned int*)(0x422126ACUL))) +#define bM4_AOS_PEVNTFAL2_FAL12 (*((volatile unsigned int*)(0x422126B0UL))) +#define bM4_AOS_PEVNTFAL2_FAL13 (*((volatile unsigned int*)(0x422126B4UL))) +#define bM4_AOS_PEVNTFAL2_FAL14 (*((volatile unsigned int*)(0x422126B8UL))) +#define bM4_AOS_PEVNTFAL2_FAL15 (*((volatile unsigned int*)(0x422126BCUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR00 (*((volatile unsigned int*)(0x42212700UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR01 (*((volatile unsigned int*)(0x42212704UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR02 (*((volatile unsigned int*)(0x42212708UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR03 (*((volatile unsigned int*)(0x4221270CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR04 (*((volatile unsigned int*)(0x42212710UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR05 (*((volatile unsigned int*)(0x42212714UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR06 (*((volatile unsigned int*)(0x42212718UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR07 (*((volatile unsigned int*)(0x4221271CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR08 (*((volatile unsigned int*)(0x42212720UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR09 (*((volatile unsigned int*)(0x42212724UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR10 (*((volatile unsigned int*)(0x42212728UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR11 (*((volatile unsigned int*)(0x4221272CUL))) +#define bM4_AOS_PEVNTDIRR3_PDIR12 (*((volatile unsigned int*)(0x42212730UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR13 (*((volatile unsigned int*)(0x42212734UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR14 (*((volatile unsigned int*)(0x42212738UL))) +#define bM4_AOS_PEVNTDIRR3_PDIR15 (*((volatile unsigned int*)(0x4221273CUL))) +#define bM4_AOS_PEVNTIDR3_PIN00 (*((volatile unsigned int*)(0x42212780UL))) +#define bM4_AOS_PEVNTIDR3_PIN01 (*((volatile unsigned int*)(0x42212784UL))) +#define bM4_AOS_PEVNTIDR3_PIN02 (*((volatile unsigned int*)(0x42212788UL))) +#define bM4_AOS_PEVNTIDR3_PIN03 (*((volatile unsigned int*)(0x4221278CUL))) +#define bM4_AOS_PEVNTIDR3_PIN04 (*((volatile unsigned int*)(0x42212790UL))) +#define bM4_AOS_PEVNTIDR3_PIN05 (*((volatile unsigned int*)(0x42212794UL))) +#define bM4_AOS_PEVNTIDR3_PIN06 (*((volatile unsigned int*)(0x42212798UL))) +#define bM4_AOS_PEVNTIDR3_PIN07 (*((volatile unsigned int*)(0x4221279CUL))) +#define bM4_AOS_PEVNTIDR3_PIN08 (*((volatile unsigned int*)(0x422127A0UL))) +#define bM4_AOS_PEVNTIDR3_PIN09 (*((volatile unsigned int*)(0x422127A4UL))) +#define bM4_AOS_PEVNTIDR3_PIN10 (*((volatile unsigned int*)(0x422127A8UL))) +#define bM4_AOS_PEVNTIDR3_PIN11 (*((volatile unsigned int*)(0x422127ACUL))) +#define bM4_AOS_PEVNTIDR3_PIN12 (*((volatile unsigned int*)(0x422127B0UL))) +#define bM4_AOS_PEVNTIDR3_PIN13 (*((volatile unsigned int*)(0x422127B4UL))) +#define bM4_AOS_PEVNTIDR3_PIN14 (*((volatile unsigned int*)(0x422127B8UL))) +#define bM4_AOS_PEVNTIDR3_PIN15 (*((volatile unsigned int*)(0x422127BCUL))) +#define bM4_AOS_PEVNTODR3_POUT00 (*((volatile unsigned int*)(0x42212800UL))) +#define bM4_AOS_PEVNTODR3_POUT01 (*((volatile unsigned int*)(0x42212804UL))) +#define bM4_AOS_PEVNTODR3_POUT02 (*((volatile unsigned int*)(0x42212808UL))) +#define bM4_AOS_PEVNTODR3_POUT03 (*((volatile unsigned int*)(0x4221280CUL))) +#define bM4_AOS_PEVNTODR3_POUT04 (*((volatile unsigned int*)(0x42212810UL))) +#define bM4_AOS_PEVNTODR3_POUT05 (*((volatile unsigned int*)(0x42212814UL))) +#define bM4_AOS_PEVNTODR3_POUT06 (*((volatile unsigned int*)(0x42212818UL))) +#define bM4_AOS_PEVNTODR3_POUT07 (*((volatile unsigned int*)(0x4221281CUL))) +#define bM4_AOS_PEVNTODR3_POUT08 (*((volatile unsigned int*)(0x42212820UL))) +#define bM4_AOS_PEVNTODR3_POUT09 (*((volatile unsigned int*)(0x42212824UL))) +#define bM4_AOS_PEVNTODR3_POUT10 (*((volatile unsigned int*)(0x42212828UL))) +#define bM4_AOS_PEVNTODR3_POUT11 (*((volatile unsigned int*)(0x4221282CUL))) +#define bM4_AOS_PEVNTODR3_POUT12 (*((volatile unsigned int*)(0x42212830UL))) +#define bM4_AOS_PEVNTODR3_POUT13 (*((volatile unsigned int*)(0x42212834UL))) +#define bM4_AOS_PEVNTODR3_POUT14 (*((volatile unsigned int*)(0x42212838UL))) +#define bM4_AOS_PEVNTODR3_POUT15 (*((volatile unsigned int*)(0x4221283CUL))) +#define bM4_AOS_PEVNTORR3_POR00 (*((volatile unsigned int*)(0x42212880UL))) +#define bM4_AOS_PEVNTORR3_POR01 (*((volatile unsigned int*)(0x42212884UL))) +#define bM4_AOS_PEVNTORR3_POR02 (*((volatile unsigned int*)(0x42212888UL))) +#define bM4_AOS_PEVNTORR3_POR03 (*((volatile unsigned int*)(0x4221288CUL))) +#define bM4_AOS_PEVNTORR3_POR04 (*((volatile unsigned int*)(0x42212890UL))) +#define bM4_AOS_PEVNTORR3_POR05 (*((volatile unsigned int*)(0x42212894UL))) +#define bM4_AOS_PEVNTORR3_POR06 (*((volatile unsigned int*)(0x42212898UL))) +#define bM4_AOS_PEVNTORR3_POR07 (*((volatile unsigned int*)(0x4221289CUL))) +#define bM4_AOS_PEVNTORR3_POR08 (*((volatile unsigned int*)(0x422128A0UL))) +#define bM4_AOS_PEVNTORR3_POR09 (*((volatile unsigned int*)(0x422128A4UL))) +#define bM4_AOS_PEVNTORR3_POR10 (*((volatile unsigned int*)(0x422128A8UL))) +#define bM4_AOS_PEVNTORR3_POR11 (*((volatile unsigned int*)(0x422128ACUL))) +#define bM4_AOS_PEVNTORR3_POR12 (*((volatile unsigned int*)(0x422128B0UL))) +#define bM4_AOS_PEVNTORR3_POR13 (*((volatile unsigned int*)(0x422128B4UL))) +#define bM4_AOS_PEVNTORR3_POR14 (*((volatile unsigned int*)(0x422128B8UL))) +#define bM4_AOS_PEVNTORR3_POR15 (*((volatile unsigned int*)(0x422128BCUL))) +#define bM4_AOS_PEVNTOSR3_POS00 (*((volatile unsigned int*)(0x42212900UL))) +#define bM4_AOS_PEVNTOSR3_POS01 (*((volatile unsigned int*)(0x42212904UL))) +#define bM4_AOS_PEVNTOSR3_POS02 (*((volatile unsigned int*)(0x42212908UL))) +#define bM4_AOS_PEVNTOSR3_POS03 (*((volatile unsigned int*)(0x4221290CUL))) +#define bM4_AOS_PEVNTOSR3_POS04 (*((volatile unsigned int*)(0x42212910UL))) +#define bM4_AOS_PEVNTOSR3_POS05 (*((volatile unsigned int*)(0x42212914UL))) +#define bM4_AOS_PEVNTOSR3_POS06 (*((volatile unsigned int*)(0x42212918UL))) +#define bM4_AOS_PEVNTOSR3_POS07 (*((volatile unsigned int*)(0x4221291CUL))) +#define bM4_AOS_PEVNTOSR3_POS08 (*((volatile unsigned int*)(0x42212920UL))) +#define bM4_AOS_PEVNTOSR3_POS09 (*((volatile unsigned int*)(0x42212924UL))) +#define bM4_AOS_PEVNTOSR3_POS10 (*((volatile unsigned int*)(0x42212928UL))) +#define bM4_AOS_PEVNTOSR3_POS11 (*((volatile unsigned int*)(0x4221292CUL))) +#define bM4_AOS_PEVNTOSR3_POS12 (*((volatile unsigned int*)(0x42212930UL))) +#define bM4_AOS_PEVNTOSR3_POS13 (*((volatile unsigned int*)(0x42212934UL))) +#define bM4_AOS_PEVNTOSR3_POS14 (*((volatile unsigned int*)(0x42212938UL))) +#define bM4_AOS_PEVNTOSR3_POS15 (*((volatile unsigned int*)(0x4221293CUL))) +#define bM4_AOS_PEVNTRISR3_RIS00 (*((volatile unsigned int*)(0x42212980UL))) +#define bM4_AOS_PEVNTRISR3_RIS01 (*((volatile unsigned int*)(0x42212984UL))) +#define bM4_AOS_PEVNTRISR3_RIS02 (*((volatile unsigned int*)(0x42212988UL))) +#define bM4_AOS_PEVNTRISR3_RIS03 (*((volatile unsigned int*)(0x4221298CUL))) +#define bM4_AOS_PEVNTRISR3_RIS04 (*((volatile unsigned int*)(0x42212990UL))) +#define bM4_AOS_PEVNTRISR3_RIS05 (*((volatile unsigned int*)(0x42212994UL))) +#define bM4_AOS_PEVNTRISR3_RIS06 (*((volatile unsigned int*)(0x42212998UL))) +#define bM4_AOS_PEVNTRISR3_RIS07 (*((volatile unsigned int*)(0x4221299CUL))) +#define bM4_AOS_PEVNTRISR3_RIS08 (*((volatile unsigned int*)(0x422129A0UL))) +#define bM4_AOS_PEVNTRISR3_RIS09 (*((volatile unsigned int*)(0x422129A4UL))) +#define bM4_AOS_PEVNTRISR3_RIS10 (*((volatile unsigned int*)(0x422129A8UL))) +#define bM4_AOS_PEVNTRISR3_RIS11 (*((volatile unsigned int*)(0x422129ACUL))) +#define bM4_AOS_PEVNTRISR3_RIS12 (*((volatile unsigned int*)(0x422129B0UL))) +#define bM4_AOS_PEVNTRISR3_RIS13 (*((volatile unsigned int*)(0x422129B4UL))) +#define bM4_AOS_PEVNTRISR3_RIS14 (*((volatile unsigned int*)(0x422129B8UL))) +#define bM4_AOS_PEVNTRISR3_RIS15 (*((volatile unsigned int*)(0x422129BCUL))) +#define bM4_AOS_PEVNTFAL3_FAL00 (*((volatile unsigned int*)(0x42212A00UL))) +#define bM4_AOS_PEVNTFAL3_FAL01 (*((volatile unsigned int*)(0x42212A04UL))) +#define bM4_AOS_PEVNTFAL3_FAL02 (*((volatile unsigned int*)(0x42212A08UL))) +#define bM4_AOS_PEVNTFAL3_FAL03 (*((volatile unsigned int*)(0x42212A0CUL))) +#define bM4_AOS_PEVNTFAL3_FAL04 (*((volatile unsigned int*)(0x42212A10UL))) +#define bM4_AOS_PEVNTFAL3_FAL05 (*((volatile unsigned int*)(0x42212A14UL))) +#define bM4_AOS_PEVNTFAL3_FAL06 (*((volatile unsigned int*)(0x42212A18UL))) +#define bM4_AOS_PEVNTFAL3_FAL07 (*((volatile unsigned int*)(0x42212A1CUL))) +#define bM4_AOS_PEVNTFAL3_FAL08 (*((volatile unsigned int*)(0x42212A20UL))) +#define bM4_AOS_PEVNTFAL3_FAL09 (*((volatile unsigned int*)(0x42212A24UL))) +#define bM4_AOS_PEVNTFAL3_FAL10 (*((volatile unsigned int*)(0x42212A28UL))) +#define bM4_AOS_PEVNTFAL3_FAL11 (*((volatile unsigned int*)(0x42212A2CUL))) +#define bM4_AOS_PEVNTFAL3_FAL12 (*((volatile unsigned int*)(0x42212A30UL))) +#define bM4_AOS_PEVNTFAL3_FAL13 (*((volatile unsigned int*)(0x42212A34UL))) +#define bM4_AOS_PEVNTFAL3_FAL14 (*((volatile unsigned int*)(0x42212A38UL))) +#define bM4_AOS_PEVNTFAL3_FAL15 (*((volatile unsigned int*)(0x42212A3CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR00 (*((volatile unsigned int*)(0x42212A80UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR01 (*((volatile unsigned int*)(0x42212A84UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR02 (*((volatile unsigned int*)(0x42212A88UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR03 (*((volatile unsigned int*)(0x42212A8CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR04 (*((volatile unsigned int*)(0x42212A90UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR05 (*((volatile unsigned int*)(0x42212A94UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR06 (*((volatile unsigned int*)(0x42212A98UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR07 (*((volatile unsigned int*)(0x42212A9CUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR08 (*((volatile unsigned int*)(0x42212AA0UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR09 (*((volatile unsigned int*)(0x42212AA4UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR10 (*((volatile unsigned int*)(0x42212AA8UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR11 (*((volatile unsigned int*)(0x42212AACUL))) +#define bM4_AOS_PEVNTDIRR4_PDIR12 (*((volatile unsigned int*)(0x42212AB0UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR13 (*((volatile unsigned int*)(0x42212AB4UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR14 (*((volatile unsigned int*)(0x42212AB8UL))) +#define bM4_AOS_PEVNTDIRR4_PDIR15 (*((volatile unsigned int*)(0x42212ABCUL))) +#define bM4_AOS_PEVNTIDR4_PIN00 (*((volatile unsigned int*)(0x42212B00UL))) +#define bM4_AOS_PEVNTIDR4_PIN01 (*((volatile unsigned int*)(0x42212B04UL))) +#define bM4_AOS_PEVNTIDR4_PIN02 (*((volatile unsigned int*)(0x42212B08UL))) +#define bM4_AOS_PEVNTIDR4_PIN03 (*((volatile unsigned int*)(0x42212B0CUL))) +#define bM4_AOS_PEVNTIDR4_PIN04 (*((volatile unsigned int*)(0x42212B10UL))) +#define bM4_AOS_PEVNTIDR4_PIN05 (*((volatile unsigned int*)(0x42212B14UL))) +#define bM4_AOS_PEVNTIDR4_PIN06 (*((volatile unsigned int*)(0x42212B18UL))) +#define bM4_AOS_PEVNTIDR4_PIN07 (*((volatile unsigned int*)(0x42212B1CUL))) +#define bM4_AOS_PEVNTIDR4_PIN08 (*((volatile unsigned int*)(0x42212B20UL))) +#define bM4_AOS_PEVNTIDR4_PIN09 (*((volatile unsigned int*)(0x42212B24UL))) +#define bM4_AOS_PEVNTIDR4_PIN10 (*((volatile unsigned int*)(0x42212B28UL))) +#define bM4_AOS_PEVNTIDR4_PIN11 (*((volatile unsigned int*)(0x42212B2CUL))) +#define bM4_AOS_PEVNTIDR4_PIN12 (*((volatile unsigned int*)(0x42212B30UL))) +#define bM4_AOS_PEVNTIDR4_PIN13 (*((volatile unsigned int*)(0x42212B34UL))) +#define bM4_AOS_PEVNTIDR4_PIN14 (*((volatile unsigned int*)(0x42212B38UL))) +#define bM4_AOS_PEVNTIDR4_PIN15 (*((volatile unsigned int*)(0x42212B3CUL))) +#define bM4_AOS_PEVNTODR4_POUT00 (*((volatile unsigned int*)(0x42212B80UL))) +#define bM4_AOS_PEVNTODR4_POUT01 (*((volatile unsigned int*)(0x42212B84UL))) +#define bM4_AOS_PEVNTODR4_POUT02 (*((volatile unsigned int*)(0x42212B88UL))) +#define bM4_AOS_PEVNTODR4_POUT03 (*((volatile unsigned int*)(0x42212B8CUL))) +#define bM4_AOS_PEVNTODR4_POUT04 (*((volatile unsigned int*)(0x42212B90UL))) +#define bM4_AOS_PEVNTODR4_POUT05 (*((volatile unsigned int*)(0x42212B94UL))) +#define bM4_AOS_PEVNTODR4_POUT06 (*((volatile unsigned int*)(0x42212B98UL))) +#define bM4_AOS_PEVNTODR4_POUT07 (*((volatile unsigned int*)(0x42212B9CUL))) +#define bM4_AOS_PEVNTODR4_POUT08 (*((volatile unsigned int*)(0x42212BA0UL))) +#define bM4_AOS_PEVNTODR4_POUT09 (*((volatile unsigned int*)(0x42212BA4UL))) +#define bM4_AOS_PEVNTODR4_POUT10 (*((volatile unsigned int*)(0x42212BA8UL))) +#define bM4_AOS_PEVNTODR4_POUT11 (*((volatile unsigned int*)(0x42212BACUL))) +#define bM4_AOS_PEVNTODR4_POUT12 (*((volatile unsigned int*)(0x42212BB0UL))) +#define bM4_AOS_PEVNTODR4_POUT13 (*((volatile unsigned int*)(0x42212BB4UL))) +#define bM4_AOS_PEVNTODR4_POUT14 (*((volatile unsigned int*)(0x42212BB8UL))) +#define bM4_AOS_PEVNTODR4_POUT15 (*((volatile unsigned int*)(0x42212BBCUL))) +#define bM4_AOS_PEVNTORR4_POR00 (*((volatile unsigned int*)(0x42212C00UL))) +#define bM4_AOS_PEVNTORR4_POR01 (*((volatile unsigned int*)(0x42212C04UL))) +#define bM4_AOS_PEVNTORR4_POR02 (*((volatile unsigned int*)(0x42212C08UL))) +#define bM4_AOS_PEVNTORR4_POR03 (*((volatile unsigned int*)(0x42212C0CUL))) +#define bM4_AOS_PEVNTORR4_POR04 (*((volatile unsigned int*)(0x42212C10UL))) +#define bM4_AOS_PEVNTORR4_POR05 (*((volatile unsigned int*)(0x42212C14UL))) +#define bM4_AOS_PEVNTORR4_POR06 (*((volatile unsigned int*)(0x42212C18UL))) +#define bM4_AOS_PEVNTORR4_POR07 (*((volatile unsigned int*)(0x42212C1CUL))) +#define bM4_AOS_PEVNTORR4_POR08 (*((volatile unsigned int*)(0x42212C20UL))) +#define bM4_AOS_PEVNTORR4_POR09 (*((volatile unsigned int*)(0x42212C24UL))) +#define bM4_AOS_PEVNTORR4_POR10 (*((volatile unsigned int*)(0x42212C28UL))) +#define bM4_AOS_PEVNTORR4_POR11 (*((volatile unsigned int*)(0x42212C2CUL))) +#define bM4_AOS_PEVNTORR4_POR12 (*((volatile unsigned int*)(0x42212C30UL))) +#define bM4_AOS_PEVNTORR4_POR13 (*((volatile unsigned int*)(0x42212C34UL))) +#define bM4_AOS_PEVNTORR4_POR14 (*((volatile unsigned int*)(0x42212C38UL))) +#define bM4_AOS_PEVNTORR4_POR15 (*((volatile unsigned int*)(0x42212C3CUL))) +#define bM4_AOS_PEVNTOSR4_POS00 (*((volatile unsigned int*)(0x42212C80UL))) +#define bM4_AOS_PEVNTOSR4_POS01 (*((volatile unsigned int*)(0x42212C84UL))) +#define bM4_AOS_PEVNTOSR4_POS02 (*((volatile unsigned int*)(0x42212C88UL))) +#define bM4_AOS_PEVNTOSR4_POS03 (*((volatile unsigned int*)(0x42212C8CUL))) +#define bM4_AOS_PEVNTOSR4_POS04 (*((volatile unsigned int*)(0x42212C90UL))) +#define bM4_AOS_PEVNTOSR4_POS05 (*((volatile unsigned int*)(0x42212C94UL))) +#define bM4_AOS_PEVNTOSR4_POS06 (*((volatile unsigned int*)(0x42212C98UL))) +#define bM4_AOS_PEVNTOSR4_POS07 (*((volatile unsigned int*)(0x42212C9CUL))) +#define bM4_AOS_PEVNTOSR4_POS08 (*((volatile unsigned int*)(0x42212CA0UL))) +#define bM4_AOS_PEVNTOSR4_POS09 (*((volatile unsigned int*)(0x42212CA4UL))) +#define bM4_AOS_PEVNTOSR4_POS10 (*((volatile unsigned int*)(0x42212CA8UL))) +#define bM4_AOS_PEVNTOSR4_POS11 (*((volatile unsigned int*)(0x42212CACUL))) +#define bM4_AOS_PEVNTOSR4_POS12 (*((volatile unsigned int*)(0x42212CB0UL))) +#define bM4_AOS_PEVNTOSR4_POS13 (*((volatile unsigned int*)(0x42212CB4UL))) +#define bM4_AOS_PEVNTOSR4_POS14 (*((volatile unsigned int*)(0x42212CB8UL))) +#define bM4_AOS_PEVNTOSR4_POS15 (*((volatile unsigned int*)(0x42212CBCUL))) +#define bM4_AOS_PEVNTRISR4_RIS00 (*((volatile unsigned int*)(0x42212D00UL))) +#define bM4_AOS_PEVNTRISR4_RIS01 (*((volatile unsigned int*)(0x42212D04UL))) +#define bM4_AOS_PEVNTRISR4_RIS02 (*((volatile unsigned int*)(0x42212D08UL))) +#define bM4_AOS_PEVNTRISR4_RIS03 (*((volatile unsigned int*)(0x42212D0CUL))) +#define bM4_AOS_PEVNTRISR4_RIS04 (*((volatile unsigned int*)(0x42212D10UL))) +#define bM4_AOS_PEVNTRISR4_RIS05 (*((volatile unsigned int*)(0x42212D14UL))) +#define bM4_AOS_PEVNTRISR4_RIS06 (*((volatile unsigned int*)(0x42212D18UL))) +#define bM4_AOS_PEVNTRISR4_RIS07 (*((volatile unsigned int*)(0x42212D1CUL))) +#define bM4_AOS_PEVNTRISR4_RIS08 (*((volatile unsigned int*)(0x42212D20UL))) +#define bM4_AOS_PEVNTRISR4_RIS09 (*((volatile unsigned int*)(0x42212D24UL))) +#define bM4_AOS_PEVNTRISR4_RIS10 (*((volatile unsigned int*)(0x42212D28UL))) +#define bM4_AOS_PEVNTRISR4_RIS11 (*((volatile unsigned int*)(0x42212D2CUL))) +#define bM4_AOS_PEVNTRISR4_RIS12 (*((volatile unsigned int*)(0x42212D30UL))) +#define bM4_AOS_PEVNTRISR4_RIS13 (*((volatile unsigned int*)(0x42212D34UL))) +#define bM4_AOS_PEVNTRISR4_RIS14 (*((volatile unsigned int*)(0x42212D38UL))) +#define bM4_AOS_PEVNTRISR4_RIS15 (*((volatile unsigned int*)(0x42212D3CUL))) +#define bM4_AOS_PEVNTFAL4_FAL00 (*((volatile unsigned int*)(0x42212D80UL))) +#define bM4_AOS_PEVNTFAL4_FAL01 (*((volatile unsigned int*)(0x42212D84UL))) +#define bM4_AOS_PEVNTFAL4_FAL02 (*((volatile unsigned int*)(0x42212D88UL))) +#define bM4_AOS_PEVNTFAL4_FAL03 (*((volatile unsigned int*)(0x42212D8CUL))) +#define bM4_AOS_PEVNTFAL4_FAL04 (*((volatile unsigned int*)(0x42212D90UL))) +#define bM4_AOS_PEVNTFAL4_FAL05 (*((volatile unsigned int*)(0x42212D94UL))) +#define bM4_AOS_PEVNTFAL4_FAL06 (*((volatile unsigned int*)(0x42212D98UL))) +#define bM4_AOS_PEVNTFAL4_FAL07 (*((volatile unsigned int*)(0x42212D9CUL))) +#define bM4_AOS_PEVNTFAL4_FAL08 (*((volatile unsigned int*)(0x42212DA0UL))) +#define bM4_AOS_PEVNTFAL4_FAL09 (*((volatile unsigned int*)(0x42212DA4UL))) +#define bM4_AOS_PEVNTFAL4_FAL10 (*((volatile unsigned int*)(0x42212DA8UL))) +#define bM4_AOS_PEVNTFAL4_FAL11 (*((volatile unsigned int*)(0x42212DACUL))) +#define bM4_AOS_PEVNTFAL4_FAL12 (*((volatile unsigned int*)(0x42212DB0UL))) +#define bM4_AOS_PEVNTFAL4_FAL13 (*((volatile unsigned int*)(0x42212DB4UL))) +#define bM4_AOS_PEVNTFAL4_FAL14 (*((volatile unsigned int*)(0x42212DB8UL))) +#define bM4_AOS_PEVNTFAL4_FAL15 (*((volatile unsigned int*)(0x42212DBCUL))) +#define bM4_AOS_PEVNTNFCR_NFEN1 (*((volatile unsigned int*)(0x42212E00UL))) +#define bM4_AOS_PEVNTNFCR_DIVS10 (*((volatile unsigned int*)(0x42212E04UL))) +#define bM4_AOS_PEVNTNFCR_DIVS11 (*((volatile unsigned int*)(0x42212E08UL))) +#define bM4_AOS_PEVNTNFCR_NFEN2 (*((volatile unsigned int*)(0x42212E20UL))) +#define bM4_AOS_PEVNTNFCR_DIVS20 (*((volatile unsigned int*)(0x42212E24UL))) +#define bM4_AOS_PEVNTNFCR_DIVS21 (*((volatile unsigned int*)(0x42212E28UL))) +#define bM4_AOS_PEVNTNFCR_NFEN3 (*((volatile unsigned int*)(0x42212E40UL))) +#define bM4_AOS_PEVNTNFCR_DIVS30 (*((volatile unsigned int*)(0x42212E44UL))) +#define bM4_AOS_PEVNTNFCR_DIVS31 (*((volatile unsigned int*)(0x42212E48UL))) +#define bM4_AOS_PEVNTNFCR_NFEN4 (*((volatile unsigned int*)(0x42212E60UL))) +#define bM4_AOS_PEVNTNFCR_DIVS40 (*((volatile unsigned int*)(0x42212E64UL))) +#define bM4_AOS_PEVNTNFCR_DIVS41 (*((volatile unsigned int*)(0x42212E68UL))) +#define bM4_CAN_CFG_STAT_BUSOFF (*((volatile unsigned int*)(0x42E09400UL))) +#define bM4_CAN_CFG_STAT_TACTIVE (*((volatile unsigned int*)(0x42E09404UL))) +#define bM4_CAN_CFG_STAT_RACTIVE (*((volatile unsigned int*)(0x42E09408UL))) +#define bM4_CAN_CFG_STAT_TSSS (*((volatile unsigned int*)(0x42E0940CUL))) +#define bM4_CAN_CFG_STAT_TPSS (*((volatile unsigned int*)(0x42E09410UL))) +#define bM4_CAN_CFG_STAT_LBMI (*((volatile unsigned int*)(0x42E09414UL))) +#define bM4_CAN_CFG_STAT_LBME (*((volatile unsigned int*)(0x42E09418UL))) +#define bM4_CAN_CFG_STAT_RESET (*((volatile unsigned int*)(0x42E0941CUL))) +#define bM4_CAN_TCMD_TSA (*((volatile unsigned int*)(0x42E09420UL))) +#define bM4_CAN_TCMD_TSALL (*((volatile unsigned int*)(0x42E09424UL))) +#define bM4_CAN_TCMD_TSONE (*((volatile unsigned int*)(0x42E09428UL))) +#define bM4_CAN_TCMD_TPA (*((volatile unsigned int*)(0x42E0942CUL))) +#define bM4_CAN_TCMD_TPE (*((volatile unsigned int*)(0x42E09430UL))) +#define bM4_CAN_TCMD_STBY (*((volatile unsigned int*)(0x42E09434UL))) +#define bM4_CAN_TCMD_LOM (*((volatile unsigned int*)(0x42E09438UL))) +#define bM4_CAN_TCMD_TBSEL (*((volatile unsigned int*)(0x42E0943CUL))) +#define bM4_CAN_TCTRL_TSSTAT0 (*((volatile unsigned int*)(0x42E09440UL))) +#define bM4_CAN_TCTRL_TSSTAT1 (*((volatile unsigned int*)(0x42E09444UL))) +#define bM4_CAN_TCTRL_TTBM (*((volatile unsigned int*)(0x42E09450UL))) +#define bM4_CAN_TCTRL_TSMODE (*((volatile unsigned int*)(0x42E09454UL))) +#define bM4_CAN_TCTRL_TSNEXT (*((volatile unsigned int*)(0x42E09458UL))) +#define bM4_CAN_RCTRL_RSSTAT0 (*((volatile unsigned int*)(0x42E09460UL))) +#define bM4_CAN_RCTRL_RSSTAT1 (*((volatile unsigned int*)(0x42E09464UL))) +#define bM4_CAN_RCTRL_RBALL (*((volatile unsigned int*)(0x42E0946CUL))) +#define bM4_CAN_RCTRL_RREL (*((volatile unsigned int*)(0x42E09470UL))) +#define bM4_CAN_RCTRL_ROV (*((volatile unsigned int*)(0x42E09474UL))) +#define bM4_CAN_RCTRL_ROM (*((volatile unsigned int*)(0x42E09478UL))) +#define bM4_CAN_RCTRL_SACK (*((volatile unsigned int*)(0x42E0947CUL))) +#define bM4_CAN_RTIE_TSFF (*((volatile unsigned int*)(0x42E09480UL))) +#define bM4_CAN_RTIE_EIE (*((volatile unsigned int*)(0x42E09484UL))) +#define bM4_CAN_RTIE_TSIE (*((volatile unsigned int*)(0x42E09488UL))) +#define bM4_CAN_RTIE_TPIE (*((volatile unsigned int*)(0x42E0948CUL))) +#define bM4_CAN_RTIE_RAFIE (*((volatile unsigned int*)(0x42E09490UL))) +#define bM4_CAN_RTIE_RFIE (*((volatile unsigned int*)(0x42E09494UL))) +#define bM4_CAN_RTIE_ROIE (*((volatile unsigned int*)(0x42E09498UL))) +#define bM4_CAN_RTIE_RIE (*((volatile unsigned int*)(0x42E0949CUL))) +#define bM4_CAN_RTIF_AIF (*((volatile unsigned int*)(0x42E094A0UL))) +#define bM4_CAN_RTIF_EIF (*((volatile unsigned int*)(0x42E094A4UL))) +#define bM4_CAN_RTIF_TSIF (*((volatile unsigned int*)(0x42E094A8UL))) +#define bM4_CAN_RTIF_TPIF (*((volatile unsigned int*)(0x42E094ACUL))) +#define bM4_CAN_RTIF_RAFIF (*((volatile unsigned int*)(0x42E094B0UL))) +#define bM4_CAN_RTIF_RFIF (*((volatile unsigned int*)(0x42E094B4UL))) +#define bM4_CAN_RTIF_ROIF (*((volatile unsigned int*)(0x42E094B8UL))) +#define bM4_CAN_RTIF_RIF (*((volatile unsigned int*)(0x42E094BCUL))) +#define bM4_CAN_ERRINT_BEIF (*((volatile unsigned int*)(0x42E094C0UL))) +#define bM4_CAN_ERRINT_BEIE (*((volatile unsigned int*)(0x42E094C4UL))) +#define bM4_CAN_ERRINT_ALIF (*((volatile unsigned int*)(0x42E094C8UL))) +#define bM4_CAN_ERRINT_ALIE (*((volatile unsigned int*)(0x42E094CCUL))) +#define bM4_CAN_ERRINT_EPIF (*((volatile unsigned int*)(0x42E094D0UL))) +#define bM4_CAN_ERRINT_EPIE (*((volatile unsigned int*)(0x42E094D4UL))) +#define bM4_CAN_ERRINT_EPASS (*((volatile unsigned int*)(0x42E094D8UL))) +#define bM4_CAN_ERRINT_EWARN (*((volatile unsigned int*)(0x42E094DCUL))) +#define bM4_CAN_LIMIT_EWL0 (*((volatile unsigned int*)(0x42E094E0UL))) +#define bM4_CAN_LIMIT_EWL1 (*((volatile unsigned int*)(0x42E094E4UL))) +#define bM4_CAN_LIMIT_EWL2 (*((volatile unsigned int*)(0x42E094E8UL))) +#define bM4_CAN_LIMIT_EWL3 (*((volatile unsigned int*)(0x42E094ECUL))) +#define bM4_CAN_LIMIT_AFWL0 (*((volatile unsigned int*)(0x42E094F0UL))) +#define bM4_CAN_LIMIT_AFWL1 (*((volatile unsigned int*)(0x42E094F4UL))) +#define bM4_CAN_LIMIT_AFWL2 (*((volatile unsigned int*)(0x42E094F8UL))) +#define bM4_CAN_LIMIT_AFWL3 (*((volatile unsigned int*)(0x42E094FCUL))) +#define bM4_CAN_BT_SEG_10 (*((volatile unsigned int*)(0x42E09500UL))) +#define bM4_CAN_BT_SEG_11 (*((volatile unsigned int*)(0x42E09504UL))) +#define bM4_CAN_BT_SEG_12 (*((volatile unsigned int*)(0x42E09508UL))) +#define bM4_CAN_BT_SEG_13 (*((volatile unsigned int*)(0x42E0950CUL))) +#define bM4_CAN_BT_SEG_14 (*((volatile unsigned int*)(0x42E09510UL))) +#define bM4_CAN_BT_SEG_15 (*((volatile unsigned int*)(0x42E09514UL))) +#define bM4_CAN_BT_SEG_16 (*((volatile unsigned int*)(0x42E09518UL))) +#define bM4_CAN_BT_SEG_17 (*((volatile unsigned int*)(0x42E0951CUL))) +#define bM4_CAN_BT_SEG_20 (*((volatile unsigned int*)(0x42E09520UL))) +#define bM4_CAN_BT_SEG_21 (*((volatile unsigned int*)(0x42E09524UL))) +#define bM4_CAN_BT_SEG_22 (*((volatile unsigned int*)(0x42E09528UL))) +#define bM4_CAN_BT_SEG_23 (*((volatile unsigned int*)(0x42E0952CUL))) +#define bM4_CAN_BT_SEG_24 (*((volatile unsigned int*)(0x42E09530UL))) +#define bM4_CAN_BT_SEG_25 (*((volatile unsigned int*)(0x42E09534UL))) +#define bM4_CAN_BT_SEG_26 (*((volatile unsigned int*)(0x42E09538UL))) +#define bM4_CAN_BT_SJW0 (*((volatile unsigned int*)(0x42E09540UL))) +#define bM4_CAN_BT_SJW1 (*((volatile unsigned int*)(0x42E09544UL))) +#define bM4_CAN_BT_SJW2 (*((volatile unsigned int*)(0x42E09548UL))) +#define bM4_CAN_BT_SJW3 (*((volatile unsigned int*)(0x42E0954CUL))) +#define bM4_CAN_BT_SJW4 (*((volatile unsigned int*)(0x42E09550UL))) +#define bM4_CAN_BT_SJW5 (*((volatile unsigned int*)(0x42E09554UL))) +#define bM4_CAN_BT_SJW6 (*((volatile unsigned int*)(0x42E09558UL))) +#define bM4_CAN_BT_PRESC0 (*((volatile unsigned int*)(0x42E09560UL))) +#define bM4_CAN_BT_PRESC1 (*((volatile unsigned int*)(0x42E09564UL))) +#define bM4_CAN_BT_PRESC2 (*((volatile unsigned int*)(0x42E09568UL))) +#define bM4_CAN_BT_PRESC3 (*((volatile unsigned int*)(0x42E0956CUL))) +#define bM4_CAN_BT_PRESC4 (*((volatile unsigned int*)(0x42E09570UL))) +#define bM4_CAN_BT_PRESC5 (*((volatile unsigned int*)(0x42E09574UL))) +#define bM4_CAN_BT_PRESC6 (*((volatile unsigned int*)(0x42E09578UL))) +#define bM4_CAN_BT_PRESC7 (*((volatile unsigned int*)(0x42E0957CUL))) +#define bM4_CAN_EALCAP_ALC0 (*((volatile unsigned int*)(0x42E09600UL))) +#define bM4_CAN_EALCAP_ALC1 (*((volatile unsigned int*)(0x42E09604UL))) +#define bM4_CAN_EALCAP_ALC2 (*((volatile unsigned int*)(0x42E09608UL))) +#define bM4_CAN_EALCAP_ALC3 (*((volatile unsigned int*)(0x42E0960CUL))) +#define bM4_CAN_EALCAP_ALC4 (*((volatile unsigned int*)(0x42E09610UL))) +#define bM4_CAN_EALCAP_KOER0 (*((volatile unsigned int*)(0x42E09614UL))) +#define bM4_CAN_EALCAP_KOER1 (*((volatile unsigned int*)(0x42E09618UL))) +#define bM4_CAN_EALCAP_KOER2 (*((volatile unsigned int*)(0x42E0961CUL))) +#define bM4_CAN_ACFCTRL_ACFADR0 (*((volatile unsigned int*)(0x42E09680UL))) +#define bM4_CAN_ACFCTRL_ACFADR1 (*((volatile unsigned int*)(0x42E09684UL))) +#define bM4_CAN_ACFCTRL_ACFADR2 (*((volatile unsigned int*)(0x42E09688UL))) +#define bM4_CAN_ACFCTRL_ACFADR3 (*((volatile unsigned int*)(0x42E0968CUL))) +#define bM4_CAN_ACFCTRL_SELMASK (*((volatile unsigned int*)(0x42E09694UL))) +#define bM4_CAN_ACFEN_AE_1 (*((volatile unsigned int*)(0x42E096C0UL))) +#define bM4_CAN_ACFEN_AE_2 (*((volatile unsigned int*)(0x42E096C4UL))) +#define bM4_CAN_ACFEN_AE_3 (*((volatile unsigned int*)(0x42E096C8UL))) +#define bM4_CAN_ACFEN_AE_4 (*((volatile unsigned int*)(0x42E096CCUL))) +#define bM4_CAN_ACFEN_AE_5 (*((volatile unsigned int*)(0x42E096D0UL))) +#define bM4_CAN_ACFEN_AE_6 (*((volatile unsigned int*)(0x42E096D4UL))) +#define bM4_CAN_ACFEN_AE_7 (*((volatile unsigned int*)(0x42E096D8UL))) +#define bM4_CAN_ACFEN_AE_8 (*((volatile unsigned int*)(0x42E096DCUL))) +#define bM4_CAN_ACF_ACODEORAMASK0 (*((volatile unsigned int*)(0x42E09700UL))) +#define bM4_CAN_ACF_ACODEORAMASK1 (*((volatile unsigned int*)(0x42E09704UL))) +#define bM4_CAN_ACF_ACODEORAMASK2 (*((volatile unsigned int*)(0x42E09708UL))) +#define bM4_CAN_ACF_ACODEORAMASK3 (*((volatile unsigned int*)(0x42E0970CUL))) +#define bM4_CAN_ACF_ACODEORAMASK4 (*((volatile unsigned int*)(0x42E09710UL))) +#define bM4_CAN_ACF_ACODEORAMASK5 (*((volatile unsigned int*)(0x42E09714UL))) +#define bM4_CAN_ACF_ACODEORAMASK6 (*((volatile unsigned int*)(0x42E09718UL))) +#define bM4_CAN_ACF_ACODEORAMASK7 (*((volatile unsigned int*)(0x42E0971CUL))) +#define bM4_CAN_ACF_ACODEORAMASK8 (*((volatile unsigned int*)(0x42E09720UL))) +#define bM4_CAN_ACF_ACODEORAMASK9 (*((volatile unsigned int*)(0x42E09724UL))) +#define bM4_CAN_ACF_ACODEORAMASK10 (*((volatile unsigned int*)(0x42E09728UL))) +#define bM4_CAN_ACF_ACODEORAMASK11 (*((volatile unsigned int*)(0x42E0972CUL))) +#define bM4_CAN_ACF_ACODEORAMASK12 (*((volatile unsigned int*)(0x42E09730UL))) +#define bM4_CAN_ACF_ACODEORAMASK13 (*((volatile unsigned int*)(0x42E09734UL))) +#define bM4_CAN_ACF_ACODEORAMASK14 (*((volatile unsigned int*)(0x42E09738UL))) +#define bM4_CAN_ACF_ACODEORAMASK15 (*((volatile unsigned int*)(0x42E0973CUL))) +#define bM4_CAN_ACF_ACODEORAMASK16 (*((volatile unsigned int*)(0x42E09740UL))) +#define bM4_CAN_ACF_ACODEORAMASK17 (*((volatile unsigned int*)(0x42E09744UL))) +#define bM4_CAN_ACF_ACODEORAMASK18 (*((volatile unsigned int*)(0x42E09748UL))) +#define bM4_CAN_ACF_ACODEORAMASK19 (*((volatile unsigned int*)(0x42E0974CUL))) +#define bM4_CAN_ACF_ACODEORAMASK20 (*((volatile unsigned int*)(0x42E09750UL))) +#define bM4_CAN_ACF_ACODEORAMASK21 (*((volatile unsigned int*)(0x42E09754UL))) +#define bM4_CAN_ACF_ACODEORAMASK22 (*((volatile unsigned int*)(0x42E09758UL))) +#define bM4_CAN_ACF_ACODEORAMASK23 (*((volatile unsigned int*)(0x42E0975CUL))) +#define bM4_CAN_ACF_ACODEORAMASK24 (*((volatile unsigned int*)(0x42E09760UL))) +#define bM4_CAN_ACF_ACODEORAMASK25 (*((volatile unsigned int*)(0x42E09764UL))) +#define bM4_CAN_ACF_ACODEORAMASK26 (*((volatile unsigned int*)(0x42E09768UL))) +#define bM4_CAN_ACF_ACODEORAMASK27 (*((volatile unsigned int*)(0x42E0976CUL))) +#define bM4_CAN_ACF_ACODEORAMASK28 (*((volatile unsigned int*)(0x42E09770UL))) +#define bM4_CAN_ACF_AIDE (*((volatile unsigned int*)(0x42E09774UL))) +#define bM4_CAN_ACF_AIDEE (*((volatile unsigned int*)(0x42E09778UL))) +#define bM4_CAN_TBSLOT_TBPTR0 (*((volatile unsigned int*)(0x42E097C0UL))) +#define bM4_CAN_TBSLOT_TBPTR1 (*((volatile unsigned int*)(0x42E097C4UL))) +#define bM4_CAN_TBSLOT_TBPTR2 (*((volatile unsigned int*)(0x42E097C8UL))) +#define bM4_CAN_TBSLOT_TBPTR3 (*((volatile unsigned int*)(0x42E097CCUL))) +#define bM4_CAN_TBSLOT_TBPTR4 (*((volatile unsigned int*)(0x42E097D0UL))) +#define bM4_CAN_TBSLOT_TBPTR5 (*((volatile unsigned int*)(0x42E097D4UL))) +#define bM4_CAN_TBSLOT_TBF (*((volatile unsigned int*)(0x42E097D8UL))) +#define bM4_CAN_TBSLOT_TBE (*((volatile unsigned int*)(0x42E097DCUL))) +#define bM4_CAN_TTCFG_TTEN (*((volatile unsigned int*)(0x42E097E0UL))) +#define bM4_CAN_TTCFG_T_PRESC0 (*((volatile unsigned int*)(0x42E097E4UL))) +#define bM4_CAN_TTCFG_T_PRESC1 (*((volatile unsigned int*)(0x42E097E8UL))) +#define bM4_CAN_TTCFG_TTIF (*((volatile unsigned int*)(0x42E097ECUL))) +#define bM4_CAN_TTCFG_TTIE (*((volatile unsigned int*)(0x42E097F0UL))) +#define bM4_CAN_TTCFG_TEIF (*((volatile unsigned int*)(0x42E097F4UL))) +#define bM4_CAN_TTCFG_WTIF (*((volatile unsigned int*)(0x42E097F8UL))) +#define bM4_CAN_TTCFG_WTIE (*((volatile unsigned int*)(0x42E097FCUL))) +#define bM4_CAN_REF_MSG_REF_ID0 (*((volatile unsigned int*)(0x42E09800UL))) +#define bM4_CAN_REF_MSG_REF_ID1 (*((volatile unsigned int*)(0x42E09804UL))) +#define bM4_CAN_REF_MSG_REF_ID2 (*((volatile unsigned int*)(0x42E09808UL))) +#define bM4_CAN_REF_MSG_REF_ID3 (*((volatile unsigned int*)(0x42E0980CUL))) +#define bM4_CAN_REF_MSG_REF_ID4 (*((volatile unsigned int*)(0x42E09810UL))) +#define bM4_CAN_REF_MSG_REF_ID5 (*((volatile unsigned int*)(0x42E09814UL))) +#define bM4_CAN_REF_MSG_REF_ID6 (*((volatile unsigned int*)(0x42E09818UL))) +#define bM4_CAN_REF_MSG_REF_ID7 (*((volatile unsigned int*)(0x42E0981CUL))) +#define bM4_CAN_REF_MSG_REF_ID8 (*((volatile unsigned int*)(0x42E09820UL))) +#define bM4_CAN_REF_MSG_REF_ID9 (*((volatile unsigned int*)(0x42E09824UL))) +#define bM4_CAN_REF_MSG_REF_ID10 (*((volatile unsigned int*)(0x42E09828UL))) +#define bM4_CAN_REF_MSG_REF_ID11 (*((volatile unsigned int*)(0x42E0982CUL))) +#define bM4_CAN_REF_MSG_REF_ID12 (*((volatile unsigned int*)(0x42E09830UL))) +#define bM4_CAN_REF_MSG_REF_ID13 (*((volatile unsigned int*)(0x42E09834UL))) +#define bM4_CAN_REF_MSG_REF_ID14 (*((volatile unsigned int*)(0x42E09838UL))) +#define bM4_CAN_REF_MSG_REF_ID15 (*((volatile unsigned int*)(0x42E0983CUL))) +#define bM4_CAN_REF_MSG_REF_ID16 (*((volatile unsigned int*)(0x42E09840UL))) +#define bM4_CAN_REF_MSG_REF_ID17 (*((volatile unsigned int*)(0x42E09844UL))) +#define bM4_CAN_REF_MSG_REF_ID18 (*((volatile unsigned int*)(0x42E09848UL))) +#define bM4_CAN_REF_MSG_REF_ID19 (*((volatile unsigned int*)(0x42E0984CUL))) +#define bM4_CAN_REF_MSG_REF_ID20 (*((volatile unsigned int*)(0x42E09850UL))) +#define bM4_CAN_REF_MSG_REF_ID21 (*((volatile unsigned int*)(0x42E09854UL))) +#define bM4_CAN_REF_MSG_REF_ID22 (*((volatile unsigned int*)(0x42E09858UL))) +#define bM4_CAN_REF_MSG_REF_ID23 (*((volatile unsigned int*)(0x42E0985CUL))) +#define bM4_CAN_REF_MSG_REF_ID24 (*((volatile unsigned int*)(0x42E09860UL))) +#define bM4_CAN_REF_MSG_REF_ID25 (*((volatile unsigned int*)(0x42E09864UL))) +#define bM4_CAN_REF_MSG_REF_ID26 (*((volatile unsigned int*)(0x42E09868UL))) +#define bM4_CAN_REF_MSG_REF_ID27 (*((volatile unsigned int*)(0x42E0986CUL))) +#define bM4_CAN_REF_MSG_REF_ID28 (*((volatile unsigned int*)(0x42E09870UL))) +#define bM4_CAN_REF_MSG_REF_IDE (*((volatile unsigned int*)(0x42E0987CUL))) +#define bM4_CAN_TRG_CFG_TTPTR0 (*((volatile unsigned int*)(0x42E09880UL))) +#define bM4_CAN_TRG_CFG_TTPTR1 (*((volatile unsigned int*)(0x42E09884UL))) +#define bM4_CAN_TRG_CFG_TTPTR2 (*((volatile unsigned int*)(0x42E09888UL))) +#define bM4_CAN_TRG_CFG_TTPTR3 (*((volatile unsigned int*)(0x42E0988CUL))) +#define bM4_CAN_TRG_CFG_TTPTR4 (*((volatile unsigned int*)(0x42E09890UL))) +#define bM4_CAN_TRG_CFG_TTPTR5 (*((volatile unsigned int*)(0x42E09894UL))) +#define bM4_CAN_TRG_CFG_TTYPE0 (*((volatile unsigned int*)(0x42E098A0UL))) +#define bM4_CAN_TRG_CFG_TTYPE1 (*((volatile unsigned int*)(0x42E098A4UL))) +#define bM4_CAN_TRG_CFG_TTYPE2 (*((volatile unsigned int*)(0x42E098A8UL))) +#define bM4_CAN_TRG_CFG_TEW0 (*((volatile unsigned int*)(0x42E098B0UL))) +#define bM4_CAN_TRG_CFG_TEW1 (*((volatile unsigned int*)(0x42E098B4UL))) +#define bM4_CAN_TRG_CFG_TEW2 (*((volatile unsigned int*)(0x42E098B8UL))) +#define bM4_CAN_TRG_CFG_TEW3 (*((volatile unsigned int*)(0x42E098BCUL))) +#define bM4_CMP1_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940000UL))) +#define bM4_CMP1_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940004UL))) +#define bM4_CMP1_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940008UL))) +#define bM4_CMP1_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940014UL))) +#define bM4_CMP1_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940018UL))) +#define bM4_CMP1_CTRL_IEN (*((volatile unsigned int*)(0x4294001CUL))) +#define bM4_CMP1_CTRL_CVSEN (*((volatile unsigned int*)(0x42940020UL))) +#define bM4_CMP1_CTRL_OUTEN (*((volatile unsigned int*)(0x42940030UL))) +#define bM4_CMP1_CTRL_INV (*((volatile unsigned int*)(0x42940034UL))) +#define bM4_CMP1_CTRL_CMPOE (*((volatile unsigned int*)(0x42940038UL))) +#define bM4_CMP1_CTRL_CMPON (*((volatile unsigned int*)(0x4294003CUL))) +#define bM4_CMP1_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940040UL))) +#define bM4_CMP1_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940044UL))) +#define bM4_CMP1_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940048UL))) +#define bM4_CMP1_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294004CUL))) +#define bM4_CMP1_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940060UL))) +#define bM4_CMP1_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940064UL))) +#define bM4_CMP1_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940068UL))) +#define bM4_CMP1_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294006CUL))) +#define bM4_CMP1_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940070UL))) +#define bM4_CMP1_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940074UL))) +#define bM4_CMP1_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940078UL))) +#define bM4_CMP1_MON_OMON (*((volatile unsigned int*)(0x42940080UL))) +#define bM4_CMP1_MON_CVST0 (*((volatile unsigned int*)(0x429400A0UL))) +#define bM4_CMP1_MON_CVST1 (*((volatile unsigned int*)(0x429400A4UL))) +#define bM4_CMP1_MON_CVST2 (*((volatile unsigned int*)(0x429400A8UL))) +#define bM4_CMP1_MON_CVST3 (*((volatile unsigned int*)(0x429400ACUL))) +#define bM4_CMP1_CVSSTB_STB0 (*((volatile unsigned int*)(0x429400C0UL))) +#define bM4_CMP1_CVSSTB_STB1 (*((volatile unsigned int*)(0x429400C4UL))) +#define bM4_CMP1_CVSSTB_STB2 (*((volatile unsigned int*)(0x429400C8UL))) +#define bM4_CMP1_CVSSTB_STB3 (*((volatile unsigned int*)(0x429400CCUL))) +#define bM4_CMP1_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940100UL))) +#define bM4_CMP1_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940104UL))) +#define bM4_CMP1_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940108UL))) +#define bM4_CMP1_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294010CUL))) +#define bM4_CMP1_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940110UL))) +#define bM4_CMP1_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940114UL))) +#define bM4_CMP1_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940118UL))) +#define bM4_CMP1_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294011CUL))) +#define bM4_CMP2_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940200UL))) +#define bM4_CMP2_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940204UL))) +#define bM4_CMP2_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940208UL))) +#define bM4_CMP2_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940214UL))) +#define bM4_CMP2_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940218UL))) +#define bM4_CMP2_CTRL_IEN (*((volatile unsigned int*)(0x4294021CUL))) +#define bM4_CMP2_CTRL_CVSEN (*((volatile unsigned int*)(0x42940220UL))) +#define bM4_CMP2_CTRL_OUTEN (*((volatile unsigned int*)(0x42940230UL))) +#define bM4_CMP2_CTRL_INV (*((volatile unsigned int*)(0x42940234UL))) +#define bM4_CMP2_CTRL_CMPOE (*((volatile unsigned int*)(0x42940238UL))) +#define bM4_CMP2_CTRL_CMPON (*((volatile unsigned int*)(0x4294023CUL))) +#define bM4_CMP2_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940240UL))) +#define bM4_CMP2_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940244UL))) +#define bM4_CMP2_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940248UL))) +#define bM4_CMP2_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294024CUL))) +#define bM4_CMP2_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940260UL))) +#define bM4_CMP2_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940264UL))) +#define bM4_CMP2_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940268UL))) +#define bM4_CMP2_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294026CUL))) +#define bM4_CMP2_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940270UL))) +#define bM4_CMP2_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940274UL))) +#define bM4_CMP2_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940278UL))) +#define bM4_CMP2_MON_OMON (*((volatile unsigned int*)(0x42940280UL))) +#define bM4_CMP2_MON_CVST0 (*((volatile unsigned int*)(0x429402A0UL))) +#define bM4_CMP2_MON_CVST1 (*((volatile unsigned int*)(0x429402A4UL))) +#define bM4_CMP2_MON_CVST2 (*((volatile unsigned int*)(0x429402A8UL))) +#define bM4_CMP2_MON_CVST3 (*((volatile unsigned int*)(0x429402ACUL))) +#define bM4_CMP2_CVSSTB_STB0 (*((volatile unsigned int*)(0x429402C0UL))) +#define bM4_CMP2_CVSSTB_STB1 (*((volatile unsigned int*)(0x429402C4UL))) +#define bM4_CMP2_CVSSTB_STB2 (*((volatile unsigned int*)(0x429402C8UL))) +#define bM4_CMP2_CVSSTB_STB3 (*((volatile unsigned int*)(0x429402CCUL))) +#define bM4_CMP2_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940300UL))) +#define bM4_CMP2_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940304UL))) +#define bM4_CMP2_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940308UL))) +#define bM4_CMP2_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294030CUL))) +#define bM4_CMP2_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940310UL))) +#define bM4_CMP2_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940314UL))) +#define bM4_CMP2_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940318UL))) +#define bM4_CMP2_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294031CUL))) +#define bM4_CMP3_CTRL_FLTSL0 (*((volatile unsigned int*)(0x42940400UL))) +#define bM4_CMP3_CTRL_FLTSL1 (*((volatile unsigned int*)(0x42940404UL))) +#define bM4_CMP3_CTRL_FLTSL2 (*((volatile unsigned int*)(0x42940408UL))) +#define bM4_CMP3_CTRL_EDGSL0 (*((volatile unsigned int*)(0x42940414UL))) +#define bM4_CMP3_CTRL_EDGSL1 (*((volatile unsigned int*)(0x42940418UL))) +#define bM4_CMP3_CTRL_IEN (*((volatile unsigned int*)(0x4294041CUL))) +#define bM4_CMP3_CTRL_CVSEN (*((volatile unsigned int*)(0x42940420UL))) +#define bM4_CMP3_CTRL_OUTEN (*((volatile unsigned int*)(0x42940430UL))) +#define bM4_CMP3_CTRL_INV (*((volatile unsigned int*)(0x42940434UL))) +#define bM4_CMP3_CTRL_CMPOE (*((volatile unsigned int*)(0x42940438UL))) +#define bM4_CMP3_CTRL_CMPON (*((volatile unsigned int*)(0x4294043CUL))) +#define bM4_CMP3_VLTSEL_RVSL0 (*((volatile unsigned int*)(0x42940440UL))) +#define bM4_CMP3_VLTSEL_RVSL1 (*((volatile unsigned int*)(0x42940444UL))) +#define bM4_CMP3_VLTSEL_RVSL2 (*((volatile unsigned int*)(0x42940448UL))) +#define bM4_CMP3_VLTSEL_RVSL3 (*((volatile unsigned int*)(0x4294044CUL))) +#define bM4_CMP3_VLTSEL_CVSL0 (*((volatile unsigned int*)(0x42940460UL))) +#define bM4_CMP3_VLTSEL_CVSL1 (*((volatile unsigned int*)(0x42940464UL))) +#define bM4_CMP3_VLTSEL_CVSL2 (*((volatile unsigned int*)(0x42940468UL))) +#define bM4_CMP3_VLTSEL_CVSL3 (*((volatile unsigned int*)(0x4294046CUL))) +#define bM4_CMP3_VLTSEL_C4SL0 (*((volatile unsigned int*)(0x42940470UL))) +#define bM4_CMP3_VLTSEL_C4SL1 (*((volatile unsigned int*)(0x42940474UL))) +#define bM4_CMP3_VLTSEL_C4SL2 (*((volatile unsigned int*)(0x42940478UL))) +#define bM4_CMP3_MON_OMON (*((volatile unsigned int*)(0x42940480UL))) +#define bM4_CMP3_MON_CVST0 (*((volatile unsigned int*)(0x429404A0UL))) +#define bM4_CMP3_MON_CVST1 (*((volatile unsigned int*)(0x429404A4UL))) +#define bM4_CMP3_MON_CVST2 (*((volatile unsigned int*)(0x429404A8UL))) +#define bM4_CMP3_MON_CVST3 (*((volatile unsigned int*)(0x429404ACUL))) +#define bM4_CMP3_CVSSTB_STB0 (*((volatile unsigned int*)(0x429404C0UL))) +#define bM4_CMP3_CVSSTB_STB1 (*((volatile unsigned int*)(0x429404C4UL))) +#define bM4_CMP3_CVSSTB_STB2 (*((volatile unsigned int*)(0x429404C8UL))) +#define bM4_CMP3_CVSSTB_STB3 (*((volatile unsigned int*)(0x429404CCUL))) +#define bM4_CMP3_CVSPRD_PRD0 (*((volatile unsigned int*)(0x42940500UL))) +#define bM4_CMP3_CVSPRD_PRD1 (*((volatile unsigned int*)(0x42940504UL))) +#define bM4_CMP3_CVSPRD_PRD2 (*((volatile unsigned int*)(0x42940508UL))) +#define bM4_CMP3_CVSPRD_PRD3 (*((volatile unsigned int*)(0x4294050CUL))) +#define bM4_CMP3_CVSPRD_PRD4 (*((volatile unsigned int*)(0x42940510UL))) +#define bM4_CMP3_CVSPRD_PRD5 (*((volatile unsigned int*)(0x42940514UL))) +#define bM4_CMP3_CVSPRD_PRD6 (*((volatile unsigned int*)(0x42940518UL))) +#define bM4_CMP3_CVSPRD_PRD7 (*((volatile unsigned int*)(0x4294051CUL))) +#define bM4_CMP_CR_DADR1_DATA0 (*((volatile unsigned int*)(0x42942000UL))) +#define bM4_CMP_CR_DADR1_DATA1 (*((volatile unsigned int*)(0x42942004UL))) +#define bM4_CMP_CR_DADR1_DATA2 (*((volatile unsigned int*)(0x42942008UL))) +#define bM4_CMP_CR_DADR1_DATA3 (*((volatile unsigned int*)(0x4294200CUL))) +#define bM4_CMP_CR_DADR1_DATA4 (*((volatile unsigned int*)(0x42942010UL))) +#define bM4_CMP_CR_DADR1_DATA5 (*((volatile unsigned int*)(0x42942014UL))) +#define bM4_CMP_CR_DADR1_DATA6 (*((volatile unsigned int*)(0x42942018UL))) +#define bM4_CMP_CR_DADR1_DATA7 (*((volatile unsigned int*)(0x4294201CUL))) +#define bM4_CMP_CR_DADR2_DATA0 (*((volatile unsigned int*)(0x42942040UL))) +#define bM4_CMP_CR_DADR2_DATA1 (*((volatile unsigned int*)(0x42942044UL))) +#define bM4_CMP_CR_DADR2_DATA2 (*((volatile unsigned int*)(0x42942048UL))) +#define bM4_CMP_CR_DADR2_DATA3 (*((volatile unsigned int*)(0x4294204CUL))) +#define bM4_CMP_CR_DADR2_DATA4 (*((volatile unsigned int*)(0x42942050UL))) +#define bM4_CMP_CR_DADR2_DATA5 (*((volatile unsigned int*)(0x42942054UL))) +#define bM4_CMP_CR_DADR2_DATA6 (*((volatile unsigned int*)(0x42942058UL))) +#define bM4_CMP_CR_DADR2_DATA7 (*((volatile unsigned int*)(0x4294205CUL))) +#define bM4_CMP_CR_DACR_DA1EN (*((volatile unsigned int*)(0x42942100UL))) +#define bM4_CMP_CR_DACR_DA2EN (*((volatile unsigned int*)(0x42942104UL))) +#define bM4_CMP_CR_RVADC_DA1SW (*((volatile unsigned int*)(0x42942180UL))) +#define bM4_CMP_CR_RVADC_DA2SW (*((volatile unsigned int*)(0x42942184UL))) +#define bM4_CMP_CR_RVADC_VREFSW (*((volatile unsigned int*)(0x42942190UL))) +#define bM4_CMP_CR_RVADC_WPRT0 (*((volatile unsigned int*)(0x429421A0UL))) +#define bM4_CMP_CR_RVADC_WPRT1 (*((volatile unsigned int*)(0x429421A4UL))) +#define bM4_CMP_CR_RVADC_WPRT2 (*((volatile unsigned int*)(0x429421A8UL))) +#define bM4_CMP_CR_RVADC_WPRT3 (*((volatile unsigned int*)(0x429421ACUL))) +#define bM4_CMP_CR_RVADC_WPRT4 (*((volatile unsigned int*)(0x429421B0UL))) +#define bM4_CMP_CR_RVADC_WPRT5 (*((volatile unsigned int*)(0x429421B4UL))) +#define bM4_CMP_CR_RVADC_WPRT6 (*((volatile unsigned int*)(0x429421B8UL))) +#define bM4_CMP_CR_RVADC_WPRT7 (*((volatile unsigned int*)(0x429421BCUL))) +#define bM4_CRC_CR_CRC_SEL (*((volatile unsigned int*)(0x42118004UL))) +#define bM4_CRC_CR_REFIN (*((volatile unsigned int*)(0x42118008UL))) +#define bM4_CRC_CR_REFOUT (*((volatile unsigned int*)(0x4211800CUL))) +#define bM4_CRC_CR_XOROUT (*((volatile unsigned int*)(0x42118010UL))) +#define bM4_CRC_FLG_FLAG (*((volatile unsigned int*)(0x42118180UL))) +#define bM4_DCU1_CTL_MODE0 (*((volatile unsigned int*)(0x42A40000UL))) +#define bM4_DCU1_CTL_MODE1 (*((volatile unsigned int*)(0x42A40004UL))) +#define bM4_DCU1_CTL_MODE2 (*((volatile unsigned int*)(0x42A40008UL))) +#define bM4_DCU1_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A4000CUL))) +#define bM4_DCU1_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A40010UL))) +#define bM4_DCU1_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A40020UL))) +#define bM4_DCU1_CTL_INTEN (*((volatile unsigned int*)(0x42A4007CUL))) +#define bM4_DCU1_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A40080UL))) +#define bM4_DCU1_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A40084UL))) +#define bM4_DCU1_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A40088UL))) +#define bM4_DCU1_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A4008CUL))) +#define bM4_DCU1_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A40090UL))) +#define bM4_DCU1_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A40094UL))) +#define bM4_DCU1_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A40098UL))) +#define bM4_DCU1_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A40280UL))) +#define bM4_DCU1_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A40284UL))) +#define bM4_DCU1_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A40288UL))) +#define bM4_DCU1_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A4028CUL))) +#define bM4_DCU1_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A40290UL))) +#define bM4_DCU1_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A40294UL))) +#define bM4_DCU1_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A40298UL))) +#define bM4_DCU1_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A40300UL))) +#define bM4_DCU1_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A40304UL))) +#define bM4_DCU1_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A40308UL))) +#define bM4_DCU1_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A4030CUL))) +#define bM4_DCU1_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A40310UL))) +#define bM4_DCU1_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A40314UL))) +#define bM4_DCU1_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A40318UL))) +#define bM4_DCU1_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A4031CUL))) +#define bM4_DCU1_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A40320UL))) +#define bM4_DCU2_CTL_MODE0 (*((volatile unsigned int*)(0x42A48000UL))) +#define bM4_DCU2_CTL_MODE1 (*((volatile unsigned int*)(0x42A48004UL))) +#define bM4_DCU2_CTL_MODE2 (*((volatile unsigned int*)(0x42A48008UL))) +#define bM4_DCU2_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A4800CUL))) +#define bM4_DCU2_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A48010UL))) +#define bM4_DCU2_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A48020UL))) +#define bM4_DCU2_CTL_INTEN (*((volatile unsigned int*)(0x42A4807CUL))) +#define bM4_DCU2_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A48080UL))) +#define bM4_DCU2_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A48084UL))) +#define bM4_DCU2_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A48088UL))) +#define bM4_DCU2_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A4808CUL))) +#define bM4_DCU2_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A48090UL))) +#define bM4_DCU2_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A48094UL))) +#define bM4_DCU2_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A48098UL))) +#define bM4_DCU2_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A48280UL))) +#define bM4_DCU2_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A48284UL))) +#define bM4_DCU2_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A48288UL))) +#define bM4_DCU2_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A4828CUL))) +#define bM4_DCU2_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A48290UL))) +#define bM4_DCU2_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A48294UL))) +#define bM4_DCU2_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A48298UL))) +#define bM4_DCU2_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A48300UL))) +#define bM4_DCU2_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A48304UL))) +#define bM4_DCU2_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A48308UL))) +#define bM4_DCU2_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A4830CUL))) +#define bM4_DCU2_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A48310UL))) +#define bM4_DCU2_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A48314UL))) +#define bM4_DCU2_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A48318UL))) +#define bM4_DCU2_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A4831CUL))) +#define bM4_DCU2_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A48320UL))) +#define bM4_DCU3_CTL_MODE0 (*((volatile unsigned int*)(0x42A50000UL))) +#define bM4_DCU3_CTL_MODE1 (*((volatile unsigned int*)(0x42A50004UL))) +#define bM4_DCU3_CTL_MODE2 (*((volatile unsigned int*)(0x42A50008UL))) +#define bM4_DCU3_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A5000CUL))) +#define bM4_DCU3_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A50010UL))) +#define bM4_DCU3_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A50020UL))) +#define bM4_DCU3_CTL_INTEN (*((volatile unsigned int*)(0x42A5007CUL))) +#define bM4_DCU3_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A50080UL))) +#define bM4_DCU3_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A50084UL))) +#define bM4_DCU3_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A50088UL))) +#define bM4_DCU3_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A5008CUL))) +#define bM4_DCU3_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A50090UL))) +#define bM4_DCU3_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A50094UL))) +#define bM4_DCU3_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A50098UL))) +#define bM4_DCU3_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A50280UL))) +#define bM4_DCU3_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A50284UL))) +#define bM4_DCU3_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A50288UL))) +#define bM4_DCU3_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A5028CUL))) +#define bM4_DCU3_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A50290UL))) +#define bM4_DCU3_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A50294UL))) +#define bM4_DCU3_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A50298UL))) +#define bM4_DCU3_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A50300UL))) +#define bM4_DCU3_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A50304UL))) +#define bM4_DCU3_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A50308UL))) +#define bM4_DCU3_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A5030CUL))) +#define bM4_DCU3_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A50310UL))) +#define bM4_DCU3_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A50314UL))) +#define bM4_DCU3_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A50318UL))) +#define bM4_DCU3_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A5031CUL))) +#define bM4_DCU3_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A50320UL))) +#define bM4_DCU4_CTL_MODE0 (*((volatile unsigned int*)(0x42A58000UL))) +#define bM4_DCU4_CTL_MODE1 (*((volatile unsigned int*)(0x42A58004UL))) +#define bM4_DCU4_CTL_MODE2 (*((volatile unsigned int*)(0x42A58008UL))) +#define bM4_DCU4_CTL_DATASIZE0 (*((volatile unsigned int*)(0x42A5800CUL))) +#define bM4_DCU4_CTL_DATASIZE1 (*((volatile unsigned int*)(0x42A58010UL))) +#define bM4_DCU4_CTL_COMP_TRG (*((volatile unsigned int*)(0x42A58020UL))) +#define bM4_DCU4_CTL_INTEN (*((volatile unsigned int*)(0x42A5807CUL))) +#define bM4_DCU4_FLAG_FLAG_OP (*((volatile unsigned int*)(0x42A58080UL))) +#define bM4_DCU4_FLAG_FLAG_LS2 (*((volatile unsigned int*)(0x42A58084UL))) +#define bM4_DCU4_FLAG_FLAG_EQ2 (*((volatile unsigned int*)(0x42A58088UL))) +#define bM4_DCU4_FLAG_FLAG_GT2 (*((volatile unsigned int*)(0x42A5808CUL))) +#define bM4_DCU4_FLAG_FLAG_LS1 (*((volatile unsigned int*)(0x42A58090UL))) +#define bM4_DCU4_FLAG_FLAG_EQ1 (*((volatile unsigned int*)(0x42A58094UL))) +#define bM4_DCU4_FLAG_FLAG_GT1 (*((volatile unsigned int*)(0x42A58098UL))) +#define bM4_DCU4_FLAGCLR_CLR_OP (*((volatile unsigned int*)(0x42A58280UL))) +#define bM4_DCU4_FLAGCLR_CLR_LS2 (*((volatile unsigned int*)(0x42A58284UL))) +#define bM4_DCU4_FLAGCLR_CLR_EQ2 (*((volatile unsigned int*)(0x42A58288UL))) +#define bM4_DCU4_FLAGCLR_CLR_GT2 (*((volatile unsigned int*)(0x42A5828CUL))) +#define bM4_DCU4_FLAGCLR_CLR_LS1 (*((volatile unsigned int*)(0x42A58290UL))) +#define bM4_DCU4_FLAGCLR_CLR_EQ1 (*((volatile unsigned int*)(0x42A58294UL))) +#define bM4_DCU4_FLAGCLR_CLR_GT1 (*((volatile unsigned int*)(0x42A58298UL))) +#define bM4_DCU4_INTSEL_INT_OP (*((volatile unsigned int*)(0x42A58300UL))) +#define bM4_DCU4_INTSEL_INT_LS2 (*((volatile unsigned int*)(0x42A58304UL))) +#define bM4_DCU4_INTSEL_INT_EQ2 (*((volatile unsigned int*)(0x42A58308UL))) +#define bM4_DCU4_INTSEL_INT_GT2 (*((volatile unsigned int*)(0x42A5830CUL))) +#define bM4_DCU4_INTSEL_INT_LS1 (*((volatile unsigned int*)(0x42A58310UL))) +#define bM4_DCU4_INTSEL_INT_EQ1 (*((volatile unsigned int*)(0x42A58314UL))) +#define bM4_DCU4_INTSEL_INT_GT1 (*((volatile unsigned int*)(0x42A58318UL))) +#define bM4_DCU4_INTSEL_INT_WIN0 (*((volatile unsigned int*)(0x42A5831CUL))) +#define bM4_DCU4_INTSEL_INT_WIN1 (*((volatile unsigned int*)(0x42A58320UL))) +#define bM4_DMA1_EN_EN (*((volatile unsigned int*)(0x42A60000UL))) +#define bM4_DMA1_INTSTAT0_TRNERR0 (*((volatile unsigned int*)(0x42A60080UL))) +#define bM4_DMA1_INTSTAT0_TRNERR1 (*((volatile unsigned int*)(0x42A60084UL))) +#define bM4_DMA1_INTSTAT0_TRNERR2 (*((volatile unsigned int*)(0x42A60088UL))) +#define bM4_DMA1_INTSTAT0_TRNERR3 (*((volatile unsigned int*)(0x42A6008CUL))) +#define bM4_DMA1_INTSTAT0_REQERR0 (*((volatile unsigned int*)(0x42A600C0UL))) +#define bM4_DMA1_INTSTAT0_REQERR1 (*((volatile unsigned int*)(0x42A600C4UL))) +#define bM4_DMA1_INTSTAT0_REQERR2 (*((volatile unsigned int*)(0x42A600C8UL))) +#define bM4_DMA1_INTSTAT0_REQERR3 (*((volatile unsigned int*)(0x42A600CCUL))) +#define bM4_DMA1_INTSTAT1_TC0 (*((volatile unsigned int*)(0x42A60100UL))) +#define bM4_DMA1_INTSTAT1_TC1 (*((volatile unsigned int*)(0x42A60104UL))) +#define bM4_DMA1_INTSTAT1_TC2 (*((volatile unsigned int*)(0x42A60108UL))) +#define bM4_DMA1_INTSTAT1_TC3 (*((volatile unsigned int*)(0x42A6010CUL))) +#define bM4_DMA1_INTSTAT1_BTC0 (*((volatile unsigned int*)(0x42A60140UL))) +#define bM4_DMA1_INTSTAT1_BTC1 (*((volatile unsigned int*)(0x42A60144UL))) +#define bM4_DMA1_INTSTAT1_BTC2 (*((volatile unsigned int*)(0x42A60148UL))) +#define bM4_DMA1_INTSTAT1_BTC3 (*((volatile unsigned int*)(0x42A6014CUL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR0 (*((volatile unsigned int*)(0x42A60180UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR1 (*((volatile unsigned int*)(0x42A60184UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR2 (*((volatile unsigned int*)(0x42A60188UL))) +#define bM4_DMA1_INTMASK0_MSKTRNERR3 (*((volatile unsigned int*)(0x42A6018CUL))) +#define bM4_DMA1_INTMASK0_MSKREQERR0 (*((volatile unsigned int*)(0x42A601C0UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR1 (*((volatile unsigned int*)(0x42A601C4UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR2 (*((volatile unsigned int*)(0x42A601C8UL))) +#define bM4_DMA1_INTMASK0_MSKREQERR3 (*((volatile unsigned int*)(0x42A601CCUL))) +#define bM4_DMA1_INTMASK1_MSKTC0 (*((volatile unsigned int*)(0x42A60200UL))) +#define bM4_DMA1_INTMASK1_MSKTC1 (*((volatile unsigned int*)(0x42A60204UL))) +#define bM4_DMA1_INTMASK1_MSKTC2 (*((volatile unsigned int*)(0x42A60208UL))) +#define bM4_DMA1_INTMASK1_MSKTC3 (*((volatile unsigned int*)(0x42A6020CUL))) +#define bM4_DMA1_INTMASK1_MSKBTC0 (*((volatile unsigned int*)(0x42A60240UL))) +#define bM4_DMA1_INTMASK1_MSKBTC1 (*((volatile unsigned int*)(0x42A60244UL))) +#define bM4_DMA1_INTMASK1_MSKBTC2 (*((volatile unsigned int*)(0x42A60248UL))) +#define bM4_DMA1_INTMASK1_MSKBTC3 (*((volatile unsigned int*)(0x42A6024CUL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR0 (*((volatile unsigned int*)(0x42A60280UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR1 (*((volatile unsigned int*)(0x42A60284UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR2 (*((volatile unsigned int*)(0x42A60288UL))) +#define bM4_DMA1_INTCLR0_CLRTRNERR3 (*((volatile unsigned int*)(0x42A6028CUL))) +#define bM4_DMA1_INTCLR0_CLRREQERR0 (*((volatile unsigned int*)(0x42A602C0UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR1 (*((volatile unsigned int*)(0x42A602C4UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR2 (*((volatile unsigned int*)(0x42A602C8UL))) +#define bM4_DMA1_INTCLR0_CLRREQERR3 (*((volatile unsigned int*)(0x42A602CCUL))) +#define bM4_DMA1_INTCLR1_CLRTC0 (*((volatile unsigned int*)(0x42A60300UL))) +#define bM4_DMA1_INTCLR1_CLRTC1 (*((volatile unsigned int*)(0x42A60304UL))) +#define bM4_DMA1_INTCLR1_CLRTC2 (*((volatile unsigned int*)(0x42A60308UL))) +#define bM4_DMA1_INTCLR1_CLRTC3 (*((volatile unsigned int*)(0x42A6030CUL))) +#define bM4_DMA1_INTCLR1_CLRBTC0 (*((volatile unsigned int*)(0x42A60340UL))) +#define bM4_DMA1_INTCLR1_CLRBTC1 (*((volatile unsigned int*)(0x42A60344UL))) +#define bM4_DMA1_INTCLR1_CLRBTC2 (*((volatile unsigned int*)(0x42A60348UL))) +#define bM4_DMA1_INTCLR1_CLRBTC3 (*((volatile unsigned int*)(0x42A6034CUL))) +#define bM4_DMA1_CHEN_CHEN0 (*((volatile unsigned int*)(0x42A60380UL))) +#define bM4_DMA1_CHEN_CHEN1 (*((volatile unsigned int*)(0x42A60384UL))) +#define bM4_DMA1_CHEN_CHEN2 (*((volatile unsigned int*)(0x42A60388UL))) +#define bM4_DMA1_CHEN_CHEN3 (*((volatile unsigned int*)(0x42A6038CUL))) +#define bM4_DMA1_CHSTAT_DMAACT (*((volatile unsigned int*)(0x42A60480UL))) +#define bM4_DMA1_CHSTAT_RCFGACT (*((volatile unsigned int*)(0x42A60484UL))) +#define bM4_DMA1_CHSTAT_CHACT0 (*((volatile unsigned int*)(0x42A604C0UL))) +#define bM4_DMA1_CHSTAT_CHACT1 (*((volatile unsigned int*)(0x42A604C4UL))) +#define bM4_DMA1_CHSTAT_CHACT2 (*((volatile unsigned int*)(0x42A604C8UL))) +#define bM4_DMA1_CHSTAT_CHACT3 (*((volatile unsigned int*)(0x42A604CCUL))) +#define bM4_DMA1_RCFGCTL_RCFGEN (*((volatile unsigned int*)(0x42A60580UL))) +#define bM4_DMA1_RCFGCTL_RCFGLLP (*((volatile unsigned int*)(0x42A60584UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS0 (*((volatile unsigned int*)(0x42A605A0UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS1 (*((volatile unsigned int*)(0x42A605A4UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS2 (*((volatile unsigned int*)(0x42A605A8UL))) +#define bM4_DMA1_RCFGCTL_RCFGCHS3 (*((volatile unsigned int*)(0x42A605ACUL))) +#define bM4_DMA1_RCFGCTL_SARMD0 (*((volatile unsigned int*)(0x42A605C0UL))) +#define bM4_DMA1_RCFGCTL_SARMD1 (*((volatile unsigned int*)(0x42A605C4UL))) +#define bM4_DMA1_RCFGCTL_DARMD0 (*((volatile unsigned int*)(0x42A605C8UL))) +#define bM4_DMA1_RCFGCTL_DARMD1 (*((volatile unsigned int*)(0x42A605CCUL))) +#define bM4_DMA1_RCFGCTL_CNTMD0 (*((volatile unsigned int*)(0x42A605D0UL))) +#define bM4_DMA1_RCFGCTL_CNTMD1 (*((volatile unsigned int*)(0x42A605D4UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A60900UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A60904UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A60908UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A6090CUL))) +#define bM4_DMA1_DTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A60910UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A60914UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A60918UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A6091CUL))) +#define bM4_DMA1_DTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A60920UL))) +#define bM4_DMA1_DTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A60924UL))) +#define bM4_DMA1_DTCTL0_CNT0 (*((volatile unsigned int*)(0x42A60940UL))) +#define bM4_DMA1_DTCTL0_CNT1 (*((volatile unsigned int*)(0x42A60944UL))) +#define bM4_DMA1_DTCTL0_CNT2 (*((volatile unsigned int*)(0x42A60948UL))) +#define bM4_DMA1_DTCTL0_CNT3 (*((volatile unsigned int*)(0x42A6094CUL))) +#define bM4_DMA1_DTCTL0_CNT4 (*((volatile unsigned int*)(0x42A60950UL))) +#define bM4_DMA1_DTCTL0_CNT5 (*((volatile unsigned int*)(0x42A60954UL))) +#define bM4_DMA1_DTCTL0_CNT6 (*((volatile unsigned int*)(0x42A60958UL))) +#define bM4_DMA1_DTCTL0_CNT7 (*((volatile unsigned int*)(0x42A6095CUL))) +#define bM4_DMA1_DTCTL0_CNT8 (*((volatile unsigned int*)(0x42A60960UL))) +#define bM4_DMA1_DTCTL0_CNT9 (*((volatile unsigned int*)(0x42A60964UL))) +#define bM4_DMA1_DTCTL0_CNT10 (*((volatile unsigned int*)(0x42A60968UL))) +#define bM4_DMA1_DTCTL0_CNT11 (*((volatile unsigned int*)(0x42A6096CUL))) +#define bM4_DMA1_DTCTL0_CNT12 (*((volatile unsigned int*)(0x42A60970UL))) +#define bM4_DMA1_DTCTL0_CNT13 (*((volatile unsigned int*)(0x42A60974UL))) +#define bM4_DMA1_DTCTL0_CNT14 (*((volatile unsigned int*)(0x42A60978UL))) +#define bM4_DMA1_DTCTL0_CNT15 (*((volatile unsigned int*)(0x42A6097CUL))) +#define bM4_DMA1_RPT0_SRPT0 (*((volatile unsigned int*)(0x42A60980UL))) +#define bM4_DMA1_RPT0_SRPT1 (*((volatile unsigned int*)(0x42A60984UL))) +#define bM4_DMA1_RPT0_SRPT2 (*((volatile unsigned int*)(0x42A60988UL))) +#define bM4_DMA1_RPT0_SRPT3 (*((volatile unsigned int*)(0x42A6098CUL))) +#define bM4_DMA1_RPT0_SRPT4 (*((volatile unsigned int*)(0x42A60990UL))) +#define bM4_DMA1_RPT0_SRPT5 (*((volatile unsigned int*)(0x42A60994UL))) +#define bM4_DMA1_RPT0_SRPT6 (*((volatile unsigned int*)(0x42A60998UL))) +#define bM4_DMA1_RPT0_SRPT7 (*((volatile unsigned int*)(0x42A6099CUL))) +#define bM4_DMA1_RPT0_SRPT8 (*((volatile unsigned int*)(0x42A609A0UL))) +#define bM4_DMA1_RPT0_SRPT9 (*((volatile unsigned int*)(0x42A609A4UL))) +#define bM4_DMA1_RPT0_DRPT0 (*((volatile unsigned int*)(0x42A609C0UL))) +#define bM4_DMA1_RPT0_DRPT1 (*((volatile unsigned int*)(0x42A609C4UL))) +#define bM4_DMA1_RPT0_DRPT2 (*((volatile unsigned int*)(0x42A609C8UL))) +#define bM4_DMA1_RPT0_DRPT3 (*((volatile unsigned int*)(0x42A609CCUL))) +#define bM4_DMA1_RPT0_DRPT4 (*((volatile unsigned int*)(0x42A609D0UL))) +#define bM4_DMA1_RPT0_DRPT5 (*((volatile unsigned int*)(0x42A609D4UL))) +#define bM4_DMA1_RPT0_DRPT6 (*((volatile unsigned int*)(0x42A609D8UL))) +#define bM4_DMA1_RPT0_DRPT7 (*((volatile unsigned int*)(0x42A609DCUL))) +#define bM4_DMA1_RPT0_DRPT8 (*((volatile unsigned int*)(0x42A609E0UL))) +#define bM4_DMA1_RPT0_DRPT9 (*((volatile unsigned int*)(0x42A609E4UL))) +#define bM4_DMA1_RPTB0_SRPTB0 (*((volatile unsigned int*)(0x42A60980UL))) +#define bM4_DMA1_RPTB0_SRPTB1 (*((volatile unsigned int*)(0x42A60984UL))) +#define bM4_DMA1_RPTB0_SRPTB2 (*((volatile unsigned int*)(0x42A60988UL))) +#define bM4_DMA1_RPTB0_SRPTB3 (*((volatile unsigned int*)(0x42A6098CUL))) +#define bM4_DMA1_RPTB0_SRPTB4 (*((volatile unsigned int*)(0x42A60990UL))) +#define bM4_DMA1_RPTB0_SRPTB5 (*((volatile unsigned int*)(0x42A60994UL))) +#define bM4_DMA1_RPTB0_SRPTB6 (*((volatile unsigned int*)(0x42A60998UL))) +#define bM4_DMA1_RPTB0_SRPTB7 (*((volatile unsigned int*)(0x42A6099CUL))) +#define bM4_DMA1_RPTB0_SRPTB8 (*((volatile unsigned int*)(0x42A609A0UL))) +#define bM4_DMA1_RPTB0_SRPTB9 (*((volatile unsigned int*)(0x42A609A4UL))) +#define bM4_DMA1_RPTB0_DRPTB0 (*((volatile unsigned int*)(0x42A609C0UL))) +#define bM4_DMA1_RPTB0_DRPTB1 (*((volatile unsigned int*)(0x42A609C4UL))) +#define bM4_DMA1_RPTB0_DRPTB2 (*((volatile unsigned int*)(0x42A609C8UL))) +#define bM4_DMA1_RPTB0_DRPTB3 (*((volatile unsigned int*)(0x42A609CCUL))) +#define bM4_DMA1_RPTB0_DRPTB4 (*((volatile unsigned int*)(0x42A609D0UL))) +#define bM4_DMA1_RPTB0_DRPTB5 (*((volatile unsigned int*)(0x42A609D4UL))) +#define bM4_DMA1_RPTB0_DRPTB6 (*((volatile unsigned int*)(0x42A609D8UL))) +#define bM4_DMA1_RPTB0_DRPTB7 (*((volatile unsigned int*)(0x42A609DCUL))) +#define bM4_DMA1_RPTB0_DRPTB8 (*((volatile unsigned int*)(0x42A609E0UL))) +#define bM4_DMA1_RPTB0_DRPTB9 (*((volatile unsigned int*)(0x42A609E4UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A60A00UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A60A04UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A60A08UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A60A0CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A60A10UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A60A14UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A60A18UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A60A1CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A60A20UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A60A24UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A60A28UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A60A2CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A60A30UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A60A34UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A60A38UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A60A3CUL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A60A40UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A60A44UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A60A48UL))) +#define bM4_DMA1_SNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A60A4CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A60A50UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A60A54UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A60A58UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A60A5CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A60A60UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A60A64UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A60A68UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A60A6CUL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A60A70UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A60A74UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A60A78UL))) +#define bM4_DMA1_SNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A60A7CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST0 (*((volatile unsigned int*)(0x42A60A00UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST1 (*((volatile unsigned int*)(0x42A60A04UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST2 (*((volatile unsigned int*)(0x42A60A08UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST3 (*((volatile unsigned int*)(0x42A60A0CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST4 (*((volatile unsigned int*)(0x42A60A10UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST5 (*((volatile unsigned int*)(0x42A60A14UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST6 (*((volatile unsigned int*)(0x42A60A18UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST7 (*((volatile unsigned int*)(0x42A60A1CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST8 (*((volatile unsigned int*)(0x42A60A20UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST9 (*((volatile unsigned int*)(0x42A60A24UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST10 (*((volatile unsigned int*)(0x42A60A28UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST11 (*((volatile unsigned int*)(0x42A60A2CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST12 (*((volatile unsigned int*)(0x42A60A30UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST13 (*((volatile unsigned int*)(0x42A60A34UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST14 (*((volatile unsigned int*)(0x42A60A38UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST15 (*((volatile unsigned int*)(0x42A60A3CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST16 (*((volatile unsigned int*)(0x42A60A40UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST17 (*((volatile unsigned int*)(0x42A60A44UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST18 (*((volatile unsigned int*)(0x42A60A48UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSDIST19 (*((volatile unsigned int*)(0x42A60A4CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB0 (*((volatile unsigned int*)(0x42A60A50UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB1 (*((volatile unsigned int*)(0x42A60A54UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB2 (*((volatile unsigned int*)(0x42A60A58UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB3 (*((volatile unsigned int*)(0x42A60A5CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB4 (*((volatile unsigned int*)(0x42A60A60UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB5 (*((volatile unsigned int*)(0x42A60A64UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB6 (*((volatile unsigned int*)(0x42A60A68UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB7 (*((volatile unsigned int*)(0x42A60A6CUL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB8 (*((volatile unsigned int*)(0x42A60A70UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB9 (*((volatile unsigned int*)(0x42A60A74UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB10 (*((volatile unsigned int*)(0x42A60A78UL))) +#define bM4_DMA1_SNSEQCTLB0_SNSCNTB11 (*((volatile unsigned int*)(0x42A60A7CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A60A80UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A60A84UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A60A88UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A60A8CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A60A90UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A60A94UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A60A98UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A60A9CUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A60AA0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A60AA4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A60AA8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A60AACUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A60AB0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A60AB4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A60AB8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A60ABCUL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A60AC0UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A60AC4UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A60AC8UL))) +#define bM4_DMA1_DNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A60ACCUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A60AD0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A60AD4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A60AD8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A60ADCUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A60AE0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A60AE4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A60AE8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A60AECUL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A60AF0UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A60AF4UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A60AF8UL))) +#define bM4_DMA1_DNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A60AFCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST0 (*((volatile unsigned int*)(0x42A60A80UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST1 (*((volatile unsigned int*)(0x42A60A84UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST2 (*((volatile unsigned int*)(0x42A60A88UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST3 (*((volatile unsigned int*)(0x42A60A8CUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST4 (*((volatile unsigned int*)(0x42A60A90UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST5 (*((volatile unsigned int*)(0x42A60A94UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST6 (*((volatile unsigned int*)(0x42A60A98UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST7 (*((volatile unsigned int*)(0x42A60A9CUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST8 (*((volatile unsigned int*)(0x42A60AA0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST9 (*((volatile unsigned int*)(0x42A60AA4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST10 (*((volatile unsigned int*)(0x42A60AA8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST11 (*((volatile unsigned int*)(0x42A60AACUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST12 (*((volatile unsigned int*)(0x42A60AB0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST13 (*((volatile unsigned int*)(0x42A60AB4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST14 (*((volatile unsigned int*)(0x42A60AB8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST15 (*((volatile unsigned int*)(0x42A60ABCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST16 (*((volatile unsigned int*)(0x42A60AC0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST17 (*((volatile unsigned int*)(0x42A60AC4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST18 (*((volatile unsigned int*)(0x42A60AC8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSDIST19 (*((volatile unsigned int*)(0x42A60ACCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB0 (*((volatile unsigned int*)(0x42A60AD0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB1 (*((volatile unsigned int*)(0x42A60AD4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB2 (*((volatile unsigned int*)(0x42A60AD8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB3 (*((volatile unsigned int*)(0x42A60ADCUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB4 (*((volatile unsigned int*)(0x42A60AE0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB5 (*((volatile unsigned int*)(0x42A60AE4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB6 (*((volatile unsigned int*)(0x42A60AE8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB7 (*((volatile unsigned int*)(0x42A60AECUL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB8 (*((volatile unsigned int*)(0x42A60AF0UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB9 (*((volatile unsigned int*)(0x42A60AF4UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB10 (*((volatile unsigned int*)(0x42A60AF8UL))) +#define bM4_DMA1_DNSEQCTLB0_DNSCNTB11 (*((volatile unsigned int*)(0x42A60AFCUL))) +#define bM4_DMA1_LLP0_LLP0 (*((volatile unsigned int*)(0x42A60B08UL))) +#define bM4_DMA1_LLP0_LLP1 (*((volatile unsigned int*)(0x42A60B0CUL))) +#define bM4_DMA1_LLP0_LLP2 (*((volatile unsigned int*)(0x42A60B10UL))) +#define bM4_DMA1_LLP0_LLP3 (*((volatile unsigned int*)(0x42A60B14UL))) +#define bM4_DMA1_LLP0_LLP4 (*((volatile unsigned int*)(0x42A60B18UL))) +#define bM4_DMA1_LLP0_LLP5 (*((volatile unsigned int*)(0x42A60B1CUL))) +#define bM4_DMA1_LLP0_LLP6 (*((volatile unsigned int*)(0x42A60B20UL))) +#define bM4_DMA1_LLP0_LLP7 (*((volatile unsigned int*)(0x42A60B24UL))) +#define bM4_DMA1_LLP0_LLP8 (*((volatile unsigned int*)(0x42A60B28UL))) +#define bM4_DMA1_LLP0_LLP9 (*((volatile unsigned int*)(0x42A60B2CUL))) +#define bM4_DMA1_LLP0_LLP10 (*((volatile unsigned int*)(0x42A60B30UL))) +#define bM4_DMA1_LLP0_LLP11 (*((volatile unsigned int*)(0x42A60B34UL))) +#define bM4_DMA1_LLP0_LLP12 (*((volatile unsigned int*)(0x42A60B38UL))) +#define bM4_DMA1_LLP0_LLP13 (*((volatile unsigned int*)(0x42A60B3CUL))) +#define bM4_DMA1_LLP0_LLP14 (*((volatile unsigned int*)(0x42A60B40UL))) +#define bM4_DMA1_LLP0_LLP15 (*((volatile unsigned int*)(0x42A60B44UL))) +#define bM4_DMA1_LLP0_LLP16 (*((volatile unsigned int*)(0x42A60B48UL))) +#define bM4_DMA1_LLP0_LLP17 (*((volatile unsigned int*)(0x42A60B4CUL))) +#define bM4_DMA1_LLP0_LLP18 (*((volatile unsigned int*)(0x42A60B50UL))) +#define bM4_DMA1_LLP0_LLP19 (*((volatile unsigned int*)(0x42A60B54UL))) +#define bM4_DMA1_LLP0_LLP20 (*((volatile unsigned int*)(0x42A60B58UL))) +#define bM4_DMA1_LLP0_LLP21 (*((volatile unsigned int*)(0x42A60B5CUL))) +#define bM4_DMA1_LLP0_LLP22 (*((volatile unsigned int*)(0x42A60B60UL))) +#define bM4_DMA1_LLP0_LLP23 (*((volatile unsigned int*)(0x42A60B64UL))) +#define bM4_DMA1_LLP0_LLP24 (*((volatile unsigned int*)(0x42A60B68UL))) +#define bM4_DMA1_LLP0_LLP25 (*((volatile unsigned int*)(0x42A60B6CUL))) +#define bM4_DMA1_LLP0_LLP26 (*((volatile unsigned int*)(0x42A60B70UL))) +#define bM4_DMA1_LLP0_LLP27 (*((volatile unsigned int*)(0x42A60B74UL))) +#define bM4_DMA1_LLP0_LLP28 (*((volatile unsigned int*)(0x42A60B78UL))) +#define bM4_DMA1_LLP0_LLP29 (*((volatile unsigned int*)(0x42A60B7CUL))) +#define bM4_DMA1_CH0CTL_SINC0 (*((volatile unsigned int*)(0x42A60B80UL))) +#define bM4_DMA1_CH0CTL_SINC1 (*((volatile unsigned int*)(0x42A60B84UL))) +#define bM4_DMA1_CH0CTL_DINC0 (*((volatile unsigned int*)(0x42A60B88UL))) +#define bM4_DMA1_CH0CTL_DINC1 (*((volatile unsigned int*)(0x42A60B8CUL))) +#define bM4_DMA1_CH0CTL_SRPTEN (*((volatile unsigned int*)(0x42A60B90UL))) +#define bM4_DMA1_CH0CTL_DRPTEN (*((volatile unsigned int*)(0x42A60B94UL))) +#define bM4_DMA1_CH0CTL_SNSEQEN (*((volatile unsigned int*)(0x42A60B98UL))) +#define bM4_DMA1_CH0CTL_DNSEQEN (*((volatile unsigned int*)(0x42A60B9CUL))) +#define bM4_DMA1_CH0CTL_HSIZE0 (*((volatile unsigned int*)(0x42A60BA0UL))) +#define bM4_DMA1_CH0CTL_HSIZE1 (*((volatile unsigned int*)(0x42A60BA4UL))) +#define bM4_DMA1_CH0CTL_LLPEN (*((volatile unsigned int*)(0x42A60BA8UL))) +#define bM4_DMA1_CH0CTL_LLPRUN (*((volatile unsigned int*)(0x42A60BACUL))) +#define bM4_DMA1_CH0CTL_IE (*((volatile unsigned int*)(0x42A60BB0UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A60D00UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A60D04UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A60D08UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A60D0CUL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A60D10UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A60D14UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A60D18UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A60D1CUL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A60D20UL))) +#define bM4_DMA1_MONDTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A60D24UL))) +#define bM4_DMA1_MONDTCTL0_CNT0 (*((volatile unsigned int*)(0x42A60D40UL))) +#define bM4_DMA1_MONDTCTL0_CNT1 (*((volatile unsigned int*)(0x42A60D44UL))) +#define bM4_DMA1_MONDTCTL0_CNT2 (*((volatile unsigned int*)(0x42A60D48UL))) +#define bM4_DMA1_MONDTCTL0_CNT3 (*((volatile unsigned int*)(0x42A60D4CUL))) +#define bM4_DMA1_MONDTCTL0_CNT4 (*((volatile unsigned int*)(0x42A60D50UL))) +#define bM4_DMA1_MONDTCTL0_CNT5 (*((volatile unsigned int*)(0x42A60D54UL))) +#define bM4_DMA1_MONDTCTL0_CNT6 (*((volatile unsigned int*)(0x42A60D58UL))) +#define bM4_DMA1_MONDTCTL0_CNT7 (*((volatile unsigned int*)(0x42A60D5CUL))) +#define bM4_DMA1_MONDTCTL0_CNT8 (*((volatile unsigned int*)(0x42A60D60UL))) +#define bM4_DMA1_MONDTCTL0_CNT9 (*((volatile unsigned int*)(0x42A60D64UL))) +#define bM4_DMA1_MONDTCTL0_CNT10 (*((volatile unsigned int*)(0x42A60D68UL))) +#define bM4_DMA1_MONDTCTL0_CNT11 (*((volatile unsigned int*)(0x42A60D6CUL))) +#define bM4_DMA1_MONDTCTL0_CNT12 (*((volatile unsigned int*)(0x42A60D70UL))) +#define bM4_DMA1_MONDTCTL0_CNT13 (*((volatile unsigned int*)(0x42A60D74UL))) +#define bM4_DMA1_MONDTCTL0_CNT14 (*((volatile unsigned int*)(0x42A60D78UL))) +#define bM4_DMA1_MONDTCTL0_CNT15 (*((volatile unsigned int*)(0x42A60D7CUL))) +#define bM4_DMA1_MONRPT0_SRPT0 (*((volatile unsigned int*)(0x42A60D80UL))) +#define bM4_DMA1_MONRPT0_SRPT1 (*((volatile unsigned int*)(0x42A60D84UL))) +#define bM4_DMA1_MONRPT0_SRPT2 (*((volatile unsigned int*)(0x42A60D88UL))) +#define bM4_DMA1_MONRPT0_SRPT3 (*((volatile unsigned int*)(0x42A60D8CUL))) +#define bM4_DMA1_MONRPT0_SRPT4 (*((volatile unsigned int*)(0x42A60D90UL))) +#define bM4_DMA1_MONRPT0_SRPT5 (*((volatile unsigned int*)(0x42A60D94UL))) +#define bM4_DMA1_MONRPT0_SRPT6 (*((volatile unsigned int*)(0x42A60D98UL))) +#define bM4_DMA1_MONRPT0_SRPT7 (*((volatile unsigned int*)(0x42A60D9CUL))) +#define bM4_DMA1_MONRPT0_SRPT8 (*((volatile unsigned int*)(0x42A60DA0UL))) +#define bM4_DMA1_MONRPT0_SRPT9 (*((volatile unsigned int*)(0x42A60DA4UL))) +#define bM4_DMA1_MONRPT0_DRPT0 (*((volatile unsigned int*)(0x42A60DC0UL))) +#define bM4_DMA1_MONRPT0_DRPT1 (*((volatile unsigned int*)(0x42A60DC4UL))) +#define bM4_DMA1_MONRPT0_DRPT2 (*((volatile unsigned int*)(0x42A60DC8UL))) +#define bM4_DMA1_MONRPT0_DRPT3 (*((volatile unsigned int*)(0x42A60DCCUL))) +#define bM4_DMA1_MONRPT0_DRPT4 (*((volatile unsigned int*)(0x42A60DD0UL))) +#define bM4_DMA1_MONRPT0_DRPT5 (*((volatile unsigned int*)(0x42A60DD4UL))) +#define bM4_DMA1_MONRPT0_DRPT6 (*((volatile unsigned int*)(0x42A60DD8UL))) +#define bM4_DMA1_MONRPT0_DRPT7 (*((volatile unsigned int*)(0x42A60DDCUL))) +#define bM4_DMA1_MONRPT0_DRPT8 (*((volatile unsigned int*)(0x42A60DE0UL))) +#define bM4_DMA1_MONRPT0_DRPT9 (*((volatile unsigned int*)(0x42A60DE4UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A60E00UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A60E04UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A60E08UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A60E0CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A60E10UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A60E14UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A60E18UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A60E1CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A60E20UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A60E24UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A60E28UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A60E2CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A60E30UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A60E34UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A60E38UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A60E3CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A60E40UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A60E44UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A60E48UL))) +#define bM4_DMA1_MONSNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A60E4CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A60E50UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A60E54UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A60E58UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A60E5CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A60E60UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A60E64UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A60E68UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A60E6CUL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A60E70UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A60E74UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A60E78UL))) +#define bM4_DMA1_MONSNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A60E7CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A60E80UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A60E84UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A60E88UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A60E8CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A60E90UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A60E94UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A60E98UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A60E9CUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A60EA0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A60EA4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A60EA8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A60EACUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A60EB0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A60EB4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A60EB8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A60EBCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A60EC0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A60EC4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A60EC8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A60ECCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A60ED0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A60ED4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A60ED8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A60EDCUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A60EE0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A60EE4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A60EE8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A60EECUL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A60EF0UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A60EF4UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A60EF8UL))) +#define bM4_DMA1_MONDNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A60EFCUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A61100UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A61104UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A61108UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6110CUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A61110UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A61114UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A61118UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6111CUL))) +#define bM4_DMA1_DTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A61120UL))) +#define bM4_DMA1_DTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A61124UL))) +#define bM4_DMA1_DTCTL1_CNT0 (*((volatile unsigned int*)(0x42A61140UL))) +#define bM4_DMA1_DTCTL1_CNT1 (*((volatile unsigned int*)(0x42A61144UL))) +#define bM4_DMA1_DTCTL1_CNT2 (*((volatile unsigned int*)(0x42A61148UL))) +#define bM4_DMA1_DTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6114CUL))) +#define bM4_DMA1_DTCTL1_CNT4 (*((volatile unsigned int*)(0x42A61150UL))) +#define bM4_DMA1_DTCTL1_CNT5 (*((volatile unsigned int*)(0x42A61154UL))) +#define bM4_DMA1_DTCTL1_CNT6 (*((volatile unsigned int*)(0x42A61158UL))) +#define bM4_DMA1_DTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6115CUL))) +#define bM4_DMA1_DTCTL1_CNT8 (*((volatile unsigned int*)(0x42A61160UL))) +#define bM4_DMA1_DTCTL1_CNT9 (*((volatile unsigned int*)(0x42A61164UL))) +#define bM4_DMA1_DTCTL1_CNT10 (*((volatile unsigned int*)(0x42A61168UL))) +#define bM4_DMA1_DTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6116CUL))) +#define bM4_DMA1_DTCTL1_CNT12 (*((volatile unsigned int*)(0x42A61170UL))) +#define bM4_DMA1_DTCTL1_CNT13 (*((volatile unsigned int*)(0x42A61174UL))) +#define bM4_DMA1_DTCTL1_CNT14 (*((volatile unsigned int*)(0x42A61178UL))) +#define bM4_DMA1_DTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6117CUL))) +#define bM4_DMA1_RPT1_SRPT0 (*((volatile unsigned int*)(0x42A61180UL))) +#define bM4_DMA1_RPT1_SRPT1 (*((volatile unsigned int*)(0x42A61184UL))) +#define bM4_DMA1_RPT1_SRPT2 (*((volatile unsigned int*)(0x42A61188UL))) +#define bM4_DMA1_RPT1_SRPT3 (*((volatile unsigned int*)(0x42A6118CUL))) +#define bM4_DMA1_RPT1_SRPT4 (*((volatile unsigned int*)(0x42A61190UL))) +#define bM4_DMA1_RPT1_SRPT5 (*((volatile unsigned int*)(0x42A61194UL))) +#define bM4_DMA1_RPT1_SRPT6 (*((volatile unsigned int*)(0x42A61198UL))) +#define bM4_DMA1_RPT1_SRPT7 (*((volatile unsigned int*)(0x42A6119CUL))) +#define bM4_DMA1_RPT1_SRPT8 (*((volatile unsigned int*)(0x42A611A0UL))) +#define bM4_DMA1_RPT1_SRPT9 (*((volatile unsigned int*)(0x42A611A4UL))) +#define bM4_DMA1_RPT1_DRPT0 (*((volatile unsigned int*)(0x42A611C0UL))) +#define bM4_DMA1_RPT1_DRPT1 (*((volatile unsigned int*)(0x42A611C4UL))) +#define bM4_DMA1_RPT1_DRPT2 (*((volatile unsigned int*)(0x42A611C8UL))) +#define bM4_DMA1_RPT1_DRPT3 (*((volatile unsigned int*)(0x42A611CCUL))) +#define bM4_DMA1_RPT1_DRPT4 (*((volatile unsigned int*)(0x42A611D0UL))) +#define bM4_DMA1_RPT1_DRPT5 (*((volatile unsigned int*)(0x42A611D4UL))) +#define bM4_DMA1_RPT1_DRPT6 (*((volatile unsigned int*)(0x42A611D8UL))) +#define bM4_DMA1_RPT1_DRPT7 (*((volatile unsigned int*)(0x42A611DCUL))) +#define bM4_DMA1_RPT1_DRPT8 (*((volatile unsigned int*)(0x42A611E0UL))) +#define bM4_DMA1_RPT1_DRPT9 (*((volatile unsigned int*)(0x42A611E4UL))) +#define bM4_DMA1_RPTB1_SRPTB0 (*((volatile unsigned int*)(0x42A61180UL))) +#define bM4_DMA1_RPTB1_SRPTB1 (*((volatile unsigned int*)(0x42A61184UL))) +#define bM4_DMA1_RPTB1_SRPTB2 (*((volatile unsigned int*)(0x42A61188UL))) +#define bM4_DMA1_RPTB1_SRPTB3 (*((volatile unsigned int*)(0x42A6118CUL))) +#define bM4_DMA1_RPTB1_SRPTB4 (*((volatile unsigned int*)(0x42A61190UL))) +#define bM4_DMA1_RPTB1_SRPTB5 (*((volatile unsigned int*)(0x42A61194UL))) +#define bM4_DMA1_RPTB1_SRPTB6 (*((volatile unsigned int*)(0x42A61198UL))) +#define bM4_DMA1_RPTB1_SRPTB7 (*((volatile unsigned int*)(0x42A6119CUL))) +#define bM4_DMA1_RPTB1_SRPTB8 (*((volatile unsigned int*)(0x42A611A0UL))) +#define bM4_DMA1_RPTB1_SRPTB9 (*((volatile unsigned int*)(0x42A611A4UL))) +#define bM4_DMA1_RPTB1_DRPTB0 (*((volatile unsigned int*)(0x42A611C0UL))) +#define bM4_DMA1_RPTB1_DRPTB1 (*((volatile unsigned int*)(0x42A611C4UL))) +#define bM4_DMA1_RPTB1_DRPTB2 (*((volatile unsigned int*)(0x42A611C8UL))) +#define bM4_DMA1_RPTB1_DRPTB3 (*((volatile unsigned int*)(0x42A611CCUL))) +#define bM4_DMA1_RPTB1_DRPTB4 (*((volatile unsigned int*)(0x42A611D0UL))) +#define bM4_DMA1_RPTB1_DRPTB5 (*((volatile unsigned int*)(0x42A611D4UL))) +#define bM4_DMA1_RPTB1_DRPTB6 (*((volatile unsigned int*)(0x42A611D8UL))) +#define bM4_DMA1_RPTB1_DRPTB7 (*((volatile unsigned int*)(0x42A611DCUL))) +#define bM4_DMA1_RPTB1_DRPTB8 (*((volatile unsigned int*)(0x42A611E0UL))) +#define bM4_DMA1_RPTB1_DRPTB9 (*((volatile unsigned int*)(0x42A611E4UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A61200UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A61204UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A61208UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6120CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A61210UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A61214UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A61218UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6121CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A61220UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A61224UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A61228UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6122CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A61230UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A61234UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A61238UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6123CUL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A61240UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A61244UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A61248UL))) +#define bM4_DMA1_SNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6124CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A61250UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A61254UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A61258UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6125CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A61260UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A61264UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A61268UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6126CUL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A61270UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A61274UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A61278UL))) +#define bM4_DMA1_SNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6127CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST0 (*((volatile unsigned int*)(0x42A61200UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST1 (*((volatile unsigned int*)(0x42A61204UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST2 (*((volatile unsigned int*)(0x42A61208UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST3 (*((volatile unsigned int*)(0x42A6120CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST4 (*((volatile unsigned int*)(0x42A61210UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST5 (*((volatile unsigned int*)(0x42A61214UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST6 (*((volatile unsigned int*)(0x42A61218UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST7 (*((volatile unsigned int*)(0x42A6121CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST8 (*((volatile unsigned int*)(0x42A61220UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST9 (*((volatile unsigned int*)(0x42A61224UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST10 (*((volatile unsigned int*)(0x42A61228UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST11 (*((volatile unsigned int*)(0x42A6122CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST12 (*((volatile unsigned int*)(0x42A61230UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST13 (*((volatile unsigned int*)(0x42A61234UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST14 (*((volatile unsigned int*)(0x42A61238UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST15 (*((volatile unsigned int*)(0x42A6123CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST16 (*((volatile unsigned int*)(0x42A61240UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST17 (*((volatile unsigned int*)(0x42A61244UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST18 (*((volatile unsigned int*)(0x42A61248UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSDIST19 (*((volatile unsigned int*)(0x42A6124CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB0 (*((volatile unsigned int*)(0x42A61250UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB1 (*((volatile unsigned int*)(0x42A61254UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB2 (*((volatile unsigned int*)(0x42A61258UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB3 (*((volatile unsigned int*)(0x42A6125CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB4 (*((volatile unsigned int*)(0x42A61260UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB5 (*((volatile unsigned int*)(0x42A61264UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB6 (*((volatile unsigned int*)(0x42A61268UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB7 (*((volatile unsigned int*)(0x42A6126CUL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB8 (*((volatile unsigned int*)(0x42A61270UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB9 (*((volatile unsigned int*)(0x42A61274UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB10 (*((volatile unsigned int*)(0x42A61278UL))) +#define bM4_DMA1_SNSEQCTLB1_SNSCNTB11 (*((volatile unsigned int*)(0x42A6127CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A61280UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A61284UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A61288UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6128CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A61290UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A61294UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A61298UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6129CUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A612A0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A612A4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A612A8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A612ACUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A612B0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A612B4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A612B8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A612BCUL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A612C0UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A612C4UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A612C8UL))) +#define bM4_DMA1_DNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A612CCUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A612D0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A612D4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A612D8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A612DCUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A612E0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A612E4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A612E8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A612ECUL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A612F0UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A612F4UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A612F8UL))) +#define bM4_DMA1_DNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A612FCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST0 (*((volatile unsigned int*)(0x42A61280UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST1 (*((volatile unsigned int*)(0x42A61284UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST2 (*((volatile unsigned int*)(0x42A61288UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST3 (*((volatile unsigned int*)(0x42A6128CUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST4 (*((volatile unsigned int*)(0x42A61290UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST5 (*((volatile unsigned int*)(0x42A61294UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST6 (*((volatile unsigned int*)(0x42A61298UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST7 (*((volatile unsigned int*)(0x42A6129CUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST8 (*((volatile unsigned int*)(0x42A612A0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST9 (*((volatile unsigned int*)(0x42A612A4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST10 (*((volatile unsigned int*)(0x42A612A8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST11 (*((volatile unsigned int*)(0x42A612ACUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST12 (*((volatile unsigned int*)(0x42A612B0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST13 (*((volatile unsigned int*)(0x42A612B4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST14 (*((volatile unsigned int*)(0x42A612B8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST15 (*((volatile unsigned int*)(0x42A612BCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST16 (*((volatile unsigned int*)(0x42A612C0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST17 (*((volatile unsigned int*)(0x42A612C4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST18 (*((volatile unsigned int*)(0x42A612C8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSDIST19 (*((volatile unsigned int*)(0x42A612CCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB0 (*((volatile unsigned int*)(0x42A612D0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB1 (*((volatile unsigned int*)(0x42A612D4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB2 (*((volatile unsigned int*)(0x42A612D8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB3 (*((volatile unsigned int*)(0x42A612DCUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB4 (*((volatile unsigned int*)(0x42A612E0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB5 (*((volatile unsigned int*)(0x42A612E4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB6 (*((volatile unsigned int*)(0x42A612E8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB7 (*((volatile unsigned int*)(0x42A612ECUL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB8 (*((volatile unsigned int*)(0x42A612F0UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB9 (*((volatile unsigned int*)(0x42A612F4UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB10 (*((volatile unsigned int*)(0x42A612F8UL))) +#define bM4_DMA1_DNSEQCTLB1_DNSCNTB11 (*((volatile unsigned int*)(0x42A612FCUL))) +#define bM4_DMA1_LLP1_LLP0 (*((volatile unsigned int*)(0x42A61308UL))) +#define bM4_DMA1_LLP1_LLP1 (*((volatile unsigned int*)(0x42A6130CUL))) +#define bM4_DMA1_LLP1_LLP2 (*((volatile unsigned int*)(0x42A61310UL))) +#define bM4_DMA1_LLP1_LLP3 (*((volatile unsigned int*)(0x42A61314UL))) +#define bM4_DMA1_LLP1_LLP4 (*((volatile unsigned int*)(0x42A61318UL))) +#define bM4_DMA1_LLP1_LLP5 (*((volatile unsigned int*)(0x42A6131CUL))) +#define bM4_DMA1_LLP1_LLP6 (*((volatile unsigned int*)(0x42A61320UL))) +#define bM4_DMA1_LLP1_LLP7 (*((volatile unsigned int*)(0x42A61324UL))) +#define bM4_DMA1_LLP1_LLP8 (*((volatile unsigned int*)(0x42A61328UL))) +#define bM4_DMA1_LLP1_LLP9 (*((volatile unsigned int*)(0x42A6132CUL))) +#define bM4_DMA1_LLP1_LLP10 (*((volatile unsigned int*)(0x42A61330UL))) +#define bM4_DMA1_LLP1_LLP11 (*((volatile unsigned int*)(0x42A61334UL))) +#define bM4_DMA1_LLP1_LLP12 (*((volatile unsigned int*)(0x42A61338UL))) +#define bM4_DMA1_LLP1_LLP13 (*((volatile unsigned int*)(0x42A6133CUL))) +#define bM4_DMA1_LLP1_LLP14 (*((volatile unsigned int*)(0x42A61340UL))) +#define bM4_DMA1_LLP1_LLP15 (*((volatile unsigned int*)(0x42A61344UL))) +#define bM4_DMA1_LLP1_LLP16 (*((volatile unsigned int*)(0x42A61348UL))) +#define bM4_DMA1_LLP1_LLP17 (*((volatile unsigned int*)(0x42A6134CUL))) +#define bM4_DMA1_LLP1_LLP18 (*((volatile unsigned int*)(0x42A61350UL))) +#define bM4_DMA1_LLP1_LLP19 (*((volatile unsigned int*)(0x42A61354UL))) +#define bM4_DMA1_LLP1_LLP20 (*((volatile unsigned int*)(0x42A61358UL))) +#define bM4_DMA1_LLP1_LLP21 (*((volatile unsigned int*)(0x42A6135CUL))) +#define bM4_DMA1_LLP1_LLP22 (*((volatile unsigned int*)(0x42A61360UL))) +#define bM4_DMA1_LLP1_LLP23 (*((volatile unsigned int*)(0x42A61364UL))) +#define bM4_DMA1_LLP1_LLP24 (*((volatile unsigned int*)(0x42A61368UL))) +#define bM4_DMA1_LLP1_LLP25 (*((volatile unsigned int*)(0x42A6136CUL))) +#define bM4_DMA1_LLP1_LLP26 (*((volatile unsigned int*)(0x42A61370UL))) +#define bM4_DMA1_LLP1_LLP27 (*((volatile unsigned int*)(0x42A61374UL))) +#define bM4_DMA1_LLP1_LLP28 (*((volatile unsigned int*)(0x42A61378UL))) +#define bM4_DMA1_LLP1_LLP29 (*((volatile unsigned int*)(0x42A6137CUL))) +#define bM4_DMA1_CH1CTL_SINC0 (*((volatile unsigned int*)(0x42A61380UL))) +#define bM4_DMA1_CH1CTL_SINC1 (*((volatile unsigned int*)(0x42A61384UL))) +#define bM4_DMA1_CH1CTL_DINC0 (*((volatile unsigned int*)(0x42A61388UL))) +#define bM4_DMA1_CH1CTL_DINC1 (*((volatile unsigned int*)(0x42A6138CUL))) +#define bM4_DMA1_CH1CTL_SRPTEN (*((volatile unsigned int*)(0x42A61390UL))) +#define bM4_DMA1_CH1CTL_DRPTEN (*((volatile unsigned int*)(0x42A61394UL))) +#define bM4_DMA1_CH1CTL_SNSEQEN (*((volatile unsigned int*)(0x42A61398UL))) +#define bM4_DMA1_CH1CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6139CUL))) +#define bM4_DMA1_CH1CTL_HSIZE0 (*((volatile unsigned int*)(0x42A613A0UL))) +#define bM4_DMA1_CH1CTL_HSIZE1 (*((volatile unsigned int*)(0x42A613A4UL))) +#define bM4_DMA1_CH1CTL_LLPEN (*((volatile unsigned int*)(0x42A613A8UL))) +#define bM4_DMA1_CH1CTL_LLPRUN (*((volatile unsigned int*)(0x42A613ACUL))) +#define bM4_DMA1_CH1CTL_IE (*((volatile unsigned int*)(0x42A613B0UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A61500UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A61504UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A61508UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6150CUL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A61510UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A61514UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A61518UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6151CUL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A61520UL))) +#define bM4_DMA1_MONDTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A61524UL))) +#define bM4_DMA1_MONDTCTL1_CNT0 (*((volatile unsigned int*)(0x42A61540UL))) +#define bM4_DMA1_MONDTCTL1_CNT1 (*((volatile unsigned int*)(0x42A61544UL))) +#define bM4_DMA1_MONDTCTL1_CNT2 (*((volatile unsigned int*)(0x42A61548UL))) +#define bM4_DMA1_MONDTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6154CUL))) +#define bM4_DMA1_MONDTCTL1_CNT4 (*((volatile unsigned int*)(0x42A61550UL))) +#define bM4_DMA1_MONDTCTL1_CNT5 (*((volatile unsigned int*)(0x42A61554UL))) +#define bM4_DMA1_MONDTCTL1_CNT6 (*((volatile unsigned int*)(0x42A61558UL))) +#define bM4_DMA1_MONDTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6155CUL))) +#define bM4_DMA1_MONDTCTL1_CNT8 (*((volatile unsigned int*)(0x42A61560UL))) +#define bM4_DMA1_MONDTCTL1_CNT9 (*((volatile unsigned int*)(0x42A61564UL))) +#define bM4_DMA1_MONDTCTL1_CNT10 (*((volatile unsigned int*)(0x42A61568UL))) +#define bM4_DMA1_MONDTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6156CUL))) +#define bM4_DMA1_MONDTCTL1_CNT12 (*((volatile unsigned int*)(0x42A61570UL))) +#define bM4_DMA1_MONDTCTL1_CNT13 (*((volatile unsigned int*)(0x42A61574UL))) +#define bM4_DMA1_MONDTCTL1_CNT14 (*((volatile unsigned int*)(0x42A61578UL))) +#define bM4_DMA1_MONDTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6157CUL))) +#define bM4_DMA1_MONRPT1_SRPT0 (*((volatile unsigned int*)(0x42A61580UL))) +#define bM4_DMA1_MONRPT1_SRPT1 (*((volatile unsigned int*)(0x42A61584UL))) +#define bM4_DMA1_MONRPT1_SRPT2 (*((volatile unsigned int*)(0x42A61588UL))) +#define bM4_DMA1_MONRPT1_SRPT3 (*((volatile unsigned int*)(0x42A6158CUL))) +#define bM4_DMA1_MONRPT1_SRPT4 (*((volatile unsigned int*)(0x42A61590UL))) +#define bM4_DMA1_MONRPT1_SRPT5 (*((volatile unsigned int*)(0x42A61594UL))) +#define bM4_DMA1_MONRPT1_SRPT6 (*((volatile unsigned int*)(0x42A61598UL))) +#define bM4_DMA1_MONRPT1_SRPT7 (*((volatile unsigned int*)(0x42A6159CUL))) +#define bM4_DMA1_MONRPT1_SRPT8 (*((volatile unsigned int*)(0x42A615A0UL))) +#define bM4_DMA1_MONRPT1_SRPT9 (*((volatile unsigned int*)(0x42A615A4UL))) +#define bM4_DMA1_MONRPT1_DRPT0 (*((volatile unsigned int*)(0x42A615C0UL))) +#define bM4_DMA1_MONRPT1_DRPT1 (*((volatile unsigned int*)(0x42A615C4UL))) +#define bM4_DMA1_MONRPT1_DRPT2 (*((volatile unsigned int*)(0x42A615C8UL))) +#define bM4_DMA1_MONRPT1_DRPT3 (*((volatile unsigned int*)(0x42A615CCUL))) +#define bM4_DMA1_MONRPT1_DRPT4 (*((volatile unsigned int*)(0x42A615D0UL))) +#define bM4_DMA1_MONRPT1_DRPT5 (*((volatile unsigned int*)(0x42A615D4UL))) +#define bM4_DMA1_MONRPT1_DRPT6 (*((volatile unsigned int*)(0x42A615D8UL))) +#define bM4_DMA1_MONRPT1_DRPT7 (*((volatile unsigned int*)(0x42A615DCUL))) +#define bM4_DMA1_MONRPT1_DRPT8 (*((volatile unsigned int*)(0x42A615E0UL))) +#define bM4_DMA1_MONRPT1_DRPT9 (*((volatile unsigned int*)(0x42A615E4UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A61600UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A61604UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A61608UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6160CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A61610UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A61614UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A61618UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6161CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A61620UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A61624UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A61628UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6162CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A61630UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A61634UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A61638UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6163CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A61640UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A61644UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A61648UL))) +#define bM4_DMA1_MONSNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6164CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A61650UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A61654UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A61658UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6165CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A61660UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A61664UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A61668UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6166CUL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A61670UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A61674UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A61678UL))) +#define bM4_DMA1_MONSNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6167CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A61680UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A61684UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A61688UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6168CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A61690UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A61694UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A61698UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6169CUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A616A0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A616A4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A616A8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A616ACUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A616B0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A616B4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A616B8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A616BCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A616C0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A616C4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A616C8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A616CCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A616D0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A616D4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A616D8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A616DCUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A616E0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A616E4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A616E8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A616ECUL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A616F0UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A616F4UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A616F8UL))) +#define bM4_DMA1_MONDNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A616FCUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A61900UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A61904UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A61908UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A6190CUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A61910UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A61914UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A61918UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A6191CUL))) +#define bM4_DMA1_DTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A61920UL))) +#define bM4_DMA1_DTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A61924UL))) +#define bM4_DMA1_DTCTL2_CNT0 (*((volatile unsigned int*)(0x42A61940UL))) +#define bM4_DMA1_DTCTL2_CNT1 (*((volatile unsigned int*)(0x42A61944UL))) +#define bM4_DMA1_DTCTL2_CNT2 (*((volatile unsigned int*)(0x42A61948UL))) +#define bM4_DMA1_DTCTL2_CNT3 (*((volatile unsigned int*)(0x42A6194CUL))) +#define bM4_DMA1_DTCTL2_CNT4 (*((volatile unsigned int*)(0x42A61950UL))) +#define bM4_DMA1_DTCTL2_CNT5 (*((volatile unsigned int*)(0x42A61954UL))) +#define bM4_DMA1_DTCTL2_CNT6 (*((volatile unsigned int*)(0x42A61958UL))) +#define bM4_DMA1_DTCTL2_CNT7 (*((volatile unsigned int*)(0x42A6195CUL))) +#define bM4_DMA1_DTCTL2_CNT8 (*((volatile unsigned int*)(0x42A61960UL))) +#define bM4_DMA1_DTCTL2_CNT9 (*((volatile unsigned int*)(0x42A61964UL))) +#define bM4_DMA1_DTCTL2_CNT10 (*((volatile unsigned int*)(0x42A61968UL))) +#define bM4_DMA1_DTCTL2_CNT11 (*((volatile unsigned int*)(0x42A6196CUL))) +#define bM4_DMA1_DTCTL2_CNT12 (*((volatile unsigned int*)(0x42A61970UL))) +#define bM4_DMA1_DTCTL2_CNT13 (*((volatile unsigned int*)(0x42A61974UL))) +#define bM4_DMA1_DTCTL2_CNT14 (*((volatile unsigned int*)(0x42A61978UL))) +#define bM4_DMA1_DTCTL2_CNT15 (*((volatile unsigned int*)(0x42A6197CUL))) +#define bM4_DMA1_RPT2_SRPT0 (*((volatile unsigned int*)(0x42A61980UL))) +#define bM4_DMA1_RPT2_SRPT1 (*((volatile unsigned int*)(0x42A61984UL))) +#define bM4_DMA1_RPT2_SRPT2 (*((volatile unsigned int*)(0x42A61988UL))) +#define bM4_DMA1_RPT2_SRPT3 (*((volatile unsigned int*)(0x42A6198CUL))) +#define bM4_DMA1_RPT2_SRPT4 (*((volatile unsigned int*)(0x42A61990UL))) +#define bM4_DMA1_RPT2_SRPT5 (*((volatile unsigned int*)(0x42A61994UL))) +#define bM4_DMA1_RPT2_SRPT6 (*((volatile unsigned int*)(0x42A61998UL))) +#define bM4_DMA1_RPT2_SRPT7 (*((volatile unsigned int*)(0x42A6199CUL))) +#define bM4_DMA1_RPT2_SRPT8 (*((volatile unsigned int*)(0x42A619A0UL))) +#define bM4_DMA1_RPT2_SRPT9 (*((volatile unsigned int*)(0x42A619A4UL))) +#define bM4_DMA1_RPT2_DRPT0 (*((volatile unsigned int*)(0x42A619C0UL))) +#define bM4_DMA1_RPT2_DRPT1 (*((volatile unsigned int*)(0x42A619C4UL))) +#define bM4_DMA1_RPT2_DRPT2 (*((volatile unsigned int*)(0x42A619C8UL))) +#define bM4_DMA1_RPT2_DRPT3 (*((volatile unsigned int*)(0x42A619CCUL))) +#define bM4_DMA1_RPT2_DRPT4 (*((volatile unsigned int*)(0x42A619D0UL))) +#define bM4_DMA1_RPT2_DRPT5 (*((volatile unsigned int*)(0x42A619D4UL))) +#define bM4_DMA1_RPT2_DRPT6 (*((volatile unsigned int*)(0x42A619D8UL))) +#define bM4_DMA1_RPT2_DRPT7 (*((volatile unsigned int*)(0x42A619DCUL))) +#define bM4_DMA1_RPT2_DRPT8 (*((volatile unsigned int*)(0x42A619E0UL))) +#define bM4_DMA1_RPT2_DRPT9 (*((volatile unsigned int*)(0x42A619E4UL))) +#define bM4_DMA1_RPTB2_SRPTB0 (*((volatile unsigned int*)(0x42A61980UL))) +#define bM4_DMA1_RPTB2_SRPTB1 (*((volatile unsigned int*)(0x42A61984UL))) +#define bM4_DMA1_RPTB2_SRPTB2 (*((volatile unsigned int*)(0x42A61988UL))) +#define bM4_DMA1_RPTB2_SRPTB3 (*((volatile unsigned int*)(0x42A6198CUL))) +#define bM4_DMA1_RPTB2_SRPTB4 (*((volatile unsigned int*)(0x42A61990UL))) +#define bM4_DMA1_RPTB2_SRPTB5 (*((volatile unsigned int*)(0x42A61994UL))) +#define bM4_DMA1_RPTB2_SRPTB6 (*((volatile unsigned int*)(0x42A61998UL))) +#define bM4_DMA1_RPTB2_SRPTB7 (*((volatile unsigned int*)(0x42A6199CUL))) +#define bM4_DMA1_RPTB2_SRPTB8 (*((volatile unsigned int*)(0x42A619A0UL))) +#define bM4_DMA1_RPTB2_SRPTB9 (*((volatile unsigned int*)(0x42A619A4UL))) +#define bM4_DMA1_RPTB2_DRPTB0 (*((volatile unsigned int*)(0x42A619C0UL))) +#define bM4_DMA1_RPTB2_DRPTB1 (*((volatile unsigned int*)(0x42A619C4UL))) +#define bM4_DMA1_RPTB2_DRPTB2 (*((volatile unsigned int*)(0x42A619C8UL))) +#define bM4_DMA1_RPTB2_DRPTB3 (*((volatile unsigned int*)(0x42A619CCUL))) +#define bM4_DMA1_RPTB2_DRPTB4 (*((volatile unsigned int*)(0x42A619D0UL))) +#define bM4_DMA1_RPTB2_DRPTB5 (*((volatile unsigned int*)(0x42A619D4UL))) +#define bM4_DMA1_RPTB2_DRPTB6 (*((volatile unsigned int*)(0x42A619D8UL))) +#define bM4_DMA1_RPTB2_DRPTB7 (*((volatile unsigned int*)(0x42A619DCUL))) +#define bM4_DMA1_RPTB2_DRPTB8 (*((volatile unsigned int*)(0x42A619E0UL))) +#define bM4_DMA1_RPTB2_DRPTB9 (*((volatile unsigned int*)(0x42A619E4UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A61A00UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A61A04UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A61A08UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A61A0CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A61A10UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A61A14UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A61A18UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A61A1CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A61A20UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A61A24UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A61A28UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A61A2CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A61A30UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A61A34UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A61A38UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A61A3CUL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A61A40UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A61A44UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A61A48UL))) +#define bM4_DMA1_SNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A61A4CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A61A50UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A61A54UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A61A58UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A61A5CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A61A60UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A61A64UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A61A68UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A61A6CUL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A61A70UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A61A74UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A61A78UL))) +#define bM4_DMA1_SNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A61A7CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST0 (*((volatile unsigned int*)(0x42A61A00UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST1 (*((volatile unsigned int*)(0x42A61A04UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST2 (*((volatile unsigned int*)(0x42A61A08UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST3 (*((volatile unsigned int*)(0x42A61A0CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST4 (*((volatile unsigned int*)(0x42A61A10UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST5 (*((volatile unsigned int*)(0x42A61A14UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST6 (*((volatile unsigned int*)(0x42A61A18UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST7 (*((volatile unsigned int*)(0x42A61A1CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST8 (*((volatile unsigned int*)(0x42A61A20UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST9 (*((volatile unsigned int*)(0x42A61A24UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST10 (*((volatile unsigned int*)(0x42A61A28UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST11 (*((volatile unsigned int*)(0x42A61A2CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST12 (*((volatile unsigned int*)(0x42A61A30UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST13 (*((volatile unsigned int*)(0x42A61A34UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST14 (*((volatile unsigned int*)(0x42A61A38UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST15 (*((volatile unsigned int*)(0x42A61A3CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST16 (*((volatile unsigned int*)(0x42A61A40UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST17 (*((volatile unsigned int*)(0x42A61A44UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST18 (*((volatile unsigned int*)(0x42A61A48UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSDIST19 (*((volatile unsigned int*)(0x42A61A4CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB0 (*((volatile unsigned int*)(0x42A61A50UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB1 (*((volatile unsigned int*)(0x42A61A54UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB2 (*((volatile unsigned int*)(0x42A61A58UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB3 (*((volatile unsigned int*)(0x42A61A5CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB4 (*((volatile unsigned int*)(0x42A61A60UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB5 (*((volatile unsigned int*)(0x42A61A64UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB6 (*((volatile unsigned int*)(0x42A61A68UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB7 (*((volatile unsigned int*)(0x42A61A6CUL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB8 (*((volatile unsigned int*)(0x42A61A70UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB9 (*((volatile unsigned int*)(0x42A61A74UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB10 (*((volatile unsigned int*)(0x42A61A78UL))) +#define bM4_DMA1_SNSEQCTLB2_SNSCNTB11 (*((volatile unsigned int*)(0x42A61A7CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A61A80UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A61A84UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A61A88UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A61A8CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A61A90UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A61A94UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A61A98UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A61A9CUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A61AA0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A61AA4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A61AA8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A61AACUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A61AB0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A61AB4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A61AB8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A61ABCUL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A61AC0UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A61AC4UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A61AC8UL))) +#define bM4_DMA1_DNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A61ACCUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A61AD0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A61AD4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A61AD8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A61ADCUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A61AE0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A61AE4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A61AE8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A61AECUL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A61AF0UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A61AF4UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A61AF8UL))) +#define bM4_DMA1_DNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A61AFCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST0 (*((volatile unsigned int*)(0x42A61A80UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST1 (*((volatile unsigned int*)(0x42A61A84UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST2 (*((volatile unsigned int*)(0x42A61A88UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST3 (*((volatile unsigned int*)(0x42A61A8CUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST4 (*((volatile unsigned int*)(0x42A61A90UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST5 (*((volatile unsigned int*)(0x42A61A94UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST6 (*((volatile unsigned int*)(0x42A61A98UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST7 (*((volatile unsigned int*)(0x42A61A9CUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST8 (*((volatile unsigned int*)(0x42A61AA0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST9 (*((volatile unsigned int*)(0x42A61AA4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST10 (*((volatile unsigned int*)(0x42A61AA8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST11 (*((volatile unsigned int*)(0x42A61AACUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST12 (*((volatile unsigned int*)(0x42A61AB0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST13 (*((volatile unsigned int*)(0x42A61AB4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST14 (*((volatile unsigned int*)(0x42A61AB8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST15 (*((volatile unsigned int*)(0x42A61ABCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST16 (*((volatile unsigned int*)(0x42A61AC0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST17 (*((volatile unsigned int*)(0x42A61AC4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST18 (*((volatile unsigned int*)(0x42A61AC8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSDIST19 (*((volatile unsigned int*)(0x42A61ACCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB0 (*((volatile unsigned int*)(0x42A61AD0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB1 (*((volatile unsigned int*)(0x42A61AD4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB2 (*((volatile unsigned int*)(0x42A61AD8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB3 (*((volatile unsigned int*)(0x42A61ADCUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB4 (*((volatile unsigned int*)(0x42A61AE0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB5 (*((volatile unsigned int*)(0x42A61AE4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB6 (*((volatile unsigned int*)(0x42A61AE8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB7 (*((volatile unsigned int*)(0x42A61AECUL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB8 (*((volatile unsigned int*)(0x42A61AF0UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB9 (*((volatile unsigned int*)(0x42A61AF4UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB10 (*((volatile unsigned int*)(0x42A61AF8UL))) +#define bM4_DMA1_DNSEQCTLB2_DNSCNTB11 (*((volatile unsigned int*)(0x42A61AFCUL))) +#define bM4_DMA1_LLP2_LLP0 (*((volatile unsigned int*)(0x42A61B08UL))) +#define bM4_DMA1_LLP2_LLP1 (*((volatile unsigned int*)(0x42A61B0CUL))) +#define bM4_DMA1_LLP2_LLP2 (*((volatile unsigned int*)(0x42A61B10UL))) +#define bM4_DMA1_LLP2_LLP3 (*((volatile unsigned int*)(0x42A61B14UL))) +#define bM4_DMA1_LLP2_LLP4 (*((volatile unsigned int*)(0x42A61B18UL))) +#define bM4_DMA1_LLP2_LLP5 (*((volatile unsigned int*)(0x42A61B1CUL))) +#define bM4_DMA1_LLP2_LLP6 (*((volatile unsigned int*)(0x42A61B20UL))) +#define bM4_DMA1_LLP2_LLP7 (*((volatile unsigned int*)(0x42A61B24UL))) +#define bM4_DMA1_LLP2_LLP8 (*((volatile unsigned int*)(0x42A61B28UL))) +#define bM4_DMA1_LLP2_LLP9 (*((volatile unsigned int*)(0x42A61B2CUL))) +#define bM4_DMA1_LLP2_LLP10 (*((volatile unsigned int*)(0x42A61B30UL))) +#define bM4_DMA1_LLP2_LLP11 (*((volatile unsigned int*)(0x42A61B34UL))) +#define bM4_DMA1_LLP2_LLP12 (*((volatile unsigned int*)(0x42A61B38UL))) +#define bM4_DMA1_LLP2_LLP13 (*((volatile unsigned int*)(0x42A61B3CUL))) +#define bM4_DMA1_LLP2_LLP14 (*((volatile unsigned int*)(0x42A61B40UL))) +#define bM4_DMA1_LLP2_LLP15 (*((volatile unsigned int*)(0x42A61B44UL))) +#define bM4_DMA1_LLP2_LLP16 (*((volatile unsigned int*)(0x42A61B48UL))) +#define bM4_DMA1_LLP2_LLP17 (*((volatile unsigned int*)(0x42A61B4CUL))) +#define bM4_DMA1_LLP2_LLP18 (*((volatile unsigned int*)(0x42A61B50UL))) +#define bM4_DMA1_LLP2_LLP19 (*((volatile unsigned int*)(0x42A61B54UL))) +#define bM4_DMA1_LLP2_LLP20 (*((volatile unsigned int*)(0x42A61B58UL))) +#define bM4_DMA1_LLP2_LLP21 (*((volatile unsigned int*)(0x42A61B5CUL))) +#define bM4_DMA1_LLP2_LLP22 (*((volatile unsigned int*)(0x42A61B60UL))) +#define bM4_DMA1_LLP2_LLP23 (*((volatile unsigned int*)(0x42A61B64UL))) +#define bM4_DMA1_LLP2_LLP24 (*((volatile unsigned int*)(0x42A61B68UL))) +#define bM4_DMA1_LLP2_LLP25 (*((volatile unsigned int*)(0x42A61B6CUL))) +#define bM4_DMA1_LLP2_LLP26 (*((volatile unsigned int*)(0x42A61B70UL))) +#define bM4_DMA1_LLP2_LLP27 (*((volatile unsigned int*)(0x42A61B74UL))) +#define bM4_DMA1_LLP2_LLP28 (*((volatile unsigned int*)(0x42A61B78UL))) +#define bM4_DMA1_LLP2_LLP29 (*((volatile unsigned int*)(0x42A61B7CUL))) +#define bM4_DMA1_CH2CTL_SINC0 (*((volatile unsigned int*)(0x42A61B80UL))) +#define bM4_DMA1_CH2CTL_SINC1 (*((volatile unsigned int*)(0x42A61B84UL))) +#define bM4_DMA1_CH2CTL_DINC0 (*((volatile unsigned int*)(0x42A61B88UL))) +#define bM4_DMA1_CH2CTL_DINC1 (*((volatile unsigned int*)(0x42A61B8CUL))) +#define bM4_DMA1_CH2CTL_SRPTEN (*((volatile unsigned int*)(0x42A61B90UL))) +#define bM4_DMA1_CH2CTL_DRPTEN (*((volatile unsigned int*)(0x42A61B94UL))) +#define bM4_DMA1_CH2CTL_SNSEQEN (*((volatile unsigned int*)(0x42A61B98UL))) +#define bM4_DMA1_CH2CTL_DNSEQEN (*((volatile unsigned int*)(0x42A61B9CUL))) +#define bM4_DMA1_CH2CTL_HSIZE0 (*((volatile unsigned int*)(0x42A61BA0UL))) +#define bM4_DMA1_CH2CTL_HSIZE1 (*((volatile unsigned int*)(0x42A61BA4UL))) +#define bM4_DMA1_CH2CTL_LLPEN (*((volatile unsigned int*)(0x42A61BA8UL))) +#define bM4_DMA1_CH2CTL_LLPRUN (*((volatile unsigned int*)(0x42A61BACUL))) +#define bM4_DMA1_CH2CTL_IE (*((volatile unsigned int*)(0x42A61BB0UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A61D00UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A61D04UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A61D08UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A61D0CUL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A61D10UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A61D14UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A61D18UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A61D1CUL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A61D20UL))) +#define bM4_DMA1_MONDTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A61D24UL))) +#define bM4_DMA1_MONDTCTL2_CNT0 (*((volatile unsigned int*)(0x42A61D40UL))) +#define bM4_DMA1_MONDTCTL2_CNT1 (*((volatile unsigned int*)(0x42A61D44UL))) +#define bM4_DMA1_MONDTCTL2_CNT2 (*((volatile unsigned int*)(0x42A61D48UL))) +#define bM4_DMA1_MONDTCTL2_CNT3 (*((volatile unsigned int*)(0x42A61D4CUL))) +#define bM4_DMA1_MONDTCTL2_CNT4 (*((volatile unsigned int*)(0x42A61D50UL))) +#define bM4_DMA1_MONDTCTL2_CNT5 (*((volatile unsigned int*)(0x42A61D54UL))) +#define bM4_DMA1_MONDTCTL2_CNT6 (*((volatile unsigned int*)(0x42A61D58UL))) +#define bM4_DMA1_MONDTCTL2_CNT7 (*((volatile unsigned int*)(0x42A61D5CUL))) +#define bM4_DMA1_MONDTCTL2_CNT8 (*((volatile unsigned int*)(0x42A61D60UL))) +#define bM4_DMA1_MONDTCTL2_CNT9 (*((volatile unsigned int*)(0x42A61D64UL))) +#define bM4_DMA1_MONDTCTL2_CNT10 (*((volatile unsigned int*)(0x42A61D68UL))) +#define bM4_DMA1_MONDTCTL2_CNT11 (*((volatile unsigned int*)(0x42A61D6CUL))) +#define bM4_DMA1_MONDTCTL2_CNT12 (*((volatile unsigned int*)(0x42A61D70UL))) +#define bM4_DMA1_MONDTCTL2_CNT13 (*((volatile unsigned int*)(0x42A61D74UL))) +#define bM4_DMA1_MONDTCTL2_CNT14 (*((volatile unsigned int*)(0x42A61D78UL))) +#define bM4_DMA1_MONDTCTL2_CNT15 (*((volatile unsigned int*)(0x42A61D7CUL))) +#define bM4_DMA1_MONRPT2_SRPT0 (*((volatile unsigned int*)(0x42A61D80UL))) +#define bM4_DMA1_MONRPT2_SRPT1 (*((volatile unsigned int*)(0x42A61D84UL))) +#define bM4_DMA1_MONRPT2_SRPT2 (*((volatile unsigned int*)(0x42A61D88UL))) +#define bM4_DMA1_MONRPT2_SRPT3 (*((volatile unsigned int*)(0x42A61D8CUL))) +#define bM4_DMA1_MONRPT2_SRPT4 (*((volatile unsigned int*)(0x42A61D90UL))) +#define bM4_DMA1_MONRPT2_SRPT5 (*((volatile unsigned int*)(0x42A61D94UL))) +#define bM4_DMA1_MONRPT2_SRPT6 (*((volatile unsigned int*)(0x42A61D98UL))) +#define bM4_DMA1_MONRPT2_SRPT7 (*((volatile unsigned int*)(0x42A61D9CUL))) +#define bM4_DMA1_MONRPT2_SRPT8 (*((volatile unsigned int*)(0x42A61DA0UL))) +#define bM4_DMA1_MONRPT2_SRPT9 (*((volatile unsigned int*)(0x42A61DA4UL))) +#define bM4_DMA1_MONRPT2_DRPT0 (*((volatile unsigned int*)(0x42A61DC0UL))) +#define bM4_DMA1_MONRPT2_DRPT1 (*((volatile unsigned int*)(0x42A61DC4UL))) +#define bM4_DMA1_MONRPT2_DRPT2 (*((volatile unsigned int*)(0x42A61DC8UL))) +#define bM4_DMA1_MONRPT2_DRPT3 (*((volatile unsigned int*)(0x42A61DCCUL))) +#define bM4_DMA1_MONRPT2_DRPT4 (*((volatile unsigned int*)(0x42A61DD0UL))) +#define bM4_DMA1_MONRPT2_DRPT5 (*((volatile unsigned int*)(0x42A61DD4UL))) +#define bM4_DMA1_MONRPT2_DRPT6 (*((volatile unsigned int*)(0x42A61DD8UL))) +#define bM4_DMA1_MONRPT2_DRPT7 (*((volatile unsigned int*)(0x42A61DDCUL))) +#define bM4_DMA1_MONRPT2_DRPT8 (*((volatile unsigned int*)(0x42A61DE0UL))) +#define bM4_DMA1_MONRPT2_DRPT9 (*((volatile unsigned int*)(0x42A61DE4UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A61E00UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A61E04UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A61E08UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A61E0CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A61E10UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A61E14UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A61E18UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A61E1CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A61E20UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A61E24UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A61E28UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A61E2CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A61E30UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A61E34UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A61E38UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A61E3CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A61E40UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A61E44UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A61E48UL))) +#define bM4_DMA1_MONSNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A61E4CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A61E50UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A61E54UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A61E58UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A61E5CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A61E60UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A61E64UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A61E68UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A61E6CUL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A61E70UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A61E74UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A61E78UL))) +#define bM4_DMA1_MONSNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A61E7CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A61E80UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A61E84UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A61E88UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A61E8CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A61E90UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A61E94UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A61E98UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A61E9CUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A61EA0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A61EA4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A61EA8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A61EACUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A61EB0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A61EB4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A61EB8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A61EBCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A61EC0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A61EC4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A61EC8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A61ECCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A61ED0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A61ED4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A61ED8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A61EDCUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A61EE0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A61EE4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A61EE8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A61EECUL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A61EF0UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A61EF4UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A61EF8UL))) +#define bM4_DMA1_MONDNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A61EFCUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A62100UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A62104UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A62108UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6210CUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A62110UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A62114UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A62118UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6211CUL))) +#define bM4_DMA1_DTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A62120UL))) +#define bM4_DMA1_DTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A62124UL))) +#define bM4_DMA1_DTCTL3_CNT0 (*((volatile unsigned int*)(0x42A62140UL))) +#define bM4_DMA1_DTCTL3_CNT1 (*((volatile unsigned int*)(0x42A62144UL))) +#define bM4_DMA1_DTCTL3_CNT2 (*((volatile unsigned int*)(0x42A62148UL))) +#define bM4_DMA1_DTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6214CUL))) +#define bM4_DMA1_DTCTL3_CNT4 (*((volatile unsigned int*)(0x42A62150UL))) +#define bM4_DMA1_DTCTL3_CNT5 (*((volatile unsigned int*)(0x42A62154UL))) +#define bM4_DMA1_DTCTL3_CNT6 (*((volatile unsigned int*)(0x42A62158UL))) +#define bM4_DMA1_DTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6215CUL))) +#define bM4_DMA1_DTCTL3_CNT8 (*((volatile unsigned int*)(0x42A62160UL))) +#define bM4_DMA1_DTCTL3_CNT9 (*((volatile unsigned int*)(0x42A62164UL))) +#define bM4_DMA1_DTCTL3_CNT10 (*((volatile unsigned int*)(0x42A62168UL))) +#define bM4_DMA1_DTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6216CUL))) +#define bM4_DMA1_DTCTL3_CNT12 (*((volatile unsigned int*)(0x42A62170UL))) +#define bM4_DMA1_DTCTL3_CNT13 (*((volatile unsigned int*)(0x42A62174UL))) +#define bM4_DMA1_DTCTL3_CNT14 (*((volatile unsigned int*)(0x42A62178UL))) +#define bM4_DMA1_DTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6217CUL))) +#define bM4_DMA1_RPT3_SRPT0 (*((volatile unsigned int*)(0x42A62180UL))) +#define bM4_DMA1_RPT3_SRPT1 (*((volatile unsigned int*)(0x42A62184UL))) +#define bM4_DMA1_RPT3_SRPT2 (*((volatile unsigned int*)(0x42A62188UL))) +#define bM4_DMA1_RPT3_SRPT3 (*((volatile unsigned int*)(0x42A6218CUL))) +#define bM4_DMA1_RPT3_SRPT4 (*((volatile unsigned int*)(0x42A62190UL))) +#define bM4_DMA1_RPT3_SRPT5 (*((volatile unsigned int*)(0x42A62194UL))) +#define bM4_DMA1_RPT3_SRPT6 (*((volatile unsigned int*)(0x42A62198UL))) +#define bM4_DMA1_RPT3_SRPT7 (*((volatile unsigned int*)(0x42A6219CUL))) +#define bM4_DMA1_RPT3_SRPT8 (*((volatile unsigned int*)(0x42A621A0UL))) +#define bM4_DMA1_RPT3_SRPT9 (*((volatile unsigned int*)(0x42A621A4UL))) +#define bM4_DMA1_RPT3_DRPT0 (*((volatile unsigned int*)(0x42A621C0UL))) +#define bM4_DMA1_RPT3_DRPT1 (*((volatile unsigned int*)(0x42A621C4UL))) +#define bM4_DMA1_RPT3_DRPT2 (*((volatile unsigned int*)(0x42A621C8UL))) +#define bM4_DMA1_RPT3_DRPT3 (*((volatile unsigned int*)(0x42A621CCUL))) +#define bM4_DMA1_RPT3_DRPT4 (*((volatile unsigned int*)(0x42A621D0UL))) +#define bM4_DMA1_RPT3_DRPT5 (*((volatile unsigned int*)(0x42A621D4UL))) +#define bM4_DMA1_RPT3_DRPT6 (*((volatile unsigned int*)(0x42A621D8UL))) +#define bM4_DMA1_RPT3_DRPT7 (*((volatile unsigned int*)(0x42A621DCUL))) +#define bM4_DMA1_RPT3_DRPT8 (*((volatile unsigned int*)(0x42A621E0UL))) +#define bM4_DMA1_RPT3_DRPT9 (*((volatile unsigned int*)(0x42A621E4UL))) +#define bM4_DMA1_RPTB3_SRPTB0 (*((volatile unsigned int*)(0x42A62180UL))) +#define bM4_DMA1_RPTB3_SRPTB1 (*((volatile unsigned int*)(0x42A62184UL))) +#define bM4_DMA1_RPTB3_SRPTB2 (*((volatile unsigned int*)(0x42A62188UL))) +#define bM4_DMA1_RPTB3_SRPTB3 (*((volatile unsigned int*)(0x42A6218CUL))) +#define bM4_DMA1_RPTB3_SRPTB4 (*((volatile unsigned int*)(0x42A62190UL))) +#define bM4_DMA1_RPTB3_SRPTB5 (*((volatile unsigned int*)(0x42A62194UL))) +#define bM4_DMA1_RPTB3_SRPTB6 (*((volatile unsigned int*)(0x42A62198UL))) +#define bM4_DMA1_RPTB3_SRPTB7 (*((volatile unsigned int*)(0x42A6219CUL))) +#define bM4_DMA1_RPTB3_SRPTB8 (*((volatile unsigned int*)(0x42A621A0UL))) +#define bM4_DMA1_RPTB3_SRPTB9 (*((volatile unsigned int*)(0x42A621A4UL))) +#define bM4_DMA1_RPTB3_DRPTB0 (*((volatile unsigned int*)(0x42A621C0UL))) +#define bM4_DMA1_RPTB3_DRPTB1 (*((volatile unsigned int*)(0x42A621C4UL))) +#define bM4_DMA1_RPTB3_DRPTB2 (*((volatile unsigned int*)(0x42A621C8UL))) +#define bM4_DMA1_RPTB3_DRPTB3 (*((volatile unsigned int*)(0x42A621CCUL))) +#define bM4_DMA1_RPTB3_DRPTB4 (*((volatile unsigned int*)(0x42A621D0UL))) +#define bM4_DMA1_RPTB3_DRPTB5 (*((volatile unsigned int*)(0x42A621D4UL))) +#define bM4_DMA1_RPTB3_DRPTB6 (*((volatile unsigned int*)(0x42A621D8UL))) +#define bM4_DMA1_RPTB3_DRPTB7 (*((volatile unsigned int*)(0x42A621DCUL))) +#define bM4_DMA1_RPTB3_DRPTB8 (*((volatile unsigned int*)(0x42A621E0UL))) +#define bM4_DMA1_RPTB3_DRPTB9 (*((volatile unsigned int*)(0x42A621E4UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A62200UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A62204UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A62208UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6220CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A62210UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A62214UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A62218UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6221CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A62220UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A62224UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A62228UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6222CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A62230UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A62234UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A62238UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6223CUL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A62240UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A62244UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A62248UL))) +#define bM4_DMA1_SNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6224CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A62250UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A62254UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A62258UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6225CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A62260UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A62264UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A62268UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6226CUL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A62270UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A62274UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A62278UL))) +#define bM4_DMA1_SNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6227CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST0 (*((volatile unsigned int*)(0x42A62200UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST1 (*((volatile unsigned int*)(0x42A62204UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST2 (*((volatile unsigned int*)(0x42A62208UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST3 (*((volatile unsigned int*)(0x42A6220CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST4 (*((volatile unsigned int*)(0x42A62210UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST5 (*((volatile unsigned int*)(0x42A62214UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST6 (*((volatile unsigned int*)(0x42A62218UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST7 (*((volatile unsigned int*)(0x42A6221CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST8 (*((volatile unsigned int*)(0x42A62220UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST9 (*((volatile unsigned int*)(0x42A62224UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST10 (*((volatile unsigned int*)(0x42A62228UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST11 (*((volatile unsigned int*)(0x42A6222CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST12 (*((volatile unsigned int*)(0x42A62230UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST13 (*((volatile unsigned int*)(0x42A62234UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST14 (*((volatile unsigned int*)(0x42A62238UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST15 (*((volatile unsigned int*)(0x42A6223CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST16 (*((volatile unsigned int*)(0x42A62240UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST17 (*((volatile unsigned int*)(0x42A62244UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST18 (*((volatile unsigned int*)(0x42A62248UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSDIST19 (*((volatile unsigned int*)(0x42A6224CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB0 (*((volatile unsigned int*)(0x42A62250UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB1 (*((volatile unsigned int*)(0x42A62254UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB2 (*((volatile unsigned int*)(0x42A62258UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB3 (*((volatile unsigned int*)(0x42A6225CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB4 (*((volatile unsigned int*)(0x42A62260UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB5 (*((volatile unsigned int*)(0x42A62264UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB6 (*((volatile unsigned int*)(0x42A62268UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB7 (*((volatile unsigned int*)(0x42A6226CUL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB8 (*((volatile unsigned int*)(0x42A62270UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB9 (*((volatile unsigned int*)(0x42A62274UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB10 (*((volatile unsigned int*)(0x42A62278UL))) +#define bM4_DMA1_SNSEQCTLB3_SNSCNTB11 (*((volatile unsigned int*)(0x42A6227CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A62280UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A62284UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A62288UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6228CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A62290UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A62294UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A62298UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6229CUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A622A0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A622A4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A622A8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A622ACUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A622B0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A622B4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A622B8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A622BCUL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A622C0UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A622C4UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A622C8UL))) +#define bM4_DMA1_DNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A622CCUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A622D0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A622D4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A622D8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A622DCUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A622E0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A622E4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A622E8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A622ECUL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A622F0UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A622F4UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A622F8UL))) +#define bM4_DMA1_DNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A622FCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST0 (*((volatile unsigned int*)(0x42A62280UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST1 (*((volatile unsigned int*)(0x42A62284UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST2 (*((volatile unsigned int*)(0x42A62288UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST3 (*((volatile unsigned int*)(0x42A6228CUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST4 (*((volatile unsigned int*)(0x42A62290UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST5 (*((volatile unsigned int*)(0x42A62294UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST6 (*((volatile unsigned int*)(0x42A62298UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST7 (*((volatile unsigned int*)(0x42A6229CUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST8 (*((volatile unsigned int*)(0x42A622A0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST9 (*((volatile unsigned int*)(0x42A622A4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST10 (*((volatile unsigned int*)(0x42A622A8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST11 (*((volatile unsigned int*)(0x42A622ACUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST12 (*((volatile unsigned int*)(0x42A622B0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST13 (*((volatile unsigned int*)(0x42A622B4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST14 (*((volatile unsigned int*)(0x42A622B8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST15 (*((volatile unsigned int*)(0x42A622BCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST16 (*((volatile unsigned int*)(0x42A622C0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST17 (*((volatile unsigned int*)(0x42A622C4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST18 (*((volatile unsigned int*)(0x42A622C8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSDIST19 (*((volatile unsigned int*)(0x42A622CCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB0 (*((volatile unsigned int*)(0x42A622D0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB1 (*((volatile unsigned int*)(0x42A622D4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB2 (*((volatile unsigned int*)(0x42A622D8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB3 (*((volatile unsigned int*)(0x42A622DCUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB4 (*((volatile unsigned int*)(0x42A622E0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB5 (*((volatile unsigned int*)(0x42A622E4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB6 (*((volatile unsigned int*)(0x42A622E8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB7 (*((volatile unsigned int*)(0x42A622ECUL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB8 (*((volatile unsigned int*)(0x42A622F0UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB9 (*((volatile unsigned int*)(0x42A622F4UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB10 (*((volatile unsigned int*)(0x42A622F8UL))) +#define bM4_DMA1_DNSEQCTLB3_DNSCNTB11 (*((volatile unsigned int*)(0x42A622FCUL))) +#define bM4_DMA1_LLP3_LLP0 (*((volatile unsigned int*)(0x42A62308UL))) +#define bM4_DMA1_LLP3_LLP1 (*((volatile unsigned int*)(0x42A6230CUL))) +#define bM4_DMA1_LLP3_LLP2 (*((volatile unsigned int*)(0x42A62310UL))) +#define bM4_DMA1_LLP3_LLP3 (*((volatile unsigned int*)(0x42A62314UL))) +#define bM4_DMA1_LLP3_LLP4 (*((volatile unsigned int*)(0x42A62318UL))) +#define bM4_DMA1_LLP3_LLP5 (*((volatile unsigned int*)(0x42A6231CUL))) +#define bM4_DMA1_LLP3_LLP6 (*((volatile unsigned int*)(0x42A62320UL))) +#define bM4_DMA1_LLP3_LLP7 (*((volatile unsigned int*)(0x42A62324UL))) +#define bM4_DMA1_LLP3_LLP8 (*((volatile unsigned int*)(0x42A62328UL))) +#define bM4_DMA1_LLP3_LLP9 (*((volatile unsigned int*)(0x42A6232CUL))) +#define bM4_DMA1_LLP3_LLP10 (*((volatile unsigned int*)(0x42A62330UL))) +#define bM4_DMA1_LLP3_LLP11 (*((volatile unsigned int*)(0x42A62334UL))) +#define bM4_DMA1_LLP3_LLP12 (*((volatile unsigned int*)(0x42A62338UL))) +#define bM4_DMA1_LLP3_LLP13 (*((volatile unsigned int*)(0x42A6233CUL))) +#define bM4_DMA1_LLP3_LLP14 (*((volatile unsigned int*)(0x42A62340UL))) +#define bM4_DMA1_LLP3_LLP15 (*((volatile unsigned int*)(0x42A62344UL))) +#define bM4_DMA1_LLP3_LLP16 (*((volatile unsigned int*)(0x42A62348UL))) +#define bM4_DMA1_LLP3_LLP17 (*((volatile unsigned int*)(0x42A6234CUL))) +#define bM4_DMA1_LLP3_LLP18 (*((volatile unsigned int*)(0x42A62350UL))) +#define bM4_DMA1_LLP3_LLP19 (*((volatile unsigned int*)(0x42A62354UL))) +#define bM4_DMA1_LLP3_LLP20 (*((volatile unsigned int*)(0x42A62358UL))) +#define bM4_DMA1_LLP3_LLP21 (*((volatile unsigned int*)(0x42A6235CUL))) +#define bM4_DMA1_LLP3_LLP22 (*((volatile unsigned int*)(0x42A62360UL))) +#define bM4_DMA1_LLP3_LLP23 (*((volatile unsigned int*)(0x42A62364UL))) +#define bM4_DMA1_LLP3_LLP24 (*((volatile unsigned int*)(0x42A62368UL))) +#define bM4_DMA1_LLP3_LLP25 (*((volatile unsigned int*)(0x42A6236CUL))) +#define bM4_DMA1_LLP3_LLP26 (*((volatile unsigned int*)(0x42A62370UL))) +#define bM4_DMA1_LLP3_LLP27 (*((volatile unsigned int*)(0x42A62374UL))) +#define bM4_DMA1_LLP3_LLP28 (*((volatile unsigned int*)(0x42A62378UL))) +#define bM4_DMA1_LLP3_LLP29 (*((volatile unsigned int*)(0x42A6237CUL))) +#define bM4_DMA1_CH3CTL_SINC0 (*((volatile unsigned int*)(0x42A62380UL))) +#define bM4_DMA1_CH3CTL_SINC1 (*((volatile unsigned int*)(0x42A62384UL))) +#define bM4_DMA1_CH3CTL_DINC0 (*((volatile unsigned int*)(0x42A62388UL))) +#define bM4_DMA1_CH3CTL_DINC1 (*((volatile unsigned int*)(0x42A6238CUL))) +#define bM4_DMA1_CH3CTL_SRPTEN (*((volatile unsigned int*)(0x42A62390UL))) +#define bM4_DMA1_CH3CTL_DRPTEN (*((volatile unsigned int*)(0x42A62394UL))) +#define bM4_DMA1_CH3CTL_SNSEQEN (*((volatile unsigned int*)(0x42A62398UL))) +#define bM4_DMA1_CH3CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6239CUL))) +#define bM4_DMA1_CH3CTL_HSIZE0 (*((volatile unsigned int*)(0x42A623A0UL))) +#define bM4_DMA1_CH3CTL_HSIZE1 (*((volatile unsigned int*)(0x42A623A4UL))) +#define bM4_DMA1_CH3CTL_LLPEN (*((volatile unsigned int*)(0x42A623A8UL))) +#define bM4_DMA1_CH3CTL_LLPRUN (*((volatile unsigned int*)(0x42A623ACUL))) +#define bM4_DMA1_CH3CTL_IE (*((volatile unsigned int*)(0x42A623B0UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A62500UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A62504UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A62508UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6250CUL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A62510UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A62514UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A62518UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6251CUL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A62520UL))) +#define bM4_DMA1_MONDTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A62524UL))) +#define bM4_DMA1_MONDTCTL3_CNT0 (*((volatile unsigned int*)(0x42A62540UL))) +#define bM4_DMA1_MONDTCTL3_CNT1 (*((volatile unsigned int*)(0x42A62544UL))) +#define bM4_DMA1_MONDTCTL3_CNT2 (*((volatile unsigned int*)(0x42A62548UL))) +#define bM4_DMA1_MONDTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6254CUL))) +#define bM4_DMA1_MONDTCTL3_CNT4 (*((volatile unsigned int*)(0x42A62550UL))) +#define bM4_DMA1_MONDTCTL3_CNT5 (*((volatile unsigned int*)(0x42A62554UL))) +#define bM4_DMA1_MONDTCTL3_CNT6 (*((volatile unsigned int*)(0x42A62558UL))) +#define bM4_DMA1_MONDTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6255CUL))) +#define bM4_DMA1_MONDTCTL3_CNT8 (*((volatile unsigned int*)(0x42A62560UL))) +#define bM4_DMA1_MONDTCTL3_CNT9 (*((volatile unsigned int*)(0x42A62564UL))) +#define bM4_DMA1_MONDTCTL3_CNT10 (*((volatile unsigned int*)(0x42A62568UL))) +#define bM4_DMA1_MONDTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6256CUL))) +#define bM4_DMA1_MONDTCTL3_CNT12 (*((volatile unsigned int*)(0x42A62570UL))) +#define bM4_DMA1_MONDTCTL3_CNT13 (*((volatile unsigned int*)(0x42A62574UL))) +#define bM4_DMA1_MONDTCTL3_CNT14 (*((volatile unsigned int*)(0x42A62578UL))) +#define bM4_DMA1_MONDTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6257CUL))) +#define bM4_DMA1_MONRPT3_SRPT0 (*((volatile unsigned int*)(0x42A62580UL))) +#define bM4_DMA1_MONRPT3_SRPT1 (*((volatile unsigned int*)(0x42A62584UL))) +#define bM4_DMA1_MONRPT3_SRPT2 (*((volatile unsigned int*)(0x42A62588UL))) +#define bM4_DMA1_MONRPT3_SRPT3 (*((volatile unsigned int*)(0x42A6258CUL))) +#define bM4_DMA1_MONRPT3_SRPT4 (*((volatile unsigned int*)(0x42A62590UL))) +#define bM4_DMA1_MONRPT3_SRPT5 (*((volatile unsigned int*)(0x42A62594UL))) +#define bM4_DMA1_MONRPT3_SRPT6 (*((volatile unsigned int*)(0x42A62598UL))) +#define bM4_DMA1_MONRPT3_SRPT7 (*((volatile unsigned int*)(0x42A6259CUL))) +#define bM4_DMA1_MONRPT3_SRPT8 (*((volatile unsigned int*)(0x42A625A0UL))) +#define bM4_DMA1_MONRPT3_SRPT9 (*((volatile unsigned int*)(0x42A625A4UL))) +#define bM4_DMA1_MONRPT3_DRPT0 (*((volatile unsigned int*)(0x42A625C0UL))) +#define bM4_DMA1_MONRPT3_DRPT1 (*((volatile unsigned int*)(0x42A625C4UL))) +#define bM4_DMA1_MONRPT3_DRPT2 (*((volatile unsigned int*)(0x42A625C8UL))) +#define bM4_DMA1_MONRPT3_DRPT3 (*((volatile unsigned int*)(0x42A625CCUL))) +#define bM4_DMA1_MONRPT3_DRPT4 (*((volatile unsigned int*)(0x42A625D0UL))) +#define bM4_DMA1_MONRPT3_DRPT5 (*((volatile unsigned int*)(0x42A625D4UL))) +#define bM4_DMA1_MONRPT3_DRPT6 (*((volatile unsigned int*)(0x42A625D8UL))) +#define bM4_DMA1_MONRPT3_DRPT7 (*((volatile unsigned int*)(0x42A625DCUL))) +#define bM4_DMA1_MONRPT3_DRPT8 (*((volatile unsigned int*)(0x42A625E0UL))) +#define bM4_DMA1_MONRPT3_DRPT9 (*((volatile unsigned int*)(0x42A625E4UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A62600UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A62604UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A62608UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6260CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A62610UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A62614UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A62618UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6261CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A62620UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A62624UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A62628UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6262CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A62630UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A62634UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A62638UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6263CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A62640UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A62644UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A62648UL))) +#define bM4_DMA1_MONSNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6264CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A62650UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A62654UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A62658UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6265CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A62660UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A62664UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A62668UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6266CUL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A62670UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A62674UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A62678UL))) +#define bM4_DMA1_MONSNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6267CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A62680UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A62684UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A62688UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6268CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A62690UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A62694UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A62698UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6269CUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A626A0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A626A4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A626A8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A626ACUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A626B0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A626B4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A626B8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A626BCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A626C0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A626C4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A626C8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A626CCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A626D0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A626D4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A626D8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A626DCUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A626E0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A626E4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A626E8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A626ECUL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A626F0UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A626F4UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A626F8UL))) +#define bM4_DMA1_MONDNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A626FCUL))) +#define bM4_DMA2_EN_EN (*((volatile unsigned int*)(0x42A68000UL))) +#define bM4_DMA2_INTSTAT0_TRNERR0 (*((volatile unsigned int*)(0x42A68080UL))) +#define bM4_DMA2_INTSTAT0_TRNERR1 (*((volatile unsigned int*)(0x42A68084UL))) +#define bM4_DMA2_INTSTAT0_TRNERR2 (*((volatile unsigned int*)(0x42A68088UL))) +#define bM4_DMA2_INTSTAT0_TRNERR3 (*((volatile unsigned int*)(0x42A6808CUL))) +#define bM4_DMA2_INTSTAT0_REQERR0 (*((volatile unsigned int*)(0x42A680C0UL))) +#define bM4_DMA2_INTSTAT0_REQERR1 (*((volatile unsigned int*)(0x42A680C4UL))) +#define bM4_DMA2_INTSTAT0_REQERR2 (*((volatile unsigned int*)(0x42A680C8UL))) +#define bM4_DMA2_INTSTAT0_REQERR3 (*((volatile unsigned int*)(0x42A680CCUL))) +#define bM4_DMA2_INTSTAT1_TC0 (*((volatile unsigned int*)(0x42A68100UL))) +#define bM4_DMA2_INTSTAT1_TC1 (*((volatile unsigned int*)(0x42A68104UL))) +#define bM4_DMA2_INTSTAT1_TC2 (*((volatile unsigned int*)(0x42A68108UL))) +#define bM4_DMA2_INTSTAT1_TC3 (*((volatile unsigned int*)(0x42A6810CUL))) +#define bM4_DMA2_INTSTAT1_BTC0 (*((volatile unsigned int*)(0x42A68140UL))) +#define bM4_DMA2_INTSTAT1_BTC1 (*((volatile unsigned int*)(0x42A68144UL))) +#define bM4_DMA2_INTSTAT1_BTC2 (*((volatile unsigned int*)(0x42A68148UL))) +#define bM4_DMA2_INTSTAT1_BTC3 (*((volatile unsigned int*)(0x42A6814CUL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR0 (*((volatile unsigned int*)(0x42A68180UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR1 (*((volatile unsigned int*)(0x42A68184UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR2 (*((volatile unsigned int*)(0x42A68188UL))) +#define bM4_DMA2_INTMASK0_MSKTRNERR3 (*((volatile unsigned int*)(0x42A6818CUL))) +#define bM4_DMA2_INTMASK0_MSKREQERR0 (*((volatile unsigned int*)(0x42A681C0UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR1 (*((volatile unsigned int*)(0x42A681C4UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR2 (*((volatile unsigned int*)(0x42A681C8UL))) +#define bM4_DMA2_INTMASK0_MSKREQERR3 (*((volatile unsigned int*)(0x42A681CCUL))) +#define bM4_DMA2_INTMASK1_MSKTC0 (*((volatile unsigned int*)(0x42A68200UL))) +#define bM4_DMA2_INTMASK1_MSKTC1 (*((volatile unsigned int*)(0x42A68204UL))) +#define bM4_DMA2_INTMASK1_MSKTC2 (*((volatile unsigned int*)(0x42A68208UL))) +#define bM4_DMA2_INTMASK1_MSKTC3 (*((volatile unsigned int*)(0x42A6820CUL))) +#define bM4_DMA2_INTMASK1_MSKBTC0 (*((volatile unsigned int*)(0x42A68240UL))) +#define bM4_DMA2_INTMASK1_MSKBTC1 (*((volatile unsigned int*)(0x42A68244UL))) +#define bM4_DMA2_INTMASK1_MSKBTC2 (*((volatile unsigned int*)(0x42A68248UL))) +#define bM4_DMA2_INTMASK1_MSKBTC3 (*((volatile unsigned int*)(0x42A6824CUL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR0 (*((volatile unsigned int*)(0x42A68280UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR1 (*((volatile unsigned int*)(0x42A68284UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR2 (*((volatile unsigned int*)(0x42A68288UL))) +#define bM4_DMA2_INTCLR0_CLRTRNERR3 (*((volatile unsigned int*)(0x42A6828CUL))) +#define bM4_DMA2_INTCLR0_CLRREQERR0 (*((volatile unsigned int*)(0x42A682C0UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR1 (*((volatile unsigned int*)(0x42A682C4UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR2 (*((volatile unsigned int*)(0x42A682C8UL))) +#define bM4_DMA2_INTCLR0_CLRREQERR3 (*((volatile unsigned int*)(0x42A682CCUL))) +#define bM4_DMA2_INTCLR1_CLRTC0 (*((volatile unsigned int*)(0x42A68300UL))) +#define bM4_DMA2_INTCLR1_CLRTC1 (*((volatile unsigned int*)(0x42A68304UL))) +#define bM4_DMA2_INTCLR1_CLRTC2 (*((volatile unsigned int*)(0x42A68308UL))) +#define bM4_DMA2_INTCLR1_CLRTC3 (*((volatile unsigned int*)(0x42A6830CUL))) +#define bM4_DMA2_INTCLR1_CLRBTC0 (*((volatile unsigned int*)(0x42A68340UL))) +#define bM4_DMA2_INTCLR1_CLRBTC1 (*((volatile unsigned int*)(0x42A68344UL))) +#define bM4_DMA2_INTCLR1_CLRBTC2 (*((volatile unsigned int*)(0x42A68348UL))) +#define bM4_DMA2_INTCLR1_CLRBTC3 (*((volatile unsigned int*)(0x42A6834CUL))) +#define bM4_DMA2_CHEN_CHEN0 (*((volatile unsigned int*)(0x42A68380UL))) +#define bM4_DMA2_CHEN_CHEN1 (*((volatile unsigned int*)(0x42A68384UL))) +#define bM4_DMA2_CHEN_CHEN2 (*((volatile unsigned int*)(0x42A68388UL))) +#define bM4_DMA2_CHEN_CHEN3 (*((volatile unsigned int*)(0x42A6838CUL))) +#define bM4_DMA2_CHSTAT_DMAACT (*((volatile unsigned int*)(0x42A68480UL))) +#define bM4_DMA2_CHSTAT_RCFGACT (*((volatile unsigned int*)(0x42A68484UL))) +#define bM4_DMA2_CHSTAT_CHACT0 (*((volatile unsigned int*)(0x42A684C0UL))) +#define bM4_DMA2_CHSTAT_CHACT1 (*((volatile unsigned int*)(0x42A684C4UL))) +#define bM4_DMA2_CHSTAT_CHACT2 (*((volatile unsigned int*)(0x42A684C8UL))) +#define bM4_DMA2_CHSTAT_CHACT3 (*((volatile unsigned int*)(0x42A684CCUL))) +#define bM4_DMA2_RCFGCTL_RCFGEN (*((volatile unsigned int*)(0x42A68580UL))) +#define bM4_DMA2_RCFGCTL_RCFGLLP (*((volatile unsigned int*)(0x42A68584UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS0 (*((volatile unsigned int*)(0x42A685A0UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS1 (*((volatile unsigned int*)(0x42A685A4UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS2 (*((volatile unsigned int*)(0x42A685A8UL))) +#define bM4_DMA2_RCFGCTL_RCFGCHS3 (*((volatile unsigned int*)(0x42A685ACUL))) +#define bM4_DMA2_RCFGCTL_SARMD0 (*((volatile unsigned int*)(0x42A685C0UL))) +#define bM4_DMA2_RCFGCTL_SARMD1 (*((volatile unsigned int*)(0x42A685C4UL))) +#define bM4_DMA2_RCFGCTL_DARMD0 (*((volatile unsigned int*)(0x42A685C8UL))) +#define bM4_DMA2_RCFGCTL_DARMD1 (*((volatile unsigned int*)(0x42A685CCUL))) +#define bM4_DMA2_RCFGCTL_CNTMD0 (*((volatile unsigned int*)(0x42A685D0UL))) +#define bM4_DMA2_RCFGCTL_CNTMD1 (*((volatile unsigned int*)(0x42A685D4UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A68900UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A68904UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A68908UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A6890CUL))) +#define bM4_DMA2_DTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A68910UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A68914UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A68918UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A6891CUL))) +#define bM4_DMA2_DTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A68920UL))) +#define bM4_DMA2_DTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A68924UL))) +#define bM4_DMA2_DTCTL0_CNT0 (*((volatile unsigned int*)(0x42A68940UL))) +#define bM4_DMA2_DTCTL0_CNT1 (*((volatile unsigned int*)(0x42A68944UL))) +#define bM4_DMA2_DTCTL0_CNT2 (*((volatile unsigned int*)(0x42A68948UL))) +#define bM4_DMA2_DTCTL0_CNT3 (*((volatile unsigned int*)(0x42A6894CUL))) +#define bM4_DMA2_DTCTL0_CNT4 (*((volatile unsigned int*)(0x42A68950UL))) +#define bM4_DMA2_DTCTL0_CNT5 (*((volatile unsigned int*)(0x42A68954UL))) +#define bM4_DMA2_DTCTL0_CNT6 (*((volatile unsigned int*)(0x42A68958UL))) +#define bM4_DMA2_DTCTL0_CNT7 (*((volatile unsigned int*)(0x42A6895CUL))) +#define bM4_DMA2_DTCTL0_CNT8 (*((volatile unsigned int*)(0x42A68960UL))) +#define bM4_DMA2_DTCTL0_CNT9 (*((volatile unsigned int*)(0x42A68964UL))) +#define bM4_DMA2_DTCTL0_CNT10 (*((volatile unsigned int*)(0x42A68968UL))) +#define bM4_DMA2_DTCTL0_CNT11 (*((volatile unsigned int*)(0x42A6896CUL))) +#define bM4_DMA2_DTCTL0_CNT12 (*((volatile unsigned int*)(0x42A68970UL))) +#define bM4_DMA2_DTCTL0_CNT13 (*((volatile unsigned int*)(0x42A68974UL))) +#define bM4_DMA2_DTCTL0_CNT14 (*((volatile unsigned int*)(0x42A68978UL))) +#define bM4_DMA2_DTCTL0_CNT15 (*((volatile unsigned int*)(0x42A6897CUL))) +#define bM4_DMA2_RPT0_SRPT0 (*((volatile unsigned int*)(0x42A68980UL))) +#define bM4_DMA2_RPT0_SRPT1 (*((volatile unsigned int*)(0x42A68984UL))) +#define bM4_DMA2_RPT0_SRPT2 (*((volatile unsigned int*)(0x42A68988UL))) +#define bM4_DMA2_RPT0_SRPT3 (*((volatile unsigned int*)(0x42A6898CUL))) +#define bM4_DMA2_RPT0_SRPT4 (*((volatile unsigned int*)(0x42A68990UL))) +#define bM4_DMA2_RPT0_SRPT5 (*((volatile unsigned int*)(0x42A68994UL))) +#define bM4_DMA2_RPT0_SRPT6 (*((volatile unsigned int*)(0x42A68998UL))) +#define bM4_DMA2_RPT0_SRPT7 (*((volatile unsigned int*)(0x42A6899CUL))) +#define bM4_DMA2_RPT0_SRPT8 (*((volatile unsigned int*)(0x42A689A0UL))) +#define bM4_DMA2_RPT0_SRPT9 (*((volatile unsigned int*)(0x42A689A4UL))) +#define bM4_DMA2_RPT0_DRPT0 (*((volatile unsigned int*)(0x42A689C0UL))) +#define bM4_DMA2_RPT0_DRPT1 (*((volatile unsigned int*)(0x42A689C4UL))) +#define bM4_DMA2_RPT0_DRPT2 (*((volatile unsigned int*)(0x42A689C8UL))) +#define bM4_DMA2_RPT0_DRPT3 (*((volatile unsigned int*)(0x42A689CCUL))) +#define bM4_DMA2_RPT0_DRPT4 (*((volatile unsigned int*)(0x42A689D0UL))) +#define bM4_DMA2_RPT0_DRPT5 (*((volatile unsigned int*)(0x42A689D4UL))) +#define bM4_DMA2_RPT0_DRPT6 (*((volatile unsigned int*)(0x42A689D8UL))) +#define bM4_DMA2_RPT0_DRPT7 (*((volatile unsigned int*)(0x42A689DCUL))) +#define bM4_DMA2_RPT0_DRPT8 (*((volatile unsigned int*)(0x42A689E0UL))) +#define bM4_DMA2_RPT0_DRPT9 (*((volatile unsigned int*)(0x42A689E4UL))) +#define bM4_DMA2_RPTB0_SRPTB0 (*((volatile unsigned int*)(0x42A68980UL))) +#define bM4_DMA2_RPTB0_SRPTB1 (*((volatile unsigned int*)(0x42A68984UL))) +#define bM4_DMA2_RPTB0_SRPTB2 (*((volatile unsigned int*)(0x42A68988UL))) +#define bM4_DMA2_RPTB0_SRPTB3 (*((volatile unsigned int*)(0x42A6898CUL))) +#define bM4_DMA2_RPTB0_SRPTB4 (*((volatile unsigned int*)(0x42A68990UL))) +#define bM4_DMA2_RPTB0_SRPTB5 (*((volatile unsigned int*)(0x42A68994UL))) +#define bM4_DMA2_RPTB0_SRPTB6 (*((volatile unsigned int*)(0x42A68998UL))) +#define bM4_DMA2_RPTB0_SRPTB7 (*((volatile unsigned int*)(0x42A6899CUL))) +#define bM4_DMA2_RPTB0_SRPTB8 (*((volatile unsigned int*)(0x42A689A0UL))) +#define bM4_DMA2_RPTB0_SRPTB9 (*((volatile unsigned int*)(0x42A689A4UL))) +#define bM4_DMA2_RPTB0_DRPTB0 (*((volatile unsigned int*)(0x42A689C0UL))) +#define bM4_DMA2_RPTB0_DRPTB1 (*((volatile unsigned int*)(0x42A689C4UL))) +#define bM4_DMA2_RPTB0_DRPTB2 (*((volatile unsigned int*)(0x42A689C8UL))) +#define bM4_DMA2_RPTB0_DRPTB3 (*((volatile unsigned int*)(0x42A689CCUL))) +#define bM4_DMA2_RPTB0_DRPTB4 (*((volatile unsigned int*)(0x42A689D0UL))) +#define bM4_DMA2_RPTB0_DRPTB5 (*((volatile unsigned int*)(0x42A689D4UL))) +#define bM4_DMA2_RPTB0_DRPTB6 (*((volatile unsigned int*)(0x42A689D8UL))) +#define bM4_DMA2_RPTB0_DRPTB7 (*((volatile unsigned int*)(0x42A689DCUL))) +#define bM4_DMA2_RPTB0_DRPTB8 (*((volatile unsigned int*)(0x42A689E0UL))) +#define bM4_DMA2_RPTB0_DRPTB9 (*((volatile unsigned int*)(0x42A689E4UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A68A00UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A68A04UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A68A08UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A68A0CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A68A10UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A68A14UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A68A18UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A68A1CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A68A20UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A68A24UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A68A28UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A68A2CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A68A30UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A68A34UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A68A38UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A68A3CUL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A68A40UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A68A44UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A68A48UL))) +#define bM4_DMA2_SNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A68A4CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A68A50UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A68A54UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A68A58UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A68A5CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A68A60UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A68A64UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A68A68UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A68A6CUL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A68A70UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A68A74UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A68A78UL))) +#define bM4_DMA2_SNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A68A7CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST0 (*((volatile unsigned int*)(0x42A68A00UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST1 (*((volatile unsigned int*)(0x42A68A04UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST2 (*((volatile unsigned int*)(0x42A68A08UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST3 (*((volatile unsigned int*)(0x42A68A0CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST4 (*((volatile unsigned int*)(0x42A68A10UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST5 (*((volatile unsigned int*)(0x42A68A14UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST6 (*((volatile unsigned int*)(0x42A68A18UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST7 (*((volatile unsigned int*)(0x42A68A1CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST8 (*((volatile unsigned int*)(0x42A68A20UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST9 (*((volatile unsigned int*)(0x42A68A24UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST10 (*((volatile unsigned int*)(0x42A68A28UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST11 (*((volatile unsigned int*)(0x42A68A2CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST12 (*((volatile unsigned int*)(0x42A68A30UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST13 (*((volatile unsigned int*)(0x42A68A34UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST14 (*((volatile unsigned int*)(0x42A68A38UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST15 (*((volatile unsigned int*)(0x42A68A3CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST16 (*((volatile unsigned int*)(0x42A68A40UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST17 (*((volatile unsigned int*)(0x42A68A44UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST18 (*((volatile unsigned int*)(0x42A68A48UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSDIST19 (*((volatile unsigned int*)(0x42A68A4CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB0 (*((volatile unsigned int*)(0x42A68A50UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB1 (*((volatile unsigned int*)(0x42A68A54UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB2 (*((volatile unsigned int*)(0x42A68A58UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB3 (*((volatile unsigned int*)(0x42A68A5CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB4 (*((volatile unsigned int*)(0x42A68A60UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB5 (*((volatile unsigned int*)(0x42A68A64UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB6 (*((volatile unsigned int*)(0x42A68A68UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB7 (*((volatile unsigned int*)(0x42A68A6CUL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB8 (*((volatile unsigned int*)(0x42A68A70UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB9 (*((volatile unsigned int*)(0x42A68A74UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB10 (*((volatile unsigned int*)(0x42A68A78UL))) +#define bM4_DMA2_SNSEQCTLB0_SNSCNTB11 (*((volatile unsigned int*)(0x42A68A7CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A68A80UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A68A84UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A68A88UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A68A8CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A68A90UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A68A94UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A68A98UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A68A9CUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A68AA0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A68AA4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A68AA8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A68AACUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A68AB0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A68AB4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A68AB8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A68ABCUL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A68AC0UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A68AC4UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A68AC8UL))) +#define bM4_DMA2_DNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A68ACCUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A68AD0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A68AD4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A68AD8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A68ADCUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A68AE0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A68AE4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A68AE8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A68AECUL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A68AF0UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A68AF4UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A68AF8UL))) +#define bM4_DMA2_DNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A68AFCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST0 (*((volatile unsigned int*)(0x42A68A80UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST1 (*((volatile unsigned int*)(0x42A68A84UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST2 (*((volatile unsigned int*)(0x42A68A88UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST3 (*((volatile unsigned int*)(0x42A68A8CUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST4 (*((volatile unsigned int*)(0x42A68A90UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST5 (*((volatile unsigned int*)(0x42A68A94UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST6 (*((volatile unsigned int*)(0x42A68A98UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST7 (*((volatile unsigned int*)(0x42A68A9CUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST8 (*((volatile unsigned int*)(0x42A68AA0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST9 (*((volatile unsigned int*)(0x42A68AA4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST10 (*((volatile unsigned int*)(0x42A68AA8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST11 (*((volatile unsigned int*)(0x42A68AACUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST12 (*((volatile unsigned int*)(0x42A68AB0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST13 (*((volatile unsigned int*)(0x42A68AB4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST14 (*((volatile unsigned int*)(0x42A68AB8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST15 (*((volatile unsigned int*)(0x42A68ABCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST16 (*((volatile unsigned int*)(0x42A68AC0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST17 (*((volatile unsigned int*)(0x42A68AC4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST18 (*((volatile unsigned int*)(0x42A68AC8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSDIST19 (*((volatile unsigned int*)(0x42A68ACCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB0 (*((volatile unsigned int*)(0x42A68AD0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB1 (*((volatile unsigned int*)(0x42A68AD4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB2 (*((volatile unsigned int*)(0x42A68AD8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB3 (*((volatile unsigned int*)(0x42A68ADCUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB4 (*((volatile unsigned int*)(0x42A68AE0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB5 (*((volatile unsigned int*)(0x42A68AE4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB6 (*((volatile unsigned int*)(0x42A68AE8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB7 (*((volatile unsigned int*)(0x42A68AECUL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB8 (*((volatile unsigned int*)(0x42A68AF0UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB9 (*((volatile unsigned int*)(0x42A68AF4UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB10 (*((volatile unsigned int*)(0x42A68AF8UL))) +#define bM4_DMA2_DNSEQCTLB0_DNSCNTB11 (*((volatile unsigned int*)(0x42A68AFCUL))) +#define bM4_DMA2_LLP0_LLP0 (*((volatile unsigned int*)(0x42A68B08UL))) +#define bM4_DMA2_LLP0_LLP1 (*((volatile unsigned int*)(0x42A68B0CUL))) +#define bM4_DMA2_LLP0_LLP2 (*((volatile unsigned int*)(0x42A68B10UL))) +#define bM4_DMA2_LLP0_LLP3 (*((volatile unsigned int*)(0x42A68B14UL))) +#define bM4_DMA2_LLP0_LLP4 (*((volatile unsigned int*)(0x42A68B18UL))) +#define bM4_DMA2_LLP0_LLP5 (*((volatile unsigned int*)(0x42A68B1CUL))) +#define bM4_DMA2_LLP0_LLP6 (*((volatile unsigned int*)(0x42A68B20UL))) +#define bM4_DMA2_LLP0_LLP7 (*((volatile unsigned int*)(0x42A68B24UL))) +#define bM4_DMA2_LLP0_LLP8 (*((volatile unsigned int*)(0x42A68B28UL))) +#define bM4_DMA2_LLP0_LLP9 (*((volatile unsigned int*)(0x42A68B2CUL))) +#define bM4_DMA2_LLP0_LLP10 (*((volatile unsigned int*)(0x42A68B30UL))) +#define bM4_DMA2_LLP0_LLP11 (*((volatile unsigned int*)(0x42A68B34UL))) +#define bM4_DMA2_LLP0_LLP12 (*((volatile unsigned int*)(0x42A68B38UL))) +#define bM4_DMA2_LLP0_LLP13 (*((volatile unsigned int*)(0x42A68B3CUL))) +#define bM4_DMA2_LLP0_LLP14 (*((volatile unsigned int*)(0x42A68B40UL))) +#define bM4_DMA2_LLP0_LLP15 (*((volatile unsigned int*)(0x42A68B44UL))) +#define bM4_DMA2_LLP0_LLP16 (*((volatile unsigned int*)(0x42A68B48UL))) +#define bM4_DMA2_LLP0_LLP17 (*((volatile unsigned int*)(0x42A68B4CUL))) +#define bM4_DMA2_LLP0_LLP18 (*((volatile unsigned int*)(0x42A68B50UL))) +#define bM4_DMA2_LLP0_LLP19 (*((volatile unsigned int*)(0x42A68B54UL))) +#define bM4_DMA2_LLP0_LLP20 (*((volatile unsigned int*)(0x42A68B58UL))) +#define bM4_DMA2_LLP0_LLP21 (*((volatile unsigned int*)(0x42A68B5CUL))) +#define bM4_DMA2_LLP0_LLP22 (*((volatile unsigned int*)(0x42A68B60UL))) +#define bM4_DMA2_LLP0_LLP23 (*((volatile unsigned int*)(0x42A68B64UL))) +#define bM4_DMA2_LLP0_LLP24 (*((volatile unsigned int*)(0x42A68B68UL))) +#define bM4_DMA2_LLP0_LLP25 (*((volatile unsigned int*)(0x42A68B6CUL))) +#define bM4_DMA2_LLP0_LLP26 (*((volatile unsigned int*)(0x42A68B70UL))) +#define bM4_DMA2_LLP0_LLP27 (*((volatile unsigned int*)(0x42A68B74UL))) +#define bM4_DMA2_LLP0_LLP28 (*((volatile unsigned int*)(0x42A68B78UL))) +#define bM4_DMA2_LLP0_LLP29 (*((volatile unsigned int*)(0x42A68B7CUL))) +#define bM4_DMA2_CH0CTL_SINC0 (*((volatile unsigned int*)(0x42A68B80UL))) +#define bM4_DMA2_CH0CTL_SINC1 (*((volatile unsigned int*)(0x42A68B84UL))) +#define bM4_DMA2_CH0CTL_DINC0 (*((volatile unsigned int*)(0x42A68B88UL))) +#define bM4_DMA2_CH0CTL_DINC1 (*((volatile unsigned int*)(0x42A68B8CUL))) +#define bM4_DMA2_CH0CTL_SRPTEN (*((volatile unsigned int*)(0x42A68B90UL))) +#define bM4_DMA2_CH0CTL_DRPTEN (*((volatile unsigned int*)(0x42A68B94UL))) +#define bM4_DMA2_CH0CTL_SNSEQEN (*((volatile unsigned int*)(0x42A68B98UL))) +#define bM4_DMA2_CH0CTL_DNSEQEN (*((volatile unsigned int*)(0x42A68B9CUL))) +#define bM4_DMA2_CH0CTL_HSIZE0 (*((volatile unsigned int*)(0x42A68BA0UL))) +#define bM4_DMA2_CH0CTL_HSIZE1 (*((volatile unsigned int*)(0x42A68BA4UL))) +#define bM4_DMA2_CH0CTL_LLPEN (*((volatile unsigned int*)(0x42A68BA8UL))) +#define bM4_DMA2_CH0CTL_LLPRUN (*((volatile unsigned int*)(0x42A68BACUL))) +#define bM4_DMA2_CH0CTL_IE (*((volatile unsigned int*)(0x42A68BB0UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE0 (*((volatile unsigned int*)(0x42A68D00UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE1 (*((volatile unsigned int*)(0x42A68D04UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE2 (*((volatile unsigned int*)(0x42A68D08UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE3 (*((volatile unsigned int*)(0x42A68D0CUL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE4 (*((volatile unsigned int*)(0x42A68D10UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE5 (*((volatile unsigned int*)(0x42A68D14UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE6 (*((volatile unsigned int*)(0x42A68D18UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE7 (*((volatile unsigned int*)(0x42A68D1CUL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE8 (*((volatile unsigned int*)(0x42A68D20UL))) +#define bM4_DMA2_MONDTCTL0_BLKSIZE9 (*((volatile unsigned int*)(0x42A68D24UL))) +#define bM4_DMA2_MONDTCTL0_CNT0 (*((volatile unsigned int*)(0x42A68D40UL))) +#define bM4_DMA2_MONDTCTL0_CNT1 (*((volatile unsigned int*)(0x42A68D44UL))) +#define bM4_DMA2_MONDTCTL0_CNT2 (*((volatile unsigned int*)(0x42A68D48UL))) +#define bM4_DMA2_MONDTCTL0_CNT3 (*((volatile unsigned int*)(0x42A68D4CUL))) +#define bM4_DMA2_MONDTCTL0_CNT4 (*((volatile unsigned int*)(0x42A68D50UL))) +#define bM4_DMA2_MONDTCTL0_CNT5 (*((volatile unsigned int*)(0x42A68D54UL))) +#define bM4_DMA2_MONDTCTL0_CNT6 (*((volatile unsigned int*)(0x42A68D58UL))) +#define bM4_DMA2_MONDTCTL0_CNT7 (*((volatile unsigned int*)(0x42A68D5CUL))) +#define bM4_DMA2_MONDTCTL0_CNT8 (*((volatile unsigned int*)(0x42A68D60UL))) +#define bM4_DMA2_MONDTCTL0_CNT9 (*((volatile unsigned int*)(0x42A68D64UL))) +#define bM4_DMA2_MONDTCTL0_CNT10 (*((volatile unsigned int*)(0x42A68D68UL))) +#define bM4_DMA2_MONDTCTL0_CNT11 (*((volatile unsigned int*)(0x42A68D6CUL))) +#define bM4_DMA2_MONDTCTL0_CNT12 (*((volatile unsigned int*)(0x42A68D70UL))) +#define bM4_DMA2_MONDTCTL0_CNT13 (*((volatile unsigned int*)(0x42A68D74UL))) +#define bM4_DMA2_MONDTCTL0_CNT14 (*((volatile unsigned int*)(0x42A68D78UL))) +#define bM4_DMA2_MONDTCTL0_CNT15 (*((volatile unsigned int*)(0x42A68D7CUL))) +#define bM4_DMA2_MONRPT0_SRPT0 (*((volatile unsigned int*)(0x42A68D80UL))) +#define bM4_DMA2_MONRPT0_SRPT1 (*((volatile unsigned int*)(0x42A68D84UL))) +#define bM4_DMA2_MONRPT0_SRPT2 (*((volatile unsigned int*)(0x42A68D88UL))) +#define bM4_DMA2_MONRPT0_SRPT3 (*((volatile unsigned int*)(0x42A68D8CUL))) +#define bM4_DMA2_MONRPT0_SRPT4 (*((volatile unsigned int*)(0x42A68D90UL))) +#define bM4_DMA2_MONRPT0_SRPT5 (*((volatile unsigned int*)(0x42A68D94UL))) +#define bM4_DMA2_MONRPT0_SRPT6 (*((volatile unsigned int*)(0x42A68D98UL))) +#define bM4_DMA2_MONRPT0_SRPT7 (*((volatile unsigned int*)(0x42A68D9CUL))) +#define bM4_DMA2_MONRPT0_SRPT8 (*((volatile unsigned int*)(0x42A68DA0UL))) +#define bM4_DMA2_MONRPT0_SRPT9 (*((volatile unsigned int*)(0x42A68DA4UL))) +#define bM4_DMA2_MONRPT0_DRPT0 (*((volatile unsigned int*)(0x42A68DC0UL))) +#define bM4_DMA2_MONRPT0_DRPT1 (*((volatile unsigned int*)(0x42A68DC4UL))) +#define bM4_DMA2_MONRPT0_DRPT2 (*((volatile unsigned int*)(0x42A68DC8UL))) +#define bM4_DMA2_MONRPT0_DRPT3 (*((volatile unsigned int*)(0x42A68DCCUL))) +#define bM4_DMA2_MONRPT0_DRPT4 (*((volatile unsigned int*)(0x42A68DD0UL))) +#define bM4_DMA2_MONRPT0_DRPT5 (*((volatile unsigned int*)(0x42A68DD4UL))) +#define bM4_DMA2_MONRPT0_DRPT6 (*((volatile unsigned int*)(0x42A68DD8UL))) +#define bM4_DMA2_MONRPT0_DRPT7 (*((volatile unsigned int*)(0x42A68DDCUL))) +#define bM4_DMA2_MONRPT0_DRPT8 (*((volatile unsigned int*)(0x42A68DE0UL))) +#define bM4_DMA2_MONRPT0_DRPT9 (*((volatile unsigned int*)(0x42A68DE4UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET0 (*((volatile unsigned int*)(0x42A68E00UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET1 (*((volatile unsigned int*)(0x42A68E04UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET2 (*((volatile unsigned int*)(0x42A68E08UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET3 (*((volatile unsigned int*)(0x42A68E0CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET4 (*((volatile unsigned int*)(0x42A68E10UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET5 (*((volatile unsigned int*)(0x42A68E14UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET6 (*((volatile unsigned int*)(0x42A68E18UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET7 (*((volatile unsigned int*)(0x42A68E1CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET8 (*((volatile unsigned int*)(0x42A68E20UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET9 (*((volatile unsigned int*)(0x42A68E24UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET10 (*((volatile unsigned int*)(0x42A68E28UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET11 (*((volatile unsigned int*)(0x42A68E2CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET12 (*((volatile unsigned int*)(0x42A68E30UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET13 (*((volatile unsigned int*)(0x42A68E34UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET14 (*((volatile unsigned int*)(0x42A68E38UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET15 (*((volatile unsigned int*)(0x42A68E3CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET16 (*((volatile unsigned int*)(0x42A68E40UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET17 (*((volatile unsigned int*)(0x42A68E44UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET18 (*((volatile unsigned int*)(0x42A68E48UL))) +#define bM4_DMA2_MONSNSEQCTL0_SOFFSET19 (*((volatile unsigned int*)(0x42A68E4CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT0 (*((volatile unsigned int*)(0x42A68E50UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT1 (*((volatile unsigned int*)(0x42A68E54UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT2 (*((volatile unsigned int*)(0x42A68E58UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT3 (*((volatile unsigned int*)(0x42A68E5CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT4 (*((volatile unsigned int*)(0x42A68E60UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT5 (*((volatile unsigned int*)(0x42A68E64UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT6 (*((volatile unsigned int*)(0x42A68E68UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT7 (*((volatile unsigned int*)(0x42A68E6CUL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT8 (*((volatile unsigned int*)(0x42A68E70UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT9 (*((volatile unsigned int*)(0x42A68E74UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT10 (*((volatile unsigned int*)(0x42A68E78UL))) +#define bM4_DMA2_MONSNSEQCTL0_SNSCNT11 (*((volatile unsigned int*)(0x42A68E7CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET0 (*((volatile unsigned int*)(0x42A68E80UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET1 (*((volatile unsigned int*)(0x42A68E84UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET2 (*((volatile unsigned int*)(0x42A68E88UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET3 (*((volatile unsigned int*)(0x42A68E8CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET4 (*((volatile unsigned int*)(0x42A68E90UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET5 (*((volatile unsigned int*)(0x42A68E94UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET6 (*((volatile unsigned int*)(0x42A68E98UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET7 (*((volatile unsigned int*)(0x42A68E9CUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET8 (*((volatile unsigned int*)(0x42A68EA0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET9 (*((volatile unsigned int*)(0x42A68EA4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET10 (*((volatile unsigned int*)(0x42A68EA8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET11 (*((volatile unsigned int*)(0x42A68EACUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET12 (*((volatile unsigned int*)(0x42A68EB0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET13 (*((volatile unsigned int*)(0x42A68EB4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET14 (*((volatile unsigned int*)(0x42A68EB8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET15 (*((volatile unsigned int*)(0x42A68EBCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET16 (*((volatile unsigned int*)(0x42A68EC0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET17 (*((volatile unsigned int*)(0x42A68EC4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET18 (*((volatile unsigned int*)(0x42A68EC8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DOFFSET19 (*((volatile unsigned int*)(0x42A68ECCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT0 (*((volatile unsigned int*)(0x42A68ED0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT1 (*((volatile unsigned int*)(0x42A68ED4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT2 (*((volatile unsigned int*)(0x42A68ED8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT3 (*((volatile unsigned int*)(0x42A68EDCUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT4 (*((volatile unsigned int*)(0x42A68EE0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT5 (*((volatile unsigned int*)(0x42A68EE4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT6 (*((volatile unsigned int*)(0x42A68EE8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT7 (*((volatile unsigned int*)(0x42A68EECUL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT8 (*((volatile unsigned int*)(0x42A68EF0UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT9 (*((volatile unsigned int*)(0x42A68EF4UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT10 (*((volatile unsigned int*)(0x42A68EF8UL))) +#define bM4_DMA2_MONDNSEQCTL0_DNSCNT11 (*((volatile unsigned int*)(0x42A68EFCUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A69100UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A69104UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A69108UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6910CUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A69110UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A69114UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A69118UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6911CUL))) +#define bM4_DMA2_DTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A69120UL))) +#define bM4_DMA2_DTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A69124UL))) +#define bM4_DMA2_DTCTL1_CNT0 (*((volatile unsigned int*)(0x42A69140UL))) +#define bM4_DMA2_DTCTL1_CNT1 (*((volatile unsigned int*)(0x42A69144UL))) +#define bM4_DMA2_DTCTL1_CNT2 (*((volatile unsigned int*)(0x42A69148UL))) +#define bM4_DMA2_DTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6914CUL))) +#define bM4_DMA2_DTCTL1_CNT4 (*((volatile unsigned int*)(0x42A69150UL))) +#define bM4_DMA2_DTCTL1_CNT5 (*((volatile unsigned int*)(0x42A69154UL))) +#define bM4_DMA2_DTCTL1_CNT6 (*((volatile unsigned int*)(0x42A69158UL))) +#define bM4_DMA2_DTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6915CUL))) +#define bM4_DMA2_DTCTL1_CNT8 (*((volatile unsigned int*)(0x42A69160UL))) +#define bM4_DMA2_DTCTL1_CNT9 (*((volatile unsigned int*)(0x42A69164UL))) +#define bM4_DMA2_DTCTL1_CNT10 (*((volatile unsigned int*)(0x42A69168UL))) +#define bM4_DMA2_DTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6916CUL))) +#define bM4_DMA2_DTCTL1_CNT12 (*((volatile unsigned int*)(0x42A69170UL))) +#define bM4_DMA2_DTCTL1_CNT13 (*((volatile unsigned int*)(0x42A69174UL))) +#define bM4_DMA2_DTCTL1_CNT14 (*((volatile unsigned int*)(0x42A69178UL))) +#define bM4_DMA2_DTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6917CUL))) +#define bM4_DMA2_RPT1_SRPT0 (*((volatile unsigned int*)(0x42A69180UL))) +#define bM4_DMA2_RPT1_SRPT1 (*((volatile unsigned int*)(0x42A69184UL))) +#define bM4_DMA2_RPT1_SRPT2 (*((volatile unsigned int*)(0x42A69188UL))) +#define bM4_DMA2_RPT1_SRPT3 (*((volatile unsigned int*)(0x42A6918CUL))) +#define bM4_DMA2_RPT1_SRPT4 (*((volatile unsigned int*)(0x42A69190UL))) +#define bM4_DMA2_RPT1_SRPT5 (*((volatile unsigned int*)(0x42A69194UL))) +#define bM4_DMA2_RPT1_SRPT6 (*((volatile unsigned int*)(0x42A69198UL))) +#define bM4_DMA2_RPT1_SRPT7 (*((volatile unsigned int*)(0x42A6919CUL))) +#define bM4_DMA2_RPT1_SRPT8 (*((volatile unsigned int*)(0x42A691A0UL))) +#define bM4_DMA2_RPT1_SRPT9 (*((volatile unsigned int*)(0x42A691A4UL))) +#define bM4_DMA2_RPT1_DRPT0 (*((volatile unsigned int*)(0x42A691C0UL))) +#define bM4_DMA2_RPT1_DRPT1 (*((volatile unsigned int*)(0x42A691C4UL))) +#define bM4_DMA2_RPT1_DRPT2 (*((volatile unsigned int*)(0x42A691C8UL))) +#define bM4_DMA2_RPT1_DRPT3 (*((volatile unsigned int*)(0x42A691CCUL))) +#define bM4_DMA2_RPT1_DRPT4 (*((volatile unsigned int*)(0x42A691D0UL))) +#define bM4_DMA2_RPT1_DRPT5 (*((volatile unsigned int*)(0x42A691D4UL))) +#define bM4_DMA2_RPT1_DRPT6 (*((volatile unsigned int*)(0x42A691D8UL))) +#define bM4_DMA2_RPT1_DRPT7 (*((volatile unsigned int*)(0x42A691DCUL))) +#define bM4_DMA2_RPT1_DRPT8 (*((volatile unsigned int*)(0x42A691E0UL))) +#define bM4_DMA2_RPT1_DRPT9 (*((volatile unsigned int*)(0x42A691E4UL))) +#define bM4_DMA2_RPTB1_SRPTB0 (*((volatile unsigned int*)(0x42A69180UL))) +#define bM4_DMA2_RPTB1_SRPTB1 (*((volatile unsigned int*)(0x42A69184UL))) +#define bM4_DMA2_RPTB1_SRPTB2 (*((volatile unsigned int*)(0x42A69188UL))) +#define bM4_DMA2_RPTB1_SRPTB3 (*((volatile unsigned int*)(0x42A6918CUL))) +#define bM4_DMA2_RPTB1_SRPTB4 (*((volatile unsigned int*)(0x42A69190UL))) +#define bM4_DMA2_RPTB1_SRPTB5 (*((volatile unsigned int*)(0x42A69194UL))) +#define bM4_DMA2_RPTB1_SRPTB6 (*((volatile unsigned int*)(0x42A69198UL))) +#define bM4_DMA2_RPTB1_SRPTB7 (*((volatile unsigned int*)(0x42A6919CUL))) +#define bM4_DMA2_RPTB1_SRPTB8 (*((volatile unsigned int*)(0x42A691A0UL))) +#define bM4_DMA2_RPTB1_SRPTB9 (*((volatile unsigned int*)(0x42A691A4UL))) +#define bM4_DMA2_RPTB1_DRPTB0 (*((volatile unsigned int*)(0x42A691C0UL))) +#define bM4_DMA2_RPTB1_DRPTB1 (*((volatile unsigned int*)(0x42A691C4UL))) +#define bM4_DMA2_RPTB1_DRPTB2 (*((volatile unsigned int*)(0x42A691C8UL))) +#define bM4_DMA2_RPTB1_DRPTB3 (*((volatile unsigned int*)(0x42A691CCUL))) +#define bM4_DMA2_RPTB1_DRPTB4 (*((volatile unsigned int*)(0x42A691D0UL))) +#define bM4_DMA2_RPTB1_DRPTB5 (*((volatile unsigned int*)(0x42A691D4UL))) +#define bM4_DMA2_RPTB1_DRPTB6 (*((volatile unsigned int*)(0x42A691D8UL))) +#define bM4_DMA2_RPTB1_DRPTB7 (*((volatile unsigned int*)(0x42A691DCUL))) +#define bM4_DMA2_RPTB1_DRPTB8 (*((volatile unsigned int*)(0x42A691E0UL))) +#define bM4_DMA2_RPTB1_DRPTB9 (*((volatile unsigned int*)(0x42A691E4UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A69200UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A69204UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A69208UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6920CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A69210UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A69214UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A69218UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6921CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A69220UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A69224UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A69228UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6922CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A69230UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A69234UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A69238UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6923CUL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A69240UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A69244UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A69248UL))) +#define bM4_DMA2_SNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6924CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A69250UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A69254UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A69258UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6925CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A69260UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A69264UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A69268UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6926CUL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A69270UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A69274UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A69278UL))) +#define bM4_DMA2_SNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6927CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST0 (*((volatile unsigned int*)(0x42A69200UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST1 (*((volatile unsigned int*)(0x42A69204UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST2 (*((volatile unsigned int*)(0x42A69208UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST3 (*((volatile unsigned int*)(0x42A6920CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST4 (*((volatile unsigned int*)(0x42A69210UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST5 (*((volatile unsigned int*)(0x42A69214UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST6 (*((volatile unsigned int*)(0x42A69218UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST7 (*((volatile unsigned int*)(0x42A6921CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST8 (*((volatile unsigned int*)(0x42A69220UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST9 (*((volatile unsigned int*)(0x42A69224UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST10 (*((volatile unsigned int*)(0x42A69228UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST11 (*((volatile unsigned int*)(0x42A6922CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST12 (*((volatile unsigned int*)(0x42A69230UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST13 (*((volatile unsigned int*)(0x42A69234UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST14 (*((volatile unsigned int*)(0x42A69238UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST15 (*((volatile unsigned int*)(0x42A6923CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST16 (*((volatile unsigned int*)(0x42A69240UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST17 (*((volatile unsigned int*)(0x42A69244UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST18 (*((volatile unsigned int*)(0x42A69248UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSDIST19 (*((volatile unsigned int*)(0x42A6924CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB0 (*((volatile unsigned int*)(0x42A69250UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB1 (*((volatile unsigned int*)(0x42A69254UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB2 (*((volatile unsigned int*)(0x42A69258UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB3 (*((volatile unsigned int*)(0x42A6925CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB4 (*((volatile unsigned int*)(0x42A69260UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB5 (*((volatile unsigned int*)(0x42A69264UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB6 (*((volatile unsigned int*)(0x42A69268UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB7 (*((volatile unsigned int*)(0x42A6926CUL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB8 (*((volatile unsigned int*)(0x42A69270UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB9 (*((volatile unsigned int*)(0x42A69274UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB10 (*((volatile unsigned int*)(0x42A69278UL))) +#define bM4_DMA2_SNSEQCTLB1_SNSCNTB11 (*((volatile unsigned int*)(0x42A6927CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A69280UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A69284UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A69288UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6928CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A69290UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A69294UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A69298UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6929CUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A692A0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A692A4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A692A8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A692ACUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A692B0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A692B4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A692B8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A692BCUL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A692C0UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A692C4UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A692C8UL))) +#define bM4_DMA2_DNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A692CCUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A692D0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A692D4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A692D8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A692DCUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A692E0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A692E4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A692E8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A692ECUL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A692F0UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A692F4UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A692F8UL))) +#define bM4_DMA2_DNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A692FCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST0 (*((volatile unsigned int*)(0x42A69280UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST1 (*((volatile unsigned int*)(0x42A69284UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST2 (*((volatile unsigned int*)(0x42A69288UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST3 (*((volatile unsigned int*)(0x42A6928CUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST4 (*((volatile unsigned int*)(0x42A69290UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST5 (*((volatile unsigned int*)(0x42A69294UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST6 (*((volatile unsigned int*)(0x42A69298UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST7 (*((volatile unsigned int*)(0x42A6929CUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST8 (*((volatile unsigned int*)(0x42A692A0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST9 (*((volatile unsigned int*)(0x42A692A4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST10 (*((volatile unsigned int*)(0x42A692A8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST11 (*((volatile unsigned int*)(0x42A692ACUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST12 (*((volatile unsigned int*)(0x42A692B0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST13 (*((volatile unsigned int*)(0x42A692B4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST14 (*((volatile unsigned int*)(0x42A692B8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST15 (*((volatile unsigned int*)(0x42A692BCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST16 (*((volatile unsigned int*)(0x42A692C0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST17 (*((volatile unsigned int*)(0x42A692C4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST18 (*((volatile unsigned int*)(0x42A692C8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSDIST19 (*((volatile unsigned int*)(0x42A692CCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB0 (*((volatile unsigned int*)(0x42A692D0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB1 (*((volatile unsigned int*)(0x42A692D4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB2 (*((volatile unsigned int*)(0x42A692D8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB3 (*((volatile unsigned int*)(0x42A692DCUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB4 (*((volatile unsigned int*)(0x42A692E0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB5 (*((volatile unsigned int*)(0x42A692E4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB6 (*((volatile unsigned int*)(0x42A692E8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB7 (*((volatile unsigned int*)(0x42A692ECUL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB8 (*((volatile unsigned int*)(0x42A692F0UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB9 (*((volatile unsigned int*)(0x42A692F4UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB10 (*((volatile unsigned int*)(0x42A692F8UL))) +#define bM4_DMA2_DNSEQCTLB1_DNSCNTB11 (*((volatile unsigned int*)(0x42A692FCUL))) +#define bM4_DMA2_LLP1_LLP0 (*((volatile unsigned int*)(0x42A69308UL))) +#define bM4_DMA2_LLP1_LLP1 (*((volatile unsigned int*)(0x42A6930CUL))) +#define bM4_DMA2_LLP1_LLP2 (*((volatile unsigned int*)(0x42A69310UL))) +#define bM4_DMA2_LLP1_LLP3 (*((volatile unsigned int*)(0x42A69314UL))) +#define bM4_DMA2_LLP1_LLP4 (*((volatile unsigned int*)(0x42A69318UL))) +#define bM4_DMA2_LLP1_LLP5 (*((volatile unsigned int*)(0x42A6931CUL))) +#define bM4_DMA2_LLP1_LLP6 (*((volatile unsigned int*)(0x42A69320UL))) +#define bM4_DMA2_LLP1_LLP7 (*((volatile unsigned int*)(0x42A69324UL))) +#define bM4_DMA2_LLP1_LLP8 (*((volatile unsigned int*)(0x42A69328UL))) +#define bM4_DMA2_LLP1_LLP9 (*((volatile unsigned int*)(0x42A6932CUL))) +#define bM4_DMA2_LLP1_LLP10 (*((volatile unsigned int*)(0x42A69330UL))) +#define bM4_DMA2_LLP1_LLP11 (*((volatile unsigned int*)(0x42A69334UL))) +#define bM4_DMA2_LLP1_LLP12 (*((volatile unsigned int*)(0x42A69338UL))) +#define bM4_DMA2_LLP1_LLP13 (*((volatile unsigned int*)(0x42A6933CUL))) +#define bM4_DMA2_LLP1_LLP14 (*((volatile unsigned int*)(0x42A69340UL))) +#define bM4_DMA2_LLP1_LLP15 (*((volatile unsigned int*)(0x42A69344UL))) +#define bM4_DMA2_LLP1_LLP16 (*((volatile unsigned int*)(0x42A69348UL))) +#define bM4_DMA2_LLP1_LLP17 (*((volatile unsigned int*)(0x42A6934CUL))) +#define bM4_DMA2_LLP1_LLP18 (*((volatile unsigned int*)(0x42A69350UL))) +#define bM4_DMA2_LLP1_LLP19 (*((volatile unsigned int*)(0x42A69354UL))) +#define bM4_DMA2_LLP1_LLP20 (*((volatile unsigned int*)(0x42A69358UL))) +#define bM4_DMA2_LLP1_LLP21 (*((volatile unsigned int*)(0x42A6935CUL))) +#define bM4_DMA2_LLP1_LLP22 (*((volatile unsigned int*)(0x42A69360UL))) +#define bM4_DMA2_LLP1_LLP23 (*((volatile unsigned int*)(0x42A69364UL))) +#define bM4_DMA2_LLP1_LLP24 (*((volatile unsigned int*)(0x42A69368UL))) +#define bM4_DMA2_LLP1_LLP25 (*((volatile unsigned int*)(0x42A6936CUL))) +#define bM4_DMA2_LLP1_LLP26 (*((volatile unsigned int*)(0x42A69370UL))) +#define bM4_DMA2_LLP1_LLP27 (*((volatile unsigned int*)(0x42A69374UL))) +#define bM4_DMA2_LLP1_LLP28 (*((volatile unsigned int*)(0x42A69378UL))) +#define bM4_DMA2_LLP1_LLP29 (*((volatile unsigned int*)(0x42A6937CUL))) +#define bM4_DMA2_CH1CTL_SINC0 (*((volatile unsigned int*)(0x42A69380UL))) +#define bM4_DMA2_CH1CTL_SINC1 (*((volatile unsigned int*)(0x42A69384UL))) +#define bM4_DMA2_CH1CTL_DINC0 (*((volatile unsigned int*)(0x42A69388UL))) +#define bM4_DMA2_CH1CTL_DINC1 (*((volatile unsigned int*)(0x42A6938CUL))) +#define bM4_DMA2_CH1CTL_SRPTEN (*((volatile unsigned int*)(0x42A69390UL))) +#define bM4_DMA2_CH1CTL_DRPTEN (*((volatile unsigned int*)(0x42A69394UL))) +#define bM4_DMA2_CH1CTL_SNSEQEN (*((volatile unsigned int*)(0x42A69398UL))) +#define bM4_DMA2_CH1CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6939CUL))) +#define bM4_DMA2_CH1CTL_HSIZE0 (*((volatile unsigned int*)(0x42A693A0UL))) +#define bM4_DMA2_CH1CTL_HSIZE1 (*((volatile unsigned int*)(0x42A693A4UL))) +#define bM4_DMA2_CH1CTL_LLPEN (*((volatile unsigned int*)(0x42A693A8UL))) +#define bM4_DMA2_CH1CTL_LLPRUN (*((volatile unsigned int*)(0x42A693ACUL))) +#define bM4_DMA2_CH1CTL_IE (*((volatile unsigned int*)(0x42A693B0UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE0 (*((volatile unsigned int*)(0x42A69500UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE1 (*((volatile unsigned int*)(0x42A69504UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE2 (*((volatile unsigned int*)(0x42A69508UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE3 (*((volatile unsigned int*)(0x42A6950CUL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE4 (*((volatile unsigned int*)(0x42A69510UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE5 (*((volatile unsigned int*)(0x42A69514UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE6 (*((volatile unsigned int*)(0x42A69518UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE7 (*((volatile unsigned int*)(0x42A6951CUL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE8 (*((volatile unsigned int*)(0x42A69520UL))) +#define bM4_DMA2_MONDTCTL1_BLKSIZE9 (*((volatile unsigned int*)(0x42A69524UL))) +#define bM4_DMA2_MONDTCTL1_CNT0 (*((volatile unsigned int*)(0x42A69540UL))) +#define bM4_DMA2_MONDTCTL1_CNT1 (*((volatile unsigned int*)(0x42A69544UL))) +#define bM4_DMA2_MONDTCTL1_CNT2 (*((volatile unsigned int*)(0x42A69548UL))) +#define bM4_DMA2_MONDTCTL1_CNT3 (*((volatile unsigned int*)(0x42A6954CUL))) +#define bM4_DMA2_MONDTCTL1_CNT4 (*((volatile unsigned int*)(0x42A69550UL))) +#define bM4_DMA2_MONDTCTL1_CNT5 (*((volatile unsigned int*)(0x42A69554UL))) +#define bM4_DMA2_MONDTCTL1_CNT6 (*((volatile unsigned int*)(0x42A69558UL))) +#define bM4_DMA2_MONDTCTL1_CNT7 (*((volatile unsigned int*)(0x42A6955CUL))) +#define bM4_DMA2_MONDTCTL1_CNT8 (*((volatile unsigned int*)(0x42A69560UL))) +#define bM4_DMA2_MONDTCTL1_CNT9 (*((volatile unsigned int*)(0x42A69564UL))) +#define bM4_DMA2_MONDTCTL1_CNT10 (*((volatile unsigned int*)(0x42A69568UL))) +#define bM4_DMA2_MONDTCTL1_CNT11 (*((volatile unsigned int*)(0x42A6956CUL))) +#define bM4_DMA2_MONDTCTL1_CNT12 (*((volatile unsigned int*)(0x42A69570UL))) +#define bM4_DMA2_MONDTCTL1_CNT13 (*((volatile unsigned int*)(0x42A69574UL))) +#define bM4_DMA2_MONDTCTL1_CNT14 (*((volatile unsigned int*)(0x42A69578UL))) +#define bM4_DMA2_MONDTCTL1_CNT15 (*((volatile unsigned int*)(0x42A6957CUL))) +#define bM4_DMA2_MONRPT1_SRPT0 (*((volatile unsigned int*)(0x42A69580UL))) +#define bM4_DMA2_MONRPT1_SRPT1 (*((volatile unsigned int*)(0x42A69584UL))) +#define bM4_DMA2_MONRPT1_SRPT2 (*((volatile unsigned int*)(0x42A69588UL))) +#define bM4_DMA2_MONRPT1_SRPT3 (*((volatile unsigned int*)(0x42A6958CUL))) +#define bM4_DMA2_MONRPT1_SRPT4 (*((volatile unsigned int*)(0x42A69590UL))) +#define bM4_DMA2_MONRPT1_SRPT5 (*((volatile unsigned int*)(0x42A69594UL))) +#define bM4_DMA2_MONRPT1_SRPT6 (*((volatile unsigned int*)(0x42A69598UL))) +#define bM4_DMA2_MONRPT1_SRPT7 (*((volatile unsigned int*)(0x42A6959CUL))) +#define bM4_DMA2_MONRPT1_SRPT8 (*((volatile unsigned int*)(0x42A695A0UL))) +#define bM4_DMA2_MONRPT1_SRPT9 (*((volatile unsigned int*)(0x42A695A4UL))) +#define bM4_DMA2_MONRPT1_DRPT0 (*((volatile unsigned int*)(0x42A695C0UL))) +#define bM4_DMA2_MONRPT1_DRPT1 (*((volatile unsigned int*)(0x42A695C4UL))) +#define bM4_DMA2_MONRPT1_DRPT2 (*((volatile unsigned int*)(0x42A695C8UL))) +#define bM4_DMA2_MONRPT1_DRPT3 (*((volatile unsigned int*)(0x42A695CCUL))) +#define bM4_DMA2_MONRPT1_DRPT4 (*((volatile unsigned int*)(0x42A695D0UL))) +#define bM4_DMA2_MONRPT1_DRPT5 (*((volatile unsigned int*)(0x42A695D4UL))) +#define bM4_DMA2_MONRPT1_DRPT6 (*((volatile unsigned int*)(0x42A695D8UL))) +#define bM4_DMA2_MONRPT1_DRPT7 (*((volatile unsigned int*)(0x42A695DCUL))) +#define bM4_DMA2_MONRPT1_DRPT8 (*((volatile unsigned int*)(0x42A695E0UL))) +#define bM4_DMA2_MONRPT1_DRPT9 (*((volatile unsigned int*)(0x42A695E4UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET0 (*((volatile unsigned int*)(0x42A69600UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET1 (*((volatile unsigned int*)(0x42A69604UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET2 (*((volatile unsigned int*)(0x42A69608UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET3 (*((volatile unsigned int*)(0x42A6960CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET4 (*((volatile unsigned int*)(0x42A69610UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET5 (*((volatile unsigned int*)(0x42A69614UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET6 (*((volatile unsigned int*)(0x42A69618UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET7 (*((volatile unsigned int*)(0x42A6961CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET8 (*((volatile unsigned int*)(0x42A69620UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET9 (*((volatile unsigned int*)(0x42A69624UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET10 (*((volatile unsigned int*)(0x42A69628UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET11 (*((volatile unsigned int*)(0x42A6962CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET12 (*((volatile unsigned int*)(0x42A69630UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET13 (*((volatile unsigned int*)(0x42A69634UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET14 (*((volatile unsigned int*)(0x42A69638UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET15 (*((volatile unsigned int*)(0x42A6963CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET16 (*((volatile unsigned int*)(0x42A69640UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET17 (*((volatile unsigned int*)(0x42A69644UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET18 (*((volatile unsigned int*)(0x42A69648UL))) +#define bM4_DMA2_MONSNSEQCTL1_SOFFSET19 (*((volatile unsigned int*)(0x42A6964CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT0 (*((volatile unsigned int*)(0x42A69650UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT1 (*((volatile unsigned int*)(0x42A69654UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT2 (*((volatile unsigned int*)(0x42A69658UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT3 (*((volatile unsigned int*)(0x42A6965CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT4 (*((volatile unsigned int*)(0x42A69660UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT5 (*((volatile unsigned int*)(0x42A69664UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT6 (*((volatile unsigned int*)(0x42A69668UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT7 (*((volatile unsigned int*)(0x42A6966CUL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT8 (*((volatile unsigned int*)(0x42A69670UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT9 (*((volatile unsigned int*)(0x42A69674UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT10 (*((volatile unsigned int*)(0x42A69678UL))) +#define bM4_DMA2_MONSNSEQCTL1_SNSCNT11 (*((volatile unsigned int*)(0x42A6967CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET0 (*((volatile unsigned int*)(0x42A69680UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET1 (*((volatile unsigned int*)(0x42A69684UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET2 (*((volatile unsigned int*)(0x42A69688UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET3 (*((volatile unsigned int*)(0x42A6968CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET4 (*((volatile unsigned int*)(0x42A69690UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET5 (*((volatile unsigned int*)(0x42A69694UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET6 (*((volatile unsigned int*)(0x42A69698UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET7 (*((volatile unsigned int*)(0x42A6969CUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET8 (*((volatile unsigned int*)(0x42A696A0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET9 (*((volatile unsigned int*)(0x42A696A4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET10 (*((volatile unsigned int*)(0x42A696A8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET11 (*((volatile unsigned int*)(0x42A696ACUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET12 (*((volatile unsigned int*)(0x42A696B0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET13 (*((volatile unsigned int*)(0x42A696B4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET14 (*((volatile unsigned int*)(0x42A696B8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET15 (*((volatile unsigned int*)(0x42A696BCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET16 (*((volatile unsigned int*)(0x42A696C0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET17 (*((volatile unsigned int*)(0x42A696C4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET18 (*((volatile unsigned int*)(0x42A696C8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DOFFSET19 (*((volatile unsigned int*)(0x42A696CCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT0 (*((volatile unsigned int*)(0x42A696D0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT1 (*((volatile unsigned int*)(0x42A696D4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT2 (*((volatile unsigned int*)(0x42A696D8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT3 (*((volatile unsigned int*)(0x42A696DCUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT4 (*((volatile unsigned int*)(0x42A696E0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT5 (*((volatile unsigned int*)(0x42A696E4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT6 (*((volatile unsigned int*)(0x42A696E8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT7 (*((volatile unsigned int*)(0x42A696ECUL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT8 (*((volatile unsigned int*)(0x42A696F0UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT9 (*((volatile unsigned int*)(0x42A696F4UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT10 (*((volatile unsigned int*)(0x42A696F8UL))) +#define bM4_DMA2_MONDNSEQCTL1_DNSCNT11 (*((volatile unsigned int*)(0x42A696FCUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A69900UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A69904UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A69908UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A6990CUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A69910UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A69914UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A69918UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A6991CUL))) +#define bM4_DMA2_DTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A69920UL))) +#define bM4_DMA2_DTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A69924UL))) +#define bM4_DMA2_DTCTL2_CNT0 (*((volatile unsigned int*)(0x42A69940UL))) +#define bM4_DMA2_DTCTL2_CNT1 (*((volatile unsigned int*)(0x42A69944UL))) +#define bM4_DMA2_DTCTL2_CNT2 (*((volatile unsigned int*)(0x42A69948UL))) +#define bM4_DMA2_DTCTL2_CNT3 (*((volatile unsigned int*)(0x42A6994CUL))) +#define bM4_DMA2_DTCTL2_CNT4 (*((volatile unsigned int*)(0x42A69950UL))) +#define bM4_DMA2_DTCTL2_CNT5 (*((volatile unsigned int*)(0x42A69954UL))) +#define bM4_DMA2_DTCTL2_CNT6 (*((volatile unsigned int*)(0x42A69958UL))) +#define bM4_DMA2_DTCTL2_CNT7 (*((volatile unsigned int*)(0x42A6995CUL))) +#define bM4_DMA2_DTCTL2_CNT8 (*((volatile unsigned int*)(0x42A69960UL))) +#define bM4_DMA2_DTCTL2_CNT9 (*((volatile unsigned int*)(0x42A69964UL))) +#define bM4_DMA2_DTCTL2_CNT10 (*((volatile unsigned int*)(0x42A69968UL))) +#define bM4_DMA2_DTCTL2_CNT11 (*((volatile unsigned int*)(0x42A6996CUL))) +#define bM4_DMA2_DTCTL2_CNT12 (*((volatile unsigned int*)(0x42A69970UL))) +#define bM4_DMA2_DTCTL2_CNT13 (*((volatile unsigned int*)(0x42A69974UL))) +#define bM4_DMA2_DTCTL2_CNT14 (*((volatile unsigned int*)(0x42A69978UL))) +#define bM4_DMA2_DTCTL2_CNT15 (*((volatile unsigned int*)(0x42A6997CUL))) +#define bM4_DMA2_RPT2_SRPT0 (*((volatile unsigned int*)(0x42A69980UL))) +#define bM4_DMA2_RPT2_SRPT1 (*((volatile unsigned int*)(0x42A69984UL))) +#define bM4_DMA2_RPT2_SRPT2 (*((volatile unsigned int*)(0x42A69988UL))) +#define bM4_DMA2_RPT2_SRPT3 (*((volatile unsigned int*)(0x42A6998CUL))) +#define bM4_DMA2_RPT2_SRPT4 (*((volatile unsigned int*)(0x42A69990UL))) +#define bM4_DMA2_RPT2_SRPT5 (*((volatile unsigned int*)(0x42A69994UL))) +#define bM4_DMA2_RPT2_SRPT6 (*((volatile unsigned int*)(0x42A69998UL))) +#define bM4_DMA2_RPT2_SRPT7 (*((volatile unsigned int*)(0x42A6999CUL))) +#define bM4_DMA2_RPT2_SRPT8 (*((volatile unsigned int*)(0x42A699A0UL))) +#define bM4_DMA2_RPT2_SRPT9 (*((volatile unsigned int*)(0x42A699A4UL))) +#define bM4_DMA2_RPT2_DRPT0 (*((volatile unsigned int*)(0x42A699C0UL))) +#define bM4_DMA2_RPT2_DRPT1 (*((volatile unsigned int*)(0x42A699C4UL))) +#define bM4_DMA2_RPT2_DRPT2 (*((volatile unsigned int*)(0x42A699C8UL))) +#define bM4_DMA2_RPT2_DRPT3 (*((volatile unsigned int*)(0x42A699CCUL))) +#define bM4_DMA2_RPT2_DRPT4 (*((volatile unsigned int*)(0x42A699D0UL))) +#define bM4_DMA2_RPT2_DRPT5 (*((volatile unsigned int*)(0x42A699D4UL))) +#define bM4_DMA2_RPT2_DRPT6 (*((volatile unsigned int*)(0x42A699D8UL))) +#define bM4_DMA2_RPT2_DRPT7 (*((volatile unsigned int*)(0x42A699DCUL))) +#define bM4_DMA2_RPT2_DRPT8 (*((volatile unsigned int*)(0x42A699E0UL))) +#define bM4_DMA2_RPT2_DRPT9 (*((volatile unsigned int*)(0x42A699E4UL))) +#define bM4_DMA2_RPTB2_SRPTB0 (*((volatile unsigned int*)(0x42A69980UL))) +#define bM4_DMA2_RPTB2_SRPTB1 (*((volatile unsigned int*)(0x42A69984UL))) +#define bM4_DMA2_RPTB2_SRPTB2 (*((volatile unsigned int*)(0x42A69988UL))) +#define bM4_DMA2_RPTB2_SRPTB3 (*((volatile unsigned int*)(0x42A6998CUL))) +#define bM4_DMA2_RPTB2_SRPTB4 (*((volatile unsigned int*)(0x42A69990UL))) +#define bM4_DMA2_RPTB2_SRPTB5 (*((volatile unsigned int*)(0x42A69994UL))) +#define bM4_DMA2_RPTB2_SRPTB6 (*((volatile unsigned int*)(0x42A69998UL))) +#define bM4_DMA2_RPTB2_SRPTB7 (*((volatile unsigned int*)(0x42A6999CUL))) +#define bM4_DMA2_RPTB2_SRPTB8 (*((volatile unsigned int*)(0x42A699A0UL))) +#define bM4_DMA2_RPTB2_SRPTB9 (*((volatile unsigned int*)(0x42A699A4UL))) +#define bM4_DMA2_RPTB2_DRPTB0 (*((volatile unsigned int*)(0x42A699C0UL))) +#define bM4_DMA2_RPTB2_DRPTB1 (*((volatile unsigned int*)(0x42A699C4UL))) +#define bM4_DMA2_RPTB2_DRPTB2 (*((volatile unsigned int*)(0x42A699C8UL))) +#define bM4_DMA2_RPTB2_DRPTB3 (*((volatile unsigned int*)(0x42A699CCUL))) +#define bM4_DMA2_RPTB2_DRPTB4 (*((volatile unsigned int*)(0x42A699D0UL))) +#define bM4_DMA2_RPTB2_DRPTB5 (*((volatile unsigned int*)(0x42A699D4UL))) +#define bM4_DMA2_RPTB2_DRPTB6 (*((volatile unsigned int*)(0x42A699D8UL))) +#define bM4_DMA2_RPTB2_DRPTB7 (*((volatile unsigned int*)(0x42A699DCUL))) +#define bM4_DMA2_RPTB2_DRPTB8 (*((volatile unsigned int*)(0x42A699E0UL))) +#define bM4_DMA2_RPTB2_DRPTB9 (*((volatile unsigned int*)(0x42A699E4UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A69A00UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A69A04UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A69A08UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A69A0CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A69A10UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A69A14UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A69A18UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A69A1CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A69A20UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A69A24UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A69A28UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A69A2CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A69A30UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A69A34UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A69A38UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A69A3CUL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A69A40UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A69A44UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A69A48UL))) +#define bM4_DMA2_SNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A69A4CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A69A50UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A69A54UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A69A58UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A69A5CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A69A60UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A69A64UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A69A68UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A69A6CUL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A69A70UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A69A74UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A69A78UL))) +#define bM4_DMA2_SNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A69A7CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST0 (*((volatile unsigned int*)(0x42A69A00UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST1 (*((volatile unsigned int*)(0x42A69A04UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST2 (*((volatile unsigned int*)(0x42A69A08UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST3 (*((volatile unsigned int*)(0x42A69A0CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST4 (*((volatile unsigned int*)(0x42A69A10UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST5 (*((volatile unsigned int*)(0x42A69A14UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST6 (*((volatile unsigned int*)(0x42A69A18UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST7 (*((volatile unsigned int*)(0x42A69A1CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST8 (*((volatile unsigned int*)(0x42A69A20UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST9 (*((volatile unsigned int*)(0x42A69A24UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST10 (*((volatile unsigned int*)(0x42A69A28UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST11 (*((volatile unsigned int*)(0x42A69A2CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST12 (*((volatile unsigned int*)(0x42A69A30UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST13 (*((volatile unsigned int*)(0x42A69A34UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST14 (*((volatile unsigned int*)(0x42A69A38UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST15 (*((volatile unsigned int*)(0x42A69A3CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST16 (*((volatile unsigned int*)(0x42A69A40UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST17 (*((volatile unsigned int*)(0x42A69A44UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST18 (*((volatile unsigned int*)(0x42A69A48UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSDIST19 (*((volatile unsigned int*)(0x42A69A4CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB0 (*((volatile unsigned int*)(0x42A69A50UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB1 (*((volatile unsigned int*)(0x42A69A54UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB2 (*((volatile unsigned int*)(0x42A69A58UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB3 (*((volatile unsigned int*)(0x42A69A5CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB4 (*((volatile unsigned int*)(0x42A69A60UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB5 (*((volatile unsigned int*)(0x42A69A64UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB6 (*((volatile unsigned int*)(0x42A69A68UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB7 (*((volatile unsigned int*)(0x42A69A6CUL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB8 (*((volatile unsigned int*)(0x42A69A70UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB9 (*((volatile unsigned int*)(0x42A69A74UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB10 (*((volatile unsigned int*)(0x42A69A78UL))) +#define bM4_DMA2_SNSEQCTLB2_SNSCNTB11 (*((volatile unsigned int*)(0x42A69A7CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A69A80UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A69A84UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A69A88UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A69A8CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A69A90UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A69A94UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A69A98UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A69A9CUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A69AA0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A69AA4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A69AA8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A69AACUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A69AB0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A69AB4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A69AB8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A69ABCUL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A69AC0UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A69AC4UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A69AC8UL))) +#define bM4_DMA2_DNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A69ACCUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A69AD0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A69AD4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A69AD8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A69ADCUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A69AE0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A69AE4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A69AE8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A69AECUL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A69AF0UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A69AF4UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A69AF8UL))) +#define bM4_DMA2_DNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A69AFCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST0 (*((volatile unsigned int*)(0x42A69A80UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST1 (*((volatile unsigned int*)(0x42A69A84UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST2 (*((volatile unsigned int*)(0x42A69A88UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST3 (*((volatile unsigned int*)(0x42A69A8CUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST4 (*((volatile unsigned int*)(0x42A69A90UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST5 (*((volatile unsigned int*)(0x42A69A94UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST6 (*((volatile unsigned int*)(0x42A69A98UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST7 (*((volatile unsigned int*)(0x42A69A9CUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST8 (*((volatile unsigned int*)(0x42A69AA0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST9 (*((volatile unsigned int*)(0x42A69AA4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST10 (*((volatile unsigned int*)(0x42A69AA8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST11 (*((volatile unsigned int*)(0x42A69AACUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST12 (*((volatile unsigned int*)(0x42A69AB0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST13 (*((volatile unsigned int*)(0x42A69AB4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST14 (*((volatile unsigned int*)(0x42A69AB8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST15 (*((volatile unsigned int*)(0x42A69ABCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST16 (*((volatile unsigned int*)(0x42A69AC0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST17 (*((volatile unsigned int*)(0x42A69AC4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST18 (*((volatile unsigned int*)(0x42A69AC8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSDIST19 (*((volatile unsigned int*)(0x42A69ACCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB0 (*((volatile unsigned int*)(0x42A69AD0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB1 (*((volatile unsigned int*)(0x42A69AD4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB2 (*((volatile unsigned int*)(0x42A69AD8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB3 (*((volatile unsigned int*)(0x42A69ADCUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB4 (*((volatile unsigned int*)(0x42A69AE0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB5 (*((volatile unsigned int*)(0x42A69AE4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB6 (*((volatile unsigned int*)(0x42A69AE8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB7 (*((volatile unsigned int*)(0x42A69AECUL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB8 (*((volatile unsigned int*)(0x42A69AF0UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB9 (*((volatile unsigned int*)(0x42A69AF4UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB10 (*((volatile unsigned int*)(0x42A69AF8UL))) +#define bM4_DMA2_DNSEQCTLB2_DNSCNTB11 (*((volatile unsigned int*)(0x42A69AFCUL))) +#define bM4_DMA2_LLP2_LLP0 (*((volatile unsigned int*)(0x42A69B08UL))) +#define bM4_DMA2_LLP2_LLP1 (*((volatile unsigned int*)(0x42A69B0CUL))) +#define bM4_DMA2_LLP2_LLP2 (*((volatile unsigned int*)(0x42A69B10UL))) +#define bM4_DMA2_LLP2_LLP3 (*((volatile unsigned int*)(0x42A69B14UL))) +#define bM4_DMA2_LLP2_LLP4 (*((volatile unsigned int*)(0x42A69B18UL))) +#define bM4_DMA2_LLP2_LLP5 (*((volatile unsigned int*)(0x42A69B1CUL))) +#define bM4_DMA2_LLP2_LLP6 (*((volatile unsigned int*)(0x42A69B20UL))) +#define bM4_DMA2_LLP2_LLP7 (*((volatile unsigned int*)(0x42A69B24UL))) +#define bM4_DMA2_LLP2_LLP8 (*((volatile unsigned int*)(0x42A69B28UL))) +#define bM4_DMA2_LLP2_LLP9 (*((volatile unsigned int*)(0x42A69B2CUL))) +#define bM4_DMA2_LLP2_LLP10 (*((volatile unsigned int*)(0x42A69B30UL))) +#define bM4_DMA2_LLP2_LLP11 (*((volatile unsigned int*)(0x42A69B34UL))) +#define bM4_DMA2_LLP2_LLP12 (*((volatile unsigned int*)(0x42A69B38UL))) +#define bM4_DMA2_LLP2_LLP13 (*((volatile unsigned int*)(0x42A69B3CUL))) +#define bM4_DMA2_LLP2_LLP14 (*((volatile unsigned int*)(0x42A69B40UL))) +#define bM4_DMA2_LLP2_LLP15 (*((volatile unsigned int*)(0x42A69B44UL))) +#define bM4_DMA2_LLP2_LLP16 (*((volatile unsigned int*)(0x42A69B48UL))) +#define bM4_DMA2_LLP2_LLP17 (*((volatile unsigned int*)(0x42A69B4CUL))) +#define bM4_DMA2_LLP2_LLP18 (*((volatile unsigned int*)(0x42A69B50UL))) +#define bM4_DMA2_LLP2_LLP19 (*((volatile unsigned int*)(0x42A69B54UL))) +#define bM4_DMA2_LLP2_LLP20 (*((volatile unsigned int*)(0x42A69B58UL))) +#define bM4_DMA2_LLP2_LLP21 (*((volatile unsigned int*)(0x42A69B5CUL))) +#define bM4_DMA2_LLP2_LLP22 (*((volatile unsigned int*)(0x42A69B60UL))) +#define bM4_DMA2_LLP2_LLP23 (*((volatile unsigned int*)(0x42A69B64UL))) +#define bM4_DMA2_LLP2_LLP24 (*((volatile unsigned int*)(0x42A69B68UL))) +#define bM4_DMA2_LLP2_LLP25 (*((volatile unsigned int*)(0x42A69B6CUL))) +#define bM4_DMA2_LLP2_LLP26 (*((volatile unsigned int*)(0x42A69B70UL))) +#define bM4_DMA2_LLP2_LLP27 (*((volatile unsigned int*)(0x42A69B74UL))) +#define bM4_DMA2_LLP2_LLP28 (*((volatile unsigned int*)(0x42A69B78UL))) +#define bM4_DMA2_LLP2_LLP29 (*((volatile unsigned int*)(0x42A69B7CUL))) +#define bM4_DMA2_CH2CTL_SINC0 (*((volatile unsigned int*)(0x42A69B80UL))) +#define bM4_DMA2_CH2CTL_SINC1 (*((volatile unsigned int*)(0x42A69B84UL))) +#define bM4_DMA2_CH2CTL_DINC0 (*((volatile unsigned int*)(0x42A69B88UL))) +#define bM4_DMA2_CH2CTL_DINC1 (*((volatile unsigned int*)(0x42A69B8CUL))) +#define bM4_DMA2_CH2CTL_SRPTEN (*((volatile unsigned int*)(0x42A69B90UL))) +#define bM4_DMA2_CH2CTL_DRPTEN (*((volatile unsigned int*)(0x42A69B94UL))) +#define bM4_DMA2_CH2CTL_SNSEQEN (*((volatile unsigned int*)(0x42A69B98UL))) +#define bM4_DMA2_CH2CTL_DNSEQEN (*((volatile unsigned int*)(0x42A69B9CUL))) +#define bM4_DMA2_CH2CTL_HSIZE0 (*((volatile unsigned int*)(0x42A69BA0UL))) +#define bM4_DMA2_CH2CTL_HSIZE1 (*((volatile unsigned int*)(0x42A69BA4UL))) +#define bM4_DMA2_CH2CTL_LLPEN (*((volatile unsigned int*)(0x42A69BA8UL))) +#define bM4_DMA2_CH2CTL_LLPRUN (*((volatile unsigned int*)(0x42A69BACUL))) +#define bM4_DMA2_CH2CTL_IE (*((volatile unsigned int*)(0x42A69BB0UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE0 (*((volatile unsigned int*)(0x42A69D00UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE1 (*((volatile unsigned int*)(0x42A69D04UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE2 (*((volatile unsigned int*)(0x42A69D08UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE3 (*((volatile unsigned int*)(0x42A69D0CUL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE4 (*((volatile unsigned int*)(0x42A69D10UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE5 (*((volatile unsigned int*)(0x42A69D14UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE6 (*((volatile unsigned int*)(0x42A69D18UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE7 (*((volatile unsigned int*)(0x42A69D1CUL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE8 (*((volatile unsigned int*)(0x42A69D20UL))) +#define bM4_DMA2_MONDTCTL2_BLKSIZE9 (*((volatile unsigned int*)(0x42A69D24UL))) +#define bM4_DMA2_MONDTCTL2_CNT0 (*((volatile unsigned int*)(0x42A69D40UL))) +#define bM4_DMA2_MONDTCTL2_CNT1 (*((volatile unsigned int*)(0x42A69D44UL))) +#define bM4_DMA2_MONDTCTL2_CNT2 (*((volatile unsigned int*)(0x42A69D48UL))) +#define bM4_DMA2_MONDTCTL2_CNT3 (*((volatile unsigned int*)(0x42A69D4CUL))) +#define bM4_DMA2_MONDTCTL2_CNT4 (*((volatile unsigned int*)(0x42A69D50UL))) +#define bM4_DMA2_MONDTCTL2_CNT5 (*((volatile unsigned int*)(0x42A69D54UL))) +#define bM4_DMA2_MONDTCTL2_CNT6 (*((volatile unsigned int*)(0x42A69D58UL))) +#define bM4_DMA2_MONDTCTL2_CNT7 (*((volatile unsigned int*)(0x42A69D5CUL))) +#define bM4_DMA2_MONDTCTL2_CNT8 (*((volatile unsigned int*)(0x42A69D60UL))) +#define bM4_DMA2_MONDTCTL2_CNT9 (*((volatile unsigned int*)(0x42A69D64UL))) +#define bM4_DMA2_MONDTCTL2_CNT10 (*((volatile unsigned int*)(0x42A69D68UL))) +#define bM4_DMA2_MONDTCTL2_CNT11 (*((volatile unsigned int*)(0x42A69D6CUL))) +#define bM4_DMA2_MONDTCTL2_CNT12 (*((volatile unsigned int*)(0x42A69D70UL))) +#define bM4_DMA2_MONDTCTL2_CNT13 (*((volatile unsigned int*)(0x42A69D74UL))) +#define bM4_DMA2_MONDTCTL2_CNT14 (*((volatile unsigned int*)(0x42A69D78UL))) +#define bM4_DMA2_MONDTCTL2_CNT15 (*((volatile unsigned int*)(0x42A69D7CUL))) +#define bM4_DMA2_MONRPT2_SRPT0 (*((volatile unsigned int*)(0x42A69D80UL))) +#define bM4_DMA2_MONRPT2_SRPT1 (*((volatile unsigned int*)(0x42A69D84UL))) +#define bM4_DMA2_MONRPT2_SRPT2 (*((volatile unsigned int*)(0x42A69D88UL))) +#define bM4_DMA2_MONRPT2_SRPT3 (*((volatile unsigned int*)(0x42A69D8CUL))) +#define bM4_DMA2_MONRPT2_SRPT4 (*((volatile unsigned int*)(0x42A69D90UL))) +#define bM4_DMA2_MONRPT2_SRPT5 (*((volatile unsigned int*)(0x42A69D94UL))) +#define bM4_DMA2_MONRPT2_SRPT6 (*((volatile unsigned int*)(0x42A69D98UL))) +#define bM4_DMA2_MONRPT2_SRPT7 (*((volatile unsigned int*)(0x42A69D9CUL))) +#define bM4_DMA2_MONRPT2_SRPT8 (*((volatile unsigned int*)(0x42A69DA0UL))) +#define bM4_DMA2_MONRPT2_SRPT9 (*((volatile unsigned int*)(0x42A69DA4UL))) +#define bM4_DMA2_MONRPT2_DRPT0 (*((volatile unsigned int*)(0x42A69DC0UL))) +#define bM4_DMA2_MONRPT2_DRPT1 (*((volatile unsigned int*)(0x42A69DC4UL))) +#define bM4_DMA2_MONRPT2_DRPT2 (*((volatile unsigned int*)(0x42A69DC8UL))) +#define bM4_DMA2_MONRPT2_DRPT3 (*((volatile unsigned int*)(0x42A69DCCUL))) +#define bM4_DMA2_MONRPT2_DRPT4 (*((volatile unsigned int*)(0x42A69DD0UL))) +#define bM4_DMA2_MONRPT2_DRPT5 (*((volatile unsigned int*)(0x42A69DD4UL))) +#define bM4_DMA2_MONRPT2_DRPT6 (*((volatile unsigned int*)(0x42A69DD8UL))) +#define bM4_DMA2_MONRPT2_DRPT7 (*((volatile unsigned int*)(0x42A69DDCUL))) +#define bM4_DMA2_MONRPT2_DRPT8 (*((volatile unsigned int*)(0x42A69DE0UL))) +#define bM4_DMA2_MONRPT2_DRPT9 (*((volatile unsigned int*)(0x42A69DE4UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET0 (*((volatile unsigned int*)(0x42A69E00UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET1 (*((volatile unsigned int*)(0x42A69E04UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET2 (*((volatile unsigned int*)(0x42A69E08UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET3 (*((volatile unsigned int*)(0x42A69E0CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET4 (*((volatile unsigned int*)(0x42A69E10UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET5 (*((volatile unsigned int*)(0x42A69E14UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET6 (*((volatile unsigned int*)(0x42A69E18UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET7 (*((volatile unsigned int*)(0x42A69E1CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET8 (*((volatile unsigned int*)(0x42A69E20UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET9 (*((volatile unsigned int*)(0x42A69E24UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET10 (*((volatile unsigned int*)(0x42A69E28UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET11 (*((volatile unsigned int*)(0x42A69E2CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET12 (*((volatile unsigned int*)(0x42A69E30UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET13 (*((volatile unsigned int*)(0x42A69E34UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET14 (*((volatile unsigned int*)(0x42A69E38UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET15 (*((volatile unsigned int*)(0x42A69E3CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET16 (*((volatile unsigned int*)(0x42A69E40UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET17 (*((volatile unsigned int*)(0x42A69E44UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET18 (*((volatile unsigned int*)(0x42A69E48UL))) +#define bM4_DMA2_MONSNSEQCTL2_SOFFSET19 (*((volatile unsigned int*)(0x42A69E4CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT0 (*((volatile unsigned int*)(0x42A69E50UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT1 (*((volatile unsigned int*)(0x42A69E54UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT2 (*((volatile unsigned int*)(0x42A69E58UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT3 (*((volatile unsigned int*)(0x42A69E5CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT4 (*((volatile unsigned int*)(0x42A69E60UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT5 (*((volatile unsigned int*)(0x42A69E64UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT6 (*((volatile unsigned int*)(0x42A69E68UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT7 (*((volatile unsigned int*)(0x42A69E6CUL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT8 (*((volatile unsigned int*)(0x42A69E70UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT9 (*((volatile unsigned int*)(0x42A69E74UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT10 (*((volatile unsigned int*)(0x42A69E78UL))) +#define bM4_DMA2_MONSNSEQCTL2_SNSCNT11 (*((volatile unsigned int*)(0x42A69E7CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET0 (*((volatile unsigned int*)(0x42A69E80UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET1 (*((volatile unsigned int*)(0x42A69E84UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET2 (*((volatile unsigned int*)(0x42A69E88UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET3 (*((volatile unsigned int*)(0x42A69E8CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET4 (*((volatile unsigned int*)(0x42A69E90UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET5 (*((volatile unsigned int*)(0x42A69E94UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET6 (*((volatile unsigned int*)(0x42A69E98UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET7 (*((volatile unsigned int*)(0x42A69E9CUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET8 (*((volatile unsigned int*)(0x42A69EA0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET9 (*((volatile unsigned int*)(0x42A69EA4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET10 (*((volatile unsigned int*)(0x42A69EA8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET11 (*((volatile unsigned int*)(0x42A69EACUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET12 (*((volatile unsigned int*)(0x42A69EB0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET13 (*((volatile unsigned int*)(0x42A69EB4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET14 (*((volatile unsigned int*)(0x42A69EB8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET15 (*((volatile unsigned int*)(0x42A69EBCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET16 (*((volatile unsigned int*)(0x42A69EC0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET17 (*((volatile unsigned int*)(0x42A69EC4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET18 (*((volatile unsigned int*)(0x42A69EC8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DOFFSET19 (*((volatile unsigned int*)(0x42A69ECCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT0 (*((volatile unsigned int*)(0x42A69ED0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT1 (*((volatile unsigned int*)(0x42A69ED4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT2 (*((volatile unsigned int*)(0x42A69ED8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT3 (*((volatile unsigned int*)(0x42A69EDCUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT4 (*((volatile unsigned int*)(0x42A69EE0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT5 (*((volatile unsigned int*)(0x42A69EE4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT6 (*((volatile unsigned int*)(0x42A69EE8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT7 (*((volatile unsigned int*)(0x42A69EECUL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT8 (*((volatile unsigned int*)(0x42A69EF0UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT9 (*((volatile unsigned int*)(0x42A69EF4UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT10 (*((volatile unsigned int*)(0x42A69EF8UL))) +#define bM4_DMA2_MONDNSEQCTL2_DNSCNT11 (*((volatile unsigned int*)(0x42A69EFCUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A6A100UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A6A104UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A6A108UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6A10CUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A6A110UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A6A114UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A6A118UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6A11CUL))) +#define bM4_DMA2_DTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A6A120UL))) +#define bM4_DMA2_DTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A6A124UL))) +#define bM4_DMA2_DTCTL3_CNT0 (*((volatile unsigned int*)(0x42A6A140UL))) +#define bM4_DMA2_DTCTL3_CNT1 (*((volatile unsigned int*)(0x42A6A144UL))) +#define bM4_DMA2_DTCTL3_CNT2 (*((volatile unsigned int*)(0x42A6A148UL))) +#define bM4_DMA2_DTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6A14CUL))) +#define bM4_DMA2_DTCTL3_CNT4 (*((volatile unsigned int*)(0x42A6A150UL))) +#define bM4_DMA2_DTCTL3_CNT5 (*((volatile unsigned int*)(0x42A6A154UL))) +#define bM4_DMA2_DTCTL3_CNT6 (*((volatile unsigned int*)(0x42A6A158UL))) +#define bM4_DMA2_DTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6A15CUL))) +#define bM4_DMA2_DTCTL3_CNT8 (*((volatile unsigned int*)(0x42A6A160UL))) +#define bM4_DMA2_DTCTL3_CNT9 (*((volatile unsigned int*)(0x42A6A164UL))) +#define bM4_DMA2_DTCTL3_CNT10 (*((volatile unsigned int*)(0x42A6A168UL))) +#define bM4_DMA2_DTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6A16CUL))) +#define bM4_DMA2_DTCTL3_CNT12 (*((volatile unsigned int*)(0x42A6A170UL))) +#define bM4_DMA2_DTCTL3_CNT13 (*((volatile unsigned int*)(0x42A6A174UL))) +#define bM4_DMA2_DTCTL3_CNT14 (*((volatile unsigned int*)(0x42A6A178UL))) +#define bM4_DMA2_DTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6A17CUL))) +#define bM4_DMA2_RPT3_SRPT0 (*((volatile unsigned int*)(0x42A6A180UL))) +#define bM4_DMA2_RPT3_SRPT1 (*((volatile unsigned int*)(0x42A6A184UL))) +#define bM4_DMA2_RPT3_SRPT2 (*((volatile unsigned int*)(0x42A6A188UL))) +#define bM4_DMA2_RPT3_SRPT3 (*((volatile unsigned int*)(0x42A6A18CUL))) +#define bM4_DMA2_RPT3_SRPT4 (*((volatile unsigned int*)(0x42A6A190UL))) +#define bM4_DMA2_RPT3_SRPT5 (*((volatile unsigned int*)(0x42A6A194UL))) +#define bM4_DMA2_RPT3_SRPT6 (*((volatile unsigned int*)(0x42A6A198UL))) +#define bM4_DMA2_RPT3_SRPT7 (*((volatile unsigned int*)(0x42A6A19CUL))) +#define bM4_DMA2_RPT3_SRPT8 (*((volatile unsigned int*)(0x42A6A1A0UL))) +#define bM4_DMA2_RPT3_SRPT9 (*((volatile unsigned int*)(0x42A6A1A4UL))) +#define bM4_DMA2_RPT3_DRPT0 (*((volatile unsigned int*)(0x42A6A1C0UL))) +#define bM4_DMA2_RPT3_DRPT1 (*((volatile unsigned int*)(0x42A6A1C4UL))) +#define bM4_DMA2_RPT3_DRPT2 (*((volatile unsigned int*)(0x42A6A1C8UL))) +#define bM4_DMA2_RPT3_DRPT3 (*((volatile unsigned int*)(0x42A6A1CCUL))) +#define bM4_DMA2_RPT3_DRPT4 (*((volatile unsigned int*)(0x42A6A1D0UL))) +#define bM4_DMA2_RPT3_DRPT5 (*((volatile unsigned int*)(0x42A6A1D4UL))) +#define bM4_DMA2_RPT3_DRPT6 (*((volatile unsigned int*)(0x42A6A1D8UL))) +#define bM4_DMA2_RPT3_DRPT7 (*((volatile unsigned int*)(0x42A6A1DCUL))) +#define bM4_DMA2_RPT3_DRPT8 (*((volatile unsigned int*)(0x42A6A1E0UL))) +#define bM4_DMA2_RPT3_DRPT9 (*((volatile unsigned int*)(0x42A6A1E4UL))) +#define bM4_DMA2_RPTB3_SRPTB0 (*((volatile unsigned int*)(0x42A6A180UL))) +#define bM4_DMA2_RPTB3_SRPTB1 (*((volatile unsigned int*)(0x42A6A184UL))) +#define bM4_DMA2_RPTB3_SRPTB2 (*((volatile unsigned int*)(0x42A6A188UL))) +#define bM4_DMA2_RPTB3_SRPTB3 (*((volatile unsigned int*)(0x42A6A18CUL))) +#define bM4_DMA2_RPTB3_SRPTB4 (*((volatile unsigned int*)(0x42A6A190UL))) +#define bM4_DMA2_RPTB3_SRPTB5 (*((volatile unsigned int*)(0x42A6A194UL))) +#define bM4_DMA2_RPTB3_SRPTB6 (*((volatile unsigned int*)(0x42A6A198UL))) +#define bM4_DMA2_RPTB3_SRPTB7 (*((volatile unsigned int*)(0x42A6A19CUL))) +#define bM4_DMA2_RPTB3_SRPTB8 (*((volatile unsigned int*)(0x42A6A1A0UL))) +#define bM4_DMA2_RPTB3_SRPTB9 (*((volatile unsigned int*)(0x42A6A1A4UL))) +#define bM4_DMA2_RPTB3_DRPTB0 (*((volatile unsigned int*)(0x42A6A1C0UL))) +#define bM4_DMA2_RPTB3_DRPTB1 (*((volatile unsigned int*)(0x42A6A1C4UL))) +#define bM4_DMA2_RPTB3_DRPTB2 (*((volatile unsigned int*)(0x42A6A1C8UL))) +#define bM4_DMA2_RPTB3_DRPTB3 (*((volatile unsigned int*)(0x42A6A1CCUL))) +#define bM4_DMA2_RPTB3_DRPTB4 (*((volatile unsigned int*)(0x42A6A1D0UL))) +#define bM4_DMA2_RPTB3_DRPTB5 (*((volatile unsigned int*)(0x42A6A1D4UL))) +#define bM4_DMA2_RPTB3_DRPTB6 (*((volatile unsigned int*)(0x42A6A1D8UL))) +#define bM4_DMA2_RPTB3_DRPTB7 (*((volatile unsigned int*)(0x42A6A1DCUL))) +#define bM4_DMA2_RPTB3_DRPTB8 (*((volatile unsigned int*)(0x42A6A1E0UL))) +#define bM4_DMA2_RPTB3_DRPTB9 (*((volatile unsigned int*)(0x42A6A1E4UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A6A200UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A6A204UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A6A208UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6A20CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A6A210UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A6A214UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A6A218UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6A21CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A6A220UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A6A224UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A6A228UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6A22CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A6A230UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A6A234UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A6A238UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6A23CUL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A6A240UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A6A244UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A6A248UL))) +#define bM4_DMA2_SNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6A24CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A6A250UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A6A254UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A6A258UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6A25CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A6A260UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A6A264UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A6A268UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6A26CUL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A6A270UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A6A274UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A6A278UL))) +#define bM4_DMA2_SNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6A27CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST0 (*((volatile unsigned int*)(0x42A6A200UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST1 (*((volatile unsigned int*)(0x42A6A204UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST2 (*((volatile unsigned int*)(0x42A6A208UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST3 (*((volatile unsigned int*)(0x42A6A20CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST4 (*((volatile unsigned int*)(0x42A6A210UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST5 (*((volatile unsigned int*)(0x42A6A214UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST6 (*((volatile unsigned int*)(0x42A6A218UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST7 (*((volatile unsigned int*)(0x42A6A21CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST8 (*((volatile unsigned int*)(0x42A6A220UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST9 (*((volatile unsigned int*)(0x42A6A224UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST10 (*((volatile unsigned int*)(0x42A6A228UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST11 (*((volatile unsigned int*)(0x42A6A22CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST12 (*((volatile unsigned int*)(0x42A6A230UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST13 (*((volatile unsigned int*)(0x42A6A234UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST14 (*((volatile unsigned int*)(0x42A6A238UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST15 (*((volatile unsigned int*)(0x42A6A23CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST16 (*((volatile unsigned int*)(0x42A6A240UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST17 (*((volatile unsigned int*)(0x42A6A244UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST18 (*((volatile unsigned int*)(0x42A6A248UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSDIST19 (*((volatile unsigned int*)(0x42A6A24CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB0 (*((volatile unsigned int*)(0x42A6A250UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB1 (*((volatile unsigned int*)(0x42A6A254UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB2 (*((volatile unsigned int*)(0x42A6A258UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB3 (*((volatile unsigned int*)(0x42A6A25CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB4 (*((volatile unsigned int*)(0x42A6A260UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB5 (*((volatile unsigned int*)(0x42A6A264UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB6 (*((volatile unsigned int*)(0x42A6A268UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB7 (*((volatile unsigned int*)(0x42A6A26CUL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB8 (*((volatile unsigned int*)(0x42A6A270UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB9 (*((volatile unsigned int*)(0x42A6A274UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB10 (*((volatile unsigned int*)(0x42A6A278UL))) +#define bM4_DMA2_SNSEQCTLB3_SNSCNTB11 (*((volatile unsigned int*)(0x42A6A27CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A6A280UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A6A284UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A6A288UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6A28CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A6A290UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A6A294UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A6A298UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6A29CUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A6A2A0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A6A2A4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A6A2A8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A6A2ACUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A6A2B0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A6A2B4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A6A2B8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A6A2BCUL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A6A2C0UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A6A2C4UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A6A2C8UL))) +#define bM4_DMA2_DNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A6A2CCUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A6A2D0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A6A2D4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A6A2D8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A6A2DCUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A6A2E0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A6A2E4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A6A2E8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A6A2ECUL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A6A2F0UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A6A2F4UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A6A2F8UL))) +#define bM4_DMA2_DNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A6A2FCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST0 (*((volatile unsigned int*)(0x42A6A280UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST1 (*((volatile unsigned int*)(0x42A6A284UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST2 (*((volatile unsigned int*)(0x42A6A288UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST3 (*((volatile unsigned int*)(0x42A6A28CUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST4 (*((volatile unsigned int*)(0x42A6A290UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST5 (*((volatile unsigned int*)(0x42A6A294UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST6 (*((volatile unsigned int*)(0x42A6A298UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST7 (*((volatile unsigned int*)(0x42A6A29CUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST8 (*((volatile unsigned int*)(0x42A6A2A0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST9 (*((volatile unsigned int*)(0x42A6A2A4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST10 (*((volatile unsigned int*)(0x42A6A2A8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST11 (*((volatile unsigned int*)(0x42A6A2ACUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST12 (*((volatile unsigned int*)(0x42A6A2B0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST13 (*((volatile unsigned int*)(0x42A6A2B4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST14 (*((volatile unsigned int*)(0x42A6A2B8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST15 (*((volatile unsigned int*)(0x42A6A2BCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST16 (*((volatile unsigned int*)(0x42A6A2C0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST17 (*((volatile unsigned int*)(0x42A6A2C4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST18 (*((volatile unsigned int*)(0x42A6A2C8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSDIST19 (*((volatile unsigned int*)(0x42A6A2CCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB0 (*((volatile unsigned int*)(0x42A6A2D0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB1 (*((volatile unsigned int*)(0x42A6A2D4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB2 (*((volatile unsigned int*)(0x42A6A2D8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB3 (*((volatile unsigned int*)(0x42A6A2DCUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB4 (*((volatile unsigned int*)(0x42A6A2E0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB5 (*((volatile unsigned int*)(0x42A6A2E4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB6 (*((volatile unsigned int*)(0x42A6A2E8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB7 (*((volatile unsigned int*)(0x42A6A2ECUL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB8 (*((volatile unsigned int*)(0x42A6A2F0UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB9 (*((volatile unsigned int*)(0x42A6A2F4UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB10 (*((volatile unsigned int*)(0x42A6A2F8UL))) +#define bM4_DMA2_DNSEQCTLB3_DNSCNTB11 (*((volatile unsigned int*)(0x42A6A2FCUL))) +#define bM4_DMA2_LLP3_LLP0 (*((volatile unsigned int*)(0x42A6A308UL))) +#define bM4_DMA2_LLP3_LLP1 (*((volatile unsigned int*)(0x42A6A30CUL))) +#define bM4_DMA2_LLP3_LLP2 (*((volatile unsigned int*)(0x42A6A310UL))) +#define bM4_DMA2_LLP3_LLP3 (*((volatile unsigned int*)(0x42A6A314UL))) +#define bM4_DMA2_LLP3_LLP4 (*((volatile unsigned int*)(0x42A6A318UL))) +#define bM4_DMA2_LLP3_LLP5 (*((volatile unsigned int*)(0x42A6A31CUL))) +#define bM4_DMA2_LLP3_LLP6 (*((volatile unsigned int*)(0x42A6A320UL))) +#define bM4_DMA2_LLP3_LLP7 (*((volatile unsigned int*)(0x42A6A324UL))) +#define bM4_DMA2_LLP3_LLP8 (*((volatile unsigned int*)(0x42A6A328UL))) +#define bM4_DMA2_LLP3_LLP9 (*((volatile unsigned int*)(0x42A6A32CUL))) +#define bM4_DMA2_LLP3_LLP10 (*((volatile unsigned int*)(0x42A6A330UL))) +#define bM4_DMA2_LLP3_LLP11 (*((volatile unsigned int*)(0x42A6A334UL))) +#define bM4_DMA2_LLP3_LLP12 (*((volatile unsigned int*)(0x42A6A338UL))) +#define bM4_DMA2_LLP3_LLP13 (*((volatile unsigned int*)(0x42A6A33CUL))) +#define bM4_DMA2_LLP3_LLP14 (*((volatile unsigned int*)(0x42A6A340UL))) +#define bM4_DMA2_LLP3_LLP15 (*((volatile unsigned int*)(0x42A6A344UL))) +#define bM4_DMA2_LLP3_LLP16 (*((volatile unsigned int*)(0x42A6A348UL))) +#define bM4_DMA2_LLP3_LLP17 (*((volatile unsigned int*)(0x42A6A34CUL))) +#define bM4_DMA2_LLP3_LLP18 (*((volatile unsigned int*)(0x42A6A350UL))) +#define bM4_DMA2_LLP3_LLP19 (*((volatile unsigned int*)(0x42A6A354UL))) +#define bM4_DMA2_LLP3_LLP20 (*((volatile unsigned int*)(0x42A6A358UL))) +#define bM4_DMA2_LLP3_LLP21 (*((volatile unsigned int*)(0x42A6A35CUL))) +#define bM4_DMA2_LLP3_LLP22 (*((volatile unsigned int*)(0x42A6A360UL))) +#define bM4_DMA2_LLP3_LLP23 (*((volatile unsigned int*)(0x42A6A364UL))) +#define bM4_DMA2_LLP3_LLP24 (*((volatile unsigned int*)(0x42A6A368UL))) +#define bM4_DMA2_LLP3_LLP25 (*((volatile unsigned int*)(0x42A6A36CUL))) +#define bM4_DMA2_LLP3_LLP26 (*((volatile unsigned int*)(0x42A6A370UL))) +#define bM4_DMA2_LLP3_LLP27 (*((volatile unsigned int*)(0x42A6A374UL))) +#define bM4_DMA2_LLP3_LLP28 (*((volatile unsigned int*)(0x42A6A378UL))) +#define bM4_DMA2_LLP3_LLP29 (*((volatile unsigned int*)(0x42A6A37CUL))) +#define bM4_DMA2_CH3CTL_SINC0 (*((volatile unsigned int*)(0x42A6A380UL))) +#define bM4_DMA2_CH3CTL_SINC1 (*((volatile unsigned int*)(0x42A6A384UL))) +#define bM4_DMA2_CH3CTL_DINC0 (*((volatile unsigned int*)(0x42A6A388UL))) +#define bM4_DMA2_CH3CTL_DINC1 (*((volatile unsigned int*)(0x42A6A38CUL))) +#define bM4_DMA2_CH3CTL_SRPTEN (*((volatile unsigned int*)(0x42A6A390UL))) +#define bM4_DMA2_CH3CTL_DRPTEN (*((volatile unsigned int*)(0x42A6A394UL))) +#define bM4_DMA2_CH3CTL_SNSEQEN (*((volatile unsigned int*)(0x42A6A398UL))) +#define bM4_DMA2_CH3CTL_DNSEQEN (*((volatile unsigned int*)(0x42A6A39CUL))) +#define bM4_DMA2_CH3CTL_HSIZE0 (*((volatile unsigned int*)(0x42A6A3A0UL))) +#define bM4_DMA2_CH3CTL_HSIZE1 (*((volatile unsigned int*)(0x42A6A3A4UL))) +#define bM4_DMA2_CH3CTL_LLPEN (*((volatile unsigned int*)(0x42A6A3A8UL))) +#define bM4_DMA2_CH3CTL_LLPRUN (*((volatile unsigned int*)(0x42A6A3ACUL))) +#define bM4_DMA2_CH3CTL_IE (*((volatile unsigned int*)(0x42A6A3B0UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE0 (*((volatile unsigned int*)(0x42A6A500UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE1 (*((volatile unsigned int*)(0x42A6A504UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE2 (*((volatile unsigned int*)(0x42A6A508UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE3 (*((volatile unsigned int*)(0x42A6A50CUL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE4 (*((volatile unsigned int*)(0x42A6A510UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE5 (*((volatile unsigned int*)(0x42A6A514UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE6 (*((volatile unsigned int*)(0x42A6A518UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE7 (*((volatile unsigned int*)(0x42A6A51CUL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE8 (*((volatile unsigned int*)(0x42A6A520UL))) +#define bM4_DMA2_MONDTCTL3_BLKSIZE9 (*((volatile unsigned int*)(0x42A6A524UL))) +#define bM4_DMA2_MONDTCTL3_CNT0 (*((volatile unsigned int*)(0x42A6A540UL))) +#define bM4_DMA2_MONDTCTL3_CNT1 (*((volatile unsigned int*)(0x42A6A544UL))) +#define bM4_DMA2_MONDTCTL3_CNT2 (*((volatile unsigned int*)(0x42A6A548UL))) +#define bM4_DMA2_MONDTCTL3_CNT3 (*((volatile unsigned int*)(0x42A6A54CUL))) +#define bM4_DMA2_MONDTCTL3_CNT4 (*((volatile unsigned int*)(0x42A6A550UL))) +#define bM4_DMA2_MONDTCTL3_CNT5 (*((volatile unsigned int*)(0x42A6A554UL))) +#define bM4_DMA2_MONDTCTL3_CNT6 (*((volatile unsigned int*)(0x42A6A558UL))) +#define bM4_DMA2_MONDTCTL3_CNT7 (*((volatile unsigned int*)(0x42A6A55CUL))) +#define bM4_DMA2_MONDTCTL3_CNT8 (*((volatile unsigned int*)(0x42A6A560UL))) +#define bM4_DMA2_MONDTCTL3_CNT9 (*((volatile unsigned int*)(0x42A6A564UL))) +#define bM4_DMA2_MONDTCTL3_CNT10 (*((volatile unsigned int*)(0x42A6A568UL))) +#define bM4_DMA2_MONDTCTL3_CNT11 (*((volatile unsigned int*)(0x42A6A56CUL))) +#define bM4_DMA2_MONDTCTL3_CNT12 (*((volatile unsigned int*)(0x42A6A570UL))) +#define bM4_DMA2_MONDTCTL3_CNT13 (*((volatile unsigned int*)(0x42A6A574UL))) +#define bM4_DMA2_MONDTCTL3_CNT14 (*((volatile unsigned int*)(0x42A6A578UL))) +#define bM4_DMA2_MONDTCTL3_CNT15 (*((volatile unsigned int*)(0x42A6A57CUL))) +#define bM4_DMA2_MONRPT3_SRPT0 (*((volatile unsigned int*)(0x42A6A580UL))) +#define bM4_DMA2_MONRPT3_SRPT1 (*((volatile unsigned int*)(0x42A6A584UL))) +#define bM4_DMA2_MONRPT3_SRPT2 (*((volatile unsigned int*)(0x42A6A588UL))) +#define bM4_DMA2_MONRPT3_SRPT3 (*((volatile unsigned int*)(0x42A6A58CUL))) +#define bM4_DMA2_MONRPT3_SRPT4 (*((volatile unsigned int*)(0x42A6A590UL))) +#define bM4_DMA2_MONRPT3_SRPT5 (*((volatile unsigned int*)(0x42A6A594UL))) +#define bM4_DMA2_MONRPT3_SRPT6 (*((volatile unsigned int*)(0x42A6A598UL))) +#define bM4_DMA2_MONRPT3_SRPT7 (*((volatile unsigned int*)(0x42A6A59CUL))) +#define bM4_DMA2_MONRPT3_SRPT8 (*((volatile unsigned int*)(0x42A6A5A0UL))) +#define bM4_DMA2_MONRPT3_SRPT9 (*((volatile unsigned int*)(0x42A6A5A4UL))) +#define bM4_DMA2_MONRPT3_DRPT0 (*((volatile unsigned int*)(0x42A6A5C0UL))) +#define bM4_DMA2_MONRPT3_DRPT1 (*((volatile unsigned int*)(0x42A6A5C4UL))) +#define bM4_DMA2_MONRPT3_DRPT2 (*((volatile unsigned int*)(0x42A6A5C8UL))) +#define bM4_DMA2_MONRPT3_DRPT3 (*((volatile unsigned int*)(0x42A6A5CCUL))) +#define bM4_DMA2_MONRPT3_DRPT4 (*((volatile unsigned int*)(0x42A6A5D0UL))) +#define bM4_DMA2_MONRPT3_DRPT5 (*((volatile unsigned int*)(0x42A6A5D4UL))) +#define bM4_DMA2_MONRPT3_DRPT6 (*((volatile unsigned int*)(0x42A6A5D8UL))) +#define bM4_DMA2_MONRPT3_DRPT7 (*((volatile unsigned int*)(0x42A6A5DCUL))) +#define bM4_DMA2_MONRPT3_DRPT8 (*((volatile unsigned int*)(0x42A6A5E0UL))) +#define bM4_DMA2_MONRPT3_DRPT9 (*((volatile unsigned int*)(0x42A6A5E4UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET0 (*((volatile unsigned int*)(0x42A6A600UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET1 (*((volatile unsigned int*)(0x42A6A604UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET2 (*((volatile unsigned int*)(0x42A6A608UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET3 (*((volatile unsigned int*)(0x42A6A60CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET4 (*((volatile unsigned int*)(0x42A6A610UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET5 (*((volatile unsigned int*)(0x42A6A614UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET6 (*((volatile unsigned int*)(0x42A6A618UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET7 (*((volatile unsigned int*)(0x42A6A61CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET8 (*((volatile unsigned int*)(0x42A6A620UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET9 (*((volatile unsigned int*)(0x42A6A624UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET10 (*((volatile unsigned int*)(0x42A6A628UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET11 (*((volatile unsigned int*)(0x42A6A62CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET12 (*((volatile unsigned int*)(0x42A6A630UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET13 (*((volatile unsigned int*)(0x42A6A634UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET14 (*((volatile unsigned int*)(0x42A6A638UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET15 (*((volatile unsigned int*)(0x42A6A63CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET16 (*((volatile unsigned int*)(0x42A6A640UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET17 (*((volatile unsigned int*)(0x42A6A644UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET18 (*((volatile unsigned int*)(0x42A6A648UL))) +#define bM4_DMA2_MONSNSEQCTL3_SOFFSET19 (*((volatile unsigned int*)(0x42A6A64CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT0 (*((volatile unsigned int*)(0x42A6A650UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT1 (*((volatile unsigned int*)(0x42A6A654UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT2 (*((volatile unsigned int*)(0x42A6A658UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT3 (*((volatile unsigned int*)(0x42A6A65CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT4 (*((volatile unsigned int*)(0x42A6A660UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT5 (*((volatile unsigned int*)(0x42A6A664UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT6 (*((volatile unsigned int*)(0x42A6A668UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT7 (*((volatile unsigned int*)(0x42A6A66CUL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT8 (*((volatile unsigned int*)(0x42A6A670UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT9 (*((volatile unsigned int*)(0x42A6A674UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT10 (*((volatile unsigned int*)(0x42A6A678UL))) +#define bM4_DMA2_MONSNSEQCTL3_SNSCNT11 (*((volatile unsigned int*)(0x42A6A67CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET0 (*((volatile unsigned int*)(0x42A6A680UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET1 (*((volatile unsigned int*)(0x42A6A684UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET2 (*((volatile unsigned int*)(0x42A6A688UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET3 (*((volatile unsigned int*)(0x42A6A68CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET4 (*((volatile unsigned int*)(0x42A6A690UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET5 (*((volatile unsigned int*)(0x42A6A694UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET6 (*((volatile unsigned int*)(0x42A6A698UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET7 (*((volatile unsigned int*)(0x42A6A69CUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET8 (*((volatile unsigned int*)(0x42A6A6A0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET9 (*((volatile unsigned int*)(0x42A6A6A4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET10 (*((volatile unsigned int*)(0x42A6A6A8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET11 (*((volatile unsigned int*)(0x42A6A6ACUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET12 (*((volatile unsigned int*)(0x42A6A6B0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET13 (*((volatile unsigned int*)(0x42A6A6B4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET14 (*((volatile unsigned int*)(0x42A6A6B8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET15 (*((volatile unsigned int*)(0x42A6A6BCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET16 (*((volatile unsigned int*)(0x42A6A6C0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET17 (*((volatile unsigned int*)(0x42A6A6C4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET18 (*((volatile unsigned int*)(0x42A6A6C8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DOFFSET19 (*((volatile unsigned int*)(0x42A6A6CCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT0 (*((volatile unsigned int*)(0x42A6A6D0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT1 (*((volatile unsigned int*)(0x42A6A6D4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT2 (*((volatile unsigned int*)(0x42A6A6D8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT3 (*((volatile unsigned int*)(0x42A6A6DCUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT4 (*((volatile unsigned int*)(0x42A6A6E0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT5 (*((volatile unsigned int*)(0x42A6A6E4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT6 (*((volatile unsigned int*)(0x42A6A6E8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT7 (*((volatile unsigned int*)(0x42A6A6ECUL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT8 (*((volatile unsigned int*)(0x42A6A6F0UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT9 (*((volatile unsigned int*)(0x42A6A6F4UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT10 (*((volatile unsigned int*)(0x42A6A6F8UL))) +#define bM4_DMA2_MONDNSEQCTL3_DNSCNT11 (*((volatile unsigned int*)(0x42A6A6FCUL))) +#define bM4_EFM_FAPRT_FAPRT0 (*((volatile unsigned int*)(0x42208000UL))) +#define bM4_EFM_FAPRT_FAPRT1 (*((volatile unsigned int*)(0x42208004UL))) +#define bM4_EFM_FAPRT_FAPRT2 (*((volatile unsigned int*)(0x42208008UL))) +#define bM4_EFM_FAPRT_FAPRT3 (*((volatile unsigned int*)(0x4220800CUL))) +#define bM4_EFM_FAPRT_FAPRT4 (*((volatile unsigned int*)(0x42208010UL))) +#define bM4_EFM_FAPRT_FAPRT5 (*((volatile unsigned int*)(0x42208014UL))) +#define bM4_EFM_FAPRT_FAPRT6 (*((volatile unsigned int*)(0x42208018UL))) +#define bM4_EFM_FAPRT_FAPRT7 (*((volatile unsigned int*)(0x4220801CUL))) +#define bM4_EFM_FAPRT_FAPRT8 (*((volatile unsigned int*)(0x42208020UL))) +#define bM4_EFM_FAPRT_FAPRT9 (*((volatile unsigned int*)(0x42208024UL))) +#define bM4_EFM_FAPRT_FAPRT10 (*((volatile unsigned int*)(0x42208028UL))) +#define bM4_EFM_FAPRT_FAPRT11 (*((volatile unsigned int*)(0x4220802CUL))) +#define bM4_EFM_FAPRT_FAPRT12 (*((volatile unsigned int*)(0x42208030UL))) +#define bM4_EFM_FAPRT_FAPRT13 (*((volatile unsigned int*)(0x42208034UL))) +#define bM4_EFM_FAPRT_FAPRT14 (*((volatile unsigned int*)(0x42208038UL))) +#define bM4_EFM_FAPRT_FAPRT15 (*((volatile unsigned int*)(0x4220803CUL))) +#define bM4_EFM_FSTP_FSTP (*((volatile unsigned int*)(0x42208080UL))) +#define bM4_EFM_FRMC_SLPMD (*((volatile unsigned int*)(0x42208100UL))) +#define bM4_EFM_FRMC_FLWT0 (*((volatile unsigned int*)(0x42208110UL))) +#define bM4_EFM_FRMC_FLWT1 (*((volatile unsigned int*)(0x42208114UL))) +#define bM4_EFM_FRMC_FLWT2 (*((volatile unsigned int*)(0x42208118UL))) +#define bM4_EFM_FRMC_FLWT3 (*((volatile unsigned int*)(0x4220811CUL))) +#define bM4_EFM_FRMC_LVM (*((volatile unsigned int*)(0x42208120UL))) +#define bM4_EFM_FRMC_CACHE (*((volatile unsigned int*)(0x42208140UL))) +#define bM4_EFM_FRMC_CRST (*((volatile unsigned int*)(0x42208160UL))) +#define bM4_EFM_FWMC_PEMODE (*((volatile unsigned int*)(0x42208180UL))) +#define bM4_EFM_FWMC_PEMOD0 (*((volatile unsigned int*)(0x42208190UL))) +#define bM4_EFM_FWMC_PEMOD1 (*((volatile unsigned int*)(0x42208194UL))) +#define bM4_EFM_FWMC_PEMOD2 (*((volatile unsigned int*)(0x42208198UL))) +#define bM4_EFM_FWMC_BUSHLDCTL (*((volatile unsigned int*)(0x422081A0UL))) +#define bM4_EFM_FSR_PEWERR (*((volatile unsigned int*)(0x42208200UL))) +#define bM4_EFM_FSR_PEPRTERR (*((volatile unsigned int*)(0x42208204UL))) +#define bM4_EFM_FSR_PGSZERR (*((volatile unsigned int*)(0x42208208UL))) +#define bM4_EFM_FSR_PGMISMTCH (*((volatile unsigned int*)(0x4220820CUL))) +#define bM4_EFM_FSR_OPTEND (*((volatile unsigned int*)(0x42208210UL))) +#define bM4_EFM_FSR_COLERR (*((volatile unsigned int*)(0x42208214UL))) +#define bM4_EFM_FSR_RDY (*((volatile unsigned int*)(0x42208220UL))) +#define bM4_EFM_FSCLR_PEWERRCLR (*((volatile unsigned int*)(0x42208280UL))) +#define bM4_EFM_FSCLR_PEPRTERRCLR (*((volatile unsigned int*)(0x42208284UL))) +#define bM4_EFM_FSCLR_PGSZERRCLR (*((volatile unsigned int*)(0x42208288UL))) +#define bM4_EFM_FSCLR_PGMISMTCHCLR (*((volatile unsigned int*)(0x4220828CUL))) +#define bM4_EFM_FSCLR_OPTENDCLR (*((volatile unsigned int*)(0x42208290UL))) +#define bM4_EFM_FSCLR_COLERRCLR (*((volatile unsigned int*)(0x42208294UL))) +#define bM4_EFM_FITE_PEERRITE (*((volatile unsigned int*)(0x42208300UL))) +#define bM4_EFM_FITE_OPTENDITE (*((volatile unsigned int*)(0x42208304UL))) +#define bM4_EFM_FITE_COLERRITE (*((volatile unsigned int*)(0x42208308UL))) +#define bM4_EFM_FSWP_FSWP (*((volatile unsigned int*)(0x42208380UL))) +#define bM4_EFM_FPMTSW_FPMTSW0 (*((volatile unsigned int*)(0x42208400UL))) +#define bM4_EFM_FPMTSW_FPMTSW1 (*((volatile unsigned int*)(0x42208404UL))) +#define bM4_EFM_FPMTSW_FPMTSW2 (*((volatile unsigned int*)(0x42208408UL))) +#define bM4_EFM_FPMTSW_FPMTSW3 (*((volatile unsigned int*)(0x4220840CUL))) +#define bM4_EFM_FPMTSW_FPMTSW4 (*((volatile unsigned int*)(0x42208410UL))) +#define bM4_EFM_FPMTSW_FPMTSW5 (*((volatile unsigned int*)(0x42208414UL))) +#define bM4_EFM_FPMTSW_FPMTSW6 (*((volatile unsigned int*)(0x42208418UL))) +#define bM4_EFM_FPMTSW_FPMTSW7 (*((volatile unsigned int*)(0x4220841CUL))) +#define bM4_EFM_FPMTSW_FPMTSW8 (*((volatile unsigned int*)(0x42208420UL))) +#define bM4_EFM_FPMTSW_FPMTSW9 (*((volatile unsigned int*)(0x42208424UL))) +#define bM4_EFM_FPMTSW_FPMTSW10 (*((volatile unsigned int*)(0x42208428UL))) +#define bM4_EFM_FPMTSW_FPMTSW11 (*((volatile unsigned int*)(0x4220842CUL))) +#define bM4_EFM_FPMTSW_FPMTSW12 (*((volatile unsigned int*)(0x42208430UL))) +#define bM4_EFM_FPMTSW_FPMTSW13 (*((volatile unsigned int*)(0x42208434UL))) +#define bM4_EFM_FPMTSW_FPMTSW14 (*((volatile unsigned int*)(0x42208438UL))) +#define bM4_EFM_FPMTSW_FPMTSW15 (*((volatile unsigned int*)(0x4220843CUL))) +#define bM4_EFM_FPMTSW_FPMTSW16 (*((volatile unsigned int*)(0x42208440UL))) +#define bM4_EFM_FPMTSW_FPMTSW17 (*((volatile unsigned int*)(0x42208444UL))) +#define bM4_EFM_FPMTSW_FPMTSW18 (*((volatile unsigned int*)(0x42208448UL))) +#define bM4_EFM_FPMTEW_FPMTEW0 (*((volatile unsigned int*)(0x42208480UL))) +#define bM4_EFM_FPMTEW_FPMTEW1 (*((volatile unsigned int*)(0x42208484UL))) +#define bM4_EFM_FPMTEW_FPMTEW2 (*((volatile unsigned int*)(0x42208488UL))) +#define bM4_EFM_FPMTEW_FPMTEW3 (*((volatile unsigned int*)(0x4220848CUL))) +#define bM4_EFM_FPMTEW_FPMTEW4 (*((volatile unsigned int*)(0x42208490UL))) +#define bM4_EFM_FPMTEW_FPMTEW5 (*((volatile unsigned int*)(0x42208494UL))) +#define bM4_EFM_FPMTEW_FPMTEW6 (*((volatile unsigned int*)(0x42208498UL))) +#define bM4_EFM_FPMTEW_FPMTEW7 (*((volatile unsigned int*)(0x4220849CUL))) +#define bM4_EFM_FPMTEW_FPMTEW8 (*((volatile unsigned int*)(0x422084A0UL))) +#define bM4_EFM_FPMTEW_FPMTEW9 (*((volatile unsigned int*)(0x422084A4UL))) +#define bM4_EFM_FPMTEW_FPMTEW10 (*((volatile unsigned int*)(0x422084A8UL))) +#define bM4_EFM_FPMTEW_FPMTEW11 (*((volatile unsigned int*)(0x422084ACUL))) +#define bM4_EFM_FPMTEW_FPMTEW12 (*((volatile unsigned int*)(0x422084B0UL))) +#define bM4_EFM_FPMTEW_FPMTEW13 (*((volatile unsigned int*)(0x422084B4UL))) +#define bM4_EFM_FPMTEW_FPMTEW14 (*((volatile unsigned int*)(0x422084B8UL))) +#define bM4_EFM_FPMTEW_FPMTEW15 (*((volatile unsigned int*)(0x422084BCUL))) +#define bM4_EFM_FPMTEW_FPMTEW16 (*((volatile unsigned int*)(0x422084C0UL))) +#define bM4_EFM_FPMTEW_FPMTEW17 (*((volatile unsigned int*)(0x422084C4UL))) +#define bM4_EFM_FPMTEW_FPMTEW18 (*((volatile unsigned int*)(0x422084C8UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT0 (*((volatile unsigned int*)(0x4220A000UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT1 (*((volatile unsigned int*)(0x4220A004UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT2 (*((volatile unsigned int*)(0x4220A008UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT3 (*((volatile unsigned int*)(0x4220A00CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT4 (*((volatile unsigned int*)(0x4220A010UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT5 (*((volatile unsigned int*)(0x4220A014UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT6 (*((volatile unsigned int*)(0x4220A018UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT7 (*((volatile unsigned int*)(0x4220A01CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT8 (*((volatile unsigned int*)(0x4220A020UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT9 (*((volatile unsigned int*)(0x4220A024UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT10 (*((volatile unsigned int*)(0x4220A028UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT11 (*((volatile unsigned int*)(0x4220A02CUL))) +#define bM4_EFM_MMF_REMPRT_REMPRT12 (*((volatile unsigned int*)(0x4220A030UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT13 (*((volatile unsigned int*)(0x4220A034UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT14 (*((volatile unsigned int*)(0x4220A038UL))) +#define bM4_EFM_MMF_REMPRT_REMPRT15 (*((volatile unsigned int*)(0x4220A03CUL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE0 (*((volatile unsigned int*)(0x4220A080UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE1 (*((volatile unsigned int*)(0x4220A084UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE2 (*((volatile unsigned int*)(0x4220A088UL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE3 (*((volatile unsigned int*)(0x4220A08CUL))) +#define bM4_EFM_MMF_REMCR0_RM0SIZE4 (*((volatile unsigned int*)(0x4220A090UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR0 (*((volatile unsigned int*)(0x4220A0B0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR1 (*((volatile unsigned int*)(0x4220A0B4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR2 (*((volatile unsigned int*)(0x4220A0B8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR3 (*((volatile unsigned int*)(0x4220A0BCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR4 (*((volatile unsigned int*)(0x4220A0C0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR5 (*((volatile unsigned int*)(0x4220A0C4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR6 (*((volatile unsigned int*)(0x4220A0C8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR7 (*((volatile unsigned int*)(0x4220A0CCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR8 (*((volatile unsigned int*)(0x4220A0D0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR9 (*((volatile unsigned int*)(0x4220A0D4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR10 (*((volatile unsigned int*)(0x4220A0D8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR11 (*((volatile unsigned int*)(0x4220A0DCUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR12 (*((volatile unsigned int*)(0x4220A0E0UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR13 (*((volatile unsigned int*)(0x4220A0E4UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR14 (*((volatile unsigned int*)(0x4220A0E8UL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR15 (*((volatile unsigned int*)(0x4220A0ECUL))) +#define bM4_EFM_MMF_REMCR0_RM0TADDR16 (*((volatile unsigned int*)(0x4220A0F0UL))) +#define bM4_EFM_MMF_REMCR0_EN0 (*((volatile unsigned int*)(0x4220A0FCUL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE0 (*((volatile unsigned int*)(0x4220A100UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE1 (*((volatile unsigned int*)(0x4220A104UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE2 (*((volatile unsigned int*)(0x4220A108UL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE3 (*((volatile unsigned int*)(0x4220A10CUL))) +#define bM4_EFM_MMF_REMCR1_RM1SIZE4 (*((volatile unsigned int*)(0x4220A110UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR0 (*((volatile unsigned int*)(0x4220A130UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR1 (*((volatile unsigned int*)(0x4220A134UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR2 (*((volatile unsigned int*)(0x4220A138UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR3 (*((volatile unsigned int*)(0x4220A13CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR4 (*((volatile unsigned int*)(0x4220A140UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR5 (*((volatile unsigned int*)(0x4220A144UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR6 (*((volatile unsigned int*)(0x4220A148UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR7 (*((volatile unsigned int*)(0x4220A14CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR8 (*((volatile unsigned int*)(0x4220A150UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR9 (*((volatile unsigned int*)(0x4220A154UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR10 (*((volatile unsigned int*)(0x4220A158UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR11 (*((volatile unsigned int*)(0x4220A15CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR12 (*((volatile unsigned int*)(0x4220A160UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR13 (*((volatile unsigned int*)(0x4220A164UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR14 (*((volatile unsigned int*)(0x4220A168UL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR15 (*((volatile unsigned int*)(0x4220A16CUL))) +#define bM4_EFM_MMF_REMCR1_RM1TADDR16 (*((volatile unsigned int*)(0x4220A170UL))) +#define bM4_EFM_MMF_REMCR1_EN1 (*((volatile unsigned int*)(0x4220A17CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS0 (*((volatile unsigned int*)(0x4220C084UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS1 (*((volatile unsigned int*)(0x4220C088UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS2 (*((volatile unsigned int*)(0x4220C08CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS3 (*((volatile unsigned int*)(0x4220C090UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS4 (*((volatile unsigned int*)(0x4220C094UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS5 (*((volatile unsigned int*)(0x4220C098UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS6 (*((volatile unsigned int*)(0x4220C09CUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS7 (*((volatile unsigned int*)(0x4220C0A0UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS8 (*((volatile unsigned int*)(0x4220C0A4UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS9 (*((volatile unsigned int*)(0x4220C0A8UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS10 (*((volatile unsigned int*)(0x4220C0ACUL))) +#define bM4_EFM_EFM_FRANDS_FRANDS11 (*((volatile unsigned int*)(0x4220C0B0UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS12 (*((volatile unsigned int*)(0x4220C0B4UL))) +#define bM4_EFM_EFM_FRANDS_FRANDS13 (*((volatile unsigned int*)(0x4220C0B8UL))) +#define bM4_EFM_EFM_FRANDS_FRANDFG (*((volatile unsigned int*)(0x4220C0C0UL))) +#define bM4_EMB1_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8000UL))) +#define bM4_EMB1_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8004UL))) +#define bM4_EMB1_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8008UL))) +#define bM4_EMB1_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F800CUL))) +#define bM4_EMB1_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8014UL))) +#define bM4_EMB1_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8018UL))) +#define bM4_EMB1_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F801CUL))) +#define bM4_EMB1_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8020UL))) +#define bM4_EMB1_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8070UL))) +#define bM4_EMB1_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8074UL))) +#define bM4_EMB1_CTL_NFEN (*((volatile unsigned int*)(0x422F8078UL))) +#define bM4_EMB1_CTL_INVSEL (*((volatile unsigned int*)(0x422F807CUL))) +#define bM4_EMB1_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8080UL))) +#define bM4_EMB1_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8084UL))) +#define bM4_EMB1_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8088UL))) +#define bM4_EMB1_SOE_SOE (*((volatile unsigned int*)(0x422F8100UL))) +#define bM4_EMB1_STAT_PORTINF (*((volatile unsigned int*)(0x422F8180UL))) +#define bM4_EMB1_STAT_PWMSF (*((volatile unsigned int*)(0x422F8184UL))) +#define bM4_EMB1_STAT_CMPF (*((volatile unsigned int*)(0x422F8188UL))) +#define bM4_EMB1_STAT_OSF (*((volatile unsigned int*)(0x422F818CUL))) +#define bM4_EMB1_STAT_PORTINST (*((volatile unsigned int*)(0x422F8190UL))) +#define bM4_EMB1_STAT_PWMST (*((volatile unsigned int*)(0x422F8194UL))) +#define bM4_EMB1_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8200UL))) +#define bM4_EMB1_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8204UL))) +#define bM4_EMB1_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8208UL))) +#define bM4_EMB1_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F820CUL))) +#define bM4_EMB1_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8280UL))) +#define bM4_EMB1_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8284UL))) +#define bM4_EMB1_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8288UL))) +#define bM4_EMB1_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F828CUL))) +#define bM4_EMB2_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8400UL))) +#define bM4_EMB2_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8404UL))) +#define bM4_EMB2_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8408UL))) +#define bM4_EMB2_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F840CUL))) +#define bM4_EMB2_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8414UL))) +#define bM4_EMB2_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8418UL))) +#define bM4_EMB2_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F841CUL))) +#define bM4_EMB2_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8420UL))) +#define bM4_EMB2_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8470UL))) +#define bM4_EMB2_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8474UL))) +#define bM4_EMB2_CTL_NFEN (*((volatile unsigned int*)(0x422F8478UL))) +#define bM4_EMB2_CTL_INVSEL (*((volatile unsigned int*)(0x422F847CUL))) +#define bM4_EMB2_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8480UL))) +#define bM4_EMB2_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8484UL))) +#define bM4_EMB2_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8488UL))) +#define bM4_EMB2_SOE_SOE (*((volatile unsigned int*)(0x422F8500UL))) +#define bM4_EMB2_STAT_PORTINF (*((volatile unsigned int*)(0x422F8580UL))) +#define bM4_EMB2_STAT_PWMSF (*((volatile unsigned int*)(0x422F8584UL))) +#define bM4_EMB2_STAT_CMPF (*((volatile unsigned int*)(0x422F8588UL))) +#define bM4_EMB2_STAT_OSF (*((volatile unsigned int*)(0x422F858CUL))) +#define bM4_EMB2_STAT_PORTINST (*((volatile unsigned int*)(0x422F8590UL))) +#define bM4_EMB2_STAT_PWMST (*((volatile unsigned int*)(0x422F8594UL))) +#define bM4_EMB2_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8600UL))) +#define bM4_EMB2_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8604UL))) +#define bM4_EMB2_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8608UL))) +#define bM4_EMB2_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F860CUL))) +#define bM4_EMB2_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8680UL))) +#define bM4_EMB2_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8684UL))) +#define bM4_EMB2_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8688UL))) +#define bM4_EMB2_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F868CUL))) +#define bM4_EMB3_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8800UL))) +#define bM4_EMB3_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8804UL))) +#define bM4_EMB3_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8808UL))) +#define bM4_EMB3_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F880CUL))) +#define bM4_EMB3_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8814UL))) +#define bM4_EMB3_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8818UL))) +#define bM4_EMB3_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F881CUL))) +#define bM4_EMB3_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8820UL))) +#define bM4_EMB3_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8870UL))) +#define bM4_EMB3_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8874UL))) +#define bM4_EMB3_CTL_NFEN (*((volatile unsigned int*)(0x422F8878UL))) +#define bM4_EMB3_CTL_INVSEL (*((volatile unsigned int*)(0x422F887CUL))) +#define bM4_EMB3_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8880UL))) +#define bM4_EMB3_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8884UL))) +#define bM4_EMB3_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8888UL))) +#define bM4_EMB3_SOE_SOE (*((volatile unsigned int*)(0x422F8900UL))) +#define bM4_EMB3_STAT_PORTINF (*((volatile unsigned int*)(0x422F8980UL))) +#define bM4_EMB3_STAT_PWMSF (*((volatile unsigned int*)(0x422F8984UL))) +#define bM4_EMB3_STAT_CMPF (*((volatile unsigned int*)(0x422F8988UL))) +#define bM4_EMB3_STAT_OSF (*((volatile unsigned int*)(0x422F898CUL))) +#define bM4_EMB3_STAT_PORTINST (*((volatile unsigned int*)(0x422F8990UL))) +#define bM4_EMB3_STAT_PWMST (*((volatile unsigned int*)(0x422F8994UL))) +#define bM4_EMB3_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8A00UL))) +#define bM4_EMB3_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8A04UL))) +#define bM4_EMB3_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8A08UL))) +#define bM4_EMB3_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F8A0CUL))) +#define bM4_EMB3_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8A80UL))) +#define bM4_EMB3_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8A84UL))) +#define bM4_EMB3_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8A88UL))) +#define bM4_EMB3_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F8A8CUL))) +#define bM4_EMB4_CTL_PORTINEN (*((volatile unsigned int*)(0x422F8C00UL))) +#define bM4_EMB4_CTL_CMPEN0 (*((volatile unsigned int*)(0x422F8C04UL))) +#define bM4_EMB4_CTL_CMPEN1 (*((volatile unsigned int*)(0x422F8C08UL))) +#define bM4_EMB4_CTL_CMPEN2 (*((volatile unsigned int*)(0x422F8C0CUL))) +#define bM4_EMB4_CTL_OSCSTPEN (*((volatile unsigned int*)(0x422F8C14UL))) +#define bM4_EMB4_CTL_PWMSEN0 (*((volatile unsigned int*)(0x422F8C18UL))) +#define bM4_EMB4_CTL_PWMSEN1 (*((volatile unsigned int*)(0x422F8C1CUL))) +#define bM4_EMB4_CTL_PWMSEN2 (*((volatile unsigned int*)(0x422F8C20UL))) +#define bM4_EMB4_CTL_NFSEL0 (*((volatile unsigned int*)(0x422F8C70UL))) +#define bM4_EMB4_CTL_NFSEL1 (*((volatile unsigned int*)(0x422F8C74UL))) +#define bM4_EMB4_CTL_NFEN (*((volatile unsigned int*)(0x422F8C78UL))) +#define bM4_EMB4_CTL_INVSEL (*((volatile unsigned int*)(0x422F8C7CUL))) +#define bM4_EMB4_PWMLV_PWMLV0 (*((volatile unsigned int*)(0x422F8C80UL))) +#define bM4_EMB4_PWMLV_PWMLV1 (*((volatile unsigned int*)(0x422F8C84UL))) +#define bM4_EMB4_PWMLV_PWMLV2 (*((volatile unsigned int*)(0x422F8C88UL))) +#define bM4_EMB4_SOE_SOE (*((volatile unsigned int*)(0x422F8D00UL))) +#define bM4_EMB4_STAT_PORTINF (*((volatile unsigned int*)(0x422F8D80UL))) +#define bM4_EMB4_STAT_PWMSF (*((volatile unsigned int*)(0x422F8D84UL))) +#define bM4_EMB4_STAT_CMPF (*((volatile unsigned int*)(0x422F8D88UL))) +#define bM4_EMB4_STAT_OSF (*((volatile unsigned int*)(0x422F8D8CUL))) +#define bM4_EMB4_STAT_PORTINST (*((volatile unsigned int*)(0x422F8D90UL))) +#define bM4_EMB4_STAT_PWMST (*((volatile unsigned int*)(0x422F8D94UL))) +#define bM4_EMB4_STATCLR_PORTINFCLR (*((volatile unsigned int*)(0x422F8E00UL))) +#define bM4_EMB4_STATCLR_PWMSFCLR (*((volatile unsigned int*)(0x422F8E04UL))) +#define bM4_EMB4_STATCLR_CMPFCLR (*((volatile unsigned int*)(0x422F8E08UL))) +#define bM4_EMB4_STATCLR_OSFCLR (*((volatile unsigned int*)(0x422F8E0CUL))) +#define bM4_EMB4_INTEN_PORTINTEN (*((volatile unsigned int*)(0x422F8E80UL))) +#define bM4_EMB4_INTEN_PWMINTEN (*((volatile unsigned int*)(0x422F8E84UL))) +#define bM4_EMB4_INTEN_CMPINTEN (*((volatile unsigned int*)(0x422F8E88UL))) +#define bM4_EMB4_INTEN_OSINTEN (*((volatile unsigned int*)(0x422F8E8CUL))) +#define bM4_FCM_LVR_LVR0 (*((volatile unsigned int*)(0x42908000UL))) +#define bM4_FCM_LVR_LVR1 (*((volatile unsigned int*)(0x42908004UL))) +#define bM4_FCM_LVR_LVR2 (*((volatile unsigned int*)(0x42908008UL))) +#define bM4_FCM_LVR_LVR3 (*((volatile unsigned int*)(0x4290800CUL))) +#define bM4_FCM_LVR_LVR4 (*((volatile unsigned int*)(0x42908010UL))) +#define bM4_FCM_LVR_LVR5 (*((volatile unsigned int*)(0x42908014UL))) +#define bM4_FCM_LVR_LVR6 (*((volatile unsigned int*)(0x42908018UL))) +#define bM4_FCM_LVR_LVR7 (*((volatile unsigned int*)(0x4290801CUL))) +#define bM4_FCM_LVR_LVR8 (*((volatile unsigned int*)(0x42908020UL))) +#define bM4_FCM_LVR_LVR9 (*((volatile unsigned int*)(0x42908024UL))) +#define bM4_FCM_LVR_LVR10 (*((volatile unsigned int*)(0x42908028UL))) +#define bM4_FCM_LVR_LVR11 (*((volatile unsigned int*)(0x4290802CUL))) +#define bM4_FCM_LVR_LVR12 (*((volatile unsigned int*)(0x42908030UL))) +#define bM4_FCM_LVR_LVR13 (*((volatile unsigned int*)(0x42908034UL))) +#define bM4_FCM_LVR_LVR14 (*((volatile unsigned int*)(0x42908038UL))) +#define bM4_FCM_LVR_LVR15 (*((volatile unsigned int*)(0x4290803CUL))) +#define bM4_FCM_UVR_UVR0 (*((volatile unsigned int*)(0x42908080UL))) +#define bM4_FCM_UVR_UVR1 (*((volatile unsigned int*)(0x42908084UL))) +#define bM4_FCM_UVR_UVR2 (*((volatile unsigned int*)(0x42908088UL))) +#define bM4_FCM_UVR_UVR3 (*((volatile unsigned int*)(0x4290808CUL))) +#define bM4_FCM_UVR_UVR4 (*((volatile unsigned int*)(0x42908090UL))) +#define bM4_FCM_UVR_UVR5 (*((volatile unsigned int*)(0x42908094UL))) +#define bM4_FCM_UVR_UVR6 (*((volatile unsigned int*)(0x42908098UL))) +#define bM4_FCM_UVR_UVR7 (*((volatile unsigned int*)(0x4290809CUL))) +#define bM4_FCM_UVR_UVR8 (*((volatile unsigned int*)(0x429080A0UL))) +#define bM4_FCM_UVR_UVR9 (*((volatile unsigned int*)(0x429080A4UL))) +#define bM4_FCM_UVR_UVR10 (*((volatile unsigned int*)(0x429080A8UL))) +#define bM4_FCM_UVR_UVR11 (*((volatile unsigned int*)(0x429080ACUL))) +#define bM4_FCM_UVR_UVR12 (*((volatile unsigned int*)(0x429080B0UL))) +#define bM4_FCM_UVR_UVR13 (*((volatile unsigned int*)(0x429080B4UL))) +#define bM4_FCM_UVR_UVR14 (*((volatile unsigned int*)(0x429080B8UL))) +#define bM4_FCM_UVR_UVR15 (*((volatile unsigned int*)(0x429080BCUL))) +#define bM4_FCM_CNTR_CNTR0 (*((volatile unsigned int*)(0x42908100UL))) +#define bM4_FCM_CNTR_CNTR1 (*((volatile unsigned int*)(0x42908104UL))) +#define bM4_FCM_CNTR_CNTR2 (*((volatile unsigned int*)(0x42908108UL))) +#define bM4_FCM_CNTR_CNTR3 (*((volatile unsigned int*)(0x4290810CUL))) +#define bM4_FCM_CNTR_CNTR4 (*((volatile unsigned int*)(0x42908110UL))) +#define bM4_FCM_CNTR_CNTR5 (*((volatile unsigned int*)(0x42908114UL))) +#define bM4_FCM_CNTR_CNTR6 (*((volatile unsigned int*)(0x42908118UL))) +#define bM4_FCM_CNTR_CNTR7 (*((volatile unsigned int*)(0x4290811CUL))) +#define bM4_FCM_CNTR_CNTR8 (*((volatile unsigned int*)(0x42908120UL))) +#define bM4_FCM_CNTR_CNTR9 (*((volatile unsigned int*)(0x42908124UL))) +#define bM4_FCM_CNTR_CNTR10 (*((volatile unsigned int*)(0x42908128UL))) +#define bM4_FCM_CNTR_CNTR11 (*((volatile unsigned int*)(0x4290812CUL))) +#define bM4_FCM_CNTR_CNTR12 (*((volatile unsigned int*)(0x42908130UL))) +#define bM4_FCM_CNTR_CNTR13 (*((volatile unsigned int*)(0x42908134UL))) +#define bM4_FCM_CNTR_CNTR14 (*((volatile unsigned int*)(0x42908138UL))) +#define bM4_FCM_CNTR_CNTR15 (*((volatile unsigned int*)(0x4290813CUL))) +#define bM4_FCM_STR_START (*((volatile unsigned int*)(0x42908180UL))) +#define bM4_FCM_MCCR_MDIVS0 (*((volatile unsigned int*)(0x42908200UL))) +#define bM4_FCM_MCCR_MDIVS1 (*((volatile unsigned int*)(0x42908204UL))) +#define bM4_FCM_MCCR_MCKS0 (*((volatile unsigned int*)(0x42908210UL))) +#define bM4_FCM_MCCR_MCKS1 (*((volatile unsigned int*)(0x42908214UL))) +#define bM4_FCM_MCCR_MCKS2 (*((volatile unsigned int*)(0x42908218UL))) +#define bM4_FCM_MCCR_MCKS3 (*((volatile unsigned int*)(0x4290821CUL))) +#define bM4_FCM_RCCR_RDIVS0 (*((volatile unsigned int*)(0x42908280UL))) +#define bM4_FCM_RCCR_RDIVS1 (*((volatile unsigned int*)(0x42908284UL))) +#define bM4_FCM_RCCR_RCKS0 (*((volatile unsigned int*)(0x4290828CUL))) +#define bM4_FCM_RCCR_RCKS1 (*((volatile unsigned int*)(0x42908290UL))) +#define bM4_FCM_RCCR_RCKS2 (*((volatile unsigned int*)(0x42908294UL))) +#define bM4_FCM_RCCR_RCKS3 (*((volatile unsigned int*)(0x42908298UL))) +#define bM4_FCM_RCCR_INEXS (*((volatile unsigned int*)(0x4290829CUL))) +#define bM4_FCM_RCCR_DNFS0 (*((volatile unsigned int*)(0x429082A0UL))) +#define bM4_FCM_RCCR_DNFS1 (*((volatile unsigned int*)(0x429082A4UL))) +#define bM4_FCM_RCCR_EDGES0 (*((volatile unsigned int*)(0x429082B0UL))) +#define bM4_FCM_RCCR_EDGES1 (*((volatile unsigned int*)(0x429082B4UL))) +#define bM4_FCM_RCCR_EXREFE (*((volatile unsigned int*)(0x429082BCUL))) +#define bM4_FCM_RIER_ERRIE (*((volatile unsigned int*)(0x42908300UL))) +#define bM4_FCM_RIER_MENDIE (*((volatile unsigned int*)(0x42908304UL))) +#define bM4_FCM_RIER_OVFIE (*((volatile unsigned int*)(0x42908308UL))) +#define bM4_FCM_RIER_ERRINTRS (*((volatile unsigned int*)(0x42908310UL))) +#define bM4_FCM_RIER_ERRE (*((volatile unsigned int*)(0x4290831CUL))) +#define bM4_FCM_SR_ERRF (*((volatile unsigned int*)(0x42908380UL))) +#define bM4_FCM_SR_MENDF (*((volatile unsigned int*)(0x42908384UL))) +#define bM4_FCM_SR_OVF (*((volatile unsigned int*)(0x42908388UL))) +#define bM4_FCM_CLR_ERRFCLR (*((volatile unsigned int*)(0x42908400UL))) +#define bM4_FCM_CLR_MENDFCLR (*((volatile unsigned int*)(0x42908404UL))) +#define bM4_FCM_CLR_OVFCLR (*((volatile unsigned int*)(0x42908408UL))) +#define bM4_HASH_CR_START (*((volatile unsigned int*)(0x42108000UL))) +#define bM4_HASH_CR_FST_GRP (*((volatile unsigned int*)(0x42108004UL))) +#define bM4_I2C1_CR1_PE (*((volatile unsigned int*)(0x429C0000UL))) +#define bM4_I2C1_CR1_SMBUS (*((volatile unsigned int*)(0x429C0004UL))) +#define bM4_I2C1_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429C0008UL))) +#define bM4_I2C1_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429C000CUL))) +#define bM4_I2C1_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429C0010UL))) +#define bM4_I2C1_CR1_ENGC (*((volatile unsigned int*)(0x429C0018UL))) +#define bM4_I2C1_CR1_RESTART (*((volatile unsigned int*)(0x429C001CUL))) +#define bM4_I2C1_CR1_START (*((volatile unsigned int*)(0x429C0020UL))) +#define bM4_I2C1_CR1_STOP (*((volatile unsigned int*)(0x429C0024UL))) +#define bM4_I2C1_CR1_ACK (*((volatile unsigned int*)(0x429C0028UL))) +#define bM4_I2C1_CR1_SWRST (*((volatile unsigned int*)(0x429C003CUL))) +#define bM4_I2C1_CR2_STARTIE (*((volatile unsigned int*)(0x429C0080UL))) +#define bM4_I2C1_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429C0084UL))) +#define bM4_I2C1_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429C0088UL))) +#define bM4_I2C1_CR2_TENDIE (*((volatile unsigned int*)(0x429C008CUL))) +#define bM4_I2C1_CR2_STOPIE (*((volatile unsigned int*)(0x429C0090UL))) +#define bM4_I2C1_CR2_RFULLIE (*((volatile unsigned int*)(0x429C0098UL))) +#define bM4_I2C1_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429C009CUL))) +#define bM4_I2C1_CR2_ARLOIE (*((volatile unsigned int*)(0x429C00A4UL))) +#define bM4_I2C1_CR2_NACKIE (*((volatile unsigned int*)(0x429C00B0UL))) +#define bM4_I2C1_CR2_TMOUTIE (*((volatile unsigned int*)(0x429C00B8UL))) +#define bM4_I2C1_CR2_GENCALLIE (*((volatile unsigned int*)(0x429C00D0UL))) +#define bM4_I2C1_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429C00D4UL))) +#define bM4_I2C1_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429C00D8UL))) +#define bM4_I2C1_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429C00DCUL))) +#define bM4_I2C1_CR3_TMOUTEN (*((volatile unsigned int*)(0x429C0100UL))) +#define bM4_I2C1_CR3_LTMOUT (*((volatile unsigned int*)(0x429C0104UL))) +#define bM4_I2C1_CR3_HTMOUT (*((volatile unsigned int*)(0x429C0108UL))) +#define bM4_I2C1_CR3_FACKEN (*((volatile unsigned int*)(0x429C011CUL))) +#define bM4_I2C1_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429C0200UL))) +#define bM4_I2C1_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429C0204UL))) +#define bM4_I2C1_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429C0208UL))) +#define bM4_I2C1_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429C020CUL))) +#define bM4_I2C1_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429C0210UL))) +#define bM4_I2C1_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429C0214UL))) +#define bM4_I2C1_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429C0218UL))) +#define bM4_I2C1_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429C021CUL))) +#define bM4_I2C1_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429C0220UL))) +#define bM4_I2C1_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429C0224UL))) +#define bM4_I2C1_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429C0230UL))) +#define bM4_I2C1_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429C023CUL))) +#define bM4_I2C1_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429C0280UL))) +#define bM4_I2C1_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429C0284UL))) +#define bM4_I2C1_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429C0288UL))) +#define bM4_I2C1_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429C028CUL))) +#define bM4_I2C1_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429C0290UL))) +#define bM4_I2C1_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429C0294UL))) +#define bM4_I2C1_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429C0298UL))) +#define bM4_I2C1_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429C029CUL))) +#define bM4_I2C1_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429C02A0UL))) +#define bM4_I2C1_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429C02A4UL))) +#define bM4_I2C1_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429C02B0UL))) +#define bM4_I2C1_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429C02BCUL))) +#define bM4_I2C1_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429C0300UL))) +#define bM4_I2C1_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429C0304UL))) +#define bM4_I2C1_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429C0308UL))) +#define bM4_I2C1_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429C030CUL))) +#define bM4_I2C1_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429C0310UL))) +#define bM4_I2C1_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429C0314UL))) +#define bM4_I2C1_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429C0318UL))) +#define bM4_I2C1_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429C031CUL))) +#define bM4_I2C1_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429C0320UL))) +#define bM4_I2C1_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429C0324UL))) +#define bM4_I2C1_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429C0328UL))) +#define bM4_I2C1_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429C032CUL))) +#define bM4_I2C1_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429C0330UL))) +#define bM4_I2C1_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429C0334UL))) +#define bM4_I2C1_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429C0338UL))) +#define bM4_I2C1_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429C033CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429C0340UL))) +#define bM4_I2C1_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429C0344UL))) +#define bM4_I2C1_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429C0348UL))) +#define bM4_I2C1_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429C034CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429C0350UL))) +#define bM4_I2C1_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429C0354UL))) +#define bM4_I2C1_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429C0358UL))) +#define bM4_I2C1_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429C035CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429C0360UL))) +#define bM4_I2C1_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429C0364UL))) +#define bM4_I2C1_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429C0368UL))) +#define bM4_I2C1_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429C036CUL))) +#define bM4_I2C1_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429C0370UL))) +#define bM4_I2C1_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429C0374UL))) +#define bM4_I2C1_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429C0378UL))) +#define bM4_I2C1_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429C037CUL))) +#define bM4_I2C1_SR_STARTF (*((volatile unsigned int*)(0x429C0380UL))) +#define bM4_I2C1_SR_SLADDR0F (*((volatile unsigned int*)(0x429C0384UL))) +#define bM4_I2C1_SR_SLADDR1F (*((volatile unsigned int*)(0x429C0388UL))) +#define bM4_I2C1_SR_TENDF (*((volatile unsigned int*)(0x429C038CUL))) +#define bM4_I2C1_SR_STOPF (*((volatile unsigned int*)(0x429C0390UL))) +#define bM4_I2C1_SR_RFULLF (*((volatile unsigned int*)(0x429C0398UL))) +#define bM4_I2C1_SR_TEMPTYF (*((volatile unsigned int*)(0x429C039CUL))) +#define bM4_I2C1_SR_ARLOF (*((volatile unsigned int*)(0x429C03A4UL))) +#define bM4_I2C1_SR_ACKRF (*((volatile unsigned int*)(0x429C03A8UL))) +#define bM4_I2C1_SR_NACKF (*((volatile unsigned int*)(0x429C03B0UL))) +#define bM4_I2C1_SR_TMOUTF (*((volatile unsigned int*)(0x429C03B8UL))) +#define bM4_I2C1_SR_MSL (*((volatile unsigned int*)(0x429C03C0UL))) +#define bM4_I2C1_SR_BUSY (*((volatile unsigned int*)(0x429C03C4UL))) +#define bM4_I2C1_SR_TRA (*((volatile unsigned int*)(0x429C03C8UL))) +#define bM4_I2C1_SR_GENCALLF (*((volatile unsigned int*)(0x429C03D0UL))) +#define bM4_I2C1_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429C03D4UL))) +#define bM4_I2C1_SR_SMBHOSTF (*((volatile unsigned int*)(0x429C03D8UL))) +#define bM4_I2C1_SR_SMBALRTF (*((volatile unsigned int*)(0x429C03DCUL))) +#define bM4_I2C1_CLR_STARTFCLR (*((volatile unsigned int*)(0x429C0400UL))) +#define bM4_I2C1_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429C0404UL))) +#define bM4_I2C1_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429C0408UL))) +#define bM4_I2C1_CLR_TENDFCLR (*((volatile unsigned int*)(0x429C040CUL))) +#define bM4_I2C1_CLR_STOPFCLR (*((volatile unsigned int*)(0x429C0410UL))) +#define bM4_I2C1_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429C0418UL))) +#define bM4_I2C1_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429C041CUL))) +#define bM4_I2C1_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429C0424UL))) +#define bM4_I2C1_CLR_NACKFCLR (*((volatile unsigned int*)(0x429C0430UL))) +#define bM4_I2C1_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429C0438UL))) +#define bM4_I2C1_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429C0450UL))) +#define bM4_I2C1_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429C0454UL))) +#define bM4_I2C1_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429C0458UL))) +#define bM4_I2C1_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429C045CUL))) +#define bM4_I2C1_DTR_DT0 (*((volatile unsigned int*)(0x429C0480UL))) +#define bM4_I2C1_DTR_DT1 (*((volatile unsigned int*)(0x429C0484UL))) +#define bM4_I2C1_DTR_DT2 (*((volatile unsigned int*)(0x429C0488UL))) +#define bM4_I2C1_DTR_DT3 (*((volatile unsigned int*)(0x429C048CUL))) +#define bM4_I2C1_DTR_DT4 (*((volatile unsigned int*)(0x429C0490UL))) +#define bM4_I2C1_DTR_DT5 (*((volatile unsigned int*)(0x429C0494UL))) +#define bM4_I2C1_DTR_DT6 (*((volatile unsigned int*)(0x429C0498UL))) +#define bM4_I2C1_DTR_DT7 (*((volatile unsigned int*)(0x429C049CUL))) +#define bM4_I2C1_DRR_DR0 (*((volatile unsigned int*)(0x429C0500UL))) +#define bM4_I2C1_DRR_DR1 (*((volatile unsigned int*)(0x429C0504UL))) +#define bM4_I2C1_DRR_DR2 (*((volatile unsigned int*)(0x429C0508UL))) +#define bM4_I2C1_DRR_DR3 (*((volatile unsigned int*)(0x429C050CUL))) +#define bM4_I2C1_DRR_DR4 (*((volatile unsigned int*)(0x429C0510UL))) +#define bM4_I2C1_DRR_DR5 (*((volatile unsigned int*)(0x429C0514UL))) +#define bM4_I2C1_DRR_DR6 (*((volatile unsigned int*)(0x429C0518UL))) +#define bM4_I2C1_DRR_DR7 (*((volatile unsigned int*)(0x429C051CUL))) +#define bM4_I2C1_CCR_SLOWW0 (*((volatile unsigned int*)(0x429C0580UL))) +#define bM4_I2C1_CCR_SLOWW1 (*((volatile unsigned int*)(0x429C0584UL))) +#define bM4_I2C1_CCR_SLOWW2 (*((volatile unsigned int*)(0x429C0588UL))) +#define bM4_I2C1_CCR_SLOWW3 (*((volatile unsigned int*)(0x429C058CUL))) +#define bM4_I2C1_CCR_SLOWW4 (*((volatile unsigned int*)(0x429C0590UL))) +#define bM4_I2C1_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429C05A0UL))) +#define bM4_I2C1_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429C05A4UL))) +#define bM4_I2C1_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429C05A8UL))) +#define bM4_I2C1_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429C05ACUL))) +#define bM4_I2C1_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429C05B0UL))) +#define bM4_I2C1_CCR_FREQ0 (*((volatile unsigned int*)(0x429C05C0UL))) +#define bM4_I2C1_CCR_FREQ1 (*((volatile unsigned int*)(0x429C05C4UL))) +#define bM4_I2C1_CCR_FREQ2 (*((volatile unsigned int*)(0x429C05C8UL))) +#define bM4_I2C1_FLTR_DNF0 (*((volatile unsigned int*)(0x429C0600UL))) +#define bM4_I2C1_FLTR_DNF1 (*((volatile unsigned int*)(0x429C0604UL))) +#define bM4_I2C1_FLTR_DNFEN (*((volatile unsigned int*)(0x429C0610UL))) +#define bM4_I2C1_FLTR_ANFEN (*((volatile unsigned int*)(0x429C0614UL))) +#define bM4_I2C2_CR1_PE (*((volatile unsigned int*)(0x429C8000UL))) +#define bM4_I2C2_CR1_SMBUS (*((volatile unsigned int*)(0x429C8004UL))) +#define bM4_I2C2_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429C8008UL))) +#define bM4_I2C2_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429C800CUL))) +#define bM4_I2C2_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429C8010UL))) +#define bM4_I2C2_CR1_ENGC (*((volatile unsigned int*)(0x429C8018UL))) +#define bM4_I2C2_CR1_RESTART (*((volatile unsigned int*)(0x429C801CUL))) +#define bM4_I2C2_CR1_START (*((volatile unsigned int*)(0x429C8020UL))) +#define bM4_I2C2_CR1_STOP (*((volatile unsigned int*)(0x429C8024UL))) +#define bM4_I2C2_CR1_ACK (*((volatile unsigned int*)(0x429C8028UL))) +#define bM4_I2C2_CR1_SWRST (*((volatile unsigned int*)(0x429C803CUL))) +#define bM4_I2C2_CR2_STARTIE (*((volatile unsigned int*)(0x429C8080UL))) +#define bM4_I2C2_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429C8084UL))) +#define bM4_I2C2_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429C8088UL))) +#define bM4_I2C2_CR2_TENDIE (*((volatile unsigned int*)(0x429C808CUL))) +#define bM4_I2C2_CR2_STOPIE (*((volatile unsigned int*)(0x429C8090UL))) +#define bM4_I2C2_CR2_RFULLIE (*((volatile unsigned int*)(0x429C8098UL))) +#define bM4_I2C2_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429C809CUL))) +#define bM4_I2C2_CR2_ARLOIE (*((volatile unsigned int*)(0x429C80A4UL))) +#define bM4_I2C2_CR2_NACKIE (*((volatile unsigned int*)(0x429C80B0UL))) +#define bM4_I2C2_CR2_TMOUTIE (*((volatile unsigned int*)(0x429C80B8UL))) +#define bM4_I2C2_CR2_GENCALLIE (*((volatile unsigned int*)(0x429C80D0UL))) +#define bM4_I2C2_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429C80D4UL))) +#define bM4_I2C2_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429C80D8UL))) +#define bM4_I2C2_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429C80DCUL))) +#define bM4_I2C2_CR3_TMOUTEN (*((volatile unsigned int*)(0x429C8100UL))) +#define bM4_I2C2_CR3_LTMOUT (*((volatile unsigned int*)(0x429C8104UL))) +#define bM4_I2C2_CR3_HTMOUT (*((volatile unsigned int*)(0x429C8108UL))) +#define bM4_I2C2_CR3_FACKEN (*((volatile unsigned int*)(0x429C811CUL))) +#define bM4_I2C2_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429C8200UL))) +#define bM4_I2C2_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429C8204UL))) +#define bM4_I2C2_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429C8208UL))) +#define bM4_I2C2_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429C820CUL))) +#define bM4_I2C2_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429C8210UL))) +#define bM4_I2C2_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429C8214UL))) +#define bM4_I2C2_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429C8218UL))) +#define bM4_I2C2_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429C821CUL))) +#define bM4_I2C2_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429C8220UL))) +#define bM4_I2C2_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429C8224UL))) +#define bM4_I2C2_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429C8230UL))) +#define bM4_I2C2_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429C823CUL))) +#define bM4_I2C2_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429C8280UL))) +#define bM4_I2C2_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429C8284UL))) +#define bM4_I2C2_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429C8288UL))) +#define bM4_I2C2_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429C828CUL))) +#define bM4_I2C2_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429C8290UL))) +#define bM4_I2C2_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429C8294UL))) +#define bM4_I2C2_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429C8298UL))) +#define bM4_I2C2_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429C829CUL))) +#define bM4_I2C2_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429C82A0UL))) +#define bM4_I2C2_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429C82A4UL))) +#define bM4_I2C2_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429C82B0UL))) +#define bM4_I2C2_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429C82BCUL))) +#define bM4_I2C2_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429C8300UL))) +#define bM4_I2C2_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429C8304UL))) +#define bM4_I2C2_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429C8308UL))) +#define bM4_I2C2_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429C830CUL))) +#define bM4_I2C2_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429C8310UL))) +#define bM4_I2C2_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429C8314UL))) +#define bM4_I2C2_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429C8318UL))) +#define bM4_I2C2_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429C831CUL))) +#define bM4_I2C2_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429C8320UL))) +#define bM4_I2C2_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429C8324UL))) +#define bM4_I2C2_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429C8328UL))) +#define bM4_I2C2_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429C832CUL))) +#define bM4_I2C2_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429C8330UL))) +#define bM4_I2C2_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429C8334UL))) +#define bM4_I2C2_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429C8338UL))) +#define bM4_I2C2_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429C833CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429C8340UL))) +#define bM4_I2C2_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429C8344UL))) +#define bM4_I2C2_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429C8348UL))) +#define bM4_I2C2_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429C834CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429C8350UL))) +#define bM4_I2C2_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429C8354UL))) +#define bM4_I2C2_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429C8358UL))) +#define bM4_I2C2_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429C835CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429C8360UL))) +#define bM4_I2C2_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429C8364UL))) +#define bM4_I2C2_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429C8368UL))) +#define bM4_I2C2_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429C836CUL))) +#define bM4_I2C2_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429C8370UL))) +#define bM4_I2C2_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429C8374UL))) +#define bM4_I2C2_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429C8378UL))) +#define bM4_I2C2_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429C837CUL))) +#define bM4_I2C2_SR_STARTF (*((volatile unsigned int*)(0x429C8380UL))) +#define bM4_I2C2_SR_SLADDR0F (*((volatile unsigned int*)(0x429C8384UL))) +#define bM4_I2C2_SR_SLADDR1F (*((volatile unsigned int*)(0x429C8388UL))) +#define bM4_I2C2_SR_TENDF (*((volatile unsigned int*)(0x429C838CUL))) +#define bM4_I2C2_SR_STOPF (*((volatile unsigned int*)(0x429C8390UL))) +#define bM4_I2C2_SR_RFULLF (*((volatile unsigned int*)(0x429C8398UL))) +#define bM4_I2C2_SR_TEMPTYF (*((volatile unsigned int*)(0x429C839CUL))) +#define bM4_I2C2_SR_ARLOF (*((volatile unsigned int*)(0x429C83A4UL))) +#define bM4_I2C2_SR_ACKRF (*((volatile unsigned int*)(0x429C83A8UL))) +#define bM4_I2C2_SR_NACKF (*((volatile unsigned int*)(0x429C83B0UL))) +#define bM4_I2C2_SR_TMOUTF (*((volatile unsigned int*)(0x429C83B8UL))) +#define bM4_I2C2_SR_MSL (*((volatile unsigned int*)(0x429C83C0UL))) +#define bM4_I2C2_SR_BUSY (*((volatile unsigned int*)(0x429C83C4UL))) +#define bM4_I2C2_SR_TRA (*((volatile unsigned int*)(0x429C83C8UL))) +#define bM4_I2C2_SR_GENCALLF (*((volatile unsigned int*)(0x429C83D0UL))) +#define bM4_I2C2_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429C83D4UL))) +#define bM4_I2C2_SR_SMBHOSTF (*((volatile unsigned int*)(0x429C83D8UL))) +#define bM4_I2C2_SR_SMBALRTF (*((volatile unsigned int*)(0x429C83DCUL))) +#define bM4_I2C2_CLR_STARTFCLR (*((volatile unsigned int*)(0x429C8400UL))) +#define bM4_I2C2_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429C8404UL))) +#define bM4_I2C2_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429C8408UL))) +#define bM4_I2C2_CLR_TENDFCLR (*((volatile unsigned int*)(0x429C840CUL))) +#define bM4_I2C2_CLR_STOPFCLR (*((volatile unsigned int*)(0x429C8410UL))) +#define bM4_I2C2_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429C8418UL))) +#define bM4_I2C2_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429C841CUL))) +#define bM4_I2C2_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429C8424UL))) +#define bM4_I2C2_CLR_NACKFCLR (*((volatile unsigned int*)(0x429C8430UL))) +#define bM4_I2C2_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429C8438UL))) +#define bM4_I2C2_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429C8450UL))) +#define bM4_I2C2_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429C8454UL))) +#define bM4_I2C2_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429C8458UL))) +#define bM4_I2C2_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429C845CUL))) +#define bM4_I2C2_DTR_DT0 (*((volatile unsigned int*)(0x429C8480UL))) +#define bM4_I2C2_DTR_DT1 (*((volatile unsigned int*)(0x429C8484UL))) +#define bM4_I2C2_DTR_DT2 (*((volatile unsigned int*)(0x429C8488UL))) +#define bM4_I2C2_DTR_DT3 (*((volatile unsigned int*)(0x429C848CUL))) +#define bM4_I2C2_DTR_DT4 (*((volatile unsigned int*)(0x429C8490UL))) +#define bM4_I2C2_DTR_DT5 (*((volatile unsigned int*)(0x429C8494UL))) +#define bM4_I2C2_DTR_DT6 (*((volatile unsigned int*)(0x429C8498UL))) +#define bM4_I2C2_DTR_DT7 (*((volatile unsigned int*)(0x429C849CUL))) +#define bM4_I2C2_DRR_DR0 (*((volatile unsigned int*)(0x429C8500UL))) +#define bM4_I2C2_DRR_DR1 (*((volatile unsigned int*)(0x429C8504UL))) +#define bM4_I2C2_DRR_DR2 (*((volatile unsigned int*)(0x429C8508UL))) +#define bM4_I2C2_DRR_DR3 (*((volatile unsigned int*)(0x429C850CUL))) +#define bM4_I2C2_DRR_DR4 (*((volatile unsigned int*)(0x429C8510UL))) +#define bM4_I2C2_DRR_DR5 (*((volatile unsigned int*)(0x429C8514UL))) +#define bM4_I2C2_DRR_DR6 (*((volatile unsigned int*)(0x429C8518UL))) +#define bM4_I2C2_DRR_DR7 (*((volatile unsigned int*)(0x429C851CUL))) +#define bM4_I2C2_CCR_SLOWW0 (*((volatile unsigned int*)(0x429C8580UL))) +#define bM4_I2C2_CCR_SLOWW1 (*((volatile unsigned int*)(0x429C8584UL))) +#define bM4_I2C2_CCR_SLOWW2 (*((volatile unsigned int*)(0x429C8588UL))) +#define bM4_I2C2_CCR_SLOWW3 (*((volatile unsigned int*)(0x429C858CUL))) +#define bM4_I2C2_CCR_SLOWW4 (*((volatile unsigned int*)(0x429C8590UL))) +#define bM4_I2C2_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429C85A0UL))) +#define bM4_I2C2_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429C85A4UL))) +#define bM4_I2C2_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429C85A8UL))) +#define bM4_I2C2_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429C85ACUL))) +#define bM4_I2C2_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429C85B0UL))) +#define bM4_I2C2_CCR_FREQ0 (*((volatile unsigned int*)(0x429C85C0UL))) +#define bM4_I2C2_CCR_FREQ1 (*((volatile unsigned int*)(0x429C85C4UL))) +#define bM4_I2C2_CCR_FREQ2 (*((volatile unsigned int*)(0x429C85C8UL))) +#define bM4_I2C2_FLTR_DNF0 (*((volatile unsigned int*)(0x429C8600UL))) +#define bM4_I2C2_FLTR_DNF1 (*((volatile unsigned int*)(0x429C8604UL))) +#define bM4_I2C2_FLTR_DNFEN (*((volatile unsigned int*)(0x429C8610UL))) +#define bM4_I2C2_FLTR_ANFEN (*((volatile unsigned int*)(0x429C8614UL))) +#define bM4_I2C3_CR1_PE (*((volatile unsigned int*)(0x429D0000UL))) +#define bM4_I2C3_CR1_SMBUS (*((volatile unsigned int*)(0x429D0004UL))) +#define bM4_I2C3_CR1_SMBALRTEN (*((volatile unsigned int*)(0x429D0008UL))) +#define bM4_I2C3_CR1_SMBDEFAULTEN (*((volatile unsigned int*)(0x429D000CUL))) +#define bM4_I2C3_CR1_SMBHOSTEN (*((volatile unsigned int*)(0x429D0010UL))) +#define bM4_I2C3_CR1_ENGC (*((volatile unsigned int*)(0x429D0018UL))) +#define bM4_I2C3_CR1_RESTART (*((volatile unsigned int*)(0x429D001CUL))) +#define bM4_I2C3_CR1_START (*((volatile unsigned int*)(0x429D0020UL))) +#define bM4_I2C3_CR1_STOP (*((volatile unsigned int*)(0x429D0024UL))) +#define bM4_I2C3_CR1_ACK (*((volatile unsigned int*)(0x429D0028UL))) +#define bM4_I2C3_CR1_SWRST (*((volatile unsigned int*)(0x429D003CUL))) +#define bM4_I2C3_CR2_STARTIE (*((volatile unsigned int*)(0x429D0080UL))) +#define bM4_I2C3_CR2_SLADDR0IE (*((volatile unsigned int*)(0x429D0084UL))) +#define bM4_I2C3_CR2_SLADDR1IE (*((volatile unsigned int*)(0x429D0088UL))) +#define bM4_I2C3_CR2_TENDIE (*((volatile unsigned int*)(0x429D008CUL))) +#define bM4_I2C3_CR2_STOPIE (*((volatile unsigned int*)(0x429D0090UL))) +#define bM4_I2C3_CR2_RFULLIE (*((volatile unsigned int*)(0x429D0098UL))) +#define bM4_I2C3_CR2_TEMPTYIE (*((volatile unsigned int*)(0x429D009CUL))) +#define bM4_I2C3_CR2_ARLOIE (*((volatile unsigned int*)(0x429D00A4UL))) +#define bM4_I2C3_CR2_NACKIE (*((volatile unsigned int*)(0x429D00B0UL))) +#define bM4_I2C3_CR2_TMOUTIE (*((volatile unsigned int*)(0x429D00B8UL))) +#define bM4_I2C3_CR2_GENCALLIE (*((volatile unsigned int*)(0x429D00D0UL))) +#define bM4_I2C3_CR2_SMBDEFAULTIE (*((volatile unsigned int*)(0x429D00D4UL))) +#define bM4_I2C3_CR2_SMBHOSTIE (*((volatile unsigned int*)(0x429D00D8UL))) +#define bM4_I2C3_CR2_SMBALRTIE (*((volatile unsigned int*)(0x429D00DCUL))) +#define bM4_I2C3_CR3_TMOUTEN (*((volatile unsigned int*)(0x429D0100UL))) +#define bM4_I2C3_CR3_LTMOUT (*((volatile unsigned int*)(0x429D0104UL))) +#define bM4_I2C3_CR3_HTMOUT (*((volatile unsigned int*)(0x429D0108UL))) +#define bM4_I2C3_CR3_FACKEN (*((volatile unsigned int*)(0x429D011CUL))) +#define bM4_I2C3_SLR0_SLADDR00 (*((volatile unsigned int*)(0x429D0200UL))) +#define bM4_I2C3_SLR0_SLADDR01 (*((volatile unsigned int*)(0x429D0204UL))) +#define bM4_I2C3_SLR0_SLADDR02 (*((volatile unsigned int*)(0x429D0208UL))) +#define bM4_I2C3_SLR0_SLADDR03 (*((volatile unsigned int*)(0x429D020CUL))) +#define bM4_I2C3_SLR0_SLADDR04 (*((volatile unsigned int*)(0x429D0210UL))) +#define bM4_I2C3_SLR0_SLADDR05 (*((volatile unsigned int*)(0x429D0214UL))) +#define bM4_I2C3_SLR0_SLADDR06 (*((volatile unsigned int*)(0x429D0218UL))) +#define bM4_I2C3_SLR0_SLADDR07 (*((volatile unsigned int*)(0x429D021CUL))) +#define bM4_I2C3_SLR0_SLADDR08 (*((volatile unsigned int*)(0x429D0220UL))) +#define bM4_I2C3_SLR0_SLADDR09 (*((volatile unsigned int*)(0x429D0224UL))) +#define bM4_I2C3_SLR0_SLADDR0EN (*((volatile unsigned int*)(0x429D0230UL))) +#define bM4_I2C3_SLR0_ADDRMOD0 (*((volatile unsigned int*)(0x429D023CUL))) +#define bM4_I2C3_SLR1_SLADDR10 (*((volatile unsigned int*)(0x429D0280UL))) +#define bM4_I2C3_SLR1_SLADDR11 (*((volatile unsigned int*)(0x429D0284UL))) +#define bM4_I2C3_SLR1_SLADDR12 (*((volatile unsigned int*)(0x429D0288UL))) +#define bM4_I2C3_SLR1_SLADDR13 (*((volatile unsigned int*)(0x429D028CUL))) +#define bM4_I2C3_SLR1_SLADDR14 (*((volatile unsigned int*)(0x429D0290UL))) +#define bM4_I2C3_SLR1_SLADDR15 (*((volatile unsigned int*)(0x429D0294UL))) +#define bM4_I2C3_SLR1_SLADDR16 (*((volatile unsigned int*)(0x429D0298UL))) +#define bM4_I2C3_SLR1_SLADDR17 (*((volatile unsigned int*)(0x429D029CUL))) +#define bM4_I2C3_SLR1_SLADDR18 (*((volatile unsigned int*)(0x429D02A0UL))) +#define bM4_I2C3_SLR1_SLADDR19 (*((volatile unsigned int*)(0x429D02A4UL))) +#define bM4_I2C3_SLR1_SLADDR1EN (*((volatile unsigned int*)(0x429D02B0UL))) +#define bM4_I2C3_SLR1_ADDRMOD1 (*((volatile unsigned int*)(0x429D02BCUL))) +#define bM4_I2C3_SLTR_TOUTLOW0 (*((volatile unsigned int*)(0x429D0300UL))) +#define bM4_I2C3_SLTR_TOUTLOW1 (*((volatile unsigned int*)(0x429D0304UL))) +#define bM4_I2C3_SLTR_TOUTLOW2 (*((volatile unsigned int*)(0x429D0308UL))) +#define bM4_I2C3_SLTR_TOUTLOW3 (*((volatile unsigned int*)(0x429D030CUL))) +#define bM4_I2C3_SLTR_TOUTLOW4 (*((volatile unsigned int*)(0x429D0310UL))) +#define bM4_I2C3_SLTR_TOUTLOW5 (*((volatile unsigned int*)(0x429D0314UL))) +#define bM4_I2C3_SLTR_TOUTLOW6 (*((volatile unsigned int*)(0x429D0318UL))) +#define bM4_I2C3_SLTR_TOUTLOW7 (*((volatile unsigned int*)(0x429D031CUL))) +#define bM4_I2C3_SLTR_TOUTLOW8 (*((volatile unsigned int*)(0x429D0320UL))) +#define bM4_I2C3_SLTR_TOUTLOW9 (*((volatile unsigned int*)(0x429D0324UL))) +#define bM4_I2C3_SLTR_TOUTLOW10 (*((volatile unsigned int*)(0x429D0328UL))) +#define bM4_I2C3_SLTR_TOUTLOW11 (*((volatile unsigned int*)(0x429D032CUL))) +#define bM4_I2C3_SLTR_TOUTLOW12 (*((volatile unsigned int*)(0x429D0330UL))) +#define bM4_I2C3_SLTR_TOUTLOW13 (*((volatile unsigned int*)(0x429D0334UL))) +#define bM4_I2C3_SLTR_TOUTLOW14 (*((volatile unsigned int*)(0x429D0338UL))) +#define bM4_I2C3_SLTR_TOUTLOW15 (*((volatile unsigned int*)(0x429D033CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH0 (*((volatile unsigned int*)(0x429D0340UL))) +#define bM4_I2C3_SLTR_TOUTHIGH1 (*((volatile unsigned int*)(0x429D0344UL))) +#define bM4_I2C3_SLTR_TOUTHIGH2 (*((volatile unsigned int*)(0x429D0348UL))) +#define bM4_I2C3_SLTR_TOUTHIGH3 (*((volatile unsigned int*)(0x429D034CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH4 (*((volatile unsigned int*)(0x429D0350UL))) +#define bM4_I2C3_SLTR_TOUTHIGH5 (*((volatile unsigned int*)(0x429D0354UL))) +#define bM4_I2C3_SLTR_TOUTHIGH6 (*((volatile unsigned int*)(0x429D0358UL))) +#define bM4_I2C3_SLTR_TOUTHIGH7 (*((volatile unsigned int*)(0x429D035CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH8 (*((volatile unsigned int*)(0x429D0360UL))) +#define bM4_I2C3_SLTR_TOUTHIGH9 (*((volatile unsigned int*)(0x429D0364UL))) +#define bM4_I2C3_SLTR_TOUTHIGH10 (*((volatile unsigned int*)(0x429D0368UL))) +#define bM4_I2C3_SLTR_TOUTHIGH11 (*((volatile unsigned int*)(0x429D036CUL))) +#define bM4_I2C3_SLTR_TOUTHIGH12 (*((volatile unsigned int*)(0x429D0370UL))) +#define bM4_I2C3_SLTR_TOUTHIGH13 (*((volatile unsigned int*)(0x429D0374UL))) +#define bM4_I2C3_SLTR_TOUTHIGH14 (*((volatile unsigned int*)(0x429D0378UL))) +#define bM4_I2C3_SLTR_TOUTHIGH15 (*((volatile unsigned int*)(0x429D037CUL))) +#define bM4_I2C3_SR_STARTF (*((volatile unsigned int*)(0x429D0380UL))) +#define bM4_I2C3_SR_SLADDR0F (*((volatile unsigned int*)(0x429D0384UL))) +#define bM4_I2C3_SR_SLADDR1F (*((volatile unsigned int*)(0x429D0388UL))) +#define bM4_I2C3_SR_TENDF (*((volatile unsigned int*)(0x429D038CUL))) +#define bM4_I2C3_SR_STOPF (*((volatile unsigned int*)(0x429D0390UL))) +#define bM4_I2C3_SR_RFULLF (*((volatile unsigned int*)(0x429D0398UL))) +#define bM4_I2C3_SR_TEMPTYF (*((volatile unsigned int*)(0x429D039CUL))) +#define bM4_I2C3_SR_ARLOF (*((volatile unsigned int*)(0x429D03A4UL))) +#define bM4_I2C3_SR_ACKRF (*((volatile unsigned int*)(0x429D03A8UL))) +#define bM4_I2C3_SR_NACKF (*((volatile unsigned int*)(0x429D03B0UL))) +#define bM4_I2C3_SR_TMOUTF (*((volatile unsigned int*)(0x429D03B8UL))) +#define bM4_I2C3_SR_MSL (*((volatile unsigned int*)(0x429D03C0UL))) +#define bM4_I2C3_SR_BUSY (*((volatile unsigned int*)(0x429D03C4UL))) +#define bM4_I2C3_SR_TRA (*((volatile unsigned int*)(0x429D03C8UL))) +#define bM4_I2C3_SR_GENCALLF (*((volatile unsigned int*)(0x429D03D0UL))) +#define bM4_I2C3_SR_SMBDEFAULTF (*((volatile unsigned int*)(0x429D03D4UL))) +#define bM4_I2C3_SR_SMBHOSTF (*((volatile unsigned int*)(0x429D03D8UL))) +#define bM4_I2C3_SR_SMBALRTF (*((volatile unsigned int*)(0x429D03DCUL))) +#define bM4_I2C3_CLR_STARTFCLR (*((volatile unsigned int*)(0x429D0400UL))) +#define bM4_I2C3_CLR_SLADDR0FCLR (*((volatile unsigned int*)(0x429D0404UL))) +#define bM4_I2C3_CLR_SLADDR1FCLR (*((volatile unsigned int*)(0x429D0408UL))) +#define bM4_I2C3_CLR_TENDFCLR (*((volatile unsigned int*)(0x429D040CUL))) +#define bM4_I2C3_CLR_STOPFCLR (*((volatile unsigned int*)(0x429D0410UL))) +#define bM4_I2C3_CLR_RFULLFCLR (*((volatile unsigned int*)(0x429D0418UL))) +#define bM4_I2C3_CLR_TEMPTYFCLR (*((volatile unsigned int*)(0x429D041CUL))) +#define bM4_I2C3_CLR_ARLOFCLR (*((volatile unsigned int*)(0x429D0424UL))) +#define bM4_I2C3_CLR_NACKFCLR (*((volatile unsigned int*)(0x429D0430UL))) +#define bM4_I2C3_CLR_TMOUTFCLR (*((volatile unsigned int*)(0x429D0438UL))) +#define bM4_I2C3_CLR_GENCALLFCLR (*((volatile unsigned int*)(0x429D0450UL))) +#define bM4_I2C3_CLR_SMBDEFAULTFCLR (*((volatile unsigned int*)(0x429D0454UL))) +#define bM4_I2C3_CLR_SMBHOSTFCLR (*((volatile unsigned int*)(0x429D0458UL))) +#define bM4_I2C3_CLR_SMBALRTFCLR (*((volatile unsigned int*)(0x429D045CUL))) +#define bM4_I2C3_DTR_DT0 (*((volatile unsigned int*)(0x429D0480UL))) +#define bM4_I2C3_DTR_DT1 (*((volatile unsigned int*)(0x429D0484UL))) +#define bM4_I2C3_DTR_DT2 (*((volatile unsigned int*)(0x429D0488UL))) +#define bM4_I2C3_DTR_DT3 (*((volatile unsigned int*)(0x429D048CUL))) +#define bM4_I2C3_DTR_DT4 (*((volatile unsigned int*)(0x429D0490UL))) +#define bM4_I2C3_DTR_DT5 (*((volatile unsigned int*)(0x429D0494UL))) +#define bM4_I2C3_DTR_DT6 (*((volatile unsigned int*)(0x429D0498UL))) +#define bM4_I2C3_DTR_DT7 (*((volatile unsigned int*)(0x429D049CUL))) +#define bM4_I2C3_DRR_DR0 (*((volatile unsigned int*)(0x429D0500UL))) +#define bM4_I2C3_DRR_DR1 (*((volatile unsigned int*)(0x429D0504UL))) +#define bM4_I2C3_DRR_DR2 (*((volatile unsigned int*)(0x429D0508UL))) +#define bM4_I2C3_DRR_DR3 (*((volatile unsigned int*)(0x429D050CUL))) +#define bM4_I2C3_DRR_DR4 (*((volatile unsigned int*)(0x429D0510UL))) +#define bM4_I2C3_DRR_DR5 (*((volatile unsigned int*)(0x429D0514UL))) +#define bM4_I2C3_DRR_DR6 (*((volatile unsigned int*)(0x429D0518UL))) +#define bM4_I2C3_DRR_DR7 (*((volatile unsigned int*)(0x429D051CUL))) +#define bM4_I2C3_CCR_SLOWW0 (*((volatile unsigned int*)(0x429D0580UL))) +#define bM4_I2C3_CCR_SLOWW1 (*((volatile unsigned int*)(0x429D0584UL))) +#define bM4_I2C3_CCR_SLOWW2 (*((volatile unsigned int*)(0x429D0588UL))) +#define bM4_I2C3_CCR_SLOWW3 (*((volatile unsigned int*)(0x429D058CUL))) +#define bM4_I2C3_CCR_SLOWW4 (*((volatile unsigned int*)(0x429D0590UL))) +#define bM4_I2C3_CCR_SHIGHW0 (*((volatile unsigned int*)(0x429D05A0UL))) +#define bM4_I2C3_CCR_SHIGHW1 (*((volatile unsigned int*)(0x429D05A4UL))) +#define bM4_I2C3_CCR_SHIGHW2 (*((volatile unsigned int*)(0x429D05A8UL))) +#define bM4_I2C3_CCR_SHIGHW3 (*((volatile unsigned int*)(0x429D05ACUL))) +#define bM4_I2C3_CCR_SHIGHW4 (*((volatile unsigned int*)(0x429D05B0UL))) +#define bM4_I2C3_CCR_FREQ0 (*((volatile unsigned int*)(0x429D05C0UL))) +#define bM4_I2C3_CCR_FREQ1 (*((volatile unsigned int*)(0x429D05C4UL))) +#define bM4_I2C3_CCR_FREQ2 (*((volatile unsigned int*)(0x429D05C8UL))) +#define bM4_I2C3_FLTR_DNF0 (*((volatile unsigned int*)(0x429D0600UL))) +#define bM4_I2C3_FLTR_DNF1 (*((volatile unsigned int*)(0x429D0604UL))) +#define bM4_I2C3_FLTR_DNFEN (*((volatile unsigned int*)(0x429D0610UL))) +#define bM4_I2C3_FLTR_ANFEN (*((volatile unsigned int*)(0x429D0614UL))) +#define bM4_I2S1_CTRL_TXE (*((volatile unsigned int*)(0x423C0000UL))) +#define bM4_I2S1_CTRL_TXIE (*((volatile unsigned int*)(0x423C0004UL))) +#define bM4_I2S1_CTRL_RXE (*((volatile unsigned int*)(0x423C0008UL))) +#define bM4_I2S1_CTRL_RXIE (*((volatile unsigned int*)(0x423C000CUL))) +#define bM4_I2S1_CTRL_EIE (*((volatile unsigned int*)(0x423C0010UL))) +#define bM4_I2S1_CTRL_WMS (*((volatile unsigned int*)(0x423C0014UL))) +#define bM4_I2S1_CTRL_ODD (*((volatile unsigned int*)(0x423C0018UL))) +#define bM4_I2S1_CTRL_MCKOE (*((volatile unsigned int*)(0x423C001CUL))) +#define bM4_I2S1_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x423C0020UL))) +#define bM4_I2S1_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x423C0024UL))) +#define bM4_I2S1_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x423C0028UL))) +#define bM4_I2S1_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x423C0030UL))) +#define bM4_I2S1_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x423C0034UL))) +#define bM4_I2S1_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x423C0038UL))) +#define bM4_I2S1_CTRL_FIFOR (*((volatile unsigned int*)(0x423C0040UL))) +#define bM4_I2S1_CTRL_CODECRC (*((volatile unsigned int*)(0x423C0044UL))) +#define bM4_I2S1_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x423C0048UL))) +#define bM4_I2S1_CTRL_SDOE (*((volatile unsigned int*)(0x423C004CUL))) +#define bM4_I2S1_CTRL_LRCKOE (*((volatile unsigned int*)(0x423C0050UL))) +#define bM4_I2S1_CTRL_CKOE (*((volatile unsigned int*)(0x423C0054UL))) +#define bM4_I2S1_CTRL_DUPLEX (*((volatile unsigned int*)(0x423C0058UL))) +#define bM4_I2S1_CTRL_CLKSEL (*((volatile unsigned int*)(0x423C005CUL))) +#define bM4_I2S1_SR_TXBA (*((volatile unsigned int*)(0x423C0080UL))) +#define bM4_I2S1_SR_RXBA (*((volatile unsigned int*)(0x423C0084UL))) +#define bM4_I2S1_SR_TXBE (*((volatile unsigned int*)(0x423C0088UL))) +#define bM4_I2S1_SR_TXBF (*((volatile unsigned int*)(0x423C008CUL))) +#define bM4_I2S1_SR_RXBE (*((volatile unsigned int*)(0x423C0090UL))) +#define bM4_I2S1_SR_RXBF (*((volatile unsigned int*)(0x423C0094UL))) +#define bM4_I2S1_ER_TXERR (*((volatile unsigned int*)(0x423C0100UL))) +#define bM4_I2S1_ER_RXERR (*((volatile unsigned int*)(0x423C0104UL))) +#define bM4_I2S1_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x423C0180UL))) +#define bM4_I2S1_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x423C0184UL))) +#define bM4_I2S1_CFGR_DATLEN0 (*((volatile unsigned int*)(0x423C0188UL))) +#define bM4_I2S1_CFGR_DATLEN1 (*((volatile unsigned int*)(0x423C018CUL))) +#define bM4_I2S1_CFGR_CHLEN (*((volatile unsigned int*)(0x423C0190UL))) +#define bM4_I2S1_CFGR_PCMSYNC (*((volatile unsigned int*)(0x423C0194UL))) +#define bM4_I2S1_PR_I2SDIV0 (*((volatile unsigned int*)(0x423C0300UL))) +#define bM4_I2S1_PR_I2SDIV1 (*((volatile unsigned int*)(0x423C0304UL))) +#define bM4_I2S1_PR_I2SDIV2 (*((volatile unsigned int*)(0x423C0308UL))) +#define bM4_I2S1_PR_I2SDIV3 (*((volatile unsigned int*)(0x423C030CUL))) +#define bM4_I2S1_PR_I2SDIV4 (*((volatile unsigned int*)(0x423C0310UL))) +#define bM4_I2S1_PR_I2SDIV5 (*((volatile unsigned int*)(0x423C0314UL))) +#define bM4_I2S1_PR_I2SDIV6 (*((volatile unsigned int*)(0x423C0318UL))) +#define bM4_I2S1_PR_I2SDIV7 (*((volatile unsigned int*)(0x423C031CUL))) +#define bM4_I2S2_CTRL_TXE (*((volatile unsigned int*)(0x423C8000UL))) +#define bM4_I2S2_CTRL_TXIE (*((volatile unsigned int*)(0x423C8004UL))) +#define bM4_I2S2_CTRL_RXE (*((volatile unsigned int*)(0x423C8008UL))) +#define bM4_I2S2_CTRL_RXIE (*((volatile unsigned int*)(0x423C800CUL))) +#define bM4_I2S2_CTRL_EIE (*((volatile unsigned int*)(0x423C8010UL))) +#define bM4_I2S2_CTRL_WMS (*((volatile unsigned int*)(0x423C8014UL))) +#define bM4_I2S2_CTRL_ODD (*((volatile unsigned int*)(0x423C8018UL))) +#define bM4_I2S2_CTRL_MCKOE (*((volatile unsigned int*)(0x423C801CUL))) +#define bM4_I2S2_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x423C8020UL))) +#define bM4_I2S2_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x423C8024UL))) +#define bM4_I2S2_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x423C8028UL))) +#define bM4_I2S2_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x423C8030UL))) +#define bM4_I2S2_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x423C8034UL))) +#define bM4_I2S2_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x423C8038UL))) +#define bM4_I2S2_CTRL_FIFOR (*((volatile unsigned int*)(0x423C8040UL))) +#define bM4_I2S2_CTRL_CODECRC (*((volatile unsigned int*)(0x423C8044UL))) +#define bM4_I2S2_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x423C8048UL))) +#define bM4_I2S2_CTRL_SDOE (*((volatile unsigned int*)(0x423C804CUL))) +#define bM4_I2S2_CTRL_LRCKOE (*((volatile unsigned int*)(0x423C8050UL))) +#define bM4_I2S2_CTRL_CKOE (*((volatile unsigned int*)(0x423C8054UL))) +#define bM4_I2S2_CTRL_DUPLEX (*((volatile unsigned int*)(0x423C8058UL))) +#define bM4_I2S2_CTRL_CLKSEL (*((volatile unsigned int*)(0x423C805CUL))) +#define bM4_I2S2_SR_TXBA (*((volatile unsigned int*)(0x423C8080UL))) +#define bM4_I2S2_SR_RXBA (*((volatile unsigned int*)(0x423C8084UL))) +#define bM4_I2S2_SR_TXBE (*((volatile unsigned int*)(0x423C8088UL))) +#define bM4_I2S2_SR_TXBF (*((volatile unsigned int*)(0x423C808CUL))) +#define bM4_I2S2_SR_RXBE (*((volatile unsigned int*)(0x423C8090UL))) +#define bM4_I2S2_SR_RXBF (*((volatile unsigned int*)(0x423C8094UL))) +#define bM4_I2S2_ER_TXERR (*((volatile unsigned int*)(0x423C8100UL))) +#define bM4_I2S2_ER_RXERR (*((volatile unsigned int*)(0x423C8104UL))) +#define bM4_I2S2_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x423C8180UL))) +#define bM4_I2S2_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x423C8184UL))) +#define bM4_I2S2_CFGR_DATLEN0 (*((volatile unsigned int*)(0x423C8188UL))) +#define bM4_I2S2_CFGR_DATLEN1 (*((volatile unsigned int*)(0x423C818CUL))) +#define bM4_I2S2_CFGR_CHLEN (*((volatile unsigned int*)(0x423C8190UL))) +#define bM4_I2S2_CFGR_PCMSYNC (*((volatile unsigned int*)(0x423C8194UL))) +#define bM4_I2S2_PR_I2SDIV0 (*((volatile unsigned int*)(0x423C8300UL))) +#define bM4_I2S2_PR_I2SDIV1 (*((volatile unsigned int*)(0x423C8304UL))) +#define bM4_I2S2_PR_I2SDIV2 (*((volatile unsigned int*)(0x423C8308UL))) +#define bM4_I2S2_PR_I2SDIV3 (*((volatile unsigned int*)(0x423C830CUL))) +#define bM4_I2S2_PR_I2SDIV4 (*((volatile unsigned int*)(0x423C8310UL))) +#define bM4_I2S2_PR_I2SDIV5 (*((volatile unsigned int*)(0x423C8314UL))) +#define bM4_I2S2_PR_I2SDIV6 (*((volatile unsigned int*)(0x423C8318UL))) +#define bM4_I2S2_PR_I2SDIV7 (*((volatile unsigned int*)(0x423C831CUL))) +#define bM4_I2S3_CTRL_TXE (*((volatile unsigned int*)(0x42440000UL))) +#define bM4_I2S3_CTRL_TXIE (*((volatile unsigned int*)(0x42440004UL))) +#define bM4_I2S3_CTRL_RXE (*((volatile unsigned int*)(0x42440008UL))) +#define bM4_I2S3_CTRL_RXIE (*((volatile unsigned int*)(0x4244000CUL))) +#define bM4_I2S3_CTRL_EIE (*((volatile unsigned int*)(0x42440010UL))) +#define bM4_I2S3_CTRL_WMS (*((volatile unsigned int*)(0x42440014UL))) +#define bM4_I2S3_CTRL_ODD (*((volatile unsigned int*)(0x42440018UL))) +#define bM4_I2S3_CTRL_MCKOE (*((volatile unsigned int*)(0x4244001CUL))) +#define bM4_I2S3_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x42440020UL))) +#define bM4_I2S3_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x42440024UL))) +#define bM4_I2S3_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x42440028UL))) +#define bM4_I2S3_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x42440030UL))) +#define bM4_I2S3_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x42440034UL))) +#define bM4_I2S3_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x42440038UL))) +#define bM4_I2S3_CTRL_FIFOR (*((volatile unsigned int*)(0x42440040UL))) +#define bM4_I2S3_CTRL_CODECRC (*((volatile unsigned int*)(0x42440044UL))) +#define bM4_I2S3_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x42440048UL))) +#define bM4_I2S3_CTRL_SDOE (*((volatile unsigned int*)(0x4244004CUL))) +#define bM4_I2S3_CTRL_LRCKOE (*((volatile unsigned int*)(0x42440050UL))) +#define bM4_I2S3_CTRL_CKOE (*((volatile unsigned int*)(0x42440054UL))) +#define bM4_I2S3_CTRL_DUPLEX (*((volatile unsigned int*)(0x42440058UL))) +#define bM4_I2S3_CTRL_CLKSEL (*((volatile unsigned int*)(0x4244005CUL))) +#define bM4_I2S3_SR_TXBA (*((volatile unsigned int*)(0x42440080UL))) +#define bM4_I2S3_SR_RXBA (*((volatile unsigned int*)(0x42440084UL))) +#define bM4_I2S3_SR_TXBE (*((volatile unsigned int*)(0x42440088UL))) +#define bM4_I2S3_SR_TXBF (*((volatile unsigned int*)(0x4244008CUL))) +#define bM4_I2S3_SR_RXBE (*((volatile unsigned int*)(0x42440090UL))) +#define bM4_I2S3_SR_RXBF (*((volatile unsigned int*)(0x42440094UL))) +#define bM4_I2S3_ER_TXERR (*((volatile unsigned int*)(0x42440100UL))) +#define bM4_I2S3_ER_RXERR (*((volatile unsigned int*)(0x42440104UL))) +#define bM4_I2S3_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x42440180UL))) +#define bM4_I2S3_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x42440184UL))) +#define bM4_I2S3_CFGR_DATLEN0 (*((volatile unsigned int*)(0x42440188UL))) +#define bM4_I2S3_CFGR_DATLEN1 (*((volatile unsigned int*)(0x4244018CUL))) +#define bM4_I2S3_CFGR_CHLEN (*((volatile unsigned int*)(0x42440190UL))) +#define bM4_I2S3_CFGR_PCMSYNC (*((volatile unsigned int*)(0x42440194UL))) +#define bM4_I2S3_PR_I2SDIV0 (*((volatile unsigned int*)(0x42440300UL))) +#define bM4_I2S3_PR_I2SDIV1 (*((volatile unsigned int*)(0x42440304UL))) +#define bM4_I2S3_PR_I2SDIV2 (*((volatile unsigned int*)(0x42440308UL))) +#define bM4_I2S3_PR_I2SDIV3 (*((volatile unsigned int*)(0x4244030CUL))) +#define bM4_I2S3_PR_I2SDIV4 (*((volatile unsigned int*)(0x42440310UL))) +#define bM4_I2S3_PR_I2SDIV5 (*((volatile unsigned int*)(0x42440314UL))) +#define bM4_I2S3_PR_I2SDIV6 (*((volatile unsigned int*)(0x42440318UL))) +#define bM4_I2S3_PR_I2SDIV7 (*((volatile unsigned int*)(0x4244031CUL))) +#define bM4_I2S4_CTRL_TXE (*((volatile unsigned int*)(0x42448000UL))) +#define bM4_I2S4_CTRL_TXIE (*((volatile unsigned int*)(0x42448004UL))) +#define bM4_I2S4_CTRL_RXE (*((volatile unsigned int*)(0x42448008UL))) +#define bM4_I2S4_CTRL_RXIE (*((volatile unsigned int*)(0x4244800CUL))) +#define bM4_I2S4_CTRL_EIE (*((volatile unsigned int*)(0x42448010UL))) +#define bM4_I2S4_CTRL_WMS (*((volatile unsigned int*)(0x42448014UL))) +#define bM4_I2S4_CTRL_ODD (*((volatile unsigned int*)(0x42448018UL))) +#define bM4_I2S4_CTRL_MCKOE (*((volatile unsigned int*)(0x4244801CUL))) +#define bM4_I2S4_CTRL_TXBIRQWL0 (*((volatile unsigned int*)(0x42448020UL))) +#define bM4_I2S4_CTRL_TXBIRQWL1 (*((volatile unsigned int*)(0x42448024UL))) +#define bM4_I2S4_CTRL_TXBIRQWL2 (*((volatile unsigned int*)(0x42448028UL))) +#define bM4_I2S4_CTRL_RXBIRQWL0 (*((volatile unsigned int*)(0x42448030UL))) +#define bM4_I2S4_CTRL_RXBIRQWL1 (*((volatile unsigned int*)(0x42448034UL))) +#define bM4_I2S4_CTRL_RXBIRQWL2 (*((volatile unsigned int*)(0x42448038UL))) +#define bM4_I2S4_CTRL_FIFOR (*((volatile unsigned int*)(0x42448040UL))) +#define bM4_I2S4_CTRL_CODECRC (*((volatile unsigned int*)(0x42448044UL))) +#define bM4_I2S4_CTRL_I2SPLLSEL (*((volatile unsigned int*)(0x42448048UL))) +#define bM4_I2S4_CTRL_SDOE (*((volatile unsigned int*)(0x4244804CUL))) +#define bM4_I2S4_CTRL_LRCKOE (*((volatile unsigned int*)(0x42448050UL))) +#define bM4_I2S4_CTRL_CKOE (*((volatile unsigned int*)(0x42448054UL))) +#define bM4_I2S4_CTRL_DUPLEX (*((volatile unsigned int*)(0x42448058UL))) +#define bM4_I2S4_CTRL_CLKSEL (*((volatile unsigned int*)(0x4244805CUL))) +#define bM4_I2S4_SR_TXBA (*((volatile unsigned int*)(0x42448080UL))) +#define bM4_I2S4_SR_RXBA (*((volatile unsigned int*)(0x42448084UL))) +#define bM4_I2S4_SR_TXBE (*((volatile unsigned int*)(0x42448088UL))) +#define bM4_I2S4_SR_TXBF (*((volatile unsigned int*)(0x4244808CUL))) +#define bM4_I2S4_SR_RXBE (*((volatile unsigned int*)(0x42448090UL))) +#define bM4_I2S4_SR_RXBF (*((volatile unsigned int*)(0x42448094UL))) +#define bM4_I2S4_ER_TXERR (*((volatile unsigned int*)(0x42448100UL))) +#define bM4_I2S4_ER_RXERR (*((volatile unsigned int*)(0x42448104UL))) +#define bM4_I2S4_CFGR_I2SSTD0 (*((volatile unsigned int*)(0x42448180UL))) +#define bM4_I2S4_CFGR_I2SSTD1 (*((volatile unsigned int*)(0x42448184UL))) +#define bM4_I2S4_CFGR_DATLEN0 (*((volatile unsigned int*)(0x42448188UL))) +#define bM4_I2S4_CFGR_DATLEN1 (*((volatile unsigned int*)(0x4244818CUL))) +#define bM4_I2S4_CFGR_CHLEN (*((volatile unsigned int*)(0x42448190UL))) +#define bM4_I2S4_CFGR_PCMSYNC (*((volatile unsigned int*)(0x42448194UL))) +#define bM4_I2S4_PR_I2SDIV0 (*((volatile unsigned int*)(0x42448300UL))) +#define bM4_I2S4_PR_I2SDIV1 (*((volatile unsigned int*)(0x42448304UL))) +#define bM4_I2S4_PR_I2SDIV2 (*((volatile unsigned int*)(0x42448308UL))) +#define bM4_I2S4_PR_I2SDIV3 (*((volatile unsigned int*)(0x4244830CUL))) +#define bM4_I2S4_PR_I2SDIV4 (*((volatile unsigned int*)(0x42448310UL))) +#define bM4_I2S4_PR_I2SDIV5 (*((volatile unsigned int*)(0x42448314UL))) +#define bM4_I2S4_PR_I2SDIV6 (*((volatile unsigned int*)(0x42448318UL))) +#define bM4_I2S4_PR_I2SDIV7 (*((volatile unsigned int*)(0x4244831CUL))) +#define bM4_INTC_NMICR_NMITRG (*((volatile unsigned int*)(0x42A20000UL))) +#define bM4_INTC_NMICR_NSMPCLK0 (*((volatile unsigned int*)(0x42A20010UL))) +#define bM4_INTC_NMICR_NSMPCLK1 (*((volatile unsigned int*)(0x42A20014UL))) +#define bM4_INTC_NMICR_NFEN (*((volatile unsigned int*)(0x42A2001CUL))) +#define bM4_INTC_NMIENR_NMIENR (*((volatile unsigned int*)(0x42A20080UL))) +#define bM4_INTC_NMIENR_SWDTENR (*((volatile unsigned int*)(0x42A20084UL))) +#define bM4_INTC_NMIENR_PVD1ENR (*((volatile unsigned int*)(0x42A20088UL))) +#define bM4_INTC_NMIENR_PVD2ENR (*((volatile unsigned int*)(0x42A2008CUL))) +#define bM4_INTC_NMIENR_XTALSTPENR (*((volatile unsigned int*)(0x42A20094UL))) +#define bM4_INTC_NMIENR_REPENR (*((volatile unsigned int*)(0x42A200A0UL))) +#define bM4_INTC_NMIENR_RECCENR (*((volatile unsigned int*)(0x42A200A4UL))) +#define bM4_INTC_NMIENR_BUSMENR (*((volatile unsigned int*)(0x42A200A8UL))) +#define bM4_INTC_NMIENR_WDTENR (*((volatile unsigned int*)(0x42A200ACUL))) +#define bM4_INTC_NMIFR_NMIFR (*((volatile unsigned int*)(0x42A20100UL))) +#define bM4_INTC_NMIFR_SWDTFR (*((volatile unsigned int*)(0x42A20104UL))) +#define bM4_INTC_NMIFR_PVD1FR (*((volatile unsigned int*)(0x42A20108UL))) +#define bM4_INTC_NMIFR_PVD2FR (*((volatile unsigned int*)(0x42A2010CUL))) +#define bM4_INTC_NMIFR_XTALSTPFR (*((volatile unsigned int*)(0x42A20114UL))) +#define bM4_INTC_NMIFR_REPFR (*((volatile unsigned int*)(0x42A20120UL))) +#define bM4_INTC_NMIFR_RECCFR (*((volatile unsigned int*)(0x42A20124UL))) +#define bM4_INTC_NMIFR_BUSMFR (*((volatile unsigned int*)(0x42A20128UL))) +#define bM4_INTC_NMIFR_WDTFR (*((volatile unsigned int*)(0x42A2012CUL))) +#define bM4_INTC_NMICFR_NMICFR (*((volatile unsigned int*)(0x42A20180UL))) +#define bM4_INTC_NMICFR_SWDTCFR (*((volatile unsigned int*)(0x42A20184UL))) +#define bM4_INTC_NMICFR_PVD1CFR (*((volatile unsigned int*)(0x42A20188UL))) +#define bM4_INTC_NMICFR_PVD2CFR (*((volatile unsigned int*)(0x42A2018CUL))) +#define bM4_INTC_NMICFR_XTALSTPCFR (*((volatile unsigned int*)(0x42A20194UL))) +#define bM4_INTC_NMICFR_REPCFR (*((volatile unsigned int*)(0x42A201A0UL))) +#define bM4_INTC_NMICFR_RECCCFR (*((volatile unsigned int*)(0x42A201A4UL))) +#define bM4_INTC_NMICFR_BUSMCFR (*((volatile unsigned int*)(0x42A201A8UL))) +#define bM4_INTC_NMICFR_WDTCFR (*((volatile unsigned int*)(0x42A201ACUL))) +#define bM4_INTC_EIRQCR0_EIRQTRG0 (*((volatile unsigned int*)(0x42A20200UL))) +#define bM4_INTC_EIRQCR0_EIRQTRG1 (*((volatile unsigned int*)(0x42A20204UL))) +#define bM4_INTC_EIRQCR0_EISMPCLK0 (*((volatile unsigned int*)(0x42A20210UL))) +#define bM4_INTC_EIRQCR0_EISMPCLK1 (*((volatile unsigned int*)(0x42A20214UL))) +#define bM4_INTC_EIRQCR0_EFEN (*((volatile unsigned int*)(0x42A2021CUL))) +#define bM4_INTC_EIRQCR1_EIRQTRG0 (*((volatile unsigned int*)(0x42A20280UL))) +#define bM4_INTC_EIRQCR1_EIRQTRG1 (*((volatile unsigned int*)(0x42A20284UL))) +#define bM4_INTC_EIRQCR1_EISMPCLK0 (*((volatile unsigned int*)(0x42A20290UL))) +#define bM4_INTC_EIRQCR1_EISMPCLK1 (*((volatile unsigned int*)(0x42A20294UL))) +#define bM4_INTC_EIRQCR1_EFEN (*((volatile unsigned int*)(0x42A2029CUL))) +#define bM4_INTC_EIRQCR2_EIRQTRG0 (*((volatile unsigned int*)(0x42A20300UL))) +#define bM4_INTC_EIRQCR2_EIRQTRG1 (*((volatile unsigned int*)(0x42A20304UL))) +#define bM4_INTC_EIRQCR2_EISMPCLK0 (*((volatile unsigned int*)(0x42A20310UL))) +#define bM4_INTC_EIRQCR2_EISMPCLK1 (*((volatile unsigned int*)(0x42A20314UL))) +#define bM4_INTC_EIRQCR2_EFEN (*((volatile unsigned int*)(0x42A2031CUL))) +#define bM4_INTC_EIRQCR3_EIRQTRG0 (*((volatile unsigned int*)(0x42A20380UL))) +#define bM4_INTC_EIRQCR3_EIRQTRG1 (*((volatile unsigned int*)(0x42A20384UL))) +#define bM4_INTC_EIRQCR3_EISMPCLK0 (*((volatile unsigned int*)(0x42A20390UL))) +#define bM4_INTC_EIRQCR3_EISMPCLK1 (*((volatile unsigned int*)(0x42A20394UL))) +#define bM4_INTC_EIRQCR3_EFEN (*((volatile unsigned int*)(0x42A2039CUL))) +#define bM4_INTC_EIRQCR4_EIRQTRG0 (*((volatile unsigned int*)(0x42A20400UL))) +#define bM4_INTC_EIRQCR4_EIRQTRG1 (*((volatile unsigned int*)(0x42A20404UL))) +#define bM4_INTC_EIRQCR4_EISMPCLK0 (*((volatile unsigned int*)(0x42A20410UL))) +#define bM4_INTC_EIRQCR4_EISMPCLK1 (*((volatile unsigned int*)(0x42A20414UL))) +#define bM4_INTC_EIRQCR4_EFEN (*((volatile unsigned int*)(0x42A2041CUL))) +#define bM4_INTC_EIRQCR5_EIRQTRG0 (*((volatile unsigned int*)(0x42A20480UL))) +#define bM4_INTC_EIRQCR5_EIRQTRG1 (*((volatile unsigned int*)(0x42A20484UL))) +#define bM4_INTC_EIRQCR5_EISMPCLK0 (*((volatile unsigned int*)(0x42A20490UL))) +#define bM4_INTC_EIRQCR5_EISMPCLK1 (*((volatile unsigned int*)(0x42A20494UL))) +#define bM4_INTC_EIRQCR5_EFEN (*((volatile unsigned int*)(0x42A2049CUL))) +#define bM4_INTC_EIRQCR6_EIRQTRG0 (*((volatile unsigned int*)(0x42A20500UL))) +#define bM4_INTC_EIRQCR6_EIRQTRG1 (*((volatile unsigned int*)(0x42A20504UL))) +#define bM4_INTC_EIRQCR6_EISMPCLK0 (*((volatile unsigned int*)(0x42A20510UL))) +#define bM4_INTC_EIRQCR6_EISMPCLK1 (*((volatile unsigned int*)(0x42A20514UL))) +#define bM4_INTC_EIRQCR6_EFEN (*((volatile unsigned int*)(0x42A2051CUL))) +#define bM4_INTC_EIRQCR7_EIRQTRG0 (*((volatile unsigned int*)(0x42A20580UL))) +#define bM4_INTC_EIRQCR7_EIRQTRG1 (*((volatile unsigned int*)(0x42A20584UL))) +#define bM4_INTC_EIRQCR7_EISMPCLK0 (*((volatile unsigned int*)(0x42A20590UL))) +#define bM4_INTC_EIRQCR7_EISMPCLK1 (*((volatile unsigned int*)(0x42A20594UL))) +#define bM4_INTC_EIRQCR7_EFEN (*((volatile unsigned int*)(0x42A2059CUL))) +#define bM4_INTC_EIRQCR8_EIRQTRG0 (*((volatile unsigned int*)(0x42A20600UL))) +#define bM4_INTC_EIRQCR8_EIRQTRG1 (*((volatile unsigned int*)(0x42A20604UL))) +#define bM4_INTC_EIRQCR8_EISMPCLK0 (*((volatile unsigned int*)(0x42A20610UL))) +#define bM4_INTC_EIRQCR8_EISMPCLK1 (*((volatile unsigned int*)(0x42A20614UL))) +#define bM4_INTC_EIRQCR8_EFEN (*((volatile unsigned int*)(0x42A2061CUL))) +#define bM4_INTC_EIRQCR9_EIRQTRG0 (*((volatile unsigned int*)(0x42A20680UL))) +#define bM4_INTC_EIRQCR9_EIRQTRG1 (*((volatile unsigned int*)(0x42A20684UL))) +#define bM4_INTC_EIRQCR9_EISMPCLK0 (*((volatile unsigned int*)(0x42A20690UL))) +#define bM4_INTC_EIRQCR9_EISMPCLK1 (*((volatile unsigned int*)(0x42A20694UL))) +#define bM4_INTC_EIRQCR9_EFEN (*((volatile unsigned int*)(0x42A2069CUL))) +#define bM4_INTC_EIRQCR10_EIRQTRG0 (*((volatile unsigned int*)(0x42A20700UL))) +#define bM4_INTC_EIRQCR10_EIRQTRG1 (*((volatile unsigned int*)(0x42A20704UL))) +#define bM4_INTC_EIRQCR10_EISMPCLK0 (*((volatile unsigned int*)(0x42A20710UL))) +#define bM4_INTC_EIRQCR10_EISMPCLK1 (*((volatile unsigned int*)(0x42A20714UL))) +#define bM4_INTC_EIRQCR10_EFEN (*((volatile unsigned int*)(0x42A2071CUL))) +#define bM4_INTC_EIRQCR11_EIRQTRG0 (*((volatile unsigned int*)(0x42A20780UL))) +#define bM4_INTC_EIRQCR11_EIRQTRG1 (*((volatile unsigned int*)(0x42A20784UL))) +#define bM4_INTC_EIRQCR11_EISMPCLK0 (*((volatile unsigned int*)(0x42A20790UL))) +#define bM4_INTC_EIRQCR11_EISMPCLK1 (*((volatile unsigned int*)(0x42A20794UL))) +#define bM4_INTC_EIRQCR11_EFEN (*((volatile unsigned int*)(0x42A2079CUL))) +#define bM4_INTC_EIRQCR12_EIRQTRG0 (*((volatile unsigned int*)(0x42A20800UL))) +#define bM4_INTC_EIRQCR12_EIRQTRG1 (*((volatile unsigned int*)(0x42A20804UL))) +#define bM4_INTC_EIRQCR12_EISMPCLK0 (*((volatile unsigned int*)(0x42A20810UL))) +#define bM4_INTC_EIRQCR12_EISMPCLK1 (*((volatile unsigned int*)(0x42A20814UL))) +#define bM4_INTC_EIRQCR12_EFEN (*((volatile unsigned int*)(0x42A2081CUL))) +#define bM4_INTC_EIRQCR13_EIRQTRG0 (*((volatile unsigned int*)(0x42A20880UL))) +#define bM4_INTC_EIRQCR13_EIRQTRG1 (*((volatile unsigned int*)(0x42A20884UL))) +#define bM4_INTC_EIRQCR13_EISMPCLK0 (*((volatile unsigned int*)(0x42A20890UL))) +#define bM4_INTC_EIRQCR13_EISMPCLK1 (*((volatile unsigned int*)(0x42A20894UL))) +#define bM4_INTC_EIRQCR13_EFEN (*((volatile unsigned int*)(0x42A2089CUL))) +#define bM4_INTC_EIRQCR14_EIRQTRG0 (*((volatile unsigned int*)(0x42A20900UL))) +#define bM4_INTC_EIRQCR14_EIRQTRG1 (*((volatile unsigned int*)(0x42A20904UL))) +#define bM4_INTC_EIRQCR14_EISMPCLK0 (*((volatile unsigned int*)(0x42A20910UL))) +#define bM4_INTC_EIRQCR14_EISMPCLK1 (*((volatile unsigned int*)(0x42A20914UL))) +#define bM4_INTC_EIRQCR14_EFEN (*((volatile unsigned int*)(0x42A2091CUL))) +#define bM4_INTC_EIRQCR15_EIRQTRG0 (*((volatile unsigned int*)(0x42A20980UL))) +#define bM4_INTC_EIRQCR15_EIRQTRG1 (*((volatile unsigned int*)(0x42A20984UL))) +#define bM4_INTC_EIRQCR15_EISMPCLK0 (*((volatile unsigned int*)(0x42A20990UL))) +#define bM4_INTC_EIRQCR15_EISMPCLK1 (*((volatile unsigned int*)(0x42A20994UL))) +#define bM4_INTC_EIRQCR15_EFEN (*((volatile unsigned int*)(0x42A2099CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN0 (*((volatile unsigned int*)(0x42A20A00UL))) +#define bM4_INTC_WUPEN_EIRQWUEN1 (*((volatile unsigned int*)(0x42A20A04UL))) +#define bM4_INTC_WUPEN_EIRQWUEN2 (*((volatile unsigned int*)(0x42A20A08UL))) +#define bM4_INTC_WUPEN_EIRQWUEN3 (*((volatile unsigned int*)(0x42A20A0CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN4 (*((volatile unsigned int*)(0x42A20A10UL))) +#define bM4_INTC_WUPEN_EIRQWUEN5 (*((volatile unsigned int*)(0x42A20A14UL))) +#define bM4_INTC_WUPEN_EIRQWUEN6 (*((volatile unsigned int*)(0x42A20A18UL))) +#define bM4_INTC_WUPEN_EIRQWUEN7 (*((volatile unsigned int*)(0x42A20A1CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN8 (*((volatile unsigned int*)(0x42A20A20UL))) +#define bM4_INTC_WUPEN_EIRQWUEN9 (*((volatile unsigned int*)(0x42A20A24UL))) +#define bM4_INTC_WUPEN_EIRQWUEN10 (*((volatile unsigned int*)(0x42A20A28UL))) +#define bM4_INTC_WUPEN_EIRQWUEN11 (*((volatile unsigned int*)(0x42A20A2CUL))) +#define bM4_INTC_WUPEN_EIRQWUEN12 (*((volatile unsigned int*)(0x42A20A30UL))) +#define bM4_INTC_WUPEN_EIRQWUEN13 (*((volatile unsigned int*)(0x42A20A34UL))) +#define bM4_INTC_WUPEN_EIRQWUEN14 (*((volatile unsigned int*)(0x42A20A38UL))) +#define bM4_INTC_WUPEN_EIRQWUEN15 (*((volatile unsigned int*)(0x42A20A3CUL))) +#define bM4_INTC_WUPEN_SWDTWUEN (*((volatile unsigned int*)(0x42A20A40UL))) +#define bM4_INTC_WUPEN_PVD1WUEN (*((volatile unsigned int*)(0x42A20A44UL))) +#define bM4_INTC_WUPEN_PVD2WUEN (*((volatile unsigned int*)(0x42A20A48UL))) +#define bM4_INTC_WUPEN_CMPI0WUEN (*((volatile unsigned int*)(0x42A20A4CUL))) +#define bM4_INTC_WUPEN_WKTMWUEN (*((volatile unsigned int*)(0x42A20A50UL))) +#define bM4_INTC_WUPEN_RTCALMWUEN (*((volatile unsigned int*)(0x42A20A54UL))) +#define bM4_INTC_WUPEN_RTCPRDWUEN (*((volatile unsigned int*)(0x42A20A58UL))) +#define bM4_INTC_WUPEN_TMR0WUEN (*((volatile unsigned int*)(0x42A20A5CUL))) +#define bM4_INTC_WUPEN_RXWUEN (*((volatile unsigned int*)(0x42A20A64UL))) +#define bM4_INTC_EIFR_EIFR0 (*((volatile unsigned int*)(0x42A20A80UL))) +#define bM4_INTC_EIFR_EIFR1 (*((volatile unsigned int*)(0x42A20A84UL))) +#define bM4_INTC_EIFR_EIFR2 (*((volatile unsigned int*)(0x42A20A88UL))) +#define bM4_INTC_EIFR_EIFR3 (*((volatile unsigned int*)(0x42A20A8CUL))) +#define bM4_INTC_EIFR_EIFR4 (*((volatile unsigned int*)(0x42A20A90UL))) +#define bM4_INTC_EIFR_EIFR5 (*((volatile unsigned int*)(0x42A20A94UL))) +#define bM4_INTC_EIFR_EIFR6 (*((volatile unsigned int*)(0x42A20A98UL))) +#define bM4_INTC_EIFR_EIFR7 (*((volatile unsigned int*)(0x42A20A9CUL))) +#define bM4_INTC_EIFR_EIFR8 (*((volatile unsigned int*)(0x42A20AA0UL))) +#define bM4_INTC_EIFR_EIFR9 (*((volatile unsigned int*)(0x42A20AA4UL))) +#define bM4_INTC_EIFR_EIFR10 (*((volatile unsigned int*)(0x42A20AA8UL))) +#define bM4_INTC_EIFR_EIFR11 (*((volatile unsigned int*)(0x42A20AACUL))) +#define bM4_INTC_EIFR_EIFR12 (*((volatile unsigned int*)(0x42A20AB0UL))) +#define bM4_INTC_EIFR_EIFR13 (*((volatile unsigned int*)(0x42A20AB4UL))) +#define bM4_INTC_EIFR_EIFR14 (*((volatile unsigned int*)(0x42A20AB8UL))) +#define bM4_INTC_EIFR_EIFR15 (*((volatile unsigned int*)(0x42A20ABCUL))) +#define bM4_INTC_EICFR_EICFR0 (*((volatile unsigned int*)(0x42A20B00UL))) +#define bM4_INTC_EICFR_EICFR1 (*((volatile unsigned int*)(0x42A20B04UL))) +#define bM4_INTC_EICFR_EICFR2 (*((volatile unsigned int*)(0x42A20B08UL))) +#define bM4_INTC_EICFR_EICFR3 (*((volatile unsigned int*)(0x42A20B0CUL))) +#define bM4_INTC_EICFR_EICFR4 (*((volatile unsigned int*)(0x42A20B10UL))) +#define bM4_INTC_EICFR_EICFR5 (*((volatile unsigned int*)(0x42A20B14UL))) +#define bM4_INTC_EICFR_EICFR6 (*((volatile unsigned int*)(0x42A20B18UL))) +#define bM4_INTC_EICFR_EICFR7 (*((volatile unsigned int*)(0x42A20B1CUL))) +#define bM4_INTC_EICFR_EICFR8 (*((volatile unsigned int*)(0x42A20B20UL))) +#define bM4_INTC_EICFR_EICFR9 (*((volatile unsigned int*)(0x42A20B24UL))) +#define bM4_INTC_EICFR_EICFR10 (*((volatile unsigned int*)(0x42A20B28UL))) +#define bM4_INTC_EICFR_EICFR11 (*((volatile unsigned int*)(0x42A20B2CUL))) +#define bM4_INTC_EICFR_EICFR12 (*((volatile unsigned int*)(0x42A20B30UL))) +#define bM4_INTC_EICFR_EICFR13 (*((volatile unsigned int*)(0x42A20B34UL))) +#define bM4_INTC_EICFR_EICFR14 (*((volatile unsigned int*)(0x42A20B38UL))) +#define bM4_INTC_EICFR_EICFR15 (*((volatile unsigned int*)(0x42A20B3CUL))) +#define bM4_INTC_SEL0_INTSEL0 (*((volatile unsigned int*)(0x42A20B80UL))) +#define bM4_INTC_SEL0_INTSEL1 (*((volatile unsigned int*)(0x42A20B84UL))) +#define bM4_INTC_SEL0_INTSEL2 (*((volatile unsigned int*)(0x42A20B88UL))) +#define bM4_INTC_SEL0_INTSEL3 (*((volatile unsigned int*)(0x42A20B8CUL))) +#define bM4_INTC_SEL0_INTSEL4 (*((volatile unsigned int*)(0x42A20B90UL))) +#define bM4_INTC_SEL0_INTSEL5 (*((volatile unsigned int*)(0x42A20B94UL))) +#define bM4_INTC_SEL0_INTSEL6 (*((volatile unsigned int*)(0x42A20B98UL))) +#define bM4_INTC_SEL0_INTSEL7 (*((volatile unsigned int*)(0x42A20B9CUL))) +#define bM4_INTC_SEL0_INTSEL8 (*((volatile unsigned int*)(0x42A20BA0UL))) +#define bM4_INTC_SEL1_INTSEL0 (*((volatile unsigned int*)(0x42A20C00UL))) +#define bM4_INTC_SEL1_INTSEL1 (*((volatile unsigned int*)(0x42A20C04UL))) +#define bM4_INTC_SEL1_INTSEL2 (*((volatile unsigned int*)(0x42A20C08UL))) +#define bM4_INTC_SEL1_INTSEL3 (*((volatile unsigned int*)(0x42A20C0CUL))) +#define bM4_INTC_SEL1_INTSEL4 (*((volatile unsigned int*)(0x42A20C10UL))) +#define bM4_INTC_SEL1_INTSEL5 (*((volatile unsigned int*)(0x42A20C14UL))) +#define bM4_INTC_SEL1_INTSEL6 (*((volatile unsigned int*)(0x42A20C18UL))) +#define bM4_INTC_SEL1_INTSEL7 (*((volatile unsigned int*)(0x42A20C1CUL))) +#define bM4_INTC_SEL1_INTSEL8 (*((volatile unsigned int*)(0x42A20C20UL))) +#define bM4_INTC_SEL2_INTSEL0 (*((volatile unsigned int*)(0x42A20C80UL))) +#define bM4_INTC_SEL2_INTSEL1 (*((volatile unsigned int*)(0x42A20C84UL))) +#define bM4_INTC_SEL2_INTSEL2 (*((volatile unsigned int*)(0x42A20C88UL))) +#define bM4_INTC_SEL2_INTSEL3 (*((volatile unsigned int*)(0x42A20C8CUL))) +#define bM4_INTC_SEL2_INTSEL4 (*((volatile unsigned int*)(0x42A20C90UL))) +#define bM4_INTC_SEL2_INTSEL5 (*((volatile unsigned int*)(0x42A20C94UL))) +#define bM4_INTC_SEL2_INTSEL6 (*((volatile unsigned int*)(0x42A20C98UL))) +#define bM4_INTC_SEL2_INTSEL7 (*((volatile unsigned int*)(0x42A20C9CUL))) +#define bM4_INTC_SEL2_INTSEL8 (*((volatile unsigned int*)(0x42A20CA0UL))) +#define bM4_INTC_SEL3_INTSEL0 (*((volatile unsigned int*)(0x42A20D00UL))) +#define bM4_INTC_SEL3_INTSEL1 (*((volatile unsigned int*)(0x42A20D04UL))) +#define bM4_INTC_SEL3_INTSEL2 (*((volatile unsigned int*)(0x42A20D08UL))) +#define bM4_INTC_SEL3_INTSEL3 (*((volatile unsigned int*)(0x42A20D0CUL))) +#define bM4_INTC_SEL3_INTSEL4 (*((volatile unsigned int*)(0x42A20D10UL))) +#define bM4_INTC_SEL3_INTSEL5 (*((volatile unsigned int*)(0x42A20D14UL))) +#define bM4_INTC_SEL3_INTSEL6 (*((volatile unsigned int*)(0x42A20D18UL))) +#define bM4_INTC_SEL3_INTSEL7 (*((volatile unsigned int*)(0x42A20D1CUL))) +#define bM4_INTC_SEL3_INTSEL8 (*((volatile unsigned int*)(0x42A20D20UL))) +#define bM4_INTC_SEL4_INTSEL0 (*((volatile unsigned int*)(0x42A20D80UL))) +#define bM4_INTC_SEL4_INTSEL1 (*((volatile unsigned int*)(0x42A20D84UL))) +#define bM4_INTC_SEL4_INTSEL2 (*((volatile unsigned int*)(0x42A20D88UL))) +#define bM4_INTC_SEL4_INTSEL3 (*((volatile unsigned int*)(0x42A20D8CUL))) +#define bM4_INTC_SEL4_INTSEL4 (*((volatile unsigned int*)(0x42A20D90UL))) +#define bM4_INTC_SEL4_INTSEL5 (*((volatile unsigned int*)(0x42A20D94UL))) +#define bM4_INTC_SEL4_INTSEL6 (*((volatile unsigned int*)(0x42A20D98UL))) +#define bM4_INTC_SEL4_INTSEL7 (*((volatile unsigned int*)(0x42A20D9CUL))) +#define bM4_INTC_SEL4_INTSEL8 (*((volatile unsigned int*)(0x42A20DA0UL))) +#define bM4_INTC_SEL5_INTSEL0 (*((volatile unsigned int*)(0x42A20E00UL))) +#define bM4_INTC_SEL5_INTSEL1 (*((volatile unsigned int*)(0x42A20E04UL))) +#define bM4_INTC_SEL5_INTSEL2 (*((volatile unsigned int*)(0x42A20E08UL))) +#define bM4_INTC_SEL5_INTSEL3 (*((volatile unsigned int*)(0x42A20E0CUL))) +#define bM4_INTC_SEL5_INTSEL4 (*((volatile unsigned int*)(0x42A20E10UL))) +#define bM4_INTC_SEL5_INTSEL5 (*((volatile unsigned int*)(0x42A20E14UL))) +#define bM4_INTC_SEL5_INTSEL6 (*((volatile unsigned int*)(0x42A20E18UL))) +#define bM4_INTC_SEL5_INTSEL7 (*((volatile unsigned int*)(0x42A20E1CUL))) +#define bM4_INTC_SEL5_INTSEL8 (*((volatile unsigned int*)(0x42A20E20UL))) +#define bM4_INTC_SEL6_INTSEL0 (*((volatile unsigned int*)(0x42A20E80UL))) +#define bM4_INTC_SEL6_INTSEL1 (*((volatile unsigned int*)(0x42A20E84UL))) +#define bM4_INTC_SEL6_INTSEL2 (*((volatile unsigned int*)(0x42A20E88UL))) +#define bM4_INTC_SEL6_INTSEL3 (*((volatile unsigned int*)(0x42A20E8CUL))) +#define bM4_INTC_SEL6_INTSEL4 (*((volatile unsigned int*)(0x42A20E90UL))) +#define bM4_INTC_SEL6_INTSEL5 (*((volatile unsigned int*)(0x42A20E94UL))) +#define bM4_INTC_SEL6_INTSEL6 (*((volatile unsigned int*)(0x42A20E98UL))) +#define bM4_INTC_SEL6_INTSEL7 (*((volatile unsigned int*)(0x42A20E9CUL))) +#define bM4_INTC_SEL6_INTSEL8 (*((volatile unsigned int*)(0x42A20EA0UL))) +#define bM4_INTC_SEL7_INTSEL0 (*((volatile unsigned int*)(0x42A20F00UL))) +#define bM4_INTC_SEL7_INTSEL1 (*((volatile unsigned int*)(0x42A20F04UL))) +#define bM4_INTC_SEL7_INTSEL2 (*((volatile unsigned int*)(0x42A20F08UL))) +#define bM4_INTC_SEL7_INTSEL3 (*((volatile unsigned int*)(0x42A20F0CUL))) +#define bM4_INTC_SEL7_INTSEL4 (*((volatile unsigned int*)(0x42A20F10UL))) +#define bM4_INTC_SEL7_INTSEL5 (*((volatile unsigned int*)(0x42A20F14UL))) +#define bM4_INTC_SEL7_INTSEL6 (*((volatile unsigned int*)(0x42A20F18UL))) +#define bM4_INTC_SEL7_INTSEL7 (*((volatile unsigned int*)(0x42A20F1CUL))) +#define bM4_INTC_SEL7_INTSEL8 (*((volatile unsigned int*)(0x42A20F20UL))) +#define bM4_INTC_SEL8_INTSEL0 (*((volatile unsigned int*)(0x42A20F80UL))) +#define bM4_INTC_SEL8_INTSEL1 (*((volatile unsigned int*)(0x42A20F84UL))) +#define bM4_INTC_SEL8_INTSEL2 (*((volatile unsigned int*)(0x42A20F88UL))) +#define bM4_INTC_SEL8_INTSEL3 (*((volatile unsigned int*)(0x42A20F8CUL))) +#define bM4_INTC_SEL8_INTSEL4 (*((volatile unsigned int*)(0x42A20F90UL))) +#define bM4_INTC_SEL8_INTSEL5 (*((volatile unsigned int*)(0x42A20F94UL))) +#define bM4_INTC_SEL8_INTSEL6 (*((volatile unsigned int*)(0x42A20F98UL))) +#define bM4_INTC_SEL8_INTSEL7 (*((volatile unsigned int*)(0x42A20F9CUL))) +#define bM4_INTC_SEL8_INTSEL8 (*((volatile unsigned int*)(0x42A20FA0UL))) +#define bM4_INTC_SEL9_INTSEL0 (*((volatile unsigned int*)(0x42A21000UL))) +#define bM4_INTC_SEL9_INTSEL1 (*((volatile unsigned int*)(0x42A21004UL))) +#define bM4_INTC_SEL9_INTSEL2 (*((volatile unsigned int*)(0x42A21008UL))) +#define bM4_INTC_SEL9_INTSEL3 (*((volatile unsigned int*)(0x42A2100CUL))) +#define bM4_INTC_SEL9_INTSEL4 (*((volatile unsigned int*)(0x42A21010UL))) +#define bM4_INTC_SEL9_INTSEL5 (*((volatile unsigned int*)(0x42A21014UL))) +#define bM4_INTC_SEL9_INTSEL6 (*((volatile unsigned int*)(0x42A21018UL))) +#define bM4_INTC_SEL9_INTSEL7 (*((volatile unsigned int*)(0x42A2101CUL))) +#define bM4_INTC_SEL9_INTSEL8 (*((volatile unsigned int*)(0x42A21020UL))) +#define bM4_INTC_SEL10_INTSEL0 (*((volatile unsigned int*)(0x42A21080UL))) +#define bM4_INTC_SEL10_INTSEL1 (*((volatile unsigned int*)(0x42A21084UL))) +#define bM4_INTC_SEL10_INTSEL2 (*((volatile unsigned int*)(0x42A21088UL))) +#define bM4_INTC_SEL10_INTSEL3 (*((volatile unsigned int*)(0x42A2108CUL))) +#define bM4_INTC_SEL10_INTSEL4 (*((volatile unsigned int*)(0x42A21090UL))) +#define bM4_INTC_SEL10_INTSEL5 (*((volatile unsigned int*)(0x42A21094UL))) +#define bM4_INTC_SEL10_INTSEL6 (*((volatile unsigned int*)(0x42A21098UL))) +#define bM4_INTC_SEL10_INTSEL7 (*((volatile unsigned int*)(0x42A2109CUL))) +#define bM4_INTC_SEL10_INTSEL8 (*((volatile unsigned int*)(0x42A210A0UL))) +#define bM4_INTC_SEL11_INTSEL0 (*((volatile unsigned int*)(0x42A21100UL))) +#define bM4_INTC_SEL11_INTSEL1 (*((volatile unsigned int*)(0x42A21104UL))) +#define bM4_INTC_SEL11_INTSEL2 (*((volatile unsigned int*)(0x42A21108UL))) +#define bM4_INTC_SEL11_INTSEL3 (*((volatile unsigned int*)(0x42A2110CUL))) +#define bM4_INTC_SEL11_INTSEL4 (*((volatile unsigned int*)(0x42A21110UL))) +#define bM4_INTC_SEL11_INTSEL5 (*((volatile unsigned int*)(0x42A21114UL))) +#define bM4_INTC_SEL11_INTSEL6 (*((volatile unsigned int*)(0x42A21118UL))) +#define bM4_INTC_SEL11_INTSEL7 (*((volatile unsigned int*)(0x42A2111CUL))) +#define bM4_INTC_SEL11_INTSEL8 (*((volatile unsigned int*)(0x42A21120UL))) +#define bM4_INTC_SEL12_INTSEL0 (*((volatile unsigned int*)(0x42A21180UL))) +#define bM4_INTC_SEL12_INTSEL1 (*((volatile unsigned int*)(0x42A21184UL))) +#define bM4_INTC_SEL12_INTSEL2 (*((volatile unsigned int*)(0x42A21188UL))) +#define bM4_INTC_SEL12_INTSEL3 (*((volatile unsigned int*)(0x42A2118CUL))) +#define bM4_INTC_SEL12_INTSEL4 (*((volatile unsigned int*)(0x42A21190UL))) +#define bM4_INTC_SEL12_INTSEL5 (*((volatile unsigned int*)(0x42A21194UL))) +#define bM4_INTC_SEL12_INTSEL6 (*((volatile unsigned int*)(0x42A21198UL))) +#define bM4_INTC_SEL12_INTSEL7 (*((volatile unsigned int*)(0x42A2119CUL))) +#define bM4_INTC_SEL12_INTSEL8 (*((volatile unsigned int*)(0x42A211A0UL))) +#define bM4_INTC_SEL13_INTSEL0 (*((volatile unsigned int*)(0x42A21200UL))) +#define bM4_INTC_SEL13_INTSEL1 (*((volatile unsigned int*)(0x42A21204UL))) +#define bM4_INTC_SEL13_INTSEL2 (*((volatile unsigned int*)(0x42A21208UL))) +#define bM4_INTC_SEL13_INTSEL3 (*((volatile unsigned int*)(0x42A2120CUL))) +#define bM4_INTC_SEL13_INTSEL4 (*((volatile unsigned int*)(0x42A21210UL))) +#define bM4_INTC_SEL13_INTSEL5 (*((volatile unsigned int*)(0x42A21214UL))) +#define bM4_INTC_SEL13_INTSEL6 (*((volatile unsigned int*)(0x42A21218UL))) +#define bM4_INTC_SEL13_INTSEL7 (*((volatile unsigned int*)(0x42A2121CUL))) +#define bM4_INTC_SEL13_INTSEL8 (*((volatile unsigned int*)(0x42A21220UL))) +#define bM4_INTC_SEL14_INTSEL0 (*((volatile unsigned int*)(0x42A21280UL))) +#define bM4_INTC_SEL14_INTSEL1 (*((volatile unsigned int*)(0x42A21284UL))) +#define bM4_INTC_SEL14_INTSEL2 (*((volatile unsigned int*)(0x42A21288UL))) +#define bM4_INTC_SEL14_INTSEL3 (*((volatile unsigned int*)(0x42A2128CUL))) +#define bM4_INTC_SEL14_INTSEL4 (*((volatile unsigned int*)(0x42A21290UL))) +#define bM4_INTC_SEL14_INTSEL5 (*((volatile unsigned int*)(0x42A21294UL))) +#define bM4_INTC_SEL14_INTSEL6 (*((volatile unsigned int*)(0x42A21298UL))) +#define bM4_INTC_SEL14_INTSEL7 (*((volatile unsigned int*)(0x42A2129CUL))) +#define bM4_INTC_SEL14_INTSEL8 (*((volatile unsigned int*)(0x42A212A0UL))) +#define bM4_INTC_SEL15_INTSEL0 (*((volatile unsigned int*)(0x42A21300UL))) +#define bM4_INTC_SEL15_INTSEL1 (*((volatile unsigned int*)(0x42A21304UL))) +#define bM4_INTC_SEL15_INTSEL2 (*((volatile unsigned int*)(0x42A21308UL))) +#define bM4_INTC_SEL15_INTSEL3 (*((volatile unsigned int*)(0x42A2130CUL))) +#define bM4_INTC_SEL15_INTSEL4 (*((volatile unsigned int*)(0x42A21310UL))) +#define bM4_INTC_SEL15_INTSEL5 (*((volatile unsigned int*)(0x42A21314UL))) +#define bM4_INTC_SEL15_INTSEL6 (*((volatile unsigned int*)(0x42A21318UL))) +#define bM4_INTC_SEL15_INTSEL7 (*((volatile unsigned int*)(0x42A2131CUL))) +#define bM4_INTC_SEL15_INTSEL8 (*((volatile unsigned int*)(0x42A21320UL))) +#define bM4_INTC_SEL16_INTSEL0 (*((volatile unsigned int*)(0x42A21380UL))) +#define bM4_INTC_SEL16_INTSEL1 (*((volatile unsigned int*)(0x42A21384UL))) +#define bM4_INTC_SEL16_INTSEL2 (*((volatile unsigned int*)(0x42A21388UL))) +#define bM4_INTC_SEL16_INTSEL3 (*((volatile unsigned int*)(0x42A2138CUL))) +#define bM4_INTC_SEL16_INTSEL4 (*((volatile unsigned int*)(0x42A21390UL))) +#define bM4_INTC_SEL16_INTSEL5 (*((volatile unsigned int*)(0x42A21394UL))) +#define bM4_INTC_SEL16_INTSEL6 (*((volatile unsigned int*)(0x42A21398UL))) +#define bM4_INTC_SEL16_INTSEL7 (*((volatile unsigned int*)(0x42A2139CUL))) +#define bM4_INTC_SEL16_INTSEL8 (*((volatile unsigned int*)(0x42A213A0UL))) +#define bM4_INTC_SEL17_INTSEL0 (*((volatile unsigned int*)(0x42A21400UL))) +#define bM4_INTC_SEL17_INTSEL1 (*((volatile unsigned int*)(0x42A21404UL))) +#define bM4_INTC_SEL17_INTSEL2 (*((volatile unsigned int*)(0x42A21408UL))) +#define bM4_INTC_SEL17_INTSEL3 (*((volatile unsigned int*)(0x42A2140CUL))) +#define bM4_INTC_SEL17_INTSEL4 (*((volatile unsigned int*)(0x42A21410UL))) +#define bM4_INTC_SEL17_INTSEL5 (*((volatile unsigned int*)(0x42A21414UL))) +#define bM4_INTC_SEL17_INTSEL6 (*((volatile unsigned int*)(0x42A21418UL))) +#define bM4_INTC_SEL17_INTSEL7 (*((volatile unsigned int*)(0x42A2141CUL))) +#define bM4_INTC_SEL17_INTSEL8 (*((volatile unsigned int*)(0x42A21420UL))) +#define bM4_INTC_SEL18_INTSEL0 (*((volatile unsigned int*)(0x42A21480UL))) +#define bM4_INTC_SEL18_INTSEL1 (*((volatile unsigned int*)(0x42A21484UL))) +#define bM4_INTC_SEL18_INTSEL2 (*((volatile unsigned int*)(0x42A21488UL))) +#define bM4_INTC_SEL18_INTSEL3 (*((volatile unsigned int*)(0x42A2148CUL))) +#define bM4_INTC_SEL18_INTSEL4 (*((volatile unsigned int*)(0x42A21490UL))) +#define bM4_INTC_SEL18_INTSEL5 (*((volatile unsigned int*)(0x42A21494UL))) +#define bM4_INTC_SEL18_INTSEL6 (*((volatile unsigned int*)(0x42A21498UL))) +#define bM4_INTC_SEL18_INTSEL7 (*((volatile unsigned int*)(0x42A2149CUL))) +#define bM4_INTC_SEL18_INTSEL8 (*((volatile unsigned int*)(0x42A214A0UL))) +#define bM4_INTC_SEL19_INTSEL0 (*((volatile unsigned int*)(0x42A21500UL))) +#define bM4_INTC_SEL19_INTSEL1 (*((volatile unsigned int*)(0x42A21504UL))) +#define bM4_INTC_SEL19_INTSEL2 (*((volatile unsigned int*)(0x42A21508UL))) +#define bM4_INTC_SEL19_INTSEL3 (*((volatile unsigned int*)(0x42A2150CUL))) +#define bM4_INTC_SEL19_INTSEL4 (*((volatile unsigned int*)(0x42A21510UL))) +#define bM4_INTC_SEL19_INTSEL5 (*((volatile unsigned int*)(0x42A21514UL))) +#define bM4_INTC_SEL19_INTSEL6 (*((volatile unsigned int*)(0x42A21518UL))) +#define bM4_INTC_SEL19_INTSEL7 (*((volatile unsigned int*)(0x42A2151CUL))) +#define bM4_INTC_SEL19_INTSEL8 (*((volatile unsigned int*)(0x42A21520UL))) +#define bM4_INTC_SEL20_INTSEL0 (*((volatile unsigned int*)(0x42A21580UL))) +#define bM4_INTC_SEL20_INTSEL1 (*((volatile unsigned int*)(0x42A21584UL))) +#define bM4_INTC_SEL20_INTSEL2 (*((volatile unsigned int*)(0x42A21588UL))) +#define bM4_INTC_SEL20_INTSEL3 (*((volatile unsigned int*)(0x42A2158CUL))) +#define bM4_INTC_SEL20_INTSEL4 (*((volatile unsigned int*)(0x42A21590UL))) +#define bM4_INTC_SEL20_INTSEL5 (*((volatile unsigned int*)(0x42A21594UL))) +#define bM4_INTC_SEL20_INTSEL6 (*((volatile unsigned int*)(0x42A21598UL))) +#define bM4_INTC_SEL20_INTSEL7 (*((volatile unsigned int*)(0x42A2159CUL))) +#define bM4_INTC_SEL20_INTSEL8 (*((volatile unsigned int*)(0x42A215A0UL))) +#define bM4_INTC_SEL21_INTSEL0 (*((volatile unsigned int*)(0x42A21600UL))) +#define bM4_INTC_SEL21_INTSEL1 (*((volatile unsigned int*)(0x42A21604UL))) +#define bM4_INTC_SEL21_INTSEL2 (*((volatile unsigned int*)(0x42A21608UL))) +#define bM4_INTC_SEL21_INTSEL3 (*((volatile unsigned int*)(0x42A2160CUL))) +#define bM4_INTC_SEL21_INTSEL4 (*((volatile unsigned int*)(0x42A21610UL))) +#define bM4_INTC_SEL21_INTSEL5 (*((volatile unsigned int*)(0x42A21614UL))) +#define bM4_INTC_SEL21_INTSEL6 (*((volatile unsigned int*)(0x42A21618UL))) +#define bM4_INTC_SEL21_INTSEL7 (*((volatile unsigned int*)(0x42A2161CUL))) +#define bM4_INTC_SEL21_INTSEL8 (*((volatile unsigned int*)(0x42A21620UL))) +#define bM4_INTC_SEL22_INTSEL0 (*((volatile unsigned int*)(0x42A21680UL))) +#define bM4_INTC_SEL22_INTSEL1 (*((volatile unsigned int*)(0x42A21684UL))) +#define bM4_INTC_SEL22_INTSEL2 (*((volatile unsigned int*)(0x42A21688UL))) +#define bM4_INTC_SEL22_INTSEL3 (*((volatile unsigned int*)(0x42A2168CUL))) +#define bM4_INTC_SEL22_INTSEL4 (*((volatile unsigned int*)(0x42A21690UL))) +#define bM4_INTC_SEL22_INTSEL5 (*((volatile unsigned int*)(0x42A21694UL))) +#define bM4_INTC_SEL22_INTSEL6 (*((volatile unsigned int*)(0x42A21698UL))) +#define bM4_INTC_SEL22_INTSEL7 (*((volatile unsigned int*)(0x42A2169CUL))) +#define bM4_INTC_SEL22_INTSEL8 (*((volatile unsigned int*)(0x42A216A0UL))) +#define bM4_INTC_SEL23_INTSEL0 (*((volatile unsigned int*)(0x42A21700UL))) +#define bM4_INTC_SEL23_INTSEL1 (*((volatile unsigned int*)(0x42A21704UL))) +#define bM4_INTC_SEL23_INTSEL2 (*((volatile unsigned int*)(0x42A21708UL))) +#define bM4_INTC_SEL23_INTSEL3 (*((volatile unsigned int*)(0x42A2170CUL))) +#define bM4_INTC_SEL23_INTSEL4 (*((volatile unsigned int*)(0x42A21710UL))) +#define bM4_INTC_SEL23_INTSEL5 (*((volatile unsigned int*)(0x42A21714UL))) +#define bM4_INTC_SEL23_INTSEL6 (*((volatile unsigned int*)(0x42A21718UL))) +#define bM4_INTC_SEL23_INTSEL7 (*((volatile unsigned int*)(0x42A2171CUL))) +#define bM4_INTC_SEL23_INTSEL8 (*((volatile unsigned int*)(0x42A21720UL))) +#define bM4_INTC_SEL24_INTSEL0 (*((volatile unsigned int*)(0x42A21780UL))) +#define bM4_INTC_SEL24_INTSEL1 (*((volatile unsigned int*)(0x42A21784UL))) +#define bM4_INTC_SEL24_INTSEL2 (*((volatile unsigned int*)(0x42A21788UL))) +#define bM4_INTC_SEL24_INTSEL3 (*((volatile unsigned int*)(0x42A2178CUL))) +#define bM4_INTC_SEL24_INTSEL4 (*((volatile unsigned int*)(0x42A21790UL))) +#define bM4_INTC_SEL24_INTSEL5 (*((volatile unsigned int*)(0x42A21794UL))) +#define bM4_INTC_SEL24_INTSEL6 (*((volatile unsigned int*)(0x42A21798UL))) +#define bM4_INTC_SEL24_INTSEL7 (*((volatile unsigned int*)(0x42A2179CUL))) +#define bM4_INTC_SEL24_INTSEL8 (*((volatile unsigned int*)(0x42A217A0UL))) +#define bM4_INTC_SEL25_INTSEL0 (*((volatile unsigned int*)(0x42A21800UL))) +#define bM4_INTC_SEL25_INTSEL1 (*((volatile unsigned int*)(0x42A21804UL))) +#define bM4_INTC_SEL25_INTSEL2 (*((volatile unsigned int*)(0x42A21808UL))) +#define bM4_INTC_SEL25_INTSEL3 (*((volatile unsigned int*)(0x42A2180CUL))) +#define bM4_INTC_SEL25_INTSEL4 (*((volatile unsigned int*)(0x42A21810UL))) +#define bM4_INTC_SEL25_INTSEL5 (*((volatile unsigned int*)(0x42A21814UL))) +#define bM4_INTC_SEL25_INTSEL6 (*((volatile unsigned int*)(0x42A21818UL))) +#define bM4_INTC_SEL25_INTSEL7 (*((volatile unsigned int*)(0x42A2181CUL))) +#define bM4_INTC_SEL25_INTSEL8 (*((volatile unsigned int*)(0x42A21820UL))) +#define bM4_INTC_SEL26_INTSEL0 (*((volatile unsigned int*)(0x42A21880UL))) +#define bM4_INTC_SEL26_INTSEL1 (*((volatile unsigned int*)(0x42A21884UL))) +#define bM4_INTC_SEL26_INTSEL2 (*((volatile unsigned int*)(0x42A21888UL))) +#define bM4_INTC_SEL26_INTSEL3 (*((volatile unsigned int*)(0x42A2188CUL))) +#define bM4_INTC_SEL26_INTSEL4 (*((volatile unsigned int*)(0x42A21890UL))) +#define bM4_INTC_SEL26_INTSEL5 (*((volatile unsigned int*)(0x42A21894UL))) +#define bM4_INTC_SEL26_INTSEL6 (*((volatile unsigned int*)(0x42A21898UL))) +#define bM4_INTC_SEL26_INTSEL7 (*((volatile unsigned int*)(0x42A2189CUL))) +#define bM4_INTC_SEL26_INTSEL8 (*((volatile unsigned int*)(0x42A218A0UL))) +#define bM4_INTC_SEL27_INTSEL0 (*((volatile unsigned int*)(0x42A21900UL))) +#define bM4_INTC_SEL27_INTSEL1 (*((volatile unsigned int*)(0x42A21904UL))) +#define bM4_INTC_SEL27_INTSEL2 (*((volatile unsigned int*)(0x42A21908UL))) +#define bM4_INTC_SEL27_INTSEL3 (*((volatile unsigned int*)(0x42A2190CUL))) +#define bM4_INTC_SEL27_INTSEL4 (*((volatile unsigned int*)(0x42A21910UL))) +#define bM4_INTC_SEL27_INTSEL5 (*((volatile unsigned int*)(0x42A21914UL))) +#define bM4_INTC_SEL27_INTSEL6 (*((volatile unsigned int*)(0x42A21918UL))) +#define bM4_INTC_SEL27_INTSEL7 (*((volatile unsigned int*)(0x42A2191CUL))) +#define bM4_INTC_SEL27_INTSEL8 (*((volatile unsigned int*)(0x42A21920UL))) +#define bM4_INTC_SEL28_INTSEL0 (*((volatile unsigned int*)(0x42A21980UL))) +#define bM4_INTC_SEL28_INTSEL1 (*((volatile unsigned int*)(0x42A21984UL))) +#define bM4_INTC_SEL28_INTSEL2 (*((volatile unsigned int*)(0x42A21988UL))) +#define bM4_INTC_SEL28_INTSEL3 (*((volatile unsigned int*)(0x42A2198CUL))) +#define bM4_INTC_SEL28_INTSEL4 (*((volatile unsigned int*)(0x42A21990UL))) +#define bM4_INTC_SEL28_INTSEL5 (*((volatile unsigned int*)(0x42A21994UL))) +#define bM4_INTC_SEL28_INTSEL6 (*((volatile unsigned int*)(0x42A21998UL))) +#define bM4_INTC_SEL28_INTSEL7 (*((volatile unsigned int*)(0x42A2199CUL))) +#define bM4_INTC_SEL28_INTSEL8 (*((volatile unsigned int*)(0x42A219A0UL))) +#define bM4_INTC_SEL29_INTSEL0 (*((volatile unsigned int*)(0x42A21A00UL))) +#define bM4_INTC_SEL29_INTSEL1 (*((volatile unsigned int*)(0x42A21A04UL))) +#define bM4_INTC_SEL29_INTSEL2 (*((volatile unsigned int*)(0x42A21A08UL))) +#define bM4_INTC_SEL29_INTSEL3 (*((volatile unsigned int*)(0x42A21A0CUL))) +#define bM4_INTC_SEL29_INTSEL4 (*((volatile unsigned int*)(0x42A21A10UL))) +#define bM4_INTC_SEL29_INTSEL5 (*((volatile unsigned int*)(0x42A21A14UL))) +#define bM4_INTC_SEL29_INTSEL6 (*((volatile unsigned int*)(0x42A21A18UL))) +#define bM4_INTC_SEL29_INTSEL7 (*((volatile unsigned int*)(0x42A21A1CUL))) +#define bM4_INTC_SEL29_INTSEL8 (*((volatile unsigned int*)(0x42A21A20UL))) +#define bM4_INTC_SEL30_INTSEL0 (*((volatile unsigned int*)(0x42A21A80UL))) +#define bM4_INTC_SEL30_INTSEL1 (*((volatile unsigned int*)(0x42A21A84UL))) +#define bM4_INTC_SEL30_INTSEL2 (*((volatile unsigned int*)(0x42A21A88UL))) +#define bM4_INTC_SEL30_INTSEL3 (*((volatile unsigned int*)(0x42A21A8CUL))) +#define bM4_INTC_SEL30_INTSEL4 (*((volatile unsigned int*)(0x42A21A90UL))) +#define bM4_INTC_SEL30_INTSEL5 (*((volatile unsigned int*)(0x42A21A94UL))) +#define bM4_INTC_SEL30_INTSEL6 (*((volatile unsigned int*)(0x42A21A98UL))) +#define bM4_INTC_SEL30_INTSEL7 (*((volatile unsigned int*)(0x42A21A9CUL))) +#define bM4_INTC_SEL30_INTSEL8 (*((volatile unsigned int*)(0x42A21AA0UL))) +#define bM4_INTC_SEL31_INTSEL0 (*((volatile unsigned int*)(0x42A21B00UL))) +#define bM4_INTC_SEL31_INTSEL1 (*((volatile unsigned int*)(0x42A21B04UL))) +#define bM4_INTC_SEL31_INTSEL2 (*((volatile unsigned int*)(0x42A21B08UL))) +#define bM4_INTC_SEL31_INTSEL3 (*((volatile unsigned int*)(0x42A21B0CUL))) +#define bM4_INTC_SEL31_INTSEL4 (*((volatile unsigned int*)(0x42A21B10UL))) +#define bM4_INTC_SEL31_INTSEL5 (*((volatile unsigned int*)(0x42A21B14UL))) +#define bM4_INTC_SEL31_INTSEL6 (*((volatile unsigned int*)(0x42A21B18UL))) +#define bM4_INTC_SEL31_INTSEL7 (*((volatile unsigned int*)(0x42A21B1CUL))) +#define bM4_INTC_SEL31_INTSEL8 (*((volatile unsigned int*)(0x42A21B20UL))) +#define bM4_INTC_SEL32_INTSEL0 (*((volatile unsigned int*)(0x42A21B80UL))) +#define bM4_INTC_SEL32_INTSEL1 (*((volatile unsigned int*)(0x42A21B84UL))) +#define bM4_INTC_SEL32_INTSEL2 (*((volatile unsigned int*)(0x42A21B88UL))) +#define bM4_INTC_SEL32_INTSEL3 (*((volatile unsigned int*)(0x42A21B8CUL))) +#define bM4_INTC_SEL32_INTSEL4 (*((volatile unsigned int*)(0x42A21B90UL))) +#define bM4_INTC_SEL32_INTSEL5 (*((volatile unsigned int*)(0x42A21B94UL))) +#define bM4_INTC_SEL32_INTSEL6 (*((volatile unsigned int*)(0x42A21B98UL))) +#define bM4_INTC_SEL32_INTSEL7 (*((volatile unsigned int*)(0x42A21B9CUL))) +#define bM4_INTC_SEL32_INTSEL8 (*((volatile unsigned int*)(0x42A21BA0UL))) +#define bM4_INTC_SEL33_INTSEL0 (*((volatile unsigned int*)(0x42A21C00UL))) +#define bM4_INTC_SEL33_INTSEL1 (*((volatile unsigned int*)(0x42A21C04UL))) +#define bM4_INTC_SEL33_INTSEL2 (*((volatile unsigned int*)(0x42A21C08UL))) +#define bM4_INTC_SEL33_INTSEL3 (*((volatile unsigned int*)(0x42A21C0CUL))) +#define bM4_INTC_SEL33_INTSEL4 (*((volatile unsigned int*)(0x42A21C10UL))) +#define bM4_INTC_SEL33_INTSEL5 (*((volatile unsigned int*)(0x42A21C14UL))) +#define bM4_INTC_SEL33_INTSEL6 (*((volatile unsigned int*)(0x42A21C18UL))) +#define bM4_INTC_SEL33_INTSEL7 (*((volatile unsigned int*)(0x42A21C1CUL))) +#define bM4_INTC_SEL33_INTSEL8 (*((volatile unsigned int*)(0x42A21C20UL))) +#define bM4_INTC_SEL34_INTSEL0 (*((volatile unsigned int*)(0x42A21C80UL))) +#define bM4_INTC_SEL34_INTSEL1 (*((volatile unsigned int*)(0x42A21C84UL))) +#define bM4_INTC_SEL34_INTSEL2 (*((volatile unsigned int*)(0x42A21C88UL))) +#define bM4_INTC_SEL34_INTSEL3 (*((volatile unsigned int*)(0x42A21C8CUL))) +#define bM4_INTC_SEL34_INTSEL4 (*((volatile unsigned int*)(0x42A21C90UL))) +#define bM4_INTC_SEL34_INTSEL5 (*((volatile unsigned int*)(0x42A21C94UL))) +#define bM4_INTC_SEL34_INTSEL6 (*((volatile unsigned int*)(0x42A21C98UL))) +#define bM4_INTC_SEL34_INTSEL7 (*((volatile unsigned int*)(0x42A21C9CUL))) +#define bM4_INTC_SEL34_INTSEL8 (*((volatile unsigned int*)(0x42A21CA0UL))) +#define bM4_INTC_SEL35_INTSEL0 (*((volatile unsigned int*)(0x42A21D00UL))) +#define bM4_INTC_SEL35_INTSEL1 (*((volatile unsigned int*)(0x42A21D04UL))) +#define bM4_INTC_SEL35_INTSEL2 (*((volatile unsigned int*)(0x42A21D08UL))) +#define bM4_INTC_SEL35_INTSEL3 (*((volatile unsigned int*)(0x42A21D0CUL))) +#define bM4_INTC_SEL35_INTSEL4 (*((volatile unsigned int*)(0x42A21D10UL))) +#define bM4_INTC_SEL35_INTSEL5 (*((volatile unsigned int*)(0x42A21D14UL))) +#define bM4_INTC_SEL35_INTSEL6 (*((volatile unsigned int*)(0x42A21D18UL))) +#define bM4_INTC_SEL35_INTSEL7 (*((volatile unsigned int*)(0x42A21D1CUL))) +#define bM4_INTC_SEL35_INTSEL8 (*((volatile unsigned int*)(0x42A21D20UL))) +#define bM4_INTC_SEL36_INTSEL0 (*((volatile unsigned int*)(0x42A21D80UL))) +#define bM4_INTC_SEL36_INTSEL1 (*((volatile unsigned int*)(0x42A21D84UL))) +#define bM4_INTC_SEL36_INTSEL2 (*((volatile unsigned int*)(0x42A21D88UL))) +#define bM4_INTC_SEL36_INTSEL3 (*((volatile unsigned int*)(0x42A21D8CUL))) +#define bM4_INTC_SEL36_INTSEL4 (*((volatile unsigned int*)(0x42A21D90UL))) +#define bM4_INTC_SEL36_INTSEL5 (*((volatile unsigned int*)(0x42A21D94UL))) +#define bM4_INTC_SEL36_INTSEL6 (*((volatile unsigned int*)(0x42A21D98UL))) +#define bM4_INTC_SEL36_INTSEL7 (*((volatile unsigned int*)(0x42A21D9CUL))) +#define bM4_INTC_SEL36_INTSEL8 (*((volatile unsigned int*)(0x42A21DA0UL))) +#define bM4_INTC_SEL37_INTSEL0 (*((volatile unsigned int*)(0x42A21E00UL))) +#define bM4_INTC_SEL37_INTSEL1 (*((volatile unsigned int*)(0x42A21E04UL))) +#define bM4_INTC_SEL37_INTSEL2 (*((volatile unsigned int*)(0x42A21E08UL))) +#define bM4_INTC_SEL37_INTSEL3 (*((volatile unsigned int*)(0x42A21E0CUL))) +#define bM4_INTC_SEL37_INTSEL4 (*((volatile unsigned int*)(0x42A21E10UL))) +#define bM4_INTC_SEL37_INTSEL5 (*((volatile unsigned int*)(0x42A21E14UL))) +#define bM4_INTC_SEL37_INTSEL6 (*((volatile unsigned int*)(0x42A21E18UL))) +#define bM4_INTC_SEL37_INTSEL7 (*((volatile unsigned int*)(0x42A21E1CUL))) +#define bM4_INTC_SEL37_INTSEL8 (*((volatile unsigned int*)(0x42A21E20UL))) +#define bM4_INTC_SEL38_INTSEL0 (*((volatile unsigned int*)(0x42A21E80UL))) +#define bM4_INTC_SEL38_INTSEL1 (*((volatile unsigned int*)(0x42A21E84UL))) +#define bM4_INTC_SEL38_INTSEL2 (*((volatile unsigned int*)(0x42A21E88UL))) +#define bM4_INTC_SEL38_INTSEL3 (*((volatile unsigned int*)(0x42A21E8CUL))) +#define bM4_INTC_SEL38_INTSEL4 (*((volatile unsigned int*)(0x42A21E90UL))) +#define bM4_INTC_SEL38_INTSEL5 (*((volatile unsigned int*)(0x42A21E94UL))) +#define bM4_INTC_SEL38_INTSEL6 (*((volatile unsigned int*)(0x42A21E98UL))) +#define bM4_INTC_SEL38_INTSEL7 (*((volatile unsigned int*)(0x42A21E9CUL))) +#define bM4_INTC_SEL38_INTSEL8 (*((volatile unsigned int*)(0x42A21EA0UL))) +#define bM4_INTC_SEL39_INTSEL0 (*((volatile unsigned int*)(0x42A21F00UL))) +#define bM4_INTC_SEL39_INTSEL1 (*((volatile unsigned int*)(0x42A21F04UL))) +#define bM4_INTC_SEL39_INTSEL2 (*((volatile unsigned int*)(0x42A21F08UL))) +#define bM4_INTC_SEL39_INTSEL3 (*((volatile unsigned int*)(0x42A21F0CUL))) +#define bM4_INTC_SEL39_INTSEL4 (*((volatile unsigned int*)(0x42A21F10UL))) +#define bM4_INTC_SEL39_INTSEL5 (*((volatile unsigned int*)(0x42A21F14UL))) +#define bM4_INTC_SEL39_INTSEL6 (*((volatile unsigned int*)(0x42A21F18UL))) +#define bM4_INTC_SEL39_INTSEL7 (*((volatile unsigned int*)(0x42A21F1CUL))) +#define bM4_INTC_SEL39_INTSEL8 (*((volatile unsigned int*)(0x42A21F20UL))) +#define bM4_INTC_SEL40_INTSEL0 (*((volatile unsigned int*)(0x42A21F80UL))) +#define bM4_INTC_SEL40_INTSEL1 (*((volatile unsigned int*)(0x42A21F84UL))) +#define bM4_INTC_SEL40_INTSEL2 (*((volatile unsigned int*)(0x42A21F88UL))) +#define bM4_INTC_SEL40_INTSEL3 (*((volatile unsigned int*)(0x42A21F8CUL))) +#define bM4_INTC_SEL40_INTSEL4 (*((volatile unsigned int*)(0x42A21F90UL))) +#define bM4_INTC_SEL40_INTSEL5 (*((volatile unsigned int*)(0x42A21F94UL))) +#define bM4_INTC_SEL40_INTSEL6 (*((volatile unsigned int*)(0x42A21F98UL))) +#define bM4_INTC_SEL40_INTSEL7 (*((volatile unsigned int*)(0x42A21F9CUL))) +#define bM4_INTC_SEL40_INTSEL8 (*((volatile unsigned int*)(0x42A21FA0UL))) +#define bM4_INTC_SEL41_INTSEL0 (*((volatile unsigned int*)(0x42A22000UL))) +#define bM4_INTC_SEL41_INTSEL1 (*((volatile unsigned int*)(0x42A22004UL))) +#define bM4_INTC_SEL41_INTSEL2 (*((volatile unsigned int*)(0x42A22008UL))) +#define bM4_INTC_SEL41_INTSEL3 (*((volatile unsigned int*)(0x42A2200CUL))) +#define bM4_INTC_SEL41_INTSEL4 (*((volatile unsigned int*)(0x42A22010UL))) +#define bM4_INTC_SEL41_INTSEL5 (*((volatile unsigned int*)(0x42A22014UL))) +#define bM4_INTC_SEL41_INTSEL6 (*((volatile unsigned int*)(0x42A22018UL))) +#define bM4_INTC_SEL41_INTSEL7 (*((volatile unsigned int*)(0x42A2201CUL))) +#define bM4_INTC_SEL41_INTSEL8 (*((volatile unsigned int*)(0x42A22020UL))) +#define bM4_INTC_SEL42_INTSEL0 (*((volatile unsigned int*)(0x42A22080UL))) +#define bM4_INTC_SEL42_INTSEL1 (*((volatile unsigned int*)(0x42A22084UL))) +#define bM4_INTC_SEL42_INTSEL2 (*((volatile unsigned int*)(0x42A22088UL))) +#define bM4_INTC_SEL42_INTSEL3 (*((volatile unsigned int*)(0x42A2208CUL))) +#define bM4_INTC_SEL42_INTSEL4 (*((volatile unsigned int*)(0x42A22090UL))) +#define bM4_INTC_SEL42_INTSEL5 (*((volatile unsigned int*)(0x42A22094UL))) +#define bM4_INTC_SEL42_INTSEL6 (*((volatile unsigned int*)(0x42A22098UL))) +#define bM4_INTC_SEL42_INTSEL7 (*((volatile unsigned int*)(0x42A2209CUL))) +#define bM4_INTC_SEL42_INTSEL8 (*((volatile unsigned int*)(0x42A220A0UL))) +#define bM4_INTC_SEL43_INTSEL0 (*((volatile unsigned int*)(0x42A22100UL))) +#define bM4_INTC_SEL43_INTSEL1 (*((volatile unsigned int*)(0x42A22104UL))) +#define bM4_INTC_SEL43_INTSEL2 (*((volatile unsigned int*)(0x42A22108UL))) +#define bM4_INTC_SEL43_INTSEL3 (*((volatile unsigned int*)(0x42A2210CUL))) +#define bM4_INTC_SEL43_INTSEL4 (*((volatile unsigned int*)(0x42A22110UL))) +#define bM4_INTC_SEL43_INTSEL5 (*((volatile unsigned int*)(0x42A22114UL))) +#define bM4_INTC_SEL43_INTSEL6 (*((volatile unsigned int*)(0x42A22118UL))) +#define bM4_INTC_SEL43_INTSEL7 (*((volatile unsigned int*)(0x42A2211CUL))) +#define bM4_INTC_SEL43_INTSEL8 (*((volatile unsigned int*)(0x42A22120UL))) +#define bM4_INTC_SEL44_INTSEL0 (*((volatile unsigned int*)(0x42A22180UL))) +#define bM4_INTC_SEL44_INTSEL1 (*((volatile unsigned int*)(0x42A22184UL))) +#define bM4_INTC_SEL44_INTSEL2 (*((volatile unsigned int*)(0x42A22188UL))) +#define bM4_INTC_SEL44_INTSEL3 (*((volatile unsigned int*)(0x42A2218CUL))) +#define bM4_INTC_SEL44_INTSEL4 (*((volatile unsigned int*)(0x42A22190UL))) +#define bM4_INTC_SEL44_INTSEL5 (*((volatile unsigned int*)(0x42A22194UL))) +#define bM4_INTC_SEL44_INTSEL6 (*((volatile unsigned int*)(0x42A22198UL))) +#define bM4_INTC_SEL44_INTSEL7 (*((volatile unsigned int*)(0x42A2219CUL))) +#define bM4_INTC_SEL44_INTSEL8 (*((volatile unsigned int*)(0x42A221A0UL))) +#define bM4_INTC_SEL45_INTSEL0 (*((volatile unsigned int*)(0x42A22200UL))) +#define bM4_INTC_SEL45_INTSEL1 (*((volatile unsigned int*)(0x42A22204UL))) +#define bM4_INTC_SEL45_INTSEL2 (*((volatile unsigned int*)(0x42A22208UL))) +#define bM4_INTC_SEL45_INTSEL3 (*((volatile unsigned int*)(0x42A2220CUL))) +#define bM4_INTC_SEL45_INTSEL4 (*((volatile unsigned int*)(0x42A22210UL))) +#define bM4_INTC_SEL45_INTSEL5 (*((volatile unsigned int*)(0x42A22214UL))) +#define bM4_INTC_SEL45_INTSEL6 (*((volatile unsigned int*)(0x42A22218UL))) +#define bM4_INTC_SEL45_INTSEL7 (*((volatile unsigned int*)(0x42A2221CUL))) +#define bM4_INTC_SEL45_INTSEL8 (*((volatile unsigned int*)(0x42A22220UL))) +#define bM4_INTC_SEL46_INTSEL0 (*((volatile unsigned int*)(0x42A22280UL))) +#define bM4_INTC_SEL46_INTSEL1 (*((volatile unsigned int*)(0x42A22284UL))) +#define bM4_INTC_SEL46_INTSEL2 (*((volatile unsigned int*)(0x42A22288UL))) +#define bM4_INTC_SEL46_INTSEL3 (*((volatile unsigned int*)(0x42A2228CUL))) +#define bM4_INTC_SEL46_INTSEL4 (*((volatile unsigned int*)(0x42A22290UL))) +#define bM4_INTC_SEL46_INTSEL5 (*((volatile unsigned int*)(0x42A22294UL))) +#define bM4_INTC_SEL46_INTSEL6 (*((volatile unsigned int*)(0x42A22298UL))) +#define bM4_INTC_SEL46_INTSEL7 (*((volatile unsigned int*)(0x42A2229CUL))) +#define bM4_INTC_SEL46_INTSEL8 (*((volatile unsigned int*)(0x42A222A0UL))) +#define bM4_INTC_SEL47_INTSEL0 (*((volatile unsigned int*)(0x42A22300UL))) +#define bM4_INTC_SEL47_INTSEL1 (*((volatile unsigned int*)(0x42A22304UL))) +#define bM4_INTC_SEL47_INTSEL2 (*((volatile unsigned int*)(0x42A22308UL))) +#define bM4_INTC_SEL47_INTSEL3 (*((volatile unsigned int*)(0x42A2230CUL))) +#define bM4_INTC_SEL47_INTSEL4 (*((volatile unsigned int*)(0x42A22310UL))) +#define bM4_INTC_SEL47_INTSEL5 (*((volatile unsigned int*)(0x42A22314UL))) +#define bM4_INTC_SEL47_INTSEL6 (*((volatile unsigned int*)(0x42A22318UL))) +#define bM4_INTC_SEL47_INTSEL7 (*((volatile unsigned int*)(0x42A2231CUL))) +#define bM4_INTC_SEL47_INTSEL8 (*((volatile unsigned int*)(0x42A22320UL))) +#define bM4_INTC_SEL48_INTSEL0 (*((volatile unsigned int*)(0x42A22380UL))) +#define bM4_INTC_SEL48_INTSEL1 (*((volatile unsigned int*)(0x42A22384UL))) +#define bM4_INTC_SEL48_INTSEL2 (*((volatile unsigned int*)(0x42A22388UL))) +#define bM4_INTC_SEL48_INTSEL3 (*((volatile unsigned int*)(0x42A2238CUL))) +#define bM4_INTC_SEL48_INTSEL4 (*((volatile unsigned int*)(0x42A22390UL))) +#define bM4_INTC_SEL48_INTSEL5 (*((volatile unsigned int*)(0x42A22394UL))) +#define bM4_INTC_SEL48_INTSEL6 (*((volatile unsigned int*)(0x42A22398UL))) +#define bM4_INTC_SEL48_INTSEL7 (*((volatile unsigned int*)(0x42A2239CUL))) +#define bM4_INTC_SEL48_INTSEL8 (*((volatile unsigned int*)(0x42A223A0UL))) +#define bM4_INTC_SEL49_INTSEL0 (*((volatile unsigned int*)(0x42A22400UL))) +#define bM4_INTC_SEL49_INTSEL1 (*((volatile unsigned int*)(0x42A22404UL))) +#define bM4_INTC_SEL49_INTSEL2 (*((volatile unsigned int*)(0x42A22408UL))) +#define bM4_INTC_SEL49_INTSEL3 (*((volatile unsigned int*)(0x42A2240CUL))) +#define bM4_INTC_SEL49_INTSEL4 (*((volatile unsigned int*)(0x42A22410UL))) +#define bM4_INTC_SEL49_INTSEL5 (*((volatile unsigned int*)(0x42A22414UL))) +#define bM4_INTC_SEL49_INTSEL6 (*((volatile unsigned int*)(0x42A22418UL))) +#define bM4_INTC_SEL49_INTSEL7 (*((volatile unsigned int*)(0x42A2241CUL))) +#define bM4_INTC_SEL49_INTSEL8 (*((volatile unsigned int*)(0x42A22420UL))) +#define bM4_INTC_SEL50_INTSEL0 (*((volatile unsigned int*)(0x42A22480UL))) +#define bM4_INTC_SEL50_INTSEL1 (*((volatile unsigned int*)(0x42A22484UL))) +#define bM4_INTC_SEL50_INTSEL2 (*((volatile unsigned int*)(0x42A22488UL))) +#define bM4_INTC_SEL50_INTSEL3 (*((volatile unsigned int*)(0x42A2248CUL))) +#define bM4_INTC_SEL50_INTSEL4 (*((volatile unsigned int*)(0x42A22490UL))) +#define bM4_INTC_SEL50_INTSEL5 (*((volatile unsigned int*)(0x42A22494UL))) +#define bM4_INTC_SEL50_INTSEL6 (*((volatile unsigned int*)(0x42A22498UL))) +#define bM4_INTC_SEL50_INTSEL7 (*((volatile unsigned int*)(0x42A2249CUL))) +#define bM4_INTC_SEL50_INTSEL8 (*((volatile unsigned int*)(0x42A224A0UL))) +#define bM4_INTC_SEL51_INTSEL0 (*((volatile unsigned int*)(0x42A22500UL))) +#define bM4_INTC_SEL51_INTSEL1 (*((volatile unsigned int*)(0x42A22504UL))) +#define bM4_INTC_SEL51_INTSEL2 (*((volatile unsigned int*)(0x42A22508UL))) +#define bM4_INTC_SEL51_INTSEL3 (*((volatile unsigned int*)(0x42A2250CUL))) +#define bM4_INTC_SEL51_INTSEL4 (*((volatile unsigned int*)(0x42A22510UL))) +#define bM4_INTC_SEL51_INTSEL5 (*((volatile unsigned int*)(0x42A22514UL))) +#define bM4_INTC_SEL51_INTSEL6 (*((volatile unsigned int*)(0x42A22518UL))) +#define bM4_INTC_SEL51_INTSEL7 (*((volatile unsigned int*)(0x42A2251CUL))) +#define bM4_INTC_SEL51_INTSEL8 (*((volatile unsigned int*)(0x42A22520UL))) +#define bM4_INTC_SEL52_INTSEL0 (*((volatile unsigned int*)(0x42A22580UL))) +#define bM4_INTC_SEL52_INTSEL1 (*((volatile unsigned int*)(0x42A22584UL))) +#define bM4_INTC_SEL52_INTSEL2 (*((volatile unsigned int*)(0x42A22588UL))) +#define bM4_INTC_SEL52_INTSEL3 (*((volatile unsigned int*)(0x42A2258CUL))) +#define bM4_INTC_SEL52_INTSEL4 (*((volatile unsigned int*)(0x42A22590UL))) +#define bM4_INTC_SEL52_INTSEL5 (*((volatile unsigned int*)(0x42A22594UL))) +#define bM4_INTC_SEL52_INTSEL6 (*((volatile unsigned int*)(0x42A22598UL))) +#define bM4_INTC_SEL52_INTSEL7 (*((volatile unsigned int*)(0x42A2259CUL))) +#define bM4_INTC_SEL52_INTSEL8 (*((volatile unsigned int*)(0x42A225A0UL))) +#define bM4_INTC_SEL53_INTSEL0 (*((volatile unsigned int*)(0x42A22600UL))) +#define bM4_INTC_SEL53_INTSEL1 (*((volatile unsigned int*)(0x42A22604UL))) +#define bM4_INTC_SEL53_INTSEL2 (*((volatile unsigned int*)(0x42A22608UL))) +#define bM4_INTC_SEL53_INTSEL3 (*((volatile unsigned int*)(0x42A2260CUL))) +#define bM4_INTC_SEL53_INTSEL4 (*((volatile unsigned int*)(0x42A22610UL))) +#define bM4_INTC_SEL53_INTSEL5 (*((volatile unsigned int*)(0x42A22614UL))) +#define bM4_INTC_SEL53_INTSEL6 (*((volatile unsigned int*)(0x42A22618UL))) +#define bM4_INTC_SEL53_INTSEL7 (*((volatile unsigned int*)(0x42A2261CUL))) +#define bM4_INTC_SEL53_INTSEL8 (*((volatile unsigned int*)(0x42A22620UL))) +#define bM4_INTC_SEL54_INTSEL0 (*((volatile unsigned int*)(0x42A22680UL))) +#define bM4_INTC_SEL54_INTSEL1 (*((volatile unsigned int*)(0x42A22684UL))) +#define bM4_INTC_SEL54_INTSEL2 (*((volatile unsigned int*)(0x42A22688UL))) +#define bM4_INTC_SEL54_INTSEL3 (*((volatile unsigned int*)(0x42A2268CUL))) +#define bM4_INTC_SEL54_INTSEL4 (*((volatile unsigned int*)(0x42A22690UL))) +#define bM4_INTC_SEL54_INTSEL5 (*((volatile unsigned int*)(0x42A22694UL))) +#define bM4_INTC_SEL54_INTSEL6 (*((volatile unsigned int*)(0x42A22698UL))) +#define bM4_INTC_SEL54_INTSEL7 (*((volatile unsigned int*)(0x42A2269CUL))) +#define bM4_INTC_SEL54_INTSEL8 (*((volatile unsigned int*)(0x42A226A0UL))) +#define bM4_INTC_SEL55_INTSEL0 (*((volatile unsigned int*)(0x42A22700UL))) +#define bM4_INTC_SEL55_INTSEL1 (*((volatile unsigned int*)(0x42A22704UL))) +#define bM4_INTC_SEL55_INTSEL2 (*((volatile unsigned int*)(0x42A22708UL))) +#define bM4_INTC_SEL55_INTSEL3 (*((volatile unsigned int*)(0x42A2270CUL))) +#define bM4_INTC_SEL55_INTSEL4 (*((volatile unsigned int*)(0x42A22710UL))) +#define bM4_INTC_SEL55_INTSEL5 (*((volatile unsigned int*)(0x42A22714UL))) +#define bM4_INTC_SEL55_INTSEL6 (*((volatile unsigned int*)(0x42A22718UL))) +#define bM4_INTC_SEL55_INTSEL7 (*((volatile unsigned int*)(0x42A2271CUL))) +#define bM4_INTC_SEL55_INTSEL8 (*((volatile unsigned int*)(0x42A22720UL))) +#define bM4_INTC_SEL56_INTSEL0 (*((volatile unsigned int*)(0x42A22780UL))) +#define bM4_INTC_SEL56_INTSEL1 (*((volatile unsigned int*)(0x42A22784UL))) +#define bM4_INTC_SEL56_INTSEL2 (*((volatile unsigned int*)(0x42A22788UL))) +#define bM4_INTC_SEL56_INTSEL3 (*((volatile unsigned int*)(0x42A2278CUL))) +#define bM4_INTC_SEL56_INTSEL4 (*((volatile unsigned int*)(0x42A22790UL))) +#define bM4_INTC_SEL56_INTSEL5 (*((volatile unsigned int*)(0x42A22794UL))) +#define bM4_INTC_SEL56_INTSEL6 (*((volatile unsigned int*)(0x42A22798UL))) +#define bM4_INTC_SEL56_INTSEL7 (*((volatile unsigned int*)(0x42A2279CUL))) +#define bM4_INTC_SEL56_INTSEL8 (*((volatile unsigned int*)(0x42A227A0UL))) +#define bM4_INTC_SEL57_INTSEL0 (*((volatile unsigned int*)(0x42A22800UL))) +#define bM4_INTC_SEL57_INTSEL1 (*((volatile unsigned int*)(0x42A22804UL))) +#define bM4_INTC_SEL57_INTSEL2 (*((volatile unsigned int*)(0x42A22808UL))) +#define bM4_INTC_SEL57_INTSEL3 (*((volatile unsigned int*)(0x42A2280CUL))) +#define bM4_INTC_SEL57_INTSEL4 (*((volatile unsigned int*)(0x42A22810UL))) +#define bM4_INTC_SEL57_INTSEL5 (*((volatile unsigned int*)(0x42A22814UL))) +#define bM4_INTC_SEL57_INTSEL6 (*((volatile unsigned int*)(0x42A22818UL))) +#define bM4_INTC_SEL57_INTSEL7 (*((volatile unsigned int*)(0x42A2281CUL))) +#define bM4_INTC_SEL57_INTSEL8 (*((volatile unsigned int*)(0x42A22820UL))) +#define bM4_INTC_SEL58_INTSEL0 (*((volatile unsigned int*)(0x42A22880UL))) +#define bM4_INTC_SEL58_INTSEL1 (*((volatile unsigned int*)(0x42A22884UL))) +#define bM4_INTC_SEL58_INTSEL2 (*((volatile unsigned int*)(0x42A22888UL))) +#define bM4_INTC_SEL58_INTSEL3 (*((volatile unsigned int*)(0x42A2288CUL))) +#define bM4_INTC_SEL58_INTSEL4 (*((volatile unsigned int*)(0x42A22890UL))) +#define bM4_INTC_SEL58_INTSEL5 (*((volatile unsigned int*)(0x42A22894UL))) +#define bM4_INTC_SEL58_INTSEL6 (*((volatile unsigned int*)(0x42A22898UL))) +#define bM4_INTC_SEL58_INTSEL7 (*((volatile unsigned int*)(0x42A2289CUL))) +#define bM4_INTC_SEL58_INTSEL8 (*((volatile unsigned int*)(0x42A228A0UL))) +#define bM4_INTC_SEL59_INTSEL0 (*((volatile unsigned int*)(0x42A22900UL))) +#define bM4_INTC_SEL59_INTSEL1 (*((volatile unsigned int*)(0x42A22904UL))) +#define bM4_INTC_SEL59_INTSEL2 (*((volatile unsigned int*)(0x42A22908UL))) +#define bM4_INTC_SEL59_INTSEL3 (*((volatile unsigned int*)(0x42A2290CUL))) +#define bM4_INTC_SEL59_INTSEL4 (*((volatile unsigned int*)(0x42A22910UL))) +#define bM4_INTC_SEL59_INTSEL5 (*((volatile unsigned int*)(0x42A22914UL))) +#define bM4_INTC_SEL59_INTSEL6 (*((volatile unsigned int*)(0x42A22918UL))) +#define bM4_INTC_SEL59_INTSEL7 (*((volatile unsigned int*)(0x42A2291CUL))) +#define bM4_INTC_SEL59_INTSEL8 (*((volatile unsigned int*)(0x42A22920UL))) +#define bM4_INTC_SEL60_INTSEL0 (*((volatile unsigned int*)(0x42A22980UL))) +#define bM4_INTC_SEL60_INTSEL1 (*((volatile unsigned int*)(0x42A22984UL))) +#define bM4_INTC_SEL60_INTSEL2 (*((volatile unsigned int*)(0x42A22988UL))) +#define bM4_INTC_SEL60_INTSEL3 (*((volatile unsigned int*)(0x42A2298CUL))) +#define bM4_INTC_SEL60_INTSEL4 (*((volatile unsigned int*)(0x42A22990UL))) +#define bM4_INTC_SEL60_INTSEL5 (*((volatile unsigned int*)(0x42A22994UL))) +#define bM4_INTC_SEL60_INTSEL6 (*((volatile unsigned int*)(0x42A22998UL))) +#define bM4_INTC_SEL60_INTSEL7 (*((volatile unsigned int*)(0x42A2299CUL))) +#define bM4_INTC_SEL60_INTSEL8 (*((volatile unsigned int*)(0x42A229A0UL))) +#define bM4_INTC_SEL61_INTSEL0 (*((volatile unsigned int*)(0x42A22A00UL))) +#define bM4_INTC_SEL61_INTSEL1 (*((volatile unsigned int*)(0x42A22A04UL))) +#define bM4_INTC_SEL61_INTSEL2 (*((volatile unsigned int*)(0x42A22A08UL))) +#define bM4_INTC_SEL61_INTSEL3 (*((volatile unsigned int*)(0x42A22A0CUL))) +#define bM4_INTC_SEL61_INTSEL4 (*((volatile unsigned int*)(0x42A22A10UL))) +#define bM4_INTC_SEL61_INTSEL5 (*((volatile unsigned int*)(0x42A22A14UL))) +#define bM4_INTC_SEL61_INTSEL6 (*((volatile unsigned int*)(0x42A22A18UL))) +#define bM4_INTC_SEL61_INTSEL7 (*((volatile unsigned int*)(0x42A22A1CUL))) +#define bM4_INTC_SEL61_INTSEL8 (*((volatile unsigned int*)(0x42A22A20UL))) +#define bM4_INTC_SEL62_INTSEL0 (*((volatile unsigned int*)(0x42A22A80UL))) +#define bM4_INTC_SEL62_INTSEL1 (*((volatile unsigned int*)(0x42A22A84UL))) +#define bM4_INTC_SEL62_INTSEL2 (*((volatile unsigned int*)(0x42A22A88UL))) +#define bM4_INTC_SEL62_INTSEL3 (*((volatile unsigned int*)(0x42A22A8CUL))) +#define bM4_INTC_SEL62_INTSEL4 (*((volatile unsigned int*)(0x42A22A90UL))) +#define bM4_INTC_SEL62_INTSEL5 (*((volatile unsigned int*)(0x42A22A94UL))) +#define bM4_INTC_SEL62_INTSEL6 (*((volatile unsigned int*)(0x42A22A98UL))) +#define bM4_INTC_SEL62_INTSEL7 (*((volatile unsigned int*)(0x42A22A9CUL))) +#define bM4_INTC_SEL62_INTSEL8 (*((volatile unsigned int*)(0x42A22AA0UL))) +#define bM4_INTC_SEL63_INTSEL0 (*((volatile unsigned int*)(0x42A22B00UL))) +#define bM4_INTC_SEL63_INTSEL1 (*((volatile unsigned int*)(0x42A22B04UL))) +#define bM4_INTC_SEL63_INTSEL2 (*((volatile unsigned int*)(0x42A22B08UL))) +#define bM4_INTC_SEL63_INTSEL3 (*((volatile unsigned int*)(0x42A22B0CUL))) +#define bM4_INTC_SEL63_INTSEL4 (*((volatile unsigned int*)(0x42A22B10UL))) +#define bM4_INTC_SEL63_INTSEL5 (*((volatile unsigned int*)(0x42A22B14UL))) +#define bM4_INTC_SEL63_INTSEL6 (*((volatile unsigned int*)(0x42A22B18UL))) +#define bM4_INTC_SEL63_INTSEL7 (*((volatile unsigned int*)(0x42A22B1CUL))) +#define bM4_INTC_SEL63_INTSEL8 (*((volatile unsigned int*)(0x42A22B20UL))) +#define bM4_INTC_SEL64_INTSEL0 (*((volatile unsigned int*)(0x42A22B80UL))) +#define bM4_INTC_SEL64_INTSEL1 (*((volatile unsigned int*)(0x42A22B84UL))) +#define bM4_INTC_SEL64_INTSEL2 (*((volatile unsigned int*)(0x42A22B88UL))) +#define bM4_INTC_SEL64_INTSEL3 (*((volatile unsigned int*)(0x42A22B8CUL))) +#define bM4_INTC_SEL64_INTSEL4 (*((volatile unsigned int*)(0x42A22B90UL))) +#define bM4_INTC_SEL64_INTSEL5 (*((volatile unsigned int*)(0x42A22B94UL))) +#define bM4_INTC_SEL64_INTSEL6 (*((volatile unsigned int*)(0x42A22B98UL))) +#define bM4_INTC_SEL64_INTSEL7 (*((volatile unsigned int*)(0x42A22B9CUL))) +#define bM4_INTC_SEL64_INTSEL8 (*((volatile unsigned int*)(0x42A22BA0UL))) +#define bM4_INTC_SEL65_INTSEL0 (*((volatile unsigned int*)(0x42A22C00UL))) +#define bM4_INTC_SEL65_INTSEL1 (*((volatile unsigned int*)(0x42A22C04UL))) +#define bM4_INTC_SEL65_INTSEL2 (*((volatile unsigned int*)(0x42A22C08UL))) +#define bM4_INTC_SEL65_INTSEL3 (*((volatile unsigned int*)(0x42A22C0CUL))) +#define bM4_INTC_SEL65_INTSEL4 (*((volatile unsigned int*)(0x42A22C10UL))) +#define bM4_INTC_SEL65_INTSEL5 (*((volatile unsigned int*)(0x42A22C14UL))) +#define bM4_INTC_SEL65_INTSEL6 (*((volatile unsigned int*)(0x42A22C18UL))) +#define bM4_INTC_SEL65_INTSEL7 (*((volatile unsigned int*)(0x42A22C1CUL))) +#define bM4_INTC_SEL65_INTSEL8 (*((volatile unsigned int*)(0x42A22C20UL))) +#define bM4_INTC_SEL66_INTSEL0 (*((volatile unsigned int*)(0x42A22C80UL))) +#define bM4_INTC_SEL66_INTSEL1 (*((volatile unsigned int*)(0x42A22C84UL))) +#define bM4_INTC_SEL66_INTSEL2 (*((volatile unsigned int*)(0x42A22C88UL))) +#define bM4_INTC_SEL66_INTSEL3 (*((volatile unsigned int*)(0x42A22C8CUL))) +#define bM4_INTC_SEL66_INTSEL4 (*((volatile unsigned int*)(0x42A22C90UL))) +#define bM4_INTC_SEL66_INTSEL5 (*((volatile unsigned int*)(0x42A22C94UL))) +#define bM4_INTC_SEL66_INTSEL6 (*((volatile unsigned int*)(0x42A22C98UL))) +#define bM4_INTC_SEL66_INTSEL7 (*((volatile unsigned int*)(0x42A22C9CUL))) +#define bM4_INTC_SEL66_INTSEL8 (*((volatile unsigned int*)(0x42A22CA0UL))) +#define bM4_INTC_SEL67_INTSEL0 (*((volatile unsigned int*)(0x42A22D00UL))) +#define bM4_INTC_SEL67_INTSEL1 (*((volatile unsigned int*)(0x42A22D04UL))) +#define bM4_INTC_SEL67_INTSEL2 (*((volatile unsigned int*)(0x42A22D08UL))) +#define bM4_INTC_SEL67_INTSEL3 (*((volatile unsigned int*)(0x42A22D0CUL))) +#define bM4_INTC_SEL67_INTSEL4 (*((volatile unsigned int*)(0x42A22D10UL))) +#define bM4_INTC_SEL67_INTSEL5 (*((volatile unsigned int*)(0x42A22D14UL))) +#define bM4_INTC_SEL67_INTSEL6 (*((volatile unsigned int*)(0x42A22D18UL))) +#define bM4_INTC_SEL67_INTSEL7 (*((volatile unsigned int*)(0x42A22D1CUL))) +#define bM4_INTC_SEL67_INTSEL8 (*((volatile unsigned int*)(0x42A22D20UL))) +#define bM4_INTC_SEL68_INTSEL0 (*((volatile unsigned int*)(0x42A22D80UL))) +#define bM4_INTC_SEL68_INTSEL1 (*((volatile unsigned int*)(0x42A22D84UL))) +#define bM4_INTC_SEL68_INTSEL2 (*((volatile unsigned int*)(0x42A22D88UL))) +#define bM4_INTC_SEL68_INTSEL3 (*((volatile unsigned int*)(0x42A22D8CUL))) +#define bM4_INTC_SEL68_INTSEL4 (*((volatile unsigned int*)(0x42A22D90UL))) +#define bM4_INTC_SEL68_INTSEL5 (*((volatile unsigned int*)(0x42A22D94UL))) +#define bM4_INTC_SEL68_INTSEL6 (*((volatile unsigned int*)(0x42A22D98UL))) +#define bM4_INTC_SEL68_INTSEL7 (*((volatile unsigned int*)(0x42A22D9CUL))) +#define bM4_INTC_SEL68_INTSEL8 (*((volatile unsigned int*)(0x42A22DA0UL))) +#define bM4_INTC_SEL69_INTSEL0 (*((volatile unsigned int*)(0x42A22E00UL))) +#define bM4_INTC_SEL69_INTSEL1 (*((volatile unsigned int*)(0x42A22E04UL))) +#define bM4_INTC_SEL69_INTSEL2 (*((volatile unsigned int*)(0x42A22E08UL))) +#define bM4_INTC_SEL69_INTSEL3 (*((volatile unsigned int*)(0x42A22E0CUL))) +#define bM4_INTC_SEL69_INTSEL4 (*((volatile unsigned int*)(0x42A22E10UL))) +#define bM4_INTC_SEL69_INTSEL5 (*((volatile unsigned int*)(0x42A22E14UL))) +#define bM4_INTC_SEL69_INTSEL6 (*((volatile unsigned int*)(0x42A22E18UL))) +#define bM4_INTC_SEL69_INTSEL7 (*((volatile unsigned int*)(0x42A22E1CUL))) +#define bM4_INTC_SEL69_INTSEL8 (*((volatile unsigned int*)(0x42A22E20UL))) +#define bM4_INTC_SEL70_INTSEL0 (*((volatile unsigned int*)(0x42A22E80UL))) +#define bM4_INTC_SEL70_INTSEL1 (*((volatile unsigned int*)(0x42A22E84UL))) +#define bM4_INTC_SEL70_INTSEL2 (*((volatile unsigned int*)(0x42A22E88UL))) +#define bM4_INTC_SEL70_INTSEL3 (*((volatile unsigned int*)(0x42A22E8CUL))) +#define bM4_INTC_SEL70_INTSEL4 (*((volatile unsigned int*)(0x42A22E90UL))) +#define bM4_INTC_SEL70_INTSEL5 (*((volatile unsigned int*)(0x42A22E94UL))) +#define bM4_INTC_SEL70_INTSEL6 (*((volatile unsigned int*)(0x42A22E98UL))) +#define bM4_INTC_SEL70_INTSEL7 (*((volatile unsigned int*)(0x42A22E9CUL))) +#define bM4_INTC_SEL70_INTSEL8 (*((volatile unsigned int*)(0x42A22EA0UL))) +#define bM4_INTC_SEL71_INTSEL0 (*((volatile unsigned int*)(0x42A22F00UL))) +#define bM4_INTC_SEL71_INTSEL1 (*((volatile unsigned int*)(0x42A22F04UL))) +#define bM4_INTC_SEL71_INTSEL2 (*((volatile unsigned int*)(0x42A22F08UL))) +#define bM4_INTC_SEL71_INTSEL3 (*((volatile unsigned int*)(0x42A22F0CUL))) +#define bM4_INTC_SEL71_INTSEL4 (*((volatile unsigned int*)(0x42A22F10UL))) +#define bM4_INTC_SEL71_INTSEL5 (*((volatile unsigned int*)(0x42A22F14UL))) +#define bM4_INTC_SEL71_INTSEL6 (*((volatile unsigned int*)(0x42A22F18UL))) +#define bM4_INTC_SEL71_INTSEL7 (*((volatile unsigned int*)(0x42A22F1CUL))) +#define bM4_INTC_SEL71_INTSEL8 (*((volatile unsigned int*)(0x42A22F20UL))) +#define bM4_INTC_SEL72_INTSEL0 (*((volatile unsigned int*)(0x42A22F80UL))) +#define bM4_INTC_SEL72_INTSEL1 (*((volatile unsigned int*)(0x42A22F84UL))) +#define bM4_INTC_SEL72_INTSEL2 (*((volatile unsigned int*)(0x42A22F88UL))) +#define bM4_INTC_SEL72_INTSEL3 (*((volatile unsigned int*)(0x42A22F8CUL))) +#define bM4_INTC_SEL72_INTSEL4 (*((volatile unsigned int*)(0x42A22F90UL))) +#define bM4_INTC_SEL72_INTSEL5 (*((volatile unsigned int*)(0x42A22F94UL))) +#define bM4_INTC_SEL72_INTSEL6 (*((volatile unsigned int*)(0x42A22F98UL))) +#define bM4_INTC_SEL72_INTSEL7 (*((volatile unsigned int*)(0x42A22F9CUL))) +#define bM4_INTC_SEL72_INTSEL8 (*((volatile unsigned int*)(0x42A22FA0UL))) +#define bM4_INTC_SEL73_INTSEL0 (*((volatile unsigned int*)(0x42A23000UL))) +#define bM4_INTC_SEL73_INTSEL1 (*((volatile unsigned int*)(0x42A23004UL))) +#define bM4_INTC_SEL73_INTSEL2 (*((volatile unsigned int*)(0x42A23008UL))) +#define bM4_INTC_SEL73_INTSEL3 (*((volatile unsigned int*)(0x42A2300CUL))) +#define bM4_INTC_SEL73_INTSEL4 (*((volatile unsigned int*)(0x42A23010UL))) +#define bM4_INTC_SEL73_INTSEL5 (*((volatile unsigned int*)(0x42A23014UL))) +#define bM4_INTC_SEL73_INTSEL6 (*((volatile unsigned int*)(0x42A23018UL))) +#define bM4_INTC_SEL73_INTSEL7 (*((volatile unsigned int*)(0x42A2301CUL))) +#define bM4_INTC_SEL73_INTSEL8 (*((volatile unsigned int*)(0x42A23020UL))) +#define bM4_INTC_SEL74_INTSEL0 (*((volatile unsigned int*)(0x42A23080UL))) +#define bM4_INTC_SEL74_INTSEL1 (*((volatile unsigned int*)(0x42A23084UL))) +#define bM4_INTC_SEL74_INTSEL2 (*((volatile unsigned int*)(0x42A23088UL))) +#define bM4_INTC_SEL74_INTSEL3 (*((volatile unsigned int*)(0x42A2308CUL))) +#define bM4_INTC_SEL74_INTSEL4 (*((volatile unsigned int*)(0x42A23090UL))) +#define bM4_INTC_SEL74_INTSEL5 (*((volatile unsigned int*)(0x42A23094UL))) +#define bM4_INTC_SEL74_INTSEL6 (*((volatile unsigned int*)(0x42A23098UL))) +#define bM4_INTC_SEL74_INTSEL7 (*((volatile unsigned int*)(0x42A2309CUL))) +#define bM4_INTC_SEL74_INTSEL8 (*((volatile unsigned int*)(0x42A230A0UL))) +#define bM4_INTC_SEL75_INTSEL0 (*((volatile unsigned int*)(0x42A23100UL))) +#define bM4_INTC_SEL75_INTSEL1 (*((volatile unsigned int*)(0x42A23104UL))) +#define bM4_INTC_SEL75_INTSEL2 (*((volatile unsigned int*)(0x42A23108UL))) +#define bM4_INTC_SEL75_INTSEL3 (*((volatile unsigned int*)(0x42A2310CUL))) +#define bM4_INTC_SEL75_INTSEL4 (*((volatile unsigned int*)(0x42A23110UL))) +#define bM4_INTC_SEL75_INTSEL5 (*((volatile unsigned int*)(0x42A23114UL))) +#define bM4_INTC_SEL75_INTSEL6 (*((volatile unsigned int*)(0x42A23118UL))) +#define bM4_INTC_SEL75_INTSEL7 (*((volatile unsigned int*)(0x42A2311CUL))) +#define bM4_INTC_SEL75_INTSEL8 (*((volatile unsigned int*)(0x42A23120UL))) +#define bM4_INTC_SEL76_INTSEL0 (*((volatile unsigned int*)(0x42A23180UL))) +#define bM4_INTC_SEL76_INTSEL1 (*((volatile unsigned int*)(0x42A23184UL))) +#define bM4_INTC_SEL76_INTSEL2 (*((volatile unsigned int*)(0x42A23188UL))) +#define bM4_INTC_SEL76_INTSEL3 (*((volatile unsigned int*)(0x42A2318CUL))) +#define bM4_INTC_SEL76_INTSEL4 (*((volatile unsigned int*)(0x42A23190UL))) +#define bM4_INTC_SEL76_INTSEL5 (*((volatile unsigned int*)(0x42A23194UL))) +#define bM4_INTC_SEL76_INTSEL6 (*((volatile unsigned int*)(0x42A23198UL))) +#define bM4_INTC_SEL76_INTSEL7 (*((volatile unsigned int*)(0x42A2319CUL))) +#define bM4_INTC_SEL76_INTSEL8 (*((volatile unsigned int*)(0x42A231A0UL))) +#define bM4_INTC_SEL77_INTSEL0 (*((volatile unsigned int*)(0x42A23200UL))) +#define bM4_INTC_SEL77_INTSEL1 (*((volatile unsigned int*)(0x42A23204UL))) +#define bM4_INTC_SEL77_INTSEL2 (*((volatile unsigned int*)(0x42A23208UL))) +#define bM4_INTC_SEL77_INTSEL3 (*((volatile unsigned int*)(0x42A2320CUL))) +#define bM4_INTC_SEL77_INTSEL4 (*((volatile unsigned int*)(0x42A23210UL))) +#define bM4_INTC_SEL77_INTSEL5 (*((volatile unsigned int*)(0x42A23214UL))) +#define bM4_INTC_SEL77_INTSEL6 (*((volatile unsigned int*)(0x42A23218UL))) +#define bM4_INTC_SEL77_INTSEL7 (*((volatile unsigned int*)(0x42A2321CUL))) +#define bM4_INTC_SEL77_INTSEL8 (*((volatile unsigned int*)(0x42A23220UL))) +#define bM4_INTC_SEL78_INTSEL0 (*((volatile unsigned int*)(0x42A23280UL))) +#define bM4_INTC_SEL78_INTSEL1 (*((volatile unsigned int*)(0x42A23284UL))) +#define bM4_INTC_SEL78_INTSEL2 (*((volatile unsigned int*)(0x42A23288UL))) +#define bM4_INTC_SEL78_INTSEL3 (*((volatile unsigned int*)(0x42A2328CUL))) +#define bM4_INTC_SEL78_INTSEL4 (*((volatile unsigned int*)(0x42A23290UL))) +#define bM4_INTC_SEL78_INTSEL5 (*((volatile unsigned int*)(0x42A23294UL))) +#define bM4_INTC_SEL78_INTSEL6 (*((volatile unsigned int*)(0x42A23298UL))) +#define bM4_INTC_SEL78_INTSEL7 (*((volatile unsigned int*)(0x42A2329CUL))) +#define bM4_INTC_SEL78_INTSEL8 (*((volatile unsigned int*)(0x42A232A0UL))) +#define bM4_INTC_SEL79_INTSEL0 (*((volatile unsigned int*)(0x42A23300UL))) +#define bM4_INTC_SEL79_INTSEL1 (*((volatile unsigned int*)(0x42A23304UL))) +#define bM4_INTC_SEL79_INTSEL2 (*((volatile unsigned int*)(0x42A23308UL))) +#define bM4_INTC_SEL79_INTSEL3 (*((volatile unsigned int*)(0x42A2330CUL))) +#define bM4_INTC_SEL79_INTSEL4 (*((volatile unsigned int*)(0x42A23310UL))) +#define bM4_INTC_SEL79_INTSEL5 (*((volatile unsigned int*)(0x42A23314UL))) +#define bM4_INTC_SEL79_INTSEL6 (*((volatile unsigned int*)(0x42A23318UL))) +#define bM4_INTC_SEL79_INTSEL7 (*((volatile unsigned int*)(0x42A2331CUL))) +#define bM4_INTC_SEL79_INTSEL8 (*((volatile unsigned int*)(0x42A23320UL))) +#define bM4_INTC_SEL80_INTSEL0 (*((volatile unsigned int*)(0x42A23380UL))) +#define bM4_INTC_SEL80_INTSEL1 (*((volatile unsigned int*)(0x42A23384UL))) +#define bM4_INTC_SEL80_INTSEL2 (*((volatile unsigned int*)(0x42A23388UL))) +#define bM4_INTC_SEL80_INTSEL3 (*((volatile unsigned int*)(0x42A2338CUL))) +#define bM4_INTC_SEL80_INTSEL4 (*((volatile unsigned int*)(0x42A23390UL))) +#define bM4_INTC_SEL80_INTSEL5 (*((volatile unsigned int*)(0x42A23394UL))) +#define bM4_INTC_SEL80_INTSEL6 (*((volatile unsigned int*)(0x42A23398UL))) +#define bM4_INTC_SEL80_INTSEL7 (*((volatile unsigned int*)(0x42A2339CUL))) +#define bM4_INTC_SEL80_INTSEL8 (*((volatile unsigned int*)(0x42A233A0UL))) +#define bM4_INTC_SEL81_INTSEL0 (*((volatile unsigned int*)(0x42A23400UL))) +#define bM4_INTC_SEL81_INTSEL1 (*((volatile unsigned int*)(0x42A23404UL))) +#define bM4_INTC_SEL81_INTSEL2 (*((volatile unsigned int*)(0x42A23408UL))) +#define bM4_INTC_SEL81_INTSEL3 (*((volatile unsigned int*)(0x42A2340CUL))) +#define bM4_INTC_SEL81_INTSEL4 (*((volatile unsigned int*)(0x42A23410UL))) +#define bM4_INTC_SEL81_INTSEL5 (*((volatile unsigned int*)(0x42A23414UL))) +#define bM4_INTC_SEL81_INTSEL6 (*((volatile unsigned int*)(0x42A23418UL))) +#define bM4_INTC_SEL81_INTSEL7 (*((volatile unsigned int*)(0x42A2341CUL))) +#define bM4_INTC_SEL81_INTSEL8 (*((volatile unsigned int*)(0x42A23420UL))) +#define bM4_INTC_SEL82_INTSEL0 (*((volatile unsigned int*)(0x42A23480UL))) +#define bM4_INTC_SEL82_INTSEL1 (*((volatile unsigned int*)(0x42A23484UL))) +#define bM4_INTC_SEL82_INTSEL2 (*((volatile unsigned int*)(0x42A23488UL))) +#define bM4_INTC_SEL82_INTSEL3 (*((volatile unsigned int*)(0x42A2348CUL))) +#define bM4_INTC_SEL82_INTSEL4 (*((volatile unsigned int*)(0x42A23490UL))) +#define bM4_INTC_SEL82_INTSEL5 (*((volatile unsigned int*)(0x42A23494UL))) +#define bM4_INTC_SEL82_INTSEL6 (*((volatile unsigned int*)(0x42A23498UL))) +#define bM4_INTC_SEL82_INTSEL7 (*((volatile unsigned int*)(0x42A2349CUL))) +#define bM4_INTC_SEL82_INTSEL8 (*((volatile unsigned int*)(0x42A234A0UL))) +#define bM4_INTC_SEL83_INTSEL0 (*((volatile unsigned int*)(0x42A23500UL))) +#define bM4_INTC_SEL83_INTSEL1 (*((volatile unsigned int*)(0x42A23504UL))) +#define bM4_INTC_SEL83_INTSEL2 (*((volatile unsigned int*)(0x42A23508UL))) +#define bM4_INTC_SEL83_INTSEL3 (*((volatile unsigned int*)(0x42A2350CUL))) +#define bM4_INTC_SEL83_INTSEL4 (*((volatile unsigned int*)(0x42A23510UL))) +#define bM4_INTC_SEL83_INTSEL5 (*((volatile unsigned int*)(0x42A23514UL))) +#define bM4_INTC_SEL83_INTSEL6 (*((volatile unsigned int*)(0x42A23518UL))) +#define bM4_INTC_SEL83_INTSEL7 (*((volatile unsigned int*)(0x42A2351CUL))) +#define bM4_INTC_SEL83_INTSEL8 (*((volatile unsigned int*)(0x42A23520UL))) +#define bM4_INTC_SEL84_INTSEL0 (*((volatile unsigned int*)(0x42A23580UL))) +#define bM4_INTC_SEL84_INTSEL1 (*((volatile unsigned int*)(0x42A23584UL))) +#define bM4_INTC_SEL84_INTSEL2 (*((volatile unsigned int*)(0x42A23588UL))) +#define bM4_INTC_SEL84_INTSEL3 (*((volatile unsigned int*)(0x42A2358CUL))) +#define bM4_INTC_SEL84_INTSEL4 (*((volatile unsigned int*)(0x42A23590UL))) +#define bM4_INTC_SEL84_INTSEL5 (*((volatile unsigned int*)(0x42A23594UL))) +#define bM4_INTC_SEL84_INTSEL6 (*((volatile unsigned int*)(0x42A23598UL))) +#define bM4_INTC_SEL84_INTSEL7 (*((volatile unsigned int*)(0x42A2359CUL))) +#define bM4_INTC_SEL84_INTSEL8 (*((volatile unsigned int*)(0x42A235A0UL))) +#define bM4_INTC_SEL85_INTSEL0 (*((volatile unsigned int*)(0x42A23600UL))) +#define bM4_INTC_SEL85_INTSEL1 (*((volatile unsigned int*)(0x42A23604UL))) +#define bM4_INTC_SEL85_INTSEL2 (*((volatile unsigned int*)(0x42A23608UL))) +#define bM4_INTC_SEL85_INTSEL3 (*((volatile unsigned int*)(0x42A2360CUL))) +#define bM4_INTC_SEL85_INTSEL4 (*((volatile unsigned int*)(0x42A23610UL))) +#define bM4_INTC_SEL85_INTSEL5 (*((volatile unsigned int*)(0x42A23614UL))) +#define bM4_INTC_SEL85_INTSEL6 (*((volatile unsigned int*)(0x42A23618UL))) +#define bM4_INTC_SEL85_INTSEL7 (*((volatile unsigned int*)(0x42A2361CUL))) +#define bM4_INTC_SEL85_INTSEL8 (*((volatile unsigned int*)(0x42A23620UL))) +#define bM4_INTC_SEL86_INTSEL0 (*((volatile unsigned int*)(0x42A23680UL))) +#define bM4_INTC_SEL86_INTSEL1 (*((volatile unsigned int*)(0x42A23684UL))) +#define bM4_INTC_SEL86_INTSEL2 (*((volatile unsigned int*)(0x42A23688UL))) +#define bM4_INTC_SEL86_INTSEL3 (*((volatile unsigned int*)(0x42A2368CUL))) +#define bM4_INTC_SEL86_INTSEL4 (*((volatile unsigned int*)(0x42A23690UL))) +#define bM4_INTC_SEL86_INTSEL5 (*((volatile unsigned int*)(0x42A23694UL))) +#define bM4_INTC_SEL86_INTSEL6 (*((volatile unsigned int*)(0x42A23698UL))) +#define bM4_INTC_SEL86_INTSEL7 (*((volatile unsigned int*)(0x42A2369CUL))) +#define bM4_INTC_SEL86_INTSEL8 (*((volatile unsigned int*)(0x42A236A0UL))) +#define bM4_INTC_SEL87_INTSEL0 (*((volatile unsigned int*)(0x42A23700UL))) +#define bM4_INTC_SEL87_INTSEL1 (*((volatile unsigned int*)(0x42A23704UL))) +#define bM4_INTC_SEL87_INTSEL2 (*((volatile unsigned int*)(0x42A23708UL))) +#define bM4_INTC_SEL87_INTSEL3 (*((volatile unsigned int*)(0x42A2370CUL))) +#define bM4_INTC_SEL87_INTSEL4 (*((volatile unsigned int*)(0x42A23710UL))) +#define bM4_INTC_SEL87_INTSEL5 (*((volatile unsigned int*)(0x42A23714UL))) +#define bM4_INTC_SEL87_INTSEL6 (*((volatile unsigned int*)(0x42A23718UL))) +#define bM4_INTC_SEL87_INTSEL7 (*((volatile unsigned int*)(0x42A2371CUL))) +#define bM4_INTC_SEL87_INTSEL8 (*((volatile unsigned int*)(0x42A23720UL))) +#define bM4_INTC_SEL88_INTSEL0 (*((volatile unsigned int*)(0x42A23780UL))) +#define bM4_INTC_SEL88_INTSEL1 (*((volatile unsigned int*)(0x42A23784UL))) +#define bM4_INTC_SEL88_INTSEL2 (*((volatile unsigned int*)(0x42A23788UL))) +#define bM4_INTC_SEL88_INTSEL3 (*((volatile unsigned int*)(0x42A2378CUL))) +#define bM4_INTC_SEL88_INTSEL4 (*((volatile unsigned int*)(0x42A23790UL))) +#define bM4_INTC_SEL88_INTSEL5 (*((volatile unsigned int*)(0x42A23794UL))) +#define bM4_INTC_SEL88_INTSEL6 (*((volatile unsigned int*)(0x42A23798UL))) +#define bM4_INTC_SEL88_INTSEL7 (*((volatile unsigned int*)(0x42A2379CUL))) +#define bM4_INTC_SEL88_INTSEL8 (*((volatile unsigned int*)(0x42A237A0UL))) +#define bM4_INTC_SEL89_INTSEL0 (*((volatile unsigned int*)(0x42A23800UL))) +#define bM4_INTC_SEL89_INTSEL1 (*((volatile unsigned int*)(0x42A23804UL))) +#define bM4_INTC_SEL89_INTSEL2 (*((volatile unsigned int*)(0x42A23808UL))) +#define bM4_INTC_SEL89_INTSEL3 (*((volatile unsigned int*)(0x42A2380CUL))) +#define bM4_INTC_SEL89_INTSEL4 (*((volatile unsigned int*)(0x42A23810UL))) +#define bM4_INTC_SEL89_INTSEL5 (*((volatile unsigned int*)(0x42A23814UL))) +#define bM4_INTC_SEL89_INTSEL6 (*((volatile unsigned int*)(0x42A23818UL))) +#define bM4_INTC_SEL89_INTSEL7 (*((volatile unsigned int*)(0x42A2381CUL))) +#define bM4_INTC_SEL89_INTSEL8 (*((volatile unsigned int*)(0x42A23820UL))) +#define bM4_INTC_SEL90_INTSEL0 (*((volatile unsigned int*)(0x42A23880UL))) +#define bM4_INTC_SEL90_INTSEL1 (*((volatile unsigned int*)(0x42A23884UL))) +#define bM4_INTC_SEL90_INTSEL2 (*((volatile unsigned int*)(0x42A23888UL))) +#define bM4_INTC_SEL90_INTSEL3 (*((volatile unsigned int*)(0x42A2388CUL))) +#define bM4_INTC_SEL90_INTSEL4 (*((volatile unsigned int*)(0x42A23890UL))) +#define bM4_INTC_SEL90_INTSEL5 (*((volatile unsigned int*)(0x42A23894UL))) +#define bM4_INTC_SEL90_INTSEL6 (*((volatile unsigned int*)(0x42A23898UL))) +#define bM4_INTC_SEL90_INTSEL7 (*((volatile unsigned int*)(0x42A2389CUL))) +#define bM4_INTC_SEL90_INTSEL8 (*((volatile unsigned int*)(0x42A238A0UL))) +#define bM4_INTC_SEL91_INTSEL0 (*((volatile unsigned int*)(0x42A23900UL))) +#define bM4_INTC_SEL91_INTSEL1 (*((volatile unsigned int*)(0x42A23904UL))) +#define bM4_INTC_SEL91_INTSEL2 (*((volatile unsigned int*)(0x42A23908UL))) +#define bM4_INTC_SEL91_INTSEL3 (*((volatile unsigned int*)(0x42A2390CUL))) +#define bM4_INTC_SEL91_INTSEL4 (*((volatile unsigned int*)(0x42A23910UL))) +#define bM4_INTC_SEL91_INTSEL5 (*((volatile unsigned int*)(0x42A23914UL))) +#define bM4_INTC_SEL91_INTSEL6 (*((volatile unsigned int*)(0x42A23918UL))) +#define bM4_INTC_SEL91_INTSEL7 (*((volatile unsigned int*)(0x42A2391CUL))) +#define bM4_INTC_SEL91_INTSEL8 (*((volatile unsigned int*)(0x42A23920UL))) +#define bM4_INTC_SEL92_INTSEL0 (*((volatile unsigned int*)(0x42A23980UL))) +#define bM4_INTC_SEL92_INTSEL1 (*((volatile unsigned int*)(0x42A23984UL))) +#define bM4_INTC_SEL92_INTSEL2 (*((volatile unsigned int*)(0x42A23988UL))) +#define bM4_INTC_SEL92_INTSEL3 (*((volatile unsigned int*)(0x42A2398CUL))) +#define bM4_INTC_SEL92_INTSEL4 (*((volatile unsigned int*)(0x42A23990UL))) +#define bM4_INTC_SEL92_INTSEL5 (*((volatile unsigned int*)(0x42A23994UL))) +#define bM4_INTC_SEL92_INTSEL6 (*((volatile unsigned int*)(0x42A23998UL))) +#define bM4_INTC_SEL92_INTSEL7 (*((volatile unsigned int*)(0x42A2399CUL))) +#define bM4_INTC_SEL92_INTSEL8 (*((volatile unsigned int*)(0x42A239A0UL))) +#define bM4_INTC_SEL93_INTSEL0 (*((volatile unsigned int*)(0x42A23A00UL))) +#define bM4_INTC_SEL93_INTSEL1 (*((volatile unsigned int*)(0x42A23A04UL))) +#define bM4_INTC_SEL93_INTSEL2 (*((volatile unsigned int*)(0x42A23A08UL))) +#define bM4_INTC_SEL93_INTSEL3 (*((volatile unsigned int*)(0x42A23A0CUL))) +#define bM4_INTC_SEL93_INTSEL4 (*((volatile unsigned int*)(0x42A23A10UL))) +#define bM4_INTC_SEL93_INTSEL5 (*((volatile unsigned int*)(0x42A23A14UL))) +#define bM4_INTC_SEL93_INTSEL6 (*((volatile unsigned int*)(0x42A23A18UL))) +#define bM4_INTC_SEL93_INTSEL7 (*((volatile unsigned int*)(0x42A23A1CUL))) +#define bM4_INTC_SEL93_INTSEL8 (*((volatile unsigned int*)(0x42A23A20UL))) +#define bM4_INTC_SEL94_INTSEL0 (*((volatile unsigned int*)(0x42A23A80UL))) +#define bM4_INTC_SEL94_INTSEL1 (*((volatile unsigned int*)(0x42A23A84UL))) +#define bM4_INTC_SEL94_INTSEL2 (*((volatile unsigned int*)(0x42A23A88UL))) +#define bM4_INTC_SEL94_INTSEL3 (*((volatile unsigned int*)(0x42A23A8CUL))) +#define bM4_INTC_SEL94_INTSEL4 (*((volatile unsigned int*)(0x42A23A90UL))) +#define bM4_INTC_SEL94_INTSEL5 (*((volatile unsigned int*)(0x42A23A94UL))) +#define bM4_INTC_SEL94_INTSEL6 (*((volatile unsigned int*)(0x42A23A98UL))) +#define bM4_INTC_SEL94_INTSEL7 (*((volatile unsigned int*)(0x42A23A9CUL))) +#define bM4_INTC_SEL94_INTSEL8 (*((volatile unsigned int*)(0x42A23AA0UL))) +#define bM4_INTC_SEL95_INTSEL0 (*((volatile unsigned int*)(0x42A23B00UL))) +#define bM4_INTC_SEL95_INTSEL1 (*((volatile unsigned int*)(0x42A23B04UL))) +#define bM4_INTC_SEL95_INTSEL2 (*((volatile unsigned int*)(0x42A23B08UL))) +#define bM4_INTC_SEL95_INTSEL3 (*((volatile unsigned int*)(0x42A23B0CUL))) +#define bM4_INTC_SEL95_INTSEL4 (*((volatile unsigned int*)(0x42A23B10UL))) +#define bM4_INTC_SEL95_INTSEL5 (*((volatile unsigned int*)(0x42A23B14UL))) +#define bM4_INTC_SEL95_INTSEL6 (*((volatile unsigned int*)(0x42A23B18UL))) +#define bM4_INTC_SEL95_INTSEL7 (*((volatile unsigned int*)(0x42A23B1CUL))) +#define bM4_INTC_SEL95_INTSEL8 (*((volatile unsigned int*)(0x42A23B20UL))) +#define bM4_INTC_SEL96_INTSEL0 (*((volatile unsigned int*)(0x42A23B80UL))) +#define bM4_INTC_SEL96_INTSEL1 (*((volatile unsigned int*)(0x42A23B84UL))) +#define bM4_INTC_SEL96_INTSEL2 (*((volatile unsigned int*)(0x42A23B88UL))) +#define bM4_INTC_SEL96_INTSEL3 (*((volatile unsigned int*)(0x42A23B8CUL))) +#define bM4_INTC_SEL96_INTSEL4 (*((volatile unsigned int*)(0x42A23B90UL))) +#define bM4_INTC_SEL96_INTSEL5 (*((volatile unsigned int*)(0x42A23B94UL))) +#define bM4_INTC_SEL96_INTSEL6 (*((volatile unsigned int*)(0x42A23B98UL))) +#define bM4_INTC_SEL96_INTSEL7 (*((volatile unsigned int*)(0x42A23B9CUL))) +#define bM4_INTC_SEL96_INTSEL8 (*((volatile unsigned int*)(0x42A23BA0UL))) +#define bM4_INTC_SEL97_INTSEL0 (*((volatile unsigned int*)(0x42A23C00UL))) +#define bM4_INTC_SEL97_INTSEL1 (*((volatile unsigned int*)(0x42A23C04UL))) +#define bM4_INTC_SEL97_INTSEL2 (*((volatile unsigned int*)(0x42A23C08UL))) +#define bM4_INTC_SEL97_INTSEL3 (*((volatile unsigned int*)(0x42A23C0CUL))) +#define bM4_INTC_SEL97_INTSEL4 (*((volatile unsigned int*)(0x42A23C10UL))) +#define bM4_INTC_SEL97_INTSEL5 (*((volatile unsigned int*)(0x42A23C14UL))) +#define bM4_INTC_SEL97_INTSEL6 (*((volatile unsigned int*)(0x42A23C18UL))) +#define bM4_INTC_SEL97_INTSEL7 (*((volatile unsigned int*)(0x42A23C1CUL))) +#define bM4_INTC_SEL97_INTSEL8 (*((volatile unsigned int*)(0x42A23C20UL))) +#define bM4_INTC_SEL98_INTSEL0 (*((volatile unsigned int*)(0x42A23C80UL))) +#define bM4_INTC_SEL98_INTSEL1 (*((volatile unsigned int*)(0x42A23C84UL))) +#define bM4_INTC_SEL98_INTSEL2 (*((volatile unsigned int*)(0x42A23C88UL))) +#define bM4_INTC_SEL98_INTSEL3 (*((volatile unsigned int*)(0x42A23C8CUL))) +#define bM4_INTC_SEL98_INTSEL4 (*((volatile unsigned int*)(0x42A23C90UL))) +#define bM4_INTC_SEL98_INTSEL5 (*((volatile unsigned int*)(0x42A23C94UL))) +#define bM4_INTC_SEL98_INTSEL6 (*((volatile unsigned int*)(0x42A23C98UL))) +#define bM4_INTC_SEL98_INTSEL7 (*((volatile unsigned int*)(0x42A23C9CUL))) +#define bM4_INTC_SEL98_INTSEL8 (*((volatile unsigned int*)(0x42A23CA0UL))) +#define bM4_INTC_SEL99_INTSEL0 (*((volatile unsigned int*)(0x42A23D00UL))) +#define bM4_INTC_SEL99_INTSEL1 (*((volatile unsigned int*)(0x42A23D04UL))) +#define bM4_INTC_SEL99_INTSEL2 (*((volatile unsigned int*)(0x42A23D08UL))) +#define bM4_INTC_SEL99_INTSEL3 (*((volatile unsigned int*)(0x42A23D0CUL))) +#define bM4_INTC_SEL99_INTSEL4 (*((volatile unsigned int*)(0x42A23D10UL))) +#define bM4_INTC_SEL99_INTSEL5 (*((volatile unsigned int*)(0x42A23D14UL))) +#define bM4_INTC_SEL99_INTSEL6 (*((volatile unsigned int*)(0x42A23D18UL))) +#define bM4_INTC_SEL99_INTSEL7 (*((volatile unsigned int*)(0x42A23D1CUL))) +#define bM4_INTC_SEL99_INTSEL8 (*((volatile unsigned int*)(0x42A23D20UL))) +#define bM4_INTC_SEL100_INTSEL0 (*((volatile unsigned int*)(0x42A23D80UL))) +#define bM4_INTC_SEL100_INTSEL1 (*((volatile unsigned int*)(0x42A23D84UL))) +#define bM4_INTC_SEL100_INTSEL2 (*((volatile unsigned int*)(0x42A23D88UL))) +#define bM4_INTC_SEL100_INTSEL3 (*((volatile unsigned int*)(0x42A23D8CUL))) +#define bM4_INTC_SEL100_INTSEL4 (*((volatile unsigned int*)(0x42A23D90UL))) +#define bM4_INTC_SEL100_INTSEL5 (*((volatile unsigned int*)(0x42A23D94UL))) +#define bM4_INTC_SEL100_INTSEL6 (*((volatile unsigned int*)(0x42A23D98UL))) +#define bM4_INTC_SEL100_INTSEL7 (*((volatile unsigned int*)(0x42A23D9CUL))) +#define bM4_INTC_SEL100_INTSEL8 (*((volatile unsigned int*)(0x42A23DA0UL))) +#define bM4_INTC_SEL101_INTSEL0 (*((volatile unsigned int*)(0x42A23E00UL))) +#define bM4_INTC_SEL101_INTSEL1 (*((volatile unsigned int*)(0x42A23E04UL))) +#define bM4_INTC_SEL101_INTSEL2 (*((volatile unsigned int*)(0x42A23E08UL))) +#define bM4_INTC_SEL101_INTSEL3 (*((volatile unsigned int*)(0x42A23E0CUL))) +#define bM4_INTC_SEL101_INTSEL4 (*((volatile unsigned int*)(0x42A23E10UL))) +#define bM4_INTC_SEL101_INTSEL5 (*((volatile unsigned int*)(0x42A23E14UL))) +#define bM4_INTC_SEL101_INTSEL6 (*((volatile unsigned int*)(0x42A23E18UL))) +#define bM4_INTC_SEL101_INTSEL7 (*((volatile unsigned int*)(0x42A23E1CUL))) +#define bM4_INTC_SEL101_INTSEL8 (*((volatile unsigned int*)(0x42A23E20UL))) +#define bM4_INTC_SEL102_INTSEL0 (*((volatile unsigned int*)(0x42A23E80UL))) +#define bM4_INTC_SEL102_INTSEL1 (*((volatile unsigned int*)(0x42A23E84UL))) +#define bM4_INTC_SEL102_INTSEL2 (*((volatile unsigned int*)(0x42A23E88UL))) +#define bM4_INTC_SEL102_INTSEL3 (*((volatile unsigned int*)(0x42A23E8CUL))) +#define bM4_INTC_SEL102_INTSEL4 (*((volatile unsigned int*)(0x42A23E90UL))) +#define bM4_INTC_SEL102_INTSEL5 (*((volatile unsigned int*)(0x42A23E94UL))) +#define bM4_INTC_SEL102_INTSEL6 (*((volatile unsigned int*)(0x42A23E98UL))) +#define bM4_INTC_SEL102_INTSEL7 (*((volatile unsigned int*)(0x42A23E9CUL))) +#define bM4_INTC_SEL102_INTSEL8 (*((volatile unsigned int*)(0x42A23EA0UL))) +#define bM4_INTC_SEL103_INTSEL0 (*((volatile unsigned int*)(0x42A23F00UL))) +#define bM4_INTC_SEL103_INTSEL1 (*((volatile unsigned int*)(0x42A23F04UL))) +#define bM4_INTC_SEL103_INTSEL2 (*((volatile unsigned int*)(0x42A23F08UL))) +#define bM4_INTC_SEL103_INTSEL3 (*((volatile unsigned int*)(0x42A23F0CUL))) +#define bM4_INTC_SEL103_INTSEL4 (*((volatile unsigned int*)(0x42A23F10UL))) +#define bM4_INTC_SEL103_INTSEL5 (*((volatile unsigned int*)(0x42A23F14UL))) +#define bM4_INTC_SEL103_INTSEL6 (*((volatile unsigned int*)(0x42A23F18UL))) +#define bM4_INTC_SEL103_INTSEL7 (*((volatile unsigned int*)(0x42A23F1CUL))) +#define bM4_INTC_SEL103_INTSEL8 (*((volatile unsigned int*)(0x42A23F20UL))) +#define bM4_INTC_SEL104_INTSEL0 (*((volatile unsigned int*)(0x42A23F80UL))) +#define bM4_INTC_SEL104_INTSEL1 (*((volatile unsigned int*)(0x42A23F84UL))) +#define bM4_INTC_SEL104_INTSEL2 (*((volatile unsigned int*)(0x42A23F88UL))) +#define bM4_INTC_SEL104_INTSEL3 (*((volatile unsigned int*)(0x42A23F8CUL))) +#define bM4_INTC_SEL104_INTSEL4 (*((volatile unsigned int*)(0x42A23F90UL))) +#define bM4_INTC_SEL104_INTSEL5 (*((volatile unsigned int*)(0x42A23F94UL))) +#define bM4_INTC_SEL104_INTSEL6 (*((volatile unsigned int*)(0x42A23F98UL))) +#define bM4_INTC_SEL104_INTSEL7 (*((volatile unsigned int*)(0x42A23F9CUL))) +#define bM4_INTC_SEL104_INTSEL8 (*((volatile unsigned int*)(0x42A23FA0UL))) +#define bM4_INTC_SEL105_INTSEL0 (*((volatile unsigned int*)(0x42A24000UL))) +#define bM4_INTC_SEL105_INTSEL1 (*((volatile unsigned int*)(0x42A24004UL))) +#define bM4_INTC_SEL105_INTSEL2 (*((volatile unsigned int*)(0x42A24008UL))) +#define bM4_INTC_SEL105_INTSEL3 (*((volatile unsigned int*)(0x42A2400CUL))) +#define bM4_INTC_SEL105_INTSEL4 (*((volatile unsigned int*)(0x42A24010UL))) +#define bM4_INTC_SEL105_INTSEL5 (*((volatile unsigned int*)(0x42A24014UL))) +#define bM4_INTC_SEL105_INTSEL6 (*((volatile unsigned int*)(0x42A24018UL))) +#define bM4_INTC_SEL105_INTSEL7 (*((volatile unsigned int*)(0x42A2401CUL))) +#define bM4_INTC_SEL105_INTSEL8 (*((volatile unsigned int*)(0x42A24020UL))) +#define bM4_INTC_SEL106_INTSEL0 (*((volatile unsigned int*)(0x42A24080UL))) +#define bM4_INTC_SEL106_INTSEL1 (*((volatile unsigned int*)(0x42A24084UL))) +#define bM4_INTC_SEL106_INTSEL2 (*((volatile unsigned int*)(0x42A24088UL))) +#define bM4_INTC_SEL106_INTSEL3 (*((volatile unsigned int*)(0x42A2408CUL))) +#define bM4_INTC_SEL106_INTSEL4 (*((volatile unsigned int*)(0x42A24090UL))) +#define bM4_INTC_SEL106_INTSEL5 (*((volatile unsigned int*)(0x42A24094UL))) +#define bM4_INTC_SEL106_INTSEL6 (*((volatile unsigned int*)(0x42A24098UL))) +#define bM4_INTC_SEL106_INTSEL7 (*((volatile unsigned int*)(0x42A2409CUL))) +#define bM4_INTC_SEL106_INTSEL8 (*((volatile unsigned int*)(0x42A240A0UL))) +#define bM4_INTC_SEL107_INTSEL0 (*((volatile unsigned int*)(0x42A24100UL))) +#define bM4_INTC_SEL107_INTSEL1 (*((volatile unsigned int*)(0x42A24104UL))) +#define bM4_INTC_SEL107_INTSEL2 (*((volatile unsigned int*)(0x42A24108UL))) +#define bM4_INTC_SEL107_INTSEL3 (*((volatile unsigned int*)(0x42A2410CUL))) +#define bM4_INTC_SEL107_INTSEL4 (*((volatile unsigned int*)(0x42A24110UL))) +#define bM4_INTC_SEL107_INTSEL5 (*((volatile unsigned int*)(0x42A24114UL))) +#define bM4_INTC_SEL107_INTSEL6 (*((volatile unsigned int*)(0x42A24118UL))) +#define bM4_INTC_SEL107_INTSEL7 (*((volatile unsigned int*)(0x42A2411CUL))) +#define bM4_INTC_SEL107_INTSEL8 (*((volatile unsigned int*)(0x42A24120UL))) +#define bM4_INTC_SEL108_INTSEL0 (*((volatile unsigned int*)(0x42A24180UL))) +#define bM4_INTC_SEL108_INTSEL1 (*((volatile unsigned int*)(0x42A24184UL))) +#define bM4_INTC_SEL108_INTSEL2 (*((volatile unsigned int*)(0x42A24188UL))) +#define bM4_INTC_SEL108_INTSEL3 (*((volatile unsigned int*)(0x42A2418CUL))) +#define bM4_INTC_SEL108_INTSEL4 (*((volatile unsigned int*)(0x42A24190UL))) +#define bM4_INTC_SEL108_INTSEL5 (*((volatile unsigned int*)(0x42A24194UL))) +#define bM4_INTC_SEL108_INTSEL6 (*((volatile unsigned int*)(0x42A24198UL))) +#define bM4_INTC_SEL108_INTSEL7 (*((volatile unsigned int*)(0x42A2419CUL))) +#define bM4_INTC_SEL108_INTSEL8 (*((volatile unsigned int*)(0x42A241A0UL))) +#define bM4_INTC_SEL109_INTSEL0 (*((volatile unsigned int*)(0x42A24200UL))) +#define bM4_INTC_SEL109_INTSEL1 (*((volatile unsigned int*)(0x42A24204UL))) +#define bM4_INTC_SEL109_INTSEL2 (*((volatile unsigned int*)(0x42A24208UL))) +#define bM4_INTC_SEL109_INTSEL3 (*((volatile unsigned int*)(0x42A2420CUL))) +#define bM4_INTC_SEL109_INTSEL4 (*((volatile unsigned int*)(0x42A24210UL))) +#define bM4_INTC_SEL109_INTSEL5 (*((volatile unsigned int*)(0x42A24214UL))) +#define bM4_INTC_SEL109_INTSEL6 (*((volatile unsigned int*)(0x42A24218UL))) +#define bM4_INTC_SEL109_INTSEL7 (*((volatile unsigned int*)(0x42A2421CUL))) +#define bM4_INTC_SEL109_INTSEL8 (*((volatile unsigned int*)(0x42A24220UL))) +#define bM4_INTC_SEL110_INTSEL0 (*((volatile unsigned int*)(0x42A24280UL))) +#define bM4_INTC_SEL110_INTSEL1 (*((volatile unsigned int*)(0x42A24284UL))) +#define bM4_INTC_SEL110_INTSEL2 (*((volatile unsigned int*)(0x42A24288UL))) +#define bM4_INTC_SEL110_INTSEL3 (*((volatile unsigned int*)(0x42A2428CUL))) +#define bM4_INTC_SEL110_INTSEL4 (*((volatile unsigned int*)(0x42A24290UL))) +#define bM4_INTC_SEL110_INTSEL5 (*((volatile unsigned int*)(0x42A24294UL))) +#define bM4_INTC_SEL110_INTSEL6 (*((volatile unsigned int*)(0x42A24298UL))) +#define bM4_INTC_SEL110_INTSEL7 (*((volatile unsigned int*)(0x42A2429CUL))) +#define bM4_INTC_SEL110_INTSEL8 (*((volatile unsigned int*)(0x42A242A0UL))) +#define bM4_INTC_SEL111_INTSEL0 (*((volatile unsigned int*)(0x42A24300UL))) +#define bM4_INTC_SEL111_INTSEL1 (*((volatile unsigned int*)(0x42A24304UL))) +#define bM4_INTC_SEL111_INTSEL2 (*((volatile unsigned int*)(0x42A24308UL))) +#define bM4_INTC_SEL111_INTSEL3 (*((volatile unsigned int*)(0x42A2430CUL))) +#define bM4_INTC_SEL111_INTSEL4 (*((volatile unsigned int*)(0x42A24310UL))) +#define bM4_INTC_SEL111_INTSEL5 (*((volatile unsigned int*)(0x42A24314UL))) +#define bM4_INTC_SEL111_INTSEL6 (*((volatile unsigned int*)(0x42A24318UL))) +#define bM4_INTC_SEL111_INTSEL7 (*((volatile unsigned int*)(0x42A2431CUL))) +#define bM4_INTC_SEL111_INTSEL8 (*((volatile unsigned int*)(0x42A24320UL))) +#define bM4_INTC_SEL112_INTSEL0 (*((volatile unsigned int*)(0x42A24380UL))) +#define bM4_INTC_SEL112_INTSEL1 (*((volatile unsigned int*)(0x42A24384UL))) +#define bM4_INTC_SEL112_INTSEL2 (*((volatile unsigned int*)(0x42A24388UL))) +#define bM4_INTC_SEL112_INTSEL3 (*((volatile unsigned int*)(0x42A2438CUL))) +#define bM4_INTC_SEL112_INTSEL4 (*((volatile unsigned int*)(0x42A24390UL))) +#define bM4_INTC_SEL112_INTSEL5 (*((volatile unsigned int*)(0x42A24394UL))) +#define bM4_INTC_SEL112_INTSEL6 (*((volatile unsigned int*)(0x42A24398UL))) +#define bM4_INTC_SEL112_INTSEL7 (*((volatile unsigned int*)(0x42A2439CUL))) +#define bM4_INTC_SEL112_INTSEL8 (*((volatile unsigned int*)(0x42A243A0UL))) +#define bM4_INTC_SEL113_INTSEL0 (*((volatile unsigned int*)(0x42A24400UL))) +#define bM4_INTC_SEL113_INTSEL1 (*((volatile unsigned int*)(0x42A24404UL))) +#define bM4_INTC_SEL113_INTSEL2 (*((volatile unsigned int*)(0x42A24408UL))) +#define bM4_INTC_SEL113_INTSEL3 (*((volatile unsigned int*)(0x42A2440CUL))) +#define bM4_INTC_SEL113_INTSEL4 (*((volatile unsigned int*)(0x42A24410UL))) +#define bM4_INTC_SEL113_INTSEL5 (*((volatile unsigned int*)(0x42A24414UL))) +#define bM4_INTC_SEL113_INTSEL6 (*((volatile unsigned int*)(0x42A24418UL))) +#define bM4_INTC_SEL113_INTSEL7 (*((volatile unsigned int*)(0x42A2441CUL))) +#define bM4_INTC_SEL113_INTSEL8 (*((volatile unsigned int*)(0x42A24420UL))) +#define bM4_INTC_SEL114_INTSEL0 (*((volatile unsigned int*)(0x42A24480UL))) +#define bM4_INTC_SEL114_INTSEL1 (*((volatile unsigned int*)(0x42A24484UL))) +#define bM4_INTC_SEL114_INTSEL2 (*((volatile unsigned int*)(0x42A24488UL))) +#define bM4_INTC_SEL114_INTSEL3 (*((volatile unsigned int*)(0x42A2448CUL))) +#define bM4_INTC_SEL114_INTSEL4 (*((volatile unsigned int*)(0x42A24490UL))) +#define bM4_INTC_SEL114_INTSEL5 (*((volatile unsigned int*)(0x42A24494UL))) +#define bM4_INTC_SEL114_INTSEL6 (*((volatile unsigned int*)(0x42A24498UL))) +#define bM4_INTC_SEL114_INTSEL7 (*((volatile unsigned int*)(0x42A2449CUL))) +#define bM4_INTC_SEL114_INTSEL8 (*((volatile unsigned int*)(0x42A244A0UL))) +#define bM4_INTC_SEL115_INTSEL0 (*((volatile unsigned int*)(0x42A24500UL))) +#define bM4_INTC_SEL115_INTSEL1 (*((volatile unsigned int*)(0x42A24504UL))) +#define bM4_INTC_SEL115_INTSEL2 (*((volatile unsigned int*)(0x42A24508UL))) +#define bM4_INTC_SEL115_INTSEL3 (*((volatile unsigned int*)(0x42A2450CUL))) +#define bM4_INTC_SEL115_INTSEL4 (*((volatile unsigned int*)(0x42A24510UL))) +#define bM4_INTC_SEL115_INTSEL5 (*((volatile unsigned int*)(0x42A24514UL))) +#define bM4_INTC_SEL115_INTSEL6 (*((volatile unsigned int*)(0x42A24518UL))) +#define bM4_INTC_SEL115_INTSEL7 (*((volatile unsigned int*)(0x42A2451CUL))) +#define bM4_INTC_SEL115_INTSEL8 (*((volatile unsigned int*)(0x42A24520UL))) +#define bM4_INTC_SEL116_INTSEL0 (*((volatile unsigned int*)(0x42A24580UL))) +#define bM4_INTC_SEL116_INTSEL1 (*((volatile unsigned int*)(0x42A24584UL))) +#define bM4_INTC_SEL116_INTSEL2 (*((volatile unsigned int*)(0x42A24588UL))) +#define bM4_INTC_SEL116_INTSEL3 (*((volatile unsigned int*)(0x42A2458CUL))) +#define bM4_INTC_SEL116_INTSEL4 (*((volatile unsigned int*)(0x42A24590UL))) +#define bM4_INTC_SEL116_INTSEL5 (*((volatile unsigned int*)(0x42A24594UL))) +#define bM4_INTC_SEL116_INTSEL6 (*((volatile unsigned int*)(0x42A24598UL))) +#define bM4_INTC_SEL116_INTSEL7 (*((volatile unsigned int*)(0x42A2459CUL))) +#define bM4_INTC_SEL116_INTSEL8 (*((volatile unsigned int*)(0x42A245A0UL))) +#define bM4_INTC_SEL117_INTSEL0 (*((volatile unsigned int*)(0x42A24600UL))) +#define bM4_INTC_SEL117_INTSEL1 (*((volatile unsigned int*)(0x42A24604UL))) +#define bM4_INTC_SEL117_INTSEL2 (*((volatile unsigned int*)(0x42A24608UL))) +#define bM4_INTC_SEL117_INTSEL3 (*((volatile unsigned int*)(0x42A2460CUL))) +#define bM4_INTC_SEL117_INTSEL4 (*((volatile unsigned int*)(0x42A24610UL))) +#define bM4_INTC_SEL117_INTSEL5 (*((volatile unsigned int*)(0x42A24614UL))) +#define bM4_INTC_SEL117_INTSEL6 (*((volatile unsigned int*)(0x42A24618UL))) +#define bM4_INTC_SEL117_INTSEL7 (*((volatile unsigned int*)(0x42A2461CUL))) +#define bM4_INTC_SEL117_INTSEL8 (*((volatile unsigned int*)(0x42A24620UL))) +#define bM4_INTC_SEL118_INTSEL0 (*((volatile unsigned int*)(0x42A24680UL))) +#define bM4_INTC_SEL118_INTSEL1 (*((volatile unsigned int*)(0x42A24684UL))) +#define bM4_INTC_SEL118_INTSEL2 (*((volatile unsigned int*)(0x42A24688UL))) +#define bM4_INTC_SEL118_INTSEL3 (*((volatile unsigned int*)(0x42A2468CUL))) +#define bM4_INTC_SEL118_INTSEL4 (*((volatile unsigned int*)(0x42A24690UL))) +#define bM4_INTC_SEL118_INTSEL5 (*((volatile unsigned int*)(0x42A24694UL))) +#define bM4_INTC_SEL118_INTSEL6 (*((volatile unsigned int*)(0x42A24698UL))) +#define bM4_INTC_SEL118_INTSEL7 (*((volatile unsigned int*)(0x42A2469CUL))) +#define bM4_INTC_SEL118_INTSEL8 (*((volatile unsigned int*)(0x42A246A0UL))) +#define bM4_INTC_SEL119_INTSEL0 (*((volatile unsigned int*)(0x42A24700UL))) +#define bM4_INTC_SEL119_INTSEL1 (*((volatile unsigned int*)(0x42A24704UL))) +#define bM4_INTC_SEL119_INTSEL2 (*((volatile unsigned int*)(0x42A24708UL))) +#define bM4_INTC_SEL119_INTSEL3 (*((volatile unsigned int*)(0x42A2470CUL))) +#define bM4_INTC_SEL119_INTSEL4 (*((volatile unsigned int*)(0x42A24710UL))) +#define bM4_INTC_SEL119_INTSEL5 (*((volatile unsigned int*)(0x42A24714UL))) +#define bM4_INTC_SEL119_INTSEL6 (*((volatile unsigned int*)(0x42A24718UL))) +#define bM4_INTC_SEL119_INTSEL7 (*((volatile unsigned int*)(0x42A2471CUL))) +#define bM4_INTC_SEL119_INTSEL8 (*((volatile unsigned int*)(0x42A24720UL))) +#define bM4_INTC_SEL120_INTSEL0 (*((volatile unsigned int*)(0x42A24780UL))) +#define bM4_INTC_SEL120_INTSEL1 (*((volatile unsigned int*)(0x42A24784UL))) +#define bM4_INTC_SEL120_INTSEL2 (*((volatile unsigned int*)(0x42A24788UL))) +#define bM4_INTC_SEL120_INTSEL3 (*((volatile unsigned int*)(0x42A2478CUL))) +#define bM4_INTC_SEL120_INTSEL4 (*((volatile unsigned int*)(0x42A24790UL))) +#define bM4_INTC_SEL120_INTSEL5 (*((volatile unsigned int*)(0x42A24794UL))) +#define bM4_INTC_SEL120_INTSEL6 (*((volatile unsigned int*)(0x42A24798UL))) +#define bM4_INTC_SEL120_INTSEL7 (*((volatile unsigned int*)(0x42A2479CUL))) +#define bM4_INTC_SEL120_INTSEL8 (*((volatile unsigned int*)(0x42A247A0UL))) +#define bM4_INTC_SEL121_INTSEL0 (*((volatile unsigned int*)(0x42A24800UL))) +#define bM4_INTC_SEL121_INTSEL1 (*((volatile unsigned int*)(0x42A24804UL))) +#define bM4_INTC_SEL121_INTSEL2 (*((volatile unsigned int*)(0x42A24808UL))) +#define bM4_INTC_SEL121_INTSEL3 (*((volatile unsigned int*)(0x42A2480CUL))) +#define bM4_INTC_SEL121_INTSEL4 (*((volatile unsigned int*)(0x42A24810UL))) +#define bM4_INTC_SEL121_INTSEL5 (*((volatile unsigned int*)(0x42A24814UL))) +#define bM4_INTC_SEL121_INTSEL6 (*((volatile unsigned int*)(0x42A24818UL))) +#define bM4_INTC_SEL121_INTSEL7 (*((volatile unsigned int*)(0x42A2481CUL))) +#define bM4_INTC_SEL121_INTSEL8 (*((volatile unsigned int*)(0x42A24820UL))) +#define bM4_INTC_SEL122_INTSEL0 (*((volatile unsigned int*)(0x42A24880UL))) +#define bM4_INTC_SEL122_INTSEL1 (*((volatile unsigned int*)(0x42A24884UL))) +#define bM4_INTC_SEL122_INTSEL2 (*((volatile unsigned int*)(0x42A24888UL))) +#define bM4_INTC_SEL122_INTSEL3 (*((volatile unsigned int*)(0x42A2488CUL))) +#define bM4_INTC_SEL122_INTSEL4 (*((volatile unsigned int*)(0x42A24890UL))) +#define bM4_INTC_SEL122_INTSEL5 (*((volatile unsigned int*)(0x42A24894UL))) +#define bM4_INTC_SEL122_INTSEL6 (*((volatile unsigned int*)(0x42A24898UL))) +#define bM4_INTC_SEL122_INTSEL7 (*((volatile unsigned int*)(0x42A2489CUL))) +#define bM4_INTC_SEL122_INTSEL8 (*((volatile unsigned int*)(0x42A248A0UL))) +#define bM4_INTC_SEL123_INTSEL0 (*((volatile unsigned int*)(0x42A24900UL))) +#define bM4_INTC_SEL123_INTSEL1 (*((volatile unsigned int*)(0x42A24904UL))) +#define bM4_INTC_SEL123_INTSEL2 (*((volatile unsigned int*)(0x42A24908UL))) +#define bM4_INTC_SEL123_INTSEL3 (*((volatile unsigned int*)(0x42A2490CUL))) +#define bM4_INTC_SEL123_INTSEL4 (*((volatile unsigned int*)(0x42A24910UL))) +#define bM4_INTC_SEL123_INTSEL5 (*((volatile unsigned int*)(0x42A24914UL))) +#define bM4_INTC_SEL123_INTSEL6 (*((volatile unsigned int*)(0x42A24918UL))) +#define bM4_INTC_SEL123_INTSEL7 (*((volatile unsigned int*)(0x42A2491CUL))) +#define bM4_INTC_SEL123_INTSEL8 (*((volatile unsigned int*)(0x42A24920UL))) +#define bM4_INTC_SEL124_INTSEL0 (*((volatile unsigned int*)(0x42A24980UL))) +#define bM4_INTC_SEL124_INTSEL1 (*((volatile unsigned int*)(0x42A24984UL))) +#define bM4_INTC_SEL124_INTSEL2 (*((volatile unsigned int*)(0x42A24988UL))) +#define bM4_INTC_SEL124_INTSEL3 (*((volatile unsigned int*)(0x42A2498CUL))) +#define bM4_INTC_SEL124_INTSEL4 (*((volatile unsigned int*)(0x42A24990UL))) +#define bM4_INTC_SEL124_INTSEL5 (*((volatile unsigned int*)(0x42A24994UL))) +#define bM4_INTC_SEL124_INTSEL6 (*((volatile unsigned int*)(0x42A24998UL))) +#define bM4_INTC_SEL124_INTSEL7 (*((volatile unsigned int*)(0x42A2499CUL))) +#define bM4_INTC_SEL124_INTSEL8 (*((volatile unsigned int*)(0x42A249A0UL))) +#define bM4_INTC_SEL125_INTSEL0 (*((volatile unsigned int*)(0x42A24A00UL))) +#define bM4_INTC_SEL125_INTSEL1 (*((volatile unsigned int*)(0x42A24A04UL))) +#define bM4_INTC_SEL125_INTSEL2 (*((volatile unsigned int*)(0x42A24A08UL))) +#define bM4_INTC_SEL125_INTSEL3 (*((volatile unsigned int*)(0x42A24A0CUL))) +#define bM4_INTC_SEL125_INTSEL4 (*((volatile unsigned int*)(0x42A24A10UL))) +#define bM4_INTC_SEL125_INTSEL5 (*((volatile unsigned int*)(0x42A24A14UL))) +#define bM4_INTC_SEL125_INTSEL6 (*((volatile unsigned int*)(0x42A24A18UL))) +#define bM4_INTC_SEL125_INTSEL7 (*((volatile unsigned int*)(0x42A24A1CUL))) +#define bM4_INTC_SEL125_INTSEL8 (*((volatile unsigned int*)(0x42A24A20UL))) +#define bM4_INTC_SEL126_INTSEL0 (*((volatile unsigned int*)(0x42A24A80UL))) +#define bM4_INTC_SEL126_INTSEL1 (*((volatile unsigned int*)(0x42A24A84UL))) +#define bM4_INTC_SEL126_INTSEL2 (*((volatile unsigned int*)(0x42A24A88UL))) +#define bM4_INTC_SEL126_INTSEL3 (*((volatile unsigned int*)(0x42A24A8CUL))) +#define bM4_INTC_SEL126_INTSEL4 (*((volatile unsigned int*)(0x42A24A90UL))) +#define bM4_INTC_SEL126_INTSEL5 (*((volatile unsigned int*)(0x42A24A94UL))) +#define bM4_INTC_SEL126_INTSEL6 (*((volatile unsigned int*)(0x42A24A98UL))) +#define bM4_INTC_SEL126_INTSEL7 (*((volatile unsigned int*)(0x42A24A9CUL))) +#define bM4_INTC_SEL126_INTSEL8 (*((volatile unsigned int*)(0x42A24AA0UL))) +#define bM4_INTC_SEL127_INTSEL0 (*((volatile unsigned int*)(0x42A24B00UL))) +#define bM4_INTC_SEL127_INTSEL1 (*((volatile unsigned int*)(0x42A24B04UL))) +#define bM4_INTC_SEL127_INTSEL2 (*((volatile unsigned int*)(0x42A24B08UL))) +#define bM4_INTC_SEL127_INTSEL3 (*((volatile unsigned int*)(0x42A24B0CUL))) +#define bM4_INTC_SEL127_INTSEL4 (*((volatile unsigned int*)(0x42A24B10UL))) +#define bM4_INTC_SEL127_INTSEL5 (*((volatile unsigned int*)(0x42A24B14UL))) +#define bM4_INTC_SEL127_INTSEL6 (*((volatile unsigned int*)(0x42A24B18UL))) +#define bM4_INTC_SEL127_INTSEL7 (*((volatile unsigned int*)(0x42A24B1CUL))) +#define bM4_INTC_SEL127_INTSEL8 (*((volatile unsigned int*)(0x42A24B20UL))) +#define bM4_INTC_VSSEL128_VSEL0 (*((volatile unsigned int*)(0x42A24B80UL))) +#define bM4_INTC_VSSEL128_VSEL1 (*((volatile unsigned int*)(0x42A24B84UL))) +#define bM4_INTC_VSSEL128_VSEL2 (*((volatile unsigned int*)(0x42A24B88UL))) +#define bM4_INTC_VSSEL128_VSEL3 (*((volatile unsigned int*)(0x42A24B8CUL))) +#define bM4_INTC_VSSEL128_VSEL4 (*((volatile unsigned int*)(0x42A24B90UL))) +#define bM4_INTC_VSSEL128_VSEL5 (*((volatile unsigned int*)(0x42A24B94UL))) +#define bM4_INTC_VSSEL128_VSEL6 (*((volatile unsigned int*)(0x42A24B98UL))) +#define bM4_INTC_VSSEL128_VSEL7 (*((volatile unsigned int*)(0x42A24B9CUL))) +#define bM4_INTC_VSSEL128_VSEL8 (*((volatile unsigned int*)(0x42A24BA0UL))) +#define bM4_INTC_VSSEL128_VSEL9 (*((volatile unsigned int*)(0x42A24BA4UL))) +#define bM4_INTC_VSSEL128_VSEL10 (*((volatile unsigned int*)(0x42A24BA8UL))) +#define bM4_INTC_VSSEL128_VSEL11 (*((volatile unsigned int*)(0x42A24BACUL))) +#define bM4_INTC_VSSEL128_VSEL12 (*((volatile unsigned int*)(0x42A24BB0UL))) +#define bM4_INTC_VSSEL128_VSEL13 (*((volatile unsigned int*)(0x42A24BB4UL))) +#define bM4_INTC_VSSEL128_VSEL14 (*((volatile unsigned int*)(0x42A24BB8UL))) +#define bM4_INTC_VSSEL128_VSEL15 (*((volatile unsigned int*)(0x42A24BBCUL))) +#define bM4_INTC_VSSEL128_VSEL16 (*((volatile unsigned int*)(0x42A24BC0UL))) +#define bM4_INTC_VSSEL128_VSEL17 (*((volatile unsigned int*)(0x42A24BC4UL))) +#define bM4_INTC_VSSEL128_VSEL18 (*((volatile unsigned int*)(0x42A24BC8UL))) +#define bM4_INTC_VSSEL128_VSEL19 (*((volatile unsigned int*)(0x42A24BCCUL))) +#define bM4_INTC_VSSEL128_VSEL20 (*((volatile unsigned int*)(0x42A24BD0UL))) +#define bM4_INTC_VSSEL128_VSEL21 (*((volatile unsigned int*)(0x42A24BD4UL))) +#define bM4_INTC_VSSEL128_VSEL22 (*((volatile unsigned int*)(0x42A24BD8UL))) +#define bM4_INTC_VSSEL128_VSEL23 (*((volatile unsigned int*)(0x42A24BDCUL))) +#define bM4_INTC_VSSEL128_VSEL24 (*((volatile unsigned int*)(0x42A24BE0UL))) +#define bM4_INTC_VSSEL128_VSEL25 (*((volatile unsigned int*)(0x42A24BE4UL))) +#define bM4_INTC_VSSEL128_VSEL26 (*((volatile unsigned int*)(0x42A24BE8UL))) +#define bM4_INTC_VSSEL128_VSEL27 (*((volatile unsigned int*)(0x42A24BECUL))) +#define bM4_INTC_VSSEL128_VSEL28 (*((volatile unsigned int*)(0x42A24BF0UL))) +#define bM4_INTC_VSSEL128_VSEL29 (*((volatile unsigned int*)(0x42A24BF4UL))) +#define bM4_INTC_VSSEL128_VSEL30 (*((volatile unsigned int*)(0x42A24BF8UL))) +#define bM4_INTC_VSSEL128_VSEL31 (*((volatile unsigned int*)(0x42A24BFCUL))) +#define bM4_INTC_VSSEL129_VSEL0 (*((volatile unsigned int*)(0x42A24C00UL))) +#define bM4_INTC_VSSEL129_VSEL1 (*((volatile unsigned int*)(0x42A24C04UL))) +#define bM4_INTC_VSSEL129_VSEL2 (*((volatile unsigned int*)(0x42A24C08UL))) +#define bM4_INTC_VSSEL129_VSEL3 (*((volatile unsigned int*)(0x42A24C0CUL))) +#define bM4_INTC_VSSEL129_VSEL4 (*((volatile unsigned int*)(0x42A24C10UL))) +#define bM4_INTC_VSSEL129_VSEL5 (*((volatile unsigned int*)(0x42A24C14UL))) +#define bM4_INTC_VSSEL129_VSEL6 (*((volatile unsigned int*)(0x42A24C18UL))) +#define bM4_INTC_VSSEL129_VSEL7 (*((volatile unsigned int*)(0x42A24C1CUL))) +#define bM4_INTC_VSSEL129_VSEL8 (*((volatile unsigned int*)(0x42A24C20UL))) +#define bM4_INTC_VSSEL129_VSEL9 (*((volatile unsigned int*)(0x42A24C24UL))) +#define bM4_INTC_VSSEL129_VSEL10 (*((volatile unsigned int*)(0x42A24C28UL))) +#define bM4_INTC_VSSEL129_VSEL11 (*((volatile unsigned int*)(0x42A24C2CUL))) +#define bM4_INTC_VSSEL129_VSEL12 (*((volatile unsigned int*)(0x42A24C30UL))) +#define bM4_INTC_VSSEL129_VSEL13 (*((volatile unsigned int*)(0x42A24C34UL))) +#define bM4_INTC_VSSEL129_VSEL14 (*((volatile unsigned int*)(0x42A24C38UL))) +#define bM4_INTC_VSSEL129_VSEL15 (*((volatile unsigned int*)(0x42A24C3CUL))) +#define bM4_INTC_VSSEL129_VSEL16 (*((volatile unsigned int*)(0x42A24C40UL))) +#define bM4_INTC_VSSEL129_VSEL17 (*((volatile unsigned int*)(0x42A24C44UL))) +#define bM4_INTC_VSSEL129_VSEL18 (*((volatile unsigned int*)(0x42A24C48UL))) +#define bM4_INTC_VSSEL129_VSEL19 (*((volatile unsigned int*)(0x42A24C4CUL))) +#define bM4_INTC_VSSEL129_VSEL20 (*((volatile unsigned int*)(0x42A24C50UL))) +#define bM4_INTC_VSSEL129_VSEL21 (*((volatile unsigned int*)(0x42A24C54UL))) +#define bM4_INTC_VSSEL129_VSEL22 (*((volatile unsigned int*)(0x42A24C58UL))) +#define bM4_INTC_VSSEL129_VSEL23 (*((volatile unsigned int*)(0x42A24C5CUL))) +#define bM4_INTC_VSSEL129_VSEL24 (*((volatile unsigned int*)(0x42A24C60UL))) +#define bM4_INTC_VSSEL129_VSEL25 (*((volatile unsigned int*)(0x42A24C64UL))) +#define bM4_INTC_VSSEL129_VSEL26 (*((volatile unsigned int*)(0x42A24C68UL))) +#define bM4_INTC_VSSEL129_VSEL27 (*((volatile unsigned int*)(0x42A24C6CUL))) +#define bM4_INTC_VSSEL129_VSEL28 (*((volatile unsigned int*)(0x42A24C70UL))) +#define bM4_INTC_VSSEL129_VSEL29 (*((volatile unsigned int*)(0x42A24C74UL))) +#define bM4_INTC_VSSEL129_VSEL30 (*((volatile unsigned int*)(0x42A24C78UL))) +#define bM4_INTC_VSSEL129_VSEL31 (*((volatile unsigned int*)(0x42A24C7CUL))) +#define bM4_INTC_VSSEL130_VSEL0 (*((volatile unsigned int*)(0x42A24C80UL))) +#define bM4_INTC_VSSEL130_VSEL1 (*((volatile unsigned int*)(0x42A24C84UL))) +#define bM4_INTC_VSSEL130_VSEL2 (*((volatile unsigned int*)(0x42A24C88UL))) +#define bM4_INTC_VSSEL130_VSEL3 (*((volatile unsigned int*)(0x42A24C8CUL))) +#define bM4_INTC_VSSEL130_VSEL4 (*((volatile unsigned int*)(0x42A24C90UL))) +#define bM4_INTC_VSSEL130_VSEL5 (*((volatile unsigned int*)(0x42A24C94UL))) +#define bM4_INTC_VSSEL130_VSEL6 (*((volatile unsigned int*)(0x42A24C98UL))) +#define bM4_INTC_VSSEL130_VSEL7 (*((volatile unsigned int*)(0x42A24C9CUL))) +#define bM4_INTC_VSSEL130_VSEL8 (*((volatile unsigned int*)(0x42A24CA0UL))) +#define bM4_INTC_VSSEL130_VSEL9 (*((volatile unsigned int*)(0x42A24CA4UL))) +#define bM4_INTC_VSSEL130_VSEL10 (*((volatile unsigned int*)(0x42A24CA8UL))) +#define bM4_INTC_VSSEL130_VSEL11 (*((volatile unsigned int*)(0x42A24CACUL))) +#define bM4_INTC_VSSEL130_VSEL12 (*((volatile unsigned int*)(0x42A24CB0UL))) +#define bM4_INTC_VSSEL130_VSEL13 (*((volatile unsigned int*)(0x42A24CB4UL))) +#define bM4_INTC_VSSEL130_VSEL14 (*((volatile unsigned int*)(0x42A24CB8UL))) +#define bM4_INTC_VSSEL130_VSEL15 (*((volatile unsigned int*)(0x42A24CBCUL))) +#define bM4_INTC_VSSEL130_VSEL16 (*((volatile unsigned int*)(0x42A24CC0UL))) +#define bM4_INTC_VSSEL130_VSEL17 (*((volatile unsigned int*)(0x42A24CC4UL))) +#define bM4_INTC_VSSEL130_VSEL18 (*((volatile unsigned int*)(0x42A24CC8UL))) +#define bM4_INTC_VSSEL130_VSEL19 (*((volatile unsigned int*)(0x42A24CCCUL))) +#define bM4_INTC_VSSEL130_VSEL20 (*((volatile unsigned int*)(0x42A24CD0UL))) +#define bM4_INTC_VSSEL130_VSEL21 (*((volatile unsigned int*)(0x42A24CD4UL))) +#define bM4_INTC_VSSEL130_VSEL22 (*((volatile unsigned int*)(0x42A24CD8UL))) +#define bM4_INTC_VSSEL130_VSEL23 (*((volatile unsigned int*)(0x42A24CDCUL))) +#define bM4_INTC_VSSEL130_VSEL24 (*((volatile unsigned int*)(0x42A24CE0UL))) +#define bM4_INTC_VSSEL130_VSEL25 (*((volatile unsigned int*)(0x42A24CE4UL))) +#define bM4_INTC_VSSEL130_VSEL26 (*((volatile unsigned int*)(0x42A24CE8UL))) +#define bM4_INTC_VSSEL130_VSEL27 (*((volatile unsigned int*)(0x42A24CECUL))) +#define bM4_INTC_VSSEL130_VSEL28 (*((volatile unsigned int*)(0x42A24CF0UL))) +#define bM4_INTC_VSSEL130_VSEL29 (*((volatile unsigned int*)(0x42A24CF4UL))) +#define bM4_INTC_VSSEL130_VSEL30 (*((volatile unsigned int*)(0x42A24CF8UL))) +#define bM4_INTC_VSSEL130_VSEL31 (*((volatile unsigned int*)(0x42A24CFCUL))) +#define bM4_INTC_VSSEL131_VSEL0 (*((volatile unsigned int*)(0x42A24D00UL))) +#define bM4_INTC_VSSEL131_VSEL1 (*((volatile unsigned int*)(0x42A24D04UL))) +#define bM4_INTC_VSSEL131_VSEL2 (*((volatile unsigned int*)(0x42A24D08UL))) +#define bM4_INTC_VSSEL131_VSEL3 (*((volatile unsigned int*)(0x42A24D0CUL))) +#define bM4_INTC_VSSEL131_VSEL4 (*((volatile unsigned int*)(0x42A24D10UL))) +#define bM4_INTC_VSSEL131_VSEL5 (*((volatile unsigned int*)(0x42A24D14UL))) +#define bM4_INTC_VSSEL131_VSEL6 (*((volatile unsigned int*)(0x42A24D18UL))) +#define bM4_INTC_VSSEL131_VSEL7 (*((volatile unsigned int*)(0x42A24D1CUL))) +#define bM4_INTC_VSSEL131_VSEL8 (*((volatile unsigned int*)(0x42A24D20UL))) +#define bM4_INTC_VSSEL131_VSEL9 (*((volatile unsigned int*)(0x42A24D24UL))) +#define bM4_INTC_VSSEL131_VSEL10 (*((volatile unsigned int*)(0x42A24D28UL))) +#define bM4_INTC_VSSEL131_VSEL11 (*((volatile unsigned int*)(0x42A24D2CUL))) +#define bM4_INTC_VSSEL131_VSEL12 (*((volatile unsigned int*)(0x42A24D30UL))) +#define bM4_INTC_VSSEL131_VSEL13 (*((volatile unsigned int*)(0x42A24D34UL))) +#define bM4_INTC_VSSEL131_VSEL14 (*((volatile unsigned int*)(0x42A24D38UL))) +#define bM4_INTC_VSSEL131_VSEL15 (*((volatile unsigned int*)(0x42A24D3CUL))) +#define bM4_INTC_VSSEL131_VSEL16 (*((volatile unsigned int*)(0x42A24D40UL))) +#define bM4_INTC_VSSEL131_VSEL17 (*((volatile unsigned int*)(0x42A24D44UL))) +#define bM4_INTC_VSSEL131_VSEL18 (*((volatile unsigned int*)(0x42A24D48UL))) +#define bM4_INTC_VSSEL131_VSEL19 (*((volatile unsigned int*)(0x42A24D4CUL))) +#define bM4_INTC_VSSEL131_VSEL20 (*((volatile unsigned int*)(0x42A24D50UL))) +#define bM4_INTC_VSSEL131_VSEL21 (*((volatile unsigned int*)(0x42A24D54UL))) +#define bM4_INTC_VSSEL131_VSEL22 (*((volatile unsigned int*)(0x42A24D58UL))) +#define bM4_INTC_VSSEL131_VSEL23 (*((volatile unsigned int*)(0x42A24D5CUL))) +#define bM4_INTC_VSSEL131_VSEL24 (*((volatile unsigned int*)(0x42A24D60UL))) +#define bM4_INTC_VSSEL131_VSEL25 (*((volatile unsigned int*)(0x42A24D64UL))) +#define bM4_INTC_VSSEL131_VSEL26 (*((volatile unsigned int*)(0x42A24D68UL))) +#define bM4_INTC_VSSEL131_VSEL27 (*((volatile unsigned int*)(0x42A24D6CUL))) +#define bM4_INTC_VSSEL131_VSEL28 (*((volatile unsigned int*)(0x42A24D70UL))) +#define bM4_INTC_VSSEL131_VSEL29 (*((volatile unsigned int*)(0x42A24D74UL))) +#define bM4_INTC_VSSEL131_VSEL30 (*((volatile unsigned int*)(0x42A24D78UL))) +#define bM4_INTC_VSSEL131_VSEL31 (*((volatile unsigned int*)(0x42A24D7CUL))) +#define bM4_INTC_VSSEL132_VSEL0 (*((volatile unsigned int*)(0x42A24D80UL))) +#define bM4_INTC_VSSEL132_VSEL1 (*((volatile unsigned int*)(0x42A24D84UL))) +#define bM4_INTC_VSSEL132_VSEL2 (*((volatile unsigned int*)(0x42A24D88UL))) +#define bM4_INTC_VSSEL132_VSEL3 (*((volatile unsigned int*)(0x42A24D8CUL))) +#define bM4_INTC_VSSEL132_VSEL4 (*((volatile unsigned int*)(0x42A24D90UL))) +#define bM4_INTC_VSSEL132_VSEL5 (*((volatile unsigned int*)(0x42A24D94UL))) +#define bM4_INTC_VSSEL132_VSEL6 (*((volatile unsigned int*)(0x42A24D98UL))) +#define bM4_INTC_VSSEL132_VSEL7 (*((volatile unsigned int*)(0x42A24D9CUL))) +#define bM4_INTC_VSSEL132_VSEL8 (*((volatile unsigned int*)(0x42A24DA0UL))) +#define bM4_INTC_VSSEL132_VSEL9 (*((volatile unsigned int*)(0x42A24DA4UL))) +#define bM4_INTC_VSSEL132_VSEL10 (*((volatile unsigned int*)(0x42A24DA8UL))) +#define bM4_INTC_VSSEL132_VSEL11 (*((volatile unsigned int*)(0x42A24DACUL))) +#define bM4_INTC_VSSEL132_VSEL12 (*((volatile unsigned int*)(0x42A24DB0UL))) +#define bM4_INTC_VSSEL132_VSEL13 (*((volatile unsigned int*)(0x42A24DB4UL))) +#define bM4_INTC_VSSEL132_VSEL14 (*((volatile unsigned int*)(0x42A24DB8UL))) +#define bM4_INTC_VSSEL132_VSEL15 (*((volatile unsigned int*)(0x42A24DBCUL))) +#define bM4_INTC_VSSEL132_VSEL16 (*((volatile unsigned int*)(0x42A24DC0UL))) +#define bM4_INTC_VSSEL132_VSEL17 (*((volatile unsigned int*)(0x42A24DC4UL))) +#define bM4_INTC_VSSEL132_VSEL18 (*((volatile unsigned int*)(0x42A24DC8UL))) +#define bM4_INTC_VSSEL132_VSEL19 (*((volatile unsigned int*)(0x42A24DCCUL))) +#define bM4_INTC_VSSEL132_VSEL20 (*((volatile unsigned int*)(0x42A24DD0UL))) +#define bM4_INTC_VSSEL132_VSEL21 (*((volatile unsigned int*)(0x42A24DD4UL))) +#define bM4_INTC_VSSEL132_VSEL22 (*((volatile unsigned int*)(0x42A24DD8UL))) +#define bM4_INTC_VSSEL132_VSEL23 (*((volatile unsigned int*)(0x42A24DDCUL))) +#define bM4_INTC_VSSEL132_VSEL24 (*((volatile unsigned int*)(0x42A24DE0UL))) +#define bM4_INTC_VSSEL132_VSEL25 (*((volatile unsigned int*)(0x42A24DE4UL))) +#define bM4_INTC_VSSEL132_VSEL26 (*((volatile unsigned int*)(0x42A24DE8UL))) +#define bM4_INTC_VSSEL132_VSEL27 (*((volatile unsigned int*)(0x42A24DECUL))) +#define bM4_INTC_VSSEL132_VSEL28 (*((volatile unsigned int*)(0x42A24DF0UL))) +#define bM4_INTC_VSSEL132_VSEL29 (*((volatile unsigned int*)(0x42A24DF4UL))) +#define bM4_INTC_VSSEL132_VSEL30 (*((volatile unsigned int*)(0x42A24DF8UL))) +#define bM4_INTC_VSSEL132_VSEL31 (*((volatile unsigned int*)(0x42A24DFCUL))) +#define bM4_INTC_VSSEL133_VSEL0 (*((volatile unsigned int*)(0x42A24E00UL))) +#define bM4_INTC_VSSEL133_VSEL1 (*((volatile unsigned int*)(0x42A24E04UL))) +#define bM4_INTC_VSSEL133_VSEL2 (*((volatile unsigned int*)(0x42A24E08UL))) +#define bM4_INTC_VSSEL133_VSEL3 (*((volatile unsigned int*)(0x42A24E0CUL))) +#define bM4_INTC_VSSEL133_VSEL4 (*((volatile unsigned int*)(0x42A24E10UL))) +#define bM4_INTC_VSSEL133_VSEL5 (*((volatile unsigned int*)(0x42A24E14UL))) +#define bM4_INTC_VSSEL133_VSEL6 (*((volatile unsigned int*)(0x42A24E18UL))) +#define bM4_INTC_VSSEL133_VSEL7 (*((volatile unsigned int*)(0x42A24E1CUL))) +#define bM4_INTC_VSSEL133_VSEL8 (*((volatile unsigned int*)(0x42A24E20UL))) +#define bM4_INTC_VSSEL133_VSEL9 (*((volatile unsigned int*)(0x42A24E24UL))) +#define bM4_INTC_VSSEL133_VSEL10 (*((volatile unsigned int*)(0x42A24E28UL))) +#define bM4_INTC_VSSEL133_VSEL11 (*((volatile unsigned int*)(0x42A24E2CUL))) +#define bM4_INTC_VSSEL133_VSEL12 (*((volatile unsigned int*)(0x42A24E30UL))) +#define bM4_INTC_VSSEL133_VSEL13 (*((volatile unsigned int*)(0x42A24E34UL))) +#define bM4_INTC_VSSEL133_VSEL14 (*((volatile unsigned int*)(0x42A24E38UL))) +#define bM4_INTC_VSSEL133_VSEL15 (*((volatile unsigned int*)(0x42A24E3CUL))) +#define bM4_INTC_VSSEL133_VSEL16 (*((volatile unsigned int*)(0x42A24E40UL))) +#define bM4_INTC_VSSEL133_VSEL17 (*((volatile unsigned int*)(0x42A24E44UL))) +#define bM4_INTC_VSSEL133_VSEL18 (*((volatile unsigned int*)(0x42A24E48UL))) +#define bM4_INTC_VSSEL133_VSEL19 (*((volatile unsigned int*)(0x42A24E4CUL))) +#define bM4_INTC_VSSEL133_VSEL20 (*((volatile unsigned int*)(0x42A24E50UL))) +#define bM4_INTC_VSSEL133_VSEL21 (*((volatile unsigned int*)(0x42A24E54UL))) +#define bM4_INTC_VSSEL133_VSEL22 (*((volatile unsigned int*)(0x42A24E58UL))) +#define bM4_INTC_VSSEL133_VSEL23 (*((volatile unsigned int*)(0x42A24E5CUL))) +#define bM4_INTC_VSSEL133_VSEL24 (*((volatile unsigned int*)(0x42A24E60UL))) +#define bM4_INTC_VSSEL133_VSEL25 (*((volatile unsigned int*)(0x42A24E64UL))) +#define bM4_INTC_VSSEL133_VSEL26 (*((volatile unsigned int*)(0x42A24E68UL))) +#define bM4_INTC_VSSEL133_VSEL27 (*((volatile unsigned int*)(0x42A24E6CUL))) +#define bM4_INTC_VSSEL133_VSEL28 (*((volatile unsigned int*)(0x42A24E70UL))) +#define bM4_INTC_VSSEL133_VSEL29 (*((volatile unsigned int*)(0x42A24E74UL))) +#define bM4_INTC_VSSEL133_VSEL30 (*((volatile unsigned int*)(0x42A24E78UL))) +#define bM4_INTC_VSSEL133_VSEL31 (*((volatile unsigned int*)(0x42A24E7CUL))) +#define bM4_INTC_VSSEL134_VSEL0 (*((volatile unsigned int*)(0x42A24E80UL))) +#define bM4_INTC_VSSEL134_VSEL1 (*((volatile unsigned int*)(0x42A24E84UL))) +#define bM4_INTC_VSSEL134_VSEL2 (*((volatile unsigned int*)(0x42A24E88UL))) +#define bM4_INTC_VSSEL134_VSEL3 (*((volatile unsigned int*)(0x42A24E8CUL))) +#define bM4_INTC_VSSEL134_VSEL4 (*((volatile unsigned int*)(0x42A24E90UL))) +#define bM4_INTC_VSSEL134_VSEL5 (*((volatile unsigned int*)(0x42A24E94UL))) +#define bM4_INTC_VSSEL134_VSEL6 (*((volatile unsigned int*)(0x42A24E98UL))) +#define bM4_INTC_VSSEL134_VSEL7 (*((volatile unsigned int*)(0x42A24E9CUL))) +#define bM4_INTC_VSSEL134_VSEL8 (*((volatile unsigned int*)(0x42A24EA0UL))) +#define bM4_INTC_VSSEL134_VSEL9 (*((volatile unsigned int*)(0x42A24EA4UL))) +#define bM4_INTC_VSSEL134_VSEL10 (*((volatile unsigned int*)(0x42A24EA8UL))) +#define bM4_INTC_VSSEL134_VSEL11 (*((volatile unsigned int*)(0x42A24EACUL))) +#define bM4_INTC_VSSEL134_VSEL12 (*((volatile unsigned int*)(0x42A24EB0UL))) +#define bM4_INTC_VSSEL134_VSEL13 (*((volatile unsigned int*)(0x42A24EB4UL))) +#define bM4_INTC_VSSEL134_VSEL14 (*((volatile unsigned int*)(0x42A24EB8UL))) +#define bM4_INTC_VSSEL134_VSEL15 (*((volatile unsigned int*)(0x42A24EBCUL))) +#define bM4_INTC_VSSEL134_VSEL16 (*((volatile unsigned int*)(0x42A24EC0UL))) +#define bM4_INTC_VSSEL134_VSEL17 (*((volatile unsigned int*)(0x42A24EC4UL))) +#define bM4_INTC_VSSEL134_VSEL18 (*((volatile unsigned int*)(0x42A24EC8UL))) +#define bM4_INTC_VSSEL134_VSEL19 (*((volatile unsigned int*)(0x42A24ECCUL))) +#define bM4_INTC_VSSEL134_VSEL20 (*((volatile unsigned int*)(0x42A24ED0UL))) +#define bM4_INTC_VSSEL134_VSEL21 (*((volatile unsigned int*)(0x42A24ED4UL))) +#define bM4_INTC_VSSEL134_VSEL22 (*((volatile unsigned int*)(0x42A24ED8UL))) +#define bM4_INTC_VSSEL134_VSEL23 (*((volatile unsigned int*)(0x42A24EDCUL))) +#define bM4_INTC_VSSEL134_VSEL24 (*((volatile unsigned int*)(0x42A24EE0UL))) +#define bM4_INTC_VSSEL134_VSEL25 (*((volatile unsigned int*)(0x42A24EE4UL))) +#define bM4_INTC_VSSEL134_VSEL26 (*((volatile unsigned int*)(0x42A24EE8UL))) +#define bM4_INTC_VSSEL134_VSEL27 (*((volatile unsigned int*)(0x42A24EECUL))) +#define bM4_INTC_VSSEL134_VSEL28 (*((volatile unsigned int*)(0x42A24EF0UL))) +#define bM4_INTC_VSSEL134_VSEL29 (*((volatile unsigned int*)(0x42A24EF4UL))) +#define bM4_INTC_VSSEL134_VSEL30 (*((volatile unsigned int*)(0x42A24EF8UL))) +#define bM4_INTC_VSSEL134_VSEL31 (*((volatile unsigned int*)(0x42A24EFCUL))) +#define bM4_INTC_VSSEL135_VSEL0 (*((volatile unsigned int*)(0x42A24F00UL))) +#define bM4_INTC_VSSEL135_VSEL1 (*((volatile unsigned int*)(0x42A24F04UL))) +#define bM4_INTC_VSSEL135_VSEL2 (*((volatile unsigned int*)(0x42A24F08UL))) +#define bM4_INTC_VSSEL135_VSEL3 (*((volatile unsigned int*)(0x42A24F0CUL))) +#define bM4_INTC_VSSEL135_VSEL4 (*((volatile unsigned int*)(0x42A24F10UL))) +#define bM4_INTC_VSSEL135_VSEL5 (*((volatile unsigned int*)(0x42A24F14UL))) +#define bM4_INTC_VSSEL135_VSEL6 (*((volatile unsigned int*)(0x42A24F18UL))) +#define bM4_INTC_VSSEL135_VSEL7 (*((volatile unsigned int*)(0x42A24F1CUL))) +#define bM4_INTC_VSSEL135_VSEL8 (*((volatile unsigned int*)(0x42A24F20UL))) +#define bM4_INTC_VSSEL135_VSEL9 (*((volatile unsigned int*)(0x42A24F24UL))) +#define bM4_INTC_VSSEL135_VSEL10 (*((volatile unsigned int*)(0x42A24F28UL))) +#define bM4_INTC_VSSEL135_VSEL11 (*((volatile unsigned int*)(0x42A24F2CUL))) +#define bM4_INTC_VSSEL135_VSEL12 (*((volatile unsigned int*)(0x42A24F30UL))) +#define bM4_INTC_VSSEL135_VSEL13 (*((volatile unsigned int*)(0x42A24F34UL))) +#define bM4_INTC_VSSEL135_VSEL14 (*((volatile unsigned int*)(0x42A24F38UL))) +#define bM4_INTC_VSSEL135_VSEL15 (*((volatile unsigned int*)(0x42A24F3CUL))) +#define bM4_INTC_VSSEL135_VSEL16 (*((volatile unsigned int*)(0x42A24F40UL))) +#define bM4_INTC_VSSEL135_VSEL17 (*((volatile unsigned int*)(0x42A24F44UL))) +#define bM4_INTC_VSSEL135_VSEL18 (*((volatile unsigned int*)(0x42A24F48UL))) +#define bM4_INTC_VSSEL135_VSEL19 (*((volatile unsigned int*)(0x42A24F4CUL))) +#define bM4_INTC_VSSEL135_VSEL20 (*((volatile unsigned int*)(0x42A24F50UL))) +#define bM4_INTC_VSSEL135_VSEL21 (*((volatile unsigned int*)(0x42A24F54UL))) +#define bM4_INTC_VSSEL135_VSEL22 (*((volatile unsigned int*)(0x42A24F58UL))) +#define bM4_INTC_VSSEL135_VSEL23 (*((volatile unsigned int*)(0x42A24F5CUL))) +#define bM4_INTC_VSSEL135_VSEL24 (*((volatile unsigned int*)(0x42A24F60UL))) +#define bM4_INTC_VSSEL135_VSEL25 (*((volatile unsigned int*)(0x42A24F64UL))) +#define bM4_INTC_VSSEL135_VSEL26 (*((volatile unsigned int*)(0x42A24F68UL))) +#define bM4_INTC_VSSEL135_VSEL27 (*((volatile unsigned int*)(0x42A24F6CUL))) +#define bM4_INTC_VSSEL135_VSEL28 (*((volatile unsigned int*)(0x42A24F70UL))) +#define bM4_INTC_VSSEL135_VSEL29 (*((volatile unsigned int*)(0x42A24F74UL))) +#define bM4_INTC_VSSEL135_VSEL30 (*((volatile unsigned int*)(0x42A24F78UL))) +#define bM4_INTC_VSSEL135_VSEL31 (*((volatile unsigned int*)(0x42A24F7CUL))) +#define bM4_INTC_VSSEL136_VSEL0 (*((volatile unsigned int*)(0x42A24F80UL))) +#define bM4_INTC_VSSEL136_VSEL1 (*((volatile unsigned int*)(0x42A24F84UL))) +#define bM4_INTC_VSSEL136_VSEL2 (*((volatile unsigned int*)(0x42A24F88UL))) +#define bM4_INTC_VSSEL136_VSEL3 (*((volatile unsigned int*)(0x42A24F8CUL))) +#define bM4_INTC_VSSEL136_VSEL4 (*((volatile unsigned int*)(0x42A24F90UL))) +#define bM4_INTC_VSSEL136_VSEL5 (*((volatile unsigned int*)(0x42A24F94UL))) +#define bM4_INTC_VSSEL136_VSEL6 (*((volatile unsigned int*)(0x42A24F98UL))) +#define bM4_INTC_VSSEL136_VSEL7 (*((volatile unsigned int*)(0x42A24F9CUL))) +#define bM4_INTC_VSSEL136_VSEL8 (*((volatile unsigned int*)(0x42A24FA0UL))) +#define bM4_INTC_VSSEL136_VSEL9 (*((volatile unsigned int*)(0x42A24FA4UL))) +#define bM4_INTC_VSSEL136_VSEL10 (*((volatile unsigned int*)(0x42A24FA8UL))) +#define bM4_INTC_VSSEL136_VSEL11 (*((volatile unsigned int*)(0x42A24FACUL))) +#define bM4_INTC_VSSEL136_VSEL12 (*((volatile unsigned int*)(0x42A24FB0UL))) +#define bM4_INTC_VSSEL136_VSEL13 (*((volatile unsigned int*)(0x42A24FB4UL))) +#define bM4_INTC_VSSEL136_VSEL14 (*((volatile unsigned int*)(0x42A24FB8UL))) +#define bM4_INTC_VSSEL136_VSEL15 (*((volatile unsigned int*)(0x42A24FBCUL))) +#define bM4_INTC_VSSEL136_VSEL16 (*((volatile unsigned int*)(0x42A24FC0UL))) +#define bM4_INTC_VSSEL136_VSEL17 (*((volatile unsigned int*)(0x42A24FC4UL))) +#define bM4_INTC_VSSEL136_VSEL18 (*((volatile unsigned int*)(0x42A24FC8UL))) +#define bM4_INTC_VSSEL136_VSEL19 (*((volatile unsigned int*)(0x42A24FCCUL))) +#define bM4_INTC_VSSEL136_VSEL20 (*((volatile unsigned int*)(0x42A24FD0UL))) +#define bM4_INTC_VSSEL136_VSEL21 (*((volatile unsigned int*)(0x42A24FD4UL))) +#define bM4_INTC_VSSEL136_VSEL22 (*((volatile unsigned int*)(0x42A24FD8UL))) +#define bM4_INTC_VSSEL136_VSEL23 (*((volatile unsigned int*)(0x42A24FDCUL))) +#define bM4_INTC_VSSEL136_VSEL24 (*((volatile unsigned int*)(0x42A24FE0UL))) +#define bM4_INTC_VSSEL136_VSEL25 (*((volatile unsigned int*)(0x42A24FE4UL))) +#define bM4_INTC_VSSEL136_VSEL26 (*((volatile unsigned int*)(0x42A24FE8UL))) +#define bM4_INTC_VSSEL136_VSEL27 (*((volatile unsigned int*)(0x42A24FECUL))) +#define bM4_INTC_VSSEL136_VSEL28 (*((volatile unsigned int*)(0x42A24FF0UL))) +#define bM4_INTC_VSSEL136_VSEL29 (*((volatile unsigned int*)(0x42A24FF4UL))) +#define bM4_INTC_VSSEL136_VSEL30 (*((volatile unsigned int*)(0x42A24FF8UL))) +#define bM4_INTC_VSSEL136_VSEL31 (*((volatile unsigned int*)(0x42A24FFCUL))) +#define bM4_INTC_VSSEL137_VSEL0 (*((volatile unsigned int*)(0x42A25000UL))) +#define bM4_INTC_VSSEL137_VSEL1 (*((volatile unsigned int*)(0x42A25004UL))) +#define bM4_INTC_VSSEL137_VSEL2 (*((volatile unsigned int*)(0x42A25008UL))) +#define bM4_INTC_VSSEL137_VSEL3 (*((volatile unsigned int*)(0x42A2500CUL))) +#define bM4_INTC_VSSEL137_VSEL4 (*((volatile unsigned int*)(0x42A25010UL))) +#define bM4_INTC_VSSEL137_VSEL5 (*((volatile unsigned int*)(0x42A25014UL))) +#define bM4_INTC_VSSEL137_VSEL6 (*((volatile unsigned int*)(0x42A25018UL))) +#define bM4_INTC_VSSEL137_VSEL7 (*((volatile unsigned int*)(0x42A2501CUL))) +#define bM4_INTC_VSSEL137_VSEL8 (*((volatile unsigned int*)(0x42A25020UL))) +#define bM4_INTC_VSSEL137_VSEL9 (*((volatile unsigned int*)(0x42A25024UL))) +#define bM4_INTC_VSSEL137_VSEL10 (*((volatile unsigned int*)(0x42A25028UL))) +#define bM4_INTC_VSSEL137_VSEL11 (*((volatile unsigned int*)(0x42A2502CUL))) +#define bM4_INTC_VSSEL137_VSEL12 (*((volatile unsigned int*)(0x42A25030UL))) +#define bM4_INTC_VSSEL137_VSEL13 (*((volatile unsigned int*)(0x42A25034UL))) +#define bM4_INTC_VSSEL137_VSEL14 (*((volatile unsigned int*)(0x42A25038UL))) +#define bM4_INTC_VSSEL137_VSEL15 (*((volatile unsigned int*)(0x42A2503CUL))) +#define bM4_INTC_VSSEL137_VSEL16 (*((volatile unsigned int*)(0x42A25040UL))) +#define bM4_INTC_VSSEL137_VSEL17 (*((volatile unsigned int*)(0x42A25044UL))) +#define bM4_INTC_VSSEL137_VSEL18 (*((volatile unsigned int*)(0x42A25048UL))) +#define bM4_INTC_VSSEL137_VSEL19 (*((volatile unsigned int*)(0x42A2504CUL))) +#define bM4_INTC_VSSEL137_VSEL20 (*((volatile unsigned int*)(0x42A25050UL))) +#define bM4_INTC_VSSEL137_VSEL21 (*((volatile unsigned int*)(0x42A25054UL))) +#define bM4_INTC_VSSEL137_VSEL22 (*((volatile unsigned int*)(0x42A25058UL))) +#define bM4_INTC_VSSEL137_VSEL23 (*((volatile unsigned int*)(0x42A2505CUL))) +#define bM4_INTC_VSSEL137_VSEL24 (*((volatile unsigned int*)(0x42A25060UL))) +#define bM4_INTC_VSSEL137_VSEL25 (*((volatile unsigned int*)(0x42A25064UL))) +#define bM4_INTC_VSSEL137_VSEL26 (*((volatile unsigned int*)(0x42A25068UL))) +#define bM4_INTC_VSSEL137_VSEL27 (*((volatile unsigned int*)(0x42A2506CUL))) +#define bM4_INTC_VSSEL137_VSEL28 (*((volatile unsigned int*)(0x42A25070UL))) +#define bM4_INTC_VSSEL137_VSEL29 (*((volatile unsigned int*)(0x42A25074UL))) +#define bM4_INTC_VSSEL137_VSEL30 (*((volatile unsigned int*)(0x42A25078UL))) +#define bM4_INTC_VSSEL137_VSEL31 (*((volatile unsigned int*)(0x42A2507CUL))) +#define bM4_INTC_VSSEL138_VSEL0 (*((volatile unsigned int*)(0x42A25080UL))) +#define bM4_INTC_VSSEL138_VSEL1 (*((volatile unsigned int*)(0x42A25084UL))) +#define bM4_INTC_VSSEL138_VSEL2 (*((volatile unsigned int*)(0x42A25088UL))) +#define bM4_INTC_VSSEL138_VSEL3 (*((volatile unsigned int*)(0x42A2508CUL))) +#define bM4_INTC_VSSEL138_VSEL4 (*((volatile unsigned int*)(0x42A25090UL))) +#define bM4_INTC_VSSEL138_VSEL5 (*((volatile unsigned int*)(0x42A25094UL))) +#define bM4_INTC_VSSEL138_VSEL6 (*((volatile unsigned int*)(0x42A25098UL))) +#define bM4_INTC_VSSEL138_VSEL7 (*((volatile unsigned int*)(0x42A2509CUL))) +#define bM4_INTC_VSSEL138_VSEL8 (*((volatile unsigned int*)(0x42A250A0UL))) +#define bM4_INTC_VSSEL138_VSEL9 (*((volatile unsigned int*)(0x42A250A4UL))) +#define bM4_INTC_VSSEL138_VSEL10 (*((volatile unsigned int*)(0x42A250A8UL))) +#define bM4_INTC_VSSEL138_VSEL11 (*((volatile unsigned int*)(0x42A250ACUL))) +#define bM4_INTC_VSSEL138_VSEL12 (*((volatile unsigned int*)(0x42A250B0UL))) +#define bM4_INTC_VSSEL138_VSEL13 (*((volatile unsigned int*)(0x42A250B4UL))) +#define bM4_INTC_VSSEL138_VSEL14 (*((volatile unsigned int*)(0x42A250B8UL))) +#define bM4_INTC_VSSEL138_VSEL15 (*((volatile unsigned int*)(0x42A250BCUL))) +#define bM4_INTC_VSSEL138_VSEL16 (*((volatile unsigned int*)(0x42A250C0UL))) +#define bM4_INTC_VSSEL138_VSEL17 (*((volatile unsigned int*)(0x42A250C4UL))) +#define bM4_INTC_VSSEL138_VSEL18 (*((volatile unsigned int*)(0x42A250C8UL))) +#define bM4_INTC_VSSEL138_VSEL19 (*((volatile unsigned int*)(0x42A250CCUL))) +#define bM4_INTC_VSSEL138_VSEL20 (*((volatile unsigned int*)(0x42A250D0UL))) +#define bM4_INTC_VSSEL138_VSEL21 (*((volatile unsigned int*)(0x42A250D4UL))) +#define bM4_INTC_VSSEL138_VSEL22 (*((volatile unsigned int*)(0x42A250D8UL))) +#define bM4_INTC_VSSEL138_VSEL23 (*((volatile unsigned int*)(0x42A250DCUL))) +#define bM4_INTC_VSSEL138_VSEL24 (*((volatile unsigned int*)(0x42A250E0UL))) +#define bM4_INTC_VSSEL138_VSEL25 (*((volatile unsigned int*)(0x42A250E4UL))) +#define bM4_INTC_VSSEL138_VSEL26 (*((volatile unsigned int*)(0x42A250E8UL))) +#define bM4_INTC_VSSEL138_VSEL27 (*((volatile unsigned int*)(0x42A250ECUL))) +#define bM4_INTC_VSSEL138_VSEL28 (*((volatile unsigned int*)(0x42A250F0UL))) +#define bM4_INTC_VSSEL138_VSEL29 (*((volatile unsigned int*)(0x42A250F4UL))) +#define bM4_INTC_VSSEL138_VSEL30 (*((volatile unsigned int*)(0x42A250F8UL))) +#define bM4_INTC_VSSEL138_VSEL31 (*((volatile unsigned int*)(0x42A250FCUL))) +#define bM4_INTC_VSSEL139_VSEL0 (*((volatile unsigned int*)(0x42A25100UL))) +#define bM4_INTC_VSSEL139_VSEL1 (*((volatile unsigned int*)(0x42A25104UL))) +#define bM4_INTC_VSSEL139_VSEL2 (*((volatile unsigned int*)(0x42A25108UL))) +#define bM4_INTC_VSSEL139_VSEL3 (*((volatile unsigned int*)(0x42A2510CUL))) +#define bM4_INTC_VSSEL139_VSEL4 (*((volatile unsigned int*)(0x42A25110UL))) +#define bM4_INTC_VSSEL139_VSEL5 (*((volatile unsigned int*)(0x42A25114UL))) +#define bM4_INTC_VSSEL139_VSEL6 (*((volatile unsigned int*)(0x42A25118UL))) +#define bM4_INTC_VSSEL139_VSEL7 (*((volatile unsigned int*)(0x42A2511CUL))) +#define bM4_INTC_VSSEL139_VSEL8 (*((volatile unsigned int*)(0x42A25120UL))) +#define bM4_INTC_VSSEL139_VSEL9 (*((volatile unsigned int*)(0x42A25124UL))) +#define bM4_INTC_VSSEL139_VSEL10 (*((volatile unsigned int*)(0x42A25128UL))) +#define bM4_INTC_VSSEL139_VSEL11 (*((volatile unsigned int*)(0x42A2512CUL))) +#define bM4_INTC_VSSEL139_VSEL12 (*((volatile unsigned int*)(0x42A25130UL))) +#define bM4_INTC_VSSEL139_VSEL13 (*((volatile unsigned int*)(0x42A25134UL))) +#define bM4_INTC_VSSEL139_VSEL14 (*((volatile unsigned int*)(0x42A25138UL))) +#define bM4_INTC_VSSEL139_VSEL15 (*((volatile unsigned int*)(0x42A2513CUL))) +#define bM4_INTC_VSSEL139_VSEL16 (*((volatile unsigned int*)(0x42A25140UL))) +#define bM4_INTC_VSSEL139_VSEL17 (*((volatile unsigned int*)(0x42A25144UL))) +#define bM4_INTC_VSSEL139_VSEL18 (*((volatile unsigned int*)(0x42A25148UL))) +#define bM4_INTC_VSSEL139_VSEL19 (*((volatile unsigned int*)(0x42A2514CUL))) +#define bM4_INTC_VSSEL139_VSEL20 (*((volatile unsigned int*)(0x42A25150UL))) +#define bM4_INTC_VSSEL139_VSEL21 (*((volatile unsigned int*)(0x42A25154UL))) +#define bM4_INTC_VSSEL139_VSEL22 (*((volatile unsigned int*)(0x42A25158UL))) +#define bM4_INTC_VSSEL139_VSEL23 (*((volatile unsigned int*)(0x42A2515CUL))) +#define bM4_INTC_VSSEL139_VSEL24 (*((volatile unsigned int*)(0x42A25160UL))) +#define bM4_INTC_VSSEL139_VSEL25 (*((volatile unsigned int*)(0x42A25164UL))) +#define bM4_INTC_VSSEL139_VSEL26 (*((volatile unsigned int*)(0x42A25168UL))) +#define bM4_INTC_VSSEL139_VSEL27 (*((volatile unsigned int*)(0x42A2516CUL))) +#define bM4_INTC_VSSEL139_VSEL28 (*((volatile unsigned int*)(0x42A25170UL))) +#define bM4_INTC_VSSEL139_VSEL29 (*((volatile unsigned int*)(0x42A25174UL))) +#define bM4_INTC_VSSEL139_VSEL30 (*((volatile unsigned int*)(0x42A25178UL))) +#define bM4_INTC_VSSEL139_VSEL31 (*((volatile unsigned int*)(0x42A2517CUL))) +#define bM4_INTC_VSSEL140_VSEL0 (*((volatile unsigned int*)(0x42A25180UL))) +#define bM4_INTC_VSSEL140_VSEL1 (*((volatile unsigned int*)(0x42A25184UL))) +#define bM4_INTC_VSSEL140_VSEL2 (*((volatile unsigned int*)(0x42A25188UL))) +#define bM4_INTC_VSSEL140_VSEL3 (*((volatile unsigned int*)(0x42A2518CUL))) +#define bM4_INTC_VSSEL140_VSEL4 (*((volatile unsigned int*)(0x42A25190UL))) +#define bM4_INTC_VSSEL140_VSEL5 (*((volatile unsigned int*)(0x42A25194UL))) +#define bM4_INTC_VSSEL140_VSEL6 (*((volatile unsigned int*)(0x42A25198UL))) +#define bM4_INTC_VSSEL140_VSEL7 (*((volatile unsigned int*)(0x42A2519CUL))) +#define bM4_INTC_VSSEL140_VSEL8 (*((volatile unsigned int*)(0x42A251A0UL))) +#define bM4_INTC_VSSEL140_VSEL9 (*((volatile unsigned int*)(0x42A251A4UL))) +#define bM4_INTC_VSSEL140_VSEL10 (*((volatile unsigned int*)(0x42A251A8UL))) +#define bM4_INTC_VSSEL140_VSEL11 (*((volatile unsigned int*)(0x42A251ACUL))) +#define bM4_INTC_VSSEL140_VSEL12 (*((volatile unsigned int*)(0x42A251B0UL))) +#define bM4_INTC_VSSEL140_VSEL13 (*((volatile unsigned int*)(0x42A251B4UL))) +#define bM4_INTC_VSSEL140_VSEL14 (*((volatile unsigned int*)(0x42A251B8UL))) +#define bM4_INTC_VSSEL140_VSEL15 (*((volatile unsigned int*)(0x42A251BCUL))) +#define bM4_INTC_VSSEL140_VSEL16 (*((volatile unsigned int*)(0x42A251C0UL))) +#define bM4_INTC_VSSEL140_VSEL17 (*((volatile unsigned int*)(0x42A251C4UL))) +#define bM4_INTC_VSSEL140_VSEL18 (*((volatile unsigned int*)(0x42A251C8UL))) +#define bM4_INTC_VSSEL140_VSEL19 (*((volatile unsigned int*)(0x42A251CCUL))) +#define bM4_INTC_VSSEL140_VSEL20 (*((volatile unsigned int*)(0x42A251D0UL))) +#define bM4_INTC_VSSEL140_VSEL21 (*((volatile unsigned int*)(0x42A251D4UL))) +#define bM4_INTC_VSSEL140_VSEL22 (*((volatile unsigned int*)(0x42A251D8UL))) +#define bM4_INTC_VSSEL140_VSEL23 (*((volatile unsigned int*)(0x42A251DCUL))) +#define bM4_INTC_VSSEL140_VSEL24 (*((volatile unsigned int*)(0x42A251E0UL))) +#define bM4_INTC_VSSEL140_VSEL25 (*((volatile unsigned int*)(0x42A251E4UL))) +#define bM4_INTC_VSSEL140_VSEL26 (*((volatile unsigned int*)(0x42A251E8UL))) +#define bM4_INTC_VSSEL140_VSEL27 (*((volatile unsigned int*)(0x42A251ECUL))) +#define bM4_INTC_VSSEL140_VSEL28 (*((volatile unsigned int*)(0x42A251F0UL))) +#define bM4_INTC_VSSEL140_VSEL29 (*((volatile unsigned int*)(0x42A251F4UL))) +#define bM4_INTC_VSSEL140_VSEL30 (*((volatile unsigned int*)(0x42A251F8UL))) +#define bM4_INTC_VSSEL140_VSEL31 (*((volatile unsigned int*)(0x42A251FCUL))) +#define bM4_INTC_VSSEL141_VSEL0 (*((volatile unsigned int*)(0x42A25200UL))) +#define bM4_INTC_VSSEL141_VSEL1 (*((volatile unsigned int*)(0x42A25204UL))) +#define bM4_INTC_VSSEL141_VSEL2 (*((volatile unsigned int*)(0x42A25208UL))) +#define bM4_INTC_VSSEL141_VSEL3 (*((volatile unsigned int*)(0x42A2520CUL))) +#define bM4_INTC_VSSEL141_VSEL4 (*((volatile unsigned int*)(0x42A25210UL))) +#define bM4_INTC_VSSEL141_VSEL5 (*((volatile unsigned int*)(0x42A25214UL))) +#define bM4_INTC_VSSEL141_VSEL6 (*((volatile unsigned int*)(0x42A25218UL))) +#define bM4_INTC_VSSEL141_VSEL7 (*((volatile unsigned int*)(0x42A2521CUL))) +#define bM4_INTC_VSSEL141_VSEL8 (*((volatile unsigned int*)(0x42A25220UL))) +#define bM4_INTC_VSSEL141_VSEL9 (*((volatile unsigned int*)(0x42A25224UL))) +#define bM4_INTC_VSSEL141_VSEL10 (*((volatile unsigned int*)(0x42A25228UL))) +#define bM4_INTC_VSSEL141_VSEL11 (*((volatile unsigned int*)(0x42A2522CUL))) +#define bM4_INTC_VSSEL141_VSEL12 (*((volatile unsigned int*)(0x42A25230UL))) +#define bM4_INTC_VSSEL141_VSEL13 (*((volatile unsigned int*)(0x42A25234UL))) +#define bM4_INTC_VSSEL141_VSEL14 (*((volatile unsigned int*)(0x42A25238UL))) +#define bM4_INTC_VSSEL141_VSEL15 (*((volatile unsigned int*)(0x42A2523CUL))) +#define bM4_INTC_VSSEL141_VSEL16 (*((volatile unsigned int*)(0x42A25240UL))) +#define bM4_INTC_VSSEL141_VSEL17 (*((volatile unsigned int*)(0x42A25244UL))) +#define bM4_INTC_VSSEL141_VSEL18 (*((volatile unsigned int*)(0x42A25248UL))) +#define bM4_INTC_VSSEL141_VSEL19 (*((volatile unsigned int*)(0x42A2524CUL))) +#define bM4_INTC_VSSEL141_VSEL20 (*((volatile unsigned int*)(0x42A25250UL))) +#define bM4_INTC_VSSEL141_VSEL21 (*((volatile unsigned int*)(0x42A25254UL))) +#define bM4_INTC_VSSEL141_VSEL22 (*((volatile unsigned int*)(0x42A25258UL))) +#define bM4_INTC_VSSEL141_VSEL23 (*((volatile unsigned int*)(0x42A2525CUL))) +#define bM4_INTC_VSSEL141_VSEL24 (*((volatile unsigned int*)(0x42A25260UL))) +#define bM4_INTC_VSSEL141_VSEL25 (*((volatile unsigned int*)(0x42A25264UL))) +#define bM4_INTC_VSSEL141_VSEL26 (*((volatile unsigned int*)(0x42A25268UL))) +#define bM4_INTC_VSSEL141_VSEL27 (*((volatile unsigned int*)(0x42A2526CUL))) +#define bM4_INTC_VSSEL141_VSEL28 (*((volatile unsigned int*)(0x42A25270UL))) +#define bM4_INTC_VSSEL141_VSEL29 (*((volatile unsigned int*)(0x42A25274UL))) +#define bM4_INTC_VSSEL141_VSEL30 (*((volatile unsigned int*)(0x42A25278UL))) +#define bM4_INTC_VSSEL141_VSEL31 (*((volatile unsigned int*)(0x42A2527CUL))) +#define bM4_INTC_VSSEL142_VSEL0 (*((volatile unsigned int*)(0x42A25280UL))) +#define bM4_INTC_VSSEL142_VSEL1 (*((volatile unsigned int*)(0x42A25284UL))) +#define bM4_INTC_VSSEL142_VSEL2 (*((volatile unsigned int*)(0x42A25288UL))) +#define bM4_INTC_VSSEL142_VSEL3 (*((volatile unsigned int*)(0x42A2528CUL))) +#define bM4_INTC_VSSEL142_VSEL4 (*((volatile unsigned int*)(0x42A25290UL))) +#define bM4_INTC_VSSEL142_VSEL5 (*((volatile unsigned int*)(0x42A25294UL))) +#define bM4_INTC_VSSEL142_VSEL6 (*((volatile unsigned int*)(0x42A25298UL))) +#define bM4_INTC_VSSEL142_VSEL7 (*((volatile unsigned int*)(0x42A2529CUL))) +#define bM4_INTC_VSSEL142_VSEL8 (*((volatile unsigned int*)(0x42A252A0UL))) +#define bM4_INTC_VSSEL142_VSEL9 (*((volatile unsigned int*)(0x42A252A4UL))) +#define bM4_INTC_VSSEL142_VSEL10 (*((volatile unsigned int*)(0x42A252A8UL))) +#define bM4_INTC_VSSEL142_VSEL11 (*((volatile unsigned int*)(0x42A252ACUL))) +#define bM4_INTC_VSSEL142_VSEL12 (*((volatile unsigned int*)(0x42A252B0UL))) +#define bM4_INTC_VSSEL142_VSEL13 (*((volatile unsigned int*)(0x42A252B4UL))) +#define bM4_INTC_VSSEL142_VSEL14 (*((volatile unsigned int*)(0x42A252B8UL))) +#define bM4_INTC_VSSEL142_VSEL15 (*((volatile unsigned int*)(0x42A252BCUL))) +#define bM4_INTC_VSSEL142_VSEL16 (*((volatile unsigned int*)(0x42A252C0UL))) +#define bM4_INTC_VSSEL142_VSEL17 (*((volatile unsigned int*)(0x42A252C4UL))) +#define bM4_INTC_VSSEL142_VSEL18 (*((volatile unsigned int*)(0x42A252C8UL))) +#define bM4_INTC_VSSEL142_VSEL19 (*((volatile unsigned int*)(0x42A252CCUL))) +#define bM4_INTC_VSSEL142_VSEL20 (*((volatile unsigned int*)(0x42A252D0UL))) +#define bM4_INTC_VSSEL142_VSEL21 (*((volatile unsigned int*)(0x42A252D4UL))) +#define bM4_INTC_VSSEL142_VSEL22 (*((volatile unsigned int*)(0x42A252D8UL))) +#define bM4_INTC_VSSEL142_VSEL23 (*((volatile unsigned int*)(0x42A252DCUL))) +#define bM4_INTC_VSSEL142_VSEL24 (*((volatile unsigned int*)(0x42A252E0UL))) +#define bM4_INTC_VSSEL142_VSEL25 (*((volatile unsigned int*)(0x42A252E4UL))) +#define bM4_INTC_VSSEL142_VSEL26 (*((volatile unsigned int*)(0x42A252E8UL))) +#define bM4_INTC_VSSEL142_VSEL27 (*((volatile unsigned int*)(0x42A252ECUL))) +#define bM4_INTC_VSSEL142_VSEL28 (*((volatile unsigned int*)(0x42A252F0UL))) +#define bM4_INTC_VSSEL142_VSEL29 (*((volatile unsigned int*)(0x42A252F4UL))) +#define bM4_INTC_VSSEL142_VSEL30 (*((volatile unsigned int*)(0x42A252F8UL))) +#define bM4_INTC_VSSEL142_VSEL31 (*((volatile unsigned int*)(0x42A252FCUL))) +#define bM4_INTC_VSSEL143_VSEL0 (*((volatile unsigned int*)(0x42A25300UL))) +#define bM4_INTC_VSSEL143_VSEL1 (*((volatile unsigned int*)(0x42A25304UL))) +#define bM4_INTC_VSSEL143_VSEL2 (*((volatile unsigned int*)(0x42A25308UL))) +#define bM4_INTC_VSSEL143_VSEL3 (*((volatile unsigned int*)(0x42A2530CUL))) +#define bM4_INTC_VSSEL143_VSEL4 (*((volatile unsigned int*)(0x42A25310UL))) +#define bM4_INTC_VSSEL143_VSEL5 (*((volatile unsigned int*)(0x42A25314UL))) +#define bM4_INTC_VSSEL143_VSEL6 (*((volatile unsigned int*)(0x42A25318UL))) +#define bM4_INTC_VSSEL143_VSEL7 (*((volatile unsigned int*)(0x42A2531CUL))) +#define bM4_INTC_VSSEL143_VSEL8 (*((volatile unsigned int*)(0x42A25320UL))) +#define bM4_INTC_VSSEL143_VSEL9 (*((volatile unsigned int*)(0x42A25324UL))) +#define bM4_INTC_VSSEL143_VSEL10 (*((volatile unsigned int*)(0x42A25328UL))) +#define bM4_INTC_VSSEL143_VSEL11 (*((volatile unsigned int*)(0x42A2532CUL))) +#define bM4_INTC_VSSEL143_VSEL12 (*((volatile unsigned int*)(0x42A25330UL))) +#define bM4_INTC_VSSEL143_VSEL13 (*((volatile unsigned int*)(0x42A25334UL))) +#define bM4_INTC_VSSEL143_VSEL14 (*((volatile unsigned int*)(0x42A25338UL))) +#define bM4_INTC_VSSEL143_VSEL15 (*((volatile unsigned int*)(0x42A2533CUL))) +#define bM4_INTC_VSSEL143_VSEL16 (*((volatile unsigned int*)(0x42A25340UL))) +#define bM4_INTC_VSSEL143_VSEL17 (*((volatile unsigned int*)(0x42A25344UL))) +#define bM4_INTC_VSSEL143_VSEL18 (*((volatile unsigned int*)(0x42A25348UL))) +#define bM4_INTC_VSSEL143_VSEL19 (*((volatile unsigned int*)(0x42A2534CUL))) +#define bM4_INTC_VSSEL143_VSEL20 (*((volatile unsigned int*)(0x42A25350UL))) +#define bM4_INTC_VSSEL143_VSEL21 (*((volatile unsigned int*)(0x42A25354UL))) +#define bM4_INTC_VSSEL143_VSEL22 (*((volatile unsigned int*)(0x42A25358UL))) +#define bM4_INTC_VSSEL143_VSEL23 (*((volatile unsigned int*)(0x42A2535CUL))) +#define bM4_INTC_VSSEL143_VSEL24 (*((volatile unsigned int*)(0x42A25360UL))) +#define bM4_INTC_VSSEL143_VSEL25 (*((volatile unsigned int*)(0x42A25364UL))) +#define bM4_INTC_VSSEL143_VSEL26 (*((volatile unsigned int*)(0x42A25368UL))) +#define bM4_INTC_VSSEL143_VSEL27 (*((volatile unsigned int*)(0x42A2536CUL))) +#define bM4_INTC_VSSEL143_VSEL28 (*((volatile unsigned int*)(0x42A25370UL))) +#define bM4_INTC_VSSEL143_VSEL29 (*((volatile unsigned int*)(0x42A25374UL))) +#define bM4_INTC_VSSEL143_VSEL30 (*((volatile unsigned int*)(0x42A25378UL))) +#define bM4_INTC_VSSEL143_VSEL31 (*((volatile unsigned int*)(0x42A2537CUL))) +#define bM4_INTC_SWIER_SWIE0 (*((volatile unsigned int*)(0x42A25380UL))) +#define bM4_INTC_SWIER_SWIE1 (*((volatile unsigned int*)(0x42A25384UL))) +#define bM4_INTC_SWIER_SWIE2 (*((volatile unsigned int*)(0x42A25388UL))) +#define bM4_INTC_SWIER_SWIE3 (*((volatile unsigned int*)(0x42A2538CUL))) +#define bM4_INTC_SWIER_SWIE4 (*((volatile unsigned int*)(0x42A25390UL))) +#define bM4_INTC_SWIER_SWIE5 (*((volatile unsigned int*)(0x42A25394UL))) +#define bM4_INTC_SWIER_SWIE6 (*((volatile unsigned int*)(0x42A25398UL))) +#define bM4_INTC_SWIER_SWIE7 (*((volatile unsigned int*)(0x42A2539CUL))) +#define bM4_INTC_SWIER_SWIE8 (*((volatile unsigned int*)(0x42A253A0UL))) +#define bM4_INTC_SWIER_SWIE9 (*((volatile unsigned int*)(0x42A253A4UL))) +#define bM4_INTC_SWIER_SWIE10 (*((volatile unsigned int*)(0x42A253A8UL))) +#define bM4_INTC_SWIER_SWIE11 (*((volatile unsigned int*)(0x42A253ACUL))) +#define bM4_INTC_SWIER_SWIE12 (*((volatile unsigned int*)(0x42A253B0UL))) +#define bM4_INTC_SWIER_SWIE13 (*((volatile unsigned int*)(0x42A253B4UL))) +#define bM4_INTC_SWIER_SWIE14 (*((volatile unsigned int*)(0x42A253B8UL))) +#define bM4_INTC_SWIER_SWIE15 (*((volatile unsigned int*)(0x42A253BCUL))) +#define bM4_INTC_SWIER_SWIE16 (*((volatile unsigned int*)(0x42A253C0UL))) +#define bM4_INTC_SWIER_SWIE17 (*((volatile unsigned int*)(0x42A253C4UL))) +#define bM4_INTC_SWIER_SWIE18 (*((volatile unsigned int*)(0x42A253C8UL))) +#define bM4_INTC_SWIER_SWIE19 (*((volatile unsigned int*)(0x42A253CCUL))) +#define bM4_INTC_SWIER_SWIE20 (*((volatile unsigned int*)(0x42A253D0UL))) +#define bM4_INTC_SWIER_SWIE21 (*((volatile unsigned int*)(0x42A253D4UL))) +#define bM4_INTC_SWIER_SWIE22 (*((volatile unsigned int*)(0x42A253D8UL))) +#define bM4_INTC_SWIER_SWIE23 (*((volatile unsigned int*)(0x42A253DCUL))) +#define bM4_INTC_SWIER_SWIE24 (*((volatile unsigned int*)(0x42A253E0UL))) +#define bM4_INTC_SWIER_SWIE25 (*((volatile unsigned int*)(0x42A253E4UL))) +#define bM4_INTC_SWIER_SWIE26 (*((volatile unsigned int*)(0x42A253E8UL))) +#define bM4_INTC_SWIER_SWIE27 (*((volatile unsigned int*)(0x42A253ECUL))) +#define bM4_INTC_SWIER_SWIE28 (*((volatile unsigned int*)(0x42A253F0UL))) +#define bM4_INTC_SWIER_SWIE29 (*((volatile unsigned int*)(0x42A253F4UL))) +#define bM4_INTC_SWIER_SWIE30 (*((volatile unsigned int*)(0x42A253F8UL))) +#define bM4_INTC_SWIER_SWIE31 (*((volatile unsigned int*)(0x42A253FCUL))) +#define bM4_INTC_EVTER_EVTE0 (*((volatile unsigned int*)(0x42A25400UL))) +#define bM4_INTC_EVTER_EVTE1 (*((volatile unsigned int*)(0x42A25404UL))) +#define bM4_INTC_EVTER_EVTE2 (*((volatile unsigned int*)(0x42A25408UL))) +#define bM4_INTC_EVTER_EVTE3 (*((volatile unsigned int*)(0x42A2540CUL))) +#define bM4_INTC_EVTER_EVTE4 (*((volatile unsigned int*)(0x42A25410UL))) +#define bM4_INTC_EVTER_EVTE5 (*((volatile unsigned int*)(0x42A25414UL))) +#define bM4_INTC_EVTER_EVTE6 (*((volatile unsigned int*)(0x42A25418UL))) +#define bM4_INTC_EVTER_EVTE7 (*((volatile unsigned int*)(0x42A2541CUL))) +#define bM4_INTC_EVTER_EVTE8 (*((volatile unsigned int*)(0x42A25420UL))) +#define bM4_INTC_EVTER_EVTE9 (*((volatile unsigned int*)(0x42A25424UL))) +#define bM4_INTC_EVTER_EVTE10 (*((volatile unsigned int*)(0x42A25428UL))) +#define bM4_INTC_EVTER_EVTE11 (*((volatile unsigned int*)(0x42A2542CUL))) +#define bM4_INTC_EVTER_EVTE12 (*((volatile unsigned int*)(0x42A25430UL))) +#define bM4_INTC_EVTER_EVTE13 (*((volatile unsigned int*)(0x42A25434UL))) +#define bM4_INTC_EVTER_EVTE14 (*((volatile unsigned int*)(0x42A25438UL))) +#define bM4_INTC_EVTER_EVTE15 (*((volatile unsigned int*)(0x42A2543CUL))) +#define bM4_INTC_EVTER_EVTE16 (*((volatile unsigned int*)(0x42A25440UL))) +#define bM4_INTC_EVTER_EVTE17 (*((volatile unsigned int*)(0x42A25444UL))) +#define bM4_INTC_EVTER_EVTE18 (*((volatile unsigned int*)(0x42A25448UL))) +#define bM4_INTC_EVTER_EVTE19 (*((volatile unsigned int*)(0x42A2544CUL))) +#define bM4_INTC_EVTER_EVTE20 (*((volatile unsigned int*)(0x42A25450UL))) +#define bM4_INTC_EVTER_EVTE21 (*((volatile unsigned int*)(0x42A25454UL))) +#define bM4_INTC_EVTER_EVTE22 (*((volatile unsigned int*)(0x42A25458UL))) +#define bM4_INTC_EVTER_EVTE23 (*((volatile unsigned int*)(0x42A2545CUL))) +#define bM4_INTC_EVTER_EVTE24 (*((volatile unsigned int*)(0x42A25460UL))) +#define bM4_INTC_EVTER_EVTE25 (*((volatile unsigned int*)(0x42A25464UL))) +#define bM4_INTC_EVTER_EVTE26 (*((volatile unsigned int*)(0x42A25468UL))) +#define bM4_INTC_EVTER_EVTE27 (*((volatile unsigned int*)(0x42A2546CUL))) +#define bM4_INTC_EVTER_EVTE28 (*((volatile unsigned int*)(0x42A25470UL))) +#define bM4_INTC_EVTER_EVTE29 (*((volatile unsigned int*)(0x42A25474UL))) +#define bM4_INTC_EVTER_EVTE30 (*((volatile unsigned int*)(0x42A25478UL))) +#define bM4_INTC_EVTER_EVTE31 (*((volatile unsigned int*)(0x42A2547CUL))) +#define bM4_INTC_IER_IER0 (*((volatile unsigned int*)(0x42A25480UL))) +#define bM4_INTC_IER_IER1 (*((volatile unsigned int*)(0x42A25484UL))) +#define bM4_INTC_IER_IER2 (*((volatile unsigned int*)(0x42A25488UL))) +#define bM4_INTC_IER_IER3 (*((volatile unsigned int*)(0x42A2548CUL))) +#define bM4_INTC_IER_IER4 (*((volatile unsigned int*)(0x42A25490UL))) +#define bM4_INTC_IER_IER5 (*((volatile unsigned int*)(0x42A25494UL))) +#define bM4_INTC_IER_IER6 (*((volatile unsigned int*)(0x42A25498UL))) +#define bM4_INTC_IER_IER7 (*((volatile unsigned int*)(0x42A2549CUL))) +#define bM4_INTC_IER_IER8 (*((volatile unsigned int*)(0x42A254A0UL))) +#define bM4_INTC_IER_IER9 (*((volatile unsigned int*)(0x42A254A4UL))) +#define bM4_INTC_IER_IER10 (*((volatile unsigned int*)(0x42A254A8UL))) +#define bM4_INTC_IER_IER11 (*((volatile unsigned int*)(0x42A254ACUL))) +#define bM4_INTC_IER_IER12 (*((volatile unsigned int*)(0x42A254B0UL))) +#define bM4_INTC_IER_IER13 (*((volatile unsigned int*)(0x42A254B4UL))) +#define bM4_INTC_IER_IER14 (*((volatile unsigned int*)(0x42A254B8UL))) +#define bM4_INTC_IER_IER15 (*((volatile unsigned int*)(0x42A254BCUL))) +#define bM4_INTC_IER_IER16 (*((volatile unsigned int*)(0x42A254C0UL))) +#define bM4_INTC_IER_IER17 (*((volatile unsigned int*)(0x42A254C4UL))) +#define bM4_INTC_IER_IER18 (*((volatile unsigned int*)(0x42A254C8UL))) +#define bM4_INTC_IER_IER19 (*((volatile unsigned int*)(0x42A254CCUL))) +#define bM4_INTC_IER_IER20 (*((volatile unsigned int*)(0x42A254D0UL))) +#define bM4_INTC_IER_IER21 (*((volatile unsigned int*)(0x42A254D4UL))) +#define bM4_INTC_IER_IER22 (*((volatile unsigned int*)(0x42A254D8UL))) +#define bM4_INTC_IER_IER23 (*((volatile unsigned int*)(0x42A254DCUL))) +#define bM4_INTC_IER_IER24 (*((volatile unsigned int*)(0x42A254E0UL))) +#define bM4_INTC_IER_IER25 (*((volatile unsigned int*)(0x42A254E4UL))) +#define bM4_INTC_IER_IER26 (*((volatile unsigned int*)(0x42A254E8UL))) +#define bM4_INTC_IER_IER27 (*((volatile unsigned int*)(0x42A254ECUL))) +#define bM4_INTC_IER_IER28 (*((volatile unsigned int*)(0x42A254F0UL))) +#define bM4_INTC_IER_IER29 (*((volatile unsigned int*)(0x42A254F4UL))) +#define bM4_INTC_IER_IER30 (*((volatile unsigned int*)(0x42A254F8UL))) +#define bM4_INTC_IER_IER31 (*((volatile unsigned int*)(0x42A254FCUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL0 (*((volatile unsigned int*)(0x42A18000UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL1 (*((volatile unsigned int*)(0x42A18004UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL2 (*((volatile unsigned int*)(0x42A18008UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL3 (*((volatile unsigned int*)(0x42A1800CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL4 (*((volatile unsigned int*)(0x42A18010UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL5 (*((volatile unsigned int*)(0x42A18014UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL6 (*((volatile unsigned int*)(0x42A18018UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL7 (*((volatile unsigned int*)(0x42A1801CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL8 (*((volatile unsigned int*)(0x42A18020UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL9 (*((volatile unsigned int*)(0x42A18024UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL10 (*((volatile unsigned int*)(0x42A18028UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL11 (*((volatile unsigned int*)(0x42A1802CUL))) +#define bM4_KEYSCAN_SCR_KEYINSEL12 (*((volatile unsigned int*)(0x42A18030UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL13 (*((volatile unsigned int*)(0x42A18034UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL14 (*((volatile unsigned int*)(0x42A18038UL))) +#define bM4_KEYSCAN_SCR_KEYINSEL15 (*((volatile unsigned int*)(0x42A1803CUL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL0 (*((volatile unsigned int*)(0x42A18040UL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL1 (*((volatile unsigned int*)(0x42A18044UL))) +#define bM4_KEYSCAN_SCR_KEYOUTSEL2 (*((volatile unsigned int*)(0x42A18048UL))) +#define bM4_KEYSCAN_SCR_CKSEL0 (*((volatile unsigned int*)(0x42A18050UL))) +#define bM4_KEYSCAN_SCR_CKSEL1 (*((volatile unsigned int*)(0x42A18054UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL0 (*((volatile unsigned int*)(0x42A18060UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL1 (*((volatile unsigned int*)(0x42A18064UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL2 (*((volatile unsigned int*)(0x42A18068UL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL3 (*((volatile unsigned int*)(0x42A1806CUL))) +#define bM4_KEYSCAN_SCR_T_LLEVEL4 (*((volatile unsigned int*)(0x42A18070UL))) +#define bM4_KEYSCAN_SCR_T_HIZ0 (*((volatile unsigned int*)(0x42A18074UL))) +#define bM4_KEYSCAN_SCR_T_HIZ1 (*((volatile unsigned int*)(0x42A18078UL))) +#define bM4_KEYSCAN_SCR_T_HIZ2 (*((volatile unsigned int*)(0x42A1807CUL))) +#define bM4_KEYSCAN_SER_SEN (*((volatile unsigned int*)(0x42A18080UL))) +#define bM4_KEYSCAN_SSR_INDEX0 (*((volatile unsigned int*)(0x42A18100UL))) +#define bM4_KEYSCAN_SSR_INDEX1 (*((volatile unsigned int*)(0x42A18104UL))) +#define bM4_KEYSCAN_SSR_INDEX2 (*((volatile unsigned int*)(0x42A18108UL))) +#define bM4_MPU_RGD0_MPURG0SIZE0 (*((volatile unsigned int*)(0x42A00000UL))) +#define bM4_MPU_RGD0_MPURG0SIZE1 (*((volatile unsigned int*)(0x42A00004UL))) +#define bM4_MPU_RGD0_MPURG0SIZE2 (*((volatile unsigned int*)(0x42A00008UL))) +#define bM4_MPU_RGD0_MPURG0SIZE3 (*((volatile unsigned int*)(0x42A0000CUL))) +#define bM4_MPU_RGD0_MPURG0SIZE4 (*((volatile unsigned int*)(0x42A00010UL))) +#define bM4_MPU_RGD0_MPURG0ADDR0 (*((volatile unsigned int*)(0x42A00014UL))) +#define bM4_MPU_RGD0_MPURG0ADDR1 (*((volatile unsigned int*)(0x42A00018UL))) +#define bM4_MPU_RGD0_MPURG0ADDR2 (*((volatile unsigned int*)(0x42A0001CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR3 (*((volatile unsigned int*)(0x42A00020UL))) +#define bM4_MPU_RGD0_MPURG0ADDR4 (*((volatile unsigned int*)(0x42A00024UL))) +#define bM4_MPU_RGD0_MPURG0ADDR5 (*((volatile unsigned int*)(0x42A00028UL))) +#define bM4_MPU_RGD0_MPURG0ADDR6 (*((volatile unsigned int*)(0x42A0002CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR7 (*((volatile unsigned int*)(0x42A00030UL))) +#define bM4_MPU_RGD0_MPURG0ADDR8 (*((volatile unsigned int*)(0x42A00034UL))) +#define bM4_MPU_RGD0_MPURG0ADDR9 (*((volatile unsigned int*)(0x42A00038UL))) +#define bM4_MPU_RGD0_MPURG0ADDR10 (*((volatile unsigned int*)(0x42A0003CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR11 (*((volatile unsigned int*)(0x42A00040UL))) +#define bM4_MPU_RGD0_MPURG0ADDR12 (*((volatile unsigned int*)(0x42A00044UL))) +#define bM4_MPU_RGD0_MPURG0ADDR13 (*((volatile unsigned int*)(0x42A00048UL))) +#define bM4_MPU_RGD0_MPURG0ADDR14 (*((volatile unsigned int*)(0x42A0004CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR15 (*((volatile unsigned int*)(0x42A00050UL))) +#define bM4_MPU_RGD0_MPURG0ADDR16 (*((volatile unsigned int*)(0x42A00054UL))) +#define bM4_MPU_RGD0_MPURG0ADDR17 (*((volatile unsigned int*)(0x42A00058UL))) +#define bM4_MPU_RGD0_MPURG0ADDR18 (*((volatile unsigned int*)(0x42A0005CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR19 (*((volatile unsigned int*)(0x42A00060UL))) +#define bM4_MPU_RGD0_MPURG0ADDR20 (*((volatile unsigned int*)(0x42A00064UL))) +#define bM4_MPU_RGD0_MPURG0ADDR21 (*((volatile unsigned int*)(0x42A00068UL))) +#define bM4_MPU_RGD0_MPURG0ADDR22 (*((volatile unsigned int*)(0x42A0006CUL))) +#define bM4_MPU_RGD0_MPURG0ADDR23 (*((volatile unsigned int*)(0x42A00070UL))) +#define bM4_MPU_RGD0_MPURG0ADDR24 (*((volatile unsigned int*)(0x42A00074UL))) +#define bM4_MPU_RGD0_MPURG0ADDR25 (*((volatile unsigned int*)(0x42A00078UL))) +#define bM4_MPU_RGD0_MPURG0ADDR26 (*((volatile unsigned int*)(0x42A0007CUL))) +#define bM4_MPU_RGD1_MPURG1SIZE0 (*((volatile unsigned int*)(0x42A00080UL))) +#define bM4_MPU_RGD1_MPURG1SIZE1 (*((volatile unsigned int*)(0x42A00084UL))) +#define bM4_MPU_RGD1_MPURG1SIZE2 (*((volatile unsigned int*)(0x42A00088UL))) +#define bM4_MPU_RGD1_MPURG1SIZE3 (*((volatile unsigned int*)(0x42A0008CUL))) +#define bM4_MPU_RGD1_MPURG1SIZE4 (*((volatile unsigned int*)(0x42A00090UL))) +#define bM4_MPU_RGD1_MPURG1ADDR0 (*((volatile unsigned int*)(0x42A00094UL))) +#define bM4_MPU_RGD1_MPURG1ADDR1 (*((volatile unsigned int*)(0x42A00098UL))) +#define bM4_MPU_RGD1_MPURG1ADDR2 (*((volatile unsigned int*)(0x42A0009CUL))) +#define bM4_MPU_RGD1_MPURG1ADDR3 (*((volatile unsigned int*)(0x42A000A0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR4 (*((volatile unsigned int*)(0x42A000A4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR5 (*((volatile unsigned int*)(0x42A000A8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR6 (*((volatile unsigned int*)(0x42A000ACUL))) +#define bM4_MPU_RGD1_MPURG1ADDR7 (*((volatile unsigned int*)(0x42A000B0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR8 (*((volatile unsigned int*)(0x42A000B4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR9 (*((volatile unsigned int*)(0x42A000B8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR10 (*((volatile unsigned int*)(0x42A000BCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR11 (*((volatile unsigned int*)(0x42A000C0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR12 (*((volatile unsigned int*)(0x42A000C4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR13 (*((volatile unsigned int*)(0x42A000C8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR14 (*((volatile unsigned int*)(0x42A000CCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR15 (*((volatile unsigned int*)(0x42A000D0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR16 (*((volatile unsigned int*)(0x42A000D4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR17 (*((volatile unsigned int*)(0x42A000D8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR18 (*((volatile unsigned int*)(0x42A000DCUL))) +#define bM4_MPU_RGD1_MPURG1ADDR19 (*((volatile unsigned int*)(0x42A000E0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR20 (*((volatile unsigned int*)(0x42A000E4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR21 (*((volatile unsigned int*)(0x42A000E8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR22 (*((volatile unsigned int*)(0x42A000ECUL))) +#define bM4_MPU_RGD1_MPURG1ADDR23 (*((volatile unsigned int*)(0x42A000F0UL))) +#define bM4_MPU_RGD1_MPURG1ADDR24 (*((volatile unsigned int*)(0x42A000F4UL))) +#define bM4_MPU_RGD1_MPURG1ADDR25 (*((volatile unsigned int*)(0x42A000F8UL))) +#define bM4_MPU_RGD1_MPURG1ADDR26 (*((volatile unsigned int*)(0x42A000FCUL))) +#define bM4_MPU_RGD2_MPURG2SIZE0 (*((volatile unsigned int*)(0x42A00100UL))) +#define bM4_MPU_RGD2_MPURG2SIZE1 (*((volatile unsigned int*)(0x42A00104UL))) +#define bM4_MPU_RGD2_MPURG2SIZE2 (*((volatile unsigned int*)(0x42A00108UL))) +#define bM4_MPU_RGD2_MPURG2SIZE3 (*((volatile unsigned int*)(0x42A0010CUL))) +#define bM4_MPU_RGD2_MPURG2SIZE4 (*((volatile unsigned int*)(0x42A00110UL))) +#define bM4_MPU_RGD2_MPURG2ADDR0 (*((volatile unsigned int*)(0x42A00114UL))) +#define bM4_MPU_RGD2_MPURG2ADDR1 (*((volatile unsigned int*)(0x42A00118UL))) +#define bM4_MPU_RGD2_MPURG2ADDR2 (*((volatile unsigned int*)(0x42A0011CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR3 (*((volatile unsigned int*)(0x42A00120UL))) +#define bM4_MPU_RGD2_MPURG2ADDR4 (*((volatile unsigned int*)(0x42A00124UL))) +#define bM4_MPU_RGD2_MPURG2ADDR5 (*((volatile unsigned int*)(0x42A00128UL))) +#define bM4_MPU_RGD2_MPURG2ADDR6 (*((volatile unsigned int*)(0x42A0012CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR7 (*((volatile unsigned int*)(0x42A00130UL))) +#define bM4_MPU_RGD2_MPURG2ADDR8 (*((volatile unsigned int*)(0x42A00134UL))) +#define bM4_MPU_RGD2_MPURG2ADDR9 (*((volatile unsigned int*)(0x42A00138UL))) +#define bM4_MPU_RGD2_MPURG2ADDR10 (*((volatile unsigned int*)(0x42A0013CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR11 (*((volatile unsigned int*)(0x42A00140UL))) +#define bM4_MPU_RGD2_MPURG2ADDR12 (*((volatile unsigned int*)(0x42A00144UL))) +#define bM4_MPU_RGD2_MPURG2ADDR13 (*((volatile unsigned int*)(0x42A00148UL))) +#define bM4_MPU_RGD2_MPURG2ADDR14 (*((volatile unsigned int*)(0x42A0014CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR15 (*((volatile unsigned int*)(0x42A00150UL))) +#define bM4_MPU_RGD2_MPURG2ADDR16 (*((volatile unsigned int*)(0x42A00154UL))) +#define bM4_MPU_RGD2_MPURG2ADDR17 (*((volatile unsigned int*)(0x42A00158UL))) +#define bM4_MPU_RGD2_MPURG2ADDR18 (*((volatile unsigned int*)(0x42A0015CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR19 (*((volatile unsigned int*)(0x42A00160UL))) +#define bM4_MPU_RGD2_MPURG2ADDR20 (*((volatile unsigned int*)(0x42A00164UL))) +#define bM4_MPU_RGD2_MPURG2ADDR21 (*((volatile unsigned int*)(0x42A00168UL))) +#define bM4_MPU_RGD2_MPURG2ADDR22 (*((volatile unsigned int*)(0x42A0016CUL))) +#define bM4_MPU_RGD2_MPURG2ADDR23 (*((volatile unsigned int*)(0x42A00170UL))) +#define bM4_MPU_RGD2_MPURG2ADDR24 (*((volatile unsigned int*)(0x42A00174UL))) +#define bM4_MPU_RGD2_MPURG2ADDR25 (*((volatile unsigned int*)(0x42A00178UL))) +#define bM4_MPU_RGD2_MPURG2ADDR26 (*((volatile unsigned int*)(0x42A0017CUL))) +#define bM4_MPU_RGD3_MPURG3SIZE0 (*((volatile unsigned int*)(0x42A00180UL))) +#define bM4_MPU_RGD3_MPURG3SIZE1 (*((volatile unsigned int*)(0x42A00184UL))) +#define bM4_MPU_RGD3_MPURG3SIZE2 (*((volatile unsigned int*)(0x42A00188UL))) +#define bM4_MPU_RGD3_MPURG3SIZE3 (*((volatile unsigned int*)(0x42A0018CUL))) +#define bM4_MPU_RGD3_MPURG3SIZE4 (*((volatile unsigned int*)(0x42A00190UL))) +#define bM4_MPU_RGD3_MPURG3ADDR0 (*((volatile unsigned int*)(0x42A00194UL))) +#define bM4_MPU_RGD3_MPURG3ADDR1 (*((volatile unsigned int*)(0x42A00198UL))) +#define bM4_MPU_RGD3_MPURG3ADDR2 (*((volatile unsigned int*)(0x42A0019CUL))) +#define bM4_MPU_RGD3_MPURG3ADDR3 (*((volatile unsigned int*)(0x42A001A0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR4 (*((volatile unsigned int*)(0x42A001A4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR5 (*((volatile unsigned int*)(0x42A001A8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR6 (*((volatile unsigned int*)(0x42A001ACUL))) +#define bM4_MPU_RGD3_MPURG3ADDR7 (*((volatile unsigned int*)(0x42A001B0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR8 (*((volatile unsigned int*)(0x42A001B4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR9 (*((volatile unsigned int*)(0x42A001B8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR10 (*((volatile unsigned int*)(0x42A001BCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR11 (*((volatile unsigned int*)(0x42A001C0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR12 (*((volatile unsigned int*)(0x42A001C4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR13 (*((volatile unsigned int*)(0x42A001C8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR14 (*((volatile unsigned int*)(0x42A001CCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR15 (*((volatile unsigned int*)(0x42A001D0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR16 (*((volatile unsigned int*)(0x42A001D4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR17 (*((volatile unsigned int*)(0x42A001D8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR18 (*((volatile unsigned int*)(0x42A001DCUL))) +#define bM4_MPU_RGD3_MPURG3ADDR19 (*((volatile unsigned int*)(0x42A001E0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR20 (*((volatile unsigned int*)(0x42A001E4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR21 (*((volatile unsigned int*)(0x42A001E8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR22 (*((volatile unsigned int*)(0x42A001ECUL))) +#define bM4_MPU_RGD3_MPURG3ADDR23 (*((volatile unsigned int*)(0x42A001F0UL))) +#define bM4_MPU_RGD3_MPURG3ADDR24 (*((volatile unsigned int*)(0x42A001F4UL))) +#define bM4_MPU_RGD3_MPURG3ADDR25 (*((volatile unsigned int*)(0x42A001F8UL))) +#define bM4_MPU_RGD3_MPURG3ADDR26 (*((volatile unsigned int*)(0x42A001FCUL))) +#define bM4_MPU_RGD4_MPURG4SIZE0 (*((volatile unsigned int*)(0x42A00200UL))) +#define bM4_MPU_RGD4_MPURG4SIZE1 (*((volatile unsigned int*)(0x42A00204UL))) +#define bM4_MPU_RGD4_MPURG4SIZE2 (*((volatile unsigned int*)(0x42A00208UL))) +#define bM4_MPU_RGD4_MPURG4SIZE3 (*((volatile unsigned int*)(0x42A0020CUL))) +#define bM4_MPU_RGD4_MPURG4SIZE4 (*((volatile unsigned int*)(0x42A00210UL))) +#define bM4_MPU_RGD4_MPURG4ADDR0 (*((volatile unsigned int*)(0x42A00214UL))) +#define bM4_MPU_RGD4_MPURG4ADDR1 (*((volatile unsigned int*)(0x42A00218UL))) +#define bM4_MPU_RGD4_MPURG4ADDR2 (*((volatile unsigned int*)(0x42A0021CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR3 (*((volatile unsigned int*)(0x42A00220UL))) +#define bM4_MPU_RGD4_MPURG4ADDR4 (*((volatile unsigned int*)(0x42A00224UL))) +#define bM4_MPU_RGD4_MPURG4ADDR5 (*((volatile unsigned int*)(0x42A00228UL))) +#define bM4_MPU_RGD4_MPURG4ADDR6 (*((volatile unsigned int*)(0x42A0022CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR7 (*((volatile unsigned int*)(0x42A00230UL))) +#define bM4_MPU_RGD4_MPURG4ADDR8 (*((volatile unsigned int*)(0x42A00234UL))) +#define bM4_MPU_RGD4_MPURG4ADDR9 (*((volatile unsigned int*)(0x42A00238UL))) +#define bM4_MPU_RGD4_MPURG4ADDR10 (*((volatile unsigned int*)(0x42A0023CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR11 (*((volatile unsigned int*)(0x42A00240UL))) +#define bM4_MPU_RGD4_MPURG4ADDR12 (*((volatile unsigned int*)(0x42A00244UL))) +#define bM4_MPU_RGD4_MPURG4ADDR13 (*((volatile unsigned int*)(0x42A00248UL))) +#define bM4_MPU_RGD4_MPURG4ADDR14 (*((volatile unsigned int*)(0x42A0024CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR15 (*((volatile unsigned int*)(0x42A00250UL))) +#define bM4_MPU_RGD4_MPURG4ADDR16 (*((volatile unsigned int*)(0x42A00254UL))) +#define bM4_MPU_RGD4_MPURG4ADDR17 (*((volatile unsigned int*)(0x42A00258UL))) +#define bM4_MPU_RGD4_MPURG4ADDR18 (*((volatile unsigned int*)(0x42A0025CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR19 (*((volatile unsigned int*)(0x42A00260UL))) +#define bM4_MPU_RGD4_MPURG4ADDR20 (*((volatile unsigned int*)(0x42A00264UL))) +#define bM4_MPU_RGD4_MPURG4ADDR21 (*((volatile unsigned int*)(0x42A00268UL))) +#define bM4_MPU_RGD4_MPURG4ADDR22 (*((volatile unsigned int*)(0x42A0026CUL))) +#define bM4_MPU_RGD4_MPURG4ADDR23 (*((volatile unsigned int*)(0x42A00270UL))) +#define bM4_MPU_RGD4_MPURG4ADDR24 (*((volatile unsigned int*)(0x42A00274UL))) +#define bM4_MPU_RGD4_MPURG4ADDR25 (*((volatile unsigned int*)(0x42A00278UL))) +#define bM4_MPU_RGD4_MPURG4ADDR26 (*((volatile unsigned int*)(0x42A0027CUL))) +#define bM4_MPU_RGD5_MPURG5SIZE0 (*((volatile unsigned int*)(0x42A00280UL))) +#define bM4_MPU_RGD5_MPURG5SIZE1 (*((volatile unsigned int*)(0x42A00284UL))) +#define bM4_MPU_RGD5_MPURG5SIZE2 (*((volatile unsigned int*)(0x42A00288UL))) +#define bM4_MPU_RGD5_MPURG5SIZE3 (*((volatile unsigned int*)(0x42A0028CUL))) +#define bM4_MPU_RGD5_MPURG5SIZE4 (*((volatile unsigned int*)(0x42A00290UL))) +#define bM4_MPU_RGD5_MPURG5ADDR0 (*((volatile unsigned int*)(0x42A00294UL))) +#define bM4_MPU_RGD5_MPURG5ADDR1 (*((volatile unsigned int*)(0x42A00298UL))) +#define bM4_MPU_RGD5_MPURG5ADDR2 (*((volatile unsigned int*)(0x42A0029CUL))) +#define bM4_MPU_RGD5_MPURG5ADDR3 (*((volatile unsigned int*)(0x42A002A0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR4 (*((volatile unsigned int*)(0x42A002A4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR5 (*((volatile unsigned int*)(0x42A002A8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR6 (*((volatile unsigned int*)(0x42A002ACUL))) +#define bM4_MPU_RGD5_MPURG5ADDR7 (*((volatile unsigned int*)(0x42A002B0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR8 (*((volatile unsigned int*)(0x42A002B4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR9 (*((volatile unsigned int*)(0x42A002B8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR10 (*((volatile unsigned int*)(0x42A002BCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR11 (*((volatile unsigned int*)(0x42A002C0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR12 (*((volatile unsigned int*)(0x42A002C4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR13 (*((volatile unsigned int*)(0x42A002C8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR14 (*((volatile unsigned int*)(0x42A002CCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR15 (*((volatile unsigned int*)(0x42A002D0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR16 (*((volatile unsigned int*)(0x42A002D4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR17 (*((volatile unsigned int*)(0x42A002D8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR18 (*((volatile unsigned int*)(0x42A002DCUL))) +#define bM4_MPU_RGD5_MPURG5ADDR19 (*((volatile unsigned int*)(0x42A002E0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR20 (*((volatile unsigned int*)(0x42A002E4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR21 (*((volatile unsigned int*)(0x42A002E8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR22 (*((volatile unsigned int*)(0x42A002ECUL))) +#define bM4_MPU_RGD5_MPURG5ADDR23 (*((volatile unsigned int*)(0x42A002F0UL))) +#define bM4_MPU_RGD5_MPURG5ADDR24 (*((volatile unsigned int*)(0x42A002F4UL))) +#define bM4_MPU_RGD5_MPURG5ADDR25 (*((volatile unsigned int*)(0x42A002F8UL))) +#define bM4_MPU_RGD5_MPURG5ADDR26 (*((volatile unsigned int*)(0x42A002FCUL))) +#define bM4_MPU_RGD6_MPURG6SIZE0 (*((volatile unsigned int*)(0x42A00300UL))) +#define bM4_MPU_RGD6_MPURG6SIZE1 (*((volatile unsigned int*)(0x42A00304UL))) +#define bM4_MPU_RGD6_MPURG6SIZE2 (*((volatile unsigned int*)(0x42A00308UL))) +#define bM4_MPU_RGD6_MPURG6SIZE3 (*((volatile unsigned int*)(0x42A0030CUL))) +#define bM4_MPU_RGD6_MPURG6SIZE4 (*((volatile unsigned int*)(0x42A00310UL))) +#define bM4_MPU_RGD6_MPURG6ADDR0 (*((volatile unsigned int*)(0x42A00314UL))) +#define bM4_MPU_RGD6_MPURG6ADDR1 (*((volatile unsigned int*)(0x42A00318UL))) +#define bM4_MPU_RGD6_MPURG6ADDR2 (*((volatile unsigned int*)(0x42A0031CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR3 (*((volatile unsigned int*)(0x42A00320UL))) +#define bM4_MPU_RGD6_MPURG6ADDR4 (*((volatile unsigned int*)(0x42A00324UL))) +#define bM4_MPU_RGD6_MPURG6ADDR5 (*((volatile unsigned int*)(0x42A00328UL))) +#define bM4_MPU_RGD6_MPURG6ADDR6 (*((volatile unsigned int*)(0x42A0032CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR7 (*((volatile unsigned int*)(0x42A00330UL))) +#define bM4_MPU_RGD6_MPURG6ADDR8 (*((volatile unsigned int*)(0x42A00334UL))) +#define bM4_MPU_RGD6_MPURG6ADDR9 (*((volatile unsigned int*)(0x42A00338UL))) +#define bM4_MPU_RGD6_MPURG6ADDR10 (*((volatile unsigned int*)(0x42A0033CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR11 (*((volatile unsigned int*)(0x42A00340UL))) +#define bM4_MPU_RGD6_MPURG6ADDR12 (*((volatile unsigned int*)(0x42A00344UL))) +#define bM4_MPU_RGD6_MPURG6ADDR13 (*((volatile unsigned int*)(0x42A00348UL))) +#define bM4_MPU_RGD6_MPURG6ADDR14 (*((volatile unsigned int*)(0x42A0034CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR15 (*((volatile unsigned int*)(0x42A00350UL))) +#define bM4_MPU_RGD6_MPURG6ADDR16 (*((volatile unsigned int*)(0x42A00354UL))) +#define bM4_MPU_RGD6_MPURG6ADDR17 (*((volatile unsigned int*)(0x42A00358UL))) +#define bM4_MPU_RGD6_MPURG6ADDR18 (*((volatile unsigned int*)(0x42A0035CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR19 (*((volatile unsigned int*)(0x42A00360UL))) +#define bM4_MPU_RGD6_MPURG6ADDR20 (*((volatile unsigned int*)(0x42A00364UL))) +#define bM4_MPU_RGD6_MPURG6ADDR21 (*((volatile unsigned int*)(0x42A00368UL))) +#define bM4_MPU_RGD6_MPURG6ADDR22 (*((volatile unsigned int*)(0x42A0036CUL))) +#define bM4_MPU_RGD6_MPURG6ADDR23 (*((volatile unsigned int*)(0x42A00370UL))) +#define bM4_MPU_RGD6_MPURG6ADDR24 (*((volatile unsigned int*)(0x42A00374UL))) +#define bM4_MPU_RGD6_MPURG6ADDR25 (*((volatile unsigned int*)(0x42A00378UL))) +#define bM4_MPU_RGD6_MPURG6ADDR26 (*((volatile unsigned int*)(0x42A0037CUL))) +#define bM4_MPU_RGD7_MPURG7SIZE0 (*((volatile unsigned int*)(0x42A00380UL))) +#define bM4_MPU_RGD7_MPURG7SIZE1 (*((volatile unsigned int*)(0x42A00384UL))) +#define bM4_MPU_RGD7_MPURG7SIZE2 (*((volatile unsigned int*)(0x42A00388UL))) +#define bM4_MPU_RGD7_MPURG7SIZE3 (*((volatile unsigned int*)(0x42A0038CUL))) +#define bM4_MPU_RGD7_MPURG7SIZE4 (*((volatile unsigned int*)(0x42A00390UL))) +#define bM4_MPU_RGD7_MPURG7ADDR0 (*((volatile unsigned int*)(0x42A00394UL))) +#define bM4_MPU_RGD7_MPURG7ADDR1 (*((volatile unsigned int*)(0x42A00398UL))) +#define bM4_MPU_RGD7_MPURG7ADDR2 (*((volatile unsigned int*)(0x42A0039CUL))) +#define bM4_MPU_RGD7_MPURG7ADDR3 (*((volatile unsigned int*)(0x42A003A0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR4 (*((volatile unsigned int*)(0x42A003A4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR5 (*((volatile unsigned int*)(0x42A003A8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR6 (*((volatile unsigned int*)(0x42A003ACUL))) +#define bM4_MPU_RGD7_MPURG7ADDR7 (*((volatile unsigned int*)(0x42A003B0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR8 (*((volatile unsigned int*)(0x42A003B4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR9 (*((volatile unsigned int*)(0x42A003B8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR10 (*((volatile unsigned int*)(0x42A003BCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR11 (*((volatile unsigned int*)(0x42A003C0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR12 (*((volatile unsigned int*)(0x42A003C4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR13 (*((volatile unsigned int*)(0x42A003C8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR14 (*((volatile unsigned int*)(0x42A003CCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR15 (*((volatile unsigned int*)(0x42A003D0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR16 (*((volatile unsigned int*)(0x42A003D4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR17 (*((volatile unsigned int*)(0x42A003D8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR18 (*((volatile unsigned int*)(0x42A003DCUL))) +#define bM4_MPU_RGD7_MPURG7ADDR19 (*((volatile unsigned int*)(0x42A003E0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR20 (*((volatile unsigned int*)(0x42A003E4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR21 (*((volatile unsigned int*)(0x42A003E8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR22 (*((volatile unsigned int*)(0x42A003ECUL))) +#define bM4_MPU_RGD7_MPURG7ADDR23 (*((volatile unsigned int*)(0x42A003F0UL))) +#define bM4_MPU_RGD7_MPURG7ADDR24 (*((volatile unsigned int*)(0x42A003F4UL))) +#define bM4_MPU_RGD7_MPURG7ADDR25 (*((volatile unsigned int*)(0x42A003F8UL))) +#define bM4_MPU_RGD7_MPURG7ADDR26 (*((volatile unsigned int*)(0x42A003FCUL))) +#define bM4_MPU_RGD8_MPURG8SIZE0 (*((volatile unsigned int*)(0x42A00400UL))) +#define bM4_MPU_RGD8_MPURG8SIZE1 (*((volatile unsigned int*)(0x42A00404UL))) +#define bM4_MPU_RGD8_MPURG8SIZE2 (*((volatile unsigned int*)(0x42A00408UL))) +#define bM4_MPU_RGD8_MPURG8SIZE3 (*((volatile unsigned int*)(0x42A0040CUL))) +#define bM4_MPU_RGD8_MPURG8SIZE4 (*((volatile unsigned int*)(0x42A00410UL))) +#define bM4_MPU_RGD8_MPURG8ADDR0 (*((volatile unsigned int*)(0x42A00414UL))) +#define bM4_MPU_RGD8_MPURG8ADDR1 (*((volatile unsigned int*)(0x42A00418UL))) +#define bM4_MPU_RGD8_MPURG8ADDR2 (*((volatile unsigned int*)(0x42A0041CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR3 (*((volatile unsigned int*)(0x42A00420UL))) +#define bM4_MPU_RGD8_MPURG8ADDR4 (*((volatile unsigned int*)(0x42A00424UL))) +#define bM4_MPU_RGD8_MPURG8ADDR5 (*((volatile unsigned int*)(0x42A00428UL))) +#define bM4_MPU_RGD8_MPURG8ADDR6 (*((volatile unsigned int*)(0x42A0042CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR7 (*((volatile unsigned int*)(0x42A00430UL))) +#define bM4_MPU_RGD8_MPURG8ADDR8 (*((volatile unsigned int*)(0x42A00434UL))) +#define bM4_MPU_RGD8_MPURG8ADDR9 (*((volatile unsigned int*)(0x42A00438UL))) +#define bM4_MPU_RGD8_MPURG8ADDR10 (*((volatile unsigned int*)(0x42A0043CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR11 (*((volatile unsigned int*)(0x42A00440UL))) +#define bM4_MPU_RGD8_MPURG8ADDR12 (*((volatile unsigned int*)(0x42A00444UL))) +#define bM4_MPU_RGD8_MPURG8ADDR13 (*((volatile unsigned int*)(0x42A00448UL))) +#define bM4_MPU_RGD8_MPURG8ADDR14 (*((volatile unsigned int*)(0x42A0044CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR15 (*((volatile unsigned int*)(0x42A00450UL))) +#define bM4_MPU_RGD8_MPURG8ADDR16 (*((volatile unsigned int*)(0x42A00454UL))) +#define bM4_MPU_RGD8_MPURG8ADDR17 (*((volatile unsigned int*)(0x42A00458UL))) +#define bM4_MPU_RGD8_MPURG8ADDR18 (*((volatile unsigned int*)(0x42A0045CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR19 (*((volatile unsigned int*)(0x42A00460UL))) +#define bM4_MPU_RGD8_MPURG8ADDR20 (*((volatile unsigned int*)(0x42A00464UL))) +#define bM4_MPU_RGD8_MPURG8ADDR21 (*((volatile unsigned int*)(0x42A00468UL))) +#define bM4_MPU_RGD8_MPURG8ADDR22 (*((volatile unsigned int*)(0x42A0046CUL))) +#define bM4_MPU_RGD8_MPURG8ADDR23 (*((volatile unsigned int*)(0x42A00470UL))) +#define bM4_MPU_RGD8_MPURG8ADDR24 (*((volatile unsigned int*)(0x42A00474UL))) +#define bM4_MPU_RGD8_MPURG8ADDR25 (*((volatile unsigned int*)(0x42A00478UL))) +#define bM4_MPU_RGD8_MPURG8ADDR26 (*((volatile unsigned int*)(0x42A0047CUL))) +#define bM4_MPU_RGD9_MPURG9SIZE0 (*((volatile unsigned int*)(0x42A00480UL))) +#define bM4_MPU_RGD9_MPURG9SIZE1 (*((volatile unsigned int*)(0x42A00484UL))) +#define bM4_MPU_RGD9_MPURG9SIZE2 (*((volatile unsigned int*)(0x42A00488UL))) +#define bM4_MPU_RGD9_MPURG9SIZE3 (*((volatile unsigned int*)(0x42A0048CUL))) +#define bM4_MPU_RGD9_MPURG9SIZE4 (*((volatile unsigned int*)(0x42A00490UL))) +#define bM4_MPU_RGD9_MPURG9ADDR0 (*((volatile unsigned int*)(0x42A00494UL))) +#define bM4_MPU_RGD9_MPURG9ADDR1 (*((volatile unsigned int*)(0x42A00498UL))) +#define bM4_MPU_RGD9_MPURG9ADDR2 (*((volatile unsigned int*)(0x42A0049CUL))) +#define bM4_MPU_RGD9_MPURG9ADDR3 (*((volatile unsigned int*)(0x42A004A0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR4 (*((volatile unsigned int*)(0x42A004A4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR5 (*((volatile unsigned int*)(0x42A004A8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR6 (*((volatile unsigned int*)(0x42A004ACUL))) +#define bM4_MPU_RGD9_MPURG9ADDR7 (*((volatile unsigned int*)(0x42A004B0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR8 (*((volatile unsigned int*)(0x42A004B4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR9 (*((volatile unsigned int*)(0x42A004B8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR10 (*((volatile unsigned int*)(0x42A004BCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR11 (*((volatile unsigned int*)(0x42A004C0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR12 (*((volatile unsigned int*)(0x42A004C4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR13 (*((volatile unsigned int*)(0x42A004C8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR14 (*((volatile unsigned int*)(0x42A004CCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR15 (*((volatile unsigned int*)(0x42A004D0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR16 (*((volatile unsigned int*)(0x42A004D4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR17 (*((volatile unsigned int*)(0x42A004D8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR18 (*((volatile unsigned int*)(0x42A004DCUL))) +#define bM4_MPU_RGD9_MPURG9ADDR19 (*((volatile unsigned int*)(0x42A004E0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR20 (*((volatile unsigned int*)(0x42A004E4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR21 (*((volatile unsigned int*)(0x42A004E8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR22 (*((volatile unsigned int*)(0x42A004ECUL))) +#define bM4_MPU_RGD9_MPURG9ADDR23 (*((volatile unsigned int*)(0x42A004F0UL))) +#define bM4_MPU_RGD9_MPURG9ADDR24 (*((volatile unsigned int*)(0x42A004F4UL))) +#define bM4_MPU_RGD9_MPURG9ADDR25 (*((volatile unsigned int*)(0x42A004F8UL))) +#define bM4_MPU_RGD9_MPURG9ADDR26 (*((volatile unsigned int*)(0x42A004FCUL))) +#define bM4_MPU_RGD10_MPURG10SIZE0 (*((volatile unsigned int*)(0x42A00500UL))) +#define bM4_MPU_RGD10_MPURG10SIZE1 (*((volatile unsigned int*)(0x42A00504UL))) +#define bM4_MPU_RGD10_MPURG10SIZE2 (*((volatile unsigned int*)(0x42A00508UL))) +#define bM4_MPU_RGD10_MPURG10SIZE3 (*((volatile unsigned int*)(0x42A0050CUL))) +#define bM4_MPU_RGD10_MPURG10SIZE4 (*((volatile unsigned int*)(0x42A00510UL))) +#define bM4_MPU_RGD10_MPURG10ADDR0 (*((volatile unsigned int*)(0x42A00514UL))) +#define bM4_MPU_RGD10_MPURG10ADDR1 (*((volatile unsigned int*)(0x42A00518UL))) +#define bM4_MPU_RGD10_MPURG10ADDR2 (*((volatile unsigned int*)(0x42A0051CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR3 (*((volatile unsigned int*)(0x42A00520UL))) +#define bM4_MPU_RGD10_MPURG10ADDR4 (*((volatile unsigned int*)(0x42A00524UL))) +#define bM4_MPU_RGD10_MPURG10ADDR5 (*((volatile unsigned int*)(0x42A00528UL))) +#define bM4_MPU_RGD10_MPURG10ADDR6 (*((volatile unsigned int*)(0x42A0052CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR7 (*((volatile unsigned int*)(0x42A00530UL))) +#define bM4_MPU_RGD10_MPURG10ADDR8 (*((volatile unsigned int*)(0x42A00534UL))) +#define bM4_MPU_RGD10_MPURG10ADDR9 (*((volatile unsigned int*)(0x42A00538UL))) +#define bM4_MPU_RGD10_MPURG10ADDR10 (*((volatile unsigned int*)(0x42A0053CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR11 (*((volatile unsigned int*)(0x42A00540UL))) +#define bM4_MPU_RGD10_MPURG10ADDR12 (*((volatile unsigned int*)(0x42A00544UL))) +#define bM4_MPU_RGD10_MPURG10ADDR13 (*((volatile unsigned int*)(0x42A00548UL))) +#define bM4_MPU_RGD10_MPURG10ADDR14 (*((volatile unsigned int*)(0x42A0054CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR15 (*((volatile unsigned int*)(0x42A00550UL))) +#define bM4_MPU_RGD10_MPURG10ADDR16 (*((volatile unsigned int*)(0x42A00554UL))) +#define bM4_MPU_RGD10_MPURG10ADDR17 (*((volatile unsigned int*)(0x42A00558UL))) +#define bM4_MPU_RGD10_MPURG10ADDR18 (*((volatile unsigned int*)(0x42A0055CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR19 (*((volatile unsigned int*)(0x42A00560UL))) +#define bM4_MPU_RGD10_MPURG10ADDR20 (*((volatile unsigned int*)(0x42A00564UL))) +#define bM4_MPU_RGD10_MPURG10ADDR21 (*((volatile unsigned int*)(0x42A00568UL))) +#define bM4_MPU_RGD10_MPURG10ADDR22 (*((volatile unsigned int*)(0x42A0056CUL))) +#define bM4_MPU_RGD10_MPURG10ADDR23 (*((volatile unsigned int*)(0x42A00570UL))) +#define bM4_MPU_RGD10_MPURG10ADDR24 (*((volatile unsigned int*)(0x42A00574UL))) +#define bM4_MPU_RGD10_MPURG10ADDR25 (*((volatile unsigned int*)(0x42A00578UL))) +#define bM4_MPU_RGD10_MPURG10ADDR26 (*((volatile unsigned int*)(0x42A0057CUL))) +#define bM4_MPU_RGD11_MPURG11SIZE0 (*((volatile unsigned int*)(0x42A00580UL))) +#define bM4_MPU_RGD11_MPURG11SIZE1 (*((volatile unsigned int*)(0x42A00584UL))) +#define bM4_MPU_RGD11_MPURG11SIZE2 (*((volatile unsigned int*)(0x42A00588UL))) +#define bM4_MPU_RGD11_MPURG11SIZE3 (*((volatile unsigned int*)(0x42A0058CUL))) +#define bM4_MPU_RGD11_MPURG11SIZE4 (*((volatile unsigned int*)(0x42A00590UL))) +#define bM4_MPU_RGD11_MPURG11ADDR0 (*((volatile unsigned int*)(0x42A00594UL))) +#define bM4_MPU_RGD11_MPURG11ADDR1 (*((volatile unsigned int*)(0x42A00598UL))) +#define bM4_MPU_RGD11_MPURG11ADDR2 (*((volatile unsigned int*)(0x42A0059CUL))) +#define bM4_MPU_RGD11_MPURG11ADDR3 (*((volatile unsigned int*)(0x42A005A0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR4 (*((volatile unsigned int*)(0x42A005A4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR5 (*((volatile unsigned int*)(0x42A005A8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR6 (*((volatile unsigned int*)(0x42A005ACUL))) +#define bM4_MPU_RGD11_MPURG11ADDR7 (*((volatile unsigned int*)(0x42A005B0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR8 (*((volatile unsigned int*)(0x42A005B4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR9 (*((volatile unsigned int*)(0x42A005B8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR10 (*((volatile unsigned int*)(0x42A005BCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR11 (*((volatile unsigned int*)(0x42A005C0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR12 (*((volatile unsigned int*)(0x42A005C4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR13 (*((volatile unsigned int*)(0x42A005C8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR14 (*((volatile unsigned int*)(0x42A005CCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR15 (*((volatile unsigned int*)(0x42A005D0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR16 (*((volatile unsigned int*)(0x42A005D4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR17 (*((volatile unsigned int*)(0x42A005D8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR18 (*((volatile unsigned int*)(0x42A005DCUL))) +#define bM4_MPU_RGD11_MPURG11ADDR19 (*((volatile unsigned int*)(0x42A005E0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR20 (*((volatile unsigned int*)(0x42A005E4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR21 (*((volatile unsigned int*)(0x42A005E8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR22 (*((volatile unsigned int*)(0x42A005ECUL))) +#define bM4_MPU_RGD11_MPURG11ADDR23 (*((volatile unsigned int*)(0x42A005F0UL))) +#define bM4_MPU_RGD11_MPURG11ADDR24 (*((volatile unsigned int*)(0x42A005F4UL))) +#define bM4_MPU_RGD11_MPURG11ADDR25 (*((volatile unsigned int*)(0x42A005F8UL))) +#define bM4_MPU_RGD11_MPURG11ADDR26 (*((volatile unsigned int*)(0x42A005FCUL))) +#define bM4_MPU_RGD12_MPURG12SIZE0 (*((volatile unsigned int*)(0x42A00600UL))) +#define bM4_MPU_RGD12_MPURG12SIZE1 (*((volatile unsigned int*)(0x42A00604UL))) +#define bM4_MPU_RGD12_MPURG12SIZE2 (*((volatile unsigned int*)(0x42A00608UL))) +#define bM4_MPU_RGD12_MPURG12SIZE3 (*((volatile unsigned int*)(0x42A0060CUL))) +#define bM4_MPU_RGD12_MPURG12SIZE4 (*((volatile unsigned int*)(0x42A00610UL))) +#define bM4_MPU_RGD12_MPURG12ADDR0 (*((volatile unsigned int*)(0x42A00614UL))) +#define bM4_MPU_RGD12_MPURG12ADDR1 (*((volatile unsigned int*)(0x42A00618UL))) +#define bM4_MPU_RGD12_MPURG12ADDR2 (*((volatile unsigned int*)(0x42A0061CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR3 (*((volatile unsigned int*)(0x42A00620UL))) +#define bM4_MPU_RGD12_MPURG12ADDR4 (*((volatile unsigned int*)(0x42A00624UL))) +#define bM4_MPU_RGD12_MPURG12ADDR5 (*((volatile unsigned int*)(0x42A00628UL))) +#define bM4_MPU_RGD12_MPURG12ADDR6 (*((volatile unsigned int*)(0x42A0062CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR7 (*((volatile unsigned int*)(0x42A00630UL))) +#define bM4_MPU_RGD12_MPURG12ADDR8 (*((volatile unsigned int*)(0x42A00634UL))) +#define bM4_MPU_RGD12_MPURG12ADDR9 (*((volatile unsigned int*)(0x42A00638UL))) +#define bM4_MPU_RGD12_MPURG12ADDR10 (*((volatile unsigned int*)(0x42A0063CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR11 (*((volatile unsigned int*)(0x42A00640UL))) +#define bM4_MPU_RGD12_MPURG12ADDR12 (*((volatile unsigned int*)(0x42A00644UL))) +#define bM4_MPU_RGD12_MPURG12ADDR13 (*((volatile unsigned int*)(0x42A00648UL))) +#define bM4_MPU_RGD12_MPURG12ADDR14 (*((volatile unsigned int*)(0x42A0064CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR15 (*((volatile unsigned int*)(0x42A00650UL))) +#define bM4_MPU_RGD12_MPURG12ADDR16 (*((volatile unsigned int*)(0x42A00654UL))) +#define bM4_MPU_RGD12_MPURG12ADDR17 (*((volatile unsigned int*)(0x42A00658UL))) +#define bM4_MPU_RGD12_MPURG12ADDR18 (*((volatile unsigned int*)(0x42A0065CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR19 (*((volatile unsigned int*)(0x42A00660UL))) +#define bM4_MPU_RGD12_MPURG12ADDR20 (*((volatile unsigned int*)(0x42A00664UL))) +#define bM4_MPU_RGD12_MPURG12ADDR21 (*((volatile unsigned int*)(0x42A00668UL))) +#define bM4_MPU_RGD12_MPURG12ADDR22 (*((volatile unsigned int*)(0x42A0066CUL))) +#define bM4_MPU_RGD12_MPURG12ADDR23 (*((volatile unsigned int*)(0x42A00670UL))) +#define bM4_MPU_RGD12_MPURG12ADDR24 (*((volatile unsigned int*)(0x42A00674UL))) +#define bM4_MPU_RGD12_MPURG12ADDR25 (*((volatile unsigned int*)(0x42A00678UL))) +#define bM4_MPU_RGD12_MPURG12ADDR26 (*((volatile unsigned int*)(0x42A0067CUL))) +#define bM4_MPU_RGD13_MPURG13SIZE0 (*((volatile unsigned int*)(0x42A00680UL))) +#define bM4_MPU_RGD13_MPURG13SIZE1 (*((volatile unsigned int*)(0x42A00684UL))) +#define bM4_MPU_RGD13_MPURG13SIZE2 (*((volatile unsigned int*)(0x42A00688UL))) +#define bM4_MPU_RGD13_MPURG13SIZE3 (*((volatile unsigned int*)(0x42A0068CUL))) +#define bM4_MPU_RGD13_MPURG13SIZE4 (*((volatile unsigned int*)(0x42A00690UL))) +#define bM4_MPU_RGD13_MPURG13ADDR0 (*((volatile unsigned int*)(0x42A00694UL))) +#define bM4_MPU_RGD13_MPURG13ADDR1 (*((volatile unsigned int*)(0x42A00698UL))) +#define bM4_MPU_RGD13_MPURG13ADDR2 (*((volatile unsigned int*)(0x42A0069CUL))) +#define bM4_MPU_RGD13_MPURG13ADDR3 (*((volatile unsigned int*)(0x42A006A0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR4 (*((volatile unsigned int*)(0x42A006A4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR5 (*((volatile unsigned int*)(0x42A006A8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR6 (*((volatile unsigned int*)(0x42A006ACUL))) +#define bM4_MPU_RGD13_MPURG13ADDR7 (*((volatile unsigned int*)(0x42A006B0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR8 (*((volatile unsigned int*)(0x42A006B4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR9 (*((volatile unsigned int*)(0x42A006B8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR10 (*((volatile unsigned int*)(0x42A006BCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR11 (*((volatile unsigned int*)(0x42A006C0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR12 (*((volatile unsigned int*)(0x42A006C4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR13 (*((volatile unsigned int*)(0x42A006C8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR14 (*((volatile unsigned int*)(0x42A006CCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR15 (*((volatile unsigned int*)(0x42A006D0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR16 (*((volatile unsigned int*)(0x42A006D4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR17 (*((volatile unsigned int*)(0x42A006D8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR18 (*((volatile unsigned int*)(0x42A006DCUL))) +#define bM4_MPU_RGD13_MPURG13ADDR19 (*((volatile unsigned int*)(0x42A006E0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR20 (*((volatile unsigned int*)(0x42A006E4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR21 (*((volatile unsigned int*)(0x42A006E8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR22 (*((volatile unsigned int*)(0x42A006ECUL))) +#define bM4_MPU_RGD13_MPURG13ADDR23 (*((volatile unsigned int*)(0x42A006F0UL))) +#define bM4_MPU_RGD13_MPURG13ADDR24 (*((volatile unsigned int*)(0x42A006F4UL))) +#define bM4_MPU_RGD13_MPURG13ADDR25 (*((volatile unsigned int*)(0x42A006F8UL))) +#define bM4_MPU_RGD13_MPURG13ADDR26 (*((volatile unsigned int*)(0x42A006FCUL))) +#define bM4_MPU_RGD14_MPURG14SIZE0 (*((volatile unsigned int*)(0x42A00700UL))) +#define bM4_MPU_RGD14_MPURG14SIZE1 (*((volatile unsigned int*)(0x42A00704UL))) +#define bM4_MPU_RGD14_MPURG14SIZE2 (*((volatile unsigned int*)(0x42A00708UL))) +#define bM4_MPU_RGD14_MPURG14SIZE3 (*((volatile unsigned int*)(0x42A0070CUL))) +#define bM4_MPU_RGD14_MPURG14SIZE4 (*((volatile unsigned int*)(0x42A00710UL))) +#define bM4_MPU_RGD14_MPURG14ADDR0 (*((volatile unsigned int*)(0x42A00714UL))) +#define bM4_MPU_RGD14_MPURG14ADDR1 (*((volatile unsigned int*)(0x42A00718UL))) +#define bM4_MPU_RGD14_MPURG14ADDR2 (*((volatile unsigned int*)(0x42A0071CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR3 (*((volatile unsigned int*)(0x42A00720UL))) +#define bM4_MPU_RGD14_MPURG14ADDR4 (*((volatile unsigned int*)(0x42A00724UL))) +#define bM4_MPU_RGD14_MPURG14ADDR5 (*((volatile unsigned int*)(0x42A00728UL))) +#define bM4_MPU_RGD14_MPURG14ADDR6 (*((volatile unsigned int*)(0x42A0072CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR7 (*((volatile unsigned int*)(0x42A00730UL))) +#define bM4_MPU_RGD14_MPURG14ADDR8 (*((volatile unsigned int*)(0x42A00734UL))) +#define bM4_MPU_RGD14_MPURG14ADDR9 (*((volatile unsigned int*)(0x42A00738UL))) +#define bM4_MPU_RGD14_MPURG14ADDR10 (*((volatile unsigned int*)(0x42A0073CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR11 (*((volatile unsigned int*)(0x42A00740UL))) +#define bM4_MPU_RGD14_MPURG14ADDR12 (*((volatile unsigned int*)(0x42A00744UL))) +#define bM4_MPU_RGD14_MPURG14ADDR13 (*((volatile unsigned int*)(0x42A00748UL))) +#define bM4_MPU_RGD14_MPURG14ADDR14 (*((volatile unsigned int*)(0x42A0074CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR15 (*((volatile unsigned int*)(0x42A00750UL))) +#define bM4_MPU_RGD14_MPURG14ADDR16 (*((volatile unsigned int*)(0x42A00754UL))) +#define bM4_MPU_RGD14_MPURG14ADDR17 (*((volatile unsigned int*)(0x42A00758UL))) +#define bM4_MPU_RGD14_MPURG14ADDR18 (*((volatile unsigned int*)(0x42A0075CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR19 (*((volatile unsigned int*)(0x42A00760UL))) +#define bM4_MPU_RGD14_MPURG14ADDR20 (*((volatile unsigned int*)(0x42A00764UL))) +#define bM4_MPU_RGD14_MPURG14ADDR21 (*((volatile unsigned int*)(0x42A00768UL))) +#define bM4_MPU_RGD14_MPURG14ADDR22 (*((volatile unsigned int*)(0x42A0076CUL))) +#define bM4_MPU_RGD14_MPURG14ADDR23 (*((volatile unsigned int*)(0x42A00770UL))) +#define bM4_MPU_RGD14_MPURG14ADDR24 (*((volatile unsigned int*)(0x42A00774UL))) +#define bM4_MPU_RGD14_MPURG14ADDR25 (*((volatile unsigned int*)(0x42A00778UL))) +#define bM4_MPU_RGD14_MPURG14ADDR26 (*((volatile unsigned int*)(0x42A0077CUL))) +#define bM4_MPU_RGD15_MPURG15SIZE0 (*((volatile unsigned int*)(0x42A00780UL))) +#define bM4_MPU_RGD15_MPURG15SIZE1 (*((volatile unsigned int*)(0x42A00784UL))) +#define bM4_MPU_RGD15_MPURG15SIZE2 (*((volatile unsigned int*)(0x42A00788UL))) +#define bM4_MPU_RGD15_MPURG15SIZE3 (*((volatile unsigned int*)(0x42A0078CUL))) +#define bM4_MPU_RGD15_MPURG15SIZE4 (*((volatile unsigned int*)(0x42A00790UL))) +#define bM4_MPU_RGD15_MPURG15ADDR0 (*((volatile unsigned int*)(0x42A00794UL))) +#define bM4_MPU_RGD15_MPURG15ADDR1 (*((volatile unsigned int*)(0x42A00798UL))) +#define bM4_MPU_RGD15_MPURG15ADDR2 (*((volatile unsigned int*)(0x42A0079CUL))) +#define bM4_MPU_RGD15_MPURG15ADDR3 (*((volatile unsigned int*)(0x42A007A0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR4 (*((volatile unsigned int*)(0x42A007A4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR5 (*((volatile unsigned int*)(0x42A007A8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR6 (*((volatile unsigned int*)(0x42A007ACUL))) +#define bM4_MPU_RGD15_MPURG15ADDR7 (*((volatile unsigned int*)(0x42A007B0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR8 (*((volatile unsigned int*)(0x42A007B4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR9 (*((volatile unsigned int*)(0x42A007B8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR10 (*((volatile unsigned int*)(0x42A007BCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR11 (*((volatile unsigned int*)(0x42A007C0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR12 (*((volatile unsigned int*)(0x42A007C4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR13 (*((volatile unsigned int*)(0x42A007C8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR14 (*((volatile unsigned int*)(0x42A007CCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR15 (*((volatile unsigned int*)(0x42A007D0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR16 (*((volatile unsigned int*)(0x42A007D4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR17 (*((volatile unsigned int*)(0x42A007D8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR18 (*((volatile unsigned int*)(0x42A007DCUL))) +#define bM4_MPU_RGD15_MPURG15ADDR19 (*((volatile unsigned int*)(0x42A007E0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR20 (*((volatile unsigned int*)(0x42A007E4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR21 (*((volatile unsigned int*)(0x42A007E8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR22 (*((volatile unsigned int*)(0x42A007ECUL))) +#define bM4_MPU_RGD15_MPURG15ADDR23 (*((volatile unsigned int*)(0x42A007F0UL))) +#define bM4_MPU_RGD15_MPURG15ADDR24 (*((volatile unsigned int*)(0x42A007F4UL))) +#define bM4_MPU_RGD15_MPURG15ADDR25 (*((volatile unsigned int*)(0x42A007F8UL))) +#define bM4_MPU_RGD15_MPURG15ADDR26 (*((volatile unsigned int*)(0x42A007FCUL))) +#define bM4_MPU_RGCR0_S2RG0RP (*((volatile unsigned int*)(0x42A00800UL))) +#define bM4_MPU_RGCR0_S2RG0WP (*((volatile unsigned int*)(0x42A00804UL))) +#define bM4_MPU_RGCR0_S2RG0E (*((volatile unsigned int*)(0x42A0081CUL))) +#define bM4_MPU_RGCR0_S1RG0RP (*((volatile unsigned int*)(0x42A00820UL))) +#define bM4_MPU_RGCR0_S1RG0WP (*((volatile unsigned int*)(0x42A00824UL))) +#define bM4_MPU_RGCR0_S1RG0E (*((volatile unsigned int*)(0x42A0083CUL))) +#define bM4_MPU_RGCR0_FRG0RP (*((volatile unsigned int*)(0x42A00840UL))) +#define bM4_MPU_RGCR0_FRG0WP (*((volatile unsigned int*)(0x42A00844UL))) +#define bM4_MPU_RGCR0_FRG0E (*((volatile unsigned int*)(0x42A0085CUL))) +#define bM4_MPU_RGCR1_S2RG1RP (*((volatile unsigned int*)(0x42A00880UL))) +#define bM4_MPU_RGCR1_S2RG1WP (*((volatile unsigned int*)(0x42A00884UL))) +#define bM4_MPU_RGCR1_S2RG1E (*((volatile unsigned int*)(0x42A0089CUL))) +#define bM4_MPU_RGCR1_S1RG1RP (*((volatile unsigned int*)(0x42A008A0UL))) +#define bM4_MPU_RGCR1_S1RG1WP (*((volatile unsigned int*)(0x42A008A4UL))) +#define bM4_MPU_RGCR1_S1RG1E (*((volatile unsigned int*)(0x42A008BCUL))) +#define bM4_MPU_RGCR1_FRG1RP (*((volatile unsigned int*)(0x42A008C0UL))) +#define bM4_MPU_RGCR1_FRG1WP (*((volatile unsigned int*)(0x42A008C4UL))) +#define bM4_MPU_RGCR1_FRG1E (*((volatile unsigned int*)(0x42A008DCUL))) +#define bM4_MPU_RGCR2_S2RG2RP (*((volatile unsigned int*)(0x42A00900UL))) +#define bM4_MPU_RGCR2_S2RG2WP (*((volatile unsigned int*)(0x42A00904UL))) +#define bM4_MPU_RGCR2_S2RG2E (*((volatile unsigned int*)(0x42A0091CUL))) +#define bM4_MPU_RGCR2_S1RG2RP (*((volatile unsigned int*)(0x42A00920UL))) +#define bM4_MPU_RGCR2_S1RG2WP (*((volatile unsigned int*)(0x42A00924UL))) +#define bM4_MPU_RGCR2_S1RG2E (*((volatile unsigned int*)(0x42A0093CUL))) +#define bM4_MPU_RGCR2_FRG2RP (*((volatile unsigned int*)(0x42A00940UL))) +#define bM4_MPU_RGCR2_FRG2WP (*((volatile unsigned int*)(0x42A00944UL))) +#define bM4_MPU_RGCR2_FRG2E (*((volatile unsigned int*)(0x42A0095CUL))) +#define bM4_MPU_RGCR3_S2RG3RP (*((volatile unsigned int*)(0x42A00980UL))) +#define bM4_MPU_RGCR3_S2RG3WP (*((volatile unsigned int*)(0x42A00984UL))) +#define bM4_MPU_RGCR3_S2RG3E (*((volatile unsigned int*)(0x42A0099CUL))) +#define bM4_MPU_RGCR3_S1RG3RP (*((volatile unsigned int*)(0x42A009A0UL))) +#define bM4_MPU_RGCR3_S1RG3WP (*((volatile unsigned int*)(0x42A009A4UL))) +#define bM4_MPU_RGCR3_S1RG3E (*((volatile unsigned int*)(0x42A009BCUL))) +#define bM4_MPU_RGCR3_FRG3RP (*((volatile unsigned int*)(0x42A009C0UL))) +#define bM4_MPU_RGCR3_FRG3WP (*((volatile unsigned int*)(0x42A009C4UL))) +#define bM4_MPU_RGCR3_FRG3E (*((volatile unsigned int*)(0x42A009DCUL))) +#define bM4_MPU_RGCR4_S2RG4RP (*((volatile unsigned int*)(0x42A00A00UL))) +#define bM4_MPU_RGCR4_S2RG4WP (*((volatile unsigned int*)(0x42A00A04UL))) +#define bM4_MPU_RGCR4_S2RG4E (*((volatile unsigned int*)(0x42A00A1CUL))) +#define bM4_MPU_RGCR4_S1RG4RP (*((volatile unsigned int*)(0x42A00A20UL))) +#define bM4_MPU_RGCR4_S1RG4WP (*((volatile unsigned int*)(0x42A00A24UL))) +#define bM4_MPU_RGCR4_S1RG4E (*((volatile unsigned int*)(0x42A00A3CUL))) +#define bM4_MPU_RGCR4_FRG4RP (*((volatile unsigned int*)(0x42A00A40UL))) +#define bM4_MPU_RGCR4_FRG4WP (*((volatile unsigned int*)(0x42A00A44UL))) +#define bM4_MPU_RGCR4_FRG4E (*((volatile unsigned int*)(0x42A00A5CUL))) +#define bM4_MPU_RGCR5_S2RG5RP (*((volatile unsigned int*)(0x42A00A80UL))) +#define bM4_MPU_RGCR5_S2RG5WP (*((volatile unsigned int*)(0x42A00A84UL))) +#define bM4_MPU_RGCR5_S2RG5E (*((volatile unsigned int*)(0x42A00A9CUL))) +#define bM4_MPU_RGCR5_S1RG5RP (*((volatile unsigned int*)(0x42A00AA0UL))) +#define bM4_MPU_RGCR5_S1RG5WP (*((volatile unsigned int*)(0x42A00AA4UL))) +#define bM4_MPU_RGCR5_S1RG5E (*((volatile unsigned int*)(0x42A00ABCUL))) +#define bM4_MPU_RGCR5_FRG5RP (*((volatile unsigned int*)(0x42A00AC0UL))) +#define bM4_MPU_RGCR5_FRG5WP (*((volatile unsigned int*)(0x42A00AC4UL))) +#define bM4_MPU_RGCR5_FRG5E (*((volatile unsigned int*)(0x42A00ADCUL))) +#define bM4_MPU_RGCR6_S2RG6RP (*((volatile unsigned int*)(0x42A00B00UL))) +#define bM4_MPU_RGCR6_S2RG6WP (*((volatile unsigned int*)(0x42A00B04UL))) +#define bM4_MPU_RGCR6_S2RG6E (*((volatile unsigned int*)(0x42A00B1CUL))) +#define bM4_MPU_RGCR6_S1RG6RP (*((volatile unsigned int*)(0x42A00B20UL))) +#define bM4_MPU_RGCR6_S1RG6WP (*((volatile unsigned int*)(0x42A00B24UL))) +#define bM4_MPU_RGCR6_S1RG6E (*((volatile unsigned int*)(0x42A00B3CUL))) +#define bM4_MPU_RGCR6_FRG6RP (*((volatile unsigned int*)(0x42A00B40UL))) +#define bM4_MPU_RGCR6_FRG6WP (*((volatile unsigned int*)(0x42A00B44UL))) +#define bM4_MPU_RGCR6_FRG6E (*((volatile unsigned int*)(0x42A00B5CUL))) +#define bM4_MPU_RGCR7_S2RG7RP (*((volatile unsigned int*)(0x42A00B80UL))) +#define bM4_MPU_RGCR7_S2RG7WP (*((volatile unsigned int*)(0x42A00B84UL))) +#define bM4_MPU_RGCR7_S2RG7E (*((volatile unsigned int*)(0x42A00B9CUL))) +#define bM4_MPU_RGCR7_S1RG7RP (*((volatile unsigned int*)(0x42A00BA0UL))) +#define bM4_MPU_RGCR7_S1RG7WP (*((volatile unsigned int*)(0x42A00BA4UL))) +#define bM4_MPU_RGCR7_S1RG7E (*((volatile unsigned int*)(0x42A00BBCUL))) +#define bM4_MPU_RGCR7_FRG7RP (*((volatile unsigned int*)(0x42A00BC0UL))) +#define bM4_MPU_RGCR7_FRG7WP (*((volatile unsigned int*)(0x42A00BC4UL))) +#define bM4_MPU_RGCR7_FRG7E (*((volatile unsigned int*)(0x42A00BDCUL))) +#define bM4_MPU_RGCR8_S2RG8RP (*((volatile unsigned int*)(0x42A00C00UL))) +#define bM4_MPU_RGCR8_S2RG8WP (*((volatile unsigned int*)(0x42A00C04UL))) +#define bM4_MPU_RGCR8_S2RG8E (*((volatile unsigned int*)(0x42A00C1CUL))) +#define bM4_MPU_RGCR8_S1RG8RP (*((volatile unsigned int*)(0x42A00C20UL))) +#define bM4_MPU_RGCR8_S1RG8WP (*((volatile unsigned int*)(0x42A00C24UL))) +#define bM4_MPU_RGCR8_S1RG8E (*((volatile unsigned int*)(0x42A00C3CUL))) +#define bM4_MPU_RGCR9_S2RG9RP (*((volatile unsigned int*)(0x42A00C80UL))) +#define bM4_MPU_RGCR9_S2RG9WP (*((volatile unsigned int*)(0x42A00C84UL))) +#define bM4_MPU_RGCR9_S2RG9E (*((volatile unsigned int*)(0x42A00C9CUL))) +#define bM4_MPU_RGCR9_S1RG9RP (*((volatile unsigned int*)(0x42A00CA0UL))) +#define bM4_MPU_RGCR9_S1RG9WP (*((volatile unsigned int*)(0x42A00CA4UL))) +#define bM4_MPU_RGCR9_S1RG9E (*((volatile unsigned int*)(0x42A00CBCUL))) +#define bM4_MPU_RGCR10_S2RG10RP (*((volatile unsigned int*)(0x42A00D00UL))) +#define bM4_MPU_RGCR10_S2RG10WP (*((volatile unsigned int*)(0x42A00D04UL))) +#define bM4_MPU_RGCR10_S2RG10E (*((volatile unsigned int*)(0x42A00D1CUL))) +#define bM4_MPU_RGCR10_S1RG10RP (*((volatile unsigned int*)(0x42A00D20UL))) +#define bM4_MPU_RGCR10_S1RG10WP (*((volatile unsigned int*)(0x42A00D24UL))) +#define bM4_MPU_RGCR10_S1RG10E (*((volatile unsigned int*)(0x42A00D3CUL))) +#define bM4_MPU_RGCR11_S2RG11RP (*((volatile unsigned int*)(0x42A00D80UL))) +#define bM4_MPU_RGCR11_S2RG11WP (*((volatile unsigned int*)(0x42A00D84UL))) +#define bM4_MPU_RGCR11_S2RG11E (*((volatile unsigned int*)(0x42A00D9CUL))) +#define bM4_MPU_RGCR11_S1RG11RP (*((volatile unsigned int*)(0x42A00DA0UL))) +#define bM4_MPU_RGCR11_S1RG11WP (*((volatile unsigned int*)(0x42A00DA4UL))) +#define bM4_MPU_RGCR11_S1RG11E (*((volatile unsigned int*)(0x42A00DBCUL))) +#define bM4_MPU_RGCR12_S2RG12RP (*((volatile unsigned int*)(0x42A00E00UL))) +#define bM4_MPU_RGCR12_S2RG12WP (*((volatile unsigned int*)(0x42A00E04UL))) +#define bM4_MPU_RGCR12_S2RG12E (*((volatile unsigned int*)(0x42A00E1CUL))) +#define bM4_MPU_RGCR12_S1RG12RP (*((volatile unsigned int*)(0x42A00E20UL))) +#define bM4_MPU_RGCR12_S1RG12WP (*((volatile unsigned int*)(0x42A00E24UL))) +#define bM4_MPU_RGCR12_S1RG12E (*((volatile unsigned int*)(0x42A00E3CUL))) +#define bM4_MPU_RGCR13_S2RG13RP (*((volatile unsigned int*)(0x42A00E80UL))) +#define bM4_MPU_RGCR13_S2RG13WP (*((volatile unsigned int*)(0x42A00E84UL))) +#define bM4_MPU_RGCR13_S2RG13E (*((volatile unsigned int*)(0x42A00E9CUL))) +#define bM4_MPU_RGCR13_S1RG13RP (*((volatile unsigned int*)(0x42A00EA0UL))) +#define bM4_MPU_RGCR13_S1RG13WP (*((volatile unsigned int*)(0x42A00EA4UL))) +#define bM4_MPU_RGCR13_S1RG13E (*((volatile unsigned int*)(0x42A00EBCUL))) +#define bM4_MPU_RGCR14_S2RG14RP (*((volatile unsigned int*)(0x42A00F00UL))) +#define bM4_MPU_RGCR14_S2RG14WP (*((volatile unsigned int*)(0x42A00F04UL))) +#define bM4_MPU_RGCR14_S2RG14E (*((volatile unsigned int*)(0x42A00F1CUL))) +#define bM4_MPU_RGCR14_S1RG14RP (*((volatile unsigned int*)(0x42A00F20UL))) +#define bM4_MPU_RGCR14_S1RG14WP (*((volatile unsigned int*)(0x42A00F24UL))) +#define bM4_MPU_RGCR14_S1RG14E (*((volatile unsigned int*)(0x42A00F3CUL))) +#define bM4_MPU_RGCR15_S2RG15RP (*((volatile unsigned int*)(0x42A00F80UL))) +#define bM4_MPU_RGCR15_S2RG15WP (*((volatile unsigned int*)(0x42A00F84UL))) +#define bM4_MPU_RGCR15_S2RG15E (*((volatile unsigned int*)(0x42A00F9CUL))) +#define bM4_MPU_RGCR15_S1RG15RP (*((volatile unsigned int*)(0x42A00FA0UL))) +#define bM4_MPU_RGCR15_S1RG15WP (*((volatile unsigned int*)(0x42A00FA4UL))) +#define bM4_MPU_RGCR15_S1RG15E (*((volatile unsigned int*)(0x42A00FBCUL))) +#define bM4_MPU_CR_SMPU2BRP (*((volatile unsigned int*)(0x42A01000UL))) +#define bM4_MPU_CR_SMPU2BWP (*((volatile unsigned int*)(0x42A01004UL))) +#define bM4_MPU_CR_SMPU2ACT0 (*((volatile unsigned int*)(0x42A01008UL))) +#define bM4_MPU_CR_SMPU2ACT1 (*((volatile unsigned int*)(0x42A0100CUL))) +#define bM4_MPU_CR_SMPU2E (*((volatile unsigned int*)(0x42A0101CUL))) +#define bM4_MPU_CR_SMPU1BRP (*((volatile unsigned int*)(0x42A01020UL))) +#define bM4_MPU_CR_SMPU1BWP (*((volatile unsigned int*)(0x42A01024UL))) +#define bM4_MPU_CR_SMPU1ACT0 (*((volatile unsigned int*)(0x42A01028UL))) +#define bM4_MPU_CR_SMPU1ACT1 (*((volatile unsigned int*)(0x42A0102CUL))) +#define bM4_MPU_CR_SMPU1E (*((volatile unsigned int*)(0x42A0103CUL))) +#define bM4_MPU_CR_FMPUBRP (*((volatile unsigned int*)(0x42A01040UL))) +#define bM4_MPU_CR_FMPUBWP (*((volatile unsigned int*)(0x42A01044UL))) +#define bM4_MPU_CR_FMPUACT0 (*((volatile unsigned int*)(0x42A01048UL))) +#define bM4_MPU_CR_FMPUACT1 (*((volatile unsigned int*)(0x42A0104CUL))) +#define bM4_MPU_CR_FMPUE (*((volatile unsigned int*)(0x42A0105CUL))) +#define bM4_MPU_SR_SMPU2EAF (*((volatile unsigned int*)(0x42A01080UL))) +#define bM4_MPU_SR_SMPU1EAF (*((volatile unsigned int*)(0x42A010A0UL))) +#define bM4_MPU_SR_FMPUEAF (*((volatile unsigned int*)(0x42A010C0UL))) +#define bM4_MPU_ECLR_SMPU2ECLR (*((volatile unsigned int*)(0x42A01100UL))) +#define bM4_MPU_ECLR_SMPU1ECLR (*((volatile unsigned int*)(0x42A01120UL))) +#define bM4_MPU_ECLR_FMPUECLR (*((volatile unsigned int*)(0x42A01140UL))) +#define bM4_MPU_WP_MPUWE (*((volatile unsigned int*)(0x42A01180UL))) +#define bM4_MPU_WP_WKEY0 (*((volatile unsigned int*)(0x42A01184UL))) +#define bM4_MPU_WP_WKEY1 (*((volatile unsigned int*)(0x42A01188UL))) +#define bM4_MPU_WP_WKEY2 (*((volatile unsigned int*)(0x42A0118CUL))) +#define bM4_MPU_WP_WKEY3 (*((volatile unsigned int*)(0x42A01190UL))) +#define bM4_MPU_WP_WKEY4 (*((volatile unsigned int*)(0x42A01194UL))) +#define bM4_MPU_WP_WKEY5 (*((volatile unsigned int*)(0x42A01198UL))) +#define bM4_MPU_WP_WKEY6 (*((volatile unsigned int*)(0x42A0119CUL))) +#define bM4_MPU_WP_WKEY7 (*((volatile unsigned int*)(0x42A011A0UL))) +#define bM4_MPU_WP_WKEY8 (*((volatile unsigned int*)(0x42A011A4UL))) +#define bM4_MPU_WP_WKEY9 (*((volatile unsigned int*)(0x42A011A8UL))) +#define bM4_MPU_WP_WKEY10 (*((volatile unsigned int*)(0x42A011ACUL))) +#define bM4_MPU_WP_WKEY11 (*((volatile unsigned int*)(0x42A011B0UL))) +#define bM4_MPU_WP_WKEY12 (*((volatile unsigned int*)(0x42A011B4UL))) +#define bM4_MPU_WP_WKEY13 (*((volatile unsigned int*)(0x42A011B8UL))) +#define bM4_MPU_WP_WKEY14 (*((volatile unsigned int*)(0x42A011BCUL))) +#define bM4_MSTP_FCG0_SRAMH (*((volatile unsigned int*)(0x42900000UL))) +#define bM4_MSTP_FCG0_SRAM12 (*((volatile unsigned int*)(0x42900010UL))) +#define bM4_MSTP_FCG0_SRAM3 (*((volatile unsigned int*)(0x42900020UL))) +#define bM4_MSTP_FCG0_SRAMRET (*((volatile unsigned int*)(0x42900028UL))) +#define bM4_MSTP_FCG0_DMA1 (*((volatile unsigned int*)(0x42900038UL))) +#define bM4_MSTP_FCG0_DMA2 (*((volatile unsigned int*)(0x4290003CUL))) +#define bM4_MSTP_FCG0_FCM (*((volatile unsigned int*)(0x42900040UL))) +#define bM4_MSTP_FCG0_AOS (*((volatile unsigned int*)(0x42900044UL))) +#define bM4_MSTP_FCG0_AES (*((volatile unsigned int*)(0x42900050UL))) +#define bM4_MSTP_FCG0_HASH (*((volatile unsigned int*)(0x42900054UL))) +#define bM4_MSTP_FCG0_TRNG (*((volatile unsigned int*)(0x42900058UL))) +#define bM4_MSTP_FCG0_CRC (*((volatile unsigned int*)(0x4290005CUL))) +#define bM4_MSTP_FCG0_DCU1 (*((volatile unsigned int*)(0x42900060UL))) +#define bM4_MSTP_FCG0_DCU2 (*((volatile unsigned int*)(0x42900064UL))) +#define bM4_MSTP_FCG0_DCU3 (*((volatile unsigned int*)(0x42900068UL))) +#define bM4_MSTP_FCG0_DCU4 (*((volatile unsigned int*)(0x4290006CUL))) +#define bM4_MSTP_FCG0_KEY (*((volatile unsigned int*)(0x4290007CUL))) +#define bM4_MSTP_FCG1_CAN (*((volatile unsigned int*)(0x42900080UL))) +#define bM4_MSTP_FCG1_QSPI (*((volatile unsigned int*)(0x4290008CUL))) +#define bM4_MSTP_FCG1_IIC1 (*((volatile unsigned int*)(0x42900090UL))) +#define bM4_MSTP_FCG1_IIC2 (*((volatile unsigned int*)(0x42900094UL))) +#define bM4_MSTP_FCG1_IIC3 (*((volatile unsigned int*)(0x42900098UL))) +#define bM4_MSTP_FCG1_USBFS (*((volatile unsigned int*)(0x429000A0UL))) +#define bM4_MSTP_FCG1_SDIOC1 (*((volatile unsigned int*)(0x429000A8UL))) +#define bM4_MSTP_FCG1_SDIOC2 (*((volatile unsigned int*)(0x429000ACUL))) +#define bM4_MSTP_FCG1_I2S1 (*((volatile unsigned int*)(0x429000B0UL))) +#define bM4_MSTP_FCG1_I2S2 (*((volatile unsigned int*)(0x429000B4UL))) +#define bM4_MSTP_FCG1_I2S3 (*((volatile unsigned int*)(0x429000B8UL))) +#define bM4_MSTP_FCG1_I2S4 (*((volatile unsigned int*)(0x429000BCUL))) +#define bM4_MSTP_FCG1_SPI1 (*((volatile unsigned int*)(0x429000C0UL))) +#define bM4_MSTP_FCG1_SPI2 (*((volatile unsigned int*)(0x429000C4UL))) +#define bM4_MSTP_FCG1_SPI3 (*((volatile unsigned int*)(0x429000C8UL))) +#define bM4_MSTP_FCG1_SPI4 (*((volatile unsigned int*)(0x429000CCUL))) +#define bM4_MSTP_FCG1_USART1 (*((volatile unsigned int*)(0x429000E0UL))) +#define bM4_MSTP_FCG1_USART2 (*((volatile unsigned int*)(0x429000E4UL))) +#define bM4_MSTP_FCG1_USART3 (*((volatile unsigned int*)(0x429000E8UL))) +#define bM4_MSTP_FCG1_USART4 (*((volatile unsigned int*)(0x429000ECUL))) +#define bM4_MSTP_FCG2_TIMER0_1 (*((volatile unsigned int*)(0x42900100UL))) +#define bM4_MSTP_FCG2_TIMER0_2 (*((volatile unsigned int*)(0x42900104UL))) +#define bM4_MSTP_FCG2_TIMERA_1 (*((volatile unsigned int*)(0x42900108UL))) +#define bM4_MSTP_FCG2_TIMERA_2 (*((volatile unsigned int*)(0x4290010CUL))) +#define bM4_MSTP_FCG2_TIMERA_3 (*((volatile unsigned int*)(0x42900110UL))) +#define bM4_MSTP_FCG2_TIMERA_4 (*((volatile unsigned int*)(0x42900114UL))) +#define bM4_MSTP_FCG2_TIMERA_5 (*((volatile unsigned int*)(0x42900118UL))) +#define bM4_MSTP_FCG2_TIMERA_6 (*((volatile unsigned int*)(0x4290011CUL))) +#define bM4_MSTP_FCG2_TIMER4_1 (*((volatile unsigned int*)(0x42900120UL))) +#define bM4_MSTP_FCG2_TIMER4_2 (*((volatile unsigned int*)(0x42900124UL))) +#define bM4_MSTP_FCG2_TIMER4_3 (*((volatile unsigned int*)(0x42900128UL))) +#define bM4_MSTP_FCG2_EMB (*((volatile unsigned int*)(0x4290013CUL))) +#define bM4_MSTP_FCG2_TIMER6_1 (*((volatile unsigned int*)(0x42900140UL))) +#define bM4_MSTP_FCG2_TIMER6_2 (*((volatile unsigned int*)(0x42900144UL))) +#define bM4_MSTP_FCG2_TIMER6_3 (*((volatile unsigned int*)(0x42900148UL))) +#define bM4_MSTP_FCG3_ADC1 (*((volatile unsigned int*)(0x42900180UL))) +#define bM4_MSTP_FCG3_ADC2 (*((volatile unsigned int*)(0x42900184UL))) +#define bM4_MSTP_FCG3_CMP (*((volatile unsigned int*)(0x429001A0UL))) +#define bM4_MSTP_FCG3_OTS (*((volatile unsigned int*)(0x429001B0UL))) +#define bM4_MSTP_FCG0PC_PRT0 (*((volatile unsigned int*)(0x42900200UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE0 (*((volatile unsigned int*)(0x42900240UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE1 (*((volatile unsigned int*)(0x42900244UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE2 (*((volatile unsigned int*)(0x42900248UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE3 (*((volatile unsigned int*)(0x4290024CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE4 (*((volatile unsigned int*)(0x42900250UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE5 (*((volatile unsigned int*)(0x42900254UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE6 (*((volatile unsigned int*)(0x42900258UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE7 (*((volatile unsigned int*)(0x4290025CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE8 (*((volatile unsigned int*)(0x42900260UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE9 (*((volatile unsigned int*)(0x42900264UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE10 (*((volatile unsigned int*)(0x42900268UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE11 (*((volatile unsigned int*)(0x4290026CUL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE12 (*((volatile unsigned int*)(0x42900270UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE13 (*((volatile unsigned int*)(0x42900274UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE14 (*((volatile unsigned int*)(0x42900278UL))) +#define bM4_MSTP_FCG0PC_FCG0PCWE15 (*((volatile unsigned int*)(0x4290027CUL))) +#define bM4_OTS_CTL_OTSST (*((volatile unsigned int*)(0x42948000UL))) +#define bM4_OTS_CTL_OTSCK (*((volatile unsigned int*)(0x42948004UL))) +#define bM4_OTS_CTL_OTSIE (*((volatile unsigned int*)(0x42948008UL))) +#define bM4_OTS_CTL_TSSTP (*((volatile unsigned int*)(0x4294800CUL))) +#define bM4_OTS_LPR_TSOFS0 (*((volatile unsigned int*)(0x42948100UL))) +#define bM4_OTS_LPR_TSOFS1 (*((volatile unsigned int*)(0x42948104UL))) +#define bM4_OTS_LPR_TSOFS2 (*((volatile unsigned int*)(0x42948108UL))) +#define bM4_OTS_LPR_TSOFS3 (*((volatile unsigned int*)(0x4294810CUL))) +#define bM4_OTS_LPR_TSOFS4 (*((volatile unsigned int*)(0x42948110UL))) +#define bM4_OTS_LPR_TSOFS5 (*((volatile unsigned int*)(0x42948114UL))) +#define bM4_OTS_LPR_TSOFS6 (*((volatile unsigned int*)(0x42948118UL))) +#define bM4_OTS_LPR_TSOFS7 (*((volatile unsigned int*)(0x4294811CUL))) +#define bM4_OTS_LPR_TSSLP0 (*((volatile unsigned int*)(0x42948120UL))) +#define bM4_OTS_LPR_TSSLP1 (*((volatile unsigned int*)(0x42948124UL))) +#define bM4_OTS_LPR_TSSLP2 (*((volatile unsigned int*)(0x42948128UL))) +#define bM4_OTS_LPR_TSSLP3 (*((volatile unsigned int*)(0x4294812CUL))) +#define bM4_OTS_LPR_TSSLP4 (*((volatile unsigned int*)(0x42948130UL))) +#define bM4_OTS_LPR_TSSLP5 (*((volatile unsigned int*)(0x42948134UL))) +#define bM4_OTS_LPR_TSSLP6 (*((volatile unsigned int*)(0x42948138UL))) +#define bM4_OTS_LPR_TSSLP7 (*((volatile unsigned int*)(0x4294813CUL))) +#define bM4_OTS_LPR_TSSLP8 (*((volatile unsigned int*)(0x42948140UL))) +#define bM4_OTS_LPR_TSSLP9 (*((volatile unsigned int*)(0x42948144UL))) +#define bM4_OTS_LPR_TSSLP10 (*((volatile unsigned int*)(0x42948148UL))) +#define bM4_OTS_LPR_TSSLP11 (*((volatile unsigned int*)(0x4294814CUL))) +#define bM4_OTS_LPR_TSSLP12 (*((volatile unsigned int*)(0x42948150UL))) +#define bM4_OTS_LPR_TSSLP13 (*((volatile unsigned int*)(0x42948154UL))) +#define bM4_OTS_LPR_TSSLP14 (*((volatile unsigned int*)(0x42948158UL))) +#define bM4_OTS_LPR_TSSLP15 (*((volatile unsigned int*)(0x4294815CUL))) +#define bM4_OTS_LPR_TSSLP16 (*((volatile unsigned int*)(0x42948160UL))) +#define bM4_OTS_LPR_TSSLP17 (*((volatile unsigned int*)(0x42948164UL))) +#define bM4_OTS_LPR_TSSLP18 (*((volatile unsigned int*)(0x42948168UL))) +#define bM4_OTS_LPR_TSSLP19 (*((volatile unsigned int*)(0x4294816CUL))) +#define bM4_OTS_LPR_TSSLP20 (*((volatile unsigned int*)(0x42948170UL))) +#define bM4_OTS_LPR_TSSLP21 (*((volatile unsigned int*)(0x42948174UL))) +#define bM4_OTS_LPR_TSSLP22 (*((volatile unsigned int*)(0x42948178UL))) +#define bM4_OTS_LPR_TSSLP23 (*((volatile unsigned int*)(0x4294817CUL))) +#define bM4_PERIC_USBFS_SYCTLREG_DFB (*((volatile unsigned int*)(0x42AA8000UL))) +#define bM4_PERIC_USBFS_SYCTLREG_SOFEN (*((volatile unsigned int*)(0x42AA8004UL))) +#define bM4_PERIC_SDIOC_SYCTLREG_SELMMC1 (*((volatile unsigned int*)(0x42AA8084UL))) +#define bM4_PERIC_SDIOC_SYCTLREG_SELMMC2 (*((volatile unsigned int*)(0x42AA808CUL))) +#define bM4_PORT_PIDRA_PIN00 (*((volatile unsigned int*)(0x42A70000UL))) +#define bM4_PORT_PIDRA_PIN01 (*((volatile unsigned int*)(0x42A70004UL))) +#define bM4_PORT_PIDRA_PIN02 (*((volatile unsigned int*)(0x42A70008UL))) +#define bM4_PORT_PIDRA_PIN03 (*((volatile unsigned int*)(0x42A7000CUL))) +#define bM4_PORT_PIDRA_PIN04 (*((volatile unsigned int*)(0x42A70010UL))) +#define bM4_PORT_PIDRA_PIN05 (*((volatile unsigned int*)(0x42A70014UL))) +#define bM4_PORT_PIDRA_PIN06 (*((volatile unsigned int*)(0x42A70018UL))) +#define bM4_PORT_PIDRA_PIN07 (*((volatile unsigned int*)(0x42A7001CUL))) +#define bM4_PORT_PIDRA_PIN08 (*((volatile unsigned int*)(0x42A70020UL))) +#define bM4_PORT_PIDRA_PIN09 (*((volatile unsigned int*)(0x42A70024UL))) +#define bM4_PORT_PIDRA_PIN10 (*((volatile unsigned int*)(0x42A70028UL))) +#define bM4_PORT_PIDRA_PIN11 (*((volatile unsigned int*)(0x42A7002CUL))) +#define bM4_PORT_PIDRA_PIN12 (*((volatile unsigned int*)(0x42A70030UL))) +#define bM4_PORT_PIDRA_PIN13 (*((volatile unsigned int*)(0x42A70034UL))) +#define bM4_PORT_PIDRA_PIN14 (*((volatile unsigned int*)(0x42A70038UL))) +#define bM4_PORT_PIDRA_PIN15 (*((volatile unsigned int*)(0x42A7003CUL))) +#define bM4_PORT_PODRA_POUT00 (*((volatile unsigned int*)(0x42A70080UL))) +#define bM4_PORT_PODRA_POUT01 (*((volatile unsigned int*)(0x42A70084UL))) +#define bM4_PORT_PODRA_POUT02 (*((volatile unsigned int*)(0x42A70088UL))) +#define bM4_PORT_PODRA_POUT03 (*((volatile unsigned int*)(0x42A7008CUL))) +#define bM4_PORT_PODRA_POUT04 (*((volatile unsigned int*)(0x42A70090UL))) +#define bM4_PORT_PODRA_POUT05 (*((volatile unsigned int*)(0x42A70094UL))) +#define bM4_PORT_PODRA_POUT06 (*((volatile unsigned int*)(0x42A70098UL))) +#define bM4_PORT_PODRA_POUT07 (*((volatile unsigned int*)(0x42A7009CUL))) +#define bM4_PORT_PODRA_POUT08 (*((volatile unsigned int*)(0x42A700A0UL))) +#define bM4_PORT_PODRA_POUT09 (*((volatile unsigned int*)(0x42A700A4UL))) +#define bM4_PORT_PODRA_POUT10 (*((volatile unsigned int*)(0x42A700A8UL))) +#define bM4_PORT_PODRA_POUT11 (*((volatile unsigned int*)(0x42A700ACUL))) +#define bM4_PORT_PODRA_POUT12 (*((volatile unsigned int*)(0x42A700B0UL))) +#define bM4_PORT_PODRA_POUT13 (*((volatile unsigned int*)(0x42A700B4UL))) +#define bM4_PORT_PODRA_POUT14 (*((volatile unsigned int*)(0x42A700B8UL))) +#define bM4_PORT_PODRA_POUT15 (*((volatile unsigned int*)(0x42A700BCUL))) +#define bM4_PORT_POERA_POUTE00 (*((volatile unsigned int*)(0x42A700C0UL))) +#define bM4_PORT_POERA_POUTE01 (*((volatile unsigned int*)(0x42A700C4UL))) +#define bM4_PORT_POERA_POUTE02 (*((volatile unsigned int*)(0x42A700C8UL))) +#define bM4_PORT_POERA_POUTE03 (*((volatile unsigned int*)(0x42A700CCUL))) +#define bM4_PORT_POERA_POUTE04 (*((volatile unsigned int*)(0x42A700D0UL))) +#define bM4_PORT_POERA_POUTE05 (*((volatile unsigned int*)(0x42A700D4UL))) +#define bM4_PORT_POERA_POUTE06 (*((volatile unsigned int*)(0x42A700D8UL))) +#define bM4_PORT_POERA_POUTE07 (*((volatile unsigned int*)(0x42A700DCUL))) +#define bM4_PORT_POERA_POUTE08 (*((volatile unsigned int*)(0x42A700E0UL))) +#define bM4_PORT_POERA_POUTE09 (*((volatile unsigned int*)(0x42A700E4UL))) +#define bM4_PORT_POERA_POUTE10 (*((volatile unsigned int*)(0x42A700E8UL))) +#define bM4_PORT_POERA_POUTE11 (*((volatile unsigned int*)(0x42A700ECUL))) +#define bM4_PORT_POERA_POUTE12 (*((volatile unsigned int*)(0x42A700F0UL))) +#define bM4_PORT_POERA_POUTE13 (*((volatile unsigned int*)(0x42A700F4UL))) +#define bM4_PORT_POERA_POUTE14 (*((volatile unsigned int*)(0x42A700F8UL))) +#define bM4_PORT_POERA_POUTE15 (*((volatile unsigned int*)(0x42A700FCUL))) +#define bM4_PORT_POSRA_POS00 (*((volatile unsigned int*)(0x42A70100UL))) +#define bM4_PORT_POSRA_POS01 (*((volatile unsigned int*)(0x42A70104UL))) +#define bM4_PORT_POSRA_POS02 (*((volatile unsigned int*)(0x42A70108UL))) +#define bM4_PORT_POSRA_POS03 (*((volatile unsigned int*)(0x42A7010CUL))) +#define bM4_PORT_POSRA_POS04 (*((volatile unsigned int*)(0x42A70110UL))) +#define bM4_PORT_POSRA_POS05 (*((volatile unsigned int*)(0x42A70114UL))) +#define bM4_PORT_POSRA_POS06 (*((volatile unsigned int*)(0x42A70118UL))) +#define bM4_PORT_POSRA_POS07 (*((volatile unsigned int*)(0x42A7011CUL))) +#define bM4_PORT_POSRA_POS08 (*((volatile unsigned int*)(0x42A70120UL))) +#define bM4_PORT_POSRA_POS09 (*((volatile unsigned int*)(0x42A70124UL))) +#define bM4_PORT_POSRA_POS10 (*((volatile unsigned int*)(0x42A70128UL))) +#define bM4_PORT_POSRA_POS11 (*((volatile unsigned int*)(0x42A7012CUL))) +#define bM4_PORT_POSRA_POS12 (*((volatile unsigned int*)(0x42A70130UL))) +#define bM4_PORT_POSRA_POS13 (*((volatile unsigned int*)(0x42A70134UL))) +#define bM4_PORT_POSRA_POS14 (*((volatile unsigned int*)(0x42A70138UL))) +#define bM4_PORT_POSRA_POS15 (*((volatile unsigned int*)(0x42A7013CUL))) +#define bM4_PORT_PORRA_POR00 (*((volatile unsigned int*)(0x42A70140UL))) +#define bM4_PORT_PORRA_POR01 (*((volatile unsigned int*)(0x42A70144UL))) +#define bM4_PORT_PORRA_POR02 (*((volatile unsigned int*)(0x42A70148UL))) +#define bM4_PORT_PORRA_POR03 (*((volatile unsigned int*)(0x42A7014CUL))) +#define bM4_PORT_PORRA_POR04 (*((volatile unsigned int*)(0x42A70150UL))) +#define bM4_PORT_PORRA_POR05 (*((volatile unsigned int*)(0x42A70154UL))) +#define bM4_PORT_PORRA_POR06 (*((volatile unsigned int*)(0x42A70158UL))) +#define bM4_PORT_PORRA_POR07 (*((volatile unsigned int*)(0x42A7015CUL))) +#define bM4_PORT_PORRA_POR08 (*((volatile unsigned int*)(0x42A70160UL))) +#define bM4_PORT_PORRA_POR09 (*((volatile unsigned int*)(0x42A70164UL))) +#define bM4_PORT_PORRA_POR10 (*((volatile unsigned int*)(0x42A70168UL))) +#define bM4_PORT_PORRA_POR11 (*((volatile unsigned int*)(0x42A7016CUL))) +#define bM4_PORT_PORRA_POR12 (*((volatile unsigned int*)(0x42A70170UL))) +#define bM4_PORT_PORRA_POR13 (*((volatile unsigned int*)(0x42A70174UL))) +#define bM4_PORT_PORRA_POR14 (*((volatile unsigned int*)(0x42A70178UL))) +#define bM4_PORT_PORRA_POR15 (*((volatile unsigned int*)(0x42A7017CUL))) +#define bM4_PORT_POTRA_POT00 (*((volatile unsigned int*)(0x42A70180UL))) +#define bM4_PORT_POTRA_POT01 (*((volatile unsigned int*)(0x42A70184UL))) +#define bM4_PORT_POTRA_POT02 (*((volatile unsigned int*)(0x42A70188UL))) +#define bM4_PORT_POTRA_POT03 (*((volatile unsigned int*)(0x42A7018CUL))) +#define bM4_PORT_POTRA_POT04 (*((volatile unsigned int*)(0x42A70190UL))) +#define bM4_PORT_POTRA_POT05 (*((volatile unsigned int*)(0x42A70194UL))) +#define bM4_PORT_POTRA_POT06 (*((volatile unsigned int*)(0x42A70198UL))) +#define bM4_PORT_POTRA_POT07 (*((volatile unsigned int*)(0x42A7019CUL))) +#define bM4_PORT_POTRA_POT08 (*((volatile unsigned int*)(0x42A701A0UL))) +#define bM4_PORT_POTRA_POT09 (*((volatile unsigned int*)(0x42A701A4UL))) +#define bM4_PORT_POTRA_POT10 (*((volatile unsigned int*)(0x42A701A8UL))) +#define bM4_PORT_POTRA_POT11 (*((volatile unsigned int*)(0x42A701ACUL))) +#define bM4_PORT_POTRA_POT12 (*((volatile unsigned int*)(0x42A701B0UL))) +#define bM4_PORT_POTRA_POT13 (*((volatile unsigned int*)(0x42A701B4UL))) +#define bM4_PORT_POTRA_POT14 (*((volatile unsigned int*)(0x42A701B8UL))) +#define bM4_PORT_POTRA_POT15 (*((volatile unsigned int*)(0x42A701BCUL))) +#define bM4_PORT_PIDRB_PIN00 (*((volatile unsigned int*)(0x42A70200UL))) +#define bM4_PORT_PIDRB_PIN01 (*((volatile unsigned int*)(0x42A70204UL))) +#define bM4_PORT_PIDRB_PIN02 (*((volatile unsigned int*)(0x42A70208UL))) +#define bM4_PORT_PIDRB_PIN03 (*((volatile unsigned int*)(0x42A7020CUL))) +#define bM4_PORT_PIDRB_PIN04 (*((volatile unsigned int*)(0x42A70210UL))) +#define bM4_PORT_PIDRB_PIN05 (*((volatile unsigned int*)(0x42A70214UL))) +#define bM4_PORT_PIDRB_PIN06 (*((volatile unsigned int*)(0x42A70218UL))) +#define bM4_PORT_PIDRB_PIN07 (*((volatile unsigned int*)(0x42A7021CUL))) +#define bM4_PORT_PIDRB_PIN08 (*((volatile unsigned int*)(0x42A70220UL))) +#define bM4_PORT_PIDRB_PIN09 (*((volatile unsigned int*)(0x42A70224UL))) +#define bM4_PORT_PIDRB_PIN10 (*((volatile unsigned int*)(0x42A70228UL))) +#define bM4_PORT_PIDRB_PIN11 (*((volatile unsigned int*)(0x42A7022CUL))) +#define bM4_PORT_PIDRB_PIN12 (*((volatile unsigned int*)(0x42A70230UL))) +#define bM4_PORT_PIDRB_PIN13 (*((volatile unsigned int*)(0x42A70234UL))) +#define bM4_PORT_PIDRB_PIN14 (*((volatile unsigned int*)(0x42A70238UL))) +#define bM4_PORT_PIDRB_PIN15 (*((volatile unsigned int*)(0x42A7023CUL))) +#define bM4_PORT_PODRB_POUT00 (*((volatile unsigned int*)(0x42A70280UL))) +#define bM4_PORT_PODRB_POUT01 (*((volatile unsigned int*)(0x42A70284UL))) +#define bM4_PORT_PODRB_POUT02 (*((volatile unsigned int*)(0x42A70288UL))) +#define bM4_PORT_PODRB_POUT03 (*((volatile unsigned int*)(0x42A7028CUL))) +#define bM4_PORT_PODRB_POUT04 (*((volatile unsigned int*)(0x42A70290UL))) +#define bM4_PORT_PODRB_POUT05 (*((volatile unsigned int*)(0x42A70294UL))) +#define bM4_PORT_PODRB_POUT06 (*((volatile unsigned int*)(0x42A70298UL))) +#define bM4_PORT_PODRB_POUT07 (*((volatile unsigned int*)(0x42A7029CUL))) +#define bM4_PORT_PODRB_POUT08 (*((volatile unsigned int*)(0x42A702A0UL))) +#define bM4_PORT_PODRB_POUT09 (*((volatile unsigned int*)(0x42A702A4UL))) +#define bM4_PORT_PODRB_POUT10 (*((volatile unsigned int*)(0x42A702A8UL))) +#define bM4_PORT_PODRB_POUT11 (*((volatile unsigned int*)(0x42A702ACUL))) +#define bM4_PORT_PODRB_POUT12 (*((volatile unsigned int*)(0x42A702B0UL))) +#define bM4_PORT_PODRB_POUT13 (*((volatile unsigned int*)(0x42A702B4UL))) +#define bM4_PORT_PODRB_POUT14 (*((volatile unsigned int*)(0x42A702B8UL))) +#define bM4_PORT_PODRB_POUT15 (*((volatile unsigned int*)(0x42A702BCUL))) +#define bM4_PORT_POERB_POUTE00 (*((volatile unsigned int*)(0x42A702C0UL))) +#define bM4_PORT_POERB_POUTE01 (*((volatile unsigned int*)(0x42A702C4UL))) +#define bM4_PORT_POERB_POUTE02 (*((volatile unsigned int*)(0x42A702C8UL))) +#define bM4_PORT_POERB_POUTE03 (*((volatile unsigned int*)(0x42A702CCUL))) +#define bM4_PORT_POERB_POUTE04 (*((volatile unsigned int*)(0x42A702D0UL))) +#define bM4_PORT_POERB_POUTE05 (*((volatile unsigned int*)(0x42A702D4UL))) +#define bM4_PORT_POERB_POUTE06 (*((volatile unsigned int*)(0x42A702D8UL))) +#define bM4_PORT_POERB_POUTE07 (*((volatile unsigned int*)(0x42A702DCUL))) +#define bM4_PORT_POERB_POUTE08 (*((volatile unsigned int*)(0x42A702E0UL))) +#define bM4_PORT_POERB_POUTE09 (*((volatile unsigned int*)(0x42A702E4UL))) +#define bM4_PORT_POERB_POUTE10 (*((volatile unsigned int*)(0x42A702E8UL))) +#define bM4_PORT_POERB_POUTE11 (*((volatile unsigned int*)(0x42A702ECUL))) +#define bM4_PORT_POERB_POUTE12 (*((volatile unsigned int*)(0x42A702F0UL))) +#define bM4_PORT_POERB_POUTE13 (*((volatile unsigned int*)(0x42A702F4UL))) +#define bM4_PORT_POERB_POUTE14 (*((volatile unsigned int*)(0x42A702F8UL))) +#define bM4_PORT_POERB_POUTE15 (*((volatile unsigned int*)(0x42A702FCUL))) +#define bM4_PORT_POSRB_POS00 (*((volatile unsigned int*)(0x42A70300UL))) +#define bM4_PORT_POSRB_POS01 (*((volatile unsigned int*)(0x42A70304UL))) +#define bM4_PORT_POSRB_POS02 (*((volatile unsigned int*)(0x42A70308UL))) +#define bM4_PORT_POSRB_POS03 (*((volatile unsigned int*)(0x42A7030CUL))) +#define bM4_PORT_POSRB_POS04 (*((volatile unsigned int*)(0x42A70310UL))) +#define bM4_PORT_POSRB_POS05 (*((volatile unsigned int*)(0x42A70314UL))) +#define bM4_PORT_POSRB_POS06 (*((volatile unsigned int*)(0x42A70318UL))) +#define bM4_PORT_POSRB_POS07 (*((volatile unsigned int*)(0x42A7031CUL))) +#define bM4_PORT_POSRB_POS08 (*((volatile unsigned int*)(0x42A70320UL))) +#define bM4_PORT_POSRB_POS09 (*((volatile unsigned int*)(0x42A70324UL))) +#define bM4_PORT_POSRB_POS10 (*((volatile unsigned int*)(0x42A70328UL))) +#define bM4_PORT_POSRB_POS11 (*((volatile unsigned int*)(0x42A7032CUL))) +#define bM4_PORT_POSRB_POS12 (*((volatile unsigned int*)(0x42A70330UL))) +#define bM4_PORT_POSRB_POS13 (*((volatile unsigned int*)(0x42A70334UL))) +#define bM4_PORT_POSRB_POS14 (*((volatile unsigned int*)(0x42A70338UL))) +#define bM4_PORT_POSRB_POS15 (*((volatile unsigned int*)(0x42A7033CUL))) +#define bM4_PORT_PORRB_POR00 (*((volatile unsigned int*)(0x42A70340UL))) +#define bM4_PORT_PORRB_POR01 (*((volatile unsigned int*)(0x42A70344UL))) +#define bM4_PORT_PORRB_POR02 (*((volatile unsigned int*)(0x42A70348UL))) +#define bM4_PORT_PORRB_POR03 (*((volatile unsigned int*)(0x42A7034CUL))) +#define bM4_PORT_PORRB_POR04 (*((volatile unsigned int*)(0x42A70350UL))) +#define bM4_PORT_PORRB_POR05 (*((volatile unsigned int*)(0x42A70354UL))) +#define bM4_PORT_PORRB_POR06 (*((volatile unsigned int*)(0x42A70358UL))) +#define bM4_PORT_PORRB_POR07 (*((volatile unsigned int*)(0x42A7035CUL))) +#define bM4_PORT_PORRB_POR08 (*((volatile unsigned int*)(0x42A70360UL))) +#define bM4_PORT_PORRB_POR09 (*((volatile unsigned int*)(0x42A70364UL))) +#define bM4_PORT_PORRB_POR10 (*((volatile unsigned int*)(0x42A70368UL))) +#define bM4_PORT_PORRB_POR11 (*((volatile unsigned int*)(0x42A7036CUL))) +#define bM4_PORT_PORRB_POR12 (*((volatile unsigned int*)(0x42A70370UL))) +#define bM4_PORT_PORRB_POR13 (*((volatile unsigned int*)(0x42A70374UL))) +#define bM4_PORT_PORRB_POR14 (*((volatile unsigned int*)(0x42A70378UL))) +#define bM4_PORT_PORRB_POR15 (*((volatile unsigned int*)(0x42A7037CUL))) +#define bM4_PORT_POTRB_POT00 (*((volatile unsigned int*)(0x42A70380UL))) +#define bM4_PORT_POTRB_POT01 (*((volatile unsigned int*)(0x42A70384UL))) +#define bM4_PORT_POTRB_POT02 (*((volatile unsigned int*)(0x42A70388UL))) +#define bM4_PORT_POTRB_POT03 (*((volatile unsigned int*)(0x42A7038CUL))) +#define bM4_PORT_POTRB_POT04 (*((volatile unsigned int*)(0x42A70390UL))) +#define bM4_PORT_POTRB_POT05 (*((volatile unsigned int*)(0x42A70394UL))) +#define bM4_PORT_POTRB_POT06 (*((volatile unsigned int*)(0x42A70398UL))) +#define bM4_PORT_POTRB_POT07 (*((volatile unsigned int*)(0x42A7039CUL))) +#define bM4_PORT_POTRB_POT08 (*((volatile unsigned int*)(0x42A703A0UL))) +#define bM4_PORT_POTRB_POT09 (*((volatile unsigned int*)(0x42A703A4UL))) +#define bM4_PORT_POTRB_POT10 (*((volatile unsigned int*)(0x42A703A8UL))) +#define bM4_PORT_POTRB_POT11 (*((volatile unsigned int*)(0x42A703ACUL))) +#define bM4_PORT_POTRB_POT12 (*((volatile unsigned int*)(0x42A703B0UL))) +#define bM4_PORT_POTRB_POT13 (*((volatile unsigned int*)(0x42A703B4UL))) +#define bM4_PORT_POTRB_POT14 (*((volatile unsigned int*)(0x42A703B8UL))) +#define bM4_PORT_POTRB_POT15 (*((volatile unsigned int*)(0x42A703BCUL))) +#define bM4_PORT_PIDRC_PIN00 (*((volatile unsigned int*)(0x42A70400UL))) +#define bM4_PORT_PIDRC_PIN01 (*((volatile unsigned int*)(0x42A70404UL))) +#define bM4_PORT_PIDRC_PIN02 (*((volatile unsigned int*)(0x42A70408UL))) +#define bM4_PORT_PIDRC_PIN03 (*((volatile unsigned int*)(0x42A7040CUL))) +#define bM4_PORT_PIDRC_PIN04 (*((volatile unsigned int*)(0x42A70410UL))) +#define bM4_PORT_PIDRC_PIN05 (*((volatile unsigned int*)(0x42A70414UL))) +#define bM4_PORT_PIDRC_PIN06 (*((volatile unsigned int*)(0x42A70418UL))) +#define bM4_PORT_PIDRC_PIN07 (*((volatile unsigned int*)(0x42A7041CUL))) +#define bM4_PORT_PIDRC_PIN08 (*((volatile unsigned int*)(0x42A70420UL))) +#define bM4_PORT_PIDRC_PIN09 (*((volatile unsigned int*)(0x42A70424UL))) +#define bM4_PORT_PIDRC_PIN10 (*((volatile unsigned int*)(0x42A70428UL))) +#define bM4_PORT_PIDRC_PIN11 (*((volatile unsigned int*)(0x42A7042CUL))) +#define bM4_PORT_PIDRC_PIN12 (*((volatile unsigned int*)(0x42A70430UL))) +#define bM4_PORT_PIDRC_PIN13 (*((volatile unsigned int*)(0x42A70434UL))) +#define bM4_PORT_PIDRC_PIN14 (*((volatile unsigned int*)(0x42A70438UL))) +#define bM4_PORT_PIDRC_PIN15 (*((volatile unsigned int*)(0x42A7043CUL))) +#define bM4_PORT_PODRC_POUT00 (*((volatile unsigned int*)(0x42A70480UL))) +#define bM4_PORT_PODRC_POUT01 (*((volatile unsigned int*)(0x42A70484UL))) +#define bM4_PORT_PODRC_POUT02 (*((volatile unsigned int*)(0x42A70488UL))) +#define bM4_PORT_PODRC_POUT03 (*((volatile unsigned int*)(0x42A7048CUL))) +#define bM4_PORT_PODRC_POUT04 (*((volatile unsigned int*)(0x42A70490UL))) +#define bM4_PORT_PODRC_POUT05 (*((volatile unsigned int*)(0x42A70494UL))) +#define bM4_PORT_PODRC_POUT06 (*((volatile unsigned int*)(0x42A70498UL))) +#define bM4_PORT_PODRC_POUT07 (*((volatile unsigned int*)(0x42A7049CUL))) +#define bM4_PORT_PODRC_POUT08 (*((volatile unsigned int*)(0x42A704A0UL))) +#define bM4_PORT_PODRC_POUT09 (*((volatile unsigned int*)(0x42A704A4UL))) +#define bM4_PORT_PODRC_POUT10 (*((volatile unsigned int*)(0x42A704A8UL))) +#define bM4_PORT_PODRC_POUT11 (*((volatile unsigned int*)(0x42A704ACUL))) +#define bM4_PORT_PODRC_POUT12 (*((volatile unsigned int*)(0x42A704B0UL))) +#define bM4_PORT_PODRC_POUT13 (*((volatile unsigned int*)(0x42A704B4UL))) +#define bM4_PORT_PODRC_POUT14 (*((volatile unsigned int*)(0x42A704B8UL))) +#define bM4_PORT_PODRC_POUT15 (*((volatile unsigned int*)(0x42A704BCUL))) +#define bM4_PORT_POERC_POUTE00 (*((volatile unsigned int*)(0x42A704C0UL))) +#define bM4_PORT_POERC_POUTE01 (*((volatile unsigned int*)(0x42A704C4UL))) +#define bM4_PORT_POERC_POUTE02 (*((volatile unsigned int*)(0x42A704C8UL))) +#define bM4_PORT_POERC_POUTE03 (*((volatile unsigned int*)(0x42A704CCUL))) +#define bM4_PORT_POERC_POUTE04 (*((volatile unsigned int*)(0x42A704D0UL))) +#define bM4_PORT_POERC_POUTE05 (*((volatile unsigned int*)(0x42A704D4UL))) +#define bM4_PORT_POERC_POUTE06 (*((volatile unsigned int*)(0x42A704D8UL))) +#define bM4_PORT_POERC_POUTE07 (*((volatile unsigned int*)(0x42A704DCUL))) +#define bM4_PORT_POERC_POUTE08 (*((volatile unsigned int*)(0x42A704E0UL))) +#define bM4_PORT_POERC_POUTE09 (*((volatile unsigned int*)(0x42A704E4UL))) +#define bM4_PORT_POERC_POUTE10 (*((volatile unsigned int*)(0x42A704E8UL))) +#define bM4_PORT_POERC_POUTE11 (*((volatile unsigned int*)(0x42A704ECUL))) +#define bM4_PORT_POERC_POUTE12 (*((volatile unsigned int*)(0x42A704F0UL))) +#define bM4_PORT_POERC_POUTE13 (*((volatile unsigned int*)(0x42A704F4UL))) +#define bM4_PORT_POERC_POUTE14 (*((volatile unsigned int*)(0x42A704F8UL))) +#define bM4_PORT_POERC_POUTE15 (*((volatile unsigned int*)(0x42A704FCUL))) +#define bM4_PORT_POSRC_POS00 (*((volatile unsigned int*)(0x42A70500UL))) +#define bM4_PORT_POSRC_POS01 (*((volatile unsigned int*)(0x42A70504UL))) +#define bM4_PORT_POSRC_POS02 (*((volatile unsigned int*)(0x42A70508UL))) +#define bM4_PORT_POSRC_POS03 (*((volatile unsigned int*)(0x42A7050CUL))) +#define bM4_PORT_POSRC_POS04 (*((volatile unsigned int*)(0x42A70510UL))) +#define bM4_PORT_POSRC_POS05 (*((volatile unsigned int*)(0x42A70514UL))) +#define bM4_PORT_POSRC_POS06 (*((volatile unsigned int*)(0x42A70518UL))) +#define bM4_PORT_POSRC_POS07 (*((volatile unsigned int*)(0x42A7051CUL))) +#define bM4_PORT_POSRC_POS08 (*((volatile unsigned int*)(0x42A70520UL))) +#define bM4_PORT_POSRC_POS09 (*((volatile unsigned int*)(0x42A70524UL))) +#define bM4_PORT_POSRC_POS10 (*((volatile unsigned int*)(0x42A70528UL))) +#define bM4_PORT_POSRC_POS11 (*((volatile unsigned int*)(0x42A7052CUL))) +#define bM4_PORT_POSRC_POS12 (*((volatile unsigned int*)(0x42A70530UL))) +#define bM4_PORT_POSRC_POS13 (*((volatile unsigned int*)(0x42A70534UL))) +#define bM4_PORT_POSRC_POS14 (*((volatile unsigned int*)(0x42A70538UL))) +#define bM4_PORT_POSRC_POS15 (*((volatile unsigned int*)(0x42A7053CUL))) +#define bM4_PORT_PORRC_POR00 (*((volatile unsigned int*)(0x42A70540UL))) +#define bM4_PORT_PORRC_POR01 (*((volatile unsigned int*)(0x42A70544UL))) +#define bM4_PORT_PORRC_POR02 (*((volatile unsigned int*)(0x42A70548UL))) +#define bM4_PORT_PORRC_POR03 (*((volatile unsigned int*)(0x42A7054CUL))) +#define bM4_PORT_PORRC_POR04 (*((volatile unsigned int*)(0x42A70550UL))) +#define bM4_PORT_PORRC_POR05 (*((volatile unsigned int*)(0x42A70554UL))) +#define bM4_PORT_PORRC_POR06 (*((volatile unsigned int*)(0x42A70558UL))) +#define bM4_PORT_PORRC_POR07 (*((volatile unsigned int*)(0x42A7055CUL))) +#define bM4_PORT_PORRC_POR08 (*((volatile unsigned int*)(0x42A70560UL))) +#define bM4_PORT_PORRC_POR09 (*((volatile unsigned int*)(0x42A70564UL))) +#define bM4_PORT_PORRC_POR10 (*((volatile unsigned int*)(0x42A70568UL))) +#define bM4_PORT_PORRC_POR11 (*((volatile unsigned int*)(0x42A7056CUL))) +#define bM4_PORT_PORRC_POR12 (*((volatile unsigned int*)(0x42A70570UL))) +#define bM4_PORT_PORRC_POR13 (*((volatile unsigned int*)(0x42A70574UL))) +#define bM4_PORT_PORRC_POR14 (*((volatile unsigned int*)(0x42A70578UL))) +#define bM4_PORT_PORRC_POR15 (*((volatile unsigned int*)(0x42A7057CUL))) +#define bM4_PORT_POTRC_POT00 (*((volatile unsigned int*)(0x42A70580UL))) +#define bM4_PORT_POTRC_POT01 (*((volatile unsigned int*)(0x42A70584UL))) +#define bM4_PORT_POTRC_POT02 (*((volatile unsigned int*)(0x42A70588UL))) +#define bM4_PORT_POTRC_POT03 (*((volatile unsigned int*)(0x42A7058CUL))) +#define bM4_PORT_POTRC_POT04 (*((volatile unsigned int*)(0x42A70590UL))) +#define bM4_PORT_POTRC_POT05 (*((volatile unsigned int*)(0x42A70594UL))) +#define bM4_PORT_POTRC_POT06 (*((volatile unsigned int*)(0x42A70598UL))) +#define bM4_PORT_POTRC_POT07 (*((volatile unsigned int*)(0x42A7059CUL))) +#define bM4_PORT_POTRC_POT08 (*((volatile unsigned int*)(0x42A705A0UL))) +#define bM4_PORT_POTRC_POT09 (*((volatile unsigned int*)(0x42A705A4UL))) +#define bM4_PORT_POTRC_POT10 (*((volatile unsigned int*)(0x42A705A8UL))) +#define bM4_PORT_POTRC_POT11 (*((volatile unsigned int*)(0x42A705ACUL))) +#define bM4_PORT_POTRC_POT12 (*((volatile unsigned int*)(0x42A705B0UL))) +#define bM4_PORT_POTRC_POT13 (*((volatile unsigned int*)(0x42A705B4UL))) +#define bM4_PORT_POTRC_POT14 (*((volatile unsigned int*)(0x42A705B8UL))) +#define bM4_PORT_POTRC_POT15 (*((volatile unsigned int*)(0x42A705BCUL))) +#define bM4_PORT_PIDRD_PIN00 (*((volatile unsigned int*)(0x42A70600UL))) +#define bM4_PORT_PIDRD_PIN01 (*((volatile unsigned int*)(0x42A70604UL))) +#define bM4_PORT_PIDRD_PIN02 (*((volatile unsigned int*)(0x42A70608UL))) +#define bM4_PORT_PIDRD_PIN03 (*((volatile unsigned int*)(0x42A7060CUL))) +#define bM4_PORT_PIDRD_PIN04 (*((volatile unsigned int*)(0x42A70610UL))) +#define bM4_PORT_PIDRD_PIN05 (*((volatile unsigned int*)(0x42A70614UL))) +#define bM4_PORT_PIDRD_PIN06 (*((volatile unsigned int*)(0x42A70618UL))) +#define bM4_PORT_PIDRD_PIN07 (*((volatile unsigned int*)(0x42A7061CUL))) +#define bM4_PORT_PIDRD_PIN08 (*((volatile unsigned int*)(0x42A70620UL))) +#define bM4_PORT_PIDRD_PIN09 (*((volatile unsigned int*)(0x42A70624UL))) +#define bM4_PORT_PIDRD_PIN10 (*((volatile unsigned int*)(0x42A70628UL))) +#define bM4_PORT_PIDRD_PIN11 (*((volatile unsigned int*)(0x42A7062CUL))) +#define bM4_PORT_PIDRD_PIN12 (*((volatile unsigned int*)(0x42A70630UL))) +#define bM4_PORT_PIDRD_PIN13 (*((volatile unsigned int*)(0x42A70634UL))) +#define bM4_PORT_PIDRD_PIN14 (*((volatile unsigned int*)(0x42A70638UL))) +#define bM4_PORT_PIDRD_PIN15 (*((volatile unsigned int*)(0x42A7063CUL))) +#define bM4_PORT_PODRD_POUT00 (*((volatile unsigned int*)(0x42A70680UL))) +#define bM4_PORT_PODRD_POUT01 (*((volatile unsigned int*)(0x42A70684UL))) +#define bM4_PORT_PODRD_POUT02 (*((volatile unsigned int*)(0x42A70688UL))) +#define bM4_PORT_PODRD_POUT03 (*((volatile unsigned int*)(0x42A7068CUL))) +#define bM4_PORT_PODRD_POUT04 (*((volatile unsigned int*)(0x42A70690UL))) +#define bM4_PORT_PODRD_POUT05 (*((volatile unsigned int*)(0x42A70694UL))) +#define bM4_PORT_PODRD_POUT06 (*((volatile unsigned int*)(0x42A70698UL))) +#define bM4_PORT_PODRD_POUT07 (*((volatile unsigned int*)(0x42A7069CUL))) +#define bM4_PORT_PODRD_POUT08 (*((volatile unsigned int*)(0x42A706A0UL))) +#define bM4_PORT_PODRD_POUT09 (*((volatile unsigned int*)(0x42A706A4UL))) +#define bM4_PORT_PODRD_POUT10 (*((volatile unsigned int*)(0x42A706A8UL))) +#define bM4_PORT_PODRD_POUT11 (*((volatile unsigned int*)(0x42A706ACUL))) +#define bM4_PORT_PODRD_POUT12 (*((volatile unsigned int*)(0x42A706B0UL))) +#define bM4_PORT_PODRD_POUT13 (*((volatile unsigned int*)(0x42A706B4UL))) +#define bM4_PORT_PODRD_POUT14 (*((volatile unsigned int*)(0x42A706B8UL))) +#define bM4_PORT_PODRD_POUT15 (*((volatile unsigned int*)(0x42A706BCUL))) +#define bM4_PORT_POERD_POUTE00 (*((volatile unsigned int*)(0x42A706C0UL))) +#define bM4_PORT_POERD_POUTE01 (*((volatile unsigned int*)(0x42A706C4UL))) +#define bM4_PORT_POERD_POUTE02 (*((volatile unsigned int*)(0x42A706C8UL))) +#define bM4_PORT_POERD_POUTE03 (*((volatile unsigned int*)(0x42A706CCUL))) +#define bM4_PORT_POERD_POUTE04 (*((volatile unsigned int*)(0x42A706D0UL))) +#define bM4_PORT_POERD_POUTE05 (*((volatile unsigned int*)(0x42A706D4UL))) +#define bM4_PORT_POERD_POUTE06 (*((volatile unsigned int*)(0x42A706D8UL))) +#define bM4_PORT_POERD_POUTE07 (*((volatile unsigned int*)(0x42A706DCUL))) +#define bM4_PORT_POERD_POUTE08 (*((volatile unsigned int*)(0x42A706E0UL))) +#define bM4_PORT_POERD_POUTE09 (*((volatile unsigned int*)(0x42A706E4UL))) +#define bM4_PORT_POERD_POUTE10 (*((volatile unsigned int*)(0x42A706E8UL))) +#define bM4_PORT_POERD_POUTE11 (*((volatile unsigned int*)(0x42A706ECUL))) +#define bM4_PORT_POERD_POUTE12 (*((volatile unsigned int*)(0x42A706F0UL))) +#define bM4_PORT_POERD_POUTE13 (*((volatile unsigned int*)(0x42A706F4UL))) +#define bM4_PORT_POERD_POUTE14 (*((volatile unsigned int*)(0x42A706F8UL))) +#define bM4_PORT_POERD_POUTE15 (*((volatile unsigned int*)(0x42A706FCUL))) +#define bM4_PORT_POSRD_POS00 (*((volatile unsigned int*)(0x42A70700UL))) +#define bM4_PORT_POSRD_POS01 (*((volatile unsigned int*)(0x42A70704UL))) +#define bM4_PORT_POSRD_POS02 (*((volatile unsigned int*)(0x42A70708UL))) +#define bM4_PORT_POSRD_POS03 (*((volatile unsigned int*)(0x42A7070CUL))) +#define bM4_PORT_POSRD_POS04 (*((volatile unsigned int*)(0x42A70710UL))) +#define bM4_PORT_POSRD_POS05 (*((volatile unsigned int*)(0x42A70714UL))) +#define bM4_PORT_POSRD_POS06 (*((volatile unsigned int*)(0x42A70718UL))) +#define bM4_PORT_POSRD_POS07 (*((volatile unsigned int*)(0x42A7071CUL))) +#define bM4_PORT_POSRD_POS08 (*((volatile unsigned int*)(0x42A70720UL))) +#define bM4_PORT_POSRD_POS09 (*((volatile unsigned int*)(0x42A70724UL))) +#define bM4_PORT_POSRD_POS10 (*((volatile unsigned int*)(0x42A70728UL))) +#define bM4_PORT_POSRD_POS11 (*((volatile unsigned int*)(0x42A7072CUL))) +#define bM4_PORT_POSRD_POS12 (*((volatile unsigned int*)(0x42A70730UL))) +#define bM4_PORT_POSRD_POS13 (*((volatile unsigned int*)(0x42A70734UL))) +#define bM4_PORT_POSRD_POS14 (*((volatile unsigned int*)(0x42A70738UL))) +#define bM4_PORT_POSRD_POS15 (*((volatile unsigned int*)(0x42A7073CUL))) +#define bM4_PORT_PORRD_POR00 (*((volatile unsigned int*)(0x42A70740UL))) +#define bM4_PORT_PORRD_POR01 (*((volatile unsigned int*)(0x42A70744UL))) +#define bM4_PORT_PORRD_POR02 (*((volatile unsigned int*)(0x42A70748UL))) +#define bM4_PORT_PORRD_POR03 (*((volatile unsigned int*)(0x42A7074CUL))) +#define bM4_PORT_PORRD_POR04 (*((volatile unsigned int*)(0x42A70750UL))) +#define bM4_PORT_PORRD_POR05 (*((volatile unsigned int*)(0x42A70754UL))) +#define bM4_PORT_PORRD_POR06 (*((volatile unsigned int*)(0x42A70758UL))) +#define bM4_PORT_PORRD_POR07 (*((volatile unsigned int*)(0x42A7075CUL))) +#define bM4_PORT_PORRD_POR08 (*((volatile unsigned int*)(0x42A70760UL))) +#define bM4_PORT_PORRD_POR09 (*((volatile unsigned int*)(0x42A70764UL))) +#define bM4_PORT_PORRD_POR10 (*((volatile unsigned int*)(0x42A70768UL))) +#define bM4_PORT_PORRD_POR11 (*((volatile unsigned int*)(0x42A7076CUL))) +#define bM4_PORT_PORRD_POR12 (*((volatile unsigned int*)(0x42A70770UL))) +#define bM4_PORT_PORRD_POR13 (*((volatile unsigned int*)(0x42A70774UL))) +#define bM4_PORT_PORRD_POR14 (*((volatile unsigned int*)(0x42A70778UL))) +#define bM4_PORT_PORRD_POR15 (*((volatile unsigned int*)(0x42A7077CUL))) +#define bM4_PORT_POTRD_POT00 (*((volatile unsigned int*)(0x42A70780UL))) +#define bM4_PORT_POTRD_POT01 (*((volatile unsigned int*)(0x42A70784UL))) +#define bM4_PORT_POTRD_POT02 (*((volatile unsigned int*)(0x42A70788UL))) +#define bM4_PORT_POTRD_POT03 (*((volatile unsigned int*)(0x42A7078CUL))) +#define bM4_PORT_POTRD_POT04 (*((volatile unsigned int*)(0x42A70790UL))) +#define bM4_PORT_POTRD_POT05 (*((volatile unsigned int*)(0x42A70794UL))) +#define bM4_PORT_POTRD_POT06 (*((volatile unsigned int*)(0x42A70798UL))) +#define bM4_PORT_POTRD_POT07 (*((volatile unsigned int*)(0x42A7079CUL))) +#define bM4_PORT_POTRD_POT08 (*((volatile unsigned int*)(0x42A707A0UL))) +#define bM4_PORT_POTRD_POT09 (*((volatile unsigned int*)(0x42A707A4UL))) +#define bM4_PORT_POTRD_POT10 (*((volatile unsigned int*)(0x42A707A8UL))) +#define bM4_PORT_POTRD_POT11 (*((volatile unsigned int*)(0x42A707ACUL))) +#define bM4_PORT_POTRD_POT12 (*((volatile unsigned int*)(0x42A707B0UL))) +#define bM4_PORT_POTRD_POT13 (*((volatile unsigned int*)(0x42A707B4UL))) +#define bM4_PORT_POTRD_POT14 (*((volatile unsigned int*)(0x42A707B8UL))) +#define bM4_PORT_POTRD_POT15 (*((volatile unsigned int*)(0x42A707BCUL))) +#define bM4_PORT_PIDRE_PIN00 (*((volatile unsigned int*)(0x42A70800UL))) +#define bM4_PORT_PIDRE_PIN01 (*((volatile unsigned int*)(0x42A70804UL))) +#define bM4_PORT_PIDRE_PIN02 (*((volatile unsigned int*)(0x42A70808UL))) +#define bM4_PORT_PIDRE_PIN03 (*((volatile unsigned int*)(0x42A7080CUL))) +#define bM4_PORT_PIDRE_PIN04 (*((volatile unsigned int*)(0x42A70810UL))) +#define bM4_PORT_PIDRE_PIN05 (*((volatile unsigned int*)(0x42A70814UL))) +#define bM4_PORT_PIDRE_PIN06 (*((volatile unsigned int*)(0x42A70818UL))) +#define bM4_PORT_PIDRE_PIN07 (*((volatile unsigned int*)(0x42A7081CUL))) +#define bM4_PORT_PIDRE_PIN08 (*((volatile unsigned int*)(0x42A70820UL))) +#define bM4_PORT_PIDRE_PIN09 (*((volatile unsigned int*)(0x42A70824UL))) +#define bM4_PORT_PIDRE_PIN10 (*((volatile unsigned int*)(0x42A70828UL))) +#define bM4_PORT_PIDRE_PIN11 (*((volatile unsigned int*)(0x42A7082CUL))) +#define bM4_PORT_PIDRE_PIN12 (*((volatile unsigned int*)(0x42A70830UL))) +#define bM4_PORT_PIDRE_PIN13 (*((volatile unsigned int*)(0x42A70834UL))) +#define bM4_PORT_PIDRE_PIN14 (*((volatile unsigned int*)(0x42A70838UL))) +#define bM4_PORT_PIDRE_PIN15 (*((volatile unsigned int*)(0x42A7083CUL))) +#define bM4_PORT_PODRE_POUT00 (*((volatile unsigned int*)(0x42A70880UL))) +#define bM4_PORT_PODRE_POUT01 (*((volatile unsigned int*)(0x42A70884UL))) +#define bM4_PORT_PODRE_POUT02 (*((volatile unsigned int*)(0x42A70888UL))) +#define bM4_PORT_PODRE_POUT03 (*((volatile unsigned int*)(0x42A7088CUL))) +#define bM4_PORT_PODRE_POUT04 (*((volatile unsigned int*)(0x42A70890UL))) +#define bM4_PORT_PODRE_POUT05 (*((volatile unsigned int*)(0x42A70894UL))) +#define bM4_PORT_PODRE_POUT06 (*((volatile unsigned int*)(0x42A70898UL))) +#define bM4_PORT_PODRE_POUT07 (*((volatile unsigned int*)(0x42A7089CUL))) +#define bM4_PORT_PODRE_POUT08 (*((volatile unsigned int*)(0x42A708A0UL))) +#define bM4_PORT_PODRE_POUT09 (*((volatile unsigned int*)(0x42A708A4UL))) +#define bM4_PORT_PODRE_POUT10 (*((volatile unsigned int*)(0x42A708A8UL))) +#define bM4_PORT_PODRE_POUT11 (*((volatile unsigned int*)(0x42A708ACUL))) +#define bM4_PORT_PODRE_POUT12 (*((volatile unsigned int*)(0x42A708B0UL))) +#define bM4_PORT_PODRE_POUT13 (*((volatile unsigned int*)(0x42A708B4UL))) +#define bM4_PORT_PODRE_POUT14 (*((volatile unsigned int*)(0x42A708B8UL))) +#define bM4_PORT_PODRE_POUT15 (*((volatile unsigned int*)(0x42A708BCUL))) +#define bM4_PORT_POERE_POUTE00 (*((volatile unsigned int*)(0x42A708C0UL))) +#define bM4_PORT_POERE_POUTE01 (*((volatile unsigned int*)(0x42A708C4UL))) +#define bM4_PORT_POERE_POUTE02 (*((volatile unsigned int*)(0x42A708C8UL))) +#define bM4_PORT_POERE_POUTE03 (*((volatile unsigned int*)(0x42A708CCUL))) +#define bM4_PORT_POERE_POUTE04 (*((volatile unsigned int*)(0x42A708D0UL))) +#define bM4_PORT_POERE_POUTE05 (*((volatile unsigned int*)(0x42A708D4UL))) +#define bM4_PORT_POERE_POUTE06 (*((volatile unsigned int*)(0x42A708D8UL))) +#define bM4_PORT_POERE_POUTE07 (*((volatile unsigned int*)(0x42A708DCUL))) +#define bM4_PORT_POERE_POUTE08 (*((volatile unsigned int*)(0x42A708E0UL))) +#define bM4_PORT_POERE_POUTE09 (*((volatile unsigned int*)(0x42A708E4UL))) +#define bM4_PORT_POERE_POUTE10 (*((volatile unsigned int*)(0x42A708E8UL))) +#define bM4_PORT_POERE_POUTE11 (*((volatile unsigned int*)(0x42A708ECUL))) +#define bM4_PORT_POERE_POUTE12 (*((volatile unsigned int*)(0x42A708F0UL))) +#define bM4_PORT_POERE_POUTE13 (*((volatile unsigned int*)(0x42A708F4UL))) +#define bM4_PORT_POERE_POUTE14 (*((volatile unsigned int*)(0x42A708F8UL))) +#define bM4_PORT_POERE_POUTE15 (*((volatile unsigned int*)(0x42A708FCUL))) +#define bM4_PORT_POSRE_POS00 (*((volatile unsigned int*)(0x42A70900UL))) +#define bM4_PORT_POSRE_POS01 (*((volatile unsigned int*)(0x42A70904UL))) +#define bM4_PORT_POSRE_POS02 (*((volatile unsigned int*)(0x42A70908UL))) +#define bM4_PORT_POSRE_POS03 (*((volatile unsigned int*)(0x42A7090CUL))) +#define bM4_PORT_POSRE_POS04 (*((volatile unsigned int*)(0x42A70910UL))) +#define bM4_PORT_POSRE_POS05 (*((volatile unsigned int*)(0x42A70914UL))) +#define bM4_PORT_POSRE_POS06 (*((volatile unsigned int*)(0x42A70918UL))) +#define bM4_PORT_POSRE_POS07 (*((volatile unsigned int*)(0x42A7091CUL))) +#define bM4_PORT_POSRE_POS08 (*((volatile unsigned int*)(0x42A70920UL))) +#define bM4_PORT_POSRE_POS09 (*((volatile unsigned int*)(0x42A70924UL))) +#define bM4_PORT_POSRE_POS10 (*((volatile unsigned int*)(0x42A70928UL))) +#define bM4_PORT_POSRE_POS11 (*((volatile unsigned int*)(0x42A7092CUL))) +#define bM4_PORT_POSRE_POS12 (*((volatile unsigned int*)(0x42A70930UL))) +#define bM4_PORT_POSRE_POS13 (*((volatile unsigned int*)(0x42A70934UL))) +#define bM4_PORT_POSRE_POS14 (*((volatile unsigned int*)(0x42A70938UL))) +#define bM4_PORT_POSRE_POS15 (*((volatile unsigned int*)(0x42A7093CUL))) +#define bM4_PORT_PORRE_POR00 (*((volatile unsigned int*)(0x42A70940UL))) +#define bM4_PORT_PORRE_POR01 (*((volatile unsigned int*)(0x42A70944UL))) +#define bM4_PORT_PORRE_POR02 (*((volatile unsigned int*)(0x42A70948UL))) +#define bM4_PORT_PORRE_POR03 (*((volatile unsigned int*)(0x42A7094CUL))) +#define bM4_PORT_PORRE_POR04 (*((volatile unsigned int*)(0x42A70950UL))) +#define bM4_PORT_PORRE_POR05 (*((volatile unsigned int*)(0x42A70954UL))) +#define bM4_PORT_PORRE_POR06 (*((volatile unsigned int*)(0x42A70958UL))) +#define bM4_PORT_PORRE_POR07 (*((volatile unsigned int*)(0x42A7095CUL))) +#define bM4_PORT_PORRE_POR08 (*((volatile unsigned int*)(0x42A70960UL))) +#define bM4_PORT_PORRE_POR09 (*((volatile unsigned int*)(0x42A70964UL))) +#define bM4_PORT_PORRE_POR10 (*((volatile unsigned int*)(0x42A70968UL))) +#define bM4_PORT_PORRE_POR11 (*((volatile unsigned int*)(0x42A7096CUL))) +#define bM4_PORT_PORRE_POR12 (*((volatile unsigned int*)(0x42A70970UL))) +#define bM4_PORT_PORRE_POR13 (*((volatile unsigned int*)(0x42A70974UL))) +#define bM4_PORT_PORRE_POR14 (*((volatile unsigned int*)(0x42A70978UL))) +#define bM4_PORT_PORRE_POR15 (*((volatile unsigned int*)(0x42A7097CUL))) +#define bM4_PORT_POTRE_POT00 (*((volatile unsigned int*)(0x42A70980UL))) +#define bM4_PORT_POTRE_POT01 (*((volatile unsigned int*)(0x42A70984UL))) +#define bM4_PORT_POTRE_POT02 (*((volatile unsigned int*)(0x42A70988UL))) +#define bM4_PORT_POTRE_POT03 (*((volatile unsigned int*)(0x42A7098CUL))) +#define bM4_PORT_POTRE_POT04 (*((volatile unsigned int*)(0x42A70990UL))) +#define bM4_PORT_POTRE_POT05 (*((volatile unsigned int*)(0x42A70994UL))) +#define bM4_PORT_POTRE_POT06 (*((volatile unsigned int*)(0x42A70998UL))) +#define bM4_PORT_POTRE_POT07 (*((volatile unsigned int*)(0x42A7099CUL))) +#define bM4_PORT_POTRE_POT08 (*((volatile unsigned int*)(0x42A709A0UL))) +#define bM4_PORT_POTRE_POT09 (*((volatile unsigned int*)(0x42A709A4UL))) +#define bM4_PORT_POTRE_POT10 (*((volatile unsigned int*)(0x42A709A8UL))) +#define bM4_PORT_POTRE_POT11 (*((volatile unsigned int*)(0x42A709ACUL))) +#define bM4_PORT_POTRE_POT12 (*((volatile unsigned int*)(0x42A709B0UL))) +#define bM4_PORT_POTRE_POT13 (*((volatile unsigned int*)(0x42A709B4UL))) +#define bM4_PORT_POTRE_POT14 (*((volatile unsigned int*)(0x42A709B8UL))) +#define bM4_PORT_POTRE_POT15 (*((volatile unsigned int*)(0x42A709BCUL))) +#define bM4_PORT_PIDRH_PIN00 (*((volatile unsigned int*)(0x42A70A00UL))) +#define bM4_PORT_PIDRH_PIN01 (*((volatile unsigned int*)(0x42A70A04UL))) +#define bM4_PORT_PIDRH_PIN02 (*((volatile unsigned int*)(0x42A70A08UL))) +#define bM4_PORT_PODRH_POUT00 (*((volatile unsigned int*)(0x42A70A80UL))) +#define bM4_PORT_PODRH_POUT01 (*((volatile unsigned int*)(0x42A70A84UL))) +#define bM4_PORT_PODRH_POUT02 (*((volatile unsigned int*)(0x42A70A88UL))) +#define bM4_PORT_POERH_POUTE00 (*((volatile unsigned int*)(0x42A70AC0UL))) +#define bM4_PORT_POERH_POUTE01 (*((volatile unsigned int*)(0x42A70AC4UL))) +#define bM4_PORT_POERH_POUTE02 (*((volatile unsigned int*)(0x42A70AC8UL))) +#define bM4_PORT_POSRH_POS00 (*((volatile unsigned int*)(0x42A70B00UL))) +#define bM4_PORT_POSRH_POS01 (*((volatile unsigned int*)(0x42A70B04UL))) +#define bM4_PORT_POSRH_POS02 (*((volatile unsigned int*)(0x42A70B08UL))) +#define bM4_PORT_PORRH_POR00 (*((volatile unsigned int*)(0x42A70B40UL))) +#define bM4_PORT_PORRH_POR01 (*((volatile unsigned int*)(0x42A70B44UL))) +#define bM4_PORT_PORRH_POR02 (*((volatile unsigned int*)(0x42A70B48UL))) +#define bM4_PORT_POTRH_POT00 (*((volatile unsigned int*)(0x42A70B80UL))) +#define bM4_PORT_POTRH_POT01 (*((volatile unsigned int*)(0x42A70B84UL))) +#define bM4_PORT_POTRH_POT02 (*((volatile unsigned int*)(0x42A70B88UL))) +#define bM4_PORT_PSPCR_SPFE0 (*((volatile unsigned int*)(0x42A77E80UL))) +#define bM4_PORT_PSPCR_SPFE1 (*((volatile unsigned int*)(0x42A77E84UL))) +#define bM4_PORT_PSPCR_SPFE2 (*((volatile unsigned int*)(0x42A77E88UL))) +#define bM4_PORT_PSPCR_SPFE3 (*((volatile unsigned int*)(0x42A77E8CUL))) +#define bM4_PORT_PSPCR_SPFE4 (*((volatile unsigned int*)(0x42A77E90UL))) +#define bM4_PORT_PCCR_BFSEL0 (*((volatile unsigned int*)(0x42A77F00UL))) +#define bM4_PORT_PCCR_BFSEL1 (*((volatile unsigned int*)(0x42A77F04UL))) +#define bM4_PORT_PCCR_BFSEL2 (*((volatile unsigned int*)(0x42A77F08UL))) +#define bM4_PORT_PCCR_BFSEL3 (*((volatile unsigned int*)(0x42A77F0CUL))) +#define bM4_PORT_PCCR_RDWT0 (*((volatile unsigned int*)(0x42A77F38UL))) +#define bM4_PORT_PCCR_RDWT1 (*((volatile unsigned int*)(0x42A77F3CUL))) +#define bM4_PORT_PINAER_PINAE0 (*((volatile unsigned int*)(0x42A77F40UL))) +#define bM4_PORT_PINAER_PINAE1 (*((volatile unsigned int*)(0x42A77F44UL))) +#define bM4_PORT_PINAER_PINAE2 (*((volatile unsigned int*)(0x42A77F48UL))) +#define bM4_PORT_PINAER_PINAE3 (*((volatile unsigned int*)(0x42A77F4CUL))) +#define bM4_PORT_PINAER_PINAE4 (*((volatile unsigned int*)(0x42A77F50UL))) +#define bM4_PORT_PINAER_PINAE5 (*((volatile unsigned int*)(0x42A77F54UL))) +#define bM4_PORT_PWPR_WE (*((volatile unsigned int*)(0x42A77F80UL))) +#define bM4_PORT_PWPR_WP0 (*((volatile unsigned int*)(0x42A77FA0UL))) +#define bM4_PORT_PWPR_WP1 (*((volatile unsigned int*)(0x42A77FA4UL))) +#define bM4_PORT_PWPR_WP2 (*((volatile unsigned int*)(0x42A77FA8UL))) +#define bM4_PORT_PWPR_WP3 (*((volatile unsigned int*)(0x42A77FACUL))) +#define bM4_PORT_PWPR_WP4 (*((volatile unsigned int*)(0x42A77FB0UL))) +#define bM4_PORT_PWPR_WP5 (*((volatile unsigned int*)(0x42A77FB4UL))) +#define bM4_PORT_PWPR_WP6 (*((volatile unsigned int*)(0x42A77FB8UL))) +#define bM4_PORT_PWPR_WP7 (*((volatile unsigned int*)(0x42A77FBCUL))) +#define bM4_PORT_PCRA0_POUT (*((volatile unsigned int*)(0x42A78000UL))) +#define bM4_PORT_PCRA0_POUTE (*((volatile unsigned int*)(0x42A78004UL))) +#define bM4_PORT_PCRA0_NOD (*((volatile unsigned int*)(0x42A78008UL))) +#define bM4_PORT_PCRA0_DRV0 (*((volatile unsigned int*)(0x42A78010UL))) +#define bM4_PORT_PCRA0_DRV1 (*((volatile unsigned int*)(0x42A78014UL))) +#define bM4_PORT_PCRA0_PUU (*((volatile unsigned int*)(0x42A78018UL))) +#define bM4_PORT_PCRA0_PIN (*((volatile unsigned int*)(0x42A78020UL))) +#define bM4_PORT_PCRA0_INVE (*((volatile unsigned int*)(0x42A78024UL))) +#define bM4_PORT_PCRA0_INTE (*((volatile unsigned int*)(0x42A78030UL))) +#define bM4_PORT_PCRA0_LTE (*((volatile unsigned int*)(0x42A78038UL))) +#define bM4_PORT_PCRA0_DDIS (*((volatile unsigned int*)(0x42A7803CUL))) +#define bM4_PORT_PFSRA0_FSEL0 (*((volatile unsigned int*)(0x42A78040UL))) +#define bM4_PORT_PFSRA0_FSEL1 (*((volatile unsigned int*)(0x42A78044UL))) +#define bM4_PORT_PFSRA0_FSEL2 (*((volatile unsigned int*)(0x42A78048UL))) +#define bM4_PORT_PFSRA0_FSEL3 (*((volatile unsigned int*)(0x42A7804CUL))) +#define bM4_PORT_PFSRA0_FSEL4 (*((volatile unsigned int*)(0x42A78050UL))) +#define bM4_PORT_PFSRA0_FSEL5 (*((volatile unsigned int*)(0x42A78054UL))) +#define bM4_PORT_PFSRA0_BFE (*((volatile unsigned int*)(0x42A78060UL))) +#define bM4_PORT_PCRA1_POUT (*((volatile unsigned int*)(0x42A78080UL))) +#define bM4_PORT_PCRA1_POUTE (*((volatile unsigned int*)(0x42A78084UL))) +#define bM4_PORT_PCRA1_NOD (*((volatile unsigned int*)(0x42A78088UL))) +#define bM4_PORT_PCRA1_DRV0 (*((volatile unsigned int*)(0x42A78090UL))) +#define bM4_PORT_PCRA1_DRV1 (*((volatile unsigned int*)(0x42A78094UL))) +#define bM4_PORT_PCRA1_PUU (*((volatile unsigned int*)(0x42A78098UL))) +#define bM4_PORT_PCRA1_PIN (*((volatile unsigned int*)(0x42A780A0UL))) +#define bM4_PORT_PCRA1_INVE (*((volatile unsigned int*)(0x42A780A4UL))) +#define bM4_PORT_PCRA1_INTE (*((volatile unsigned int*)(0x42A780B0UL))) +#define bM4_PORT_PCRA1_LTE (*((volatile unsigned int*)(0x42A780B8UL))) +#define bM4_PORT_PCRA1_DDIS (*((volatile unsigned int*)(0x42A780BCUL))) +#define bM4_PORT_PFSRA1_FSEL0 (*((volatile unsigned int*)(0x42A780C0UL))) +#define bM4_PORT_PFSRA1_FSEL1 (*((volatile unsigned int*)(0x42A780C4UL))) +#define bM4_PORT_PFSRA1_FSEL2 (*((volatile unsigned int*)(0x42A780C8UL))) +#define bM4_PORT_PFSRA1_FSEL3 (*((volatile unsigned int*)(0x42A780CCUL))) +#define bM4_PORT_PFSRA1_FSEL4 (*((volatile unsigned int*)(0x42A780D0UL))) +#define bM4_PORT_PFSRA1_FSEL5 (*((volatile unsigned int*)(0x42A780D4UL))) +#define bM4_PORT_PFSRA1_BFE (*((volatile unsigned int*)(0x42A780E0UL))) +#define bM4_PORT_PCRA2_POUT (*((volatile unsigned int*)(0x42A78100UL))) +#define bM4_PORT_PCRA2_POUTE (*((volatile unsigned int*)(0x42A78104UL))) +#define bM4_PORT_PCRA2_NOD (*((volatile unsigned int*)(0x42A78108UL))) +#define bM4_PORT_PCRA2_DRV0 (*((volatile unsigned int*)(0x42A78110UL))) +#define bM4_PORT_PCRA2_DRV1 (*((volatile unsigned int*)(0x42A78114UL))) +#define bM4_PORT_PCRA2_PUU (*((volatile unsigned int*)(0x42A78118UL))) +#define bM4_PORT_PCRA2_PIN (*((volatile unsigned int*)(0x42A78120UL))) +#define bM4_PORT_PCRA2_INVE (*((volatile unsigned int*)(0x42A78124UL))) +#define bM4_PORT_PCRA2_INTE (*((volatile unsigned int*)(0x42A78130UL))) +#define bM4_PORT_PCRA2_LTE (*((volatile unsigned int*)(0x42A78138UL))) +#define bM4_PORT_PCRA2_DDIS (*((volatile unsigned int*)(0x42A7813CUL))) +#define bM4_PORT_PFSRA2_FSEL0 (*((volatile unsigned int*)(0x42A78140UL))) +#define bM4_PORT_PFSRA2_FSEL1 (*((volatile unsigned int*)(0x42A78144UL))) +#define bM4_PORT_PFSRA2_FSEL2 (*((volatile unsigned int*)(0x42A78148UL))) +#define bM4_PORT_PFSRA2_FSEL3 (*((volatile unsigned int*)(0x42A7814CUL))) +#define bM4_PORT_PFSRA2_FSEL4 (*((volatile unsigned int*)(0x42A78150UL))) +#define bM4_PORT_PFSRA2_FSEL5 (*((volatile unsigned int*)(0x42A78154UL))) +#define bM4_PORT_PFSRA2_BFE (*((volatile unsigned int*)(0x42A78160UL))) +#define bM4_PORT_PCRA3_POUT (*((volatile unsigned int*)(0x42A78180UL))) +#define bM4_PORT_PCRA3_POUTE (*((volatile unsigned int*)(0x42A78184UL))) +#define bM4_PORT_PCRA3_NOD (*((volatile unsigned int*)(0x42A78188UL))) +#define bM4_PORT_PCRA3_DRV0 (*((volatile unsigned int*)(0x42A78190UL))) +#define bM4_PORT_PCRA3_DRV1 (*((volatile unsigned int*)(0x42A78194UL))) +#define bM4_PORT_PCRA3_PUU (*((volatile unsigned int*)(0x42A78198UL))) +#define bM4_PORT_PCRA3_PIN (*((volatile unsigned int*)(0x42A781A0UL))) +#define bM4_PORT_PCRA3_INVE (*((volatile unsigned int*)(0x42A781A4UL))) +#define bM4_PORT_PCRA3_INTE (*((volatile unsigned int*)(0x42A781B0UL))) +#define bM4_PORT_PCRA3_LTE (*((volatile unsigned int*)(0x42A781B8UL))) +#define bM4_PORT_PCRA3_DDIS (*((volatile unsigned int*)(0x42A781BCUL))) +#define bM4_PORT_PFSRA3_FSEL0 (*((volatile unsigned int*)(0x42A781C0UL))) +#define bM4_PORT_PFSRA3_FSEL1 (*((volatile unsigned int*)(0x42A781C4UL))) +#define bM4_PORT_PFSRA3_FSEL2 (*((volatile unsigned int*)(0x42A781C8UL))) +#define bM4_PORT_PFSRA3_FSEL3 (*((volatile unsigned int*)(0x42A781CCUL))) +#define bM4_PORT_PFSRA3_FSEL4 (*((volatile unsigned int*)(0x42A781D0UL))) +#define bM4_PORT_PFSRA3_FSEL5 (*((volatile unsigned int*)(0x42A781D4UL))) +#define bM4_PORT_PFSRA3_BFE (*((volatile unsigned int*)(0x42A781E0UL))) +#define bM4_PORT_PCRA4_POUT (*((volatile unsigned int*)(0x42A78200UL))) +#define bM4_PORT_PCRA4_POUTE (*((volatile unsigned int*)(0x42A78204UL))) +#define bM4_PORT_PCRA4_NOD (*((volatile unsigned int*)(0x42A78208UL))) +#define bM4_PORT_PCRA4_DRV0 (*((volatile unsigned int*)(0x42A78210UL))) +#define bM4_PORT_PCRA4_DRV1 (*((volatile unsigned int*)(0x42A78214UL))) +#define bM4_PORT_PCRA4_PUU (*((volatile unsigned int*)(0x42A78218UL))) +#define bM4_PORT_PCRA4_PIN (*((volatile unsigned int*)(0x42A78220UL))) +#define bM4_PORT_PCRA4_INVE (*((volatile unsigned int*)(0x42A78224UL))) +#define bM4_PORT_PCRA4_INTE (*((volatile unsigned int*)(0x42A78230UL))) +#define bM4_PORT_PCRA4_LTE (*((volatile unsigned int*)(0x42A78238UL))) +#define bM4_PORT_PCRA4_DDIS (*((volatile unsigned int*)(0x42A7823CUL))) +#define bM4_PORT_PFSRA4_FSEL0 (*((volatile unsigned int*)(0x42A78240UL))) +#define bM4_PORT_PFSRA4_FSEL1 (*((volatile unsigned int*)(0x42A78244UL))) +#define bM4_PORT_PFSRA4_FSEL2 (*((volatile unsigned int*)(0x42A78248UL))) +#define bM4_PORT_PFSRA4_FSEL3 (*((volatile unsigned int*)(0x42A7824CUL))) +#define bM4_PORT_PFSRA4_FSEL4 (*((volatile unsigned int*)(0x42A78250UL))) +#define bM4_PORT_PFSRA4_FSEL5 (*((volatile unsigned int*)(0x42A78254UL))) +#define bM4_PORT_PFSRA4_BFE (*((volatile unsigned int*)(0x42A78260UL))) +#define bM4_PORT_PCRA5_POUT (*((volatile unsigned int*)(0x42A78280UL))) +#define bM4_PORT_PCRA5_POUTE (*((volatile unsigned int*)(0x42A78284UL))) +#define bM4_PORT_PCRA5_NOD (*((volatile unsigned int*)(0x42A78288UL))) +#define bM4_PORT_PCRA5_DRV0 (*((volatile unsigned int*)(0x42A78290UL))) +#define bM4_PORT_PCRA5_DRV1 (*((volatile unsigned int*)(0x42A78294UL))) +#define bM4_PORT_PCRA5_PUU (*((volatile unsigned int*)(0x42A78298UL))) +#define bM4_PORT_PCRA5_PIN (*((volatile unsigned int*)(0x42A782A0UL))) +#define bM4_PORT_PCRA5_INVE (*((volatile unsigned int*)(0x42A782A4UL))) +#define bM4_PORT_PCRA5_INTE (*((volatile unsigned int*)(0x42A782B0UL))) +#define bM4_PORT_PCRA5_LTE (*((volatile unsigned int*)(0x42A782B8UL))) +#define bM4_PORT_PCRA5_DDIS (*((volatile unsigned int*)(0x42A782BCUL))) +#define bM4_PORT_PFSRA5_FSEL0 (*((volatile unsigned int*)(0x42A782C0UL))) +#define bM4_PORT_PFSRA5_FSEL1 (*((volatile unsigned int*)(0x42A782C4UL))) +#define bM4_PORT_PFSRA5_FSEL2 (*((volatile unsigned int*)(0x42A782C8UL))) +#define bM4_PORT_PFSRA5_FSEL3 (*((volatile unsigned int*)(0x42A782CCUL))) +#define bM4_PORT_PFSRA5_FSEL4 (*((volatile unsigned int*)(0x42A782D0UL))) +#define bM4_PORT_PFSRA5_FSEL5 (*((volatile unsigned int*)(0x42A782D4UL))) +#define bM4_PORT_PFSRA5_BFE (*((volatile unsigned int*)(0x42A782E0UL))) +#define bM4_PORT_PCRA6_POUT (*((volatile unsigned int*)(0x42A78300UL))) +#define bM4_PORT_PCRA6_POUTE (*((volatile unsigned int*)(0x42A78304UL))) +#define bM4_PORT_PCRA6_NOD (*((volatile unsigned int*)(0x42A78308UL))) +#define bM4_PORT_PCRA6_DRV0 (*((volatile unsigned int*)(0x42A78310UL))) +#define bM4_PORT_PCRA6_DRV1 (*((volatile unsigned int*)(0x42A78314UL))) +#define bM4_PORT_PCRA6_PUU (*((volatile unsigned int*)(0x42A78318UL))) +#define bM4_PORT_PCRA6_PIN (*((volatile unsigned int*)(0x42A78320UL))) +#define bM4_PORT_PCRA6_INVE (*((volatile unsigned int*)(0x42A78324UL))) +#define bM4_PORT_PCRA6_INTE (*((volatile unsigned int*)(0x42A78330UL))) +#define bM4_PORT_PCRA6_LTE (*((volatile unsigned int*)(0x42A78338UL))) +#define bM4_PORT_PCRA6_DDIS (*((volatile unsigned int*)(0x42A7833CUL))) +#define bM4_PORT_PFSRA6_FSEL0 (*((volatile unsigned int*)(0x42A78340UL))) +#define bM4_PORT_PFSRA6_FSEL1 (*((volatile unsigned int*)(0x42A78344UL))) +#define bM4_PORT_PFSRA6_FSEL2 (*((volatile unsigned int*)(0x42A78348UL))) +#define bM4_PORT_PFSRA6_FSEL3 (*((volatile unsigned int*)(0x42A7834CUL))) +#define bM4_PORT_PFSRA6_FSEL4 (*((volatile unsigned int*)(0x42A78350UL))) +#define bM4_PORT_PFSRA6_FSEL5 (*((volatile unsigned int*)(0x42A78354UL))) +#define bM4_PORT_PFSRA6_BFE (*((volatile unsigned int*)(0x42A78360UL))) +#define bM4_PORT_PCRA7_POUT (*((volatile unsigned int*)(0x42A78380UL))) +#define bM4_PORT_PCRA7_POUTE (*((volatile unsigned int*)(0x42A78384UL))) +#define bM4_PORT_PCRA7_NOD (*((volatile unsigned int*)(0x42A78388UL))) +#define bM4_PORT_PCRA7_DRV0 (*((volatile unsigned int*)(0x42A78390UL))) +#define bM4_PORT_PCRA7_DRV1 (*((volatile unsigned int*)(0x42A78394UL))) +#define bM4_PORT_PCRA7_PUU (*((volatile unsigned int*)(0x42A78398UL))) +#define bM4_PORT_PCRA7_PIN (*((volatile unsigned int*)(0x42A783A0UL))) +#define bM4_PORT_PCRA7_INVE (*((volatile unsigned int*)(0x42A783A4UL))) +#define bM4_PORT_PCRA7_INTE (*((volatile unsigned int*)(0x42A783B0UL))) +#define bM4_PORT_PCRA7_LTE (*((volatile unsigned int*)(0x42A783B8UL))) +#define bM4_PORT_PCRA7_DDIS (*((volatile unsigned int*)(0x42A783BCUL))) +#define bM4_PORT_PFSRA7_FSEL0 (*((volatile unsigned int*)(0x42A783C0UL))) +#define bM4_PORT_PFSRA7_FSEL1 (*((volatile unsigned int*)(0x42A783C4UL))) +#define bM4_PORT_PFSRA7_FSEL2 (*((volatile unsigned int*)(0x42A783C8UL))) +#define bM4_PORT_PFSRA7_FSEL3 (*((volatile unsigned int*)(0x42A783CCUL))) +#define bM4_PORT_PFSRA7_FSEL4 (*((volatile unsigned int*)(0x42A783D0UL))) +#define bM4_PORT_PFSRA7_FSEL5 (*((volatile unsigned int*)(0x42A783D4UL))) +#define bM4_PORT_PFSRA7_BFE (*((volatile unsigned int*)(0x42A783E0UL))) +#define bM4_PORT_PCRA8_POUT (*((volatile unsigned int*)(0x42A78400UL))) +#define bM4_PORT_PCRA8_POUTE (*((volatile unsigned int*)(0x42A78404UL))) +#define bM4_PORT_PCRA8_NOD (*((volatile unsigned int*)(0x42A78408UL))) +#define bM4_PORT_PCRA8_DRV0 (*((volatile unsigned int*)(0x42A78410UL))) +#define bM4_PORT_PCRA8_DRV1 (*((volatile unsigned int*)(0x42A78414UL))) +#define bM4_PORT_PCRA8_PUU (*((volatile unsigned int*)(0x42A78418UL))) +#define bM4_PORT_PCRA8_PIN (*((volatile unsigned int*)(0x42A78420UL))) +#define bM4_PORT_PCRA8_INVE (*((volatile unsigned int*)(0x42A78424UL))) +#define bM4_PORT_PCRA8_INTE (*((volatile unsigned int*)(0x42A78430UL))) +#define bM4_PORT_PCRA8_LTE (*((volatile unsigned int*)(0x42A78438UL))) +#define bM4_PORT_PCRA8_DDIS (*((volatile unsigned int*)(0x42A7843CUL))) +#define bM4_PORT_PFSRA8_FSEL0 (*((volatile unsigned int*)(0x42A78440UL))) +#define bM4_PORT_PFSRA8_FSEL1 (*((volatile unsigned int*)(0x42A78444UL))) +#define bM4_PORT_PFSRA8_FSEL2 (*((volatile unsigned int*)(0x42A78448UL))) +#define bM4_PORT_PFSRA8_FSEL3 (*((volatile unsigned int*)(0x42A7844CUL))) +#define bM4_PORT_PFSRA8_FSEL4 (*((volatile unsigned int*)(0x42A78450UL))) +#define bM4_PORT_PFSRA8_FSEL5 (*((volatile unsigned int*)(0x42A78454UL))) +#define bM4_PORT_PFSRA8_BFE (*((volatile unsigned int*)(0x42A78460UL))) +#define bM4_PORT_PCRA9_POUT (*((volatile unsigned int*)(0x42A78480UL))) +#define bM4_PORT_PCRA9_POUTE (*((volatile unsigned int*)(0x42A78484UL))) +#define bM4_PORT_PCRA9_NOD (*((volatile unsigned int*)(0x42A78488UL))) +#define bM4_PORT_PCRA9_DRV0 (*((volatile unsigned int*)(0x42A78490UL))) +#define bM4_PORT_PCRA9_DRV1 (*((volatile unsigned int*)(0x42A78494UL))) +#define bM4_PORT_PCRA9_PUU (*((volatile unsigned int*)(0x42A78498UL))) +#define bM4_PORT_PCRA9_PIN (*((volatile unsigned int*)(0x42A784A0UL))) +#define bM4_PORT_PCRA9_INVE (*((volatile unsigned int*)(0x42A784A4UL))) +#define bM4_PORT_PCRA9_INTE (*((volatile unsigned int*)(0x42A784B0UL))) +#define bM4_PORT_PCRA9_LTE (*((volatile unsigned int*)(0x42A784B8UL))) +#define bM4_PORT_PCRA9_DDIS (*((volatile unsigned int*)(0x42A784BCUL))) +#define bM4_PORT_PFSRA9_FSEL0 (*((volatile unsigned int*)(0x42A784C0UL))) +#define bM4_PORT_PFSRA9_FSEL1 (*((volatile unsigned int*)(0x42A784C4UL))) +#define bM4_PORT_PFSRA9_FSEL2 (*((volatile unsigned int*)(0x42A784C8UL))) +#define bM4_PORT_PFSRA9_FSEL3 (*((volatile unsigned int*)(0x42A784CCUL))) +#define bM4_PORT_PFSRA9_FSEL4 (*((volatile unsigned int*)(0x42A784D0UL))) +#define bM4_PORT_PFSRA9_FSEL5 (*((volatile unsigned int*)(0x42A784D4UL))) +#define bM4_PORT_PFSRA9_BFE (*((volatile unsigned int*)(0x42A784E0UL))) +#define bM4_PORT_PCRA10_POUT (*((volatile unsigned int*)(0x42A78500UL))) +#define bM4_PORT_PCRA10_POUTE (*((volatile unsigned int*)(0x42A78504UL))) +#define bM4_PORT_PCRA10_NOD (*((volatile unsigned int*)(0x42A78508UL))) +#define bM4_PORT_PCRA10_DRV0 (*((volatile unsigned int*)(0x42A78510UL))) +#define bM4_PORT_PCRA10_DRV1 (*((volatile unsigned int*)(0x42A78514UL))) +#define bM4_PORT_PCRA10_PUU (*((volatile unsigned int*)(0x42A78518UL))) +#define bM4_PORT_PCRA10_PIN (*((volatile unsigned int*)(0x42A78520UL))) +#define bM4_PORT_PCRA10_INVE (*((volatile unsigned int*)(0x42A78524UL))) +#define bM4_PORT_PCRA10_INTE (*((volatile unsigned int*)(0x42A78530UL))) +#define bM4_PORT_PCRA10_LTE (*((volatile unsigned int*)(0x42A78538UL))) +#define bM4_PORT_PCRA10_DDIS (*((volatile unsigned int*)(0x42A7853CUL))) +#define bM4_PORT_PFSRA10_FSEL0 (*((volatile unsigned int*)(0x42A78540UL))) +#define bM4_PORT_PFSRA10_FSEL1 (*((volatile unsigned int*)(0x42A78544UL))) +#define bM4_PORT_PFSRA10_FSEL2 (*((volatile unsigned int*)(0x42A78548UL))) +#define bM4_PORT_PFSRA10_FSEL3 (*((volatile unsigned int*)(0x42A7854CUL))) +#define bM4_PORT_PFSRA10_FSEL4 (*((volatile unsigned int*)(0x42A78550UL))) +#define bM4_PORT_PFSRA10_FSEL5 (*((volatile unsigned int*)(0x42A78554UL))) +#define bM4_PORT_PFSRA10_BFE (*((volatile unsigned int*)(0x42A78560UL))) +#define bM4_PORT_PCRA11_POUT (*((volatile unsigned int*)(0x42A78580UL))) +#define bM4_PORT_PCRA11_POUTE (*((volatile unsigned int*)(0x42A78584UL))) +#define bM4_PORT_PCRA11_NOD (*((volatile unsigned int*)(0x42A78588UL))) +#define bM4_PORT_PCRA11_DRV0 (*((volatile unsigned int*)(0x42A78590UL))) +#define bM4_PORT_PCRA11_DRV1 (*((volatile unsigned int*)(0x42A78594UL))) +#define bM4_PORT_PCRA11_PUU (*((volatile unsigned int*)(0x42A78598UL))) +#define bM4_PORT_PCRA11_PIN (*((volatile unsigned int*)(0x42A785A0UL))) +#define bM4_PORT_PCRA11_INVE (*((volatile unsigned int*)(0x42A785A4UL))) +#define bM4_PORT_PCRA11_INTE (*((volatile unsigned int*)(0x42A785B0UL))) +#define bM4_PORT_PCRA11_LTE (*((volatile unsigned int*)(0x42A785B8UL))) +#define bM4_PORT_PCRA11_DDIS (*((volatile unsigned int*)(0x42A785BCUL))) +#define bM4_PORT_PFSRA11_FSEL0 (*((volatile unsigned int*)(0x42A785C0UL))) +#define bM4_PORT_PFSRA11_FSEL1 (*((volatile unsigned int*)(0x42A785C4UL))) +#define bM4_PORT_PFSRA11_FSEL2 (*((volatile unsigned int*)(0x42A785C8UL))) +#define bM4_PORT_PFSRA11_FSEL3 (*((volatile unsigned int*)(0x42A785CCUL))) +#define bM4_PORT_PFSRA11_FSEL4 (*((volatile unsigned int*)(0x42A785D0UL))) +#define bM4_PORT_PFSRA11_FSEL5 (*((volatile unsigned int*)(0x42A785D4UL))) +#define bM4_PORT_PFSRA11_BFE (*((volatile unsigned int*)(0x42A785E0UL))) +#define bM4_PORT_PCRA12_POUT (*((volatile unsigned int*)(0x42A78600UL))) +#define bM4_PORT_PCRA12_POUTE (*((volatile unsigned int*)(0x42A78604UL))) +#define bM4_PORT_PCRA12_NOD (*((volatile unsigned int*)(0x42A78608UL))) +#define bM4_PORT_PCRA12_DRV0 (*((volatile unsigned int*)(0x42A78610UL))) +#define bM4_PORT_PCRA12_DRV1 (*((volatile unsigned int*)(0x42A78614UL))) +#define bM4_PORT_PCRA12_PUU (*((volatile unsigned int*)(0x42A78618UL))) +#define bM4_PORT_PCRA12_PIN (*((volatile unsigned int*)(0x42A78620UL))) +#define bM4_PORT_PCRA12_INVE (*((volatile unsigned int*)(0x42A78624UL))) +#define bM4_PORT_PCRA12_INTE (*((volatile unsigned int*)(0x42A78630UL))) +#define bM4_PORT_PCRA12_LTE (*((volatile unsigned int*)(0x42A78638UL))) +#define bM4_PORT_PCRA12_DDIS (*((volatile unsigned int*)(0x42A7863CUL))) +#define bM4_PORT_PFSRA12_FSEL0 (*((volatile unsigned int*)(0x42A78640UL))) +#define bM4_PORT_PFSRA12_FSEL1 (*((volatile unsigned int*)(0x42A78644UL))) +#define bM4_PORT_PFSRA12_FSEL2 (*((volatile unsigned int*)(0x42A78648UL))) +#define bM4_PORT_PFSRA12_FSEL3 (*((volatile unsigned int*)(0x42A7864CUL))) +#define bM4_PORT_PFSRA12_FSEL4 (*((volatile unsigned int*)(0x42A78650UL))) +#define bM4_PORT_PFSRA12_FSEL5 (*((volatile unsigned int*)(0x42A78654UL))) +#define bM4_PORT_PFSRA12_BFE (*((volatile unsigned int*)(0x42A78660UL))) +#define bM4_PORT_PCRA13_POUT (*((volatile unsigned int*)(0x42A78680UL))) +#define bM4_PORT_PCRA13_POUTE (*((volatile unsigned int*)(0x42A78684UL))) +#define bM4_PORT_PCRA13_NOD (*((volatile unsigned int*)(0x42A78688UL))) +#define bM4_PORT_PCRA13_DRV0 (*((volatile unsigned int*)(0x42A78690UL))) +#define bM4_PORT_PCRA13_DRV1 (*((volatile unsigned int*)(0x42A78694UL))) +#define bM4_PORT_PCRA13_PUU (*((volatile unsigned int*)(0x42A78698UL))) +#define bM4_PORT_PCRA13_PIN (*((volatile unsigned int*)(0x42A786A0UL))) +#define bM4_PORT_PCRA13_INVE (*((volatile unsigned int*)(0x42A786A4UL))) +#define bM4_PORT_PCRA13_INTE (*((volatile unsigned int*)(0x42A786B0UL))) +#define bM4_PORT_PCRA13_LTE (*((volatile unsigned int*)(0x42A786B8UL))) +#define bM4_PORT_PCRA13_DDIS (*((volatile unsigned int*)(0x42A786BCUL))) +#define bM4_PORT_PFSRA13_FSEL0 (*((volatile unsigned int*)(0x42A786C0UL))) +#define bM4_PORT_PFSRA13_FSEL1 (*((volatile unsigned int*)(0x42A786C4UL))) +#define bM4_PORT_PFSRA13_FSEL2 (*((volatile unsigned int*)(0x42A786C8UL))) +#define bM4_PORT_PFSRA13_FSEL3 (*((volatile unsigned int*)(0x42A786CCUL))) +#define bM4_PORT_PFSRA13_FSEL4 (*((volatile unsigned int*)(0x42A786D0UL))) +#define bM4_PORT_PFSRA13_FSEL5 (*((volatile unsigned int*)(0x42A786D4UL))) +#define bM4_PORT_PFSRA13_BFE (*((volatile unsigned int*)(0x42A786E0UL))) +#define bM4_PORT_PCRA14_POUT (*((volatile unsigned int*)(0x42A78700UL))) +#define bM4_PORT_PCRA14_POUTE (*((volatile unsigned int*)(0x42A78704UL))) +#define bM4_PORT_PCRA14_NOD (*((volatile unsigned int*)(0x42A78708UL))) +#define bM4_PORT_PCRA14_DRV0 (*((volatile unsigned int*)(0x42A78710UL))) +#define bM4_PORT_PCRA14_DRV1 (*((volatile unsigned int*)(0x42A78714UL))) +#define bM4_PORT_PCRA14_PUU (*((volatile unsigned int*)(0x42A78718UL))) +#define bM4_PORT_PCRA14_PIN (*((volatile unsigned int*)(0x42A78720UL))) +#define bM4_PORT_PCRA14_INVE (*((volatile unsigned int*)(0x42A78724UL))) +#define bM4_PORT_PCRA14_INTE (*((volatile unsigned int*)(0x42A78730UL))) +#define bM4_PORT_PCRA14_LTE (*((volatile unsigned int*)(0x42A78738UL))) +#define bM4_PORT_PCRA14_DDIS (*((volatile unsigned int*)(0x42A7873CUL))) +#define bM4_PORT_PFSRA14_FSEL0 (*((volatile unsigned int*)(0x42A78740UL))) +#define bM4_PORT_PFSRA14_FSEL1 (*((volatile unsigned int*)(0x42A78744UL))) +#define bM4_PORT_PFSRA14_FSEL2 (*((volatile unsigned int*)(0x42A78748UL))) +#define bM4_PORT_PFSRA14_FSEL3 (*((volatile unsigned int*)(0x42A7874CUL))) +#define bM4_PORT_PFSRA14_FSEL4 (*((volatile unsigned int*)(0x42A78750UL))) +#define bM4_PORT_PFSRA14_FSEL5 (*((volatile unsigned int*)(0x42A78754UL))) +#define bM4_PORT_PFSRA14_BFE (*((volatile unsigned int*)(0x42A78760UL))) +#define bM4_PORT_PCRA15_POUT (*((volatile unsigned int*)(0x42A78780UL))) +#define bM4_PORT_PCRA15_POUTE (*((volatile unsigned int*)(0x42A78784UL))) +#define bM4_PORT_PCRA15_NOD (*((volatile unsigned int*)(0x42A78788UL))) +#define bM4_PORT_PCRA15_DRV0 (*((volatile unsigned int*)(0x42A78790UL))) +#define bM4_PORT_PCRA15_DRV1 (*((volatile unsigned int*)(0x42A78794UL))) +#define bM4_PORT_PCRA15_PUU (*((volatile unsigned int*)(0x42A78798UL))) +#define bM4_PORT_PCRA15_PIN (*((volatile unsigned int*)(0x42A787A0UL))) +#define bM4_PORT_PCRA15_INVE (*((volatile unsigned int*)(0x42A787A4UL))) +#define bM4_PORT_PCRA15_INTE (*((volatile unsigned int*)(0x42A787B0UL))) +#define bM4_PORT_PCRA15_LTE (*((volatile unsigned int*)(0x42A787B8UL))) +#define bM4_PORT_PCRA15_DDIS (*((volatile unsigned int*)(0x42A787BCUL))) +#define bM4_PORT_PFSRA15_FSEL0 (*((volatile unsigned int*)(0x42A787C0UL))) +#define bM4_PORT_PFSRA15_FSEL1 (*((volatile unsigned int*)(0x42A787C4UL))) +#define bM4_PORT_PFSRA15_FSEL2 (*((volatile unsigned int*)(0x42A787C8UL))) +#define bM4_PORT_PFSRA15_FSEL3 (*((volatile unsigned int*)(0x42A787CCUL))) +#define bM4_PORT_PFSRA15_FSEL4 (*((volatile unsigned int*)(0x42A787D0UL))) +#define bM4_PORT_PFSRA15_FSEL5 (*((volatile unsigned int*)(0x42A787D4UL))) +#define bM4_PORT_PFSRA15_BFE (*((volatile unsigned int*)(0x42A787E0UL))) +#define bM4_PORT_PCRB0_POUT (*((volatile unsigned int*)(0x42A78800UL))) +#define bM4_PORT_PCRB0_POUTE (*((volatile unsigned int*)(0x42A78804UL))) +#define bM4_PORT_PCRB0_NOD (*((volatile unsigned int*)(0x42A78808UL))) +#define bM4_PORT_PCRB0_DRV0 (*((volatile unsigned int*)(0x42A78810UL))) +#define bM4_PORT_PCRB0_DRV1 (*((volatile unsigned int*)(0x42A78814UL))) +#define bM4_PORT_PCRB0_PUU (*((volatile unsigned int*)(0x42A78818UL))) +#define bM4_PORT_PCRB0_PIN (*((volatile unsigned int*)(0x42A78820UL))) +#define bM4_PORT_PCRB0_INVE (*((volatile unsigned int*)(0x42A78824UL))) +#define bM4_PORT_PCRB0_INTE (*((volatile unsigned int*)(0x42A78830UL))) +#define bM4_PORT_PCRB0_LTE (*((volatile unsigned int*)(0x42A78838UL))) +#define bM4_PORT_PCRB0_DDIS (*((volatile unsigned int*)(0x42A7883CUL))) +#define bM4_PORT_PFSRB0_FSEL0 (*((volatile unsigned int*)(0x42A78840UL))) +#define bM4_PORT_PFSRB0_FSEL1 (*((volatile unsigned int*)(0x42A78844UL))) +#define bM4_PORT_PFSRB0_FSEL2 (*((volatile unsigned int*)(0x42A78848UL))) +#define bM4_PORT_PFSRB0_FSEL3 (*((volatile unsigned int*)(0x42A7884CUL))) +#define bM4_PORT_PFSRB0_FSEL4 (*((volatile unsigned int*)(0x42A78850UL))) +#define bM4_PORT_PFSRB0_FSEL5 (*((volatile unsigned int*)(0x42A78854UL))) +#define bM4_PORT_PFSRB0_BFE (*((volatile unsigned int*)(0x42A78860UL))) +#define bM4_PORT_PCRB1_POUT (*((volatile unsigned int*)(0x42A78880UL))) +#define bM4_PORT_PCRB1_POUTE (*((volatile unsigned int*)(0x42A78884UL))) +#define bM4_PORT_PCRB1_NOD (*((volatile unsigned int*)(0x42A78888UL))) +#define bM4_PORT_PCRB1_DRV0 (*((volatile unsigned int*)(0x42A78890UL))) +#define bM4_PORT_PCRB1_DRV1 (*((volatile unsigned int*)(0x42A78894UL))) +#define bM4_PORT_PCRB1_PUU (*((volatile unsigned int*)(0x42A78898UL))) +#define bM4_PORT_PCRB1_PIN (*((volatile unsigned int*)(0x42A788A0UL))) +#define bM4_PORT_PCRB1_INVE (*((volatile unsigned int*)(0x42A788A4UL))) +#define bM4_PORT_PCRB1_INTE (*((volatile unsigned int*)(0x42A788B0UL))) +#define bM4_PORT_PCRB1_LTE (*((volatile unsigned int*)(0x42A788B8UL))) +#define bM4_PORT_PCRB1_DDIS (*((volatile unsigned int*)(0x42A788BCUL))) +#define bM4_PORT_PFSRB1_FSEL0 (*((volatile unsigned int*)(0x42A788C0UL))) +#define bM4_PORT_PFSRB1_FSEL1 (*((volatile unsigned int*)(0x42A788C4UL))) +#define bM4_PORT_PFSRB1_FSEL2 (*((volatile unsigned int*)(0x42A788C8UL))) +#define bM4_PORT_PFSRB1_FSEL3 (*((volatile unsigned int*)(0x42A788CCUL))) +#define bM4_PORT_PFSRB1_FSEL4 (*((volatile unsigned int*)(0x42A788D0UL))) +#define bM4_PORT_PFSRB1_FSEL5 (*((volatile unsigned int*)(0x42A788D4UL))) +#define bM4_PORT_PFSRB1_BFE (*((volatile unsigned int*)(0x42A788E0UL))) +#define bM4_PORT_PCRB2_POUT (*((volatile unsigned int*)(0x42A78900UL))) +#define bM4_PORT_PCRB2_POUTE (*((volatile unsigned int*)(0x42A78904UL))) +#define bM4_PORT_PCRB2_NOD (*((volatile unsigned int*)(0x42A78908UL))) +#define bM4_PORT_PCRB2_DRV0 (*((volatile unsigned int*)(0x42A78910UL))) +#define bM4_PORT_PCRB2_DRV1 (*((volatile unsigned int*)(0x42A78914UL))) +#define bM4_PORT_PCRB2_PUU (*((volatile unsigned int*)(0x42A78918UL))) +#define bM4_PORT_PCRB2_PIN (*((volatile unsigned int*)(0x42A78920UL))) +#define bM4_PORT_PCRB2_INVE (*((volatile unsigned int*)(0x42A78924UL))) +#define bM4_PORT_PCRB2_INTE (*((volatile unsigned int*)(0x42A78930UL))) +#define bM4_PORT_PCRB2_LTE (*((volatile unsigned int*)(0x42A78938UL))) +#define bM4_PORT_PCRB2_DDIS (*((volatile unsigned int*)(0x42A7893CUL))) +#define bM4_PORT_PFSRB2_FSEL0 (*((volatile unsigned int*)(0x42A78940UL))) +#define bM4_PORT_PFSRB2_FSEL1 (*((volatile unsigned int*)(0x42A78944UL))) +#define bM4_PORT_PFSRB2_FSEL2 (*((volatile unsigned int*)(0x42A78948UL))) +#define bM4_PORT_PFSRB2_FSEL3 (*((volatile unsigned int*)(0x42A7894CUL))) +#define bM4_PORT_PFSRB2_FSEL4 (*((volatile unsigned int*)(0x42A78950UL))) +#define bM4_PORT_PFSRB2_FSEL5 (*((volatile unsigned int*)(0x42A78954UL))) +#define bM4_PORT_PFSRB2_BFE (*((volatile unsigned int*)(0x42A78960UL))) +#define bM4_PORT_PCRB3_POUT (*((volatile unsigned int*)(0x42A78980UL))) +#define bM4_PORT_PCRB3_POUTE (*((volatile unsigned int*)(0x42A78984UL))) +#define bM4_PORT_PCRB3_NOD (*((volatile unsigned int*)(0x42A78988UL))) +#define bM4_PORT_PCRB3_DRV0 (*((volatile unsigned int*)(0x42A78990UL))) +#define bM4_PORT_PCRB3_DRV1 (*((volatile unsigned int*)(0x42A78994UL))) +#define bM4_PORT_PCRB3_PUU (*((volatile unsigned int*)(0x42A78998UL))) +#define bM4_PORT_PCRB3_PIN (*((volatile unsigned int*)(0x42A789A0UL))) +#define bM4_PORT_PCRB3_INVE (*((volatile unsigned int*)(0x42A789A4UL))) +#define bM4_PORT_PCRB3_INTE (*((volatile unsigned int*)(0x42A789B0UL))) +#define bM4_PORT_PCRB3_LTE (*((volatile unsigned int*)(0x42A789B8UL))) +#define bM4_PORT_PCRB3_DDIS (*((volatile unsigned int*)(0x42A789BCUL))) +#define bM4_PORT_PFSRB3_FSEL0 (*((volatile unsigned int*)(0x42A789C0UL))) +#define bM4_PORT_PFSRB3_FSEL1 (*((volatile unsigned int*)(0x42A789C4UL))) +#define bM4_PORT_PFSRB3_FSEL2 (*((volatile unsigned int*)(0x42A789C8UL))) +#define bM4_PORT_PFSRB3_FSEL3 (*((volatile unsigned int*)(0x42A789CCUL))) +#define bM4_PORT_PFSRB3_FSEL4 (*((volatile unsigned int*)(0x42A789D0UL))) +#define bM4_PORT_PFSRB3_FSEL5 (*((volatile unsigned int*)(0x42A789D4UL))) +#define bM4_PORT_PFSRB3_BFE (*((volatile unsigned int*)(0x42A789E0UL))) +#define bM4_PORT_PCRB4_POUT (*((volatile unsigned int*)(0x42A78A00UL))) +#define bM4_PORT_PCRB4_POUTE (*((volatile unsigned int*)(0x42A78A04UL))) +#define bM4_PORT_PCRB4_NOD (*((volatile unsigned int*)(0x42A78A08UL))) +#define bM4_PORT_PCRB4_DRV0 (*((volatile unsigned int*)(0x42A78A10UL))) +#define bM4_PORT_PCRB4_DRV1 (*((volatile unsigned int*)(0x42A78A14UL))) +#define bM4_PORT_PCRB4_PUU (*((volatile unsigned int*)(0x42A78A18UL))) +#define bM4_PORT_PCRB4_PIN (*((volatile unsigned int*)(0x42A78A20UL))) +#define bM4_PORT_PCRB4_INVE (*((volatile unsigned int*)(0x42A78A24UL))) +#define bM4_PORT_PCRB4_INTE (*((volatile unsigned int*)(0x42A78A30UL))) +#define bM4_PORT_PCRB4_LTE (*((volatile unsigned int*)(0x42A78A38UL))) +#define bM4_PORT_PCRB4_DDIS (*((volatile unsigned int*)(0x42A78A3CUL))) +#define bM4_PORT_PFSRB4_FSEL0 (*((volatile unsigned int*)(0x42A78A40UL))) +#define bM4_PORT_PFSRB4_FSEL1 (*((volatile unsigned int*)(0x42A78A44UL))) +#define bM4_PORT_PFSRB4_FSEL2 (*((volatile unsigned int*)(0x42A78A48UL))) +#define bM4_PORT_PFSRB4_FSEL3 (*((volatile unsigned int*)(0x42A78A4CUL))) +#define bM4_PORT_PFSRB4_FSEL4 (*((volatile unsigned int*)(0x42A78A50UL))) +#define bM4_PORT_PFSRB4_FSEL5 (*((volatile unsigned int*)(0x42A78A54UL))) +#define bM4_PORT_PFSRB4_BFE (*((volatile unsigned int*)(0x42A78A60UL))) +#define bM4_PORT_PCRB5_POUT (*((volatile unsigned int*)(0x42A78A80UL))) +#define bM4_PORT_PCRB5_POUTE (*((volatile unsigned int*)(0x42A78A84UL))) +#define bM4_PORT_PCRB5_NOD (*((volatile unsigned int*)(0x42A78A88UL))) +#define bM4_PORT_PCRB5_DRV0 (*((volatile unsigned int*)(0x42A78A90UL))) +#define bM4_PORT_PCRB5_DRV1 (*((volatile unsigned int*)(0x42A78A94UL))) +#define bM4_PORT_PCRB5_PUU (*((volatile unsigned int*)(0x42A78A98UL))) +#define bM4_PORT_PCRB5_PIN (*((volatile unsigned int*)(0x42A78AA0UL))) +#define bM4_PORT_PCRB5_INVE (*((volatile unsigned int*)(0x42A78AA4UL))) +#define bM4_PORT_PCRB5_INTE (*((volatile unsigned int*)(0x42A78AB0UL))) +#define bM4_PORT_PCRB5_LTE (*((volatile unsigned int*)(0x42A78AB8UL))) +#define bM4_PORT_PCRB5_DDIS (*((volatile unsigned int*)(0x42A78ABCUL))) +#define bM4_PORT_PFSRB5_FSEL0 (*((volatile unsigned int*)(0x42A78AC0UL))) +#define bM4_PORT_PFSRB5_FSEL1 (*((volatile unsigned int*)(0x42A78AC4UL))) +#define bM4_PORT_PFSRB5_FSEL2 (*((volatile unsigned int*)(0x42A78AC8UL))) +#define bM4_PORT_PFSRB5_FSEL3 (*((volatile unsigned int*)(0x42A78ACCUL))) +#define bM4_PORT_PFSRB5_FSEL4 (*((volatile unsigned int*)(0x42A78AD0UL))) +#define bM4_PORT_PFSRB5_FSEL5 (*((volatile unsigned int*)(0x42A78AD4UL))) +#define bM4_PORT_PFSRB5_BFE (*((volatile unsigned int*)(0x42A78AE0UL))) +#define bM4_PORT_PCRB6_POUT (*((volatile unsigned int*)(0x42A78B00UL))) +#define bM4_PORT_PCRB6_POUTE (*((volatile unsigned int*)(0x42A78B04UL))) +#define bM4_PORT_PCRB6_NOD (*((volatile unsigned int*)(0x42A78B08UL))) +#define bM4_PORT_PCRB6_DRV0 (*((volatile unsigned int*)(0x42A78B10UL))) +#define bM4_PORT_PCRB6_DRV1 (*((volatile unsigned int*)(0x42A78B14UL))) +#define bM4_PORT_PCRB6_PUU (*((volatile unsigned int*)(0x42A78B18UL))) +#define bM4_PORT_PCRB6_PIN (*((volatile unsigned int*)(0x42A78B20UL))) +#define bM4_PORT_PCRB6_INVE (*((volatile unsigned int*)(0x42A78B24UL))) +#define bM4_PORT_PCRB6_INTE (*((volatile unsigned int*)(0x42A78B30UL))) +#define bM4_PORT_PCRB6_LTE (*((volatile unsigned int*)(0x42A78B38UL))) +#define bM4_PORT_PCRB6_DDIS (*((volatile unsigned int*)(0x42A78B3CUL))) +#define bM4_PORT_PFSRB6_FSEL0 (*((volatile unsigned int*)(0x42A78B40UL))) +#define bM4_PORT_PFSRB6_FSEL1 (*((volatile unsigned int*)(0x42A78B44UL))) +#define bM4_PORT_PFSRB6_FSEL2 (*((volatile unsigned int*)(0x42A78B48UL))) +#define bM4_PORT_PFSRB6_FSEL3 (*((volatile unsigned int*)(0x42A78B4CUL))) +#define bM4_PORT_PFSRB6_FSEL4 (*((volatile unsigned int*)(0x42A78B50UL))) +#define bM4_PORT_PFSRB6_FSEL5 (*((volatile unsigned int*)(0x42A78B54UL))) +#define bM4_PORT_PFSRB6_BFE (*((volatile unsigned int*)(0x42A78B60UL))) +#define bM4_PORT_PCRB7_POUT (*((volatile unsigned int*)(0x42A78B80UL))) +#define bM4_PORT_PCRB7_POUTE (*((volatile unsigned int*)(0x42A78B84UL))) +#define bM4_PORT_PCRB7_NOD (*((volatile unsigned int*)(0x42A78B88UL))) +#define bM4_PORT_PCRB7_DRV0 (*((volatile unsigned int*)(0x42A78B90UL))) +#define bM4_PORT_PCRB7_DRV1 (*((volatile unsigned int*)(0x42A78B94UL))) +#define bM4_PORT_PCRB7_PUU (*((volatile unsigned int*)(0x42A78B98UL))) +#define bM4_PORT_PCRB7_PIN (*((volatile unsigned int*)(0x42A78BA0UL))) +#define bM4_PORT_PCRB7_INVE (*((volatile unsigned int*)(0x42A78BA4UL))) +#define bM4_PORT_PCRB7_INTE (*((volatile unsigned int*)(0x42A78BB0UL))) +#define bM4_PORT_PCRB7_LTE (*((volatile unsigned int*)(0x42A78BB8UL))) +#define bM4_PORT_PCRB7_DDIS (*((volatile unsigned int*)(0x42A78BBCUL))) +#define bM4_PORT_PFSRB7_FSEL0 (*((volatile unsigned int*)(0x42A78BC0UL))) +#define bM4_PORT_PFSRB7_FSEL1 (*((volatile unsigned int*)(0x42A78BC4UL))) +#define bM4_PORT_PFSRB7_FSEL2 (*((volatile unsigned int*)(0x42A78BC8UL))) +#define bM4_PORT_PFSRB7_FSEL3 (*((volatile unsigned int*)(0x42A78BCCUL))) +#define bM4_PORT_PFSRB7_FSEL4 (*((volatile unsigned int*)(0x42A78BD0UL))) +#define bM4_PORT_PFSRB7_FSEL5 (*((volatile unsigned int*)(0x42A78BD4UL))) +#define bM4_PORT_PFSRB7_BFE (*((volatile unsigned int*)(0x42A78BE0UL))) +#define bM4_PORT_PCRB8_POUT (*((volatile unsigned int*)(0x42A78C00UL))) +#define bM4_PORT_PCRB8_POUTE (*((volatile unsigned int*)(0x42A78C04UL))) +#define bM4_PORT_PCRB8_NOD (*((volatile unsigned int*)(0x42A78C08UL))) +#define bM4_PORT_PCRB8_DRV0 (*((volatile unsigned int*)(0x42A78C10UL))) +#define bM4_PORT_PCRB8_DRV1 (*((volatile unsigned int*)(0x42A78C14UL))) +#define bM4_PORT_PCRB8_PUU (*((volatile unsigned int*)(0x42A78C18UL))) +#define bM4_PORT_PCRB8_PIN (*((volatile unsigned int*)(0x42A78C20UL))) +#define bM4_PORT_PCRB8_INVE (*((volatile unsigned int*)(0x42A78C24UL))) +#define bM4_PORT_PCRB8_INTE (*((volatile unsigned int*)(0x42A78C30UL))) +#define bM4_PORT_PCRB8_LTE (*((volatile unsigned int*)(0x42A78C38UL))) +#define bM4_PORT_PCRB8_DDIS (*((volatile unsigned int*)(0x42A78C3CUL))) +#define bM4_PORT_PFSRB8_FSEL0 (*((volatile unsigned int*)(0x42A78C40UL))) +#define bM4_PORT_PFSRB8_FSEL1 (*((volatile unsigned int*)(0x42A78C44UL))) +#define bM4_PORT_PFSRB8_FSEL2 (*((volatile unsigned int*)(0x42A78C48UL))) +#define bM4_PORT_PFSRB8_FSEL3 (*((volatile unsigned int*)(0x42A78C4CUL))) +#define bM4_PORT_PFSRB8_FSEL4 (*((volatile unsigned int*)(0x42A78C50UL))) +#define bM4_PORT_PFSRB8_FSEL5 (*((volatile unsigned int*)(0x42A78C54UL))) +#define bM4_PORT_PFSRB8_BFE (*((volatile unsigned int*)(0x42A78C60UL))) +#define bM4_PORT_PCRB9_POUT (*((volatile unsigned int*)(0x42A78C80UL))) +#define bM4_PORT_PCRB9_POUTE (*((volatile unsigned int*)(0x42A78C84UL))) +#define bM4_PORT_PCRB9_NOD (*((volatile unsigned int*)(0x42A78C88UL))) +#define bM4_PORT_PCRB9_DRV0 (*((volatile unsigned int*)(0x42A78C90UL))) +#define bM4_PORT_PCRB9_DRV1 (*((volatile unsigned int*)(0x42A78C94UL))) +#define bM4_PORT_PCRB9_PUU (*((volatile unsigned int*)(0x42A78C98UL))) +#define bM4_PORT_PCRB9_PIN (*((volatile unsigned int*)(0x42A78CA0UL))) +#define bM4_PORT_PCRB9_INVE (*((volatile unsigned int*)(0x42A78CA4UL))) +#define bM4_PORT_PCRB9_INTE (*((volatile unsigned int*)(0x42A78CB0UL))) +#define bM4_PORT_PCRB9_LTE (*((volatile unsigned int*)(0x42A78CB8UL))) +#define bM4_PORT_PCRB9_DDIS (*((volatile unsigned int*)(0x42A78CBCUL))) +#define bM4_PORT_PFSRB9_FSEL0 (*((volatile unsigned int*)(0x42A78CC0UL))) +#define bM4_PORT_PFSRB9_FSEL1 (*((volatile unsigned int*)(0x42A78CC4UL))) +#define bM4_PORT_PFSRB9_FSEL2 (*((volatile unsigned int*)(0x42A78CC8UL))) +#define bM4_PORT_PFSRB9_FSEL3 (*((volatile unsigned int*)(0x42A78CCCUL))) +#define bM4_PORT_PFSRB9_FSEL4 (*((volatile unsigned int*)(0x42A78CD0UL))) +#define bM4_PORT_PFSRB9_FSEL5 (*((volatile unsigned int*)(0x42A78CD4UL))) +#define bM4_PORT_PFSRB9_BFE (*((volatile unsigned int*)(0x42A78CE0UL))) +#define bM4_PORT_PCRB10_POUT (*((volatile unsigned int*)(0x42A78D00UL))) +#define bM4_PORT_PCRB10_POUTE (*((volatile unsigned int*)(0x42A78D04UL))) +#define bM4_PORT_PCRB10_NOD (*((volatile unsigned int*)(0x42A78D08UL))) +#define bM4_PORT_PCRB10_DRV0 (*((volatile unsigned int*)(0x42A78D10UL))) +#define bM4_PORT_PCRB10_DRV1 (*((volatile unsigned int*)(0x42A78D14UL))) +#define bM4_PORT_PCRB10_PUU (*((volatile unsigned int*)(0x42A78D18UL))) +#define bM4_PORT_PCRB10_PIN (*((volatile unsigned int*)(0x42A78D20UL))) +#define bM4_PORT_PCRB10_INVE (*((volatile unsigned int*)(0x42A78D24UL))) +#define bM4_PORT_PCRB10_INTE (*((volatile unsigned int*)(0x42A78D30UL))) +#define bM4_PORT_PCRB10_LTE (*((volatile unsigned int*)(0x42A78D38UL))) +#define bM4_PORT_PCRB10_DDIS (*((volatile unsigned int*)(0x42A78D3CUL))) +#define bM4_PORT_PFSRB10_FSEL0 (*((volatile unsigned int*)(0x42A78D40UL))) +#define bM4_PORT_PFSRB10_FSEL1 (*((volatile unsigned int*)(0x42A78D44UL))) +#define bM4_PORT_PFSRB10_FSEL2 (*((volatile unsigned int*)(0x42A78D48UL))) +#define bM4_PORT_PFSRB10_FSEL3 (*((volatile unsigned int*)(0x42A78D4CUL))) +#define bM4_PORT_PFSRB10_FSEL4 (*((volatile unsigned int*)(0x42A78D50UL))) +#define bM4_PORT_PFSRB10_FSEL5 (*((volatile unsigned int*)(0x42A78D54UL))) +#define bM4_PORT_PFSRB10_BFE (*((volatile unsigned int*)(0x42A78D60UL))) +#define bM4_PORT_PCRB11_POUT (*((volatile unsigned int*)(0x42A78D80UL))) +#define bM4_PORT_PCRB11_POUTE (*((volatile unsigned int*)(0x42A78D84UL))) +#define bM4_PORT_PCRB11_NOD (*((volatile unsigned int*)(0x42A78D88UL))) +#define bM4_PORT_PCRB11_DRV0 (*((volatile unsigned int*)(0x42A78D90UL))) +#define bM4_PORT_PCRB11_DRV1 (*((volatile unsigned int*)(0x42A78D94UL))) +#define bM4_PORT_PCRB11_PUU (*((volatile unsigned int*)(0x42A78D98UL))) +#define bM4_PORT_PCRB11_PIN (*((volatile unsigned int*)(0x42A78DA0UL))) +#define bM4_PORT_PCRB11_INVE (*((volatile unsigned int*)(0x42A78DA4UL))) +#define bM4_PORT_PCRB11_INTE (*((volatile unsigned int*)(0x42A78DB0UL))) +#define bM4_PORT_PCRB11_LTE (*((volatile unsigned int*)(0x42A78DB8UL))) +#define bM4_PORT_PCRB11_DDIS (*((volatile unsigned int*)(0x42A78DBCUL))) +#define bM4_PORT_PFSRB11_FSEL0 (*((volatile unsigned int*)(0x42A78DC0UL))) +#define bM4_PORT_PFSRB11_FSEL1 (*((volatile unsigned int*)(0x42A78DC4UL))) +#define bM4_PORT_PFSRB11_FSEL2 (*((volatile unsigned int*)(0x42A78DC8UL))) +#define bM4_PORT_PFSRB11_FSEL3 (*((volatile unsigned int*)(0x42A78DCCUL))) +#define bM4_PORT_PFSRB11_FSEL4 (*((volatile unsigned int*)(0x42A78DD0UL))) +#define bM4_PORT_PFSRB11_FSEL5 (*((volatile unsigned int*)(0x42A78DD4UL))) +#define bM4_PORT_PFSRB11_BFE (*((volatile unsigned int*)(0x42A78DE0UL))) +#define bM4_PORT_PCRB12_POUT (*((volatile unsigned int*)(0x42A78E00UL))) +#define bM4_PORT_PCRB12_POUTE (*((volatile unsigned int*)(0x42A78E04UL))) +#define bM4_PORT_PCRB12_NOD (*((volatile unsigned int*)(0x42A78E08UL))) +#define bM4_PORT_PCRB12_DRV0 (*((volatile unsigned int*)(0x42A78E10UL))) +#define bM4_PORT_PCRB12_DRV1 (*((volatile unsigned int*)(0x42A78E14UL))) +#define bM4_PORT_PCRB12_PUU (*((volatile unsigned int*)(0x42A78E18UL))) +#define bM4_PORT_PCRB12_PIN (*((volatile unsigned int*)(0x42A78E20UL))) +#define bM4_PORT_PCRB12_INVE (*((volatile unsigned int*)(0x42A78E24UL))) +#define bM4_PORT_PCRB12_INTE (*((volatile unsigned int*)(0x42A78E30UL))) +#define bM4_PORT_PCRB12_LTE (*((volatile unsigned int*)(0x42A78E38UL))) +#define bM4_PORT_PCRB12_DDIS (*((volatile unsigned int*)(0x42A78E3CUL))) +#define bM4_PORT_PFSRB12_FSEL0 (*((volatile unsigned int*)(0x42A78E40UL))) +#define bM4_PORT_PFSRB12_FSEL1 (*((volatile unsigned int*)(0x42A78E44UL))) +#define bM4_PORT_PFSRB12_FSEL2 (*((volatile unsigned int*)(0x42A78E48UL))) +#define bM4_PORT_PFSRB12_FSEL3 (*((volatile unsigned int*)(0x42A78E4CUL))) +#define bM4_PORT_PFSRB12_FSEL4 (*((volatile unsigned int*)(0x42A78E50UL))) +#define bM4_PORT_PFSRB12_FSEL5 (*((volatile unsigned int*)(0x42A78E54UL))) +#define bM4_PORT_PFSRB12_BFE (*((volatile unsigned int*)(0x42A78E60UL))) +#define bM4_PORT_PCRB13_POUT (*((volatile unsigned int*)(0x42A78E80UL))) +#define bM4_PORT_PCRB13_POUTE (*((volatile unsigned int*)(0x42A78E84UL))) +#define bM4_PORT_PCRB13_NOD (*((volatile unsigned int*)(0x42A78E88UL))) +#define bM4_PORT_PCRB13_DRV0 (*((volatile unsigned int*)(0x42A78E90UL))) +#define bM4_PORT_PCRB13_DRV1 (*((volatile unsigned int*)(0x42A78E94UL))) +#define bM4_PORT_PCRB13_PUU (*((volatile unsigned int*)(0x42A78E98UL))) +#define bM4_PORT_PCRB13_PIN (*((volatile unsigned int*)(0x42A78EA0UL))) +#define bM4_PORT_PCRB13_INVE (*((volatile unsigned int*)(0x42A78EA4UL))) +#define bM4_PORT_PCRB13_INTE (*((volatile unsigned int*)(0x42A78EB0UL))) +#define bM4_PORT_PCRB13_LTE (*((volatile unsigned int*)(0x42A78EB8UL))) +#define bM4_PORT_PCRB13_DDIS (*((volatile unsigned int*)(0x42A78EBCUL))) +#define bM4_PORT_PFSRB13_FSEL0 (*((volatile unsigned int*)(0x42A78EC0UL))) +#define bM4_PORT_PFSRB13_FSEL1 (*((volatile unsigned int*)(0x42A78EC4UL))) +#define bM4_PORT_PFSRB13_FSEL2 (*((volatile unsigned int*)(0x42A78EC8UL))) +#define bM4_PORT_PFSRB13_FSEL3 (*((volatile unsigned int*)(0x42A78ECCUL))) +#define bM4_PORT_PFSRB13_FSEL4 (*((volatile unsigned int*)(0x42A78ED0UL))) +#define bM4_PORT_PFSRB13_FSEL5 (*((volatile unsigned int*)(0x42A78ED4UL))) +#define bM4_PORT_PFSRB13_BFE (*((volatile unsigned int*)(0x42A78EE0UL))) +#define bM4_PORT_PCRB14_POUT (*((volatile unsigned int*)(0x42A78F00UL))) +#define bM4_PORT_PCRB14_POUTE (*((volatile unsigned int*)(0x42A78F04UL))) +#define bM4_PORT_PCRB14_NOD (*((volatile unsigned int*)(0x42A78F08UL))) +#define bM4_PORT_PCRB14_DRV0 (*((volatile unsigned int*)(0x42A78F10UL))) +#define bM4_PORT_PCRB14_DRV1 (*((volatile unsigned int*)(0x42A78F14UL))) +#define bM4_PORT_PCRB14_PUU (*((volatile unsigned int*)(0x42A78F18UL))) +#define bM4_PORT_PCRB14_PIN (*((volatile unsigned int*)(0x42A78F20UL))) +#define bM4_PORT_PCRB14_INVE (*((volatile unsigned int*)(0x42A78F24UL))) +#define bM4_PORT_PCRB14_INTE (*((volatile unsigned int*)(0x42A78F30UL))) +#define bM4_PORT_PCRB14_LTE (*((volatile unsigned int*)(0x42A78F38UL))) +#define bM4_PORT_PCRB14_DDIS (*((volatile unsigned int*)(0x42A78F3CUL))) +#define bM4_PORT_PFSRB14_FSEL0 (*((volatile unsigned int*)(0x42A78F40UL))) +#define bM4_PORT_PFSRB14_FSEL1 (*((volatile unsigned int*)(0x42A78F44UL))) +#define bM4_PORT_PFSRB14_FSEL2 (*((volatile unsigned int*)(0x42A78F48UL))) +#define bM4_PORT_PFSRB14_FSEL3 (*((volatile unsigned int*)(0x42A78F4CUL))) +#define bM4_PORT_PFSRB14_FSEL4 (*((volatile unsigned int*)(0x42A78F50UL))) +#define bM4_PORT_PFSRB14_FSEL5 (*((volatile unsigned int*)(0x42A78F54UL))) +#define bM4_PORT_PFSRB14_BFE (*((volatile unsigned int*)(0x42A78F60UL))) +#define bM4_PORT_PCRB15_POUT (*((volatile unsigned int*)(0x42A78F80UL))) +#define bM4_PORT_PCRB15_POUTE (*((volatile unsigned int*)(0x42A78F84UL))) +#define bM4_PORT_PCRB15_NOD (*((volatile unsigned int*)(0x42A78F88UL))) +#define bM4_PORT_PCRB15_DRV0 (*((volatile unsigned int*)(0x42A78F90UL))) +#define bM4_PORT_PCRB15_DRV1 (*((volatile unsigned int*)(0x42A78F94UL))) +#define bM4_PORT_PCRB15_PUU (*((volatile unsigned int*)(0x42A78F98UL))) +#define bM4_PORT_PCRB15_PIN (*((volatile unsigned int*)(0x42A78FA0UL))) +#define bM4_PORT_PCRB15_INVE (*((volatile unsigned int*)(0x42A78FA4UL))) +#define bM4_PORT_PCRB15_INTE (*((volatile unsigned int*)(0x42A78FB0UL))) +#define bM4_PORT_PCRB15_LTE (*((volatile unsigned int*)(0x42A78FB8UL))) +#define bM4_PORT_PCRB15_DDIS (*((volatile unsigned int*)(0x42A78FBCUL))) +#define bM4_PORT_PFSRB15_FSEL0 (*((volatile unsigned int*)(0x42A78FC0UL))) +#define bM4_PORT_PFSRB15_FSEL1 (*((volatile unsigned int*)(0x42A78FC4UL))) +#define bM4_PORT_PFSRB15_FSEL2 (*((volatile unsigned int*)(0x42A78FC8UL))) +#define bM4_PORT_PFSRB15_FSEL3 (*((volatile unsigned int*)(0x42A78FCCUL))) +#define bM4_PORT_PFSRB15_FSEL4 (*((volatile unsigned int*)(0x42A78FD0UL))) +#define bM4_PORT_PFSRB15_FSEL5 (*((volatile unsigned int*)(0x42A78FD4UL))) +#define bM4_PORT_PFSRB15_BFE (*((volatile unsigned int*)(0x42A78FE0UL))) +#define bM4_PORT_PCRC0_POUT (*((volatile unsigned int*)(0x42A79000UL))) +#define bM4_PORT_PCRC0_POUTE (*((volatile unsigned int*)(0x42A79004UL))) +#define bM4_PORT_PCRC0_NOD (*((volatile unsigned int*)(0x42A79008UL))) +#define bM4_PORT_PCRC0_DRV0 (*((volatile unsigned int*)(0x42A79010UL))) +#define bM4_PORT_PCRC0_DRV1 (*((volatile unsigned int*)(0x42A79014UL))) +#define bM4_PORT_PCRC0_PUU (*((volatile unsigned int*)(0x42A79018UL))) +#define bM4_PORT_PCRC0_PIN (*((volatile unsigned int*)(0x42A79020UL))) +#define bM4_PORT_PCRC0_INVE (*((volatile unsigned int*)(0x42A79024UL))) +#define bM4_PORT_PCRC0_INTE (*((volatile unsigned int*)(0x42A79030UL))) +#define bM4_PORT_PCRC0_LTE (*((volatile unsigned int*)(0x42A79038UL))) +#define bM4_PORT_PCRC0_DDIS (*((volatile unsigned int*)(0x42A7903CUL))) +#define bM4_PORT_PFSRC0_FSEL0 (*((volatile unsigned int*)(0x42A79040UL))) +#define bM4_PORT_PFSRC0_FSEL1 (*((volatile unsigned int*)(0x42A79044UL))) +#define bM4_PORT_PFSRC0_FSEL2 (*((volatile unsigned int*)(0x42A79048UL))) +#define bM4_PORT_PFSRC0_FSEL3 (*((volatile unsigned int*)(0x42A7904CUL))) +#define bM4_PORT_PFSRC0_FSEL4 (*((volatile unsigned int*)(0x42A79050UL))) +#define bM4_PORT_PFSRC0_FSEL5 (*((volatile unsigned int*)(0x42A79054UL))) +#define bM4_PORT_PFSRC0_BFE (*((volatile unsigned int*)(0x42A79060UL))) +#define bM4_PORT_PCRC1_POUT (*((volatile unsigned int*)(0x42A79080UL))) +#define bM4_PORT_PCRC1_POUTE (*((volatile unsigned int*)(0x42A79084UL))) +#define bM4_PORT_PCRC1_NOD (*((volatile unsigned int*)(0x42A79088UL))) +#define bM4_PORT_PCRC1_DRV0 (*((volatile unsigned int*)(0x42A79090UL))) +#define bM4_PORT_PCRC1_DRV1 (*((volatile unsigned int*)(0x42A79094UL))) +#define bM4_PORT_PCRC1_PUU (*((volatile unsigned int*)(0x42A79098UL))) +#define bM4_PORT_PCRC1_PIN (*((volatile unsigned int*)(0x42A790A0UL))) +#define bM4_PORT_PCRC1_INVE (*((volatile unsigned int*)(0x42A790A4UL))) +#define bM4_PORT_PCRC1_INTE (*((volatile unsigned int*)(0x42A790B0UL))) +#define bM4_PORT_PCRC1_LTE (*((volatile unsigned int*)(0x42A790B8UL))) +#define bM4_PORT_PCRC1_DDIS (*((volatile unsigned int*)(0x42A790BCUL))) +#define bM4_PORT_PFSRC1_FSEL0 (*((volatile unsigned int*)(0x42A790C0UL))) +#define bM4_PORT_PFSRC1_FSEL1 (*((volatile unsigned int*)(0x42A790C4UL))) +#define bM4_PORT_PFSRC1_FSEL2 (*((volatile unsigned int*)(0x42A790C8UL))) +#define bM4_PORT_PFSRC1_FSEL3 (*((volatile unsigned int*)(0x42A790CCUL))) +#define bM4_PORT_PFSRC1_FSEL4 (*((volatile unsigned int*)(0x42A790D0UL))) +#define bM4_PORT_PFSRC1_FSEL5 (*((volatile unsigned int*)(0x42A790D4UL))) +#define bM4_PORT_PFSRC1_BFE (*((volatile unsigned int*)(0x42A790E0UL))) +#define bM4_PORT_PCRC2_POUT (*((volatile unsigned int*)(0x42A79100UL))) +#define bM4_PORT_PCRC2_POUTE (*((volatile unsigned int*)(0x42A79104UL))) +#define bM4_PORT_PCRC2_NOD (*((volatile unsigned int*)(0x42A79108UL))) +#define bM4_PORT_PCRC2_DRV0 (*((volatile unsigned int*)(0x42A79110UL))) +#define bM4_PORT_PCRC2_DRV1 (*((volatile unsigned int*)(0x42A79114UL))) +#define bM4_PORT_PCRC2_PUU (*((volatile unsigned int*)(0x42A79118UL))) +#define bM4_PORT_PCRC2_PIN (*((volatile unsigned int*)(0x42A79120UL))) +#define bM4_PORT_PCRC2_INVE (*((volatile unsigned int*)(0x42A79124UL))) +#define bM4_PORT_PCRC2_INTE (*((volatile unsigned int*)(0x42A79130UL))) +#define bM4_PORT_PCRC2_LTE (*((volatile unsigned int*)(0x42A79138UL))) +#define bM4_PORT_PCRC2_DDIS (*((volatile unsigned int*)(0x42A7913CUL))) +#define bM4_PORT_PFSRC2_FSEL0 (*((volatile unsigned int*)(0x42A79140UL))) +#define bM4_PORT_PFSRC2_FSEL1 (*((volatile unsigned int*)(0x42A79144UL))) +#define bM4_PORT_PFSRC2_FSEL2 (*((volatile unsigned int*)(0x42A79148UL))) +#define bM4_PORT_PFSRC2_FSEL3 (*((volatile unsigned int*)(0x42A7914CUL))) +#define bM4_PORT_PFSRC2_FSEL4 (*((volatile unsigned int*)(0x42A79150UL))) +#define bM4_PORT_PFSRC2_FSEL5 (*((volatile unsigned int*)(0x42A79154UL))) +#define bM4_PORT_PFSRC2_BFE (*((volatile unsigned int*)(0x42A79160UL))) +#define bM4_PORT_PCRC3_POUT (*((volatile unsigned int*)(0x42A79180UL))) +#define bM4_PORT_PCRC3_POUTE (*((volatile unsigned int*)(0x42A79184UL))) +#define bM4_PORT_PCRC3_NOD (*((volatile unsigned int*)(0x42A79188UL))) +#define bM4_PORT_PCRC3_DRV0 (*((volatile unsigned int*)(0x42A79190UL))) +#define bM4_PORT_PCRC3_DRV1 (*((volatile unsigned int*)(0x42A79194UL))) +#define bM4_PORT_PCRC3_PUU (*((volatile unsigned int*)(0x42A79198UL))) +#define bM4_PORT_PCRC3_PIN (*((volatile unsigned int*)(0x42A791A0UL))) +#define bM4_PORT_PCRC3_INVE (*((volatile unsigned int*)(0x42A791A4UL))) +#define bM4_PORT_PCRC3_INTE (*((volatile unsigned int*)(0x42A791B0UL))) +#define bM4_PORT_PCRC3_LTE (*((volatile unsigned int*)(0x42A791B8UL))) +#define bM4_PORT_PCRC3_DDIS (*((volatile unsigned int*)(0x42A791BCUL))) +#define bM4_PORT_PFSRC3_FSEL0 (*((volatile unsigned int*)(0x42A791C0UL))) +#define bM4_PORT_PFSRC3_FSEL1 (*((volatile unsigned int*)(0x42A791C4UL))) +#define bM4_PORT_PFSRC3_FSEL2 (*((volatile unsigned int*)(0x42A791C8UL))) +#define bM4_PORT_PFSRC3_FSEL3 (*((volatile unsigned int*)(0x42A791CCUL))) +#define bM4_PORT_PFSRC3_FSEL4 (*((volatile unsigned int*)(0x42A791D0UL))) +#define bM4_PORT_PFSRC3_FSEL5 (*((volatile unsigned int*)(0x42A791D4UL))) +#define bM4_PORT_PFSRC3_BFE (*((volatile unsigned int*)(0x42A791E0UL))) +#define bM4_PORT_PCRC4_POUT (*((volatile unsigned int*)(0x42A79200UL))) +#define bM4_PORT_PCRC4_POUTE (*((volatile unsigned int*)(0x42A79204UL))) +#define bM4_PORT_PCRC4_NOD (*((volatile unsigned int*)(0x42A79208UL))) +#define bM4_PORT_PCRC4_DRV0 (*((volatile unsigned int*)(0x42A79210UL))) +#define bM4_PORT_PCRC4_DRV1 (*((volatile unsigned int*)(0x42A79214UL))) +#define bM4_PORT_PCRC4_PUU (*((volatile unsigned int*)(0x42A79218UL))) +#define bM4_PORT_PCRC4_PIN (*((volatile unsigned int*)(0x42A79220UL))) +#define bM4_PORT_PCRC4_INVE (*((volatile unsigned int*)(0x42A79224UL))) +#define bM4_PORT_PCRC4_INTE (*((volatile unsigned int*)(0x42A79230UL))) +#define bM4_PORT_PCRC4_LTE (*((volatile unsigned int*)(0x42A79238UL))) +#define bM4_PORT_PCRC4_DDIS (*((volatile unsigned int*)(0x42A7923CUL))) +#define bM4_PORT_PFSRC4_FSEL0 (*((volatile unsigned int*)(0x42A79240UL))) +#define bM4_PORT_PFSRC4_FSEL1 (*((volatile unsigned int*)(0x42A79244UL))) +#define bM4_PORT_PFSRC4_FSEL2 (*((volatile unsigned int*)(0x42A79248UL))) +#define bM4_PORT_PFSRC4_FSEL3 (*((volatile unsigned int*)(0x42A7924CUL))) +#define bM4_PORT_PFSRC4_FSEL4 (*((volatile unsigned int*)(0x42A79250UL))) +#define bM4_PORT_PFSRC4_FSEL5 (*((volatile unsigned int*)(0x42A79254UL))) +#define bM4_PORT_PFSRC4_BFE (*((volatile unsigned int*)(0x42A79260UL))) +#define bM4_PORT_PCRC5_POUT (*((volatile unsigned int*)(0x42A79280UL))) +#define bM4_PORT_PCRC5_POUTE (*((volatile unsigned int*)(0x42A79284UL))) +#define bM4_PORT_PCRC5_NOD (*((volatile unsigned int*)(0x42A79288UL))) +#define bM4_PORT_PCRC5_DRV0 (*((volatile unsigned int*)(0x42A79290UL))) +#define bM4_PORT_PCRC5_DRV1 (*((volatile unsigned int*)(0x42A79294UL))) +#define bM4_PORT_PCRC5_PUU (*((volatile unsigned int*)(0x42A79298UL))) +#define bM4_PORT_PCRC5_PIN (*((volatile unsigned int*)(0x42A792A0UL))) +#define bM4_PORT_PCRC5_INVE (*((volatile unsigned int*)(0x42A792A4UL))) +#define bM4_PORT_PCRC5_INTE (*((volatile unsigned int*)(0x42A792B0UL))) +#define bM4_PORT_PCRC5_LTE (*((volatile unsigned int*)(0x42A792B8UL))) +#define bM4_PORT_PCRC5_DDIS (*((volatile unsigned int*)(0x42A792BCUL))) +#define bM4_PORT_PFSRC5_FSEL0 (*((volatile unsigned int*)(0x42A792C0UL))) +#define bM4_PORT_PFSRC5_FSEL1 (*((volatile unsigned int*)(0x42A792C4UL))) +#define bM4_PORT_PFSRC5_FSEL2 (*((volatile unsigned int*)(0x42A792C8UL))) +#define bM4_PORT_PFSRC5_FSEL3 (*((volatile unsigned int*)(0x42A792CCUL))) +#define bM4_PORT_PFSRC5_FSEL4 (*((volatile unsigned int*)(0x42A792D0UL))) +#define bM4_PORT_PFSRC5_FSEL5 (*((volatile unsigned int*)(0x42A792D4UL))) +#define bM4_PORT_PFSRC5_BFE (*((volatile unsigned int*)(0x42A792E0UL))) +#define bM4_PORT_PCRC6_POUT (*((volatile unsigned int*)(0x42A79300UL))) +#define bM4_PORT_PCRC6_POUTE (*((volatile unsigned int*)(0x42A79304UL))) +#define bM4_PORT_PCRC6_NOD (*((volatile unsigned int*)(0x42A79308UL))) +#define bM4_PORT_PCRC6_DRV0 (*((volatile unsigned int*)(0x42A79310UL))) +#define bM4_PORT_PCRC6_DRV1 (*((volatile unsigned int*)(0x42A79314UL))) +#define bM4_PORT_PCRC6_PUU (*((volatile unsigned int*)(0x42A79318UL))) +#define bM4_PORT_PCRC6_PIN (*((volatile unsigned int*)(0x42A79320UL))) +#define bM4_PORT_PCRC6_INVE (*((volatile unsigned int*)(0x42A79324UL))) +#define bM4_PORT_PCRC6_INTE (*((volatile unsigned int*)(0x42A79330UL))) +#define bM4_PORT_PCRC6_LTE (*((volatile unsigned int*)(0x42A79338UL))) +#define bM4_PORT_PCRC6_DDIS (*((volatile unsigned int*)(0x42A7933CUL))) +#define bM4_PORT_PFSRC6_FSEL0 (*((volatile unsigned int*)(0x42A79340UL))) +#define bM4_PORT_PFSRC6_FSEL1 (*((volatile unsigned int*)(0x42A79344UL))) +#define bM4_PORT_PFSRC6_FSEL2 (*((volatile unsigned int*)(0x42A79348UL))) +#define bM4_PORT_PFSRC6_FSEL3 (*((volatile unsigned int*)(0x42A7934CUL))) +#define bM4_PORT_PFSRC6_FSEL4 (*((volatile unsigned int*)(0x42A79350UL))) +#define bM4_PORT_PFSRC6_FSEL5 (*((volatile unsigned int*)(0x42A79354UL))) +#define bM4_PORT_PFSRC6_BFE (*((volatile unsigned int*)(0x42A79360UL))) +#define bM4_PORT_PCRC7_POUT (*((volatile unsigned int*)(0x42A79380UL))) +#define bM4_PORT_PCRC7_POUTE (*((volatile unsigned int*)(0x42A79384UL))) +#define bM4_PORT_PCRC7_NOD (*((volatile unsigned int*)(0x42A79388UL))) +#define bM4_PORT_PCRC7_DRV0 (*((volatile unsigned int*)(0x42A79390UL))) +#define bM4_PORT_PCRC7_DRV1 (*((volatile unsigned int*)(0x42A79394UL))) +#define bM4_PORT_PCRC7_PUU (*((volatile unsigned int*)(0x42A79398UL))) +#define bM4_PORT_PCRC7_PIN (*((volatile unsigned int*)(0x42A793A0UL))) +#define bM4_PORT_PCRC7_INVE (*((volatile unsigned int*)(0x42A793A4UL))) +#define bM4_PORT_PCRC7_INTE (*((volatile unsigned int*)(0x42A793B0UL))) +#define bM4_PORT_PCRC7_LTE (*((volatile unsigned int*)(0x42A793B8UL))) +#define bM4_PORT_PCRC7_DDIS (*((volatile unsigned int*)(0x42A793BCUL))) +#define bM4_PORT_PFSRC7_FSEL0 (*((volatile unsigned int*)(0x42A793C0UL))) +#define bM4_PORT_PFSRC7_FSEL1 (*((volatile unsigned int*)(0x42A793C4UL))) +#define bM4_PORT_PFSRC7_FSEL2 (*((volatile unsigned int*)(0x42A793C8UL))) +#define bM4_PORT_PFSRC7_FSEL3 (*((volatile unsigned int*)(0x42A793CCUL))) +#define bM4_PORT_PFSRC7_FSEL4 (*((volatile unsigned int*)(0x42A793D0UL))) +#define bM4_PORT_PFSRC7_FSEL5 (*((volatile unsigned int*)(0x42A793D4UL))) +#define bM4_PORT_PFSRC7_BFE (*((volatile unsigned int*)(0x42A793E0UL))) +#define bM4_PORT_PCRC8_POUT (*((volatile unsigned int*)(0x42A79400UL))) +#define bM4_PORT_PCRC8_POUTE (*((volatile unsigned int*)(0x42A79404UL))) +#define bM4_PORT_PCRC8_NOD (*((volatile unsigned int*)(0x42A79408UL))) +#define bM4_PORT_PCRC8_DRV0 (*((volatile unsigned int*)(0x42A79410UL))) +#define bM4_PORT_PCRC8_DRV1 (*((volatile unsigned int*)(0x42A79414UL))) +#define bM4_PORT_PCRC8_PUU (*((volatile unsigned int*)(0x42A79418UL))) +#define bM4_PORT_PCRC8_PIN (*((volatile unsigned int*)(0x42A79420UL))) +#define bM4_PORT_PCRC8_INVE (*((volatile unsigned int*)(0x42A79424UL))) +#define bM4_PORT_PCRC8_INTE (*((volatile unsigned int*)(0x42A79430UL))) +#define bM4_PORT_PCRC8_LTE (*((volatile unsigned int*)(0x42A79438UL))) +#define bM4_PORT_PCRC8_DDIS (*((volatile unsigned int*)(0x42A7943CUL))) +#define bM4_PORT_PFSRC8_FSEL0 (*((volatile unsigned int*)(0x42A79440UL))) +#define bM4_PORT_PFSRC8_FSEL1 (*((volatile unsigned int*)(0x42A79444UL))) +#define bM4_PORT_PFSRC8_FSEL2 (*((volatile unsigned int*)(0x42A79448UL))) +#define bM4_PORT_PFSRC8_FSEL3 (*((volatile unsigned int*)(0x42A7944CUL))) +#define bM4_PORT_PFSRC8_FSEL4 (*((volatile unsigned int*)(0x42A79450UL))) +#define bM4_PORT_PFSRC8_FSEL5 (*((volatile unsigned int*)(0x42A79454UL))) +#define bM4_PORT_PFSRC8_BFE (*((volatile unsigned int*)(0x42A79460UL))) +#define bM4_PORT_PCRC9_POUT (*((volatile unsigned int*)(0x42A79480UL))) +#define bM4_PORT_PCRC9_POUTE (*((volatile unsigned int*)(0x42A79484UL))) +#define bM4_PORT_PCRC9_NOD (*((volatile unsigned int*)(0x42A79488UL))) +#define bM4_PORT_PCRC9_DRV0 (*((volatile unsigned int*)(0x42A79490UL))) +#define bM4_PORT_PCRC9_DRV1 (*((volatile unsigned int*)(0x42A79494UL))) +#define bM4_PORT_PCRC9_PUU (*((volatile unsigned int*)(0x42A79498UL))) +#define bM4_PORT_PCRC9_PIN (*((volatile unsigned int*)(0x42A794A0UL))) +#define bM4_PORT_PCRC9_INVE (*((volatile unsigned int*)(0x42A794A4UL))) +#define bM4_PORT_PCRC9_INTE (*((volatile unsigned int*)(0x42A794B0UL))) +#define bM4_PORT_PCRC9_LTE (*((volatile unsigned int*)(0x42A794B8UL))) +#define bM4_PORT_PCRC9_DDIS (*((volatile unsigned int*)(0x42A794BCUL))) +#define bM4_PORT_PFSRC9_FSEL0 (*((volatile unsigned int*)(0x42A794C0UL))) +#define bM4_PORT_PFSRC9_FSEL1 (*((volatile unsigned int*)(0x42A794C4UL))) +#define bM4_PORT_PFSRC9_FSEL2 (*((volatile unsigned int*)(0x42A794C8UL))) +#define bM4_PORT_PFSRC9_FSEL3 (*((volatile unsigned int*)(0x42A794CCUL))) +#define bM4_PORT_PFSRC9_FSEL4 (*((volatile unsigned int*)(0x42A794D0UL))) +#define bM4_PORT_PFSRC9_FSEL5 (*((volatile unsigned int*)(0x42A794D4UL))) +#define bM4_PORT_PFSRC9_BFE (*((volatile unsigned int*)(0x42A794E0UL))) +#define bM4_PORT_PCRC10_POUT (*((volatile unsigned int*)(0x42A79500UL))) +#define bM4_PORT_PCRC10_POUTE (*((volatile unsigned int*)(0x42A79504UL))) +#define bM4_PORT_PCRC10_NOD (*((volatile unsigned int*)(0x42A79508UL))) +#define bM4_PORT_PCRC10_DRV0 (*((volatile unsigned int*)(0x42A79510UL))) +#define bM4_PORT_PCRC10_DRV1 (*((volatile unsigned int*)(0x42A79514UL))) +#define bM4_PORT_PCRC10_PUU (*((volatile unsigned int*)(0x42A79518UL))) +#define bM4_PORT_PCRC10_PIN (*((volatile unsigned int*)(0x42A79520UL))) +#define bM4_PORT_PCRC10_INVE (*((volatile unsigned int*)(0x42A79524UL))) +#define bM4_PORT_PCRC10_INTE (*((volatile unsigned int*)(0x42A79530UL))) +#define bM4_PORT_PCRC10_LTE (*((volatile unsigned int*)(0x42A79538UL))) +#define bM4_PORT_PCRC10_DDIS (*((volatile unsigned int*)(0x42A7953CUL))) +#define bM4_PORT_PFSRC10_FSEL0 (*((volatile unsigned int*)(0x42A79540UL))) +#define bM4_PORT_PFSRC10_FSEL1 (*((volatile unsigned int*)(0x42A79544UL))) +#define bM4_PORT_PFSRC10_FSEL2 (*((volatile unsigned int*)(0x42A79548UL))) +#define bM4_PORT_PFSRC10_FSEL3 (*((volatile unsigned int*)(0x42A7954CUL))) +#define bM4_PORT_PFSRC10_FSEL4 (*((volatile unsigned int*)(0x42A79550UL))) +#define bM4_PORT_PFSRC10_FSEL5 (*((volatile unsigned int*)(0x42A79554UL))) +#define bM4_PORT_PFSRC10_BFE (*((volatile unsigned int*)(0x42A79560UL))) +#define bM4_PORT_PCRC11_POUT (*((volatile unsigned int*)(0x42A79580UL))) +#define bM4_PORT_PCRC11_POUTE (*((volatile unsigned int*)(0x42A79584UL))) +#define bM4_PORT_PCRC11_NOD (*((volatile unsigned int*)(0x42A79588UL))) +#define bM4_PORT_PCRC11_DRV0 (*((volatile unsigned int*)(0x42A79590UL))) +#define bM4_PORT_PCRC11_DRV1 (*((volatile unsigned int*)(0x42A79594UL))) +#define bM4_PORT_PCRC11_PUU (*((volatile unsigned int*)(0x42A79598UL))) +#define bM4_PORT_PCRC11_PIN (*((volatile unsigned int*)(0x42A795A0UL))) +#define bM4_PORT_PCRC11_INVE (*((volatile unsigned int*)(0x42A795A4UL))) +#define bM4_PORT_PCRC11_INTE (*((volatile unsigned int*)(0x42A795B0UL))) +#define bM4_PORT_PCRC11_LTE (*((volatile unsigned int*)(0x42A795B8UL))) +#define bM4_PORT_PCRC11_DDIS (*((volatile unsigned int*)(0x42A795BCUL))) +#define bM4_PORT_PFSRC11_FSEL0 (*((volatile unsigned int*)(0x42A795C0UL))) +#define bM4_PORT_PFSRC11_FSEL1 (*((volatile unsigned int*)(0x42A795C4UL))) +#define bM4_PORT_PFSRC11_FSEL2 (*((volatile unsigned int*)(0x42A795C8UL))) +#define bM4_PORT_PFSRC11_FSEL3 (*((volatile unsigned int*)(0x42A795CCUL))) +#define bM4_PORT_PFSRC11_FSEL4 (*((volatile unsigned int*)(0x42A795D0UL))) +#define bM4_PORT_PFSRC11_FSEL5 (*((volatile unsigned int*)(0x42A795D4UL))) +#define bM4_PORT_PFSRC11_BFE (*((volatile unsigned int*)(0x42A795E0UL))) +#define bM4_PORT_PCRC12_POUT (*((volatile unsigned int*)(0x42A79600UL))) +#define bM4_PORT_PCRC12_POUTE (*((volatile unsigned int*)(0x42A79604UL))) +#define bM4_PORT_PCRC12_NOD (*((volatile unsigned int*)(0x42A79608UL))) +#define bM4_PORT_PCRC12_DRV0 (*((volatile unsigned int*)(0x42A79610UL))) +#define bM4_PORT_PCRC12_DRV1 (*((volatile unsigned int*)(0x42A79614UL))) +#define bM4_PORT_PCRC12_PUU (*((volatile unsigned int*)(0x42A79618UL))) +#define bM4_PORT_PCRC12_PIN (*((volatile unsigned int*)(0x42A79620UL))) +#define bM4_PORT_PCRC12_INVE (*((volatile unsigned int*)(0x42A79624UL))) +#define bM4_PORT_PCRC12_INTE (*((volatile unsigned int*)(0x42A79630UL))) +#define bM4_PORT_PCRC12_LTE (*((volatile unsigned int*)(0x42A79638UL))) +#define bM4_PORT_PCRC12_DDIS (*((volatile unsigned int*)(0x42A7963CUL))) +#define bM4_PORT_PFSRC12_FSEL0 (*((volatile unsigned int*)(0x42A79640UL))) +#define bM4_PORT_PFSRC12_FSEL1 (*((volatile unsigned int*)(0x42A79644UL))) +#define bM4_PORT_PFSRC12_FSEL2 (*((volatile unsigned int*)(0x42A79648UL))) +#define bM4_PORT_PFSRC12_FSEL3 (*((volatile unsigned int*)(0x42A7964CUL))) +#define bM4_PORT_PFSRC12_FSEL4 (*((volatile unsigned int*)(0x42A79650UL))) +#define bM4_PORT_PFSRC12_FSEL5 (*((volatile unsigned int*)(0x42A79654UL))) +#define bM4_PORT_PFSRC12_BFE (*((volatile unsigned int*)(0x42A79660UL))) +#define bM4_PORT_PCRC13_POUT (*((volatile unsigned int*)(0x42A79680UL))) +#define bM4_PORT_PCRC13_POUTE (*((volatile unsigned int*)(0x42A79684UL))) +#define bM4_PORT_PCRC13_NOD (*((volatile unsigned int*)(0x42A79688UL))) +#define bM4_PORT_PCRC13_DRV0 (*((volatile unsigned int*)(0x42A79690UL))) +#define bM4_PORT_PCRC13_DRV1 (*((volatile unsigned int*)(0x42A79694UL))) +#define bM4_PORT_PCRC13_PUU (*((volatile unsigned int*)(0x42A79698UL))) +#define bM4_PORT_PCRC13_PIN (*((volatile unsigned int*)(0x42A796A0UL))) +#define bM4_PORT_PCRC13_INVE (*((volatile unsigned int*)(0x42A796A4UL))) +#define bM4_PORT_PCRC13_INTE (*((volatile unsigned int*)(0x42A796B0UL))) +#define bM4_PORT_PCRC13_LTE (*((volatile unsigned int*)(0x42A796B8UL))) +#define bM4_PORT_PCRC13_DDIS (*((volatile unsigned int*)(0x42A796BCUL))) +#define bM4_PORT_PFSRC13_FSEL0 (*((volatile unsigned int*)(0x42A796C0UL))) +#define bM4_PORT_PFSRC13_FSEL1 (*((volatile unsigned int*)(0x42A796C4UL))) +#define bM4_PORT_PFSRC13_FSEL2 (*((volatile unsigned int*)(0x42A796C8UL))) +#define bM4_PORT_PFSRC13_FSEL3 (*((volatile unsigned int*)(0x42A796CCUL))) +#define bM4_PORT_PFSRC13_FSEL4 (*((volatile unsigned int*)(0x42A796D0UL))) +#define bM4_PORT_PFSRC13_FSEL5 (*((volatile unsigned int*)(0x42A796D4UL))) +#define bM4_PORT_PFSRC13_BFE (*((volatile unsigned int*)(0x42A796E0UL))) +#define bM4_PORT_PCRC14_POUT (*((volatile unsigned int*)(0x42A79700UL))) +#define bM4_PORT_PCRC14_POUTE (*((volatile unsigned int*)(0x42A79704UL))) +#define bM4_PORT_PCRC14_NOD (*((volatile unsigned int*)(0x42A79708UL))) +#define bM4_PORT_PCRC14_DRV0 (*((volatile unsigned int*)(0x42A79710UL))) +#define bM4_PORT_PCRC14_DRV1 (*((volatile unsigned int*)(0x42A79714UL))) +#define bM4_PORT_PCRC14_PUU (*((volatile unsigned int*)(0x42A79718UL))) +#define bM4_PORT_PCRC14_PIN (*((volatile unsigned int*)(0x42A79720UL))) +#define bM4_PORT_PCRC14_INVE (*((volatile unsigned int*)(0x42A79724UL))) +#define bM4_PORT_PCRC14_INTE (*((volatile unsigned int*)(0x42A79730UL))) +#define bM4_PORT_PCRC14_LTE (*((volatile unsigned int*)(0x42A79738UL))) +#define bM4_PORT_PCRC14_DDIS (*((volatile unsigned int*)(0x42A7973CUL))) +#define bM4_PORT_PFSRC14_FSEL0 (*((volatile unsigned int*)(0x42A79740UL))) +#define bM4_PORT_PFSRC14_FSEL1 (*((volatile unsigned int*)(0x42A79744UL))) +#define bM4_PORT_PFSRC14_FSEL2 (*((volatile unsigned int*)(0x42A79748UL))) +#define bM4_PORT_PFSRC14_FSEL3 (*((volatile unsigned int*)(0x42A7974CUL))) +#define bM4_PORT_PFSRC14_FSEL4 (*((volatile unsigned int*)(0x42A79750UL))) +#define bM4_PORT_PFSRC14_FSEL5 (*((volatile unsigned int*)(0x42A79754UL))) +#define bM4_PORT_PFSRC14_BFE (*((volatile unsigned int*)(0x42A79760UL))) +#define bM4_PORT_PCRC15_POUT (*((volatile unsigned int*)(0x42A79780UL))) +#define bM4_PORT_PCRC15_POUTE (*((volatile unsigned int*)(0x42A79784UL))) +#define bM4_PORT_PCRC15_NOD (*((volatile unsigned int*)(0x42A79788UL))) +#define bM4_PORT_PCRC15_DRV0 (*((volatile unsigned int*)(0x42A79790UL))) +#define bM4_PORT_PCRC15_DRV1 (*((volatile unsigned int*)(0x42A79794UL))) +#define bM4_PORT_PCRC15_PUU (*((volatile unsigned int*)(0x42A79798UL))) +#define bM4_PORT_PCRC15_PIN (*((volatile unsigned int*)(0x42A797A0UL))) +#define bM4_PORT_PCRC15_INVE (*((volatile unsigned int*)(0x42A797A4UL))) +#define bM4_PORT_PCRC15_INTE (*((volatile unsigned int*)(0x42A797B0UL))) +#define bM4_PORT_PCRC15_LTE (*((volatile unsigned int*)(0x42A797B8UL))) +#define bM4_PORT_PCRC15_DDIS (*((volatile unsigned int*)(0x42A797BCUL))) +#define bM4_PORT_PFSRC15_FSEL0 (*((volatile unsigned int*)(0x42A797C0UL))) +#define bM4_PORT_PFSRC15_FSEL1 (*((volatile unsigned int*)(0x42A797C4UL))) +#define bM4_PORT_PFSRC15_FSEL2 (*((volatile unsigned int*)(0x42A797C8UL))) +#define bM4_PORT_PFSRC15_FSEL3 (*((volatile unsigned int*)(0x42A797CCUL))) +#define bM4_PORT_PFSRC15_FSEL4 (*((volatile unsigned int*)(0x42A797D0UL))) +#define bM4_PORT_PFSRC15_FSEL5 (*((volatile unsigned int*)(0x42A797D4UL))) +#define bM4_PORT_PFSRC15_BFE (*((volatile unsigned int*)(0x42A797E0UL))) +#define bM4_PORT_PCRD0_POUT (*((volatile unsigned int*)(0x42A79800UL))) +#define bM4_PORT_PCRD0_POUTE (*((volatile unsigned int*)(0x42A79804UL))) +#define bM4_PORT_PCRD0_NOD (*((volatile unsigned int*)(0x42A79808UL))) +#define bM4_PORT_PCRD0_DRV0 (*((volatile unsigned int*)(0x42A79810UL))) +#define bM4_PORT_PCRD0_DRV1 (*((volatile unsigned int*)(0x42A79814UL))) +#define bM4_PORT_PCRD0_PUU (*((volatile unsigned int*)(0x42A79818UL))) +#define bM4_PORT_PCRD0_PIN (*((volatile unsigned int*)(0x42A79820UL))) +#define bM4_PORT_PCRD0_INVE (*((volatile unsigned int*)(0x42A79824UL))) +#define bM4_PORT_PCRD0_INTE (*((volatile unsigned int*)(0x42A79830UL))) +#define bM4_PORT_PCRD0_LTE (*((volatile unsigned int*)(0x42A79838UL))) +#define bM4_PORT_PCRD0_DDIS (*((volatile unsigned int*)(0x42A7983CUL))) +#define bM4_PORT_PFSRD0_FSEL0 (*((volatile unsigned int*)(0x42A79840UL))) +#define bM4_PORT_PFSRD0_FSEL1 (*((volatile unsigned int*)(0x42A79844UL))) +#define bM4_PORT_PFSRD0_FSEL2 (*((volatile unsigned int*)(0x42A79848UL))) +#define bM4_PORT_PFSRD0_FSEL3 (*((volatile unsigned int*)(0x42A7984CUL))) +#define bM4_PORT_PFSRD0_FSEL4 (*((volatile unsigned int*)(0x42A79850UL))) +#define bM4_PORT_PFSRD0_FSEL5 (*((volatile unsigned int*)(0x42A79854UL))) +#define bM4_PORT_PFSRD0_BFE (*((volatile unsigned int*)(0x42A79860UL))) +#define bM4_PORT_PCRD1_POUT (*((volatile unsigned int*)(0x42A79880UL))) +#define bM4_PORT_PCRD1_POUTE (*((volatile unsigned int*)(0x42A79884UL))) +#define bM4_PORT_PCRD1_NOD (*((volatile unsigned int*)(0x42A79888UL))) +#define bM4_PORT_PCRD1_DRV0 (*((volatile unsigned int*)(0x42A79890UL))) +#define bM4_PORT_PCRD1_DRV1 (*((volatile unsigned int*)(0x42A79894UL))) +#define bM4_PORT_PCRD1_PUU (*((volatile unsigned int*)(0x42A79898UL))) +#define bM4_PORT_PCRD1_PIN (*((volatile unsigned int*)(0x42A798A0UL))) +#define bM4_PORT_PCRD1_INVE (*((volatile unsigned int*)(0x42A798A4UL))) +#define bM4_PORT_PCRD1_INTE (*((volatile unsigned int*)(0x42A798B0UL))) +#define bM4_PORT_PCRD1_LTE (*((volatile unsigned int*)(0x42A798B8UL))) +#define bM4_PORT_PCRD1_DDIS (*((volatile unsigned int*)(0x42A798BCUL))) +#define bM4_PORT_PFSRD1_FSEL0 (*((volatile unsigned int*)(0x42A798C0UL))) +#define bM4_PORT_PFSRD1_FSEL1 (*((volatile unsigned int*)(0x42A798C4UL))) +#define bM4_PORT_PFSRD1_FSEL2 (*((volatile unsigned int*)(0x42A798C8UL))) +#define bM4_PORT_PFSRD1_FSEL3 (*((volatile unsigned int*)(0x42A798CCUL))) +#define bM4_PORT_PFSRD1_FSEL4 (*((volatile unsigned int*)(0x42A798D0UL))) +#define bM4_PORT_PFSRD1_FSEL5 (*((volatile unsigned int*)(0x42A798D4UL))) +#define bM4_PORT_PFSRD1_BFE (*((volatile unsigned int*)(0x42A798E0UL))) +#define bM4_PORT_PCRD2_POUT (*((volatile unsigned int*)(0x42A79900UL))) +#define bM4_PORT_PCRD2_POUTE (*((volatile unsigned int*)(0x42A79904UL))) +#define bM4_PORT_PCRD2_NOD (*((volatile unsigned int*)(0x42A79908UL))) +#define bM4_PORT_PCRD2_DRV0 (*((volatile unsigned int*)(0x42A79910UL))) +#define bM4_PORT_PCRD2_DRV1 (*((volatile unsigned int*)(0x42A79914UL))) +#define bM4_PORT_PCRD2_PUU (*((volatile unsigned int*)(0x42A79918UL))) +#define bM4_PORT_PCRD2_PIN (*((volatile unsigned int*)(0x42A79920UL))) +#define bM4_PORT_PCRD2_INVE (*((volatile unsigned int*)(0x42A79924UL))) +#define bM4_PORT_PCRD2_INTE (*((volatile unsigned int*)(0x42A79930UL))) +#define bM4_PORT_PCRD2_LTE (*((volatile unsigned int*)(0x42A79938UL))) +#define bM4_PORT_PCRD2_DDIS (*((volatile unsigned int*)(0x42A7993CUL))) +#define bM4_PORT_PFSRD2_FSEL0 (*((volatile unsigned int*)(0x42A79940UL))) +#define bM4_PORT_PFSRD2_FSEL1 (*((volatile unsigned int*)(0x42A79944UL))) +#define bM4_PORT_PFSRD2_FSEL2 (*((volatile unsigned int*)(0x42A79948UL))) +#define bM4_PORT_PFSRD2_FSEL3 (*((volatile unsigned int*)(0x42A7994CUL))) +#define bM4_PORT_PFSRD2_FSEL4 (*((volatile unsigned int*)(0x42A79950UL))) +#define bM4_PORT_PFSRD2_FSEL5 (*((volatile unsigned int*)(0x42A79954UL))) +#define bM4_PORT_PFSRD2_BFE (*((volatile unsigned int*)(0x42A79960UL))) +#define bM4_PORT_PCRD3_POUT (*((volatile unsigned int*)(0x42A79980UL))) +#define bM4_PORT_PCRD3_POUTE (*((volatile unsigned int*)(0x42A79984UL))) +#define bM4_PORT_PCRD3_NOD (*((volatile unsigned int*)(0x42A79988UL))) +#define bM4_PORT_PCRD3_DRV0 (*((volatile unsigned int*)(0x42A79990UL))) +#define bM4_PORT_PCRD3_DRV1 (*((volatile unsigned int*)(0x42A79994UL))) +#define bM4_PORT_PCRD3_PUU (*((volatile unsigned int*)(0x42A79998UL))) +#define bM4_PORT_PCRD3_PIN (*((volatile unsigned int*)(0x42A799A0UL))) +#define bM4_PORT_PCRD3_INVE (*((volatile unsigned int*)(0x42A799A4UL))) +#define bM4_PORT_PCRD3_INTE (*((volatile unsigned int*)(0x42A799B0UL))) +#define bM4_PORT_PCRD3_LTE (*((volatile unsigned int*)(0x42A799B8UL))) +#define bM4_PORT_PCRD3_DDIS (*((volatile unsigned int*)(0x42A799BCUL))) +#define bM4_PORT_PFSRD3_FSEL0 (*((volatile unsigned int*)(0x42A799C0UL))) +#define bM4_PORT_PFSRD3_FSEL1 (*((volatile unsigned int*)(0x42A799C4UL))) +#define bM4_PORT_PFSRD3_FSEL2 (*((volatile unsigned int*)(0x42A799C8UL))) +#define bM4_PORT_PFSRD3_FSEL3 (*((volatile unsigned int*)(0x42A799CCUL))) +#define bM4_PORT_PFSRD3_FSEL4 (*((volatile unsigned int*)(0x42A799D0UL))) +#define bM4_PORT_PFSRD3_FSEL5 (*((volatile unsigned int*)(0x42A799D4UL))) +#define bM4_PORT_PFSRD3_BFE (*((volatile unsigned int*)(0x42A799E0UL))) +#define bM4_PORT_PCRD4_POUT (*((volatile unsigned int*)(0x42A79A00UL))) +#define bM4_PORT_PCRD4_POUTE (*((volatile unsigned int*)(0x42A79A04UL))) +#define bM4_PORT_PCRD4_NOD (*((volatile unsigned int*)(0x42A79A08UL))) +#define bM4_PORT_PCRD4_DRV0 (*((volatile unsigned int*)(0x42A79A10UL))) +#define bM4_PORT_PCRD4_DRV1 (*((volatile unsigned int*)(0x42A79A14UL))) +#define bM4_PORT_PCRD4_PUU (*((volatile unsigned int*)(0x42A79A18UL))) +#define bM4_PORT_PCRD4_PIN (*((volatile unsigned int*)(0x42A79A20UL))) +#define bM4_PORT_PCRD4_INVE (*((volatile unsigned int*)(0x42A79A24UL))) +#define bM4_PORT_PCRD4_INTE (*((volatile unsigned int*)(0x42A79A30UL))) +#define bM4_PORT_PCRD4_LTE (*((volatile unsigned int*)(0x42A79A38UL))) +#define bM4_PORT_PCRD4_DDIS (*((volatile unsigned int*)(0x42A79A3CUL))) +#define bM4_PORT_PFSRD4_FSEL0 (*((volatile unsigned int*)(0x42A79A40UL))) +#define bM4_PORT_PFSRD4_FSEL1 (*((volatile unsigned int*)(0x42A79A44UL))) +#define bM4_PORT_PFSRD4_FSEL2 (*((volatile unsigned int*)(0x42A79A48UL))) +#define bM4_PORT_PFSRD4_FSEL3 (*((volatile unsigned int*)(0x42A79A4CUL))) +#define bM4_PORT_PFSRD4_FSEL4 (*((volatile unsigned int*)(0x42A79A50UL))) +#define bM4_PORT_PFSRD4_FSEL5 (*((volatile unsigned int*)(0x42A79A54UL))) +#define bM4_PORT_PFSRD4_BFE (*((volatile unsigned int*)(0x42A79A60UL))) +#define bM4_PORT_PCRD5_POUT (*((volatile unsigned int*)(0x42A79A80UL))) +#define bM4_PORT_PCRD5_POUTE (*((volatile unsigned int*)(0x42A79A84UL))) +#define bM4_PORT_PCRD5_NOD (*((volatile unsigned int*)(0x42A79A88UL))) +#define bM4_PORT_PCRD5_DRV0 (*((volatile unsigned int*)(0x42A79A90UL))) +#define bM4_PORT_PCRD5_DRV1 (*((volatile unsigned int*)(0x42A79A94UL))) +#define bM4_PORT_PCRD5_PUU (*((volatile unsigned int*)(0x42A79A98UL))) +#define bM4_PORT_PCRD5_PIN (*((volatile unsigned int*)(0x42A79AA0UL))) +#define bM4_PORT_PCRD5_INVE (*((volatile unsigned int*)(0x42A79AA4UL))) +#define bM4_PORT_PCRD5_INTE (*((volatile unsigned int*)(0x42A79AB0UL))) +#define bM4_PORT_PCRD5_LTE (*((volatile unsigned int*)(0x42A79AB8UL))) +#define bM4_PORT_PCRD5_DDIS (*((volatile unsigned int*)(0x42A79ABCUL))) +#define bM4_PORT_PFSRD5_FSEL0 (*((volatile unsigned int*)(0x42A79AC0UL))) +#define bM4_PORT_PFSRD5_FSEL1 (*((volatile unsigned int*)(0x42A79AC4UL))) +#define bM4_PORT_PFSRD5_FSEL2 (*((volatile unsigned int*)(0x42A79AC8UL))) +#define bM4_PORT_PFSRD5_FSEL3 (*((volatile unsigned int*)(0x42A79ACCUL))) +#define bM4_PORT_PFSRD5_FSEL4 (*((volatile unsigned int*)(0x42A79AD0UL))) +#define bM4_PORT_PFSRD5_FSEL5 (*((volatile unsigned int*)(0x42A79AD4UL))) +#define bM4_PORT_PFSRD5_BFE (*((volatile unsigned int*)(0x42A79AE0UL))) +#define bM4_PORT_PCRD6_POUT (*((volatile unsigned int*)(0x42A79B00UL))) +#define bM4_PORT_PCRD6_POUTE (*((volatile unsigned int*)(0x42A79B04UL))) +#define bM4_PORT_PCRD6_NOD (*((volatile unsigned int*)(0x42A79B08UL))) +#define bM4_PORT_PCRD6_DRV0 (*((volatile unsigned int*)(0x42A79B10UL))) +#define bM4_PORT_PCRD6_DRV1 (*((volatile unsigned int*)(0x42A79B14UL))) +#define bM4_PORT_PCRD6_PUU (*((volatile unsigned int*)(0x42A79B18UL))) +#define bM4_PORT_PCRD6_PIN (*((volatile unsigned int*)(0x42A79B20UL))) +#define bM4_PORT_PCRD6_INVE (*((volatile unsigned int*)(0x42A79B24UL))) +#define bM4_PORT_PCRD6_INTE (*((volatile unsigned int*)(0x42A79B30UL))) +#define bM4_PORT_PCRD6_LTE (*((volatile unsigned int*)(0x42A79B38UL))) +#define bM4_PORT_PCRD6_DDIS (*((volatile unsigned int*)(0x42A79B3CUL))) +#define bM4_PORT_PFSRD6_FSEL0 (*((volatile unsigned int*)(0x42A79B40UL))) +#define bM4_PORT_PFSRD6_FSEL1 (*((volatile unsigned int*)(0x42A79B44UL))) +#define bM4_PORT_PFSRD6_FSEL2 (*((volatile unsigned int*)(0x42A79B48UL))) +#define bM4_PORT_PFSRD6_FSEL3 (*((volatile unsigned int*)(0x42A79B4CUL))) +#define bM4_PORT_PFSRD6_FSEL4 (*((volatile unsigned int*)(0x42A79B50UL))) +#define bM4_PORT_PFSRD6_FSEL5 (*((volatile unsigned int*)(0x42A79B54UL))) +#define bM4_PORT_PFSRD6_BFE (*((volatile unsigned int*)(0x42A79B60UL))) +#define bM4_PORT_PCRD7_POUT (*((volatile unsigned int*)(0x42A79B80UL))) +#define bM4_PORT_PCRD7_POUTE (*((volatile unsigned int*)(0x42A79B84UL))) +#define bM4_PORT_PCRD7_NOD (*((volatile unsigned int*)(0x42A79B88UL))) +#define bM4_PORT_PCRD7_DRV0 (*((volatile unsigned int*)(0x42A79B90UL))) +#define bM4_PORT_PCRD7_DRV1 (*((volatile unsigned int*)(0x42A79B94UL))) +#define bM4_PORT_PCRD7_PUU (*((volatile unsigned int*)(0x42A79B98UL))) +#define bM4_PORT_PCRD7_PIN (*((volatile unsigned int*)(0x42A79BA0UL))) +#define bM4_PORT_PCRD7_INVE (*((volatile unsigned int*)(0x42A79BA4UL))) +#define bM4_PORT_PCRD7_INTE (*((volatile unsigned int*)(0x42A79BB0UL))) +#define bM4_PORT_PCRD7_LTE (*((volatile unsigned int*)(0x42A79BB8UL))) +#define bM4_PORT_PCRD7_DDIS (*((volatile unsigned int*)(0x42A79BBCUL))) +#define bM4_PORT_PFSRD7_FSEL0 (*((volatile unsigned int*)(0x42A79BC0UL))) +#define bM4_PORT_PFSRD7_FSEL1 (*((volatile unsigned int*)(0x42A79BC4UL))) +#define bM4_PORT_PFSRD7_FSEL2 (*((volatile unsigned int*)(0x42A79BC8UL))) +#define bM4_PORT_PFSRD7_FSEL3 (*((volatile unsigned int*)(0x42A79BCCUL))) +#define bM4_PORT_PFSRD7_FSEL4 (*((volatile unsigned int*)(0x42A79BD0UL))) +#define bM4_PORT_PFSRD7_FSEL5 (*((volatile unsigned int*)(0x42A79BD4UL))) +#define bM4_PORT_PFSRD7_BFE (*((volatile unsigned int*)(0x42A79BE0UL))) +#define bM4_PORT_PCRD8_POUT (*((volatile unsigned int*)(0x42A79C00UL))) +#define bM4_PORT_PCRD8_POUTE (*((volatile unsigned int*)(0x42A79C04UL))) +#define bM4_PORT_PCRD8_NOD (*((volatile unsigned int*)(0x42A79C08UL))) +#define bM4_PORT_PCRD8_DRV0 (*((volatile unsigned int*)(0x42A79C10UL))) +#define bM4_PORT_PCRD8_DRV1 (*((volatile unsigned int*)(0x42A79C14UL))) +#define bM4_PORT_PCRD8_PUU (*((volatile unsigned int*)(0x42A79C18UL))) +#define bM4_PORT_PCRD8_PIN (*((volatile unsigned int*)(0x42A79C20UL))) +#define bM4_PORT_PCRD8_INVE (*((volatile unsigned int*)(0x42A79C24UL))) +#define bM4_PORT_PCRD8_INTE (*((volatile unsigned int*)(0x42A79C30UL))) +#define bM4_PORT_PCRD8_LTE (*((volatile unsigned int*)(0x42A79C38UL))) +#define bM4_PORT_PCRD8_DDIS (*((volatile unsigned int*)(0x42A79C3CUL))) +#define bM4_PORT_PFSRD8_FSEL0 (*((volatile unsigned int*)(0x42A79C40UL))) +#define bM4_PORT_PFSRD8_FSEL1 (*((volatile unsigned int*)(0x42A79C44UL))) +#define bM4_PORT_PFSRD8_FSEL2 (*((volatile unsigned int*)(0x42A79C48UL))) +#define bM4_PORT_PFSRD8_FSEL3 (*((volatile unsigned int*)(0x42A79C4CUL))) +#define bM4_PORT_PFSRD8_FSEL4 (*((volatile unsigned int*)(0x42A79C50UL))) +#define bM4_PORT_PFSRD8_FSEL5 (*((volatile unsigned int*)(0x42A79C54UL))) +#define bM4_PORT_PFSRD8_BFE (*((volatile unsigned int*)(0x42A79C60UL))) +#define bM4_PORT_PCRD9_POUT (*((volatile unsigned int*)(0x42A79C80UL))) +#define bM4_PORT_PCRD9_POUTE (*((volatile unsigned int*)(0x42A79C84UL))) +#define bM4_PORT_PCRD9_NOD (*((volatile unsigned int*)(0x42A79C88UL))) +#define bM4_PORT_PCRD9_DRV0 (*((volatile unsigned int*)(0x42A79C90UL))) +#define bM4_PORT_PCRD9_DRV1 (*((volatile unsigned int*)(0x42A79C94UL))) +#define bM4_PORT_PCRD9_PUU (*((volatile unsigned int*)(0x42A79C98UL))) +#define bM4_PORT_PCRD9_PIN (*((volatile unsigned int*)(0x42A79CA0UL))) +#define bM4_PORT_PCRD9_INVE (*((volatile unsigned int*)(0x42A79CA4UL))) +#define bM4_PORT_PCRD9_INTE (*((volatile unsigned int*)(0x42A79CB0UL))) +#define bM4_PORT_PCRD9_LTE (*((volatile unsigned int*)(0x42A79CB8UL))) +#define bM4_PORT_PCRD9_DDIS (*((volatile unsigned int*)(0x42A79CBCUL))) +#define bM4_PORT_PFSRD9_FSEL0 (*((volatile unsigned int*)(0x42A79CC0UL))) +#define bM4_PORT_PFSRD9_FSEL1 (*((volatile unsigned int*)(0x42A79CC4UL))) +#define bM4_PORT_PFSRD9_FSEL2 (*((volatile unsigned int*)(0x42A79CC8UL))) +#define bM4_PORT_PFSRD9_FSEL3 (*((volatile unsigned int*)(0x42A79CCCUL))) +#define bM4_PORT_PFSRD9_FSEL4 (*((volatile unsigned int*)(0x42A79CD0UL))) +#define bM4_PORT_PFSRD9_FSEL5 (*((volatile unsigned int*)(0x42A79CD4UL))) +#define bM4_PORT_PFSRD9_BFE (*((volatile unsigned int*)(0x42A79CE0UL))) +#define bM4_PORT_PCRD10_POUT (*((volatile unsigned int*)(0x42A79D00UL))) +#define bM4_PORT_PCRD10_POUTE (*((volatile unsigned int*)(0x42A79D04UL))) +#define bM4_PORT_PCRD10_NOD (*((volatile unsigned int*)(0x42A79D08UL))) +#define bM4_PORT_PCRD10_DRV0 (*((volatile unsigned int*)(0x42A79D10UL))) +#define bM4_PORT_PCRD10_DRV1 (*((volatile unsigned int*)(0x42A79D14UL))) +#define bM4_PORT_PCRD10_PUU (*((volatile unsigned int*)(0x42A79D18UL))) +#define bM4_PORT_PCRD10_PIN (*((volatile unsigned int*)(0x42A79D20UL))) +#define bM4_PORT_PCRD10_INVE (*((volatile unsigned int*)(0x42A79D24UL))) +#define bM4_PORT_PCRD10_INTE (*((volatile unsigned int*)(0x42A79D30UL))) +#define bM4_PORT_PCRD10_LTE (*((volatile unsigned int*)(0x42A79D38UL))) +#define bM4_PORT_PCRD10_DDIS (*((volatile unsigned int*)(0x42A79D3CUL))) +#define bM4_PORT_PFSRD10_FSEL0 (*((volatile unsigned int*)(0x42A79D40UL))) +#define bM4_PORT_PFSRD10_FSEL1 (*((volatile unsigned int*)(0x42A79D44UL))) +#define bM4_PORT_PFSRD10_FSEL2 (*((volatile unsigned int*)(0x42A79D48UL))) +#define bM4_PORT_PFSRD10_FSEL3 (*((volatile unsigned int*)(0x42A79D4CUL))) +#define bM4_PORT_PFSRD10_FSEL4 (*((volatile unsigned int*)(0x42A79D50UL))) +#define bM4_PORT_PFSRD10_FSEL5 (*((volatile unsigned int*)(0x42A79D54UL))) +#define bM4_PORT_PFSRD10_BFE (*((volatile unsigned int*)(0x42A79D60UL))) +#define bM4_PORT_PCRD11_POUT (*((volatile unsigned int*)(0x42A79D80UL))) +#define bM4_PORT_PCRD11_POUTE (*((volatile unsigned int*)(0x42A79D84UL))) +#define bM4_PORT_PCRD11_NOD (*((volatile unsigned int*)(0x42A79D88UL))) +#define bM4_PORT_PCRD11_DRV0 (*((volatile unsigned int*)(0x42A79D90UL))) +#define bM4_PORT_PCRD11_DRV1 (*((volatile unsigned int*)(0x42A79D94UL))) +#define bM4_PORT_PCRD11_PUU (*((volatile unsigned int*)(0x42A79D98UL))) +#define bM4_PORT_PCRD11_PIN (*((volatile unsigned int*)(0x42A79DA0UL))) +#define bM4_PORT_PCRD11_INVE (*((volatile unsigned int*)(0x42A79DA4UL))) +#define bM4_PORT_PCRD11_INTE (*((volatile unsigned int*)(0x42A79DB0UL))) +#define bM4_PORT_PCRD11_LTE (*((volatile unsigned int*)(0x42A79DB8UL))) +#define bM4_PORT_PCRD11_DDIS (*((volatile unsigned int*)(0x42A79DBCUL))) +#define bM4_PORT_PFSRD11_FSEL0 (*((volatile unsigned int*)(0x42A79DC0UL))) +#define bM4_PORT_PFSRD11_FSEL1 (*((volatile unsigned int*)(0x42A79DC4UL))) +#define bM4_PORT_PFSRD11_FSEL2 (*((volatile unsigned int*)(0x42A79DC8UL))) +#define bM4_PORT_PFSRD11_FSEL3 (*((volatile unsigned int*)(0x42A79DCCUL))) +#define bM4_PORT_PFSRD11_FSEL4 (*((volatile unsigned int*)(0x42A79DD0UL))) +#define bM4_PORT_PFSRD11_FSEL5 (*((volatile unsigned int*)(0x42A79DD4UL))) +#define bM4_PORT_PFSRD11_BFE (*((volatile unsigned int*)(0x42A79DE0UL))) +#define bM4_PORT_PCRD12_POUT (*((volatile unsigned int*)(0x42A79E00UL))) +#define bM4_PORT_PCRD12_POUTE (*((volatile unsigned int*)(0x42A79E04UL))) +#define bM4_PORT_PCRD12_NOD (*((volatile unsigned int*)(0x42A79E08UL))) +#define bM4_PORT_PCRD12_DRV0 (*((volatile unsigned int*)(0x42A79E10UL))) +#define bM4_PORT_PCRD12_DRV1 (*((volatile unsigned int*)(0x42A79E14UL))) +#define bM4_PORT_PCRD12_PUU (*((volatile unsigned int*)(0x42A79E18UL))) +#define bM4_PORT_PCRD12_PIN (*((volatile unsigned int*)(0x42A79E20UL))) +#define bM4_PORT_PCRD12_INVE (*((volatile unsigned int*)(0x42A79E24UL))) +#define bM4_PORT_PCRD12_INTE (*((volatile unsigned int*)(0x42A79E30UL))) +#define bM4_PORT_PCRD12_LTE (*((volatile unsigned int*)(0x42A79E38UL))) +#define bM4_PORT_PCRD12_DDIS (*((volatile unsigned int*)(0x42A79E3CUL))) +#define bM4_PORT_PFSRD12_FSEL0 (*((volatile unsigned int*)(0x42A79E40UL))) +#define bM4_PORT_PFSRD12_FSEL1 (*((volatile unsigned int*)(0x42A79E44UL))) +#define bM4_PORT_PFSRD12_FSEL2 (*((volatile unsigned int*)(0x42A79E48UL))) +#define bM4_PORT_PFSRD12_FSEL3 (*((volatile unsigned int*)(0x42A79E4CUL))) +#define bM4_PORT_PFSRD12_FSEL4 (*((volatile unsigned int*)(0x42A79E50UL))) +#define bM4_PORT_PFSRD12_FSEL5 (*((volatile unsigned int*)(0x42A79E54UL))) +#define bM4_PORT_PFSRD12_BFE (*((volatile unsigned int*)(0x42A79E60UL))) +#define bM4_PORT_PCRD13_POUT (*((volatile unsigned int*)(0x42A79E80UL))) +#define bM4_PORT_PCRD13_POUTE (*((volatile unsigned int*)(0x42A79E84UL))) +#define bM4_PORT_PCRD13_NOD (*((volatile unsigned int*)(0x42A79E88UL))) +#define bM4_PORT_PCRD13_DRV0 (*((volatile unsigned int*)(0x42A79E90UL))) +#define bM4_PORT_PCRD13_DRV1 (*((volatile unsigned int*)(0x42A79E94UL))) +#define bM4_PORT_PCRD13_PUU (*((volatile unsigned int*)(0x42A79E98UL))) +#define bM4_PORT_PCRD13_PIN (*((volatile unsigned int*)(0x42A79EA0UL))) +#define bM4_PORT_PCRD13_INVE (*((volatile unsigned int*)(0x42A79EA4UL))) +#define bM4_PORT_PCRD13_INTE (*((volatile unsigned int*)(0x42A79EB0UL))) +#define bM4_PORT_PCRD13_LTE (*((volatile unsigned int*)(0x42A79EB8UL))) +#define bM4_PORT_PCRD13_DDIS (*((volatile unsigned int*)(0x42A79EBCUL))) +#define bM4_PORT_PFSRD13_FSEL0 (*((volatile unsigned int*)(0x42A79EC0UL))) +#define bM4_PORT_PFSRD13_FSEL1 (*((volatile unsigned int*)(0x42A79EC4UL))) +#define bM4_PORT_PFSRD13_FSEL2 (*((volatile unsigned int*)(0x42A79EC8UL))) +#define bM4_PORT_PFSRD13_FSEL3 (*((volatile unsigned int*)(0x42A79ECCUL))) +#define bM4_PORT_PFSRD13_FSEL4 (*((volatile unsigned int*)(0x42A79ED0UL))) +#define bM4_PORT_PFSRD13_FSEL5 (*((volatile unsigned int*)(0x42A79ED4UL))) +#define bM4_PORT_PFSRD13_BFE (*((volatile unsigned int*)(0x42A79EE0UL))) +#define bM4_PORT_PCRD14_POUT (*((volatile unsigned int*)(0x42A79F00UL))) +#define bM4_PORT_PCRD14_POUTE (*((volatile unsigned int*)(0x42A79F04UL))) +#define bM4_PORT_PCRD14_NOD (*((volatile unsigned int*)(0x42A79F08UL))) +#define bM4_PORT_PCRD14_DRV0 (*((volatile unsigned int*)(0x42A79F10UL))) +#define bM4_PORT_PCRD14_DRV1 (*((volatile unsigned int*)(0x42A79F14UL))) +#define bM4_PORT_PCRD14_PUU (*((volatile unsigned int*)(0x42A79F18UL))) +#define bM4_PORT_PCRD14_PIN (*((volatile unsigned int*)(0x42A79F20UL))) +#define bM4_PORT_PCRD14_INVE (*((volatile unsigned int*)(0x42A79F24UL))) +#define bM4_PORT_PCRD14_INTE (*((volatile unsigned int*)(0x42A79F30UL))) +#define bM4_PORT_PCRD14_LTE (*((volatile unsigned int*)(0x42A79F38UL))) +#define bM4_PORT_PCRD14_DDIS (*((volatile unsigned int*)(0x42A79F3CUL))) +#define bM4_PORT_PFSRD14_FSEL0 (*((volatile unsigned int*)(0x42A79F40UL))) +#define bM4_PORT_PFSRD14_FSEL1 (*((volatile unsigned int*)(0x42A79F44UL))) +#define bM4_PORT_PFSRD14_FSEL2 (*((volatile unsigned int*)(0x42A79F48UL))) +#define bM4_PORT_PFSRD14_FSEL3 (*((volatile unsigned int*)(0x42A79F4CUL))) +#define bM4_PORT_PFSRD14_FSEL4 (*((volatile unsigned int*)(0x42A79F50UL))) +#define bM4_PORT_PFSRD14_FSEL5 (*((volatile unsigned int*)(0x42A79F54UL))) +#define bM4_PORT_PFSRD14_BFE (*((volatile unsigned int*)(0x42A79F60UL))) +#define bM4_PORT_PCRD15_POUT (*((volatile unsigned int*)(0x42A79F80UL))) +#define bM4_PORT_PCRD15_POUTE (*((volatile unsigned int*)(0x42A79F84UL))) +#define bM4_PORT_PCRD15_NOD (*((volatile unsigned int*)(0x42A79F88UL))) +#define bM4_PORT_PCRD15_DRV0 (*((volatile unsigned int*)(0x42A79F90UL))) +#define bM4_PORT_PCRD15_DRV1 (*((volatile unsigned int*)(0x42A79F94UL))) +#define bM4_PORT_PCRD15_PUU (*((volatile unsigned int*)(0x42A79F98UL))) +#define bM4_PORT_PCRD15_PIN (*((volatile unsigned int*)(0x42A79FA0UL))) +#define bM4_PORT_PCRD15_INVE (*((volatile unsigned int*)(0x42A79FA4UL))) +#define bM4_PORT_PCRD15_INTE (*((volatile unsigned int*)(0x42A79FB0UL))) +#define bM4_PORT_PCRD15_LTE (*((volatile unsigned int*)(0x42A79FB8UL))) +#define bM4_PORT_PCRD15_DDIS (*((volatile unsigned int*)(0x42A79FBCUL))) +#define bM4_PORT_PFSRD15_FSEL0 (*((volatile unsigned int*)(0x42A79FC0UL))) +#define bM4_PORT_PFSRD15_FSEL1 (*((volatile unsigned int*)(0x42A79FC4UL))) +#define bM4_PORT_PFSRD15_FSEL2 (*((volatile unsigned int*)(0x42A79FC8UL))) +#define bM4_PORT_PFSRD15_FSEL3 (*((volatile unsigned int*)(0x42A79FCCUL))) +#define bM4_PORT_PFSRD15_FSEL4 (*((volatile unsigned int*)(0x42A79FD0UL))) +#define bM4_PORT_PFSRD15_FSEL5 (*((volatile unsigned int*)(0x42A79FD4UL))) +#define bM4_PORT_PFSRD15_BFE (*((volatile unsigned int*)(0x42A79FE0UL))) +#define bM4_PORT_PCRE0_POUT (*((volatile unsigned int*)(0x42A7A000UL))) +#define bM4_PORT_PCRE0_POUTE (*((volatile unsigned int*)(0x42A7A004UL))) +#define bM4_PORT_PCRE0_NOD (*((volatile unsigned int*)(0x42A7A008UL))) +#define bM4_PORT_PCRE0_DRV0 (*((volatile unsigned int*)(0x42A7A010UL))) +#define bM4_PORT_PCRE0_DRV1 (*((volatile unsigned int*)(0x42A7A014UL))) +#define bM4_PORT_PCRE0_PUU (*((volatile unsigned int*)(0x42A7A018UL))) +#define bM4_PORT_PCRE0_PIN (*((volatile unsigned int*)(0x42A7A020UL))) +#define bM4_PORT_PCRE0_INVE (*((volatile unsigned int*)(0x42A7A024UL))) +#define bM4_PORT_PCRE0_INTE (*((volatile unsigned int*)(0x42A7A030UL))) +#define bM4_PORT_PCRE0_LTE (*((volatile unsigned int*)(0x42A7A038UL))) +#define bM4_PORT_PCRE0_DDIS (*((volatile unsigned int*)(0x42A7A03CUL))) +#define bM4_PORT_PFSRE0_FSEL0 (*((volatile unsigned int*)(0x42A7A040UL))) +#define bM4_PORT_PFSRE0_FSEL1 (*((volatile unsigned int*)(0x42A7A044UL))) +#define bM4_PORT_PFSRE0_FSEL2 (*((volatile unsigned int*)(0x42A7A048UL))) +#define bM4_PORT_PFSRE0_FSEL3 (*((volatile unsigned int*)(0x42A7A04CUL))) +#define bM4_PORT_PFSRE0_FSEL4 (*((volatile unsigned int*)(0x42A7A050UL))) +#define bM4_PORT_PFSRE0_FSEL5 (*((volatile unsigned int*)(0x42A7A054UL))) +#define bM4_PORT_PFSRE0_BFE (*((volatile unsigned int*)(0x42A7A060UL))) +#define bM4_PORT_PCRE1_POUT (*((volatile unsigned int*)(0x42A7A080UL))) +#define bM4_PORT_PCRE1_POUTE (*((volatile unsigned int*)(0x42A7A084UL))) +#define bM4_PORT_PCRE1_NOD (*((volatile unsigned int*)(0x42A7A088UL))) +#define bM4_PORT_PCRE1_DRV0 (*((volatile unsigned int*)(0x42A7A090UL))) +#define bM4_PORT_PCRE1_DRV1 (*((volatile unsigned int*)(0x42A7A094UL))) +#define bM4_PORT_PCRE1_PUU (*((volatile unsigned int*)(0x42A7A098UL))) +#define bM4_PORT_PCRE1_PIN (*((volatile unsigned int*)(0x42A7A0A0UL))) +#define bM4_PORT_PCRE1_INVE (*((volatile unsigned int*)(0x42A7A0A4UL))) +#define bM4_PORT_PCRE1_INTE (*((volatile unsigned int*)(0x42A7A0B0UL))) +#define bM4_PORT_PCRE1_LTE (*((volatile unsigned int*)(0x42A7A0B8UL))) +#define bM4_PORT_PCRE1_DDIS (*((volatile unsigned int*)(0x42A7A0BCUL))) +#define bM4_PORT_PFSRE1_FSEL0 (*((volatile unsigned int*)(0x42A7A0C0UL))) +#define bM4_PORT_PFSRE1_FSEL1 (*((volatile unsigned int*)(0x42A7A0C4UL))) +#define bM4_PORT_PFSRE1_FSEL2 (*((volatile unsigned int*)(0x42A7A0C8UL))) +#define bM4_PORT_PFSRE1_FSEL3 (*((volatile unsigned int*)(0x42A7A0CCUL))) +#define bM4_PORT_PFSRE1_FSEL4 (*((volatile unsigned int*)(0x42A7A0D0UL))) +#define bM4_PORT_PFSRE1_FSEL5 (*((volatile unsigned int*)(0x42A7A0D4UL))) +#define bM4_PORT_PFSRE1_BFE (*((volatile unsigned int*)(0x42A7A0E0UL))) +#define bM4_PORT_PCRE2_POUT (*((volatile unsigned int*)(0x42A7A100UL))) +#define bM4_PORT_PCRE2_POUTE (*((volatile unsigned int*)(0x42A7A104UL))) +#define bM4_PORT_PCRE2_NOD (*((volatile unsigned int*)(0x42A7A108UL))) +#define bM4_PORT_PCRE2_DRV0 (*((volatile unsigned int*)(0x42A7A110UL))) +#define bM4_PORT_PCRE2_DRV1 (*((volatile unsigned int*)(0x42A7A114UL))) +#define bM4_PORT_PCRE2_PUU (*((volatile unsigned int*)(0x42A7A118UL))) +#define bM4_PORT_PCRE2_PIN (*((volatile unsigned int*)(0x42A7A120UL))) +#define bM4_PORT_PCRE2_INVE (*((volatile unsigned int*)(0x42A7A124UL))) +#define bM4_PORT_PCRE2_INTE (*((volatile unsigned int*)(0x42A7A130UL))) +#define bM4_PORT_PCRE2_LTE (*((volatile unsigned int*)(0x42A7A138UL))) +#define bM4_PORT_PCRE2_DDIS (*((volatile unsigned int*)(0x42A7A13CUL))) +#define bM4_PORT_PFSRE2_FSEL0 (*((volatile unsigned int*)(0x42A7A140UL))) +#define bM4_PORT_PFSRE2_FSEL1 (*((volatile unsigned int*)(0x42A7A144UL))) +#define bM4_PORT_PFSRE2_FSEL2 (*((volatile unsigned int*)(0x42A7A148UL))) +#define bM4_PORT_PFSRE2_FSEL3 (*((volatile unsigned int*)(0x42A7A14CUL))) +#define bM4_PORT_PFSRE2_FSEL4 (*((volatile unsigned int*)(0x42A7A150UL))) +#define bM4_PORT_PFSRE2_FSEL5 (*((volatile unsigned int*)(0x42A7A154UL))) +#define bM4_PORT_PFSRE2_BFE (*((volatile unsigned int*)(0x42A7A160UL))) +#define bM4_PORT_PCRE3_POUT (*((volatile unsigned int*)(0x42A7A180UL))) +#define bM4_PORT_PCRE3_POUTE (*((volatile unsigned int*)(0x42A7A184UL))) +#define bM4_PORT_PCRE3_NOD (*((volatile unsigned int*)(0x42A7A188UL))) +#define bM4_PORT_PCRE3_DRV0 (*((volatile unsigned int*)(0x42A7A190UL))) +#define bM4_PORT_PCRE3_DRV1 (*((volatile unsigned int*)(0x42A7A194UL))) +#define bM4_PORT_PCRE3_PUU (*((volatile unsigned int*)(0x42A7A198UL))) +#define bM4_PORT_PCRE3_PIN (*((volatile unsigned int*)(0x42A7A1A0UL))) +#define bM4_PORT_PCRE3_INVE (*((volatile unsigned int*)(0x42A7A1A4UL))) +#define bM4_PORT_PCRE3_INTE (*((volatile unsigned int*)(0x42A7A1B0UL))) +#define bM4_PORT_PCRE3_LTE (*((volatile unsigned int*)(0x42A7A1B8UL))) +#define bM4_PORT_PCRE3_DDIS (*((volatile unsigned int*)(0x42A7A1BCUL))) +#define bM4_PORT_PFSRE3_FSEL0 (*((volatile unsigned int*)(0x42A7A1C0UL))) +#define bM4_PORT_PFSRE3_FSEL1 (*((volatile unsigned int*)(0x42A7A1C4UL))) +#define bM4_PORT_PFSRE3_FSEL2 (*((volatile unsigned int*)(0x42A7A1C8UL))) +#define bM4_PORT_PFSRE3_FSEL3 (*((volatile unsigned int*)(0x42A7A1CCUL))) +#define bM4_PORT_PFSRE3_FSEL4 (*((volatile unsigned int*)(0x42A7A1D0UL))) +#define bM4_PORT_PFSRE3_FSEL5 (*((volatile unsigned int*)(0x42A7A1D4UL))) +#define bM4_PORT_PFSRE3_BFE (*((volatile unsigned int*)(0x42A7A1E0UL))) +#define bM4_PORT_PCRE4_POUT (*((volatile unsigned int*)(0x42A7A200UL))) +#define bM4_PORT_PCRE4_POUTE (*((volatile unsigned int*)(0x42A7A204UL))) +#define bM4_PORT_PCRE4_NOD (*((volatile unsigned int*)(0x42A7A208UL))) +#define bM4_PORT_PCRE4_DRV0 (*((volatile unsigned int*)(0x42A7A210UL))) +#define bM4_PORT_PCRE4_DRV1 (*((volatile unsigned int*)(0x42A7A214UL))) +#define bM4_PORT_PCRE4_PUU (*((volatile unsigned int*)(0x42A7A218UL))) +#define bM4_PORT_PCRE4_PIN (*((volatile unsigned int*)(0x42A7A220UL))) +#define bM4_PORT_PCRE4_INVE (*((volatile unsigned int*)(0x42A7A224UL))) +#define bM4_PORT_PCRE4_INTE (*((volatile unsigned int*)(0x42A7A230UL))) +#define bM4_PORT_PCRE4_LTE (*((volatile unsigned int*)(0x42A7A238UL))) +#define bM4_PORT_PCRE4_DDIS (*((volatile unsigned int*)(0x42A7A23CUL))) +#define bM4_PORT_PFSRE4_FSEL0 (*((volatile unsigned int*)(0x42A7A240UL))) +#define bM4_PORT_PFSRE4_FSEL1 (*((volatile unsigned int*)(0x42A7A244UL))) +#define bM4_PORT_PFSRE4_FSEL2 (*((volatile unsigned int*)(0x42A7A248UL))) +#define bM4_PORT_PFSRE4_FSEL3 (*((volatile unsigned int*)(0x42A7A24CUL))) +#define bM4_PORT_PFSRE4_FSEL4 (*((volatile unsigned int*)(0x42A7A250UL))) +#define bM4_PORT_PFSRE4_FSEL5 (*((volatile unsigned int*)(0x42A7A254UL))) +#define bM4_PORT_PFSRE4_BFE (*((volatile unsigned int*)(0x42A7A260UL))) +#define bM4_PORT_PCRE5_POUT (*((volatile unsigned int*)(0x42A7A280UL))) +#define bM4_PORT_PCRE5_POUTE (*((volatile unsigned int*)(0x42A7A284UL))) +#define bM4_PORT_PCRE5_NOD (*((volatile unsigned int*)(0x42A7A288UL))) +#define bM4_PORT_PCRE5_DRV0 (*((volatile unsigned int*)(0x42A7A290UL))) +#define bM4_PORT_PCRE5_DRV1 (*((volatile unsigned int*)(0x42A7A294UL))) +#define bM4_PORT_PCRE5_PUU (*((volatile unsigned int*)(0x42A7A298UL))) +#define bM4_PORT_PCRE5_PIN (*((volatile unsigned int*)(0x42A7A2A0UL))) +#define bM4_PORT_PCRE5_INVE (*((volatile unsigned int*)(0x42A7A2A4UL))) +#define bM4_PORT_PCRE5_INTE (*((volatile unsigned int*)(0x42A7A2B0UL))) +#define bM4_PORT_PCRE5_LTE (*((volatile unsigned int*)(0x42A7A2B8UL))) +#define bM4_PORT_PCRE5_DDIS (*((volatile unsigned int*)(0x42A7A2BCUL))) +#define bM4_PORT_PFSRE5_FSEL0 (*((volatile unsigned int*)(0x42A7A2C0UL))) +#define bM4_PORT_PFSRE5_FSEL1 (*((volatile unsigned int*)(0x42A7A2C4UL))) +#define bM4_PORT_PFSRE5_FSEL2 (*((volatile unsigned int*)(0x42A7A2C8UL))) +#define bM4_PORT_PFSRE5_FSEL3 (*((volatile unsigned int*)(0x42A7A2CCUL))) +#define bM4_PORT_PFSRE5_FSEL4 (*((volatile unsigned int*)(0x42A7A2D0UL))) +#define bM4_PORT_PFSRE5_FSEL5 (*((volatile unsigned int*)(0x42A7A2D4UL))) +#define bM4_PORT_PFSRE5_BFE (*((volatile unsigned int*)(0x42A7A2E0UL))) +#define bM4_PORT_PCRE6_POUT (*((volatile unsigned int*)(0x42A7A300UL))) +#define bM4_PORT_PCRE6_POUTE (*((volatile unsigned int*)(0x42A7A304UL))) +#define bM4_PORT_PCRE6_NOD (*((volatile unsigned int*)(0x42A7A308UL))) +#define bM4_PORT_PCRE6_DRV0 (*((volatile unsigned int*)(0x42A7A310UL))) +#define bM4_PORT_PCRE6_DRV1 (*((volatile unsigned int*)(0x42A7A314UL))) +#define bM4_PORT_PCRE6_PUU (*((volatile unsigned int*)(0x42A7A318UL))) +#define bM4_PORT_PCRE6_PIN (*((volatile unsigned int*)(0x42A7A320UL))) +#define bM4_PORT_PCRE6_INVE (*((volatile unsigned int*)(0x42A7A324UL))) +#define bM4_PORT_PCRE6_INTE (*((volatile unsigned int*)(0x42A7A330UL))) +#define bM4_PORT_PCRE6_LTE (*((volatile unsigned int*)(0x42A7A338UL))) +#define bM4_PORT_PCRE6_DDIS (*((volatile unsigned int*)(0x42A7A33CUL))) +#define bM4_PORT_PFSRE6_FSEL0 (*((volatile unsigned int*)(0x42A7A340UL))) +#define bM4_PORT_PFSRE6_FSEL1 (*((volatile unsigned int*)(0x42A7A344UL))) +#define bM4_PORT_PFSRE6_FSEL2 (*((volatile unsigned int*)(0x42A7A348UL))) +#define bM4_PORT_PFSRE6_FSEL3 (*((volatile unsigned int*)(0x42A7A34CUL))) +#define bM4_PORT_PFSRE6_FSEL4 (*((volatile unsigned int*)(0x42A7A350UL))) +#define bM4_PORT_PFSRE6_FSEL5 (*((volatile unsigned int*)(0x42A7A354UL))) +#define bM4_PORT_PFSRE6_BFE (*((volatile unsigned int*)(0x42A7A360UL))) +#define bM4_PORT_PCRE7_POUT (*((volatile unsigned int*)(0x42A7A380UL))) +#define bM4_PORT_PCRE7_POUTE (*((volatile unsigned int*)(0x42A7A384UL))) +#define bM4_PORT_PCRE7_NOD (*((volatile unsigned int*)(0x42A7A388UL))) +#define bM4_PORT_PCRE7_DRV0 (*((volatile unsigned int*)(0x42A7A390UL))) +#define bM4_PORT_PCRE7_DRV1 (*((volatile unsigned int*)(0x42A7A394UL))) +#define bM4_PORT_PCRE7_PUU (*((volatile unsigned int*)(0x42A7A398UL))) +#define bM4_PORT_PCRE7_PIN (*((volatile unsigned int*)(0x42A7A3A0UL))) +#define bM4_PORT_PCRE7_INVE (*((volatile unsigned int*)(0x42A7A3A4UL))) +#define bM4_PORT_PCRE7_INTE (*((volatile unsigned int*)(0x42A7A3B0UL))) +#define bM4_PORT_PCRE7_LTE (*((volatile unsigned int*)(0x42A7A3B8UL))) +#define bM4_PORT_PCRE7_DDIS (*((volatile unsigned int*)(0x42A7A3BCUL))) +#define bM4_PORT_PFSRE7_FSEL0 (*((volatile unsigned int*)(0x42A7A3C0UL))) +#define bM4_PORT_PFSRE7_FSEL1 (*((volatile unsigned int*)(0x42A7A3C4UL))) +#define bM4_PORT_PFSRE7_FSEL2 (*((volatile unsigned int*)(0x42A7A3C8UL))) +#define bM4_PORT_PFSRE7_FSEL3 (*((volatile unsigned int*)(0x42A7A3CCUL))) +#define bM4_PORT_PFSRE7_FSEL4 (*((volatile unsigned int*)(0x42A7A3D0UL))) +#define bM4_PORT_PFSRE7_FSEL5 (*((volatile unsigned int*)(0x42A7A3D4UL))) +#define bM4_PORT_PFSRE7_BFE (*((volatile unsigned int*)(0x42A7A3E0UL))) +#define bM4_PORT_PCRE8_POUT (*((volatile unsigned int*)(0x42A7A400UL))) +#define bM4_PORT_PCRE8_POUTE (*((volatile unsigned int*)(0x42A7A404UL))) +#define bM4_PORT_PCRE8_NOD (*((volatile unsigned int*)(0x42A7A408UL))) +#define bM4_PORT_PCRE8_DRV0 (*((volatile unsigned int*)(0x42A7A410UL))) +#define bM4_PORT_PCRE8_DRV1 (*((volatile unsigned int*)(0x42A7A414UL))) +#define bM4_PORT_PCRE8_PUU (*((volatile unsigned int*)(0x42A7A418UL))) +#define bM4_PORT_PCRE8_PIN (*((volatile unsigned int*)(0x42A7A420UL))) +#define bM4_PORT_PCRE8_INVE (*((volatile unsigned int*)(0x42A7A424UL))) +#define bM4_PORT_PCRE8_INTE (*((volatile unsigned int*)(0x42A7A430UL))) +#define bM4_PORT_PCRE8_LTE (*((volatile unsigned int*)(0x42A7A438UL))) +#define bM4_PORT_PCRE8_DDIS (*((volatile unsigned int*)(0x42A7A43CUL))) +#define bM4_PORT_PFSRE8_FSEL0 (*((volatile unsigned int*)(0x42A7A440UL))) +#define bM4_PORT_PFSRE8_FSEL1 (*((volatile unsigned int*)(0x42A7A444UL))) +#define bM4_PORT_PFSRE8_FSEL2 (*((volatile unsigned int*)(0x42A7A448UL))) +#define bM4_PORT_PFSRE8_FSEL3 (*((volatile unsigned int*)(0x42A7A44CUL))) +#define bM4_PORT_PFSRE8_FSEL4 (*((volatile unsigned int*)(0x42A7A450UL))) +#define bM4_PORT_PFSRE8_FSEL5 (*((volatile unsigned int*)(0x42A7A454UL))) +#define bM4_PORT_PFSRE8_BFE (*((volatile unsigned int*)(0x42A7A460UL))) +#define bM4_PORT_PCRE9_POUT (*((volatile unsigned int*)(0x42A7A480UL))) +#define bM4_PORT_PCRE9_POUTE (*((volatile unsigned int*)(0x42A7A484UL))) +#define bM4_PORT_PCRE9_NOD (*((volatile unsigned int*)(0x42A7A488UL))) +#define bM4_PORT_PCRE9_DRV0 (*((volatile unsigned int*)(0x42A7A490UL))) +#define bM4_PORT_PCRE9_DRV1 (*((volatile unsigned int*)(0x42A7A494UL))) +#define bM4_PORT_PCRE9_PUU (*((volatile unsigned int*)(0x42A7A498UL))) +#define bM4_PORT_PCRE9_PIN (*((volatile unsigned int*)(0x42A7A4A0UL))) +#define bM4_PORT_PCRE9_INVE (*((volatile unsigned int*)(0x42A7A4A4UL))) +#define bM4_PORT_PCRE9_INTE (*((volatile unsigned int*)(0x42A7A4B0UL))) +#define bM4_PORT_PCRE9_LTE (*((volatile unsigned int*)(0x42A7A4B8UL))) +#define bM4_PORT_PCRE9_DDIS (*((volatile unsigned int*)(0x42A7A4BCUL))) +#define bM4_PORT_PFSRE9_FSEL0 (*((volatile unsigned int*)(0x42A7A4C0UL))) +#define bM4_PORT_PFSRE9_FSEL1 (*((volatile unsigned int*)(0x42A7A4C4UL))) +#define bM4_PORT_PFSRE9_FSEL2 (*((volatile unsigned int*)(0x42A7A4C8UL))) +#define bM4_PORT_PFSRE9_FSEL3 (*((volatile unsigned int*)(0x42A7A4CCUL))) +#define bM4_PORT_PFSRE9_FSEL4 (*((volatile unsigned int*)(0x42A7A4D0UL))) +#define bM4_PORT_PFSRE9_FSEL5 (*((volatile unsigned int*)(0x42A7A4D4UL))) +#define bM4_PORT_PFSRE9_BFE (*((volatile unsigned int*)(0x42A7A4E0UL))) +#define bM4_PORT_PCRE10_POUT (*((volatile unsigned int*)(0x42A7A500UL))) +#define bM4_PORT_PCRE10_POUTE (*((volatile unsigned int*)(0x42A7A504UL))) +#define bM4_PORT_PCRE10_NOD (*((volatile unsigned int*)(0x42A7A508UL))) +#define bM4_PORT_PCRE10_DRV0 (*((volatile unsigned int*)(0x42A7A510UL))) +#define bM4_PORT_PCRE10_DRV1 (*((volatile unsigned int*)(0x42A7A514UL))) +#define bM4_PORT_PCRE10_PUU (*((volatile unsigned int*)(0x42A7A518UL))) +#define bM4_PORT_PCRE10_PIN (*((volatile unsigned int*)(0x42A7A520UL))) +#define bM4_PORT_PCRE10_INVE (*((volatile unsigned int*)(0x42A7A524UL))) +#define bM4_PORT_PCRE10_INTE (*((volatile unsigned int*)(0x42A7A530UL))) +#define bM4_PORT_PCRE10_LTE (*((volatile unsigned int*)(0x42A7A538UL))) +#define bM4_PORT_PCRE10_DDIS (*((volatile unsigned int*)(0x42A7A53CUL))) +#define bM4_PORT_PFSRE10_FSEL0 (*((volatile unsigned int*)(0x42A7A540UL))) +#define bM4_PORT_PFSRE10_FSEL1 (*((volatile unsigned int*)(0x42A7A544UL))) +#define bM4_PORT_PFSRE10_FSEL2 (*((volatile unsigned int*)(0x42A7A548UL))) +#define bM4_PORT_PFSRE10_FSEL3 (*((volatile unsigned int*)(0x42A7A54CUL))) +#define bM4_PORT_PFSRE10_FSEL4 (*((volatile unsigned int*)(0x42A7A550UL))) +#define bM4_PORT_PFSRE10_FSEL5 (*((volatile unsigned int*)(0x42A7A554UL))) +#define bM4_PORT_PFSRE10_BFE (*((volatile unsigned int*)(0x42A7A560UL))) +#define bM4_PORT_PCRE11_POUT (*((volatile unsigned int*)(0x42A7A580UL))) +#define bM4_PORT_PCRE11_POUTE (*((volatile unsigned int*)(0x42A7A584UL))) +#define bM4_PORT_PCRE11_NOD (*((volatile unsigned int*)(0x42A7A588UL))) +#define bM4_PORT_PCRE11_DRV0 (*((volatile unsigned int*)(0x42A7A590UL))) +#define bM4_PORT_PCRE11_DRV1 (*((volatile unsigned int*)(0x42A7A594UL))) +#define bM4_PORT_PCRE11_PUU (*((volatile unsigned int*)(0x42A7A598UL))) +#define bM4_PORT_PCRE11_PIN (*((volatile unsigned int*)(0x42A7A5A0UL))) +#define bM4_PORT_PCRE11_INVE (*((volatile unsigned int*)(0x42A7A5A4UL))) +#define bM4_PORT_PCRE11_INTE (*((volatile unsigned int*)(0x42A7A5B0UL))) +#define bM4_PORT_PCRE11_LTE (*((volatile unsigned int*)(0x42A7A5B8UL))) +#define bM4_PORT_PCRE11_DDIS (*((volatile unsigned int*)(0x42A7A5BCUL))) +#define bM4_PORT_PFSRE11_FSEL0 (*((volatile unsigned int*)(0x42A7A5C0UL))) +#define bM4_PORT_PFSRE11_FSEL1 (*((volatile unsigned int*)(0x42A7A5C4UL))) +#define bM4_PORT_PFSRE11_FSEL2 (*((volatile unsigned int*)(0x42A7A5C8UL))) +#define bM4_PORT_PFSRE11_FSEL3 (*((volatile unsigned int*)(0x42A7A5CCUL))) +#define bM4_PORT_PFSRE11_FSEL4 (*((volatile unsigned int*)(0x42A7A5D0UL))) +#define bM4_PORT_PFSRE11_FSEL5 (*((volatile unsigned int*)(0x42A7A5D4UL))) +#define bM4_PORT_PFSRE11_BFE (*((volatile unsigned int*)(0x42A7A5E0UL))) +#define bM4_PORT_PCRE12_POUT (*((volatile unsigned int*)(0x42A7A600UL))) +#define bM4_PORT_PCRE12_POUTE (*((volatile unsigned int*)(0x42A7A604UL))) +#define bM4_PORT_PCRE12_NOD (*((volatile unsigned int*)(0x42A7A608UL))) +#define bM4_PORT_PCRE12_DRV0 (*((volatile unsigned int*)(0x42A7A610UL))) +#define bM4_PORT_PCRE12_DRV1 (*((volatile unsigned int*)(0x42A7A614UL))) +#define bM4_PORT_PCRE12_PUU (*((volatile unsigned int*)(0x42A7A618UL))) +#define bM4_PORT_PCRE12_PIN (*((volatile unsigned int*)(0x42A7A620UL))) +#define bM4_PORT_PCRE12_INVE (*((volatile unsigned int*)(0x42A7A624UL))) +#define bM4_PORT_PCRE12_INTE (*((volatile unsigned int*)(0x42A7A630UL))) +#define bM4_PORT_PCRE12_LTE (*((volatile unsigned int*)(0x42A7A638UL))) +#define bM4_PORT_PCRE12_DDIS (*((volatile unsigned int*)(0x42A7A63CUL))) +#define bM4_PORT_PFSRE12_FSEL0 (*((volatile unsigned int*)(0x42A7A640UL))) +#define bM4_PORT_PFSRE12_FSEL1 (*((volatile unsigned int*)(0x42A7A644UL))) +#define bM4_PORT_PFSRE12_FSEL2 (*((volatile unsigned int*)(0x42A7A648UL))) +#define bM4_PORT_PFSRE12_FSEL3 (*((volatile unsigned int*)(0x42A7A64CUL))) +#define bM4_PORT_PFSRE12_FSEL4 (*((volatile unsigned int*)(0x42A7A650UL))) +#define bM4_PORT_PFSRE12_FSEL5 (*((volatile unsigned int*)(0x42A7A654UL))) +#define bM4_PORT_PFSRE12_BFE (*((volatile unsigned int*)(0x42A7A660UL))) +#define bM4_PORT_PCRE13_POUT (*((volatile unsigned int*)(0x42A7A680UL))) +#define bM4_PORT_PCRE13_POUTE (*((volatile unsigned int*)(0x42A7A684UL))) +#define bM4_PORT_PCRE13_NOD (*((volatile unsigned int*)(0x42A7A688UL))) +#define bM4_PORT_PCRE13_DRV0 (*((volatile unsigned int*)(0x42A7A690UL))) +#define bM4_PORT_PCRE13_DRV1 (*((volatile unsigned int*)(0x42A7A694UL))) +#define bM4_PORT_PCRE13_PUU (*((volatile unsigned int*)(0x42A7A698UL))) +#define bM4_PORT_PCRE13_PIN (*((volatile unsigned int*)(0x42A7A6A0UL))) +#define bM4_PORT_PCRE13_INVE (*((volatile unsigned int*)(0x42A7A6A4UL))) +#define bM4_PORT_PCRE13_INTE (*((volatile unsigned int*)(0x42A7A6B0UL))) +#define bM4_PORT_PCRE13_LTE (*((volatile unsigned int*)(0x42A7A6B8UL))) +#define bM4_PORT_PCRE13_DDIS (*((volatile unsigned int*)(0x42A7A6BCUL))) +#define bM4_PORT_PFSRE13_FSEL0 (*((volatile unsigned int*)(0x42A7A6C0UL))) +#define bM4_PORT_PFSRE13_FSEL1 (*((volatile unsigned int*)(0x42A7A6C4UL))) +#define bM4_PORT_PFSRE13_FSEL2 (*((volatile unsigned int*)(0x42A7A6C8UL))) +#define bM4_PORT_PFSRE13_FSEL3 (*((volatile unsigned int*)(0x42A7A6CCUL))) +#define bM4_PORT_PFSRE13_FSEL4 (*((volatile unsigned int*)(0x42A7A6D0UL))) +#define bM4_PORT_PFSRE13_FSEL5 (*((volatile unsigned int*)(0x42A7A6D4UL))) +#define bM4_PORT_PFSRE13_BFE (*((volatile unsigned int*)(0x42A7A6E0UL))) +#define bM4_PORT_PCRE14_POUT (*((volatile unsigned int*)(0x42A7A700UL))) +#define bM4_PORT_PCRE14_POUTE (*((volatile unsigned int*)(0x42A7A704UL))) +#define bM4_PORT_PCRE14_NOD (*((volatile unsigned int*)(0x42A7A708UL))) +#define bM4_PORT_PCRE14_DRV0 (*((volatile unsigned int*)(0x42A7A710UL))) +#define bM4_PORT_PCRE14_DRV1 (*((volatile unsigned int*)(0x42A7A714UL))) +#define bM4_PORT_PCRE14_PUU (*((volatile unsigned int*)(0x42A7A718UL))) +#define bM4_PORT_PCRE14_PIN (*((volatile unsigned int*)(0x42A7A720UL))) +#define bM4_PORT_PCRE14_INVE (*((volatile unsigned int*)(0x42A7A724UL))) +#define bM4_PORT_PCRE14_INTE (*((volatile unsigned int*)(0x42A7A730UL))) +#define bM4_PORT_PCRE14_LTE (*((volatile unsigned int*)(0x42A7A738UL))) +#define bM4_PORT_PCRE14_DDIS (*((volatile unsigned int*)(0x42A7A73CUL))) +#define bM4_PORT_PFSRE14_FSEL0 (*((volatile unsigned int*)(0x42A7A740UL))) +#define bM4_PORT_PFSRE14_FSEL1 (*((volatile unsigned int*)(0x42A7A744UL))) +#define bM4_PORT_PFSRE14_FSEL2 (*((volatile unsigned int*)(0x42A7A748UL))) +#define bM4_PORT_PFSRE14_FSEL3 (*((volatile unsigned int*)(0x42A7A74CUL))) +#define bM4_PORT_PFSRE14_FSEL4 (*((volatile unsigned int*)(0x42A7A750UL))) +#define bM4_PORT_PFSRE14_FSEL5 (*((volatile unsigned int*)(0x42A7A754UL))) +#define bM4_PORT_PFSRE14_BFE (*((volatile unsigned int*)(0x42A7A760UL))) +#define bM4_PORT_PCRE15_POUT (*((volatile unsigned int*)(0x42A7A780UL))) +#define bM4_PORT_PCRE15_POUTE (*((volatile unsigned int*)(0x42A7A784UL))) +#define bM4_PORT_PCRE15_NOD (*((volatile unsigned int*)(0x42A7A788UL))) +#define bM4_PORT_PCRE15_DRV0 (*((volatile unsigned int*)(0x42A7A790UL))) +#define bM4_PORT_PCRE15_DRV1 (*((volatile unsigned int*)(0x42A7A794UL))) +#define bM4_PORT_PCRE15_PUU (*((volatile unsigned int*)(0x42A7A798UL))) +#define bM4_PORT_PCRE15_PIN (*((volatile unsigned int*)(0x42A7A7A0UL))) +#define bM4_PORT_PCRE15_INVE (*((volatile unsigned int*)(0x42A7A7A4UL))) +#define bM4_PORT_PCRE15_INTE (*((volatile unsigned int*)(0x42A7A7B0UL))) +#define bM4_PORT_PCRE15_LTE (*((volatile unsigned int*)(0x42A7A7B8UL))) +#define bM4_PORT_PCRE15_DDIS (*((volatile unsigned int*)(0x42A7A7BCUL))) +#define bM4_PORT_PFSRE15_FSEL0 (*((volatile unsigned int*)(0x42A7A7C0UL))) +#define bM4_PORT_PFSRE15_FSEL1 (*((volatile unsigned int*)(0x42A7A7C4UL))) +#define bM4_PORT_PFSRE15_FSEL2 (*((volatile unsigned int*)(0x42A7A7C8UL))) +#define bM4_PORT_PFSRE15_FSEL3 (*((volatile unsigned int*)(0x42A7A7CCUL))) +#define bM4_PORT_PFSRE15_FSEL4 (*((volatile unsigned int*)(0x42A7A7D0UL))) +#define bM4_PORT_PFSRE15_FSEL5 (*((volatile unsigned int*)(0x42A7A7D4UL))) +#define bM4_PORT_PFSRE15_BFE (*((volatile unsigned int*)(0x42A7A7E0UL))) +#define bM4_PORT_PCRH0_POUT (*((volatile unsigned int*)(0x42A7A800UL))) +#define bM4_PORT_PCRH0_POUTE (*((volatile unsigned int*)(0x42A7A804UL))) +#define bM4_PORT_PCRH0_NOD (*((volatile unsigned int*)(0x42A7A808UL))) +#define bM4_PORT_PCRH0_DRV0 (*((volatile unsigned int*)(0x42A7A810UL))) +#define bM4_PORT_PCRH0_DRV1 (*((volatile unsigned int*)(0x42A7A814UL))) +#define bM4_PORT_PCRH0_PUU (*((volatile unsigned int*)(0x42A7A818UL))) +#define bM4_PORT_PCRH0_PIN (*((volatile unsigned int*)(0x42A7A820UL))) +#define bM4_PORT_PCRH0_INVE (*((volatile unsigned int*)(0x42A7A824UL))) +#define bM4_PORT_PCRH0_INTE (*((volatile unsigned int*)(0x42A7A830UL))) +#define bM4_PORT_PCRH0_LTE (*((volatile unsigned int*)(0x42A7A838UL))) +#define bM4_PORT_PCRH0_DDIS (*((volatile unsigned int*)(0x42A7A83CUL))) +#define bM4_PORT_PFSRH0_FSEL0 (*((volatile unsigned int*)(0x42A7A840UL))) +#define bM4_PORT_PFSRH0_FSEL1 (*((volatile unsigned int*)(0x42A7A844UL))) +#define bM4_PORT_PFSRH0_FSEL2 (*((volatile unsigned int*)(0x42A7A848UL))) +#define bM4_PORT_PFSRH0_FSEL3 (*((volatile unsigned int*)(0x42A7A84CUL))) +#define bM4_PORT_PFSRH0_FSEL4 (*((volatile unsigned int*)(0x42A7A850UL))) +#define bM4_PORT_PFSRH0_FSEL5 (*((volatile unsigned int*)(0x42A7A854UL))) +#define bM4_PORT_PFSRH0_BFE (*((volatile unsigned int*)(0x42A7A860UL))) +#define bM4_PORT_PCRH1_POUT (*((volatile unsigned int*)(0x42A7A880UL))) +#define bM4_PORT_PCRH1_POUTE (*((volatile unsigned int*)(0x42A7A884UL))) +#define bM4_PORT_PCRH1_NOD (*((volatile unsigned int*)(0x42A7A888UL))) +#define bM4_PORT_PCRH1_DRV0 (*((volatile unsigned int*)(0x42A7A890UL))) +#define bM4_PORT_PCRH1_DRV1 (*((volatile unsigned int*)(0x42A7A894UL))) +#define bM4_PORT_PCRH1_PUU (*((volatile unsigned int*)(0x42A7A898UL))) +#define bM4_PORT_PCRH1_PIN (*((volatile unsigned int*)(0x42A7A8A0UL))) +#define bM4_PORT_PCRH1_INVE (*((volatile unsigned int*)(0x42A7A8A4UL))) +#define bM4_PORT_PCRH1_INTE (*((volatile unsigned int*)(0x42A7A8B0UL))) +#define bM4_PORT_PCRH1_LTE (*((volatile unsigned int*)(0x42A7A8B8UL))) +#define bM4_PORT_PCRH1_DDIS (*((volatile unsigned int*)(0x42A7A8BCUL))) +#define bM4_PORT_PFSRH1_FSEL0 (*((volatile unsigned int*)(0x42A7A8C0UL))) +#define bM4_PORT_PFSRH1_FSEL1 (*((volatile unsigned int*)(0x42A7A8C4UL))) +#define bM4_PORT_PFSRH1_FSEL2 (*((volatile unsigned int*)(0x42A7A8C8UL))) +#define bM4_PORT_PFSRH1_FSEL3 (*((volatile unsigned int*)(0x42A7A8CCUL))) +#define bM4_PORT_PFSRH1_FSEL4 (*((volatile unsigned int*)(0x42A7A8D0UL))) +#define bM4_PORT_PFSRH1_FSEL5 (*((volatile unsigned int*)(0x42A7A8D4UL))) +#define bM4_PORT_PFSRH1_BFE (*((volatile unsigned int*)(0x42A7A8E0UL))) +#define bM4_PORT_PCRH2_POUT (*((volatile unsigned int*)(0x42A7A900UL))) +#define bM4_PORT_PCRH2_POUTE (*((volatile unsigned int*)(0x42A7A904UL))) +#define bM4_PORT_PCRH2_NOD (*((volatile unsigned int*)(0x42A7A908UL))) +#define bM4_PORT_PCRH2_DRV0 (*((volatile unsigned int*)(0x42A7A910UL))) +#define bM4_PORT_PCRH2_DRV1 (*((volatile unsigned int*)(0x42A7A914UL))) +#define bM4_PORT_PCRH2_PUU (*((volatile unsigned int*)(0x42A7A918UL))) +#define bM4_PORT_PCRH2_PIN (*((volatile unsigned int*)(0x42A7A920UL))) +#define bM4_PORT_PCRH2_INVE (*((volatile unsigned int*)(0x42A7A924UL))) +#define bM4_PORT_PCRH2_INTE (*((volatile unsigned int*)(0x42A7A930UL))) +#define bM4_PORT_PCRH2_LTE (*((volatile unsigned int*)(0x42A7A938UL))) +#define bM4_PORT_PCRH2_DDIS (*((volatile unsigned int*)(0x42A7A93CUL))) +#define bM4_PORT_PFSRH2_FSEL0 (*((volatile unsigned int*)(0x42A7A940UL))) +#define bM4_PORT_PFSRH2_FSEL1 (*((volatile unsigned int*)(0x42A7A944UL))) +#define bM4_PORT_PFSRH2_FSEL2 (*((volatile unsigned int*)(0x42A7A948UL))) +#define bM4_PORT_PFSRH2_FSEL3 (*((volatile unsigned int*)(0x42A7A94CUL))) +#define bM4_PORT_PFSRH2_FSEL4 (*((volatile unsigned int*)(0x42A7A950UL))) +#define bM4_PORT_PFSRH2_FSEL5 (*((volatile unsigned int*)(0x42A7A954UL))) +#define bM4_PORT_PFSRH2_BFE (*((volatile unsigned int*)(0x42A7A960UL))) +#define bM4_RTC_CR0_RESET (*((volatile unsigned int*)(0x42980000UL))) +#define bM4_RTC_CR1_PRDS0 (*((volatile unsigned int*)(0x42980080UL))) +#define bM4_RTC_CR1_PRDS1 (*((volatile unsigned int*)(0x42980084UL))) +#define bM4_RTC_CR1_PRDS2 (*((volatile unsigned int*)(0x42980088UL))) +#define bM4_RTC_CR1_AMPM (*((volatile unsigned int*)(0x4298008CUL))) +#define bM4_RTC_CR1_ALMFCLR (*((volatile unsigned int*)(0x42980090UL))) +#define bM4_RTC_CR1_ONEHZOE (*((volatile unsigned int*)(0x42980094UL))) +#define bM4_RTC_CR1_ONEHZSEL (*((volatile unsigned int*)(0x42980098UL))) +#define bM4_RTC_CR1_START (*((volatile unsigned int*)(0x4298009CUL))) +#define bM4_RTC_CR2_RWREQ (*((volatile unsigned int*)(0x42980100UL))) +#define bM4_RTC_CR2_RWEN (*((volatile unsigned int*)(0x42980104UL))) +#define bM4_RTC_CR2_ALMF (*((volatile unsigned int*)(0x4298010CUL))) +#define bM4_RTC_CR2_PRDIE (*((volatile unsigned int*)(0x42980114UL))) +#define bM4_RTC_CR2_ALMIE (*((volatile unsigned int*)(0x42980118UL))) +#define bM4_RTC_CR2_ALME (*((volatile unsigned int*)(0x4298011CUL))) +#define bM4_RTC_CR3_LRCEN (*((volatile unsigned int*)(0x42980190UL))) +#define bM4_RTC_CR3_RCKSEL (*((volatile unsigned int*)(0x4298019CUL))) +#define bM4_RTC_SEC_SECU0 (*((volatile unsigned int*)(0x42980200UL))) +#define bM4_RTC_SEC_SECU1 (*((volatile unsigned int*)(0x42980204UL))) +#define bM4_RTC_SEC_SECU2 (*((volatile unsigned int*)(0x42980208UL))) +#define bM4_RTC_SEC_SECU3 (*((volatile unsigned int*)(0x4298020CUL))) +#define bM4_RTC_SEC_SECD0 (*((volatile unsigned int*)(0x42980210UL))) +#define bM4_RTC_SEC_SECD1 (*((volatile unsigned int*)(0x42980214UL))) +#define bM4_RTC_SEC_SECD2 (*((volatile unsigned int*)(0x42980218UL))) +#define bM4_RTC_MIN_MINU0 (*((volatile unsigned int*)(0x42980280UL))) +#define bM4_RTC_MIN_MINU1 (*((volatile unsigned int*)(0x42980284UL))) +#define bM4_RTC_MIN_MINU2 (*((volatile unsigned int*)(0x42980288UL))) +#define bM4_RTC_MIN_MINU3 (*((volatile unsigned int*)(0x4298028CUL))) +#define bM4_RTC_MIN_MIND0 (*((volatile unsigned int*)(0x42980290UL))) +#define bM4_RTC_MIN_MIND1 (*((volatile unsigned int*)(0x42980294UL))) +#define bM4_RTC_MIN_MIND2 (*((volatile unsigned int*)(0x42980298UL))) +#define bM4_RTC_HOUR_HOURU0 (*((volatile unsigned int*)(0x42980300UL))) +#define bM4_RTC_HOUR_HOURU1 (*((volatile unsigned int*)(0x42980304UL))) +#define bM4_RTC_HOUR_HOURU2 (*((volatile unsigned int*)(0x42980308UL))) +#define bM4_RTC_HOUR_HOURU3 (*((volatile unsigned int*)(0x4298030CUL))) +#define bM4_RTC_HOUR_HOURD0 (*((volatile unsigned int*)(0x42980310UL))) +#define bM4_RTC_HOUR_HOURD1 (*((volatile unsigned int*)(0x42980314UL))) +#define bM4_RTC_WEEK_WEEK0 (*((volatile unsigned int*)(0x42980380UL))) +#define bM4_RTC_WEEK_WEEK1 (*((volatile unsigned int*)(0x42980384UL))) +#define bM4_RTC_WEEK_WEEK2 (*((volatile unsigned int*)(0x42980388UL))) +#define bM4_RTC_DAY_DAYU0 (*((volatile unsigned int*)(0x42980400UL))) +#define bM4_RTC_DAY_DAYU1 (*((volatile unsigned int*)(0x42980404UL))) +#define bM4_RTC_DAY_DAYU2 (*((volatile unsigned int*)(0x42980408UL))) +#define bM4_RTC_DAY_DAYU3 (*((volatile unsigned int*)(0x4298040CUL))) +#define bM4_RTC_DAY_DAYD0 (*((volatile unsigned int*)(0x42980410UL))) +#define bM4_RTC_DAY_DAYD1 (*((volatile unsigned int*)(0x42980414UL))) +#define bM4_RTC_MON_MON0 (*((volatile unsigned int*)(0x42980480UL))) +#define bM4_RTC_MON_MON1 (*((volatile unsigned int*)(0x42980484UL))) +#define bM4_RTC_MON_MON2 (*((volatile unsigned int*)(0x42980488UL))) +#define bM4_RTC_MON_MON3 (*((volatile unsigned int*)(0x4298048CUL))) +#define bM4_RTC_MON_MON4 (*((volatile unsigned int*)(0x42980490UL))) +#define bM4_RTC_YEAR_YEARU0 (*((volatile unsigned int*)(0x42980500UL))) +#define bM4_RTC_YEAR_YEARU1 (*((volatile unsigned int*)(0x42980504UL))) +#define bM4_RTC_YEAR_YEARU2 (*((volatile unsigned int*)(0x42980508UL))) +#define bM4_RTC_YEAR_YEARU3 (*((volatile unsigned int*)(0x4298050CUL))) +#define bM4_RTC_YEAR_YEARD0 (*((volatile unsigned int*)(0x42980510UL))) +#define bM4_RTC_YEAR_YEARD1 (*((volatile unsigned int*)(0x42980514UL))) +#define bM4_RTC_YEAR_YEARD2 (*((volatile unsigned int*)(0x42980518UL))) +#define bM4_RTC_YEAR_YEARD3 (*((volatile unsigned int*)(0x4298051CUL))) +#define bM4_RTC_ALMMIN_ALMMINU0 (*((volatile unsigned int*)(0x42980580UL))) +#define bM4_RTC_ALMMIN_ALMMINU1 (*((volatile unsigned int*)(0x42980584UL))) +#define bM4_RTC_ALMMIN_ALMMINU2 (*((volatile unsigned int*)(0x42980588UL))) +#define bM4_RTC_ALMMIN_ALMMINU3 (*((volatile unsigned int*)(0x4298058CUL))) +#define bM4_RTC_ALMMIN_ALMMIND0 (*((volatile unsigned int*)(0x42980590UL))) +#define bM4_RTC_ALMMIN_ALMMIND1 (*((volatile unsigned int*)(0x42980594UL))) +#define bM4_RTC_ALMMIN_ALMMIND2 (*((volatile unsigned int*)(0x42980598UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU0 (*((volatile unsigned int*)(0x42980600UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU1 (*((volatile unsigned int*)(0x42980604UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU2 (*((volatile unsigned int*)(0x42980608UL))) +#define bM4_RTC_ALMHOUR_ALMHOURU3 (*((volatile unsigned int*)(0x4298060CUL))) +#define bM4_RTC_ALMHOUR_ALMHOURD0 (*((volatile unsigned int*)(0x42980610UL))) +#define bM4_RTC_ALMHOUR_ALMHOURD1 (*((volatile unsigned int*)(0x42980614UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK0 (*((volatile unsigned int*)(0x42980680UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK1 (*((volatile unsigned int*)(0x42980684UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK2 (*((volatile unsigned int*)(0x42980688UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK3 (*((volatile unsigned int*)(0x4298068CUL))) +#define bM4_RTC_ALMWEEK_ALMWEEK4 (*((volatile unsigned int*)(0x42980690UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK5 (*((volatile unsigned int*)(0x42980694UL))) +#define bM4_RTC_ALMWEEK_ALMWEEK6 (*((volatile unsigned int*)(0x42980698UL))) +#define bM4_RTC_ERRCRH_COMP8 (*((volatile unsigned int*)(0x42980700UL))) +#define bM4_RTC_ERRCRH_COMPEN (*((volatile unsigned int*)(0x4298071CUL))) +#define bM4_RTC_ERRCRL_COMP0 (*((volatile unsigned int*)(0x42980780UL))) +#define bM4_RTC_ERRCRL_COMP1 (*((volatile unsigned int*)(0x42980784UL))) +#define bM4_RTC_ERRCRL_COMP2 (*((volatile unsigned int*)(0x42980788UL))) +#define bM4_RTC_ERRCRL_COMP3 (*((volatile unsigned int*)(0x4298078CUL))) +#define bM4_RTC_ERRCRL_COMP4 (*((volatile unsigned int*)(0x42980790UL))) +#define bM4_RTC_ERRCRL_COMP5 (*((volatile unsigned int*)(0x42980794UL))) +#define bM4_RTC_ERRCRL_COMP6 (*((volatile unsigned int*)(0x42980798UL))) +#define bM4_RTC_ERRCRL_COMP7 (*((volatile unsigned int*)(0x4298079CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS0 (*((volatile unsigned int*)(0x42DF8080UL))) +#define bM4_SDIOC1_BLKSIZE_TBS1 (*((volatile unsigned int*)(0x42DF8084UL))) +#define bM4_SDIOC1_BLKSIZE_TBS2 (*((volatile unsigned int*)(0x42DF8088UL))) +#define bM4_SDIOC1_BLKSIZE_TBS3 (*((volatile unsigned int*)(0x42DF808CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS4 (*((volatile unsigned int*)(0x42DF8090UL))) +#define bM4_SDIOC1_BLKSIZE_TBS5 (*((volatile unsigned int*)(0x42DF8094UL))) +#define bM4_SDIOC1_BLKSIZE_TBS6 (*((volatile unsigned int*)(0x42DF8098UL))) +#define bM4_SDIOC1_BLKSIZE_TBS7 (*((volatile unsigned int*)(0x42DF809CUL))) +#define bM4_SDIOC1_BLKSIZE_TBS8 (*((volatile unsigned int*)(0x42DF80A0UL))) +#define bM4_SDIOC1_BLKSIZE_TBS9 (*((volatile unsigned int*)(0x42DF80A4UL))) +#define bM4_SDIOC1_BLKSIZE_TBS10 (*((volatile unsigned int*)(0x42DF80A8UL))) +#define bM4_SDIOC1_BLKSIZE_TBS11 (*((volatile unsigned int*)(0x42DF80ACUL))) +#define bM4_SDIOC1_TRANSMODE_BCE (*((volatile unsigned int*)(0x42DF8184UL))) +#define bM4_SDIOC1_TRANSMODE_ATCEN0 (*((volatile unsigned int*)(0x42DF8188UL))) +#define bM4_SDIOC1_TRANSMODE_ATCEN1 (*((volatile unsigned int*)(0x42DF818CUL))) +#define bM4_SDIOC1_TRANSMODE_DDIR (*((volatile unsigned int*)(0x42DF8190UL))) +#define bM4_SDIOC1_TRANSMODE_MULB (*((volatile unsigned int*)(0x42DF8194UL))) +#define bM4_SDIOC1_CMD_RESTYP0 (*((volatile unsigned int*)(0x42DF81C0UL))) +#define bM4_SDIOC1_CMD_RESTYP1 (*((volatile unsigned int*)(0x42DF81C4UL))) +#define bM4_SDIOC1_CMD_CCE (*((volatile unsigned int*)(0x42DF81CCUL))) +#define bM4_SDIOC1_CMD_ICE (*((volatile unsigned int*)(0x42DF81D0UL))) +#define bM4_SDIOC1_CMD_DAT (*((volatile unsigned int*)(0x42DF81D4UL))) +#define bM4_SDIOC1_CMD_TYP0 (*((volatile unsigned int*)(0x42DF81D8UL))) +#define bM4_SDIOC1_CMD_TYP1 (*((volatile unsigned int*)(0x42DF81DCUL))) +#define bM4_SDIOC1_CMD_IDX0 (*((volatile unsigned int*)(0x42DF81E0UL))) +#define bM4_SDIOC1_CMD_IDX1 (*((volatile unsigned int*)(0x42DF81E4UL))) +#define bM4_SDIOC1_CMD_IDX2 (*((volatile unsigned int*)(0x42DF81E8UL))) +#define bM4_SDIOC1_CMD_IDX3 (*((volatile unsigned int*)(0x42DF81ECUL))) +#define bM4_SDIOC1_CMD_IDX4 (*((volatile unsigned int*)(0x42DF81F0UL))) +#define bM4_SDIOC1_CMD_IDX5 (*((volatile unsigned int*)(0x42DF81F4UL))) +#define bM4_SDIOC1_PSTAT_CIC (*((volatile unsigned int*)(0x42DF8480UL))) +#define bM4_SDIOC1_PSTAT_CID (*((volatile unsigned int*)(0x42DF8484UL))) +#define bM4_SDIOC1_PSTAT_DA (*((volatile unsigned int*)(0x42DF8488UL))) +#define bM4_SDIOC1_PSTAT_WTA (*((volatile unsigned int*)(0x42DF84A0UL))) +#define bM4_SDIOC1_PSTAT_RTA (*((volatile unsigned int*)(0x42DF84A4UL))) +#define bM4_SDIOC1_PSTAT_BWE (*((volatile unsigned int*)(0x42DF84A8UL))) +#define bM4_SDIOC1_PSTAT_BRE (*((volatile unsigned int*)(0x42DF84ACUL))) +#define bM4_SDIOC1_PSTAT_CIN (*((volatile unsigned int*)(0x42DF84C0UL))) +#define bM4_SDIOC1_PSTAT_CSS (*((volatile unsigned int*)(0x42DF84C4UL))) +#define bM4_SDIOC1_PSTAT_CDL (*((volatile unsigned int*)(0x42DF84C8UL))) +#define bM4_SDIOC1_PSTAT_WPL (*((volatile unsigned int*)(0x42DF84CCUL))) +#define bM4_SDIOC1_PSTAT_DATL0 (*((volatile unsigned int*)(0x42DF84D0UL))) +#define bM4_SDIOC1_PSTAT_DATL1 (*((volatile unsigned int*)(0x42DF84D4UL))) +#define bM4_SDIOC1_PSTAT_DATL2 (*((volatile unsigned int*)(0x42DF84D8UL))) +#define bM4_SDIOC1_PSTAT_DATL3 (*((volatile unsigned int*)(0x42DF84DCUL))) +#define bM4_SDIOC1_PSTAT_CMDL (*((volatile unsigned int*)(0x42DF84E0UL))) +#define bM4_SDIOC1_HOSTCON_DW (*((volatile unsigned int*)(0x42DF8504UL))) +#define bM4_SDIOC1_HOSTCON_HSEN (*((volatile unsigned int*)(0x42DF8508UL))) +#define bM4_SDIOC1_HOSTCON_EXDW (*((volatile unsigned int*)(0x42DF8514UL))) +#define bM4_SDIOC1_HOSTCON_CDTL (*((volatile unsigned int*)(0x42DF8518UL))) +#define bM4_SDIOC1_HOSTCON_CDSS (*((volatile unsigned int*)(0x42DF851CUL))) +#define bM4_SDIOC1_PWRCON_PWON (*((volatile unsigned int*)(0x42DF8520UL))) +#define bM4_SDIOC1_BLKGPCON_SABGR (*((volatile unsigned int*)(0x42DF8540UL))) +#define bM4_SDIOC1_BLKGPCON_CR (*((volatile unsigned int*)(0x42DF8544UL))) +#define bM4_SDIOC1_BLKGPCON_RWC (*((volatile unsigned int*)(0x42DF8548UL))) +#define bM4_SDIOC1_BLKGPCON_IABG (*((volatile unsigned int*)(0x42DF854CUL))) +#define bM4_SDIOC1_CLKCON_ICE (*((volatile unsigned int*)(0x42DF8580UL))) +#define bM4_SDIOC1_CLKCON_CE (*((volatile unsigned int*)(0x42DF8588UL))) +#define bM4_SDIOC1_CLKCON_FS0 (*((volatile unsigned int*)(0x42DF85A0UL))) +#define bM4_SDIOC1_CLKCON_FS1 (*((volatile unsigned int*)(0x42DF85A4UL))) +#define bM4_SDIOC1_CLKCON_FS2 (*((volatile unsigned int*)(0x42DF85A8UL))) +#define bM4_SDIOC1_CLKCON_FS3 (*((volatile unsigned int*)(0x42DF85ACUL))) +#define bM4_SDIOC1_CLKCON_FS4 (*((volatile unsigned int*)(0x42DF85B0UL))) +#define bM4_SDIOC1_CLKCON_FS5 (*((volatile unsigned int*)(0x42DF85B4UL))) +#define bM4_SDIOC1_CLKCON_FS6 (*((volatile unsigned int*)(0x42DF85B8UL))) +#define bM4_SDIOC1_CLKCON_FS7 (*((volatile unsigned int*)(0x42DF85BCUL))) +#define bM4_SDIOC1_TOUTCON_DTO0 (*((volatile unsigned int*)(0x42DF85C0UL))) +#define bM4_SDIOC1_TOUTCON_DTO1 (*((volatile unsigned int*)(0x42DF85C4UL))) +#define bM4_SDIOC1_TOUTCON_DTO2 (*((volatile unsigned int*)(0x42DF85C8UL))) +#define bM4_SDIOC1_TOUTCON_DTO3 (*((volatile unsigned int*)(0x42DF85CCUL))) +#define bM4_SDIOC1_SFTRST_RSTA (*((volatile unsigned int*)(0x42DF85E0UL))) +#define bM4_SDIOC1_SFTRST_RSTC (*((volatile unsigned int*)(0x42DF85E4UL))) +#define bM4_SDIOC1_SFTRST_RSTD (*((volatile unsigned int*)(0x42DF85E8UL))) +#define bM4_SDIOC1_NORINTST_CC (*((volatile unsigned int*)(0x42DF8600UL))) +#define bM4_SDIOC1_NORINTST_TC (*((volatile unsigned int*)(0x42DF8604UL))) +#define bM4_SDIOC1_NORINTST_BGE (*((volatile unsigned int*)(0x42DF8608UL))) +#define bM4_SDIOC1_NORINTST_BWR (*((volatile unsigned int*)(0x42DF8610UL))) +#define bM4_SDIOC1_NORINTST_BRR (*((volatile unsigned int*)(0x42DF8614UL))) +#define bM4_SDIOC1_NORINTST_CIST (*((volatile unsigned int*)(0x42DF8618UL))) +#define bM4_SDIOC1_NORINTST_CRM (*((volatile unsigned int*)(0x42DF861CUL))) +#define bM4_SDIOC1_NORINTST_CINT (*((volatile unsigned int*)(0x42DF8620UL))) +#define bM4_SDIOC1_NORINTST_EI (*((volatile unsigned int*)(0x42DF863CUL))) +#define bM4_SDIOC1_ERRINTST_CTOE (*((volatile unsigned int*)(0x42DF8640UL))) +#define bM4_SDIOC1_ERRINTST_CCE (*((volatile unsigned int*)(0x42DF8644UL))) +#define bM4_SDIOC1_ERRINTST_CEBE (*((volatile unsigned int*)(0x42DF8648UL))) +#define bM4_SDIOC1_ERRINTST_CIE (*((volatile unsigned int*)(0x42DF864CUL))) +#define bM4_SDIOC1_ERRINTST_DTOE (*((volatile unsigned int*)(0x42DF8650UL))) +#define bM4_SDIOC1_ERRINTST_DCE (*((volatile unsigned int*)(0x42DF8654UL))) +#define bM4_SDIOC1_ERRINTST_DEBE (*((volatile unsigned int*)(0x42DF8658UL))) +#define bM4_SDIOC1_ERRINTST_ACE (*((volatile unsigned int*)(0x42DF8660UL))) +#define bM4_SDIOC1_NORINTSTEN_CCEN (*((volatile unsigned int*)(0x42DF8680UL))) +#define bM4_SDIOC1_NORINTSTEN_TCEN (*((volatile unsigned int*)(0x42DF8684UL))) +#define bM4_SDIOC1_NORINTSTEN_BGEEN (*((volatile unsigned int*)(0x42DF8688UL))) +#define bM4_SDIOC1_NORINTSTEN_BWREN (*((volatile unsigned int*)(0x42DF8690UL))) +#define bM4_SDIOC1_NORINTSTEN_BRREN (*((volatile unsigned int*)(0x42DF8694UL))) +#define bM4_SDIOC1_NORINTSTEN_CISTEN (*((volatile unsigned int*)(0x42DF8698UL))) +#define bM4_SDIOC1_NORINTSTEN_CRMEN (*((volatile unsigned int*)(0x42DF869CUL))) +#define bM4_SDIOC1_NORINTSTEN_CINTEN (*((volatile unsigned int*)(0x42DF86A0UL))) +#define bM4_SDIOC1_ERRINTSTEN_CTOEEN (*((volatile unsigned int*)(0x42DF86C0UL))) +#define bM4_SDIOC1_ERRINTSTEN_CCEEN (*((volatile unsigned int*)(0x42DF86C4UL))) +#define bM4_SDIOC1_ERRINTSTEN_CEBEEN (*((volatile unsigned int*)(0x42DF86C8UL))) +#define bM4_SDIOC1_ERRINTSTEN_CIEEN (*((volatile unsigned int*)(0x42DF86CCUL))) +#define bM4_SDIOC1_ERRINTSTEN_DTOEEN (*((volatile unsigned int*)(0x42DF86D0UL))) +#define bM4_SDIOC1_ERRINTSTEN_DCEEN (*((volatile unsigned int*)(0x42DF86D4UL))) +#define bM4_SDIOC1_ERRINTSTEN_DEBEEN (*((volatile unsigned int*)(0x42DF86D8UL))) +#define bM4_SDIOC1_ERRINTSTEN_ACEEN (*((volatile unsigned int*)(0x42DF86E0UL))) +#define bM4_SDIOC1_NORINTSGEN_CCSEN (*((volatile unsigned int*)(0x42DF8700UL))) +#define bM4_SDIOC1_NORINTSGEN_TCSEN (*((volatile unsigned int*)(0x42DF8704UL))) +#define bM4_SDIOC1_NORINTSGEN_BGESEN (*((volatile unsigned int*)(0x42DF8708UL))) +#define bM4_SDIOC1_NORINTSGEN_BWRSEN (*((volatile unsigned int*)(0x42DF8710UL))) +#define bM4_SDIOC1_NORINTSGEN_BRRSEN (*((volatile unsigned int*)(0x42DF8714UL))) +#define bM4_SDIOC1_NORINTSGEN_CISTSEN (*((volatile unsigned int*)(0x42DF8718UL))) +#define bM4_SDIOC1_NORINTSGEN_CRMSEN (*((volatile unsigned int*)(0x42DF871CUL))) +#define bM4_SDIOC1_NORINTSGEN_CINTSEN (*((volatile unsigned int*)(0x42DF8720UL))) +#define bM4_SDIOC1_ERRINTSGEN_CTOESEN (*((volatile unsigned int*)(0x42DF8740UL))) +#define bM4_SDIOC1_ERRINTSGEN_CCESEN (*((volatile unsigned int*)(0x42DF8744UL))) +#define bM4_SDIOC1_ERRINTSGEN_CEBESEN (*((volatile unsigned int*)(0x42DF8748UL))) +#define bM4_SDIOC1_ERRINTSGEN_CIESEN (*((volatile unsigned int*)(0x42DF874CUL))) +#define bM4_SDIOC1_ERRINTSGEN_DTOESEN (*((volatile unsigned int*)(0x42DF8750UL))) +#define bM4_SDIOC1_ERRINTSGEN_DCESEN (*((volatile unsigned int*)(0x42DF8754UL))) +#define bM4_SDIOC1_ERRINTSGEN_DEBESEN (*((volatile unsigned int*)(0x42DF8758UL))) +#define bM4_SDIOC1_ERRINTSGEN_ACESEN (*((volatile unsigned int*)(0x42DF8760UL))) +#define bM4_SDIOC1_ATCERRST_NE (*((volatile unsigned int*)(0x42DF8780UL))) +#define bM4_SDIOC1_ATCERRST_TOE (*((volatile unsigned int*)(0x42DF8784UL))) +#define bM4_SDIOC1_ATCERRST_CE (*((volatile unsigned int*)(0x42DF8788UL))) +#define bM4_SDIOC1_ATCERRST_EBE (*((volatile unsigned int*)(0x42DF878CUL))) +#define bM4_SDIOC1_ATCERRST_IE (*((volatile unsigned int*)(0x42DF8790UL))) +#define bM4_SDIOC1_ATCERRST_CMDE (*((volatile unsigned int*)(0x42DF879CUL))) +#define bM4_SDIOC1_FEA_FNE (*((volatile unsigned int*)(0x42DF8A00UL))) +#define bM4_SDIOC1_FEA_FTOE (*((volatile unsigned int*)(0x42DF8A04UL))) +#define bM4_SDIOC1_FEA_FCE (*((volatile unsigned int*)(0x42DF8A08UL))) +#define bM4_SDIOC1_FEA_FEBE (*((volatile unsigned int*)(0x42DF8A0CUL))) +#define bM4_SDIOC1_FEA_FIE (*((volatile unsigned int*)(0x42DF8A10UL))) +#define bM4_SDIOC1_FEA_FCMDE (*((volatile unsigned int*)(0x42DF8A1CUL))) +#define bM4_SDIOC1_FEE_FCTOE (*((volatile unsigned int*)(0x42DF8A40UL))) +#define bM4_SDIOC1_FEE_FCCE (*((volatile unsigned int*)(0x42DF8A44UL))) +#define bM4_SDIOC1_FEE_FCEBE (*((volatile unsigned int*)(0x42DF8A48UL))) +#define bM4_SDIOC1_FEE_FCIE (*((volatile unsigned int*)(0x42DF8A4CUL))) +#define bM4_SDIOC1_FEE_FDTOE (*((volatile unsigned int*)(0x42DF8A50UL))) +#define bM4_SDIOC1_FEE_FDCE (*((volatile unsigned int*)(0x42DF8A54UL))) +#define bM4_SDIOC1_FEE_FDEBE (*((volatile unsigned int*)(0x42DF8A58UL))) +#define bM4_SDIOC1_FEE_FACE (*((volatile unsigned int*)(0x42DF8A60UL))) +#define bM4_SDIOC2_BLKSIZE_TBS0 (*((volatile unsigned int*)(0x42E00080UL))) +#define bM4_SDIOC2_BLKSIZE_TBS1 (*((volatile unsigned int*)(0x42E00084UL))) +#define bM4_SDIOC2_BLKSIZE_TBS2 (*((volatile unsigned int*)(0x42E00088UL))) +#define bM4_SDIOC2_BLKSIZE_TBS3 (*((volatile unsigned int*)(0x42E0008CUL))) +#define bM4_SDIOC2_BLKSIZE_TBS4 (*((volatile unsigned int*)(0x42E00090UL))) +#define bM4_SDIOC2_BLKSIZE_TBS5 (*((volatile unsigned int*)(0x42E00094UL))) +#define bM4_SDIOC2_BLKSIZE_TBS6 (*((volatile unsigned int*)(0x42E00098UL))) +#define bM4_SDIOC2_BLKSIZE_TBS7 (*((volatile unsigned int*)(0x42E0009CUL))) +#define bM4_SDIOC2_BLKSIZE_TBS8 (*((volatile unsigned int*)(0x42E000A0UL))) +#define bM4_SDIOC2_BLKSIZE_TBS9 (*((volatile unsigned int*)(0x42E000A4UL))) +#define bM4_SDIOC2_BLKSIZE_TBS10 (*((volatile unsigned int*)(0x42E000A8UL))) +#define bM4_SDIOC2_BLKSIZE_TBS11 (*((volatile unsigned int*)(0x42E000ACUL))) +#define bM4_SDIOC2_TRANSMODE_BCE (*((volatile unsigned int*)(0x42E00184UL))) +#define bM4_SDIOC2_TRANSMODE_ATCEN0 (*((volatile unsigned int*)(0x42E00188UL))) +#define bM4_SDIOC2_TRANSMODE_ATCEN1 (*((volatile unsigned int*)(0x42E0018CUL))) +#define bM4_SDIOC2_TRANSMODE_DDIR (*((volatile unsigned int*)(0x42E00190UL))) +#define bM4_SDIOC2_TRANSMODE_MULB (*((volatile unsigned int*)(0x42E00194UL))) +#define bM4_SDIOC2_CMD_RESTYP0 (*((volatile unsigned int*)(0x42E001C0UL))) +#define bM4_SDIOC2_CMD_RESTYP1 (*((volatile unsigned int*)(0x42E001C4UL))) +#define bM4_SDIOC2_CMD_CCE (*((volatile unsigned int*)(0x42E001CCUL))) +#define bM4_SDIOC2_CMD_ICE (*((volatile unsigned int*)(0x42E001D0UL))) +#define bM4_SDIOC2_CMD_DAT (*((volatile unsigned int*)(0x42E001D4UL))) +#define bM4_SDIOC2_CMD_TYP0 (*((volatile unsigned int*)(0x42E001D8UL))) +#define bM4_SDIOC2_CMD_TYP1 (*((volatile unsigned int*)(0x42E001DCUL))) +#define bM4_SDIOC2_CMD_IDX0 (*((volatile unsigned int*)(0x42E001E0UL))) +#define bM4_SDIOC2_CMD_IDX1 (*((volatile unsigned int*)(0x42E001E4UL))) +#define bM4_SDIOC2_CMD_IDX2 (*((volatile unsigned int*)(0x42E001E8UL))) +#define bM4_SDIOC2_CMD_IDX3 (*((volatile unsigned int*)(0x42E001ECUL))) +#define bM4_SDIOC2_CMD_IDX4 (*((volatile unsigned int*)(0x42E001F0UL))) +#define bM4_SDIOC2_CMD_IDX5 (*((volatile unsigned int*)(0x42E001F4UL))) +#define bM4_SDIOC2_PSTAT_CIC (*((volatile unsigned int*)(0x42E00480UL))) +#define bM4_SDIOC2_PSTAT_CID (*((volatile unsigned int*)(0x42E00484UL))) +#define bM4_SDIOC2_PSTAT_DA (*((volatile unsigned int*)(0x42E00488UL))) +#define bM4_SDIOC2_PSTAT_WTA (*((volatile unsigned int*)(0x42E004A0UL))) +#define bM4_SDIOC2_PSTAT_RTA (*((volatile unsigned int*)(0x42E004A4UL))) +#define bM4_SDIOC2_PSTAT_BWE (*((volatile unsigned int*)(0x42E004A8UL))) +#define bM4_SDIOC2_PSTAT_BRE (*((volatile unsigned int*)(0x42E004ACUL))) +#define bM4_SDIOC2_PSTAT_CIN (*((volatile unsigned int*)(0x42E004C0UL))) +#define bM4_SDIOC2_PSTAT_CSS (*((volatile unsigned int*)(0x42E004C4UL))) +#define bM4_SDIOC2_PSTAT_CDL (*((volatile unsigned int*)(0x42E004C8UL))) +#define bM4_SDIOC2_PSTAT_WPL (*((volatile unsigned int*)(0x42E004CCUL))) +#define bM4_SDIOC2_PSTAT_DATL0 (*((volatile unsigned int*)(0x42E004D0UL))) +#define bM4_SDIOC2_PSTAT_DATL1 (*((volatile unsigned int*)(0x42E004D4UL))) +#define bM4_SDIOC2_PSTAT_DATL2 (*((volatile unsigned int*)(0x42E004D8UL))) +#define bM4_SDIOC2_PSTAT_DATL3 (*((volatile unsigned int*)(0x42E004DCUL))) +#define bM4_SDIOC2_PSTAT_CMDL (*((volatile unsigned int*)(0x42E004E0UL))) +#define bM4_SDIOC2_HOSTCON_DW (*((volatile unsigned int*)(0x42E00504UL))) +#define bM4_SDIOC2_HOSTCON_HSEN (*((volatile unsigned int*)(0x42E00508UL))) +#define bM4_SDIOC2_HOSTCON_EXDW (*((volatile unsigned int*)(0x42E00514UL))) +#define bM4_SDIOC2_HOSTCON_CDTL (*((volatile unsigned int*)(0x42E00518UL))) +#define bM4_SDIOC2_HOSTCON_CDSS (*((volatile unsigned int*)(0x42E0051CUL))) +#define bM4_SDIOC2_PWRCON_PWON (*((volatile unsigned int*)(0x42E00520UL))) +#define bM4_SDIOC2_BLKGPCON_SABGR (*((volatile unsigned int*)(0x42E00540UL))) +#define bM4_SDIOC2_BLKGPCON_CR (*((volatile unsigned int*)(0x42E00544UL))) +#define bM4_SDIOC2_BLKGPCON_RWC (*((volatile unsigned int*)(0x42E00548UL))) +#define bM4_SDIOC2_BLKGPCON_IABG (*((volatile unsigned int*)(0x42E0054CUL))) +#define bM4_SDIOC2_CLKCON_ICE (*((volatile unsigned int*)(0x42E00580UL))) +#define bM4_SDIOC2_CLKCON_CE (*((volatile unsigned int*)(0x42E00588UL))) +#define bM4_SDIOC2_CLKCON_FS0 (*((volatile unsigned int*)(0x42E005A0UL))) +#define bM4_SDIOC2_CLKCON_FS1 (*((volatile unsigned int*)(0x42E005A4UL))) +#define bM4_SDIOC2_CLKCON_FS2 (*((volatile unsigned int*)(0x42E005A8UL))) +#define bM4_SDIOC2_CLKCON_FS3 (*((volatile unsigned int*)(0x42E005ACUL))) +#define bM4_SDIOC2_CLKCON_FS4 (*((volatile unsigned int*)(0x42E005B0UL))) +#define bM4_SDIOC2_CLKCON_FS5 (*((volatile unsigned int*)(0x42E005B4UL))) +#define bM4_SDIOC2_CLKCON_FS6 (*((volatile unsigned int*)(0x42E005B8UL))) +#define bM4_SDIOC2_CLKCON_FS7 (*((volatile unsigned int*)(0x42E005BCUL))) +#define bM4_SDIOC2_TOUTCON_DTO0 (*((volatile unsigned int*)(0x42E005C0UL))) +#define bM4_SDIOC2_TOUTCON_DTO1 (*((volatile unsigned int*)(0x42E005C4UL))) +#define bM4_SDIOC2_TOUTCON_DTO2 (*((volatile unsigned int*)(0x42E005C8UL))) +#define bM4_SDIOC2_TOUTCON_DTO3 (*((volatile unsigned int*)(0x42E005CCUL))) +#define bM4_SDIOC2_SFTRST_RSTA (*((volatile unsigned int*)(0x42E005E0UL))) +#define bM4_SDIOC2_SFTRST_RSTC (*((volatile unsigned int*)(0x42E005E4UL))) +#define bM4_SDIOC2_SFTRST_RSTD (*((volatile unsigned int*)(0x42E005E8UL))) +#define bM4_SDIOC2_NORINTST_CC (*((volatile unsigned int*)(0x42E00600UL))) +#define bM4_SDIOC2_NORINTST_TC (*((volatile unsigned int*)(0x42E00604UL))) +#define bM4_SDIOC2_NORINTST_BGE (*((volatile unsigned int*)(0x42E00608UL))) +#define bM4_SDIOC2_NORINTST_BWR (*((volatile unsigned int*)(0x42E00610UL))) +#define bM4_SDIOC2_NORINTST_BRR (*((volatile unsigned int*)(0x42E00614UL))) +#define bM4_SDIOC2_NORINTST_CIST (*((volatile unsigned int*)(0x42E00618UL))) +#define bM4_SDIOC2_NORINTST_CRM (*((volatile unsigned int*)(0x42E0061CUL))) +#define bM4_SDIOC2_NORINTST_CINT (*((volatile unsigned int*)(0x42E00620UL))) +#define bM4_SDIOC2_NORINTST_EI (*((volatile unsigned int*)(0x42E0063CUL))) +#define bM4_SDIOC2_ERRINTST_CTOE (*((volatile unsigned int*)(0x42E00640UL))) +#define bM4_SDIOC2_ERRINTST_CCE (*((volatile unsigned int*)(0x42E00644UL))) +#define bM4_SDIOC2_ERRINTST_CEBE (*((volatile unsigned int*)(0x42E00648UL))) +#define bM4_SDIOC2_ERRINTST_CIE (*((volatile unsigned int*)(0x42E0064CUL))) +#define bM4_SDIOC2_ERRINTST_DTOE (*((volatile unsigned int*)(0x42E00650UL))) +#define bM4_SDIOC2_ERRINTST_DCE (*((volatile unsigned int*)(0x42E00654UL))) +#define bM4_SDIOC2_ERRINTST_DEBE (*((volatile unsigned int*)(0x42E00658UL))) +#define bM4_SDIOC2_ERRINTST_ACE (*((volatile unsigned int*)(0x42E00660UL))) +#define bM4_SDIOC2_NORINTSTEN_CCEN (*((volatile unsigned int*)(0x42E00680UL))) +#define bM4_SDIOC2_NORINTSTEN_TCEN (*((volatile unsigned int*)(0x42E00684UL))) +#define bM4_SDIOC2_NORINTSTEN_BGEEN (*((volatile unsigned int*)(0x42E00688UL))) +#define bM4_SDIOC2_NORINTSTEN_BWREN (*((volatile unsigned int*)(0x42E00690UL))) +#define bM4_SDIOC2_NORINTSTEN_BRREN (*((volatile unsigned int*)(0x42E00694UL))) +#define bM4_SDIOC2_NORINTSTEN_CISTEN (*((volatile unsigned int*)(0x42E00698UL))) +#define bM4_SDIOC2_NORINTSTEN_CRMEN (*((volatile unsigned int*)(0x42E0069CUL))) +#define bM4_SDIOC2_NORINTSTEN_CINTEN (*((volatile unsigned int*)(0x42E006A0UL))) +#define bM4_SDIOC2_ERRINTSTEN_CTOEEN (*((volatile unsigned int*)(0x42E006C0UL))) +#define bM4_SDIOC2_ERRINTSTEN_CCEEN (*((volatile unsigned int*)(0x42E006C4UL))) +#define bM4_SDIOC2_ERRINTSTEN_CEBEEN (*((volatile unsigned int*)(0x42E006C8UL))) +#define bM4_SDIOC2_ERRINTSTEN_CIEEN (*((volatile unsigned int*)(0x42E006CCUL))) +#define bM4_SDIOC2_ERRINTSTEN_DTOEEN (*((volatile unsigned int*)(0x42E006D0UL))) +#define bM4_SDIOC2_ERRINTSTEN_DCEEN (*((volatile unsigned int*)(0x42E006D4UL))) +#define bM4_SDIOC2_ERRINTSTEN_DEBEEN (*((volatile unsigned int*)(0x42E006D8UL))) +#define bM4_SDIOC2_ERRINTSTEN_ACEEN (*((volatile unsigned int*)(0x42E006E0UL))) +#define bM4_SDIOC2_NORINTSGEN_CCSEN (*((volatile unsigned int*)(0x42E00700UL))) +#define bM4_SDIOC2_NORINTSGEN_TCSEN (*((volatile unsigned int*)(0x42E00704UL))) +#define bM4_SDIOC2_NORINTSGEN_BGESEN (*((volatile unsigned int*)(0x42E00708UL))) +#define bM4_SDIOC2_NORINTSGEN_BWRSEN (*((volatile unsigned int*)(0x42E00710UL))) +#define bM4_SDIOC2_NORINTSGEN_BRRSEN (*((volatile unsigned int*)(0x42E00714UL))) +#define bM4_SDIOC2_NORINTSGEN_CISTSEN (*((volatile unsigned int*)(0x42E00718UL))) +#define bM4_SDIOC2_NORINTSGEN_CRMSEN (*((volatile unsigned int*)(0x42E0071CUL))) +#define bM4_SDIOC2_NORINTSGEN_CINTSEN (*((volatile unsigned int*)(0x42E00720UL))) +#define bM4_SDIOC2_ERRINTSGEN_CTOESEN (*((volatile unsigned int*)(0x42E00740UL))) +#define bM4_SDIOC2_ERRINTSGEN_CCESEN (*((volatile unsigned int*)(0x42E00744UL))) +#define bM4_SDIOC2_ERRINTSGEN_CEBESEN (*((volatile unsigned int*)(0x42E00748UL))) +#define bM4_SDIOC2_ERRINTSGEN_CIESEN (*((volatile unsigned int*)(0x42E0074CUL))) +#define bM4_SDIOC2_ERRINTSGEN_DTOESEN (*((volatile unsigned int*)(0x42E00750UL))) +#define bM4_SDIOC2_ERRINTSGEN_DCESEN (*((volatile unsigned int*)(0x42E00754UL))) +#define bM4_SDIOC2_ERRINTSGEN_DEBESEN (*((volatile unsigned int*)(0x42E00758UL))) +#define bM4_SDIOC2_ERRINTSGEN_ACESEN (*((volatile unsigned int*)(0x42E00760UL))) +#define bM4_SDIOC2_ATCERRST_NE (*((volatile unsigned int*)(0x42E00780UL))) +#define bM4_SDIOC2_ATCERRST_TOE (*((volatile unsigned int*)(0x42E00784UL))) +#define bM4_SDIOC2_ATCERRST_CE (*((volatile unsigned int*)(0x42E00788UL))) +#define bM4_SDIOC2_ATCERRST_EBE (*((volatile unsigned int*)(0x42E0078CUL))) +#define bM4_SDIOC2_ATCERRST_IE (*((volatile unsigned int*)(0x42E00790UL))) +#define bM4_SDIOC2_ATCERRST_CMDE (*((volatile unsigned int*)(0x42E0079CUL))) +#define bM4_SDIOC2_FEA_FNE (*((volatile unsigned int*)(0x42E00A00UL))) +#define bM4_SDIOC2_FEA_FTOE (*((volatile unsigned int*)(0x42E00A04UL))) +#define bM4_SDIOC2_FEA_FCE (*((volatile unsigned int*)(0x42E00A08UL))) +#define bM4_SDIOC2_FEA_FEBE (*((volatile unsigned int*)(0x42E00A0CUL))) +#define bM4_SDIOC2_FEA_FIE (*((volatile unsigned int*)(0x42E00A10UL))) +#define bM4_SDIOC2_FEA_FCMDE (*((volatile unsigned int*)(0x42E00A1CUL))) +#define bM4_SDIOC2_FEE_FCTOE (*((volatile unsigned int*)(0x42E00A40UL))) +#define bM4_SDIOC2_FEE_FCCE (*((volatile unsigned int*)(0x42E00A44UL))) +#define bM4_SDIOC2_FEE_FCEBE (*((volatile unsigned int*)(0x42E00A48UL))) +#define bM4_SDIOC2_FEE_FCIE (*((volatile unsigned int*)(0x42E00A4CUL))) +#define bM4_SDIOC2_FEE_FDTOE (*((volatile unsigned int*)(0x42E00A50UL))) +#define bM4_SDIOC2_FEE_FDCE (*((volatile unsigned int*)(0x42E00A54UL))) +#define bM4_SDIOC2_FEE_FDEBE (*((volatile unsigned int*)(0x42E00A58UL))) +#define bM4_SDIOC2_FEE_FACE (*((volatile unsigned int*)(0x42E00A60UL))) +#define bM4_SPI1_CR1_SPIMDS (*((volatile unsigned int*)(0x42380080UL))) +#define bM4_SPI1_CR1_TXMDS (*((volatile unsigned int*)(0x42380084UL))) +#define bM4_SPI1_CR1_MSTR (*((volatile unsigned int*)(0x4238008CUL))) +#define bM4_SPI1_CR1_SPLPBK (*((volatile unsigned int*)(0x42380090UL))) +#define bM4_SPI1_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42380094UL))) +#define bM4_SPI1_CR1_SPE (*((volatile unsigned int*)(0x42380098UL))) +#define bM4_SPI1_CR1_CSUSPE (*((volatile unsigned int*)(0x4238009CUL))) +#define bM4_SPI1_CR1_EIE (*((volatile unsigned int*)(0x423800A0UL))) +#define bM4_SPI1_CR1_TXIE (*((volatile unsigned int*)(0x423800A4UL))) +#define bM4_SPI1_CR1_RXIE (*((volatile unsigned int*)(0x423800A8UL))) +#define bM4_SPI1_CR1_IDIE (*((volatile unsigned int*)(0x423800ACUL))) +#define bM4_SPI1_CR1_MODFE (*((volatile unsigned int*)(0x423800B0UL))) +#define bM4_SPI1_CR1_PATE (*((volatile unsigned int*)(0x423800B4UL))) +#define bM4_SPI1_CR1_PAOE (*((volatile unsigned int*)(0x423800B8UL))) +#define bM4_SPI1_CR1_PAE (*((volatile unsigned int*)(0x423800BCUL))) +#define bM4_SPI1_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42380180UL))) +#define bM4_SPI1_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42380184UL))) +#define bM4_SPI1_CFG1_SPRDTD (*((volatile unsigned int*)(0x42380198UL))) +#define bM4_SPI1_CFG1_SS0PV (*((volatile unsigned int*)(0x423801A0UL))) +#define bM4_SPI1_CFG1_SS1PV (*((volatile unsigned int*)(0x423801A4UL))) +#define bM4_SPI1_CFG1_SS2PV (*((volatile unsigned int*)(0x423801A8UL))) +#define bM4_SPI1_CFG1_SS3PV (*((volatile unsigned int*)(0x423801ACUL))) +#define bM4_SPI1_CFG1_MSSI0 (*((volatile unsigned int*)(0x423801D0UL))) +#define bM4_SPI1_CFG1_MSSI1 (*((volatile unsigned int*)(0x423801D4UL))) +#define bM4_SPI1_CFG1_MSSI2 (*((volatile unsigned int*)(0x423801D8UL))) +#define bM4_SPI1_CFG1_MSSDL0 (*((volatile unsigned int*)(0x423801E0UL))) +#define bM4_SPI1_CFG1_MSSDL1 (*((volatile unsigned int*)(0x423801E4UL))) +#define bM4_SPI1_CFG1_MSSDL2 (*((volatile unsigned int*)(0x423801E8UL))) +#define bM4_SPI1_CFG1_MIDI0 (*((volatile unsigned int*)(0x423801F0UL))) +#define bM4_SPI1_CFG1_MIDI1 (*((volatile unsigned int*)(0x423801F4UL))) +#define bM4_SPI1_CFG1_MIDI2 (*((volatile unsigned int*)(0x423801F8UL))) +#define bM4_SPI1_SR_OVRERF (*((volatile unsigned int*)(0x42380280UL))) +#define bM4_SPI1_SR_IDLNF (*((volatile unsigned int*)(0x42380284UL))) +#define bM4_SPI1_SR_MODFERF (*((volatile unsigned int*)(0x42380288UL))) +#define bM4_SPI1_SR_PERF (*((volatile unsigned int*)(0x4238028CUL))) +#define bM4_SPI1_SR_UDRERF (*((volatile unsigned int*)(0x42380290UL))) +#define bM4_SPI1_SR_TDEF (*((volatile unsigned int*)(0x42380294UL))) +#define bM4_SPI1_SR_RDFF (*((volatile unsigned int*)(0x4238029CUL))) +#define bM4_SPI1_CFG2_CPHA (*((volatile unsigned int*)(0x42380300UL))) +#define bM4_SPI1_CFG2_CPOL (*((volatile unsigned int*)(0x42380304UL))) +#define bM4_SPI1_CFG2_MBR0 (*((volatile unsigned int*)(0x42380308UL))) +#define bM4_SPI1_CFG2_MBR1 (*((volatile unsigned int*)(0x4238030CUL))) +#define bM4_SPI1_CFG2_MBR2 (*((volatile unsigned int*)(0x42380310UL))) +#define bM4_SPI1_CFG2_SSA0 (*((volatile unsigned int*)(0x42380314UL))) +#define bM4_SPI1_CFG2_SSA1 (*((volatile unsigned int*)(0x42380318UL))) +#define bM4_SPI1_CFG2_SSA2 (*((volatile unsigned int*)(0x4238031CUL))) +#define bM4_SPI1_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42380320UL))) +#define bM4_SPI1_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42380324UL))) +#define bM4_SPI1_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42380328UL))) +#define bM4_SPI1_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4238032CUL))) +#define bM4_SPI1_CFG2_LSBF (*((volatile unsigned int*)(0x42380330UL))) +#define bM4_SPI1_CFG2_MIDIE (*((volatile unsigned int*)(0x42380334UL))) +#define bM4_SPI1_CFG2_MSSDLE (*((volatile unsigned int*)(0x42380338UL))) +#define bM4_SPI1_CFG2_MSSIE (*((volatile unsigned int*)(0x4238033CUL))) +#define bM4_SPI2_CR1_SPIMDS (*((volatile unsigned int*)(0x42388080UL))) +#define bM4_SPI2_CR1_TXMDS (*((volatile unsigned int*)(0x42388084UL))) +#define bM4_SPI2_CR1_MSTR (*((volatile unsigned int*)(0x4238808CUL))) +#define bM4_SPI2_CR1_SPLPBK (*((volatile unsigned int*)(0x42388090UL))) +#define bM4_SPI2_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42388094UL))) +#define bM4_SPI2_CR1_SPE (*((volatile unsigned int*)(0x42388098UL))) +#define bM4_SPI2_CR1_CSUSPE (*((volatile unsigned int*)(0x4238809CUL))) +#define bM4_SPI2_CR1_EIE (*((volatile unsigned int*)(0x423880A0UL))) +#define bM4_SPI2_CR1_TXIE (*((volatile unsigned int*)(0x423880A4UL))) +#define bM4_SPI2_CR1_RXIE (*((volatile unsigned int*)(0x423880A8UL))) +#define bM4_SPI2_CR1_IDIE (*((volatile unsigned int*)(0x423880ACUL))) +#define bM4_SPI2_CR1_MODFE (*((volatile unsigned int*)(0x423880B0UL))) +#define bM4_SPI2_CR1_PATE (*((volatile unsigned int*)(0x423880B4UL))) +#define bM4_SPI2_CR1_PAOE (*((volatile unsigned int*)(0x423880B8UL))) +#define bM4_SPI2_CR1_PAE (*((volatile unsigned int*)(0x423880BCUL))) +#define bM4_SPI2_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42388180UL))) +#define bM4_SPI2_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42388184UL))) +#define bM4_SPI2_CFG1_SPRDTD (*((volatile unsigned int*)(0x42388198UL))) +#define bM4_SPI2_CFG1_SS0PV (*((volatile unsigned int*)(0x423881A0UL))) +#define bM4_SPI2_CFG1_SS1PV (*((volatile unsigned int*)(0x423881A4UL))) +#define bM4_SPI2_CFG1_SS2PV (*((volatile unsigned int*)(0x423881A8UL))) +#define bM4_SPI2_CFG1_SS3PV (*((volatile unsigned int*)(0x423881ACUL))) +#define bM4_SPI2_CFG1_MSSI0 (*((volatile unsigned int*)(0x423881D0UL))) +#define bM4_SPI2_CFG1_MSSI1 (*((volatile unsigned int*)(0x423881D4UL))) +#define bM4_SPI2_CFG1_MSSI2 (*((volatile unsigned int*)(0x423881D8UL))) +#define bM4_SPI2_CFG1_MSSDL0 (*((volatile unsigned int*)(0x423881E0UL))) +#define bM4_SPI2_CFG1_MSSDL1 (*((volatile unsigned int*)(0x423881E4UL))) +#define bM4_SPI2_CFG1_MSSDL2 (*((volatile unsigned int*)(0x423881E8UL))) +#define bM4_SPI2_CFG1_MIDI0 (*((volatile unsigned int*)(0x423881F0UL))) +#define bM4_SPI2_CFG1_MIDI1 (*((volatile unsigned int*)(0x423881F4UL))) +#define bM4_SPI2_CFG1_MIDI2 (*((volatile unsigned int*)(0x423881F8UL))) +#define bM4_SPI2_SR_OVRERF (*((volatile unsigned int*)(0x42388280UL))) +#define bM4_SPI2_SR_IDLNF (*((volatile unsigned int*)(0x42388284UL))) +#define bM4_SPI2_SR_MODFERF (*((volatile unsigned int*)(0x42388288UL))) +#define bM4_SPI2_SR_PERF (*((volatile unsigned int*)(0x4238828CUL))) +#define bM4_SPI2_SR_UDRERF (*((volatile unsigned int*)(0x42388290UL))) +#define bM4_SPI2_SR_TDEF (*((volatile unsigned int*)(0x42388294UL))) +#define bM4_SPI2_SR_RDFF (*((volatile unsigned int*)(0x4238829CUL))) +#define bM4_SPI2_CFG2_CPHA (*((volatile unsigned int*)(0x42388300UL))) +#define bM4_SPI2_CFG2_CPOL (*((volatile unsigned int*)(0x42388304UL))) +#define bM4_SPI2_CFG2_MBR0 (*((volatile unsigned int*)(0x42388308UL))) +#define bM4_SPI2_CFG2_MBR1 (*((volatile unsigned int*)(0x4238830CUL))) +#define bM4_SPI2_CFG2_MBR2 (*((volatile unsigned int*)(0x42388310UL))) +#define bM4_SPI2_CFG2_SSA0 (*((volatile unsigned int*)(0x42388314UL))) +#define bM4_SPI2_CFG2_SSA1 (*((volatile unsigned int*)(0x42388318UL))) +#define bM4_SPI2_CFG2_SSA2 (*((volatile unsigned int*)(0x4238831CUL))) +#define bM4_SPI2_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42388320UL))) +#define bM4_SPI2_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42388324UL))) +#define bM4_SPI2_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42388328UL))) +#define bM4_SPI2_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4238832CUL))) +#define bM4_SPI2_CFG2_LSBF (*((volatile unsigned int*)(0x42388330UL))) +#define bM4_SPI2_CFG2_MIDIE (*((volatile unsigned int*)(0x42388334UL))) +#define bM4_SPI2_CFG2_MSSDLE (*((volatile unsigned int*)(0x42388338UL))) +#define bM4_SPI2_CFG2_MSSIE (*((volatile unsigned int*)(0x4238833CUL))) +#define bM4_SPI3_CR1_SPIMDS (*((volatile unsigned int*)(0x42400080UL))) +#define bM4_SPI3_CR1_TXMDS (*((volatile unsigned int*)(0x42400084UL))) +#define bM4_SPI3_CR1_MSTR (*((volatile unsigned int*)(0x4240008CUL))) +#define bM4_SPI3_CR1_SPLPBK (*((volatile unsigned int*)(0x42400090UL))) +#define bM4_SPI3_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42400094UL))) +#define bM4_SPI3_CR1_SPE (*((volatile unsigned int*)(0x42400098UL))) +#define bM4_SPI3_CR1_CSUSPE (*((volatile unsigned int*)(0x4240009CUL))) +#define bM4_SPI3_CR1_EIE (*((volatile unsigned int*)(0x424000A0UL))) +#define bM4_SPI3_CR1_TXIE (*((volatile unsigned int*)(0x424000A4UL))) +#define bM4_SPI3_CR1_RXIE (*((volatile unsigned int*)(0x424000A8UL))) +#define bM4_SPI3_CR1_IDIE (*((volatile unsigned int*)(0x424000ACUL))) +#define bM4_SPI3_CR1_MODFE (*((volatile unsigned int*)(0x424000B0UL))) +#define bM4_SPI3_CR1_PATE (*((volatile unsigned int*)(0x424000B4UL))) +#define bM4_SPI3_CR1_PAOE (*((volatile unsigned int*)(0x424000B8UL))) +#define bM4_SPI3_CR1_PAE (*((volatile unsigned int*)(0x424000BCUL))) +#define bM4_SPI3_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42400180UL))) +#define bM4_SPI3_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42400184UL))) +#define bM4_SPI3_CFG1_SPRDTD (*((volatile unsigned int*)(0x42400198UL))) +#define bM4_SPI3_CFG1_SS0PV (*((volatile unsigned int*)(0x424001A0UL))) +#define bM4_SPI3_CFG1_SS1PV (*((volatile unsigned int*)(0x424001A4UL))) +#define bM4_SPI3_CFG1_SS2PV (*((volatile unsigned int*)(0x424001A8UL))) +#define bM4_SPI3_CFG1_SS3PV (*((volatile unsigned int*)(0x424001ACUL))) +#define bM4_SPI3_CFG1_MSSI0 (*((volatile unsigned int*)(0x424001D0UL))) +#define bM4_SPI3_CFG1_MSSI1 (*((volatile unsigned int*)(0x424001D4UL))) +#define bM4_SPI3_CFG1_MSSI2 (*((volatile unsigned int*)(0x424001D8UL))) +#define bM4_SPI3_CFG1_MSSDL0 (*((volatile unsigned int*)(0x424001E0UL))) +#define bM4_SPI3_CFG1_MSSDL1 (*((volatile unsigned int*)(0x424001E4UL))) +#define bM4_SPI3_CFG1_MSSDL2 (*((volatile unsigned int*)(0x424001E8UL))) +#define bM4_SPI3_CFG1_MIDI0 (*((volatile unsigned int*)(0x424001F0UL))) +#define bM4_SPI3_CFG1_MIDI1 (*((volatile unsigned int*)(0x424001F4UL))) +#define bM4_SPI3_CFG1_MIDI2 (*((volatile unsigned int*)(0x424001F8UL))) +#define bM4_SPI3_SR_OVRERF (*((volatile unsigned int*)(0x42400280UL))) +#define bM4_SPI3_SR_IDLNF (*((volatile unsigned int*)(0x42400284UL))) +#define bM4_SPI3_SR_MODFERF (*((volatile unsigned int*)(0x42400288UL))) +#define bM4_SPI3_SR_PERF (*((volatile unsigned int*)(0x4240028CUL))) +#define bM4_SPI3_SR_UDRERF (*((volatile unsigned int*)(0x42400290UL))) +#define bM4_SPI3_SR_TDEF (*((volatile unsigned int*)(0x42400294UL))) +#define bM4_SPI3_SR_RDFF (*((volatile unsigned int*)(0x4240029CUL))) +#define bM4_SPI3_CFG2_CPHA (*((volatile unsigned int*)(0x42400300UL))) +#define bM4_SPI3_CFG2_CPOL (*((volatile unsigned int*)(0x42400304UL))) +#define bM4_SPI3_CFG2_MBR0 (*((volatile unsigned int*)(0x42400308UL))) +#define bM4_SPI3_CFG2_MBR1 (*((volatile unsigned int*)(0x4240030CUL))) +#define bM4_SPI3_CFG2_MBR2 (*((volatile unsigned int*)(0x42400310UL))) +#define bM4_SPI3_CFG2_SSA0 (*((volatile unsigned int*)(0x42400314UL))) +#define bM4_SPI3_CFG2_SSA1 (*((volatile unsigned int*)(0x42400318UL))) +#define bM4_SPI3_CFG2_SSA2 (*((volatile unsigned int*)(0x4240031CUL))) +#define bM4_SPI3_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42400320UL))) +#define bM4_SPI3_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42400324UL))) +#define bM4_SPI3_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42400328UL))) +#define bM4_SPI3_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4240032CUL))) +#define bM4_SPI3_CFG2_LSBF (*((volatile unsigned int*)(0x42400330UL))) +#define bM4_SPI3_CFG2_MIDIE (*((volatile unsigned int*)(0x42400334UL))) +#define bM4_SPI3_CFG2_MSSDLE (*((volatile unsigned int*)(0x42400338UL))) +#define bM4_SPI3_CFG2_MSSIE (*((volatile unsigned int*)(0x4240033CUL))) +#define bM4_SPI4_CR1_SPIMDS (*((volatile unsigned int*)(0x42408080UL))) +#define bM4_SPI4_CR1_TXMDS (*((volatile unsigned int*)(0x42408084UL))) +#define bM4_SPI4_CR1_MSTR (*((volatile unsigned int*)(0x4240808CUL))) +#define bM4_SPI4_CR1_SPLPBK (*((volatile unsigned int*)(0x42408090UL))) +#define bM4_SPI4_CR1_SPLPBK2 (*((volatile unsigned int*)(0x42408094UL))) +#define bM4_SPI4_CR1_SPE (*((volatile unsigned int*)(0x42408098UL))) +#define bM4_SPI4_CR1_CSUSPE (*((volatile unsigned int*)(0x4240809CUL))) +#define bM4_SPI4_CR1_EIE (*((volatile unsigned int*)(0x424080A0UL))) +#define bM4_SPI4_CR1_TXIE (*((volatile unsigned int*)(0x424080A4UL))) +#define bM4_SPI4_CR1_RXIE (*((volatile unsigned int*)(0x424080A8UL))) +#define bM4_SPI4_CR1_IDIE (*((volatile unsigned int*)(0x424080ACUL))) +#define bM4_SPI4_CR1_MODFE (*((volatile unsigned int*)(0x424080B0UL))) +#define bM4_SPI4_CR1_PATE (*((volatile unsigned int*)(0x424080B4UL))) +#define bM4_SPI4_CR1_PAOE (*((volatile unsigned int*)(0x424080B8UL))) +#define bM4_SPI4_CR1_PAE (*((volatile unsigned int*)(0x424080BCUL))) +#define bM4_SPI4_CFG1_FTHLV0 (*((volatile unsigned int*)(0x42408180UL))) +#define bM4_SPI4_CFG1_FTHLV1 (*((volatile unsigned int*)(0x42408184UL))) +#define bM4_SPI4_CFG1_SPRDTD (*((volatile unsigned int*)(0x42408198UL))) +#define bM4_SPI4_CFG1_SS0PV (*((volatile unsigned int*)(0x424081A0UL))) +#define bM4_SPI4_CFG1_SS1PV (*((volatile unsigned int*)(0x424081A4UL))) +#define bM4_SPI4_CFG1_SS2PV (*((volatile unsigned int*)(0x424081A8UL))) +#define bM4_SPI4_CFG1_SS3PV (*((volatile unsigned int*)(0x424081ACUL))) +#define bM4_SPI4_CFG1_MSSI0 (*((volatile unsigned int*)(0x424081D0UL))) +#define bM4_SPI4_CFG1_MSSI1 (*((volatile unsigned int*)(0x424081D4UL))) +#define bM4_SPI4_CFG1_MSSI2 (*((volatile unsigned int*)(0x424081D8UL))) +#define bM4_SPI4_CFG1_MSSDL0 (*((volatile unsigned int*)(0x424081E0UL))) +#define bM4_SPI4_CFG1_MSSDL1 (*((volatile unsigned int*)(0x424081E4UL))) +#define bM4_SPI4_CFG1_MSSDL2 (*((volatile unsigned int*)(0x424081E8UL))) +#define bM4_SPI4_CFG1_MIDI0 (*((volatile unsigned int*)(0x424081F0UL))) +#define bM4_SPI4_CFG1_MIDI1 (*((volatile unsigned int*)(0x424081F4UL))) +#define bM4_SPI4_CFG1_MIDI2 (*((volatile unsigned int*)(0x424081F8UL))) +#define bM4_SPI4_SR_OVRERF (*((volatile unsigned int*)(0x42408280UL))) +#define bM4_SPI4_SR_IDLNF (*((volatile unsigned int*)(0x42408284UL))) +#define bM4_SPI4_SR_MODFERF (*((volatile unsigned int*)(0x42408288UL))) +#define bM4_SPI4_SR_PERF (*((volatile unsigned int*)(0x4240828CUL))) +#define bM4_SPI4_SR_UDRERF (*((volatile unsigned int*)(0x42408290UL))) +#define bM4_SPI4_SR_TDEF (*((volatile unsigned int*)(0x42408294UL))) +#define bM4_SPI4_SR_RDFF (*((volatile unsigned int*)(0x4240829CUL))) +#define bM4_SPI4_CFG2_CPHA (*((volatile unsigned int*)(0x42408300UL))) +#define bM4_SPI4_CFG2_CPOL (*((volatile unsigned int*)(0x42408304UL))) +#define bM4_SPI4_CFG2_MBR0 (*((volatile unsigned int*)(0x42408308UL))) +#define bM4_SPI4_CFG2_MBR1 (*((volatile unsigned int*)(0x4240830CUL))) +#define bM4_SPI4_CFG2_MBR2 (*((volatile unsigned int*)(0x42408310UL))) +#define bM4_SPI4_CFG2_SSA0 (*((volatile unsigned int*)(0x42408314UL))) +#define bM4_SPI4_CFG2_SSA1 (*((volatile unsigned int*)(0x42408318UL))) +#define bM4_SPI4_CFG2_SSA2 (*((volatile unsigned int*)(0x4240831CUL))) +#define bM4_SPI4_CFG2_DSIZE0 (*((volatile unsigned int*)(0x42408320UL))) +#define bM4_SPI4_CFG2_DSIZE1 (*((volatile unsigned int*)(0x42408324UL))) +#define bM4_SPI4_CFG2_DSIZE2 (*((volatile unsigned int*)(0x42408328UL))) +#define bM4_SPI4_CFG2_DSIZE3 (*((volatile unsigned int*)(0x4240832CUL))) +#define bM4_SPI4_CFG2_LSBF (*((volatile unsigned int*)(0x42408330UL))) +#define bM4_SPI4_CFG2_MIDIE (*((volatile unsigned int*)(0x42408334UL))) +#define bM4_SPI4_CFG2_MSSDLE (*((volatile unsigned int*)(0x42408338UL))) +#define bM4_SPI4_CFG2_MSSIE (*((volatile unsigned int*)(0x4240833CUL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT0 (*((volatile unsigned int*)(0x42A10000UL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT1 (*((volatile unsigned int*)(0x42A10004UL))) +#define bM4_SRAMC_WTCR_SRAM12_RWT2 (*((volatile unsigned int*)(0x42A10008UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT0 (*((volatile unsigned int*)(0x42A10010UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT1 (*((volatile unsigned int*)(0x42A10014UL))) +#define bM4_SRAMC_WTCR_SRAM12_WWT2 (*((volatile unsigned int*)(0x42A10018UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT0 (*((volatile unsigned int*)(0x42A10020UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT1 (*((volatile unsigned int*)(0x42A10024UL))) +#define bM4_SRAMC_WTCR_SRAM3_RWT2 (*((volatile unsigned int*)(0x42A10028UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT0 (*((volatile unsigned int*)(0x42A10030UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT1 (*((volatile unsigned int*)(0x42A10034UL))) +#define bM4_SRAMC_WTCR_SRAM3_WWT2 (*((volatile unsigned int*)(0x42A10038UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT0 (*((volatile unsigned int*)(0x42A10040UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT1 (*((volatile unsigned int*)(0x42A10044UL))) +#define bM4_SRAMC_WTCR_SRAMH_RWT2 (*((volatile unsigned int*)(0x42A10048UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT0 (*((volatile unsigned int*)(0x42A10050UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT1 (*((volatile unsigned int*)(0x42A10054UL))) +#define bM4_SRAMC_WTCR_SRAMH_WWT2 (*((volatile unsigned int*)(0x42A10058UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT0 (*((volatile unsigned int*)(0x42A10060UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT1 (*((volatile unsigned int*)(0x42A10064UL))) +#define bM4_SRAMC_WTCR_SRAMR_RWT2 (*((volatile unsigned int*)(0x42A10068UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT0 (*((volatile unsigned int*)(0x42A10070UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT1 (*((volatile unsigned int*)(0x42A10074UL))) +#define bM4_SRAMC_WTCR_SRAMR_WWT2 (*((volatile unsigned int*)(0x42A10078UL))) +#define bM4_SRAMC_WTPR_WTPRC (*((volatile unsigned int*)(0x42A10080UL))) +#define bM4_SRAMC_WTPR_WTPRKW0 (*((volatile unsigned int*)(0x42A10084UL))) +#define bM4_SRAMC_WTPR_WTPRKW1 (*((volatile unsigned int*)(0x42A10088UL))) +#define bM4_SRAMC_WTPR_WTPRKW2 (*((volatile unsigned int*)(0x42A1008CUL))) +#define bM4_SRAMC_WTPR_WTPRKW3 (*((volatile unsigned int*)(0x42A10090UL))) +#define bM4_SRAMC_WTPR_WTPRKW4 (*((volatile unsigned int*)(0x42A10094UL))) +#define bM4_SRAMC_WTPR_WTPRKW5 (*((volatile unsigned int*)(0x42A10098UL))) +#define bM4_SRAMC_WTPR_WTPRKW6 (*((volatile unsigned int*)(0x42A1009CUL))) +#define bM4_SRAMC_CKCR_PYOAD (*((volatile unsigned int*)(0x42A10100UL))) +#define bM4_SRAMC_CKCR_ECCOAD (*((volatile unsigned int*)(0x42A10140UL))) +#define bM4_SRAMC_CKCR_ECCMOD0 (*((volatile unsigned int*)(0x42A10160UL))) +#define bM4_SRAMC_CKCR_ECCMOD1 (*((volatile unsigned int*)(0x42A10164UL))) +#define bM4_SRAMC_CKPR_CKPRC (*((volatile unsigned int*)(0x42A10180UL))) +#define bM4_SRAMC_CKPR_CKPRKW0 (*((volatile unsigned int*)(0x42A10184UL))) +#define bM4_SRAMC_CKPR_CKPRKW1 (*((volatile unsigned int*)(0x42A10188UL))) +#define bM4_SRAMC_CKPR_CKPRKW2 (*((volatile unsigned int*)(0x42A1018CUL))) +#define bM4_SRAMC_CKPR_CKPRKW3 (*((volatile unsigned int*)(0x42A10190UL))) +#define bM4_SRAMC_CKPR_CKPRKW4 (*((volatile unsigned int*)(0x42A10194UL))) +#define bM4_SRAMC_CKPR_CKPRKW5 (*((volatile unsigned int*)(0x42A10198UL))) +#define bM4_SRAMC_CKPR_CKPRKW6 (*((volatile unsigned int*)(0x42A1019CUL))) +#define bM4_SRAMC_CKSR_SRAM3_1ERR (*((volatile unsigned int*)(0x42A10200UL))) +#define bM4_SRAMC_CKSR_SRAM3_2ERR (*((volatile unsigned int*)(0x42A10204UL))) +#define bM4_SRAMC_CKSR_SRAM12_PYERR (*((volatile unsigned int*)(0x42A10208UL))) +#define bM4_SRAMC_CKSR_SRAMH_PYERR (*((volatile unsigned int*)(0x42A1020CUL))) +#define bM4_SRAMC_CKSR_SRAMR_PYERR (*((volatile unsigned int*)(0x42A10210UL))) +#define bM4_SWDT_SR_CNT0 (*((volatile unsigned int*)(0x42928080UL))) +#define bM4_SWDT_SR_CNT1 (*((volatile unsigned int*)(0x42928084UL))) +#define bM4_SWDT_SR_CNT2 (*((volatile unsigned int*)(0x42928088UL))) +#define bM4_SWDT_SR_CNT3 (*((volatile unsigned int*)(0x4292808CUL))) +#define bM4_SWDT_SR_CNT4 (*((volatile unsigned int*)(0x42928090UL))) +#define bM4_SWDT_SR_CNT5 (*((volatile unsigned int*)(0x42928094UL))) +#define bM4_SWDT_SR_CNT6 (*((volatile unsigned int*)(0x42928098UL))) +#define bM4_SWDT_SR_CNT7 (*((volatile unsigned int*)(0x4292809CUL))) +#define bM4_SWDT_SR_CNT8 (*((volatile unsigned int*)(0x429280A0UL))) +#define bM4_SWDT_SR_CNT9 (*((volatile unsigned int*)(0x429280A4UL))) +#define bM4_SWDT_SR_CNT10 (*((volatile unsigned int*)(0x429280A8UL))) +#define bM4_SWDT_SR_CNT11 (*((volatile unsigned int*)(0x429280ACUL))) +#define bM4_SWDT_SR_CNT12 (*((volatile unsigned int*)(0x429280B0UL))) +#define bM4_SWDT_SR_CNT13 (*((volatile unsigned int*)(0x429280B4UL))) +#define bM4_SWDT_SR_CNT14 (*((volatile unsigned int*)(0x429280B8UL))) +#define bM4_SWDT_SR_CNT15 (*((volatile unsigned int*)(0x429280BCUL))) +#define bM4_SWDT_SR_UDF (*((volatile unsigned int*)(0x429280C0UL))) +#define bM4_SWDT_SR_REF (*((volatile unsigned int*)(0x429280C4UL))) +#define bM4_SWDT_RR_RF0 (*((volatile unsigned int*)(0x42928100UL))) +#define bM4_SWDT_RR_RF1 (*((volatile unsigned int*)(0x42928104UL))) +#define bM4_SWDT_RR_RF2 (*((volatile unsigned int*)(0x42928108UL))) +#define bM4_SWDT_RR_RF3 (*((volatile unsigned int*)(0x4292810CUL))) +#define bM4_SWDT_RR_RF4 (*((volatile unsigned int*)(0x42928110UL))) +#define bM4_SWDT_RR_RF5 (*((volatile unsigned int*)(0x42928114UL))) +#define bM4_SWDT_RR_RF6 (*((volatile unsigned int*)(0x42928118UL))) +#define bM4_SWDT_RR_RF7 (*((volatile unsigned int*)(0x4292811CUL))) +#define bM4_SWDT_RR_RF8 (*((volatile unsigned int*)(0x42928120UL))) +#define bM4_SWDT_RR_RF9 (*((volatile unsigned int*)(0x42928124UL))) +#define bM4_SWDT_RR_RF10 (*((volatile unsigned int*)(0x42928128UL))) +#define bM4_SWDT_RR_RF11 (*((volatile unsigned int*)(0x4292812CUL))) +#define bM4_SWDT_RR_RF12 (*((volatile unsigned int*)(0x42928130UL))) +#define bM4_SWDT_RR_RF13 (*((volatile unsigned int*)(0x42928134UL))) +#define bM4_SWDT_RR_RF14 (*((volatile unsigned int*)(0x42928138UL))) +#define bM4_SWDT_RR_RF15 (*((volatile unsigned int*)(0x4292813CUL))) +#define bM4_SYSREG_PWR_STPMCR_FLNWT (*((volatile unsigned int*)(0x42A80180UL))) +#define bM4_SYSREG_PWR_STPMCR_CKSMRC (*((volatile unsigned int*)(0x42A80184UL))) +#define bM4_SYSREG_PWR_STPMCR_STOP (*((volatile unsigned int*)(0x42A801BCUL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL0 (*((volatile unsigned int*)(0x42A80200UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL1 (*((volatile unsigned int*)(0x42A80204UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL2 (*((volatile unsigned int*)(0x42A80208UL))) +#define bM4_SYSREG_CMU_PERICKSEL_PERICKSEL3 (*((volatile unsigned int*)(0x42A8020CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL0 (*((volatile unsigned int*)(0x42A80240UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL1 (*((volatile unsigned int*)(0x42A80244UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL2 (*((volatile unsigned int*)(0x42A80248UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S1CKSEL3 (*((volatile unsigned int*)(0x42A8024CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL0 (*((volatile unsigned int*)(0x42A80250UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL1 (*((volatile unsigned int*)(0x42A80254UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL2 (*((volatile unsigned int*)(0x42A80258UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S2CKSEL3 (*((volatile unsigned int*)(0x42A8025CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL0 (*((volatile unsigned int*)(0x42A80260UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL1 (*((volatile unsigned int*)(0x42A80264UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL2 (*((volatile unsigned int*)(0x42A80268UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S3CKSEL3 (*((volatile unsigned int*)(0x42A8026CUL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL0 (*((volatile unsigned int*)(0x42A80270UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL1 (*((volatile unsigned int*)(0x42A80274UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL2 (*((volatile unsigned int*)(0x42A80278UL))) +#define bM4_SYSREG_CMU_I2SCKSEL_I2S4CKSEL3 (*((volatile unsigned int*)(0x42A8027CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC0 (*((volatile unsigned int*)(0x42A80280UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC1 (*((volatile unsigned int*)(0x42A80284UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC2 (*((volatile unsigned int*)(0x42A80288UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC3 (*((volatile unsigned int*)(0x42A8028CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC4 (*((volatile unsigned int*)(0x42A80290UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC5 (*((volatile unsigned int*)(0x42A80294UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC6 (*((volatile unsigned int*)(0x42A80298UL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC7 (*((volatile unsigned int*)(0x42A8029CUL))) +#define bM4_SYSREG_PWR_RAMPC0_RAMPDC8 (*((volatile unsigned int*)(0x42A802A0UL))) +#define bM4_SYSREG_MPU_IPPR_AESRDP (*((volatile unsigned int*)(0x42A80380UL))) +#define bM4_SYSREG_MPU_IPPR_AESWRP (*((volatile unsigned int*)(0x42A80384UL))) +#define bM4_SYSREG_MPU_IPPR_HASHRDP (*((volatile unsigned int*)(0x42A80388UL))) +#define bM4_SYSREG_MPU_IPPR_HASHWRP (*((volatile unsigned int*)(0x42A8038CUL))) +#define bM4_SYSREG_MPU_IPPR_TRNGRDP (*((volatile unsigned int*)(0x42A80390UL))) +#define bM4_SYSREG_MPU_IPPR_TRNGWRP (*((volatile unsigned int*)(0x42A80394UL))) +#define bM4_SYSREG_MPU_IPPR_CRCRDP (*((volatile unsigned int*)(0x42A80398UL))) +#define bM4_SYSREG_MPU_IPPR_CRCWRP (*((volatile unsigned int*)(0x42A8039CUL))) +#define bM4_SYSREG_MPU_IPPR_FMCRDP (*((volatile unsigned int*)(0x42A803A0UL))) +#define bM4_SYSREG_MPU_IPPR_FMCWRP (*((volatile unsigned int*)(0x42A803A4UL))) +#define bM4_SYSREG_MPU_IPPR_WDTRDP (*((volatile unsigned int*)(0x42A803B0UL))) +#define bM4_SYSREG_MPU_IPPR_WDTWRP (*((volatile unsigned int*)(0x42A803B4UL))) +#define bM4_SYSREG_MPU_IPPR_SWDTRDP (*((volatile unsigned int*)(0x42A803B8UL))) +#define bM4_SYSREG_MPU_IPPR_SWDTWRP (*((volatile unsigned int*)(0x42A803BCUL))) +#define bM4_SYSREG_MPU_IPPR_BKSRAMRDP (*((volatile unsigned int*)(0x42A803C0UL))) +#define bM4_SYSREG_MPU_IPPR_BKSRAMWRP (*((volatile unsigned int*)(0x42A803C4UL))) +#define bM4_SYSREG_MPU_IPPR_RTCRDP (*((volatile unsigned int*)(0x42A803C8UL))) +#define bM4_SYSREG_MPU_IPPR_RTCWRP (*((volatile unsigned int*)(0x42A803CCUL))) +#define bM4_SYSREG_MPU_IPPR_DMPURDP (*((volatile unsigned int*)(0x42A803D0UL))) +#define bM4_SYSREG_MPU_IPPR_DMPUWRP (*((volatile unsigned int*)(0x42A803D4UL))) +#define bM4_SYSREG_MPU_IPPR_SRAMCRDP (*((volatile unsigned int*)(0x42A803D8UL))) +#define bM4_SYSREG_MPU_IPPR_SRAMCWRP (*((volatile unsigned int*)(0x42A803DCUL))) +#define bM4_SYSREG_MPU_IPPR_INTCRDP (*((volatile unsigned int*)(0x42A803E0UL))) +#define bM4_SYSREG_MPU_IPPR_INTCWRP (*((volatile unsigned int*)(0x42A803E4UL))) +#define bM4_SYSREG_MPU_IPPR_SYSCRDP (*((volatile unsigned int*)(0x42A803E8UL))) +#define bM4_SYSREG_MPU_IPPR_SYSCWRP (*((volatile unsigned int*)(0x42A803ECUL))) +#define bM4_SYSREG_MPU_IPPR_MSTPRDP (*((volatile unsigned int*)(0x42A803F0UL))) +#define bM4_SYSREG_MPU_IPPR_MSTPWRP (*((volatile unsigned int*)(0x42A803F4UL))) +#define bM4_SYSREG_MPU_IPPR_BUSERRE (*((volatile unsigned int*)(0x42A803FCUL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S0 (*((volatile unsigned int*)(0x42A80400UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S1 (*((volatile unsigned int*)(0x42A80404UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK0S2 (*((volatile unsigned int*)(0x42A80408UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S0 (*((volatile unsigned int*)(0x42A80410UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S1 (*((volatile unsigned int*)(0x42A80414UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK1S2 (*((volatile unsigned int*)(0x42A80418UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S0 (*((volatile unsigned int*)(0x42A80420UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S1 (*((volatile unsigned int*)(0x42A80424UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK2S2 (*((volatile unsigned int*)(0x42A80428UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S0 (*((volatile unsigned int*)(0x42A80430UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S1 (*((volatile unsigned int*)(0x42A80434UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK3S2 (*((volatile unsigned int*)(0x42A80438UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S0 (*((volatile unsigned int*)(0x42A80440UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S1 (*((volatile unsigned int*)(0x42A80444UL))) +#define bM4_SYSREG_CMU_SCFGR_PCLK4S2 (*((volatile unsigned int*)(0x42A80448UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS0 (*((volatile unsigned int*)(0x42A80450UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS1 (*((volatile unsigned int*)(0x42A80454UL))) +#define bM4_SYSREG_CMU_SCFGR_EXCKS2 (*((volatile unsigned int*)(0x42A80458UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS0 (*((volatile unsigned int*)(0x42A80460UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS1 (*((volatile unsigned int*)(0x42A80464UL))) +#define bM4_SYSREG_CMU_SCFGR_HCLKS2 (*((volatile unsigned int*)(0x42A80468UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS0 (*((volatile unsigned int*)(0x42A80490UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS1 (*((volatile unsigned int*)(0x42A80494UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS2 (*((volatile unsigned int*)(0x42A80498UL))) +#define bM4_SYSREG_CMU_UFSCKCFGR_USBCKS3 (*((volatile unsigned int*)(0x42A8049CUL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW0 (*((volatile unsigned int*)(0x42A804C0UL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW1 (*((volatile unsigned int*)(0x42A804C4UL))) +#define bM4_SYSREG_CMU_CKSWR_CKSW2 (*((volatile unsigned int*)(0x42A804C8UL))) +#define bM4_SYSREG_CMU_PLLCR_MPLLOFF (*((volatile unsigned int*)(0x42A80540UL))) +#define bM4_SYSREG_CMU_UPLLCR_UPLLOFF (*((volatile unsigned int*)(0x42A805C0UL))) +#define bM4_SYSREG_CMU_XTALCR_XTALSTP (*((volatile unsigned int*)(0x42A80640UL))) +#define bM4_SYSREG_CMU_HRCCR_HRCSTP (*((volatile unsigned int*)(0x42A806C0UL))) +#define bM4_SYSREG_CMU_MRCCR_MRCSTP (*((volatile unsigned int*)(0x42A80700UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_HRCSTBF (*((volatile unsigned int*)(0x42A80780UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_XTALSTBF (*((volatile unsigned int*)(0x42A8078CUL))) +#define bM4_SYSREG_CMU_OSCSTBSR_MPLLSTBF (*((volatile unsigned int*)(0x42A80794UL))) +#define bM4_SYSREG_CMU_OSCSTBSR_UPLLSTBF (*((volatile unsigned int*)(0x42A80798UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL0 (*((volatile unsigned int*)(0x42A807A0UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL1 (*((volatile unsigned int*)(0x42A807A4UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL2 (*((volatile unsigned int*)(0x42A807A8UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1SEL3 (*((volatile unsigned int*)(0x42A807ACUL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV0 (*((volatile unsigned int*)(0x42A807B0UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV1 (*((volatile unsigned int*)(0x42A807B4UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1DIV2 (*((volatile unsigned int*)(0x42A807B8UL))) +#define bM4_SYSREG_CMU_MCO1CFGR_MCO1EN (*((volatile unsigned int*)(0x42A807BCUL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL0 (*((volatile unsigned int*)(0x42A807C0UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL1 (*((volatile unsigned int*)(0x42A807C4UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL2 (*((volatile unsigned int*)(0x42A807C8UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2SEL3 (*((volatile unsigned int*)(0x42A807CCUL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV0 (*((volatile unsigned int*)(0x42A807D0UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV1 (*((volatile unsigned int*)(0x42A807D4UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2DIV2 (*((volatile unsigned int*)(0x42A807D8UL))) +#define bM4_SYSREG_CMU_MCO2CFGR_MCO2EN (*((volatile unsigned int*)(0x42A807DCUL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKS0 (*((volatile unsigned int*)(0x42A807E0UL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKS1 (*((volatile unsigned int*)(0x42A807E4UL))) +#define bM4_SYSREG_CMU_TPIUCKCFGR_TPIUCKOE (*((volatile unsigned int*)(0x42A807FCUL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDIE (*((volatile unsigned int*)(0x42A80800UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDRE (*((volatile unsigned int*)(0x42A80804UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDRIS (*((volatile unsigned int*)(0x42A80808UL))) +#define bM4_SYSREG_CMU_XTALSTDCR_XTALSTDE (*((volatile unsigned int*)(0x42A8081CUL))) +#define bM4_SYSREG_CMU_XTALSTDSR_XTALSTDF (*((volatile unsigned int*)(0x42A80820UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB0 (*((volatile unsigned int*)(0x42A81440UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB1 (*((volatile unsigned int*)(0x42A81444UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB2 (*((volatile unsigned int*)(0x42A81448UL))) +#define bM4_SYSREG_CMU_XTALSTBCR_XTALSTB3 (*((volatile unsigned int*)(0x42A8144CUL))) +#define bM4_SYSREG_RMU_RSTF0_PORF (*((volatile unsigned int*)(0x42A81800UL))) +#define bM4_SYSREG_RMU_RSTF0_PINRF (*((volatile unsigned int*)(0x42A81804UL))) +#define bM4_SYSREG_RMU_RSTF0_BORF (*((volatile unsigned int*)(0x42A81808UL))) +#define bM4_SYSREG_RMU_RSTF0_PVD1RF (*((volatile unsigned int*)(0x42A8180CUL))) +#define bM4_SYSREG_RMU_RSTF0_PVD2RF (*((volatile unsigned int*)(0x42A81810UL))) +#define bM4_SYSREG_RMU_RSTF0_WDRF (*((volatile unsigned int*)(0x42A81814UL))) +#define bM4_SYSREG_RMU_RSTF0_SWDRF (*((volatile unsigned int*)(0x42A81818UL))) +#define bM4_SYSREG_RMU_RSTF0_PDRF (*((volatile unsigned int*)(0x42A8181CUL))) +#define bM4_SYSREG_RMU_RSTF0_SWRF (*((volatile unsigned int*)(0x42A81820UL))) +#define bM4_SYSREG_RMU_RSTF0_MPUERF (*((volatile unsigned int*)(0x42A81824UL))) +#define bM4_SYSREG_RMU_RSTF0_RAPERF (*((volatile unsigned int*)(0x42A81828UL))) +#define bM4_SYSREG_RMU_RSTF0_RAECRF (*((volatile unsigned int*)(0x42A8182CUL))) +#define bM4_SYSREG_RMU_RSTF0_CKFERF (*((volatile unsigned int*)(0x42A81830UL))) +#define bM4_SYSREG_RMU_RSTF0_XTALERF (*((volatile unsigned int*)(0x42A81834UL))) +#define bM4_SYSREG_RMU_RSTF0_MULTIRF (*((volatile unsigned int*)(0x42A81838UL))) +#define bM4_SYSREG_RMU_RSTF0_CLRF (*((volatile unsigned int*)(0x42A8183CUL))) +#define bM4_SYSREG_PWR_PVDICR_PVD1NMIS (*((volatile unsigned int*)(0x42A81C00UL))) +#define bM4_SYSREG_PWR_PVDICR_PVD2NMIS (*((volatile unsigned int*)(0x42A81C10UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD1MON (*((volatile unsigned int*)(0x42A81C20UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD1DETFLG (*((volatile unsigned int*)(0x42A81C24UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD2MON (*((volatile unsigned int*)(0x42A81C30UL))) +#define bM4_SYSREG_PWR_PVDDSR_PVD2DETFLG (*((volatile unsigned int*)(0x42A81C34UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM0 (*((volatile unsigned int*)(0x42A82000UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM1 (*((volatile unsigned int*)(0x42A82004UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM2 (*((volatile unsigned int*)(0x42A82008UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM3 (*((volatile unsigned int*)(0x42A8200CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLM4 (*((volatile unsigned int*)(0x42A82010UL))) +#define bM4_SYSREG_CMU_PLLCFGR_PLLSRC (*((volatile unsigned int*)(0x42A8201CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN0 (*((volatile unsigned int*)(0x42A82020UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN1 (*((volatile unsigned int*)(0x42A82024UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN2 (*((volatile unsigned int*)(0x42A82028UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN3 (*((volatile unsigned int*)(0x42A8202CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN4 (*((volatile unsigned int*)(0x42A82030UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN5 (*((volatile unsigned int*)(0x42A82034UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN6 (*((volatile unsigned int*)(0x42A82038UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN7 (*((volatile unsigned int*)(0x42A8203CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLN8 (*((volatile unsigned int*)(0x42A82040UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR0 (*((volatile unsigned int*)(0x42A82050UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR1 (*((volatile unsigned int*)(0x42A82054UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR2 (*((volatile unsigned int*)(0x42A82058UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLR3 (*((volatile unsigned int*)(0x42A8205CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ0 (*((volatile unsigned int*)(0x42A82060UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ1 (*((volatile unsigned int*)(0x42A82064UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ2 (*((volatile unsigned int*)(0x42A82068UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLQ3 (*((volatile unsigned int*)(0x42A8206CUL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP0 (*((volatile unsigned int*)(0x42A82070UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP1 (*((volatile unsigned int*)(0x42A82074UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP2 (*((volatile unsigned int*)(0x42A82078UL))) +#define bM4_SYSREG_CMU_PLLCFGR_MPLLP3 (*((volatile unsigned int*)(0x42A8207CUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM0 (*((volatile unsigned int*)(0x42A82080UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM1 (*((volatile unsigned int*)(0x42A82084UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM2 (*((volatile unsigned int*)(0x42A82088UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM3 (*((volatile unsigned int*)(0x42A8208CUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLM4 (*((volatile unsigned int*)(0x42A82090UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN0 (*((volatile unsigned int*)(0x42A820A0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN1 (*((volatile unsigned int*)(0x42A820A4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN2 (*((volatile unsigned int*)(0x42A820A8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN3 (*((volatile unsigned int*)(0x42A820ACUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN4 (*((volatile unsigned int*)(0x42A820B0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN5 (*((volatile unsigned int*)(0x42A820B4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN6 (*((volatile unsigned int*)(0x42A820B8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN7 (*((volatile unsigned int*)(0x42A820BCUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLN8 (*((volatile unsigned int*)(0x42A820C0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR0 (*((volatile unsigned int*)(0x42A820D0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR1 (*((volatile unsigned int*)(0x42A820D4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR2 (*((volatile unsigned int*)(0x42A820D8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLR3 (*((volatile unsigned int*)(0x42A820DCUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ0 (*((volatile unsigned int*)(0x42A820E0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ1 (*((volatile unsigned int*)(0x42A820E4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ2 (*((volatile unsigned int*)(0x42A820E8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLQ3 (*((volatile unsigned int*)(0x42A820ECUL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP0 (*((volatile unsigned int*)(0x42A820F0UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP1 (*((volatile unsigned int*)(0x42A820F4UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP2 (*((volatile unsigned int*)(0x42A820F8UL))) +#define bM4_SYSREG_CMU_UPLLCFGR_UPLLP3 (*((volatile unsigned int*)(0x42A820FCUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB0 (*((volatile unsigned int*)(0x42A87FC0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB1 (*((volatile unsigned int*)(0x42A87FC4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB2 (*((volatile unsigned int*)(0x42A87FC8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCB3 (*((volatile unsigned int*)(0x42A87FCCUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE0 (*((volatile unsigned int*)(0x42A87FE0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE1 (*((volatile unsigned int*)(0x42A87FE4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE2 (*((volatile unsigned int*)(0x42A87FE8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE3 (*((volatile unsigned int*)(0x42A87FECUL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE4 (*((volatile unsigned int*)(0x42A87FF0UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE5 (*((volatile unsigned int*)(0x42A87FF4UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE6 (*((volatile unsigned int*)(0x42A87FF8UL))) +#define bM4_SYSREG_PWR_FPRC_FPRCWE7 (*((volatile unsigned int*)(0x42A87FFCUL))) +#define bM4_SYSREG_PWR_PWRC0_PDMDS0 (*((volatile unsigned int*)(0x42A88000UL))) +#define bM4_SYSREG_PWR_PWRC0_PDMDS1 (*((volatile unsigned int*)(0x42A88004UL))) +#define bM4_SYSREG_PWR_PWRC0_VVDRSD (*((volatile unsigned int*)(0x42A88008UL))) +#define bM4_SYSREG_PWR_PWRC0_RETRAMSD (*((volatile unsigned int*)(0x42A8800CUL))) +#define bM4_SYSREG_PWR_PWRC0_IORTN0 (*((volatile unsigned int*)(0x42A88010UL))) +#define bM4_SYSREG_PWR_PWRC0_IORTN1 (*((volatile unsigned int*)(0x42A88014UL))) +#define bM4_SYSREG_PWR_PWRC0_PWDN (*((volatile unsigned int*)(0x42A8801CUL))) +#define bM4_SYSREG_PWR_PWRC1_VPLLSD (*((volatile unsigned int*)(0x42A88020UL))) +#define bM4_SYSREG_PWR_PWRC1_VHRCSD (*((volatile unsigned int*)(0x42A88024UL))) +#define bM4_SYSREG_PWR_PWRC1_STPDAS0 (*((volatile unsigned int*)(0x42A88038UL))) +#define bM4_SYSREG_PWR_PWRC1_STPDAS1 (*((volatile unsigned int*)(0x42A8803CUL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS0 (*((volatile unsigned int*)(0x42A88040UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS1 (*((volatile unsigned int*)(0x42A88044UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS2 (*((volatile unsigned int*)(0x42A88048UL))) +#define bM4_SYSREG_PWR_PWRC2_DDAS3 (*((volatile unsigned int*)(0x42A8804CUL))) +#define bM4_SYSREG_PWR_PWRC2_DVS0 (*((volatile unsigned int*)(0x42A88050UL))) +#define bM4_SYSREG_PWR_PWRC2_DVS1 (*((volatile unsigned int*)(0x42A88054UL))) +#define bM4_SYSREG_PWR_PWRC3_PDTS (*((volatile unsigned int*)(0x42A88068UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE00 (*((volatile unsigned int*)(0x42A88080UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE01 (*((volatile unsigned int*)(0x42A88084UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE02 (*((volatile unsigned int*)(0x42A88088UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE03 (*((volatile unsigned int*)(0x42A8808CUL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE10 (*((volatile unsigned int*)(0x42A88090UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE11 (*((volatile unsigned int*)(0x42A88094UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE12 (*((volatile unsigned int*)(0x42A88098UL))) +#define bM4_SYSREG_PWR_PDWKE0_WKE13 (*((volatile unsigned int*)(0x42A8809CUL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE20 (*((volatile unsigned int*)(0x42A880A0UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE21 (*((volatile unsigned int*)(0x42A880A4UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE22 (*((volatile unsigned int*)(0x42A880A8UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE23 (*((volatile unsigned int*)(0x42A880ACUL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE30 (*((volatile unsigned int*)(0x42A880B0UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE31 (*((volatile unsigned int*)(0x42A880B4UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE32 (*((volatile unsigned int*)(0x42A880B8UL))) +#define bM4_SYSREG_PWR_PDWKE1_WKE33 (*((volatile unsigned int*)(0x42A880BCUL))) +#define bM4_SYSREG_PWR_PDWKE2_VD1WKE (*((volatile unsigned int*)(0x42A880C0UL))) +#define bM4_SYSREG_PWR_PDWKE2_VD2WKE (*((volatile unsigned int*)(0x42A880C4UL))) +#define bM4_SYSREG_PWR_PDWKE2_NMIWKE (*((volatile unsigned int*)(0x42A880C8UL))) +#define bM4_SYSREG_PWR_PDWKE2_RTCPRDWKE (*((volatile unsigned int*)(0x42A880D0UL))) +#define bM4_SYSREG_PWR_PDWKE2_RTCALMWKE (*((volatile unsigned int*)(0x42A880D4UL))) +#define bM4_SYSREG_PWR_PDWKE2_WKTMWKE (*((volatile unsigned int*)(0x42A880DCUL))) +#define bM4_SYSREG_PWR_PDWKES_WK0EGS (*((volatile unsigned int*)(0x42A880E0UL))) +#define bM4_SYSREG_PWR_PDWKES_WK1EGS (*((volatile unsigned int*)(0x42A880E4UL))) +#define bM4_SYSREG_PWR_PDWKES_WK2EGS (*((volatile unsigned int*)(0x42A880E8UL))) +#define bM4_SYSREG_PWR_PDWKES_WK3EGS (*((volatile unsigned int*)(0x42A880ECUL))) +#define bM4_SYSREG_PWR_PDWKES_VD1EGS (*((volatile unsigned int*)(0x42A880F0UL))) +#define bM4_SYSREG_PWR_PDWKES_VD2EGS (*((volatile unsigned int*)(0x42A880F4UL))) +#define bM4_SYSREG_PWR_PDWKES_NMIEGS (*((volatile unsigned int*)(0x42A880F8UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK0F (*((volatile unsigned int*)(0x42A88100UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK1F (*((volatile unsigned int*)(0x42A88104UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK2F (*((volatile unsigned int*)(0x42A88108UL))) +#define bM4_SYSREG_PWR_PDWKF0_PTWK3F (*((volatile unsigned int*)(0x42A8810CUL))) +#define bM4_SYSREG_PWR_PDWKF0_VD1WKF (*((volatile unsigned int*)(0x42A88110UL))) +#define bM4_SYSREG_PWR_PDWKF0_VD2WKF (*((volatile unsigned int*)(0x42A88114UL))) +#define bM4_SYSREG_PWR_PDWKF0_NMIWKF (*((volatile unsigned int*)(0x42A88118UL))) +#define bM4_SYSREG_PWR_PDWKF1_RTCPRDWKF (*((volatile unsigned int*)(0x42A88130UL))) +#define bM4_SYSREG_PWR_PDWKF1_RTCALMWKF (*((volatile unsigned int*)(0x42A88134UL))) +#define bM4_SYSREG_PWR_PDWKF1_WKTMWKF (*((volatile unsigned int*)(0x42A8813CUL))) +#define bM4_SYSREG_PWR_PWCMR_ADBUFE (*((volatile unsigned int*)(0x42A8815CUL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALDRV0 (*((volatile unsigned int*)(0x42A88210UL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALDRV1 (*((volatile unsigned int*)(0x42A88214UL))) +#define bM4_SYSREG_CMU_XTALCFGR_XTALMS (*((volatile unsigned int*)(0x42A88218UL))) +#define bM4_SYSREG_CMU_XTALCFGR_SUPDRV (*((volatile unsigned int*)(0x42A8821CUL))) +#define bM4_SYSREG_PWR_PVDCR0_EXVCCINEN (*((volatile unsigned int*)(0x42A88240UL))) +#define bM4_SYSREG_PWR_PVDCR0_PVD1EN (*((volatile unsigned int*)(0x42A88254UL))) +#define bM4_SYSREG_PWR_PVDCR0_PVD2EN (*((volatile unsigned int*)(0x42A88258UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1IRE (*((volatile unsigned int*)(0x42A88260UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1IRS (*((volatile unsigned int*)(0x42A88264UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD1CMPOE (*((volatile unsigned int*)(0x42A88268UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2IRE (*((volatile unsigned int*)(0x42A88270UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2IRS (*((volatile unsigned int*)(0x42A88274UL))) +#define bM4_SYSREG_PWR_PVDCR1_PVD2CMPOE (*((volatile unsigned int*)(0x42A88278UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFDIS (*((volatile unsigned int*)(0x42A88280UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFCKS0 (*((volatile unsigned int*)(0x42A88284UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD1NFCKS1 (*((volatile unsigned int*)(0x42A88288UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFDIS (*((volatile unsigned int*)(0x42A88290UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFCKS0 (*((volatile unsigned int*)(0x42A88294UL))) +#define bM4_SYSREG_PWR_PVDFCR_PVD2NFCKS1 (*((volatile unsigned int*)(0x42A88298UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL0 (*((volatile unsigned int*)(0x42A882A0UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL1 (*((volatile unsigned int*)(0x42A882A4UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD1LVL2 (*((volatile unsigned int*)(0x42A882A8UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL0 (*((volatile unsigned int*)(0x42A882B0UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL1 (*((volatile unsigned int*)(0x42A882B4UL))) +#define bM4_SYSREG_PWR_PVDLCR_PVD2LVL2 (*((volatile unsigned int*)(0x42A882B8UL))) +#define bM4_SYSREG_CMU_XTAL32CR_XTAL32STP (*((volatile unsigned int*)(0x42A88400UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV0 (*((volatile unsigned int*)(0x42A88420UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV1 (*((volatile unsigned int*)(0x42A88424UL))) +#define bM4_SYSREG_CMU_XTAL32CFGR_XTAL32DRV2 (*((volatile unsigned int*)(0x42A88428UL))) +#define bM4_SYSREG_CMU_XTAL32NFR_XTAL32NF0 (*((volatile unsigned int*)(0x42A884A0UL))) +#define bM4_SYSREG_CMU_XTAL32NFR_XTAL32NF1 (*((volatile unsigned int*)(0x42A884A4UL))) +#define bM4_SYSREG_CMU_LRCCR_LRCSTP (*((volatile unsigned int*)(0x42A884E0UL))) +#define bM4_SYSREG_PWR_XTAL32CS_CSDIS (*((volatile unsigned int*)(0x42A8857CUL))) +#define bM4_TMR01_CNTAR_CNTA0 (*((volatile unsigned int*)(0x42480000UL))) +#define bM4_TMR01_CNTAR_CNTA1 (*((volatile unsigned int*)(0x42480004UL))) +#define bM4_TMR01_CNTAR_CNTA2 (*((volatile unsigned int*)(0x42480008UL))) +#define bM4_TMR01_CNTAR_CNTA3 (*((volatile unsigned int*)(0x4248000CUL))) +#define bM4_TMR01_CNTAR_CNTA4 (*((volatile unsigned int*)(0x42480010UL))) +#define bM4_TMR01_CNTAR_CNTA5 (*((volatile unsigned int*)(0x42480014UL))) +#define bM4_TMR01_CNTAR_CNTA6 (*((volatile unsigned int*)(0x42480018UL))) +#define bM4_TMR01_CNTAR_CNTA7 (*((volatile unsigned int*)(0x4248001CUL))) +#define bM4_TMR01_CNTAR_CNTA8 (*((volatile unsigned int*)(0x42480020UL))) +#define bM4_TMR01_CNTAR_CNTA9 (*((volatile unsigned int*)(0x42480024UL))) +#define bM4_TMR01_CNTAR_CNTA10 (*((volatile unsigned int*)(0x42480028UL))) +#define bM4_TMR01_CNTAR_CNTA11 (*((volatile unsigned int*)(0x4248002CUL))) +#define bM4_TMR01_CNTAR_CNTA12 (*((volatile unsigned int*)(0x42480030UL))) +#define bM4_TMR01_CNTAR_CNTA13 (*((volatile unsigned int*)(0x42480034UL))) +#define bM4_TMR01_CNTAR_CNTA14 (*((volatile unsigned int*)(0x42480038UL))) +#define bM4_TMR01_CNTAR_CNTA15 (*((volatile unsigned int*)(0x4248003CUL))) +#define bM4_TMR01_CNTBR_CNTB0 (*((volatile unsigned int*)(0x42480080UL))) +#define bM4_TMR01_CNTBR_CNTB1 (*((volatile unsigned int*)(0x42480084UL))) +#define bM4_TMR01_CNTBR_CNTB2 (*((volatile unsigned int*)(0x42480088UL))) +#define bM4_TMR01_CNTBR_CNTB3 (*((volatile unsigned int*)(0x4248008CUL))) +#define bM4_TMR01_CNTBR_CNTB4 (*((volatile unsigned int*)(0x42480090UL))) +#define bM4_TMR01_CNTBR_CNTB5 (*((volatile unsigned int*)(0x42480094UL))) +#define bM4_TMR01_CNTBR_CNTB6 (*((volatile unsigned int*)(0x42480098UL))) +#define bM4_TMR01_CNTBR_CNTB7 (*((volatile unsigned int*)(0x4248009CUL))) +#define bM4_TMR01_CNTBR_CNTB8 (*((volatile unsigned int*)(0x424800A0UL))) +#define bM4_TMR01_CNTBR_CNTB9 (*((volatile unsigned int*)(0x424800A4UL))) +#define bM4_TMR01_CNTBR_CNTB10 (*((volatile unsigned int*)(0x424800A8UL))) +#define bM4_TMR01_CNTBR_CNTB11 (*((volatile unsigned int*)(0x424800ACUL))) +#define bM4_TMR01_CNTBR_CNTB12 (*((volatile unsigned int*)(0x424800B0UL))) +#define bM4_TMR01_CNTBR_CNTB13 (*((volatile unsigned int*)(0x424800B4UL))) +#define bM4_TMR01_CNTBR_CNTB14 (*((volatile unsigned int*)(0x424800B8UL))) +#define bM4_TMR01_CNTBR_CNTB15 (*((volatile unsigned int*)(0x424800BCUL))) +#define bM4_TMR01_CMPAR_CMPA0 (*((volatile unsigned int*)(0x42480100UL))) +#define bM4_TMR01_CMPAR_CMPA1 (*((volatile unsigned int*)(0x42480104UL))) +#define bM4_TMR01_CMPAR_CMPA2 (*((volatile unsigned int*)(0x42480108UL))) +#define bM4_TMR01_CMPAR_CMPA3 (*((volatile unsigned int*)(0x4248010CUL))) +#define bM4_TMR01_CMPAR_CMPA4 (*((volatile unsigned int*)(0x42480110UL))) +#define bM4_TMR01_CMPAR_CMPA5 (*((volatile unsigned int*)(0x42480114UL))) +#define bM4_TMR01_CMPAR_CMPA6 (*((volatile unsigned int*)(0x42480118UL))) +#define bM4_TMR01_CMPAR_CMPA7 (*((volatile unsigned int*)(0x4248011CUL))) +#define bM4_TMR01_CMPAR_CMPA8 (*((volatile unsigned int*)(0x42480120UL))) +#define bM4_TMR01_CMPAR_CMPA9 (*((volatile unsigned int*)(0x42480124UL))) +#define bM4_TMR01_CMPAR_CMPA10 (*((volatile unsigned int*)(0x42480128UL))) +#define bM4_TMR01_CMPAR_CMPA11 (*((volatile unsigned int*)(0x4248012CUL))) +#define bM4_TMR01_CMPAR_CMPA12 (*((volatile unsigned int*)(0x42480130UL))) +#define bM4_TMR01_CMPAR_CMPA13 (*((volatile unsigned int*)(0x42480134UL))) +#define bM4_TMR01_CMPAR_CMPA14 (*((volatile unsigned int*)(0x42480138UL))) +#define bM4_TMR01_CMPAR_CMPA15 (*((volatile unsigned int*)(0x4248013CUL))) +#define bM4_TMR01_CMPBR_CMPB0 (*((volatile unsigned int*)(0x42480180UL))) +#define bM4_TMR01_CMPBR_CMPB1 (*((volatile unsigned int*)(0x42480184UL))) +#define bM4_TMR01_CMPBR_CMPB2 (*((volatile unsigned int*)(0x42480188UL))) +#define bM4_TMR01_CMPBR_CMPB3 (*((volatile unsigned int*)(0x4248018CUL))) +#define bM4_TMR01_CMPBR_CMPB4 (*((volatile unsigned int*)(0x42480190UL))) +#define bM4_TMR01_CMPBR_CMPB5 (*((volatile unsigned int*)(0x42480194UL))) +#define bM4_TMR01_CMPBR_CMPB6 (*((volatile unsigned int*)(0x42480198UL))) +#define bM4_TMR01_CMPBR_CMPB7 (*((volatile unsigned int*)(0x4248019CUL))) +#define bM4_TMR01_CMPBR_CMPB8 (*((volatile unsigned int*)(0x424801A0UL))) +#define bM4_TMR01_CMPBR_CMPB9 (*((volatile unsigned int*)(0x424801A4UL))) +#define bM4_TMR01_CMPBR_CMPB10 (*((volatile unsigned int*)(0x424801A8UL))) +#define bM4_TMR01_CMPBR_CMPB11 (*((volatile unsigned int*)(0x424801ACUL))) +#define bM4_TMR01_CMPBR_CMPB12 (*((volatile unsigned int*)(0x424801B0UL))) +#define bM4_TMR01_CMPBR_CMPB13 (*((volatile unsigned int*)(0x424801B4UL))) +#define bM4_TMR01_CMPBR_CMPB14 (*((volatile unsigned int*)(0x424801B8UL))) +#define bM4_TMR01_CMPBR_CMPB15 (*((volatile unsigned int*)(0x424801BCUL))) +#define bM4_TMR01_BCONR_CSTA (*((volatile unsigned int*)(0x42480200UL))) +#define bM4_TMR01_BCONR_CAPMDA (*((volatile unsigned int*)(0x42480204UL))) +#define bM4_TMR01_BCONR_INTENA (*((volatile unsigned int*)(0x42480208UL))) +#define bM4_TMR01_BCONR_CKDIVA0 (*((volatile unsigned int*)(0x42480210UL))) +#define bM4_TMR01_BCONR_CKDIVA1 (*((volatile unsigned int*)(0x42480214UL))) +#define bM4_TMR01_BCONR_CKDIVA2 (*((volatile unsigned int*)(0x42480218UL))) +#define bM4_TMR01_BCONR_CKDIVA3 (*((volatile unsigned int*)(0x4248021CUL))) +#define bM4_TMR01_BCONR_SYNSA (*((volatile unsigned int*)(0x42480220UL))) +#define bM4_TMR01_BCONR_SYNCLKA (*((volatile unsigned int*)(0x42480224UL))) +#define bM4_TMR01_BCONR_ASYNCLKA (*((volatile unsigned int*)(0x42480228UL))) +#define bM4_TMR01_BCONR_HSTAA (*((volatile unsigned int*)(0x42480230UL))) +#define bM4_TMR01_BCONR_HSTPA (*((volatile unsigned int*)(0x42480234UL))) +#define bM4_TMR01_BCONR_HCLEA (*((volatile unsigned int*)(0x42480238UL))) +#define bM4_TMR01_BCONR_HICPA (*((volatile unsigned int*)(0x4248023CUL))) +#define bM4_TMR01_BCONR_CSTB (*((volatile unsigned int*)(0x42480240UL))) +#define bM4_TMR01_BCONR_CAPMDB (*((volatile unsigned int*)(0x42480244UL))) +#define bM4_TMR01_BCONR_INTENB (*((volatile unsigned int*)(0x42480248UL))) +#define bM4_TMR01_BCONR_CKDIVB0 (*((volatile unsigned int*)(0x42480250UL))) +#define bM4_TMR01_BCONR_CKDIVB1 (*((volatile unsigned int*)(0x42480254UL))) +#define bM4_TMR01_BCONR_CKDIVB2 (*((volatile unsigned int*)(0x42480258UL))) +#define bM4_TMR01_BCONR_CKDIVB3 (*((volatile unsigned int*)(0x4248025CUL))) +#define bM4_TMR01_BCONR_SYNSB (*((volatile unsigned int*)(0x42480260UL))) +#define bM4_TMR01_BCONR_SYNCLKB (*((volatile unsigned int*)(0x42480264UL))) +#define bM4_TMR01_BCONR_ASYNCLKB (*((volatile unsigned int*)(0x42480268UL))) +#define bM4_TMR01_BCONR_HSTAB (*((volatile unsigned int*)(0x42480270UL))) +#define bM4_TMR01_BCONR_HSTPB (*((volatile unsigned int*)(0x42480274UL))) +#define bM4_TMR01_BCONR_HCLEB (*((volatile unsigned int*)(0x42480278UL))) +#define bM4_TMR01_BCONR_HICPB (*((volatile unsigned int*)(0x4248027CUL))) +#define bM4_TMR01_STFLR_CMAF (*((volatile unsigned int*)(0x42480280UL))) +#define bM4_TMR01_STFLR_CMBF (*((volatile unsigned int*)(0x424802C0UL))) +#define bM4_TMR02_CNTAR_CNTA0 (*((volatile unsigned int*)(0x42488000UL))) +#define bM4_TMR02_CNTAR_CNTA1 (*((volatile unsigned int*)(0x42488004UL))) +#define bM4_TMR02_CNTAR_CNTA2 (*((volatile unsigned int*)(0x42488008UL))) +#define bM4_TMR02_CNTAR_CNTA3 (*((volatile unsigned int*)(0x4248800CUL))) +#define bM4_TMR02_CNTAR_CNTA4 (*((volatile unsigned int*)(0x42488010UL))) +#define bM4_TMR02_CNTAR_CNTA5 (*((volatile unsigned int*)(0x42488014UL))) +#define bM4_TMR02_CNTAR_CNTA6 (*((volatile unsigned int*)(0x42488018UL))) +#define bM4_TMR02_CNTAR_CNTA7 (*((volatile unsigned int*)(0x4248801CUL))) +#define bM4_TMR02_CNTAR_CNTA8 (*((volatile unsigned int*)(0x42488020UL))) +#define bM4_TMR02_CNTAR_CNTA9 (*((volatile unsigned int*)(0x42488024UL))) +#define bM4_TMR02_CNTAR_CNTA10 (*((volatile unsigned int*)(0x42488028UL))) +#define bM4_TMR02_CNTAR_CNTA11 (*((volatile unsigned int*)(0x4248802CUL))) +#define bM4_TMR02_CNTAR_CNTA12 (*((volatile unsigned int*)(0x42488030UL))) +#define bM4_TMR02_CNTAR_CNTA13 (*((volatile unsigned int*)(0x42488034UL))) +#define bM4_TMR02_CNTAR_CNTA14 (*((volatile unsigned int*)(0x42488038UL))) +#define bM4_TMR02_CNTAR_CNTA15 (*((volatile unsigned int*)(0x4248803CUL))) +#define bM4_TMR02_CNTBR_CNTB0 (*((volatile unsigned int*)(0x42488080UL))) +#define bM4_TMR02_CNTBR_CNTB1 (*((volatile unsigned int*)(0x42488084UL))) +#define bM4_TMR02_CNTBR_CNTB2 (*((volatile unsigned int*)(0x42488088UL))) +#define bM4_TMR02_CNTBR_CNTB3 (*((volatile unsigned int*)(0x4248808CUL))) +#define bM4_TMR02_CNTBR_CNTB4 (*((volatile unsigned int*)(0x42488090UL))) +#define bM4_TMR02_CNTBR_CNTB5 (*((volatile unsigned int*)(0x42488094UL))) +#define bM4_TMR02_CNTBR_CNTB6 (*((volatile unsigned int*)(0x42488098UL))) +#define bM4_TMR02_CNTBR_CNTB7 (*((volatile unsigned int*)(0x4248809CUL))) +#define bM4_TMR02_CNTBR_CNTB8 (*((volatile unsigned int*)(0x424880A0UL))) +#define bM4_TMR02_CNTBR_CNTB9 (*((volatile unsigned int*)(0x424880A4UL))) +#define bM4_TMR02_CNTBR_CNTB10 (*((volatile unsigned int*)(0x424880A8UL))) +#define bM4_TMR02_CNTBR_CNTB11 (*((volatile unsigned int*)(0x424880ACUL))) +#define bM4_TMR02_CNTBR_CNTB12 (*((volatile unsigned int*)(0x424880B0UL))) +#define bM4_TMR02_CNTBR_CNTB13 (*((volatile unsigned int*)(0x424880B4UL))) +#define bM4_TMR02_CNTBR_CNTB14 (*((volatile unsigned int*)(0x424880B8UL))) +#define bM4_TMR02_CNTBR_CNTB15 (*((volatile unsigned int*)(0x424880BCUL))) +#define bM4_TMR02_CMPAR_CMPA0 (*((volatile unsigned int*)(0x42488100UL))) +#define bM4_TMR02_CMPAR_CMPA1 (*((volatile unsigned int*)(0x42488104UL))) +#define bM4_TMR02_CMPAR_CMPA2 (*((volatile unsigned int*)(0x42488108UL))) +#define bM4_TMR02_CMPAR_CMPA3 (*((volatile unsigned int*)(0x4248810CUL))) +#define bM4_TMR02_CMPAR_CMPA4 (*((volatile unsigned int*)(0x42488110UL))) +#define bM4_TMR02_CMPAR_CMPA5 (*((volatile unsigned int*)(0x42488114UL))) +#define bM4_TMR02_CMPAR_CMPA6 (*((volatile unsigned int*)(0x42488118UL))) +#define bM4_TMR02_CMPAR_CMPA7 (*((volatile unsigned int*)(0x4248811CUL))) +#define bM4_TMR02_CMPAR_CMPA8 (*((volatile unsigned int*)(0x42488120UL))) +#define bM4_TMR02_CMPAR_CMPA9 (*((volatile unsigned int*)(0x42488124UL))) +#define bM4_TMR02_CMPAR_CMPA10 (*((volatile unsigned int*)(0x42488128UL))) +#define bM4_TMR02_CMPAR_CMPA11 (*((volatile unsigned int*)(0x4248812CUL))) +#define bM4_TMR02_CMPAR_CMPA12 (*((volatile unsigned int*)(0x42488130UL))) +#define bM4_TMR02_CMPAR_CMPA13 (*((volatile unsigned int*)(0x42488134UL))) +#define bM4_TMR02_CMPAR_CMPA14 (*((volatile unsigned int*)(0x42488138UL))) +#define bM4_TMR02_CMPAR_CMPA15 (*((volatile unsigned int*)(0x4248813CUL))) +#define bM4_TMR02_CMPBR_CMPB0 (*((volatile unsigned int*)(0x42488180UL))) +#define bM4_TMR02_CMPBR_CMPB1 (*((volatile unsigned int*)(0x42488184UL))) +#define bM4_TMR02_CMPBR_CMPB2 (*((volatile unsigned int*)(0x42488188UL))) +#define bM4_TMR02_CMPBR_CMPB3 (*((volatile unsigned int*)(0x4248818CUL))) +#define bM4_TMR02_CMPBR_CMPB4 (*((volatile unsigned int*)(0x42488190UL))) +#define bM4_TMR02_CMPBR_CMPB5 (*((volatile unsigned int*)(0x42488194UL))) +#define bM4_TMR02_CMPBR_CMPB6 (*((volatile unsigned int*)(0x42488198UL))) +#define bM4_TMR02_CMPBR_CMPB7 (*((volatile unsigned int*)(0x4248819CUL))) +#define bM4_TMR02_CMPBR_CMPB8 (*((volatile unsigned int*)(0x424881A0UL))) +#define bM4_TMR02_CMPBR_CMPB9 (*((volatile unsigned int*)(0x424881A4UL))) +#define bM4_TMR02_CMPBR_CMPB10 (*((volatile unsigned int*)(0x424881A8UL))) +#define bM4_TMR02_CMPBR_CMPB11 (*((volatile unsigned int*)(0x424881ACUL))) +#define bM4_TMR02_CMPBR_CMPB12 (*((volatile unsigned int*)(0x424881B0UL))) +#define bM4_TMR02_CMPBR_CMPB13 (*((volatile unsigned int*)(0x424881B4UL))) +#define bM4_TMR02_CMPBR_CMPB14 (*((volatile unsigned int*)(0x424881B8UL))) +#define bM4_TMR02_CMPBR_CMPB15 (*((volatile unsigned int*)(0x424881BCUL))) +#define bM4_TMR02_BCONR_CSTA (*((volatile unsigned int*)(0x42488200UL))) +#define bM4_TMR02_BCONR_CAPMDA (*((volatile unsigned int*)(0x42488204UL))) +#define bM4_TMR02_BCONR_INTENA (*((volatile unsigned int*)(0x42488208UL))) +#define bM4_TMR02_BCONR_CKDIVA0 (*((volatile unsigned int*)(0x42488210UL))) +#define bM4_TMR02_BCONR_CKDIVA1 (*((volatile unsigned int*)(0x42488214UL))) +#define bM4_TMR02_BCONR_CKDIVA2 (*((volatile unsigned int*)(0x42488218UL))) +#define bM4_TMR02_BCONR_CKDIVA3 (*((volatile unsigned int*)(0x4248821CUL))) +#define bM4_TMR02_BCONR_SYNSA (*((volatile unsigned int*)(0x42488220UL))) +#define bM4_TMR02_BCONR_SYNCLKA (*((volatile unsigned int*)(0x42488224UL))) +#define bM4_TMR02_BCONR_ASYNCLKA (*((volatile unsigned int*)(0x42488228UL))) +#define bM4_TMR02_BCONR_HSTAA (*((volatile unsigned int*)(0x42488230UL))) +#define bM4_TMR02_BCONR_HSTPA (*((volatile unsigned int*)(0x42488234UL))) +#define bM4_TMR02_BCONR_HCLEA (*((volatile unsigned int*)(0x42488238UL))) +#define bM4_TMR02_BCONR_HICPA (*((volatile unsigned int*)(0x4248823CUL))) +#define bM4_TMR02_BCONR_CSTB (*((volatile unsigned int*)(0x42488240UL))) +#define bM4_TMR02_BCONR_CAPMDB (*((volatile unsigned int*)(0x42488244UL))) +#define bM4_TMR02_BCONR_INTENB (*((volatile unsigned int*)(0x42488248UL))) +#define bM4_TMR02_BCONR_CKDIVB0 (*((volatile unsigned int*)(0x42488250UL))) +#define bM4_TMR02_BCONR_CKDIVB1 (*((volatile unsigned int*)(0x42488254UL))) +#define bM4_TMR02_BCONR_CKDIVB2 (*((volatile unsigned int*)(0x42488258UL))) +#define bM4_TMR02_BCONR_CKDIVB3 (*((volatile unsigned int*)(0x4248825CUL))) +#define bM4_TMR02_BCONR_SYNSB (*((volatile unsigned int*)(0x42488260UL))) +#define bM4_TMR02_BCONR_SYNCLKB (*((volatile unsigned int*)(0x42488264UL))) +#define bM4_TMR02_BCONR_ASYNCLKB (*((volatile unsigned int*)(0x42488268UL))) +#define bM4_TMR02_BCONR_HSTAB (*((volatile unsigned int*)(0x42488270UL))) +#define bM4_TMR02_BCONR_HSTPB (*((volatile unsigned int*)(0x42488274UL))) +#define bM4_TMR02_BCONR_HCLEB (*((volatile unsigned int*)(0x42488278UL))) +#define bM4_TMR02_BCONR_HICPB (*((volatile unsigned int*)(0x4248827CUL))) +#define bM4_TMR02_STFLR_CMAF (*((volatile unsigned int*)(0x42488280UL))) +#define bM4_TMR02_STFLR_CMBF (*((volatile unsigned int*)(0x424882C0UL))) +#define bM4_TMR41_OCSRU_OCEH (*((volatile unsigned int*)(0x422E0300UL))) +#define bM4_TMR41_OCSRU_OCEL (*((volatile unsigned int*)(0x422E0304UL))) +#define bM4_TMR41_OCSRU_OCPH (*((volatile unsigned int*)(0x422E0308UL))) +#define bM4_TMR41_OCSRU_OCPL (*((volatile unsigned int*)(0x422E030CUL))) +#define bM4_TMR41_OCSRU_OCIEH (*((volatile unsigned int*)(0x422E0310UL))) +#define bM4_TMR41_OCSRU_OCIEL (*((volatile unsigned int*)(0x422E0314UL))) +#define bM4_TMR41_OCSRU_OCFH (*((volatile unsigned int*)(0x422E0318UL))) +#define bM4_TMR41_OCSRU_OCFL (*((volatile unsigned int*)(0x422E031CUL))) +#define bM4_TMR41_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x422E0340UL))) +#define bM4_TMR41_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x422E0344UL))) +#define bM4_TMR41_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x422E0348UL))) +#define bM4_TMR41_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x422E034CUL))) +#define bM4_TMR41_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x422E0350UL))) +#define bM4_TMR41_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x422E0354UL))) +#define bM4_TMR41_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x422E0358UL))) +#define bM4_TMR41_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x422E035CUL))) +#define bM4_TMR41_OCERU_LMCH (*((volatile unsigned int*)(0x422E0360UL))) +#define bM4_TMR41_OCERU_LMCL (*((volatile unsigned int*)(0x422E0364UL))) +#define bM4_TMR41_OCERU_LMMH (*((volatile unsigned int*)(0x422E0368UL))) +#define bM4_TMR41_OCERU_LMML (*((volatile unsigned int*)(0x422E036CUL))) +#define bM4_TMR41_OCERU_MCECH (*((volatile unsigned int*)(0x422E0370UL))) +#define bM4_TMR41_OCERU_MCECL (*((volatile unsigned int*)(0x422E0374UL))) +#define bM4_TMR41_OCSRV_OCEH (*((volatile unsigned int*)(0x422E0380UL))) +#define bM4_TMR41_OCSRV_OCEL (*((volatile unsigned int*)(0x422E0384UL))) +#define bM4_TMR41_OCSRV_OCPH (*((volatile unsigned int*)(0x422E0388UL))) +#define bM4_TMR41_OCSRV_OCPL (*((volatile unsigned int*)(0x422E038CUL))) +#define bM4_TMR41_OCSRV_OCIEH (*((volatile unsigned int*)(0x422E0390UL))) +#define bM4_TMR41_OCSRV_OCIEL (*((volatile unsigned int*)(0x422E0394UL))) +#define bM4_TMR41_OCSRV_OCFH (*((volatile unsigned int*)(0x422E0398UL))) +#define bM4_TMR41_OCSRV_OCFL (*((volatile unsigned int*)(0x422E039CUL))) +#define bM4_TMR41_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x422E03C0UL))) +#define bM4_TMR41_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x422E03C4UL))) +#define bM4_TMR41_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x422E03C8UL))) +#define bM4_TMR41_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x422E03CCUL))) +#define bM4_TMR41_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x422E03D0UL))) +#define bM4_TMR41_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x422E03D4UL))) +#define bM4_TMR41_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x422E03D8UL))) +#define bM4_TMR41_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x422E03DCUL))) +#define bM4_TMR41_OCERV_LMCH (*((volatile unsigned int*)(0x422E03E0UL))) +#define bM4_TMR41_OCERV_LMCL (*((volatile unsigned int*)(0x422E03E4UL))) +#define bM4_TMR41_OCERV_LMMH (*((volatile unsigned int*)(0x422E03E8UL))) +#define bM4_TMR41_OCERV_LMML (*((volatile unsigned int*)(0x422E03ECUL))) +#define bM4_TMR41_OCERV_MCECH (*((volatile unsigned int*)(0x422E03F0UL))) +#define bM4_TMR41_OCERV_MCECL (*((volatile unsigned int*)(0x422E03F4UL))) +#define bM4_TMR41_OCSRW_OCEH (*((volatile unsigned int*)(0x422E0400UL))) +#define bM4_TMR41_OCSRW_OCEL (*((volatile unsigned int*)(0x422E0404UL))) +#define bM4_TMR41_OCSRW_OCPH (*((volatile unsigned int*)(0x422E0408UL))) +#define bM4_TMR41_OCSRW_OCPL (*((volatile unsigned int*)(0x422E040CUL))) +#define bM4_TMR41_OCSRW_OCIEH (*((volatile unsigned int*)(0x422E0410UL))) +#define bM4_TMR41_OCSRW_OCIEL (*((volatile unsigned int*)(0x422E0414UL))) +#define bM4_TMR41_OCSRW_OCFH (*((volatile unsigned int*)(0x422E0418UL))) +#define bM4_TMR41_OCSRW_OCFL (*((volatile unsigned int*)(0x422E041CUL))) +#define bM4_TMR41_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x422E0440UL))) +#define bM4_TMR41_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x422E0444UL))) +#define bM4_TMR41_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x422E0448UL))) +#define bM4_TMR41_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x422E044CUL))) +#define bM4_TMR41_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x422E0450UL))) +#define bM4_TMR41_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x422E0454UL))) +#define bM4_TMR41_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x422E0458UL))) +#define bM4_TMR41_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x422E045CUL))) +#define bM4_TMR41_OCERW_LMCH (*((volatile unsigned int*)(0x422E0460UL))) +#define bM4_TMR41_OCERW_LMCL (*((volatile unsigned int*)(0x422E0464UL))) +#define bM4_TMR41_OCERW_LMMH (*((volatile unsigned int*)(0x422E0468UL))) +#define bM4_TMR41_OCERW_LMML (*((volatile unsigned int*)(0x422E046CUL))) +#define bM4_TMR41_OCERW_MCECH (*((volatile unsigned int*)(0x422E0470UL))) +#define bM4_TMR41_OCERW_MCECL (*((volatile unsigned int*)(0x422E0474UL))) +#define bM4_TMR41_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x422E0480UL))) +#define bM4_TMR41_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x422E0484UL))) +#define bM4_TMR41_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x422E0488UL))) +#define bM4_TMR41_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x422E048CUL))) +#define bM4_TMR41_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x422E0490UL))) +#define bM4_TMR41_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x422E0494UL))) +#define bM4_TMR41_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x422E0498UL))) +#define bM4_TMR41_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x422E049CUL))) +#define bM4_TMR41_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x422E04A0UL))) +#define bM4_TMR41_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x422E04A4UL))) +#define bM4_TMR41_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x422E04A8UL))) +#define bM4_TMR41_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x422E04ACUL))) +#define bM4_TMR41_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x422E04B0UL))) +#define bM4_TMR41_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x422E04B4UL))) +#define bM4_TMR41_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x422E04B8UL))) +#define bM4_TMR41_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x422E04BCUL))) +#define bM4_TMR41_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x422E0500UL))) +#define bM4_TMR41_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x422E0504UL))) +#define bM4_TMR41_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x422E0508UL))) +#define bM4_TMR41_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x422E050CUL))) +#define bM4_TMR41_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x422E0510UL))) +#define bM4_TMR41_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x422E0514UL))) +#define bM4_TMR41_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x422E0518UL))) +#define bM4_TMR41_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x422E051CUL))) +#define bM4_TMR41_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x422E0520UL))) +#define bM4_TMR41_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x422E0524UL))) +#define bM4_TMR41_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x422E0528UL))) +#define bM4_TMR41_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x422E052CUL))) +#define bM4_TMR41_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x422E0530UL))) +#define bM4_TMR41_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x422E0534UL))) +#define bM4_TMR41_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x422E0538UL))) +#define bM4_TMR41_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x422E053CUL))) +#define bM4_TMR41_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0540UL))) +#define bM4_TMR41_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0544UL))) +#define bM4_TMR41_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0548UL))) +#define bM4_TMR41_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x422E054CUL))) +#define bM4_TMR41_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x422E0550UL))) +#define bM4_TMR41_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x422E0554UL))) +#define bM4_TMR41_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x422E0558UL))) +#define bM4_TMR41_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x422E055CUL))) +#define bM4_TMR41_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x422E0560UL))) +#define bM4_TMR41_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x422E0564UL))) +#define bM4_TMR41_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x422E0568UL))) +#define bM4_TMR41_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x422E056CUL))) +#define bM4_TMR41_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0570UL))) +#define bM4_TMR41_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0574UL))) +#define bM4_TMR41_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0578UL))) +#define bM4_TMR41_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x422E057CUL))) +#define bM4_TMR41_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x422E0580UL))) +#define bM4_TMR41_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x422E0584UL))) +#define bM4_TMR41_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x422E0588UL))) +#define bM4_TMR41_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x422E058CUL))) +#define bM4_TMR41_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x422E0590UL))) +#define bM4_TMR41_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x422E0594UL))) +#define bM4_TMR41_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x422E0598UL))) +#define bM4_TMR41_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x422E059CUL))) +#define bM4_TMR41_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x422E05A0UL))) +#define bM4_TMR41_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x422E05A4UL))) +#define bM4_TMR41_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x422E05A8UL))) +#define bM4_TMR41_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x422E05ACUL))) +#define bM4_TMR41_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x422E05B0UL))) +#define bM4_TMR41_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x422E05B4UL))) +#define bM4_TMR41_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x422E05B8UL))) +#define bM4_TMR41_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x422E05BCUL))) +#define bM4_TMR41_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x422E0600UL))) +#define bM4_TMR41_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x422E0604UL))) +#define bM4_TMR41_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x422E0608UL))) +#define bM4_TMR41_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x422E060CUL))) +#define bM4_TMR41_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x422E0610UL))) +#define bM4_TMR41_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x422E0614UL))) +#define bM4_TMR41_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x422E0618UL))) +#define bM4_TMR41_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x422E061CUL))) +#define bM4_TMR41_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x422E0620UL))) +#define bM4_TMR41_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x422E0624UL))) +#define bM4_TMR41_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x422E0628UL))) +#define bM4_TMR41_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x422E062CUL))) +#define bM4_TMR41_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x422E0630UL))) +#define bM4_TMR41_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x422E0634UL))) +#define bM4_TMR41_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x422E0638UL))) +#define bM4_TMR41_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x422E063CUL))) +#define bM4_TMR41_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0640UL))) +#define bM4_TMR41_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0644UL))) +#define bM4_TMR41_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0648UL))) +#define bM4_TMR41_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x422E064CUL))) +#define bM4_TMR41_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x422E0650UL))) +#define bM4_TMR41_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x422E0654UL))) +#define bM4_TMR41_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x422E0658UL))) +#define bM4_TMR41_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x422E065CUL))) +#define bM4_TMR41_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x422E0660UL))) +#define bM4_TMR41_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x422E0664UL))) +#define bM4_TMR41_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x422E0668UL))) +#define bM4_TMR41_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x422E066CUL))) +#define bM4_TMR41_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0670UL))) +#define bM4_TMR41_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0674UL))) +#define bM4_TMR41_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0678UL))) +#define bM4_TMR41_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x422E067CUL))) +#define bM4_TMR41_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x422E0680UL))) +#define bM4_TMR41_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x422E0684UL))) +#define bM4_TMR41_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x422E0688UL))) +#define bM4_TMR41_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x422E068CUL))) +#define bM4_TMR41_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x422E0690UL))) +#define bM4_TMR41_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x422E0694UL))) +#define bM4_TMR41_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x422E0698UL))) +#define bM4_TMR41_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x422E069CUL))) +#define bM4_TMR41_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x422E06A0UL))) +#define bM4_TMR41_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x422E06A4UL))) +#define bM4_TMR41_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x422E06A8UL))) +#define bM4_TMR41_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x422E06ACUL))) +#define bM4_TMR41_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x422E06B0UL))) +#define bM4_TMR41_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x422E06B4UL))) +#define bM4_TMR41_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x422E06B8UL))) +#define bM4_TMR41_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x422E06BCUL))) +#define bM4_TMR41_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x422E0700UL))) +#define bM4_TMR41_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x422E0704UL))) +#define bM4_TMR41_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x422E0708UL))) +#define bM4_TMR41_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x422E070CUL))) +#define bM4_TMR41_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x422E0710UL))) +#define bM4_TMR41_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x422E0714UL))) +#define bM4_TMR41_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x422E0718UL))) +#define bM4_TMR41_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x422E071CUL))) +#define bM4_TMR41_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x422E0720UL))) +#define bM4_TMR41_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x422E0724UL))) +#define bM4_TMR41_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x422E0728UL))) +#define bM4_TMR41_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x422E072CUL))) +#define bM4_TMR41_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x422E0730UL))) +#define bM4_TMR41_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x422E0734UL))) +#define bM4_TMR41_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x422E0738UL))) +#define bM4_TMR41_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x422E073CUL))) +#define bM4_TMR41_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x422E0740UL))) +#define bM4_TMR41_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x422E0744UL))) +#define bM4_TMR41_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x422E0748UL))) +#define bM4_TMR41_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x422E074CUL))) +#define bM4_TMR41_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x422E0750UL))) +#define bM4_TMR41_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x422E0754UL))) +#define bM4_TMR41_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x422E0758UL))) +#define bM4_TMR41_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x422E075CUL))) +#define bM4_TMR41_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x422E0760UL))) +#define bM4_TMR41_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x422E0764UL))) +#define bM4_TMR41_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x422E0768UL))) +#define bM4_TMR41_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x422E076CUL))) +#define bM4_TMR41_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x422E0770UL))) +#define bM4_TMR41_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x422E0774UL))) +#define bM4_TMR41_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x422E0778UL))) +#define bM4_TMR41_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x422E077CUL))) +#define bM4_TMR41_CCSR_CKDIV0 (*((volatile unsigned int*)(0x422E0900UL))) +#define bM4_TMR41_CCSR_CKDIV1 (*((volatile unsigned int*)(0x422E0904UL))) +#define bM4_TMR41_CCSR_CKDIV2 (*((volatile unsigned int*)(0x422E0908UL))) +#define bM4_TMR41_CCSR_CKDIV3 (*((volatile unsigned int*)(0x422E090CUL))) +#define bM4_TMR41_CCSR_CLEAR (*((volatile unsigned int*)(0x422E0910UL))) +#define bM4_TMR41_CCSR_MODE (*((volatile unsigned int*)(0x422E0914UL))) +#define bM4_TMR41_CCSR_STOP (*((volatile unsigned int*)(0x422E0918UL))) +#define bM4_TMR41_CCSR_BUFEN (*((volatile unsigned int*)(0x422E091CUL))) +#define bM4_TMR41_CCSR_IRQPEN (*((volatile unsigned int*)(0x422E0920UL))) +#define bM4_TMR41_CCSR_IRQPF (*((volatile unsigned int*)(0x422E0924UL))) +#define bM4_TMR41_CCSR_IRQZEN (*((volatile unsigned int*)(0x422E0934UL))) +#define bM4_TMR41_CCSR_IRQZF (*((volatile unsigned int*)(0x422E0938UL))) +#define bM4_TMR41_CCSR_ECKEN (*((volatile unsigned int*)(0x422E093CUL))) +#define bM4_TMR41_CVPR_ZIM0 (*((volatile unsigned int*)(0x422E0940UL))) +#define bM4_TMR41_CVPR_ZIM1 (*((volatile unsigned int*)(0x422E0944UL))) +#define bM4_TMR41_CVPR_ZIM2 (*((volatile unsigned int*)(0x422E0948UL))) +#define bM4_TMR41_CVPR_ZIM3 (*((volatile unsigned int*)(0x422E094CUL))) +#define bM4_TMR41_CVPR_PIM0 (*((volatile unsigned int*)(0x422E0950UL))) +#define bM4_TMR41_CVPR_PIM1 (*((volatile unsigned int*)(0x422E0954UL))) +#define bM4_TMR41_CVPR_PIM2 (*((volatile unsigned int*)(0x422E0958UL))) +#define bM4_TMR41_CVPR_PIM3 (*((volatile unsigned int*)(0x422E095CUL))) +#define bM4_TMR41_CVPR_ZIC0 (*((volatile unsigned int*)(0x422E0960UL))) +#define bM4_TMR41_CVPR_ZIC1 (*((volatile unsigned int*)(0x422E0964UL))) +#define bM4_TMR41_CVPR_ZIC2 (*((volatile unsigned int*)(0x422E0968UL))) +#define bM4_TMR41_CVPR_ZIC3 (*((volatile unsigned int*)(0x422E096CUL))) +#define bM4_TMR41_CVPR_PIC0 (*((volatile unsigned int*)(0x422E0970UL))) +#define bM4_TMR41_CVPR_PIC1 (*((volatile unsigned int*)(0x422E0974UL))) +#define bM4_TMR41_CVPR_PIC2 (*((volatile unsigned int*)(0x422E0978UL))) +#define bM4_TMR41_CVPR_PIC3 (*((volatile unsigned int*)(0x422E097CUL))) +#define bM4_TMR41_POCRU_DIVCK0 (*((volatile unsigned int*)(0x422E1300UL))) +#define bM4_TMR41_POCRU_DIVCK1 (*((volatile unsigned int*)(0x422E1304UL))) +#define bM4_TMR41_POCRU_DIVCK2 (*((volatile unsigned int*)(0x422E1308UL))) +#define bM4_TMR41_POCRU_DIVCK3 (*((volatile unsigned int*)(0x422E130CUL))) +#define bM4_TMR41_POCRU_PWMMD0 (*((volatile unsigned int*)(0x422E1310UL))) +#define bM4_TMR41_POCRU_PWMMD1 (*((volatile unsigned int*)(0x422E1314UL))) +#define bM4_TMR41_POCRU_LVLS0 (*((volatile unsigned int*)(0x422E1318UL))) +#define bM4_TMR41_POCRU_LVLS1 (*((volatile unsigned int*)(0x422E131CUL))) +#define bM4_TMR41_POCRV_DIVCK0 (*((volatile unsigned int*)(0x422E1380UL))) +#define bM4_TMR41_POCRV_DIVCK1 (*((volatile unsigned int*)(0x422E1384UL))) +#define bM4_TMR41_POCRV_DIVCK2 (*((volatile unsigned int*)(0x422E1388UL))) +#define bM4_TMR41_POCRV_DIVCK3 (*((volatile unsigned int*)(0x422E138CUL))) +#define bM4_TMR41_POCRV_PWMMD0 (*((volatile unsigned int*)(0x422E1390UL))) +#define bM4_TMR41_POCRV_PWMMD1 (*((volatile unsigned int*)(0x422E1394UL))) +#define bM4_TMR41_POCRV_LVLS0 (*((volatile unsigned int*)(0x422E1398UL))) +#define bM4_TMR41_POCRV_LVLS1 (*((volatile unsigned int*)(0x422E139CUL))) +#define bM4_TMR41_POCRW_DIVCK0 (*((volatile unsigned int*)(0x422E1400UL))) +#define bM4_TMR41_POCRW_DIVCK1 (*((volatile unsigned int*)(0x422E1404UL))) +#define bM4_TMR41_POCRW_DIVCK2 (*((volatile unsigned int*)(0x422E1408UL))) +#define bM4_TMR41_POCRW_DIVCK3 (*((volatile unsigned int*)(0x422E140CUL))) +#define bM4_TMR41_POCRW_PWMMD0 (*((volatile unsigned int*)(0x422E1410UL))) +#define bM4_TMR41_POCRW_PWMMD1 (*((volatile unsigned int*)(0x422E1414UL))) +#define bM4_TMR41_POCRW_LVLS0 (*((volatile unsigned int*)(0x422E1418UL))) +#define bM4_TMR41_POCRW_LVLS1 (*((volatile unsigned int*)(0x422E141CUL))) +#define bM4_TMR41_RCSR_RTIDU (*((volatile unsigned int*)(0x422E1480UL))) +#define bM4_TMR41_RCSR_RTIDV (*((volatile unsigned int*)(0x422E1484UL))) +#define bM4_TMR41_RCSR_RTIDW (*((volatile unsigned int*)(0x422E1488UL))) +#define bM4_TMR41_RCSR_RTIFU (*((volatile unsigned int*)(0x422E1490UL))) +#define bM4_TMR41_RCSR_RTICU (*((volatile unsigned int*)(0x422E1494UL))) +#define bM4_TMR41_RCSR_RTEU (*((volatile unsigned int*)(0x422E1498UL))) +#define bM4_TMR41_RCSR_RTSU (*((volatile unsigned int*)(0x422E149CUL))) +#define bM4_TMR41_RCSR_RTIFV (*((volatile unsigned int*)(0x422E14A0UL))) +#define bM4_TMR41_RCSR_RTICV (*((volatile unsigned int*)(0x422E14A4UL))) +#define bM4_TMR41_RCSR_RTEV (*((volatile unsigned int*)(0x422E14A8UL))) +#define bM4_TMR41_RCSR_RTSV (*((volatile unsigned int*)(0x422E14ACUL))) +#define bM4_TMR41_RCSR_RTIFW (*((volatile unsigned int*)(0x422E14B0UL))) +#define bM4_TMR41_RCSR_RTICW (*((volatile unsigned int*)(0x422E14B4UL))) +#define bM4_TMR41_RCSR_RTEW (*((volatile unsigned int*)(0x422E14B8UL))) +#define bM4_TMR41_RCSR_RTSW (*((volatile unsigned int*)(0x422E14BCUL))) +#define bM4_TMR41_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x422E1900UL))) +#define bM4_TMR41_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x422E1904UL))) +#define bM4_TMR41_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x422E1908UL))) +#define bM4_TMR41_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x422E190CUL))) +#define bM4_TMR41_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x422E1910UL))) +#define bM4_TMR41_SCSRUH_LMC (*((volatile unsigned int*)(0x422E1914UL))) +#define bM4_TMR41_SCSRUH_EVTMS (*((volatile unsigned int*)(0x422E1920UL))) +#define bM4_TMR41_SCSRUH_EVTDS (*((volatile unsigned int*)(0x422E1924UL))) +#define bM4_TMR41_SCSRUH_DEN (*((volatile unsigned int*)(0x422E1930UL))) +#define bM4_TMR41_SCSRUH_PEN (*((volatile unsigned int*)(0x422E1934UL))) +#define bM4_TMR41_SCSRUH_UEN (*((volatile unsigned int*)(0x422E1938UL))) +#define bM4_TMR41_SCSRUH_ZEN (*((volatile unsigned int*)(0x422E193CUL))) +#define bM4_TMR41_SCMRUH_AMC0 (*((volatile unsigned int*)(0x422E1940UL))) +#define bM4_TMR41_SCMRUH_AMC1 (*((volatile unsigned int*)(0x422E1944UL))) +#define bM4_TMR41_SCMRUH_AMC2 (*((volatile unsigned int*)(0x422E1948UL))) +#define bM4_TMR41_SCMRUH_AMC3 (*((volatile unsigned int*)(0x422E194CUL))) +#define bM4_TMR41_SCMRUH_MZCE (*((volatile unsigned int*)(0x422E1958UL))) +#define bM4_TMR41_SCMRUH_MPCE (*((volatile unsigned int*)(0x422E195CUL))) +#define bM4_TMR41_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x422E1980UL))) +#define bM4_TMR41_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x422E1984UL))) +#define bM4_TMR41_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x422E1988UL))) +#define bM4_TMR41_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x422E198CUL))) +#define bM4_TMR41_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x422E1990UL))) +#define bM4_TMR41_SCSRUL_LMC (*((volatile unsigned int*)(0x422E1994UL))) +#define bM4_TMR41_SCSRUL_EVTMS (*((volatile unsigned int*)(0x422E19A0UL))) +#define bM4_TMR41_SCSRUL_EVTDS (*((volatile unsigned int*)(0x422E19A4UL))) +#define bM4_TMR41_SCSRUL_DEN (*((volatile unsigned int*)(0x422E19B0UL))) +#define bM4_TMR41_SCSRUL_PEN (*((volatile unsigned int*)(0x422E19B4UL))) +#define bM4_TMR41_SCSRUL_UEN (*((volatile unsigned int*)(0x422E19B8UL))) +#define bM4_TMR41_SCSRUL_ZEN (*((volatile unsigned int*)(0x422E19BCUL))) +#define bM4_TMR41_SCMRUL_AMC0 (*((volatile unsigned int*)(0x422E19C0UL))) +#define bM4_TMR41_SCMRUL_AMC1 (*((volatile unsigned int*)(0x422E19C4UL))) +#define bM4_TMR41_SCMRUL_AMC2 (*((volatile unsigned int*)(0x422E19C8UL))) +#define bM4_TMR41_SCMRUL_AMC3 (*((volatile unsigned int*)(0x422E19CCUL))) +#define bM4_TMR41_SCMRUL_MZCE (*((volatile unsigned int*)(0x422E19D8UL))) +#define bM4_TMR41_SCMRUL_MPCE (*((volatile unsigned int*)(0x422E19DCUL))) +#define bM4_TMR41_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x422E1A00UL))) +#define bM4_TMR41_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x422E1A04UL))) +#define bM4_TMR41_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x422E1A08UL))) +#define bM4_TMR41_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x422E1A0CUL))) +#define bM4_TMR41_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x422E1A10UL))) +#define bM4_TMR41_SCSRVH_LMC (*((volatile unsigned int*)(0x422E1A14UL))) +#define bM4_TMR41_SCSRVH_EVTMS (*((volatile unsigned int*)(0x422E1A20UL))) +#define bM4_TMR41_SCSRVH_EVTDS (*((volatile unsigned int*)(0x422E1A24UL))) +#define bM4_TMR41_SCSRVH_DEN (*((volatile unsigned int*)(0x422E1A30UL))) +#define bM4_TMR41_SCSRVH_PEN (*((volatile unsigned int*)(0x422E1A34UL))) +#define bM4_TMR41_SCSRVH_UEN (*((volatile unsigned int*)(0x422E1A38UL))) +#define bM4_TMR41_SCSRVH_ZEN (*((volatile unsigned int*)(0x422E1A3CUL))) +#define bM4_TMR41_SCMRVH_AMC0 (*((volatile unsigned int*)(0x422E1A40UL))) +#define bM4_TMR41_SCMRVH_AMC1 (*((volatile unsigned int*)(0x422E1A44UL))) +#define bM4_TMR41_SCMRVH_AMC2 (*((volatile unsigned int*)(0x422E1A48UL))) +#define bM4_TMR41_SCMRVH_AMC3 (*((volatile unsigned int*)(0x422E1A4CUL))) +#define bM4_TMR41_SCMRVH_MZCE (*((volatile unsigned int*)(0x422E1A58UL))) +#define bM4_TMR41_SCMRVH_MPCE (*((volatile unsigned int*)(0x422E1A5CUL))) +#define bM4_TMR41_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x422E1A80UL))) +#define bM4_TMR41_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x422E1A84UL))) +#define bM4_TMR41_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x422E1A88UL))) +#define bM4_TMR41_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x422E1A8CUL))) +#define bM4_TMR41_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x422E1A90UL))) +#define bM4_TMR41_SCSRVL_LMC (*((volatile unsigned int*)(0x422E1A94UL))) +#define bM4_TMR41_SCSRVL_EVTMS (*((volatile unsigned int*)(0x422E1AA0UL))) +#define bM4_TMR41_SCSRVL_EVTDS (*((volatile unsigned int*)(0x422E1AA4UL))) +#define bM4_TMR41_SCSRVL_DEN (*((volatile unsigned int*)(0x422E1AB0UL))) +#define bM4_TMR41_SCSRVL_PEN (*((volatile unsigned int*)(0x422E1AB4UL))) +#define bM4_TMR41_SCSRVL_UEN (*((volatile unsigned int*)(0x422E1AB8UL))) +#define bM4_TMR41_SCSRVL_ZEN (*((volatile unsigned int*)(0x422E1ABCUL))) +#define bM4_TMR41_SCMRVL_AMC0 (*((volatile unsigned int*)(0x422E1AC0UL))) +#define bM4_TMR41_SCMRVL_AMC1 (*((volatile unsigned int*)(0x422E1AC4UL))) +#define bM4_TMR41_SCMRVL_AMC2 (*((volatile unsigned int*)(0x422E1AC8UL))) +#define bM4_TMR41_SCMRVL_AMC3 (*((volatile unsigned int*)(0x422E1ACCUL))) +#define bM4_TMR41_SCMRVL_MZCE (*((volatile unsigned int*)(0x422E1AD8UL))) +#define bM4_TMR41_SCMRVL_MPCE (*((volatile unsigned int*)(0x422E1ADCUL))) +#define bM4_TMR41_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x422E1B00UL))) +#define bM4_TMR41_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x422E1B04UL))) +#define bM4_TMR41_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x422E1B08UL))) +#define bM4_TMR41_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x422E1B0CUL))) +#define bM4_TMR41_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x422E1B10UL))) +#define bM4_TMR41_SCSRWH_LMC (*((volatile unsigned int*)(0x422E1B14UL))) +#define bM4_TMR41_SCSRWH_EVTMS (*((volatile unsigned int*)(0x422E1B20UL))) +#define bM4_TMR41_SCSRWH_EVTDS (*((volatile unsigned int*)(0x422E1B24UL))) +#define bM4_TMR41_SCSRWH_DEN (*((volatile unsigned int*)(0x422E1B30UL))) +#define bM4_TMR41_SCSRWH_PEN (*((volatile unsigned int*)(0x422E1B34UL))) +#define bM4_TMR41_SCSRWH_UEN (*((volatile unsigned int*)(0x422E1B38UL))) +#define bM4_TMR41_SCSRWH_ZEN (*((volatile unsigned int*)(0x422E1B3CUL))) +#define bM4_TMR41_SCMRWH_AMC0 (*((volatile unsigned int*)(0x422E1B40UL))) +#define bM4_TMR41_SCMRWH_AMC1 (*((volatile unsigned int*)(0x422E1B44UL))) +#define bM4_TMR41_SCMRWH_AMC2 (*((volatile unsigned int*)(0x422E1B48UL))) +#define bM4_TMR41_SCMRWH_AMC3 (*((volatile unsigned int*)(0x422E1B4CUL))) +#define bM4_TMR41_SCMRWH_MZCE (*((volatile unsigned int*)(0x422E1B58UL))) +#define bM4_TMR41_SCMRWH_MPCE (*((volatile unsigned int*)(0x422E1B5CUL))) +#define bM4_TMR41_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x422E1B80UL))) +#define bM4_TMR41_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x422E1B84UL))) +#define bM4_TMR41_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x422E1B88UL))) +#define bM4_TMR41_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x422E1B8CUL))) +#define bM4_TMR41_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x422E1B90UL))) +#define bM4_TMR41_SCSRWL_LMC (*((volatile unsigned int*)(0x422E1B94UL))) +#define bM4_TMR41_SCSRWL_EVTMS (*((volatile unsigned int*)(0x422E1BA0UL))) +#define bM4_TMR41_SCSRWL_EVTDS (*((volatile unsigned int*)(0x422E1BA4UL))) +#define bM4_TMR41_SCSRWL_DEN (*((volatile unsigned int*)(0x422E1BB0UL))) +#define bM4_TMR41_SCSRWL_PEN (*((volatile unsigned int*)(0x422E1BB4UL))) +#define bM4_TMR41_SCSRWL_UEN (*((volatile unsigned int*)(0x422E1BB8UL))) +#define bM4_TMR41_SCSRWL_ZEN (*((volatile unsigned int*)(0x422E1BBCUL))) +#define bM4_TMR41_SCMRWL_AMC0 (*((volatile unsigned int*)(0x422E1BC0UL))) +#define bM4_TMR41_SCMRWL_AMC1 (*((volatile unsigned int*)(0x422E1BC4UL))) +#define bM4_TMR41_SCMRWL_AMC2 (*((volatile unsigned int*)(0x422E1BC8UL))) +#define bM4_TMR41_SCMRWL_AMC3 (*((volatile unsigned int*)(0x422E1BCCUL))) +#define bM4_TMR41_SCMRWL_MZCE (*((volatile unsigned int*)(0x422E1BD8UL))) +#define bM4_TMR41_SCMRWL_MPCE (*((volatile unsigned int*)(0x422E1BDCUL))) +#define bM4_TMR41_ECSR_HOLD (*((volatile unsigned int*)(0x422E1E1CUL))) +#define bM4_TMR42_OCSRU_OCEH (*((volatile unsigned int*)(0x42490300UL))) +#define bM4_TMR42_OCSRU_OCEL (*((volatile unsigned int*)(0x42490304UL))) +#define bM4_TMR42_OCSRU_OCPH (*((volatile unsigned int*)(0x42490308UL))) +#define bM4_TMR42_OCSRU_OCPL (*((volatile unsigned int*)(0x4249030CUL))) +#define bM4_TMR42_OCSRU_OCIEH (*((volatile unsigned int*)(0x42490310UL))) +#define bM4_TMR42_OCSRU_OCIEL (*((volatile unsigned int*)(0x42490314UL))) +#define bM4_TMR42_OCSRU_OCFH (*((volatile unsigned int*)(0x42490318UL))) +#define bM4_TMR42_OCSRU_OCFL (*((volatile unsigned int*)(0x4249031CUL))) +#define bM4_TMR42_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x42490340UL))) +#define bM4_TMR42_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x42490344UL))) +#define bM4_TMR42_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x42490348UL))) +#define bM4_TMR42_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x4249034CUL))) +#define bM4_TMR42_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x42490350UL))) +#define bM4_TMR42_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x42490354UL))) +#define bM4_TMR42_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x42490358UL))) +#define bM4_TMR42_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x4249035CUL))) +#define bM4_TMR42_OCERU_LMCH (*((volatile unsigned int*)(0x42490360UL))) +#define bM4_TMR42_OCERU_LMCL (*((volatile unsigned int*)(0x42490364UL))) +#define bM4_TMR42_OCERU_LMMH (*((volatile unsigned int*)(0x42490368UL))) +#define bM4_TMR42_OCERU_LMML (*((volatile unsigned int*)(0x4249036CUL))) +#define bM4_TMR42_OCERU_MCECH (*((volatile unsigned int*)(0x42490370UL))) +#define bM4_TMR42_OCERU_MCECL (*((volatile unsigned int*)(0x42490374UL))) +#define bM4_TMR42_OCSRV_OCEH (*((volatile unsigned int*)(0x42490380UL))) +#define bM4_TMR42_OCSRV_OCEL (*((volatile unsigned int*)(0x42490384UL))) +#define bM4_TMR42_OCSRV_OCPH (*((volatile unsigned int*)(0x42490388UL))) +#define bM4_TMR42_OCSRV_OCPL (*((volatile unsigned int*)(0x4249038CUL))) +#define bM4_TMR42_OCSRV_OCIEH (*((volatile unsigned int*)(0x42490390UL))) +#define bM4_TMR42_OCSRV_OCIEL (*((volatile unsigned int*)(0x42490394UL))) +#define bM4_TMR42_OCSRV_OCFH (*((volatile unsigned int*)(0x42490398UL))) +#define bM4_TMR42_OCSRV_OCFL (*((volatile unsigned int*)(0x4249039CUL))) +#define bM4_TMR42_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x424903C0UL))) +#define bM4_TMR42_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x424903C4UL))) +#define bM4_TMR42_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x424903C8UL))) +#define bM4_TMR42_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x424903CCUL))) +#define bM4_TMR42_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x424903D0UL))) +#define bM4_TMR42_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x424903D4UL))) +#define bM4_TMR42_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x424903D8UL))) +#define bM4_TMR42_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x424903DCUL))) +#define bM4_TMR42_OCERV_LMCH (*((volatile unsigned int*)(0x424903E0UL))) +#define bM4_TMR42_OCERV_LMCL (*((volatile unsigned int*)(0x424903E4UL))) +#define bM4_TMR42_OCERV_LMMH (*((volatile unsigned int*)(0x424903E8UL))) +#define bM4_TMR42_OCERV_LMML (*((volatile unsigned int*)(0x424903ECUL))) +#define bM4_TMR42_OCERV_MCECH (*((volatile unsigned int*)(0x424903F0UL))) +#define bM4_TMR42_OCERV_MCECL (*((volatile unsigned int*)(0x424903F4UL))) +#define bM4_TMR42_OCSRW_OCEH (*((volatile unsigned int*)(0x42490400UL))) +#define bM4_TMR42_OCSRW_OCEL (*((volatile unsigned int*)(0x42490404UL))) +#define bM4_TMR42_OCSRW_OCPH (*((volatile unsigned int*)(0x42490408UL))) +#define bM4_TMR42_OCSRW_OCPL (*((volatile unsigned int*)(0x4249040CUL))) +#define bM4_TMR42_OCSRW_OCIEH (*((volatile unsigned int*)(0x42490410UL))) +#define bM4_TMR42_OCSRW_OCIEL (*((volatile unsigned int*)(0x42490414UL))) +#define bM4_TMR42_OCSRW_OCFH (*((volatile unsigned int*)(0x42490418UL))) +#define bM4_TMR42_OCSRW_OCFL (*((volatile unsigned int*)(0x4249041CUL))) +#define bM4_TMR42_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x42490440UL))) +#define bM4_TMR42_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x42490444UL))) +#define bM4_TMR42_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x42490448UL))) +#define bM4_TMR42_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x4249044CUL))) +#define bM4_TMR42_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x42490450UL))) +#define bM4_TMR42_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x42490454UL))) +#define bM4_TMR42_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x42490458UL))) +#define bM4_TMR42_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x4249045CUL))) +#define bM4_TMR42_OCERW_LMCH (*((volatile unsigned int*)(0x42490460UL))) +#define bM4_TMR42_OCERW_LMCL (*((volatile unsigned int*)(0x42490464UL))) +#define bM4_TMR42_OCERW_LMMH (*((volatile unsigned int*)(0x42490468UL))) +#define bM4_TMR42_OCERW_LMML (*((volatile unsigned int*)(0x4249046CUL))) +#define bM4_TMR42_OCERW_MCECH (*((volatile unsigned int*)(0x42490470UL))) +#define bM4_TMR42_OCERW_MCECL (*((volatile unsigned int*)(0x42490474UL))) +#define bM4_TMR42_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x42490480UL))) +#define bM4_TMR42_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x42490484UL))) +#define bM4_TMR42_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x42490488UL))) +#define bM4_TMR42_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x4249048CUL))) +#define bM4_TMR42_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x42490490UL))) +#define bM4_TMR42_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x42490494UL))) +#define bM4_TMR42_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x42490498UL))) +#define bM4_TMR42_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x4249049CUL))) +#define bM4_TMR42_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x424904A0UL))) +#define bM4_TMR42_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x424904A4UL))) +#define bM4_TMR42_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x424904A8UL))) +#define bM4_TMR42_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x424904ACUL))) +#define bM4_TMR42_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x424904B0UL))) +#define bM4_TMR42_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x424904B4UL))) +#define bM4_TMR42_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x424904B8UL))) +#define bM4_TMR42_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x424904BCUL))) +#define bM4_TMR42_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x42490500UL))) +#define bM4_TMR42_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x42490504UL))) +#define bM4_TMR42_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x42490508UL))) +#define bM4_TMR42_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x4249050CUL))) +#define bM4_TMR42_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x42490510UL))) +#define bM4_TMR42_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x42490514UL))) +#define bM4_TMR42_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x42490518UL))) +#define bM4_TMR42_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x4249051CUL))) +#define bM4_TMR42_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x42490520UL))) +#define bM4_TMR42_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x42490524UL))) +#define bM4_TMR42_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x42490528UL))) +#define bM4_TMR42_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x4249052CUL))) +#define bM4_TMR42_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x42490530UL))) +#define bM4_TMR42_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x42490534UL))) +#define bM4_TMR42_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x42490538UL))) +#define bM4_TMR42_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x4249053CUL))) +#define bM4_TMR42_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x42490540UL))) +#define bM4_TMR42_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x42490544UL))) +#define bM4_TMR42_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x42490548UL))) +#define bM4_TMR42_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x4249054CUL))) +#define bM4_TMR42_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x42490550UL))) +#define bM4_TMR42_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x42490554UL))) +#define bM4_TMR42_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x42490558UL))) +#define bM4_TMR42_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x4249055CUL))) +#define bM4_TMR42_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x42490560UL))) +#define bM4_TMR42_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x42490564UL))) +#define bM4_TMR42_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x42490568UL))) +#define bM4_TMR42_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x4249056CUL))) +#define bM4_TMR42_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x42490570UL))) +#define bM4_TMR42_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x42490574UL))) +#define bM4_TMR42_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x42490578UL))) +#define bM4_TMR42_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x4249057CUL))) +#define bM4_TMR42_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x42490580UL))) +#define bM4_TMR42_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x42490584UL))) +#define bM4_TMR42_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x42490588UL))) +#define bM4_TMR42_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x4249058CUL))) +#define bM4_TMR42_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x42490590UL))) +#define bM4_TMR42_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x42490594UL))) +#define bM4_TMR42_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x42490598UL))) +#define bM4_TMR42_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x4249059CUL))) +#define bM4_TMR42_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x424905A0UL))) +#define bM4_TMR42_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x424905A4UL))) +#define bM4_TMR42_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x424905A8UL))) +#define bM4_TMR42_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x424905ACUL))) +#define bM4_TMR42_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x424905B0UL))) +#define bM4_TMR42_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x424905B4UL))) +#define bM4_TMR42_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x424905B8UL))) +#define bM4_TMR42_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x424905BCUL))) +#define bM4_TMR42_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x42490600UL))) +#define bM4_TMR42_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x42490604UL))) +#define bM4_TMR42_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x42490608UL))) +#define bM4_TMR42_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x4249060CUL))) +#define bM4_TMR42_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x42490610UL))) +#define bM4_TMR42_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x42490614UL))) +#define bM4_TMR42_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x42490618UL))) +#define bM4_TMR42_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x4249061CUL))) +#define bM4_TMR42_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x42490620UL))) +#define bM4_TMR42_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x42490624UL))) +#define bM4_TMR42_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x42490628UL))) +#define bM4_TMR42_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x4249062CUL))) +#define bM4_TMR42_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x42490630UL))) +#define bM4_TMR42_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x42490634UL))) +#define bM4_TMR42_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x42490638UL))) +#define bM4_TMR42_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x4249063CUL))) +#define bM4_TMR42_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x42490640UL))) +#define bM4_TMR42_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x42490644UL))) +#define bM4_TMR42_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x42490648UL))) +#define bM4_TMR42_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x4249064CUL))) +#define bM4_TMR42_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x42490650UL))) +#define bM4_TMR42_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x42490654UL))) +#define bM4_TMR42_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x42490658UL))) +#define bM4_TMR42_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x4249065CUL))) +#define bM4_TMR42_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x42490660UL))) +#define bM4_TMR42_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x42490664UL))) +#define bM4_TMR42_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x42490668UL))) +#define bM4_TMR42_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x4249066CUL))) +#define bM4_TMR42_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x42490670UL))) +#define bM4_TMR42_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x42490674UL))) +#define bM4_TMR42_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x42490678UL))) +#define bM4_TMR42_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x4249067CUL))) +#define bM4_TMR42_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x42490680UL))) +#define bM4_TMR42_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x42490684UL))) +#define bM4_TMR42_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x42490688UL))) +#define bM4_TMR42_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x4249068CUL))) +#define bM4_TMR42_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x42490690UL))) +#define bM4_TMR42_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x42490694UL))) +#define bM4_TMR42_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x42490698UL))) +#define bM4_TMR42_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x4249069CUL))) +#define bM4_TMR42_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x424906A0UL))) +#define bM4_TMR42_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x424906A4UL))) +#define bM4_TMR42_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x424906A8UL))) +#define bM4_TMR42_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x424906ACUL))) +#define bM4_TMR42_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x424906B0UL))) +#define bM4_TMR42_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x424906B4UL))) +#define bM4_TMR42_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x424906B8UL))) +#define bM4_TMR42_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x424906BCUL))) +#define bM4_TMR42_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x42490700UL))) +#define bM4_TMR42_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x42490704UL))) +#define bM4_TMR42_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x42490708UL))) +#define bM4_TMR42_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x4249070CUL))) +#define bM4_TMR42_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x42490710UL))) +#define bM4_TMR42_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x42490714UL))) +#define bM4_TMR42_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x42490718UL))) +#define bM4_TMR42_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x4249071CUL))) +#define bM4_TMR42_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x42490720UL))) +#define bM4_TMR42_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x42490724UL))) +#define bM4_TMR42_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x42490728UL))) +#define bM4_TMR42_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x4249072CUL))) +#define bM4_TMR42_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x42490730UL))) +#define bM4_TMR42_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x42490734UL))) +#define bM4_TMR42_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x42490738UL))) +#define bM4_TMR42_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x4249073CUL))) +#define bM4_TMR42_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x42490740UL))) +#define bM4_TMR42_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x42490744UL))) +#define bM4_TMR42_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x42490748UL))) +#define bM4_TMR42_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x4249074CUL))) +#define bM4_TMR42_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x42490750UL))) +#define bM4_TMR42_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x42490754UL))) +#define bM4_TMR42_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x42490758UL))) +#define bM4_TMR42_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x4249075CUL))) +#define bM4_TMR42_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x42490760UL))) +#define bM4_TMR42_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x42490764UL))) +#define bM4_TMR42_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x42490768UL))) +#define bM4_TMR42_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x4249076CUL))) +#define bM4_TMR42_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x42490770UL))) +#define bM4_TMR42_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x42490774UL))) +#define bM4_TMR42_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x42490778UL))) +#define bM4_TMR42_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x4249077CUL))) +#define bM4_TMR42_CCSR_CKDIV0 (*((volatile unsigned int*)(0x42490900UL))) +#define bM4_TMR42_CCSR_CKDIV1 (*((volatile unsigned int*)(0x42490904UL))) +#define bM4_TMR42_CCSR_CKDIV2 (*((volatile unsigned int*)(0x42490908UL))) +#define bM4_TMR42_CCSR_CKDIV3 (*((volatile unsigned int*)(0x4249090CUL))) +#define bM4_TMR42_CCSR_CLEAR (*((volatile unsigned int*)(0x42490910UL))) +#define bM4_TMR42_CCSR_MODE (*((volatile unsigned int*)(0x42490914UL))) +#define bM4_TMR42_CCSR_STOP (*((volatile unsigned int*)(0x42490918UL))) +#define bM4_TMR42_CCSR_BUFEN (*((volatile unsigned int*)(0x4249091CUL))) +#define bM4_TMR42_CCSR_IRQPEN (*((volatile unsigned int*)(0x42490920UL))) +#define bM4_TMR42_CCSR_IRQPF (*((volatile unsigned int*)(0x42490924UL))) +#define bM4_TMR42_CCSR_IRQZEN (*((volatile unsigned int*)(0x42490934UL))) +#define bM4_TMR42_CCSR_IRQZF (*((volatile unsigned int*)(0x42490938UL))) +#define bM4_TMR42_CCSR_ECKEN (*((volatile unsigned int*)(0x4249093CUL))) +#define bM4_TMR42_CVPR_ZIM0 (*((volatile unsigned int*)(0x42490940UL))) +#define bM4_TMR42_CVPR_ZIM1 (*((volatile unsigned int*)(0x42490944UL))) +#define bM4_TMR42_CVPR_ZIM2 (*((volatile unsigned int*)(0x42490948UL))) +#define bM4_TMR42_CVPR_ZIM3 (*((volatile unsigned int*)(0x4249094CUL))) +#define bM4_TMR42_CVPR_PIM0 (*((volatile unsigned int*)(0x42490950UL))) +#define bM4_TMR42_CVPR_PIM1 (*((volatile unsigned int*)(0x42490954UL))) +#define bM4_TMR42_CVPR_PIM2 (*((volatile unsigned int*)(0x42490958UL))) +#define bM4_TMR42_CVPR_PIM3 (*((volatile unsigned int*)(0x4249095CUL))) +#define bM4_TMR42_CVPR_ZIC0 (*((volatile unsigned int*)(0x42490960UL))) +#define bM4_TMR42_CVPR_ZIC1 (*((volatile unsigned int*)(0x42490964UL))) +#define bM4_TMR42_CVPR_ZIC2 (*((volatile unsigned int*)(0x42490968UL))) +#define bM4_TMR42_CVPR_ZIC3 (*((volatile unsigned int*)(0x4249096CUL))) +#define bM4_TMR42_CVPR_PIC0 (*((volatile unsigned int*)(0x42490970UL))) +#define bM4_TMR42_CVPR_PIC1 (*((volatile unsigned int*)(0x42490974UL))) +#define bM4_TMR42_CVPR_PIC2 (*((volatile unsigned int*)(0x42490978UL))) +#define bM4_TMR42_CVPR_PIC3 (*((volatile unsigned int*)(0x4249097CUL))) +#define bM4_TMR42_POCRU_DIVCK0 (*((volatile unsigned int*)(0x42491300UL))) +#define bM4_TMR42_POCRU_DIVCK1 (*((volatile unsigned int*)(0x42491304UL))) +#define bM4_TMR42_POCRU_DIVCK2 (*((volatile unsigned int*)(0x42491308UL))) +#define bM4_TMR42_POCRU_DIVCK3 (*((volatile unsigned int*)(0x4249130CUL))) +#define bM4_TMR42_POCRU_PWMMD0 (*((volatile unsigned int*)(0x42491310UL))) +#define bM4_TMR42_POCRU_PWMMD1 (*((volatile unsigned int*)(0x42491314UL))) +#define bM4_TMR42_POCRU_LVLS0 (*((volatile unsigned int*)(0x42491318UL))) +#define bM4_TMR42_POCRU_LVLS1 (*((volatile unsigned int*)(0x4249131CUL))) +#define bM4_TMR42_POCRV_DIVCK0 (*((volatile unsigned int*)(0x42491380UL))) +#define bM4_TMR42_POCRV_DIVCK1 (*((volatile unsigned int*)(0x42491384UL))) +#define bM4_TMR42_POCRV_DIVCK2 (*((volatile unsigned int*)(0x42491388UL))) +#define bM4_TMR42_POCRV_DIVCK3 (*((volatile unsigned int*)(0x4249138CUL))) +#define bM4_TMR42_POCRV_PWMMD0 (*((volatile unsigned int*)(0x42491390UL))) +#define bM4_TMR42_POCRV_PWMMD1 (*((volatile unsigned int*)(0x42491394UL))) +#define bM4_TMR42_POCRV_LVLS0 (*((volatile unsigned int*)(0x42491398UL))) +#define bM4_TMR42_POCRV_LVLS1 (*((volatile unsigned int*)(0x4249139CUL))) +#define bM4_TMR42_POCRW_DIVCK0 (*((volatile unsigned int*)(0x42491400UL))) +#define bM4_TMR42_POCRW_DIVCK1 (*((volatile unsigned int*)(0x42491404UL))) +#define bM4_TMR42_POCRW_DIVCK2 (*((volatile unsigned int*)(0x42491408UL))) +#define bM4_TMR42_POCRW_DIVCK3 (*((volatile unsigned int*)(0x4249140CUL))) +#define bM4_TMR42_POCRW_PWMMD0 (*((volatile unsigned int*)(0x42491410UL))) +#define bM4_TMR42_POCRW_PWMMD1 (*((volatile unsigned int*)(0x42491414UL))) +#define bM4_TMR42_POCRW_LVLS0 (*((volatile unsigned int*)(0x42491418UL))) +#define bM4_TMR42_POCRW_LVLS1 (*((volatile unsigned int*)(0x4249141CUL))) +#define bM4_TMR42_RCSR_RTIDU (*((volatile unsigned int*)(0x42491480UL))) +#define bM4_TMR42_RCSR_RTIDV (*((volatile unsigned int*)(0x42491484UL))) +#define bM4_TMR42_RCSR_RTIDW (*((volatile unsigned int*)(0x42491488UL))) +#define bM4_TMR42_RCSR_RTIFU (*((volatile unsigned int*)(0x42491490UL))) +#define bM4_TMR42_RCSR_RTICU (*((volatile unsigned int*)(0x42491494UL))) +#define bM4_TMR42_RCSR_RTEU (*((volatile unsigned int*)(0x42491498UL))) +#define bM4_TMR42_RCSR_RTSU (*((volatile unsigned int*)(0x4249149CUL))) +#define bM4_TMR42_RCSR_RTIFV (*((volatile unsigned int*)(0x424914A0UL))) +#define bM4_TMR42_RCSR_RTICV (*((volatile unsigned int*)(0x424914A4UL))) +#define bM4_TMR42_RCSR_RTEV (*((volatile unsigned int*)(0x424914A8UL))) +#define bM4_TMR42_RCSR_RTSV (*((volatile unsigned int*)(0x424914ACUL))) +#define bM4_TMR42_RCSR_RTIFW (*((volatile unsigned int*)(0x424914B0UL))) +#define bM4_TMR42_RCSR_RTICW (*((volatile unsigned int*)(0x424914B4UL))) +#define bM4_TMR42_RCSR_RTEW (*((volatile unsigned int*)(0x424914B8UL))) +#define bM4_TMR42_RCSR_RTSW (*((volatile unsigned int*)(0x424914BCUL))) +#define bM4_TMR42_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x42491900UL))) +#define bM4_TMR42_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x42491904UL))) +#define bM4_TMR42_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x42491908UL))) +#define bM4_TMR42_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x4249190CUL))) +#define bM4_TMR42_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x42491910UL))) +#define bM4_TMR42_SCSRUH_LMC (*((volatile unsigned int*)(0x42491914UL))) +#define bM4_TMR42_SCSRUH_EVTMS (*((volatile unsigned int*)(0x42491920UL))) +#define bM4_TMR42_SCSRUH_EVTDS (*((volatile unsigned int*)(0x42491924UL))) +#define bM4_TMR42_SCSRUH_DEN (*((volatile unsigned int*)(0x42491930UL))) +#define bM4_TMR42_SCSRUH_PEN (*((volatile unsigned int*)(0x42491934UL))) +#define bM4_TMR42_SCSRUH_UEN (*((volatile unsigned int*)(0x42491938UL))) +#define bM4_TMR42_SCSRUH_ZEN (*((volatile unsigned int*)(0x4249193CUL))) +#define bM4_TMR42_SCMRUH_AMC0 (*((volatile unsigned int*)(0x42491940UL))) +#define bM4_TMR42_SCMRUH_AMC1 (*((volatile unsigned int*)(0x42491944UL))) +#define bM4_TMR42_SCMRUH_AMC2 (*((volatile unsigned int*)(0x42491948UL))) +#define bM4_TMR42_SCMRUH_AMC3 (*((volatile unsigned int*)(0x4249194CUL))) +#define bM4_TMR42_SCMRUH_MZCE (*((volatile unsigned int*)(0x42491958UL))) +#define bM4_TMR42_SCMRUH_MPCE (*((volatile unsigned int*)(0x4249195CUL))) +#define bM4_TMR42_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x42491980UL))) +#define bM4_TMR42_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x42491984UL))) +#define bM4_TMR42_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x42491988UL))) +#define bM4_TMR42_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x4249198CUL))) +#define bM4_TMR42_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x42491990UL))) +#define bM4_TMR42_SCSRUL_LMC (*((volatile unsigned int*)(0x42491994UL))) +#define bM4_TMR42_SCSRUL_EVTMS (*((volatile unsigned int*)(0x424919A0UL))) +#define bM4_TMR42_SCSRUL_EVTDS (*((volatile unsigned int*)(0x424919A4UL))) +#define bM4_TMR42_SCSRUL_DEN (*((volatile unsigned int*)(0x424919B0UL))) +#define bM4_TMR42_SCSRUL_PEN (*((volatile unsigned int*)(0x424919B4UL))) +#define bM4_TMR42_SCSRUL_UEN (*((volatile unsigned int*)(0x424919B8UL))) +#define bM4_TMR42_SCSRUL_ZEN (*((volatile unsigned int*)(0x424919BCUL))) +#define bM4_TMR42_SCMRUL_AMC0 (*((volatile unsigned int*)(0x424919C0UL))) +#define bM4_TMR42_SCMRUL_AMC1 (*((volatile unsigned int*)(0x424919C4UL))) +#define bM4_TMR42_SCMRUL_AMC2 (*((volatile unsigned int*)(0x424919C8UL))) +#define bM4_TMR42_SCMRUL_AMC3 (*((volatile unsigned int*)(0x424919CCUL))) +#define bM4_TMR42_SCMRUL_MZCE (*((volatile unsigned int*)(0x424919D8UL))) +#define bM4_TMR42_SCMRUL_MPCE (*((volatile unsigned int*)(0x424919DCUL))) +#define bM4_TMR42_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x42491A00UL))) +#define bM4_TMR42_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x42491A04UL))) +#define bM4_TMR42_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x42491A08UL))) +#define bM4_TMR42_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x42491A0CUL))) +#define bM4_TMR42_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x42491A10UL))) +#define bM4_TMR42_SCSRVH_LMC (*((volatile unsigned int*)(0x42491A14UL))) +#define bM4_TMR42_SCSRVH_EVTMS (*((volatile unsigned int*)(0x42491A20UL))) +#define bM4_TMR42_SCSRVH_EVTDS (*((volatile unsigned int*)(0x42491A24UL))) +#define bM4_TMR42_SCSRVH_DEN (*((volatile unsigned int*)(0x42491A30UL))) +#define bM4_TMR42_SCSRVH_PEN (*((volatile unsigned int*)(0x42491A34UL))) +#define bM4_TMR42_SCSRVH_UEN (*((volatile unsigned int*)(0x42491A38UL))) +#define bM4_TMR42_SCSRVH_ZEN (*((volatile unsigned int*)(0x42491A3CUL))) +#define bM4_TMR42_SCMRVH_AMC0 (*((volatile unsigned int*)(0x42491A40UL))) +#define bM4_TMR42_SCMRVH_AMC1 (*((volatile unsigned int*)(0x42491A44UL))) +#define bM4_TMR42_SCMRVH_AMC2 (*((volatile unsigned int*)(0x42491A48UL))) +#define bM4_TMR42_SCMRVH_AMC3 (*((volatile unsigned int*)(0x42491A4CUL))) +#define bM4_TMR42_SCMRVH_MZCE (*((volatile unsigned int*)(0x42491A58UL))) +#define bM4_TMR42_SCMRVH_MPCE (*((volatile unsigned int*)(0x42491A5CUL))) +#define bM4_TMR42_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x42491A80UL))) +#define bM4_TMR42_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x42491A84UL))) +#define bM4_TMR42_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x42491A88UL))) +#define bM4_TMR42_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x42491A8CUL))) +#define bM4_TMR42_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x42491A90UL))) +#define bM4_TMR42_SCSRVL_LMC (*((volatile unsigned int*)(0x42491A94UL))) +#define bM4_TMR42_SCSRVL_EVTMS (*((volatile unsigned int*)(0x42491AA0UL))) +#define bM4_TMR42_SCSRVL_EVTDS (*((volatile unsigned int*)(0x42491AA4UL))) +#define bM4_TMR42_SCSRVL_DEN (*((volatile unsigned int*)(0x42491AB0UL))) +#define bM4_TMR42_SCSRVL_PEN (*((volatile unsigned int*)(0x42491AB4UL))) +#define bM4_TMR42_SCSRVL_UEN (*((volatile unsigned int*)(0x42491AB8UL))) +#define bM4_TMR42_SCSRVL_ZEN (*((volatile unsigned int*)(0x42491ABCUL))) +#define bM4_TMR42_SCMRVL_AMC0 (*((volatile unsigned int*)(0x42491AC0UL))) +#define bM4_TMR42_SCMRVL_AMC1 (*((volatile unsigned int*)(0x42491AC4UL))) +#define bM4_TMR42_SCMRVL_AMC2 (*((volatile unsigned int*)(0x42491AC8UL))) +#define bM4_TMR42_SCMRVL_AMC3 (*((volatile unsigned int*)(0x42491ACCUL))) +#define bM4_TMR42_SCMRVL_MZCE (*((volatile unsigned int*)(0x42491AD8UL))) +#define bM4_TMR42_SCMRVL_MPCE (*((volatile unsigned int*)(0x42491ADCUL))) +#define bM4_TMR42_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x42491B00UL))) +#define bM4_TMR42_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x42491B04UL))) +#define bM4_TMR42_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x42491B08UL))) +#define bM4_TMR42_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x42491B0CUL))) +#define bM4_TMR42_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x42491B10UL))) +#define bM4_TMR42_SCSRWH_LMC (*((volatile unsigned int*)(0x42491B14UL))) +#define bM4_TMR42_SCSRWH_EVTMS (*((volatile unsigned int*)(0x42491B20UL))) +#define bM4_TMR42_SCSRWH_EVTDS (*((volatile unsigned int*)(0x42491B24UL))) +#define bM4_TMR42_SCSRWH_DEN (*((volatile unsigned int*)(0x42491B30UL))) +#define bM4_TMR42_SCSRWH_PEN (*((volatile unsigned int*)(0x42491B34UL))) +#define bM4_TMR42_SCSRWH_UEN (*((volatile unsigned int*)(0x42491B38UL))) +#define bM4_TMR42_SCSRWH_ZEN (*((volatile unsigned int*)(0x42491B3CUL))) +#define bM4_TMR42_SCMRWH_AMC0 (*((volatile unsigned int*)(0x42491B40UL))) +#define bM4_TMR42_SCMRWH_AMC1 (*((volatile unsigned int*)(0x42491B44UL))) +#define bM4_TMR42_SCMRWH_AMC2 (*((volatile unsigned int*)(0x42491B48UL))) +#define bM4_TMR42_SCMRWH_AMC3 (*((volatile unsigned int*)(0x42491B4CUL))) +#define bM4_TMR42_SCMRWH_MZCE (*((volatile unsigned int*)(0x42491B58UL))) +#define bM4_TMR42_SCMRWH_MPCE (*((volatile unsigned int*)(0x42491B5CUL))) +#define bM4_TMR42_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x42491B80UL))) +#define bM4_TMR42_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x42491B84UL))) +#define bM4_TMR42_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x42491B88UL))) +#define bM4_TMR42_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x42491B8CUL))) +#define bM4_TMR42_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x42491B90UL))) +#define bM4_TMR42_SCSRWL_LMC (*((volatile unsigned int*)(0x42491B94UL))) +#define bM4_TMR42_SCSRWL_EVTMS (*((volatile unsigned int*)(0x42491BA0UL))) +#define bM4_TMR42_SCSRWL_EVTDS (*((volatile unsigned int*)(0x42491BA4UL))) +#define bM4_TMR42_SCSRWL_DEN (*((volatile unsigned int*)(0x42491BB0UL))) +#define bM4_TMR42_SCSRWL_PEN (*((volatile unsigned int*)(0x42491BB4UL))) +#define bM4_TMR42_SCSRWL_UEN (*((volatile unsigned int*)(0x42491BB8UL))) +#define bM4_TMR42_SCSRWL_ZEN (*((volatile unsigned int*)(0x42491BBCUL))) +#define bM4_TMR42_SCMRWL_AMC0 (*((volatile unsigned int*)(0x42491BC0UL))) +#define bM4_TMR42_SCMRWL_AMC1 (*((volatile unsigned int*)(0x42491BC4UL))) +#define bM4_TMR42_SCMRWL_AMC2 (*((volatile unsigned int*)(0x42491BC8UL))) +#define bM4_TMR42_SCMRWL_AMC3 (*((volatile unsigned int*)(0x42491BCCUL))) +#define bM4_TMR42_SCMRWL_MZCE (*((volatile unsigned int*)(0x42491BD8UL))) +#define bM4_TMR42_SCMRWL_MPCE (*((volatile unsigned int*)(0x42491BDCUL))) +#define bM4_TMR42_ECSR_HOLD (*((volatile unsigned int*)(0x42491E1CUL))) +#define bM4_TMR43_OCSRU_OCEH (*((volatile unsigned int*)(0x42498300UL))) +#define bM4_TMR43_OCSRU_OCEL (*((volatile unsigned int*)(0x42498304UL))) +#define bM4_TMR43_OCSRU_OCPH (*((volatile unsigned int*)(0x42498308UL))) +#define bM4_TMR43_OCSRU_OCPL (*((volatile unsigned int*)(0x4249830CUL))) +#define bM4_TMR43_OCSRU_OCIEH (*((volatile unsigned int*)(0x42498310UL))) +#define bM4_TMR43_OCSRU_OCIEL (*((volatile unsigned int*)(0x42498314UL))) +#define bM4_TMR43_OCSRU_OCFH (*((volatile unsigned int*)(0x42498318UL))) +#define bM4_TMR43_OCSRU_OCFL (*((volatile unsigned int*)(0x4249831CUL))) +#define bM4_TMR43_OCERU_CHBUFEN0 (*((volatile unsigned int*)(0x42498340UL))) +#define bM4_TMR43_OCERU_CHBUFEN1 (*((volatile unsigned int*)(0x42498344UL))) +#define bM4_TMR43_OCERU_CLBUFEN0 (*((volatile unsigned int*)(0x42498348UL))) +#define bM4_TMR43_OCERU_CLBUFEN1 (*((volatile unsigned int*)(0x4249834CUL))) +#define bM4_TMR43_OCERU_MHBUFEN0 (*((volatile unsigned int*)(0x42498350UL))) +#define bM4_TMR43_OCERU_MHBUFEN1 (*((volatile unsigned int*)(0x42498354UL))) +#define bM4_TMR43_OCERU_MLBUFEN0 (*((volatile unsigned int*)(0x42498358UL))) +#define bM4_TMR43_OCERU_MLBUFEN1 (*((volatile unsigned int*)(0x4249835CUL))) +#define bM4_TMR43_OCERU_LMCH (*((volatile unsigned int*)(0x42498360UL))) +#define bM4_TMR43_OCERU_LMCL (*((volatile unsigned int*)(0x42498364UL))) +#define bM4_TMR43_OCERU_LMMH (*((volatile unsigned int*)(0x42498368UL))) +#define bM4_TMR43_OCERU_LMML (*((volatile unsigned int*)(0x4249836CUL))) +#define bM4_TMR43_OCERU_MCECH (*((volatile unsigned int*)(0x42498370UL))) +#define bM4_TMR43_OCERU_MCECL (*((volatile unsigned int*)(0x42498374UL))) +#define bM4_TMR43_OCSRV_OCEH (*((volatile unsigned int*)(0x42498380UL))) +#define bM4_TMR43_OCSRV_OCEL (*((volatile unsigned int*)(0x42498384UL))) +#define bM4_TMR43_OCSRV_OCPH (*((volatile unsigned int*)(0x42498388UL))) +#define bM4_TMR43_OCSRV_OCPL (*((volatile unsigned int*)(0x4249838CUL))) +#define bM4_TMR43_OCSRV_OCIEH (*((volatile unsigned int*)(0x42498390UL))) +#define bM4_TMR43_OCSRV_OCIEL (*((volatile unsigned int*)(0x42498394UL))) +#define bM4_TMR43_OCSRV_OCFH (*((volatile unsigned int*)(0x42498398UL))) +#define bM4_TMR43_OCSRV_OCFL (*((volatile unsigned int*)(0x4249839CUL))) +#define bM4_TMR43_OCERV_CHBUFEN0 (*((volatile unsigned int*)(0x424983C0UL))) +#define bM4_TMR43_OCERV_CHBUFEN1 (*((volatile unsigned int*)(0x424983C4UL))) +#define bM4_TMR43_OCERV_CLBUFEN0 (*((volatile unsigned int*)(0x424983C8UL))) +#define bM4_TMR43_OCERV_CLBUFEN1 (*((volatile unsigned int*)(0x424983CCUL))) +#define bM4_TMR43_OCERV_MHBUFEN0 (*((volatile unsigned int*)(0x424983D0UL))) +#define bM4_TMR43_OCERV_MHBUFEN1 (*((volatile unsigned int*)(0x424983D4UL))) +#define bM4_TMR43_OCERV_MLBUFEN0 (*((volatile unsigned int*)(0x424983D8UL))) +#define bM4_TMR43_OCERV_MLBUFEN1 (*((volatile unsigned int*)(0x424983DCUL))) +#define bM4_TMR43_OCERV_LMCH (*((volatile unsigned int*)(0x424983E0UL))) +#define bM4_TMR43_OCERV_LMCL (*((volatile unsigned int*)(0x424983E4UL))) +#define bM4_TMR43_OCERV_LMMH (*((volatile unsigned int*)(0x424983E8UL))) +#define bM4_TMR43_OCERV_LMML (*((volatile unsigned int*)(0x424983ECUL))) +#define bM4_TMR43_OCERV_MCECH (*((volatile unsigned int*)(0x424983F0UL))) +#define bM4_TMR43_OCERV_MCECL (*((volatile unsigned int*)(0x424983F4UL))) +#define bM4_TMR43_OCSRW_OCEH (*((volatile unsigned int*)(0x42498400UL))) +#define bM4_TMR43_OCSRW_OCEL (*((volatile unsigned int*)(0x42498404UL))) +#define bM4_TMR43_OCSRW_OCPH (*((volatile unsigned int*)(0x42498408UL))) +#define bM4_TMR43_OCSRW_OCPL (*((volatile unsigned int*)(0x4249840CUL))) +#define bM4_TMR43_OCSRW_OCIEH (*((volatile unsigned int*)(0x42498410UL))) +#define bM4_TMR43_OCSRW_OCIEL (*((volatile unsigned int*)(0x42498414UL))) +#define bM4_TMR43_OCSRW_OCFH (*((volatile unsigned int*)(0x42498418UL))) +#define bM4_TMR43_OCSRW_OCFL (*((volatile unsigned int*)(0x4249841CUL))) +#define bM4_TMR43_OCERW_CHBUFEN0 (*((volatile unsigned int*)(0x42498440UL))) +#define bM4_TMR43_OCERW_CHBUFEN1 (*((volatile unsigned int*)(0x42498444UL))) +#define bM4_TMR43_OCERW_CLBUFEN0 (*((volatile unsigned int*)(0x42498448UL))) +#define bM4_TMR43_OCERW_CLBUFEN1 (*((volatile unsigned int*)(0x4249844CUL))) +#define bM4_TMR43_OCERW_MHBUFEN0 (*((volatile unsigned int*)(0x42498450UL))) +#define bM4_TMR43_OCERW_MHBUFEN1 (*((volatile unsigned int*)(0x42498454UL))) +#define bM4_TMR43_OCERW_MLBUFEN0 (*((volatile unsigned int*)(0x42498458UL))) +#define bM4_TMR43_OCERW_MLBUFEN1 (*((volatile unsigned int*)(0x4249845CUL))) +#define bM4_TMR43_OCERW_LMCH (*((volatile unsigned int*)(0x42498460UL))) +#define bM4_TMR43_OCERW_LMCL (*((volatile unsigned int*)(0x42498464UL))) +#define bM4_TMR43_OCERW_LMMH (*((volatile unsigned int*)(0x42498468UL))) +#define bM4_TMR43_OCERW_LMML (*((volatile unsigned int*)(0x4249846CUL))) +#define bM4_TMR43_OCERW_MCECH (*((volatile unsigned int*)(0x42498470UL))) +#define bM4_TMR43_OCERW_MCECL (*((volatile unsigned int*)(0x42498474UL))) +#define bM4_TMR43_OCMRHUH_OCFDCH (*((volatile unsigned int*)(0x42498480UL))) +#define bM4_TMR43_OCMRHUH_OCFPKH (*((volatile unsigned int*)(0x42498484UL))) +#define bM4_TMR43_OCMRHUH_OCFUCH (*((volatile unsigned int*)(0x42498488UL))) +#define bM4_TMR43_OCMRHUH_OCFZRH (*((volatile unsigned int*)(0x4249848CUL))) +#define bM4_TMR43_OCMRHUH_OPDCH0 (*((volatile unsigned int*)(0x42498490UL))) +#define bM4_TMR43_OCMRHUH_OPDCH1 (*((volatile unsigned int*)(0x42498494UL))) +#define bM4_TMR43_OCMRHUH_OPPKH0 (*((volatile unsigned int*)(0x42498498UL))) +#define bM4_TMR43_OCMRHUH_OPPKH1 (*((volatile unsigned int*)(0x4249849CUL))) +#define bM4_TMR43_OCMRHUH_OPUCH0 (*((volatile unsigned int*)(0x424984A0UL))) +#define bM4_TMR43_OCMRHUH_OPUCH1 (*((volatile unsigned int*)(0x424984A4UL))) +#define bM4_TMR43_OCMRHUH_OPZRH0 (*((volatile unsigned int*)(0x424984A8UL))) +#define bM4_TMR43_OCMRHUH_OPZRH1 (*((volatile unsigned int*)(0x424984ACUL))) +#define bM4_TMR43_OCMRHUH_OPNPKH0 (*((volatile unsigned int*)(0x424984B0UL))) +#define bM4_TMR43_OCMRHUH_OPNPKH1 (*((volatile unsigned int*)(0x424984B4UL))) +#define bM4_TMR43_OCMRHUH_OPNZRH0 (*((volatile unsigned int*)(0x424984B8UL))) +#define bM4_TMR43_OCMRHUH_OPNZRH1 (*((volatile unsigned int*)(0x424984BCUL))) +#define bM4_TMR43_OCMRLUL_OCFDCL (*((volatile unsigned int*)(0x42498500UL))) +#define bM4_TMR43_OCMRLUL_OCFPKL (*((volatile unsigned int*)(0x42498504UL))) +#define bM4_TMR43_OCMRLUL_OCFUCL (*((volatile unsigned int*)(0x42498508UL))) +#define bM4_TMR43_OCMRLUL_OCFZRL (*((volatile unsigned int*)(0x4249850CUL))) +#define bM4_TMR43_OCMRLUL_OPDCL0 (*((volatile unsigned int*)(0x42498510UL))) +#define bM4_TMR43_OCMRLUL_OPDCL1 (*((volatile unsigned int*)(0x42498514UL))) +#define bM4_TMR43_OCMRLUL_OPPKL0 (*((volatile unsigned int*)(0x42498518UL))) +#define bM4_TMR43_OCMRLUL_OPPKL1 (*((volatile unsigned int*)(0x4249851CUL))) +#define bM4_TMR43_OCMRLUL_OPUCL0 (*((volatile unsigned int*)(0x42498520UL))) +#define bM4_TMR43_OCMRLUL_OPUCL1 (*((volatile unsigned int*)(0x42498524UL))) +#define bM4_TMR43_OCMRLUL_OPZRL0 (*((volatile unsigned int*)(0x42498528UL))) +#define bM4_TMR43_OCMRLUL_OPZRL1 (*((volatile unsigned int*)(0x4249852CUL))) +#define bM4_TMR43_OCMRLUL_OPNPKL0 (*((volatile unsigned int*)(0x42498530UL))) +#define bM4_TMR43_OCMRLUL_OPNPKL1 (*((volatile unsigned int*)(0x42498534UL))) +#define bM4_TMR43_OCMRLUL_OPNZRL0 (*((volatile unsigned int*)(0x42498538UL))) +#define bM4_TMR43_OCMRLUL_OPNZRL1 (*((volatile unsigned int*)(0x4249853CUL))) +#define bM4_TMR43_OCMRLUL_EOPNDCL0 (*((volatile unsigned int*)(0x42498540UL))) +#define bM4_TMR43_OCMRLUL_EOPNDCL1 (*((volatile unsigned int*)(0x42498544UL))) +#define bM4_TMR43_OCMRLUL_EOPNUCL0 (*((volatile unsigned int*)(0x42498548UL))) +#define bM4_TMR43_OCMRLUL_EOPNUCL1 (*((volatile unsigned int*)(0x4249854CUL))) +#define bM4_TMR43_OCMRLUL_EOPDCL0 (*((volatile unsigned int*)(0x42498550UL))) +#define bM4_TMR43_OCMRLUL_EOPDCL1 (*((volatile unsigned int*)(0x42498554UL))) +#define bM4_TMR43_OCMRLUL_EOPPKL0 (*((volatile unsigned int*)(0x42498558UL))) +#define bM4_TMR43_OCMRLUL_EOPPKL1 (*((volatile unsigned int*)(0x4249855CUL))) +#define bM4_TMR43_OCMRLUL_EOPUCL0 (*((volatile unsigned int*)(0x42498560UL))) +#define bM4_TMR43_OCMRLUL_EOPUCL1 (*((volatile unsigned int*)(0x42498564UL))) +#define bM4_TMR43_OCMRLUL_EOPZRL0 (*((volatile unsigned int*)(0x42498568UL))) +#define bM4_TMR43_OCMRLUL_EOPZRL1 (*((volatile unsigned int*)(0x4249856CUL))) +#define bM4_TMR43_OCMRLUL_EOPNPKL0 (*((volatile unsigned int*)(0x42498570UL))) +#define bM4_TMR43_OCMRLUL_EOPNPKL1 (*((volatile unsigned int*)(0x42498574UL))) +#define bM4_TMR43_OCMRLUL_EOPNZRL0 (*((volatile unsigned int*)(0x42498578UL))) +#define bM4_TMR43_OCMRLUL_EOPNZRL1 (*((volatile unsigned int*)(0x4249857CUL))) +#define bM4_TMR43_OCMRHVH_OCFDCH (*((volatile unsigned int*)(0x42498580UL))) +#define bM4_TMR43_OCMRHVH_OCFPKH (*((volatile unsigned int*)(0x42498584UL))) +#define bM4_TMR43_OCMRHVH_OCFUCH (*((volatile unsigned int*)(0x42498588UL))) +#define bM4_TMR43_OCMRHVH_OCFZRH (*((volatile unsigned int*)(0x4249858CUL))) +#define bM4_TMR43_OCMRHVH_OPDCH0 (*((volatile unsigned int*)(0x42498590UL))) +#define bM4_TMR43_OCMRHVH_OPDCH1 (*((volatile unsigned int*)(0x42498594UL))) +#define bM4_TMR43_OCMRHVH_OPPKH0 (*((volatile unsigned int*)(0x42498598UL))) +#define bM4_TMR43_OCMRHVH_OPPKH1 (*((volatile unsigned int*)(0x4249859CUL))) +#define bM4_TMR43_OCMRHVH_OPUCH0 (*((volatile unsigned int*)(0x424985A0UL))) +#define bM4_TMR43_OCMRHVH_OPUCH1 (*((volatile unsigned int*)(0x424985A4UL))) +#define bM4_TMR43_OCMRHVH_OPZRH0 (*((volatile unsigned int*)(0x424985A8UL))) +#define bM4_TMR43_OCMRHVH_OPZRH1 (*((volatile unsigned int*)(0x424985ACUL))) +#define bM4_TMR43_OCMRHVH_OPNPKH0 (*((volatile unsigned int*)(0x424985B0UL))) +#define bM4_TMR43_OCMRHVH_OPNPKH1 (*((volatile unsigned int*)(0x424985B4UL))) +#define bM4_TMR43_OCMRHVH_OPNZRH0 (*((volatile unsigned int*)(0x424985B8UL))) +#define bM4_TMR43_OCMRHVH_OPNZRH1 (*((volatile unsigned int*)(0x424985BCUL))) +#define bM4_TMR43_OCMRLVL_OCFDCL (*((volatile unsigned int*)(0x42498600UL))) +#define bM4_TMR43_OCMRLVL_OCFPKL (*((volatile unsigned int*)(0x42498604UL))) +#define bM4_TMR43_OCMRLVL_OCFUCL (*((volatile unsigned int*)(0x42498608UL))) +#define bM4_TMR43_OCMRLVL_OCFZRL (*((volatile unsigned int*)(0x4249860CUL))) +#define bM4_TMR43_OCMRLVL_OPDCL0 (*((volatile unsigned int*)(0x42498610UL))) +#define bM4_TMR43_OCMRLVL_OPDCL1 (*((volatile unsigned int*)(0x42498614UL))) +#define bM4_TMR43_OCMRLVL_OPPKL0 (*((volatile unsigned int*)(0x42498618UL))) +#define bM4_TMR43_OCMRLVL_OPPKL1 (*((volatile unsigned int*)(0x4249861CUL))) +#define bM4_TMR43_OCMRLVL_OPUCL0 (*((volatile unsigned int*)(0x42498620UL))) +#define bM4_TMR43_OCMRLVL_OPUCL1 (*((volatile unsigned int*)(0x42498624UL))) +#define bM4_TMR43_OCMRLVL_OPZRL0 (*((volatile unsigned int*)(0x42498628UL))) +#define bM4_TMR43_OCMRLVL_OPZRL1 (*((volatile unsigned int*)(0x4249862CUL))) +#define bM4_TMR43_OCMRLVL_OPNPKL0 (*((volatile unsigned int*)(0x42498630UL))) +#define bM4_TMR43_OCMRLVL_OPNPKL1 (*((volatile unsigned int*)(0x42498634UL))) +#define bM4_TMR43_OCMRLVL_OPNZRL0 (*((volatile unsigned int*)(0x42498638UL))) +#define bM4_TMR43_OCMRLVL_OPNZRL1 (*((volatile unsigned int*)(0x4249863CUL))) +#define bM4_TMR43_OCMRLVL_EOPNDCL0 (*((volatile unsigned int*)(0x42498640UL))) +#define bM4_TMR43_OCMRLVL_EOPNDCL1 (*((volatile unsigned int*)(0x42498644UL))) +#define bM4_TMR43_OCMRLVL_EOPNUCL0 (*((volatile unsigned int*)(0x42498648UL))) +#define bM4_TMR43_OCMRLVL_EOPNUCL1 (*((volatile unsigned int*)(0x4249864CUL))) +#define bM4_TMR43_OCMRLVL_EOPDCL0 (*((volatile unsigned int*)(0x42498650UL))) +#define bM4_TMR43_OCMRLVL_EOPDCL1 (*((volatile unsigned int*)(0x42498654UL))) +#define bM4_TMR43_OCMRLVL_EOPPKL0 (*((volatile unsigned int*)(0x42498658UL))) +#define bM4_TMR43_OCMRLVL_EOPPKL1 (*((volatile unsigned int*)(0x4249865CUL))) +#define bM4_TMR43_OCMRLVL_EOPUCL0 (*((volatile unsigned int*)(0x42498660UL))) +#define bM4_TMR43_OCMRLVL_EOPUCL1 (*((volatile unsigned int*)(0x42498664UL))) +#define bM4_TMR43_OCMRLVL_EOPZRL0 (*((volatile unsigned int*)(0x42498668UL))) +#define bM4_TMR43_OCMRLVL_EOPZRL1 (*((volatile unsigned int*)(0x4249866CUL))) +#define bM4_TMR43_OCMRLVL_EOPNPKL0 (*((volatile unsigned int*)(0x42498670UL))) +#define bM4_TMR43_OCMRLVL_EOPNPKL1 (*((volatile unsigned int*)(0x42498674UL))) +#define bM4_TMR43_OCMRLVL_EOPNZRL0 (*((volatile unsigned int*)(0x42498678UL))) +#define bM4_TMR43_OCMRLVL_EOPNZRL1 (*((volatile unsigned int*)(0x4249867CUL))) +#define bM4_TMR43_OCMRHWH_OCFDCH (*((volatile unsigned int*)(0x42498680UL))) +#define bM4_TMR43_OCMRHWH_OCFPKH (*((volatile unsigned int*)(0x42498684UL))) +#define bM4_TMR43_OCMRHWH_OCFUCH (*((volatile unsigned int*)(0x42498688UL))) +#define bM4_TMR43_OCMRHWH_OCFZRH (*((volatile unsigned int*)(0x4249868CUL))) +#define bM4_TMR43_OCMRHWH_OPDCH0 (*((volatile unsigned int*)(0x42498690UL))) +#define bM4_TMR43_OCMRHWH_OPDCH1 (*((volatile unsigned int*)(0x42498694UL))) +#define bM4_TMR43_OCMRHWH_OPPKH0 (*((volatile unsigned int*)(0x42498698UL))) +#define bM4_TMR43_OCMRHWH_OPPKH1 (*((volatile unsigned int*)(0x4249869CUL))) +#define bM4_TMR43_OCMRHWH_OPUCH0 (*((volatile unsigned int*)(0x424986A0UL))) +#define bM4_TMR43_OCMRHWH_OPUCH1 (*((volatile unsigned int*)(0x424986A4UL))) +#define bM4_TMR43_OCMRHWH_OPZRH0 (*((volatile unsigned int*)(0x424986A8UL))) +#define bM4_TMR43_OCMRHWH_OPZRH1 (*((volatile unsigned int*)(0x424986ACUL))) +#define bM4_TMR43_OCMRHWH_OPNPKH0 (*((volatile unsigned int*)(0x424986B0UL))) +#define bM4_TMR43_OCMRHWH_OPNPKH1 (*((volatile unsigned int*)(0x424986B4UL))) +#define bM4_TMR43_OCMRHWH_OPNZRH0 (*((volatile unsigned int*)(0x424986B8UL))) +#define bM4_TMR43_OCMRHWH_OPNZRH1 (*((volatile unsigned int*)(0x424986BCUL))) +#define bM4_TMR43_OCMRLWL_OCFDCL (*((volatile unsigned int*)(0x42498700UL))) +#define bM4_TMR43_OCMRLWL_OCFPKL (*((volatile unsigned int*)(0x42498704UL))) +#define bM4_TMR43_OCMRLWL_OCFUCL (*((volatile unsigned int*)(0x42498708UL))) +#define bM4_TMR43_OCMRLWL_OCFZRL (*((volatile unsigned int*)(0x4249870CUL))) +#define bM4_TMR43_OCMRLWL_OPDCL0 (*((volatile unsigned int*)(0x42498710UL))) +#define bM4_TMR43_OCMRLWL_OPDCL1 (*((volatile unsigned int*)(0x42498714UL))) +#define bM4_TMR43_OCMRLWL_OPPKL0 (*((volatile unsigned int*)(0x42498718UL))) +#define bM4_TMR43_OCMRLWL_OPPKL1 (*((volatile unsigned int*)(0x4249871CUL))) +#define bM4_TMR43_OCMRLWL_OPUCL0 (*((volatile unsigned int*)(0x42498720UL))) +#define bM4_TMR43_OCMRLWL_OPUCL1 (*((volatile unsigned int*)(0x42498724UL))) +#define bM4_TMR43_OCMRLWL_OPZRL0 (*((volatile unsigned int*)(0x42498728UL))) +#define bM4_TMR43_OCMRLWL_OPZRL1 (*((volatile unsigned int*)(0x4249872CUL))) +#define bM4_TMR43_OCMRLWL_OPNPKL0 (*((volatile unsigned int*)(0x42498730UL))) +#define bM4_TMR43_OCMRLWL_OPNPKL1 (*((volatile unsigned int*)(0x42498734UL))) +#define bM4_TMR43_OCMRLWL_OPNZRL0 (*((volatile unsigned int*)(0x42498738UL))) +#define bM4_TMR43_OCMRLWL_OPNZRL1 (*((volatile unsigned int*)(0x4249873CUL))) +#define bM4_TMR43_OCMRLWL_EOPNDCL0 (*((volatile unsigned int*)(0x42498740UL))) +#define bM4_TMR43_OCMRLWL_EOPNDCL1 (*((volatile unsigned int*)(0x42498744UL))) +#define bM4_TMR43_OCMRLWL_EOPNUCL0 (*((volatile unsigned int*)(0x42498748UL))) +#define bM4_TMR43_OCMRLWL_EOPNUCL1 (*((volatile unsigned int*)(0x4249874CUL))) +#define bM4_TMR43_OCMRLWL_EOPDCL0 (*((volatile unsigned int*)(0x42498750UL))) +#define bM4_TMR43_OCMRLWL_EOPDCL1 (*((volatile unsigned int*)(0x42498754UL))) +#define bM4_TMR43_OCMRLWL_EOPPKL0 (*((volatile unsigned int*)(0x42498758UL))) +#define bM4_TMR43_OCMRLWL_EOPPKL1 (*((volatile unsigned int*)(0x4249875CUL))) +#define bM4_TMR43_OCMRLWL_EOPUCL0 (*((volatile unsigned int*)(0x42498760UL))) +#define bM4_TMR43_OCMRLWL_EOPUCL1 (*((volatile unsigned int*)(0x42498764UL))) +#define bM4_TMR43_OCMRLWL_EOPZRL0 (*((volatile unsigned int*)(0x42498768UL))) +#define bM4_TMR43_OCMRLWL_EOPZRL1 (*((volatile unsigned int*)(0x4249876CUL))) +#define bM4_TMR43_OCMRLWL_EOPNPKL0 (*((volatile unsigned int*)(0x42498770UL))) +#define bM4_TMR43_OCMRLWL_EOPNPKL1 (*((volatile unsigned int*)(0x42498774UL))) +#define bM4_TMR43_OCMRLWL_EOPNZRL0 (*((volatile unsigned int*)(0x42498778UL))) +#define bM4_TMR43_OCMRLWL_EOPNZRL1 (*((volatile unsigned int*)(0x4249877CUL))) +#define bM4_TMR43_CCSR_CKDIV0 (*((volatile unsigned int*)(0x42498900UL))) +#define bM4_TMR43_CCSR_CKDIV1 (*((volatile unsigned int*)(0x42498904UL))) +#define bM4_TMR43_CCSR_CKDIV2 (*((volatile unsigned int*)(0x42498908UL))) +#define bM4_TMR43_CCSR_CKDIV3 (*((volatile unsigned int*)(0x4249890CUL))) +#define bM4_TMR43_CCSR_CLEAR (*((volatile unsigned int*)(0x42498910UL))) +#define bM4_TMR43_CCSR_MODE (*((volatile unsigned int*)(0x42498914UL))) +#define bM4_TMR43_CCSR_STOP (*((volatile unsigned int*)(0x42498918UL))) +#define bM4_TMR43_CCSR_BUFEN (*((volatile unsigned int*)(0x4249891CUL))) +#define bM4_TMR43_CCSR_IRQPEN (*((volatile unsigned int*)(0x42498920UL))) +#define bM4_TMR43_CCSR_IRQPF (*((volatile unsigned int*)(0x42498924UL))) +#define bM4_TMR43_CCSR_IRQZEN (*((volatile unsigned int*)(0x42498934UL))) +#define bM4_TMR43_CCSR_IRQZF (*((volatile unsigned int*)(0x42498938UL))) +#define bM4_TMR43_CCSR_ECKEN (*((volatile unsigned int*)(0x4249893CUL))) +#define bM4_TMR43_CVPR_ZIM0 (*((volatile unsigned int*)(0x42498940UL))) +#define bM4_TMR43_CVPR_ZIM1 (*((volatile unsigned int*)(0x42498944UL))) +#define bM4_TMR43_CVPR_ZIM2 (*((volatile unsigned int*)(0x42498948UL))) +#define bM4_TMR43_CVPR_ZIM3 (*((volatile unsigned int*)(0x4249894CUL))) +#define bM4_TMR43_CVPR_PIM0 (*((volatile unsigned int*)(0x42498950UL))) +#define bM4_TMR43_CVPR_PIM1 (*((volatile unsigned int*)(0x42498954UL))) +#define bM4_TMR43_CVPR_PIM2 (*((volatile unsigned int*)(0x42498958UL))) +#define bM4_TMR43_CVPR_PIM3 (*((volatile unsigned int*)(0x4249895CUL))) +#define bM4_TMR43_CVPR_ZIC0 (*((volatile unsigned int*)(0x42498960UL))) +#define bM4_TMR43_CVPR_ZIC1 (*((volatile unsigned int*)(0x42498964UL))) +#define bM4_TMR43_CVPR_ZIC2 (*((volatile unsigned int*)(0x42498968UL))) +#define bM4_TMR43_CVPR_ZIC3 (*((volatile unsigned int*)(0x4249896CUL))) +#define bM4_TMR43_CVPR_PIC0 (*((volatile unsigned int*)(0x42498970UL))) +#define bM4_TMR43_CVPR_PIC1 (*((volatile unsigned int*)(0x42498974UL))) +#define bM4_TMR43_CVPR_PIC2 (*((volatile unsigned int*)(0x42498978UL))) +#define bM4_TMR43_CVPR_PIC3 (*((volatile unsigned int*)(0x4249897CUL))) +#define bM4_TMR43_POCRU_DIVCK0 (*((volatile unsigned int*)(0x42499300UL))) +#define bM4_TMR43_POCRU_DIVCK1 (*((volatile unsigned int*)(0x42499304UL))) +#define bM4_TMR43_POCRU_DIVCK2 (*((volatile unsigned int*)(0x42499308UL))) +#define bM4_TMR43_POCRU_DIVCK3 (*((volatile unsigned int*)(0x4249930CUL))) +#define bM4_TMR43_POCRU_PWMMD0 (*((volatile unsigned int*)(0x42499310UL))) +#define bM4_TMR43_POCRU_PWMMD1 (*((volatile unsigned int*)(0x42499314UL))) +#define bM4_TMR43_POCRU_LVLS0 (*((volatile unsigned int*)(0x42499318UL))) +#define bM4_TMR43_POCRU_LVLS1 (*((volatile unsigned int*)(0x4249931CUL))) +#define bM4_TMR43_POCRV_DIVCK0 (*((volatile unsigned int*)(0x42499380UL))) +#define bM4_TMR43_POCRV_DIVCK1 (*((volatile unsigned int*)(0x42499384UL))) +#define bM4_TMR43_POCRV_DIVCK2 (*((volatile unsigned int*)(0x42499388UL))) +#define bM4_TMR43_POCRV_DIVCK3 (*((volatile unsigned int*)(0x4249938CUL))) +#define bM4_TMR43_POCRV_PWMMD0 (*((volatile unsigned int*)(0x42499390UL))) +#define bM4_TMR43_POCRV_PWMMD1 (*((volatile unsigned int*)(0x42499394UL))) +#define bM4_TMR43_POCRV_LVLS0 (*((volatile unsigned int*)(0x42499398UL))) +#define bM4_TMR43_POCRV_LVLS1 (*((volatile unsigned int*)(0x4249939CUL))) +#define bM4_TMR43_POCRW_DIVCK0 (*((volatile unsigned int*)(0x42499400UL))) +#define bM4_TMR43_POCRW_DIVCK1 (*((volatile unsigned int*)(0x42499404UL))) +#define bM4_TMR43_POCRW_DIVCK2 (*((volatile unsigned int*)(0x42499408UL))) +#define bM4_TMR43_POCRW_DIVCK3 (*((volatile unsigned int*)(0x4249940CUL))) +#define bM4_TMR43_POCRW_PWMMD0 (*((volatile unsigned int*)(0x42499410UL))) +#define bM4_TMR43_POCRW_PWMMD1 (*((volatile unsigned int*)(0x42499414UL))) +#define bM4_TMR43_POCRW_LVLS0 (*((volatile unsigned int*)(0x42499418UL))) +#define bM4_TMR43_POCRW_LVLS1 (*((volatile unsigned int*)(0x4249941CUL))) +#define bM4_TMR43_RCSR_RTIDU (*((volatile unsigned int*)(0x42499480UL))) +#define bM4_TMR43_RCSR_RTIDV (*((volatile unsigned int*)(0x42499484UL))) +#define bM4_TMR43_RCSR_RTIDW (*((volatile unsigned int*)(0x42499488UL))) +#define bM4_TMR43_RCSR_RTIFU (*((volatile unsigned int*)(0x42499490UL))) +#define bM4_TMR43_RCSR_RTICU (*((volatile unsigned int*)(0x42499494UL))) +#define bM4_TMR43_RCSR_RTEU (*((volatile unsigned int*)(0x42499498UL))) +#define bM4_TMR43_RCSR_RTSU (*((volatile unsigned int*)(0x4249949CUL))) +#define bM4_TMR43_RCSR_RTIFV (*((volatile unsigned int*)(0x424994A0UL))) +#define bM4_TMR43_RCSR_RTICV (*((volatile unsigned int*)(0x424994A4UL))) +#define bM4_TMR43_RCSR_RTEV (*((volatile unsigned int*)(0x424994A8UL))) +#define bM4_TMR43_RCSR_RTSV (*((volatile unsigned int*)(0x424994ACUL))) +#define bM4_TMR43_RCSR_RTIFW (*((volatile unsigned int*)(0x424994B0UL))) +#define bM4_TMR43_RCSR_RTICW (*((volatile unsigned int*)(0x424994B4UL))) +#define bM4_TMR43_RCSR_RTEW (*((volatile unsigned int*)(0x424994B8UL))) +#define bM4_TMR43_RCSR_RTSW (*((volatile unsigned int*)(0x424994BCUL))) +#define bM4_TMR43_SCSRUH_BUFEN0 (*((volatile unsigned int*)(0x42499900UL))) +#define bM4_TMR43_SCSRUH_BUFEN1 (*((volatile unsigned int*)(0x42499904UL))) +#define bM4_TMR43_SCSRUH_EVTOS0 (*((volatile unsigned int*)(0x42499908UL))) +#define bM4_TMR43_SCSRUH_EVTOS1 (*((volatile unsigned int*)(0x4249990CUL))) +#define bM4_TMR43_SCSRUH_EVTOS2 (*((volatile unsigned int*)(0x42499910UL))) +#define bM4_TMR43_SCSRUH_LMC (*((volatile unsigned int*)(0x42499914UL))) +#define bM4_TMR43_SCSRUH_EVTMS (*((volatile unsigned int*)(0x42499920UL))) +#define bM4_TMR43_SCSRUH_EVTDS (*((volatile unsigned int*)(0x42499924UL))) +#define bM4_TMR43_SCSRUH_DEN (*((volatile unsigned int*)(0x42499930UL))) +#define bM4_TMR43_SCSRUH_PEN (*((volatile unsigned int*)(0x42499934UL))) +#define bM4_TMR43_SCSRUH_UEN (*((volatile unsigned int*)(0x42499938UL))) +#define bM4_TMR43_SCSRUH_ZEN (*((volatile unsigned int*)(0x4249993CUL))) +#define bM4_TMR43_SCMRUH_AMC0 (*((volatile unsigned int*)(0x42499940UL))) +#define bM4_TMR43_SCMRUH_AMC1 (*((volatile unsigned int*)(0x42499944UL))) +#define bM4_TMR43_SCMRUH_AMC2 (*((volatile unsigned int*)(0x42499948UL))) +#define bM4_TMR43_SCMRUH_AMC3 (*((volatile unsigned int*)(0x4249994CUL))) +#define bM4_TMR43_SCMRUH_MZCE (*((volatile unsigned int*)(0x42499958UL))) +#define bM4_TMR43_SCMRUH_MPCE (*((volatile unsigned int*)(0x4249995CUL))) +#define bM4_TMR43_SCSRUL_BUFEN0 (*((volatile unsigned int*)(0x42499980UL))) +#define bM4_TMR43_SCSRUL_BUFEN1 (*((volatile unsigned int*)(0x42499984UL))) +#define bM4_TMR43_SCSRUL_EVTOS0 (*((volatile unsigned int*)(0x42499988UL))) +#define bM4_TMR43_SCSRUL_EVTOS1 (*((volatile unsigned int*)(0x4249998CUL))) +#define bM4_TMR43_SCSRUL_EVTOS2 (*((volatile unsigned int*)(0x42499990UL))) +#define bM4_TMR43_SCSRUL_LMC (*((volatile unsigned int*)(0x42499994UL))) +#define bM4_TMR43_SCSRUL_EVTMS (*((volatile unsigned int*)(0x424999A0UL))) +#define bM4_TMR43_SCSRUL_EVTDS (*((volatile unsigned int*)(0x424999A4UL))) +#define bM4_TMR43_SCSRUL_DEN (*((volatile unsigned int*)(0x424999B0UL))) +#define bM4_TMR43_SCSRUL_PEN (*((volatile unsigned int*)(0x424999B4UL))) +#define bM4_TMR43_SCSRUL_UEN (*((volatile unsigned int*)(0x424999B8UL))) +#define bM4_TMR43_SCSRUL_ZEN (*((volatile unsigned int*)(0x424999BCUL))) +#define bM4_TMR43_SCMRUL_AMC0 (*((volatile unsigned int*)(0x424999C0UL))) +#define bM4_TMR43_SCMRUL_AMC1 (*((volatile unsigned int*)(0x424999C4UL))) +#define bM4_TMR43_SCMRUL_AMC2 (*((volatile unsigned int*)(0x424999C8UL))) +#define bM4_TMR43_SCMRUL_AMC3 (*((volatile unsigned int*)(0x424999CCUL))) +#define bM4_TMR43_SCMRUL_MZCE (*((volatile unsigned int*)(0x424999D8UL))) +#define bM4_TMR43_SCMRUL_MPCE (*((volatile unsigned int*)(0x424999DCUL))) +#define bM4_TMR43_SCSRVH_BUFEN0 (*((volatile unsigned int*)(0x42499A00UL))) +#define bM4_TMR43_SCSRVH_BUFEN1 (*((volatile unsigned int*)(0x42499A04UL))) +#define bM4_TMR43_SCSRVH_EVTOS0 (*((volatile unsigned int*)(0x42499A08UL))) +#define bM4_TMR43_SCSRVH_EVTOS1 (*((volatile unsigned int*)(0x42499A0CUL))) +#define bM4_TMR43_SCSRVH_EVTOS2 (*((volatile unsigned int*)(0x42499A10UL))) +#define bM4_TMR43_SCSRVH_LMC (*((volatile unsigned int*)(0x42499A14UL))) +#define bM4_TMR43_SCSRVH_EVTMS (*((volatile unsigned int*)(0x42499A20UL))) +#define bM4_TMR43_SCSRVH_EVTDS (*((volatile unsigned int*)(0x42499A24UL))) +#define bM4_TMR43_SCSRVH_DEN (*((volatile unsigned int*)(0x42499A30UL))) +#define bM4_TMR43_SCSRVH_PEN (*((volatile unsigned int*)(0x42499A34UL))) +#define bM4_TMR43_SCSRVH_UEN (*((volatile unsigned int*)(0x42499A38UL))) +#define bM4_TMR43_SCSRVH_ZEN (*((volatile unsigned int*)(0x42499A3CUL))) +#define bM4_TMR43_SCMRVH_AMC0 (*((volatile unsigned int*)(0x42499A40UL))) +#define bM4_TMR43_SCMRVH_AMC1 (*((volatile unsigned int*)(0x42499A44UL))) +#define bM4_TMR43_SCMRVH_AMC2 (*((volatile unsigned int*)(0x42499A48UL))) +#define bM4_TMR43_SCMRVH_AMC3 (*((volatile unsigned int*)(0x42499A4CUL))) +#define bM4_TMR43_SCMRVH_MZCE (*((volatile unsigned int*)(0x42499A58UL))) +#define bM4_TMR43_SCMRVH_MPCE (*((volatile unsigned int*)(0x42499A5CUL))) +#define bM4_TMR43_SCSRVL_BUFEN0 (*((volatile unsigned int*)(0x42499A80UL))) +#define bM4_TMR43_SCSRVL_BUFEN1 (*((volatile unsigned int*)(0x42499A84UL))) +#define bM4_TMR43_SCSRVL_EVTOS0 (*((volatile unsigned int*)(0x42499A88UL))) +#define bM4_TMR43_SCSRVL_EVTOS1 (*((volatile unsigned int*)(0x42499A8CUL))) +#define bM4_TMR43_SCSRVL_EVTOS2 (*((volatile unsigned int*)(0x42499A90UL))) +#define bM4_TMR43_SCSRVL_LMC (*((volatile unsigned int*)(0x42499A94UL))) +#define bM4_TMR43_SCSRVL_EVTMS (*((volatile unsigned int*)(0x42499AA0UL))) +#define bM4_TMR43_SCSRVL_EVTDS (*((volatile unsigned int*)(0x42499AA4UL))) +#define bM4_TMR43_SCSRVL_DEN (*((volatile unsigned int*)(0x42499AB0UL))) +#define bM4_TMR43_SCSRVL_PEN (*((volatile unsigned int*)(0x42499AB4UL))) +#define bM4_TMR43_SCSRVL_UEN (*((volatile unsigned int*)(0x42499AB8UL))) +#define bM4_TMR43_SCSRVL_ZEN (*((volatile unsigned int*)(0x42499ABCUL))) +#define bM4_TMR43_SCMRVL_AMC0 (*((volatile unsigned int*)(0x42499AC0UL))) +#define bM4_TMR43_SCMRVL_AMC1 (*((volatile unsigned int*)(0x42499AC4UL))) +#define bM4_TMR43_SCMRVL_AMC2 (*((volatile unsigned int*)(0x42499AC8UL))) +#define bM4_TMR43_SCMRVL_AMC3 (*((volatile unsigned int*)(0x42499ACCUL))) +#define bM4_TMR43_SCMRVL_MZCE (*((volatile unsigned int*)(0x42499AD8UL))) +#define bM4_TMR43_SCMRVL_MPCE (*((volatile unsigned int*)(0x42499ADCUL))) +#define bM4_TMR43_SCSRWH_BUFEN0 (*((volatile unsigned int*)(0x42499B00UL))) +#define bM4_TMR43_SCSRWH_BUFEN1 (*((volatile unsigned int*)(0x42499B04UL))) +#define bM4_TMR43_SCSRWH_EVTOS0 (*((volatile unsigned int*)(0x42499B08UL))) +#define bM4_TMR43_SCSRWH_EVTOS1 (*((volatile unsigned int*)(0x42499B0CUL))) +#define bM4_TMR43_SCSRWH_EVTOS2 (*((volatile unsigned int*)(0x42499B10UL))) +#define bM4_TMR43_SCSRWH_LMC (*((volatile unsigned int*)(0x42499B14UL))) +#define bM4_TMR43_SCSRWH_EVTMS (*((volatile unsigned int*)(0x42499B20UL))) +#define bM4_TMR43_SCSRWH_EVTDS (*((volatile unsigned int*)(0x42499B24UL))) +#define bM4_TMR43_SCSRWH_DEN (*((volatile unsigned int*)(0x42499B30UL))) +#define bM4_TMR43_SCSRWH_PEN (*((volatile unsigned int*)(0x42499B34UL))) +#define bM4_TMR43_SCSRWH_UEN (*((volatile unsigned int*)(0x42499B38UL))) +#define bM4_TMR43_SCSRWH_ZEN (*((volatile unsigned int*)(0x42499B3CUL))) +#define bM4_TMR43_SCMRWH_AMC0 (*((volatile unsigned int*)(0x42499B40UL))) +#define bM4_TMR43_SCMRWH_AMC1 (*((volatile unsigned int*)(0x42499B44UL))) +#define bM4_TMR43_SCMRWH_AMC2 (*((volatile unsigned int*)(0x42499B48UL))) +#define bM4_TMR43_SCMRWH_AMC3 (*((volatile unsigned int*)(0x42499B4CUL))) +#define bM4_TMR43_SCMRWH_MZCE (*((volatile unsigned int*)(0x42499B58UL))) +#define bM4_TMR43_SCMRWH_MPCE (*((volatile unsigned int*)(0x42499B5CUL))) +#define bM4_TMR43_SCSRWL_BUFEN0 (*((volatile unsigned int*)(0x42499B80UL))) +#define bM4_TMR43_SCSRWL_BUFEN1 (*((volatile unsigned int*)(0x42499B84UL))) +#define bM4_TMR43_SCSRWL_EVTOS0 (*((volatile unsigned int*)(0x42499B88UL))) +#define bM4_TMR43_SCSRWL_EVTOS1 (*((volatile unsigned int*)(0x42499B8CUL))) +#define bM4_TMR43_SCSRWL_EVTOS2 (*((volatile unsigned int*)(0x42499B90UL))) +#define bM4_TMR43_SCSRWL_LMC (*((volatile unsigned int*)(0x42499B94UL))) +#define bM4_TMR43_SCSRWL_EVTMS (*((volatile unsigned int*)(0x42499BA0UL))) +#define bM4_TMR43_SCSRWL_EVTDS (*((volatile unsigned int*)(0x42499BA4UL))) +#define bM4_TMR43_SCSRWL_DEN (*((volatile unsigned int*)(0x42499BB0UL))) +#define bM4_TMR43_SCSRWL_PEN (*((volatile unsigned int*)(0x42499BB4UL))) +#define bM4_TMR43_SCSRWL_UEN (*((volatile unsigned int*)(0x42499BB8UL))) +#define bM4_TMR43_SCSRWL_ZEN (*((volatile unsigned int*)(0x42499BBCUL))) +#define bM4_TMR43_SCMRWL_AMC0 (*((volatile unsigned int*)(0x42499BC0UL))) +#define bM4_TMR43_SCMRWL_AMC1 (*((volatile unsigned int*)(0x42499BC4UL))) +#define bM4_TMR43_SCMRWL_AMC2 (*((volatile unsigned int*)(0x42499BC8UL))) +#define bM4_TMR43_SCMRWL_AMC3 (*((volatile unsigned int*)(0x42499BCCUL))) +#define bM4_TMR43_SCMRWL_MZCE (*((volatile unsigned int*)(0x42499BD8UL))) +#define bM4_TMR43_SCMRWL_MPCE (*((volatile unsigned int*)(0x42499BDCUL))) +#define bM4_TMR43_ECSR_HOLD (*((volatile unsigned int*)(0x42499E1CUL))) +#define bM4_TMR4_CR_ECER1_EMBVAL0 (*((volatile unsigned int*)(0x42AA8100UL))) +#define bM4_TMR4_CR_ECER1_EMBVAL1 (*((volatile unsigned int*)(0x42AA8104UL))) +#define bM4_TMR4_CR_ECER2_EMBVAL0 (*((volatile unsigned int*)(0x42AA8180UL))) +#define bM4_TMR4_CR_ECER2_EMBVAL1 (*((volatile unsigned int*)(0x42AA8184UL))) +#define bM4_TMR4_CR_ECER3_EMBVAL0 (*((volatile unsigned int*)(0x42AA8200UL))) +#define bM4_TMR4_CR_ECER3_EMBVAL1 (*((volatile unsigned int*)(0x42AA8204UL))) +#define bM4_TMR61_CNTER_CNT0 (*((volatile unsigned int*)(0x42300000UL))) +#define bM4_TMR61_CNTER_CNT1 (*((volatile unsigned int*)(0x42300004UL))) +#define bM4_TMR61_CNTER_CNT2 (*((volatile unsigned int*)(0x42300008UL))) +#define bM4_TMR61_CNTER_CNT3 (*((volatile unsigned int*)(0x4230000CUL))) +#define bM4_TMR61_CNTER_CNT4 (*((volatile unsigned int*)(0x42300010UL))) +#define bM4_TMR61_CNTER_CNT5 (*((volatile unsigned int*)(0x42300014UL))) +#define bM4_TMR61_CNTER_CNT6 (*((volatile unsigned int*)(0x42300018UL))) +#define bM4_TMR61_CNTER_CNT7 (*((volatile unsigned int*)(0x4230001CUL))) +#define bM4_TMR61_CNTER_CNT8 (*((volatile unsigned int*)(0x42300020UL))) +#define bM4_TMR61_CNTER_CNT9 (*((volatile unsigned int*)(0x42300024UL))) +#define bM4_TMR61_CNTER_CNT10 (*((volatile unsigned int*)(0x42300028UL))) +#define bM4_TMR61_CNTER_CNT11 (*((volatile unsigned int*)(0x4230002CUL))) +#define bM4_TMR61_CNTER_CNT12 (*((volatile unsigned int*)(0x42300030UL))) +#define bM4_TMR61_CNTER_CNT13 (*((volatile unsigned int*)(0x42300034UL))) +#define bM4_TMR61_CNTER_CNT14 (*((volatile unsigned int*)(0x42300038UL))) +#define bM4_TMR61_CNTER_CNT15 (*((volatile unsigned int*)(0x4230003CUL))) +#define bM4_TMR61_PERAR_PERA0 (*((volatile unsigned int*)(0x42300080UL))) +#define bM4_TMR61_PERAR_PERA1 (*((volatile unsigned int*)(0x42300084UL))) +#define bM4_TMR61_PERAR_PERA2 (*((volatile unsigned int*)(0x42300088UL))) +#define bM4_TMR61_PERAR_PERA3 (*((volatile unsigned int*)(0x4230008CUL))) +#define bM4_TMR61_PERAR_PERA4 (*((volatile unsigned int*)(0x42300090UL))) +#define bM4_TMR61_PERAR_PERA5 (*((volatile unsigned int*)(0x42300094UL))) +#define bM4_TMR61_PERAR_PERA6 (*((volatile unsigned int*)(0x42300098UL))) +#define bM4_TMR61_PERAR_PERA7 (*((volatile unsigned int*)(0x4230009CUL))) +#define bM4_TMR61_PERAR_PERA8 (*((volatile unsigned int*)(0x423000A0UL))) +#define bM4_TMR61_PERAR_PERA9 (*((volatile unsigned int*)(0x423000A4UL))) +#define bM4_TMR61_PERAR_PERA10 (*((volatile unsigned int*)(0x423000A8UL))) +#define bM4_TMR61_PERAR_PERA11 (*((volatile unsigned int*)(0x423000ACUL))) +#define bM4_TMR61_PERAR_PERA12 (*((volatile unsigned int*)(0x423000B0UL))) +#define bM4_TMR61_PERAR_PERA13 (*((volatile unsigned int*)(0x423000B4UL))) +#define bM4_TMR61_PERAR_PERA14 (*((volatile unsigned int*)(0x423000B8UL))) +#define bM4_TMR61_PERAR_PERA15 (*((volatile unsigned int*)(0x423000BCUL))) +#define bM4_TMR61_PERBR_PERB0 (*((volatile unsigned int*)(0x42300100UL))) +#define bM4_TMR61_PERBR_PERB1 (*((volatile unsigned int*)(0x42300104UL))) +#define bM4_TMR61_PERBR_PERB2 (*((volatile unsigned int*)(0x42300108UL))) +#define bM4_TMR61_PERBR_PERB3 (*((volatile unsigned int*)(0x4230010CUL))) +#define bM4_TMR61_PERBR_PERB4 (*((volatile unsigned int*)(0x42300110UL))) +#define bM4_TMR61_PERBR_PERB5 (*((volatile unsigned int*)(0x42300114UL))) +#define bM4_TMR61_PERBR_PERB6 (*((volatile unsigned int*)(0x42300118UL))) +#define bM4_TMR61_PERBR_PERB7 (*((volatile unsigned int*)(0x4230011CUL))) +#define bM4_TMR61_PERBR_PERB8 (*((volatile unsigned int*)(0x42300120UL))) +#define bM4_TMR61_PERBR_PERB9 (*((volatile unsigned int*)(0x42300124UL))) +#define bM4_TMR61_PERBR_PERB10 (*((volatile unsigned int*)(0x42300128UL))) +#define bM4_TMR61_PERBR_PERB11 (*((volatile unsigned int*)(0x4230012CUL))) +#define bM4_TMR61_PERBR_PERB12 (*((volatile unsigned int*)(0x42300130UL))) +#define bM4_TMR61_PERBR_PERB13 (*((volatile unsigned int*)(0x42300134UL))) +#define bM4_TMR61_PERBR_PERB14 (*((volatile unsigned int*)(0x42300138UL))) +#define bM4_TMR61_PERBR_PERB15 (*((volatile unsigned int*)(0x4230013CUL))) +#define bM4_TMR61_PERCR_PERC0 (*((volatile unsigned int*)(0x42300180UL))) +#define bM4_TMR61_PERCR_PERC1 (*((volatile unsigned int*)(0x42300184UL))) +#define bM4_TMR61_PERCR_PERC2 (*((volatile unsigned int*)(0x42300188UL))) +#define bM4_TMR61_PERCR_PERC3 (*((volatile unsigned int*)(0x4230018CUL))) +#define bM4_TMR61_PERCR_PERC4 (*((volatile unsigned int*)(0x42300190UL))) +#define bM4_TMR61_PERCR_PERC5 (*((volatile unsigned int*)(0x42300194UL))) +#define bM4_TMR61_PERCR_PERC6 (*((volatile unsigned int*)(0x42300198UL))) +#define bM4_TMR61_PERCR_PERC7 (*((volatile unsigned int*)(0x4230019CUL))) +#define bM4_TMR61_PERCR_PERC8 (*((volatile unsigned int*)(0x423001A0UL))) +#define bM4_TMR61_PERCR_PERC9 (*((volatile unsigned int*)(0x423001A4UL))) +#define bM4_TMR61_PERCR_PERC10 (*((volatile unsigned int*)(0x423001A8UL))) +#define bM4_TMR61_PERCR_PERC11 (*((volatile unsigned int*)(0x423001ACUL))) +#define bM4_TMR61_PERCR_PERC12 (*((volatile unsigned int*)(0x423001B0UL))) +#define bM4_TMR61_PERCR_PERC13 (*((volatile unsigned int*)(0x423001B4UL))) +#define bM4_TMR61_PERCR_PERC14 (*((volatile unsigned int*)(0x423001B8UL))) +#define bM4_TMR61_PERCR_PERC15 (*((volatile unsigned int*)(0x423001BCUL))) +#define bM4_TMR61_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42300200UL))) +#define bM4_TMR61_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42300204UL))) +#define bM4_TMR61_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42300208UL))) +#define bM4_TMR61_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4230020CUL))) +#define bM4_TMR61_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42300210UL))) +#define bM4_TMR61_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42300214UL))) +#define bM4_TMR61_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42300218UL))) +#define bM4_TMR61_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4230021CUL))) +#define bM4_TMR61_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42300220UL))) +#define bM4_TMR61_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42300224UL))) +#define bM4_TMR61_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42300228UL))) +#define bM4_TMR61_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4230022CUL))) +#define bM4_TMR61_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42300230UL))) +#define bM4_TMR61_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42300234UL))) +#define bM4_TMR61_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42300238UL))) +#define bM4_TMR61_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4230023CUL))) +#define bM4_TMR61_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42300280UL))) +#define bM4_TMR61_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42300284UL))) +#define bM4_TMR61_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42300288UL))) +#define bM4_TMR61_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4230028CUL))) +#define bM4_TMR61_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42300290UL))) +#define bM4_TMR61_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42300294UL))) +#define bM4_TMR61_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42300298UL))) +#define bM4_TMR61_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4230029CUL))) +#define bM4_TMR61_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423002A0UL))) +#define bM4_TMR61_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423002A4UL))) +#define bM4_TMR61_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423002A8UL))) +#define bM4_TMR61_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423002ACUL))) +#define bM4_TMR61_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423002B0UL))) +#define bM4_TMR61_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423002B4UL))) +#define bM4_TMR61_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423002B8UL))) +#define bM4_TMR61_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423002BCUL))) +#define bM4_TMR61_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42300300UL))) +#define bM4_TMR61_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42300304UL))) +#define bM4_TMR61_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42300308UL))) +#define bM4_TMR61_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4230030CUL))) +#define bM4_TMR61_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42300310UL))) +#define bM4_TMR61_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42300314UL))) +#define bM4_TMR61_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42300318UL))) +#define bM4_TMR61_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4230031CUL))) +#define bM4_TMR61_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42300320UL))) +#define bM4_TMR61_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42300324UL))) +#define bM4_TMR61_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42300328UL))) +#define bM4_TMR61_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4230032CUL))) +#define bM4_TMR61_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42300330UL))) +#define bM4_TMR61_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42300334UL))) +#define bM4_TMR61_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42300338UL))) +#define bM4_TMR61_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4230033CUL))) +#define bM4_TMR61_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42300380UL))) +#define bM4_TMR61_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42300384UL))) +#define bM4_TMR61_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42300388UL))) +#define bM4_TMR61_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4230038CUL))) +#define bM4_TMR61_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42300390UL))) +#define bM4_TMR61_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42300394UL))) +#define bM4_TMR61_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42300398UL))) +#define bM4_TMR61_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4230039CUL))) +#define bM4_TMR61_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423003A0UL))) +#define bM4_TMR61_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423003A4UL))) +#define bM4_TMR61_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423003A8UL))) +#define bM4_TMR61_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423003ACUL))) +#define bM4_TMR61_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423003B0UL))) +#define bM4_TMR61_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423003B4UL))) +#define bM4_TMR61_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423003B8UL))) +#define bM4_TMR61_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423003BCUL))) +#define bM4_TMR61_GCMER_GCME0 (*((volatile unsigned int*)(0x42300400UL))) +#define bM4_TMR61_GCMER_GCME1 (*((volatile unsigned int*)(0x42300404UL))) +#define bM4_TMR61_GCMER_GCME2 (*((volatile unsigned int*)(0x42300408UL))) +#define bM4_TMR61_GCMER_GCME3 (*((volatile unsigned int*)(0x4230040CUL))) +#define bM4_TMR61_GCMER_GCME4 (*((volatile unsigned int*)(0x42300410UL))) +#define bM4_TMR61_GCMER_GCME5 (*((volatile unsigned int*)(0x42300414UL))) +#define bM4_TMR61_GCMER_GCME6 (*((volatile unsigned int*)(0x42300418UL))) +#define bM4_TMR61_GCMER_GCME7 (*((volatile unsigned int*)(0x4230041CUL))) +#define bM4_TMR61_GCMER_GCME8 (*((volatile unsigned int*)(0x42300420UL))) +#define bM4_TMR61_GCMER_GCME9 (*((volatile unsigned int*)(0x42300424UL))) +#define bM4_TMR61_GCMER_GCME10 (*((volatile unsigned int*)(0x42300428UL))) +#define bM4_TMR61_GCMER_GCME11 (*((volatile unsigned int*)(0x4230042CUL))) +#define bM4_TMR61_GCMER_GCME12 (*((volatile unsigned int*)(0x42300430UL))) +#define bM4_TMR61_GCMER_GCME13 (*((volatile unsigned int*)(0x42300434UL))) +#define bM4_TMR61_GCMER_GCME14 (*((volatile unsigned int*)(0x42300438UL))) +#define bM4_TMR61_GCMER_GCME15 (*((volatile unsigned int*)(0x4230043CUL))) +#define bM4_TMR61_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42300480UL))) +#define bM4_TMR61_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42300484UL))) +#define bM4_TMR61_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42300488UL))) +#define bM4_TMR61_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4230048CUL))) +#define bM4_TMR61_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42300490UL))) +#define bM4_TMR61_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42300494UL))) +#define bM4_TMR61_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42300498UL))) +#define bM4_TMR61_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4230049CUL))) +#define bM4_TMR61_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423004A0UL))) +#define bM4_TMR61_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423004A4UL))) +#define bM4_TMR61_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423004A8UL))) +#define bM4_TMR61_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423004ACUL))) +#define bM4_TMR61_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423004B0UL))) +#define bM4_TMR61_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423004B4UL))) +#define bM4_TMR61_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423004B8UL))) +#define bM4_TMR61_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423004BCUL))) +#define bM4_TMR61_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42300500UL))) +#define bM4_TMR61_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42300504UL))) +#define bM4_TMR61_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42300508UL))) +#define bM4_TMR61_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4230050CUL))) +#define bM4_TMR61_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42300510UL))) +#define bM4_TMR61_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42300514UL))) +#define bM4_TMR61_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42300518UL))) +#define bM4_TMR61_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4230051CUL))) +#define bM4_TMR61_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42300520UL))) +#define bM4_TMR61_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42300524UL))) +#define bM4_TMR61_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42300528UL))) +#define bM4_TMR61_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4230052CUL))) +#define bM4_TMR61_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42300530UL))) +#define bM4_TMR61_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42300534UL))) +#define bM4_TMR61_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42300538UL))) +#define bM4_TMR61_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4230053CUL))) +#define bM4_TMR61_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42300580UL))) +#define bM4_TMR61_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42300584UL))) +#define bM4_TMR61_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42300588UL))) +#define bM4_TMR61_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4230058CUL))) +#define bM4_TMR61_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42300590UL))) +#define bM4_TMR61_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42300594UL))) +#define bM4_TMR61_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42300598UL))) +#define bM4_TMR61_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4230059CUL))) +#define bM4_TMR61_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423005A0UL))) +#define bM4_TMR61_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423005A4UL))) +#define bM4_TMR61_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423005A8UL))) +#define bM4_TMR61_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423005ACUL))) +#define bM4_TMR61_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423005B0UL))) +#define bM4_TMR61_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423005B4UL))) +#define bM4_TMR61_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423005B8UL))) +#define bM4_TMR61_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423005BCUL))) +#define bM4_TMR61_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42300600UL))) +#define bM4_TMR61_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42300604UL))) +#define bM4_TMR61_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42300608UL))) +#define bM4_TMR61_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4230060CUL))) +#define bM4_TMR61_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42300610UL))) +#define bM4_TMR61_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42300614UL))) +#define bM4_TMR61_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42300618UL))) +#define bM4_TMR61_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4230061CUL))) +#define bM4_TMR61_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42300620UL))) +#define bM4_TMR61_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42300624UL))) +#define bM4_TMR61_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42300628UL))) +#define bM4_TMR61_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4230062CUL))) +#define bM4_TMR61_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42300630UL))) +#define bM4_TMR61_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42300634UL))) +#define bM4_TMR61_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42300638UL))) +#define bM4_TMR61_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4230063CUL))) +#define bM4_TMR61_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42300680UL))) +#define bM4_TMR61_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42300684UL))) +#define bM4_TMR61_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42300688UL))) +#define bM4_TMR61_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4230068CUL))) +#define bM4_TMR61_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42300690UL))) +#define bM4_TMR61_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42300694UL))) +#define bM4_TMR61_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42300698UL))) +#define bM4_TMR61_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4230069CUL))) +#define bM4_TMR61_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423006A0UL))) +#define bM4_TMR61_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423006A4UL))) +#define bM4_TMR61_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423006A8UL))) +#define bM4_TMR61_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423006ACUL))) +#define bM4_TMR61_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423006B0UL))) +#define bM4_TMR61_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423006B4UL))) +#define bM4_TMR61_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423006B8UL))) +#define bM4_TMR61_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423006BCUL))) +#define bM4_TMR61_SCMER_SCME0 (*((volatile unsigned int*)(0x42300700UL))) +#define bM4_TMR61_SCMER_SCME1 (*((volatile unsigned int*)(0x42300704UL))) +#define bM4_TMR61_SCMER_SCME2 (*((volatile unsigned int*)(0x42300708UL))) +#define bM4_TMR61_SCMER_SCME3 (*((volatile unsigned int*)(0x4230070CUL))) +#define bM4_TMR61_SCMER_SCME4 (*((volatile unsigned int*)(0x42300710UL))) +#define bM4_TMR61_SCMER_SCME5 (*((volatile unsigned int*)(0x42300714UL))) +#define bM4_TMR61_SCMER_SCME6 (*((volatile unsigned int*)(0x42300718UL))) +#define bM4_TMR61_SCMER_SCME7 (*((volatile unsigned int*)(0x4230071CUL))) +#define bM4_TMR61_SCMER_SCME8 (*((volatile unsigned int*)(0x42300720UL))) +#define bM4_TMR61_SCMER_SCME9 (*((volatile unsigned int*)(0x42300724UL))) +#define bM4_TMR61_SCMER_SCME10 (*((volatile unsigned int*)(0x42300728UL))) +#define bM4_TMR61_SCMER_SCME11 (*((volatile unsigned int*)(0x4230072CUL))) +#define bM4_TMR61_SCMER_SCME12 (*((volatile unsigned int*)(0x42300730UL))) +#define bM4_TMR61_SCMER_SCME13 (*((volatile unsigned int*)(0x42300734UL))) +#define bM4_TMR61_SCMER_SCME14 (*((volatile unsigned int*)(0x42300738UL))) +#define bM4_TMR61_SCMER_SCME15 (*((volatile unsigned int*)(0x4230073CUL))) +#define bM4_TMR61_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42300780UL))) +#define bM4_TMR61_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42300784UL))) +#define bM4_TMR61_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42300788UL))) +#define bM4_TMR61_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4230078CUL))) +#define bM4_TMR61_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42300790UL))) +#define bM4_TMR61_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42300794UL))) +#define bM4_TMR61_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42300798UL))) +#define bM4_TMR61_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4230079CUL))) +#define bM4_TMR61_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423007A0UL))) +#define bM4_TMR61_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423007A4UL))) +#define bM4_TMR61_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423007A8UL))) +#define bM4_TMR61_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423007ACUL))) +#define bM4_TMR61_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423007B0UL))) +#define bM4_TMR61_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423007B4UL))) +#define bM4_TMR61_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423007B8UL))) +#define bM4_TMR61_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423007BCUL))) +#define bM4_TMR61_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42300800UL))) +#define bM4_TMR61_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42300804UL))) +#define bM4_TMR61_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42300808UL))) +#define bM4_TMR61_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4230080CUL))) +#define bM4_TMR61_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42300810UL))) +#define bM4_TMR61_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42300814UL))) +#define bM4_TMR61_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42300818UL))) +#define bM4_TMR61_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4230081CUL))) +#define bM4_TMR61_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42300820UL))) +#define bM4_TMR61_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42300824UL))) +#define bM4_TMR61_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42300828UL))) +#define bM4_TMR61_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4230082CUL))) +#define bM4_TMR61_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42300830UL))) +#define bM4_TMR61_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42300834UL))) +#define bM4_TMR61_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42300838UL))) +#define bM4_TMR61_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4230083CUL))) +#define bM4_TMR61_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42300880UL))) +#define bM4_TMR61_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42300884UL))) +#define bM4_TMR61_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42300888UL))) +#define bM4_TMR61_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4230088CUL))) +#define bM4_TMR61_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42300890UL))) +#define bM4_TMR61_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42300894UL))) +#define bM4_TMR61_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42300898UL))) +#define bM4_TMR61_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4230089CUL))) +#define bM4_TMR61_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423008A0UL))) +#define bM4_TMR61_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423008A4UL))) +#define bM4_TMR61_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423008A8UL))) +#define bM4_TMR61_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423008ACUL))) +#define bM4_TMR61_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423008B0UL))) +#define bM4_TMR61_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423008B4UL))) +#define bM4_TMR61_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423008B8UL))) +#define bM4_TMR61_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423008BCUL))) +#define bM4_TMR61_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42300900UL))) +#define bM4_TMR61_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42300904UL))) +#define bM4_TMR61_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42300908UL))) +#define bM4_TMR61_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4230090CUL))) +#define bM4_TMR61_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42300910UL))) +#define bM4_TMR61_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42300914UL))) +#define bM4_TMR61_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42300918UL))) +#define bM4_TMR61_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4230091CUL))) +#define bM4_TMR61_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42300920UL))) +#define bM4_TMR61_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42300924UL))) +#define bM4_TMR61_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42300928UL))) +#define bM4_TMR61_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4230092CUL))) +#define bM4_TMR61_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42300930UL))) +#define bM4_TMR61_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42300934UL))) +#define bM4_TMR61_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42300938UL))) +#define bM4_TMR61_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4230093CUL))) +#define bM4_TMR61_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42300980UL))) +#define bM4_TMR61_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42300984UL))) +#define bM4_TMR61_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42300988UL))) +#define bM4_TMR61_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4230098CUL))) +#define bM4_TMR61_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42300990UL))) +#define bM4_TMR61_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42300994UL))) +#define bM4_TMR61_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42300998UL))) +#define bM4_TMR61_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4230099CUL))) +#define bM4_TMR61_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423009A0UL))) +#define bM4_TMR61_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423009A4UL))) +#define bM4_TMR61_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423009A8UL))) +#define bM4_TMR61_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423009ACUL))) +#define bM4_TMR61_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423009B0UL))) +#define bM4_TMR61_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423009B4UL))) +#define bM4_TMR61_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423009B8UL))) +#define bM4_TMR61_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423009BCUL))) +#define bM4_TMR61_GCONR_START (*((volatile unsigned int*)(0x42300A00UL))) +#define bM4_TMR61_GCONR_MODE0 (*((volatile unsigned int*)(0x42300A04UL))) +#define bM4_TMR61_GCONR_MODE1 (*((volatile unsigned int*)(0x42300A08UL))) +#define bM4_TMR61_GCONR_MODE2 (*((volatile unsigned int*)(0x42300A0CUL))) +#define bM4_TMR61_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42300A10UL))) +#define bM4_TMR61_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42300A14UL))) +#define bM4_TMR61_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42300A18UL))) +#define bM4_TMR61_GCONR_DIR (*((volatile unsigned int*)(0x42300A20UL))) +#define bM4_TMR61_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42300A40UL))) +#define bM4_TMR61_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42300A44UL))) +#define bM4_TMR61_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42300A48UL))) +#define bM4_TMR61_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42300A4CUL))) +#define bM4_TMR61_ICONR_INTENA (*((volatile unsigned int*)(0x42300A80UL))) +#define bM4_TMR61_ICONR_INTENB (*((volatile unsigned int*)(0x42300A84UL))) +#define bM4_TMR61_ICONR_INTENC (*((volatile unsigned int*)(0x42300A88UL))) +#define bM4_TMR61_ICONR_INTEND (*((volatile unsigned int*)(0x42300A8CUL))) +#define bM4_TMR61_ICONR_INTENE (*((volatile unsigned int*)(0x42300A90UL))) +#define bM4_TMR61_ICONR_INTENF (*((volatile unsigned int*)(0x42300A94UL))) +#define bM4_TMR61_ICONR_INTENOVF (*((volatile unsigned int*)(0x42300A98UL))) +#define bM4_TMR61_ICONR_INTENUDF (*((volatile unsigned int*)(0x42300A9CUL))) +#define bM4_TMR61_ICONR_INTENDTE (*((volatile unsigned int*)(0x42300AA0UL))) +#define bM4_TMR61_ICONR_INTENSAU (*((volatile unsigned int*)(0x42300AC0UL))) +#define bM4_TMR61_ICONR_INTENSAD (*((volatile unsigned int*)(0x42300AC4UL))) +#define bM4_TMR61_ICONR_INTENSBU (*((volatile unsigned int*)(0x42300AC8UL))) +#define bM4_TMR61_ICONR_INTENSBD (*((volatile unsigned int*)(0x42300ACCUL))) +#define bM4_TMR61_PCONR_CAPMDA (*((volatile unsigned int*)(0x42300B00UL))) +#define bM4_TMR61_PCONR_STACA (*((volatile unsigned int*)(0x42300B04UL))) +#define bM4_TMR61_PCONR_STPCA (*((volatile unsigned int*)(0x42300B08UL))) +#define bM4_TMR61_PCONR_STASTPSA (*((volatile unsigned int*)(0x42300B0CUL))) +#define bM4_TMR61_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42300B10UL))) +#define bM4_TMR61_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42300B14UL))) +#define bM4_TMR61_PCONR_PERCA0 (*((volatile unsigned int*)(0x42300B18UL))) +#define bM4_TMR61_PCONR_PERCA1 (*((volatile unsigned int*)(0x42300B1CUL))) +#define bM4_TMR61_PCONR_OUTENA (*((volatile unsigned int*)(0x42300B20UL))) +#define bM4_TMR61_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42300B2CUL))) +#define bM4_TMR61_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42300B30UL))) +#define bM4_TMR61_PCONR_CAPMDB (*((volatile unsigned int*)(0x42300B40UL))) +#define bM4_TMR61_PCONR_STACB (*((volatile unsigned int*)(0x42300B44UL))) +#define bM4_TMR61_PCONR_STPCB (*((volatile unsigned int*)(0x42300B48UL))) +#define bM4_TMR61_PCONR_STASTPSB (*((volatile unsigned int*)(0x42300B4CUL))) +#define bM4_TMR61_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42300B50UL))) +#define bM4_TMR61_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42300B54UL))) +#define bM4_TMR61_PCONR_PERCB0 (*((volatile unsigned int*)(0x42300B58UL))) +#define bM4_TMR61_PCONR_PERCB1 (*((volatile unsigned int*)(0x42300B5CUL))) +#define bM4_TMR61_PCONR_OUTENB (*((volatile unsigned int*)(0x42300B60UL))) +#define bM4_TMR61_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42300B6CUL))) +#define bM4_TMR61_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42300B70UL))) +#define bM4_TMR61_BCONR_BENA (*((volatile unsigned int*)(0x42300B80UL))) +#define bM4_TMR61_BCONR_BSEA (*((volatile unsigned int*)(0x42300B84UL))) +#define bM4_TMR61_BCONR_BENB (*((volatile unsigned int*)(0x42300B88UL))) +#define bM4_TMR61_BCONR_BSEB (*((volatile unsigned int*)(0x42300B8CUL))) +#define bM4_TMR61_BCONR_BENP (*((volatile unsigned int*)(0x42300BA0UL))) +#define bM4_TMR61_BCONR_BSEP (*((volatile unsigned int*)(0x42300BA4UL))) +#define bM4_TMR61_BCONR_BENSPA (*((volatile unsigned int*)(0x42300BC0UL))) +#define bM4_TMR61_BCONR_BSESPA (*((volatile unsigned int*)(0x42300BC4UL))) +#define bM4_TMR61_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42300BD0UL))) +#define bM4_TMR61_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42300BD4UL))) +#define bM4_TMR61_BCONR_BENSPB (*((volatile unsigned int*)(0x42300BE0UL))) +#define bM4_TMR61_BCONR_BSESPB (*((volatile unsigned int*)(0x42300BE4UL))) +#define bM4_TMR61_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42300BF0UL))) +#define bM4_TMR61_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42300BF4UL))) +#define bM4_TMR61_DCONR_DTCEN (*((volatile unsigned int*)(0x42300C00UL))) +#define bM4_TMR61_DCONR_DTBENU (*((volatile unsigned int*)(0x42300C10UL))) +#define bM4_TMR61_DCONR_DTBEND (*((volatile unsigned int*)(0x42300C14UL))) +#define bM4_TMR61_DCONR_SEPA (*((volatile unsigned int*)(0x42300C20UL))) +#define bM4_TMR61_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42300D00UL))) +#define bM4_TMR61_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42300D04UL))) +#define bM4_TMR61_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42300D08UL))) +#define bM4_TMR61_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42300D10UL))) +#define bM4_TMR61_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42300D14UL))) +#define bM4_TMR61_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42300D18UL))) +#define bM4_TMR61_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42300D40UL))) +#define bM4_TMR61_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42300D44UL))) +#define bM4_TMR61_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42300D48UL))) +#define bM4_TMR61_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42300D50UL))) +#define bM4_TMR61_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42300D54UL))) +#define bM4_TMR61_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42300D58UL))) +#define bM4_TMR61_VPERR_SPPERIA (*((volatile unsigned int*)(0x42300DA0UL))) +#define bM4_TMR61_VPERR_SPPERIB (*((volatile unsigned int*)(0x42300DA4UL))) +#define bM4_TMR61_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42300DC0UL))) +#define bM4_TMR61_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42300DC4UL))) +#define bM4_TMR61_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42300DC8UL))) +#define bM4_TMR61_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42300DCCUL))) +#define bM4_TMR61_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42300DD0UL))) +#define bM4_TMR61_STFLR_CMAF (*((volatile unsigned int*)(0x42300E00UL))) +#define bM4_TMR61_STFLR_CMBF (*((volatile unsigned int*)(0x42300E04UL))) +#define bM4_TMR61_STFLR_CMCF (*((volatile unsigned int*)(0x42300E08UL))) +#define bM4_TMR61_STFLR_CMDF (*((volatile unsigned int*)(0x42300E0CUL))) +#define bM4_TMR61_STFLR_CMEF (*((volatile unsigned int*)(0x42300E10UL))) +#define bM4_TMR61_STFLR_CMFF (*((volatile unsigned int*)(0x42300E14UL))) +#define bM4_TMR61_STFLR_OVFF (*((volatile unsigned int*)(0x42300E18UL))) +#define bM4_TMR61_STFLR_UDFF (*((volatile unsigned int*)(0x42300E1CUL))) +#define bM4_TMR61_STFLR_DTEF (*((volatile unsigned int*)(0x42300E20UL))) +#define bM4_TMR61_STFLR_CMSAUF (*((volatile unsigned int*)(0x42300E24UL))) +#define bM4_TMR61_STFLR_CMSADF (*((volatile unsigned int*)(0x42300E28UL))) +#define bM4_TMR61_STFLR_CMSBUF (*((volatile unsigned int*)(0x42300E2CUL))) +#define bM4_TMR61_STFLR_CMSBDF (*((volatile unsigned int*)(0x42300E30UL))) +#define bM4_TMR61_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42300E54UL))) +#define bM4_TMR61_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42300E58UL))) +#define bM4_TMR61_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42300E5CUL))) +#define bM4_TMR61_STFLR_DIRF (*((volatile unsigned int*)(0x42300E7CUL))) +#define bM4_TMR61_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42300E80UL))) +#define bM4_TMR61_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42300E84UL))) +#define bM4_TMR61_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42300E90UL))) +#define bM4_TMR61_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42300E94UL))) +#define bM4_TMR61_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42300E98UL))) +#define bM4_TMR61_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42300E9CUL))) +#define bM4_TMR61_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42300EA0UL))) +#define bM4_TMR61_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42300EA4UL))) +#define bM4_TMR61_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42300EA8UL))) +#define bM4_TMR61_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42300EACUL))) +#define bM4_TMR61_HSTAR_STARTS (*((volatile unsigned int*)(0x42300EFCUL))) +#define bM4_TMR61_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42300F00UL))) +#define bM4_TMR61_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42300F04UL))) +#define bM4_TMR61_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42300F10UL))) +#define bM4_TMR61_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42300F14UL))) +#define bM4_TMR61_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42300F18UL))) +#define bM4_TMR61_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42300F1CUL))) +#define bM4_TMR61_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42300F20UL))) +#define bM4_TMR61_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42300F24UL))) +#define bM4_TMR61_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42300F28UL))) +#define bM4_TMR61_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42300F2CUL))) +#define bM4_TMR61_HSTPR_STOPS (*((volatile unsigned int*)(0x42300F7CUL))) +#define bM4_TMR61_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42300F80UL))) +#define bM4_TMR61_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42300F84UL))) +#define bM4_TMR61_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42300F90UL))) +#define bM4_TMR61_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42300F94UL))) +#define bM4_TMR61_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42300F98UL))) +#define bM4_TMR61_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42300F9CUL))) +#define bM4_TMR61_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42300FA0UL))) +#define bM4_TMR61_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42300FA4UL))) +#define bM4_TMR61_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42300FA8UL))) +#define bM4_TMR61_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42300FACUL))) +#define bM4_TMR61_HCLRR_CLEARS (*((volatile unsigned int*)(0x42300FFCUL))) +#define bM4_TMR61_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42301000UL))) +#define bM4_TMR61_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42301004UL))) +#define bM4_TMR61_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42301010UL))) +#define bM4_TMR61_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42301014UL))) +#define bM4_TMR61_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42301018UL))) +#define bM4_TMR61_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4230101CUL))) +#define bM4_TMR61_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42301020UL))) +#define bM4_TMR61_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42301024UL))) +#define bM4_TMR61_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42301028UL))) +#define bM4_TMR61_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4230102CUL))) +#define bM4_TMR61_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42301080UL))) +#define bM4_TMR61_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42301084UL))) +#define bM4_TMR61_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42301090UL))) +#define bM4_TMR61_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42301094UL))) +#define bM4_TMR61_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42301098UL))) +#define bM4_TMR61_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4230109CUL))) +#define bM4_TMR61_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423010A0UL))) +#define bM4_TMR61_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423010A4UL))) +#define bM4_TMR61_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423010A8UL))) +#define bM4_TMR61_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423010ACUL))) +#define bM4_TMR61_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42301100UL))) +#define bM4_TMR61_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42301104UL))) +#define bM4_TMR61_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42301108UL))) +#define bM4_TMR61_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4230110CUL))) +#define bM4_TMR61_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42301110UL))) +#define bM4_TMR61_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42301114UL))) +#define bM4_TMR61_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42301118UL))) +#define bM4_TMR61_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4230111CUL))) +#define bM4_TMR61_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42301120UL))) +#define bM4_TMR61_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42301124UL))) +#define bM4_TMR61_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42301128UL))) +#define bM4_TMR61_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4230112CUL))) +#define bM4_TMR61_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42301140UL))) +#define bM4_TMR61_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42301144UL))) +#define bM4_TMR61_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42301180UL))) +#define bM4_TMR61_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42301184UL))) +#define bM4_TMR61_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42301188UL))) +#define bM4_TMR61_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4230118CUL))) +#define bM4_TMR61_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42301190UL))) +#define bM4_TMR61_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42301194UL))) +#define bM4_TMR61_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42301198UL))) +#define bM4_TMR61_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4230119CUL))) +#define bM4_TMR61_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423011A0UL))) +#define bM4_TMR61_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423011A4UL))) +#define bM4_TMR61_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423011A8UL))) +#define bM4_TMR61_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423011ACUL))) +#define bM4_TMR61_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423011C0UL))) +#define bM4_TMR61_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423011C4UL))) +#define bM4_TMR62_CNTER_CNT0 (*((volatile unsigned int*)(0x42308000UL))) +#define bM4_TMR62_CNTER_CNT1 (*((volatile unsigned int*)(0x42308004UL))) +#define bM4_TMR62_CNTER_CNT2 (*((volatile unsigned int*)(0x42308008UL))) +#define bM4_TMR62_CNTER_CNT3 (*((volatile unsigned int*)(0x4230800CUL))) +#define bM4_TMR62_CNTER_CNT4 (*((volatile unsigned int*)(0x42308010UL))) +#define bM4_TMR62_CNTER_CNT5 (*((volatile unsigned int*)(0x42308014UL))) +#define bM4_TMR62_CNTER_CNT6 (*((volatile unsigned int*)(0x42308018UL))) +#define bM4_TMR62_CNTER_CNT7 (*((volatile unsigned int*)(0x4230801CUL))) +#define bM4_TMR62_CNTER_CNT8 (*((volatile unsigned int*)(0x42308020UL))) +#define bM4_TMR62_CNTER_CNT9 (*((volatile unsigned int*)(0x42308024UL))) +#define bM4_TMR62_CNTER_CNT10 (*((volatile unsigned int*)(0x42308028UL))) +#define bM4_TMR62_CNTER_CNT11 (*((volatile unsigned int*)(0x4230802CUL))) +#define bM4_TMR62_CNTER_CNT12 (*((volatile unsigned int*)(0x42308030UL))) +#define bM4_TMR62_CNTER_CNT13 (*((volatile unsigned int*)(0x42308034UL))) +#define bM4_TMR62_CNTER_CNT14 (*((volatile unsigned int*)(0x42308038UL))) +#define bM4_TMR62_CNTER_CNT15 (*((volatile unsigned int*)(0x4230803CUL))) +#define bM4_TMR62_PERAR_PERA0 (*((volatile unsigned int*)(0x42308080UL))) +#define bM4_TMR62_PERAR_PERA1 (*((volatile unsigned int*)(0x42308084UL))) +#define bM4_TMR62_PERAR_PERA2 (*((volatile unsigned int*)(0x42308088UL))) +#define bM4_TMR62_PERAR_PERA3 (*((volatile unsigned int*)(0x4230808CUL))) +#define bM4_TMR62_PERAR_PERA4 (*((volatile unsigned int*)(0x42308090UL))) +#define bM4_TMR62_PERAR_PERA5 (*((volatile unsigned int*)(0x42308094UL))) +#define bM4_TMR62_PERAR_PERA6 (*((volatile unsigned int*)(0x42308098UL))) +#define bM4_TMR62_PERAR_PERA7 (*((volatile unsigned int*)(0x4230809CUL))) +#define bM4_TMR62_PERAR_PERA8 (*((volatile unsigned int*)(0x423080A0UL))) +#define bM4_TMR62_PERAR_PERA9 (*((volatile unsigned int*)(0x423080A4UL))) +#define bM4_TMR62_PERAR_PERA10 (*((volatile unsigned int*)(0x423080A8UL))) +#define bM4_TMR62_PERAR_PERA11 (*((volatile unsigned int*)(0x423080ACUL))) +#define bM4_TMR62_PERAR_PERA12 (*((volatile unsigned int*)(0x423080B0UL))) +#define bM4_TMR62_PERAR_PERA13 (*((volatile unsigned int*)(0x423080B4UL))) +#define bM4_TMR62_PERAR_PERA14 (*((volatile unsigned int*)(0x423080B8UL))) +#define bM4_TMR62_PERAR_PERA15 (*((volatile unsigned int*)(0x423080BCUL))) +#define bM4_TMR62_PERBR_PERB0 (*((volatile unsigned int*)(0x42308100UL))) +#define bM4_TMR62_PERBR_PERB1 (*((volatile unsigned int*)(0x42308104UL))) +#define bM4_TMR62_PERBR_PERB2 (*((volatile unsigned int*)(0x42308108UL))) +#define bM4_TMR62_PERBR_PERB3 (*((volatile unsigned int*)(0x4230810CUL))) +#define bM4_TMR62_PERBR_PERB4 (*((volatile unsigned int*)(0x42308110UL))) +#define bM4_TMR62_PERBR_PERB5 (*((volatile unsigned int*)(0x42308114UL))) +#define bM4_TMR62_PERBR_PERB6 (*((volatile unsigned int*)(0x42308118UL))) +#define bM4_TMR62_PERBR_PERB7 (*((volatile unsigned int*)(0x4230811CUL))) +#define bM4_TMR62_PERBR_PERB8 (*((volatile unsigned int*)(0x42308120UL))) +#define bM4_TMR62_PERBR_PERB9 (*((volatile unsigned int*)(0x42308124UL))) +#define bM4_TMR62_PERBR_PERB10 (*((volatile unsigned int*)(0x42308128UL))) +#define bM4_TMR62_PERBR_PERB11 (*((volatile unsigned int*)(0x4230812CUL))) +#define bM4_TMR62_PERBR_PERB12 (*((volatile unsigned int*)(0x42308130UL))) +#define bM4_TMR62_PERBR_PERB13 (*((volatile unsigned int*)(0x42308134UL))) +#define bM4_TMR62_PERBR_PERB14 (*((volatile unsigned int*)(0x42308138UL))) +#define bM4_TMR62_PERBR_PERB15 (*((volatile unsigned int*)(0x4230813CUL))) +#define bM4_TMR62_PERCR_PERC0 (*((volatile unsigned int*)(0x42308180UL))) +#define bM4_TMR62_PERCR_PERC1 (*((volatile unsigned int*)(0x42308184UL))) +#define bM4_TMR62_PERCR_PERC2 (*((volatile unsigned int*)(0x42308188UL))) +#define bM4_TMR62_PERCR_PERC3 (*((volatile unsigned int*)(0x4230818CUL))) +#define bM4_TMR62_PERCR_PERC4 (*((volatile unsigned int*)(0x42308190UL))) +#define bM4_TMR62_PERCR_PERC5 (*((volatile unsigned int*)(0x42308194UL))) +#define bM4_TMR62_PERCR_PERC6 (*((volatile unsigned int*)(0x42308198UL))) +#define bM4_TMR62_PERCR_PERC7 (*((volatile unsigned int*)(0x4230819CUL))) +#define bM4_TMR62_PERCR_PERC8 (*((volatile unsigned int*)(0x423081A0UL))) +#define bM4_TMR62_PERCR_PERC9 (*((volatile unsigned int*)(0x423081A4UL))) +#define bM4_TMR62_PERCR_PERC10 (*((volatile unsigned int*)(0x423081A8UL))) +#define bM4_TMR62_PERCR_PERC11 (*((volatile unsigned int*)(0x423081ACUL))) +#define bM4_TMR62_PERCR_PERC12 (*((volatile unsigned int*)(0x423081B0UL))) +#define bM4_TMR62_PERCR_PERC13 (*((volatile unsigned int*)(0x423081B4UL))) +#define bM4_TMR62_PERCR_PERC14 (*((volatile unsigned int*)(0x423081B8UL))) +#define bM4_TMR62_PERCR_PERC15 (*((volatile unsigned int*)(0x423081BCUL))) +#define bM4_TMR62_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42308200UL))) +#define bM4_TMR62_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42308204UL))) +#define bM4_TMR62_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42308208UL))) +#define bM4_TMR62_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4230820CUL))) +#define bM4_TMR62_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42308210UL))) +#define bM4_TMR62_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42308214UL))) +#define bM4_TMR62_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42308218UL))) +#define bM4_TMR62_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4230821CUL))) +#define bM4_TMR62_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42308220UL))) +#define bM4_TMR62_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42308224UL))) +#define bM4_TMR62_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42308228UL))) +#define bM4_TMR62_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4230822CUL))) +#define bM4_TMR62_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42308230UL))) +#define bM4_TMR62_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42308234UL))) +#define bM4_TMR62_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42308238UL))) +#define bM4_TMR62_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4230823CUL))) +#define bM4_TMR62_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42308280UL))) +#define bM4_TMR62_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42308284UL))) +#define bM4_TMR62_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42308288UL))) +#define bM4_TMR62_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4230828CUL))) +#define bM4_TMR62_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42308290UL))) +#define bM4_TMR62_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42308294UL))) +#define bM4_TMR62_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42308298UL))) +#define bM4_TMR62_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4230829CUL))) +#define bM4_TMR62_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423082A0UL))) +#define bM4_TMR62_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423082A4UL))) +#define bM4_TMR62_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423082A8UL))) +#define bM4_TMR62_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423082ACUL))) +#define bM4_TMR62_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423082B0UL))) +#define bM4_TMR62_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423082B4UL))) +#define bM4_TMR62_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423082B8UL))) +#define bM4_TMR62_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423082BCUL))) +#define bM4_TMR62_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42308300UL))) +#define bM4_TMR62_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42308304UL))) +#define bM4_TMR62_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42308308UL))) +#define bM4_TMR62_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4230830CUL))) +#define bM4_TMR62_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42308310UL))) +#define bM4_TMR62_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42308314UL))) +#define bM4_TMR62_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42308318UL))) +#define bM4_TMR62_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4230831CUL))) +#define bM4_TMR62_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42308320UL))) +#define bM4_TMR62_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42308324UL))) +#define bM4_TMR62_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42308328UL))) +#define bM4_TMR62_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4230832CUL))) +#define bM4_TMR62_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42308330UL))) +#define bM4_TMR62_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42308334UL))) +#define bM4_TMR62_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42308338UL))) +#define bM4_TMR62_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4230833CUL))) +#define bM4_TMR62_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42308380UL))) +#define bM4_TMR62_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42308384UL))) +#define bM4_TMR62_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42308388UL))) +#define bM4_TMR62_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4230838CUL))) +#define bM4_TMR62_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42308390UL))) +#define bM4_TMR62_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42308394UL))) +#define bM4_TMR62_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42308398UL))) +#define bM4_TMR62_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4230839CUL))) +#define bM4_TMR62_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423083A0UL))) +#define bM4_TMR62_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423083A4UL))) +#define bM4_TMR62_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423083A8UL))) +#define bM4_TMR62_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423083ACUL))) +#define bM4_TMR62_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423083B0UL))) +#define bM4_TMR62_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423083B4UL))) +#define bM4_TMR62_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423083B8UL))) +#define bM4_TMR62_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423083BCUL))) +#define bM4_TMR62_GCMER_GCME0 (*((volatile unsigned int*)(0x42308400UL))) +#define bM4_TMR62_GCMER_GCME1 (*((volatile unsigned int*)(0x42308404UL))) +#define bM4_TMR62_GCMER_GCME2 (*((volatile unsigned int*)(0x42308408UL))) +#define bM4_TMR62_GCMER_GCME3 (*((volatile unsigned int*)(0x4230840CUL))) +#define bM4_TMR62_GCMER_GCME4 (*((volatile unsigned int*)(0x42308410UL))) +#define bM4_TMR62_GCMER_GCME5 (*((volatile unsigned int*)(0x42308414UL))) +#define bM4_TMR62_GCMER_GCME6 (*((volatile unsigned int*)(0x42308418UL))) +#define bM4_TMR62_GCMER_GCME7 (*((volatile unsigned int*)(0x4230841CUL))) +#define bM4_TMR62_GCMER_GCME8 (*((volatile unsigned int*)(0x42308420UL))) +#define bM4_TMR62_GCMER_GCME9 (*((volatile unsigned int*)(0x42308424UL))) +#define bM4_TMR62_GCMER_GCME10 (*((volatile unsigned int*)(0x42308428UL))) +#define bM4_TMR62_GCMER_GCME11 (*((volatile unsigned int*)(0x4230842CUL))) +#define bM4_TMR62_GCMER_GCME12 (*((volatile unsigned int*)(0x42308430UL))) +#define bM4_TMR62_GCMER_GCME13 (*((volatile unsigned int*)(0x42308434UL))) +#define bM4_TMR62_GCMER_GCME14 (*((volatile unsigned int*)(0x42308438UL))) +#define bM4_TMR62_GCMER_GCME15 (*((volatile unsigned int*)(0x4230843CUL))) +#define bM4_TMR62_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42308480UL))) +#define bM4_TMR62_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42308484UL))) +#define bM4_TMR62_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42308488UL))) +#define bM4_TMR62_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4230848CUL))) +#define bM4_TMR62_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42308490UL))) +#define bM4_TMR62_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42308494UL))) +#define bM4_TMR62_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42308498UL))) +#define bM4_TMR62_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4230849CUL))) +#define bM4_TMR62_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423084A0UL))) +#define bM4_TMR62_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423084A4UL))) +#define bM4_TMR62_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423084A8UL))) +#define bM4_TMR62_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423084ACUL))) +#define bM4_TMR62_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423084B0UL))) +#define bM4_TMR62_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423084B4UL))) +#define bM4_TMR62_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423084B8UL))) +#define bM4_TMR62_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423084BCUL))) +#define bM4_TMR62_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42308500UL))) +#define bM4_TMR62_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42308504UL))) +#define bM4_TMR62_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42308508UL))) +#define bM4_TMR62_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4230850CUL))) +#define bM4_TMR62_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42308510UL))) +#define bM4_TMR62_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42308514UL))) +#define bM4_TMR62_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42308518UL))) +#define bM4_TMR62_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4230851CUL))) +#define bM4_TMR62_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42308520UL))) +#define bM4_TMR62_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42308524UL))) +#define bM4_TMR62_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42308528UL))) +#define bM4_TMR62_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4230852CUL))) +#define bM4_TMR62_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42308530UL))) +#define bM4_TMR62_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42308534UL))) +#define bM4_TMR62_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42308538UL))) +#define bM4_TMR62_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4230853CUL))) +#define bM4_TMR62_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42308580UL))) +#define bM4_TMR62_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42308584UL))) +#define bM4_TMR62_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42308588UL))) +#define bM4_TMR62_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4230858CUL))) +#define bM4_TMR62_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42308590UL))) +#define bM4_TMR62_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42308594UL))) +#define bM4_TMR62_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42308598UL))) +#define bM4_TMR62_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4230859CUL))) +#define bM4_TMR62_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423085A0UL))) +#define bM4_TMR62_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423085A4UL))) +#define bM4_TMR62_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423085A8UL))) +#define bM4_TMR62_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423085ACUL))) +#define bM4_TMR62_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423085B0UL))) +#define bM4_TMR62_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423085B4UL))) +#define bM4_TMR62_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423085B8UL))) +#define bM4_TMR62_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423085BCUL))) +#define bM4_TMR62_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42308600UL))) +#define bM4_TMR62_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42308604UL))) +#define bM4_TMR62_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42308608UL))) +#define bM4_TMR62_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4230860CUL))) +#define bM4_TMR62_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42308610UL))) +#define bM4_TMR62_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42308614UL))) +#define bM4_TMR62_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42308618UL))) +#define bM4_TMR62_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4230861CUL))) +#define bM4_TMR62_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42308620UL))) +#define bM4_TMR62_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42308624UL))) +#define bM4_TMR62_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42308628UL))) +#define bM4_TMR62_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4230862CUL))) +#define bM4_TMR62_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42308630UL))) +#define bM4_TMR62_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42308634UL))) +#define bM4_TMR62_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42308638UL))) +#define bM4_TMR62_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4230863CUL))) +#define bM4_TMR62_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42308680UL))) +#define bM4_TMR62_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42308684UL))) +#define bM4_TMR62_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42308688UL))) +#define bM4_TMR62_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4230868CUL))) +#define bM4_TMR62_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42308690UL))) +#define bM4_TMR62_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42308694UL))) +#define bM4_TMR62_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42308698UL))) +#define bM4_TMR62_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4230869CUL))) +#define bM4_TMR62_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423086A0UL))) +#define bM4_TMR62_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423086A4UL))) +#define bM4_TMR62_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423086A8UL))) +#define bM4_TMR62_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423086ACUL))) +#define bM4_TMR62_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423086B0UL))) +#define bM4_TMR62_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423086B4UL))) +#define bM4_TMR62_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423086B8UL))) +#define bM4_TMR62_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423086BCUL))) +#define bM4_TMR62_SCMER_SCME0 (*((volatile unsigned int*)(0x42308700UL))) +#define bM4_TMR62_SCMER_SCME1 (*((volatile unsigned int*)(0x42308704UL))) +#define bM4_TMR62_SCMER_SCME2 (*((volatile unsigned int*)(0x42308708UL))) +#define bM4_TMR62_SCMER_SCME3 (*((volatile unsigned int*)(0x4230870CUL))) +#define bM4_TMR62_SCMER_SCME4 (*((volatile unsigned int*)(0x42308710UL))) +#define bM4_TMR62_SCMER_SCME5 (*((volatile unsigned int*)(0x42308714UL))) +#define bM4_TMR62_SCMER_SCME6 (*((volatile unsigned int*)(0x42308718UL))) +#define bM4_TMR62_SCMER_SCME7 (*((volatile unsigned int*)(0x4230871CUL))) +#define bM4_TMR62_SCMER_SCME8 (*((volatile unsigned int*)(0x42308720UL))) +#define bM4_TMR62_SCMER_SCME9 (*((volatile unsigned int*)(0x42308724UL))) +#define bM4_TMR62_SCMER_SCME10 (*((volatile unsigned int*)(0x42308728UL))) +#define bM4_TMR62_SCMER_SCME11 (*((volatile unsigned int*)(0x4230872CUL))) +#define bM4_TMR62_SCMER_SCME12 (*((volatile unsigned int*)(0x42308730UL))) +#define bM4_TMR62_SCMER_SCME13 (*((volatile unsigned int*)(0x42308734UL))) +#define bM4_TMR62_SCMER_SCME14 (*((volatile unsigned int*)(0x42308738UL))) +#define bM4_TMR62_SCMER_SCME15 (*((volatile unsigned int*)(0x4230873CUL))) +#define bM4_TMR62_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42308780UL))) +#define bM4_TMR62_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42308784UL))) +#define bM4_TMR62_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42308788UL))) +#define bM4_TMR62_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4230878CUL))) +#define bM4_TMR62_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42308790UL))) +#define bM4_TMR62_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42308794UL))) +#define bM4_TMR62_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42308798UL))) +#define bM4_TMR62_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4230879CUL))) +#define bM4_TMR62_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423087A0UL))) +#define bM4_TMR62_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423087A4UL))) +#define bM4_TMR62_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423087A8UL))) +#define bM4_TMR62_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423087ACUL))) +#define bM4_TMR62_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423087B0UL))) +#define bM4_TMR62_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423087B4UL))) +#define bM4_TMR62_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423087B8UL))) +#define bM4_TMR62_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423087BCUL))) +#define bM4_TMR62_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42308800UL))) +#define bM4_TMR62_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42308804UL))) +#define bM4_TMR62_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42308808UL))) +#define bM4_TMR62_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4230880CUL))) +#define bM4_TMR62_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42308810UL))) +#define bM4_TMR62_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42308814UL))) +#define bM4_TMR62_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42308818UL))) +#define bM4_TMR62_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4230881CUL))) +#define bM4_TMR62_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42308820UL))) +#define bM4_TMR62_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42308824UL))) +#define bM4_TMR62_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42308828UL))) +#define bM4_TMR62_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4230882CUL))) +#define bM4_TMR62_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42308830UL))) +#define bM4_TMR62_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42308834UL))) +#define bM4_TMR62_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42308838UL))) +#define bM4_TMR62_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4230883CUL))) +#define bM4_TMR62_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42308880UL))) +#define bM4_TMR62_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42308884UL))) +#define bM4_TMR62_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42308888UL))) +#define bM4_TMR62_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4230888CUL))) +#define bM4_TMR62_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42308890UL))) +#define bM4_TMR62_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42308894UL))) +#define bM4_TMR62_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42308898UL))) +#define bM4_TMR62_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4230889CUL))) +#define bM4_TMR62_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423088A0UL))) +#define bM4_TMR62_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423088A4UL))) +#define bM4_TMR62_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423088A8UL))) +#define bM4_TMR62_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423088ACUL))) +#define bM4_TMR62_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423088B0UL))) +#define bM4_TMR62_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423088B4UL))) +#define bM4_TMR62_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423088B8UL))) +#define bM4_TMR62_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423088BCUL))) +#define bM4_TMR62_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42308900UL))) +#define bM4_TMR62_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42308904UL))) +#define bM4_TMR62_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42308908UL))) +#define bM4_TMR62_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4230890CUL))) +#define bM4_TMR62_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42308910UL))) +#define bM4_TMR62_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42308914UL))) +#define bM4_TMR62_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42308918UL))) +#define bM4_TMR62_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4230891CUL))) +#define bM4_TMR62_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42308920UL))) +#define bM4_TMR62_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42308924UL))) +#define bM4_TMR62_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42308928UL))) +#define bM4_TMR62_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4230892CUL))) +#define bM4_TMR62_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42308930UL))) +#define bM4_TMR62_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42308934UL))) +#define bM4_TMR62_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42308938UL))) +#define bM4_TMR62_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4230893CUL))) +#define bM4_TMR62_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42308980UL))) +#define bM4_TMR62_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42308984UL))) +#define bM4_TMR62_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42308988UL))) +#define bM4_TMR62_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4230898CUL))) +#define bM4_TMR62_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42308990UL))) +#define bM4_TMR62_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42308994UL))) +#define bM4_TMR62_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42308998UL))) +#define bM4_TMR62_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4230899CUL))) +#define bM4_TMR62_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423089A0UL))) +#define bM4_TMR62_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423089A4UL))) +#define bM4_TMR62_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423089A8UL))) +#define bM4_TMR62_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423089ACUL))) +#define bM4_TMR62_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423089B0UL))) +#define bM4_TMR62_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423089B4UL))) +#define bM4_TMR62_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423089B8UL))) +#define bM4_TMR62_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423089BCUL))) +#define bM4_TMR62_GCONR_START (*((volatile unsigned int*)(0x42308A00UL))) +#define bM4_TMR62_GCONR_MODE0 (*((volatile unsigned int*)(0x42308A04UL))) +#define bM4_TMR62_GCONR_MODE1 (*((volatile unsigned int*)(0x42308A08UL))) +#define bM4_TMR62_GCONR_MODE2 (*((volatile unsigned int*)(0x42308A0CUL))) +#define bM4_TMR62_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42308A10UL))) +#define bM4_TMR62_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42308A14UL))) +#define bM4_TMR62_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42308A18UL))) +#define bM4_TMR62_GCONR_DIR (*((volatile unsigned int*)(0x42308A20UL))) +#define bM4_TMR62_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42308A40UL))) +#define bM4_TMR62_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42308A44UL))) +#define bM4_TMR62_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42308A48UL))) +#define bM4_TMR62_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42308A4CUL))) +#define bM4_TMR62_ICONR_INTENA (*((volatile unsigned int*)(0x42308A80UL))) +#define bM4_TMR62_ICONR_INTENB (*((volatile unsigned int*)(0x42308A84UL))) +#define bM4_TMR62_ICONR_INTENC (*((volatile unsigned int*)(0x42308A88UL))) +#define bM4_TMR62_ICONR_INTEND (*((volatile unsigned int*)(0x42308A8CUL))) +#define bM4_TMR62_ICONR_INTENE (*((volatile unsigned int*)(0x42308A90UL))) +#define bM4_TMR62_ICONR_INTENF (*((volatile unsigned int*)(0x42308A94UL))) +#define bM4_TMR62_ICONR_INTENOVF (*((volatile unsigned int*)(0x42308A98UL))) +#define bM4_TMR62_ICONR_INTENUDF (*((volatile unsigned int*)(0x42308A9CUL))) +#define bM4_TMR62_ICONR_INTENDTE (*((volatile unsigned int*)(0x42308AA0UL))) +#define bM4_TMR62_ICONR_INTENSAU (*((volatile unsigned int*)(0x42308AC0UL))) +#define bM4_TMR62_ICONR_INTENSAD (*((volatile unsigned int*)(0x42308AC4UL))) +#define bM4_TMR62_ICONR_INTENSBU (*((volatile unsigned int*)(0x42308AC8UL))) +#define bM4_TMR62_ICONR_INTENSBD (*((volatile unsigned int*)(0x42308ACCUL))) +#define bM4_TMR62_PCONR_CAPMDA (*((volatile unsigned int*)(0x42308B00UL))) +#define bM4_TMR62_PCONR_STACA (*((volatile unsigned int*)(0x42308B04UL))) +#define bM4_TMR62_PCONR_STPCA (*((volatile unsigned int*)(0x42308B08UL))) +#define bM4_TMR62_PCONR_STASTPSA (*((volatile unsigned int*)(0x42308B0CUL))) +#define bM4_TMR62_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42308B10UL))) +#define bM4_TMR62_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42308B14UL))) +#define bM4_TMR62_PCONR_PERCA0 (*((volatile unsigned int*)(0x42308B18UL))) +#define bM4_TMR62_PCONR_PERCA1 (*((volatile unsigned int*)(0x42308B1CUL))) +#define bM4_TMR62_PCONR_OUTENA (*((volatile unsigned int*)(0x42308B20UL))) +#define bM4_TMR62_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42308B2CUL))) +#define bM4_TMR62_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42308B30UL))) +#define bM4_TMR62_PCONR_CAPMDB (*((volatile unsigned int*)(0x42308B40UL))) +#define bM4_TMR62_PCONR_STACB (*((volatile unsigned int*)(0x42308B44UL))) +#define bM4_TMR62_PCONR_STPCB (*((volatile unsigned int*)(0x42308B48UL))) +#define bM4_TMR62_PCONR_STASTPSB (*((volatile unsigned int*)(0x42308B4CUL))) +#define bM4_TMR62_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42308B50UL))) +#define bM4_TMR62_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42308B54UL))) +#define bM4_TMR62_PCONR_PERCB0 (*((volatile unsigned int*)(0x42308B58UL))) +#define bM4_TMR62_PCONR_PERCB1 (*((volatile unsigned int*)(0x42308B5CUL))) +#define bM4_TMR62_PCONR_OUTENB (*((volatile unsigned int*)(0x42308B60UL))) +#define bM4_TMR62_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42308B6CUL))) +#define bM4_TMR62_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42308B70UL))) +#define bM4_TMR62_BCONR_BENA (*((volatile unsigned int*)(0x42308B80UL))) +#define bM4_TMR62_BCONR_BSEA (*((volatile unsigned int*)(0x42308B84UL))) +#define bM4_TMR62_BCONR_BENB (*((volatile unsigned int*)(0x42308B88UL))) +#define bM4_TMR62_BCONR_BSEB (*((volatile unsigned int*)(0x42308B8CUL))) +#define bM4_TMR62_BCONR_BENP (*((volatile unsigned int*)(0x42308BA0UL))) +#define bM4_TMR62_BCONR_BSEP (*((volatile unsigned int*)(0x42308BA4UL))) +#define bM4_TMR62_BCONR_BENSPA (*((volatile unsigned int*)(0x42308BC0UL))) +#define bM4_TMR62_BCONR_BSESPA (*((volatile unsigned int*)(0x42308BC4UL))) +#define bM4_TMR62_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42308BD0UL))) +#define bM4_TMR62_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42308BD4UL))) +#define bM4_TMR62_BCONR_BENSPB (*((volatile unsigned int*)(0x42308BE0UL))) +#define bM4_TMR62_BCONR_BSESPB (*((volatile unsigned int*)(0x42308BE4UL))) +#define bM4_TMR62_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42308BF0UL))) +#define bM4_TMR62_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42308BF4UL))) +#define bM4_TMR62_DCONR_DTCEN (*((volatile unsigned int*)(0x42308C00UL))) +#define bM4_TMR62_DCONR_DTBENU (*((volatile unsigned int*)(0x42308C10UL))) +#define bM4_TMR62_DCONR_DTBEND (*((volatile unsigned int*)(0x42308C14UL))) +#define bM4_TMR62_DCONR_SEPA (*((volatile unsigned int*)(0x42308C20UL))) +#define bM4_TMR62_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42308D00UL))) +#define bM4_TMR62_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42308D04UL))) +#define bM4_TMR62_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42308D08UL))) +#define bM4_TMR62_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42308D10UL))) +#define bM4_TMR62_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42308D14UL))) +#define bM4_TMR62_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42308D18UL))) +#define bM4_TMR62_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42308D40UL))) +#define bM4_TMR62_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42308D44UL))) +#define bM4_TMR62_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42308D48UL))) +#define bM4_TMR62_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42308D50UL))) +#define bM4_TMR62_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42308D54UL))) +#define bM4_TMR62_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42308D58UL))) +#define bM4_TMR62_VPERR_SPPERIA (*((volatile unsigned int*)(0x42308DA0UL))) +#define bM4_TMR62_VPERR_SPPERIB (*((volatile unsigned int*)(0x42308DA4UL))) +#define bM4_TMR62_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42308DC0UL))) +#define bM4_TMR62_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42308DC4UL))) +#define bM4_TMR62_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42308DC8UL))) +#define bM4_TMR62_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42308DCCUL))) +#define bM4_TMR62_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42308DD0UL))) +#define bM4_TMR62_STFLR_CMAF (*((volatile unsigned int*)(0x42308E00UL))) +#define bM4_TMR62_STFLR_CMBF (*((volatile unsigned int*)(0x42308E04UL))) +#define bM4_TMR62_STFLR_CMCF (*((volatile unsigned int*)(0x42308E08UL))) +#define bM4_TMR62_STFLR_CMDF (*((volatile unsigned int*)(0x42308E0CUL))) +#define bM4_TMR62_STFLR_CMEF (*((volatile unsigned int*)(0x42308E10UL))) +#define bM4_TMR62_STFLR_CMFF (*((volatile unsigned int*)(0x42308E14UL))) +#define bM4_TMR62_STFLR_OVFF (*((volatile unsigned int*)(0x42308E18UL))) +#define bM4_TMR62_STFLR_UDFF (*((volatile unsigned int*)(0x42308E1CUL))) +#define bM4_TMR62_STFLR_DTEF (*((volatile unsigned int*)(0x42308E20UL))) +#define bM4_TMR62_STFLR_CMSAUF (*((volatile unsigned int*)(0x42308E24UL))) +#define bM4_TMR62_STFLR_CMSADF (*((volatile unsigned int*)(0x42308E28UL))) +#define bM4_TMR62_STFLR_CMSBUF (*((volatile unsigned int*)(0x42308E2CUL))) +#define bM4_TMR62_STFLR_CMSBDF (*((volatile unsigned int*)(0x42308E30UL))) +#define bM4_TMR62_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42308E54UL))) +#define bM4_TMR62_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42308E58UL))) +#define bM4_TMR62_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42308E5CUL))) +#define bM4_TMR62_STFLR_DIRF (*((volatile unsigned int*)(0x42308E7CUL))) +#define bM4_TMR62_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42308E80UL))) +#define bM4_TMR62_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42308E84UL))) +#define bM4_TMR62_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42308E90UL))) +#define bM4_TMR62_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42308E94UL))) +#define bM4_TMR62_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42308E98UL))) +#define bM4_TMR62_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42308E9CUL))) +#define bM4_TMR62_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42308EA0UL))) +#define bM4_TMR62_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42308EA4UL))) +#define bM4_TMR62_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42308EA8UL))) +#define bM4_TMR62_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42308EACUL))) +#define bM4_TMR62_HSTAR_STARTS (*((volatile unsigned int*)(0x42308EFCUL))) +#define bM4_TMR62_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42308F00UL))) +#define bM4_TMR62_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42308F04UL))) +#define bM4_TMR62_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42308F10UL))) +#define bM4_TMR62_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42308F14UL))) +#define bM4_TMR62_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42308F18UL))) +#define bM4_TMR62_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42308F1CUL))) +#define bM4_TMR62_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42308F20UL))) +#define bM4_TMR62_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42308F24UL))) +#define bM4_TMR62_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42308F28UL))) +#define bM4_TMR62_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42308F2CUL))) +#define bM4_TMR62_HSTPR_STOPS (*((volatile unsigned int*)(0x42308F7CUL))) +#define bM4_TMR62_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42308F80UL))) +#define bM4_TMR62_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42308F84UL))) +#define bM4_TMR62_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42308F90UL))) +#define bM4_TMR62_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42308F94UL))) +#define bM4_TMR62_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42308F98UL))) +#define bM4_TMR62_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42308F9CUL))) +#define bM4_TMR62_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42308FA0UL))) +#define bM4_TMR62_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42308FA4UL))) +#define bM4_TMR62_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42308FA8UL))) +#define bM4_TMR62_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42308FACUL))) +#define bM4_TMR62_HCLRR_CLEARS (*((volatile unsigned int*)(0x42308FFCUL))) +#define bM4_TMR62_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42309000UL))) +#define bM4_TMR62_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42309004UL))) +#define bM4_TMR62_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42309010UL))) +#define bM4_TMR62_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42309014UL))) +#define bM4_TMR62_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42309018UL))) +#define bM4_TMR62_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4230901CUL))) +#define bM4_TMR62_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42309020UL))) +#define bM4_TMR62_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42309024UL))) +#define bM4_TMR62_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42309028UL))) +#define bM4_TMR62_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4230902CUL))) +#define bM4_TMR62_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42309080UL))) +#define bM4_TMR62_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42309084UL))) +#define bM4_TMR62_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42309090UL))) +#define bM4_TMR62_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42309094UL))) +#define bM4_TMR62_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42309098UL))) +#define bM4_TMR62_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4230909CUL))) +#define bM4_TMR62_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423090A0UL))) +#define bM4_TMR62_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423090A4UL))) +#define bM4_TMR62_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423090A8UL))) +#define bM4_TMR62_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423090ACUL))) +#define bM4_TMR62_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42309100UL))) +#define bM4_TMR62_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42309104UL))) +#define bM4_TMR62_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42309108UL))) +#define bM4_TMR62_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4230910CUL))) +#define bM4_TMR62_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42309110UL))) +#define bM4_TMR62_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42309114UL))) +#define bM4_TMR62_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42309118UL))) +#define bM4_TMR62_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4230911CUL))) +#define bM4_TMR62_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42309120UL))) +#define bM4_TMR62_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42309124UL))) +#define bM4_TMR62_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42309128UL))) +#define bM4_TMR62_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4230912CUL))) +#define bM4_TMR62_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42309140UL))) +#define bM4_TMR62_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42309144UL))) +#define bM4_TMR62_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42309180UL))) +#define bM4_TMR62_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42309184UL))) +#define bM4_TMR62_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42309188UL))) +#define bM4_TMR62_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4230918CUL))) +#define bM4_TMR62_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42309190UL))) +#define bM4_TMR62_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42309194UL))) +#define bM4_TMR62_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42309198UL))) +#define bM4_TMR62_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4230919CUL))) +#define bM4_TMR62_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423091A0UL))) +#define bM4_TMR62_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423091A4UL))) +#define bM4_TMR62_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423091A8UL))) +#define bM4_TMR62_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423091ACUL))) +#define bM4_TMR62_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423091C0UL))) +#define bM4_TMR62_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423091C4UL))) +#define bM4_TMR63_CNTER_CNT0 (*((volatile unsigned int*)(0x42310000UL))) +#define bM4_TMR63_CNTER_CNT1 (*((volatile unsigned int*)(0x42310004UL))) +#define bM4_TMR63_CNTER_CNT2 (*((volatile unsigned int*)(0x42310008UL))) +#define bM4_TMR63_CNTER_CNT3 (*((volatile unsigned int*)(0x4231000CUL))) +#define bM4_TMR63_CNTER_CNT4 (*((volatile unsigned int*)(0x42310010UL))) +#define bM4_TMR63_CNTER_CNT5 (*((volatile unsigned int*)(0x42310014UL))) +#define bM4_TMR63_CNTER_CNT6 (*((volatile unsigned int*)(0x42310018UL))) +#define bM4_TMR63_CNTER_CNT7 (*((volatile unsigned int*)(0x4231001CUL))) +#define bM4_TMR63_CNTER_CNT8 (*((volatile unsigned int*)(0x42310020UL))) +#define bM4_TMR63_CNTER_CNT9 (*((volatile unsigned int*)(0x42310024UL))) +#define bM4_TMR63_CNTER_CNT10 (*((volatile unsigned int*)(0x42310028UL))) +#define bM4_TMR63_CNTER_CNT11 (*((volatile unsigned int*)(0x4231002CUL))) +#define bM4_TMR63_CNTER_CNT12 (*((volatile unsigned int*)(0x42310030UL))) +#define bM4_TMR63_CNTER_CNT13 (*((volatile unsigned int*)(0x42310034UL))) +#define bM4_TMR63_CNTER_CNT14 (*((volatile unsigned int*)(0x42310038UL))) +#define bM4_TMR63_CNTER_CNT15 (*((volatile unsigned int*)(0x4231003CUL))) +#define bM4_TMR63_PERAR_PERA0 (*((volatile unsigned int*)(0x42310080UL))) +#define bM4_TMR63_PERAR_PERA1 (*((volatile unsigned int*)(0x42310084UL))) +#define bM4_TMR63_PERAR_PERA2 (*((volatile unsigned int*)(0x42310088UL))) +#define bM4_TMR63_PERAR_PERA3 (*((volatile unsigned int*)(0x4231008CUL))) +#define bM4_TMR63_PERAR_PERA4 (*((volatile unsigned int*)(0x42310090UL))) +#define bM4_TMR63_PERAR_PERA5 (*((volatile unsigned int*)(0x42310094UL))) +#define bM4_TMR63_PERAR_PERA6 (*((volatile unsigned int*)(0x42310098UL))) +#define bM4_TMR63_PERAR_PERA7 (*((volatile unsigned int*)(0x4231009CUL))) +#define bM4_TMR63_PERAR_PERA8 (*((volatile unsigned int*)(0x423100A0UL))) +#define bM4_TMR63_PERAR_PERA9 (*((volatile unsigned int*)(0x423100A4UL))) +#define bM4_TMR63_PERAR_PERA10 (*((volatile unsigned int*)(0x423100A8UL))) +#define bM4_TMR63_PERAR_PERA11 (*((volatile unsigned int*)(0x423100ACUL))) +#define bM4_TMR63_PERAR_PERA12 (*((volatile unsigned int*)(0x423100B0UL))) +#define bM4_TMR63_PERAR_PERA13 (*((volatile unsigned int*)(0x423100B4UL))) +#define bM4_TMR63_PERAR_PERA14 (*((volatile unsigned int*)(0x423100B8UL))) +#define bM4_TMR63_PERAR_PERA15 (*((volatile unsigned int*)(0x423100BCUL))) +#define bM4_TMR63_PERBR_PERB0 (*((volatile unsigned int*)(0x42310100UL))) +#define bM4_TMR63_PERBR_PERB1 (*((volatile unsigned int*)(0x42310104UL))) +#define bM4_TMR63_PERBR_PERB2 (*((volatile unsigned int*)(0x42310108UL))) +#define bM4_TMR63_PERBR_PERB3 (*((volatile unsigned int*)(0x4231010CUL))) +#define bM4_TMR63_PERBR_PERB4 (*((volatile unsigned int*)(0x42310110UL))) +#define bM4_TMR63_PERBR_PERB5 (*((volatile unsigned int*)(0x42310114UL))) +#define bM4_TMR63_PERBR_PERB6 (*((volatile unsigned int*)(0x42310118UL))) +#define bM4_TMR63_PERBR_PERB7 (*((volatile unsigned int*)(0x4231011CUL))) +#define bM4_TMR63_PERBR_PERB8 (*((volatile unsigned int*)(0x42310120UL))) +#define bM4_TMR63_PERBR_PERB9 (*((volatile unsigned int*)(0x42310124UL))) +#define bM4_TMR63_PERBR_PERB10 (*((volatile unsigned int*)(0x42310128UL))) +#define bM4_TMR63_PERBR_PERB11 (*((volatile unsigned int*)(0x4231012CUL))) +#define bM4_TMR63_PERBR_PERB12 (*((volatile unsigned int*)(0x42310130UL))) +#define bM4_TMR63_PERBR_PERB13 (*((volatile unsigned int*)(0x42310134UL))) +#define bM4_TMR63_PERBR_PERB14 (*((volatile unsigned int*)(0x42310138UL))) +#define bM4_TMR63_PERBR_PERB15 (*((volatile unsigned int*)(0x4231013CUL))) +#define bM4_TMR63_PERCR_PERC0 (*((volatile unsigned int*)(0x42310180UL))) +#define bM4_TMR63_PERCR_PERC1 (*((volatile unsigned int*)(0x42310184UL))) +#define bM4_TMR63_PERCR_PERC2 (*((volatile unsigned int*)(0x42310188UL))) +#define bM4_TMR63_PERCR_PERC3 (*((volatile unsigned int*)(0x4231018CUL))) +#define bM4_TMR63_PERCR_PERC4 (*((volatile unsigned int*)(0x42310190UL))) +#define bM4_TMR63_PERCR_PERC5 (*((volatile unsigned int*)(0x42310194UL))) +#define bM4_TMR63_PERCR_PERC6 (*((volatile unsigned int*)(0x42310198UL))) +#define bM4_TMR63_PERCR_PERC7 (*((volatile unsigned int*)(0x4231019CUL))) +#define bM4_TMR63_PERCR_PERC8 (*((volatile unsigned int*)(0x423101A0UL))) +#define bM4_TMR63_PERCR_PERC9 (*((volatile unsigned int*)(0x423101A4UL))) +#define bM4_TMR63_PERCR_PERC10 (*((volatile unsigned int*)(0x423101A8UL))) +#define bM4_TMR63_PERCR_PERC11 (*((volatile unsigned int*)(0x423101ACUL))) +#define bM4_TMR63_PERCR_PERC12 (*((volatile unsigned int*)(0x423101B0UL))) +#define bM4_TMR63_PERCR_PERC13 (*((volatile unsigned int*)(0x423101B4UL))) +#define bM4_TMR63_PERCR_PERC14 (*((volatile unsigned int*)(0x423101B8UL))) +#define bM4_TMR63_PERCR_PERC15 (*((volatile unsigned int*)(0x423101BCUL))) +#define bM4_TMR63_GCMAR_GCMA0 (*((volatile unsigned int*)(0x42310200UL))) +#define bM4_TMR63_GCMAR_GCMA1 (*((volatile unsigned int*)(0x42310204UL))) +#define bM4_TMR63_GCMAR_GCMA2 (*((volatile unsigned int*)(0x42310208UL))) +#define bM4_TMR63_GCMAR_GCMA3 (*((volatile unsigned int*)(0x4231020CUL))) +#define bM4_TMR63_GCMAR_GCMA4 (*((volatile unsigned int*)(0x42310210UL))) +#define bM4_TMR63_GCMAR_GCMA5 (*((volatile unsigned int*)(0x42310214UL))) +#define bM4_TMR63_GCMAR_GCMA6 (*((volatile unsigned int*)(0x42310218UL))) +#define bM4_TMR63_GCMAR_GCMA7 (*((volatile unsigned int*)(0x4231021CUL))) +#define bM4_TMR63_GCMAR_GCMA8 (*((volatile unsigned int*)(0x42310220UL))) +#define bM4_TMR63_GCMAR_GCMA9 (*((volatile unsigned int*)(0x42310224UL))) +#define bM4_TMR63_GCMAR_GCMA10 (*((volatile unsigned int*)(0x42310228UL))) +#define bM4_TMR63_GCMAR_GCMA11 (*((volatile unsigned int*)(0x4231022CUL))) +#define bM4_TMR63_GCMAR_GCMA12 (*((volatile unsigned int*)(0x42310230UL))) +#define bM4_TMR63_GCMAR_GCMA13 (*((volatile unsigned int*)(0x42310234UL))) +#define bM4_TMR63_GCMAR_GCMA14 (*((volatile unsigned int*)(0x42310238UL))) +#define bM4_TMR63_GCMAR_GCMA15 (*((volatile unsigned int*)(0x4231023CUL))) +#define bM4_TMR63_GCMBR_GCMB0 (*((volatile unsigned int*)(0x42310280UL))) +#define bM4_TMR63_GCMBR_GCMB1 (*((volatile unsigned int*)(0x42310284UL))) +#define bM4_TMR63_GCMBR_GCMB2 (*((volatile unsigned int*)(0x42310288UL))) +#define bM4_TMR63_GCMBR_GCMB3 (*((volatile unsigned int*)(0x4231028CUL))) +#define bM4_TMR63_GCMBR_GCMB4 (*((volatile unsigned int*)(0x42310290UL))) +#define bM4_TMR63_GCMBR_GCMB5 (*((volatile unsigned int*)(0x42310294UL))) +#define bM4_TMR63_GCMBR_GCMB6 (*((volatile unsigned int*)(0x42310298UL))) +#define bM4_TMR63_GCMBR_GCMB7 (*((volatile unsigned int*)(0x4231029CUL))) +#define bM4_TMR63_GCMBR_GCMB8 (*((volatile unsigned int*)(0x423102A0UL))) +#define bM4_TMR63_GCMBR_GCMB9 (*((volatile unsigned int*)(0x423102A4UL))) +#define bM4_TMR63_GCMBR_GCMB10 (*((volatile unsigned int*)(0x423102A8UL))) +#define bM4_TMR63_GCMBR_GCMB11 (*((volatile unsigned int*)(0x423102ACUL))) +#define bM4_TMR63_GCMBR_GCMB12 (*((volatile unsigned int*)(0x423102B0UL))) +#define bM4_TMR63_GCMBR_GCMB13 (*((volatile unsigned int*)(0x423102B4UL))) +#define bM4_TMR63_GCMBR_GCMB14 (*((volatile unsigned int*)(0x423102B8UL))) +#define bM4_TMR63_GCMBR_GCMB15 (*((volatile unsigned int*)(0x423102BCUL))) +#define bM4_TMR63_GCMCR_GCMC0 (*((volatile unsigned int*)(0x42310300UL))) +#define bM4_TMR63_GCMCR_GCMC1 (*((volatile unsigned int*)(0x42310304UL))) +#define bM4_TMR63_GCMCR_GCMC2 (*((volatile unsigned int*)(0x42310308UL))) +#define bM4_TMR63_GCMCR_GCMC3 (*((volatile unsigned int*)(0x4231030CUL))) +#define bM4_TMR63_GCMCR_GCMC4 (*((volatile unsigned int*)(0x42310310UL))) +#define bM4_TMR63_GCMCR_GCMC5 (*((volatile unsigned int*)(0x42310314UL))) +#define bM4_TMR63_GCMCR_GCMC6 (*((volatile unsigned int*)(0x42310318UL))) +#define bM4_TMR63_GCMCR_GCMC7 (*((volatile unsigned int*)(0x4231031CUL))) +#define bM4_TMR63_GCMCR_GCMC8 (*((volatile unsigned int*)(0x42310320UL))) +#define bM4_TMR63_GCMCR_GCMC9 (*((volatile unsigned int*)(0x42310324UL))) +#define bM4_TMR63_GCMCR_GCMC10 (*((volatile unsigned int*)(0x42310328UL))) +#define bM4_TMR63_GCMCR_GCMC11 (*((volatile unsigned int*)(0x4231032CUL))) +#define bM4_TMR63_GCMCR_GCMC12 (*((volatile unsigned int*)(0x42310330UL))) +#define bM4_TMR63_GCMCR_GCMC13 (*((volatile unsigned int*)(0x42310334UL))) +#define bM4_TMR63_GCMCR_GCMC14 (*((volatile unsigned int*)(0x42310338UL))) +#define bM4_TMR63_GCMCR_GCMC15 (*((volatile unsigned int*)(0x4231033CUL))) +#define bM4_TMR63_GCMDR_GCMD0 (*((volatile unsigned int*)(0x42310380UL))) +#define bM4_TMR63_GCMDR_GCMD1 (*((volatile unsigned int*)(0x42310384UL))) +#define bM4_TMR63_GCMDR_GCMD2 (*((volatile unsigned int*)(0x42310388UL))) +#define bM4_TMR63_GCMDR_GCMD3 (*((volatile unsigned int*)(0x4231038CUL))) +#define bM4_TMR63_GCMDR_GCMD4 (*((volatile unsigned int*)(0x42310390UL))) +#define bM4_TMR63_GCMDR_GCMD5 (*((volatile unsigned int*)(0x42310394UL))) +#define bM4_TMR63_GCMDR_GCMD6 (*((volatile unsigned int*)(0x42310398UL))) +#define bM4_TMR63_GCMDR_GCMD7 (*((volatile unsigned int*)(0x4231039CUL))) +#define bM4_TMR63_GCMDR_GCMD8 (*((volatile unsigned int*)(0x423103A0UL))) +#define bM4_TMR63_GCMDR_GCMD9 (*((volatile unsigned int*)(0x423103A4UL))) +#define bM4_TMR63_GCMDR_GCMD10 (*((volatile unsigned int*)(0x423103A8UL))) +#define bM4_TMR63_GCMDR_GCMD11 (*((volatile unsigned int*)(0x423103ACUL))) +#define bM4_TMR63_GCMDR_GCMD12 (*((volatile unsigned int*)(0x423103B0UL))) +#define bM4_TMR63_GCMDR_GCMD13 (*((volatile unsigned int*)(0x423103B4UL))) +#define bM4_TMR63_GCMDR_GCMD14 (*((volatile unsigned int*)(0x423103B8UL))) +#define bM4_TMR63_GCMDR_GCMD15 (*((volatile unsigned int*)(0x423103BCUL))) +#define bM4_TMR63_GCMER_GCME0 (*((volatile unsigned int*)(0x42310400UL))) +#define bM4_TMR63_GCMER_GCME1 (*((volatile unsigned int*)(0x42310404UL))) +#define bM4_TMR63_GCMER_GCME2 (*((volatile unsigned int*)(0x42310408UL))) +#define bM4_TMR63_GCMER_GCME3 (*((volatile unsigned int*)(0x4231040CUL))) +#define bM4_TMR63_GCMER_GCME4 (*((volatile unsigned int*)(0x42310410UL))) +#define bM4_TMR63_GCMER_GCME5 (*((volatile unsigned int*)(0x42310414UL))) +#define bM4_TMR63_GCMER_GCME6 (*((volatile unsigned int*)(0x42310418UL))) +#define bM4_TMR63_GCMER_GCME7 (*((volatile unsigned int*)(0x4231041CUL))) +#define bM4_TMR63_GCMER_GCME8 (*((volatile unsigned int*)(0x42310420UL))) +#define bM4_TMR63_GCMER_GCME9 (*((volatile unsigned int*)(0x42310424UL))) +#define bM4_TMR63_GCMER_GCME10 (*((volatile unsigned int*)(0x42310428UL))) +#define bM4_TMR63_GCMER_GCME11 (*((volatile unsigned int*)(0x4231042CUL))) +#define bM4_TMR63_GCMER_GCME12 (*((volatile unsigned int*)(0x42310430UL))) +#define bM4_TMR63_GCMER_GCME13 (*((volatile unsigned int*)(0x42310434UL))) +#define bM4_TMR63_GCMER_GCME14 (*((volatile unsigned int*)(0x42310438UL))) +#define bM4_TMR63_GCMER_GCME15 (*((volatile unsigned int*)(0x4231043CUL))) +#define bM4_TMR63_GCMFR_GCMF0 (*((volatile unsigned int*)(0x42310480UL))) +#define bM4_TMR63_GCMFR_GCMF1 (*((volatile unsigned int*)(0x42310484UL))) +#define bM4_TMR63_GCMFR_GCMF2 (*((volatile unsigned int*)(0x42310488UL))) +#define bM4_TMR63_GCMFR_GCMF3 (*((volatile unsigned int*)(0x4231048CUL))) +#define bM4_TMR63_GCMFR_GCMF4 (*((volatile unsigned int*)(0x42310490UL))) +#define bM4_TMR63_GCMFR_GCMF5 (*((volatile unsigned int*)(0x42310494UL))) +#define bM4_TMR63_GCMFR_GCMF6 (*((volatile unsigned int*)(0x42310498UL))) +#define bM4_TMR63_GCMFR_GCMF7 (*((volatile unsigned int*)(0x4231049CUL))) +#define bM4_TMR63_GCMFR_GCMF8 (*((volatile unsigned int*)(0x423104A0UL))) +#define bM4_TMR63_GCMFR_GCMF9 (*((volatile unsigned int*)(0x423104A4UL))) +#define bM4_TMR63_GCMFR_GCMF10 (*((volatile unsigned int*)(0x423104A8UL))) +#define bM4_TMR63_GCMFR_GCMF11 (*((volatile unsigned int*)(0x423104ACUL))) +#define bM4_TMR63_GCMFR_GCMF12 (*((volatile unsigned int*)(0x423104B0UL))) +#define bM4_TMR63_GCMFR_GCMF13 (*((volatile unsigned int*)(0x423104B4UL))) +#define bM4_TMR63_GCMFR_GCMF14 (*((volatile unsigned int*)(0x423104B8UL))) +#define bM4_TMR63_GCMFR_GCMF15 (*((volatile unsigned int*)(0x423104BCUL))) +#define bM4_TMR63_SCMAR_SCMA0 (*((volatile unsigned int*)(0x42310500UL))) +#define bM4_TMR63_SCMAR_SCMA1 (*((volatile unsigned int*)(0x42310504UL))) +#define bM4_TMR63_SCMAR_SCMA2 (*((volatile unsigned int*)(0x42310508UL))) +#define bM4_TMR63_SCMAR_SCMA3 (*((volatile unsigned int*)(0x4231050CUL))) +#define bM4_TMR63_SCMAR_SCMA4 (*((volatile unsigned int*)(0x42310510UL))) +#define bM4_TMR63_SCMAR_SCMA5 (*((volatile unsigned int*)(0x42310514UL))) +#define bM4_TMR63_SCMAR_SCMA6 (*((volatile unsigned int*)(0x42310518UL))) +#define bM4_TMR63_SCMAR_SCMA7 (*((volatile unsigned int*)(0x4231051CUL))) +#define bM4_TMR63_SCMAR_SCMA8 (*((volatile unsigned int*)(0x42310520UL))) +#define bM4_TMR63_SCMAR_SCMA9 (*((volatile unsigned int*)(0x42310524UL))) +#define bM4_TMR63_SCMAR_SCMA10 (*((volatile unsigned int*)(0x42310528UL))) +#define bM4_TMR63_SCMAR_SCMA11 (*((volatile unsigned int*)(0x4231052CUL))) +#define bM4_TMR63_SCMAR_SCMA12 (*((volatile unsigned int*)(0x42310530UL))) +#define bM4_TMR63_SCMAR_SCMA13 (*((volatile unsigned int*)(0x42310534UL))) +#define bM4_TMR63_SCMAR_SCMA14 (*((volatile unsigned int*)(0x42310538UL))) +#define bM4_TMR63_SCMAR_SCMA15 (*((volatile unsigned int*)(0x4231053CUL))) +#define bM4_TMR63_SCMBR_SCMB0 (*((volatile unsigned int*)(0x42310580UL))) +#define bM4_TMR63_SCMBR_SCMB1 (*((volatile unsigned int*)(0x42310584UL))) +#define bM4_TMR63_SCMBR_SCMB2 (*((volatile unsigned int*)(0x42310588UL))) +#define bM4_TMR63_SCMBR_SCMB3 (*((volatile unsigned int*)(0x4231058CUL))) +#define bM4_TMR63_SCMBR_SCMB4 (*((volatile unsigned int*)(0x42310590UL))) +#define bM4_TMR63_SCMBR_SCMB5 (*((volatile unsigned int*)(0x42310594UL))) +#define bM4_TMR63_SCMBR_SCMB6 (*((volatile unsigned int*)(0x42310598UL))) +#define bM4_TMR63_SCMBR_SCMB7 (*((volatile unsigned int*)(0x4231059CUL))) +#define bM4_TMR63_SCMBR_SCMB8 (*((volatile unsigned int*)(0x423105A0UL))) +#define bM4_TMR63_SCMBR_SCMB9 (*((volatile unsigned int*)(0x423105A4UL))) +#define bM4_TMR63_SCMBR_SCMB10 (*((volatile unsigned int*)(0x423105A8UL))) +#define bM4_TMR63_SCMBR_SCMB11 (*((volatile unsigned int*)(0x423105ACUL))) +#define bM4_TMR63_SCMBR_SCMB12 (*((volatile unsigned int*)(0x423105B0UL))) +#define bM4_TMR63_SCMBR_SCMB13 (*((volatile unsigned int*)(0x423105B4UL))) +#define bM4_TMR63_SCMBR_SCMB14 (*((volatile unsigned int*)(0x423105B8UL))) +#define bM4_TMR63_SCMBR_SCMB15 (*((volatile unsigned int*)(0x423105BCUL))) +#define bM4_TMR63_SCMCR_SCMC0 (*((volatile unsigned int*)(0x42310600UL))) +#define bM4_TMR63_SCMCR_SCMC1 (*((volatile unsigned int*)(0x42310604UL))) +#define bM4_TMR63_SCMCR_SCMC2 (*((volatile unsigned int*)(0x42310608UL))) +#define bM4_TMR63_SCMCR_SCMC3 (*((volatile unsigned int*)(0x4231060CUL))) +#define bM4_TMR63_SCMCR_SCMC4 (*((volatile unsigned int*)(0x42310610UL))) +#define bM4_TMR63_SCMCR_SCMC5 (*((volatile unsigned int*)(0x42310614UL))) +#define bM4_TMR63_SCMCR_SCMC6 (*((volatile unsigned int*)(0x42310618UL))) +#define bM4_TMR63_SCMCR_SCMC7 (*((volatile unsigned int*)(0x4231061CUL))) +#define bM4_TMR63_SCMCR_SCMC8 (*((volatile unsigned int*)(0x42310620UL))) +#define bM4_TMR63_SCMCR_SCMC9 (*((volatile unsigned int*)(0x42310624UL))) +#define bM4_TMR63_SCMCR_SCMC10 (*((volatile unsigned int*)(0x42310628UL))) +#define bM4_TMR63_SCMCR_SCMC11 (*((volatile unsigned int*)(0x4231062CUL))) +#define bM4_TMR63_SCMCR_SCMC12 (*((volatile unsigned int*)(0x42310630UL))) +#define bM4_TMR63_SCMCR_SCMC13 (*((volatile unsigned int*)(0x42310634UL))) +#define bM4_TMR63_SCMCR_SCMC14 (*((volatile unsigned int*)(0x42310638UL))) +#define bM4_TMR63_SCMCR_SCMC15 (*((volatile unsigned int*)(0x4231063CUL))) +#define bM4_TMR63_SCMDR_SCMD0 (*((volatile unsigned int*)(0x42310680UL))) +#define bM4_TMR63_SCMDR_SCMD1 (*((volatile unsigned int*)(0x42310684UL))) +#define bM4_TMR63_SCMDR_SCMD2 (*((volatile unsigned int*)(0x42310688UL))) +#define bM4_TMR63_SCMDR_SCMD3 (*((volatile unsigned int*)(0x4231068CUL))) +#define bM4_TMR63_SCMDR_SCMD4 (*((volatile unsigned int*)(0x42310690UL))) +#define bM4_TMR63_SCMDR_SCMD5 (*((volatile unsigned int*)(0x42310694UL))) +#define bM4_TMR63_SCMDR_SCMD6 (*((volatile unsigned int*)(0x42310698UL))) +#define bM4_TMR63_SCMDR_SCMD7 (*((volatile unsigned int*)(0x4231069CUL))) +#define bM4_TMR63_SCMDR_SCMD8 (*((volatile unsigned int*)(0x423106A0UL))) +#define bM4_TMR63_SCMDR_SCMD9 (*((volatile unsigned int*)(0x423106A4UL))) +#define bM4_TMR63_SCMDR_SCMD10 (*((volatile unsigned int*)(0x423106A8UL))) +#define bM4_TMR63_SCMDR_SCMD11 (*((volatile unsigned int*)(0x423106ACUL))) +#define bM4_TMR63_SCMDR_SCMD12 (*((volatile unsigned int*)(0x423106B0UL))) +#define bM4_TMR63_SCMDR_SCMD13 (*((volatile unsigned int*)(0x423106B4UL))) +#define bM4_TMR63_SCMDR_SCMD14 (*((volatile unsigned int*)(0x423106B8UL))) +#define bM4_TMR63_SCMDR_SCMD15 (*((volatile unsigned int*)(0x423106BCUL))) +#define bM4_TMR63_SCMER_SCME0 (*((volatile unsigned int*)(0x42310700UL))) +#define bM4_TMR63_SCMER_SCME1 (*((volatile unsigned int*)(0x42310704UL))) +#define bM4_TMR63_SCMER_SCME2 (*((volatile unsigned int*)(0x42310708UL))) +#define bM4_TMR63_SCMER_SCME3 (*((volatile unsigned int*)(0x4231070CUL))) +#define bM4_TMR63_SCMER_SCME4 (*((volatile unsigned int*)(0x42310710UL))) +#define bM4_TMR63_SCMER_SCME5 (*((volatile unsigned int*)(0x42310714UL))) +#define bM4_TMR63_SCMER_SCME6 (*((volatile unsigned int*)(0x42310718UL))) +#define bM4_TMR63_SCMER_SCME7 (*((volatile unsigned int*)(0x4231071CUL))) +#define bM4_TMR63_SCMER_SCME8 (*((volatile unsigned int*)(0x42310720UL))) +#define bM4_TMR63_SCMER_SCME9 (*((volatile unsigned int*)(0x42310724UL))) +#define bM4_TMR63_SCMER_SCME10 (*((volatile unsigned int*)(0x42310728UL))) +#define bM4_TMR63_SCMER_SCME11 (*((volatile unsigned int*)(0x4231072CUL))) +#define bM4_TMR63_SCMER_SCME12 (*((volatile unsigned int*)(0x42310730UL))) +#define bM4_TMR63_SCMER_SCME13 (*((volatile unsigned int*)(0x42310734UL))) +#define bM4_TMR63_SCMER_SCME14 (*((volatile unsigned int*)(0x42310738UL))) +#define bM4_TMR63_SCMER_SCME15 (*((volatile unsigned int*)(0x4231073CUL))) +#define bM4_TMR63_SCMFR_SCMF0 (*((volatile unsigned int*)(0x42310780UL))) +#define bM4_TMR63_SCMFR_SCMF1 (*((volatile unsigned int*)(0x42310784UL))) +#define bM4_TMR63_SCMFR_SCMF2 (*((volatile unsigned int*)(0x42310788UL))) +#define bM4_TMR63_SCMFR_SCMF3 (*((volatile unsigned int*)(0x4231078CUL))) +#define bM4_TMR63_SCMFR_SCMF4 (*((volatile unsigned int*)(0x42310790UL))) +#define bM4_TMR63_SCMFR_SCMF5 (*((volatile unsigned int*)(0x42310794UL))) +#define bM4_TMR63_SCMFR_SCMF6 (*((volatile unsigned int*)(0x42310798UL))) +#define bM4_TMR63_SCMFR_SCMF7 (*((volatile unsigned int*)(0x4231079CUL))) +#define bM4_TMR63_SCMFR_SCMF8 (*((volatile unsigned int*)(0x423107A0UL))) +#define bM4_TMR63_SCMFR_SCMF9 (*((volatile unsigned int*)(0x423107A4UL))) +#define bM4_TMR63_SCMFR_SCMF10 (*((volatile unsigned int*)(0x423107A8UL))) +#define bM4_TMR63_SCMFR_SCMF11 (*((volatile unsigned int*)(0x423107ACUL))) +#define bM4_TMR63_SCMFR_SCMF12 (*((volatile unsigned int*)(0x423107B0UL))) +#define bM4_TMR63_SCMFR_SCMF13 (*((volatile unsigned int*)(0x423107B4UL))) +#define bM4_TMR63_SCMFR_SCMF14 (*((volatile unsigned int*)(0x423107B8UL))) +#define bM4_TMR63_SCMFR_SCMF15 (*((volatile unsigned int*)(0x423107BCUL))) +#define bM4_TMR63_DTUAR_DTUA0 (*((volatile unsigned int*)(0x42310800UL))) +#define bM4_TMR63_DTUAR_DTUA1 (*((volatile unsigned int*)(0x42310804UL))) +#define bM4_TMR63_DTUAR_DTUA2 (*((volatile unsigned int*)(0x42310808UL))) +#define bM4_TMR63_DTUAR_DTUA3 (*((volatile unsigned int*)(0x4231080CUL))) +#define bM4_TMR63_DTUAR_DTUA4 (*((volatile unsigned int*)(0x42310810UL))) +#define bM4_TMR63_DTUAR_DTUA5 (*((volatile unsigned int*)(0x42310814UL))) +#define bM4_TMR63_DTUAR_DTUA6 (*((volatile unsigned int*)(0x42310818UL))) +#define bM4_TMR63_DTUAR_DTUA7 (*((volatile unsigned int*)(0x4231081CUL))) +#define bM4_TMR63_DTUAR_DTUA8 (*((volatile unsigned int*)(0x42310820UL))) +#define bM4_TMR63_DTUAR_DTUA9 (*((volatile unsigned int*)(0x42310824UL))) +#define bM4_TMR63_DTUAR_DTUA10 (*((volatile unsigned int*)(0x42310828UL))) +#define bM4_TMR63_DTUAR_DTUA11 (*((volatile unsigned int*)(0x4231082CUL))) +#define bM4_TMR63_DTUAR_DTUA12 (*((volatile unsigned int*)(0x42310830UL))) +#define bM4_TMR63_DTUAR_DTUA13 (*((volatile unsigned int*)(0x42310834UL))) +#define bM4_TMR63_DTUAR_DTUA14 (*((volatile unsigned int*)(0x42310838UL))) +#define bM4_TMR63_DTUAR_DTUA15 (*((volatile unsigned int*)(0x4231083CUL))) +#define bM4_TMR63_DTDAR_DTDA0 (*((volatile unsigned int*)(0x42310880UL))) +#define bM4_TMR63_DTDAR_DTDA1 (*((volatile unsigned int*)(0x42310884UL))) +#define bM4_TMR63_DTDAR_DTDA2 (*((volatile unsigned int*)(0x42310888UL))) +#define bM4_TMR63_DTDAR_DTDA3 (*((volatile unsigned int*)(0x4231088CUL))) +#define bM4_TMR63_DTDAR_DTDA4 (*((volatile unsigned int*)(0x42310890UL))) +#define bM4_TMR63_DTDAR_DTDA5 (*((volatile unsigned int*)(0x42310894UL))) +#define bM4_TMR63_DTDAR_DTDA6 (*((volatile unsigned int*)(0x42310898UL))) +#define bM4_TMR63_DTDAR_DTDA7 (*((volatile unsigned int*)(0x4231089CUL))) +#define bM4_TMR63_DTDAR_DTDA8 (*((volatile unsigned int*)(0x423108A0UL))) +#define bM4_TMR63_DTDAR_DTDA9 (*((volatile unsigned int*)(0x423108A4UL))) +#define bM4_TMR63_DTDAR_DTDA10 (*((volatile unsigned int*)(0x423108A8UL))) +#define bM4_TMR63_DTDAR_DTDA11 (*((volatile unsigned int*)(0x423108ACUL))) +#define bM4_TMR63_DTDAR_DTDA12 (*((volatile unsigned int*)(0x423108B0UL))) +#define bM4_TMR63_DTDAR_DTDA13 (*((volatile unsigned int*)(0x423108B4UL))) +#define bM4_TMR63_DTDAR_DTDA14 (*((volatile unsigned int*)(0x423108B8UL))) +#define bM4_TMR63_DTDAR_DTDA15 (*((volatile unsigned int*)(0x423108BCUL))) +#define bM4_TMR63_DTUBR_DTUB0 (*((volatile unsigned int*)(0x42310900UL))) +#define bM4_TMR63_DTUBR_DTUB1 (*((volatile unsigned int*)(0x42310904UL))) +#define bM4_TMR63_DTUBR_DTUB2 (*((volatile unsigned int*)(0x42310908UL))) +#define bM4_TMR63_DTUBR_DTUB3 (*((volatile unsigned int*)(0x4231090CUL))) +#define bM4_TMR63_DTUBR_DTUB4 (*((volatile unsigned int*)(0x42310910UL))) +#define bM4_TMR63_DTUBR_DTUB5 (*((volatile unsigned int*)(0x42310914UL))) +#define bM4_TMR63_DTUBR_DTUB6 (*((volatile unsigned int*)(0x42310918UL))) +#define bM4_TMR63_DTUBR_DTUB7 (*((volatile unsigned int*)(0x4231091CUL))) +#define bM4_TMR63_DTUBR_DTUB8 (*((volatile unsigned int*)(0x42310920UL))) +#define bM4_TMR63_DTUBR_DTUB9 (*((volatile unsigned int*)(0x42310924UL))) +#define bM4_TMR63_DTUBR_DTUB10 (*((volatile unsigned int*)(0x42310928UL))) +#define bM4_TMR63_DTUBR_DTUB11 (*((volatile unsigned int*)(0x4231092CUL))) +#define bM4_TMR63_DTUBR_DTUB12 (*((volatile unsigned int*)(0x42310930UL))) +#define bM4_TMR63_DTUBR_DTUB13 (*((volatile unsigned int*)(0x42310934UL))) +#define bM4_TMR63_DTUBR_DTUB14 (*((volatile unsigned int*)(0x42310938UL))) +#define bM4_TMR63_DTUBR_DTUB15 (*((volatile unsigned int*)(0x4231093CUL))) +#define bM4_TMR63_DTDBR_DTDB0 (*((volatile unsigned int*)(0x42310980UL))) +#define bM4_TMR63_DTDBR_DTDB1 (*((volatile unsigned int*)(0x42310984UL))) +#define bM4_TMR63_DTDBR_DTDB2 (*((volatile unsigned int*)(0x42310988UL))) +#define bM4_TMR63_DTDBR_DTDB3 (*((volatile unsigned int*)(0x4231098CUL))) +#define bM4_TMR63_DTDBR_DTDB4 (*((volatile unsigned int*)(0x42310990UL))) +#define bM4_TMR63_DTDBR_DTDB5 (*((volatile unsigned int*)(0x42310994UL))) +#define bM4_TMR63_DTDBR_DTDB6 (*((volatile unsigned int*)(0x42310998UL))) +#define bM4_TMR63_DTDBR_DTDB7 (*((volatile unsigned int*)(0x4231099CUL))) +#define bM4_TMR63_DTDBR_DTDB8 (*((volatile unsigned int*)(0x423109A0UL))) +#define bM4_TMR63_DTDBR_DTDB9 (*((volatile unsigned int*)(0x423109A4UL))) +#define bM4_TMR63_DTDBR_DTDB10 (*((volatile unsigned int*)(0x423109A8UL))) +#define bM4_TMR63_DTDBR_DTDB11 (*((volatile unsigned int*)(0x423109ACUL))) +#define bM4_TMR63_DTDBR_DTDB12 (*((volatile unsigned int*)(0x423109B0UL))) +#define bM4_TMR63_DTDBR_DTDB13 (*((volatile unsigned int*)(0x423109B4UL))) +#define bM4_TMR63_DTDBR_DTDB14 (*((volatile unsigned int*)(0x423109B8UL))) +#define bM4_TMR63_DTDBR_DTDB15 (*((volatile unsigned int*)(0x423109BCUL))) +#define bM4_TMR63_GCONR_START (*((volatile unsigned int*)(0x42310A00UL))) +#define bM4_TMR63_GCONR_MODE0 (*((volatile unsigned int*)(0x42310A04UL))) +#define bM4_TMR63_GCONR_MODE1 (*((volatile unsigned int*)(0x42310A08UL))) +#define bM4_TMR63_GCONR_MODE2 (*((volatile unsigned int*)(0x42310A0CUL))) +#define bM4_TMR63_GCONR_CKDIV0 (*((volatile unsigned int*)(0x42310A10UL))) +#define bM4_TMR63_GCONR_CKDIV1 (*((volatile unsigned int*)(0x42310A14UL))) +#define bM4_TMR63_GCONR_CKDIV2 (*((volatile unsigned int*)(0x42310A18UL))) +#define bM4_TMR63_GCONR_DIR (*((volatile unsigned int*)(0x42310A20UL))) +#define bM4_TMR63_GCONR_ZMSKREV (*((volatile unsigned int*)(0x42310A40UL))) +#define bM4_TMR63_GCONR_ZMSKPOS (*((volatile unsigned int*)(0x42310A44UL))) +#define bM4_TMR63_GCONR_ZMSKVAL0 (*((volatile unsigned int*)(0x42310A48UL))) +#define bM4_TMR63_GCONR_ZMSKVAL1 (*((volatile unsigned int*)(0x42310A4CUL))) +#define bM4_TMR63_ICONR_INTENA (*((volatile unsigned int*)(0x42310A80UL))) +#define bM4_TMR63_ICONR_INTENB (*((volatile unsigned int*)(0x42310A84UL))) +#define bM4_TMR63_ICONR_INTENC (*((volatile unsigned int*)(0x42310A88UL))) +#define bM4_TMR63_ICONR_INTEND (*((volatile unsigned int*)(0x42310A8CUL))) +#define bM4_TMR63_ICONR_INTENE (*((volatile unsigned int*)(0x42310A90UL))) +#define bM4_TMR63_ICONR_INTENF (*((volatile unsigned int*)(0x42310A94UL))) +#define bM4_TMR63_ICONR_INTENOVF (*((volatile unsigned int*)(0x42310A98UL))) +#define bM4_TMR63_ICONR_INTENUDF (*((volatile unsigned int*)(0x42310A9CUL))) +#define bM4_TMR63_ICONR_INTENDTE (*((volatile unsigned int*)(0x42310AA0UL))) +#define bM4_TMR63_ICONR_INTENSAU (*((volatile unsigned int*)(0x42310AC0UL))) +#define bM4_TMR63_ICONR_INTENSAD (*((volatile unsigned int*)(0x42310AC4UL))) +#define bM4_TMR63_ICONR_INTENSBU (*((volatile unsigned int*)(0x42310AC8UL))) +#define bM4_TMR63_ICONR_INTENSBD (*((volatile unsigned int*)(0x42310ACCUL))) +#define bM4_TMR63_PCONR_CAPMDA (*((volatile unsigned int*)(0x42310B00UL))) +#define bM4_TMR63_PCONR_STACA (*((volatile unsigned int*)(0x42310B04UL))) +#define bM4_TMR63_PCONR_STPCA (*((volatile unsigned int*)(0x42310B08UL))) +#define bM4_TMR63_PCONR_STASTPSA (*((volatile unsigned int*)(0x42310B0CUL))) +#define bM4_TMR63_PCONR_CMPCA0 (*((volatile unsigned int*)(0x42310B10UL))) +#define bM4_TMR63_PCONR_CMPCA1 (*((volatile unsigned int*)(0x42310B14UL))) +#define bM4_TMR63_PCONR_PERCA0 (*((volatile unsigned int*)(0x42310B18UL))) +#define bM4_TMR63_PCONR_PERCA1 (*((volatile unsigned int*)(0x42310B1CUL))) +#define bM4_TMR63_PCONR_OUTENA (*((volatile unsigned int*)(0x42310B20UL))) +#define bM4_TMR63_PCONR_EMBVALA0 (*((volatile unsigned int*)(0x42310B2CUL))) +#define bM4_TMR63_PCONR_EMBVALA1 (*((volatile unsigned int*)(0x42310B30UL))) +#define bM4_TMR63_PCONR_CAPMDB (*((volatile unsigned int*)(0x42310B40UL))) +#define bM4_TMR63_PCONR_STACB (*((volatile unsigned int*)(0x42310B44UL))) +#define bM4_TMR63_PCONR_STPCB (*((volatile unsigned int*)(0x42310B48UL))) +#define bM4_TMR63_PCONR_STASTPSB (*((volatile unsigned int*)(0x42310B4CUL))) +#define bM4_TMR63_PCONR_CMPCB0 (*((volatile unsigned int*)(0x42310B50UL))) +#define bM4_TMR63_PCONR_CMPCB1 (*((volatile unsigned int*)(0x42310B54UL))) +#define bM4_TMR63_PCONR_PERCB0 (*((volatile unsigned int*)(0x42310B58UL))) +#define bM4_TMR63_PCONR_PERCB1 (*((volatile unsigned int*)(0x42310B5CUL))) +#define bM4_TMR63_PCONR_OUTENB (*((volatile unsigned int*)(0x42310B60UL))) +#define bM4_TMR63_PCONR_EMBVALB0 (*((volatile unsigned int*)(0x42310B6CUL))) +#define bM4_TMR63_PCONR_EMBVALB1 (*((volatile unsigned int*)(0x42310B70UL))) +#define bM4_TMR63_BCONR_BENA (*((volatile unsigned int*)(0x42310B80UL))) +#define bM4_TMR63_BCONR_BSEA (*((volatile unsigned int*)(0x42310B84UL))) +#define bM4_TMR63_BCONR_BENB (*((volatile unsigned int*)(0x42310B88UL))) +#define bM4_TMR63_BCONR_BSEB (*((volatile unsigned int*)(0x42310B8CUL))) +#define bM4_TMR63_BCONR_BENP (*((volatile unsigned int*)(0x42310BA0UL))) +#define bM4_TMR63_BCONR_BSEP (*((volatile unsigned int*)(0x42310BA4UL))) +#define bM4_TMR63_BCONR_BENSPA (*((volatile unsigned int*)(0x42310BC0UL))) +#define bM4_TMR63_BCONR_BSESPA (*((volatile unsigned int*)(0x42310BC4UL))) +#define bM4_TMR63_BCONR_BTRSPA0 (*((volatile unsigned int*)(0x42310BD0UL))) +#define bM4_TMR63_BCONR_BTRSPA1 (*((volatile unsigned int*)(0x42310BD4UL))) +#define bM4_TMR63_BCONR_BENSPB (*((volatile unsigned int*)(0x42310BE0UL))) +#define bM4_TMR63_BCONR_BSESPB (*((volatile unsigned int*)(0x42310BE4UL))) +#define bM4_TMR63_BCONR_BTRSPB0 (*((volatile unsigned int*)(0x42310BF0UL))) +#define bM4_TMR63_BCONR_BTRSPB1 (*((volatile unsigned int*)(0x42310BF4UL))) +#define bM4_TMR63_DCONR_DTCEN (*((volatile unsigned int*)(0x42310C00UL))) +#define bM4_TMR63_DCONR_DTBENU (*((volatile unsigned int*)(0x42310C10UL))) +#define bM4_TMR63_DCONR_DTBEND (*((volatile unsigned int*)(0x42310C14UL))) +#define bM4_TMR63_DCONR_SEPA (*((volatile unsigned int*)(0x42310C20UL))) +#define bM4_TMR63_FCONR_NOFIENGA (*((volatile unsigned int*)(0x42310D00UL))) +#define bM4_TMR63_FCONR_NOFICKGA0 (*((volatile unsigned int*)(0x42310D04UL))) +#define bM4_TMR63_FCONR_NOFICKGA1 (*((volatile unsigned int*)(0x42310D08UL))) +#define bM4_TMR63_FCONR_NOFIENGB (*((volatile unsigned int*)(0x42310D10UL))) +#define bM4_TMR63_FCONR_NOFICKGB0 (*((volatile unsigned int*)(0x42310D14UL))) +#define bM4_TMR63_FCONR_NOFICKGB1 (*((volatile unsigned int*)(0x42310D18UL))) +#define bM4_TMR63_FCONR_NOFIENTA (*((volatile unsigned int*)(0x42310D40UL))) +#define bM4_TMR63_FCONR_NOFICKTA0 (*((volatile unsigned int*)(0x42310D44UL))) +#define bM4_TMR63_FCONR_NOFICKTA1 (*((volatile unsigned int*)(0x42310D48UL))) +#define bM4_TMR63_FCONR_NOFIENTB (*((volatile unsigned int*)(0x42310D50UL))) +#define bM4_TMR63_FCONR_NOFICKTB0 (*((volatile unsigned int*)(0x42310D54UL))) +#define bM4_TMR63_FCONR_NOFICKTB1 (*((volatile unsigned int*)(0x42310D58UL))) +#define bM4_TMR63_VPERR_SPPERIA (*((volatile unsigned int*)(0x42310DA0UL))) +#define bM4_TMR63_VPERR_SPPERIB (*((volatile unsigned int*)(0x42310DA4UL))) +#define bM4_TMR63_VPERR_PCNTE0 (*((volatile unsigned int*)(0x42310DC0UL))) +#define bM4_TMR63_VPERR_PCNTE1 (*((volatile unsigned int*)(0x42310DC4UL))) +#define bM4_TMR63_VPERR_PCNTS0 (*((volatile unsigned int*)(0x42310DC8UL))) +#define bM4_TMR63_VPERR_PCNTS1 (*((volatile unsigned int*)(0x42310DCCUL))) +#define bM4_TMR63_VPERR_PCNTS2 (*((volatile unsigned int*)(0x42310DD0UL))) +#define bM4_TMR63_STFLR_CMAF (*((volatile unsigned int*)(0x42310E00UL))) +#define bM4_TMR63_STFLR_CMBF (*((volatile unsigned int*)(0x42310E04UL))) +#define bM4_TMR63_STFLR_CMCF (*((volatile unsigned int*)(0x42310E08UL))) +#define bM4_TMR63_STFLR_CMDF (*((volatile unsigned int*)(0x42310E0CUL))) +#define bM4_TMR63_STFLR_CMEF (*((volatile unsigned int*)(0x42310E10UL))) +#define bM4_TMR63_STFLR_CMFF (*((volatile unsigned int*)(0x42310E14UL))) +#define bM4_TMR63_STFLR_OVFF (*((volatile unsigned int*)(0x42310E18UL))) +#define bM4_TMR63_STFLR_UDFF (*((volatile unsigned int*)(0x42310E1CUL))) +#define bM4_TMR63_STFLR_DTEF (*((volatile unsigned int*)(0x42310E20UL))) +#define bM4_TMR63_STFLR_CMSAUF (*((volatile unsigned int*)(0x42310E24UL))) +#define bM4_TMR63_STFLR_CMSADF (*((volatile unsigned int*)(0x42310E28UL))) +#define bM4_TMR63_STFLR_CMSBUF (*((volatile unsigned int*)(0x42310E2CUL))) +#define bM4_TMR63_STFLR_CMSBDF (*((volatile unsigned int*)(0x42310E30UL))) +#define bM4_TMR63_STFLR_VPERNUM0 (*((volatile unsigned int*)(0x42310E54UL))) +#define bM4_TMR63_STFLR_VPERNUM1 (*((volatile unsigned int*)(0x42310E58UL))) +#define bM4_TMR63_STFLR_VPERNUM2 (*((volatile unsigned int*)(0x42310E5CUL))) +#define bM4_TMR63_STFLR_DIRF (*((volatile unsigned int*)(0x42310E7CUL))) +#define bM4_TMR63_HSTAR_HSTA0 (*((volatile unsigned int*)(0x42310E80UL))) +#define bM4_TMR63_HSTAR_HSTA1 (*((volatile unsigned int*)(0x42310E84UL))) +#define bM4_TMR63_HSTAR_HSTA4 (*((volatile unsigned int*)(0x42310E90UL))) +#define bM4_TMR63_HSTAR_HSTA5 (*((volatile unsigned int*)(0x42310E94UL))) +#define bM4_TMR63_HSTAR_HSTA6 (*((volatile unsigned int*)(0x42310E98UL))) +#define bM4_TMR63_HSTAR_HSTA7 (*((volatile unsigned int*)(0x42310E9CUL))) +#define bM4_TMR63_HSTAR_HSTA8 (*((volatile unsigned int*)(0x42310EA0UL))) +#define bM4_TMR63_HSTAR_HSTA9 (*((volatile unsigned int*)(0x42310EA4UL))) +#define bM4_TMR63_HSTAR_HSTA10 (*((volatile unsigned int*)(0x42310EA8UL))) +#define bM4_TMR63_HSTAR_HSTA11 (*((volatile unsigned int*)(0x42310EACUL))) +#define bM4_TMR63_HSTAR_STARTS (*((volatile unsigned int*)(0x42310EFCUL))) +#define bM4_TMR63_HSTPR_HSTP0 (*((volatile unsigned int*)(0x42310F00UL))) +#define bM4_TMR63_HSTPR_HSTP1 (*((volatile unsigned int*)(0x42310F04UL))) +#define bM4_TMR63_HSTPR_HSTP4 (*((volatile unsigned int*)(0x42310F10UL))) +#define bM4_TMR63_HSTPR_HSTP5 (*((volatile unsigned int*)(0x42310F14UL))) +#define bM4_TMR63_HSTPR_HSTP6 (*((volatile unsigned int*)(0x42310F18UL))) +#define bM4_TMR63_HSTPR_HSTP7 (*((volatile unsigned int*)(0x42310F1CUL))) +#define bM4_TMR63_HSTPR_HSTP8 (*((volatile unsigned int*)(0x42310F20UL))) +#define bM4_TMR63_HSTPR_HSTP9 (*((volatile unsigned int*)(0x42310F24UL))) +#define bM4_TMR63_HSTPR_HSTP10 (*((volatile unsigned int*)(0x42310F28UL))) +#define bM4_TMR63_HSTPR_HSTP11 (*((volatile unsigned int*)(0x42310F2CUL))) +#define bM4_TMR63_HSTPR_STOPS (*((volatile unsigned int*)(0x42310F7CUL))) +#define bM4_TMR63_HCLRR_HCLE0 (*((volatile unsigned int*)(0x42310F80UL))) +#define bM4_TMR63_HCLRR_HCLE1 (*((volatile unsigned int*)(0x42310F84UL))) +#define bM4_TMR63_HCLRR_HCLE4 (*((volatile unsigned int*)(0x42310F90UL))) +#define bM4_TMR63_HCLRR_HCLE5 (*((volatile unsigned int*)(0x42310F94UL))) +#define bM4_TMR63_HCLRR_HCLE6 (*((volatile unsigned int*)(0x42310F98UL))) +#define bM4_TMR63_HCLRR_HCLE7 (*((volatile unsigned int*)(0x42310F9CUL))) +#define bM4_TMR63_HCLRR_HCLE8 (*((volatile unsigned int*)(0x42310FA0UL))) +#define bM4_TMR63_HCLRR_HCLE9 (*((volatile unsigned int*)(0x42310FA4UL))) +#define bM4_TMR63_HCLRR_HCLE10 (*((volatile unsigned int*)(0x42310FA8UL))) +#define bM4_TMR63_HCLRR_HCLE11 (*((volatile unsigned int*)(0x42310FACUL))) +#define bM4_TMR63_HCLRR_CLEARS (*((volatile unsigned int*)(0x42310FFCUL))) +#define bM4_TMR63_HCPAR_HCPA0 (*((volatile unsigned int*)(0x42311000UL))) +#define bM4_TMR63_HCPAR_HCPA1 (*((volatile unsigned int*)(0x42311004UL))) +#define bM4_TMR63_HCPAR_HCPA4 (*((volatile unsigned int*)(0x42311010UL))) +#define bM4_TMR63_HCPAR_HCPA5 (*((volatile unsigned int*)(0x42311014UL))) +#define bM4_TMR63_HCPAR_HCPA6 (*((volatile unsigned int*)(0x42311018UL))) +#define bM4_TMR63_HCPAR_HCPA7 (*((volatile unsigned int*)(0x4231101CUL))) +#define bM4_TMR63_HCPAR_HCPA8 (*((volatile unsigned int*)(0x42311020UL))) +#define bM4_TMR63_HCPAR_HCPA9 (*((volatile unsigned int*)(0x42311024UL))) +#define bM4_TMR63_HCPAR_HCPA10 (*((volatile unsigned int*)(0x42311028UL))) +#define bM4_TMR63_HCPAR_HCPA11 (*((volatile unsigned int*)(0x4231102CUL))) +#define bM4_TMR63_HCPBR_HCPB0 (*((volatile unsigned int*)(0x42311080UL))) +#define bM4_TMR63_HCPBR_HCPB1 (*((volatile unsigned int*)(0x42311084UL))) +#define bM4_TMR63_HCPBR_HCPB4 (*((volatile unsigned int*)(0x42311090UL))) +#define bM4_TMR63_HCPBR_HCPB5 (*((volatile unsigned int*)(0x42311094UL))) +#define bM4_TMR63_HCPBR_HCPB6 (*((volatile unsigned int*)(0x42311098UL))) +#define bM4_TMR63_HCPBR_HCPB7 (*((volatile unsigned int*)(0x4231109CUL))) +#define bM4_TMR63_HCPBR_HCPB8 (*((volatile unsigned int*)(0x423110A0UL))) +#define bM4_TMR63_HCPBR_HCPB9 (*((volatile unsigned int*)(0x423110A4UL))) +#define bM4_TMR63_HCPBR_HCPB10 (*((volatile unsigned int*)(0x423110A8UL))) +#define bM4_TMR63_HCPBR_HCPB11 (*((volatile unsigned int*)(0x423110ACUL))) +#define bM4_TMR63_HCUPR_HCUP0 (*((volatile unsigned int*)(0x42311100UL))) +#define bM4_TMR63_HCUPR_HCUP1 (*((volatile unsigned int*)(0x42311104UL))) +#define bM4_TMR63_HCUPR_HCUP2 (*((volatile unsigned int*)(0x42311108UL))) +#define bM4_TMR63_HCUPR_HCUP3 (*((volatile unsigned int*)(0x4231110CUL))) +#define bM4_TMR63_HCUPR_HCUP4 (*((volatile unsigned int*)(0x42311110UL))) +#define bM4_TMR63_HCUPR_HCUP5 (*((volatile unsigned int*)(0x42311114UL))) +#define bM4_TMR63_HCUPR_HCUP6 (*((volatile unsigned int*)(0x42311118UL))) +#define bM4_TMR63_HCUPR_HCUP7 (*((volatile unsigned int*)(0x4231111CUL))) +#define bM4_TMR63_HCUPR_HCUP8 (*((volatile unsigned int*)(0x42311120UL))) +#define bM4_TMR63_HCUPR_HCUP9 (*((volatile unsigned int*)(0x42311124UL))) +#define bM4_TMR63_HCUPR_HCUP10 (*((volatile unsigned int*)(0x42311128UL))) +#define bM4_TMR63_HCUPR_HCUP11 (*((volatile unsigned int*)(0x4231112CUL))) +#define bM4_TMR63_HCUPR_HCUP16 (*((volatile unsigned int*)(0x42311140UL))) +#define bM4_TMR63_HCUPR_HCUP17 (*((volatile unsigned int*)(0x42311144UL))) +#define bM4_TMR63_HCDOR_HCDO0 (*((volatile unsigned int*)(0x42311180UL))) +#define bM4_TMR63_HCDOR_HCDO1 (*((volatile unsigned int*)(0x42311184UL))) +#define bM4_TMR63_HCDOR_HCDO2 (*((volatile unsigned int*)(0x42311188UL))) +#define bM4_TMR63_HCDOR_HCDO3 (*((volatile unsigned int*)(0x4231118CUL))) +#define bM4_TMR63_HCDOR_HCDO4 (*((volatile unsigned int*)(0x42311190UL))) +#define bM4_TMR63_HCDOR_HCDO5 (*((volatile unsigned int*)(0x42311194UL))) +#define bM4_TMR63_HCDOR_HCDO6 (*((volatile unsigned int*)(0x42311198UL))) +#define bM4_TMR63_HCDOR_HCDO7 (*((volatile unsigned int*)(0x4231119CUL))) +#define bM4_TMR63_HCDOR_HCDO8 (*((volatile unsigned int*)(0x423111A0UL))) +#define bM4_TMR63_HCDOR_HCDO9 (*((volatile unsigned int*)(0x423111A4UL))) +#define bM4_TMR63_HCDOR_HCDO10 (*((volatile unsigned int*)(0x423111A8UL))) +#define bM4_TMR63_HCDOR_HCDO11 (*((volatile unsigned int*)(0x423111ACUL))) +#define bM4_TMR63_HCDOR_HCDO16 (*((volatile unsigned int*)(0x423111C0UL))) +#define bM4_TMR63_HCDOR_HCDO17 (*((volatile unsigned int*)(0x423111C4UL))) +#define bM4_TMR6_CR_SSTAR_SSTA1 (*((volatile unsigned int*)(0x42307E80UL))) +#define bM4_TMR6_CR_SSTAR_SSTA2 (*((volatile unsigned int*)(0x42307E84UL))) +#define bM4_TMR6_CR_SSTAR_SSTA3 (*((volatile unsigned int*)(0x42307E88UL))) +#define bM4_TMR6_CR_SSTAR_RESV0 (*((volatile unsigned int*)(0x42307EC0UL))) +#define bM4_TMR6_CR_SSTAR_RESV (*((volatile unsigned int*)(0x42307EE0UL))) +#define bM4_TMR6_CR_SSTPR_SSTP1 (*((volatile unsigned int*)(0x42307F00UL))) +#define bM4_TMR6_CR_SSTPR_SSTP2 (*((volatile unsigned int*)(0x42307F04UL))) +#define bM4_TMR6_CR_SSTPR_SSTP3 (*((volatile unsigned int*)(0x42307F08UL))) +#define bM4_TMR6_CR_SCLRR_SCLE1 (*((volatile unsigned int*)(0x42307F80UL))) +#define bM4_TMR6_CR_SCLRR_SCLE2 (*((volatile unsigned int*)(0x42307F84UL))) +#define bM4_TMR6_CR_SCLRR_SCLE3 (*((volatile unsigned int*)(0x42307F88UL))) +#define bM4_TMRA1_CNTER_CNT0 (*((volatile unsigned int*)(0x422A0000UL))) +#define bM4_TMRA1_CNTER_CNT1 (*((volatile unsigned int*)(0x422A0004UL))) +#define bM4_TMRA1_CNTER_CNT2 (*((volatile unsigned int*)(0x422A0008UL))) +#define bM4_TMRA1_CNTER_CNT3 (*((volatile unsigned int*)(0x422A000CUL))) +#define bM4_TMRA1_CNTER_CNT4 (*((volatile unsigned int*)(0x422A0010UL))) +#define bM4_TMRA1_CNTER_CNT5 (*((volatile unsigned int*)(0x422A0014UL))) +#define bM4_TMRA1_CNTER_CNT6 (*((volatile unsigned int*)(0x422A0018UL))) +#define bM4_TMRA1_CNTER_CNT7 (*((volatile unsigned int*)(0x422A001CUL))) +#define bM4_TMRA1_CNTER_CNT8 (*((volatile unsigned int*)(0x422A0020UL))) +#define bM4_TMRA1_CNTER_CNT9 (*((volatile unsigned int*)(0x422A0024UL))) +#define bM4_TMRA1_CNTER_CNT10 (*((volatile unsigned int*)(0x422A0028UL))) +#define bM4_TMRA1_CNTER_CNT11 (*((volatile unsigned int*)(0x422A002CUL))) +#define bM4_TMRA1_CNTER_CNT12 (*((volatile unsigned int*)(0x422A0030UL))) +#define bM4_TMRA1_CNTER_CNT13 (*((volatile unsigned int*)(0x422A0034UL))) +#define bM4_TMRA1_CNTER_CNT14 (*((volatile unsigned int*)(0x422A0038UL))) +#define bM4_TMRA1_CNTER_CNT15 (*((volatile unsigned int*)(0x422A003CUL))) +#define bM4_TMRA1_PERAR_PER0 (*((volatile unsigned int*)(0x422A0080UL))) +#define bM4_TMRA1_PERAR_PER1 (*((volatile unsigned int*)(0x422A0084UL))) +#define bM4_TMRA1_PERAR_PER2 (*((volatile unsigned int*)(0x422A0088UL))) +#define bM4_TMRA1_PERAR_PER3 (*((volatile unsigned int*)(0x422A008CUL))) +#define bM4_TMRA1_PERAR_PER4 (*((volatile unsigned int*)(0x422A0090UL))) +#define bM4_TMRA1_PERAR_PER5 (*((volatile unsigned int*)(0x422A0094UL))) +#define bM4_TMRA1_PERAR_PER6 (*((volatile unsigned int*)(0x422A0098UL))) +#define bM4_TMRA1_PERAR_PER7 (*((volatile unsigned int*)(0x422A009CUL))) +#define bM4_TMRA1_PERAR_PER8 (*((volatile unsigned int*)(0x422A00A0UL))) +#define bM4_TMRA1_PERAR_PER9 (*((volatile unsigned int*)(0x422A00A4UL))) +#define bM4_TMRA1_PERAR_PER10 (*((volatile unsigned int*)(0x422A00A8UL))) +#define bM4_TMRA1_PERAR_PER11 (*((volatile unsigned int*)(0x422A00ACUL))) +#define bM4_TMRA1_PERAR_PER12 (*((volatile unsigned int*)(0x422A00B0UL))) +#define bM4_TMRA1_PERAR_PER13 (*((volatile unsigned int*)(0x422A00B4UL))) +#define bM4_TMRA1_PERAR_PER14 (*((volatile unsigned int*)(0x422A00B8UL))) +#define bM4_TMRA1_PERAR_PER15 (*((volatile unsigned int*)(0x422A00BCUL))) +#define bM4_TMRA1_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422A0800UL))) +#define bM4_TMRA1_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422A0804UL))) +#define bM4_TMRA1_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422A0808UL))) +#define bM4_TMRA1_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422A080CUL))) +#define bM4_TMRA1_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422A0810UL))) +#define bM4_TMRA1_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422A0814UL))) +#define bM4_TMRA1_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422A0818UL))) +#define bM4_TMRA1_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422A081CUL))) +#define bM4_TMRA1_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422A0820UL))) +#define bM4_TMRA1_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422A0824UL))) +#define bM4_TMRA1_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422A0828UL))) +#define bM4_TMRA1_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422A082CUL))) +#define bM4_TMRA1_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422A0830UL))) +#define bM4_TMRA1_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422A0834UL))) +#define bM4_TMRA1_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422A0838UL))) +#define bM4_TMRA1_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422A083CUL))) +#define bM4_TMRA1_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422A0880UL))) +#define bM4_TMRA1_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422A0884UL))) +#define bM4_TMRA1_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422A0888UL))) +#define bM4_TMRA1_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422A088CUL))) +#define bM4_TMRA1_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422A0890UL))) +#define bM4_TMRA1_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422A0894UL))) +#define bM4_TMRA1_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422A0898UL))) +#define bM4_TMRA1_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422A089CUL))) +#define bM4_TMRA1_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422A08A0UL))) +#define bM4_TMRA1_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422A08A4UL))) +#define bM4_TMRA1_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422A08A8UL))) +#define bM4_TMRA1_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422A08ACUL))) +#define bM4_TMRA1_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422A08B0UL))) +#define bM4_TMRA1_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422A08B4UL))) +#define bM4_TMRA1_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422A08B8UL))) +#define bM4_TMRA1_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422A08BCUL))) +#define bM4_TMRA1_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422A0900UL))) +#define bM4_TMRA1_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422A0904UL))) +#define bM4_TMRA1_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422A0908UL))) +#define bM4_TMRA1_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422A090CUL))) +#define bM4_TMRA1_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422A0910UL))) +#define bM4_TMRA1_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422A0914UL))) +#define bM4_TMRA1_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422A0918UL))) +#define bM4_TMRA1_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422A091CUL))) +#define bM4_TMRA1_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422A0920UL))) +#define bM4_TMRA1_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422A0924UL))) +#define bM4_TMRA1_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422A0928UL))) +#define bM4_TMRA1_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422A092CUL))) +#define bM4_TMRA1_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422A0930UL))) +#define bM4_TMRA1_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422A0934UL))) +#define bM4_TMRA1_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422A0938UL))) +#define bM4_TMRA1_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422A093CUL))) +#define bM4_TMRA1_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422A0980UL))) +#define bM4_TMRA1_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422A0984UL))) +#define bM4_TMRA1_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422A0988UL))) +#define bM4_TMRA1_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422A098CUL))) +#define bM4_TMRA1_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422A0990UL))) +#define bM4_TMRA1_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422A0994UL))) +#define bM4_TMRA1_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422A0998UL))) +#define bM4_TMRA1_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422A099CUL))) +#define bM4_TMRA1_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422A09A0UL))) +#define bM4_TMRA1_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422A09A4UL))) +#define bM4_TMRA1_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422A09A8UL))) +#define bM4_TMRA1_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422A09ACUL))) +#define bM4_TMRA1_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422A09B0UL))) +#define bM4_TMRA1_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422A09B4UL))) +#define bM4_TMRA1_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422A09B8UL))) +#define bM4_TMRA1_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422A09BCUL))) +#define bM4_TMRA1_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422A0A00UL))) +#define bM4_TMRA1_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422A0A04UL))) +#define bM4_TMRA1_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422A0A08UL))) +#define bM4_TMRA1_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422A0A0CUL))) +#define bM4_TMRA1_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422A0A10UL))) +#define bM4_TMRA1_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422A0A14UL))) +#define bM4_TMRA1_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422A0A18UL))) +#define bM4_TMRA1_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422A0A1CUL))) +#define bM4_TMRA1_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422A0A20UL))) +#define bM4_TMRA1_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422A0A24UL))) +#define bM4_TMRA1_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422A0A28UL))) +#define bM4_TMRA1_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422A0A2CUL))) +#define bM4_TMRA1_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422A0A30UL))) +#define bM4_TMRA1_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422A0A34UL))) +#define bM4_TMRA1_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422A0A38UL))) +#define bM4_TMRA1_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422A0A3CUL))) +#define bM4_TMRA1_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422A0A80UL))) +#define bM4_TMRA1_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422A0A84UL))) +#define bM4_TMRA1_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422A0A88UL))) +#define bM4_TMRA1_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422A0A8CUL))) +#define bM4_TMRA1_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422A0A90UL))) +#define bM4_TMRA1_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422A0A94UL))) +#define bM4_TMRA1_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422A0A98UL))) +#define bM4_TMRA1_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422A0A9CUL))) +#define bM4_TMRA1_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422A0AA0UL))) +#define bM4_TMRA1_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422A0AA4UL))) +#define bM4_TMRA1_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422A0AA8UL))) +#define bM4_TMRA1_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422A0AACUL))) +#define bM4_TMRA1_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422A0AB0UL))) +#define bM4_TMRA1_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422A0AB4UL))) +#define bM4_TMRA1_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422A0AB8UL))) +#define bM4_TMRA1_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422A0ABCUL))) +#define bM4_TMRA1_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422A0B00UL))) +#define bM4_TMRA1_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422A0B04UL))) +#define bM4_TMRA1_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422A0B08UL))) +#define bM4_TMRA1_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422A0B0CUL))) +#define bM4_TMRA1_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422A0B10UL))) +#define bM4_TMRA1_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422A0B14UL))) +#define bM4_TMRA1_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422A0B18UL))) +#define bM4_TMRA1_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422A0B1CUL))) +#define bM4_TMRA1_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422A0B20UL))) +#define bM4_TMRA1_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422A0B24UL))) +#define bM4_TMRA1_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422A0B28UL))) +#define bM4_TMRA1_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422A0B2CUL))) +#define bM4_TMRA1_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422A0B30UL))) +#define bM4_TMRA1_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422A0B34UL))) +#define bM4_TMRA1_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422A0B38UL))) +#define bM4_TMRA1_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422A0B3CUL))) +#define bM4_TMRA1_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422A0B80UL))) +#define bM4_TMRA1_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422A0B84UL))) +#define bM4_TMRA1_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422A0B88UL))) +#define bM4_TMRA1_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422A0B8CUL))) +#define bM4_TMRA1_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422A0B90UL))) +#define bM4_TMRA1_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422A0B94UL))) +#define bM4_TMRA1_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422A0B98UL))) +#define bM4_TMRA1_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422A0B9CUL))) +#define bM4_TMRA1_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422A0BA0UL))) +#define bM4_TMRA1_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422A0BA4UL))) +#define bM4_TMRA1_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422A0BA8UL))) +#define bM4_TMRA1_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422A0BACUL))) +#define bM4_TMRA1_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422A0BB0UL))) +#define bM4_TMRA1_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422A0BB4UL))) +#define bM4_TMRA1_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422A0BB8UL))) +#define bM4_TMRA1_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422A0BBCUL))) +#define bM4_TMRA1_BCSTR_START (*((volatile unsigned int*)(0x422A1000UL))) +#define bM4_TMRA1_BCSTR_DIR (*((volatile unsigned int*)(0x422A1004UL))) +#define bM4_TMRA1_BCSTR_MODE (*((volatile unsigned int*)(0x422A1008UL))) +#define bM4_TMRA1_BCSTR_SYNST (*((volatile unsigned int*)(0x422A100CUL))) +#define bM4_TMRA1_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422A1010UL))) +#define bM4_TMRA1_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422A1014UL))) +#define bM4_TMRA1_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422A1018UL))) +#define bM4_TMRA1_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422A101CUL))) +#define bM4_TMRA1_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422A1030UL))) +#define bM4_TMRA1_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422A1034UL))) +#define bM4_TMRA1_BCSTR_OVFF (*((volatile unsigned int*)(0x422A1038UL))) +#define bM4_TMRA1_BCSTR_UDFF (*((volatile unsigned int*)(0x422A103CUL))) +#define bM4_TMRA1_HCONR_HSTA0 (*((volatile unsigned int*)(0x422A1080UL))) +#define bM4_TMRA1_HCONR_HSTA1 (*((volatile unsigned int*)(0x422A1084UL))) +#define bM4_TMRA1_HCONR_HSTA2 (*((volatile unsigned int*)(0x422A1088UL))) +#define bM4_TMRA1_HCONR_HSTP0 (*((volatile unsigned int*)(0x422A1090UL))) +#define bM4_TMRA1_HCONR_HSTP1 (*((volatile unsigned int*)(0x422A1094UL))) +#define bM4_TMRA1_HCONR_HSTP2 (*((volatile unsigned int*)(0x422A1098UL))) +#define bM4_TMRA1_HCONR_HCLE0 (*((volatile unsigned int*)(0x422A10A0UL))) +#define bM4_TMRA1_HCONR_HCLE1 (*((volatile unsigned int*)(0x422A10A4UL))) +#define bM4_TMRA1_HCONR_HCLE2 (*((volatile unsigned int*)(0x422A10A8UL))) +#define bM4_TMRA1_HCONR_HCLE3 (*((volatile unsigned int*)(0x422A10B0UL))) +#define bM4_TMRA1_HCONR_HCLE4 (*((volatile unsigned int*)(0x422A10B4UL))) +#define bM4_TMRA1_HCONR_HCLE5 (*((volatile unsigned int*)(0x422A10B8UL))) +#define bM4_TMRA1_HCONR_HCLE6 (*((volatile unsigned int*)(0x422A10BCUL))) +#define bM4_TMRA1_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422A1100UL))) +#define bM4_TMRA1_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422A1104UL))) +#define bM4_TMRA1_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422A1108UL))) +#define bM4_TMRA1_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422A110CUL))) +#define bM4_TMRA1_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422A1110UL))) +#define bM4_TMRA1_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422A1114UL))) +#define bM4_TMRA1_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422A1118UL))) +#define bM4_TMRA1_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422A111CUL))) +#define bM4_TMRA1_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422A1120UL))) +#define bM4_TMRA1_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422A1124UL))) +#define bM4_TMRA1_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422A1128UL))) +#define bM4_TMRA1_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422A112CUL))) +#define bM4_TMRA1_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422A1130UL))) +#define bM4_TMRA1_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422A1180UL))) +#define bM4_TMRA1_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422A1184UL))) +#define bM4_TMRA1_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422A1188UL))) +#define bM4_TMRA1_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422A118CUL))) +#define bM4_TMRA1_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422A1190UL))) +#define bM4_TMRA1_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422A1194UL))) +#define bM4_TMRA1_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422A1198UL))) +#define bM4_TMRA1_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422A119CUL))) +#define bM4_TMRA1_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422A11A0UL))) +#define bM4_TMRA1_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422A11A4UL))) +#define bM4_TMRA1_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422A11A8UL))) +#define bM4_TMRA1_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422A11ACUL))) +#define bM4_TMRA1_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422A11B0UL))) +#define bM4_TMRA1_ICONR_ITEN1 (*((volatile unsigned int*)(0x422A1200UL))) +#define bM4_TMRA1_ICONR_ITEN2 (*((volatile unsigned int*)(0x422A1204UL))) +#define bM4_TMRA1_ICONR_ITEN3 (*((volatile unsigned int*)(0x422A1208UL))) +#define bM4_TMRA1_ICONR_ITEN4 (*((volatile unsigned int*)(0x422A120CUL))) +#define bM4_TMRA1_ICONR_ITEN5 (*((volatile unsigned int*)(0x422A1210UL))) +#define bM4_TMRA1_ICONR_ITEN6 (*((volatile unsigned int*)(0x422A1214UL))) +#define bM4_TMRA1_ICONR_ITEN7 (*((volatile unsigned int*)(0x422A1218UL))) +#define bM4_TMRA1_ICONR_ITEN8 (*((volatile unsigned int*)(0x422A121CUL))) +#define bM4_TMRA1_ECONR_ETEN1 (*((volatile unsigned int*)(0x422A1280UL))) +#define bM4_TMRA1_ECONR_ETEN2 (*((volatile unsigned int*)(0x422A1284UL))) +#define bM4_TMRA1_ECONR_ETEN3 (*((volatile unsigned int*)(0x422A1288UL))) +#define bM4_TMRA1_ECONR_ETEN4 (*((volatile unsigned int*)(0x422A128CUL))) +#define bM4_TMRA1_ECONR_ETEN5 (*((volatile unsigned int*)(0x422A1290UL))) +#define bM4_TMRA1_ECONR_ETEN6 (*((volatile unsigned int*)(0x422A1294UL))) +#define bM4_TMRA1_ECONR_ETEN7 (*((volatile unsigned int*)(0x422A1298UL))) +#define bM4_TMRA1_ECONR_ETEN8 (*((volatile unsigned int*)(0x422A129CUL))) +#define bM4_TMRA1_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422A1300UL))) +#define bM4_TMRA1_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422A1304UL))) +#define bM4_TMRA1_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422A1308UL))) +#define bM4_TMRA1_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422A1320UL))) +#define bM4_TMRA1_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422A1324UL))) +#define bM4_TMRA1_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422A1328UL))) +#define bM4_TMRA1_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422A1330UL))) +#define bM4_TMRA1_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422A1334UL))) +#define bM4_TMRA1_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422A1338UL))) +#define bM4_TMRA1_STFLR_CMPF1 (*((volatile unsigned int*)(0x422A1380UL))) +#define bM4_TMRA1_STFLR_CMPF2 (*((volatile unsigned int*)(0x422A1384UL))) +#define bM4_TMRA1_STFLR_CMPF3 (*((volatile unsigned int*)(0x422A1388UL))) +#define bM4_TMRA1_STFLR_CMPF4 (*((volatile unsigned int*)(0x422A138CUL))) +#define bM4_TMRA1_STFLR_CMPF5 (*((volatile unsigned int*)(0x422A1390UL))) +#define bM4_TMRA1_STFLR_CMPF6 (*((volatile unsigned int*)(0x422A1394UL))) +#define bM4_TMRA1_STFLR_CMPF7 (*((volatile unsigned int*)(0x422A1398UL))) +#define bM4_TMRA1_STFLR_CMPF8 (*((volatile unsigned int*)(0x422A139CUL))) +#define bM4_TMRA1_BCONR1_BEN (*((volatile unsigned int*)(0x422A1800UL))) +#define bM4_TMRA1_BCONR1_BSE0 (*((volatile unsigned int*)(0x422A1804UL))) +#define bM4_TMRA1_BCONR1_BSE1 (*((volatile unsigned int*)(0x422A1808UL))) +#define bM4_TMRA1_BCONR2_BEN (*((volatile unsigned int*)(0x422A1900UL))) +#define bM4_TMRA1_BCONR2_BSE0 (*((volatile unsigned int*)(0x422A1904UL))) +#define bM4_TMRA1_BCONR2_BSE1 (*((volatile unsigned int*)(0x422A1908UL))) +#define bM4_TMRA1_BCONR3_BEN (*((volatile unsigned int*)(0x422A1A00UL))) +#define bM4_TMRA1_BCONR3_BSE0 (*((volatile unsigned int*)(0x422A1A04UL))) +#define bM4_TMRA1_BCONR3_BSE1 (*((volatile unsigned int*)(0x422A1A08UL))) +#define bM4_TMRA1_BCONR4_BEN (*((volatile unsigned int*)(0x422A1B00UL))) +#define bM4_TMRA1_BCONR4_BSE0 (*((volatile unsigned int*)(0x422A1B04UL))) +#define bM4_TMRA1_BCONR4_BSE1 (*((volatile unsigned int*)(0x422A1B08UL))) +#define bM4_TMRA1_CCONR1_CAPMD (*((volatile unsigned int*)(0x422A2000UL))) +#define bM4_TMRA1_CCONR1_HICP0 (*((volatile unsigned int*)(0x422A2010UL))) +#define bM4_TMRA1_CCONR1_HICP1 (*((volatile unsigned int*)(0x422A2014UL))) +#define bM4_TMRA1_CCONR1_HICP2 (*((volatile unsigned int*)(0x422A2018UL))) +#define bM4_TMRA1_CCONR1_HICP3 (*((volatile unsigned int*)(0x422A2020UL))) +#define bM4_TMRA1_CCONR1_HICP4 (*((volatile unsigned int*)(0x422A2024UL))) +#define bM4_TMRA1_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422A2030UL))) +#define bM4_TMRA1_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422A2034UL))) +#define bM4_TMRA1_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422A2038UL))) +#define bM4_TMRA1_CCONR2_CAPMD (*((volatile unsigned int*)(0x422A2080UL))) +#define bM4_TMRA1_CCONR2_HICP0 (*((volatile unsigned int*)(0x422A2090UL))) +#define bM4_TMRA1_CCONR2_HICP1 (*((volatile unsigned int*)(0x422A2094UL))) +#define bM4_TMRA1_CCONR2_HICP2 (*((volatile unsigned int*)(0x422A2098UL))) +#define bM4_TMRA1_CCONR2_HICP3 (*((volatile unsigned int*)(0x422A20A0UL))) +#define bM4_TMRA1_CCONR2_HICP4 (*((volatile unsigned int*)(0x422A20A4UL))) +#define bM4_TMRA1_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422A20B0UL))) +#define bM4_TMRA1_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422A20B4UL))) +#define bM4_TMRA1_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422A20B8UL))) +#define bM4_TMRA1_CCONR3_CAPMD (*((volatile unsigned int*)(0x422A2100UL))) +#define bM4_TMRA1_CCONR3_HICP0 (*((volatile unsigned int*)(0x422A2110UL))) +#define bM4_TMRA1_CCONR3_HICP1 (*((volatile unsigned int*)(0x422A2114UL))) +#define bM4_TMRA1_CCONR3_HICP2 (*((volatile unsigned int*)(0x422A2118UL))) +#define bM4_TMRA1_CCONR3_HICP3 (*((volatile unsigned int*)(0x422A2120UL))) +#define bM4_TMRA1_CCONR3_HICP4 (*((volatile unsigned int*)(0x422A2124UL))) +#define bM4_TMRA1_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422A2130UL))) +#define bM4_TMRA1_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422A2134UL))) +#define bM4_TMRA1_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422A2138UL))) +#define bM4_TMRA1_CCONR4_CAPMD (*((volatile unsigned int*)(0x422A2180UL))) +#define bM4_TMRA1_CCONR4_HICP0 (*((volatile unsigned int*)(0x422A2190UL))) +#define bM4_TMRA1_CCONR4_HICP1 (*((volatile unsigned int*)(0x422A2194UL))) +#define bM4_TMRA1_CCONR4_HICP2 (*((volatile unsigned int*)(0x422A2198UL))) +#define bM4_TMRA1_CCONR4_HICP3 (*((volatile unsigned int*)(0x422A21A0UL))) +#define bM4_TMRA1_CCONR4_HICP4 (*((volatile unsigned int*)(0x422A21A4UL))) +#define bM4_TMRA1_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422A21B0UL))) +#define bM4_TMRA1_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422A21B4UL))) +#define bM4_TMRA1_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422A21B8UL))) +#define bM4_TMRA1_CCONR5_CAPMD (*((volatile unsigned int*)(0x422A2200UL))) +#define bM4_TMRA1_CCONR5_HICP0 (*((volatile unsigned int*)(0x422A2210UL))) +#define bM4_TMRA1_CCONR5_HICP1 (*((volatile unsigned int*)(0x422A2214UL))) +#define bM4_TMRA1_CCONR5_HICP2 (*((volatile unsigned int*)(0x422A2218UL))) +#define bM4_TMRA1_CCONR5_HICP3 (*((volatile unsigned int*)(0x422A2220UL))) +#define bM4_TMRA1_CCONR5_HICP4 (*((volatile unsigned int*)(0x422A2224UL))) +#define bM4_TMRA1_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422A2230UL))) +#define bM4_TMRA1_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422A2234UL))) +#define bM4_TMRA1_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422A2238UL))) +#define bM4_TMRA1_CCONR6_CAPMD (*((volatile unsigned int*)(0x422A2280UL))) +#define bM4_TMRA1_CCONR6_HICP0 (*((volatile unsigned int*)(0x422A2290UL))) +#define bM4_TMRA1_CCONR6_HICP1 (*((volatile unsigned int*)(0x422A2294UL))) +#define bM4_TMRA1_CCONR6_HICP2 (*((volatile unsigned int*)(0x422A2298UL))) +#define bM4_TMRA1_CCONR6_HICP3 (*((volatile unsigned int*)(0x422A22A0UL))) +#define bM4_TMRA1_CCONR6_HICP4 (*((volatile unsigned int*)(0x422A22A4UL))) +#define bM4_TMRA1_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422A22B0UL))) +#define bM4_TMRA1_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422A22B4UL))) +#define bM4_TMRA1_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422A22B8UL))) +#define bM4_TMRA1_CCONR7_CAPMD (*((volatile unsigned int*)(0x422A2300UL))) +#define bM4_TMRA1_CCONR7_HICP0 (*((volatile unsigned int*)(0x422A2310UL))) +#define bM4_TMRA1_CCONR7_HICP1 (*((volatile unsigned int*)(0x422A2314UL))) +#define bM4_TMRA1_CCONR7_HICP2 (*((volatile unsigned int*)(0x422A2318UL))) +#define bM4_TMRA1_CCONR7_HICP3 (*((volatile unsigned int*)(0x422A2320UL))) +#define bM4_TMRA1_CCONR7_HICP4 (*((volatile unsigned int*)(0x422A2324UL))) +#define bM4_TMRA1_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422A2330UL))) +#define bM4_TMRA1_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422A2334UL))) +#define bM4_TMRA1_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422A2338UL))) +#define bM4_TMRA1_CCONR8_CAPMD (*((volatile unsigned int*)(0x422A2380UL))) +#define bM4_TMRA1_CCONR8_HICP0 (*((volatile unsigned int*)(0x422A2390UL))) +#define bM4_TMRA1_CCONR8_HICP1 (*((volatile unsigned int*)(0x422A2394UL))) +#define bM4_TMRA1_CCONR8_HICP2 (*((volatile unsigned int*)(0x422A2398UL))) +#define bM4_TMRA1_CCONR8_HICP3 (*((volatile unsigned int*)(0x422A23A0UL))) +#define bM4_TMRA1_CCONR8_HICP4 (*((volatile unsigned int*)(0x422A23A4UL))) +#define bM4_TMRA1_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422A23B0UL))) +#define bM4_TMRA1_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422A23B4UL))) +#define bM4_TMRA1_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422A23B8UL))) +#define bM4_TMRA1_PCONR1_STAC0 (*((volatile unsigned int*)(0x422A2800UL))) +#define bM4_TMRA1_PCONR1_STAC1 (*((volatile unsigned int*)(0x422A2804UL))) +#define bM4_TMRA1_PCONR1_STPC0 (*((volatile unsigned int*)(0x422A2808UL))) +#define bM4_TMRA1_PCONR1_STPC1 (*((volatile unsigned int*)(0x422A280CUL))) +#define bM4_TMRA1_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422A2810UL))) +#define bM4_TMRA1_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422A2814UL))) +#define bM4_TMRA1_PCONR1_PERC0 (*((volatile unsigned int*)(0x422A2818UL))) +#define bM4_TMRA1_PCONR1_PERC1 (*((volatile unsigned int*)(0x422A281CUL))) +#define bM4_TMRA1_PCONR1_FORC0 (*((volatile unsigned int*)(0x422A2820UL))) +#define bM4_TMRA1_PCONR1_FORC1 (*((volatile unsigned int*)(0x422A2824UL))) +#define bM4_TMRA1_PCONR1_OUTEN (*((volatile unsigned int*)(0x422A2830UL))) +#define bM4_TMRA1_PCONR2_STAC0 (*((volatile unsigned int*)(0x422A2880UL))) +#define bM4_TMRA1_PCONR2_STAC1 (*((volatile unsigned int*)(0x422A2884UL))) +#define bM4_TMRA1_PCONR2_STPC0 (*((volatile unsigned int*)(0x422A2888UL))) +#define bM4_TMRA1_PCONR2_STPC1 (*((volatile unsigned int*)(0x422A288CUL))) +#define bM4_TMRA1_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422A2890UL))) +#define bM4_TMRA1_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422A2894UL))) +#define bM4_TMRA1_PCONR2_PERC0 (*((volatile unsigned int*)(0x422A2898UL))) +#define bM4_TMRA1_PCONR2_PERC1 (*((volatile unsigned int*)(0x422A289CUL))) +#define bM4_TMRA1_PCONR2_FORC0 (*((volatile unsigned int*)(0x422A28A0UL))) +#define bM4_TMRA1_PCONR2_FORC1 (*((volatile unsigned int*)(0x422A28A4UL))) +#define bM4_TMRA1_PCONR2_OUTEN (*((volatile unsigned int*)(0x422A28B0UL))) +#define bM4_TMRA1_PCONR3_STAC0 (*((volatile unsigned int*)(0x422A2900UL))) +#define bM4_TMRA1_PCONR3_STAC1 (*((volatile unsigned int*)(0x422A2904UL))) +#define bM4_TMRA1_PCONR3_STPC0 (*((volatile unsigned int*)(0x422A2908UL))) +#define bM4_TMRA1_PCONR3_STPC1 (*((volatile unsigned int*)(0x422A290CUL))) +#define bM4_TMRA1_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422A2910UL))) +#define bM4_TMRA1_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422A2914UL))) +#define bM4_TMRA1_PCONR3_PERC0 (*((volatile unsigned int*)(0x422A2918UL))) +#define bM4_TMRA1_PCONR3_PERC1 (*((volatile unsigned int*)(0x422A291CUL))) +#define bM4_TMRA1_PCONR3_FORC0 (*((volatile unsigned int*)(0x422A2920UL))) +#define bM4_TMRA1_PCONR3_FORC1 (*((volatile unsigned int*)(0x422A2924UL))) +#define bM4_TMRA1_PCONR3_OUTEN (*((volatile unsigned int*)(0x422A2930UL))) +#define bM4_TMRA1_PCONR4_STAC0 (*((volatile unsigned int*)(0x422A2980UL))) +#define bM4_TMRA1_PCONR4_STAC1 (*((volatile unsigned int*)(0x422A2984UL))) +#define bM4_TMRA1_PCONR4_STPC0 (*((volatile unsigned int*)(0x422A2988UL))) +#define bM4_TMRA1_PCONR4_STPC1 (*((volatile unsigned int*)(0x422A298CUL))) +#define bM4_TMRA1_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422A2990UL))) +#define bM4_TMRA1_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422A2994UL))) +#define bM4_TMRA1_PCONR4_PERC0 (*((volatile unsigned int*)(0x422A2998UL))) +#define bM4_TMRA1_PCONR4_PERC1 (*((volatile unsigned int*)(0x422A299CUL))) +#define bM4_TMRA1_PCONR4_FORC0 (*((volatile unsigned int*)(0x422A29A0UL))) +#define bM4_TMRA1_PCONR4_FORC1 (*((volatile unsigned int*)(0x422A29A4UL))) +#define bM4_TMRA1_PCONR4_OUTEN (*((volatile unsigned int*)(0x422A29B0UL))) +#define bM4_TMRA1_PCONR5_STAC0 (*((volatile unsigned int*)(0x422A2A00UL))) +#define bM4_TMRA1_PCONR5_STAC1 (*((volatile unsigned int*)(0x422A2A04UL))) +#define bM4_TMRA1_PCONR5_STPC0 (*((volatile unsigned int*)(0x422A2A08UL))) +#define bM4_TMRA1_PCONR5_STPC1 (*((volatile unsigned int*)(0x422A2A0CUL))) +#define bM4_TMRA1_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422A2A10UL))) +#define bM4_TMRA1_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422A2A14UL))) +#define bM4_TMRA1_PCONR5_PERC0 (*((volatile unsigned int*)(0x422A2A18UL))) +#define bM4_TMRA1_PCONR5_PERC1 (*((volatile unsigned int*)(0x422A2A1CUL))) +#define bM4_TMRA1_PCONR5_FORC0 (*((volatile unsigned int*)(0x422A2A20UL))) +#define bM4_TMRA1_PCONR5_FORC1 (*((volatile unsigned int*)(0x422A2A24UL))) +#define bM4_TMRA1_PCONR5_OUTEN (*((volatile unsigned int*)(0x422A2A30UL))) +#define bM4_TMRA1_PCONR6_STAC0 (*((volatile unsigned int*)(0x422A2A80UL))) +#define bM4_TMRA1_PCONR6_STAC1 (*((volatile unsigned int*)(0x422A2A84UL))) +#define bM4_TMRA1_PCONR6_STPC0 (*((volatile unsigned int*)(0x422A2A88UL))) +#define bM4_TMRA1_PCONR6_STPC1 (*((volatile unsigned int*)(0x422A2A8CUL))) +#define bM4_TMRA1_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422A2A90UL))) +#define bM4_TMRA1_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422A2A94UL))) +#define bM4_TMRA1_PCONR6_PERC0 (*((volatile unsigned int*)(0x422A2A98UL))) +#define bM4_TMRA1_PCONR6_PERC1 (*((volatile unsigned int*)(0x422A2A9CUL))) +#define bM4_TMRA1_PCONR6_FORC0 (*((volatile unsigned int*)(0x422A2AA0UL))) +#define bM4_TMRA1_PCONR6_FORC1 (*((volatile unsigned int*)(0x422A2AA4UL))) +#define bM4_TMRA1_PCONR6_OUTEN (*((volatile unsigned int*)(0x422A2AB0UL))) +#define bM4_TMRA1_PCONR7_STAC0 (*((volatile unsigned int*)(0x422A2B00UL))) +#define bM4_TMRA1_PCONR7_STAC1 (*((volatile unsigned int*)(0x422A2B04UL))) +#define bM4_TMRA1_PCONR7_STPC0 (*((volatile unsigned int*)(0x422A2B08UL))) +#define bM4_TMRA1_PCONR7_STPC1 (*((volatile unsigned int*)(0x422A2B0CUL))) +#define bM4_TMRA1_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422A2B10UL))) +#define bM4_TMRA1_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422A2B14UL))) +#define bM4_TMRA1_PCONR7_PERC0 (*((volatile unsigned int*)(0x422A2B18UL))) +#define bM4_TMRA1_PCONR7_PERC1 (*((volatile unsigned int*)(0x422A2B1CUL))) +#define bM4_TMRA1_PCONR7_FORC0 (*((volatile unsigned int*)(0x422A2B20UL))) +#define bM4_TMRA1_PCONR7_FORC1 (*((volatile unsigned int*)(0x422A2B24UL))) +#define bM4_TMRA1_PCONR7_OUTEN (*((volatile unsigned int*)(0x422A2B30UL))) +#define bM4_TMRA1_PCONR8_STAC0 (*((volatile unsigned int*)(0x422A2B80UL))) +#define bM4_TMRA1_PCONR8_STAC1 (*((volatile unsigned int*)(0x422A2B84UL))) +#define bM4_TMRA1_PCONR8_STPC0 (*((volatile unsigned int*)(0x422A2B88UL))) +#define bM4_TMRA1_PCONR8_STPC1 (*((volatile unsigned int*)(0x422A2B8CUL))) +#define bM4_TMRA1_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422A2B90UL))) +#define bM4_TMRA1_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422A2B94UL))) +#define bM4_TMRA1_PCONR8_PERC0 (*((volatile unsigned int*)(0x422A2B98UL))) +#define bM4_TMRA1_PCONR8_PERC1 (*((volatile unsigned int*)(0x422A2B9CUL))) +#define bM4_TMRA1_PCONR8_FORC0 (*((volatile unsigned int*)(0x422A2BA0UL))) +#define bM4_TMRA1_PCONR8_FORC1 (*((volatile unsigned int*)(0x422A2BA4UL))) +#define bM4_TMRA1_PCONR8_OUTEN (*((volatile unsigned int*)(0x422A2BB0UL))) +#define bM4_TMRA2_CNTER_CNT0 (*((volatile unsigned int*)(0x422A8000UL))) +#define bM4_TMRA2_CNTER_CNT1 (*((volatile unsigned int*)(0x422A8004UL))) +#define bM4_TMRA2_CNTER_CNT2 (*((volatile unsigned int*)(0x422A8008UL))) +#define bM4_TMRA2_CNTER_CNT3 (*((volatile unsigned int*)(0x422A800CUL))) +#define bM4_TMRA2_CNTER_CNT4 (*((volatile unsigned int*)(0x422A8010UL))) +#define bM4_TMRA2_CNTER_CNT5 (*((volatile unsigned int*)(0x422A8014UL))) +#define bM4_TMRA2_CNTER_CNT6 (*((volatile unsigned int*)(0x422A8018UL))) +#define bM4_TMRA2_CNTER_CNT7 (*((volatile unsigned int*)(0x422A801CUL))) +#define bM4_TMRA2_CNTER_CNT8 (*((volatile unsigned int*)(0x422A8020UL))) +#define bM4_TMRA2_CNTER_CNT9 (*((volatile unsigned int*)(0x422A8024UL))) +#define bM4_TMRA2_CNTER_CNT10 (*((volatile unsigned int*)(0x422A8028UL))) +#define bM4_TMRA2_CNTER_CNT11 (*((volatile unsigned int*)(0x422A802CUL))) +#define bM4_TMRA2_CNTER_CNT12 (*((volatile unsigned int*)(0x422A8030UL))) +#define bM4_TMRA2_CNTER_CNT13 (*((volatile unsigned int*)(0x422A8034UL))) +#define bM4_TMRA2_CNTER_CNT14 (*((volatile unsigned int*)(0x422A8038UL))) +#define bM4_TMRA2_CNTER_CNT15 (*((volatile unsigned int*)(0x422A803CUL))) +#define bM4_TMRA2_PERAR_PER0 (*((volatile unsigned int*)(0x422A8080UL))) +#define bM4_TMRA2_PERAR_PER1 (*((volatile unsigned int*)(0x422A8084UL))) +#define bM4_TMRA2_PERAR_PER2 (*((volatile unsigned int*)(0x422A8088UL))) +#define bM4_TMRA2_PERAR_PER3 (*((volatile unsigned int*)(0x422A808CUL))) +#define bM4_TMRA2_PERAR_PER4 (*((volatile unsigned int*)(0x422A8090UL))) +#define bM4_TMRA2_PERAR_PER5 (*((volatile unsigned int*)(0x422A8094UL))) +#define bM4_TMRA2_PERAR_PER6 (*((volatile unsigned int*)(0x422A8098UL))) +#define bM4_TMRA2_PERAR_PER7 (*((volatile unsigned int*)(0x422A809CUL))) +#define bM4_TMRA2_PERAR_PER8 (*((volatile unsigned int*)(0x422A80A0UL))) +#define bM4_TMRA2_PERAR_PER9 (*((volatile unsigned int*)(0x422A80A4UL))) +#define bM4_TMRA2_PERAR_PER10 (*((volatile unsigned int*)(0x422A80A8UL))) +#define bM4_TMRA2_PERAR_PER11 (*((volatile unsigned int*)(0x422A80ACUL))) +#define bM4_TMRA2_PERAR_PER12 (*((volatile unsigned int*)(0x422A80B0UL))) +#define bM4_TMRA2_PERAR_PER13 (*((volatile unsigned int*)(0x422A80B4UL))) +#define bM4_TMRA2_PERAR_PER14 (*((volatile unsigned int*)(0x422A80B8UL))) +#define bM4_TMRA2_PERAR_PER15 (*((volatile unsigned int*)(0x422A80BCUL))) +#define bM4_TMRA2_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422A8800UL))) +#define bM4_TMRA2_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422A8804UL))) +#define bM4_TMRA2_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422A8808UL))) +#define bM4_TMRA2_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422A880CUL))) +#define bM4_TMRA2_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422A8810UL))) +#define bM4_TMRA2_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422A8814UL))) +#define bM4_TMRA2_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422A8818UL))) +#define bM4_TMRA2_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422A881CUL))) +#define bM4_TMRA2_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422A8820UL))) +#define bM4_TMRA2_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422A8824UL))) +#define bM4_TMRA2_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422A8828UL))) +#define bM4_TMRA2_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422A882CUL))) +#define bM4_TMRA2_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422A8830UL))) +#define bM4_TMRA2_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422A8834UL))) +#define bM4_TMRA2_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422A8838UL))) +#define bM4_TMRA2_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422A883CUL))) +#define bM4_TMRA2_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422A8880UL))) +#define bM4_TMRA2_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422A8884UL))) +#define bM4_TMRA2_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422A8888UL))) +#define bM4_TMRA2_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422A888CUL))) +#define bM4_TMRA2_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422A8890UL))) +#define bM4_TMRA2_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422A8894UL))) +#define bM4_TMRA2_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422A8898UL))) +#define bM4_TMRA2_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422A889CUL))) +#define bM4_TMRA2_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422A88A0UL))) +#define bM4_TMRA2_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422A88A4UL))) +#define bM4_TMRA2_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422A88A8UL))) +#define bM4_TMRA2_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422A88ACUL))) +#define bM4_TMRA2_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422A88B0UL))) +#define bM4_TMRA2_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422A88B4UL))) +#define bM4_TMRA2_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422A88B8UL))) +#define bM4_TMRA2_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422A88BCUL))) +#define bM4_TMRA2_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422A8900UL))) +#define bM4_TMRA2_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422A8904UL))) +#define bM4_TMRA2_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422A8908UL))) +#define bM4_TMRA2_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422A890CUL))) +#define bM4_TMRA2_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422A8910UL))) +#define bM4_TMRA2_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422A8914UL))) +#define bM4_TMRA2_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422A8918UL))) +#define bM4_TMRA2_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422A891CUL))) +#define bM4_TMRA2_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422A8920UL))) +#define bM4_TMRA2_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422A8924UL))) +#define bM4_TMRA2_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422A8928UL))) +#define bM4_TMRA2_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422A892CUL))) +#define bM4_TMRA2_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422A8930UL))) +#define bM4_TMRA2_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422A8934UL))) +#define bM4_TMRA2_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422A8938UL))) +#define bM4_TMRA2_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422A893CUL))) +#define bM4_TMRA2_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422A8980UL))) +#define bM4_TMRA2_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422A8984UL))) +#define bM4_TMRA2_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422A8988UL))) +#define bM4_TMRA2_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422A898CUL))) +#define bM4_TMRA2_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422A8990UL))) +#define bM4_TMRA2_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422A8994UL))) +#define bM4_TMRA2_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422A8998UL))) +#define bM4_TMRA2_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422A899CUL))) +#define bM4_TMRA2_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422A89A0UL))) +#define bM4_TMRA2_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422A89A4UL))) +#define bM4_TMRA2_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422A89A8UL))) +#define bM4_TMRA2_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422A89ACUL))) +#define bM4_TMRA2_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422A89B0UL))) +#define bM4_TMRA2_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422A89B4UL))) +#define bM4_TMRA2_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422A89B8UL))) +#define bM4_TMRA2_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422A89BCUL))) +#define bM4_TMRA2_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422A8A00UL))) +#define bM4_TMRA2_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422A8A04UL))) +#define bM4_TMRA2_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422A8A08UL))) +#define bM4_TMRA2_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422A8A0CUL))) +#define bM4_TMRA2_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422A8A10UL))) +#define bM4_TMRA2_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422A8A14UL))) +#define bM4_TMRA2_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422A8A18UL))) +#define bM4_TMRA2_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422A8A1CUL))) +#define bM4_TMRA2_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422A8A20UL))) +#define bM4_TMRA2_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422A8A24UL))) +#define bM4_TMRA2_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422A8A28UL))) +#define bM4_TMRA2_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422A8A2CUL))) +#define bM4_TMRA2_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422A8A30UL))) +#define bM4_TMRA2_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422A8A34UL))) +#define bM4_TMRA2_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422A8A38UL))) +#define bM4_TMRA2_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422A8A3CUL))) +#define bM4_TMRA2_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422A8A80UL))) +#define bM4_TMRA2_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422A8A84UL))) +#define bM4_TMRA2_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422A8A88UL))) +#define bM4_TMRA2_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422A8A8CUL))) +#define bM4_TMRA2_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422A8A90UL))) +#define bM4_TMRA2_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422A8A94UL))) +#define bM4_TMRA2_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422A8A98UL))) +#define bM4_TMRA2_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422A8A9CUL))) +#define bM4_TMRA2_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422A8AA0UL))) +#define bM4_TMRA2_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422A8AA4UL))) +#define bM4_TMRA2_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422A8AA8UL))) +#define bM4_TMRA2_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422A8AACUL))) +#define bM4_TMRA2_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422A8AB0UL))) +#define bM4_TMRA2_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422A8AB4UL))) +#define bM4_TMRA2_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422A8AB8UL))) +#define bM4_TMRA2_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422A8ABCUL))) +#define bM4_TMRA2_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422A8B00UL))) +#define bM4_TMRA2_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422A8B04UL))) +#define bM4_TMRA2_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422A8B08UL))) +#define bM4_TMRA2_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422A8B0CUL))) +#define bM4_TMRA2_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422A8B10UL))) +#define bM4_TMRA2_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422A8B14UL))) +#define bM4_TMRA2_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422A8B18UL))) +#define bM4_TMRA2_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422A8B1CUL))) +#define bM4_TMRA2_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422A8B20UL))) +#define bM4_TMRA2_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422A8B24UL))) +#define bM4_TMRA2_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422A8B28UL))) +#define bM4_TMRA2_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422A8B2CUL))) +#define bM4_TMRA2_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422A8B30UL))) +#define bM4_TMRA2_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422A8B34UL))) +#define bM4_TMRA2_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422A8B38UL))) +#define bM4_TMRA2_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422A8B3CUL))) +#define bM4_TMRA2_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422A8B80UL))) +#define bM4_TMRA2_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422A8B84UL))) +#define bM4_TMRA2_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422A8B88UL))) +#define bM4_TMRA2_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422A8B8CUL))) +#define bM4_TMRA2_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422A8B90UL))) +#define bM4_TMRA2_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422A8B94UL))) +#define bM4_TMRA2_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422A8B98UL))) +#define bM4_TMRA2_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422A8B9CUL))) +#define bM4_TMRA2_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422A8BA0UL))) +#define bM4_TMRA2_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422A8BA4UL))) +#define bM4_TMRA2_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422A8BA8UL))) +#define bM4_TMRA2_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422A8BACUL))) +#define bM4_TMRA2_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422A8BB0UL))) +#define bM4_TMRA2_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422A8BB4UL))) +#define bM4_TMRA2_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422A8BB8UL))) +#define bM4_TMRA2_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422A8BBCUL))) +#define bM4_TMRA2_BCSTR_START (*((volatile unsigned int*)(0x422A9000UL))) +#define bM4_TMRA2_BCSTR_DIR (*((volatile unsigned int*)(0x422A9004UL))) +#define bM4_TMRA2_BCSTR_MODE (*((volatile unsigned int*)(0x422A9008UL))) +#define bM4_TMRA2_BCSTR_SYNST (*((volatile unsigned int*)(0x422A900CUL))) +#define bM4_TMRA2_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422A9010UL))) +#define bM4_TMRA2_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422A9014UL))) +#define bM4_TMRA2_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422A9018UL))) +#define bM4_TMRA2_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422A901CUL))) +#define bM4_TMRA2_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422A9030UL))) +#define bM4_TMRA2_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422A9034UL))) +#define bM4_TMRA2_BCSTR_OVFF (*((volatile unsigned int*)(0x422A9038UL))) +#define bM4_TMRA2_BCSTR_UDFF (*((volatile unsigned int*)(0x422A903CUL))) +#define bM4_TMRA2_HCONR_HSTA0 (*((volatile unsigned int*)(0x422A9080UL))) +#define bM4_TMRA2_HCONR_HSTA1 (*((volatile unsigned int*)(0x422A9084UL))) +#define bM4_TMRA2_HCONR_HSTA2 (*((volatile unsigned int*)(0x422A9088UL))) +#define bM4_TMRA2_HCONR_HSTP0 (*((volatile unsigned int*)(0x422A9090UL))) +#define bM4_TMRA2_HCONR_HSTP1 (*((volatile unsigned int*)(0x422A9094UL))) +#define bM4_TMRA2_HCONR_HSTP2 (*((volatile unsigned int*)(0x422A9098UL))) +#define bM4_TMRA2_HCONR_HCLE0 (*((volatile unsigned int*)(0x422A90A0UL))) +#define bM4_TMRA2_HCONR_HCLE1 (*((volatile unsigned int*)(0x422A90A4UL))) +#define bM4_TMRA2_HCONR_HCLE2 (*((volatile unsigned int*)(0x422A90A8UL))) +#define bM4_TMRA2_HCONR_HCLE3 (*((volatile unsigned int*)(0x422A90B0UL))) +#define bM4_TMRA2_HCONR_HCLE4 (*((volatile unsigned int*)(0x422A90B4UL))) +#define bM4_TMRA2_HCONR_HCLE5 (*((volatile unsigned int*)(0x422A90B8UL))) +#define bM4_TMRA2_HCONR_HCLE6 (*((volatile unsigned int*)(0x422A90BCUL))) +#define bM4_TMRA2_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422A9100UL))) +#define bM4_TMRA2_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422A9104UL))) +#define bM4_TMRA2_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422A9108UL))) +#define bM4_TMRA2_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422A910CUL))) +#define bM4_TMRA2_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422A9110UL))) +#define bM4_TMRA2_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422A9114UL))) +#define bM4_TMRA2_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422A9118UL))) +#define bM4_TMRA2_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422A911CUL))) +#define bM4_TMRA2_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422A9120UL))) +#define bM4_TMRA2_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422A9124UL))) +#define bM4_TMRA2_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422A9128UL))) +#define bM4_TMRA2_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422A912CUL))) +#define bM4_TMRA2_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422A9130UL))) +#define bM4_TMRA2_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422A9180UL))) +#define bM4_TMRA2_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422A9184UL))) +#define bM4_TMRA2_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422A9188UL))) +#define bM4_TMRA2_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422A918CUL))) +#define bM4_TMRA2_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422A9190UL))) +#define bM4_TMRA2_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422A9194UL))) +#define bM4_TMRA2_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422A9198UL))) +#define bM4_TMRA2_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422A919CUL))) +#define bM4_TMRA2_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422A91A0UL))) +#define bM4_TMRA2_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422A91A4UL))) +#define bM4_TMRA2_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422A91A8UL))) +#define bM4_TMRA2_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422A91ACUL))) +#define bM4_TMRA2_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422A91B0UL))) +#define bM4_TMRA2_ICONR_ITEN1 (*((volatile unsigned int*)(0x422A9200UL))) +#define bM4_TMRA2_ICONR_ITEN2 (*((volatile unsigned int*)(0x422A9204UL))) +#define bM4_TMRA2_ICONR_ITEN3 (*((volatile unsigned int*)(0x422A9208UL))) +#define bM4_TMRA2_ICONR_ITEN4 (*((volatile unsigned int*)(0x422A920CUL))) +#define bM4_TMRA2_ICONR_ITEN5 (*((volatile unsigned int*)(0x422A9210UL))) +#define bM4_TMRA2_ICONR_ITEN6 (*((volatile unsigned int*)(0x422A9214UL))) +#define bM4_TMRA2_ICONR_ITEN7 (*((volatile unsigned int*)(0x422A9218UL))) +#define bM4_TMRA2_ICONR_ITEN8 (*((volatile unsigned int*)(0x422A921CUL))) +#define bM4_TMRA2_ECONR_ETEN1 (*((volatile unsigned int*)(0x422A9280UL))) +#define bM4_TMRA2_ECONR_ETEN2 (*((volatile unsigned int*)(0x422A9284UL))) +#define bM4_TMRA2_ECONR_ETEN3 (*((volatile unsigned int*)(0x422A9288UL))) +#define bM4_TMRA2_ECONR_ETEN4 (*((volatile unsigned int*)(0x422A928CUL))) +#define bM4_TMRA2_ECONR_ETEN5 (*((volatile unsigned int*)(0x422A9290UL))) +#define bM4_TMRA2_ECONR_ETEN6 (*((volatile unsigned int*)(0x422A9294UL))) +#define bM4_TMRA2_ECONR_ETEN7 (*((volatile unsigned int*)(0x422A9298UL))) +#define bM4_TMRA2_ECONR_ETEN8 (*((volatile unsigned int*)(0x422A929CUL))) +#define bM4_TMRA2_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422A9300UL))) +#define bM4_TMRA2_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422A9304UL))) +#define bM4_TMRA2_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422A9308UL))) +#define bM4_TMRA2_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422A9320UL))) +#define bM4_TMRA2_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422A9324UL))) +#define bM4_TMRA2_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422A9328UL))) +#define bM4_TMRA2_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422A9330UL))) +#define bM4_TMRA2_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422A9334UL))) +#define bM4_TMRA2_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422A9338UL))) +#define bM4_TMRA2_STFLR_CMPF1 (*((volatile unsigned int*)(0x422A9380UL))) +#define bM4_TMRA2_STFLR_CMPF2 (*((volatile unsigned int*)(0x422A9384UL))) +#define bM4_TMRA2_STFLR_CMPF3 (*((volatile unsigned int*)(0x422A9388UL))) +#define bM4_TMRA2_STFLR_CMPF4 (*((volatile unsigned int*)(0x422A938CUL))) +#define bM4_TMRA2_STFLR_CMPF5 (*((volatile unsigned int*)(0x422A9390UL))) +#define bM4_TMRA2_STFLR_CMPF6 (*((volatile unsigned int*)(0x422A9394UL))) +#define bM4_TMRA2_STFLR_CMPF7 (*((volatile unsigned int*)(0x422A9398UL))) +#define bM4_TMRA2_STFLR_CMPF8 (*((volatile unsigned int*)(0x422A939CUL))) +#define bM4_TMRA2_BCONR1_BEN (*((volatile unsigned int*)(0x422A9800UL))) +#define bM4_TMRA2_BCONR1_BSE0 (*((volatile unsigned int*)(0x422A9804UL))) +#define bM4_TMRA2_BCONR1_BSE1 (*((volatile unsigned int*)(0x422A9808UL))) +#define bM4_TMRA2_BCONR2_BEN (*((volatile unsigned int*)(0x422A9900UL))) +#define bM4_TMRA2_BCONR2_BSE0 (*((volatile unsigned int*)(0x422A9904UL))) +#define bM4_TMRA2_BCONR2_BSE1 (*((volatile unsigned int*)(0x422A9908UL))) +#define bM4_TMRA2_BCONR3_BEN (*((volatile unsigned int*)(0x422A9A00UL))) +#define bM4_TMRA2_BCONR3_BSE0 (*((volatile unsigned int*)(0x422A9A04UL))) +#define bM4_TMRA2_BCONR3_BSE1 (*((volatile unsigned int*)(0x422A9A08UL))) +#define bM4_TMRA2_BCONR4_BEN (*((volatile unsigned int*)(0x422A9B00UL))) +#define bM4_TMRA2_BCONR4_BSE0 (*((volatile unsigned int*)(0x422A9B04UL))) +#define bM4_TMRA2_BCONR4_BSE1 (*((volatile unsigned int*)(0x422A9B08UL))) +#define bM4_TMRA2_CCONR1_CAPMD (*((volatile unsigned int*)(0x422AA000UL))) +#define bM4_TMRA2_CCONR1_HICP0 (*((volatile unsigned int*)(0x422AA010UL))) +#define bM4_TMRA2_CCONR1_HICP1 (*((volatile unsigned int*)(0x422AA014UL))) +#define bM4_TMRA2_CCONR1_HICP2 (*((volatile unsigned int*)(0x422AA018UL))) +#define bM4_TMRA2_CCONR1_HICP3 (*((volatile unsigned int*)(0x422AA020UL))) +#define bM4_TMRA2_CCONR1_HICP4 (*((volatile unsigned int*)(0x422AA024UL))) +#define bM4_TMRA2_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422AA030UL))) +#define bM4_TMRA2_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422AA034UL))) +#define bM4_TMRA2_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422AA038UL))) +#define bM4_TMRA2_CCONR2_CAPMD (*((volatile unsigned int*)(0x422AA080UL))) +#define bM4_TMRA2_CCONR2_HICP0 (*((volatile unsigned int*)(0x422AA090UL))) +#define bM4_TMRA2_CCONR2_HICP1 (*((volatile unsigned int*)(0x422AA094UL))) +#define bM4_TMRA2_CCONR2_HICP2 (*((volatile unsigned int*)(0x422AA098UL))) +#define bM4_TMRA2_CCONR2_HICP3 (*((volatile unsigned int*)(0x422AA0A0UL))) +#define bM4_TMRA2_CCONR2_HICP4 (*((volatile unsigned int*)(0x422AA0A4UL))) +#define bM4_TMRA2_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422AA0B0UL))) +#define bM4_TMRA2_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422AA0B4UL))) +#define bM4_TMRA2_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422AA0B8UL))) +#define bM4_TMRA2_CCONR3_CAPMD (*((volatile unsigned int*)(0x422AA100UL))) +#define bM4_TMRA2_CCONR3_HICP0 (*((volatile unsigned int*)(0x422AA110UL))) +#define bM4_TMRA2_CCONR3_HICP1 (*((volatile unsigned int*)(0x422AA114UL))) +#define bM4_TMRA2_CCONR3_HICP2 (*((volatile unsigned int*)(0x422AA118UL))) +#define bM4_TMRA2_CCONR3_HICP3 (*((volatile unsigned int*)(0x422AA120UL))) +#define bM4_TMRA2_CCONR3_HICP4 (*((volatile unsigned int*)(0x422AA124UL))) +#define bM4_TMRA2_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422AA130UL))) +#define bM4_TMRA2_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422AA134UL))) +#define bM4_TMRA2_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422AA138UL))) +#define bM4_TMRA2_CCONR4_CAPMD (*((volatile unsigned int*)(0x422AA180UL))) +#define bM4_TMRA2_CCONR4_HICP0 (*((volatile unsigned int*)(0x422AA190UL))) +#define bM4_TMRA2_CCONR4_HICP1 (*((volatile unsigned int*)(0x422AA194UL))) +#define bM4_TMRA2_CCONR4_HICP2 (*((volatile unsigned int*)(0x422AA198UL))) +#define bM4_TMRA2_CCONR4_HICP3 (*((volatile unsigned int*)(0x422AA1A0UL))) +#define bM4_TMRA2_CCONR4_HICP4 (*((volatile unsigned int*)(0x422AA1A4UL))) +#define bM4_TMRA2_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422AA1B0UL))) +#define bM4_TMRA2_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422AA1B4UL))) +#define bM4_TMRA2_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422AA1B8UL))) +#define bM4_TMRA2_CCONR5_CAPMD (*((volatile unsigned int*)(0x422AA200UL))) +#define bM4_TMRA2_CCONR5_HICP0 (*((volatile unsigned int*)(0x422AA210UL))) +#define bM4_TMRA2_CCONR5_HICP1 (*((volatile unsigned int*)(0x422AA214UL))) +#define bM4_TMRA2_CCONR5_HICP2 (*((volatile unsigned int*)(0x422AA218UL))) +#define bM4_TMRA2_CCONR5_HICP3 (*((volatile unsigned int*)(0x422AA220UL))) +#define bM4_TMRA2_CCONR5_HICP4 (*((volatile unsigned int*)(0x422AA224UL))) +#define bM4_TMRA2_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422AA230UL))) +#define bM4_TMRA2_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422AA234UL))) +#define bM4_TMRA2_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422AA238UL))) +#define bM4_TMRA2_CCONR6_CAPMD (*((volatile unsigned int*)(0x422AA280UL))) +#define bM4_TMRA2_CCONR6_HICP0 (*((volatile unsigned int*)(0x422AA290UL))) +#define bM4_TMRA2_CCONR6_HICP1 (*((volatile unsigned int*)(0x422AA294UL))) +#define bM4_TMRA2_CCONR6_HICP2 (*((volatile unsigned int*)(0x422AA298UL))) +#define bM4_TMRA2_CCONR6_HICP3 (*((volatile unsigned int*)(0x422AA2A0UL))) +#define bM4_TMRA2_CCONR6_HICP4 (*((volatile unsigned int*)(0x422AA2A4UL))) +#define bM4_TMRA2_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422AA2B0UL))) +#define bM4_TMRA2_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422AA2B4UL))) +#define bM4_TMRA2_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422AA2B8UL))) +#define bM4_TMRA2_CCONR7_CAPMD (*((volatile unsigned int*)(0x422AA300UL))) +#define bM4_TMRA2_CCONR7_HICP0 (*((volatile unsigned int*)(0x422AA310UL))) +#define bM4_TMRA2_CCONR7_HICP1 (*((volatile unsigned int*)(0x422AA314UL))) +#define bM4_TMRA2_CCONR7_HICP2 (*((volatile unsigned int*)(0x422AA318UL))) +#define bM4_TMRA2_CCONR7_HICP3 (*((volatile unsigned int*)(0x422AA320UL))) +#define bM4_TMRA2_CCONR7_HICP4 (*((volatile unsigned int*)(0x422AA324UL))) +#define bM4_TMRA2_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422AA330UL))) +#define bM4_TMRA2_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422AA334UL))) +#define bM4_TMRA2_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422AA338UL))) +#define bM4_TMRA2_CCONR8_CAPMD (*((volatile unsigned int*)(0x422AA380UL))) +#define bM4_TMRA2_CCONR8_HICP0 (*((volatile unsigned int*)(0x422AA390UL))) +#define bM4_TMRA2_CCONR8_HICP1 (*((volatile unsigned int*)(0x422AA394UL))) +#define bM4_TMRA2_CCONR8_HICP2 (*((volatile unsigned int*)(0x422AA398UL))) +#define bM4_TMRA2_CCONR8_HICP3 (*((volatile unsigned int*)(0x422AA3A0UL))) +#define bM4_TMRA2_CCONR8_HICP4 (*((volatile unsigned int*)(0x422AA3A4UL))) +#define bM4_TMRA2_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422AA3B0UL))) +#define bM4_TMRA2_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422AA3B4UL))) +#define bM4_TMRA2_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422AA3B8UL))) +#define bM4_TMRA2_PCONR1_STAC0 (*((volatile unsigned int*)(0x422AA800UL))) +#define bM4_TMRA2_PCONR1_STAC1 (*((volatile unsigned int*)(0x422AA804UL))) +#define bM4_TMRA2_PCONR1_STPC0 (*((volatile unsigned int*)(0x422AA808UL))) +#define bM4_TMRA2_PCONR1_STPC1 (*((volatile unsigned int*)(0x422AA80CUL))) +#define bM4_TMRA2_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422AA810UL))) +#define bM4_TMRA2_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422AA814UL))) +#define bM4_TMRA2_PCONR1_PERC0 (*((volatile unsigned int*)(0x422AA818UL))) +#define bM4_TMRA2_PCONR1_PERC1 (*((volatile unsigned int*)(0x422AA81CUL))) +#define bM4_TMRA2_PCONR1_FORC0 (*((volatile unsigned int*)(0x422AA820UL))) +#define bM4_TMRA2_PCONR1_FORC1 (*((volatile unsigned int*)(0x422AA824UL))) +#define bM4_TMRA2_PCONR1_OUTEN (*((volatile unsigned int*)(0x422AA830UL))) +#define bM4_TMRA2_PCONR2_STAC0 (*((volatile unsigned int*)(0x422AA880UL))) +#define bM4_TMRA2_PCONR2_STAC1 (*((volatile unsigned int*)(0x422AA884UL))) +#define bM4_TMRA2_PCONR2_STPC0 (*((volatile unsigned int*)(0x422AA888UL))) +#define bM4_TMRA2_PCONR2_STPC1 (*((volatile unsigned int*)(0x422AA88CUL))) +#define bM4_TMRA2_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422AA890UL))) +#define bM4_TMRA2_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422AA894UL))) +#define bM4_TMRA2_PCONR2_PERC0 (*((volatile unsigned int*)(0x422AA898UL))) +#define bM4_TMRA2_PCONR2_PERC1 (*((volatile unsigned int*)(0x422AA89CUL))) +#define bM4_TMRA2_PCONR2_FORC0 (*((volatile unsigned int*)(0x422AA8A0UL))) +#define bM4_TMRA2_PCONR2_FORC1 (*((volatile unsigned int*)(0x422AA8A4UL))) +#define bM4_TMRA2_PCONR2_OUTEN (*((volatile unsigned int*)(0x422AA8B0UL))) +#define bM4_TMRA2_PCONR3_STAC0 (*((volatile unsigned int*)(0x422AA900UL))) +#define bM4_TMRA2_PCONR3_STAC1 (*((volatile unsigned int*)(0x422AA904UL))) +#define bM4_TMRA2_PCONR3_STPC0 (*((volatile unsigned int*)(0x422AA908UL))) +#define bM4_TMRA2_PCONR3_STPC1 (*((volatile unsigned int*)(0x422AA90CUL))) +#define bM4_TMRA2_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422AA910UL))) +#define bM4_TMRA2_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422AA914UL))) +#define bM4_TMRA2_PCONR3_PERC0 (*((volatile unsigned int*)(0x422AA918UL))) +#define bM4_TMRA2_PCONR3_PERC1 (*((volatile unsigned int*)(0x422AA91CUL))) +#define bM4_TMRA2_PCONR3_FORC0 (*((volatile unsigned int*)(0x422AA920UL))) +#define bM4_TMRA2_PCONR3_FORC1 (*((volatile unsigned int*)(0x422AA924UL))) +#define bM4_TMRA2_PCONR3_OUTEN (*((volatile unsigned int*)(0x422AA930UL))) +#define bM4_TMRA2_PCONR4_STAC0 (*((volatile unsigned int*)(0x422AA980UL))) +#define bM4_TMRA2_PCONR4_STAC1 (*((volatile unsigned int*)(0x422AA984UL))) +#define bM4_TMRA2_PCONR4_STPC0 (*((volatile unsigned int*)(0x422AA988UL))) +#define bM4_TMRA2_PCONR4_STPC1 (*((volatile unsigned int*)(0x422AA98CUL))) +#define bM4_TMRA2_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422AA990UL))) +#define bM4_TMRA2_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422AA994UL))) +#define bM4_TMRA2_PCONR4_PERC0 (*((volatile unsigned int*)(0x422AA998UL))) +#define bM4_TMRA2_PCONR4_PERC1 (*((volatile unsigned int*)(0x422AA99CUL))) +#define bM4_TMRA2_PCONR4_FORC0 (*((volatile unsigned int*)(0x422AA9A0UL))) +#define bM4_TMRA2_PCONR4_FORC1 (*((volatile unsigned int*)(0x422AA9A4UL))) +#define bM4_TMRA2_PCONR4_OUTEN (*((volatile unsigned int*)(0x422AA9B0UL))) +#define bM4_TMRA2_PCONR5_STAC0 (*((volatile unsigned int*)(0x422AAA00UL))) +#define bM4_TMRA2_PCONR5_STAC1 (*((volatile unsigned int*)(0x422AAA04UL))) +#define bM4_TMRA2_PCONR5_STPC0 (*((volatile unsigned int*)(0x422AAA08UL))) +#define bM4_TMRA2_PCONR5_STPC1 (*((volatile unsigned int*)(0x422AAA0CUL))) +#define bM4_TMRA2_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422AAA10UL))) +#define bM4_TMRA2_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422AAA14UL))) +#define bM4_TMRA2_PCONR5_PERC0 (*((volatile unsigned int*)(0x422AAA18UL))) +#define bM4_TMRA2_PCONR5_PERC1 (*((volatile unsigned int*)(0x422AAA1CUL))) +#define bM4_TMRA2_PCONR5_FORC0 (*((volatile unsigned int*)(0x422AAA20UL))) +#define bM4_TMRA2_PCONR5_FORC1 (*((volatile unsigned int*)(0x422AAA24UL))) +#define bM4_TMRA2_PCONR5_OUTEN (*((volatile unsigned int*)(0x422AAA30UL))) +#define bM4_TMRA2_PCONR6_STAC0 (*((volatile unsigned int*)(0x422AAA80UL))) +#define bM4_TMRA2_PCONR6_STAC1 (*((volatile unsigned int*)(0x422AAA84UL))) +#define bM4_TMRA2_PCONR6_STPC0 (*((volatile unsigned int*)(0x422AAA88UL))) +#define bM4_TMRA2_PCONR6_STPC1 (*((volatile unsigned int*)(0x422AAA8CUL))) +#define bM4_TMRA2_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422AAA90UL))) +#define bM4_TMRA2_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422AAA94UL))) +#define bM4_TMRA2_PCONR6_PERC0 (*((volatile unsigned int*)(0x422AAA98UL))) +#define bM4_TMRA2_PCONR6_PERC1 (*((volatile unsigned int*)(0x422AAA9CUL))) +#define bM4_TMRA2_PCONR6_FORC0 (*((volatile unsigned int*)(0x422AAAA0UL))) +#define bM4_TMRA2_PCONR6_FORC1 (*((volatile unsigned int*)(0x422AAAA4UL))) +#define bM4_TMRA2_PCONR6_OUTEN (*((volatile unsigned int*)(0x422AAAB0UL))) +#define bM4_TMRA2_PCONR7_STAC0 (*((volatile unsigned int*)(0x422AAB00UL))) +#define bM4_TMRA2_PCONR7_STAC1 (*((volatile unsigned int*)(0x422AAB04UL))) +#define bM4_TMRA2_PCONR7_STPC0 (*((volatile unsigned int*)(0x422AAB08UL))) +#define bM4_TMRA2_PCONR7_STPC1 (*((volatile unsigned int*)(0x422AAB0CUL))) +#define bM4_TMRA2_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422AAB10UL))) +#define bM4_TMRA2_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422AAB14UL))) +#define bM4_TMRA2_PCONR7_PERC0 (*((volatile unsigned int*)(0x422AAB18UL))) +#define bM4_TMRA2_PCONR7_PERC1 (*((volatile unsigned int*)(0x422AAB1CUL))) +#define bM4_TMRA2_PCONR7_FORC0 (*((volatile unsigned int*)(0x422AAB20UL))) +#define bM4_TMRA2_PCONR7_FORC1 (*((volatile unsigned int*)(0x422AAB24UL))) +#define bM4_TMRA2_PCONR7_OUTEN (*((volatile unsigned int*)(0x422AAB30UL))) +#define bM4_TMRA2_PCONR8_STAC0 (*((volatile unsigned int*)(0x422AAB80UL))) +#define bM4_TMRA2_PCONR8_STAC1 (*((volatile unsigned int*)(0x422AAB84UL))) +#define bM4_TMRA2_PCONR8_STPC0 (*((volatile unsigned int*)(0x422AAB88UL))) +#define bM4_TMRA2_PCONR8_STPC1 (*((volatile unsigned int*)(0x422AAB8CUL))) +#define bM4_TMRA2_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422AAB90UL))) +#define bM4_TMRA2_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422AAB94UL))) +#define bM4_TMRA2_PCONR8_PERC0 (*((volatile unsigned int*)(0x422AAB98UL))) +#define bM4_TMRA2_PCONR8_PERC1 (*((volatile unsigned int*)(0x422AAB9CUL))) +#define bM4_TMRA2_PCONR8_FORC0 (*((volatile unsigned int*)(0x422AABA0UL))) +#define bM4_TMRA2_PCONR8_FORC1 (*((volatile unsigned int*)(0x422AABA4UL))) +#define bM4_TMRA2_PCONR8_OUTEN (*((volatile unsigned int*)(0x422AABB0UL))) +#define bM4_TMRA3_CNTER_CNT0 (*((volatile unsigned int*)(0x422B0000UL))) +#define bM4_TMRA3_CNTER_CNT1 (*((volatile unsigned int*)(0x422B0004UL))) +#define bM4_TMRA3_CNTER_CNT2 (*((volatile unsigned int*)(0x422B0008UL))) +#define bM4_TMRA3_CNTER_CNT3 (*((volatile unsigned int*)(0x422B000CUL))) +#define bM4_TMRA3_CNTER_CNT4 (*((volatile unsigned int*)(0x422B0010UL))) +#define bM4_TMRA3_CNTER_CNT5 (*((volatile unsigned int*)(0x422B0014UL))) +#define bM4_TMRA3_CNTER_CNT6 (*((volatile unsigned int*)(0x422B0018UL))) +#define bM4_TMRA3_CNTER_CNT7 (*((volatile unsigned int*)(0x422B001CUL))) +#define bM4_TMRA3_CNTER_CNT8 (*((volatile unsigned int*)(0x422B0020UL))) +#define bM4_TMRA3_CNTER_CNT9 (*((volatile unsigned int*)(0x422B0024UL))) +#define bM4_TMRA3_CNTER_CNT10 (*((volatile unsigned int*)(0x422B0028UL))) +#define bM4_TMRA3_CNTER_CNT11 (*((volatile unsigned int*)(0x422B002CUL))) +#define bM4_TMRA3_CNTER_CNT12 (*((volatile unsigned int*)(0x422B0030UL))) +#define bM4_TMRA3_CNTER_CNT13 (*((volatile unsigned int*)(0x422B0034UL))) +#define bM4_TMRA3_CNTER_CNT14 (*((volatile unsigned int*)(0x422B0038UL))) +#define bM4_TMRA3_CNTER_CNT15 (*((volatile unsigned int*)(0x422B003CUL))) +#define bM4_TMRA3_PERAR_PER0 (*((volatile unsigned int*)(0x422B0080UL))) +#define bM4_TMRA3_PERAR_PER1 (*((volatile unsigned int*)(0x422B0084UL))) +#define bM4_TMRA3_PERAR_PER2 (*((volatile unsigned int*)(0x422B0088UL))) +#define bM4_TMRA3_PERAR_PER3 (*((volatile unsigned int*)(0x422B008CUL))) +#define bM4_TMRA3_PERAR_PER4 (*((volatile unsigned int*)(0x422B0090UL))) +#define bM4_TMRA3_PERAR_PER5 (*((volatile unsigned int*)(0x422B0094UL))) +#define bM4_TMRA3_PERAR_PER6 (*((volatile unsigned int*)(0x422B0098UL))) +#define bM4_TMRA3_PERAR_PER7 (*((volatile unsigned int*)(0x422B009CUL))) +#define bM4_TMRA3_PERAR_PER8 (*((volatile unsigned int*)(0x422B00A0UL))) +#define bM4_TMRA3_PERAR_PER9 (*((volatile unsigned int*)(0x422B00A4UL))) +#define bM4_TMRA3_PERAR_PER10 (*((volatile unsigned int*)(0x422B00A8UL))) +#define bM4_TMRA3_PERAR_PER11 (*((volatile unsigned int*)(0x422B00ACUL))) +#define bM4_TMRA3_PERAR_PER12 (*((volatile unsigned int*)(0x422B00B0UL))) +#define bM4_TMRA3_PERAR_PER13 (*((volatile unsigned int*)(0x422B00B4UL))) +#define bM4_TMRA3_PERAR_PER14 (*((volatile unsigned int*)(0x422B00B8UL))) +#define bM4_TMRA3_PERAR_PER15 (*((volatile unsigned int*)(0x422B00BCUL))) +#define bM4_TMRA3_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422B0800UL))) +#define bM4_TMRA3_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422B0804UL))) +#define bM4_TMRA3_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422B0808UL))) +#define bM4_TMRA3_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422B080CUL))) +#define bM4_TMRA3_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422B0810UL))) +#define bM4_TMRA3_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422B0814UL))) +#define bM4_TMRA3_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422B0818UL))) +#define bM4_TMRA3_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422B081CUL))) +#define bM4_TMRA3_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422B0820UL))) +#define bM4_TMRA3_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422B0824UL))) +#define bM4_TMRA3_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422B0828UL))) +#define bM4_TMRA3_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422B082CUL))) +#define bM4_TMRA3_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422B0830UL))) +#define bM4_TMRA3_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422B0834UL))) +#define bM4_TMRA3_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422B0838UL))) +#define bM4_TMRA3_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422B083CUL))) +#define bM4_TMRA3_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422B0880UL))) +#define bM4_TMRA3_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422B0884UL))) +#define bM4_TMRA3_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422B0888UL))) +#define bM4_TMRA3_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422B088CUL))) +#define bM4_TMRA3_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422B0890UL))) +#define bM4_TMRA3_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422B0894UL))) +#define bM4_TMRA3_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422B0898UL))) +#define bM4_TMRA3_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422B089CUL))) +#define bM4_TMRA3_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422B08A0UL))) +#define bM4_TMRA3_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422B08A4UL))) +#define bM4_TMRA3_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422B08A8UL))) +#define bM4_TMRA3_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422B08ACUL))) +#define bM4_TMRA3_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422B08B0UL))) +#define bM4_TMRA3_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422B08B4UL))) +#define bM4_TMRA3_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422B08B8UL))) +#define bM4_TMRA3_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422B08BCUL))) +#define bM4_TMRA3_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422B0900UL))) +#define bM4_TMRA3_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422B0904UL))) +#define bM4_TMRA3_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422B0908UL))) +#define bM4_TMRA3_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422B090CUL))) +#define bM4_TMRA3_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422B0910UL))) +#define bM4_TMRA3_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422B0914UL))) +#define bM4_TMRA3_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422B0918UL))) +#define bM4_TMRA3_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422B091CUL))) +#define bM4_TMRA3_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422B0920UL))) +#define bM4_TMRA3_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422B0924UL))) +#define bM4_TMRA3_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422B0928UL))) +#define bM4_TMRA3_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422B092CUL))) +#define bM4_TMRA3_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422B0930UL))) +#define bM4_TMRA3_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422B0934UL))) +#define bM4_TMRA3_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422B0938UL))) +#define bM4_TMRA3_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422B093CUL))) +#define bM4_TMRA3_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422B0980UL))) +#define bM4_TMRA3_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422B0984UL))) +#define bM4_TMRA3_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422B0988UL))) +#define bM4_TMRA3_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422B098CUL))) +#define bM4_TMRA3_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422B0990UL))) +#define bM4_TMRA3_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422B0994UL))) +#define bM4_TMRA3_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422B0998UL))) +#define bM4_TMRA3_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422B099CUL))) +#define bM4_TMRA3_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422B09A0UL))) +#define bM4_TMRA3_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422B09A4UL))) +#define bM4_TMRA3_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422B09A8UL))) +#define bM4_TMRA3_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422B09ACUL))) +#define bM4_TMRA3_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422B09B0UL))) +#define bM4_TMRA3_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422B09B4UL))) +#define bM4_TMRA3_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422B09B8UL))) +#define bM4_TMRA3_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422B09BCUL))) +#define bM4_TMRA3_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422B0A00UL))) +#define bM4_TMRA3_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422B0A04UL))) +#define bM4_TMRA3_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422B0A08UL))) +#define bM4_TMRA3_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422B0A0CUL))) +#define bM4_TMRA3_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422B0A10UL))) +#define bM4_TMRA3_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422B0A14UL))) +#define bM4_TMRA3_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422B0A18UL))) +#define bM4_TMRA3_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422B0A1CUL))) +#define bM4_TMRA3_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422B0A20UL))) +#define bM4_TMRA3_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422B0A24UL))) +#define bM4_TMRA3_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422B0A28UL))) +#define bM4_TMRA3_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422B0A2CUL))) +#define bM4_TMRA3_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422B0A30UL))) +#define bM4_TMRA3_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422B0A34UL))) +#define bM4_TMRA3_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422B0A38UL))) +#define bM4_TMRA3_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422B0A3CUL))) +#define bM4_TMRA3_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422B0A80UL))) +#define bM4_TMRA3_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422B0A84UL))) +#define bM4_TMRA3_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422B0A88UL))) +#define bM4_TMRA3_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422B0A8CUL))) +#define bM4_TMRA3_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422B0A90UL))) +#define bM4_TMRA3_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422B0A94UL))) +#define bM4_TMRA3_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422B0A98UL))) +#define bM4_TMRA3_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422B0A9CUL))) +#define bM4_TMRA3_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422B0AA0UL))) +#define bM4_TMRA3_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422B0AA4UL))) +#define bM4_TMRA3_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422B0AA8UL))) +#define bM4_TMRA3_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422B0AACUL))) +#define bM4_TMRA3_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422B0AB0UL))) +#define bM4_TMRA3_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422B0AB4UL))) +#define bM4_TMRA3_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422B0AB8UL))) +#define bM4_TMRA3_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422B0ABCUL))) +#define bM4_TMRA3_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422B0B00UL))) +#define bM4_TMRA3_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422B0B04UL))) +#define bM4_TMRA3_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422B0B08UL))) +#define bM4_TMRA3_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422B0B0CUL))) +#define bM4_TMRA3_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422B0B10UL))) +#define bM4_TMRA3_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422B0B14UL))) +#define bM4_TMRA3_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422B0B18UL))) +#define bM4_TMRA3_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422B0B1CUL))) +#define bM4_TMRA3_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422B0B20UL))) +#define bM4_TMRA3_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422B0B24UL))) +#define bM4_TMRA3_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422B0B28UL))) +#define bM4_TMRA3_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422B0B2CUL))) +#define bM4_TMRA3_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422B0B30UL))) +#define bM4_TMRA3_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422B0B34UL))) +#define bM4_TMRA3_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422B0B38UL))) +#define bM4_TMRA3_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422B0B3CUL))) +#define bM4_TMRA3_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422B0B80UL))) +#define bM4_TMRA3_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422B0B84UL))) +#define bM4_TMRA3_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422B0B88UL))) +#define bM4_TMRA3_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422B0B8CUL))) +#define bM4_TMRA3_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422B0B90UL))) +#define bM4_TMRA3_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422B0B94UL))) +#define bM4_TMRA3_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422B0B98UL))) +#define bM4_TMRA3_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422B0B9CUL))) +#define bM4_TMRA3_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422B0BA0UL))) +#define bM4_TMRA3_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422B0BA4UL))) +#define bM4_TMRA3_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422B0BA8UL))) +#define bM4_TMRA3_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422B0BACUL))) +#define bM4_TMRA3_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422B0BB0UL))) +#define bM4_TMRA3_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422B0BB4UL))) +#define bM4_TMRA3_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422B0BB8UL))) +#define bM4_TMRA3_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422B0BBCUL))) +#define bM4_TMRA3_BCSTR_START (*((volatile unsigned int*)(0x422B1000UL))) +#define bM4_TMRA3_BCSTR_DIR (*((volatile unsigned int*)(0x422B1004UL))) +#define bM4_TMRA3_BCSTR_MODE (*((volatile unsigned int*)(0x422B1008UL))) +#define bM4_TMRA3_BCSTR_SYNST (*((volatile unsigned int*)(0x422B100CUL))) +#define bM4_TMRA3_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422B1010UL))) +#define bM4_TMRA3_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422B1014UL))) +#define bM4_TMRA3_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422B1018UL))) +#define bM4_TMRA3_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422B101CUL))) +#define bM4_TMRA3_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422B1030UL))) +#define bM4_TMRA3_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422B1034UL))) +#define bM4_TMRA3_BCSTR_OVFF (*((volatile unsigned int*)(0x422B1038UL))) +#define bM4_TMRA3_BCSTR_UDFF (*((volatile unsigned int*)(0x422B103CUL))) +#define bM4_TMRA3_HCONR_HSTA0 (*((volatile unsigned int*)(0x422B1080UL))) +#define bM4_TMRA3_HCONR_HSTA1 (*((volatile unsigned int*)(0x422B1084UL))) +#define bM4_TMRA3_HCONR_HSTA2 (*((volatile unsigned int*)(0x422B1088UL))) +#define bM4_TMRA3_HCONR_HSTP0 (*((volatile unsigned int*)(0x422B1090UL))) +#define bM4_TMRA3_HCONR_HSTP1 (*((volatile unsigned int*)(0x422B1094UL))) +#define bM4_TMRA3_HCONR_HSTP2 (*((volatile unsigned int*)(0x422B1098UL))) +#define bM4_TMRA3_HCONR_HCLE0 (*((volatile unsigned int*)(0x422B10A0UL))) +#define bM4_TMRA3_HCONR_HCLE1 (*((volatile unsigned int*)(0x422B10A4UL))) +#define bM4_TMRA3_HCONR_HCLE2 (*((volatile unsigned int*)(0x422B10A8UL))) +#define bM4_TMRA3_HCONR_HCLE3 (*((volatile unsigned int*)(0x422B10B0UL))) +#define bM4_TMRA3_HCONR_HCLE4 (*((volatile unsigned int*)(0x422B10B4UL))) +#define bM4_TMRA3_HCONR_HCLE5 (*((volatile unsigned int*)(0x422B10B8UL))) +#define bM4_TMRA3_HCONR_HCLE6 (*((volatile unsigned int*)(0x422B10BCUL))) +#define bM4_TMRA3_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422B1100UL))) +#define bM4_TMRA3_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422B1104UL))) +#define bM4_TMRA3_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422B1108UL))) +#define bM4_TMRA3_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422B110CUL))) +#define bM4_TMRA3_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422B1110UL))) +#define bM4_TMRA3_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422B1114UL))) +#define bM4_TMRA3_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422B1118UL))) +#define bM4_TMRA3_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422B111CUL))) +#define bM4_TMRA3_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422B1120UL))) +#define bM4_TMRA3_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422B1124UL))) +#define bM4_TMRA3_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422B1128UL))) +#define bM4_TMRA3_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422B112CUL))) +#define bM4_TMRA3_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422B1130UL))) +#define bM4_TMRA3_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422B1180UL))) +#define bM4_TMRA3_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422B1184UL))) +#define bM4_TMRA3_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422B1188UL))) +#define bM4_TMRA3_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422B118CUL))) +#define bM4_TMRA3_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422B1190UL))) +#define bM4_TMRA3_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422B1194UL))) +#define bM4_TMRA3_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422B1198UL))) +#define bM4_TMRA3_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422B119CUL))) +#define bM4_TMRA3_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422B11A0UL))) +#define bM4_TMRA3_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422B11A4UL))) +#define bM4_TMRA3_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422B11A8UL))) +#define bM4_TMRA3_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422B11ACUL))) +#define bM4_TMRA3_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422B11B0UL))) +#define bM4_TMRA3_ICONR_ITEN1 (*((volatile unsigned int*)(0x422B1200UL))) +#define bM4_TMRA3_ICONR_ITEN2 (*((volatile unsigned int*)(0x422B1204UL))) +#define bM4_TMRA3_ICONR_ITEN3 (*((volatile unsigned int*)(0x422B1208UL))) +#define bM4_TMRA3_ICONR_ITEN4 (*((volatile unsigned int*)(0x422B120CUL))) +#define bM4_TMRA3_ICONR_ITEN5 (*((volatile unsigned int*)(0x422B1210UL))) +#define bM4_TMRA3_ICONR_ITEN6 (*((volatile unsigned int*)(0x422B1214UL))) +#define bM4_TMRA3_ICONR_ITEN7 (*((volatile unsigned int*)(0x422B1218UL))) +#define bM4_TMRA3_ICONR_ITEN8 (*((volatile unsigned int*)(0x422B121CUL))) +#define bM4_TMRA3_ECONR_ETEN1 (*((volatile unsigned int*)(0x422B1280UL))) +#define bM4_TMRA3_ECONR_ETEN2 (*((volatile unsigned int*)(0x422B1284UL))) +#define bM4_TMRA3_ECONR_ETEN3 (*((volatile unsigned int*)(0x422B1288UL))) +#define bM4_TMRA3_ECONR_ETEN4 (*((volatile unsigned int*)(0x422B128CUL))) +#define bM4_TMRA3_ECONR_ETEN5 (*((volatile unsigned int*)(0x422B1290UL))) +#define bM4_TMRA3_ECONR_ETEN6 (*((volatile unsigned int*)(0x422B1294UL))) +#define bM4_TMRA3_ECONR_ETEN7 (*((volatile unsigned int*)(0x422B1298UL))) +#define bM4_TMRA3_ECONR_ETEN8 (*((volatile unsigned int*)(0x422B129CUL))) +#define bM4_TMRA3_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422B1300UL))) +#define bM4_TMRA3_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422B1304UL))) +#define bM4_TMRA3_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422B1308UL))) +#define bM4_TMRA3_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422B1320UL))) +#define bM4_TMRA3_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422B1324UL))) +#define bM4_TMRA3_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422B1328UL))) +#define bM4_TMRA3_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422B1330UL))) +#define bM4_TMRA3_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422B1334UL))) +#define bM4_TMRA3_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422B1338UL))) +#define bM4_TMRA3_STFLR_CMPF1 (*((volatile unsigned int*)(0x422B1380UL))) +#define bM4_TMRA3_STFLR_CMPF2 (*((volatile unsigned int*)(0x422B1384UL))) +#define bM4_TMRA3_STFLR_CMPF3 (*((volatile unsigned int*)(0x422B1388UL))) +#define bM4_TMRA3_STFLR_CMPF4 (*((volatile unsigned int*)(0x422B138CUL))) +#define bM4_TMRA3_STFLR_CMPF5 (*((volatile unsigned int*)(0x422B1390UL))) +#define bM4_TMRA3_STFLR_CMPF6 (*((volatile unsigned int*)(0x422B1394UL))) +#define bM4_TMRA3_STFLR_CMPF7 (*((volatile unsigned int*)(0x422B1398UL))) +#define bM4_TMRA3_STFLR_CMPF8 (*((volatile unsigned int*)(0x422B139CUL))) +#define bM4_TMRA3_BCONR1_BEN (*((volatile unsigned int*)(0x422B1800UL))) +#define bM4_TMRA3_BCONR1_BSE0 (*((volatile unsigned int*)(0x422B1804UL))) +#define bM4_TMRA3_BCONR1_BSE1 (*((volatile unsigned int*)(0x422B1808UL))) +#define bM4_TMRA3_BCONR2_BEN (*((volatile unsigned int*)(0x422B1900UL))) +#define bM4_TMRA3_BCONR2_BSE0 (*((volatile unsigned int*)(0x422B1904UL))) +#define bM4_TMRA3_BCONR2_BSE1 (*((volatile unsigned int*)(0x422B1908UL))) +#define bM4_TMRA3_BCONR3_BEN (*((volatile unsigned int*)(0x422B1A00UL))) +#define bM4_TMRA3_BCONR3_BSE0 (*((volatile unsigned int*)(0x422B1A04UL))) +#define bM4_TMRA3_BCONR3_BSE1 (*((volatile unsigned int*)(0x422B1A08UL))) +#define bM4_TMRA3_BCONR4_BEN (*((volatile unsigned int*)(0x422B1B00UL))) +#define bM4_TMRA3_BCONR4_BSE0 (*((volatile unsigned int*)(0x422B1B04UL))) +#define bM4_TMRA3_BCONR4_BSE1 (*((volatile unsigned int*)(0x422B1B08UL))) +#define bM4_TMRA3_CCONR1_CAPMD (*((volatile unsigned int*)(0x422B2000UL))) +#define bM4_TMRA3_CCONR1_HICP0 (*((volatile unsigned int*)(0x422B2010UL))) +#define bM4_TMRA3_CCONR1_HICP1 (*((volatile unsigned int*)(0x422B2014UL))) +#define bM4_TMRA3_CCONR1_HICP2 (*((volatile unsigned int*)(0x422B2018UL))) +#define bM4_TMRA3_CCONR1_HICP3 (*((volatile unsigned int*)(0x422B2020UL))) +#define bM4_TMRA3_CCONR1_HICP4 (*((volatile unsigned int*)(0x422B2024UL))) +#define bM4_TMRA3_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422B2030UL))) +#define bM4_TMRA3_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422B2034UL))) +#define bM4_TMRA3_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422B2038UL))) +#define bM4_TMRA3_CCONR2_CAPMD (*((volatile unsigned int*)(0x422B2080UL))) +#define bM4_TMRA3_CCONR2_HICP0 (*((volatile unsigned int*)(0x422B2090UL))) +#define bM4_TMRA3_CCONR2_HICP1 (*((volatile unsigned int*)(0x422B2094UL))) +#define bM4_TMRA3_CCONR2_HICP2 (*((volatile unsigned int*)(0x422B2098UL))) +#define bM4_TMRA3_CCONR2_HICP3 (*((volatile unsigned int*)(0x422B20A0UL))) +#define bM4_TMRA3_CCONR2_HICP4 (*((volatile unsigned int*)(0x422B20A4UL))) +#define bM4_TMRA3_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422B20B0UL))) +#define bM4_TMRA3_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422B20B4UL))) +#define bM4_TMRA3_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422B20B8UL))) +#define bM4_TMRA3_CCONR3_CAPMD (*((volatile unsigned int*)(0x422B2100UL))) +#define bM4_TMRA3_CCONR3_HICP0 (*((volatile unsigned int*)(0x422B2110UL))) +#define bM4_TMRA3_CCONR3_HICP1 (*((volatile unsigned int*)(0x422B2114UL))) +#define bM4_TMRA3_CCONR3_HICP2 (*((volatile unsigned int*)(0x422B2118UL))) +#define bM4_TMRA3_CCONR3_HICP3 (*((volatile unsigned int*)(0x422B2120UL))) +#define bM4_TMRA3_CCONR3_HICP4 (*((volatile unsigned int*)(0x422B2124UL))) +#define bM4_TMRA3_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422B2130UL))) +#define bM4_TMRA3_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422B2134UL))) +#define bM4_TMRA3_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422B2138UL))) +#define bM4_TMRA3_CCONR4_CAPMD (*((volatile unsigned int*)(0x422B2180UL))) +#define bM4_TMRA3_CCONR4_HICP0 (*((volatile unsigned int*)(0x422B2190UL))) +#define bM4_TMRA3_CCONR4_HICP1 (*((volatile unsigned int*)(0x422B2194UL))) +#define bM4_TMRA3_CCONR4_HICP2 (*((volatile unsigned int*)(0x422B2198UL))) +#define bM4_TMRA3_CCONR4_HICP3 (*((volatile unsigned int*)(0x422B21A0UL))) +#define bM4_TMRA3_CCONR4_HICP4 (*((volatile unsigned int*)(0x422B21A4UL))) +#define bM4_TMRA3_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422B21B0UL))) +#define bM4_TMRA3_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422B21B4UL))) +#define bM4_TMRA3_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422B21B8UL))) +#define bM4_TMRA3_CCONR5_CAPMD (*((volatile unsigned int*)(0x422B2200UL))) +#define bM4_TMRA3_CCONR5_HICP0 (*((volatile unsigned int*)(0x422B2210UL))) +#define bM4_TMRA3_CCONR5_HICP1 (*((volatile unsigned int*)(0x422B2214UL))) +#define bM4_TMRA3_CCONR5_HICP2 (*((volatile unsigned int*)(0x422B2218UL))) +#define bM4_TMRA3_CCONR5_HICP3 (*((volatile unsigned int*)(0x422B2220UL))) +#define bM4_TMRA3_CCONR5_HICP4 (*((volatile unsigned int*)(0x422B2224UL))) +#define bM4_TMRA3_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422B2230UL))) +#define bM4_TMRA3_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422B2234UL))) +#define bM4_TMRA3_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422B2238UL))) +#define bM4_TMRA3_CCONR6_CAPMD (*((volatile unsigned int*)(0x422B2280UL))) +#define bM4_TMRA3_CCONR6_HICP0 (*((volatile unsigned int*)(0x422B2290UL))) +#define bM4_TMRA3_CCONR6_HICP1 (*((volatile unsigned int*)(0x422B2294UL))) +#define bM4_TMRA3_CCONR6_HICP2 (*((volatile unsigned int*)(0x422B2298UL))) +#define bM4_TMRA3_CCONR6_HICP3 (*((volatile unsigned int*)(0x422B22A0UL))) +#define bM4_TMRA3_CCONR6_HICP4 (*((volatile unsigned int*)(0x422B22A4UL))) +#define bM4_TMRA3_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422B22B0UL))) +#define bM4_TMRA3_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422B22B4UL))) +#define bM4_TMRA3_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422B22B8UL))) +#define bM4_TMRA3_CCONR7_CAPMD (*((volatile unsigned int*)(0x422B2300UL))) +#define bM4_TMRA3_CCONR7_HICP0 (*((volatile unsigned int*)(0x422B2310UL))) +#define bM4_TMRA3_CCONR7_HICP1 (*((volatile unsigned int*)(0x422B2314UL))) +#define bM4_TMRA3_CCONR7_HICP2 (*((volatile unsigned int*)(0x422B2318UL))) +#define bM4_TMRA3_CCONR7_HICP3 (*((volatile unsigned int*)(0x422B2320UL))) +#define bM4_TMRA3_CCONR7_HICP4 (*((volatile unsigned int*)(0x422B2324UL))) +#define bM4_TMRA3_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422B2330UL))) +#define bM4_TMRA3_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422B2334UL))) +#define bM4_TMRA3_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422B2338UL))) +#define bM4_TMRA3_CCONR8_CAPMD (*((volatile unsigned int*)(0x422B2380UL))) +#define bM4_TMRA3_CCONR8_HICP0 (*((volatile unsigned int*)(0x422B2390UL))) +#define bM4_TMRA3_CCONR8_HICP1 (*((volatile unsigned int*)(0x422B2394UL))) +#define bM4_TMRA3_CCONR8_HICP2 (*((volatile unsigned int*)(0x422B2398UL))) +#define bM4_TMRA3_CCONR8_HICP3 (*((volatile unsigned int*)(0x422B23A0UL))) +#define bM4_TMRA3_CCONR8_HICP4 (*((volatile unsigned int*)(0x422B23A4UL))) +#define bM4_TMRA3_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422B23B0UL))) +#define bM4_TMRA3_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422B23B4UL))) +#define bM4_TMRA3_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422B23B8UL))) +#define bM4_TMRA3_PCONR1_STAC0 (*((volatile unsigned int*)(0x422B2800UL))) +#define bM4_TMRA3_PCONR1_STAC1 (*((volatile unsigned int*)(0x422B2804UL))) +#define bM4_TMRA3_PCONR1_STPC0 (*((volatile unsigned int*)(0x422B2808UL))) +#define bM4_TMRA3_PCONR1_STPC1 (*((volatile unsigned int*)(0x422B280CUL))) +#define bM4_TMRA3_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422B2810UL))) +#define bM4_TMRA3_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422B2814UL))) +#define bM4_TMRA3_PCONR1_PERC0 (*((volatile unsigned int*)(0x422B2818UL))) +#define bM4_TMRA3_PCONR1_PERC1 (*((volatile unsigned int*)(0x422B281CUL))) +#define bM4_TMRA3_PCONR1_FORC0 (*((volatile unsigned int*)(0x422B2820UL))) +#define bM4_TMRA3_PCONR1_FORC1 (*((volatile unsigned int*)(0x422B2824UL))) +#define bM4_TMRA3_PCONR1_OUTEN (*((volatile unsigned int*)(0x422B2830UL))) +#define bM4_TMRA3_PCONR2_STAC0 (*((volatile unsigned int*)(0x422B2880UL))) +#define bM4_TMRA3_PCONR2_STAC1 (*((volatile unsigned int*)(0x422B2884UL))) +#define bM4_TMRA3_PCONR2_STPC0 (*((volatile unsigned int*)(0x422B2888UL))) +#define bM4_TMRA3_PCONR2_STPC1 (*((volatile unsigned int*)(0x422B288CUL))) +#define bM4_TMRA3_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422B2890UL))) +#define bM4_TMRA3_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422B2894UL))) +#define bM4_TMRA3_PCONR2_PERC0 (*((volatile unsigned int*)(0x422B2898UL))) +#define bM4_TMRA3_PCONR2_PERC1 (*((volatile unsigned int*)(0x422B289CUL))) +#define bM4_TMRA3_PCONR2_FORC0 (*((volatile unsigned int*)(0x422B28A0UL))) +#define bM4_TMRA3_PCONR2_FORC1 (*((volatile unsigned int*)(0x422B28A4UL))) +#define bM4_TMRA3_PCONR2_OUTEN (*((volatile unsigned int*)(0x422B28B0UL))) +#define bM4_TMRA3_PCONR3_STAC0 (*((volatile unsigned int*)(0x422B2900UL))) +#define bM4_TMRA3_PCONR3_STAC1 (*((volatile unsigned int*)(0x422B2904UL))) +#define bM4_TMRA3_PCONR3_STPC0 (*((volatile unsigned int*)(0x422B2908UL))) +#define bM4_TMRA3_PCONR3_STPC1 (*((volatile unsigned int*)(0x422B290CUL))) +#define bM4_TMRA3_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422B2910UL))) +#define bM4_TMRA3_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422B2914UL))) +#define bM4_TMRA3_PCONR3_PERC0 (*((volatile unsigned int*)(0x422B2918UL))) +#define bM4_TMRA3_PCONR3_PERC1 (*((volatile unsigned int*)(0x422B291CUL))) +#define bM4_TMRA3_PCONR3_FORC0 (*((volatile unsigned int*)(0x422B2920UL))) +#define bM4_TMRA3_PCONR3_FORC1 (*((volatile unsigned int*)(0x422B2924UL))) +#define bM4_TMRA3_PCONR3_OUTEN (*((volatile unsigned int*)(0x422B2930UL))) +#define bM4_TMRA3_PCONR4_STAC0 (*((volatile unsigned int*)(0x422B2980UL))) +#define bM4_TMRA3_PCONR4_STAC1 (*((volatile unsigned int*)(0x422B2984UL))) +#define bM4_TMRA3_PCONR4_STPC0 (*((volatile unsigned int*)(0x422B2988UL))) +#define bM4_TMRA3_PCONR4_STPC1 (*((volatile unsigned int*)(0x422B298CUL))) +#define bM4_TMRA3_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422B2990UL))) +#define bM4_TMRA3_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422B2994UL))) +#define bM4_TMRA3_PCONR4_PERC0 (*((volatile unsigned int*)(0x422B2998UL))) +#define bM4_TMRA3_PCONR4_PERC1 (*((volatile unsigned int*)(0x422B299CUL))) +#define bM4_TMRA3_PCONR4_FORC0 (*((volatile unsigned int*)(0x422B29A0UL))) +#define bM4_TMRA3_PCONR4_FORC1 (*((volatile unsigned int*)(0x422B29A4UL))) +#define bM4_TMRA3_PCONR4_OUTEN (*((volatile unsigned int*)(0x422B29B0UL))) +#define bM4_TMRA3_PCONR5_STAC0 (*((volatile unsigned int*)(0x422B2A00UL))) +#define bM4_TMRA3_PCONR5_STAC1 (*((volatile unsigned int*)(0x422B2A04UL))) +#define bM4_TMRA3_PCONR5_STPC0 (*((volatile unsigned int*)(0x422B2A08UL))) +#define bM4_TMRA3_PCONR5_STPC1 (*((volatile unsigned int*)(0x422B2A0CUL))) +#define bM4_TMRA3_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422B2A10UL))) +#define bM4_TMRA3_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422B2A14UL))) +#define bM4_TMRA3_PCONR5_PERC0 (*((volatile unsigned int*)(0x422B2A18UL))) +#define bM4_TMRA3_PCONR5_PERC1 (*((volatile unsigned int*)(0x422B2A1CUL))) +#define bM4_TMRA3_PCONR5_FORC0 (*((volatile unsigned int*)(0x422B2A20UL))) +#define bM4_TMRA3_PCONR5_FORC1 (*((volatile unsigned int*)(0x422B2A24UL))) +#define bM4_TMRA3_PCONR5_OUTEN (*((volatile unsigned int*)(0x422B2A30UL))) +#define bM4_TMRA3_PCONR6_STAC0 (*((volatile unsigned int*)(0x422B2A80UL))) +#define bM4_TMRA3_PCONR6_STAC1 (*((volatile unsigned int*)(0x422B2A84UL))) +#define bM4_TMRA3_PCONR6_STPC0 (*((volatile unsigned int*)(0x422B2A88UL))) +#define bM4_TMRA3_PCONR6_STPC1 (*((volatile unsigned int*)(0x422B2A8CUL))) +#define bM4_TMRA3_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422B2A90UL))) +#define bM4_TMRA3_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422B2A94UL))) +#define bM4_TMRA3_PCONR6_PERC0 (*((volatile unsigned int*)(0x422B2A98UL))) +#define bM4_TMRA3_PCONR6_PERC1 (*((volatile unsigned int*)(0x422B2A9CUL))) +#define bM4_TMRA3_PCONR6_FORC0 (*((volatile unsigned int*)(0x422B2AA0UL))) +#define bM4_TMRA3_PCONR6_FORC1 (*((volatile unsigned int*)(0x422B2AA4UL))) +#define bM4_TMRA3_PCONR6_OUTEN (*((volatile unsigned int*)(0x422B2AB0UL))) +#define bM4_TMRA3_PCONR7_STAC0 (*((volatile unsigned int*)(0x422B2B00UL))) +#define bM4_TMRA3_PCONR7_STAC1 (*((volatile unsigned int*)(0x422B2B04UL))) +#define bM4_TMRA3_PCONR7_STPC0 (*((volatile unsigned int*)(0x422B2B08UL))) +#define bM4_TMRA3_PCONR7_STPC1 (*((volatile unsigned int*)(0x422B2B0CUL))) +#define bM4_TMRA3_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422B2B10UL))) +#define bM4_TMRA3_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422B2B14UL))) +#define bM4_TMRA3_PCONR7_PERC0 (*((volatile unsigned int*)(0x422B2B18UL))) +#define bM4_TMRA3_PCONR7_PERC1 (*((volatile unsigned int*)(0x422B2B1CUL))) +#define bM4_TMRA3_PCONR7_FORC0 (*((volatile unsigned int*)(0x422B2B20UL))) +#define bM4_TMRA3_PCONR7_FORC1 (*((volatile unsigned int*)(0x422B2B24UL))) +#define bM4_TMRA3_PCONR7_OUTEN (*((volatile unsigned int*)(0x422B2B30UL))) +#define bM4_TMRA3_PCONR8_STAC0 (*((volatile unsigned int*)(0x422B2B80UL))) +#define bM4_TMRA3_PCONR8_STAC1 (*((volatile unsigned int*)(0x422B2B84UL))) +#define bM4_TMRA3_PCONR8_STPC0 (*((volatile unsigned int*)(0x422B2B88UL))) +#define bM4_TMRA3_PCONR8_STPC1 (*((volatile unsigned int*)(0x422B2B8CUL))) +#define bM4_TMRA3_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422B2B90UL))) +#define bM4_TMRA3_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422B2B94UL))) +#define bM4_TMRA3_PCONR8_PERC0 (*((volatile unsigned int*)(0x422B2B98UL))) +#define bM4_TMRA3_PCONR8_PERC1 (*((volatile unsigned int*)(0x422B2B9CUL))) +#define bM4_TMRA3_PCONR8_FORC0 (*((volatile unsigned int*)(0x422B2BA0UL))) +#define bM4_TMRA3_PCONR8_FORC1 (*((volatile unsigned int*)(0x422B2BA4UL))) +#define bM4_TMRA3_PCONR8_OUTEN (*((volatile unsigned int*)(0x422B2BB0UL))) +#define bM4_TMRA4_CNTER_CNT0 (*((volatile unsigned int*)(0x422B8000UL))) +#define bM4_TMRA4_CNTER_CNT1 (*((volatile unsigned int*)(0x422B8004UL))) +#define bM4_TMRA4_CNTER_CNT2 (*((volatile unsigned int*)(0x422B8008UL))) +#define bM4_TMRA4_CNTER_CNT3 (*((volatile unsigned int*)(0x422B800CUL))) +#define bM4_TMRA4_CNTER_CNT4 (*((volatile unsigned int*)(0x422B8010UL))) +#define bM4_TMRA4_CNTER_CNT5 (*((volatile unsigned int*)(0x422B8014UL))) +#define bM4_TMRA4_CNTER_CNT6 (*((volatile unsigned int*)(0x422B8018UL))) +#define bM4_TMRA4_CNTER_CNT7 (*((volatile unsigned int*)(0x422B801CUL))) +#define bM4_TMRA4_CNTER_CNT8 (*((volatile unsigned int*)(0x422B8020UL))) +#define bM4_TMRA4_CNTER_CNT9 (*((volatile unsigned int*)(0x422B8024UL))) +#define bM4_TMRA4_CNTER_CNT10 (*((volatile unsigned int*)(0x422B8028UL))) +#define bM4_TMRA4_CNTER_CNT11 (*((volatile unsigned int*)(0x422B802CUL))) +#define bM4_TMRA4_CNTER_CNT12 (*((volatile unsigned int*)(0x422B8030UL))) +#define bM4_TMRA4_CNTER_CNT13 (*((volatile unsigned int*)(0x422B8034UL))) +#define bM4_TMRA4_CNTER_CNT14 (*((volatile unsigned int*)(0x422B8038UL))) +#define bM4_TMRA4_CNTER_CNT15 (*((volatile unsigned int*)(0x422B803CUL))) +#define bM4_TMRA4_PERAR_PER0 (*((volatile unsigned int*)(0x422B8080UL))) +#define bM4_TMRA4_PERAR_PER1 (*((volatile unsigned int*)(0x422B8084UL))) +#define bM4_TMRA4_PERAR_PER2 (*((volatile unsigned int*)(0x422B8088UL))) +#define bM4_TMRA4_PERAR_PER3 (*((volatile unsigned int*)(0x422B808CUL))) +#define bM4_TMRA4_PERAR_PER4 (*((volatile unsigned int*)(0x422B8090UL))) +#define bM4_TMRA4_PERAR_PER5 (*((volatile unsigned int*)(0x422B8094UL))) +#define bM4_TMRA4_PERAR_PER6 (*((volatile unsigned int*)(0x422B8098UL))) +#define bM4_TMRA4_PERAR_PER7 (*((volatile unsigned int*)(0x422B809CUL))) +#define bM4_TMRA4_PERAR_PER8 (*((volatile unsigned int*)(0x422B80A0UL))) +#define bM4_TMRA4_PERAR_PER9 (*((volatile unsigned int*)(0x422B80A4UL))) +#define bM4_TMRA4_PERAR_PER10 (*((volatile unsigned int*)(0x422B80A8UL))) +#define bM4_TMRA4_PERAR_PER11 (*((volatile unsigned int*)(0x422B80ACUL))) +#define bM4_TMRA4_PERAR_PER12 (*((volatile unsigned int*)(0x422B80B0UL))) +#define bM4_TMRA4_PERAR_PER13 (*((volatile unsigned int*)(0x422B80B4UL))) +#define bM4_TMRA4_PERAR_PER14 (*((volatile unsigned int*)(0x422B80B8UL))) +#define bM4_TMRA4_PERAR_PER15 (*((volatile unsigned int*)(0x422B80BCUL))) +#define bM4_TMRA4_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422B8800UL))) +#define bM4_TMRA4_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422B8804UL))) +#define bM4_TMRA4_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422B8808UL))) +#define bM4_TMRA4_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422B880CUL))) +#define bM4_TMRA4_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422B8810UL))) +#define bM4_TMRA4_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422B8814UL))) +#define bM4_TMRA4_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422B8818UL))) +#define bM4_TMRA4_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422B881CUL))) +#define bM4_TMRA4_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422B8820UL))) +#define bM4_TMRA4_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422B8824UL))) +#define bM4_TMRA4_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422B8828UL))) +#define bM4_TMRA4_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422B882CUL))) +#define bM4_TMRA4_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422B8830UL))) +#define bM4_TMRA4_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422B8834UL))) +#define bM4_TMRA4_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422B8838UL))) +#define bM4_TMRA4_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422B883CUL))) +#define bM4_TMRA4_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422B8880UL))) +#define bM4_TMRA4_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422B8884UL))) +#define bM4_TMRA4_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422B8888UL))) +#define bM4_TMRA4_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422B888CUL))) +#define bM4_TMRA4_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422B8890UL))) +#define bM4_TMRA4_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422B8894UL))) +#define bM4_TMRA4_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422B8898UL))) +#define bM4_TMRA4_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422B889CUL))) +#define bM4_TMRA4_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422B88A0UL))) +#define bM4_TMRA4_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422B88A4UL))) +#define bM4_TMRA4_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422B88A8UL))) +#define bM4_TMRA4_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422B88ACUL))) +#define bM4_TMRA4_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422B88B0UL))) +#define bM4_TMRA4_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422B88B4UL))) +#define bM4_TMRA4_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422B88B8UL))) +#define bM4_TMRA4_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422B88BCUL))) +#define bM4_TMRA4_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422B8900UL))) +#define bM4_TMRA4_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422B8904UL))) +#define bM4_TMRA4_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422B8908UL))) +#define bM4_TMRA4_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422B890CUL))) +#define bM4_TMRA4_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422B8910UL))) +#define bM4_TMRA4_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422B8914UL))) +#define bM4_TMRA4_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422B8918UL))) +#define bM4_TMRA4_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422B891CUL))) +#define bM4_TMRA4_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422B8920UL))) +#define bM4_TMRA4_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422B8924UL))) +#define bM4_TMRA4_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422B8928UL))) +#define bM4_TMRA4_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422B892CUL))) +#define bM4_TMRA4_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422B8930UL))) +#define bM4_TMRA4_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422B8934UL))) +#define bM4_TMRA4_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422B8938UL))) +#define bM4_TMRA4_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422B893CUL))) +#define bM4_TMRA4_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422B8980UL))) +#define bM4_TMRA4_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422B8984UL))) +#define bM4_TMRA4_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422B8988UL))) +#define bM4_TMRA4_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422B898CUL))) +#define bM4_TMRA4_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422B8990UL))) +#define bM4_TMRA4_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422B8994UL))) +#define bM4_TMRA4_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422B8998UL))) +#define bM4_TMRA4_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422B899CUL))) +#define bM4_TMRA4_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422B89A0UL))) +#define bM4_TMRA4_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422B89A4UL))) +#define bM4_TMRA4_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422B89A8UL))) +#define bM4_TMRA4_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422B89ACUL))) +#define bM4_TMRA4_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422B89B0UL))) +#define bM4_TMRA4_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422B89B4UL))) +#define bM4_TMRA4_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422B89B8UL))) +#define bM4_TMRA4_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422B89BCUL))) +#define bM4_TMRA4_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422B8A00UL))) +#define bM4_TMRA4_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422B8A04UL))) +#define bM4_TMRA4_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422B8A08UL))) +#define bM4_TMRA4_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422B8A0CUL))) +#define bM4_TMRA4_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422B8A10UL))) +#define bM4_TMRA4_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422B8A14UL))) +#define bM4_TMRA4_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422B8A18UL))) +#define bM4_TMRA4_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422B8A1CUL))) +#define bM4_TMRA4_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422B8A20UL))) +#define bM4_TMRA4_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422B8A24UL))) +#define bM4_TMRA4_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422B8A28UL))) +#define bM4_TMRA4_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422B8A2CUL))) +#define bM4_TMRA4_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422B8A30UL))) +#define bM4_TMRA4_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422B8A34UL))) +#define bM4_TMRA4_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422B8A38UL))) +#define bM4_TMRA4_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422B8A3CUL))) +#define bM4_TMRA4_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422B8A80UL))) +#define bM4_TMRA4_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422B8A84UL))) +#define bM4_TMRA4_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422B8A88UL))) +#define bM4_TMRA4_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422B8A8CUL))) +#define bM4_TMRA4_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422B8A90UL))) +#define bM4_TMRA4_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422B8A94UL))) +#define bM4_TMRA4_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422B8A98UL))) +#define bM4_TMRA4_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422B8A9CUL))) +#define bM4_TMRA4_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422B8AA0UL))) +#define bM4_TMRA4_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422B8AA4UL))) +#define bM4_TMRA4_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422B8AA8UL))) +#define bM4_TMRA4_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422B8AACUL))) +#define bM4_TMRA4_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422B8AB0UL))) +#define bM4_TMRA4_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422B8AB4UL))) +#define bM4_TMRA4_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422B8AB8UL))) +#define bM4_TMRA4_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422B8ABCUL))) +#define bM4_TMRA4_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422B8B00UL))) +#define bM4_TMRA4_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422B8B04UL))) +#define bM4_TMRA4_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422B8B08UL))) +#define bM4_TMRA4_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422B8B0CUL))) +#define bM4_TMRA4_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422B8B10UL))) +#define bM4_TMRA4_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422B8B14UL))) +#define bM4_TMRA4_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422B8B18UL))) +#define bM4_TMRA4_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422B8B1CUL))) +#define bM4_TMRA4_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422B8B20UL))) +#define bM4_TMRA4_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422B8B24UL))) +#define bM4_TMRA4_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422B8B28UL))) +#define bM4_TMRA4_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422B8B2CUL))) +#define bM4_TMRA4_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422B8B30UL))) +#define bM4_TMRA4_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422B8B34UL))) +#define bM4_TMRA4_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422B8B38UL))) +#define bM4_TMRA4_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422B8B3CUL))) +#define bM4_TMRA4_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422B8B80UL))) +#define bM4_TMRA4_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422B8B84UL))) +#define bM4_TMRA4_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422B8B88UL))) +#define bM4_TMRA4_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422B8B8CUL))) +#define bM4_TMRA4_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422B8B90UL))) +#define bM4_TMRA4_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422B8B94UL))) +#define bM4_TMRA4_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422B8B98UL))) +#define bM4_TMRA4_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422B8B9CUL))) +#define bM4_TMRA4_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422B8BA0UL))) +#define bM4_TMRA4_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422B8BA4UL))) +#define bM4_TMRA4_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422B8BA8UL))) +#define bM4_TMRA4_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422B8BACUL))) +#define bM4_TMRA4_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422B8BB0UL))) +#define bM4_TMRA4_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422B8BB4UL))) +#define bM4_TMRA4_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422B8BB8UL))) +#define bM4_TMRA4_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422B8BBCUL))) +#define bM4_TMRA4_BCSTR_START (*((volatile unsigned int*)(0x422B9000UL))) +#define bM4_TMRA4_BCSTR_DIR (*((volatile unsigned int*)(0x422B9004UL))) +#define bM4_TMRA4_BCSTR_MODE (*((volatile unsigned int*)(0x422B9008UL))) +#define bM4_TMRA4_BCSTR_SYNST (*((volatile unsigned int*)(0x422B900CUL))) +#define bM4_TMRA4_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422B9010UL))) +#define bM4_TMRA4_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422B9014UL))) +#define bM4_TMRA4_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422B9018UL))) +#define bM4_TMRA4_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422B901CUL))) +#define bM4_TMRA4_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422B9030UL))) +#define bM4_TMRA4_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422B9034UL))) +#define bM4_TMRA4_BCSTR_OVFF (*((volatile unsigned int*)(0x422B9038UL))) +#define bM4_TMRA4_BCSTR_UDFF (*((volatile unsigned int*)(0x422B903CUL))) +#define bM4_TMRA4_HCONR_HSTA0 (*((volatile unsigned int*)(0x422B9080UL))) +#define bM4_TMRA4_HCONR_HSTA1 (*((volatile unsigned int*)(0x422B9084UL))) +#define bM4_TMRA4_HCONR_HSTA2 (*((volatile unsigned int*)(0x422B9088UL))) +#define bM4_TMRA4_HCONR_HSTP0 (*((volatile unsigned int*)(0x422B9090UL))) +#define bM4_TMRA4_HCONR_HSTP1 (*((volatile unsigned int*)(0x422B9094UL))) +#define bM4_TMRA4_HCONR_HSTP2 (*((volatile unsigned int*)(0x422B9098UL))) +#define bM4_TMRA4_HCONR_HCLE0 (*((volatile unsigned int*)(0x422B90A0UL))) +#define bM4_TMRA4_HCONR_HCLE1 (*((volatile unsigned int*)(0x422B90A4UL))) +#define bM4_TMRA4_HCONR_HCLE2 (*((volatile unsigned int*)(0x422B90A8UL))) +#define bM4_TMRA4_HCONR_HCLE3 (*((volatile unsigned int*)(0x422B90B0UL))) +#define bM4_TMRA4_HCONR_HCLE4 (*((volatile unsigned int*)(0x422B90B4UL))) +#define bM4_TMRA4_HCONR_HCLE5 (*((volatile unsigned int*)(0x422B90B8UL))) +#define bM4_TMRA4_HCONR_HCLE6 (*((volatile unsigned int*)(0x422B90BCUL))) +#define bM4_TMRA4_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422B9100UL))) +#define bM4_TMRA4_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422B9104UL))) +#define bM4_TMRA4_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422B9108UL))) +#define bM4_TMRA4_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422B910CUL))) +#define bM4_TMRA4_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422B9110UL))) +#define bM4_TMRA4_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422B9114UL))) +#define bM4_TMRA4_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422B9118UL))) +#define bM4_TMRA4_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422B911CUL))) +#define bM4_TMRA4_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422B9120UL))) +#define bM4_TMRA4_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422B9124UL))) +#define bM4_TMRA4_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422B9128UL))) +#define bM4_TMRA4_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422B912CUL))) +#define bM4_TMRA4_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422B9130UL))) +#define bM4_TMRA4_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422B9180UL))) +#define bM4_TMRA4_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422B9184UL))) +#define bM4_TMRA4_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422B9188UL))) +#define bM4_TMRA4_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422B918CUL))) +#define bM4_TMRA4_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422B9190UL))) +#define bM4_TMRA4_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422B9194UL))) +#define bM4_TMRA4_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422B9198UL))) +#define bM4_TMRA4_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422B919CUL))) +#define bM4_TMRA4_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422B91A0UL))) +#define bM4_TMRA4_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422B91A4UL))) +#define bM4_TMRA4_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422B91A8UL))) +#define bM4_TMRA4_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422B91ACUL))) +#define bM4_TMRA4_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422B91B0UL))) +#define bM4_TMRA4_ICONR_ITEN1 (*((volatile unsigned int*)(0x422B9200UL))) +#define bM4_TMRA4_ICONR_ITEN2 (*((volatile unsigned int*)(0x422B9204UL))) +#define bM4_TMRA4_ICONR_ITEN3 (*((volatile unsigned int*)(0x422B9208UL))) +#define bM4_TMRA4_ICONR_ITEN4 (*((volatile unsigned int*)(0x422B920CUL))) +#define bM4_TMRA4_ICONR_ITEN5 (*((volatile unsigned int*)(0x422B9210UL))) +#define bM4_TMRA4_ICONR_ITEN6 (*((volatile unsigned int*)(0x422B9214UL))) +#define bM4_TMRA4_ICONR_ITEN7 (*((volatile unsigned int*)(0x422B9218UL))) +#define bM4_TMRA4_ICONR_ITEN8 (*((volatile unsigned int*)(0x422B921CUL))) +#define bM4_TMRA4_ECONR_ETEN1 (*((volatile unsigned int*)(0x422B9280UL))) +#define bM4_TMRA4_ECONR_ETEN2 (*((volatile unsigned int*)(0x422B9284UL))) +#define bM4_TMRA4_ECONR_ETEN3 (*((volatile unsigned int*)(0x422B9288UL))) +#define bM4_TMRA4_ECONR_ETEN4 (*((volatile unsigned int*)(0x422B928CUL))) +#define bM4_TMRA4_ECONR_ETEN5 (*((volatile unsigned int*)(0x422B9290UL))) +#define bM4_TMRA4_ECONR_ETEN6 (*((volatile unsigned int*)(0x422B9294UL))) +#define bM4_TMRA4_ECONR_ETEN7 (*((volatile unsigned int*)(0x422B9298UL))) +#define bM4_TMRA4_ECONR_ETEN8 (*((volatile unsigned int*)(0x422B929CUL))) +#define bM4_TMRA4_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422B9300UL))) +#define bM4_TMRA4_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422B9304UL))) +#define bM4_TMRA4_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422B9308UL))) +#define bM4_TMRA4_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422B9320UL))) +#define bM4_TMRA4_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422B9324UL))) +#define bM4_TMRA4_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422B9328UL))) +#define bM4_TMRA4_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422B9330UL))) +#define bM4_TMRA4_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422B9334UL))) +#define bM4_TMRA4_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422B9338UL))) +#define bM4_TMRA4_STFLR_CMPF1 (*((volatile unsigned int*)(0x422B9380UL))) +#define bM4_TMRA4_STFLR_CMPF2 (*((volatile unsigned int*)(0x422B9384UL))) +#define bM4_TMRA4_STFLR_CMPF3 (*((volatile unsigned int*)(0x422B9388UL))) +#define bM4_TMRA4_STFLR_CMPF4 (*((volatile unsigned int*)(0x422B938CUL))) +#define bM4_TMRA4_STFLR_CMPF5 (*((volatile unsigned int*)(0x422B9390UL))) +#define bM4_TMRA4_STFLR_CMPF6 (*((volatile unsigned int*)(0x422B9394UL))) +#define bM4_TMRA4_STFLR_CMPF7 (*((volatile unsigned int*)(0x422B9398UL))) +#define bM4_TMRA4_STFLR_CMPF8 (*((volatile unsigned int*)(0x422B939CUL))) +#define bM4_TMRA4_BCONR1_BEN (*((volatile unsigned int*)(0x422B9800UL))) +#define bM4_TMRA4_BCONR1_BSE0 (*((volatile unsigned int*)(0x422B9804UL))) +#define bM4_TMRA4_BCONR1_BSE1 (*((volatile unsigned int*)(0x422B9808UL))) +#define bM4_TMRA4_BCONR2_BEN (*((volatile unsigned int*)(0x422B9900UL))) +#define bM4_TMRA4_BCONR2_BSE0 (*((volatile unsigned int*)(0x422B9904UL))) +#define bM4_TMRA4_BCONR2_BSE1 (*((volatile unsigned int*)(0x422B9908UL))) +#define bM4_TMRA4_BCONR3_BEN (*((volatile unsigned int*)(0x422B9A00UL))) +#define bM4_TMRA4_BCONR3_BSE0 (*((volatile unsigned int*)(0x422B9A04UL))) +#define bM4_TMRA4_BCONR3_BSE1 (*((volatile unsigned int*)(0x422B9A08UL))) +#define bM4_TMRA4_BCONR4_BEN (*((volatile unsigned int*)(0x422B9B00UL))) +#define bM4_TMRA4_BCONR4_BSE0 (*((volatile unsigned int*)(0x422B9B04UL))) +#define bM4_TMRA4_BCONR4_BSE1 (*((volatile unsigned int*)(0x422B9B08UL))) +#define bM4_TMRA4_CCONR1_CAPMD (*((volatile unsigned int*)(0x422BA000UL))) +#define bM4_TMRA4_CCONR1_HICP0 (*((volatile unsigned int*)(0x422BA010UL))) +#define bM4_TMRA4_CCONR1_HICP1 (*((volatile unsigned int*)(0x422BA014UL))) +#define bM4_TMRA4_CCONR1_HICP2 (*((volatile unsigned int*)(0x422BA018UL))) +#define bM4_TMRA4_CCONR1_HICP3 (*((volatile unsigned int*)(0x422BA020UL))) +#define bM4_TMRA4_CCONR1_HICP4 (*((volatile unsigned int*)(0x422BA024UL))) +#define bM4_TMRA4_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422BA030UL))) +#define bM4_TMRA4_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422BA034UL))) +#define bM4_TMRA4_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422BA038UL))) +#define bM4_TMRA4_CCONR2_CAPMD (*((volatile unsigned int*)(0x422BA080UL))) +#define bM4_TMRA4_CCONR2_HICP0 (*((volatile unsigned int*)(0x422BA090UL))) +#define bM4_TMRA4_CCONR2_HICP1 (*((volatile unsigned int*)(0x422BA094UL))) +#define bM4_TMRA4_CCONR2_HICP2 (*((volatile unsigned int*)(0x422BA098UL))) +#define bM4_TMRA4_CCONR2_HICP3 (*((volatile unsigned int*)(0x422BA0A0UL))) +#define bM4_TMRA4_CCONR2_HICP4 (*((volatile unsigned int*)(0x422BA0A4UL))) +#define bM4_TMRA4_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422BA0B0UL))) +#define bM4_TMRA4_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422BA0B4UL))) +#define bM4_TMRA4_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422BA0B8UL))) +#define bM4_TMRA4_CCONR3_CAPMD (*((volatile unsigned int*)(0x422BA100UL))) +#define bM4_TMRA4_CCONR3_HICP0 (*((volatile unsigned int*)(0x422BA110UL))) +#define bM4_TMRA4_CCONR3_HICP1 (*((volatile unsigned int*)(0x422BA114UL))) +#define bM4_TMRA4_CCONR3_HICP2 (*((volatile unsigned int*)(0x422BA118UL))) +#define bM4_TMRA4_CCONR3_HICP3 (*((volatile unsigned int*)(0x422BA120UL))) +#define bM4_TMRA4_CCONR3_HICP4 (*((volatile unsigned int*)(0x422BA124UL))) +#define bM4_TMRA4_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422BA130UL))) +#define bM4_TMRA4_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422BA134UL))) +#define bM4_TMRA4_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422BA138UL))) +#define bM4_TMRA4_CCONR4_CAPMD (*((volatile unsigned int*)(0x422BA180UL))) +#define bM4_TMRA4_CCONR4_HICP0 (*((volatile unsigned int*)(0x422BA190UL))) +#define bM4_TMRA4_CCONR4_HICP1 (*((volatile unsigned int*)(0x422BA194UL))) +#define bM4_TMRA4_CCONR4_HICP2 (*((volatile unsigned int*)(0x422BA198UL))) +#define bM4_TMRA4_CCONR4_HICP3 (*((volatile unsigned int*)(0x422BA1A0UL))) +#define bM4_TMRA4_CCONR4_HICP4 (*((volatile unsigned int*)(0x422BA1A4UL))) +#define bM4_TMRA4_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422BA1B0UL))) +#define bM4_TMRA4_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422BA1B4UL))) +#define bM4_TMRA4_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422BA1B8UL))) +#define bM4_TMRA4_CCONR5_CAPMD (*((volatile unsigned int*)(0x422BA200UL))) +#define bM4_TMRA4_CCONR5_HICP0 (*((volatile unsigned int*)(0x422BA210UL))) +#define bM4_TMRA4_CCONR5_HICP1 (*((volatile unsigned int*)(0x422BA214UL))) +#define bM4_TMRA4_CCONR5_HICP2 (*((volatile unsigned int*)(0x422BA218UL))) +#define bM4_TMRA4_CCONR5_HICP3 (*((volatile unsigned int*)(0x422BA220UL))) +#define bM4_TMRA4_CCONR5_HICP4 (*((volatile unsigned int*)(0x422BA224UL))) +#define bM4_TMRA4_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422BA230UL))) +#define bM4_TMRA4_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422BA234UL))) +#define bM4_TMRA4_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422BA238UL))) +#define bM4_TMRA4_CCONR6_CAPMD (*((volatile unsigned int*)(0x422BA280UL))) +#define bM4_TMRA4_CCONR6_HICP0 (*((volatile unsigned int*)(0x422BA290UL))) +#define bM4_TMRA4_CCONR6_HICP1 (*((volatile unsigned int*)(0x422BA294UL))) +#define bM4_TMRA4_CCONR6_HICP2 (*((volatile unsigned int*)(0x422BA298UL))) +#define bM4_TMRA4_CCONR6_HICP3 (*((volatile unsigned int*)(0x422BA2A0UL))) +#define bM4_TMRA4_CCONR6_HICP4 (*((volatile unsigned int*)(0x422BA2A4UL))) +#define bM4_TMRA4_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422BA2B0UL))) +#define bM4_TMRA4_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422BA2B4UL))) +#define bM4_TMRA4_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422BA2B8UL))) +#define bM4_TMRA4_CCONR7_CAPMD (*((volatile unsigned int*)(0x422BA300UL))) +#define bM4_TMRA4_CCONR7_HICP0 (*((volatile unsigned int*)(0x422BA310UL))) +#define bM4_TMRA4_CCONR7_HICP1 (*((volatile unsigned int*)(0x422BA314UL))) +#define bM4_TMRA4_CCONR7_HICP2 (*((volatile unsigned int*)(0x422BA318UL))) +#define bM4_TMRA4_CCONR7_HICP3 (*((volatile unsigned int*)(0x422BA320UL))) +#define bM4_TMRA4_CCONR7_HICP4 (*((volatile unsigned int*)(0x422BA324UL))) +#define bM4_TMRA4_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422BA330UL))) +#define bM4_TMRA4_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422BA334UL))) +#define bM4_TMRA4_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422BA338UL))) +#define bM4_TMRA4_CCONR8_CAPMD (*((volatile unsigned int*)(0x422BA380UL))) +#define bM4_TMRA4_CCONR8_HICP0 (*((volatile unsigned int*)(0x422BA390UL))) +#define bM4_TMRA4_CCONR8_HICP1 (*((volatile unsigned int*)(0x422BA394UL))) +#define bM4_TMRA4_CCONR8_HICP2 (*((volatile unsigned int*)(0x422BA398UL))) +#define bM4_TMRA4_CCONR8_HICP3 (*((volatile unsigned int*)(0x422BA3A0UL))) +#define bM4_TMRA4_CCONR8_HICP4 (*((volatile unsigned int*)(0x422BA3A4UL))) +#define bM4_TMRA4_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422BA3B0UL))) +#define bM4_TMRA4_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422BA3B4UL))) +#define bM4_TMRA4_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422BA3B8UL))) +#define bM4_TMRA4_PCONR1_STAC0 (*((volatile unsigned int*)(0x422BA800UL))) +#define bM4_TMRA4_PCONR1_STAC1 (*((volatile unsigned int*)(0x422BA804UL))) +#define bM4_TMRA4_PCONR1_STPC0 (*((volatile unsigned int*)(0x422BA808UL))) +#define bM4_TMRA4_PCONR1_STPC1 (*((volatile unsigned int*)(0x422BA80CUL))) +#define bM4_TMRA4_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422BA810UL))) +#define bM4_TMRA4_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422BA814UL))) +#define bM4_TMRA4_PCONR1_PERC0 (*((volatile unsigned int*)(0x422BA818UL))) +#define bM4_TMRA4_PCONR1_PERC1 (*((volatile unsigned int*)(0x422BA81CUL))) +#define bM4_TMRA4_PCONR1_FORC0 (*((volatile unsigned int*)(0x422BA820UL))) +#define bM4_TMRA4_PCONR1_FORC1 (*((volatile unsigned int*)(0x422BA824UL))) +#define bM4_TMRA4_PCONR1_OUTEN (*((volatile unsigned int*)(0x422BA830UL))) +#define bM4_TMRA4_PCONR2_STAC0 (*((volatile unsigned int*)(0x422BA880UL))) +#define bM4_TMRA4_PCONR2_STAC1 (*((volatile unsigned int*)(0x422BA884UL))) +#define bM4_TMRA4_PCONR2_STPC0 (*((volatile unsigned int*)(0x422BA888UL))) +#define bM4_TMRA4_PCONR2_STPC1 (*((volatile unsigned int*)(0x422BA88CUL))) +#define bM4_TMRA4_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422BA890UL))) +#define bM4_TMRA4_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422BA894UL))) +#define bM4_TMRA4_PCONR2_PERC0 (*((volatile unsigned int*)(0x422BA898UL))) +#define bM4_TMRA4_PCONR2_PERC1 (*((volatile unsigned int*)(0x422BA89CUL))) +#define bM4_TMRA4_PCONR2_FORC0 (*((volatile unsigned int*)(0x422BA8A0UL))) +#define bM4_TMRA4_PCONR2_FORC1 (*((volatile unsigned int*)(0x422BA8A4UL))) +#define bM4_TMRA4_PCONR2_OUTEN (*((volatile unsigned int*)(0x422BA8B0UL))) +#define bM4_TMRA4_PCONR3_STAC0 (*((volatile unsigned int*)(0x422BA900UL))) +#define bM4_TMRA4_PCONR3_STAC1 (*((volatile unsigned int*)(0x422BA904UL))) +#define bM4_TMRA4_PCONR3_STPC0 (*((volatile unsigned int*)(0x422BA908UL))) +#define bM4_TMRA4_PCONR3_STPC1 (*((volatile unsigned int*)(0x422BA90CUL))) +#define bM4_TMRA4_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422BA910UL))) +#define bM4_TMRA4_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422BA914UL))) +#define bM4_TMRA4_PCONR3_PERC0 (*((volatile unsigned int*)(0x422BA918UL))) +#define bM4_TMRA4_PCONR3_PERC1 (*((volatile unsigned int*)(0x422BA91CUL))) +#define bM4_TMRA4_PCONR3_FORC0 (*((volatile unsigned int*)(0x422BA920UL))) +#define bM4_TMRA4_PCONR3_FORC1 (*((volatile unsigned int*)(0x422BA924UL))) +#define bM4_TMRA4_PCONR3_OUTEN (*((volatile unsigned int*)(0x422BA930UL))) +#define bM4_TMRA4_PCONR4_STAC0 (*((volatile unsigned int*)(0x422BA980UL))) +#define bM4_TMRA4_PCONR4_STAC1 (*((volatile unsigned int*)(0x422BA984UL))) +#define bM4_TMRA4_PCONR4_STPC0 (*((volatile unsigned int*)(0x422BA988UL))) +#define bM4_TMRA4_PCONR4_STPC1 (*((volatile unsigned int*)(0x422BA98CUL))) +#define bM4_TMRA4_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422BA990UL))) +#define bM4_TMRA4_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422BA994UL))) +#define bM4_TMRA4_PCONR4_PERC0 (*((volatile unsigned int*)(0x422BA998UL))) +#define bM4_TMRA4_PCONR4_PERC1 (*((volatile unsigned int*)(0x422BA99CUL))) +#define bM4_TMRA4_PCONR4_FORC0 (*((volatile unsigned int*)(0x422BA9A0UL))) +#define bM4_TMRA4_PCONR4_FORC1 (*((volatile unsigned int*)(0x422BA9A4UL))) +#define bM4_TMRA4_PCONR4_OUTEN (*((volatile unsigned int*)(0x422BA9B0UL))) +#define bM4_TMRA4_PCONR5_STAC0 (*((volatile unsigned int*)(0x422BAA00UL))) +#define bM4_TMRA4_PCONR5_STAC1 (*((volatile unsigned int*)(0x422BAA04UL))) +#define bM4_TMRA4_PCONR5_STPC0 (*((volatile unsigned int*)(0x422BAA08UL))) +#define bM4_TMRA4_PCONR5_STPC1 (*((volatile unsigned int*)(0x422BAA0CUL))) +#define bM4_TMRA4_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422BAA10UL))) +#define bM4_TMRA4_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422BAA14UL))) +#define bM4_TMRA4_PCONR5_PERC0 (*((volatile unsigned int*)(0x422BAA18UL))) +#define bM4_TMRA4_PCONR5_PERC1 (*((volatile unsigned int*)(0x422BAA1CUL))) +#define bM4_TMRA4_PCONR5_FORC0 (*((volatile unsigned int*)(0x422BAA20UL))) +#define bM4_TMRA4_PCONR5_FORC1 (*((volatile unsigned int*)(0x422BAA24UL))) +#define bM4_TMRA4_PCONR5_OUTEN (*((volatile unsigned int*)(0x422BAA30UL))) +#define bM4_TMRA4_PCONR6_STAC0 (*((volatile unsigned int*)(0x422BAA80UL))) +#define bM4_TMRA4_PCONR6_STAC1 (*((volatile unsigned int*)(0x422BAA84UL))) +#define bM4_TMRA4_PCONR6_STPC0 (*((volatile unsigned int*)(0x422BAA88UL))) +#define bM4_TMRA4_PCONR6_STPC1 (*((volatile unsigned int*)(0x422BAA8CUL))) +#define bM4_TMRA4_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422BAA90UL))) +#define bM4_TMRA4_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422BAA94UL))) +#define bM4_TMRA4_PCONR6_PERC0 (*((volatile unsigned int*)(0x422BAA98UL))) +#define bM4_TMRA4_PCONR6_PERC1 (*((volatile unsigned int*)(0x422BAA9CUL))) +#define bM4_TMRA4_PCONR6_FORC0 (*((volatile unsigned int*)(0x422BAAA0UL))) +#define bM4_TMRA4_PCONR6_FORC1 (*((volatile unsigned int*)(0x422BAAA4UL))) +#define bM4_TMRA4_PCONR6_OUTEN (*((volatile unsigned int*)(0x422BAAB0UL))) +#define bM4_TMRA4_PCONR7_STAC0 (*((volatile unsigned int*)(0x422BAB00UL))) +#define bM4_TMRA4_PCONR7_STAC1 (*((volatile unsigned int*)(0x422BAB04UL))) +#define bM4_TMRA4_PCONR7_STPC0 (*((volatile unsigned int*)(0x422BAB08UL))) +#define bM4_TMRA4_PCONR7_STPC1 (*((volatile unsigned int*)(0x422BAB0CUL))) +#define bM4_TMRA4_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422BAB10UL))) +#define bM4_TMRA4_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422BAB14UL))) +#define bM4_TMRA4_PCONR7_PERC0 (*((volatile unsigned int*)(0x422BAB18UL))) +#define bM4_TMRA4_PCONR7_PERC1 (*((volatile unsigned int*)(0x422BAB1CUL))) +#define bM4_TMRA4_PCONR7_FORC0 (*((volatile unsigned int*)(0x422BAB20UL))) +#define bM4_TMRA4_PCONR7_FORC1 (*((volatile unsigned int*)(0x422BAB24UL))) +#define bM4_TMRA4_PCONR7_OUTEN (*((volatile unsigned int*)(0x422BAB30UL))) +#define bM4_TMRA4_PCONR8_STAC0 (*((volatile unsigned int*)(0x422BAB80UL))) +#define bM4_TMRA4_PCONR8_STAC1 (*((volatile unsigned int*)(0x422BAB84UL))) +#define bM4_TMRA4_PCONR8_STPC0 (*((volatile unsigned int*)(0x422BAB88UL))) +#define bM4_TMRA4_PCONR8_STPC1 (*((volatile unsigned int*)(0x422BAB8CUL))) +#define bM4_TMRA4_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422BAB90UL))) +#define bM4_TMRA4_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422BAB94UL))) +#define bM4_TMRA4_PCONR8_PERC0 (*((volatile unsigned int*)(0x422BAB98UL))) +#define bM4_TMRA4_PCONR8_PERC1 (*((volatile unsigned int*)(0x422BAB9CUL))) +#define bM4_TMRA4_PCONR8_FORC0 (*((volatile unsigned int*)(0x422BABA0UL))) +#define bM4_TMRA4_PCONR8_FORC1 (*((volatile unsigned int*)(0x422BABA4UL))) +#define bM4_TMRA4_PCONR8_OUTEN (*((volatile unsigned int*)(0x422BABB0UL))) +#define bM4_TMRA5_CNTER_CNT0 (*((volatile unsigned int*)(0x422C0000UL))) +#define bM4_TMRA5_CNTER_CNT1 (*((volatile unsigned int*)(0x422C0004UL))) +#define bM4_TMRA5_CNTER_CNT2 (*((volatile unsigned int*)(0x422C0008UL))) +#define bM4_TMRA5_CNTER_CNT3 (*((volatile unsigned int*)(0x422C000CUL))) +#define bM4_TMRA5_CNTER_CNT4 (*((volatile unsigned int*)(0x422C0010UL))) +#define bM4_TMRA5_CNTER_CNT5 (*((volatile unsigned int*)(0x422C0014UL))) +#define bM4_TMRA5_CNTER_CNT6 (*((volatile unsigned int*)(0x422C0018UL))) +#define bM4_TMRA5_CNTER_CNT7 (*((volatile unsigned int*)(0x422C001CUL))) +#define bM4_TMRA5_CNTER_CNT8 (*((volatile unsigned int*)(0x422C0020UL))) +#define bM4_TMRA5_CNTER_CNT9 (*((volatile unsigned int*)(0x422C0024UL))) +#define bM4_TMRA5_CNTER_CNT10 (*((volatile unsigned int*)(0x422C0028UL))) +#define bM4_TMRA5_CNTER_CNT11 (*((volatile unsigned int*)(0x422C002CUL))) +#define bM4_TMRA5_CNTER_CNT12 (*((volatile unsigned int*)(0x422C0030UL))) +#define bM4_TMRA5_CNTER_CNT13 (*((volatile unsigned int*)(0x422C0034UL))) +#define bM4_TMRA5_CNTER_CNT14 (*((volatile unsigned int*)(0x422C0038UL))) +#define bM4_TMRA5_CNTER_CNT15 (*((volatile unsigned int*)(0x422C003CUL))) +#define bM4_TMRA5_PERAR_PER0 (*((volatile unsigned int*)(0x422C0080UL))) +#define bM4_TMRA5_PERAR_PER1 (*((volatile unsigned int*)(0x422C0084UL))) +#define bM4_TMRA5_PERAR_PER2 (*((volatile unsigned int*)(0x422C0088UL))) +#define bM4_TMRA5_PERAR_PER3 (*((volatile unsigned int*)(0x422C008CUL))) +#define bM4_TMRA5_PERAR_PER4 (*((volatile unsigned int*)(0x422C0090UL))) +#define bM4_TMRA5_PERAR_PER5 (*((volatile unsigned int*)(0x422C0094UL))) +#define bM4_TMRA5_PERAR_PER6 (*((volatile unsigned int*)(0x422C0098UL))) +#define bM4_TMRA5_PERAR_PER7 (*((volatile unsigned int*)(0x422C009CUL))) +#define bM4_TMRA5_PERAR_PER8 (*((volatile unsigned int*)(0x422C00A0UL))) +#define bM4_TMRA5_PERAR_PER9 (*((volatile unsigned int*)(0x422C00A4UL))) +#define bM4_TMRA5_PERAR_PER10 (*((volatile unsigned int*)(0x422C00A8UL))) +#define bM4_TMRA5_PERAR_PER11 (*((volatile unsigned int*)(0x422C00ACUL))) +#define bM4_TMRA5_PERAR_PER12 (*((volatile unsigned int*)(0x422C00B0UL))) +#define bM4_TMRA5_PERAR_PER13 (*((volatile unsigned int*)(0x422C00B4UL))) +#define bM4_TMRA5_PERAR_PER14 (*((volatile unsigned int*)(0x422C00B8UL))) +#define bM4_TMRA5_PERAR_PER15 (*((volatile unsigned int*)(0x422C00BCUL))) +#define bM4_TMRA5_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422C0800UL))) +#define bM4_TMRA5_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422C0804UL))) +#define bM4_TMRA5_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422C0808UL))) +#define bM4_TMRA5_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422C080CUL))) +#define bM4_TMRA5_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422C0810UL))) +#define bM4_TMRA5_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422C0814UL))) +#define bM4_TMRA5_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422C0818UL))) +#define bM4_TMRA5_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422C081CUL))) +#define bM4_TMRA5_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422C0820UL))) +#define bM4_TMRA5_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422C0824UL))) +#define bM4_TMRA5_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422C0828UL))) +#define bM4_TMRA5_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422C082CUL))) +#define bM4_TMRA5_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422C0830UL))) +#define bM4_TMRA5_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422C0834UL))) +#define bM4_TMRA5_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422C0838UL))) +#define bM4_TMRA5_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422C083CUL))) +#define bM4_TMRA5_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422C0880UL))) +#define bM4_TMRA5_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422C0884UL))) +#define bM4_TMRA5_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422C0888UL))) +#define bM4_TMRA5_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422C088CUL))) +#define bM4_TMRA5_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422C0890UL))) +#define bM4_TMRA5_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422C0894UL))) +#define bM4_TMRA5_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422C0898UL))) +#define bM4_TMRA5_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422C089CUL))) +#define bM4_TMRA5_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422C08A0UL))) +#define bM4_TMRA5_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422C08A4UL))) +#define bM4_TMRA5_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422C08A8UL))) +#define bM4_TMRA5_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422C08ACUL))) +#define bM4_TMRA5_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422C08B0UL))) +#define bM4_TMRA5_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422C08B4UL))) +#define bM4_TMRA5_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422C08B8UL))) +#define bM4_TMRA5_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422C08BCUL))) +#define bM4_TMRA5_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422C0900UL))) +#define bM4_TMRA5_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422C0904UL))) +#define bM4_TMRA5_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422C0908UL))) +#define bM4_TMRA5_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422C090CUL))) +#define bM4_TMRA5_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422C0910UL))) +#define bM4_TMRA5_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422C0914UL))) +#define bM4_TMRA5_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422C0918UL))) +#define bM4_TMRA5_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422C091CUL))) +#define bM4_TMRA5_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422C0920UL))) +#define bM4_TMRA5_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422C0924UL))) +#define bM4_TMRA5_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422C0928UL))) +#define bM4_TMRA5_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422C092CUL))) +#define bM4_TMRA5_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422C0930UL))) +#define bM4_TMRA5_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422C0934UL))) +#define bM4_TMRA5_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422C0938UL))) +#define bM4_TMRA5_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422C093CUL))) +#define bM4_TMRA5_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422C0980UL))) +#define bM4_TMRA5_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422C0984UL))) +#define bM4_TMRA5_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422C0988UL))) +#define bM4_TMRA5_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422C098CUL))) +#define bM4_TMRA5_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422C0990UL))) +#define bM4_TMRA5_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422C0994UL))) +#define bM4_TMRA5_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422C0998UL))) +#define bM4_TMRA5_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422C099CUL))) +#define bM4_TMRA5_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422C09A0UL))) +#define bM4_TMRA5_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422C09A4UL))) +#define bM4_TMRA5_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422C09A8UL))) +#define bM4_TMRA5_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422C09ACUL))) +#define bM4_TMRA5_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422C09B0UL))) +#define bM4_TMRA5_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422C09B4UL))) +#define bM4_TMRA5_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422C09B8UL))) +#define bM4_TMRA5_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422C09BCUL))) +#define bM4_TMRA5_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422C0A00UL))) +#define bM4_TMRA5_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422C0A04UL))) +#define bM4_TMRA5_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422C0A08UL))) +#define bM4_TMRA5_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422C0A0CUL))) +#define bM4_TMRA5_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422C0A10UL))) +#define bM4_TMRA5_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422C0A14UL))) +#define bM4_TMRA5_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422C0A18UL))) +#define bM4_TMRA5_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422C0A1CUL))) +#define bM4_TMRA5_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422C0A20UL))) +#define bM4_TMRA5_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422C0A24UL))) +#define bM4_TMRA5_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422C0A28UL))) +#define bM4_TMRA5_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422C0A2CUL))) +#define bM4_TMRA5_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422C0A30UL))) +#define bM4_TMRA5_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422C0A34UL))) +#define bM4_TMRA5_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422C0A38UL))) +#define bM4_TMRA5_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422C0A3CUL))) +#define bM4_TMRA5_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422C0A80UL))) +#define bM4_TMRA5_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422C0A84UL))) +#define bM4_TMRA5_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422C0A88UL))) +#define bM4_TMRA5_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422C0A8CUL))) +#define bM4_TMRA5_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422C0A90UL))) +#define bM4_TMRA5_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422C0A94UL))) +#define bM4_TMRA5_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422C0A98UL))) +#define bM4_TMRA5_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422C0A9CUL))) +#define bM4_TMRA5_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422C0AA0UL))) +#define bM4_TMRA5_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422C0AA4UL))) +#define bM4_TMRA5_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422C0AA8UL))) +#define bM4_TMRA5_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422C0AACUL))) +#define bM4_TMRA5_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422C0AB0UL))) +#define bM4_TMRA5_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422C0AB4UL))) +#define bM4_TMRA5_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422C0AB8UL))) +#define bM4_TMRA5_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422C0ABCUL))) +#define bM4_TMRA5_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422C0B00UL))) +#define bM4_TMRA5_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422C0B04UL))) +#define bM4_TMRA5_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422C0B08UL))) +#define bM4_TMRA5_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422C0B0CUL))) +#define bM4_TMRA5_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422C0B10UL))) +#define bM4_TMRA5_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422C0B14UL))) +#define bM4_TMRA5_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422C0B18UL))) +#define bM4_TMRA5_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422C0B1CUL))) +#define bM4_TMRA5_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422C0B20UL))) +#define bM4_TMRA5_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422C0B24UL))) +#define bM4_TMRA5_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422C0B28UL))) +#define bM4_TMRA5_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422C0B2CUL))) +#define bM4_TMRA5_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422C0B30UL))) +#define bM4_TMRA5_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422C0B34UL))) +#define bM4_TMRA5_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422C0B38UL))) +#define bM4_TMRA5_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422C0B3CUL))) +#define bM4_TMRA5_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422C0B80UL))) +#define bM4_TMRA5_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422C0B84UL))) +#define bM4_TMRA5_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422C0B88UL))) +#define bM4_TMRA5_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422C0B8CUL))) +#define bM4_TMRA5_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422C0B90UL))) +#define bM4_TMRA5_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422C0B94UL))) +#define bM4_TMRA5_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422C0B98UL))) +#define bM4_TMRA5_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422C0B9CUL))) +#define bM4_TMRA5_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422C0BA0UL))) +#define bM4_TMRA5_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422C0BA4UL))) +#define bM4_TMRA5_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422C0BA8UL))) +#define bM4_TMRA5_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422C0BACUL))) +#define bM4_TMRA5_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422C0BB0UL))) +#define bM4_TMRA5_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422C0BB4UL))) +#define bM4_TMRA5_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422C0BB8UL))) +#define bM4_TMRA5_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422C0BBCUL))) +#define bM4_TMRA5_BCSTR_START (*((volatile unsigned int*)(0x422C1000UL))) +#define bM4_TMRA5_BCSTR_DIR (*((volatile unsigned int*)(0x422C1004UL))) +#define bM4_TMRA5_BCSTR_MODE (*((volatile unsigned int*)(0x422C1008UL))) +#define bM4_TMRA5_BCSTR_SYNST (*((volatile unsigned int*)(0x422C100CUL))) +#define bM4_TMRA5_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422C1010UL))) +#define bM4_TMRA5_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422C1014UL))) +#define bM4_TMRA5_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422C1018UL))) +#define bM4_TMRA5_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422C101CUL))) +#define bM4_TMRA5_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422C1030UL))) +#define bM4_TMRA5_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422C1034UL))) +#define bM4_TMRA5_BCSTR_OVFF (*((volatile unsigned int*)(0x422C1038UL))) +#define bM4_TMRA5_BCSTR_UDFF (*((volatile unsigned int*)(0x422C103CUL))) +#define bM4_TMRA5_HCONR_HSTA0 (*((volatile unsigned int*)(0x422C1080UL))) +#define bM4_TMRA5_HCONR_HSTA1 (*((volatile unsigned int*)(0x422C1084UL))) +#define bM4_TMRA5_HCONR_HSTA2 (*((volatile unsigned int*)(0x422C1088UL))) +#define bM4_TMRA5_HCONR_HSTP0 (*((volatile unsigned int*)(0x422C1090UL))) +#define bM4_TMRA5_HCONR_HSTP1 (*((volatile unsigned int*)(0x422C1094UL))) +#define bM4_TMRA5_HCONR_HSTP2 (*((volatile unsigned int*)(0x422C1098UL))) +#define bM4_TMRA5_HCONR_HCLE0 (*((volatile unsigned int*)(0x422C10A0UL))) +#define bM4_TMRA5_HCONR_HCLE1 (*((volatile unsigned int*)(0x422C10A4UL))) +#define bM4_TMRA5_HCONR_HCLE2 (*((volatile unsigned int*)(0x422C10A8UL))) +#define bM4_TMRA5_HCONR_HCLE3 (*((volatile unsigned int*)(0x422C10B0UL))) +#define bM4_TMRA5_HCONR_HCLE4 (*((volatile unsigned int*)(0x422C10B4UL))) +#define bM4_TMRA5_HCONR_HCLE5 (*((volatile unsigned int*)(0x422C10B8UL))) +#define bM4_TMRA5_HCONR_HCLE6 (*((volatile unsigned int*)(0x422C10BCUL))) +#define bM4_TMRA5_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422C1100UL))) +#define bM4_TMRA5_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422C1104UL))) +#define bM4_TMRA5_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422C1108UL))) +#define bM4_TMRA5_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422C110CUL))) +#define bM4_TMRA5_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422C1110UL))) +#define bM4_TMRA5_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422C1114UL))) +#define bM4_TMRA5_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422C1118UL))) +#define bM4_TMRA5_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422C111CUL))) +#define bM4_TMRA5_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422C1120UL))) +#define bM4_TMRA5_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422C1124UL))) +#define bM4_TMRA5_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422C1128UL))) +#define bM4_TMRA5_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422C112CUL))) +#define bM4_TMRA5_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422C1130UL))) +#define bM4_TMRA5_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422C1180UL))) +#define bM4_TMRA5_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422C1184UL))) +#define bM4_TMRA5_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422C1188UL))) +#define bM4_TMRA5_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422C118CUL))) +#define bM4_TMRA5_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422C1190UL))) +#define bM4_TMRA5_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422C1194UL))) +#define bM4_TMRA5_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422C1198UL))) +#define bM4_TMRA5_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422C119CUL))) +#define bM4_TMRA5_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422C11A0UL))) +#define bM4_TMRA5_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422C11A4UL))) +#define bM4_TMRA5_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422C11A8UL))) +#define bM4_TMRA5_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422C11ACUL))) +#define bM4_TMRA5_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422C11B0UL))) +#define bM4_TMRA5_ICONR_ITEN1 (*((volatile unsigned int*)(0x422C1200UL))) +#define bM4_TMRA5_ICONR_ITEN2 (*((volatile unsigned int*)(0x422C1204UL))) +#define bM4_TMRA5_ICONR_ITEN3 (*((volatile unsigned int*)(0x422C1208UL))) +#define bM4_TMRA5_ICONR_ITEN4 (*((volatile unsigned int*)(0x422C120CUL))) +#define bM4_TMRA5_ICONR_ITEN5 (*((volatile unsigned int*)(0x422C1210UL))) +#define bM4_TMRA5_ICONR_ITEN6 (*((volatile unsigned int*)(0x422C1214UL))) +#define bM4_TMRA5_ICONR_ITEN7 (*((volatile unsigned int*)(0x422C1218UL))) +#define bM4_TMRA5_ICONR_ITEN8 (*((volatile unsigned int*)(0x422C121CUL))) +#define bM4_TMRA5_ECONR_ETEN1 (*((volatile unsigned int*)(0x422C1280UL))) +#define bM4_TMRA5_ECONR_ETEN2 (*((volatile unsigned int*)(0x422C1284UL))) +#define bM4_TMRA5_ECONR_ETEN3 (*((volatile unsigned int*)(0x422C1288UL))) +#define bM4_TMRA5_ECONR_ETEN4 (*((volatile unsigned int*)(0x422C128CUL))) +#define bM4_TMRA5_ECONR_ETEN5 (*((volatile unsigned int*)(0x422C1290UL))) +#define bM4_TMRA5_ECONR_ETEN6 (*((volatile unsigned int*)(0x422C1294UL))) +#define bM4_TMRA5_ECONR_ETEN7 (*((volatile unsigned int*)(0x422C1298UL))) +#define bM4_TMRA5_ECONR_ETEN8 (*((volatile unsigned int*)(0x422C129CUL))) +#define bM4_TMRA5_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422C1300UL))) +#define bM4_TMRA5_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422C1304UL))) +#define bM4_TMRA5_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422C1308UL))) +#define bM4_TMRA5_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422C1320UL))) +#define bM4_TMRA5_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422C1324UL))) +#define bM4_TMRA5_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422C1328UL))) +#define bM4_TMRA5_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422C1330UL))) +#define bM4_TMRA5_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422C1334UL))) +#define bM4_TMRA5_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422C1338UL))) +#define bM4_TMRA5_STFLR_CMPF1 (*((volatile unsigned int*)(0x422C1380UL))) +#define bM4_TMRA5_STFLR_CMPF2 (*((volatile unsigned int*)(0x422C1384UL))) +#define bM4_TMRA5_STFLR_CMPF3 (*((volatile unsigned int*)(0x422C1388UL))) +#define bM4_TMRA5_STFLR_CMPF4 (*((volatile unsigned int*)(0x422C138CUL))) +#define bM4_TMRA5_STFLR_CMPF5 (*((volatile unsigned int*)(0x422C1390UL))) +#define bM4_TMRA5_STFLR_CMPF6 (*((volatile unsigned int*)(0x422C1394UL))) +#define bM4_TMRA5_STFLR_CMPF7 (*((volatile unsigned int*)(0x422C1398UL))) +#define bM4_TMRA5_STFLR_CMPF8 (*((volatile unsigned int*)(0x422C139CUL))) +#define bM4_TMRA5_BCONR1_BEN (*((volatile unsigned int*)(0x422C1800UL))) +#define bM4_TMRA5_BCONR1_BSE0 (*((volatile unsigned int*)(0x422C1804UL))) +#define bM4_TMRA5_BCONR1_BSE1 (*((volatile unsigned int*)(0x422C1808UL))) +#define bM4_TMRA5_BCONR2_BEN (*((volatile unsigned int*)(0x422C1900UL))) +#define bM4_TMRA5_BCONR2_BSE0 (*((volatile unsigned int*)(0x422C1904UL))) +#define bM4_TMRA5_BCONR2_BSE1 (*((volatile unsigned int*)(0x422C1908UL))) +#define bM4_TMRA5_BCONR3_BEN (*((volatile unsigned int*)(0x422C1A00UL))) +#define bM4_TMRA5_BCONR3_BSE0 (*((volatile unsigned int*)(0x422C1A04UL))) +#define bM4_TMRA5_BCONR3_BSE1 (*((volatile unsigned int*)(0x422C1A08UL))) +#define bM4_TMRA5_BCONR4_BEN (*((volatile unsigned int*)(0x422C1B00UL))) +#define bM4_TMRA5_BCONR4_BSE0 (*((volatile unsigned int*)(0x422C1B04UL))) +#define bM4_TMRA5_BCONR4_BSE1 (*((volatile unsigned int*)(0x422C1B08UL))) +#define bM4_TMRA5_CCONR1_CAPMD (*((volatile unsigned int*)(0x422C2000UL))) +#define bM4_TMRA5_CCONR1_HICP0 (*((volatile unsigned int*)(0x422C2010UL))) +#define bM4_TMRA5_CCONR1_HICP1 (*((volatile unsigned int*)(0x422C2014UL))) +#define bM4_TMRA5_CCONR1_HICP2 (*((volatile unsigned int*)(0x422C2018UL))) +#define bM4_TMRA5_CCONR1_HICP3 (*((volatile unsigned int*)(0x422C2020UL))) +#define bM4_TMRA5_CCONR1_HICP4 (*((volatile unsigned int*)(0x422C2024UL))) +#define bM4_TMRA5_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422C2030UL))) +#define bM4_TMRA5_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422C2034UL))) +#define bM4_TMRA5_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422C2038UL))) +#define bM4_TMRA5_CCONR2_CAPMD (*((volatile unsigned int*)(0x422C2080UL))) +#define bM4_TMRA5_CCONR2_HICP0 (*((volatile unsigned int*)(0x422C2090UL))) +#define bM4_TMRA5_CCONR2_HICP1 (*((volatile unsigned int*)(0x422C2094UL))) +#define bM4_TMRA5_CCONR2_HICP2 (*((volatile unsigned int*)(0x422C2098UL))) +#define bM4_TMRA5_CCONR2_HICP3 (*((volatile unsigned int*)(0x422C20A0UL))) +#define bM4_TMRA5_CCONR2_HICP4 (*((volatile unsigned int*)(0x422C20A4UL))) +#define bM4_TMRA5_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422C20B0UL))) +#define bM4_TMRA5_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422C20B4UL))) +#define bM4_TMRA5_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422C20B8UL))) +#define bM4_TMRA5_CCONR3_CAPMD (*((volatile unsigned int*)(0x422C2100UL))) +#define bM4_TMRA5_CCONR3_HICP0 (*((volatile unsigned int*)(0x422C2110UL))) +#define bM4_TMRA5_CCONR3_HICP1 (*((volatile unsigned int*)(0x422C2114UL))) +#define bM4_TMRA5_CCONR3_HICP2 (*((volatile unsigned int*)(0x422C2118UL))) +#define bM4_TMRA5_CCONR3_HICP3 (*((volatile unsigned int*)(0x422C2120UL))) +#define bM4_TMRA5_CCONR3_HICP4 (*((volatile unsigned int*)(0x422C2124UL))) +#define bM4_TMRA5_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422C2130UL))) +#define bM4_TMRA5_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422C2134UL))) +#define bM4_TMRA5_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422C2138UL))) +#define bM4_TMRA5_CCONR4_CAPMD (*((volatile unsigned int*)(0x422C2180UL))) +#define bM4_TMRA5_CCONR4_HICP0 (*((volatile unsigned int*)(0x422C2190UL))) +#define bM4_TMRA5_CCONR4_HICP1 (*((volatile unsigned int*)(0x422C2194UL))) +#define bM4_TMRA5_CCONR4_HICP2 (*((volatile unsigned int*)(0x422C2198UL))) +#define bM4_TMRA5_CCONR4_HICP3 (*((volatile unsigned int*)(0x422C21A0UL))) +#define bM4_TMRA5_CCONR4_HICP4 (*((volatile unsigned int*)(0x422C21A4UL))) +#define bM4_TMRA5_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422C21B0UL))) +#define bM4_TMRA5_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422C21B4UL))) +#define bM4_TMRA5_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422C21B8UL))) +#define bM4_TMRA5_CCONR5_CAPMD (*((volatile unsigned int*)(0x422C2200UL))) +#define bM4_TMRA5_CCONR5_HICP0 (*((volatile unsigned int*)(0x422C2210UL))) +#define bM4_TMRA5_CCONR5_HICP1 (*((volatile unsigned int*)(0x422C2214UL))) +#define bM4_TMRA5_CCONR5_HICP2 (*((volatile unsigned int*)(0x422C2218UL))) +#define bM4_TMRA5_CCONR5_HICP3 (*((volatile unsigned int*)(0x422C2220UL))) +#define bM4_TMRA5_CCONR5_HICP4 (*((volatile unsigned int*)(0x422C2224UL))) +#define bM4_TMRA5_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422C2230UL))) +#define bM4_TMRA5_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422C2234UL))) +#define bM4_TMRA5_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422C2238UL))) +#define bM4_TMRA5_CCONR6_CAPMD (*((volatile unsigned int*)(0x422C2280UL))) +#define bM4_TMRA5_CCONR6_HICP0 (*((volatile unsigned int*)(0x422C2290UL))) +#define bM4_TMRA5_CCONR6_HICP1 (*((volatile unsigned int*)(0x422C2294UL))) +#define bM4_TMRA5_CCONR6_HICP2 (*((volatile unsigned int*)(0x422C2298UL))) +#define bM4_TMRA5_CCONR6_HICP3 (*((volatile unsigned int*)(0x422C22A0UL))) +#define bM4_TMRA5_CCONR6_HICP4 (*((volatile unsigned int*)(0x422C22A4UL))) +#define bM4_TMRA5_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422C22B0UL))) +#define bM4_TMRA5_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422C22B4UL))) +#define bM4_TMRA5_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422C22B8UL))) +#define bM4_TMRA5_CCONR7_CAPMD (*((volatile unsigned int*)(0x422C2300UL))) +#define bM4_TMRA5_CCONR7_HICP0 (*((volatile unsigned int*)(0x422C2310UL))) +#define bM4_TMRA5_CCONR7_HICP1 (*((volatile unsigned int*)(0x422C2314UL))) +#define bM4_TMRA5_CCONR7_HICP2 (*((volatile unsigned int*)(0x422C2318UL))) +#define bM4_TMRA5_CCONR7_HICP3 (*((volatile unsigned int*)(0x422C2320UL))) +#define bM4_TMRA5_CCONR7_HICP4 (*((volatile unsigned int*)(0x422C2324UL))) +#define bM4_TMRA5_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422C2330UL))) +#define bM4_TMRA5_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422C2334UL))) +#define bM4_TMRA5_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422C2338UL))) +#define bM4_TMRA5_CCONR8_CAPMD (*((volatile unsigned int*)(0x422C2380UL))) +#define bM4_TMRA5_CCONR8_HICP0 (*((volatile unsigned int*)(0x422C2390UL))) +#define bM4_TMRA5_CCONR8_HICP1 (*((volatile unsigned int*)(0x422C2394UL))) +#define bM4_TMRA5_CCONR8_HICP2 (*((volatile unsigned int*)(0x422C2398UL))) +#define bM4_TMRA5_CCONR8_HICP3 (*((volatile unsigned int*)(0x422C23A0UL))) +#define bM4_TMRA5_CCONR8_HICP4 (*((volatile unsigned int*)(0x422C23A4UL))) +#define bM4_TMRA5_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422C23B0UL))) +#define bM4_TMRA5_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422C23B4UL))) +#define bM4_TMRA5_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422C23B8UL))) +#define bM4_TMRA5_PCONR1_STAC0 (*((volatile unsigned int*)(0x422C2800UL))) +#define bM4_TMRA5_PCONR1_STAC1 (*((volatile unsigned int*)(0x422C2804UL))) +#define bM4_TMRA5_PCONR1_STPC0 (*((volatile unsigned int*)(0x422C2808UL))) +#define bM4_TMRA5_PCONR1_STPC1 (*((volatile unsigned int*)(0x422C280CUL))) +#define bM4_TMRA5_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422C2810UL))) +#define bM4_TMRA5_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422C2814UL))) +#define bM4_TMRA5_PCONR1_PERC0 (*((volatile unsigned int*)(0x422C2818UL))) +#define bM4_TMRA5_PCONR1_PERC1 (*((volatile unsigned int*)(0x422C281CUL))) +#define bM4_TMRA5_PCONR1_FORC0 (*((volatile unsigned int*)(0x422C2820UL))) +#define bM4_TMRA5_PCONR1_FORC1 (*((volatile unsigned int*)(0x422C2824UL))) +#define bM4_TMRA5_PCONR1_OUTEN (*((volatile unsigned int*)(0x422C2830UL))) +#define bM4_TMRA5_PCONR2_STAC0 (*((volatile unsigned int*)(0x422C2880UL))) +#define bM4_TMRA5_PCONR2_STAC1 (*((volatile unsigned int*)(0x422C2884UL))) +#define bM4_TMRA5_PCONR2_STPC0 (*((volatile unsigned int*)(0x422C2888UL))) +#define bM4_TMRA5_PCONR2_STPC1 (*((volatile unsigned int*)(0x422C288CUL))) +#define bM4_TMRA5_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422C2890UL))) +#define bM4_TMRA5_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422C2894UL))) +#define bM4_TMRA5_PCONR2_PERC0 (*((volatile unsigned int*)(0x422C2898UL))) +#define bM4_TMRA5_PCONR2_PERC1 (*((volatile unsigned int*)(0x422C289CUL))) +#define bM4_TMRA5_PCONR2_FORC0 (*((volatile unsigned int*)(0x422C28A0UL))) +#define bM4_TMRA5_PCONR2_FORC1 (*((volatile unsigned int*)(0x422C28A4UL))) +#define bM4_TMRA5_PCONR2_OUTEN (*((volatile unsigned int*)(0x422C28B0UL))) +#define bM4_TMRA5_PCONR3_STAC0 (*((volatile unsigned int*)(0x422C2900UL))) +#define bM4_TMRA5_PCONR3_STAC1 (*((volatile unsigned int*)(0x422C2904UL))) +#define bM4_TMRA5_PCONR3_STPC0 (*((volatile unsigned int*)(0x422C2908UL))) +#define bM4_TMRA5_PCONR3_STPC1 (*((volatile unsigned int*)(0x422C290CUL))) +#define bM4_TMRA5_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422C2910UL))) +#define bM4_TMRA5_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422C2914UL))) +#define bM4_TMRA5_PCONR3_PERC0 (*((volatile unsigned int*)(0x422C2918UL))) +#define bM4_TMRA5_PCONR3_PERC1 (*((volatile unsigned int*)(0x422C291CUL))) +#define bM4_TMRA5_PCONR3_FORC0 (*((volatile unsigned int*)(0x422C2920UL))) +#define bM4_TMRA5_PCONR3_FORC1 (*((volatile unsigned int*)(0x422C2924UL))) +#define bM4_TMRA5_PCONR3_OUTEN (*((volatile unsigned int*)(0x422C2930UL))) +#define bM4_TMRA5_PCONR4_STAC0 (*((volatile unsigned int*)(0x422C2980UL))) +#define bM4_TMRA5_PCONR4_STAC1 (*((volatile unsigned int*)(0x422C2984UL))) +#define bM4_TMRA5_PCONR4_STPC0 (*((volatile unsigned int*)(0x422C2988UL))) +#define bM4_TMRA5_PCONR4_STPC1 (*((volatile unsigned int*)(0x422C298CUL))) +#define bM4_TMRA5_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422C2990UL))) +#define bM4_TMRA5_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422C2994UL))) +#define bM4_TMRA5_PCONR4_PERC0 (*((volatile unsigned int*)(0x422C2998UL))) +#define bM4_TMRA5_PCONR4_PERC1 (*((volatile unsigned int*)(0x422C299CUL))) +#define bM4_TMRA5_PCONR4_FORC0 (*((volatile unsigned int*)(0x422C29A0UL))) +#define bM4_TMRA5_PCONR4_FORC1 (*((volatile unsigned int*)(0x422C29A4UL))) +#define bM4_TMRA5_PCONR4_OUTEN (*((volatile unsigned int*)(0x422C29B0UL))) +#define bM4_TMRA5_PCONR5_STAC0 (*((volatile unsigned int*)(0x422C2A00UL))) +#define bM4_TMRA5_PCONR5_STAC1 (*((volatile unsigned int*)(0x422C2A04UL))) +#define bM4_TMRA5_PCONR5_STPC0 (*((volatile unsigned int*)(0x422C2A08UL))) +#define bM4_TMRA5_PCONR5_STPC1 (*((volatile unsigned int*)(0x422C2A0CUL))) +#define bM4_TMRA5_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422C2A10UL))) +#define bM4_TMRA5_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422C2A14UL))) +#define bM4_TMRA5_PCONR5_PERC0 (*((volatile unsigned int*)(0x422C2A18UL))) +#define bM4_TMRA5_PCONR5_PERC1 (*((volatile unsigned int*)(0x422C2A1CUL))) +#define bM4_TMRA5_PCONR5_FORC0 (*((volatile unsigned int*)(0x422C2A20UL))) +#define bM4_TMRA5_PCONR5_FORC1 (*((volatile unsigned int*)(0x422C2A24UL))) +#define bM4_TMRA5_PCONR5_OUTEN (*((volatile unsigned int*)(0x422C2A30UL))) +#define bM4_TMRA5_PCONR6_STAC0 (*((volatile unsigned int*)(0x422C2A80UL))) +#define bM4_TMRA5_PCONR6_STAC1 (*((volatile unsigned int*)(0x422C2A84UL))) +#define bM4_TMRA5_PCONR6_STPC0 (*((volatile unsigned int*)(0x422C2A88UL))) +#define bM4_TMRA5_PCONR6_STPC1 (*((volatile unsigned int*)(0x422C2A8CUL))) +#define bM4_TMRA5_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422C2A90UL))) +#define bM4_TMRA5_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422C2A94UL))) +#define bM4_TMRA5_PCONR6_PERC0 (*((volatile unsigned int*)(0x422C2A98UL))) +#define bM4_TMRA5_PCONR6_PERC1 (*((volatile unsigned int*)(0x422C2A9CUL))) +#define bM4_TMRA5_PCONR6_FORC0 (*((volatile unsigned int*)(0x422C2AA0UL))) +#define bM4_TMRA5_PCONR6_FORC1 (*((volatile unsigned int*)(0x422C2AA4UL))) +#define bM4_TMRA5_PCONR6_OUTEN (*((volatile unsigned int*)(0x422C2AB0UL))) +#define bM4_TMRA5_PCONR7_STAC0 (*((volatile unsigned int*)(0x422C2B00UL))) +#define bM4_TMRA5_PCONR7_STAC1 (*((volatile unsigned int*)(0x422C2B04UL))) +#define bM4_TMRA5_PCONR7_STPC0 (*((volatile unsigned int*)(0x422C2B08UL))) +#define bM4_TMRA5_PCONR7_STPC1 (*((volatile unsigned int*)(0x422C2B0CUL))) +#define bM4_TMRA5_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422C2B10UL))) +#define bM4_TMRA5_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422C2B14UL))) +#define bM4_TMRA5_PCONR7_PERC0 (*((volatile unsigned int*)(0x422C2B18UL))) +#define bM4_TMRA5_PCONR7_PERC1 (*((volatile unsigned int*)(0x422C2B1CUL))) +#define bM4_TMRA5_PCONR7_FORC0 (*((volatile unsigned int*)(0x422C2B20UL))) +#define bM4_TMRA5_PCONR7_FORC1 (*((volatile unsigned int*)(0x422C2B24UL))) +#define bM4_TMRA5_PCONR7_OUTEN (*((volatile unsigned int*)(0x422C2B30UL))) +#define bM4_TMRA5_PCONR8_STAC0 (*((volatile unsigned int*)(0x422C2B80UL))) +#define bM4_TMRA5_PCONR8_STAC1 (*((volatile unsigned int*)(0x422C2B84UL))) +#define bM4_TMRA5_PCONR8_STPC0 (*((volatile unsigned int*)(0x422C2B88UL))) +#define bM4_TMRA5_PCONR8_STPC1 (*((volatile unsigned int*)(0x422C2B8CUL))) +#define bM4_TMRA5_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422C2B90UL))) +#define bM4_TMRA5_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422C2B94UL))) +#define bM4_TMRA5_PCONR8_PERC0 (*((volatile unsigned int*)(0x422C2B98UL))) +#define bM4_TMRA5_PCONR8_PERC1 (*((volatile unsigned int*)(0x422C2B9CUL))) +#define bM4_TMRA5_PCONR8_FORC0 (*((volatile unsigned int*)(0x422C2BA0UL))) +#define bM4_TMRA5_PCONR8_FORC1 (*((volatile unsigned int*)(0x422C2BA4UL))) +#define bM4_TMRA5_PCONR8_OUTEN (*((volatile unsigned int*)(0x422C2BB0UL))) +#define bM4_TMRA6_CNTER_CNT0 (*((volatile unsigned int*)(0x422C8000UL))) +#define bM4_TMRA6_CNTER_CNT1 (*((volatile unsigned int*)(0x422C8004UL))) +#define bM4_TMRA6_CNTER_CNT2 (*((volatile unsigned int*)(0x422C8008UL))) +#define bM4_TMRA6_CNTER_CNT3 (*((volatile unsigned int*)(0x422C800CUL))) +#define bM4_TMRA6_CNTER_CNT4 (*((volatile unsigned int*)(0x422C8010UL))) +#define bM4_TMRA6_CNTER_CNT5 (*((volatile unsigned int*)(0x422C8014UL))) +#define bM4_TMRA6_CNTER_CNT6 (*((volatile unsigned int*)(0x422C8018UL))) +#define bM4_TMRA6_CNTER_CNT7 (*((volatile unsigned int*)(0x422C801CUL))) +#define bM4_TMRA6_CNTER_CNT8 (*((volatile unsigned int*)(0x422C8020UL))) +#define bM4_TMRA6_CNTER_CNT9 (*((volatile unsigned int*)(0x422C8024UL))) +#define bM4_TMRA6_CNTER_CNT10 (*((volatile unsigned int*)(0x422C8028UL))) +#define bM4_TMRA6_CNTER_CNT11 (*((volatile unsigned int*)(0x422C802CUL))) +#define bM4_TMRA6_CNTER_CNT12 (*((volatile unsigned int*)(0x422C8030UL))) +#define bM4_TMRA6_CNTER_CNT13 (*((volatile unsigned int*)(0x422C8034UL))) +#define bM4_TMRA6_CNTER_CNT14 (*((volatile unsigned int*)(0x422C8038UL))) +#define bM4_TMRA6_CNTER_CNT15 (*((volatile unsigned int*)(0x422C803CUL))) +#define bM4_TMRA6_PERAR_PER0 (*((volatile unsigned int*)(0x422C8080UL))) +#define bM4_TMRA6_PERAR_PER1 (*((volatile unsigned int*)(0x422C8084UL))) +#define bM4_TMRA6_PERAR_PER2 (*((volatile unsigned int*)(0x422C8088UL))) +#define bM4_TMRA6_PERAR_PER3 (*((volatile unsigned int*)(0x422C808CUL))) +#define bM4_TMRA6_PERAR_PER4 (*((volatile unsigned int*)(0x422C8090UL))) +#define bM4_TMRA6_PERAR_PER5 (*((volatile unsigned int*)(0x422C8094UL))) +#define bM4_TMRA6_PERAR_PER6 (*((volatile unsigned int*)(0x422C8098UL))) +#define bM4_TMRA6_PERAR_PER7 (*((volatile unsigned int*)(0x422C809CUL))) +#define bM4_TMRA6_PERAR_PER8 (*((volatile unsigned int*)(0x422C80A0UL))) +#define bM4_TMRA6_PERAR_PER9 (*((volatile unsigned int*)(0x422C80A4UL))) +#define bM4_TMRA6_PERAR_PER10 (*((volatile unsigned int*)(0x422C80A8UL))) +#define bM4_TMRA6_PERAR_PER11 (*((volatile unsigned int*)(0x422C80ACUL))) +#define bM4_TMRA6_PERAR_PER12 (*((volatile unsigned int*)(0x422C80B0UL))) +#define bM4_TMRA6_PERAR_PER13 (*((volatile unsigned int*)(0x422C80B4UL))) +#define bM4_TMRA6_PERAR_PER14 (*((volatile unsigned int*)(0x422C80B8UL))) +#define bM4_TMRA6_PERAR_PER15 (*((volatile unsigned int*)(0x422C80BCUL))) +#define bM4_TMRA6_CMPAR1_CMP0 (*((volatile unsigned int*)(0x422C8800UL))) +#define bM4_TMRA6_CMPAR1_CMP1 (*((volatile unsigned int*)(0x422C8804UL))) +#define bM4_TMRA6_CMPAR1_CMP2 (*((volatile unsigned int*)(0x422C8808UL))) +#define bM4_TMRA6_CMPAR1_CMP3 (*((volatile unsigned int*)(0x422C880CUL))) +#define bM4_TMRA6_CMPAR1_CMP4 (*((volatile unsigned int*)(0x422C8810UL))) +#define bM4_TMRA6_CMPAR1_CMP5 (*((volatile unsigned int*)(0x422C8814UL))) +#define bM4_TMRA6_CMPAR1_CMP6 (*((volatile unsigned int*)(0x422C8818UL))) +#define bM4_TMRA6_CMPAR1_CMP7 (*((volatile unsigned int*)(0x422C881CUL))) +#define bM4_TMRA6_CMPAR1_CMP8 (*((volatile unsigned int*)(0x422C8820UL))) +#define bM4_TMRA6_CMPAR1_CMP9 (*((volatile unsigned int*)(0x422C8824UL))) +#define bM4_TMRA6_CMPAR1_CMP10 (*((volatile unsigned int*)(0x422C8828UL))) +#define bM4_TMRA6_CMPAR1_CMP11 (*((volatile unsigned int*)(0x422C882CUL))) +#define bM4_TMRA6_CMPAR1_CMP12 (*((volatile unsigned int*)(0x422C8830UL))) +#define bM4_TMRA6_CMPAR1_CMP13 (*((volatile unsigned int*)(0x422C8834UL))) +#define bM4_TMRA6_CMPAR1_CMP14 (*((volatile unsigned int*)(0x422C8838UL))) +#define bM4_TMRA6_CMPAR1_CMP15 (*((volatile unsigned int*)(0x422C883CUL))) +#define bM4_TMRA6_CMPAR2_CMP0 (*((volatile unsigned int*)(0x422C8880UL))) +#define bM4_TMRA6_CMPAR2_CMP1 (*((volatile unsigned int*)(0x422C8884UL))) +#define bM4_TMRA6_CMPAR2_CMP2 (*((volatile unsigned int*)(0x422C8888UL))) +#define bM4_TMRA6_CMPAR2_CMP3 (*((volatile unsigned int*)(0x422C888CUL))) +#define bM4_TMRA6_CMPAR2_CMP4 (*((volatile unsigned int*)(0x422C8890UL))) +#define bM4_TMRA6_CMPAR2_CMP5 (*((volatile unsigned int*)(0x422C8894UL))) +#define bM4_TMRA6_CMPAR2_CMP6 (*((volatile unsigned int*)(0x422C8898UL))) +#define bM4_TMRA6_CMPAR2_CMP7 (*((volatile unsigned int*)(0x422C889CUL))) +#define bM4_TMRA6_CMPAR2_CMP8 (*((volatile unsigned int*)(0x422C88A0UL))) +#define bM4_TMRA6_CMPAR2_CMP9 (*((volatile unsigned int*)(0x422C88A4UL))) +#define bM4_TMRA6_CMPAR2_CMP10 (*((volatile unsigned int*)(0x422C88A8UL))) +#define bM4_TMRA6_CMPAR2_CMP11 (*((volatile unsigned int*)(0x422C88ACUL))) +#define bM4_TMRA6_CMPAR2_CMP12 (*((volatile unsigned int*)(0x422C88B0UL))) +#define bM4_TMRA6_CMPAR2_CMP13 (*((volatile unsigned int*)(0x422C88B4UL))) +#define bM4_TMRA6_CMPAR2_CMP14 (*((volatile unsigned int*)(0x422C88B8UL))) +#define bM4_TMRA6_CMPAR2_CMP15 (*((volatile unsigned int*)(0x422C88BCUL))) +#define bM4_TMRA6_CMPAR3_CMP0 (*((volatile unsigned int*)(0x422C8900UL))) +#define bM4_TMRA6_CMPAR3_CMP1 (*((volatile unsigned int*)(0x422C8904UL))) +#define bM4_TMRA6_CMPAR3_CMP2 (*((volatile unsigned int*)(0x422C8908UL))) +#define bM4_TMRA6_CMPAR3_CMP3 (*((volatile unsigned int*)(0x422C890CUL))) +#define bM4_TMRA6_CMPAR3_CMP4 (*((volatile unsigned int*)(0x422C8910UL))) +#define bM4_TMRA6_CMPAR3_CMP5 (*((volatile unsigned int*)(0x422C8914UL))) +#define bM4_TMRA6_CMPAR3_CMP6 (*((volatile unsigned int*)(0x422C8918UL))) +#define bM4_TMRA6_CMPAR3_CMP7 (*((volatile unsigned int*)(0x422C891CUL))) +#define bM4_TMRA6_CMPAR3_CMP8 (*((volatile unsigned int*)(0x422C8920UL))) +#define bM4_TMRA6_CMPAR3_CMP9 (*((volatile unsigned int*)(0x422C8924UL))) +#define bM4_TMRA6_CMPAR3_CMP10 (*((volatile unsigned int*)(0x422C8928UL))) +#define bM4_TMRA6_CMPAR3_CMP11 (*((volatile unsigned int*)(0x422C892CUL))) +#define bM4_TMRA6_CMPAR3_CMP12 (*((volatile unsigned int*)(0x422C8930UL))) +#define bM4_TMRA6_CMPAR3_CMP13 (*((volatile unsigned int*)(0x422C8934UL))) +#define bM4_TMRA6_CMPAR3_CMP14 (*((volatile unsigned int*)(0x422C8938UL))) +#define bM4_TMRA6_CMPAR3_CMP15 (*((volatile unsigned int*)(0x422C893CUL))) +#define bM4_TMRA6_CMPAR4_CMP0 (*((volatile unsigned int*)(0x422C8980UL))) +#define bM4_TMRA6_CMPAR4_CMP1 (*((volatile unsigned int*)(0x422C8984UL))) +#define bM4_TMRA6_CMPAR4_CMP2 (*((volatile unsigned int*)(0x422C8988UL))) +#define bM4_TMRA6_CMPAR4_CMP3 (*((volatile unsigned int*)(0x422C898CUL))) +#define bM4_TMRA6_CMPAR4_CMP4 (*((volatile unsigned int*)(0x422C8990UL))) +#define bM4_TMRA6_CMPAR4_CMP5 (*((volatile unsigned int*)(0x422C8994UL))) +#define bM4_TMRA6_CMPAR4_CMP6 (*((volatile unsigned int*)(0x422C8998UL))) +#define bM4_TMRA6_CMPAR4_CMP7 (*((volatile unsigned int*)(0x422C899CUL))) +#define bM4_TMRA6_CMPAR4_CMP8 (*((volatile unsigned int*)(0x422C89A0UL))) +#define bM4_TMRA6_CMPAR4_CMP9 (*((volatile unsigned int*)(0x422C89A4UL))) +#define bM4_TMRA6_CMPAR4_CMP10 (*((volatile unsigned int*)(0x422C89A8UL))) +#define bM4_TMRA6_CMPAR4_CMP11 (*((volatile unsigned int*)(0x422C89ACUL))) +#define bM4_TMRA6_CMPAR4_CMP12 (*((volatile unsigned int*)(0x422C89B0UL))) +#define bM4_TMRA6_CMPAR4_CMP13 (*((volatile unsigned int*)(0x422C89B4UL))) +#define bM4_TMRA6_CMPAR4_CMP14 (*((volatile unsigned int*)(0x422C89B8UL))) +#define bM4_TMRA6_CMPAR4_CMP15 (*((volatile unsigned int*)(0x422C89BCUL))) +#define bM4_TMRA6_CMPAR5_CMP0 (*((volatile unsigned int*)(0x422C8A00UL))) +#define bM4_TMRA6_CMPAR5_CMP1 (*((volatile unsigned int*)(0x422C8A04UL))) +#define bM4_TMRA6_CMPAR5_CMP2 (*((volatile unsigned int*)(0x422C8A08UL))) +#define bM4_TMRA6_CMPAR5_CMP3 (*((volatile unsigned int*)(0x422C8A0CUL))) +#define bM4_TMRA6_CMPAR5_CMP4 (*((volatile unsigned int*)(0x422C8A10UL))) +#define bM4_TMRA6_CMPAR5_CMP5 (*((volatile unsigned int*)(0x422C8A14UL))) +#define bM4_TMRA6_CMPAR5_CMP6 (*((volatile unsigned int*)(0x422C8A18UL))) +#define bM4_TMRA6_CMPAR5_CMP7 (*((volatile unsigned int*)(0x422C8A1CUL))) +#define bM4_TMRA6_CMPAR5_CMP8 (*((volatile unsigned int*)(0x422C8A20UL))) +#define bM4_TMRA6_CMPAR5_CMP9 (*((volatile unsigned int*)(0x422C8A24UL))) +#define bM4_TMRA6_CMPAR5_CMP10 (*((volatile unsigned int*)(0x422C8A28UL))) +#define bM4_TMRA6_CMPAR5_CMP11 (*((volatile unsigned int*)(0x422C8A2CUL))) +#define bM4_TMRA6_CMPAR5_CMP12 (*((volatile unsigned int*)(0x422C8A30UL))) +#define bM4_TMRA6_CMPAR5_CMP13 (*((volatile unsigned int*)(0x422C8A34UL))) +#define bM4_TMRA6_CMPAR5_CMP14 (*((volatile unsigned int*)(0x422C8A38UL))) +#define bM4_TMRA6_CMPAR5_CMP15 (*((volatile unsigned int*)(0x422C8A3CUL))) +#define bM4_TMRA6_CMPAR6_CMP0 (*((volatile unsigned int*)(0x422C8A80UL))) +#define bM4_TMRA6_CMPAR6_CMP1 (*((volatile unsigned int*)(0x422C8A84UL))) +#define bM4_TMRA6_CMPAR6_CMP2 (*((volatile unsigned int*)(0x422C8A88UL))) +#define bM4_TMRA6_CMPAR6_CMP3 (*((volatile unsigned int*)(0x422C8A8CUL))) +#define bM4_TMRA6_CMPAR6_CMP4 (*((volatile unsigned int*)(0x422C8A90UL))) +#define bM4_TMRA6_CMPAR6_CMP5 (*((volatile unsigned int*)(0x422C8A94UL))) +#define bM4_TMRA6_CMPAR6_CMP6 (*((volatile unsigned int*)(0x422C8A98UL))) +#define bM4_TMRA6_CMPAR6_CMP7 (*((volatile unsigned int*)(0x422C8A9CUL))) +#define bM4_TMRA6_CMPAR6_CMP8 (*((volatile unsigned int*)(0x422C8AA0UL))) +#define bM4_TMRA6_CMPAR6_CMP9 (*((volatile unsigned int*)(0x422C8AA4UL))) +#define bM4_TMRA6_CMPAR6_CMP10 (*((volatile unsigned int*)(0x422C8AA8UL))) +#define bM4_TMRA6_CMPAR6_CMP11 (*((volatile unsigned int*)(0x422C8AACUL))) +#define bM4_TMRA6_CMPAR6_CMP12 (*((volatile unsigned int*)(0x422C8AB0UL))) +#define bM4_TMRA6_CMPAR6_CMP13 (*((volatile unsigned int*)(0x422C8AB4UL))) +#define bM4_TMRA6_CMPAR6_CMP14 (*((volatile unsigned int*)(0x422C8AB8UL))) +#define bM4_TMRA6_CMPAR6_CMP15 (*((volatile unsigned int*)(0x422C8ABCUL))) +#define bM4_TMRA6_CMPAR7_CMP0 (*((volatile unsigned int*)(0x422C8B00UL))) +#define bM4_TMRA6_CMPAR7_CMP1 (*((volatile unsigned int*)(0x422C8B04UL))) +#define bM4_TMRA6_CMPAR7_CMP2 (*((volatile unsigned int*)(0x422C8B08UL))) +#define bM4_TMRA6_CMPAR7_CMP3 (*((volatile unsigned int*)(0x422C8B0CUL))) +#define bM4_TMRA6_CMPAR7_CMP4 (*((volatile unsigned int*)(0x422C8B10UL))) +#define bM4_TMRA6_CMPAR7_CMP5 (*((volatile unsigned int*)(0x422C8B14UL))) +#define bM4_TMRA6_CMPAR7_CMP6 (*((volatile unsigned int*)(0x422C8B18UL))) +#define bM4_TMRA6_CMPAR7_CMP7 (*((volatile unsigned int*)(0x422C8B1CUL))) +#define bM4_TMRA6_CMPAR7_CMP8 (*((volatile unsigned int*)(0x422C8B20UL))) +#define bM4_TMRA6_CMPAR7_CMP9 (*((volatile unsigned int*)(0x422C8B24UL))) +#define bM4_TMRA6_CMPAR7_CMP10 (*((volatile unsigned int*)(0x422C8B28UL))) +#define bM4_TMRA6_CMPAR7_CMP11 (*((volatile unsigned int*)(0x422C8B2CUL))) +#define bM4_TMRA6_CMPAR7_CMP12 (*((volatile unsigned int*)(0x422C8B30UL))) +#define bM4_TMRA6_CMPAR7_CMP13 (*((volatile unsigned int*)(0x422C8B34UL))) +#define bM4_TMRA6_CMPAR7_CMP14 (*((volatile unsigned int*)(0x422C8B38UL))) +#define bM4_TMRA6_CMPAR7_CMP15 (*((volatile unsigned int*)(0x422C8B3CUL))) +#define bM4_TMRA6_CMPAR8_CMP0 (*((volatile unsigned int*)(0x422C8B80UL))) +#define bM4_TMRA6_CMPAR8_CMP1 (*((volatile unsigned int*)(0x422C8B84UL))) +#define bM4_TMRA6_CMPAR8_CMP2 (*((volatile unsigned int*)(0x422C8B88UL))) +#define bM4_TMRA6_CMPAR8_CMP3 (*((volatile unsigned int*)(0x422C8B8CUL))) +#define bM4_TMRA6_CMPAR8_CMP4 (*((volatile unsigned int*)(0x422C8B90UL))) +#define bM4_TMRA6_CMPAR8_CMP5 (*((volatile unsigned int*)(0x422C8B94UL))) +#define bM4_TMRA6_CMPAR8_CMP6 (*((volatile unsigned int*)(0x422C8B98UL))) +#define bM4_TMRA6_CMPAR8_CMP7 (*((volatile unsigned int*)(0x422C8B9CUL))) +#define bM4_TMRA6_CMPAR8_CMP8 (*((volatile unsigned int*)(0x422C8BA0UL))) +#define bM4_TMRA6_CMPAR8_CMP9 (*((volatile unsigned int*)(0x422C8BA4UL))) +#define bM4_TMRA6_CMPAR8_CMP10 (*((volatile unsigned int*)(0x422C8BA8UL))) +#define bM4_TMRA6_CMPAR8_CMP11 (*((volatile unsigned int*)(0x422C8BACUL))) +#define bM4_TMRA6_CMPAR8_CMP12 (*((volatile unsigned int*)(0x422C8BB0UL))) +#define bM4_TMRA6_CMPAR8_CMP13 (*((volatile unsigned int*)(0x422C8BB4UL))) +#define bM4_TMRA6_CMPAR8_CMP14 (*((volatile unsigned int*)(0x422C8BB8UL))) +#define bM4_TMRA6_CMPAR8_CMP15 (*((volatile unsigned int*)(0x422C8BBCUL))) +#define bM4_TMRA6_BCSTR_START (*((volatile unsigned int*)(0x422C9000UL))) +#define bM4_TMRA6_BCSTR_DIR (*((volatile unsigned int*)(0x422C9004UL))) +#define bM4_TMRA6_BCSTR_MODE (*((volatile unsigned int*)(0x422C9008UL))) +#define bM4_TMRA6_BCSTR_SYNST (*((volatile unsigned int*)(0x422C900CUL))) +#define bM4_TMRA6_BCSTR_CKDIV0 (*((volatile unsigned int*)(0x422C9010UL))) +#define bM4_TMRA6_BCSTR_CKDIV1 (*((volatile unsigned int*)(0x422C9014UL))) +#define bM4_TMRA6_BCSTR_CKDIV2 (*((volatile unsigned int*)(0x422C9018UL))) +#define bM4_TMRA6_BCSTR_CKDIV3 (*((volatile unsigned int*)(0x422C901CUL))) +#define bM4_TMRA6_BCSTR_ITENOVF (*((volatile unsigned int*)(0x422C9030UL))) +#define bM4_TMRA6_BCSTR_ITENUDF (*((volatile unsigned int*)(0x422C9034UL))) +#define bM4_TMRA6_BCSTR_OVFF (*((volatile unsigned int*)(0x422C9038UL))) +#define bM4_TMRA6_BCSTR_UDFF (*((volatile unsigned int*)(0x422C903CUL))) +#define bM4_TMRA6_HCONR_HSTA0 (*((volatile unsigned int*)(0x422C9080UL))) +#define bM4_TMRA6_HCONR_HSTA1 (*((volatile unsigned int*)(0x422C9084UL))) +#define bM4_TMRA6_HCONR_HSTA2 (*((volatile unsigned int*)(0x422C9088UL))) +#define bM4_TMRA6_HCONR_HSTP0 (*((volatile unsigned int*)(0x422C9090UL))) +#define bM4_TMRA6_HCONR_HSTP1 (*((volatile unsigned int*)(0x422C9094UL))) +#define bM4_TMRA6_HCONR_HSTP2 (*((volatile unsigned int*)(0x422C9098UL))) +#define bM4_TMRA6_HCONR_HCLE0 (*((volatile unsigned int*)(0x422C90A0UL))) +#define bM4_TMRA6_HCONR_HCLE1 (*((volatile unsigned int*)(0x422C90A4UL))) +#define bM4_TMRA6_HCONR_HCLE2 (*((volatile unsigned int*)(0x422C90A8UL))) +#define bM4_TMRA6_HCONR_HCLE3 (*((volatile unsigned int*)(0x422C90B0UL))) +#define bM4_TMRA6_HCONR_HCLE4 (*((volatile unsigned int*)(0x422C90B4UL))) +#define bM4_TMRA6_HCONR_HCLE5 (*((volatile unsigned int*)(0x422C90B8UL))) +#define bM4_TMRA6_HCONR_HCLE6 (*((volatile unsigned int*)(0x422C90BCUL))) +#define bM4_TMRA6_HCUPR_HCUP0 (*((volatile unsigned int*)(0x422C9100UL))) +#define bM4_TMRA6_HCUPR_HCUP1 (*((volatile unsigned int*)(0x422C9104UL))) +#define bM4_TMRA6_HCUPR_HCUP2 (*((volatile unsigned int*)(0x422C9108UL))) +#define bM4_TMRA6_HCUPR_HCUP3 (*((volatile unsigned int*)(0x422C910CUL))) +#define bM4_TMRA6_HCUPR_HCUP4 (*((volatile unsigned int*)(0x422C9110UL))) +#define bM4_TMRA6_HCUPR_HCUP5 (*((volatile unsigned int*)(0x422C9114UL))) +#define bM4_TMRA6_HCUPR_HCUP6 (*((volatile unsigned int*)(0x422C9118UL))) +#define bM4_TMRA6_HCUPR_HCUP7 (*((volatile unsigned int*)(0x422C911CUL))) +#define bM4_TMRA6_HCUPR_HCUP8 (*((volatile unsigned int*)(0x422C9120UL))) +#define bM4_TMRA6_HCUPR_HCUP9 (*((volatile unsigned int*)(0x422C9124UL))) +#define bM4_TMRA6_HCUPR_HCUP10 (*((volatile unsigned int*)(0x422C9128UL))) +#define bM4_TMRA6_HCUPR_HCUP11 (*((volatile unsigned int*)(0x422C912CUL))) +#define bM4_TMRA6_HCUPR_HCUP12 (*((volatile unsigned int*)(0x422C9130UL))) +#define bM4_TMRA6_HCDOR_HCDO0 (*((volatile unsigned int*)(0x422C9180UL))) +#define bM4_TMRA6_HCDOR_HCDO1 (*((volatile unsigned int*)(0x422C9184UL))) +#define bM4_TMRA6_HCDOR_HCDO2 (*((volatile unsigned int*)(0x422C9188UL))) +#define bM4_TMRA6_HCDOR_HCDO3 (*((volatile unsigned int*)(0x422C918CUL))) +#define bM4_TMRA6_HCDOR_HCDO4 (*((volatile unsigned int*)(0x422C9190UL))) +#define bM4_TMRA6_HCDOR_HCDO5 (*((volatile unsigned int*)(0x422C9194UL))) +#define bM4_TMRA6_HCDOR_HCDO6 (*((volatile unsigned int*)(0x422C9198UL))) +#define bM4_TMRA6_HCDOR_HCDO7 (*((volatile unsigned int*)(0x422C919CUL))) +#define bM4_TMRA6_HCDOR_HCDO8 (*((volatile unsigned int*)(0x422C91A0UL))) +#define bM4_TMRA6_HCDOR_HCDO9 (*((volatile unsigned int*)(0x422C91A4UL))) +#define bM4_TMRA6_HCDOR_HCDO10 (*((volatile unsigned int*)(0x422C91A8UL))) +#define bM4_TMRA6_HCDOR_HCDO11 (*((volatile unsigned int*)(0x422C91ACUL))) +#define bM4_TMRA6_HCDOR_HCDO12 (*((volatile unsigned int*)(0x422C91B0UL))) +#define bM4_TMRA6_ICONR_ITEN1 (*((volatile unsigned int*)(0x422C9200UL))) +#define bM4_TMRA6_ICONR_ITEN2 (*((volatile unsigned int*)(0x422C9204UL))) +#define bM4_TMRA6_ICONR_ITEN3 (*((volatile unsigned int*)(0x422C9208UL))) +#define bM4_TMRA6_ICONR_ITEN4 (*((volatile unsigned int*)(0x422C920CUL))) +#define bM4_TMRA6_ICONR_ITEN5 (*((volatile unsigned int*)(0x422C9210UL))) +#define bM4_TMRA6_ICONR_ITEN6 (*((volatile unsigned int*)(0x422C9214UL))) +#define bM4_TMRA6_ICONR_ITEN7 (*((volatile unsigned int*)(0x422C9218UL))) +#define bM4_TMRA6_ICONR_ITEN8 (*((volatile unsigned int*)(0x422C921CUL))) +#define bM4_TMRA6_ECONR_ETEN1 (*((volatile unsigned int*)(0x422C9280UL))) +#define bM4_TMRA6_ECONR_ETEN2 (*((volatile unsigned int*)(0x422C9284UL))) +#define bM4_TMRA6_ECONR_ETEN3 (*((volatile unsigned int*)(0x422C9288UL))) +#define bM4_TMRA6_ECONR_ETEN4 (*((volatile unsigned int*)(0x422C928CUL))) +#define bM4_TMRA6_ECONR_ETEN5 (*((volatile unsigned int*)(0x422C9290UL))) +#define bM4_TMRA6_ECONR_ETEN6 (*((volatile unsigned int*)(0x422C9294UL))) +#define bM4_TMRA6_ECONR_ETEN7 (*((volatile unsigned int*)(0x422C9298UL))) +#define bM4_TMRA6_ECONR_ETEN8 (*((volatile unsigned int*)(0x422C929CUL))) +#define bM4_TMRA6_FCONR_NOFIENTG (*((volatile unsigned int*)(0x422C9300UL))) +#define bM4_TMRA6_FCONR_NOFICKTG0 (*((volatile unsigned int*)(0x422C9304UL))) +#define bM4_TMRA6_FCONR_NOFICKTG1 (*((volatile unsigned int*)(0x422C9308UL))) +#define bM4_TMRA6_FCONR_NOFIENCA (*((volatile unsigned int*)(0x422C9320UL))) +#define bM4_TMRA6_FCONR_NOFICKCA0 (*((volatile unsigned int*)(0x422C9324UL))) +#define bM4_TMRA6_FCONR_NOFICKCA1 (*((volatile unsigned int*)(0x422C9328UL))) +#define bM4_TMRA6_FCONR_NOFIENCB (*((volatile unsigned int*)(0x422C9330UL))) +#define bM4_TMRA6_FCONR_NOFICKCB0 (*((volatile unsigned int*)(0x422C9334UL))) +#define bM4_TMRA6_FCONR_NOFICKCB1 (*((volatile unsigned int*)(0x422C9338UL))) +#define bM4_TMRA6_STFLR_CMPF1 (*((volatile unsigned int*)(0x422C9380UL))) +#define bM4_TMRA6_STFLR_CMPF2 (*((volatile unsigned int*)(0x422C9384UL))) +#define bM4_TMRA6_STFLR_CMPF3 (*((volatile unsigned int*)(0x422C9388UL))) +#define bM4_TMRA6_STFLR_CMPF4 (*((volatile unsigned int*)(0x422C938CUL))) +#define bM4_TMRA6_STFLR_CMPF5 (*((volatile unsigned int*)(0x422C9390UL))) +#define bM4_TMRA6_STFLR_CMPF6 (*((volatile unsigned int*)(0x422C9394UL))) +#define bM4_TMRA6_STFLR_CMPF7 (*((volatile unsigned int*)(0x422C9398UL))) +#define bM4_TMRA6_STFLR_CMPF8 (*((volatile unsigned int*)(0x422C939CUL))) +#define bM4_TMRA6_BCONR1_BEN (*((volatile unsigned int*)(0x422C9800UL))) +#define bM4_TMRA6_BCONR1_BSE0 (*((volatile unsigned int*)(0x422C9804UL))) +#define bM4_TMRA6_BCONR1_BSE1 (*((volatile unsigned int*)(0x422C9808UL))) +#define bM4_TMRA6_BCONR2_BEN (*((volatile unsigned int*)(0x422C9900UL))) +#define bM4_TMRA6_BCONR2_BSE0 (*((volatile unsigned int*)(0x422C9904UL))) +#define bM4_TMRA6_BCONR2_BSE1 (*((volatile unsigned int*)(0x422C9908UL))) +#define bM4_TMRA6_BCONR3_BEN (*((volatile unsigned int*)(0x422C9A00UL))) +#define bM4_TMRA6_BCONR3_BSE0 (*((volatile unsigned int*)(0x422C9A04UL))) +#define bM4_TMRA6_BCONR3_BSE1 (*((volatile unsigned int*)(0x422C9A08UL))) +#define bM4_TMRA6_BCONR4_BEN (*((volatile unsigned int*)(0x422C9B00UL))) +#define bM4_TMRA6_BCONR4_BSE0 (*((volatile unsigned int*)(0x422C9B04UL))) +#define bM4_TMRA6_BCONR4_BSE1 (*((volatile unsigned int*)(0x422C9B08UL))) +#define bM4_TMRA6_CCONR1_CAPMD (*((volatile unsigned int*)(0x422CA000UL))) +#define bM4_TMRA6_CCONR1_HICP0 (*((volatile unsigned int*)(0x422CA010UL))) +#define bM4_TMRA6_CCONR1_HICP1 (*((volatile unsigned int*)(0x422CA014UL))) +#define bM4_TMRA6_CCONR1_HICP2 (*((volatile unsigned int*)(0x422CA018UL))) +#define bM4_TMRA6_CCONR1_HICP3 (*((volatile unsigned int*)(0x422CA020UL))) +#define bM4_TMRA6_CCONR1_HICP4 (*((volatile unsigned int*)(0x422CA024UL))) +#define bM4_TMRA6_CCONR1_NOFIENCP (*((volatile unsigned int*)(0x422CA030UL))) +#define bM4_TMRA6_CCONR1_NOFICKCP0 (*((volatile unsigned int*)(0x422CA034UL))) +#define bM4_TMRA6_CCONR1_NOFICKCP1 (*((volatile unsigned int*)(0x422CA038UL))) +#define bM4_TMRA6_CCONR2_CAPMD (*((volatile unsigned int*)(0x422CA080UL))) +#define bM4_TMRA6_CCONR2_HICP0 (*((volatile unsigned int*)(0x422CA090UL))) +#define bM4_TMRA6_CCONR2_HICP1 (*((volatile unsigned int*)(0x422CA094UL))) +#define bM4_TMRA6_CCONR2_HICP2 (*((volatile unsigned int*)(0x422CA098UL))) +#define bM4_TMRA6_CCONR2_HICP3 (*((volatile unsigned int*)(0x422CA0A0UL))) +#define bM4_TMRA6_CCONR2_HICP4 (*((volatile unsigned int*)(0x422CA0A4UL))) +#define bM4_TMRA6_CCONR2_NOFIENCP (*((volatile unsigned int*)(0x422CA0B0UL))) +#define bM4_TMRA6_CCONR2_NOFICKCP0 (*((volatile unsigned int*)(0x422CA0B4UL))) +#define bM4_TMRA6_CCONR2_NOFICKCP1 (*((volatile unsigned int*)(0x422CA0B8UL))) +#define bM4_TMRA6_CCONR3_CAPMD (*((volatile unsigned int*)(0x422CA100UL))) +#define bM4_TMRA6_CCONR3_HICP0 (*((volatile unsigned int*)(0x422CA110UL))) +#define bM4_TMRA6_CCONR3_HICP1 (*((volatile unsigned int*)(0x422CA114UL))) +#define bM4_TMRA6_CCONR3_HICP2 (*((volatile unsigned int*)(0x422CA118UL))) +#define bM4_TMRA6_CCONR3_HICP3 (*((volatile unsigned int*)(0x422CA120UL))) +#define bM4_TMRA6_CCONR3_HICP4 (*((volatile unsigned int*)(0x422CA124UL))) +#define bM4_TMRA6_CCONR3_NOFIENCP (*((volatile unsigned int*)(0x422CA130UL))) +#define bM4_TMRA6_CCONR3_NOFICKCP0 (*((volatile unsigned int*)(0x422CA134UL))) +#define bM4_TMRA6_CCONR3_NOFICKCP1 (*((volatile unsigned int*)(0x422CA138UL))) +#define bM4_TMRA6_CCONR4_CAPMD (*((volatile unsigned int*)(0x422CA180UL))) +#define bM4_TMRA6_CCONR4_HICP0 (*((volatile unsigned int*)(0x422CA190UL))) +#define bM4_TMRA6_CCONR4_HICP1 (*((volatile unsigned int*)(0x422CA194UL))) +#define bM4_TMRA6_CCONR4_HICP2 (*((volatile unsigned int*)(0x422CA198UL))) +#define bM4_TMRA6_CCONR4_HICP3 (*((volatile unsigned int*)(0x422CA1A0UL))) +#define bM4_TMRA6_CCONR4_HICP4 (*((volatile unsigned int*)(0x422CA1A4UL))) +#define bM4_TMRA6_CCONR4_NOFIENCP (*((volatile unsigned int*)(0x422CA1B0UL))) +#define bM4_TMRA6_CCONR4_NOFICKCP0 (*((volatile unsigned int*)(0x422CA1B4UL))) +#define bM4_TMRA6_CCONR4_NOFICKCP1 (*((volatile unsigned int*)(0x422CA1B8UL))) +#define bM4_TMRA6_CCONR5_CAPMD (*((volatile unsigned int*)(0x422CA200UL))) +#define bM4_TMRA6_CCONR5_HICP0 (*((volatile unsigned int*)(0x422CA210UL))) +#define bM4_TMRA6_CCONR5_HICP1 (*((volatile unsigned int*)(0x422CA214UL))) +#define bM4_TMRA6_CCONR5_HICP2 (*((volatile unsigned int*)(0x422CA218UL))) +#define bM4_TMRA6_CCONR5_HICP3 (*((volatile unsigned int*)(0x422CA220UL))) +#define bM4_TMRA6_CCONR5_HICP4 (*((volatile unsigned int*)(0x422CA224UL))) +#define bM4_TMRA6_CCONR5_NOFIENCP (*((volatile unsigned int*)(0x422CA230UL))) +#define bM4_TMRA6_CCONR5_NOFICKCP0 (*((volatile unsigned int*)(0x422CA234UL))) +#define bM4_TMRA6_CCONR5_NOFICKCP1 (*((volatile unsigned int*)(0x422CA238UL))) +#define bM4_TMRA6_CCONR6_CAPMD (*((volatile unsigned int*)(0x422CA280UL))) +#define bM4_TMRA6_CCONR6_HICP0 (*((volatile unsigned int*)(0x422CA290UL))) +#define bM4_TMRA6_CCONR6_HICP1 (*((volatile unsigned int*)(0x422CA294UL))) +#define bM4_TMRA6_CCONR6_HICP2 (*((volatile unsigned int*)(0x422CA298UL))) +#define bM4_TMRA6_CCONR6_HICP3 (*((volatile unsigned int*)(0x422CA2A0UL))) +#define bM4_TMRA6_CCONR6_HICP4 (*((volatile unsigned int*)(0x422CA2A4UL))) +#define bM4_TMRA6_CCONR6_NOFIENCP (*((volatile unsigned int*)(0x422CA2B0UL))) +#define bM4_TMRA6_CCONR6_NOFICKCP0 (*((volatile unsigned int*)(0x422CA2B4UL))) +#define bM4_TMRA6_CCONR6_NOFICKCP1 (*((volatile unsigned int*)(0x422CA2B8UL))) +#define bM4_TMRA6_CCONR7_CAPMD (*((volatile unsigned int*)(0x422CA300UL))) +#define bM4_TMRA6_CCONR7_HICP0 (*((volatile unsigned int*)(0x422CA310UL))) +#define bM4_TMRA6_CCONR7_HICP1 (*((volatile unsigned int*)(0x422CA314UL))) +#define bM4_TMRA6_CCONR7_HICP2 (*((volatile unsigned int*)(0x422CA318UL))) +#define bM4_TMRA6_CCONR7_HICP3 (*((volatile unsigned int*)(0x422CA320UL))) +#define bM4_TMRA6_CCONR7_HICP4 (*((volatile unsigned int*)(0x422CA324UL))) +#define bM4_TMRA6_CCONR7_NOFIENCP (*((volatile unsigned int*)(0x422CA330UL))) +#define bM4_TMRA6_CCONR7_NOFICKCP0 (*((volatile unsigned int*)(0x422CA334UL))) +#define bM4_TMRA6_CCONR7_NOFICKCP1 (*((volatile unsigned int*)(0x422CA338UL))) +#define bM4_TMRA6_CCONR8_CAPMD (*((volatile unsigned int*)(0x422CA380UL))) +#define bM4_TMRA6_CCONR8_HICP0 (*((volatile unsigned int*)(0x422CA390UL))) +#define bM4_TMRA6_CCONR8_HICP1 (*((volatile unsigned int*)(0x422CA394UL))) +#define bM4_TMRA6_CCONR8_HICP2 (*((volatile unsigned int*)(0x422CA398UL))) +#define bM4_TMRA6_CCONR8_HICP3 (*((volatile unsigned int*)(0x422CA3A0UL))) +#define bM4_TMRA6_CCONR8_HICP4 (*((volatile unsigned int*)(0x422CA3A4UL))) +#define bM4_TMRA6_CCONR8_NOFIENCP (*((volatile unsigned int*)(0x422CA3B0UL))) +#define bM4_TMRA6_CCONR8_NOFICKCP0 (*((volatile unsigned int*)(0x422CA3B4UL))) +#define bM4_TMRA6_CCONR8_NOFICKCP1 (*((volatile unsigned int*)(0x422CA3B8UL))) +#define bM4_TMRA6_PCONR1_STAC0 (*((volatile unsigned int*)(0x422CA800UL))) +#define bM4_TMRA6_PCONR1_STAC1 (*((volatile unsigned int*)(0x422CA804UL))) +#define bM4_TMRA6_PCONR1_STPC0 (*((volatile unsigned int*)(0x422CA808UL))) +#define bM4_TMRA6_PCONR1_STPC1 (*((volatile unsigned int*)(0x422CA80CUL))) +#define bM4_TMRA6_PCONR1_CMPC0 (*((volatile unsigned int*)(0x422CA810UL))) +#define bM4_TMRA6_PCONR1_CMPC1 (*((volatile unsigned int*)(0x422CA814UL))) +#define bM4_TMRA6_PCONR1_PERC0 (*((volatile unsigned int*)(0x422CA818UL))) +#define bM4_TMRA6_PCONR1_PERC1 (*((volatile unsigned int*)(0x422CA81CUL))) +#define bM4_TMRA6_PCONR1_FORC0 (*((volatile unsigned int*)(0x422CA820UL))) +#define bM4_TMRA6_PCONR1_FORC1 (*((volatile unsigned int*)(0x422CA824UL))) +#define bM4_TMRA6_PCONR1_OUTEN (*((volatile unsigned int*)(0x422CA830UL))) +#define bM4_TMRA6_PCONR2_STAC0 (*((volatile unsigned int*)(0x422CA880UL))) +#define bM4_TMRA6_PCONR2_STAC1 (*((volatile unsigned int*)(0x422CA884UL))) +#define bM4_TMRA6_PCONR2_STPC0 (*((volatile unsigned int*)(0x422CA888UL))) +#define bM4_TMRA6_PCONR2_STPC1 (*((volatile unsigned int*)(0x422CA88CUL))) +#define bM4_TMRA6_PCONR2_CMPC0 (*((volatile unsigned int*)(0x422CA890UL))) +#define bM4_TMRA6_PCONR2_CMPC1 (*((volatile unsigned int*)(0x422CA894UL))) +#define bM4_TMRA6_PCONR2_PERC0 (*((volatile unsigned int*)(0x422CA898UL))) +#define bM4_TMRA6_PCONR2_PERC1 (*((volatile unsigned int*)(0x422CA89CUL))) +#define bM4_TMRA6_PCONR2_FORC0 (*((volatile unsigned int*)(0x422CA8A0UL))) +#define bM4_TMRA6_PCONR2_FORC1 (*((volatile unsigned int*)(0x422CA8A4UL))) +#define bM4_TMRA6_PCONR2_OUTEN (*((volatile unsigned int*)(0x422CA8B0UL))) +#define bM4_TMRA6_PCONR3_STAC0 (*((volatile unsigned int*)(0x422CA900UL))) +#define bM4_TMRA6_PCONR3_STAC1 (*((volatile unsigned int*)(0x422CA904UL))) +#define bM4_TMRA6_PCONR3_STPC0 (*((volatile unsigned int*)(0x422CA908UL))) +#define bM4_TMRA6_PCONR3_STPC1 (*((volatile unsigned int*)(0x422CA90CUL))) +#define bM4_TMRA6_PCONR3_CMPC0 (*((volatile unsigned int*)(0x422CA910UL))) +#define bM4_TMRA6_PCONR3_CMPC1 (*((volatile unsigned int*)(0x422CA914UL))) +#define bM4_TMRA6_PCONR3_PERC0 (*((volatile unsigned int*)(0x422CA918UL))) +#define bM4_TMRA6_PCONR3_PERC1 (*((volatile unsigned int*)(0x422CA91CUL))) +#define bM4_TMRA6_PCONR3_FORC0 (*((volatile unsigned int*)(0x422CA920UL))) +#define bM4_TMRA6_PCONR3_FORC1 (*((volatile unsigned int*)(0x422CA924UL))) +#define bM4_TMRA6_PCONR3_OUTEN (*((volatile unsigned int*)(0x422CA930UL))) +#define bM4_TMRA6_PCONR4_STAC0 (*((volatile unsigned int*)(0x422CA980UL))) +#define bM4_TMRA6_PCONR4_STAC1 (*((volatile unsigned int*)(0x422CA984UL))) +#define bM4_TMRA6_PCONR4_STPC0 (*((volatile unsigned int*)(0x422CA988UL))) +#define bM4_TMRA6_PCONR4_STPC1 (*((volatile unsigned int*)(0x422CA98CUL))) +#define bM4_TMRA6_PCONR4_CMPC0 (*((volatile unsigned int*)(0x422CA990UL))) +#define bM4_TMRA6_PCONR4_CMPC1 (*((volatile unsigned int*)(0x422CA994UL))) +#define bM4_TMRA6_PCONR4_PERC0 (*((volatile unsigned int*)(0x422CA998UL))) +#define bM4_TMRA6_PCONR4_PERC1 (*((volatile unsigned int*)(0x422CA99CUL))) +#define bM4_TMRA6_PCONR4_FORC0 (*((volatile unsigned int*)(0x422CA9A0UL))) +#define bM4_TMRA6_PCONR4_FORC1 (*((volatile unsigned int*)(0x422CA9A4UL))) +#define bM4_TMRA6_PCONR4_OUTEN (*((volatile unsigned int*)(0x422CA9B0UL))) +#define bM4_TMRA6_PCONR5_STAC0 (*((volatile unsigned int*)(0x422CAA00UL))) +#define bM4_TMRA6_PCONR5_STAC1 (*((volatile unsigned int*)(0x422CAA04UL))) +#define bM4_TMRA6_PCONR5_STPC0 (*((volatile unsigned int*)(0x422CAA08UL))) +#define bM4_TMRA6_PCONR5_STPC1 (*((volatile unsigned int*)(0x422CAA0CUL))) +#define bM4_TMRA6_PCONR5_CMPC0 (*((volatile unsigned int*)(0x422CAA10UL))) +#define bM4_TMRA6_PCONR5_CMPC1 (*((volatile unsigned int*)(0x422CAA14UL))) +#define bM4_TMRA6_PCONR5_PERC0 (*((volatile unsigned int*)(0x422CAA18UL))) +#define bM4_TMRA6_PCONR5_PERC1 (*((volatile unsigned int*)(0x422CAA1CUL))) +#define bM4_TMRA6_PCONR5_FORC0 (*((volatile unsigned int*)(0x422CAA20UL))) +#define bM4_TMRA6_PCONR5_FORC1 (*((volatile unsigned int*)(0x422CAA24UL))) +#define bM4_TMRA6_PCONR5_OUTEN (*((volatile unsigned int*)(0x422CAA30UL))) +#define bM4_TMRA6_PCONR6_STAC0 (*((volatile unsigned int*)(0x422CAA80UL))) +#define bM4_TMRA6_PCONR6_STAC1 (*((volatile unsigned int*)(0x422CAA84UL))) +#define bM4_TMRA6_PCONR6_STPC0 (*((volatile unsigned int*)(0x422CAA88UL))) +#define bM4_TMRA6_PCONR6_STPC1 (*((volatile unsigned int*)(0x422CAA8CUL))) +#define bM4_TMRA6_PCONR6_CMPC0 (*((volatile unsigned int*)(0x422CAA90UL))) +#define bM4_TMRA6_PCONR6_CMPC1 (*((volatile unsigned int*)(0x422CAA94UL))) +#define bM4_TMRA6_PCONR6_PERC0 (*((volatile unsigned int*)(0x422CAA98UL))) +#define bM4_TMRA6_PCONR6_PERC1 (*((volatile unsigned int*)(0x422CAA9CUL))) +#define bM4_TMRA6_PCONR6_FORC0 (*((volatile unsigned int*)(0x422CAAA0UL))) +#define bM4_TMRA6_PCONR6_FORC1 (*((volatile unsigned int*)(0x422CAAA4UL))) +#define bM4_TMRA6_PCONR6_OUTEN (*((volatile unsigned int*)(0x422CAAB0UL))) +#define bM4_TMRA6_PCONR7_STAC0 (*((volatile unsigned int*)(0x422CAB00UL))) +#define bM4_TMRA6_PCONR7_STAC1 (*((volatile unsigned int*)(0x422CAB04UL))) +#define bM4_TMRA6_PCONR7_STPC0 (*((volatile unsigned int*)(0x422CAB08UL))) +#define bM4_TMRA6_PCONR7_STPC1 (*((volatile unsigned int*)(0x422CAB0CUL))) +#define bM4_TMRA6_PCONR7_CMPC0 (*((volatile unsigned int*)(0x422CAB10UL))) +#define bM4_TMRA6_PCONR7_CMPC1 (*((volatile unsigned int*)(0x422CAB14UL))) +#define bM4_TMRA6_PCONR7_PERC0 (*((volatile unsigned int*)(0x422CAB18UL))) +#define bM4_TMRA6_PCONR7_PERC1 (*((volatile unsigned int*)(0x422CAB1CUL))) +#define bM4_TMRA6_PCONR7_FORC0 (*((volatile unsigned int*)(0x422CAB20UL))) +#define bM4_TMRA6_PCONR7_FORC1 (*((volatile unsigned int*)(0x422CAB24UL))) +#define bM4_TMRA6_PCONR7_OUTEN (*((volatile unsigned int*)(0x422CAB30UL))) +#define bM4_TMRA6_PCONR8_STAC0 (*((volatile unsigned int*)(0x422CAB80UL))) +#define bM4_TMRA6_PCONR8_STAC1 (*((volatile unsigned int*)(0x422CAB84UL))) +#define bM4_TMRA6_PCONR8_STPC0 (*((volatile unsigned int*)(0x422CAB88UL))) +#define bM4_TMRA6_PCONR8_STPC1 (*((volatile unsigned int*)(0x422CAB8CUL))) +#define bM4_TMRA6_PCONR8_CMPC0 (*((volatile unsigned int*)(0x422CAB90UL))) +#define bM4_TMRA6_PCONR8_CMPC1 (*((volatile unsigned int*)(0x422CAB94UL))) +#define bM4_TMRA6_PCONR8_PERC0 (*((volatile unsigned int*)(0x422CAB98UL))) +#define bM4_TMRA6_PCONR8_PERC1 (*((volatile unsigned int*)(0x422CAB9CUL))) +#define bM4_TMRA6_PCONR8_FORC0 (*((volatile unsigned int*)(0x422CABA0UL))) +#define bM4_TMRA6_PCONR8_FORC1 (*((volatile unsigned int*)(0x422CABA4UL))) +#define bM4_TMRA6_PCONR8_OUTEN (*((volatile unsigned int*)(0x422CABB0UL))) +#define bM4_TRNG_CR_EN (*((volatile unsigned int*)(0x42820000UL))) +#define bM4_TRNG_CR_RUN (*((volatile unsigned int*)(0x42820004UL))) +#define bM4_TRNG_MR_LOAD (*((volatile unsigned int*)(0x42820080UL))) +#define bM4_TRNG_MR_CNT0 (*((volatile unsigned int*)(0x42820088UL))) +#define bM4_TRNG_MR_CNT1 (*((volatile unsigned int*)(0x4282008CUL))) +#define bM4_TRNG_MR_CNT2 (*((volatile unsigned int*)(0x42820090UL))) +#define bM4_USART1_SR_PE (*((volatile unsigned int*)(0x423A0000UL))) +#define bM4_USART1_SR_FE (*((volatile unsigned int*)(0x423A0004UL))) +#define bM4_USART1_SR_ORE (*((volatile unsigned int*)(0x423A000CUL))) +#define bM4_USART1_SR_RXNE (*((volatile unsigned int*)(0x423A0014UL))) +#define bM4_USART1_SR_TC (*((volatile unsigned int*)(0x423A0018UL))) +#define bM4_USART1_SR_TXE (*((volatile unsigned int*)(0x423A001CUL))) +#define bM4_USART1_SR_RTOF (*((volatile unsigned int*)(0x423A0020UL))) +#define bM4_USART1_SR_MPB (*((volatile unsigned int*)(0x423A0040UL))) +#define bM4_USART1_DR_TDR0 (*((volatile unsigned int*)(0x423A0080UL))) +#define bM4_USART1_DR_TDR1 (*((volatile unsigned int*)(0x423A0084UL))) +#define bM4_USART1_DR_TDR2 (*((volatile unsigned int*)(0x423A0088UL))) +#define bM4_USART1_DR_TDR3 (*((volatile unsigned int*)(0x423A008CUL))) +#define bM4_USART1_DR_TDR4 (*((volatile unsigned int*)(0x423A0090UL))) +#define bM4_USART1_DR_TDR5 (*((volatile unsigned int*)(0x423A0094UL))) +#define bM4_USART1_DR_TDR6 (*((volatile unsigned int*)(0x423A0098UL))) +#define bM4_USART1_DR_TDR7 (*((volatile unsigned int*)(0x423A009CUL))) +#define bM4_USART1_DR_TDR8 (*((volatile unsigned int*)(0x423A00A0UL))) +#define bM4_USART1_DR_MPID (*((volatile unsigned int*)(0x423A00A4UL))) +#define bM4_USART1_DR_RDR0 (*((volatile unsigned int*)(0x423A00C0UL))) +#define bM4_USART1_DR_RDR1 (*((volatile unsigned int*)(0x423A00C4UL))) +#define bM4_USART1_DR_RDR2 (*((volatile unsigned int*)(0x423A00C8UL))) +#define bM4_USART1_DR_RDR3 (*((volatile unsigned int*)(0x423A00CCUL))) +#define bM4_USART1_DR_RDR4 (*((volatile unsigned int*)(0x423A00D0UL))) +#define bM4_USART1_DR_RDR5 (*((volatile unsigned int*)(0x423A00D4UL))) +#define bM4_USART1_DR_RDR6 (*((volatile unsigned int*)(0x423A00D8UL))) +#define bM4_USART1_DR_RDR7 (*((volatile unsigned int*)(0x423A00DCUL))) +#define bM4_USART1_DR_RDR8 (*((volatile unsigned int*)(0x423A00E0UL))) +#define bM4_USART1_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x423A0100UL))) +#define bM4_USART1_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x423A0104UL))) +#define bM4_USART1_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x423A0108UL))) +#define bM4_USART1_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x423A010CUL))) +#define bM4_USART1_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x423A0110UL))) +#define bM4_USART1_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x423A0114UL))) +#define bM4_USART1_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x423A0118UL))) +#define bM4_USART1_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x423A0120UL))) +#define bM4_USART1_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x423A0124UL))) +#define bM4_USART1_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x423A0128UL))) +#define bM4_USART1_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x423A012CUL))) +#define bM4_USART1_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x423A0130UL))) +#define bM4_USART1_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x423A0134UL))) +#define bM4_USART1_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x423A0138UL))) +#define bM4_USART1_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x423A013CUL))) +#define bM4_USART1_CR1_RTOE (*((volatile unsigned int*)(0x423A0180UL))) +#define bM4_USART1_CR1_RTOIE (*((volatile unsigned int*)(0x423A0184UL))) +#define bM4_USART1_CR1_RE (*((volatile unsigned int*)(0x423A0188UL))) +#define bM4_USART1_CR1_TE (*((volatile unsigned int*)(0x423A018CUL))) +#define bM4_USART1_CR1_SLME (*((volatile unsigned int*)(0x423A0190UL))) +#define bM4_USART1_CR1_RIE (*((volatile unsigned int*)(0x423A0194UL))) +#define bM4_USART1_CR1_TCIE (*((volatile unsigned int*)(0x423A0198UL))) +#define bM4_USART1_CR1_TXEIE (*((volatile unsigned int*)(0x423A019CUL))) +#define bM4_USART1_CR1_PS (*((volatile unsigned int*)(0x423A01A4UL))) +#define bM4_USART1_CR1_PCE (*((volatile unsigned int*)(0x423A01A8UL))) +#define bM4_USART1_CR1_M (*((volatile unsigned int*)(0x423A01B0UL))) +#define bM4_USART1_CR1_OVER8 (*((volatile unsigned int*)(0x423A01BCUL))) +#define bM4_USART1_CR1_CPE (*((volatile unsigned int*)(0x423A01C0UL))) +#define bM4_USART1_CR1_CFE (*((volatile unsigned int*)(0x423A01C4UL))) +#define bM4_USART1_CR1_CORE (*((volatile unsigned int*)(0x423A01CCUL))) +#define bM4_USART1_CR1_CRTOF (*((volatile unsigned int*)(0x423A01D0UL))) +#define bM4_USART1_CR1_MS (*((volatile unsigned int*)(0x423A01E0UL))) +#define bM4_USART1_CR1_ML (*((volatile unsigned int*)(0x423A01F0UL))) +#define bM4_USART1_CR1_FBME (*((volatile unsigned int*)(0x423A01F4UL))) +#define bM4_USART1_CR1_NFE (*((volatile unsigned int*)(0x423A01F8UL))) +#define bM4_USART1_CR1_SBS (*((volatile unsigned int*)(0x423A01FCUL))) +#define bM4_USART1_CR2_MPE (*((volatile unsigned int*)(0x423A0200UL))) +#define bM4_USART1_CR2_CLKC0 (*((volatile unsigned int*)(0x423A022CUL))) +#define bM4_USART1_CR2_CLKC1 (*((volatile unsigned int*)(0x423A0230UL))) +#define bM4_USART1_CR2_STOP (*((volatile unsigned int*)(0x423A0234UL))) +#define bM4_USART1_CR3_SCEN (*((volatile unsigned int*)(0x423A0294UL))) +#define bM4_USART1_CR3_CTSE (*((volatile unsigned int*)(0x423A02A4UL))) +#define bM4_USART1_CR3_BCN0 (*((volatile unsigned int*)(0x423A02D4UL))) +#define bM4_USART1_CR3_BCN1 (*((volatile unsigned int*)(0x423A02D8UL))) +#define bM4_USART1_CR3_BCN2 (*((volatile unsigned int*)(0x423A02DCUL))) +#define bM4_USART1_PR_PSC0 (*((volatile unsigned int*)(0x423A0300UL))) +#define bM4_USART1_PR_PSC1 (*((volatile unsigned int*)(0x423A0304UL))) +#define bM4_USART2_SR_PE (*((volatile unsigned int*)(0x423A8000UL))) +#define bM4_USART2_SR_FE (*((volatile unsigned int*)(0x423A8004UL))) +#define bM4_USART2_SR_ORE (*((volatile unsigned int*)(0x423A800CUL))) +#define bM4_USART2_SR_RXNE (*((volatile unsigned int*)(0x423A8014UL))) +#define bM4_USART2_SR_TC (*((volatile unsigned int*)(0x423A8018UL))) +#define bM4_USART2_SR_TXE (*((volatile unsigned int*)(0x423A801CUL))) +#define bM4_USART2_SR_RTOF (*((volatile unsigned int*)(0x423A8020UL))) +#define bM4_USART2_SR_MPB (*((volatile unsigned int*)(0x423A8040UL))) +#define bM4_USART2_DR_TDR0 (*((volatile unsigned int*)(0x423A8080UL))) +#define bM4_USART2_DR_TDR1 (*((volatile unsigned int*)(0x423A8084UL))) +#define bM4_USART2_DR_TDR2 (*((volatile unsigned int*)(0x423A8088UL))) +#define bM4_USART2_DR_TDR3 (*((volatile unsigned int*)(0x423A808CUL))) +#define bM4_USART2_DR_TDR4 (*((volatile unsigned int*)(0x423A8090UL))) +#define bM4_USART2_DR_TDR5 (*((volatile unsigned int*)(0x423A8094UL))) +#define bM4_USART2_DR_TDR6 (*((volatile unsigned int*)(0x423A8098UL))) +#define bM4_USART2_DR_TDR7 (*((volatile unsigned int*)(0x423A809CUL))) +#define bM4_USART2_DR_TDR8 (*((volatile unsigned int*)(0x423A80A0UL))) +#define bM4_USART2_DR_MPID (*((volatile unsigned int*)(0x423A80A4UL))) +#define bM4_USART2_DR_RDR0 (*((volatile unsigned int*)(0x423A80C0UL))) +#define bM4_USART2_DR_RDR1 (*((volatile unsigned int*)(0x423A80C4UL))) +#define bM4_USART2_DR_RDR2 (*((volatile unsigned int*)(0x423A80C8UL))) +#define bM4_USART2_DR_RDR3 (*((volatile unsigned int*)(0x423A80CCUL))) +#define bM4_USART2_DR_RDR4 (*((volatile unsigned int*)(0x423A80D0UL))) +#define bM4_USART2_DR_RDR5 (*((volatile unsigned int*)(0x423A80D4UL))) +#define bM4_USART2_DR_RDR6 (*((volatile unsigned int*)(0x423A80D8UL))) +#define bM4_USART2_DR_RDR7 (*((volatile unsigned int*)(0x423A80DCUL))) +#define bM4_USART2_DR_RDR8 (*((volatile unsigned int*)(0x423A80E0UL))) +#define bM4_USART2_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x423A8100UL))) +#define bM4_USART2_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x423A8104UL))) +#define bM4_USART2_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x423A8108UL))) +#define bM4_USART2_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x423A810CUL))) +#define bM4_USART2_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x423A8110UL))) +#define bM4_USART2_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x423A8114UL))) +#define bM4_USART2_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x423A8118UL))) +#define bM4_USART2_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x423A8120UL))) +#define bM4_USART2_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x423A8124UL))) +#define bM4_USART2_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x423A8128UL))) +#define bM4_USART2_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x423A812CUL))) +#define bM4_USART2_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x423A8130UL))) +#define bM4_USART2_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x423A8134UL))) +#define bM4_USART2_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x423A8138UL))) +#define bM4_USART2_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x423A813CUL))) +#define bM4_USART2_CR1_RTOE (*((volatile unsigned int*)(0x423A8180UL))) +#define bM4_USART2_CR1_RTOIE (*((volatile unsigned int*)(0x423A8184UL))) +#define bM4_USART2_CR1_RE (*((volatile unsigned int*)(0x423A8188UL))) +#define bM4_USART2_CR1_TE (*((volatile unsigned int*)(0x423A818CUL))) +#define bM4_USART2_CR1_SLME (*((volatile unsigned int*)(0x423A8190UL))) +#define bM4_USART2_CR1_RIE (*((volatile unsigned int*)(0x423A8194UL))) +#define bM4_USART2_CR1_TCIE (*((volatile unsigned int*)(0x423A8198UL))) +#define bM4_USART2_CR1_TXEIE (*((volatile unsigned int*)(0x423A819CUL))) +#define bM4_USART2_CR1_PS (*((volatile unsigned int*)(0x423A81A4UL))) +#define bM4_USART2_CR1_PCE (*((volatile unsigned int*)(0x423A81A8UL))) +#define bM4_USART2_CR1_M (*((volatile unsigned int*)(0x423A81B0UL))) +#define bM4_USART2_CR1_OVER8 (*((volatile unsigned int*)(0x423A81BCUL))) +#define bM4_USART2_CR1_CPE (*((volatile unsigned int*)(0x423A81C0UL))) +#define bM4_USART2_CR1_CFE (*((volatile unsigned int*)(0x423A81C4UL))) +#define bM4_USART2_CR1_CORE (*((volatile unsigned int*)(0x423A81CCUL))) +#define bM4_USART2_CR1_CRTOF (*((volatile unsigned int*)(0x423A81D0UL))) +#define bM4_USART2_CR1_MS (*((volatile unsigned int*)(0x423A81E0UL))) +#define bM4_USART2_CR1_ML (*((volatile unsigned int*)(0x423A81F0UL))) +#define bM4_USART2_CR1_FBME (*((volatile unsigned int*)(0x423A81F4UL))) +#define bM4_USART2_CR1_NFE (*((volatile unsigned int*)(0x423A81F8UL))) +#define bM4_USART2_CR1_SBS (*((volatile unsigned int*)(0x423A81FCUL))) +#define bM4_USART2_CR2_MPE (*((volatile unsigned int*)(0x423A8200UL))) +#define bM4_USART2_CR2_CLKC0 (*((volatile unsigned int*)(0x423A822CUL))) +#define bM4_USART2_CR2_CLKC1 (*((volatile unsigned int*)(0x423A8230UL))) +#define bM4_USART2_CR2_STOP (*((volatile unsigned int*)(0x423A8234UL))) +#define bM4_USART2_CR3_SCEN (*((volatile unsigned int*)(0x423A8294UL))) +#define bM4_USART2_CR3_CTSE (*((volatile unsigned int*)(0x423A82A4UL))) +#define bM4_USART2_CR3_BCN0 (*((volatile unsigned int*)(0x423A82D4UL))) +#define bM4_USART2_CR3_BCN1 (*((volatile unsigned int*)(0x423A82D8UL))) +#define bM4_USART2_CR3_BCN2 (*((volatile unsigned int*)(0x423A82DCUL))) +#define bM4_USART2_PR_PSC0 (*((volatile unsigned int*)(0x423A8300UL))) +#define bM4_USART2_PR_PSC1 (*((volatile unsigned int*)(0x423A8304UL))) +#define bM4_USART3_SR_PE (*((volatile unsigned int*)(0x42420000UL))) +#define bM4_USART3_SR_FE (*((volatile unsigned int*)(0x42420004UL))) +#define bM4_USART3_SR_ORE (*((volatile unsigned int*)(0x4242000CUL))) +#define bM4_USART3_SR_RXNE (*((volatile unsigned int*)(0x42420014UL))) +#define bM4_USART3_SR_TC (*((volatile unsigned int*)(0x42420018UL))) +#define bM4_USART3_SR_TXE (*((volatile unsigned int*)(0x4242001CUL))) +#define bM4_USART3_SR_RTOF (*((volatile unsigned int*)(0x42420020UL))) +#define bM4_USART3_SR_MPB (*((volatile unsigned int*)(0x42420040UL))) +#define bM4_USART3_DR_TDR0 (*((volatile unsigned int*)(0x42420080UL))) +#define bM4_USART3_DR_TDR1 (*((volatile unsigned int*)(0x42420084UL))) +#define bM4_USART3_DR_TDR2 (*((volatile unsigned int*)(0x42420088UL))) +#define bM4_USART3_DR_TDR3 (*((volatile unsigned int*)(0x4242008CUL))) +#define bM4_USART3_DR_TDR4 (*((volatile unsigned int*)(0x42420090UL))) +#define bM4_USART3_DR_TDR5 (*((volatile unsigned int*)(0x42420094UL))) +#define bM4_USART3_DR_TDR6 (*((volatile unsigned int*)(0x42420098UL))) +#define bM4_USART3_DR_TDR7 (*((volatile unsigned int*)(0x4242009CUL))) +#define bM4_USART3_DR_TDR8 (*((volatile unsigned int*)(0x424200A0UL))) +#define bM4_USART3_DR_MPID (*((volatile unsigned int*)(0x424200A4UL))) +#define bM4_USART3_DR_RDR0 (*((volatile unsigned int*)(0x424200C0UL))) +#define bM4_USART3_DR_RDR1 (*((volatile unsigned int*)(0x424200C4UL))) +#define bM4_USART3_DR_RDR2 (*((volatile unsigned int*)(0x424200C8UL))) +#define bM4_USART3_DR_RDR3 (*((volatile unsigned int*)(0x424200CCUL))) +#define bM4_USART3_DR_RDR4 (*((volatile unsigned int*)(0x424200D0UL))) +#define bM4_USART3_DR_RDR5 (*((volatile unsigned int*)(0x424200D4UL))) +#define bM4_USART3_DR_RDR6 (*((volatile unsigned int*)(0x424200D8UL))) +#define bM4_USART3_DR_RDR7 (*((volatile unsigned int*)(0x424200DCUL))) +#define bM4_USART3_DR_RDR8 (*((volatile unsigned int*)(0x424200E0UL))) +#define bM4_USART3_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x42420100UL))) +#define bM4_USART3_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x42420104UL))) +#define bM4_USART3_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x42420108UL))) +#define bM4_USART3_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x4242010CUL))) +#define bM4_USART3_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x42420110UL))) +#define bM4_USART3_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x42420114UL))) +#define bM4_USART3_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x42420118UL))) +#define bM4_USART3_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x42420120UL))) +#define bM4_USART3_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x42420124UL))) +#define bM4_USART3_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x42420128UL))) +#define bM4_USART3_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x4242012CUL))) +#define bM4_USART3_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x42420130UL))) +#define bM4_USART3_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x42420134UL))) +#define bM4_USART3_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x42420138UL))) +#define bM4_USART3_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x4242013CUL))) +#define bM4_USART3_CR1_RTOE (*((volatile unsigned int*)(0x42420180UL))) +#define bM4_USART3_CR1_RTOIE (*((volatile unsigned int*)(0x42420184UL))) +#define bM4_USART3_CR1_RE (*((volatile unsigned int*)(0x42420188UL))) +#define bM4_USART3_CR1_TE (*((volatile unsigned int*)(0x4242018CUL))) +#define bM4_USART3_CR1_SLME (*((volatile unsigned int*)(0x42420190UL))) +#define bM4_USART3_CR1_RIE (*((volatile unsigned int*)(0x42420194UL))) +#define bM4_USART3_CR1_TCIE (*((volatile unsigned int*)(0x42420198UL))) +#define bM4_USART3_CR1_TXEIE (*((volatile unsigned int*)(0x4242019CUL))) +#define bM4_USART3_CR1_PS (*((volatile unsigned int*)(0x424201A4UL))) +#define bM4_USART3_CR1_PCE (*((volatile unsigned int*)(0x424201A8UL))) +#define bM4_USART3_CR1_M (*((volatile unsigned int*)(0x424201B0UL))) +#define bM4_USART3_CR1_OVER8 (*((volatile unsigned int*)(0x424201BCUL))) +#define bM4_USART3_CR1_CPE (*((volatile unsigned int*)(0x424201C0UL))) +#define bM4_USART3_CR1_CFE (*((volatile unsigned int*)(0x424201C4UL))) +#define bM4_USART3_CR1_CORE (*((volatile unsigned int*)(0x424201CCUL))) +#define bM4_USART3_CR1_CRTOF (*((volatile unsigned int*)(0x424201D0UL))) +#define bM4_USART3_CR1_MS (*((volatile unsigned int*)(0x424201E0UL))) +#define bM4_USART3_CR1_ML (*((volatile unsigned int*)(0x424201F0UL))) +#define bM4_USART3_CR1_FBME (*((volatile unsigned int*)(0x424201F4UL))) +#define bM4_USART3_CR1_NFE (*((volatile unsigned int*)(0x424201F8UL))) +#define bM4_USART3_CR1_SBS (*((volatile unsigned int*)(0x424201FCUL))) +#define bM4_USART3_CR2_MPE (*((volatile unsigned int*)(0x42420200UL))) +#define bM4_USART3_CR2_CLKC0 (*((volatile unsigned int*)(0x4242022CUL))) +#define bM4_USART3_CR2_CLKC1 (*((volatile unsigned int*)(0x42420230UL))) +#define bM4_USART3_CR2_STOP (*((volatile unsigned int*)(0x42420234UL))) +#define bM4_USART3_CR3_SCEN (*((volatile unsigned int*)(0x42420294UL))) +#define bM4_USART3_CR3_CTSE (*((volatile unsigned int*)(0x424202A4UL))) +#define bM4_USART3_CR3_BCN0 (*((volatile unsigned int*)(0x424202D4UL))) +#define bM4_USART3_CR3_BCN1 (*((volatile unsigned int*)(0x424202D8UL))) +#define bM4_USART3_CR3_BCN2 (*((volatile unsigned int*)(0x424202DCUL))) +#define bM4_USART3_PR_PSC0 (*((volatile unsigned int*)(0x42420300UL))) +#define bM4_USART3_PR_PSC1 (*((volatile unsigned int*)(0x42420304UL))) +#define bM4_USART4_SR_PE (*((volatile unsigned int*)(0x42428000UL))) +#define bM4_USART4_SR_FE (*((volatile unsigned int*)(0x42428004UL))) +#define bM4_USART4_SR_ORE (*((volatile unsigned int*)(0x4242800CUL))) +#define bM4_USART4_SR_RXNE (*((volatile unsigned int*)(0x42428014UL))) +#define bM4_USART4_SR_TC (*((volatile unsigned int*)(0x42428018UL))) +#define bM4_USART4_SR_TXE (*((volatile unsigned int*)(0x4242801CUL))) +#define bM4_USART4_SR_RTOF (*((volatile unsigned int*)(0x42428020UL))) +#define bM4_USART4_SR_MPB (*((volatile unsigned int*)(0x42428040UL))) +#define bM4_USART4_DR_TDR0 (*((volatile unsigned int*)(0x42428080UL))) +#define bM4_USART4_DR_TDR1 (*((volatile unsigned int*)(0x42428084UL))) +#define bM4_USART4_DR_TDR2 (*((volatile unsigned int*)(0x42428088UL))) +#define bM4_USART4_DR_TDR3 (*((volatile unsigned int*)(0x4242808CUL))) +#define bM4_USART4_DR_TDR4 (*((volatile unsigned int*)(0x42428090UL))) +#define bM4_USART4_DR_TDR5 (*((volatile unsigned int*)(0x42428094UL))) +#define bM4_USART4_DR_TDR6 (*((volatile unsigned int*)(0x42428098UL))) +#define bM4_USART4_DR_TDR7 (*((volatile unsigned int*)(0x4242809CUL))) +#define bM4_USART4_DR_TDR8 (*((volatile unsigned int*)(0x424280A0UL))) +#define bM4_USART4_DR_MPID (*((volatile unsigned int*)(0x424280A4UL))) +#define bM4_USART4_DR_RDR0 (*((volatile unsigned int*)(0x424280C0UL))) +#define bM4_USART4_DR_RDR1 (*((volatile unsigned int*)(0x424280C4UL))) +#define bM4_USART4_DR_RDR2 (*((volatile unsigned int*)(0x424280C8UL))) +#define bM4_USART4_DR_RDR3 (*((volatile unsigned int*)(0x424280CCUL))) +#define bM4_USART4_DR_RDR4 (*((volatile unsigned int*)(0x424280D0UL))) +#define bM4_USART4_DR_RDR5 (*((volatile unsigned int*)(0x424280D4UL))) +#define bM4_USART4_DR_RDR6 (*((volatile unsigned int*)(0x424280D8UL))) +#define bM4_USART4_DR_RDR7 (*((volatile unsigned int*)(0x424280DCUL))) +#define bM4_USART4_DR_RDR8 (*((volatile unsigned int*)(0x424280E0UL))) +#define bM4_USART4_BRR_DIV_FRACTION0 (*((volatile unsigned int*)(0x42428100UL))) +#define bM4_USART4_BRR_DIV_FRACTION1 (*((volatile unsigned int*)(0x42428104UL))) +#define bM4_USART4_BRR_DIV_FRACTION2 (*((volatile unsigned int*)(0x42428108UL))) +#define bM4_USART4_BRR_DIV_FRACTION3 (*((volatile unsigned int*)(0x4242810CUL))) +#define bM4_USART4_BRR_DIV_FRACTION4 (*((volatile unsigned int*)(0x42428110UL))) +#define bM4_USART4_BRR_DIV_FRACTION5 (*((volatile unsigned int*)(0x42428114UL))) +#define bM4_USART4_BRR_DIV_FRACTION6 (*((volatile unsigned int*)(0x42428118UL))) +#define bM4_USART4_BRR_DIV_INTEGER0 (*((volatile unsigned int*)(0x42428120UL))) +#define bM4_USART4_BRR_DIV_INTEGER1 (*((volatile unsigned int*)(0x42428124UL))) +#define bM4_USART4_BRR_DIV_INTEGER2 (*((volatile unsigned int*)(0x42428128UL))) +#define bM4_USART4_BRR_DIV_INTEGER3 (*((volatile unsigned int*)(0x4242812CUL))) +#define bM4_USART4_BRR_DIV_INTEGER4 (*((volatile unsigned int*)(0x42428130UL))) +#define bM4_USART4_BRR_DIV_INTEGER5 (*((volatile unsigned int*)(0x42428134UL))) +#define bM4_USART4_BRR_DIV_INTEGER6 (*((volatile unsigned int*)(0x42428138UL))) +#define bM4_USART4_BRR_DIV_INTEGER7 (*((volatile unsigned int*)(0x4242813CUL))) +#define bM4_USART4_CR1_RTOE (*((volatile unsigned int*)(0x42428180UL))) +#define bM4_USART4_CR1_RTOIE (*((volatile unsigned int*)(0x42428184UL))) +#define bM4_USART4_CR1_RE (*((volatile unsigned int*)(0x42428188UL))) +#define bM4_USART4_CR1_TE (*((volatile unsigned int*)(0x4242818CUL))) +#define bM4_USART4_CR1_SLME (*((volatile unsigned int*)(0x42428190UL))) +#define bM4_USART4_CR1_RIE (*((volatile unsigned int*)(0x42428194UL))) +#define bM4_USART4_CR1_TCIE (*((volatile unsigned int*)(0x42428198UL))) +#define bM4_USART4_CR1_TXEIE (*((volatile unsigned int*)(0x4242819CUL))) +#define bM4_USART4_CR1_PS (*((volatile unsigned int*)(0x424281A4UL))) +#define bM4_USART4_CR1_PCE (*((volatile unsigned int*)(0x424281A8UL))) +#define bM4_USART4_CR1_M (*((volatile unsigned int*)(0x424281B0UL))) +#define bM4_USART4_CR1_OVER8 (*((volatile unsigned int*)(0x424281BCUL))) +#define bM4_USART4_CR1_CPE (*((volatile unsigned int*)(0x424281C0UL))) +#define bM4_USART4_CR1_CFE (*((volatile unsigned int*)(0x424281C4UL))) +#define bM4_USART4_CR1_CORE (*((volatile unsigned int*)(0x424281CCUL))) +#define bM4_USART4_CR1_CRTOF (*((volatile unsigned int*)(0x424281D0UL))) +#define bM4_USART4_CR1_MS (*((volatile unsigned int*)(0x424281E0UL))) +#define bM4_USART4_CR1_ML (*((volatile unsigned int*)(0x424281F0UL))) +#define bM4_USART4_CR1_FBME (*((volatile unsigned int*)(0x424281F4UL))) +#define bM4_USART4_CR1_NFE (*((volatile unsigned int*)(0x424281F8UL))) +#define bM4_USART4_CR1_SBS (*((volatile unsigned int*)(0x424281FCUL))) +#define bM4_USART4_CR2_MPE (*((volatile unsigned int*)(0x42428200UL))) +#define bM4_USART4_CR2_CLKC0 (*((volatile unsigned int*)(0x4242822CUL))) +#define bM4_USART4_CR2_CLKC1 (*((volatile unsigned int*)(0x42428230UL))) +#define bM4_USART4_CR2_STOP (*((volatile unsigned int*)(0x42428234UL))) +#define bM4_USART4_CR3_SCEN (*((volatile unsigned int*)(0x42428294UL))) +#define bM4_USART4_CR3_CTSE (*((volatile unsigned int*)(0x424282A4UL))) +#define bM4_USART4_CR3_BCN0 (*((volatile unsigned int*)(0x424282D4UL))) +#define bM4_USART4_CR3_BCN1 (*((volatile unsigned int*)(0x424282D8UL))) +#define bM4_USART4_CR3_BCN2 (*((volatile unsigned int*)(0x424282DCUL))) +#define bM4_USART4_PR_PSC0 (*((volatile unsigned int*)(0x42428300UL))) +#define bM4_USART4_PR_PSC1 (*((volatile unsigned int*)(0x42428304UL))) +#define bM4_USBFS_USBFS_GVBUSCFG_VBUSOVEN (*((volatile unsigned int*)(0x43800018UL))) +#define bM4_USBFS_USBFS_GVBUSCFG_VBUSVAL (*((volatile unsigned int*)(0x4380001CUL))) +#define bM4_USBFS_GAHBCFG_GINTMSK (*((volatile unsigned int*)(0x43800100UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN0 (*((volatile unsigned int*)(0x43800104UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN1 (*((volatile unsigned int*)(0x43800108UL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN2 (*((volatile unsigned int*)(0x4380010CUL))) +#define bM4_USBFS_GAHBCFG_HBSTLEN3 (*((volatile unsigned int*)(0x43800110UL))) +#define bM4_USBFS_GAHBCFG_DMAEN (*((volatile unsigned int*)(0x43800114UL))) +#define bM4_USBFS_GAHBCFG_TXFELVL (*((volatile unsigned int*)(0x4380011CUL))) +#define bM4_USBFS_GAHBCFG_PTXFELVL (*((volatile unsigned int*)(0x43800120UL))) +#define bM4_USBFS_GUSBCFG_TOCAL0 (*((volatile unsigned int*)(0x43800180UL))) +#define bM4_USBFS_GUSBCFG_TOCAL1 (*((volatile unsigned int*)(0x43800184UL))) +#define bM4_USBFS_GUSBCFG_TOCAL2 (*((volatile unsigned int*)(0x43800188UL))) +#define bM4_USBFS_GUSBCFG_PHYSEL (*((volatile unsigned int*)(0x43800198UL))) +#define bM4_USBFS_GUSBCFG_TRDT0 (*((volatile unsigned int*)(0x438001A8UL))) +#define bM4_USBFS_GUSBCFG_TRDT1 (*((volatile unsigned int*)(0x438001ACUL))) +#define bM4_USBFS_GUSBCFG_TRDT2 (*((volatile unsigned int*)(0x438001B0UL))) +#define bM4_USBFS_GUSBCFG_TRDT3 (*((volatile unsigned int*)(0x438001B4UL))) +#define bM4_USBFS_GUSBCFG_FHMOD (*((volatile unsigned int*)(0x438001F4UL))) +#define bM4_USBFS_GUSBCFG_FDMOD (*((volatile unsigned int*)(0x438001F8UL))) +#define bM4_USBFS_GRSTCTL_CSRST (*((volatile unsigned int*)(0x43800200UL))) +#define bM4_USBFS_GRSTCTL_HSRST (*((volatile unsigned int*)(0x43800204UL))) +#define bM4_USBFS_GRSTCTL_FCRST (*((volatile unsigned int*)(0x43800208UL))) +#define bM4_USBFS_GRSTCTL_RXFFLSH (*((volatile unsigned int*)(0x43800210UL))) +#define bM4_USBFS_GRSTCTL_TXFFLSH (*((volatile unsigned int*)(0x43800214UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM0 (*((volatile unsigned int*)(0x43800218UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM1 (*((volatile unsigned int*)(0x4380021CUL))) +#define bM4_USBFS_GRSTCTL_TXFNUM2 (*((volatile unsigned int*)(0x43800220UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM3 (*((volatile unsigned int*)(0x43800224UL))) +#define bM4_USBFS_GRSTCTL_TXFNUM4 (*((volatile unsigned int*)(0x43800228UL))) +#define bM4_USBFS_GRSTCTL_DMAREQ (*((volatile unsigned int*)(0x43800278UL))) +#define bM4_USBFS_GRSTCTL_AHBIDL (*((volatile unsigned int*)(0x4380027CUL))) +#define bM4_USBFS_GINTSTS_CMOD (*((volatile unsigned int*)(0x43800280UL))) +#define bM4_USBFS_GINTSTS_MMIS (*((volatile unsigned int*)(0x43800284UL))) +#define bM4_USBFS_GINTSTS_SOF (*((volatile unsigned int*)(0x4380028CUL))) +#define bM4_USBFS_GINTSTS_RXFNE (*((volatile unsigned int*)(0x43800290UL))) +#define bM4_USBFS_GINTSTS_NPTXFE (*((volatile unsigned int*)(0x43800294UL))) +#define bM4_USBFS_GINTSTS_GINAKEFF (*((volatile unsigned int*)(0x43800298UL))) +#define bM4_USBFS_GINTSTS_GONAKEFF (*((volatile unsigned int*)(0x4380029CUL))) +#define bM4_USBFS_GINTSTS_ESUSP (*((volatile unsigned int*)(0x438002A8UL))) +#define bM4_USBFS_GINTSTS_USBSUSP (*((volatile unsigned int*)(0x438002ACUL))) +#define bM4_USBFS_GINTSTS_USBRST (*((volatile unsigned int*)(0x438002B0UL))) +#define bM4_USBFS_GINTSTS_ENUMDNE (*((volatile unsigned int*)(0x438002B4UL))) +#define bM4_USBFS_GINTSTS_ISOODRP (*((volatile unsigned int*)(0x438002B8UL))) +#define bM4_USBFS_GINTSTS_EOPF (*((volatile unsigned int*)(0x438002BCUL))) +#define bM4_USBFS_GINTSTS_IEPINT (*((volatile unsigned int*)(0x438002C8UL))) +#define bM4_USBFS_GINTSTS_OEPINT (*((volatile unsigned int*)(0x438002CCUL))) +#define bM4_USBFS_GINTSTS_IISOIXFR (*((volatile unsigned int*)(0x438002D0UL))) +#define bM4_USBFS_GINTSTS_IPXFR_INCOMPISOOUT (*((volatile unsigned int*)(0x438002D4UL))) +#define bM4_USBFS_GINTSTS_DATAFSUSP (*((volatile unsigned int*)(0x438002D8UL))) +#define bM4_USBFS_GINTSTS_HPRTINT (*((volatile unsigned int*)(0x438002E0UL))) +#define bM4_USBFS_GINTSTS_HCINT (*((volatile unsigned int*)(0x438002E4UL))) +#define bM4_USBFS_GINTSTS_PTXFE (*((volatile unsigned int*)(0x438002E8UL))) +#define bM4_USBFS_GINTSTS_CIDSCHG (*((volatile unsigned int*)(0x438002F0UL))) +#define bM4_USBFS_GINTSTS_DISCINT (*((volatile unsigned int*)(0x438002F4UL))) +#define bM4_USBFS_GINTSTS_VBUSVINT (*((volatile unsigned int*)(0x438002F8UL))) +#define bM4_USBFS_GINTSTS_WKUINT (*((volatile unsigned int*)(0x438002FCUL))) +#define bM4_USBFS_GINTMSK_MMISM (*((volatile unsigned int*)(0x43800304UL))) +#define bM4_USBFS_GINTMSK_SOFM (*((volatile unsigned int*)(0x4380030CUL))) +#define bM4_USBFS_GINTMSK_RXFNEM (*((volatile unsigned int*)(0x43800310UL))) +#define bM4_USBFS_GINTMSK_NPTXFEM (*((volatile unsigned int*)(0x43800314UL))) +#define bM4_USBFS_GINTMSK_GINAKEFFM (*((volatile unsigned int*)(0x43800318UL))) +#define bM4_USBFS_GINTMSK_GONAKEFFM (*((volatile unsigned int*)(0x4380031CUL))) +#define bM4_USBFS_GINTMSK_ESUSPM (*((volatile unsigned int*)(0x43800328UL))) +#define bM4_USBFS_GINTMSK_USBSUSPM (*((volatile unsigned int*)(0x4380032CUL))) +#define bM4_USBFS_GINTMSK_USBRSTM (*((volatile unsigned int*)(0x43800330UL))) +#define bM4_USBFS_GINTMSK_ENUMDNEM (*((volatile unsigned int*)(0x43800334UL))) +#define bM4_USBFS_GINTMSK_ISOODRPM (*((volatile unsigned int*)(0x43800338UL))) +#define bM4_USBFS_GINTMSK_EOPFM (*((volatile unsigned int*)(0x4380033CUL))) +#define bM4_USBFS_GINTMSK_IEPIM (*((volatile unsigned int*)(0x43800348UL))) +#define bM4_USBFS_GINTMSK_OEPIM (*((volatile unsigned int*)(0x4380034CUL))) +#define bM4_USBFS_GINTMSK_IISOIXFRM (*((volatile unsigned int*)(0x43800350UL))) +#define bM4_USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM (*((volatile unsigned int*)(0x43800354UL))) +#define bM4_USBFS_GINTMSK_DATAFSUSPM (*((volatile unsigned int*)(0x43800358UL))) +#define bM4_USBFS_GINTMSK_HPRTIM (*((volatile unsigned int*)(0x43800360UL))) +#define bM4_USBFS_GINTMSK_HCIM (*((volatile unsigned int*)(0x43800364UL))) +#define bM4_USBFS_GINTMSK_PTXFEM (*((volatile unsigned int*)(0x43800368UL))) +#define bM4_USBFS_GINTMSK_CIDSCHGM (*((volatile unsigned int*)(0x43800370UL))) +#define bM4_USBFS_GINTMSK_DISCIM (*((volatile unsigned int*)(0x43800374UL))) +#define bM4_USBFS_GINTMSK_VBUSVIM (*((volatile unsigned int*)(0x43800378UL))) +#define bM4_USBFS_GINTMSK_WKUIM (*((volatile unsigned int*)(0x4380037CUL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM0 (*((volatile unsigned int*)(0x43800380UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM1 (*((volatile unsigned int*)(0x43800384UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM2 (*((volatile unsigned int*)(0x43800388UL))) +#define bM4_USBFS_GRXSTSR_CHNUM_EPNUM3 (*((volatile unsigned int*)(0x4380038CUL))) +#define bM4_USBFS_GRXSTSR_BCNT0 (*((volatile unsigned int*)(0x43800390UL))) +#define bM4_USBFS_GRXSTSR_BCNT1 (*((volatile unsigned int*)(0x43800394UL))) +#define bM4_USBFS_GRXSTSR_BCNT2 (*((volatile unsigned int*)(0x43800398UL))) +#define bM4_USBFS_GRXSTSR_BCNT3 (*((volatile unsigned int*)(0x4380039CUL))) +#define bM4_USBFS_GRXSTSR_BCNT4 (*((volatile unsigned int*)(0x438003A0UL))) +#define bM4_USBFS_GRXSTSR_BCNT5 (*((volatile unsigned int*)(0x438003A4UL))) +#define bM4_USBFS_GRXSTSR_BCNT6 (*((volatile unsigned int*)(0x438003A8UL))) +#define bM4_USBFS_GRXSTSR_BCNT7 (*((volatile unsigned int*)(0x438003ACUL))) +#define bM4_USBFS_GRXSTSR_BCNT8 (*((volatile unsigned int*)(0x438003B0UL))) +#define bM4_USBFS_GRXSTSR_BCNT9 (*((volatile unsigned int*)(0x438003B4UL))) +#define bM4_USBFS_GRXSTSR_BCNT10 (*((volatile unsigned int*)(0x438003B8UL))) +#define bM4_USBFS_GRXSTSR_DPID0 (*((volatile unsigned int*)(0x438003BCUL))) +#define bM4_USBFS_GRXSTSR_DPID1 (*((volatile unsigned int*)(0x438003C0UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS0 (*((volatile unsigned int*)(0x438003C4UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS1 (*((volatile unsigned int*)(0x438003C8UL))) +#define bM4_USBFS_GRXSTSR_PKTSTS2 (*((volatile unsigned int*)(0x438003CCUL))) +#define bM4_USBFS_GRXSTSR_PKTSTS3 (*((volatile unsigned int*)(0x438003D0UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM0 (*((volatile unsigned int*)(0x43800400UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM1 (*((volatile unsigned int*)(0x43800404UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM2 (*((volatile unsigned int*)(0x43800408UL))) +#define bM4_USBFS_GRXSTSP_CHNUM_EPNUM3 (*((volatile unsigned int*)(0x4380040CUL))) +#define bM4_USBFS_GRXSTSP_BCNT0 (*((volatile unsigned int*)(0x43800410UL))) +#define bM4_USBFS_GRXSTSP_BCNT1 (*((volatile unsigned int*)(0x43800414UL))) +#define bM4_USBFS_GRXSTSP_BCNT2 (*((volatile unsigned int*)(0x43800418UL))) +#define bM4_USBFS_GRXSTSP_BCNT3 (*((volatile unsigned int*)(0x4380041CUL))) +#define bM4_USBFS_GRXSTSP_BCNT4 (*((volatile unsigned int*)(0x43800420UL))) +#define bM4_USBFS_GRXSTSP_BCNT5 (*((volatile unsigned int*)(0x43800424UL))) +#define bM4_USBFS_GRXSTSP_BCNT6 (*((volatile unsigned int*)(0x43800428UL))) +#define bM4_USBFS_GRXSTSP_BCNT7 (*((volatile unsigned int*)(0x4380042CUL))) +#define bM4_USBFS_GRXSTSP_BCNT8 (*((volatile unsigned int*)(0x43800430UL))) +#define bM4_USBFS_GRXSTSP_BCNT9 (*((volatile unsigned int*)(0x43800434UL))) +#define bM4_USBFS_GRXSTSP_BCNT10 (*((volatile unsigned int*)(0x43800438UL))) +#define bM4_USBFS_GRXSTSP_DPID0 (*((volatile unsigned int*)(0x4380043CUL))) +#define bM4_USBFS_GRXSTSP_DPID1 (*((volatile unsigned int*)(0x43800440UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS0 (*((volatile unsigned int*)(0x43800444UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS1 (*((volatile unsigned int*)(0x43800448UL))) +#define bM4_USBFS_GRXSTSP_PKTSTS2 (*((volatile unsigned int*)(0x4380044CUL))) +#define bM4_USBFS_GRXSTSP_PKTSTS3 (*((volatile unsigned int*)(0x43800450UL))) +#define bM4_USBFS_GRXFSIZ_RXFD0 (*((volatile unsigned int*)(0x43800480UL))) +#define bM4_USBFS_GRXFSIZ_RXFD1 (*((volatile unsigned int*)(0x43800484UL))) +#define bM4_USBFS_GRXFSIZ_RXFD2 (*((volatile unsigned int*)(0x43800488UL))) +#define bM4_USBFS_GRXFSIZ_RXFD3 (*((volatile unsigned int*)(0x4380048CUL))) +#define bM4_USBFS_GRXFSIZ_RXFD4 (*((volatile unsigned int*)(0x43800490UL))) +#define bM4_USBFS_GRXFSIZ_RXFD5 (*((volatile unsigned int*)(0x43800494UL))) +#define bM4_USBFS_GRXFSIZ_RXFD6 (*((volatile unsigned int*)(0x43800498UL))) +#define bM4_USBFS_GRXFSIZ_RXFD7 (*((volatile unsigned int*)(0x4380049CUL))) +#define bM4_USBFS_GRXFSIZ_RXFD8 (*((volatile unsigned int*)(0x438004A0UL))) +#define bM4_USBFS_GRXFSIZ_RXFD9 (*((volatile unsigned int*)(0x438004A4UL))) +#define bM4_USBFS_GRXFSIZ_RXFD10 (*((volatile unsigned int*)(0x438004A8UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA0 (*((volatile unsigned int*)(0x43800500UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA1 (*((volatile unsigned int*)(0x43800504UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA2 (*((volatile unsigned int*)(0x43800508UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA3 (*((volatile unsigned int*)(0x4380050CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA4 (*((volatile unsigned int*)(0x43800510UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA5 (*((volatile unsigned int*)(0x43800514UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA6 (*((volatile unsigned int*)(0x43800518UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA7 (*((volatile unsigned int*)(0x4380051CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA8 (*((volatile unsigned int*)(0x43800520UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA9 (*((volatile unsigned int*)(0x43800524UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA10 (*((volatile unsigned int*)(0x43800528UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA11 (*((volatile unsigned int*)(0x4380052CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA12 (*((volatile unsigned int*)(0x43800530UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA13 (*((volatile unsigned int*)(0x43800534UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA14 (*((volatile unsigned int*)(0x43800538UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFSA15 (*((volatile unsigned int*)(0x4380053CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD0 (*((volatile unsigned int*)(0x43800540UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD1 (*((volatile unsigned int*)(0x43800544UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD2 (*((volatile unsigned int*)(0x43800548UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD3 (*((volatile unsigned int*)(0x4380054CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD4 (*((volatile unsigned int*)(0x43800550UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD5 (*((volatile unsigned int*)(0x43800554UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD6 (*((volatile unsigned int*)(0x43800558UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD7 (*((volatile unsigned int*)(0x4380055CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD8 (*((volatile unsigned int*)(0x43800560UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD9 (*((volatile unsigned int*)(0x43800564UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD10 (*((volatile unsigned int*)(0x43800568UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD11 (*((volatile unsigned int*)(0x4380056CUL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD12 (*((volatile unsigned int*)(0x43800570UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD13 (*((volatile unsigned int*)(0x43800574UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD14 (*((volatile unsigned int*)(0x43800578UL))) +#define bM4_USBFS_HNPTXFSIZ_NPTXFD15 (*((volatile unsigned int*)(0x4380057CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV0 (*((volatile unsigned int*)(0x43800580UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV1 (*((volatile unsigned int*)(0x43800584UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV2 (*((volatile unsigned int*)(0x43800588UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV3 (*((volatile unsigned int*)(0x4380058CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV4 (*((volatile unsigned int*)(0x43800590UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV5 (*((volatile unsigned int*)(0x43800594UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV6 (*((volatile unsigned int*)(0x43800598UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV7 (*((volatile unsigned int*)(0x4380059CUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV8 (*((volatile unsigned int*)(0x438005A0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV9 (*((volatile unsigned int*)(0x438005A4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV10 (*((volatile unsigned int*)(0x438005A8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV11 (*((volatile unsigned int*)(0x438005ACUL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV12 (*((volatile unsigned int*)(0x438005B0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV13 (*((volatile unsigned int*)(0x438005B4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV14 (*((volatile unsigned int*)(0x438005B8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXFSAV15 (*((volatile unsigned int*)(0x438005BCUL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV0 (*((volatile unsigned int*)(0x438005C0UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV1 (*((volatile unsigned int*)(0x438005C4UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV2 (*((volatile unsigned int*)(0x438005C8UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV3 (*((volatile unsigned int*)(0x438005CCUL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV4 (*((volatile unsigned int*)(0x438005D0UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV5 (*((volatile unsigned int*)(0x438005D4UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV6 (*((volatile unsigned int*)(0x438005D8UL))) +#define bM4_USBFS_HNPTXSTS_NPTQXSAV7 (*((volatile unsigned int*)(0x438005DCUL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP0 (*((volatile unsigned int*)(0x438005E0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP1 (*((volatile unsigned int*)(0x438005E4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP2 (*((volatile unsigned int*)(0x438005E8UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP3 (*((volatile unsigned int*)(0x438005ECUL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP4 (*((volatile unsigned int*)(0x438005F0UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP5 (*((volatile unsigned int*)(0x438005F4UL))) +#define bM4_USBFS_HNPTXSTS_NPTXQTOP6 (*((volatile unsigned int*)(0x438005F8UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA0 (*((volatile unsigned int*)(0x43802000UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA1 (*((volatile unsigned int*)(0x43802004UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA2 (*((volatile unsigned int*)(0x43802008UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA3 (*((volatile unsigned int*)(0x4380200CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA4 (*((volatile unsigned int*)(0x43802010UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA5 (*((volatile unsigned int*)(0x43802014UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA6 (*((volatile unsigned int*)(0x43802018UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA7 (*((volatile unsigned int*)(0x4380201CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA8 (*((volatile unsigned int*)(0x43802020UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA9 (*((volatile unsigned int*)(0x43802024UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA10 (*((volatile unsigned int*)(0x43802028UL))) +#define bM4_USBFS_HPTXFSIZ_PTXSA11 (*((volatile unsigned int*)(0x4380202CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD0 (*((volatile unsigned int*)(0x43802040UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD1 (*((volatile unsigned int*)(0x43802044UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD2 (*((volatile unsigned int*)(0x43802048UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD3 (*((volatile unsigned int*)(0x4380204CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD4 (*((volatile unsigned int*)(0x43802050UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD5 (*((volatile unsigned int*)(0x43802054UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD6 (*((volatile unsigned int*)(0x43802058UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD7 (*((volatile unsigned int*)(0x4380205CUL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD8 (*((volatile unsigned int*)(0x43802060UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD9 (*((volatile unsigned int*)(0x43802064UL))) +#define bM4_USBFS_HPTXFSIZ_PTXFD10 (*((volatile unsigned int*)(0x43802068UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA0 (*((volatile unsigned int*)(0x43802080UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA1 (*((volatile unsigned int*)(0x43802084UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA2 (*((volatile unsigned int*)(0x43802088UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA3 (*((volatile unsigned int*)(0x4380208CUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA4 (*((volatile unsigned int*)(0x43802090UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA5 (*((volatile unsigned int*)(0x43802094UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA6 (*((volatile unsigned int*)(0x43802098UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA7 (*((volatile unsigned int*)(0x4380209CUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA8 (*((volatile unsigned int*)(0x438020A0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA9 (*((volatile unsigned int*)(0x438020A4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA10 (*((volatile unsigned int*)(0x438020A8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXSA11 (*((volatile unsigned int*)(0x438020ACUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD0 (*((volatile unsigned int*)(0x438020C0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD1 (*((volatile unsigned int*)(0x438020C4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD2 (*((volatile unsigned int*)(0x438020C8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD3 (*((volatile unsigned int*)(0x438020CCUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD4 (*((volatile unsigned int*)(0x438020D0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD5 (*((volatile unsigned int*)(0x438020D4UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD6 (*((volatile unsigned int*)(0x438020D8UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD7 (*((volatile unsigned int*)(0x438020DCUL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD8 (*((volatile unsigned int*)(0x438020E0UL))) +#define bM4_USBFS_DIEPTXF1_INEPTXFD9 (*((volatile unsigned int*)(0x438020E4UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA0 (*((volatile unsigned int*)(0x43802100UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA1 (*((volatile unsigned int*)(0x43802104UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA2 (*((volatile unsigned int*)(0x43802108UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA3 (*((volatile unsigned int*)(0x4380210CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA4 (*((volatile unsigned int*)(0x43802110UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA5 (*((volatile unsigned int*)(0x43802114UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA6 (*((volatile unsigned int*)(0x43802118UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA7 (*((volatile unsigned int*)(0x4380211CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA8 (*((volatile unsigned int*)(0x43802120UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA9 (*((volatile unsigned int*)(0x43802124UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA10 (*((volatile unsigned int*)(0x43802128UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXSA11 (*((volatile unsigned int*)(0x4380212CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD0 (*((volatile unsigned int*)(0x43802140UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD1 (*((volatile unsigned int*)(0x43802144UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD2 (*((volatile unsigned int*)(0x43802148UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD3 (*((volatile unsigned int*)(0x4380214CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD4 (*((volatile unsigned int*)(0x43802150UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD5 (*((volatile unsigned int*)(0x43802154UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD6 (*((volatile unsigned int*)(0x43802158UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD7 (*((volatile unsigned int*)(0x4380215CUL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD8 (*((volatile unsigned int*)(0x43802160UL))) +#define bM4_USBFS_DIEPTXF2_INEPTXFD9 (*((volatile unsigned int*)(0x43802164UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA0 (*((volatile unsigned int*)(0x43802180UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA1 (*((volatile unsigned int*)(0x43802184UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA2 (*((volatile unsigned int*)(0x43802188UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA3 (*((volatile unsigned int*)(0x4380218CUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA4 (*((volatile unsigned int*)(0x43802190UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA5 (*((volatile unsigned int*)(0x43802194UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA6 (*((volatile unsigned int*)(0x43802198UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA7 (*((volatile unsigned int*)(0x4380219CUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA8 (*((volatile unsigned int*)(0x438021A0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA9 (*((volatile unsigned int*)(0x438021A4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA10 (*((volatile unsigned int*)(0x438021A8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXSA11 (*((volatile unsigned int*)(0x438021ACUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD0 (*((volatile unsigned int*)(0x438021C0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD1 (*((volatile unsigned int*)(0x438021C4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD2 (*((volatile unsigned int*)(0x438021C8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD3 (*((volatile unsigned int*)(0x438021CCUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD4 (*((volatile unsigned int*)(0x438021D0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD5 (*((volatile unsigned int*)(0x438021D4UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD6 (*((volatile unsigned int*)(0x438021D8UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD7 (*((volatile unsigned int*)(0x438021DCUL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD8 (*((volatile unsigned int*)(0x438021E0UL))) +#define bM4_USBFS_DIEPTXF3_INEPTXFD9 (*((volatile unsigned int*)(0x438021E4UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA0 (*((volatile unsigned int*)(0x43802200UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA1 (*((volatile unsigned int*)(0x43802204UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA2 (*((volatile unsigned int*)(0x43802208UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA3 (*((volatile unsigned int*)(0x4380220CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA4 (*((volatile unsigned int*)(0x43802210UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA5 (*((volatile unsigned int*)(0x43802214UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA6 (*((volatile unsigned int*)(0x43802218UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA7 (*((volatile unsigned int*)(0x4380221CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA8 (*((volatile unsigned int*)(0x43802220UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA9 (*((volatile unsigned int*)(0x43802224UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA10 (*((volatile unsigned int*)(0x43802228UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXSA11 (*((volatile unsigned int*)(0x4380222CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD0 (*((volatile unsigned int*)(0x43802240UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD1 (*((volatile unsigned int*)(0x43802244UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD2 (*((volatile unsigned int*)(0x43802248UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD3 (*((volatile unsigned int*)(0x4380224CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD4 (*((volatile unsigned int*)(0x43802250UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD5 (*((volatile unsigned int*)(0x43802254UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD6 (*((volatile unsigned int*)(0x43802258UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD7 (*((volatile unsigned int*)(0x4380225CUL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD8 (*((volatile unsigned int*)(0x43802260UL))) +#define bM4_USBFS_DIEPTXF4_INEPTXFD9 (*((volatile unsigned int*)(0x43802264UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA0 (*((volatile unsigned int*)(0x43802280UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA1 (*((volatile unsigned int*)(0x43802284UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA2 (*((volatile unsigned int*)(0x43802288UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA3 (*((volatile unsigned int*)(0x4380228CUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA4 (*((volatile unsigned int*)(0x43802290UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA5 (*((volatile unsigned int*)(0x43802294UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA6 (*((volatile unsigned int*)(0x43802298UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA7 (*((volatile unsigned int*)(0x4380229CUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA8 (*((volatile unsigned int*)(0x438022A0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA9 (*((volatile unsigned int*)(0x438022A4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA10 (*((volatile unsigned int*)(0x438022A8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXSA11 (*((volatile unsigned int*)(0x438022ACUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD0 (*((volatile unsigned int*)(0x438022C0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD1 (*((volatile unsigned int*)(0x438022C4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD2 (*((volatile unsigned int*)(0x438022C8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD3 (*((volatile unsigned int*)(0x438022CCUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD4 (*((volatile unsigned int*)(0x438022D0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD5 (*((volatile unsigned int*)(0x438022D4UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD6 (*((volatile unsigned int*)(0x438022D8UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD7 (*((volatile unsigned int*)(0x438022DCUL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD8 (*((volatile unsigned int*)(0x438022E0UL))) +#define bM4_USBFS_DIEPTXF5_INEPTXFD9 (*((volatile unsigned int*)(0x438022E4UL))) +#define bM4_USBFS_HCFG_FSLSPCS0 (*((volatile unsigned int*)(0x43808000UL))) +#define bM4_USBFS_HCFG_FSLSPCS1 (*((volatile unsigned int*)(0x43808004UL))) +#define bM4_USBFS_HCFG_FSLSS (*((volatile unsigned int*)(0x43808008UL))) +#define bM4_USBFS_HFIR_FRIVL0 (*((volatile unsigned int*)(0x43808080UL))) +#define bM4_USBFS_HFIR_FRIVL1 (*((volatile unsigned int*)(0x43808084UL))) +#define bM4_USBFS_HFIR_FRIVL2 (*((volatile unsigned int*)(0x43808088UL))) +#define bM4_USBFS_HFIR_FRIVL3 (*((volatile unsigned int*)(0x4380808CUL))) +#define bM4_USBFS_HFIR_FRIVL4 (*((volatile unsigned int*)(0x43808090UL))) +#define bM4_USBFS_HFIR_FRIVL5 (*((volatile unsigned int*)(0x43808094UL))) +#define bM4_USBFS_HFIR_FRIVL6 (*((volatile unsigned int*)(0x43808098UL))) +#define bM4_USBFS_HFIR_FRIVL7 (*((volatile unsigned int*)(0x4380809CUL))) +#define bM4_USBFS_HFIR_FRIVL8 (*((volatile unsigned int*)(0x438080A0UL))) +#define bM4_USBFS_HFIR_FRIVL9 (*((volatile unsigned int*)(0x438080A4UL))) +#define bM4_USBFS_HFIR_FRIVL10 (*((volatile unsigned int*)(0x438080A8UL))) +#define bM4_USBFS_HFIR_FRIVL11 (*((volatile unsigned int*)(0x438080ACUL))) +#define bM4_USBFS_HFIR_FRIVL12 (*((volatile unsigned int*)(0x438080B0UL))) +#define bM4_USBFS_HFIR_FRIVL13 (*((volatile unsigned int*)(0x438080B4UL))) +#define bM4_USBFS_HFIR_FRIVL14 (*((volatile unsigned int*)(0x438080B8UL))) +#define bM4_USBFS_HFIR_FRIVL15 (*((volatile unsigned int*)(0x438080BCUL))) +#define bM4_USBFS_HFNUM_FRNUM0 (*((volatile unsigned int*)(0x43808100UL))) +#define bM4_USBFS_HFNUM_FRNUM1 (*((volatile unsigned int*)(0x43808104UL))) +#define bM4_USBFS_HFNUM_FRNUM2 (*((volatile unsigned int*)(0x43808108UL))) +#define bM4_USBFS_HFNUM_FRNUM3 (*((volatile unsigned int*)(0x4380810CUL))) +#define bM4_USBFS_HFNUM_FRNUM4 (*((volatile unsigned int*)(0x43808110UL))) +#define bM4_USBFS_HFNUM_FRNUM5 (*((volatile unsigned int*)(0x43808114UL))) +#define bM4_USBFS_HFNUM_FRNUM6 (*((volatile unsigned int*)(0x43808118UL))) +#define bM4_USBFS_HFNUM_FRNUM7 (*((volatile unsigned int*)(0x4380811CUL))) +#define bM4_USBFS_HFNUM_FRNUM8 (*((volatile unsigned int*)(0x43808120UL))) +#define bM4_USBFS_HFNUM_FRNUM9 (*((volatile unsigned int*)(0x43808124UL))) +#define bM4_USBFS_HFNUM_FRNUM10 (*((volatile unsigned int*)(0x43808128UL))) +#define bM4_USBFS_HFNUM_FRNUM11 (*((volatile unsigned int*)(0x4380812CUL))) +#define bM4_USBFS_HFNUM_FRNUM12 (*((volatile unsigned int*)(0x43808130UL))) +#define bM4_USBFS_HFNUM_FRNUM13 (*((volatile unsigned int*)(0x43808134UL))) +#define bM4_USBFS_HFNUM_FRNUM14 (*((volatile unsigned int*)(0x43808138UL))) +#define bM4_USBFS_HFNUM_FRNUM15 (*((volatile unsigned int*)(0x4380813CUL))) +#define bM4_USBFS_HFNUM_FTREM0 (*((volatile unsigned int*)(0x43808140UL))) +#define bM4_USBFS_HFNUM_FTREM1 (*((volatile unsigned int*)(0x43808144UL))) +#define bM4_USBFS_HFNUM_FTREM2 (*((volatile unsigned int*)(0x43808148UL))) +#define bM4_USBFS_HFNUM_FTREM3 (*((volatile unsigned int*)(0x4380814CUL))) +#define bM4_USBFS_HFNUM_FTREM4 (*((volatile unsigned int*)(0x43808150UL))) +#define bM4_USBFS_HFNUM_FTREM5 (*((volatile unsigned int*)(0x43808154UL))) +#define bM4_USBFS_HFNUM_FTREM6 (*((volatile unsigned int*)(0x43808158UL))) +#define bM4_USBFS_HFNUM_FTREM7 (*((volatile unsigned int*)(0x4380815CUL))) +#define bM4_USBFS_HFNUM_FTREM8 (*((volatile unsigned int*)(0x43808160UL))) +#define bM4_USBFS_HFNUM_FTREM9 (*((volatile unsigned int*)(0x43808164UL))) +#define bM4_USBFS_HFNUM_FTREM10 (*((volatile unsigned int*)(0x43808168UL))) +#define bM4_USBFS_HFNUM_FTREM11 (*((volatile unsigned int*)(0x4380816CUL))) +#define bM4_USBFS_HFNUM_FTREM12 (*((volatile unsigned int*)(0x43808170UL))) +#define bM4_USBFS_HFNUM_FTREM13 (*((volatile unsigned int*)(0x43808174UL))) +#define bM4_USBFS_HFNUM_FTREM14 (*((volatile unsigned int*)(0x43808178UL))) +#define bM4_USBFS_HFNUM_FTREM15 (*((volatile unsigned int*)(0x4380817CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL0 (*((volatile unsigned int*)(0x43808200UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL1 (*((volatile unsigned int*)(0x43808204UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL2 (*((volatile unsigned int*)(0x43808208UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL3 (*((volatile unsigned int*)(0x4380820CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL4 (*((volatile unsigned int*)(0x43808210UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL5 (*((volatile unsigned int*)(0x43808214UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL6 (*((volatile unsigned int*)(0x43808218UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL7 (*((volatile unsigned int*)(0x4380821CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL8 (*((volatile unsigned int*)(0x43808220UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL9 (*((volatile unsigned int*)(0x43808224UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL10 (*((volatile unsigned int*)(0x43808228UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL11 (*((volatile unsigned int*)(0x4380822CUL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL12 (*((volatile unsigned int*)(0x43808230UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL13 (*((volatile unsigned int*)(0x43808234UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL14 (*((volatile unsigned int*)(0x43808238UL))) +#define bM4_USBFS_HPTXSTS_PTXFSAVL15 (*((volatile unsigned int*)(0x4380823CUL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV0 (*((volatile unsigned int*)(0x43808240UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV1 (*((volatile unsigned int*)(0x43808244UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV2 (*((volatile unsigned int*)(0x43808248UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV3 (*((volatile unsigned int*)(0x4380824CUL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV4 (*((volatile unsigned int*)(0x43808250UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV5 (*((volatile unsigned int*)(0x43808254UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV6 (*((volatile unsigned int*)(0x43808258UL))) +#define bM4_USBFS_HPTXSTS_PTXQSAV7 (*((volatile unsigned int*)(0x4380825CUL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP0 (*((volatile unsigned int*)(0x43808260UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP1 (*((volatile unsigned int*)(0x43808264UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP2 (*((volatile unsigned int*)(0x43808268UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP3 (*((volatile unsigned int*)(0x4380826CUL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP4 (*((volatile unsigned int*)(0x43808270UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP5 (*((volatile unsigned int*)(0x43808274UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP6 (*((volatile unsigned int*)(0x43808278UL))) +#define bM4_USBFS_HPTXSTS_PTXQTOP7 (*((volatile unsigned int*)(0x4380827CUL))) +#define bM4_USBFS_HAINT_HAINT0 (*((volatile unsigned int*)(0x43808280UL))) +#define bM4_USBFS_HAINT_HAINT1 (*((volatile unsigned int*)(0x43808284UL))) +#define bM4_USBFS_HAINT_HAINT2 (*((volatile unsigned int*)(0x43808288UL))) +#define bM4_USBFS_HAINT_HAINT3 (*((volatile unsigned int*)(0x4380828CUL))) +#define bM4_USBFS_HAINT_HAINT4 (*((volatile unsigned int*)(0x43808290UL))) +#define bM4_USBFS_HAINT_HAINT5 (*((volatile unsigned int*)(0x43808294UL))) +#define bM4_USBFS_HAINT_HAINT6 (*((volatile unsigned int*)(0x43808298UL))) +#define bM4_USBFS_HAINT_HAINT7 (*((volatile unsigned int*)(0x4380829CUL))) +#define bM4_USBFS_HAINT_HAINT8 (*((volatile unsigned int*)(0x438082A0UL))) +#define bM4_USBFS_HAINT_HAINT9 (*((volatile unsigned int*)(0x438082A4UL))) +#define bM4_USBFS_HAINT_HAINT10 (*((volatile unsigned int*)(0x438082A8UL))) +#define bM4_USBFS_HAINT_HAINT11 (*((volatile unsigned int*)(0x438082ACUL))) +#define bM4_USBFS_HAINTMSK_HAINTM0 (*((volatile unsigned int*)(0x43808300UL))) +#define bM4_USBFS_HAINTMSK_HAINTM1 (*((volatile unsigned int*)(0x43808304UL))) +#define bM4_USBFS_HAINTMSK_HAINTM2 (*((volatile unsigned int*)(0x43808308UL))) +#define bM4_USBFS_HAINTMSK_HAINTM3 (*((volatile unsigned int*)(0x4380830CUL))) +#define bM4_USBFS_HAINTMSK_HAINTM4 (*((volatile unsigned int*)(0x43808310UL))) +#define bM4_USBFS_HAINTMSK_HAINTM5 (*((volatile unsigned int*)(0x43808314UL))) +#define bM4_USBFS_HAINTMSK_HAINTM6 (*((volatile unsigned int*)(0x43808318UL))) +#define bM4_USBFS_HAINTMSK_HAINTM7 (*((volatile unsigned int*)(0x4380831CUL))) +#define bM4_USBFS_HAINTMSK_HAINTM8 (*((volatile unsigned int*)(0x43808320UL))) +#define bM4_USBFS_HAINTMSK_HAINTM9 (*((volatile unsigned int*)(0x43808324UL))) +#define bM4_USBFS_HAINTMSK_HAINTM10 (*((volatile unsigned int*)(0x43808328UL))) +#define bM4_USBFS_HAINTMSK_HAINTM11 (*((volatile unsigned int*)(0x4380832CUL))) +#define bM4_USBFS_HPRT_PCSTS (*((volatile unsigned int*)(0x43808800UL))) +#define bM4_USBFS_HPRT_PCDET (*((volatile unsigned int*)(0x43808804UL))) +#define bM4_USBFS_HPRT_PENA (*((volatile unsigned int*)(0x43808808UL))) +#define bM4_USBFS_HPRT_PENCHNG (*((volatile unsigned int*)(0x4380880CUL))) +#define bM4_USBFS_HPRT_PRES (*((volatile unsigned int*)(0x43808818UL))) +#define bM4_USBFS_HPRT_PSUSP (*((volatile unsigned int*)(0x4380881CUL))) +#define bM4_USBFS_HPRT_PRST (*((volatile unsigned int*)(0x43808820UL))) +#define bM4_USBFS_HPRT_PLSTS0 (*((volatile unsigned int*)(0x43808828UL))) +#define bM4_USBFS_HPRT_PLSTS1 (*((volatile unsigned int*)(0x4380882CUL))) +#define bM4_USBFS_HPRT_PWPR (*((volatile unsigned int*)(0x43808830UL))) +#define bM4_USBFS_HPRT_PSPD0 (*((volatile unsigned int*)(0x43808844UL))) +#define bM4_USBFS_HPRT_PSPD1 (*((volatile unsigned int*)(0x43808848UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ0 (*((volatile unsigned int*)(0x4380A000UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ1 (*((volatile unsigned int*)(0x4380A004UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ2 (*((volatile unsigned int*)(0x4380A008UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ3 (*((volatile unsigned int*)(0x4380A00CUL))) +#define bM4_USBFS_HCCHAR0_MPSIZ4 (*((volatile unsigned int*)(0x4380A010UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ5 (*((volatile unsigned int*)(0x4380A014UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ6 (*((volatile unsigned int*)(0x4380A018UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ7 (*((volatile unsigned int*)(0x4380A01CUL))) +#define bM4_USBFS_HCCHAR0_MPSIZ8 (*((volatile unsigned int*)(0x4380A020UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ9 (*((volatile unsigned int*)(0x4380A024UL))) +#define bM4_USBFS_HCCHAR0_MPSIZ10 (*((volatile unsigned int*)(0x4380A028UL))) +#define bM4_USBFS_HCCHAR0_EPNUM0 (*((volatile unsigned int*)(0x4380A02CUL))) +#define bM4_USBFS_HCCHAR0_EPNUM1 (*((volatile unsigned int*)(0x4380A030UL))) +#define bM4_USBFS_HCCHAR0_EPNUM2 (*((volatile unsigned int*)(0x4380A034UL))) +#define bM4_USBFS_HCCHAR0_EPNUM3 (*((volatile unsigned int*)(0x4380A038UL))) +#define bM4_USBFS_HCCHAR0_EPDIR (*((volatile unsigned int*)(0x4380A03CUL))) +#define bM4_USBFS_HCCHAR0_LSDEV (*((volatile unsigned int*)(0x4380A044UL))) +#define bM4_USBFS_HCCHAR0_EPTYP0 (*((volatile unsigned int*)(0x4380A048UL))) +#define bM4_USBFS_HCCHAR0_EPTYP1 (*((volatile unsigned int*)(0x4380A04CUL))) +#define bM4_USBFS_HCCHAR0_DAD0 (*((volatile unsigned int*)(0x4380A058UL))) +#define bM4_USBFS_HCCHAR0_DAD1 (*((volatile unsigned int*)(0x4380A05CUL))) +#define bM4_USBFS_HCCHAR0_DAD2 (*((volatile unsigned int*)(0x4380A060UL))) +#define bM4_USBFS_HCCHAR0_DAD3 (*((volatile unsigned int*)(0x4380A064UL))) +#define bM4_USBFS_HCCHAR0_DAD4 (*((volatile unsigned int*)(0x4380A068UL))) +#define bM4_USBFS_HCCHAR0_DAD5 (*((volatile unsigned int*)(0x4380A06CUL))) +#define bM4_USBFS_HCCHAR0_DAD6 (*((volatile unsigned int*)(0x4380A070UL))) +#define bM4_USBFS_HCCHAR0_ODDFRM (*((volatile unsigned int*)(0x4380A074UL))) +#define bM4_USBFS_HCCHAR0_CHDIS (*((volatile unsigned int*)(0x4380A078UL))) +#define bM4_USBFS_HCCHAR0_CHENA (*((volatile unsigned int*)(0x4380A07CUL))) +#define bM4_USBFS_HCINT0_XFRC (*((volatile unsigned int*)(0x4380A100UL))) +#define bM4_USBFS_HCINT0_CHH (*((volatile unsigned int*)(0x4380A104UL))) +#define bM4_USBFS_HCINT0_STALL (*((volatile unsigned int*)(0x4380A10CUL))) +#define bM4_USBFS_HCINT0_NAK (*((volatile unsigned int*)(0x4380A110UL))) +#define bM4_USBFS_HCINT0_ACK (*((volatile unsigned int*)(0x4380A114UL))) +#define bM4_USBFS_HCINT0_TXERR (*((volatile unsigned int*)(0x4380A11CUL))) +#define bM4_USBFS_HCINT0_BBERR (*((volatile unsigned int*)(0x4380A120UL))) +#define bM4_USBFS_HCINT0_FRMOR (*((volatile unsigned int*)(0x4380A124UL))) +#define bM4_USBFS_HCINT0_DTERR (*((volatile unsigned int*)(0x4380A128UL))) +#define bM4_USBFS_HCINTMSK0_XFRCM (*((volatile unsigned int*)(0x4380A180UL))) +#define bM4_USBFS_HCINTMSK0_CHHM (*((volatile unsigned int*)(0x4380A184UL))) +#define bM4_USBFS_HCINTMSK0_STALLM (*((volatile unsigned int*)(0x4380A18CUL))) +#define bM4_USBFS_HCINTMSK0_NAKM (*((volatile unsigned int*)(0x4380A190UL))) +#define bM4_USBFS_HCINTMSK0_ACKM (*((volatile unsigned int*)(0x4380A194UL))) +#define bM4_USBFS_HCINTMSK0_TXERRM (*((volatile unsigned int*)(0x4380A19CUL))) +#define bM4_USBFS_HCINTMSK0_BBERRM (*((volatile unsigned int*)(0x4380A1A0UL))) +#define bM4_USBFS_HCINTMSK0_FRMORM (*((volatile unsigned int*)(0x4380A1A4UL))) +#define bM4_USBFS_HCINTMSK0_DTERRM (*((volatile unsigned int*)(0x4380A1A8UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x4380A200UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x4380A204UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x4380A208UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4380A20CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x4380A210UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x4380A214UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x4380A218UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ7 (*((volatile unsigned int*)(0x4380A21CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ8 (*((volatile unsigned int*)(0x4380A220UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ9 (*((volatile unsigned int*)(0x4380A224UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ10 (*((volatile unsigned int*)(0x4380A228UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ11 (*((volatile unsigned int*)(0x4380A22CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ12 (*((volatile unsigned int*)(0x4380A230UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ13 (*((volatile unsigned int*)(0x4380A234UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ14 (*((volatile unsigned int*)(0x4380A238UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ15 (*((volatile unsigned int*)(0x4380A23CUL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ16 (*((volatile unsigned int*)(0x4380A240UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ17 (*((volatile unsigned int*)(0x4380A244UL))) +#define bM4_USBFS_HCTSIZ0_XFRSIZ18 (*((volatile unsigned int*)(0x4380A248UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT0 (*((volatile unsigned int*)(0x4380A24CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT1 (*((volatile unsigned int*)(0x4380A250UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT2 (*((volatile unsigned int*)(0x4380A254UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT3 (*((volatile unsigned int*)(0x4380A258UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT4 (*((volatile unsigned int*)(0x4380A25CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT5 (*((volatile unsigned int*)(0x4380A260UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT6 (*((volatile unsigned int*)(0x4380A264UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT7 (*((volatile unsigned int*)(0x4380A268UL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT8 (*((volatile unsigned int*)(0x4380A26CUL))) +#define bM4_USBFS_HCTSIZ0_PKTCNT9 (*((volatile unsigned int*)(0x4380A270UL))) +#define bM4_USBFS_HCTSIZ0_DPID0 (*((volatile unsigned int*)(0x4380A274UL))) +#define bM4_USBFS_HCTSIZ0_DPID1 (*((volatile unsigned int*)(0x4380A278UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ0 (*((volatile unsigned int*)(0x4380A400UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ1 (*((volatile unsigned int*)(0x4380A404UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ2 (*((volatile unsigned int*)(0x4380A408UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ3 (*((volatile unsigned int*)(0x4380A40CUL))) +#define bM4_USBFS_HCCHAR1_MPSIZ4 (*((volatile unsigned int*)(0x4380A410UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ5 (*((volatile unsigned int*)(0x4380A414UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ6 (*((volatile unsigned int*)(0x4380A418UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ7 (*((volatile unsigned int*)(0x4380A41CUL))) +#define bM4_USBFS_HCCHAR1_MPSIZ8 (*((volatile unsigned int*)(0x4380A420UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ9 (*((volatile unsigned int*)(0x4380A424UL))) +#define bM4_USBFS_HCCHAR1_MPSIZ10 (*((volatile unsigned int*)(0x4380A428UL))) +#define bM4_USBFS_HCCHAR1_EPNUM0 (*((volatile unsigned int*)(0x4380A42CUL))) +#define bM4_USBFS_HCCHAR1_EPNUM1 (*((volatile unsigned int*)(0x4380A430UL))) +#define bM4_USBFS_HCCHAR1_EPNUM2 (*((volatile unsigned int*)(0x4380A434UL))) +#define bM4_USBFS_HCCHAR1_EPNUM3 (*((volatile unsigned int*)(0x4380A438UL))) +#define bM4_USBFS_HCCHAR1_EPDIR (*((volatile unsigned int*)(0x4380A43CUL))) +#define bM4_USBFS_HCCHAR1_LSDEV (*((volatile unsigned int*)(0x4380A444UL))) +#define bM4_USBFS_HCCHAR1_EPTYP0 (*((volatile unsigned int*)(0x4380A448UL))) +#define bM4_USBFS_HCCHAR1_EPTYP1 (*((volatile unsigned int*)(0x4380A44CUL))) +#define bM4_USBFS_HCCHAR1_DAD0 (*((volatile unsigned int*)(0x4380A458UL))) +#define bM4_USBFS_HCCHAR1_DAD1 (*((volatile unsigned int*)(0x4380A45CUL))) +#define bM4_USBFS_HCCHAR1_DAD2 (*((volatile unsigned int*)(0x4380A460UL))) +#define bM4_USBFS_HCCHAR1_DAD3 (*((volatile unsigned int*)(0x4380A464UL))) +#define bM4_USBFS_HCCHAR1_DAD4 (*((volatile unsigned int*)(0x4380A468UL))) +#define bM4_USBFS_HCCHAR1_DAD5 (*((volatile unsigned int*)(0x4380A46CUL))) +#define bM4_USBFS_HCCHAR1_DAD6 (*((volatile unsigned int*)(0x4380A470UL))) +#define bM4_USBFS_HCCHAR1_ODDFRM (*((volatile unsigned int*)(0x4380A474UL))) +#define bM4_USBFS_HCCHAR1_CHDIS (*((volatile unsigned int*)(0x4380A478UL))) +#define bM4_USBFS_HCCHAR1_CHENA (*((volatile unsigned int*)(0x4380A47CUL))) +#define bM4_USBFS_HCINT1_XFRC (*((volatile unsigned int*)(0x4380A500UL))) +#define bM4_USBFS_HCINT1_CHH (*((volatile unsigned int*)(0x4380A504UL))) +#define bM4_USBFS_HCINT1_STALL (*((volatile unsigned int*)(0x4380A50CUL))) +#define bM4_USBFS_HCINT1_NAK (*((volatile unsigned int*)(0x4380A510UL))) +#define bM4_USBFS_HCINT1_ACK (*((volatile unsigned int*)(0x4380A514UL))) +#define bM4_USBFS_HCINT1_TXERR (*((volatile unsigned int*)(0x4380A51CUL))) +#define bM4_USBFS_HCINT1_BBERR (*((volatile unsigned int*)(0x4380A520UL))) +#define bM4_USBFS_HCINT1_FRMOR (*((volatile unsigned int*)(0x4380A524UL))) +#define bM4_USBFS_HCINT1_DTERR (*((volatile unsigned int*)(0x4380A528UL))) +#define bM4_USBFS_HCINTMSK1_XFRCM (*((volatile unsigned int*)(0x4380A580UL))) +#define bM4_USBFS_HCINTMSK1_CHHM (*((volatile unsigned int*)(0x4380A584UL))) +#define bM4_USBFS_HCINTMSK1_STALLM (*((volatile unsigned int*)(0x4380A58CUL))) +#define bM4_USBFS_HCINTMSK1_NAKM (*((volatile unsigned int*)(0x4380A590UL))) +#define bM4_USBFS_HCINTMSK1_ACKM (*((volatile unsigned int*)(0x4380A594UL))) +#define bM4_USBFS_HCINTMSK1_TXERRM (*((volatile unsigned int*)(0x4380A59CUL))) +#define bM4_USBFS_HCINTMSK1_BBERRM (*((volatile unsigned int*)(0x4380A5A0UL))) +#define bM4_USBFS_HCINTMSK1_FRMORM (*((volatile unsigned int*)(0x4380A5A4UL))) +#define bM4_USBFS_HCINTMSK1_DTERRM (*((volatile unsigned int*)(0x4380A5A8UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x4380A600UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x4380A604UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x4380A608UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4380A60CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x4380A610UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x4380A614UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x4380A618UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4380A61CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x4380A620UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x4380A624UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x4380A628UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4380A62CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x4380A630UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x4380A634UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x4380A638UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4380A63CUL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x4380A640UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x4380A644UL))) +#define bM4_USBFS_HCTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x4380A648UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4380A64CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x4380A650UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x4380A654UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x4380A658UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4380A65CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x4380A660UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x4380A664UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x4380A668UL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4380A66CUL))) +#define bM4_USBFS_HCTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x4380A670UL))) +#define bM4_USBFS_HCTSIZ1_DPID0 (*((volatile unsigned int*)(0x4380A674UL))) +#define bM4_USBFS_HCTSIZ1_DPID1 (*((volatile unsigned int*)(0x4380A678UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ0 (*((volatile unsigned int*)(0x4380A800UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ1 (*((volatile unsigned int*)(0x4380A804UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ2 (*((volatile unsigned int*)(0x4380A808UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ3 (*((volatile unsigned int*)(0x4380A80CUL))) +#define bM4_USBFS_HCCHAR2_MPSIZ4 (*((volatile unsigned int*)(0x4380A810UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ5 (*((volatile unsigned int*)(0x4380A814UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ6 (*((volatile unsigned int*)(0x4380A818UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ7 (*((volatile unsigned int*)(0x4380A81CUL))) +#define bM4_USBFS_HCCHAR2_MPSIZ8 (*((volatile unsigned int*)(0x4380A820UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ9 (*((volatile unsigned int*)(0x4380A824UL))) +#define bM4_USBFS_HCCHAR2_MPSIZ10 (*((volatile unsigned int*)(0x4380A828UL))) +#define bM4_USBFS_HCCHAR2_EPNUM0 (*((volatile unsigned int*)(0x4380A82CUL))) +#define bM4_USBFS_HCCHAR2_EPNUM1 (*((volatile unsigned int*)(0x4380A830UL))) +#define bM4_USBFS_HCCHAR2_EPNUM2 (*((volatile unsigned int*)(0x4380A834UL))) +#define bM4_USBFS_HCCHAR2_EPNUM3 (*((volatile unsigned int*)(0x4380A838UL))) +#define bM4_USBFS_HCCHAR2_EPDIR (*((volatile unsigned int*)(0x4380A83CUL))) +#define bM4_USBFS_HCCHAR2_LSDEV (*((volatile unsigned int*)(0x4380A844UL))) +#define bM4_USBFS_HCCHAR2_EPTYP0 (*((volatile unsigned int*)(0x4380A848UL))) +#define bM4_USBFS_HCCHAR2_EPTYP1 (*((volatile unsigned int*)(0x4380A84CUL))) +#define bM4_USBFS_HCCHAR2_DAD0 (*((volatile unsigned int*)(0x4380A858UL))) +#define bM4_USBFS_HCCHAR2_DAD1 (*((volatile unsigned int*)(0x4380A85CUL))) +#define bM4_USBFS_HCCHAR2_DAD2 (*((volatile unsigned int*)(0x4380A860UL))) +#define bM4_USBFS_HCCHAR2_DAD3 (*((volatile unsigned int*)(0x4380A864UL))) +#define bM4_USBFS_HCCHAR2_DAD4 (*((volatile unsigned int*)(0x4380A868UL))) +#define bM4_USBFS_HCCHAR2_DAD5 (*((volatile unsigned int*)(0x4380A86CUL))) +#define bM4_USBFS_HCCHAR2_DAD6 (*((volatile unsigned int*)(0x4380A870UL))) +#define bM4_USBFS_HCCHAR2_ODDFRM (*((volatile unsigned int*)(0x4380A874UL))) +#define bM4_USBFS_HCCHAR2_CHDIS (*((volatile unsigned int*)(0x4380A878UL))) +#define bM4_USBFS_HCCHAR2_CHENA (*((volatile unsigned int*)(0x4380A87CUL))) +#define bM4_USBFS_HCINT2_XFRC (*((volatile unsigned int*)(0x4380A900UL))) +#define bM4_USBFS_HCINT2_CHH (*((volatile unsigned int*)(0x4380A904UL))) +#define bM4_USBFS_HCINT2_STALL (*((volatile unsigned int*)(0x4380A90CUL))) +#define bM4_USBFS_HCINT2_NAK (*((volatile unsigned int*)(0x4380A910UL))) +#define bM4_USBFS_HCINT2_ACK (*((volatile unsigned int*)(0x4380A914UL))) +#define bM4_USBFS_HCINT2_TXERR (*((volatile unsigned int*)(0x4380A91CUL))) +#define bM4_USBFS_HCINT2_BBERR (*((volatile unsigned int*)(0x4380A920UL))) +#define bM4_USBFS_HCINT2_FRMOR (*((volatile unsigned int*)(0x4380A924UL))) +#define bM4_USBFS_HCINT2_DTERR (*((volatile unsigned int*)(0x4380A928UL))) +#define bM4_USBFS_HCINTMSK2_XFRCM (*((volatile unsigned int*)(0x4380A980UL))) +#define bM4_USBFS_HCINTMSK2_CHHM (*((volatile unsigned int*)(0x4380A984UL))) +#define bM4_USBFS_HCINTMSK2_STALLM (*((volatile unsigned int*)(0x4380A98CUL))) +#define bM4_USBFS_HCINTMSK2_NAKM (*((volatile unsigned int*)(0x4380A990UL))) +#define bM4_USBFS_HCINTMSK2_ACKM (*((volatile unsigned int*)(0x4380A994UL))) +#define bM4_USBFS_HCINTMSK2_TXERRM (*((volatile unsigned int*)(0x4380A99CUL))) +#define bM4_USBFS_HCINTMSK2_BBERRM (*((volatile unsigned int*)(0x4380A9A0UL))) +#define bM4_USBFS_HCINTMSK2_FRMORM (*((volatile unsigned int*)(0x4380A9A4UL))) +#define bM4_USBFS_HCINTMSK2_DTERRM (*((volatile unsigned int*)(0x4380A9A8UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x4380AA00UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x4380AA04UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x4380AA08UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x4380AA0CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x4380AA10UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x4380AA14UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x4380AA18UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x4380AA1CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x4380AA20UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x4380AA24UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x4380AA28UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x4380AA2CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x4380AA30UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x4380AA34UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x4380AA38UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x4380AA3CUL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x4380AA40UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x4380AA44UL))) +#define bM4_USBFS_HCTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x4380AA48UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x4380AA4CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x4380AA50UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x4380AA54UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x4380AA58UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x4380AA5CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x4380AA60UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x4380AA64UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x4380AA68UL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x4380AA6CUL))) +#define bM4_USBFS_HCTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x4380AA70UL))) +#define bM4_USBFS_HCTSIZ2_DPID0 (*((volatile unsigned int*)(0x4380AA74UL))) +#define bM4_USBFS_HCTSIZ2_DPID1 (*((volatile unsigned int*)(0x4380AA78UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ0 (*((volatile unsigned int*)(0x4380AC00UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ1 (*((volatile unsigned int*)(0x4380AC04UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ2 (*((volatile unsigned int*)(0x4380AC08UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ3 (*((volatile unsigned int*)(0x4380AC0CUL))) +#define bM4_USBFS_HCCHAR3_MPSIZ4 (*((volatile unsigned int*)(0x4380AC10UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ5 (*((volatile unsigned int*)(0x4380AC14UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ6 (*((volatile unsigned int*)(0x4380AC18UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ7 (*((volatile unsigned int*)(0x4380AC1CUL))) +#define bM4_USBFS_HCCHAR3_MPSIZ8 (*((volatile unsigned int*)(0x4380AC20UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ9 (*((volatile unsigned int*)(0x4380AC24UL))) +#define bM4_USBFS_HCCHAR3_MPSIZ10 (*((volatile unsigned int*)(0x4380AC28UL))) +#define bM4_USBFS_HCCHAR3_EPNUM0 (*((volatile unsigned int*)(0x4380AC2CUL))) +#define bM4_USBFS_HCCHAR3_EPNUM1 (*((volatile unsigned int*)(0x4380AC30UL))) +#define bM4_USBFS_HCCHAR3_EPNUM2 (*((volatile unsigned int*)(0x4380AC34UL))) +#define bM4_USBFS_HCCHAR3_EPNUM3 (*((volatile unsigned int*)(0x4380AC38UL))) +#define bM4_USBFS_HCCHAR3_EPDIR (*((volatile unsigned int*)(0x4380AC3CUL))) +#define bM4_USBFS_HCCHAR3_LSDEV (*((volatile unsigned int*)(0x4380AC44UL))) +#define bM4_USBFS_HCCHAR3_EPTYP0 (*((volatile unsigned int*)(0x4380AC48UL))) +#define bM4_USBFS_HCCHAR3_EPTYP1 (*((volatile unsigned int*)(0x4380AC4CUL))) +#define bM4_USBFS_HCCHAR3_DAD0 (*((volatile unsigned int*)(0x4380AC58UL))) +#define bM4_USBFS_HCCHAR3_DAD1 (*((volatile unsigned int*)(0x4380AC5CUL))) +#define bM4_USBFS_HCCHAR3_DAD2 (*((volatile unsigned int*)(0x4380AC60UL))) +#define bM4_USBFS_HCCHAR3_DAD3 (*((volatile unsigned int*)(0x4380AC64UL))) +#define bM4_USBFS_HCCHAR3_DAD4 (*((volatile unsigned int*)(0x4380AC68UL))) +#define bM4_USBFS_HCCHAR3_DAD5 (*((volatile unsigned int*)(0x4380AC6CUL))) +#define bM4_USBFS_HCCHAR3_DAD6 (*((volatile unsigned int*)(0x4380AC70UL))) +#define bM4_USBFS_HCCHAR3_ODDFRM (*((volatile unsigned int*)(0x4380AC74UL))) +#define bM4_USBFS_HCCHAR3_CHDIS (*((volatile unsigned int*)(0x4380AC78UL))) +#define bM4_USBFS_HCCHAR3_CHENA (*((volatile unsigned int*)(0x4380AC7CUL))) +#define bM4_USBFS_HCINT3_XFRC (*((volatile unsigned int*)(0x4380AD00UL))) +#define bM4_USBFS_HCINT3_CHH (*((volatile unsigned int*)(0x4380AD04UL))) +#define bM4_USBFS_HCINT3_STALL (*((volatile unsigned int*)(0x4380AD0CUL))) +#define bM4_USBFS_HCINT3_NAK (*((volatile unsigned int*)(0x4380AD10UL))) +#define bM4_USBFS_HCINT3_ACK (*((volatile unsigned int*)(0x4380AD14UL))) +#define bM4_USBFS_HCINT3_TXERR (*((volatile unsigned int*)(0x4380AD1CUL))) +#define bM4_USBFS_HCINT3_BBERR (*((volatile unsigned int*)(0x4380AD20UL))) +#define bM4_USBFS_HCINT3_FRMOR (*((volatile unsigned int*)(0x4380AD24UL))) +#define bM4_USBFS_HCINT3_DTERR (*((volatile unsigned int*)(0x4380AD28UL))) +#define bM4_USBFS_HCINTMSK3_XFRCM (*((volatile unsigned int*)(0x4380AD80UL))) +#define bM4_USBFS_HCINTMSK3_CHHM (*((volatile unsigned int*)(0x4380AD84UL))) +#define bM4_USBFS_HCINTMSK3_STALLM (*((volatile unsigned int*)(0x4380AD8CUL))) +#define bM4_USBFS_HCINTMSK3_NAKM (*((volatile unsigned int*)(0x4380AD90UL))) +#define bM4_USBFS_HCINTMSK3_ACKM (*((volatile unsigned int*)(0x4380AD94UL))) +#define bM4_USBFS_HCINTMSK3_TXERRM (*((volatile unsigned int*)(0x4380AD9CUL))) +#define bM4_USBFS_HCINTMSK3_BBERRM (*((volatile unsigned int*)(0x4380ADA0UL))) +#define bM4_USBFS_HCINTMSK3_FRMORM (*((volatile unsigned int*)(0x4380ADA4UL))) +#define bM4_USBFS_HCINTMSK3_DTERRM (*((volatile unsigned int*)(0x4380ADA8UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x4380AE00UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x4380AE04UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x4380AE08UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x4380AE0CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x4380AE10UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x4380AE14UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x4380AE18UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x4380AE1CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x4380AE20UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x4380AE24UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x4380AE28UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x4380AE2CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x4380AE30UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x4380AE34UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x4380AE38UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x4380AE3CUL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x4380AE40UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x4380AE44UL))) +#define bM4_USBFS_HCTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x4380AE48UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x4380AE4CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x4380AE50UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x4380AE54UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x4380AE58UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x4380AE5CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x4380AE60UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x4380AE64UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x4380AE68UL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x4380AE6CUL))) +#define bM4_USBFS_HCTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x4380AE70UL))) +#define bM4_USBFS_HCTSIZ3_DPID0 (*((volatile unsigned int*)(0x4380AE74UL))) +#define bM4_USBFS_HCTSIZ3_DPID1 (*((volatile unsigned int*)(0x4380AE78UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ0 (*((volatile unsigned int*)(0x4380B000UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ1 (*((volatile unsigned int*)(0x4380B004UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ2 (*((volatile unsigned int*)(0x4380B008UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ3 (*((volatile unsigned int*)(0x4380B00CUL))) +#define bM4_USBFS_HCCHAR4_MPSIZ4 (*((volatile unsigned int*)(0x4380B010UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ5 (*((volatile unsigned int*)(0x4380B014UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ6 (*((volatile unsigned int*)(0x4380B018UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ7 (*((volatile unsigned int*)(0x4380B01CUL))) +#define bM4_USBFS_HCCHAR4_MPSIZ8 (*((volatile unsigned int*)(0x4380B020UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ9 (*((volatile unsigned int*)(0x4380B024UL))) +#define bM4_USBFS_HCCHAR4_MPSIZ10 (*((volatile unsigned int*)(0x4380B028UL))) +#define bM4_USBFS_HCCHAR4_EPNUM0 (*((volatile unsigned int*)(0x4380B02CUL))) +#define bM4_USBFS_HCCHAR4_EPNUM1 (*((volatile unsigned int*)(0x4380B030UL))) +#define bM4_USBFS_HCCHAR4_EPNUM2 (*((volatile unsigned int*)(0x4380B034UL))) +#define bM4_USBFS_HCCHAR4_EPNUM3 (*((volatile unsigned int*)(0x4380B038UL))) +#define bM4_USBFS_HCCHAR4_EPDIR (*((volatile unsigned int*)(0x4380B03CUL))) +#define bM4_USBFS_HCCHAR4_LSDEV (*((volatile unsigned int*)(0x4380B044UL))) +#define bM4_USBFS_HCCHAR4_EPTYP0 (*((volatile unsigned int*)(0x4380B048UL))) +#define bM4_USBFS_HCCHAR4_EPTYP1 (*((volatile unsigned int*)(0x4380B04CUL))) +#define bM4_USBFS_HCCHAR4_DAD0 (*((volatile unsigned int*)(0x4380B058UL))) +#define bM4_USBFS_HCCHAR4_DAD1 (*((volatile unsigned int*)(0x4380B05CUL))) +#define bM4_USBFS_HCCHAR4_DAD2 (*((volatile unsigned int*)(0x4380B060UL))) +#define bM4_USBFS_HCCHAR4_DAD3 (*((volatile unsigned int*)(0x4380B064UL))) +#define bM4_USBFS_HCCHAR4_DAD4 (*((volatile unsigned int*)(0x4380B068UL))) +#define bM4_USBFS_HCCHAR4_DAD5 (*((volatile unsigned int*)(0x4380B06CUL))) +#define bM4_USBFS_HCCHAR4_DAD6 (*((volatile unsigned int*)(0x4380B070UL))) +#define bM4_USBFS_HCCHAR4_ODDFRM (*((volatile unsigned int*)(0x4380B074UL))) +#define bM4_USBFS_HCCHAR4_CHDIS (*((volatile unsigned int*)(0x4380B078UL))) +#define bM4_USBFS_HCCHAR4_CHENA (*((volatile unsigned int*)(0x4380B07CUL))) +#define bM4_USBFS_HCINT4_XFRC (*((volatile unsigned int*)(0x4380B100UL))) +#define bM4_USBFS_HCINT4_CHH (*((volatile unsigned int*)(0x4380B104UL))) +#define bM4_USBFS_HCINT4_STALL (*((volatile unsigned int*)(0x4380B10CUL))) +#define bM4_USBFS_HCINT4_NAK (*((volatile unsigned int*)(0x4380B110UL))) +#define bM4_USBFS_HCINT4_ACK (*((volatile unsigned int*)(0x4380B114UL))) +#define bM4_USBFS_HCINT4_TXERR (*((volatile unsigned int*)(0x4380B11CUL))) +#define bM4_USBFS_HCINT4_BBERR (*((volatile unsigned int*)(0x4380B120UL))) +#define bM4_USBFS_HCINT4_FRMOR (*((volatile unsigned int*)(0x4380B124UL))) +#define bM4_USBFS_HCINT4_DTERR (*((volatile unsigned int*)(0x4380B128UL))) +#define bM4_USBFS_HCINTMSK4_XFRCM (*((volatile unsigned int*)(0x4380B180UL))) +#define bM4_USBFS_HCINTMSK4_CHHM (*((volatile unsigned int*)(0x4380B184UL))) +#define bM4_USBFS_HCINTMSK4_STALLM (*((volatile unsigned int*)(0x4380B18CUL))) +#define bM4_USBFS_HCINTMSK4_NAKM (*((volatile unsigned int*)(0x4380B190UL))) +#define bM4_USBFS_HCINTMSK4_ACKM (*((volatile unsigned int*)(0x4380B194UL))) +#define bM4_USBFS_HCINTMSK4_TXERRM (*((volatile unsigned int*)(0x4380B19CUL))) +#define bM4_USBFS_HCINTMSK4_BBERRM (*((volatile unsigned int*)(0x4380B1A0UL))) +#define bM4_USBFS_HCINTMSK4_FRMORM (*((volatile unsigned int*)(0x4380B1A4UL))) +#define bM4_USBFS_HCINTMSK4_DTERRM (*((volatile unsigned int*)(0x4380B1A8UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x4380B200UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x4380B204UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x4380B208UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4380B20CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x4380B210UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x4380B214UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x4380B218UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4380B21CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x4380B220UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x4380B224UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x4380B228UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4380B22CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x4380B230UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x4380B234UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x4380B238UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4380B23CUL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x4380B240UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x4380B244UL))) +#define bM4_USBFS_HCTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x4380B248UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4380B24CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x4380B250UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x4380B254UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x4380B258UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4380B25CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x4380B260UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x4380B264UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x4380B268UL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4380B26CUL))) +#define bM4_USBFS_HCTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x4380B270UL))) +#define bM4_USBFS_HCTSIZ4_DPID0 (*((volatile unsigned int*)(0x4380B274UL))) +#define bM4_USBFS_HCTSIZ4_DPID1 (*((volatile unsigned int*)(0x4380B278UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ0 (*((volatile unsigned int*)(0x4380B400UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ1 (*((volatile unsigned int*)(0x4380B404UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ2 (*((volatile unsigned int*)(0x4380B408UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ3 (*((volatile unsigned int*)(0x4380B40CUL))) +#define bM4_USBFS_HCCHAR5_MPSIZ4 (*((volatile unsigned int*)(0x4380B410UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ5 (*((volatile unsigned int*)(0x4380B414UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ6 (*((volatile unsigned int*)(0x4380B418UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ7 (*((volatile unsigned int*)(0x4380B41CUL))) +#define bM4_USBFS_HCCHAR5_MPSIZ8 (*((volatile unsigned int*)(0x4380B420UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ9 (*((volatile unsigned int*)(0x4380B424UL))) +#define bM4_USBFS_HCCHAR5_MPSIZ10 (*((volatile unsigned int*)(0x4380B428UL))) +#define bM4_USBFS_HCCHAR5_EPNUM0 (*((volatile unsigned int*)(0x4380B42CUL))) +#define bM4_USBFS_HCCHAR5_EPNUM1 (*((volatile unsigned int*)(0x4380B430UL))) +#define bM4_USBFS_HCCHAR5_EPNUM2 (*((volatile unsigned int*)(0x4380B434UL))) +#define bM4_USBFS_HCCHAR5_EPNUM3 (*((volatile unsigned int*)(0x4380B438UL))) +#define bM4_USBFS_HCCHAR5_EPDIR (*((volatile unsigned int*)(0x4380B43CUL))) +#define bM4_USBFS_HCCHAR5_LSDEV (*((volatile unsigned int*)(0x4380B444UL))) +#define bM4_USBFS_HCCHAR5_EPTYP0 (*((volatile unsigned int*)(0x4380B448UL))) +#define bM4_USBFS_HCCHAR5_EPTYP1 (*((volatile unsigned int*)(0x4380B44CUL))) +#define bM4_USBFS_HCCHAR5_DAD0 (*((volatile unsigned int*)(0x4380B458UL))) +#define bM4_USBFS_HCCHAR5_DAD1 (*((volatile unsigned int*)(0x4380B45CUL))) +#define bM4_USBFS_HCCHAR5_DAD2 (*((volatile unsigned int*)(0x4380B460UL))) +#define bM4_USBFS_HCCHAR5_DAD3 (*((volatile unsigned int*)(0x4380B464UL))) +#define bM4_USBFS_HCCHAR5_DAD4 (*((volatile unsigned int*)(0x4380B468UL))) +#define bM4_USBFS_HCCHAR5_DAD5 (*((volatile unsigned int*)(0x4380B46CUL))) +#define bM4_USBFS_HCCHAR5_DAD6 (*((volatile unsigned int*)(0x4380B470UL))) +#define bM4_USBFS_HCCHAR5_ODDFRM (*((volatile unsigned int*)(0x4380B474UL))) +#define bM4_USBFS_HCCHAR5_CHDIS (*((volatile unsigned int*)(0x4380B478UL))) +#define bM4_USBFS_HCCHAR5_CHENA (*((volatile unsigned int*)(0x4380B47CUL))) +#define bM4_USBFS_HCINT5_XFRC (*((volatile unsigned int*)(0x4380B500UL))) +#define bM4_USBFS_HCINT5_CHH (*((volatile unsigned int*)(0x4380B504UL))) +#define bM4_USBFS_HCINT5_STALL (*((volatile unsigned int*)(0x4380B50CUL))) +#define bM4_USBFS_HCINT5_NAK (*((volatile unsigned int*)(0x4380B510UL))) +#define bM4_USBFS_HCINT5_ACK (*((volatile unsigned int*)(0x4380B514UL))) +#define bM4_USBFS_HCINT5_TXERR (*((volatile unsigned int*)(0x4380B51CUL))) +#define bM4_USBFS_HCINT5_BBERR (*((volatile unsigned int*)(0x4380B520UL))) +#define bM4_USBFS_HCINT5_FRMOR (*((volatile unsigned int*)(0x4380B524UL))) +#define bM4_USBFS_HCINT5_DTERR (*((volatile unsigned int*)(0x4380B528UL))) +#define bM4_USBFS_HCINTMSK5_XFRCM (*((volatile unsigned int*)(0x4380B580UL))) +#define bM4_USBFS_HCINTMSK5_CHHM (*((volatile unsigned int*)(0x4380B584UL))) +#define bM4_USBFS_HCINTMSK5_STALLM (*((volatile unsigned int*)(0x4380B58CUL))) +#define bM4_USBFS_HCINTMSK5_NAKM (*((volatile unsigned int*)(0x4380B590UL))) +#define bM4_USBFS_HCINTMSK5_ACKM (*((volatile unsigned int*)(0x4380B594UL))) +#define bM4_USBFS_HCINTMSK5_TXERRM (*((volatile unsigned int*)(0x4380B59CUL))) +#define bM4_USBFS_HCINTMSK5_BBERRM (*((volatile unsigned int*)(0x4380B5A0UL))) +#define bM4_USBFS_HCINTMSK5_FRMORM (*((volatile unsigned int*)(0x4380B5A4UL))) +#define bM4_USBFS_HCINTMSK5_DTERRM (*((volatile unsigned int*)(0x4380B5A8UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x4380B600UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x4380B604UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x4380B608UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4380B60CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x4380B610UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x4380B614UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x4380B618UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4380B61CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x4380B620UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x4380B624UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x4380B628UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4380B62CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x4380B630UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x4380B634UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x4380B638UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4380B63CUL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x4380B640UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x4380B644UL))) +#define bM4_USBFS_HCTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x4380B648UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4380B64CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x4380B650UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x4380B654UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x4380B658UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4380B65CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x4380B660UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x4380B664UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x4380B668UL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4380B66CUL))) +#define bM4_USBFS_HCTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x4380B670UL))) +#define bM4_USBFS_HCTSIZ5_DPID0 (*((volatile unsigned int*)(0x4380B674UL))) +#define bM4_USBFS_HCTSIZ5_DPID1 (*((volatile unsigned int*)(0x4380B678UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ0 (*((volatile unsigned int*)(0x4380B800UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ1 (*((volatile unsigned int*)(0x4380B804UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ2 (*((volatile unsigned int*)(0x4380B808UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ3 (*((volatile unsigned int*)(0x4380B80CUL))) +#define bM4_USBFS_HCCHAR6_MPSIZ4 (*((volatile unsigned int*)(0x4380B810UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ5 (*((volatile unsigned int*)(0x4380B814UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ6 (*((volatile unsigned int*)(0x4380B818UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ7 (*((volatile unsigned int*)(0x4380B81CUL))) +#define bM4_USBFS_HCCHAR6_MPSIZ8 (*((volatile unsigned int*)(0x4380B820UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ9 (*((volatile unsigned int*)(0x4380B824UL))) +#define bM4_USBFS_HCCHAR6_MPSIZ10 (*((volatile unsigned int*)(0x4380B828UL))) +#define bM4_USBFS_HCCHAR6_EPNUM0 (*((volatile unsigned int*)(0x4380B82CUL))) +#define bM4_USBFS_HCCHAR6_EPNUM1 (*((volatile unsigned int*)(0x4380B830UL))) +#define bM4_USBFS_HCCHAR6_EPNUM2 (*((volatile unsigned int*)(0x4380B834UL))) +#define bM4_USBFS_HCCHAR6_EPNUM3 (*((volatile unsigned int*)(0x4380B838UL))) +#define bM4_USBFS_HCCHAR6_EPDIR (*((volatile unsigned int*)(0x4380B83CUL))) +#define bM4_USBFS_HCCHAR6_LSDEV (*((volatile unsigned int*)(0x4380B844UL))) +#define bM4_USBFS_HCCHAR6_EPTYP0 (*((volatile unsigned int*)(0x4380B848UL))) +#define bM4_USBFS_HCCHAR6_EPTYP1 (*((volatile unsigned int*)(0x4380B84CUL))) +#define bM4_USBFS_HCCHAR6_DAD0 (*((volatile unsigned int*)(0x4380B858UL))) +#define bM4_USBFS_HCCHAR6_DAD1 (*((volatile unsigned int*)(0x4380B85CUL))) +#define bM4_USBFS_HCCHAR6_DAD2 (*((volatile unsigned int*)(0x4380B860UL))) +#define bM4_USBFS_HCCHAR6_DAD3 (*((volatile unsigned int*)(0x4380B864UL))) +#define bM4_USBFS_HCCHAR6_DAD4 (*((volatile unsigned int*)(0x4380B868UL))) +#define bM4_USBFS_HCCHAR6_DAD5 (*((volatile unsigned int*)(0x4380B86CUL))) +#define bM4_USBFS_HCCHAR6_DAD6 (*((volatile unsigned int*)(0x4380B870UL))) +#define bM4_USBFS_HCCHAR6_ODDFRM (*((volatile unsigned int*)(0x4380B874UL))) +#define bM4_USBFS_HCCHAR6_CHDIS (*((volatile unsigned int*)(0x4380B878UL))) +#define bM4_USBFS_HCCHAR6_CHENA (*((volatile unsigned int*)(0x4380B87CUL))) +#define bM4_USBFS_HCINT6_XFRC (*((volatile unsigned int*)(0x4380B900UL))) +#define bM4_USBFS_HCINT6_CHH (*((volatile unsigned int*)(0x4380B904UL))) +#define bM4_USBFS_HCINT6_STALL (*((volatile unsigned int*)(0x4380B90CUL))) +#define bM4_USBFS_HCINT6_NAK (*((volatile unsigned int*)(0x4380B910UL))) +#define bM4_USBFS_HCINT6_ACK (*((volatile unsigned int*)(0x4380B914UL))) +#define bM4_USBFS_HCINT6_TXERR (*((volatile unsigned int*)(0x4380B91CUL))) +#define bM4_USBFS_HCINT6_BBERR (*((volatile unsigned int*)(0x4380B920UL))) +#define bM4_USBFS_HCINT6_FRMOR (*((volatile unsigned int*)(0x4380B924UL))) +#define bM4_USBFS_HCINT6_DTERR (*((volatile unsigned int*)(0x4380B928UL))) +#define bM4_USBFS_HCINTMSK6_XFRCM (*((volatile unsigned int*)(0x4380B980UL))) +#define bM4_USBFS_HCINTMSK6_CHHM (*((volatile unsigned int*)(0x4380B984UL))) +#define bM4_USBFS_HCINTMSK6_STALLM (*((volatile unsigned int*)(0x4380B98CUL))) +#define bM4_USBFS_HCINTMSK6_NAKM (*((volatile unsigned int*)(0x4380B990UL))) +#define bM4_USBFS_HCINTMSK6_ACKM (*((volatile unsigned int*)(0x4380B994UL))) +#define bM4_USBFS_HCINTMSK6_TXERRM (*((volatile unsigned int*)(0x4380B99CUL))) +#define bM4_USBFS_HCINTMSK6_BBERRM (*((volatile unsigned int*)(0x4380B9A0UL))) +#define bM4_USBFS_HCINTMSK6_FRMORM (*((volatile unsigned int*)(0x4380B9A4UL))) +#define bM4_USBFS_HCINTMSK6_DTERRM (*((volatile unsigned int*)(0x4380B9A8UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ0 (*((volatile unsigned int*)(0x4380BA00UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ1 (*((volatile unsigned int*)(0x4380BA04UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ2 (*((volatile unsigned int*)(0x4380BA08UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ3 (*((volatile unsigned int*)(0x4380BA0CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ4 (*((volatile unsigned int*)(0x4380BA10UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ5 (*((volatile unsigned int*)(0x4380BA14UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ6 (*((volatile unsigned int*)(0x4380BA18UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ7 (*((volatile unsigned int*)(0x4380BA1CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ8 (*((volatile unsigned int*)(0x4380BA20UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ9 (*((volatile unsigned int*)(0x4380BA24UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ10 (*((volatile unsigned int*)(0x4380BA28UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ11 (*((volatile unsigned int*)(0x4380BA2CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ12 (*((volatile unsigned int*)(0x4380BA30UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ13 (*((volatile unsigned int*)(0x4380BA34UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ14 (*((volatile unsigned int*)(0x4380BA38UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ15 (*((volatile unsigned int*)(0x4380BA3CUL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ16 (*((volatile unsigned int*)(0x4380BA40UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ17 (*((volatile unsigned int*)(0x4380BA44UL))) +#define bM4_USBFS_HCTSIZ6_XFRSIZ18 (*((volatile unsigned int*)(0x4380BA48UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT0 (*((volatile unsigned int*)(0x4380BA4CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT1 (*((volatile unsigned int*)(0x4380BA50UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT2 (*((volatile unsigned int*)(0x4380BA54UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT3 (*((volatile unsigned int*)(0x4380BA58UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT4 (*((volatile unsigned int*)(0x4380BA5CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT5 (*((volatile unsigned int*)(0x4380BA60UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT6 (*((volatile unsigned int*)(0x4380BA64UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT7 (*((volatile unsigned int*)(0x4380BA68UL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT8 (*((volatile unsigned int*)(0x4380BA6CUL))) +#define bM4_USBFS_HCTSIZ6_PKTCNT9 (*((volatile unsigned int*)(0x4380BA70UL))) +#define bM4_USBFS_HCTSIZ6_DPID0 (*((volatile unsigned int*)(0x4380BA74UL))) +#define bM4_USBFS_HCTSIZ6_DPID1 (*((volatile unsigned int*)(0x4380BA78UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ0 (*((volatile unsigned int*)(0x4380BC00UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ1 (*((volatile unsigned int*)(0x4380BC04UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ2 (*((volatile unsigned int*)(0x4380BC08UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ3 (*((volatile unsigned int*)(0x4380BC0CUL))) +#define bM4_USBFS_HCCHAR7_MPSIZ4 (*((volatile unsigned int*)(0x4380BC10UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ5 (*((volatile unsigned int*)(0x4380BC14UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ6 (*((volatile unsigned int*)(0x4380BC18UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ7 (*((volatile unsigned int*)(0x4380BC1CUL))) +#define bM4_USBFS_HCCHAR7_MPSIZ8 (*((volatile unsigned int*)(0x4380BC20UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ9 (*((volatile unsigned int*)(0x4380BC24UL))) +#define bM4_USBFS_HCCHAR7_MPSIZ10 (*((volatile unsigned int*)(0x4380BC28UL))) +#define bM4_USBFS_HCCHAR7_EPNUM0 (*((volatile unsigned int*)(0x4380BC2CUL))) +#define bM4_USBFS_HCCHAR7_EPNUM1 (*((volatile unsigned int*)(0x4380BC30UL))) +#define bM4_USBFS_HCCHAR7_EPNUM2 (*((volatile unsigned int*)(0x4380BC34UL))) +#define bM4_USBFS_HCCHAR7_EPNUM3 (*((volatile unsigned int*)(0x4380BC38UL))) +#define bM4_USBFS_HCCHAR7_EPDIR (*((volatile unsigned int*)(0x4380BC3CUL))) +#define bM4_USBFS_HCCHAR7_LSDEV (*((volatile unsigned int*)(0x4380BC44UL))) +#define bM4_USBFS_HCCHAR7_EPTYP0 (*((volatile unsigned int*)(0x4380BC48UL))) +#define bM4_USBFS_HCCHAR7_EPTYP1 (*((volatile unsigned int*)(0x4380BC4CUL))) +#define bM4_USBFS_HCCHAR7_DAD0 (*((volatile unsigned int*)(0x4380BC58UL))) +#define bM4_USBFS_HCCHAR7_DAD1 (*((volatile unsigned int*)(0x4380BC5CUL))) +#define bM4_USBFS_HCCHAR7_DAD2 (*((volatile unsigned int*)(0x4380BC60UL))) +#define bM4_USBFS_HCCHAR7_DAD3 (*((volatile unsigned int*)(0x4380BC64UL))) +#define bM4_USBFS_HCCHAR7_DAD4 (*((volatile unsigned int*)(0x4380BC68UL))) +#define bM4_USBFS_HCCHAR7_DAD5 (*((volatile unsigned int*)(0x4380BC6CUL))) +#define bM4_USBFS_HCCHAR7_DAD6 (*((volatile unsigned int*)(0x4380BC70UL))) +#define bM4_USBFS_HCCHAR7_ODDFRM (*((volatile unsigned int*)(0x4380BC74UL))) +#define bM4_USBFS_HCCHAR7_CHDIS (*((volatile unsigned int*)(0x4380BC78UL))) +#define bM4_USBFS_HCCHAR7_CHENA (*((volatile unsigned int*)(0x4380BC7CUL))) +#define bM4_USBFS_HCINT7_XFRC (*((volatile unsigned int*)(0x4380BD00UL))) +#define bM4_USBFS_HCINT7_CHH (*((volatile unsigned int*)(0x4380BD04UL))) +#define bM4_USBFS_HCINT7_STALL (*((volatile unsigned int*)(0x4380BD0CUL))) +#define bM4_USBFS_HCINT7_NAK (*((volatile unsigned int*)(0x4380BD10UL))) +#define bM4_USBFS_HCINT7_ACK (*((volatile unsigned int*)(0x4380BD14UL))) +#define bM4_USBFS_HCINT7_TXERR (*((volatile unsigned int*)(0x4380BD1CUL))) +#define bM4_USBFS_HCINT7_BBERR (*((volatile unsigned int*)(0x4380BD20UL))) +#define bM4_USBFS_HCINT7_FRMOR (*((volatile unsigned int*)(0x4380BD24UL))) +#define bM4_USBFS_HCINT7_DTERR (*((volatile unsigned int*)(0x4380BD28UL))) +#define bM4_USBFS_HCINTMSK7_XFRCM (*((volatile unsigned int*)(0x4380BD80UL))) +#define bM4_USBFS_HCINTMSK7_CHHM (*((volatile unsigned int*)(0x4380BD84UL))) +#define bM4_USBFS_HCINTMSK7_STALLM (*((volatile unsigned int*)(0x4380BD8CUL))) +#define bM4_USBFS_HCINTMSK7_NAKM (*((volatile unsigned int*)(0x4380BD90UL))) +#define bM4_USBFS_HCINTMSK7_ACKM (*((volatile unsigned int*)(0x4380BD94UL))) +#define bM4_USBFS_HCINTMSK7_TXERRM (*((volatile unsigned int*)(0x4380BD9CUL))) +#define bM4_USBFS_HCINTMSK7_BBERRM (*((volatile unsigned int*)(0x4380BDA0UL))) +#define bM4_USBFS_HCINTMSK7_FRMORM (*((volatile unsigned int*)(0x4380BDA4UL))) +#define bM4_USBFS_HCINTMSK7_DTERRM (*((volatile unsigned int*)(0x4380BDA8UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ0 (*((volatile unsigned int*)(0x4380BE00UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ1 (*((volatile unsigned int*)(0x4380BE04UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ2 (*((volatile unsigned int*)(0x4380BE08UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ3 (*((volatile unsigned int*)(0x4380BE0CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ4 (*((volatile unsigned int*)(0x4380BE10UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ5 (*((volatile unsigned int*)(0x4380BE14UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ6 (*((volatile unsigned int*)(0x4380BE18UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ7 (*((volatile unsigned int*)(0x4380BE1CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ8 (*((volatile unsigned int*)(0x4380BE20UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ9 (*((volatile unsigned int*)(0x4380BE24UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ10 (*((volatile unsigned int*)(0x4380BE28UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ11 (*((volatile unsigned int*)(0x4380BE2CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ12 (*((volatile unsigned int*)(0x4380BE30UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ13 (*((volatile unsigned int*)(0x4380BE34UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ14 (*((volatile unsigned int*)(0x4380BE38UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ15 (*((volatile unsigned int*)(0x4380BE3CUL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ16 (*((volatile unsigned int*)(0x4380BE40UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ17 (*((volatile unsigned int*)(0x4380BE44UL))) +#define bM4_USBFS_HCTSIZ7_XFRSIZ18 (*((volatile unsigned int*)(0x4380BE48UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT0 (*((volatile unsigned int*)(0x4380BE4CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT1 (*((volatile unsigned int*)(0x4380BE50UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT2 (*((volatile unsigned int*)(0x4380BE54UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT3 (*((volatile unsigned int*)(0x4380BE58UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT4 (*((volatile unsigned int*)(0x4380BE5CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT5 (*((volatile unsigned int*)(0x4380BE60UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT6 (*((volatile unsigned int*)(0x4380BE64UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT7 (*((volatile unsigned int*)(0x4380BE68UL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT8 (*((volatile unsigned int*)(0x4380BE6CUL))) +#define bM4_USBFS_HCTSIZ7_PKTCNT9 (*((volatile unsigned int*)(0x4380BE70UL))) +#define bM4_USBFS_HCTSIZ7_DPID0 (*((volatile unsigned int*)(0x4380BE74UL))) +#define bM4_USBFS_HCTSIZ7_DPID1 (*((volatile unsigned int*)(0x4380BE78UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ0 (*((volatile unsigned int*)(0x4380C000UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ1 (*((volatile unsigned int*)(0x4380C004UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ2 (*((volatile unsigned int*)(0x4380C008UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ3 (*((volatile unsigned int*)(0x4380C00CUL))) +#define bM4_USBFS_HCCHAR8_MPSIZ4 (*((volatile unsigned int*)(0x4380C010UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ5 (*((volatile unsigned int*)(0x4380C014UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ6 (*((volatile unsigned int*)(0x4380C018UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ7 (*((volatile unsigned int*)(0x4380C01CUL))) +#define bM4_USBFS_HCCHAR8_MPSIZ8 (*((volatile unsigned int*)(0x4380C020UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ9 (*((volatile unsigned int*)(0x4380C024UL))) +#define bM4_USBFS_HCCHAR8_MPSIZ10 (*((volatile unsigned int*)(0x4380C028UL))) +#define bM4_USBFS_HCCHAR8_EPNUM0 (*((volatile unsigned int*)(0x4380C02CUL))) +#define bM4_USBFS_HCCHAR8_EPNUM1 (*((volatile unsigned int*)(0x4380C030UL))) +#define bM4_USBFS_HCCHAR8_EPNUM2 (*((volatile unsigned int*)(0x4380C034UL))) +#define bM4_USBFS_HCCHAR8_EPNUM3 (*((volatile unsigned int*)(0x4380C038UL))) +#define bM4_USBFS_HCCHAR8_EPDIR (*((volatile unsigned int*)(0x4380C03CUL))) +#define bM4_USBFS_HCCHAR8_LSDEV (*((volatile unsigned int*)(0x4380C044UL))) +#define bM4_USBFS_HCCHAR8_EPTYP0 (*((volatile unsigned int*)(0x4380C048UL))) +#define bM4_USBFS_HCCHAR8_EPTYP1 (*((volatile unsigned int*)(0x4380C04CUL))) +#define bM4_USBFS_HCCHAR8_DAD0 (*((volatile unsigned int*)(0x4380C058UL))) +#define bM4_USBFS_HCCHAR8_DAD1 (*((volatile unsigned int*)(0x4380C05CUL))) +#define bM4_USBFS_HCCHAR8_DAD2 (*((volatile unsigned int*)(0x4380C060UL))) +#define bM4_USBFS_HCCHAR8_DAD3 (*((volatile unsigned int*)(0x4380C064UL))) +#define bM4_USBFS_HCCHAR8_DAD4 (*((volatile unsigned int*)(0x4380C068UL))) +#define bM4_USBFS_HCCHAR8_DAD5 (*((volatile unsigned int*)(0x4380C06CUL))) +#define bM4_USBFS_HCCHAR8_DAD6 (*((volatile unsigned int*)(0x4380C070UL))) +#define bM4_USBFS_HCCHAR8_ODDFRM (*((volatile unsigned int*)(0x4380C074UL))) +#define bM4_USBFS_HCCHAR8_CHDIS (*((volatile unsigned int*)(0x4380C078UL))) +#define bM4_USBFS_HCCHAR8_CHENA (*((volatile unsigned int*)(0x4380C07CUL))) +#define bM4_USBFS_HCINT8_XFRC (*((volatile unsigned int*)(0x4380C100UL))) +#define bM4_USBFS_HCINT8_CHH (*((volatile unsigned int*)(0x4380C104UL))) +#define bM4_USBFS_HCINT8_STALL (*((volatile unsigned int*)(0x4380C10CUL))) +#define bM4_USBFS_HCINT8_NAK (*((volatile unsigned int*)(0x4380C110UL))) +#define bM4_USBFS_HCINT8_ACK (*((volatile unsigned int*)(0x4380C114UL))) +#define bM4_USBFS_HCINT8_TXERR (*((volatile unsigned int*)(0x4380C11CUL))) +#define bM4_USBFS_HCINT8_BBERR (*((volatile unsigned int*)(0x4380C120UL))) +#define bM4_USBFS_HCINT8_FRMOR (*((volatile unsigned int*)(0x4380C124UL))) +#define bM4_USBFS_HCINT8_DTERR (*((volatile unsigned int*)(0x4380C128UL))) +#define bM4_USBFS_HCINTMSK8_XFRCM (*((volatile unsigned int*)(0x4380C180UL))) +#define bM4_USBFS_HCINTMSK8_CHHM (*((volatile unsigned int*)(0x4380C184UL))) +#define bM4_USBFS_HCINTMSK8_STALLM (*((volatile unsigned int*)(0x4380C18CUL))) +#define bM4_USBFS_HCINTMSK8_NAKM (*((volatile unsigned int*)(0x4380C190UL))) +#define bM4_USBFS_HCINTMSK8_ACKM (*((volatile unsigned int*)(0x4380C194UL))) +#define bM4_USBFS_HCINTMSK8_TXERRM (*((volatile unsigned int*)(0x4380C19CUL))) +#define bM4_USBFS_HCINTMSK8_BBERRM (*((volatile unsigned int*)(0x4380C1A0UL))) +#define bM4_USBFS_HCINTMSK8_FRMORM (*((volatile unsigned int*)(0x4380C1A4UL))) +#define bM4_USBFS_HCINTMSK8_DTERRM (*((volatile unsigned int*)(0x4380C1A8UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ0 (*((volatile unsigned int*)(0x4380C200UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ1 (*((volatile unsigned int*)(0x4380C204UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ2 (*((volatile unsigned int*)(0x4380C208UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ3 (*((volatile unsigned int*)(0x4380C20CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ4 (*((volatile unsigned int*)(0x4380C210UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ5 (*((volatile unsigned int*)(0x4380C214UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ6 (*((volatile unsigned int*)(0x4380C218UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ7 (*((volatile unsigned int*)(0x4380C21CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ8 (*((volatile unsigned int*)(0x4380C220UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ9 (*((volatile unsigned int*)(0x4380C224UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ10 (*((volatile unsigned int*)(0x4380C228UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ11 (*((volatile unsigned int*)(0x4380C22CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ12 (*((volatile unsigned int*)(0x4380C230UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ13 (*((volatile unsigned int*)(0x4380C234UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ14 (*((volatile unsigned int*)(0x4380C238UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ15 (*((volatile unsigned int*)(0x4380C23CUL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ16 (*((volatile unsigned int*)(0x4380C240UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ17 (*((volatile unsigned int*)(0x4380C244UL))) +#define bM4_USBFS_HCTSIZ8_XFRSIZ18 (*((volatile unsigned int*)(0x4380C248UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT0 (*((volatile unsigned int*)(0x4380C24CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT1 (*((volatile unsigned int*)(0x4380C250UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT2 (*((volatile unsigned int*)(0x4380C254UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT3 (*((volatile unsigned int*)(0x4380C258UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT4 (*((volatile unsigned int*)(0x4380C25CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT5 (*((volatile unsigned int*)(0x4380C260UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT6 (*((volatile unsigned int*)(0x4380C264UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT7 (*((volatile unsigned int*)(0x4380C268UL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT8 (*((volatile unsigned int*)(0x4380C26CUL))) +#define bM4_USBFS_HCTSIZ8_PKTCNT9 (*((volatile unsigned int*)(0x4380C270UL))) +#define bM4_USBFS_HCTSIZ8_DPID0 (*((volatile unsigned int*)(0x4380C274UL))) +#define bM4_USBFS_HCTSIZ8_DPID1 (*((volatile unsigned int*)(0x4380C278UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ0 (*((volatile unsigned int*)(0x4380C400UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ1 (*((volatile unsigned int*)(0x4380C404UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ2 (*((volatile unsigned int*)(0x4380C408UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ3 (*((volatile unsigned int*)(0x4380C40CUL))) +#define bM4_USBFS_HCCHAR9_MPSIZ4 (*((volatile unsigned int*)(0x4380C410UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ5 (*((volatile unsigned int*)(0x4380C414UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ6 (*((volatile unsigned int*)(0x4380C418UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ7 (*((volatile unsigned int*)(0x4380C41CUL))) +#define bM4_USBFS_HCCHAR9_MPSIZ8 (*((volatile unsigned int*)(0x4380C420UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ9 (*((volatile unsigned int*)(0x4380C424UL))) +#define bM4_USBFS_HCCHAR9_MPSIZ10 (*((volatile unsigned int*)(0x4380C428UL))) +#define bM4_USBFS_HCCHAR9_EPNUM0 (*((volatile unsigned int*)(0x4380C42CUL))) +#define bM4_USBFS_HCCHAR9_EPNUM1 (*((volatile unsigned int*)(0x4380C430UL))) +#define bM4_USBFS_HCCHAR9_EPNUM2 (*((volatile unsigned int*)(0x4380C434UL))) +#define bM4_USBFS_HCCHAR9_EPNUM3 (*((volatile unsigned int*)(0x4380C438UL))) +#define bM4_USBFS_HCCHAR9_EPDIR (*((volatile unsigned int*)(0x4380C43CUL))) +#define bM4_USBFS_HCCHAR9_LSDEV (*((volatile unsigned int*)(0x4380C444UL))) +#define bM4_USBFS_HCCHAR9_EPTYP0 (*((volatile unsigned int*)(0x4380C448UL))) +#define bM4_USBFS_HCCHAR9_EPTYP1 (*((volatile unsigned int*)(0x4380C44CUL))) +#define bM4_USBFS_HCCHAR9_DAD0 (*((volatile unsigned int*)(0x4380C458UL))) +#define bM4_USBFS_HCCHAR9_DAD1 (*((volatile unsigned int*)(0x4380C45CUL))) +#define bM4_USBFS_HCCHAR9_DAD2 (*((volatile unsigned int*)(0x4380C460UL))) +#define bM4_USBFS_HCCHAR9_DAD3 (*((volatile unsigned int*)(0x4380C464UL))) +#define bM4_USBFS_HCCHAR9_DAD4 (*((volatile unsigned int*)(0x4380C468UL))) +#define bM4_USBFS_HCCHAR9_DAD5 (*((volatile unsigned int*)(0x4380C46CUL))) +#define bM4_USBFS_HCCHAR9_DAD6 (*((volatile unsigned int*)(0x4380C470UL))) +#define bM4_USBFS_HCCHAR9_ODDFRM (*((volatile unsigned int*)(0x4380C474UL))) +#define bM4_USBFS_HCCHAR9_CHDIS (*((volatile unsigned int*)(0x4380C478UL))) +#define bM4_USBFS_HCCHAR9_CHENA (*((volatile unsigned int*)(0x4380C47CUL))) +#define bM4_USBFS_HCINT9_XFRC (*((volatile unsigned int*)(0x4380C500UL))) +#define bM4_USBFS_HCINT9_CHH (*((volatile unsigned int*)(0x4380C504UL))) +#define bM4_USBFS_HCINT9_STALL (*((volatile unsigned int*)(0x4380C50CUL))) +#define bM4_USBFS_HCINT9_NAK (*((volatile unsigned int*)(0x4380C510UL))) +#define bM4_USBFS_HCINT9_ACK (*((volatile unsigned int*)(0x4380C514UL))) +#define bM4_USBFS_HCINT9_TXERR (*((volatile unsigned int*)(0x4380C51CUL))) +#define bM4_USBFS_HCINT9_BBERR (*((volatile unsigned int*)(0x4380C520UL))) +#define bM4_USBFS_HCINT9_FRMOR (*((volatile unsigned int*)(0x4380C524UL))) +#define bM4_USBFS_HCINT9_DTERR (*((volatile unsigned int*)(0x4380C528UL))) +#define bM4_USBFS_HCINTMSK9_XFRCM (*((volatile unsigned int*)(0x4380C580UL))) +#define bM4_USBFS_HCINTMSK9_CHHM (*((volatile unsigned int*)(0x4380C584UL))) +#define bM4_USBFS_HCINTMSK9_STALLM (*((volatile unsigned int*)(0x4380C58CUL))) +#define bM4_USBFS_HCINTMSK9_NAKM (*((volatile unsigned int*)(0x4380C590UL))) +#define bM4_USBFS_HCINTMSK9_ACKM (*((volatile unsigned int*)(0x4380C594UL))) +#define bM4_USBFS_HCINTMSK9_TXERRM (*((volatile unsigned int*)(0x4380C59CUL))) +#define bM4_USBFS_HCINTMSK9_BBERRM (*((volatile unsigned int*)(0x4380C5A0UL))) +#define bM4_USBFS_HCINTMSK9_FRMORM (*((volatile unsigned int*)(0x4380C5A4UL))) +#define bM4_USBFS_HCINTMSK9_DTERRM (*((volatile unsigned int*)(0x4380C5A8UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ0 (*((volatile unsigned int*)(0x4380C600UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ1 (*((volatile unsigned int*)(0x4380C604UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ2 (*((volatile unsigned int*)(0x4380C608UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ3 (*((volatile unsigned int*)(0x4380C60CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ4 (*((volatile unsigned int*)(0x4380C610UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ5 (*((volatile unsigned int*)(0x4380C614UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ6 (*((volatile unsigned int*)(0x4380C618UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ7 (*((volatile unsigned int*)(0x4380C61CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ8 (*((volatile unsigned int*)(0x4380C620UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ9 (*((volatile unsigned int*)(0x4380C624UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ10 (*((volatile unsigned int*)(0x4380C628UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ11 (*((volatile unsigned int*)(0x4380C62CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ12 (*((volatile unsigned int*)(0x4380C630UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ13 (*((volatile unsigned int*)(0x4380C634UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ14 (*((volatile unsigned int*)(0x4380C638UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ15 (*((volatile unsigned int*)(0x4380C63CUL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ16 (*((volatile unsigned int*)(0x4380C640UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ17 (*((volatile unsigned int*)(0x4380C644UL))) +#define bM4_USBFS_HCTSIZ9_XFRSIZ18 (*((volatile unsigned int*)(0x4380C648UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT0 (*((volatile unsigned int*)(0x4380C64CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT1 (*((volatile unsigned int*)(0x4380C650UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT2 (*((volatile unsigned int*)(0x4380C654UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT3 (*((volatile unsigned int*)(0x4380C658UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT4 (*((volatile unsigned int*)(0x4380C65CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT5 (*((volatile unsigned int*)(0x4380C660UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT6 (*((volatile unsigned int*)(0x4380C664UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT7 (*((volatile unsigned int*)(0x4380C668UL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT8 (*((volatile unsigned int*)(0x4380C66CUL))) +#define bM4_USBFS_HCTSIZ9_PKTCNT9 (*((volatile unsigned int*)(0x4380C670UL))) +#define bM4_USBFS_HCTSIZ9_DPID0 (*((volatile unsigned int*)(0x4380C674UL))) +#define bM4_USBFS_HCTSIZ9_DPID1 (*((volatile unsigned int*)(0x4380C678UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ0 (*((volatile unsigned int*)(0x4380C800UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ1 (*((volatile unsigned int*)(0x4380C804UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ2 (*((volatile unsigned int*)(0x4380C808UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ3 (*((volatile unsigned int*)(0x4380C80CUL))) +#define bM4_USBFS_HCCHAR10_MPSIZ4 (*((volatile unsigned int*)(0x4380C810UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ5 (*((volatile unsigned int*)(0x4380C814UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ6 (*((volatile unsigned int*)(0x4380C818UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ7 (*((volatile unsigned int*)(0x4380C81CUL))) +#define bM4_USBFS_HCCHAR10_MPSIZ8 (*((volatile unsigned int*)(0x4380C820UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ9 (*((volatile unsigned int*)(0x4380C824UL))) +#define bM4_USBFS_HCCHAR10_MPSIZ10 (*((volatile unsigned int*)(0x4380C828UL))) +#define bM4_USBFS_HCCHAR10_EPNUM0 (*((volatile unsigned int*)(0x4380C82CUL))) +#define bM4_USBFS_HCCHAR10_EPNUM1 (*((volatile unsigned int*)(0x4380C830UL))) +#define bM4_USBFS_HCCHAR10_EPNUM2 (*((volatile unsigned int*)(0x4380C834UL))) +#define bM4_USBFS_HCCHAR10_EPNUM3 (*((volatile unsigned int*)(0x4380C838UL))) +#define bM4_USBFS_HCCHAR10_EPDIR (*((volatile unsigned int*)(0x4380C83CUL))) +#define bM4_USBFS_HCCHAR10_LSDEV (*((volatile unsigned int*)(0x4380C844UL))) +#define bM4_USBFS_HCCHAR10_EPTYP0 (*((volatile unsigned int*)(0x4380C848UL))) +#define bM4_USBFS_HCCHAR10_EPTYP1 (*((volatile unsigned int*)(0x4380C84CUL))) +#define bM4_USBFS_HCCHAR10_DAD0 (*((volatile unsigned int*)(0x4380C858UL))) +#define bM4_USBFS_HCCHAR10_DAD1 (*((volatile unsigned int*)(0x4380C85CUL))) +#define bM4_USBFS_HCCHAR10_DAD2 (*((volatile unsigned int*)(0x4380C860UL))) +#define bM4_USBFS_HCCHAR10_DAD3 (*((volatile unsigned int*)(0x4380C864UL))) +#define bM4_USBFS_HCCHAR10_DAD4 (*((volatile unsigned int*)(0x4380C868UL))) +#define bM4_USBFS_HCCHAR10_DAD5 (*((volatile unsigned int*)(0x4380C86CUL))) +#define bM4_USBFS_HCCHAR10_DAD6 (*((volatile unsigned int*)(0x4380C870UL))) +#define bM4_USBFS_HCCHAR10_ODDFRM (*((volatile unsigned int*)(0x4380C874UL))) +#define bM4_USBFS_HCCHAR10_CHDIS (*((volatile unsigned int*)(0x4380C878UL))) +#define bM4_USBFS_HCCHAR10_CHENA (*((volatile unsigned int*)(0x4380C87CUL))) +#define bM4_USBFS_HCINT10_XFRC (*((volatile unsigned int*)(0x4380C900UL))) +#define bM4_USBFS_HCINT10_CHH (*((volatile unsigned int*)(0x4380C904UL))) +#define bM4_USBFS_HCINT10_STALL (*((volatile unsigned int*)(0x4380C90CUL))) +#define bM4_USBFS_HCINT10_NAK (*((volatile unsigned int*)(0x4380C910UL))) +#define bM4_USBFS_HCINT10_ACK (*((volatile unsigned int*)(0x4380C914UL))) +#define bM4_USBFS_HCINT10_TXERR (*((volatile unsigned int*)(0x4380C91CUL))) +#define bM4_USBFS_HCINT10_BBERR (*((volatile unsigned int*)(0x4380C920UL))) +#define bM4_USBFS_HCINT10_FRMOR (*((volatile unsigned int*)(0x4380C924UL))) +#define bM4_USBFS_HCINT10_DTERR (*((volatile unsigned int*)(0x4380C928UL))) +#define bM4_USBFS_HCINTMSK10_XFRCM (*((volatile unsigned int*)(0x4380C980UL))) +#define bM4_USBFS_HCINTMSK10_CHHM (*((volatile unsigned int*)(0x4380C984UL))) +#define bM4_USBFS_HCINTMSK10_STALLM (*((volatile unsigned int*)(0x4380C98CUL))) +#define bM4_USBFS_HCINTMSK10_NAKM (*((volatile unsigned int*)(0x4380C990UL))) +#define bM4_USBFS_HCINTMSK10_ACKM (*((volatile unsigned int*)(0x4380C994UL))) +#define bM4_USBFS_HCINTMSK10_TXERRM (*((volatile unsigned int*)(0x4380C99CUL))) +#define bM4_USBFS_HCINTMSK10_BBERRM (*((volatile unsigned int*)(0x4380C9A0UL))) +#define bM4_USBFS_HCINTMSK10_FRMORM (*((volatile unsigned int*)(0x4380C9A4UL))) +#define bM4_USBFS_HCINTMSK10_DTERRM (*((volatile unsigned int*)(0x4380C9A8UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ0 (*((volatile unsigned int*)(0x4380CA00UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ1 (*((volatile unsigned int*)(0x4380CA04UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ2 (*((volatile unsigned int*)(0x4380CA08UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ3 (*((volatile unsigned int*)(0x4380CA0CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ4 (*((volatile unsigned int*)(0x4380CA10UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ5 (*((volatile unsigned int*)(0x4380CA14UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ6 (*((volatile unsigned int*)(0x4380CA18UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ7 (*((volatile unsigned int*)(0x4380CA1CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ8 (*((volatile unsigned int*)(0x4380CA20UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ9 (*((volatile unsigned int*)(0x4380CA24UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ10 (*((volatile unsigned int*)(0x4380CA28UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ11 (*((volatile unsigned int*)(0x4380CA2CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ12 (*((volatile unsigned int*)(0x4380CA30UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ13 (*((volatile unsigned int*)(0x4380CA34UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ14 (*((volatile unsigned int*)(0x4380CA38UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ15 (*((volatile unsigned int*)(0x4380CA3CUL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ16 (*((volatile unsigned int*)(0x4380CA40UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ17 (*((volatile unsigned int*)(0x4380CA44UL))) +#define bM4_USBFS_HCTSIZ10_XFRSIZ18 (*((volatile unsigned int*)(0x4380CA48UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT0 (*((volatile unsigned int*)(0x4380CA4CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT1 (*((volatile unsigned int*)(0x4380CA50UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT2 (*((volatile unsigned int*)(0x4380CA54UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT3 (*((volatile unsigned int*)(0x4380CA58UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT4 (*((volatile unsigned int*)(0x4380CA5CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT5 (*((volatile unsigned int*)(0x4380CA60UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT6 (*((volatile unsigned int*)(0x4380CA64UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT7 (*((volatile unsigned int*)(0x4380CA68UL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT8 (*((volatile unsigned int*)(0x4380CA6CUL))) +#define bM4_USBFS_HCTSIZ10_PKTCNT9 (*((volatile unsigned int*)(0x4380CA70UL))) +#define bM4_USBFS_HCTSIZ10_DPID0 (*((volatile unsigned int*)(0x4380CA74UL))) +#define bM4_USBFS_HCTSIZ10_DPID1 (*((volatile unsigned int*)(0x4380CA78UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ0 (*((volatile unsigned int*)(0x4380CC00UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ1 (*((volatile unsigned int*)(0x4380CC04UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ2 (*((volatile unsigned int*)(0x4380CC08UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ3 (*((volatile unsigned int*)(0x4380CC0CUL))) +#define bM4_USBFS_HCCHAR11_MPSIZ4 (*((volatile unsigned int*)(0x4380CC10UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ5 (*((volatile unsigned int*)(0x4380CC14UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ6 (*((volatile unsigned int*)(0x4380CC18UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ7 (*((volatile unsigned int*)(0x4380CC1CUL))) +#define bM4_USBFS_HCCHAR11_MPSIZ8 (*((volatile unsigned int*)(0x4380CC20UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ9 (*((volatile unsigned int*)(0x4380CC24UL))) +#define bM4_USBFS_HCCHAR11_MPSIZ10 (*((volatile unsigned int*)(0x4380CC28UL))) +#define bM4_USBFS_HCCHAR11_EPNUM0 (*((volatile unsigned int*)(0x4380CC2CUL))) +#define bM4_USBFS_HCCHAR11_EPNUM1 (*((volatile unsigned int*)(0x4380CC30UL))) +#define bM4_USBFS_HCCHAR11_EPNUM2 (*((volatile unsigned int*)(0x4380CC34UL))) +#define bM4_USBFS_HCCHAR11_EPNUM3 (*((volatile unsigned int*)(0x4380CC38UL))) +#define bM4_USBFS_HCCHAR11_EPDIR (*((volatile unsigned int*)(0x4380CC3CUL))) +#define bM4_USBFS_HCCHAR11_LSDEV (*((volatile unsigned int*)(0x4380CC44UL))) +#define bM4_USBFS_HCCHAR11_EPTYP0 (*((volatile unsigned int*)(0x4380CC48UL))) +#define bM4_USBFS_HCCHAR11_EPTYP1 (*((volatile unsigned int*)(0x4380CC4CUL))) +#define bM4_USBFS_HCCHAR11_DAD0 (*((volatile unsigned int*)(0x4380CC58UL))) +#define bM4_USBFS_HCCHAR11_DAD1 (*((volatile unsigned int*)(0x4380CC5CUL))) +#define bM4_USBFS_HCCHAR11_DAD2 (*((volatile unsigned int*)(0x4380CC60UL))) +#define bM4_USBFS_HCCHAR11_DAD3 (*((volatile unsigned int*)(0x4380CC64UL))) +#define bM4_USBFS_HCCHAR11_DAD4 (*((volatile unsigned int*)(0x4380CC68UL))) +#define bM4_USBFS_HCCHAR11_DAD5 (*((volatile unsigned int*)(0x4380CC6CUL))) +#define bM4_USBFS_HCCHAR11_DAD6 (*((volatile unsigned int*)(0x4380CC70UL))) +#define bM4_USBFS_HCCHAR11_ODDFRM (*((volatile unsigned int*)(0x4380CC74UL))) +#define bM4_USBFS_HCCHAR11_CHDIS (*((volatile unsigned int*)(0x4380CC78UL))) +#define bM4_USBFS_HCCHAR11_CHENA (*((volatile unsigned int*)(0x4380CC7CUL))) +#define bM4_USBFS_HCINT11_XFRC (*((volatile unsigned int*)(0x4380CD00UL))) +#define bM4_USBFS_HCINT11_CHH (*((volatile unsigned int*)(0x4380CD04UL))) +#define bM4_USBFS_HCINT11_STALL (*((volatile unsigned int*)(0x4380CD0CUL))) +#define bM4_USBFS_HCINT11_NAK (*((volatile unsigned int*)(0x4380CD10UL))) +#define bM4_USBFS_HCINT11_ACK (*((volatile unsigned int*)(0x4380CD14UL))) +#define bM4_USBFS_HCINT11_TXERR (*((volatile unsigned int*)(0x4380CD1CUL))) +#define bM4_USBFS_HCINT11_BBERR (*((volatile unsigned int*)(0x4380CD20UL))) +#define bM4_USBFS_HCINT11_FRMOR (*((volatile unsigned int*)(0x4380CD24UL))) +#define bM4_USBFS_HCINT11_DTERR (*((volatile unsigned int*)(0x4380CD28UL))) +#define bM4_USBFS_HCINTMSK11_XFRCM (*((volatile unsigned int*)(0x4380CD80UL))) +#define bM4_USBFS_HCINTMSK11_CHHM (*((volatile unsigned int*)(0x4380CD84UL))) +#define bM4_USBFS_HCINTMSK11_STALLM (*((volatile unsigned int*)(0x4380CD8CUL))) +#define bM4_USBFS_HCINTMSK11_NAKM (*((volatile unsigned int*)(0x4380CD90UL))) +#define bM4_USBFS_HCINTMSK11_ACKM (*((volatile unsigned int*)(0x4380CD94UL))) +#define bM4_USBFS_HCINTMSK11_TXERRM (*((volatile unsigned int*)(0x4380CD9CUL))) +#define bM4_USBFS_HCINTMSK11_BBERRM (*((volatile unsigned int*)(0x4380CDA0UL))) +#define bM4_USBFS_HCINTMSK11_FRMORM (*((volatile unsigned int*)(0x4380CDA4UL))) +#define bM4_USBFS_HCINTMSK11_DTERRM (*((volatile unsigned int*)(0x4380CDA8UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ0 (*((volatile unsigned int*)(0x4380CE00UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ1 (*((volatile unsigned int*)(0x4380CE04UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ2 (*((volatile unsigned int*)(0x4380CE08UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ3 (*((volatile unsigned int*)(0x4380CE0CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ4 (*((volatile unsigned int*)(0x4380CE10UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ5 (*((volatile unsigned int*)(0x4380CE14UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ6 (*((volatile unsigned int*)(0x4380CE18UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ7 (*((volatile unsigned int*)(0x4380CE1CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ8 (*((volatile unsigned int*)(0x4380CE20UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ9 (*((volatile unsigned int*)(0x4380CE24UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ10 (*((volatile unsigned int*)(0x4380CE28UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ11 (*((volatile unsigned int*)(0x4380CE2CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ12 (*((volatile unsigned int*)(0x4380CE30UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ13 (*((volatile unsigned int*)(0x4380CE34UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ14 (*((volatile unsigned int*)(0x4380CE38UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ15 (*((volatile unsigned int*)(0x4380CE3CUL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ16 (*((volatile unsigned int*)(0x4380CE40UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ17 (*((volatile unsigned int*)(0x4380CE44UL))) +#define bM4_USBFS_HCTSIZ11_XFRSIZ18 (*((volatile unsigned int*)(0x4380CE48UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT0 (*((volatile unsigned int*)(0x4380CE4CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT1 (*((volatile unsigned int*)(0x4380CE50UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT2 (*((volatile unsigned int*)(0x4380CE54UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT3 (*((volatile unsigned int*)(0x4380CE58UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT4 (*((volatile unsigned int*)(0x4380CE5CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT5 (*((volatile unsigned int*)(0x4380CE60UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT6 (*((volatile unsigned int*)(0x4380CE64UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT7 (*((volatile unsigned int*)(0x4380CE68UL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT8 (*((volatile unsigned int*)(0x4380CE6CUL))) +#define bM4_USBFS_HCTSIZ11_PKTCNT9 (*((volatile unsigned int*)(0x4380CE70UL))) +#define bM4_USBFS_HCTSIZ11_DPID0 (*((volatile unsigned int*)(0x4380CE74UL))) +#define bM4_USBFS_HCTSIZ11_DPID1 (*((volatile unsigned int*)(0x4380CE78UL))) +#define bM4_USBFS_DCFG_DSPD0 (*((volatile unsigned int*)(0x43810000UL))) +#define bM4_USBFS_DCFG_DSPD1 (*((volatile unsigned int*)(0x43810004UL))) +#define bM4_USBFS_DCFG_NZLSOHSK (*((volatile unsigned int*)(0x43810008UL))) +#define bM4_USBFS_DCFG_DAD0 (*((volatile unsigned int*)(0x43810010UL))) +#define bM4_USBFS_DCFG_DAD1 (*((volatile unsigned int*)(0x43810014UL))) +#define bM4_USBFS_DCFG_DAD2 (*((volatile unsigned int*)(0x43810018UL))) +#define bM4_USBFS_DCFG_DAD3 (*((volatile unsigned int*)(0x4381001CUL))) +#define bM4_USBFS_DCFG_DAD4 (*((volatile unsigned int*)(0x43810020UL))) +#define bM4_USBFS_DCFG_DAD5 (*((volatile unsigned int*)(0x43810024UL))) +#define bM4_USBFS_DCFG_DAD6 (*((volatile unsigned int*)(0x43810028UL))) +#define bM4_USBFS_DCFG_PFIVL0 (*((volatile unsigned int*)(0x4381002CUL))) +#define bM4_USBFS_DCFG_PFIVL1 (*((volatile unsigned int*)(0x43810030UL))) +#define bM4_USBFS_DCTL_RWUSIG (*((volatile unsigned int*)(0x43810080UL))) +#define bM4_USBFS_DCTL_SDIS (*((volatile unsigned int*)(0x43810084UL))) +#define bM4_USBFS_DCTL_GINSTS (*((volatile unsigned int*)(0x43810088UL))) +#define bM4_USBFS_DCTL_GONSTS (*((volatile unsigned int*)(0x4381008CUL))) +#define bM4_USBFS_DCTL_SGINAK (*((volatile unsigned int*)(0x4381009CUL))) +#define bM4_USBFS_DCTL_CGINAK (*((volatile unsigned int*)(0x438100A0UL))) +#define bM4_USBFS_DCTL_SGONAK (*((volatile unsigned int*)(0x438100A4UL))) +#define bM4_USBFS_DCTL_CGONAK (*((volatile unsigned int*)(0x438100A8UL))) +#define bM4_USBFS_DCTL_POPRGDNE (*((volatile unsigned int*)(0x438100ACUL))) +#define bM4_USBFS_DSTS_SUSPSTS (*((volatile unsigned int*)(0x43810100UL))) +#define bM4_USBFS_DSTS_ENUMSPD0 (*((volatile unsigned int*)(0x43810104UL))) +#define bM4_USBFS_DSTS_ENUMSPD1 (*((volatile unsigned int*)(0x43810108UL))) +#define bM4_USBFS_DSTS_EERR (*((volatile unsigned int*)(0x4381010CUL))) +#define bM4_USBFS_DSTS_FNSOF0 (*((volatile unsigned int*)(0x43810120UL))) +#define bM4_USBFS_DSTS_FNSOF1 (*((volatile unsigned int*)(0x43810124UL))) +#define bM4_USBFS_DSTS_FNSOF2 (*((volatile unsigned int*)(0x43810128UL))) +#define bM4_USBFS_DSTS_FNSOF3 (*((volatile unsigned int*)(0x4381012CUL))) +#define bM4_USBFS_DSTS_FNSOF4 (*((volatile unsigned int*)(0x43810130UL))) +#define bM4_USBFS_DSTS_FNSOF5 (*((volatile unsigned int*)(0x43810134UL))) +#define bM4_USBFS_DSTS_FNSOF6 (*((volatile unsigned int*)(0x43810138UL))) +#define bM4_USBFS_DSTS_FNSOF7 (*((volatile unsigned int*)(0x4381013CUL))) +#define bM4_USBFS_DSTS_FNSOF8 (*((volatile unsigned int*)(0x43810140UL))) +#define bM4_USBFS_DSTS_FNSOF9 (*((volatile unsigned int*)(0x43810144UL))) +#define bM4_USBFS_DSTS_FNSOF10 (*((volatile unsigned int*)(0x43810148UL))) +#define bM4_USBFS_DSTS_FNSOF11 (*((volatile unsigned int*)(0x4381014CUL))) +#define bM4_USBFS_DSTS_FNSOF12 (*((volatile unsigned int*)(0x43810150UL))) +#define bM4_USBFS_DSTS_FNSOF13 (*((volatile unsigned int*)(0x43810154UL))) +#define bM4_USBFS_DIEPMSK_XFRCM (*((volatile unsigned int*)(0x43810200UL))) +#define bM4_USBFS_DIEPMSK_EPDM (*((volatile unsigned int*)(0x43810204UL))) +#define bM4_USBFS_DIEPMSK_TOM (*((volatile unsigned int*)(0x4381020CUL))) +#define bM4_USBFS_DIEPMSK_ITTXFEMSK (*((volatile unsigned int*)(0x43810210UL))) +#define bM4_USBFS_DIEPMSK_INEPNMM (*((volatile unsigned int*)(0x43810214UL))) +#define bM4_USBFS_DIEPMSK_INEPNEM (*((volatile unsigned int*)(0x43810218UL))) +#define bM4_USBFS_DOEPMSK_XFRCM (*((volatile unsigned int*)(0x43810280UL))) +#define bM4_USBFS_DOEPMSK_EPDM (*((volatile unsigned int*)(0x43810284UL))) +#define bM4_USBFS_DOEPMSK_STUPM (*((volatile unsigned int*)(0x4381028CUL))) +#define bM4_USBFS_DOEPMSK_OTEPDM (*((volatile unsigned int*)(0x43810290UL))) +#define bM4_USBFS_DAINT_IEPINT0 (*((volatile unsigned int*)(0x43810300UL))) +#define bM4_USBFS_DAINT_IEPINT1 (*((volatile unsigned int*)(0x43810304UL))) +#define bM4_USBFS_DAINT_IEPINT2 (*((volatile unsigned int*)(0x43810308UL))) +#define bM4_USBFS_DAINT_IEPINT3 (*((volatile unsigned int*)(0x4381030CUL))) +#define bM4_USBFS_DAINT_IEPINT4 (*((volatile unsigned int*)(0x43810310UL))) +#define bM4_USBFS_DAINT_IEPINT5 (*((volatile unsigned int*)(0x43810314UL))) +#define bM4_USBFS_DAINT_OEPINT0 (*((volatile unsigned int*)(0x43810340UL))) +#define bM4_USBFS_DAINT_OEPINT1 (*((volatile unsigned int*)(0x43810344UL))) +#define bM4_USBFS_DAINT_OEPINT2 (*((volatile unsigned int*)(0x43810348UL))) +#define bM4_USBFS_DAINT_OEPINT3 (*((volatile unsigned int*)(0x4381034CUL))) +#define bM4_USBFS_DAINT_OEPINT4 (*((volatile unsigned int*)(0x43810350UL))) +#define bM4_USBFS_DAINT_OEPINT5 (*((volatile unsigned int*)(0x43810354UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM0 (*((volatile unsigned int*)(0x43810380UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM1 (*((volatile unsigned int*)(0x43810384UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM2 (*((volatile unsigned int*)(0x43810388UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM3 (*((volatile unsigned int*)(0x4381038CUL))) +#define bM4_USBFS_DAINTMSK_IEPINTM4 (*((volatile unsigned int*)(0x43810390UL))) +#define bM4_USBFS_DAINTMSK_IEPINTM5 (*((volatile unsigned int*)(0x43810394UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM0 (*((volatile unsigned int*)(0x438103C0UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM1 (*((volatile unsigned int*)(0x438103C4UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM2 (*((volatile unsigned int*)(0x438103C8UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM3 (*((volatile unsigned int*)(0x438103CCUL))) +#define bM4_USBFS_DAINTMSK_OEPINTM4 (*((volatile unsigned int*)(0x438103D0UL))) +#define bM4_USBFS_DAINTMSK_OEPINTM5 (*((volatile unsigned int*)(0x438103D4UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM0 (*((volatile unsigned int*)(0x43810680UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM1 (*((volatile unsigned int*)(0x43810684UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM2 (*((volatile unsigned int*)(0x43810688UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM3 (*((volatile unsigned int*)(0x4381068CUL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM4 (*((volatile unsigned int*)(0x43810690UL))) +#define bM4_USBFS_DIEPEMPMSK_INEPTXFEM5 (*((volatile unsigned int*)(0x43810694UL))) +#define bM4_USBFS_DIEPCTL0_MPSIZ0 (*((volatile unsigned int*)(0x43812000UL))) +#define bM4_USBFS_DIEPCTL0_MPSIZ1 (*((volatile unsigned int*)(0x43812004UL))) +#define bM4_USBFS_DIEPCTL0_USBAEP (*((volatile unsigned int*)(0x4381203CUL))) +#define bM4_USBFS_DIEPCTL0_NAKSTS (*((volatile unsigned int*)(0x43812044UL))) +#define bM4_USBFS_DIEPCTL0_EPTYP0 (*((volatile unsigned int*)(0x43812048UL))) +#define bM4_USBFS_DIEPCTL0_EPTYP1 (*((volatile unsigned int*)(0x4381204CUL))) +#define bM4_USBFS_DIEPCTL0_STALL (*((volatile unsigned int*)(0x43812054UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM0 (*((volatile unsigned int*)(0x43812058UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM1 (*((volatile unsigned int*)(0x4381205CUL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM2 (*((volatile unsigned int*)(0x43812060UL))) +#define bM4_USBFS_DIEPCTL0_TXFNUM3 (*((volatile unsigned int*)(0x43812064UL))) +#define bM4_USBFS_DIEPCTL0_CNAK (*((volatile unsigned int*)(0x43812068UL))) +#define bM4_USBFS_DIEPCTL0_SNAK (*((volatile unsigned int*)(0x4381206CUL))) +#define bM4_USBFS_DIEPCTL0_EPDIS (*((volatile unsigned int*)(0x43812078UL))) +#define bM4_USBFS_DIEPCTL0_EPENA (*((volatile unsigned int*)(0x4381207CUL))) +#define bM4_USBFS_DIEPINT0_XFRC (*((volatile unsigned int*)(0x43812100UL))) +#define bM4_USBFS_DIEPINT0_EPDISD (*((volatile unsigned int*)(0x43812104UL))) +#define bM4_USBFS_DIEPINT0_TOC (*((volatile unsigned int*)(0x4381210CUL))) +#define bM4_USBFS_DIEPINT0_TTXFE (*((volatile unsigned int*)(0x43812110UL))) +#define bM4_USBFS_DIEPINT0_INEPNE (*((volatile unsigned int*)(0x43812118UL))) +#define bM4_USBFS_DIEPINT0_TXFE (*((volatile unsigned int*)(0x4381211CUL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x43812200UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x43812204UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x43812208UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4381220CUL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x43812210UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x43812214UL))) +#define bM4_USBFS_DIEPTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x43812218UL))) +#define bM4_USBFS_DIEPTSIZ0_PKTCNT0 (*((volatile unsigned int*)(0x4381224CUL))) +#define bM4_USBFS_DIEPTSIZ0_PKTCNT1 (*((volatile unsigned int*)(0x43812250UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV0 (*((volatile unsigned int*)(0x43812300UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV1 (*((volatile unsigned int*)(0x43812304UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV2 (*((volatile unsigned int*)(0x43812308UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV3 (*((volatile unsigned int*)(0x4381230CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV4 (*((volatile unsigned int*)(0x43812310UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV5 (*((volatile unsigned int*)(0x43812314UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV6 (*((volatile unsigned int*)(0x43812318UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV7 (*((volatile unsigned int*)(0x4381231CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV8 (*((volatile unsigned int*)(0x43812320UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV9 (*((volatile unsigned int*)(0x43812324UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV10 (*((volatile unsigned int*)(0x43812328UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV11 (*((volatile unsigned int*)(0x4381232CUL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV12 (*((volatile unsigned int*)(0x43812330UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV13 (*((volatile unsigned int*)(0x43812334UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV14 (*((volatile unsigned int*)(0x43812338UL))) +#define bM4_USBFS_DTXFSTS0_INEPTFSAV15 (*((volatile unsigned int*)(0x4381233CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ0 (*((volatile unsigned int*)(0x43812400UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ1 (*((volatile unsigned int*)(0x43812404UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ2 (*((volatile unsigned int*)(0x43812408UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ3 (*((volatile unsigned int*)(0x4381240CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ4 (*((volatile unsigned int*)(0x43812410UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ5 (*((volatile unsigned int*)(0x43812414UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ6 (*((volatile unsigned int*)(0x43812418UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ7 (*((volatile unsigned int*)(0x4381241CUL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ8 (*((volatile unsigned int*)(0x43812420UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ9 (*((volatile unsigned int*)(0x43812424UL))) +#define bM4_USBFS_DIEPCTL1_MPSIZ10 (*((volatile unsigned int*)(0x43812428UL))) +#define bM4_USBFS_DIEPCTL1_USBAEP (*((volatile unsigned int*)(0x4381243CUL))) +#define bM4_USBFS_DIEPCTL1_EONUM_DPID (*((volatile unsigned int*)(0x43812440UL))) +#define bM4_USBFS_DIEPCTL1_NAKSTS (*((volatile unsigned int*)(0x43812444UL))) +#define bM4_USBFS_DIEPCTL1_EPTYP0 (*((volatile unsigned int*)(0x43812448UL))) +#define bM4_USBFS_DIEPCTL1_EPTYP1 (*((volatile unsigned int*)(0x4381244CUL))) +#define bM4_USBFS_DIEPCTL1_STALL (*((volatile unsigned int*)(0x43812454UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM0 (*((volatile unsigned int*)(0x43812458UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM1 (*((volatile unsigned int*)(0x4381245CUL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM2 (*((volatile unsigned int*)(0x43812460UL))) +#define bM4_USBFS_DIEPCTL1_TXFNUM3 (*((volatile unsigned int*)(0x43812464UL))) +#define bM4_USBFS_DIEPCTL1_CNAK (*((volatile unsigned int*)(0x43812468UL))) +#define bM4_USBFS_DIEPCTL1_SNAK (*((volatile unsigned int*)(0x4381246CUL))) +#define bM4_USBFS_DIEPCTL1_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812470UL))) +#define bM4_USBFS_DIEPCTL1_SODDFRM (*((volatile unsigned int*)(0x43812474UL))) +#define bM4_USBFS_DIEPCTL1_EPDIS (*((volatile unsigned int*)(0x43812478UL))) +#define bM4_USBFS_DIEPCTL1_EPENA (*((volatile unsigned int*)(0x4381247CUL))) +#define bM4_USBFS_DIEPINT1_XFRC (*((volatile unsigned int*)(0x43812500UL))) +#define bM4_USBFS_DIEPINT1_EPDISD (*((volatile unsigned int*)(0x43812504UL))) +#define bM4_USBFS_DIEPINT1_TOC (*((volatile unsigned int*)(0x4381250CUL))) +#define bM4_USBFS_DIEPINT1_TTXFE (*((volatile unsigned int*)(0x43812510UL))) +#define bM4_USBFS_DIEPINT1_INEPNE (*((volatile unsigned int*)(0x43812518UL))) +#define bM4_USBFS_DIEPINT1_TXFE (*((volatile unsigned int*)(0x4381251CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x43812600UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x43812604UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x43812608UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4381260CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x43812610UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x43812614UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x43812618UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4381261CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x43812620UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x43812624UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x43812628UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4381262CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x43812630UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x43812634UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x43812638UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4381263CUL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x43812640UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x43812644UL))) +#define bM4_USBFS_DIEPTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x43812648UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4381264CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x43812650UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x43812654UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x43812658UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4381265CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x43812660UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x43812664UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x43812668UL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4381266CUL))) +#define bM4_USBFS_DIEPTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x43812670UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV0 (*((volatile unsigned int*)(0x43812700UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV1 (*((volatile unsigned int*)(0x43812704UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV2 (*((volatile unsigned int*)(0x43812708UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV3 (*((volatile unsigned int*)(0x4381270CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV4 (*((volatile unsigned int*)(0x43812710UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV5 (*((volatile unsigned int*)(0x43812714UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV6 (*((volatile unsigned int*)(0x43812718UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV7 (*((volatile unsigned int*)(0x4381271CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV8 (*((volatile unsigned int*)(0x43812720UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV9 (*((volatile unsigned int*)(0x43812724UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV10 (*((volatile unsigned int*)(0x43812728UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV11 (*((volatile unsigned int*)(0x4381272CUL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV12 (*((volatile unsigned int*)(0x43812730UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV13 (*((volatile unsigned int*)(0x43812734UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV14 (*((volatile unsigned int*)(0x43812738UL))) +#define bM4_USBFS_DTXFSTS1_INEPTFSAV15 (*((volatile unsigned int*)(0x4381273CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ0 (*((volatile unsigned int*)(0x43812800UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ1 (*((volatile unsigned int*)(0x43812804UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ2 (*((volatile unsigned int*)(0x43812808UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ3 (*((volatile unsigned int*)(0x4381280CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ4 (*((volatile unsigned int*)(0x43812810UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ5 (*((volatile unsigned int*)(0x43812814UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ6 (*((volatile unsigned int*)(0x43812818UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ7 (*((volatile unsigned int*)(0x4381281CUL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ8 (*((volatile unsigned int*)(0x43812820UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ9 (*((volatile unsigned int*)(0x43812824UL))) +#define bM4_USBFS_DIEPCTL2_MPSIZ10 (*((volatile unsigned int*)(0x43812828UL))) +#define bM4_USBFS_DIEPCTL2_USBAEP (*((volatile unsigned int*)(0x4381283CUL))) +#define bM4_USBFS_DIEPCTL2_EONUM_DPID (*((volatile unsigned int*)(0x43812840UL))) +#define bM4_USBFS_DIEPCTL2_NAKSTS (*((volatile unsigned int*)(0x43812844UL))) +#define bM4_USBFS_DIEPCTL2_EPTYP0 (*((volatile unsigned int*)(0x43812848UL))) +#define bM4_USBFS_DIEPCTL2_EPTYP1 (*((volatile unsigned int*)(0x4381284CUL))) +#define bM4_USBFS_DIEPCTL2_STALL (*((volatile unsigned int*)(0x43812854UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM0 (*((volatile unsigned int*)(0x43812858UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM1 (*((volatile unsigned int*)(0x4381285CUL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM2 (*((volatile unsigned int*)(0x43812860UL))) +#define bM4_USBFS_DIEPCTL2_TXFNUM3 (*((volatile unsigned int*)(0x43812864UL))) +#define bM4_USBFS_DIEPCTL2_CNAK (*((volatile unsigned int*)(0x43812868UL))) +#define bM4_USBFS_DIEPCTL2_SNAK (*((volatile unsigned int*)(0x4381286CUL))) +#define bM4_USBFS_DIEPCTL2_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812870UL))) +#define bM4_USBFS_DIEPCTL2_SODDFRM (*((volatile unsigned int*)(0x43812874UL))) +#define bM4_USBFS_DIEPCTL2_EPDIS (*((volatile unsigned int*)(0x43812878UL))) +#define bM4_USBFS_DIEPCTL2_EPENA (*((volatile unsigned int*)(0x4381287CUL))) +#define bM4_USBFS_DIEPINT2_XFRC (*((volatile unsigned int*)(0x43812900UL))) +#define bM4_USBFS_DIEPINT2_EPDISD (*((volatile unsigned int*)(0x43812904UL))) +#define bM4_USBFS_DIEPINT2_TOC (*((volatile unsigned int*)(0x4381290CUL))) +#define bM4_USBFS_DIEPINT2_TTXFE (*((volatile unsigned int*)(0x43812910UL))) +#define bM4_USBFS_DIEPINT2_INEPNE (*((volatile unsigned int*)(0x43812918UL))) +#define bM4_USBFS_DIEPINT2_TXFE (*((volatile unsigned int*)(0x4381291CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x43812A00UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x43812A04UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x43812A08UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x43812A0CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x43812A10UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x43812A14UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x43812A18UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x43812A1CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x43812A20UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x43812A24UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x43812A28UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x43812A2CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x43812A30UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x43812A34UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x43812A38UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x43812A3CUL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x43812A40UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x43812A44UL))) +#define bM4_USBFS_DIEPTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x43812A48UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x43812A4CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x43812A50UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x43812A54UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x43812A58UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x43812A5CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x43812A60UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x43812A64UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x43812A68UL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x43812A6CUL))) +#define bM4_USBFS_DIEPTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x43812A70UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV0 (*((volatile unsigned int*)(0x43812B00UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV1 (*((volatile unsigned int*)(0x43812B04UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV2 (*((volatile unsigned int*)(0x43812B08UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV3 (*((volatile unsigned int*)(0x43812B0CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV4 (*((volatile unsigned int*)(0x43812B10UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV5 (*((volatile unsigned int*)(0x43812B14UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV6 (*((volatile unsigned int*)(0x43812B18UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV7 (*((volatile unsigned int*)(0x43812B1CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV8 (*((volatile unsigned int*)(0x43812B20UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV9 (*((volatile unsigned int*)(0x43812B24UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV10 (*((volatile unsigned int*)(0x43812B28UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV11 (*((volatile unsigned int*)(0x43812B2CUL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV12 (*((volatile unsigned int*)(0x43812B30UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV13 (*((volatile unsigned int*)(0x43812B34UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV14 (*((volatile unsigned int*)(0x43812B38UL))) +#define bM4_USBFS_DTXFSTS2_INEPTFSAV15 (*((volatile unsigned int*)(0x43812B3CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ0 (*((volatile unsigned int*)(0x43812C00UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ1 (*((volatile unsigned int*)(0x43812C04UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ2 (*((volatile unsigned int*)(0x43812C08UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ3 (*((volatile unsigned int*)(0x43812C0CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ4 (*((volatile unsigned int*)(0x43812C10UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ5 (*((volatile unsigned int*)(0x43812C14UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ6 (*((volatile unsigned int*)(0x43812C18UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ7 (*((volatile unsigned int*)(0x43812C1CUL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ8 (*((volatile unsigned int*)(0x43812C20UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ9 (*((volatile unsigned int*)(0x43812C24UL))) +#define bM4_USBFS_DIEPCTL3_MPSIZ10 (*((volatile unsigned int*)(0x43812C28UL))) +#define bM4_USBFS_DIEPCTL3_USBAEP (*((volatile unsigned int*)(0x43812C3CUL))) +#define bM4_USBFS_DIEPCTL3_EONUM_DPID (*((volatile unsigned int*)(0x43812C40UL))) +#define bM4_USBFS_DIEPCTL3_NAKSTS (*((volatile unsigned int*)(0x43812C44UL))) +#define bM4_USBFS_DIEPCTL3_EPTYP0 (*((volatile unsigned int*)(0x43812C48UL))) +#define bM4_USBFS_DIEPCTL3_EPTYP1 (*((volatile unsigned int*)(0x43812C4CUL))) +#define bM4_USBFS_DIEPCTL3_STALL (*((volatile unsigned int*)(0x43812C54UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM0 (*((volatile unsigned int*)(0x43812C58UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM1 (*((volatile unsigned int*)(0x43812C5CUL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM2 (*((volatile unsigned int*)(0x43812C60UL))) +#define bM4_USBFS_DIEPCTL3_TXFNUM3 (*((volatile unsigned int*)(0x43812C64UL))) +#define bM4_USBFS_DIEPCTL3_CNAK (*((volatile unsigned int*)(0x43812C68UL))) +#define bM4_USBFS_DIEPCTL3_SNAK (*((volatile unsigned int*)(0x43812C6CUL))) +#define bM4_USBFS_DIEPCTL3_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43812C70UL))) +#define bM4_USBFS_DIEPCTL3_SODDFRM (*((volatile unsigned int*)(0x43812C74UL))) +#define bM4_USBFS_DIEPCTL3_EPDIS (*((volatile unsigned int*)(0x43812C78UL))) +#define bM4_USBFS_DIEPCTL3_EPENA (*((volatile unsigned int*)(0x43812C7CUL))) +#define bM4_USBFS_DIEPINT3_XFRC (*((volatile unsigned int*)(0x43812D00UL))) +#define bM4_USBFS_DIEPINT3_EPDISD (*((volatile unsigned int*)(0x43812D04UL))) +#define bM4_USBFS_DIEPINT3_TOC (*((volatile unsigned int*)(0x43812D0CUL))) +#define bM4_USBFS_DIEPINT3_TTXFE (*((volatile unsigned int*)(0x43812D10UL))) +#define bM4_USBFS_DIEPINT3_INEPNE (*((volatile unsigned int*)(0x43812D18UL))) +#define bM4_USBFS_DIEPINT3_TXFE (*((volatile unsigned int*)(0x43812D1CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x43812E00UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x43812E04UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x43812E08UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x43812E0CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x43812E10UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x43812E14UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x43812E18UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x43812E1CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x43812E20UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x43812E24UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x43812E28UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x43812E2CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x43812E30UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x43812E34UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x43812E38UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x43812E3CUL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x43812E40UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x43812E44UL))) +#define bM4_USBFS_DIEPTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x43812E48UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x43812E4CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x43812E50UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x43812E54UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x43812E58UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x43812E5CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x43812E60UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x43812E64UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x43812E68UL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x43812E6CUL))) +#define bM4_USBFS_DIEPTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x43812E70UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV0 (*((volatile unsigned int*)(0x43812F00UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV1 (*((volatile unsigned int*)(0x43812F04UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV2 (*((volatile unsigned int*)(0x43812F08UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV3 (*((volatile unsigned int*)(0x43812F0CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV4 (*((volatile unsigned int*)(0x43812F10UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV5 (*((volatile unsigned int*)(0x43812F14UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV6 (*((volatile unsigned int*)(0x43812F18UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV7 (*((volatile unsigned int*)(0x43812F1CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV8 (*((volatile unsigned int*)(0x43812F20UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV9 (*((volatile unsigned int*)(0x43812F24UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV10 (*((volatile unsigned int*)(0x43812F28UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV11 (*((volatile unsigned int*)(0x43812F2CUL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV12 (*((volatile unsigned int*)(0x43812F30UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV13 (*((volatile unsigned int*)(0x43812F34UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV14 (*((volatile unsigned int*)(0x43812F38UL))) +#define bM4_USBFS_DTXFSTS3_INEPTFSAV15 (*((volatile unsigned int*)(0x43812F3CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ0 (*((volatile unsigned int*)(0x43813000UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ1 (*((volatile unsigned int*)(0x43813004UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ2 (*((volatile unsigned int*)(0x43813008UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ3 (*((volatile unsigned int*)(0x4381300CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ4 (*((volatile unsigned int*)(0x43813010UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ5 (*((volatile unsigned int*)(0x43813014UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ6 (*((volatile unsigned int*)(0x43813018UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ7 (*((volatile unsigned int*)(0x4381301CUL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ8 (*((volatile unsigned int*)(0x43813020UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ9 (*((volatile unsigned int*)(0x43813024UL))) +#define bM4_USBFS_DIEPCTL4_MPSIZ10 (*((volatile unsigned int*)(0x43813028UL))) +#define bM4_USBFS_DIEPCTL4_USBAEP (*((volatile unsigned int*)(0x4381303CUL))) +#define bM4_USBFS_DIEPCTL4_EONUM_DPID (*((volatile unsigned int*)(0x43813040UL))) +#define bM4_USBFS_DIEPCTL4_NAKSTS (*((volatile unsigned int*)(0x43813044UL))) +#define bM4_USBFS_DIEPCTL4_EPTYP0 (*((volatile unsigned int*)(0x43813048UL))) +#define bM4_USBFS_DIEPCTL4_EPTYP1 (*((volatile unsigned int*)(0x4381304CUL))) +#define bM4_USBFS_DIEPCTL4_STALL (*((volatile unsigned int*)(0x43813054UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM0 (*((volatile unsigned int*)(0x43813058UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM1 (*((volatile unsigned int*)(0x4381305CUL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM2 (*((volatile unsigned int*)(0x43813060UL))) +#define bM4_USBFS_DIEPCTL4_TXFNUM3 (*((volatile unsigned int*)(0x43813064UL))) +#define bM4_USBFS_DIEPCTL4_CNAK (*((volatile unsigned int*)(0x43813068UL))) +#define bM4_USBFS_DIEPCTL4_SNAK (*((volatile unsigned int*)(0x4381306CUL))) +#define bM4_USBFS_DIEPCTL4_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43813070UL))) +#define bM4_USBFS_DIEPCTL4_SODDFRM (*((volatile unsigned int*)(0x43813074UL))) +#define bM4_USBFS_DIEPCTL4_EPDIS (*((volatile unsigned int*)(0x43813078UL))) +#define bM4_USBFS_DIEPCTL4_EPENA (*((volatile unsigned int*)(0x4381307CUL))) +#define bM4_USBFS_DIEPINT4_XFRC (*((volatile unsigned int*)(0x43813100UL))) +#define bM4_USBFS_DIEPINT4_EPDISD (*((volatile unsigned int*)(0x43813104UL))) +#define bM4_USBFS_DIEPINT4_TOC (*((volatile unsigned int*)(0x4381310CUL))) +#define bM4_USBFS_DIEPINT4_TTXFE (*((volatile unsigned int*)(0x43813110UL))) +#define bM4_USBFS_DIEPINT4_INEPNE (*((volatile unsigned int*)(0x43813118UL))) +#define bM4_USBFS_DIEPINT4_TXFE (*((volatile unsigned int*)(0x4381311CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x43813200UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x43813204UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x43813208UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4381320CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x43813210UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x43813214UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x43813218UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4381321CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x43813220UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x43813224UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x43813228UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4381322CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x43813230UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x43813234UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x43813238UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4381323CUL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x43813240UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x43813244UL))) +#define bM4_USBFS_DIEPTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x43813248UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4381324CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x43813250UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x43813254UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x43813258UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4381325CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x43813260UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x43813264UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x43813268UL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4381326CUL))) +#define bM4_USBFS_DIEPTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x43813270UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV0 (*((volatile unsigned int*)(0x43813300UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV1 (*((volatile unsigned int*)(0x43813304UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV2 (*((volatile unsigned int*)(0x43813308UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV3 (*((volatile unsigned int*)(0x4381330CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV4 (*((volatile unsigned int*)(0x43813310UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV5 (*((volatile unsigned int*)(0x43813314UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV6 (*((volatile unsigned int*)(0x43813318UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV7 (*((volatile unsigned int*)(0x4381331CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV8 (*((volatile unsigned int*)(0x43813320UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV9 (*((volatile unsigned int*)(0x43813324UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV10 (*((volatile unsigned int*)(0x43813328UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV11 (*((volatile unsigned int*)(0x4381332CUL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV12 (*((volatile unsigned int*)(0x43813330UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV13 (*((volatile unsigned int*)(0x43813334UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV14 (*((volatile unsigned int*)(0x43813338UL))) +#define bM4_USBFS_DTXFSTS4_INEPTFSAV15 (*((volatile unsigned int*)(0x4381333CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ0 (*((volatile unsigned int*)(0x43813400UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ1 (*((volatile unsigned int*)(0x43813404UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ2 (*((volatile unsigned int*)(0x43813408UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ3 (*((volatile unsigned int*)(0x4381340CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ4 (*((volatile unsigned int*)(0x43813410UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ5 (*((volatile unsigned int*)(0x43813414UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ6 (*((volatile unsigned int*)(0x43813418UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ7 (*((volatile unsigned int*)(0x4381341CUL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ8 (*((volatile unsigned int*)(0x43813420UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ9 (*((volatile unsigned int*)(0x43813424UL))) +#define bM4_USBFS_DIEPCTL5_MPSIZ10 (*((volatile unsigned int*)(0x43813428UL))) +#define bM4_USBFS_DIEPCTL5_USBAEP (*((volatile unsigned int*)(0x4381343CUL))) +#define bM4_USBFS_DIEPCTL5_EONUM_DPID (*((volatile unsigned int*)(0x43813440UL))) +#define bM4_USBFS_DIEPCTL5_NAKSTS (*((volatile unsigned int*)(0x43813444UL))) +#define bM4_USBFS_DIEPCTL5_EPTYP0 (*((volatile unsigned int*)(0x43813448UL))) +#define bM4_USBFS_DIEPCTL5_EPTYP1 (*((volatile unsigned int*)(0x4381344CUL))) +#define bM4_USBFS_DIEPCTL5_STALL (*((volatile unsigned int*)(0x43813454UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM0 (*((volatile unsigned int*)(0x43813458UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM1 (*((volatile unsigned int*)(0x4381345CUL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM2 (*((volatile unsigned int*)(0x43813460UL))) +#define bM4_USBFS_DIEPCTL5_TXFNUM3 (*((volatile unsigned int*)(0x43813464UL))) +#define bM4_USBFS_DIEPCTL5_CNAK (*((volatile unsigned int*)(0x43813468UL))) +#define bM4_USBFS_DIEPCTL5_SNAK (*((volatile unsigned int*)(0x4381346CUL))) +#define bM4_USBFS_DIEPCTL5_SD0PID_SEVNFRM (*((volatile unsigned int*)(0x43813470UL))) +#define bM4_USBFS_DIEPCTL5_SODDFRM (*((volatile unsigned int*)(0x43813474UL))) +#define bM4_USBFS_DIEPCTL5_EPDIS (*((volatile unsigned int*)(0x43813478UL))) +#define bM4_USBFS_DIEPCTL5_EPENA (*((volatile unsigned int*)(0x4381347CUL))) +#define bM4_USBFS_DIEPINT5_XFRC (*((volatile unsigned int*)(0x43813500UL))) +#define bM4_USBFS_DIEPINT5_EPDISD (*((volatile unsigned int*)(0x43813504UL))) +#define bM4_USBFS_DIEPINT5_TOC (*((volatile unsigned int*)(0x4381350CUL))) +#define bM4_USBFS_DIEPINT5_TTXFE (*((volatile unsigned int*)(0x43813510UL))) +#define bM4_USBFS_DIEPINT5_INEPNE (*((volatile unsigned int*)(0x43813518UL))) +#define bM4_USBFS_DIEPINT5_TXFE (*((volatile unsigned int*)(0x4381351CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x43813600UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x43813604UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x43813608UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4381360CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x43813610UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x43813614UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x43813618UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4381361CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x43813620UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x43813624UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x43813628UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4381362CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x43813630UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x43813634UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x43813638UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4381363CUL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x43813640UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x43813644UL))) +#define bM4_USBFS_DIEPTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x43813648UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4381364CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x43813650UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x43813654UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x43813658UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4381365CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x43813660UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x43813664UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x43813668UL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4381366CUL))) +#define bM4_USBFS_DIEPTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x43813670UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV0 (*((volatile unsigned int*)(0x43813700UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV1 (*((volatile unsigned int*)(0x43813704UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV2 (*((volatile unsigned int*)(0x43813708UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV3 (*((volatile unsigned int*)(0x4381370CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV4 (*((volatile unsigned int*)(0x43813710UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV5 (*((volatile unsigned int*)(0x43813714UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV6 (*((volatile unsigned int*)(0x43813718UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV7 (*((volatile unsigned int*)(0x4381371CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV8 (*((volatile unsigned int*)(0x43813720UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV9 (*((volatile unsigned int*)(0x43813724UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV10 (*((volatile unsigned int*)(0x43813728UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV11 (*((volatile unsigned int*)(0x4381372CUL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV12 (*((volatile unsigned int*)(0x43813730UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV13 (*((volatile unsigned int*)(0x43813734UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV14 (*((volatile unsigned int*)(0x43813738UL))) +#define bM4_USBFS_DTXFSTS5_INEPTFSAV15 (*((volatile unsigned int*)(0x4381373CUL))) +#define bM4_USBFS_DOEPCTL0_MPSIZ0 (*((volatile unsigned int*)(0x43816000UL))) +#define bM4_USBFS_DOEPCTL0_MPSIZ1 (*((volatile unsigned int*)(0x43816004UL))) +#define bM4_USBFS_DOEPCTL0_USBAEP (*((volatile unsigned int*)(0x4381603CUL))) +#define bM4_USBFS_DOEPCTL0_NAKSTS (*((volatile unsigned int*)(0x43816044UL))) +#define bM4_USBFS_DOEPCTL0_EPTYP0 (*((volatile unsigned int*)(0x43816048UL))) +#define bM4_USBFS_DOEPCTL0_EPTYP1 (*((volatile unsigned int*)(0x4381604CUL))) +#define bM4_USBFS_DOEPCTL0_SNPM (*((volatile unsigned int*)(0x43816050UL))) +#define bM4_USBFS_DOEPCTL0_STALL (*((volatile unsigned int*)(0x43816054UL))) +#define bM4_USBFS_DOEPCTL0_CNAK (*((volatile unsigned int*)(0x43816068UL))) +#define bM4_USBFS_DOEPCTL0_SNAK (*((volatile unsigned int*)(0x4381606CUL))) +#define bM4_USBFS_DOEPCTL0_EPDIS (*((volatile unsigned int*)(0x43816078UL))) +#define bM4_USBFS_DOEPCTL0_EPENA (*((volatile unsigned int*)(0x4381607CUL))) +#define bM4_USBFS_DOEPINT0_XFRC (*((volatile unsigned int*)(0x43816100UL))) +#define bM4_USBFS_DOEPINT0_EPDISD (*((volatile unsigned int*)(0x43816104UL))) +#define bM4_USBFS_DOEPINT0_STUP (*((volatile unsigned int*)(0x4381610CUL))) +#define bM4_USBFS_DOEPINT0_OTEPDIS (*((volatile unsigned int*)(0x43816110UL))) +#define bM4_USBFS_DOEPINT0_B2BSTUP (*((volatile unsigned int*)(0x43816118UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ0 (*((volatile unsigned int*)(0x43816200UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ1 (*((volatile unsigned int*)(0x43816204UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ2 (*((volatile unsigned int*)(0x43816208UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ3 (*((volatile unsigned int*)(0x4381620CUL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ4 (*((volatile unsigned int*)(0x43816210UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ5 (*((volatile unsigned int*)(0x43816214UL))) +#define bM4_USBFS_DOEPTSIZ0_XFRSIZ6 (*((volatile unsigned int*)(0x43816218UL))) +#define bM4_USBFS_DOEPTSIZ0_PKTCNT (*((volatile unsigned int*)(0x4381624CUL))) +#define bM4_USBFS_DOEPTSIZ0_STUPCNT0 (*((volatile unsigned int*)(0x43816274UL))) +#define bM4_USBFS_DOEPTSIZ0_STUPCNT1 (*((volatile unsigned int*)(0x43816278UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ0 (*((volatile unsigned int*)(0x43816400UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ1 (*((volatile unsigned int*)(0x43816404UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ2 (*((volatile unsigned int*)(0x43816408UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ3 (*((volatile unsigned int*)(0x4381640CUL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ4 (*((volatile unsigned int*)(0x43816410UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ5 (*((volatile unsigned int*)(0x43816414UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ6 (*((volatile unsigned int*)(0x43816418UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ7 (*((volatile unsigned int*)(0x4381641CUL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ8 (*((volatile unsigned int*)(0x43816420UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ9 (*((volatile unsigned int*)(0x43816424UL))) +#define bM4_USBFS_DOEPCTL1_MPSIZ10 (*((volatile unsigned int*)(0x43816428UL))) +#define bM4_USBFS_DOEPCTL1_USBAEP (*((volatile unsigned int*)(0x4381643CUL))) +#define bM4_USBFS_DOEPCTL1_DPID (*((volatile unsigned int*)(0x43816440UL))) +#define bM4_USBFS_DOEPCTL1_NAKSTS (*((volatile unsigned int*)(0x43816444UL))) +#define bM4_USBFS_DOEPCTL1_EPTYP0 (*((volatile unsigned int*)(0x43816448UL))) +#define bM4_USBFS_DOEPCTL1_EPTYP1 (*((volatile unsigned int*)(0x4381644CUL))) +#define bM4_USBFS_DOEPCTL1_SNPM (*((volatile unsigned int*)(0x43816450UL))) +#define bM4_USBFS_DOEPCTL1_STALL (*((volatile unsigned int*)(0x43816454UL))) +#define bM4_USBFS_DOEPCTL1_CNAK (*((volatile unsigned int*)(0x43816468UL))) +#define bM4_USBFS_DOEPCTL1_SNAK (*((volatile unsigned int*)(0x4381646CUL))) +#define bM4_USBFS_DOEPCTL1_SD0PID (*((volatile unsigned int*)(0x43816470UL))) +#define bM4_USBFS_DOEPCTL1_SD1PID (*((volatile unsigned int*)(0x43816474UL))) +#define bM4_USBFS_DOEPCTL1_EPDIS (*((volatile unsigned int*)(0x43816478UL))) +#define bM4_USBFS_DOEPCTL1_EPENA (*((volatile unsigned int*)(0x4381647CUL))) +#define bM4_USBFS_DOEPINT1_XFRC (*((volatile unsigned int*)(0x43816500UL))) +#define bM4_USBFS_DOEPINT1_EPDISD (*((volatile unsigned int*)(0x43816504UL))) +#define bM4_USBFS_DOEPINT1_STUP (*((volatile unsigned int*)(0x4381650CUL))) +#define bM4_USBFS_DOEPINT1_OTEPDIS (*((volatile unsigned int*)(0x43816510UL))) +#define bM4_USBFS_DOEPINT1_B2BSTUP (*((volatile unsigned int*)(0x43816518UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ0 (*((volatile unsigned int*)(0x43816600UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ1 (*((volatile unsigned int*)(0x43816604UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ2 (*((volatile unsigned int*)(0x43816608UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ3 (*((volatile unsigned int*)(0x4381660CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ4 (*((volatile unsigned int*)(0x43816610UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ5 (*((volatile unsigned int*)(0x43816614UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ6 (*((volatile unsigned int*)(0x43816618UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ7 (*((volatile unsigned int*)(0x4381661CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ8 (*((volatile unsigned int*)(0x43816620UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ9 (*((volatile unsigned int*)(0x43816624UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ10 (*((volatile unsigned int*)(0x43816628UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ11 (*((volatile unsigned int*)(0x4381662CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ12 (*((volatile unsigned int*)(0x43816630UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ13 (*((volatile unsigned int*)(0x43816634UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ14 (*((volatile unsigned int*)(0x43816638UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ15 (*((volatile unsigned int*)(0x4381663CUL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ16 (*((volatile unsigned int*)(0x43816640UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ17 (*((volatile unsigned int*)(0x43816644UL))) +#define bM4_USBFS_DOEPTSIZ1_XFRSIZ18 (*((volatile unsigned int*)(0x43816648UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT0 (*((volatile unsigned int*)(0x4381664CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT1 (*((volatile unsigned int*)(0x43816650UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT2 (*((volatile unsigned int*)(0x43816654UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT3 (*((volatile unsigned int*)(0x43816658UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT4 (*((volatile unsigned int*)(0x4381665CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT5 (*((volatile unsigned int*)(0x43816660UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT6 (*((volatile unsigned int*)(0x43816664UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT7 (*((volatile unsigned int*)(0x43816668UL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT8 (*((volatile unsigned int*)(0x4381666CUL))) +#define bM4_USBFS_DOEPTSIZ1_PKTCNT9 (*((volatile unsigned int*)(0x43816670UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ0 (*((volatile unsigned int*)(0x43816800UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ1 (*((volatile unsigned int*)(0x43816804UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ2 (*((volatile unsigned int*)(0x43816808UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ3 (*((volatile unsigned int*)(0x4381680CUL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ4 (*((volatile unsigned int*)(0x43816810UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ5 (*((volatile unsigned int*)(0x43816814UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ6 (*((volatile unsigned int*)(0x43816818UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ7 (*((volatile unsigned int*)(0x4381681CUL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ8 (*((volatile unsigned int*)(0x43816820UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ9 (*((volatile unsigned int*)(0x43816824UL))) +#define bM4_USBFS_DOEPCTL2_MPSIZ10 (*((volatile unsigned int*)(0x43816828UL))) +#define bM4_USBFS_DOEPCTL2_USBAEP (*((volatile unsigned int*)(0x4381683CUL))) +#define bM4_USBFS_DOEPCTL2_DPID (*((volatile unsigned int*)(0x43816840UL))) +#define bM4_USBFS_DOEPCTL2_NAKSTS (*((volatile unsigned int*)(0x43816844UL))) +#define bM4_USBFS_DOEPCTL2_EPTYP0 (*((volatile unsigned int*)(0x43816848UL))) +#define bM4_USBFS_DOEPCTL2_EPTYP1 (*((volatile unsigned int*)(0x4381684CUL))) +#define bM4_USBFS_DOEPCTL2_SNPM (*((volatile unsigned int*)(0x43816850UL))) +#define bM4_USBFS_DOEPCTL2_STALL (*((volatile unsigned int*)(0x43816854UL))) +#define bM4_USBFS_DOEPCTL2_CNAK (*((volatile unsigned int*)(0x43816868UL))) +#define bM4_USBFS_DOEPCTL2_SNAK (*((volatile unsigned int*)(0x4381686CUL))) +#define bM4_USBFS_DOEPCTL2_SD0PID (*((volatile unsigned int*)(0x43816870UL))) +#define bM4_USBFS_DOEPCTL2_SD1PID (*((volatile unsigned int*)(0x43816874UL))) +#define bM4_USBFS_DOEPCTL2_EPDIS (*((volatile unsigned int*)(0x43816878UL))) +#define bM4_USBFS_DOEPCTL2_EPENA (*((volatile unsigned int*)(0x4381687CUL))) +#define bM4_USBFS_DOEPINT2_XFRC (*((volatile unsigned int*)(0x43816900UL))) +#define bM4_USBFS_DOEPINT2_EPDISD (*((volatile unsigned int*)(0x43816904UL))) +#define bM4_USBFS_DOEPINT2_STUP (*((volatile unsigned int*)(0x4381690CUL))) +#define bM4_USBFS_DOEPINT2_OTEPDIS (*((volatile unsigned int*)(0x43816910UL))) +#define bM4_USBFS_DOEPINT2_B2BSTUP (*((volatile unsigned int*)(0x43816918UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ0 (*((volatile unsigned int*)(0x43816A00UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ1 (*((volatile unsigned int*)(0x43816A04UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ2 (*((volatile unsigned int*)(0x43816A08UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ3 (*((volatile unsigned int*)(0x43816A0CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ4 (*((volatile unsigned int*)(0x43816A10UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ5 (*((volatile unsigned int*)(0x43816A14UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ6 (*((volatile unsigned int*)(0x43816A18UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ7 (*((volatile unsigned int*)(0x43816A1CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ8 (*((volatile unsigned int*)(0x43816A20UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ9 (*((volatile unsigned int*)(0x43816A24UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ10 (*((volatile unsigned int*)(0x43816A28UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ11 (*((volatile unsigned int*)(0x43816A2CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ12 (*((volatile unsigned int*)(0x43816A30UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ13 (*((volatile unsigned int*)(0x43816A34UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ14 (*((volatile unsigned int*)(0x43816A38UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ15 (*((volatile unsigned int*)(0x43816A3CUL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ16 (*((volatile unsigned int*)(0x43816A40UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ17 (*((volatile unsigned int*)(0x43816A44UL))) +#define bM4_USBFS_DOEPTSIZ2_XFRSIZ18 (*((volatile unsigned int*)(0x43816A48UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT0 (*((volatile unsigned int*)(0x43816A4CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT1 (*((volatile unsigned int*)(0x43816A50UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT2 (*((volatile unsigned int*)(0x43816A54UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT3 (*((volatile unsigned int*)(0x43816A58UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT4 (*((volatile unsigned int*)(0x43816A5CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT5 (*((volatile unsigned int*)(0x43816A60UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT6 (*((volatile unsigned int*)(0x43816A64UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT7 (*((volatile unsigned int*)(0x43816A68UL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT8 (*((volatile unsigned int*)(0x43816A6CUL))) +#define bM4_USBFS_DOEPTSIZ2_PKTCNT9 (*((volatile unsigned int*)(0x43816A70UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ0 (*((volatile unsigned int*)(0x43816C00UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ1 (*((volatile unsigned int*)(0x43816C04UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ2 (*((volatile unsigned int*)(0x43816C08UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ3 (*((volatile unsigned int*)(0x43816C0CUL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ4 (*((volatile unsigned int*)(0x43816C10UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ5 (*((volatile unsigned int*)(0x43816C14UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ6 (*((volatile unsigned int*)(0x43816C18UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ7 (*((volatile unsigned int*)(0x43816C1CUL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ8 (*((volatile unsigned int*)(0x43816C20UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ9 (*((volatile unsigned int*)(0x43816C24UL))) +#define bM4_USBFS_DOEPCTL3_MPSIZ10 (*((volatile unsigned int*)(0x43816C28UL))) +#define bM4_USBFS_DOEPCTL3_USBAEP (*((volatile unsigned int*)(0x43816C3CUL))) +#define bM4_USBFS_DOEPCTL3_DPID (*((volatile unsigned int*)(0x43816C40UL))) +#define bM4_USBFS_DOEPCTL3_NAKSTS (*((volatile unsigned int*)(0x43816C44UL))) +#define bM4_USBFS_DOEPCTL3_EPTYP0 (*((volatile unsigned int*)(0x43816C48UL))) +#define bM4_USBFS_DOEPCTL3_EPTYP1 (*((volatile unsigned int*)(0x43816C4CUL))) +#define bM4_USBFS_DOEPCTL3_SNPM (*((volatile unsigned int*)(0x43816C50UL))) +#define bM4_USBFS_DOEPCTL3_STALL (*((volatile unsigned int*)(0x43816C54UL))) +#define bM4_USBFS_DOEPCTL3_CNAK (*((volatile unsigned int*)(0x43816C68UL))) +#define bM4_USBFS_DOEPCTL3_SNAK (*((volatile unsigned int*)(0x43816C6CUL))) +#define bM4_USBFS_DOEPCTL3_SD0PID (*((volatile unsigned int*)(0x43816C70UL))) +#define bM4_USBFS_DOEPCTL3_SD1PID (*((volatile unsigned int*)(0x43816C74UL))) +#define bM4_USBFS_DOEPCTL3_EPDIS (*((volatile unsigned int*)(0x43816C78UL))) +#define bM4_USBFS_DOEPCTL3_EPENA (*((volatile unsigned int*)(0x43816C7CUL))) +#define bM4_USBFS_DOEPINT3_XFRC (*((volatile unsigned int*)(0x43816D00UL))) +#define bM4_USBFS_DOEPINT3_EPDISD (*((volatile unsigned int*)(0x43816D04UL))) +#define bM4_USBFS_DOEPINT3_STUP (*((volatile unsigned int*)(0x43816D0CUL))) +#define bM4_USBFS_DOEPINT3_OTEPDIS (*((volatile unsigned int*)(0x43816D10UL))) +#define bM4_USBFS_DOEPINT3_B2BSTUP (*((volatile unsigned int*)(0x43816D18UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ0 (*((volatile unsigned int*)(0x43816E00UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ1 (*((volatile unsigned int*)(0x43816E04UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ2 (*((volatile unsigned int*)(0x43816E08UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ3 (*((volatile unsigned int*)(0x43816E0CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ4 (*((volatile unsigned int*)(0x43816E10UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ5 (*((volatile unsigned int*)(0x43816E14UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ6 (*((volatile unsigned int*)(0x43816E18UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ7 (*((volatile unsigned int*)(0x43816E1CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ8 (*((volatile unsigned int*)(0x43816E20UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ9 (*((volatile unsigned int*)(0x43816E24UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ10 (*((volatile unsigned int*)(0x43816E28UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ11 (*((volatile unsigned int*)(0x43816E2CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ12 (*((volatile unsigned int*)(0x43816E30UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ13 (*((volatile unsigned int*)(0x43816E34UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ14 (*((volatile unsigned int*)(0x43816E38UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ15 (*((volatile unsigned int*)(0x43816E3CUL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ16 (*((volatile unsigned int*)(0x43816E40UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ17 (*((volatile unsigned int*)(0x43816E44UL))) +#define bM4_USBFS_DOEPTSIZ3_XFRSIZ18 (*((volatile unsigned int*)(0x43816E48UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT0 (*((volatile unsigned int*)(0x43816E4CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT1 (*((volatile unsigned int*)(0x43816E50UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT2 (*((volatile unsigned int*)(0x43816E54UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT3 (*((volatile unsigned int*)(0x43816E58UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT4 (*((volatile unsigned int*)(0x43816E5CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT5 (*((volatile unsigned int*)(0x43816E60UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT6 (*((volatile unsigned int*)(0x43816E64UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT7 (*((volatile unsigned int*)(0x43816E68UL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT8 (*((volatile unsigned int*)(0x43816E6CUL))) +#define bM4_USBFS_DOEPTSIZ3_PKTCNT9 (*((volatile unsigned int*)(0x43816E70UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ0 (*((volatile unsigned int*)(0x43817000UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ1 (*((volatile unsigned int*)(0x43817004UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ2 (*((volatile unsigned int*)(0x43817008UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ3 (*((volatile unsigned int*)(0x4381700CUL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ4 (*((volatile unsigned int*)(0x43817010UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ5 (*((volatile unsigned int*)(0x43817014UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ6 (*((volatile unsigned int*)(0x43817018UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ7 (*((volatile unsigned int*)(0x4381701CUL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ8 (*((volatile unsigned int*)(0x43817020UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ9 (*((volatile unsigned int*)(0x43817024UL))) +#define bM4_USBFS_DOEPCTL4_MPSIZ10 (*((volatile unsigned int*)(0x43817028UL))) +#define bM4_USBFS_DOEPCTL4_USBAEP (*((volatile unsigned int*)(0x4381703CUL))) +#define bM4_USBFS_DOEPCTL4_DPID (*((volatile unsigned int*)(0x43817040UL))) +#define bM4_USBFS_DOEPCTL4_NAKSTS (*((volatile unsigned int*)(0x43817044UL))) +#define bM4_USBFS_DOEPCTL4_EPTYP0 (*((volatile unsigned int*)(0x43817048UL))) +#define bM4_USBFS_DOEPCTL4_EPTYP1 (*((volatile unsigned int*)(0x4381704CUL))) +#define bM4_USBFS_DOEPCTL4_SNPM (*((volatile unsigned int*)(0x43817050UL))) +#define bM4_USBFS_DOEPCTL4_STALL (*((volatile unsigned int*)(0x43817054UL))) +#define bM4_USBFS_DOEPCTL4_CNAK (*((volatile unsigned int*)(0x43817068UL))) +#define bM4_USBFS_DOEPCTL4_SNAK (*((volatile unsigned int*)(0x4381706CUL))) +#define bM4_USBFS_DOEPCTL4_SD0PID (*((volatile unsigned int*)(0x43817070UL))) +#define bM4_USBFS_DOEPCTL4_SD1PID (*((volatile unsigned int*)(0x43817074UL))) +#define bM4_USBFS_DOEPCTL4_EPDIS (*((volatile unsigned int*)(0x43817078UL))) +#define bM4_USBFS_DOEPCTL4_EPENA (*((volatile unsigned int*)(0x4381707CUL))) +#define bM4_USBFS_DOEPINT4_XFRC (*((volatile unsigned int*)(0x43817100UL))) +#define bM4_USBFS_DOEPINT4_EPDISD (*((volatile unsigned int*)(0x43817104UL))) +#define bM4_USBFS_DOEPINT4_STUP (*((volatile unsigned int*)(0x4381710CUL))) +#define bM4_USBFS_DOEPINT4_OTEPDIS (*((volatile unsigned int*)(0x43817110UL))) +#define bM4_USBFS_DOEPINT4_B2BSTUP (*((volatile unsigned int*)(0x43817118UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ0 (*((volatile unsigned int*)(0x43817200UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ1 (*((volatile unsigned int*)(0x43817204UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ2 (*((volatile unsigned int*)(0x43817208UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ3 (*((volatile unsigned int*)(0x4381720CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ4 (*((volatile unsigned int*)(0x43817210UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ5 (*((volatile unsigned int*)(0x43817214UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ6 (*((volatile unsigned int*)(0x43817218UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ7 (*((volatile unsigned int*)(0x4381721CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ8 (*((volatile unsigned int*)(0x43817220UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ9 (*((volatile unsigned int*)(0x43817224UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ10 (*((volatile unsigned int*)(0x43817228UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ11 (*((volatile unsigned int*)(0x4381722CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ12 (*((volatile unsigned int*)(0x43817230UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ13 (*((volatile unsigned int*)(0x43817234UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ14 (*((volatile unsigned int*)(0x43817238UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ15 (*((volatile unsigned int*)(0x4381723CUL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ16 (*((volatile unsigned int*)(0x43817240UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ17 (*((volatile unsigned int*)(0x43817244UL))) +#define bM4_USBFS_DOEPTSIZ4_XFRSIZ18 (*((volatile unsigned int*)(0x43817248UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT0 (*((volatile unsigned int*)(0x4381724CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT1 (*((volatile unsigned int*)(0x43817250UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT2 (*((volatile unsigned int*)(0x43817254UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT3 (*((volatile unsigned int*)(0x43817258UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT4 (*((volatile unsigned int*)(0x4381725CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT5 (*((volatile unsigned int*)(0x43817260UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT6 (*((volatile unsigned int*)(0x43817264UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT7 (*((volatile unsigned int*)(0x43817268UL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT8 (*((volatile unsigned int*)(0x4381726CUL))) +#define bM4_USBFS_DOEPTSIZ4_PKTCNT9 (*((volatile unsigned int*)(0x43817270UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ0 (*((volatile unsigned int*)(0x43817400UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ1 (*((volatile unsigned int*)(0x43817404UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ2 (*((volatile unsigned int*)(0x43817408UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ3 (*((volatile unsigned int*)(0x4381740CUL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ4 (*((volatile unsigned int*)(0x43817410UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ5 (*((volatile unsigned int*)(0x43817414UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ6 (*((volatile unsigned int*)(0x43817418UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ7 (*((volatile unsigned int*)(0x4381741CUL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ8 (*((volatile unsigned int*)(0x43817420UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ9 (*((volatile unsigned int*)(0x43817424UL))) +#define bM4_USBFS_DOEPCTL5_MPSIZ10 (*((volatile unsigned int*)(0x43817428UL))) +#define bM4_USBFS_DOEPCTL5_USBAEP (*((volatile unsigned int*)(0x4381743CUL))) +#define bM4_USBFS_DOEPCTL5_DPID (*((volatile unsigned int*)(0x43817440UL))) +#define bM4_USBFS_DOEPCTL5_NAKSTS (*((volatile unsigned int*)(0x43817444UL))) +#define bM4_USBFS_DOEPCTL5_EPTYP0 (*((volatile unsigned int*)(0x43817448UL))) +#define bM4_USBFS_DOEPCTL5_EPTYP1 (*((volatile unsigned int*)(0x4381744CUL))) +#define bM4_USBFS_DOEPCTL5_SNPM (*((volatile unsigned int*)(0x43817450UL))) +#define bM4_USBFS_DOEPCTL5_STALL (*((volatile unsigned int*)(0x43817454UL))) +#define bM4_USBFS_DOEPCTL5_CNAK (*((volatile unsigned int*)(0x43817468UL))) +#define bM4_USBFS_DOEPCTL5_SNAK (*((volatile unsigned int*)(0x4381746CUL))) +#define bM4_USBFS_DOEPCTL5_SD0PID (*((volatile unsigned int*)(0x43817470UL))) +#define bM4_USBFS_DOEPCTL5_SD1PID (*((volatile unsigned int*)(0x43817474UL))) +#define bM4_USBFS_DOEPCTL5_EPDIS (*((volatile unsigned int*)(0x43817478UL))) +#define bM4_USBFS_DOEPCTL5_EPENA (*((volatile unsigned int*)(0x4381747CUL))) +#define bM4_USBFS_DOEPINT5_XFRC (*((volatile unsigned int*)(0x43817500UL))) +#define bM4_USBFS_DOEPINT5_EPDISD (*((volatile unsigned int*)(0x43817504UL))) +#define bM4_USBFS_DOEPINT5_STUP (*((volatile unsigned int*)(0x4381750CUL))) +#define bM4_USBFS_DOEPINT5_OTEPDIS (*((volatile unsigned int*)(0x43817510UL))) +#define bM4_USBFS_DOEPINT5_B2BSTUP (*((volatile unsigned int*)(0x43817518UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ0 (*((volatile unsigned int*)(0x43817600UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ1 (*((volatile unsigned int*)(0x43817604UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ2 (*((volatile unsigned int*)(0x43817608UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ3 (*((volatile unsigned int*)(0x4381760CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ4 (*((volatile unsigned int*)(0x43817610UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ5 (*((volatile unsigned int*)(0x43817614UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ6 (*((volatile unsigned int*)(0x43817618UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ7 (*((volatile unsigned int*)(0x4381761CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ8 (*((volatile unsigned int*)(0x43817620UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ9 (*((volatile unsigned int*)(0x43817624UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ10 (*((volatile unsigned int*)(0x43817628UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ11 (*((volatile unsigned int*)(0x4381762CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ12 (*((volatile unsigned int*)(0x43817630UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ13 (*((volatile unsigned int*)(0x43817634UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ14 (*((volatile unsigned int*)(0x43817638UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ15 (*((volatile unsigned int*)(0x4381763CUL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ16 (*((volatile unsigned int*)(0x43817640UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ17 (*((volatile unsigned int*)(0x43817644UL))) +#define bM4_USBFS_DOEPTSIZ5_XFRSIZ18 (*((volatile unsigned int*)(0x43817648UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT0 (*((volatile unsigned int*)(0x4381764CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT1 (*((volatile unsigned int*)(0x43817650UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT2 (*((volatile unsigned int*)(0x43817654UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT3 (*((volatile unsigned int*)(0x43817658UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT4 (*((volatile unsigned int*)(0x4381765CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT5 (*((volatile unsigned int*)(0x43817660UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT6 (*((volatile unsigned int*)(0x43817664UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT7 (*((volatile unsigned int*)(0x43817668UL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT8 (*((volatile unsigned int*)(0x4381766CUL))) +#define bM4_USBFS_DOEPTSIZ5_PKTCNT9 (*((volatile unsigned int*)(0x43817670UL))) +#define bM4_USBFS_PCGCCTL_STPPCLK (*((volatile unsigned int*)(0x4381C000UL))) +#define bM4_USBFS_PCGCCTL_GATEHCLK (*((volatile unsigned int*)(0x4381C004UL))) +#define bM4_WDT_CR_PERI0 (*((volatile unsigned int*)(0x42920000UL))) +#define bM4_WDT_CR_PERI1 (*((volatile unsigned int*)(0x42920004UL))) +#define bM4_WDT_CR_CKS0 (*((volatile unsigned int*)(0x42920010UL))) +#define bM4_WDT_CR_CKS1 (*((volatile unsigned int*)(0x42920014UL))) +#define bM4_WDT_CR_CKS2 (*((volatile unsigned int*)(0x42920018UL))) +#define bM4_WDT_CR_CKS3 (*((volatile unsigned int*)(0x4292001CUL))) +#define bM4_WDT_CR_WDPT0 (*((volatile unsigned int*)(0x42920020UL))) +#define bM4_WDT_CR_WDPT1 (*((volatile unsigned int*)(0x42920024UL))) +#define bM4_WDT_CR_WDPT2 (*((volatile unsigned int*)(0x42920028UL))) +#define bM4_WDT_CR_WDPT3 (*((volatile unsigned int*)(0x4292002CUL))) +#define bM4_WDT_CR_SLPOFF (*((volatile unsigned int*)(0x42920040UL))) +#define bM4_WDT_CR_ITS (*((volatile unsigned int*)(0x4292007CUL))) +#define bM4_WDT_SR_CNT0 (*((volatile unsigned int*)(0x42920080UL))) +#define bM4_WDT_SR_CNT1 (*((volatile unsigned int*)(0x42920084UL))) +#define bM4_WDT_SR_CNT2 (*((volatile unsigned int*)(0x42920088UL))) +#define bM4_WDT_SR_CNT3 (*((volatile unsigned int*)(0x4292008CUL))) +#define bM4_WDT_SR_CNT4 (*((volatile unsigned int*)(0x42920090UL))) +#define bM4_WDT_SR_CNT5 (*((volatile unsigned int*)(0x42920094UL))) +#define bM4_WDT_SR_CNT6 (*((volatile unsigned int*)(0x42920098UL))) +#define bM4_WDT_SR_CNT7 (*((volatile unsigned int*)(0x4292009CUL))) +#define bM4_WDT_SR_CNT8 (*((volatile unsigned int*)(0x429200A0UL))) +#define bM4_WDT_SR_CNT9 (*((volatile unsigned int*)(0x429200A4UL))) +#define bM4_WDT_SR_CNT10 (*((volatile unsigned int*)(0x429200A8UL))) +#define bM4_WDT_SR_CNT11 (*((volatile unsigned int*)(0x429200ACUL))) +#define bM4_WDT_SR_CNT12 (*((volatile unsigned int*)(0x429200B0UL))) +#define bM4_WDT_SR_CNT13 (*((volatile unsigned int*)(0x429200B4UL))) +#define bM4_WDT_SR_CNT14 (*((volatile unsigned int*)(0x429200B8UL))) +#define bM4_WDT_SR_CNT15 (*((volatile unsigned int*)(0x429200BCUL))) +#define bM4_WDT_SR_UDF (*((volatile unsigned int*)(0x429200C0UL))) +#define bM4_WDT_SR_REF (*((volatile unsigned int*)(0x429200C4UL))) +#define bM4_WDT_RR_RF0 (*((volatile unsigned int*)(0x42920100UL))) +#define bM4_WDT_RR_RF1 (*((volatile unsigned int*)(0x42920104UL))) +#define bM4_WDT_RR_RF2 (*((volatile unsigned int*)(0x42920108UL))) +#define bM4_WDT_RR_RF3 (*((volatile unsigned int*)(0x4292010CUL))) +#define bM4_WDT_RR_RF4 (*((volatile unsigned int*)(0x42920110UL))) +#define bM4_WDT_RR_RF5 (*((volatile unsigned int*)(0x42920114UL))) +#define bM4_WDT_RR_RF6 (*((volatile unsigned int*)(0x42920118UL))) +#define bM4_WDT_RR_RF7 (*((volatile unsigned int*)(0x4292011CUL))) +#define bM4_WDT_RR_RF8 (*((volatile unsigned int*)(0x42920120UL))) +#define bM4_WDT_RR_RF9 (*((volatile unsigned int*)(0x42920124UL))) +#define bM4_WDT_RR_RF10 (*((volatile unsigned int*)(0x42920128UL))) +#define bM4_WDT_RR_RF11 (*((volatile unsigned int*)(0x4292012CUL))) +#define bM4_WDT_RR_RF12 (*((volatile unsigned int*)(0x42920130UL))) +#define bM4_WDT_RR_RF13 (*((volatile unsigned int*)(0x42920134UL))) +#define bM4_WDT_RR_RF14 (*((volatile unsigned int*)(0x42920138UL))) +#define bM4_WDT_RR_RF15 (*((volatile unsigned int*)(0x4292013CUL))) +#define bM4_WKTM_CR_WKTMCMP0 (*((volatile unsigned int*)(0x42988000UL))) +#define bM4_WKTM_CR_WKTMCMP1 (*((volatile unsigned int*)(0x42988004UL))) +#define bM4_WKTM_CR_WKTMCMP2 (*((volatile unsigned int*)(0x42988008UL))) +#define bM4_WKTM_CR_WKTMCMP3 (*((volatile unsigned int*)(0x4298800CUL))) +#define bM4_WKTM_CR_WKTMCMP4 (*((volatile unsigned int*)(0x42988010UL))) +#define bM4_WKTM_CR_WKTMCMP5 (*((volatile unsigned int*)(0x42988014UL))) +#define bM4_WKTM_CR_WKTMCMP6 (*((volatile unsigned int*)(0x42988018UL))) +#define bM4_WKTM_CR_WKTMCMP7 (*((volatile unsigned int*)(0x4298801CUL))) +#define bM4_WKTM_CR_WKTMCMP8 (*((volatile unsigned int*)(0x42988020UL))) +#define bM4_WKTM_CR_WKTMCMP9 (*((volatile unsigned int*)(0x42988024UL))) +#define bM4_WKTM_CR_WKTMCMP10 (*((volatile unsigned int*)(0x42988028UL))) +#define bM4_WKTM_CR_WKTMCMP11 (*((volatile unsigned int*)(0x4298802CUL))) +#define bM4_WKTM_CR_WKOVF (*((volatile unsigned int*)(0x42988030UL))) +#define bM4_WKTM_CR_WKCKS0 (*((volatile unsigned int*)(0x42988034UL))) +#define bM4_WKTM_CR_WKCKS1 (*((volatile unsigned int*)(0x42988038UL))) +#define bM4_WKTM_CR_WKTCE (*((volatile unsigned int*)(0x4298803CUL))) + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F460_H__ */ + diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/system_hc32f460.h b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/system_hc32f460.h new file mode 100644 index 0000000000..624519f9ae --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Include/system_hc32f460.h @@ -0,0 +1,105 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file system_hc32f460.h + ** + ** A detailed description is available at + ** @link Hc32f460SystemGroup Hc32f460System description @endlink + ** + ** - 2018-10-15 CDT First version. + ** + ******************************************************************************/ +#ifndef __SYSTEM_HC32F460_H__ +#define __SYSTEM_HC32F460_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + ******************************************************************************* + ** \defgroup Hc32f460SystemGroup HC32F460 System Configure + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + +#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL))) + +#if !defined (HRC_16MHz_VALUE) + #define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */ +#endif + +#if !defined (HRC_20MHz_VALUE) + #define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */ +#endif + +#if !defined (MRC_VALUE) +#define MRC_VALUE ((uint32_t)8000000) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE ((uint32_t)32768) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE ((uint32_t)8000000) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE ((uint32_t)32768) /*!< External low speed OSC freq. */ +#endif + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +extern uint32_t HRC_VALUE; // HRC Clock Frequency (Core Clock) +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit(void); // Initialize the system +extern void SystemCoreClockUpdate(void); // Update SystemCoreClock variable + +//@} // Hc32f460SystemGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F460_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/HDSC_HC32F460PETB.SFR b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/HDSC_HC32F460PETB.SFR new file mode 100644 index 0000000000..2f6262eef9 Binary files /dev/null and b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/HDSC_HC32F460PETB.SFR differ diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s new file mode 100644 index 0000000000..40ebda2b8a --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s @@ -0,0 +1,621 @@ +;/****************************************************************************** +; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by HDSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2018-10-13 */ +;/* Target-mcu HC32F460 */ +;/*****************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler ; IRQ000_Handler + DCD IRQ001_Handler ; IRQ001_Handler + DCD IRQ002_Handler ; IRQ002_Handler + DCD IRQ003_Handler ; IRQ003_Handler + DCD IRQ004_Handler ; IRQ004_Handler + DCD IRQ005_Handler ; IRQ005_Handler + DCD IRQ006_Handler ; IRQ006_Handler + DCD IRQ007_Handler ; IRQ007_Handler + DCD IRQ008_Handler ; IRQ008_Handler + DCD IRQ009_Handler ; IRQ009_Handler + DCD IRQ010_Handler ; IRQ010_Handler + DCD IRQ011_Handler ; IRQ011_Handler + DCD IRQ012_Handler ; IRQ012_Handler + DCD IRQ013_Handler ; IRQ013_Handler + DCD IRQ014_Handler ; IRQ014_Handler + DCD IRQ015_Handler ; IRQ015_Handler + DCD IRQ016_Handler ; IRQ016_Handler + DCD IRQ017_Handler ; IRQ017_Handler + DCD IRQ018_Handler ; IRQ018_Handler + DCD IRQ019_Handler ; IRQ019_Handler + DCD IRQ020_Handler ; IRQ020_Handler + DCD IRQ021_Handler ; IRQ021_Handler + DCD IRQ022_Handler ; IRQ022_Handler + DCD IRQ023_Handler ; IRQ023_Handler + DCD IRQ024_Handler ; IRQ024_Handler + DCD IRQ025_Handler ; IRQ025_Handler + DCD IRQ026_Handler ; IRQ026_Handler + DCD IRQ027_Handler ; IRQ027_Handler + DCD IRQ028_Handler ; IRQ028_Handler + DCD IRQ029_Handler ; IRQ029_Handler + DCD IRQ030_Handler ; IRQ030_Handler + DCD IRQ031_Handler ; IRQ031_Handler + DCD IRQ032_Handler ; IRQ032_Handler + DCD IRQ033_Handler ; IRQ033_Handler + DCD IRQ034_Handler ; IRQ034_Handler + DCD IRQ035_Handler ; IRQ035_Handler + DCD IRQ036_Handler ; IRQ036_Handler + DCD IRQ037_Handler ; IRQ037_Handler + DCD IRQ038_Handler ; IRQ038_Handler + DCD IRQ039_Handler ; IRQ039_Handler + DCD IRQ040_Handler ; IRQ040_Handler + DCD IRQ041_Handler ; IRQ041_Handler + DCD IRQ042_Handler ; IRQ042_Handler + DCD IRQ043_Handler ; IRQ043_Handler + DCD IRQ044_Handler ; IRQ044_Handler + DCD IRQ045_Handler ; IRQ045_Handler + DCD IRQ046_Handler ; IRQ046_Handler + DCD IRQ047_Handler ; IRQ047_Handler + DCD IRQ048_Handler ; IRQ048_Handler + DCD IRQ049_Handler ; IRQ049_Handler + DCD IRQ050_Handler ; IRQ050_Handler + DCD IRQ051_Handler ; IRQ051_Handler + DCD IRQ052_Handler ; IRQ052_Handler + DCD IRQ053_Handler ; IRQ053_Handler + DCD IRQ054_Handler ; IRQ054_Handler + DCD IRQ055_Handler ; IRQ055_Handler + DCD IRQ056_Handler ; IRQ056_Handler + DCD IRQ057_Handler ; IRQ057_Handler + DCD IRQ058_Handler ; IRQ058_Handler + DCD IRQ059_Handler ; IRQ059_Handler + DCD IRQ060_Handler ; IRQ060_Handler + DCD IRQ061_Handler ; IRQ061_Handler + DCD IRQ062_Handler ; IRQ062_Handler + DCD IRQ063_Handler ; IRQ063_Handler + DCD IRQ064_Handler ; IRQ064_Handler + DCD IRQ065_Handler ; IRQ065_Handler + DCD IRQ066_Handler ; IRQ066_Handler + DCD IRQ067_Handler ; IRQ067_Handler + DCD IRQ068_Handler ; IRQ068_Handler + DCD IRQ069_Handler ; IRQ069_Handler + DCD IRQ070_Handler ; IRQ070_Handler + DCD IRQ071_Handler ; IRQ071_Handler + DCD IRQ072_Handler ; IRQ072_Handler + DCD IRQ073_Handler ; IRQ073_Handler + DCD IRQ074_Handler ; IRQ074_Handler + DCD IRQ075_Handler ; IRQ075_Handler + DCD IRQ076_Handler ; IRQ076_Handler + DCD IRQ077_Handler ; IRQ077_Handler + DCD IRQ078_Handler ; IRQ078_Handler + DCD IRQ079_Handler ; IRQ079_Handler + DCD IRQ080_Handler ; IRQ080_Handler + DCD IRQ081_Handler ; IRQ081_Handler + DCD IRQ082_Handler ; IRQ082_Handler + DCD IRQ083_Handler ; IRQ083_Handler + DCD IRQ084_Handler ; IRQ084_Handler + DCD IRQ085_Handler ; IRQ085_Handler + DCD IRQ086_Handler ; IRQ086_Handler + DCD IRQ087_Handler ; IRQ087_Handler + DCD IRQ088_Handler ; IRQ088_Handler + DCD IRQ089_Handler ; IRQ089_Handler + DCD IRQ090_Handler ; IRQ090_Handler + DCD IRQ091_Handler ; IRQ091_Handler + DCD IRQ092_Handler ; IRQ092_Handler + DCD IRQ093_Handler ; IRQ093_Handler + DCD IRQ094_Handler ; IRQ094_Handler + DCD IRQ095_Handler ; IRQ095_Handler + DCD IRQ096_Handler ; IRQ096_Handler + DCD IRQ097_Handler ; IRQ097_Handler + DCD IRQ098_Handler ; IRQ098_Handler + DCD IRQ099_Handler ; IRQ099_Handler + DCD IRQ100_Handler ; IRQ100_Handler + DCD IRQ101_Handler ; IRQ101_Handler + DCD IRQ102_Handler ; IRQ102_Handler + DCD IRQ103_Handler ; IRQ103_Handler + DCD IRQ104_Handler ; IRQ104_Handler + DCD IRQ105_Handler ; IRQ105_Handler + DCD IRQ106_Handler ; IRQ106_Handler + DCD IRQ107_Handler ; IRQ107_Handler + DCD IRQ108_Handler ; IRQ108_Handler + DCD IRQ109_Handler ; IRQ109_Handler + DCD IRQ110_Handler ; IRQ110_Handler + DCD IRQ111_Handler ; IRQ111_Handler + DCD IRQ112_Handler ; IRQ112_Handler + DCD IRQ113_Handler ; IRQ113_Handler + DCD IRQ114_Handler ; IRQ114_Handler + DCD IRQ115_Handler ; IRQ115_Handler + DCD IRQ116_Handler ; IRQ116_Handler + DCD IRQ117_Handler ; IRQ117_Handler + DCD IRQ118_Handler ; IRQ118_Handler + DCD IRQ119_Handler ; IRQ119_Handler + DCD IRQ120_Handler ; IRQ120_Handler + DCD IRQ121_Handler ; IRQ121_Handler + DCD IRQ122_Handler ; IRQ122_Handler + DCD IRQ123_Handler ; IRQ123_Handler + DCD IRQ124_Handler ; IRQ124_Handler + DCD IRQ125_Handler ; IRQ125_Handler + DCD IRQ126_Handler ; IRQ126_Handler + DCD IRQ127_Handler ; IRQ127_Handler + DCD IRQ128_Handler ; IRQ128_Handler + DCD IRQ129_Handler ; IRQ129_Handler + DCD IRQ130_Handler ; IRQ130_Handler + DCD IRQ131_Handler ; IRQ131_Handler + DCD IRQ132_Handler ; IRQ132_Handler + DCD IRQ133_Handler ; IRQ133_Handler + DCD IRQ134_Handler ; IRQ134_Handler + DCD IRQ135_Handler ; IRQ135_Handler + DCD IRQ136_Handler ; IRQ136_Handler + DCD IRQ137_Handler ; IRQ137_Handler + DCD IRQ138_Handler ; IRQ138_Handler + DCD IRQ139_Handler ; IRQ139_Handler + DCD IRQ140_Handler ; IRQ140_Handler + DCD IRQ141_Handler ; IRQ141_Handler + DCD IRQ142_Handler ; IRQ142_Handler + DCD IRQ143_Handler ; IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +SET_SRAM3_WAIT + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S new file mode 100644 index 0000000000..b27e3bc757 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S @@ -0,0 +1,538 @@ +/* +;******************************************************************************* +; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by HDSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +*/ +/*****************************************************************************/ +/* Startup for GCC */ +/* Version V1.0 */ +/* Date 2019-03-13 */ +/* Target-mcu HC32F460 */ +/*****************************************************************************/ + +/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + .syntax unified + .arch armv7e-m + .cpu cortex-m4 + .fpu softvfp + .thumb + +/* +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Stack_Size, 0x00000400 + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Heap_Size, 0x00000C00 + + .if Heap_Size != 0 /* Heap is provided */ + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + .endif + +/* +; Interrupt vector table start. +*/ + .section .vectors, "a", %progbits + .align 2 + .type __Vectors, %object + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long IRQ000_Handler + .long IRQ001_Handler + .long IRQ002_Handler + .long IRQ003_Handler + .long IRQ004_Handler + .long IRQ005_Handler + .long IRQ006_Handler + .long IRQ007_Handler + .long IRQ008_Handler + .long IRQ009_Handler + .long IRQ010_Handler + .long IRQ011_Handler + .long IRQ012_Handler + .long IRQ013_Handler + .long IRQ014_Handler + .long IRQ015_Handler + .long IRQ016_Handler + .long IRQ017_Handler + .long IRQ018_Handler + .long IRQ019_Handler + .long IRQ020_Handler + .long IRQ021_Handler + .long IRQ022_Handler + .long IRQ023_Handler + .long IRQ024_Handler + .long IRQ025_Handler + .long IRQ026_Handler + .long IRQ027_Handler + .long IRQ028_Handler + .long IRQ029_Handler + .long IRQ030_Handler + .long IRQ031_Handler + .long IRQ032_Handler + .long IRQ033_Handler + .long IRQ034_Handler + .long IRQ035_Handler + .long IRQ036_Handler + .long IRQ037_Handler + .long IRQ038_Handler + .long IRQ039_Handler + .long IRQ040_Handler + .long IRQ041_Handler + .long IRQ042_Handler + .long IRQ043_Handler + .long IRQ044_Handler + .long IRQ045_Handler + .long IRQ046_Handler + .long IRQ047_Handler + .long IRQ048_Handler + .long IRQ049_Handler + .long IRQ050_Handler + .long IRQ051_Handler + .long IRQ052_Handler + .long IRQ053_Handler + .long IRQ054_Handler + .long IRQ055_Handler + .long IRQ056_Handler + .long IRQ057_Handler + .long IRQ058_Handler + .long IRQ059_Handler + .long IRQ060_Handler + .long IRQ061_Handler + .long IRQ062_Handler + .long IRQ063_Handler + .long IRQ064_Handler + .long IRQ065_Handler + .long IRQ066_Handler + .long IRQ067_Handler + .long IRQ068_Handler + .long IRQ069_Handler + .long IRQ070_Handler + .long IRQ071_Handler + .long IRQ072_Handler + .long IRQ073_Handler + .long IRQ074_Handler + .long IRQ075_Handler + .long IRQ076_Handler + .long IRQ077_Handler + .long IRQ078_Handler + .long IRQ079_Handler + .long IRQ080_Handler + .long IRQ081_Handler + .long IRQ082_Handler + .long IRQ083_Handler + .long IRQ084_Handler + .long IRQ085_Handler + .long IRQ086_Handler + .long IRQ087_Handler + .long IRQ088_Handler + .long IRQ089_Handler + .long IRQ090_Handler + .long IRQ091_Handler + .long IRQ092_Handler + .long IRQ093_Handler + .long IRQ094_Handler + .long IRQ095_Handler + .long IRQ096_Handler + .long IRQ097_Handler + .long IRQ098_Handler + .long IRQ099_Handler + .long IRQ100_Handler + .long IRQ101_Handler + .long IRQ102_Handler + .long IRQ103_Handler + .long IRQ104_Handler + .long IRQ105_Handler + .long IRQ106_Handler + .long IRQ107_Handler + .long IRQ108_Handler + .long IRQ109_Handler + .long IRQ110_Handler + .long IRQ111_Handler + .long IRQ112_Handler + .long IRQ113_Handler + .long IRQ114_Handler + .long IRQ115_Handler + .long IRQ116_Handler + .long IRQ117_Handler + .long IRQ118_Handler + .long IRQ119_Handler + .long IRQ120_Handler + .long IRQ121_Handler + .long IRQ122_Handler + .long IRQ123_Handler + .long IRQ124_Handler + .long IRQ125_Handler + .long IRQ126_Handler + .long IRQ127_Handler + .long IRQ128_Handler + .long IRQ129_Handler + .long IRQ130_Handler + .long IRQ131_Handler + .long IRQ132_Handler + .long IRQ133_Handler + .long IRQ134_Handler + .long IRQ135_Handler + .long IRQ136_Handler + .long IRQ137_Handler + .long IRQ138_Handler + .long IRQ139_Handler + .long IRQ140_Handler + .long IRQ141_Handler + .long IRQ142_Handler + .long IRQ143_Handler + + .space (80 * 4) /* Interrupts 144 .. 224 are left out */ +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors +/* +; Interrupt vector table end. +*/ + +/* +; Reset handler start. +*/ + .section .text.Reset_Handler + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + .globl Reset_Handler +Reset_Handler: + /* Set stack top pointer. */ + ldr sp, =__StackTop +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + /* Copy data from read only memory to RAM. */ +CopyData: + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ +CopyLoop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop + +CopyData1: + ldr r1, =__etext_ret_ram + ldr r2, =__data_start_ret_ram__ + ldr r3, =__data_end_ret_ram__ +CopyLoop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop1 + +/* This part of work usually is done in C library startup code. + * Otherwise, define this macro to enable it in this startup. + * + * There are two schemes too. + * One can clear multiple BSS sections. Another can only clear one section. + * The former is more size expensive than the latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + /* Clear BSS section. */ +ClearBss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +ClearLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop + +ClearBss1: + ldr r1, =__bss_start_ret_ram__ + ldr r2, =__bss_end_ret_ram__ + + movs r0, 0 +ClearLoop1: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop1 + +SetSRAM3Wait: + ldr r0, =0x40050804 + mov r1, #0x77 + str r1, [r0] + + ldr r0, =0x4005080C + mov r1, #0x77 + str r1, [r0] + + ldr r0, =0x40050800 + mov r1, #0x1100 + str r1, [r0] + + ldr r0, =0x40050804 + mov r1, #0x76 + str r1, [r0] + + ldr r0, =0x4005080C + mov r1, #0x76 + str r1, [r0] + + /* Call the clock system initialization function. */ + bl SystemInit + /* Call the application's entry point. */ + bl main + bx lr + .size Reset_Handler, . - Reset_Handler +/* +; Reset handler end. +*/ + +/* +; Default handler start. +*/ + .section .text.Default_Handler, "ax", %progbits + .align 2 +Default_Handler: + b . + .size Default_Handler, . - Default_Handler +/* +; Default handler end. +*/ + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler IRQ000_Handler + Set_Default_Handler IRQ001_Handler + Set_Default_Handler IRQ002_Handler + Set_Default_Handler IRQ003_Handler + Set_Default_Handler IRQ004_Handler + Set_Default_Handler IRQ005_Handler + Set_Default_Handler IRQ006_Handler + Set_Default_Handler IRQ007_Handler + Set_Default_Handler IRQ008_Handler + Set_Default_Handler IRQ009_Handler + Set_Default_Handler IRQ010_Handler + Set_Default_Handler IRQ011_Handler + Set_Default_Handler IRQ012_Handler + Set_Default_Handler IRQ013_Handler + Set_Default_Handler IRQ014_Handler + Set_Default_Handler IRQ015_Handler + Set_Default_Handler IRQ016_Handler + Set_Default_Handler IRQ017_Handler + Set_Default_Handler IRQ018_Handler + Set_Default_Handler IRQ019_Handler + Set_Default_Handler IRQ020_Handler + Set_Default_Handler IRQ021_Handler + Set_Default_Handler IRQ022_Handler + Set_Default_Handler IRQ023_Handler + Set_Default_Handler IRQ024_Handler + Set_Default_Handler IRQ025_Handler + Set_Default_Handler IRQ026_Handler + Set_Default_Handler IRQ027_Handler + Set_Default_Handler IRQ028_Handler + Set_Default_Handler IRQ029_Handler + Set_Default_Handler IRQ030_Handler + Set_Default_Handler IRQ031_Handler + Set_Default_Handler IRQ032_Handler + Set_Default_Handler IRQ033_Handler + Set_Default_Handler IRQ034_Handler + Set_Default_Handler IRQ035_Handler + Set_Default_Handler IRQ036_Handler + Set_Default_Handler IRQ037_Handler + Set_Default_Handler IRQ038_Handler + Set_Default_Handler IRQ039_Handler + Set_Default_Handler IRQ040_Handler + Set_Default_Handler IRQ041_Handler + Set_Default_Handler IRQ042_Handler + Set_Default_Handler IRQ043_Handler + Set_Default_Handler IRQ044_Handler + Set_Default_Handler IRQ045_Handler + Set_Default_Handler IRQ046_Handler + Set_Default_Handler IRQ047_Handler + Set_Default_Handler IRQ048_Handler + Set_Default_Handler IRQ049_Handler + Set_Default_Handler IRQ050_Handler + Set_Default_Handler IRQ051_Handler + Set_Default_Handler IRQ052_Handler + Set_Default_Handler IRQ053_Handler + Set_Default_Handler IRQ054_Handler + Set_Default_Handler IRQ055_Handler + Set_Default_Handler IRQ056_Handler + Set_Default_Handler IRQ057_Handler + Set_Default_Handler IRQ058_Handler + Set_Default_Handler IRQ059_Handler + Set_Default_Handler IRQ060_Handler + Set_Default_Handler IRQ061_Handler + Set_Default_Handler IRQ062_Handler + Set_Default_Handler IRQ063_Handler + Set_Default_Handler IRQ064_Handler + Set_Default_Handler IRQ065_Handler + Set_Default_Handler IRQ066_Handler + Set_Default_Handler IRQ067_Handler + Set_Default_Handler IRQ068_Handler + Set_Default_Handler IRQ069_Handler + Set_Default_Handler IRQ070_Handler + Set_Default_Handler IRQ071_Handler + Set_Default_Handler IRQ072_Handler + Set_Default_Handler IRQ073_Handler + Set_Default_Handler IRQ074_Handler + Set_Default_Handler IRQ075_Handler + Set_Default_Handler IRQ076_Handler + Set_Default_Handler IRQ077_Handler + Set_Default_Handler IRQ078_Handler + Set_Default_Handler IRQ079_Handler + Set_Default_Handler IRQ080_Handler + Set_Default_Handler IRQ081_Handler + Set_Default_Handler IRQ082_Handler + Set_Default_Handler IRQ083_Handler + Set_Default_Handler IRQ084_Handler + Set_Default_Handler IRQ085_Handler + Set_Default_Handler IRQ086_Handler + Set_Default_Handler IRQ087_Handler + Set_Default_Handler IRQ088_Handler + Set_Default_Handler IRQ089_Handler + Set_Default_Handler IRQ090_Handler + Set_Default_Handler IRQ091_Handler + Set_Default_Handler IRQ092_Handler + Set_Default_Handler IRQ093_Handler + Set_Default_Handler IRQ094_Handler + Set_Default_Handler IRQ095_Handler + Set_Default_Handler IRQ096_Handler + Set_Default_Handler IRQ097_Handler + Set_Default_Handler IRQ098_Handler + Set_Default_Handler IRQ099_Handler + Set_Default_Handler IRQ100_Handler + Set_Default_Handler IRQ101_Handler + Set_Default_Handler IRQ102_Handler + Set_Default_Handler IRQ103_Handler + Set_Default_Handler IRQ104_Handler + Set_Default_Handler IRQ105_Handler + Set_Default_Handler IRQ106_Handler + Set_Default_Handler IRQ107_Handler + Set_Default_Handler IRQ108_Handler + Set_Default_Handler IRQ109_Handler + Set_Default_Handler IRQ110_Handler + Set_Default_Handler IRQ111_Handler + Set_Default_Handler IRQ112_Handler + Set_Default_Handler IRQ113_Handler + Set_Default_Handler IRQ114_Handler + Set_Default_Handler IRQ115_Handler + Set_Default_Handler IRQ116_Handler + Set_Default_Handler IRQ117_Handler + Set_Default_Handler IRQ118_Handler + Set_Default_Handler IRQ119_Handler + Set_Default_Handler IRQ120_Handler + Set_Default_Handler IRQ121_Handler + Set_Default_Handler IRQ122_Handler + Set_Default_Handler IRQ123_Handler + Set_Default_Handler IRQ124_Handler + Set_Default_Handler IRQ125_Handler + Set_Default_Handler IRQ126_Handler + Set_Default_Handler IRQ127_Handler + Set_Default_Handler IRQ128_Handler + Set_Default_Handler IRQ129_Handler + Set_Default_Handler IRQ130_Handler + Set_Default_Handler IRQ131_Handler + Set_Default_Handler IRQ132_Handler + Set_Default_Handler IRQ133_Handler + Set_Default_Handler IRQ134_Handler + Set_Default_Handler IRQ135_Handler + Set_Default_Handler IRQ136_Handler + Set_Default_Handler IRQ137_Handler + Set_Default_Handler IRQ138_Handler + Set_Default_Handler IRQ139_Handler + Set_Default_Handler IRQ140_Handler + Set_Default_Handler IRQ141_Handler + Set_Default_Handler IRQ142_Handler + Set_Default_Handler IRQ143_Handler + + .end diff --git a/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c new file mode 100644 index 0000000000..cdf68c023b --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c @@ -0,0 +1,117 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file system_hc32f460.c + ** + ** A detailed description is available at + ** @link Hc32f460SystemGroup Hc32f460System description @endlink + ** + ** - 2018-10-15 CDT First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +/** + ******************************************************************************* + ** \addtogroup Hc32f460SystemGroup + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +//@{ + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t HRC_VALUE = HRC_16MHz_VALUE; +uint32_t SystemCoreClock = MRC_VALUE; + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param None + ** \return None + ******************************************************************************/ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); +} + +void SystemCoreClockUpdate(void) // Update SystemCoreClock variable +{ + uint8_t tmp = 0u; + uint32_t plln = 19u, pllp = 1u, pllm = 0u, pllsource = 0u; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + /* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */ + /* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */ + if (1UL == (HRC_FREQ_MON() & 1UL)) + { + HRC_VALUE = HRC_16MHz_VALUE; + } + else + { + HRC_VALUE = HRC_20MHz_VALUE; + } + + tmp = M4_SYSREG->CMU_CKSWR_f.CKSW; + switch (tmp) + { + case 0x00: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05: /* use MPLL */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + /* use exteranl high speed OSC as PLL source */ + if (0ul == pllsource) + { + SystemCoreClock = (XTAL_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul); + } + /* use interanl high RC as PLL source */ + else if (1ul == pllsource) + { + SystemCoreClock = (HRC_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul); + } + else + { + /* Reserved */ + } + break; + } +} +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..1c9674bc5b --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..8224cdb37b --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..d6b28d430a --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..b111f6248c --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..6580cce3ce --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_version.h b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..f2e2746626 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_armv81mml.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000000..dfcdc4d12d --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000..344dca5148 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000..5ddb8aeda7 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..773e6edf59 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..4c02ee9ad9 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm1.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000000..83b8fc6a0d --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm23.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000..c355f60379 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm3.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm33.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000..20bf69b12f --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm35p.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000000..d811b2a315 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm4.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..12c023b801 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_cm7.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..71e1459f5d --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_sc000.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..cf92577b63 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/core_sc300.h b/bsp/hc32f460/Libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..40f3af81be --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000..4592d60879 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000..e2b7c28497 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32f460/Libraries/CMSIS/Include/tz_context.h b/bsp/hc32f460/Libraries/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000..facc2c9a47 --- /dev/null +++ b/bsp/hc32f460/Libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_adc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_adc.h new file mode 100644 index 0000000000..edaf0b9e85 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_adc.h @@ -0,0 +1,509 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_adc.h + ** + ** A detailed description is available at + ** @link AdcGroup Adc description @endlink + ** + ** - 2018-11-30 CDT First version for Device Driver Library of Adc. + ** + ******************************************************************************/ +#ifndef __HC32F460_ADC_H__ +#define __HC32F460_ADC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_ADC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup AdcGroup Analog-to-Digital Converter(ADC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief ADC average count. + ** + ******************************************************************************/ +typedef enum en_adc_avcnt +{ + AdcAvcnt_2 = 0x0, ///< Average after 2 conversions. + AdcAvcnt_4 = 0x1, ///< Average after 4 conversions. + AdcAvcnt_8 = 0x2, ///< Average after 8 conversions. + AdcAvcnt_16 = 0x3, ///< Average after 16 conversions. + AdcAvcnt_32 = 0x4, ///< Average after 32 conversions. + AdcAvcnt_64 = 0x5, ///< Average after 64 conversions. + AdcAvcnt_128 = 0x6, ///< Average after 128 conversions. + AdcAvcnt_256 = 0x7, ///< Average after 256 conversions. +} en_adc_avcnt_t; + +/** + ******************************************************************************* + ** \brief ADC data alignment + ** + ******************************************************************************/ +typedef enum en_adc_data_align +{ + AdcDataAlign_Right = 0x0, ///< Data right alignment. + AdcDataAlign_Left = 0x1, ///< Data left alignment. +} en_adc_data_align_t; + +/** + ******************************************************************************* + ** \brief Automatically clear data registers after reading data. + ** The auto clear function is mainly used to detect whether the data register + ** is updated. + ** + ******************************************************************************/ +typedef enum en_adc_clren +{ + AdcClren_Disable = 0x0, ///< Automatic clear function disable. + AdcClren_Enable = 0x1, ///< Automatic clear function enable. +} en_adc_clren_t; + +/** + ******************************************************************************* + ** \brief ADC resolution. + ** + ******************************************************************************/ +typedef enum en_adc_resolution +{ + AdcResolution_12Bit = 0x0, ///< Resolution is 12 bit. + AdcResolution_10Bit = 0x1, ///< Resolution is 10 bit. + AdcResolution_8Bit = 0x2, ///< Resolution is 8 bit. +} en_adc_resolution_t; + +/** + ******************************************************************************* + ** \brief ADC scan mode. + ** + ******************************************************************************/ +typedef enum en_adc_scan_mode +{ + AdcMode_SAOnce = 0x0, ///< Sequence A works once. + AdcMode_SAContinuous = 0x1, ///< Sequence A works always. + AdcMode_SAOnceSBOnce = 0x2, ///< Sequence A and sequence B work once. + AdcMode_SAContinuousSBOnce = 0x3, ///< Sequence A works always, sequence works once. +} en_adc_scan_mode_t; + +/** + ******************************************************************************* + ** \brief ADC sequence A restart position. + ** + ******************************************************************************/ +typedef enum en_adc_rschsel +{ + AdcRschsel_Continue = 0x0, ///< After sequence A is interrupted by sequence B, + ///< sequence A continues to scan from the interrupt + ///< when it restarts. + + AdcRschsel_Restart = 0x1, ///< After sequence A is interrupted by sequence B, + ///< sequence A restarts scanning from the first channel + ///< when it restarts. +} en_adc_rschsel_t; + +/** + ******************************************************************************* + ** \brief ADC external or internal trigger source enable/disable . + ** + ******************************************************************************/ +typedef enum en_adc_trgen +{ + AdcTrgen_Disable = 0x0, ///< External or internal trigger source disable. + AdcTrgen_Enable = 0x1, ///< External or internal trigger source enable. +} en_adc_trgen_t; + +/** + ******************************************************************************* + ** \brief ADC sequence trigger source selection. + ** + ******************************************************************************/ +typedef enum en_adc_trgsel +{ + AdcTrgsel_ADTRGX = 0x0, ///< X = 1(use ADC1) / 2(use ADC2), same as below. + AdcTrgsel_TRGX0 = 0x1, ///< Pin IN_TRG10 / IN_TRG20. + AdcTrgsel_TRGX1 = 0x2, ///< Pin IN_TRG11 / IN_TRG21. + AdcTrgsel_TRGX0_TRGX1 = 0x3, ///< Pin IN_TRG10 + IN_TRG11 / IN_TRG20 + IN_TRG21. +} en_adc_trgsel_t; + +/** + ******************************************************************************* + ** \brief Sequence A/B conversion completion interrupt enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_eocien +{ + AdcEocien_Disable = 0x0, ///< Conversion completion interrupt disable. + AdcEocien_Enable = 0x1, ///< Conversion completion interrupt enable. +} en_adc_eocien_t; + +/** + ******************************************************************************* + ** \brief ADC sync mode. + ** + ******************************************************************************/ +typedef enum en_adc_sync_mode +{ + AdcSync_SingleSerial = 0x0u, ///< Single: ADC1 and ADC2 only sample and convert once after triggering. + ///< Serial: ADC2 start after ADC1 N PCLK4 cycles. + AdcSync_SingleParallel = 0x2u, ///< Parallel: ADC1 and ADC2 start at the same time. + AdcSync_ContinuousSerial = 0x4u, ///< Continuous: ADC1 and ADC2 continuously sample and convert after triggering. + AdcSync_ContinuousParallel = 0x6u, +} en_adc_sync_mode_t; + +/** + ******************************************************************************* + ** \brief ADC sync enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_syncen +{ + AdcSync_Disable = 0x0, ///< Disable sync mode. + AdcSync_Enable = 0x1, ///< Enable sync mode. +} en_adc_syncen_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog interrupt enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_awdien +{ + AdcAwdInt_Disable = 0x0, ///< Disable AWD interrupt. + AdcAwdInt_Enable = 0x1, ///< Enable AWD interrupt. +} en_adc_awdien_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog interrupt event sequence selection. + ** + ******************************************************************************/ +typedef enum en_adc_awdss +{ + AdcAwdSel_SA_SB = 0x0, ///< Sequence A and B output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SA = 0x1, ///< Sequence A output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SB = 0x2, ///< Sequence B output interrupt event -- ADC_SEQCMP. + AdcAwdSel_SB_SA = 0x3, ///< Same as AdcAwdSel_SA_SB. +} en_adc_awdss_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog comparison mode selection. + ** + ******************************************************************************/ +typedef enum en_adc_awdmd +{ + AdcAwdCmpMode_0 = 0x0, ///< Upper limit is AWDDR0, lower limit is AWDDR1. + ///< If AWDDR0 > result or result > AWDDR1, + ///< the interrupt will be occur. + + AdcAwdCmpMode_1 = 0x1, ///< The range is [AWDDR0, AWDDR1]. + ///< If AWDDR0 <= result <= AWDDR1, the interrupt will be occur. +} en_adc_awdmd_t; + +/** + ******************************************************************************* + ** \brief Analog watchdog enable/disable. + ** + ******************************************************************************/ +typedef enum en_adc_awden +{ + AdcAwd_Disable = 0x0, ///< Disable AWD. + AdcAwd_Enable = 0x1, ///< Enable AWD. +} en_adc_awden_t; + +/** + ******************************************************************************* + ** \brief PGA control. + ** + ******************************************************************************/ +typedef enum en_adc_pga_ctl +{ + AdcPgaCtl_Invalid = 0x0, ///< Amplifier is invalid. + AdcPgaCtl_Amplify = 0xE, ///< Amplifier effective. +} en_adc_pga_ctl_t; + +/** + ******************************************************************************* + ** \brief The amplification factor of the amplifier is as follows. + ** + ******************************************************************************/ +typedef enum en_adc_pga_factor +{ + AdcPgaFactor_2 = 0x0, ///< PGA magnification 2. + AdcPgaFactor_2P133 = 0x1, ///< PGA magnification 2.133. + AdcPgaFactor_2P286 = 0x2, ///< PGA magnification 2.286. + AdcPgaFactor_2P667 = 0x3, ///< PGA magnification 2.667. + AdcPgaFactor_2P909 = 0x4, ///< PGA magnification 2.909. + AdcPgaFactor_3P2 = 0x5, ///< PGA magnification 3.2. + AdcPgaFactor_3P556 = 0x6, ///< PGA magnification 3.556. + AdcPgaFactor_4 = 0x7, ///< PGA magnification 4. + AdcPgaFactor_4P571 = 0x8, ///< PGA magnification 4.571. + AdcPgaFactor_5P333 = 0x9, ///< PGA magnification 5.333. + AdcPgaFactor_6P4 = 0xA, ///< PGA magnification 6.4. + AdcPgaFactor_8 = 0xB, ///< PGA magnification 8. + AdcPgaFactor_10P667 = 0xC, ///< PGA magnification 10.667. + AdcPgaFactor_16 = 0xD, ///< PGA magnification 16. + AdcPgaFactor_32 = 0xE, ///< PGA magnification 32. +} en_adc_pga_factor_t; + +/** + ******************************************************************************* + ** \brief Negative phase input selection + ** + ******************************************************************************/ +typedef enum en_adc_pga_negative +{ + AdcPgaNegative_PGAVSS = 0x0, ///< Use external port PGAVSS as PGA negative input. + AdcPgaNegative_VSSA = 0x1, ///< Use internal analog ground VSSA as PGA negative input. +} en_adc_pga_negative_t; + +/** + ******************************************************************************* + ** \brief ADC common trigger source select + ** + ******************************************************************************/ +typedef enum en_adc_com_trigger +{ + AdcComTrigger_1 = 0x1, ///< Select common trigger 1. + AdcComTrigger_2 = 0x2, ///< Select common trigger 2. + AdcComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_adc_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Structure definition of ADC + ** + ******************************************************************************/ +typedef struct stc_adc_ch_cfg +{ + uint32_t u32Channel; ///< ADC channels mask. + uint8_t u8Sequence; ///< The sequence which the channel(s) belong to. + uint8_t *pu8SampTime; ///< Pointer to sampling time. +} stc_adc_ch_cfg_t; + +typedef struct stc_adc_awd_cfg +{ + en_adc_awdmd_t enAwdmd; ///< Comparison mode of the values. + en_adc_awdss_t enAwdss; ///< Interrupt output select. + uint16_t u16AwdDr0; ///< Your range DR0. + uint16_t u16AwdDr1; ///< Your range DR1. +} stc_adc_awd_cfg_t; + +typedef struct stc_adc_trg_cfg +{ + uint8_t u8Sequence; ///< The sequence will be configured trigger source. + en_adc_trgsel_t enTrgSel; ///< Trigger source type. + en_event_src_t enInTrg0; ///< Internal trigger 0 source number + ///< (event number @ref en_event_src_t). + en_event_src_t enInTrg1; ///< Internal trigger 1 source number + ///< (event number @ref en_event_src_t). +} stc_adc_trg_cfg_t; + +typedef struct stc_adc_init +{ + en_adc_resolution_t enResolution; ///< ADC resolution 12bit/10bit/8bit. + en_adc_data_align_t enDataAlign; ///< ADC data alignment. + en_adc_clren_t enAutoClear; ///< Automatically clear data register. + ///< after reading data register(enable/disable). + en_adc_scan_mode_t enScanMode; ///< ADC scan mode. + en_adc_rschsel_t enRschsel; ///< Restart or continue. +} stc_adc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief ADC sequence definition. + ** + ******************************************************************************/ +/* ADC sequence definition */ +#define ADC_SEQ_A ((uint8_t)0) +#define ADC_SEQ_B ((uint8_t)1) + +/* ADC pin definition */ +#define ADC1_IN0 ((uint8_t)0) +#define ADC1_IN1 ((uint8_t)1) +#define ADC1_IN2 ((uint8_t)2) +#define ADC1_IN3 ((uint8_t)3) +#define ADC12_IN4 ((uint8_t)4) +#define ADC12_IN5 ((uint8_t)5) +#define ADC12_IN6 ((uint8_t)6) +#define ADC12_IN7 ((uint8_t)7) +#define ADC12_IN8 ((uint8_t)8) +#define ADC12_IN9 ((uint8_t)9) +#define ADC12_IN10 ((uint8_t)10) +#define ADC12_IN11 ((uint8_t)11) +#define ADC1_IN12 ((uint8_t)12) +#define ADC1_IN13 ((uint8_t)13) +#define ADC1_IN14 ((uint8_t)14) +#define ADC1_IN15 ((uint8_t)15) +#define ADC_PIN_INVALID ((uint8_t)0xFF) + +/* ADC channel index definition */ +#define ADC_CH_IDX0 (0u) +#define ADC_CH_IDX1 (1u) +#define ADC_CH_IDX2 (2u) +#define ADC_CH_IDX3 (3u) +#define ADC_CH_IDX4 (4u) +#define ADC_CH_IDX5 (5u) +#define ADC_CH_IDX6 (6u) +#define ADC_CH_IDX7 (7u) +#define ADC_CH_IDX8 (8u) +#define ADC_CH_IDX9 (9u) +#define ADC_CH_IDX10 (10u) +#define ADC_CH_IDX11 (11u) +#define ADC_CH_IDX12 (12u) +#define ADC_CH_IDX13 (13u) +#define ADC_CH_IDX14 (14u) +#define ADC_CH_IDX15 (15u) +#define ADC_CH_IDX16 (16u) + +/* ADC1 channel mask definition */ +#define ADC1_CH0 (0x1ul << 0u) ///< Default mapping pin ADC1_IN0 +#define ADC1_CH1 (0x1ul << 1u) ///< Default mapping pin ADC1_IN1 +#define ADC1_CH2 (0x1ul << 2u) ///< Default mapping pin ADC1_IN2 +#define ADC1_CH3 (0x1ul << 3u) ///< Default mapping pin ADC1_IN3 +#define ADC1_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN4 +#define ADC1_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN5 +#define ADC1_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN6 +#define ADC1_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN7 +#define ADC1_CH8 (0x1ul << 8u) ///< Default mapping pin ADC12_IN8 +#define ADC1_CH9 (0x1ul << 9u) ///< Default mapping pin ADC12_IN9 +#define ADC1_CH10 (0x1ul << 10u) ///< Default mapping pin ADC12_IN10 +#define ADC1_CH11 (0x1ul << 11u) ///< Default mapping pin ADC12_IN11 +#define ADC1_CH12 (0x1ul << 12u) ///< Default mapping pin ADC12_IN12 +#define ADC1_CH13 (0x1ul << 13u) ///< Default mapping pin ADC12_IN13 +#define ADC1_CH14 (0x1ul << 14u) ///< Default mapping pin ADC12_IN14 +#define ADC1_CH15 (0x1ul << 15u) ///< Default mapping pin ADC12_IN15 +#define ADC1_CH16 (0x1ul << 16u) +#define ADC1_CH_INTERNAL (ADC1_CH16) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC +#define ADC1_CH_ALL (0x0001FFFFul) +#define ADC1_PIN_MASK_ALL (ADC1_CH_ALL & ~ADC1_CH_INTERNAL) + +/* ADC2 channel definition */ +#define ADC2_CH0 (0x1ul << 0u) ///< Default mapping pin ADC12_IN4 +#define ADC2_CH1 (0x1ul << 1u) ///< Default mapping pin ADC12_IN5 +#define ADC2_CH2 (0x1ul << 2u) ///< Default mapping pin ADC12_IN6 +#define ADC2_CH3 (0x1ul << 3u) ///< Default mapping pin ADC12_IN7 +#define ADC2_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN8 +#define ADC2_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN9 +#define ADC2_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN10 +#define ADC2_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN11 +#define ADC2_CH8 (0x1ul << 8u) +#define ADC2_CH_INTERNAL (ADC2_CH8) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC +#define ADC2_CH_ALL (0x000001FFul) +#define ADC2_PIN_MASK_ALL (ADC2_CH_ALL & ~ADC2_CH_INTERNAL) + +/* +* PGA channel definition. +* NOTE: The PGA channel directly maps external pins and does not correspond to the ADC channel. +*/ +#define PGA_CH0 (0x1ul << ADC1_IN0) ///< Mapping pin ADC1_IN0 +#define PGA_CH1 (0x1ul << ADC1_IN1) ///< Mapping pin ADC1_IN1 +#define PGA_CH2 (0x1ul << ADC1_IN2) ///< Mapping pin ADC1_IN2 +#define PGA_CH3 (0x1ul << ADC1_IN3) ///< Mapping pin ADC1_IN3 +#define PGA_CH4 (0x1ul << ADC12_IN4) ///< Mapping pin ADC12_IN4 +#define PGA_CH5 (0x1ul << ADC12_IN5) ///< Mapping pin ADC12_IN5 +#define PGA_CH6 (0x1ul << ADC12_IN6) ///< Mapping pin ADC12_IN6 +#define PGA_CH7 (0x1ul << ADC12_IN7) ///< Mapping pin ADC12_IN7 +#define PGA_CH8 (0x1ul << ADC12_IN8) ///< Mapping internal 8bit DAC1 output +#define PGA_CH_ALL (0x000001FFul) + +/* ADC1 has up to 17 channels */ +#define ADC1_CH_COUNT (17u) + +/* ADC2 has up to 9 channels */ +#define ADC2_CH_COUNT (9u) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit); +en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx); + +en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode); +en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, const stc_adc_trg_cfg_t *pstcTrgCfg); +en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState); +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \ + en_adc_com_trigger_t enComTrigger, en_functional_state_t enState); + +en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg); +en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState); + +en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt); +en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); + +en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg); +en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState); +en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState); +en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); +en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel); + +void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn); +void ADC_PgaCmd(en_functional_state_t enState); +void ADC_AddPgaChannel(uint32_t u32Channel); +void ADC_DelPgaChannel(uint32_t u32Channel); + +void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay); +void ADC_SyncCmd(en_functional_state_t enState); + +en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx); +en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx); +en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq); +void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq); +en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length, uint32_t u32Timeout); + +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length); +en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, uint16_t *pu16AdcData, uint8_t u8Length); +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex); + +uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx); +void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx); +void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh); + +en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32DestChannel, uint8_t u8AdcPin); +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex); + +//@} // AdcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_ADC_ENABLE */ + +#endif /* __HC32F460_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_aes.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_aes.h new file mode 100644 index 0000000000..eca2f48cb8 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_aes.h @@ -0,0 +1,81 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_aes.h + ** + ** A detailed description is available at + ** @link AesGroup Aes description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Aes. + ** + ******************************************************************************/ +#ifndef __HC32F460_AES_H__ +#define __HC32F460_AES_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_AES_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup AesGroup Advanced Encryption Standard(AES) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + /* AES key length in bytes is 16. */ +#define AES_KEYLEN ((uint8_t)16) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t AES_Encrypt(const uint8_t *pu8Plaintext, + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t *pu8Ciphertext); + +en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext, + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t *pu8Plaintext); + +//@} // AesGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_AES_ENABLE */ + +#endif /* __HC32F460_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_can.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_can.h new file mode 100644 index 0000000000..9bba878b4e --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_can.h @@ -0,0 +1,514 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.h + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of CAN + ** + ******************************************************************************/ +#ifndef __HC32F460_CAN_H__ +#define __HC32F460_CAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CAN_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CanGroup Controller Area Network(CAN) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The Can error types. + ******************************************************************************/ +typedef enum +{ + NO_ERROR = 0U, + BIT_ERROR = 1U, + FORM_ERROR = 2U, + STUFF_ERROR = 3U, + ACK_ERROR = 4U, + CRC_ERROR = 5U, + UNKOWN_ERROR = 6U, +}en_can_error_t; + +/** + ******************************************************************************* + ** \brief The Can transmit buffer select.(TCMD) + ******************************************************************************/ +typedef enum +{ + CanPTBSel = 0U, ///< high-priority buffer + CanSTBSel = 1U, ///< secondary buffer +}en_can_buffer_sel_t; + +/** + ******************************************************************************* + ** \brief The Can warning limits.(AFWL) + ******************************************************************************/ +typedef struct stc_can_warning_limit +{ + uint8_t CanWarningLimitVal; ///< Receive buffer almost full warning limit + uint8_t CanErrorWarningLimitVal; ///< Programmable error warning limit +}stc_can_warning_limit_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Frame Format Check.(ACF) + ******************************************************************************/ +typedef enum en_can_acf_format_en +{ + CanStdFrames = 0x02u, ///< Accepts only Standard frames + CanExtFrames = 0x03u, ///< Accepts only Extended frames + CanAllFrames = 0x00u, ///< Accepts both standard or extended frames +}en_can_acf_format_en_t; + +/** + ******************************************************************************* + ** \brief The Acceptance Filters Enable.(ACFEN) + ******************************************************************************/ +typedef enum en_can_filter_sel +{ + CanFilterSel1 = 0u, ///< The Acceptance Filter 1 Enable + CanFilterSel2 = 1u, ///< The Acceptance Filter 2 Enable + CanFilterSel3 = 2u, ///< The Acceptance Filter 3 Enable + CanFilterSel4 = 3u, ///< The Acceptance Filter 4 Enable + CanFilterSel5 = 4u, ///< The Acceptance Filter 5 Enable + CanFilterSel6 = 5u, ///< The Acceptance Filter 6 Enable + CanFilterSel7 = 6u, ///< The Acceptance Filter 7 Enable + CanFilterSel8 = 7u, ///< The Acceptance Filter 8 Enable +}en_can_filter_sel_t; + +/** + ******************************************************************************* + ** \brief The can interrupt enable.(IE) + ******************************************************************************/ +typedef enum +{ + //<empty and =almost full, but not full and no overflow + CanRxBufFull = 3, ///< full +}en_can_rx_buf_status_t; + +/** + ******************************************************************************* + ** \brief The Can Transmission secondary Status.(TSSTAT) + ******************************************************************************/ +typedef enum +{ + CanTxBufEmpty = 0, ///< TTEN=0 or TTTBM=0: STB is empty + ///< TTEN=1 and TTTBM=1: PTB and STB are empty + CanTxBufnotHalfFull = 1, ///< TTEN=0 or TTTBM=0: STB is less than or equal to half full + ///< TTEN=1 and TTTBM=1: PTB and STB are not empty and not full + CanTxBufHalfFull = 2, ///< TTEN=0 or TTTBM=0: STB is more than half full + ///< TTEN=1 and TTTBM=1: None + CanTxBufFull = 3, ///< TTEN=0 or TTTBM=0: STB is full + ///< TTEN=1 and TTTBM=1: PTB and STB are full +}en_can_tx_buf_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Acceptance Filter Code and Mask. + ******************************************************************************/ +typedef struct stc_can_filter +{ + uint32_t u32CODE; ///< Acceptance CODE + uint32_t u32MASK; ///< Acceptance MASK + en_can_filter_sel_t enFilterSel; ///< The Acceptance Filters Enable + en_can_acf_format_en_t enAcfFormat; ///< The Acceptance Filters Frame Format Check. +}stc_can_filter_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Bit Timing. + ******************************************************************************/ +typedef struct stc_can_bt +{ + uint8_t SEG_1; ///< Bit timing segment 1(Tseg_1 = (SEG_1 + 2)*TQ) + uint8_t SEG_2; ///< Bit timing segment 2(Tseg_2 = (SEG_2 + 1)*TQ) + uint8_t SJW; ///< Synchronization jump width(Tsjw = (SJW + 1)*TQ) + uint8_t PRESC; ///< The Prescaler divides the system clock to get the time quanta clock tq_clk(TQ) +}stc_can_bt_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Control Frame. + ******************************************************************************/ +typedef struct +{ + uint32_t DLC : 4; ///< Data length code + uint32_t RESERVED0 : 2; ///< Ignore + uint32_t RTR : 1; ///< Remote transmission request + uint32_t IDE : 1; ///< IDentifier extension + uint32_t RESERVED1 : 24; ///< Ignore +}stc_can_txcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Tx Frame. + ******************************************************************************/ +typedef struct stc_can_txframe +{ + union + { + uint32_t TBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t TBUF32_1; ///< Ignore + stc_can_txcontrol_t Control_f; ///< CAN Tx Control + }; + union + { + uint32_t TBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; + en_can_buffer_sel_t enBufferSel; ///< CAN Tx buffer select +}stc_can_txframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx Ctrl. + ******************************************************************************/ +typedef struct +{ + uint8_t DLC : 4; ///< Data length code + uint8_t RESERVED0 : 2; ///< Ignore + uint8_t RTR : 1; ///< Remote transmission request + uint8_t IDE : 1; ///< IDentifier extension +}stc_can_rxcontrol_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN status. + ******************************************************************************/ +typedef struct +{ + uint8_t RESERVED0 : 4; ///< Ignore + uint8_t TX : 1; ///< TX is set to 1 if the loop back mode is activated + uint8_t KOER : 3; ///< Kind of error +}stc_can_status_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN control, status and cycletime. + ******************************************************************************/ +typedef struct +{ + stc_can_rxcontrol_t Control_f; ///< @ref stc_can_rxcontrol_t + stc_can_status_t Status_f; ///< @ref stc_can_status_t + uint16_t CycleTime; ///< TTCAN cycletime +}stc_can_cst_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_rxframe +{ + union + { + uint32_t RBUF32_0; ///< Ignore + uint32_t StdID; ///< Standard ID + uint32_t ExtID; ///< Extended ID + }; + union + { + uint32_t RBUF32_1; ///< Ignore + stc_can_cst_t Cst; ///< @ref stc_can_cst_t + }; + union + { + uint32_t RBUF32_2[2]; ///< Ignore + uint8_t Data[8]; ///< CAN data + }; +}stc_can_rxframe_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN Rx frame. + ******************************************************************************/ +typedef struct stc_can_init_config +{ + en_can_rx_buf_all_t enCanRxBufAll; ///< @ref en_can_rx_buf_all_t + en_can_rx_buf_mode_en_t enCanRxBufMode; ///< @ref en_can_rx_buf_mode_en_t + en_can_self_ack_en_t enCanSAck; ///< @ref en_can_self_ack_en_t + en_can_stb_mode_t enCanSTBMode; ///< @ref en_can_stb_mode_t + stc_can_bt_t stcCanBt; ///< @ref stc_can_bt_t + stc_can_warning_limit_t stcWarningLimit; ///< @ref stc_can_warning_limit_t +}stc_can_init_config_t; + +/** + ******************************************************************************* + ** \brief CAN TTCAN + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN pointer to a TB message slot + ******************************************************************************/ +typedef enum +{ + CanTTcanPTBSel = 0x00u, ///< PTB + CanTTcanSTB1Sel = 0x01u, ///< STB1 + CanTTcanSTB2Sel = 0x02u, ///< STB2 + CanTTcanSTB3Sel = 0x03u, ///< STB3 + CanTTcanSTB4Sel = 0x04u, ///< STB4 +}en_can_ttcan_tbslot_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Timer prescaler + ******************************************************************************/ +typedef enum +{ + CanTTcanTprescDiv1 = 0x00u, ///< Div1 + CanTTcanTprescDiv2 = 0x01u, ///< Div2 + CanTTcanTprescDiv3 = 0x02u, ///< Div3 + CanTTcanTprescDiv4 = 0x03u, ///< Div4 +}en_can_ttcan_Tpresc_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of CAN TTCAN Trigger type + ******************************************************************************/ +typedef enum +{ + CanTTcanImmediate = 0x00, ///< Immediate trigger for immediate transmission + CanTTcanTime = 0x01, ///< Time trigger for receive trigger + CanTTcanSingle = 0x02, ///< Single shot transmit trigger for exclusive time windows + CanTTcanTransStart = 0x03, ///< Transmit start trigger for merged arbitrating time windows + CanTTcanTransStop = 0x04, ///< Transmit stop trigger for merged arbitrating time windows +}en_can_ttcan_trigger_type_t; + +typedef enum +{ + CanTTcanWdtTriggerIrq = 0x80, ///< Watch trigger interrupt + CanTTcanTimTriggerIrq = 0x10, ///< Time trigger interrupt +}en_can_ttcan_irq_type_t; + + +typedef struct stc_can_ttcan_ref_msg +{ + uint8_t u8IDE; ///< Reference message IDE:1-Extended; 0-Standard; + union ///< Reference message ID + { + uint32_t RefStdID; ///< Reference standard ID + uint32_t RefExtID; ///< Reference Extended ID + }; +}stc_can_ttcan_ref_msg_t; + +typedef struct stc_can_ttcan_trigger_config +{ + en_can_ttcan_tbslot_t enTbSlot; ///< Transmit trigger TB slot pointer + en_can_ttcan_trigger_type_t enTrigType; ///< Trigger type + en_can_ttcan_Tpresc_t enTpresc; ///< Timer prescaler + uint8_t u8Tew; ///< Transmit enable window + uint16_t u16TrigTime; ///< TTCAN trigger time + uint16_t u16WatchTrigTime; ///< TTCAN watch trigger time register +}stc_can_ttcan_trigger_config_t; + + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CAN_Init(stc_can_init_config_t *pstcCanInitCfg); +void CAN_DeInit(void); +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState); +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType); +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState); +en_can_error_t CAN_ErrorStatusGet(void); +bool CAN_StatusGet(en_can_status_t enCanStatus); + +void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState); +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame); +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd); +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame); + +uint8_t CAN_ArbitrationLostCap(void); +uint8_t CAN_RxErrorCntGet(void); +uint8_t CAN_TxErrorCntGet(void); + + +//<< void CAN_TTCAN_Enable(void); +//<< void CAN_TTCAN_Disable(void); +//<< void CAN_TTCAN_IrqCmd(void); +//<< void CAN_TTCAN_ReferenceMsgSet(stc_can_ttcan_ref_msg_t *pstcRefMsg); +//<< void CAN_TTCAN_TriggerConfig(stc_can_ttcan_trigger_config_t *pstcTriggerCfg); + +//@} // CanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CAN_ENABLE */ + +#endif /* __HC32F460_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_clk.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_clk.h new file mode 100644 index 0000000000..84c555dc2a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_clk.h @@ -0,0 +1,647 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_clk.h + ** + ** A detailed description is available at + ** @link CmuGroup Clock description @endlink + ** + ** - 2018-10-13 CDT First version for Device Driver Library of CMU. + ** + ******************************************************************************/ +#ifndef __HC32F460_CLK_H__ +#define __HC32F460_CLK_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CLK_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CmuGroup Clock Manage Unit(CMU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief The system clock source. + ** + ******************************************************************************/ + typedef enum en_clk_sys_source + { + ClkSysSrcHRC = 0u, ///< The system clock source is HRC. + ClkSysSrcMRC = 1u, ///< The system clock source is MRC. + ClkSysSrcLRC = 2u, ///< The system clock source is LRC. + ClkSysSrcXTAL = 3u, ///< The system clock source is XTAL. + ClkSysSrcXTAL32 = 4u, ///< The system clock source is XTAL32. + CLKSysSrcMPLL = 5u, ///< The system clock source is MPLL. + }en_clk_sys_source_t; + +/** + ******************************************************************************* + ** \brief The pll clock source. + ** + ******************************************************************************/ + typedef enum en_clk_pll_source + { + ClkPllSrcXTAL = 0u, ///< The pll clock source is XTAL. + ClkPllSrcHRC = 1u, ///< The pll clock source is HRC. + }en_clk_pll_source_t; + +/** + ******************************************************************************* + ** \brief The usb clock source. + ** + ******************************************************************************/ +typedef enum en_clk_usb_source +{ + ClkUsbSrcSysDiv2 = 2u, ///< The usb clock source is 1/2 system clock. + ClkUsbSrcSysDiv3 = 3u, ///< The usb clock source is 1/3 system clock. + ClkUsbSrcSysDiv4 = 4u, ///< The usb clock source is 1/4 system clock. + ClkUsbSrcMpllp = 8u, ///< The usb clock source is MPLLP. + ClkUsbSrcMpllq = 9u, ///< The usb clock source is MPLLQ. + ClkUsbSrcMpllr = 10u, ///< The usb clock source is MPLLR. + ClkUsbSrcUpllp = 11u, ///< The usb clock source is UPLLP. + ClkUsbSrcUpllq = 12u, ///< The usb clock source is UPLLQ. + ClkUsbSrcUpllr = 13u, ///< The usb clock source is UPLLR. +}en_clk_usb_source_t; + +/** + ******************************************************************************* + ** \brief The peripheral(adc/trng/I2S) clock source. + ** + ******************************************************************************/ +typedef enum en_clk_peri_source +{ + ClkPeriSrcPclk = 0u, ///< The peripheral(adc/trng/I2S) clock source is division from system clock. + ClkPeriSrcMpllp = 8u, ///< The peripheral(adc/trng/I2S) clock source is MPLLP. + ClkPeriSrcMpllq = 9u, ///< The peripheral(adc/trng/I2S) clock source is MPLLQ. + ClkPeriSrcMpllr = 10u, ///< The peripheral(adc/trng/I2S) clock source is MPLLR. + ClkPeriSrcUpllp = 11u, ///< The peripheral(adc/trng/I2S) clock source is UPLLP. + ClkPeriSrcUpllq = 12u, ///< The peripheral(adc/trng/I2S) clock source is UPLLQ. + ClkPeriSrcUpllr = 13u, ///< The peripheral(adc/trng/I2S) clock source is UPLLR. +}en_clk_peri_source_t; + +/** + ******************************************************************************* + ** \brief The clock output source. + ** + ******************************************************************************/ +typedef enum en_clk_output_source +{ + ClkOutputSrcHrc = 0u, ///< The clock output source is HRC + ClkOutputSrcMrc = 1u, ///< The clock output source is MRC. + ClkOutputSrcLrc = 2u, ///< The clock output source is LRC. + ClkOutputSrcXtal = 3u, ///< The clock output source is XTAL. + ClkOutputSrcXtal32 = 4u, ///< The clock output source is XTAL32 + ClkOutputSrcMpllp = 6u, ///< The clock output source is MPLLP. + ClkOutputSrcUpllp = 7u, ///< The clock output source is UPLLP. + ClkOutputSrcMpllq = 8u, ///< The clock output source is MPLLQ. + ClkOutputSrcUpllq = 9u, ///< The clock output source is UPLLQ. + ClkOutputSrcSysclk = 11u, ///< The clock output source is system clock. +}en_clk_output_source_t; + +/** + ******************************************************************************* + ** \brief The clock frequency source for measure or reference. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_source +{ + ClkFcmSrcXtal = 0u, ///< The clock frequency measure or reference source is XTAL + ClkFcmSrcXtal32 = 1u, ///< The clock frequency measure or reference source is XTAL32. + ClkFcmSrcHrc = 2u, ///< The clock frequency measure or reference source is HRC. + ClkFcmSrcLrc = 3u, ///< The clock frequency measure or reference source is LRC. + ClkFcmSrcSwdtrc = 4u, ///< The clock frequency measure or reference source is SWDTRC + ClkFcmSrcPclk1 = 5u, ///< The clock frequency measure or reference source is PCLK1. + ClkFcmSrcUpllp = 6u, ///< The clock frequency measure or reference source is UPLLP. + ClkFcmSrcMrc = 7u, ///< The clock frequency measure or reference source is MRC. + ClkFcmSrcMpllp = 8u, ///< The clock frequency measure or reference source is MPLLP. + ClkFcmSrcRtcLrc = 9u, ///< The clock frequency measure or reference source is RTCLRC. +}en_clk_fcm_intref_source_t,en_clk_fcm_measure_source_t; + +/** + ******************************************************************************* + ** \brief The clock flag status. + ** + ******************************************************************************/ +typedef enum en_clk_flag +{ + ClkFlagHRCRdy = 0u, ///< The clock flag is HRC ready. + ClkFlagXTALRdy = 1u, ///< The clock flag is XTAL ready. + ClkFlagMPLLRdy = 2u, ///< The clock flag is MPLL ready. + ClkFlagUPLLRdy = 3u, ///< The clock flag is UPLL ready. + ClkFlagXTALStoppage = 4u, ///< The clock flag is XTAL stoppage. +}en_clk_flag_t; + +/** + ******************************************************************************* + ** \brief The clock frequency measure flag status. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_flag +{ + ClkFcmFlagErrf = 0u, ///< The clock frequency flag is frequency abnormal. + ClkFcmFlagMendf = 1u, ///< The clock frequency flag is end of measurement. + ClkFcmFlagOvf = 2u, ///< The clock frequency flag is counter overflow. +}en_clk_fcm_flag_t; + +/** + ******************************************************************************* + ** \brief The source of xtal. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_mode +{ + ClkXtalModeOsc = 0u, ///< Use external high speed osc as source. + ClkXtalModeExtClk = 1u, ///< Use external clk as source. +}en_clk_xtal_mode_t; + +/** + ******************************************************************************* + ** \brief The drive capability of xtal. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_drv +{ + ClkXtalHighDrv = 0u, ///< High drive capability.20MHz~24MHz. + ClkXtalMidDrv = 1u, ///< Middle drive capability.16MHz~20MHz. + ClkXtalLowDrv = 2u, ///< Low drive capability.8MHz~16MHz. + ClkXtalTinyDrv = 3u, ///< Tiny drive capability.8MHz. +}en_clk_xtal_drv_t; + +/** + ******************************************************************************* + ** \brief The stable time of XTAL. + ** + ** \note It depends on SUPDRV bit. + ******************************************************************************/ +typedef enum en_clk_xtal_stb_cycle +{ + ClkXtalStbCycle35 = 1u, ///< stable time is 35(36) cycle. + ClkXtalStbCycle67 = 2u, ///< stable time is 67(68) cycle. + ClkXtalStbCycle131 = 3u, ///< stable time is 131(132) cycle. + ClkXtalStbCycle259 = 4u, ///< stable time is 259(260) cycle. + ClkXtalStbCycle547 = 5u, ///< stable time is 547(548) cycle. + ClkXtalStbCycle1059 = 6u, ///< stable time is 1059(1060) cycle. + ClkXtalStbCycle2147 = 7u, ///< stable time is 2147(2148) cycle. + ClkXtalStbCycle4291 = 8u, ///< stable time is 4291(4292) cycle. + ClkXtalStbCycle8163 = 9u, ///< stable time is 8163(8164) cycle. +}en_clk_xtal_stb_cycle_t; + +/** + ******************************************************************************* + ** \brief The handle of xtal stoppage. + ** + ******************************************************************************/ +typedef enum en_clk_xtal_stp_mode +{ + ClkXtalStpModeInt = 0u, ///< The handle of stoppage is interrupt. + ClkXtalStpModeReset = 1u, ///< The handle of stoppage is reset. +}en_clk_xtal_stp_mode_t; + +/** + ******************************************************************************* + ** \brief The drive capability of xtal32. + ** + ******************************************************************************/ +typedef enum en_clk_xtal32_drv +{ + ClkXtal32MidDrv = 0u, ///< Middle drive capability.32.768KHz. + ClkXtal32HighDrv = 1u, ///< High drive capability.32.768KHz. +}en_clk_xtal32_drv_t; + +/** + ******************************************************************************* + ** \brief The filter mode of xtal32. + ** + ******************************************************************************/ +typedef enum en_clk_xtal32_filter_mode +{ + ClkXtal32FilterModeFull = 0u, ///< Valid in run,stop,power down mode. + ClkXtal32FilterModePart = 2u, ///< Valid in run mode. + ClkXtal32FilterModeNone = 3u, ///< Invalid in run,stop,power down mode. +}en_clk_xtal32_filter_mode_t; + +/** + ******************************************************************************* + ** \brief The division factor of system clock. + ** + ******************************************************************************/ +typedef enum en_clk_sysclk_div_factor +{ + ClkSysclkDiv1 = 0u, ///< 1 division. + ClkSysclkDiv2 = 1u, ///< 2 division. + ClkSysclkDiv4 = 2u, ///< 4 division. + ClkSysclkDiv8 = 3u, ///< 8 division. + ClkSysclkDiv16 = 4u, ///< 16 division. + ClkSysclkDiv32 = 5u, ///< 32 division. + ClkSysclkDiv64 = 6u, ///< 64 division. +}en_clk_sysclk_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of system clock.It will be used for debug clock. + ** + ******************************************************************************/ +typedef enum en_clk_tpiuclk_div_factor +{ + ClkTpiuclkDiv1 = 0u, ///< 1 division. + ClkTpiuclkDiv2 = 1u, ///< 2 division. + ClkTpiuclkDiv4 = 2u, ///< 4 division. +}en_clk_tpiuclk_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of clock output. + ** + ******************************************************************************/ +typedef enum en_clk_output_div_factor +{ + ClkOutputDiv1 = 0u, ///< 1 division. + ClkOutputDiv2 = 1u, ///< 2 division. + ClkOutputDiv4 = 2u, ///< 4 division. + ClkOutputDiv8 = 3u, ///< 8 division. + ClkOutputDiv16 = 4u, ///< 16 division. + ClkOutputDiv32 = 5u, ///< 32 division. + ClkOutputDiv64 = 6u, ///< 64 division. + ClkOutputDiv128 = 7u, ///< 128 division. +}en_clk_output_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of fcm measure source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_measure_div_factor +{ + ClkFcmMeaDiv1 = 0u, ///< 1 division. + ClkFcmMeaDiv4 = 1u, ///< 4 division. + ClkFcmMeaDiv8 = 2u, ///< 8 division. + ClkFcmMeaDiv32 = 3u, ///< 32 division. +}en_clk_fcm_measure_div_factor_t; + +/** + ******************************************************************************* + ** \brief The division factor of fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_intref_div_factor +{ + ClkFcmIntrefDiv32 = 0u, ///< 32 division. + ClkFcmIntrefDiv128 = 1u, ///< 128 division. + ClkFcmIntrefDiv1024 = 2u, ///< 1024 division. + ClkFcmIntrefDiv8192 = 3u, ///< 8192 division. +}en_clk_fcm_intref_div_factor_t; + +/** + ******************************************************************************* + ** \brief The edge of the fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_edge +{ + ClkFcmEdgeRising = 0u, ///< Rising edge. + ClkFcmEdgeFalling = 1u, ///< Falling edge. + ClkFcmEdgeBoth = 2u, ///< Both edge. +}en_clk_fcm_edge_t; + +/** + ******************************************************************************* + ** \brief The filter clock of the fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_filter_clk +{ + ClkFcmFilterClkNone = 0u, ///< None filter. + ClkFcmFilterClkFcmSrc = 1u, ///< Use fcm measurement source as filter clock. + ClkFcmFilterClkFcmSrcDiv4 = 2u, ///< Use 1/4 fcm measurement source as filter clock. + ClkFcmFilterClkFcmSrcDiv16 = 3u, ///< Use 1/16 fcm measurement source as filter clock. +}en_clk_fcm_filter_clk_t; + +/** + ******************************************************************************* + ** \brief The fcm reference source. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_refer +{ + ClkFcmExtRef = 0u, ///< Use external reference. + ClkFcmInterRef = 1u, ///< Use internal reference. +}en_clk_fcm_refer_t; + +/** + ******************************************************************************* + ** \brief The handle of fcm abnormal. + ** + ******************************************************************************/ +typedef enum en_clk_fcm_abnormal_handle +{ + ClkFcmHandleInterrupt = 0u, ///< The handle of fcm abnormal is interrupt. + ClkFcmHandleReset = 1u, ///< The handle of fcm abnormal is reset. +}en_clk_fcm_abnormal_handle_t; + +/** + ******************************************************************************* + ** \brief The channel of clock output. + ** + ******************************************************************************/ +typedef enum en_clk_output_ch +{ + ClkOutputCh1 = 1u, ///< The output of clk is MCO_1. + ClkOutputCh2 = 2u, ///< The output of clk is MCO_2. +}en_clk_output_ch_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL. + ** + ** \note Configures the XTAL if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal_cfg +{ + en_functional_state_t enFastStartup; ///< Enable fast start up or not. + en_clk_xtal_mode_t enMode; ///< Select xtal mode. + en_clk_xtal_drv_t enDrv; ///< Select xtal drive capability. +}stc_clk_xtal_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL stoppage. + ** + ** \note Configures the XTAL stoppage if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal_stp_cfg +{ + en_functional_state_t enDetect; ///< Enable detect stoppage or not. + en_clk_xtal_stp_mode_t enMode; ///< Select the handle of xtal stoppage. + en_functional_state_t enModeReset; ///< Enable reset for handle the xtal stoppage. + en_functional_state_t enModeInt; ///< Enable interrupt for handle the xtal stoppage. +}stc_clk_xtal_stp_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of XTAL32. + ** + ** \note Configures the XTAL32 if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_xtal32_cfg +{ + en_clk_xtal32_drv_t enDrv; ///< Select xtal32 drive capability. + en_clk_xtal32_filter_mode_t enFilterMode; ///< The filter mode of xtal32. +}stc_clk_xtal32_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of PLL. + ** + ** \note Configures the PLL if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_pll_cfg +{ + uint32_t PllpDiv; ///< Pllp clk, division factor of VCO out. + uint32_t PllqDiv; ///< Pllq clk, division factor of VCO out. + uint32_t PllrDiv; ///< Pllr clk, division factor of VCO out. + uint32_t plln; ///< Multiplication factor of vco out, ensure between 240M~480M + uint32_t pllmDiv; ///< Division factor of VCO in, ensure between 1M~12M. +}stc_clk_mpll_cfg_t, stc_clk_upll_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of system clock. + ** + ** \note Configures the system clock if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_sysclk_cfg +{ + en_clk_sysclk_div_factor_t enHclkDiv; ///< Division for hclk. + en_clk_sysclk_div_factor_t enExclkDiv; ///< Division for exclk. + en_clk_sysclk_div_factor_t enPclk0Div; ///< Division for pclk0. + en_clk_sysclk_div_factor_t enPclk1Div; ///< Division for pclk1. + en_clk_sysclk_div_factor_t enPclk2Div; ///< Division for pclk2. + en_clk_sysclk_div_factor_t enPclk3Div; ///< Division for pclk3. + en_clk_sysclk_div_factor_t enPclk4Div; ///< Division for pclk4. +}stc_clk_sysclk_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of clock output. + ** + ** \note Configures the clock output if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_output_cfg +{ + en_clk_output_source_t enOutputSrc; ///< The clock output source. + en_clk_output_div_factor_t enOutputDiv; ///< The division factor of clock output source. +}stc_clk_output_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm window. + ** + ** \note Configures the fcm window if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_window_cfg +{ + uint16_t windowLower; ///< The lower value of the window. + uint16_t windowUpper; ///< The upper value of the window. +}stc_clk_fcm_window_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm measurement. + ** + ** \note Configures the fcm measurement if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_measure_cfg +{ + en_clk_fcm_measure_source_t enSrc; ///< The measurement source. + en_clk_fcm_measure_div_factor_t enSrcDiv; ///< The division factor of measurement source. +}stc_clk_fcm_measure_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm reference. + ** + ** \note Configures the fcm reference if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_reference_cfg +{ + en_functional_state_t enExtRef; ///< Enable external reference or not. + en_clk_fcm_edge_t enEdge; ///< The edge of internal reference. + en_clk_fcm_filter_clk_t enFilterClk; ///< The filter clock of internal reference. + en_clk_fcm_refer_t enRefSel; ///< Select reference. + en_clk_fcm_intref_source_t enIntRefSrc; ///< Select internal reference. + en_clk_fcm_intref_div_factor_t enIntRefDiv; ///< The division factor of internal reference. +}stc_clk_fcm_reference_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm interrupt. + ** + ** \note Configures the fcm interrupt if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_interrupt_cfg +{ + en_clk_fcm_abnormal_handle_t enHandleSel; ///< Use interrupt or reset. + en_functional_state_t enHandleReset; ///< Enable reset or not. + en_functional_state_t enHandleInterrupt; ///< Enable interrupt or not. + en_functional_state_t enOvfInterrupt; ///< Enable overflow interrupt or not. + en_functional_state_t enEndInterrupt; ///< Enable measurement end interrupt or not. +}stc_clk_fcm_interrupt_cfg_t; + +/** + ******************************************************************************* + ** \brief Configuration structure of fcm. + ** + ** \note Configures the fcm if needed. + ** + ******************************************************************************/ +typedef struct stc_clk_fcm_cfg +{ + stc_clk_fcm_window_cfg_t *pstcFcmWindowCfg; ///< Window configuration struct. + stc_clk_fcm_measure_cfg_t *pstcFcmMeaCfg; ///< Measurement configuration struct. + stc_clk_fcm_reference_cfg_t *pstcFcmRefCfg; ///< Reference configuration struct. + stc_clk_fcm_interrupt_cfg_t *pstcFcmIntCfg; ///< Interrupt configuration struct. +}stc_clk_fcm_cfg_t; + +/** + ******************************************************************************* + ** \brief Clock frequency structure. + ** + ******************************************************************************/ +typedef struct stc_clk_freq +{ + uint32_t sysclkFreq; ///< System clock frequency. + uint32_t hclkFreq; ///< Hclk frequency. + uint32_t exckFreq; ///< Exclk frequency. + uint32_t pclk0Freq; ///< Pclk0 frequency. + uint32_t pclk1Freq; ///< Pclk1 frequency. + uint32_t pclk2Freq; ///< Pclk2 frequency. + uint32_t pclk3Freq; ///< Pclk3 frequency. + uint32_t pclk4Freq; ///< Pclk4 frequency. +}stc_clk_freq_t; + +/** + ******************************************************************************* + ** \brief PLL Clock frequency structure. + ** + ******************************************************************************/ +typedef struct stc_pll_clk_freq +{ + uint32_t mpllp; ///< mpllp clock frequency. + uint32_t mpllq; ///< mpllq clock frequency. + uint32_t mpllr; ///< mpllr clock frequency. + uint32_t upllp; ///< upllp clock frequency. + uint32_t upllq; ///< upllq clock frequency. + uint32_t upllr; ///< upllr clock frequency. +}stc_pll_clk_freq_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg); +void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb); +void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg); +en_result_t CLK_XtalCmd(en_functional_state_t enNewState); + +void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg); +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState); + +void CLK_HrcTrim(int8_t trimValue); +en_result_t CLK_HrcCmd(en_functional_state_t enNewState); + +void CLK_MrcTrim(int8_t trimValue); +en_result_t CLK_MrcCmd(en_functional_state_t enNewState); + +void CLK_LrcTrim(int8_t trimValue); +en_result_t CLK_LrcCmd(en_functional_state_t enNewState); + +void CLK_SetPllSource(en_clk_pll_source_t enPllSrc); +void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg); +en_result_t CLK_MpllCmd(en_functional_state_t enNewState); + +void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg); +en_result_t CLK_UpllCmd(en_functional_state_t enNewState); + +void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc); +en_clk_sys_source_t CLK_GetSysClkSource(void); + +void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg); +void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq); +void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq); + +void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc); +void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc); +void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc); +en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg); + +void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv); +void CLK_TpiuClkCmd(en_functional_state_t enNewState); + +void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg); +void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState); +en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag); + +void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg); +void CLK_FcmCmd(en_functional_state_t enNewState); + +uint16_t CLK_GetFcmCounter(void); +en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag); +void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag); + +void CLK_ClearXtalStdFlag(void); + +//@} // CmuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CLK_ENABLE */ + +#endif /* __HC32F460_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_cmp.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_cmp.h new file mode 100644 index 0000000000..19d4b632d2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_cmp.h @@ -0,0 +1,279 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_cmp.h + ** + ** A detailed description is available at + ** @link CmpGroup CMP @endlink + ** + ** - 2018-10-22 CDT First version for Device Driver Library of CMP. + ** + ******************************************************************************/ +#ifndef __HC32F460_CMP_H__ +#define __HC32F460_CMP_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CMP_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CmpGroup Comparator(CMP) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief CMP function enumeration + ******************************************************************************/ +typedef enum en_cmp_func +{ + CmpVcoutOutput = (1u << 12), ///< CMP vcout output enable function + CmpOutpuInv = (1u << 13), ///< CMP output invert enable function + CmpOutput = (1u << 14), ///< CMP output enable function +} en_cmp_func_t; + +/** + ******************************************************************************* + ** \brief CMP edge selection enumeration + ******************************************************************************/ +typedef enum en_cmp_edge_sel +{ + CmpNoneEdge = 0u, ///< None edge detection + CmpRisingEdge = 1u, ///< Rising edge detection + CmpFaillingEdge = 2u, ///< Falling edge detection + CmpBothEdge = 3u, ///< Falling or Rising edge detection +} en_cmp_edge_sel_t; + +/** + ******************************************************************************* + ** \brief CMP filter sample clock division enumeration + ******************************************************************************/ +typedef enum en_cmp_fltclk_div +{ + CmpNoneFlt = 0u, ///< Unuse filter + CmpFltPclk3Div1 = 1u, ///< PCLK3/1 + CmpFltPclk3Div2 = 2u, ///< PCLK3/2 + CmpFltPclk3Div4 = 3u, ///< PCLK3/4 + CmpFltPclk3Div8 = 4u, ///< PCLK3/8 + CmpFltPclk3Div16 = 5u, ///< PCLK3/16 + CmpFltPclk3Div32 = 6u, ///< PCLK3/32 + CmpFltPclk3Div64 = 7u, ///< PCLK3/64 +} en_cmp_fltclk_div_t; + +/** + ******************************************************************************* + ** \brief CMP INP4 input enumeration + ******************************************************************************/ +typedef enum en_cmp_inp4_sel +{ + CmpInp4None = 0u, ///< None input + CmpInp4PGAO = 1u, ///< PGAO output + CmpInp4PGAO_BP = 2u, ///< PGAO_BP output + CmpInp4CMP1_INP4 = 4u, ///< CMP1_INP4 +} en_cmp_inp4_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INP input enumeration + ******************************************************************************/ +typedef enum en_cmp_inp_sel +{ + CmpInpNone = 0u, ///< None input + CmpInp1 = 1u, ///< INP1 input + CmpInp2 = 2u, ///< INP2 input + CmpInp1_Inp2 = 3u, ///< INP1 INP2 input + CmpInp3 = 4u, ///< INP3 input + CmpInp1_Inp3 = 5u, ///< INP1 INP3 input + CmpInp2_Inp3 = 6u, ///< INP2 INP3 input + CmpInp1_Inp2_Inp3 = 7u, ///< INP1 INP2 INP3 input + CmpInp4 = 8u, ///< INP4 input + CmpInp1_Inp4 = 9u, ///< INP1 INP4 input + CmpInp2_Inp4 = 10u, ///< INP2 INP4 input + CmpInp1_Inp2_Inp4 = 11u, ///< INP1 INP2 INP4 input + CmpInp3_Inp4 = 12u, ///< INP3 INP4 input + CmpInp1_Inp3_Inp4 = 13u, ///< INP1 INP3 INP4 input + CmpInp2_Inp3_Inp4 = 14u, ///< INP2 INP3 INP4 input + CmpInp1_Inp2_Inp3_Inp4 = 15u, ///< INP1 INP2 INP3 INP4 input +} en_cmp_inp_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INM input enumeration + ******************************************************************************/ +typedef enum en_cmp_inm_sel +{ + CmpInmNone = 0u, ///< None input + CmpInm1 = 1u, ///< INM1 input + CmpInm2 = 2u, ///< INM2 input + CmpInm3 = 4u, ///< INM3 input + CmpInm4 = 8u, ///< INM4 input +} en_cmp_inm_sel_t; + +/** + ******************************************************************************* + ** \brief CMP INP State enumeration (read only) + ******************************************************************************/ +typedef enum en_cmp_inp_state +{ + CmpInpNoneState = 0u, ///< none input state + CmpInp1State = 1u, ///< INP1 input state + CmpInp2State = 2u, ///< INP2 input state + CmpInp3State = 4u, ///< INP3 input state + CmpInp4State = 8u, ///< INP4 input state +} en_cmp_inp_state_t; + +/** + ******************************************************************************* + ** \brief CMP Output State enumeration (read only) + ******************************************************************************/ +typedef enum en_cmp_output_state +{ + CmpOutputLow = 0u, ///< Compare output Low "0" + CmpOutputHigh = 1u, ///< Compare output High "1" +} en_cmp_output_state_t; + +/** + ******************************************************************************* + ** \brief CMP input selection + ******************************************************************************/ +typedef struct stc_cmp_input_sel +{ + en_cmp_inm_sel_t enInmSel; ///< CMP INM sel + + en_cmp_inp_sel_t enInpSel; ///< CMP INP sel + + en_cmp_inp4_sel_t enInp4Sel; ///< CMP INP4 sel +} stc_cmp_input_sel_t; + +/** + ****************************************************************************** + ** \brief DAC channel + ******************************************************************************/ +typedef enum en_cmp_dac_ch +{ + CmpDac1 = 0u, ///< DAC1 + CmpDac2 = 1u, ///< DAC2 +} en_cmp_dac_ch_t; + +/** + ****************************************************************************** + ** \brief ADC internal reference voltage path + ******************************************************************************/ +typedef enum en_cmp_adc_int_ref_volt_path +{ + CmpAdcRefVoltPathDac1 = (1u << 0u), ///< ADC internal reference voltage path: DAC1 + CmpAdcRefVoltPathDac2 = (1u << 1u), ///< ADC internal reference voltage path: DAC2 + CmpAdcRefVoltPathVref = (1u << 4u), ///< ADC internal reference voltage path: VREF +} en_cmp_adc_int_ref_volt_path_t; + +/** + ******************************************************************************* + ** \brief CMP initialization structure definition + ******************************************************************************/ +typedef struct stc_cmp_init +{ + en_cmp_edge_sel_t enEdgeSel; ///< CMP edge sel + + en_cmp_fltclk_div_t enFltClkDiv; ///< CMP FLTclock division + + en_functional_state_t enCmpOutputEn; ///< CMP Output enable + + en_functional_state_t enCmpVcoutOutputEn; ///< CMP output result enable + + en_functional_state_t enCmpInvEn; ///< CMP INV sel for output + + en_functional_state_t enCmpIntEN; ///< CMP interrupt enable +} stc_cmp_init_t; + +/** + ******************************************************************************* + ** \brief CMP DAC initialization structure definition + ******************************************************************************/ +typedef struct stc_cmp_dac_init +{ + uint8_t u8DacData; ///< CMP DAC Data register value + + en_functional_state_t enCmpDacEN; ///< CMP DAC enable +} stc_cmp_dac_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg); +en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx); +en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd); +en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd); +en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx, + uint8_t u8ScanStable, + uint8_t u8ScanPeriod); +en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx, + en_cmp_func_t enFunc, + en_functional_state_t enCmd); +en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx); +en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx, + en_cmp_fltclk_div_t enFltClkDiv); +en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx, + en_cmp_edge_sel_t enEdgeSel); +en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx); +en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx, + const stc_cmp_input_sel_t *pstcInputSel); +en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel); +en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel); +en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx); +en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel); +en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx); +en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx); +en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx); +en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh, + const stc_cmp_dac_init_t *pstcInitCfg); +en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh); +en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd); +en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData); +uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh); +en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath); + +//@} // CmpGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CMP_ENABLE */ + +#endif /* __HC32F460_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_crc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_crc.h new file mode 100644 index 0000000000..756d24924d --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_crc.h @@ -0,0 +1,118 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_crc.h + ** + ** A detailed description is available at + ** @link CrcGroup Crc description @endlink + ** + ** - 2019-03-07 CDT First version for Device Driver Library of Crc. + ** + ******************************************************************************/ +#ifndef __HC32F460_CRC_H__ +#define __HC32F460_CRC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_CRC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup CrcGroup Cyclic Redundancy Check(CRC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* Bits definitions of CRC control register(CRC_CR). */ +/* + * Definitions of CRC protocol. + * NOTE: CRC16 polynomial is X16 + X12 + X5 + 1 + * CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \ + * X8 + X7 + X5 + X4 + X2 + X + 1 + */ +#define CRC_SEL_16B ((uint32_t)0x0) +#define CRC_SEL_32B ((uint32_t)(0x1ul << 1u)) + +/* + * Identifies the transpose configuration of the source data. + * If this function is enabled, the source data's bits in bytes are transposed. + * e.g. There's a source data 0x1234 which will be calculated checksum and this + * function is enabled, the final data be calculated is 0x482C. + * 0x12: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x48. + * 0x48: bit0->bit7, bit1->bit6, ..., bit7->bit0, the data byte changed to 0x2C. + * The same to 32 bit data while using CRC32. + */ +#define CRC_REFIN_DISABLE ((uint32_t)0x0) +#define CRC_REFIN_ENABLE ((uint32_t)(0x1ul << 2u)) + +/* + * Identifies the transpose configuration of the checksum. + * If this function is enabled, bits of the checksum will be transposed. + * e.g. There is a CRC16 checksum is 0x5678 before this function enabled, then + * this function is enabled, the checksum will be 0x1E6A. + * 0x5678: bit0->bit15, bit1->bit14, ..., bit15->bit0, the final data is 0x1E6A. + * The same to CRC32 checksum while using CRC32. + */ +#define CRC_REFOUT_DISABLE ((uint32_t)0x0) +#define CRC_REFOUT_ENABLE ((uint32_t)(0x1ul << 3u)) + +/* + * XORs the CRC checksum with 0xFFFF(CRC16) or 0xFFFFFFFF(CRC32). + * e.g. There is a CRC16 checksum is 0x5678 before this function enabled. + * If this function enabled, the checksum will be 0xA987. + * The same to CRC32 checksum while using CRC32. + */ +#define CRC_XOROUT_DISABLE ((uint32_t)0x0) +#define CRC_XOROUT_ENABLE ((uint32_t)(0x1ul << 4u)) + +#define CRC_CONFIG_MASK ((uint32_t)(0x1Eu)) + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void CRC_Init(uint32_t u32Config); +uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length); +uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length); +bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16CheckSum, const uint16_t *pu16Data, uint32_t u32Length); +bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32CheckSum, const uint32_t *pu32Data, uint32_t u32Length); + +//@} // CrcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_CRC_ENABLE */ + +#endif /* __HC32F460_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dcu.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dcu.h new file mode 100644 index 0000000000..9ed3942d7a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dcu.h @@ -0,0 +1,216 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dcu.h + ** + ** A detailed description is available at + ** @link DcuGroup DCU description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of DCU. + ** + ******************************************************************************/ +#ifndef __HC32F460_DCU_H__ +#define __HC32F460_DCU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_DCU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DcuGroup Data Computing Unit(DCU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief DCU register data enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_data_register +{ + DcuRegisterData0 = 0u, ///< DCU DATA0 + DcuRegisterData1 = 1u, ///< DCU DATA1 + DcuRegisterData2 = 2u, ///< DCU DATA2 +} en_dcu_data_register_t; + +/** + ******************************************************************************* + ** \brief DCU operation enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_operation_mode +{ + DcuInvalid = 0u, ///< DCU Invalid + DcuOpAdd = 1u, ///< DCU operation: Add + DcuOpSub = 2u, ///< DCU operation: Sub + DcuHwTrigOpAdd = 3u, ///< DCU operation: Hardware trigger Add + DcuHwTrigOpSub = 4u, ///< DCU operation: Hardware trigger Sub + DcuOpCompare = 5u, ///< DCU operation: Compare +} en_dcu_operation_mode_t; + +/** + ******************************************************************************* + ** \brief DCU data size enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_data_size +{ + DcuDataBit8 = 0u, ///< DCU data size: 8 bit + DcuDataBit16 = 1u, ///< DCU data size: 16 bit + DcuDataBit32 = 2u, ///< DCU data size: 32 bit +} en_dcu_data_size_t; + +/** + ******************************************************************************* + ** \brief DCU compare operation trigger mode enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_cmp_trigger_mode +{ + DcuCmpTrigbyData0 = 0u, ///< DCU compare triggered by DATA0 + DcuCmpTrigbyData012 = 1u, ///< DCU compare triggered by DATA0 or DATA1 or DATA2 +} en_dcu_cmp_trigger_mode_t; + +/** + ******************************************************************************* + ** \brief DCU interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_int_sel +{ + DcuIntOp = (1ul << 0), ///< DCU overflow or underflow interrupt + DcuIntLs2 = (1ul << 1), ///< DCU DATA0 < DATA2 interrupt + DcuIntEq2 = (1ul << 2), ///< DCU DATA0 = DATA2 interrupt + DcuIntGt2 = (1ul << 3), ///< DCU DATA0 > DATA2 interrupt + DcuIntLs1 = (1ul << 4), ///< DCU DATA0 < DATA1 interrupt + DcuIntEq1 = (1ul << 5), ///< DCU DATA0 = DATA1 interrupt + DcuIntGt1 = (1ul << 6), ///< DCU DATA0 > DATA1 interrupt +} en_dcu_int_sel_t, en_dcu_flag_t; + +/** + ******************************************************************************* + ** \brief DCU window interrupt mode enumeration + ** + ******************************************************************************/ +typedef enum en_dcu_int_win_mode +{ + DcuIntInvalid = 0u, ///< DCU don't occur interrupt + DcuWinIntInvalid = 1u, ///< DCU window interrupt is invalid. + DcuInsideWinCmpInt = 2u, ///< DCU occur interrupt when DATA2 ≤ DATA0 ≤ DATA2 + DcuOutsideWinCmpInt = 3u, ///< DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 +} en_dcu_int_win_mode_t; + +/* DCU common trigger source select */ +typedef enum en_dcu_com_trigger +{ + DcuComTrigger_1 = 1u, ///< Select common trigger 1. + DcuComTrigger_2 = 2u, ///< Select common trigger 2. + DcuComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_dcu_com_trigger_t; + +/** + ******************************************************************************* + ** \brief DCU initialization configuration + ** + ******************************************************************************/ +typedef struct stc_dcu_init +{ + uint32_t u32IntSel; ///< Specifies interrupt selection and This parameter can be a value of @ref en_dcu_int_sel_t + + en_functional_state_t enIntCmd; ///< Select DCU interrupt function. Enable:Enable DCU interrupt function; Disable:Disable DCU interrupt function + + en_dcu_int_win_mode_t enIntWinMode; ///< Specifies interrupt window mode and This parameter can be a value of @ref en_dcu_int_win_mode_t + + en_dcu_data_size_t enDataSize; ///< Specifies DCU data size and This parameter can be a value of @ref en_dcu_data_size_t + + en_dcu_operation_mode_t enOperation; ///< Specifies DCU operation and This parameter can be a value of @ref en_dcu_operation_mode_t + + en_dcu_cmp_trigger_mode_t enCmpTriggerMode; ///< Specifies DCU compare operation trigger mode size and This parameter can be a value of @ref en_dcu_cmp_trigger_mode_t + +} stc_dcu_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg); +en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx, + en_dcu_operation_mode_t enMode); +en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize); +en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx, + en_dcu_int_win_mode_t enIntWinMode); +en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx, + en_dcu_cmp_trigger_mode_t enTriggerMode); +en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx); +en_result_t DCU_EnableInterrupt(M4_DCU_TypeDef *DCUx); +en_result_t DCU_DisableInterrupt(M4_DCU_TypeDef *DCUx); +en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag); +en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag); +en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx, + en_dcu_int_sel_t enIntSel, + en_functional_state_t enCmd); +uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, uint8_t u8Data); +uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint16_t u16Data); +uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg); +en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint32_t u32Data); +en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx, + en_event_src_t enTriggerSrc); +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + en_dcu_com_trigger_t enComTrigger, + en_functional_state_t enState); + +//@} // DcuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_DCU_ENABLE */ + +#endif /* __HC32F460_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dmac.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dmac.h new file mode 100644 index 0000000000..6a75373712 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_dmac.h @@ -0,0 +1,363 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dmac.h + ** + ** A detailed description is available at + ** @link DmacGroup DMAC description @endlink + ** + ** - 2018-11-18 CDT First version for Device Driver Library of DMAC. + ** + ******************************************************************************/ +#ifndef __HC32F460_DMAC_H__ +#define __HC32F460_DMAC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_DMAC_ENABLE == DDL_ON) + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DmacGroup Direct Memory Access Control(DMAC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief DMA Channel + ** + ******************************************************************************/ +typedef enum en_dma_channel +{ + DmaCh0 = 0u, ///< DMA channel 0 + DmaCh1 = 1u, ///< DMA channel 1 + DmaCh2 = 2u, ///< DMA channel 2 + DmaCh3 = 3u, ///< DMA channel 3 + DmaChMax = 4u ///< DMA channel max +}en_dma_channel_t; + +/** + ******************************************************************************* + ** \brief DMA transfer data width + ** + ******************************************************************************/ +typedef enum en_dma_transfer_width +{ + Dma8Bit = 0u, ///< 8 bit transfer via DMA + Dma16Bit = 1u, ///< 16 bit transfer via DMA + Dma32Bit = 2u ///< 32 bit transfer via DMA +}en_dma_transfer_width_t; + +/** + ******************************************************************************* + ** \brief DMA flag + ** + ******************************************************************************/ +typedef enum en_dma_flag +{ + DmaTransferComplete = 0u, ///< DMA transfer complete + DmaBlockComplete = 1u, ///< DMA block transfer complete + DmaTransferErr = 2u, ///< DMA transfer error + DmaReqErr = 3u, ///< DMA transfer request error + DmaFlagMax = 4u +}en_dma_flag_t; + +/** + ******************************************************************************* + ** \brief DMA address mode + ** + ******************************************************************************/ +typedef enum en_dma_address_mode +{ + AddressFix = 0u, ///< Address fixed + AddressIncrease = 1u, ///< Address increased + AddressDecrease = 2u, ///< Address decreased +}en_dma_address_mode_t; + +/** + ******************************************************************************* + ** \brief DMA link list pointer mode + ** + ******************************************************************************/ +typedef enum en_dma_llp_mode +{ + LlpWaitNextReq = 0u, ///< DMA trigger transfer after wait next request + LlpRunNow = 1u, ///< DMA trigger transfer now +}en_dma_llp_mode_t; + +/** + ******************************************************************************* + ** \brief DMA interrupt selection + ** + ******************************************************************************/ +typedef enum en_dma_irq_sel +{ + TrnErrIrq = 0u, ///< Select DMA transfer error interrupt + TrnReqErrIrq = 1u, ///< Select DMA transfer req over error interrupt + TrnCpltIrq = 2u, ///< Select DMA transfer completion interrupt + BlkTrnCpltIrq = 3u, ///< Select DMA block completion interrupt + DmaIrqSelMax = 4u +}en_dma_irq_sel_t; + +/** + ******************************************************************************* + ** \brief DMA re_config count mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_cnt_mode +{ + CntFix = 0u, ///< Fix + CntSrcAddr = 1u, ///< Source address mode + CntDesAddr = 2u, ///< Destination address mode +}en_dma_recfg_cnt_mode_t; + +/** + ******************************************************************************* + ** \brief DMA re_config destination address mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_daddr_mode +{ + DaddrFix = 0u, ///< Fix + DaddrNseq = 1u, ///< No_sequence address + DaddrRep = 2u, ///< Repeat address +}en_dma_recfg_daddr_mode_t; + +/** + ******************************************************************************* + ** \brief DMA re_config source address mode + ** + ******************************************************************************/ +typedef enum en_dma_recfg_saddr_mode +{ + SaddrFix = 0u, ///< Fix + SaddrNseq = 1u, ///< No_sequence address + SaddrRep = 2u, ///< Repeat address +}en_dma_recfg_saddr_mode_t; + +/** + ******************************************************************************* + ** \brief DMA channel status + ** + ******************************************************************************/ +typedef enum en_dma_ch_flag +{ + DmaSta = 0u, ///< DMA status. + ReCfgSta = 1u, ///< DMA re_configuration status. + DmaCh0Sta = 2u, ///< DMA channel 0 status. + DmaCh1Sta = 3u, ///< DMA channel 1 status. + DmaCh2Sta = 4u, ///< DMA channel 2 status. + DmaCh3Sta = 5u, ///< DMA channel 3 status. +}en_dma_ch_flag_t; + +/** + ******************************************************************************* + ** \brief DMA common trigger source select + ** + ******************************************************************************/ +typedef enum en_dma_com_trigger +{ + DmaComTrigger_1 = 0x1, ///< Select common trigger 1. + DmaComTrigger_2 = 0x2, ///< Select common trigger 2. + DmaComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_dma_com_trigger_t; + +/** + ******************************************************************************* + ** \brief DMA llp descriptor + ** + ******************************************************************************/ +typedef struct stc_dma_llp_descriptor +{ + uint32_t SARx; ///< DMA source address register + uint32_t DARx; ///< DMA destination address register + union + { + uint32_t DTCTLx; + stc_dma_dtctl_field_t DTCTLx_f; ///< DMA data control register + }; + union + { + uint32_t RPTx; + stc_dma_rpt_field_t RPTx_f; ///< DMA repeat control register + }; + union + { + uint32_t SNSEQCTLx; + stc_dma_snseqctl_field_t SNSEQCTLx_f; ///< DMA source no-sequence control register + }; + union + { + __IO uint32_t DNSEQCTLx; + stc_dma_dnseqctl_field_t DNSEQCTLx_f; ///< DMA destination no-sequence control register + }; + union + { + uint32_t LLPx; + stc_dma_llp_field_t LLPx_f; ///< DMA link-list-pointer register + }; + union + { + uint32_t CHxCTL; + stc_dma_ch0ctl_field_t CHxCTL_f; ///< DMA channel control register + }; +}stc_dma_llp_descriptor_t; + +/** + ******************************************************************************* + ** \brief DMA no-sequence function configuration + ** + ******************************************************************************/ +typedef struct stc_dma_nseq_cfg +{ + uint32_t u32Offset; ///< DMA no-sequence offset. + uint16_t u16Cnt; ///< DMA no-sequence count. +}stc_dma_nseq_cfg_t; + +/** + ******************************************************************************* + ** \brief DMA no-sequence function configuration + ** + ******************************************************************************/ +typedef struct stc_dma_nseqb_cfg +{ + uint32_t u32NseqDist; ///< DMA no-sequence district interval. + uint16_t u16CntB; ///< DMA no-sequence count. +}stc_dma_nseqb_cfg_t; + +/** + ******************************************************************************* + ** \brief DMA re_config configuration + ** + ******************************************************************************/ +typedef struct stc_dma_recfg_ctl +{ + uint16_t u16SrcRptBSize; ///< The source repeat size. + uint16_t u16DesRptBSize; ///< The destination repeat size. + en_dma_recfg_saddr_mode_t enSaddrMd; ///< DMA re_config source address mode. + en_dma_recfg_daddr_mode_t enDaddrMd; ///< DMA re_config destination address mode. + en_dma_recfg_cnt_mode_t enCntMd; ///< DMA re_config count mode. + stc_dma_nseq_cfg_t stcSrcNseqBCfg; ///< The source no_sequence re_config. + stc_dma_nseq_cfg_t stcDesNseqBCfg; ///< The destination no_sequence re_config. +}stc_dma_recfg_ctl_t; + +/** + ******************************************************************************* + ** \brief DMA channel configuration + ** + ******************************************************************************/ +typedef struct stc_dma_ch_cfg +{ + en_dma_address_mode_t enSrcInc; ///< DMA source address update mode. + en_dma_address_mode_t enDesInc; ///< DMA destination address update mode. + en_functional_state_t enSrcRptEn; ///< Enable source repeat function or not. + en_functional_state_t enDesRptEn; ///< Enable destination repeat function or not. + en_functional_state_t enSrcNseqEn; ///< Enable source no_sequence function or not. + en_functional_state_t enDesNseqEn; ///< Enable destination no_sequence function or not. + en_dma_transfer_width_t enTrnWidth; ///< DMA transfer data width. + en_functional_state_t enLlpEn; ///< Enable linked list pointer function or not. + en_dma_llp_mode_t enLlpMd; ///< Dma linked list pointer mode. + en_functional_state_t enIntEn; ///< Enable interrupt function or not. +}stc_dma_ch_cfg_t; + + +/** + ******************************************************************************* + ** \brief DMA configuration + ** + ******************************************************************************/ +typedef struct stc_dma_config +{ + uint16_t u16BlockSize; ///< Transfer block size = 1024, when 0 is set. + uint16_t u16TransferCnt; ///< Transfer counter. + uint32_t u32SrcAddr; ///< The source address. + uint32_t u32DesAddr; ///< The destination address. + uint16_t u16SrcRptSize; ///< The source repeat size. + uint16_t u16DesRptSize; ///< The destination repeat size. + uint32_t u32DmaLlp; ///< The Dma linked list pointer address + stc_dma_nseq_cfg_t stcSrcNseqCfg; ///< The source no_sequence configuration. + stc_dma_nseq_cfg_t stcDesNseqCfg; ///< The destination no_sequence configuration. + stc_dma_ch_cfg_t stcDmaChCfg; ///< The Dma channel configuration. +}stc_dma_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState); +en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel); +en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState); +void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_recfg_ctl_t* pstcDmaReCfg); +void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg,en_functional_state_t enNewState); +en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag); + +en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address); +en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address); +en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize); +en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt); +en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetDesRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size); +en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstcSrcNseqCfg); +en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg); +en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstDesNseqCfg); +en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstDesNseqBCfg); +en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer); + +void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc); +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc); +void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState); +void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState); + +void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_ch_cfg_t* pstcChCfg); +void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_config_t* pstcDmaCfg); +void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch); + + + +//@} // DmacGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_DMAC_ENABLE */ + +#endif /* __HC32F460_DMAC_H__*/ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_efm.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_efm.h new file mode 100644 index 0000000000..a6185bb013 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_efm.h @@ -0,0 +1,209 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_efm.h + ** + ** A detailed description is available at + ** @link EfmGroup EFM description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of EFM. + ** + ******************************************************************************/ +#ifndef __HC32F460_EFM_H__ +#define __HC32F460_EFM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EFM_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup EfmGroup Embedded Flash Management unit(EFM) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The flash status. + ** + ******************************************************************************/ +typedef enum en_efm_flash_status +{ + FlashReady = 1u, ///< The flash ready flag. + FlashRWErr = 2u, ///< The flash read/write error flag. + FlashEOP = 3u, ///< The flash end of operation flag. + FlashPgMissMatch = 4u, ///< The flash program miss match flag. + FlashPgSizeErr = 5u, ///< The flash program size error flag. + FlashPgareaPErr = 6u, ///< The flash program protect area error flag. + FlashWRPErr = 7u, ///< The flash write protect error flag. +}en_efm_flash_status_t; + +/** + ******************************************************************************* + ** \brief The flash read mode. + ** + ******************************************************************************/ +typedef enum en_efm_read_md +{ + NormalRead = 0u, ///< The flash normal read mode. + UltraPowerRead = 1u, ///< The flash ultra power read mode. +}en_efm_read_md_t; + +/** + ******************************************************************************* + ** \brief The flash interrupt select. + ** + ******************************************************************************/ +typedef enum en_efm_int_sel +{ + PgmErsErrInt = 0u, ///< The flash program / erase error interrupt. + EndPgmInt = 1u, ///< The flash end of program interrupt. + ColErrInt = 2u, ///< The flash read collided error interrupt. +}en_efm_int_sel_t; + +/** + ******************************************************************************* + ** \brief The bus state while flash program & erase. + ** + ******************************************************************************/ +typedef enum en_efm_bus_sta +{ + BusBusy = 0u, ///< The bus busy while flash program & erase. + BusRelease = 1u, ///< The bus release while flash program & erase. +}en_efm_bus_sta_t; + +/** + ******************************************************************************* + ** \brief Structure of windows protect address. + ** + ** \note None. + ** + ******************************************************************************/ +typedef struct stc_efm_win_protect_addr +{ + uint32_t StartAddr; ///< The protect start address. + uint32_t EndAddr; ///< The protect end address. +}stc_efm_win_protect_addr_t; + +/** + ******************************************************************************* + ** \brief Structure of unique ID. + ** + ** \note None. + ** + ******************************************************************************/ +typedef struct stc_efm_unique_id +{ + uint32_t uniqueID1; ///< unique ID 1. + uint32_t uniqueID2; ///< unique ID 2. + uint32_t uniqueID3; ///< unique ID 3. +}stc_efm_unique_id_t; +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + /* Flach latency cycle (0~15) */ +#define EFM_LATENCY_0 (0ul) +#define EFM_LATENCY_1 (1ul) +#define EFM_LATENCY_2 (2ul) +#define EFM_LATENCY_3 (3ul) +#define EFM_LATENCY_4 (4ul) +#define EFM_LATENCY_5 (5ul) +#define EFM_LATENCY_6 (6ul) +#define EFM_LATENCY_7 (7ul) +#define EFM_LATENCY_8 (8ul) +#define EFM_LATENCY_9 (9ul) +#define EFM_LATENCY_10 (10ul) +#define EFM_LATENCY_11 (11ul) +#define EFM_LATENCY_12 (12ul) +#define EFM_LATENCY_13 (13ul) +#define EFM_LATENCY_14 (14ul) +#define EFM_LATENCY_15 (15ul) + +/* Flash flag */ +#define EFM_FLAG_WRPERR (0x00000001ul) +#define EFM_FLAG_PEPRTERR (0x00000002ul) +#define EFM_FLAG_PGSZERR (0x00000004ul) +#define EFM_FLAG_PGMISMTCH (0x00000008ul) +#define EFM_FLAG_EOP (0x00000010ul) +#define EFM_FLAG_COLERR (0x00000020ul) +#define EFM_FLAG_RDY (0x00000100ul) + +/* Flash operate mode */ +#define EFM_MODE_READONLY (0ul) +#define EFM_MODE_SINGLEPROGRAM (1ul) +#define EFM_MODE_SINGLEPROGRAMRB (2ul) +#define EFM_MODE_SEQUENCEPROGRAM (3ul) +#define EFM_MODE_SECTORERASE (4ul) +#define EFM_MODE_CHIPERASE (5ul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void EFM_Unlock(void); +void EFM_Lock(void); + +void EFM_FlashCmd(en_functional_state_t enNewState); +void EFM_SetLatency(uint32_t u32Latency); +void EFM_InstructionCacheCmd(en_functional_state_t enNewState); +void EFM_DataCacheRstCmd(en_functional_state_t enNewState); +void EFM_SetReadMode(en_efm_read_md_t enReadMD); +void EFM_ErasePgmCmd(en_functional_state_t enNewState); +en_result_t EFM_SetErasePgmMode(uint32_t u32Mode); +void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState); + +en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag); +en_flag_status_t EFM_GetSwitchStatus(void); +void EFM_ClearFlag(uint32_t u32flag); +en_efm_flash_status_t EFM_GetStatus(void); +void EFM_SetBusState(en_efm_bus_sta_t enState); + +void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr); + +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf); +en_result_t EFM_SectorErase(uint32_t u32Addr); +en_result_t EFM_MassErase(uint32_t u32Addr); + +en_result_t EFM_OtpLock(uint32_t u32Addr); +stc_efm_unique_id_t EFM_ReadUID(void); + + +//@} // EfmGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EFM_ENABLE */ + +#endif /* __HC32F460_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_emb.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_emb.h new file mode 100644 index 0000000000..0820870beb --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_emb.h @@ -0,0 +1,205 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_emb.h + ** + ** A detailed description is available at + ** @link EMBGroup EMB description @endlink + ** + ** - 2018-11-24 CDT First version for Device Driver Library of EMB. + ** + ******************************************************************************/ +#ifndef __HC32F460_EMB_H__ +#define __HC32F460_EMB_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EMB_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + ******************************************************************************* + ** \defgroup EMBGroup Emergency Brake(EMB) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief EMB status enumeration + ******************************************************************************/ +typedef enum en_emb_status +{ + EMBFlagPortIn = 0u, ///< EMB port in brake flag + EMBFlagPWMSame = 1u, ///< EMB PWM same brake flag + EMBFlagCmp = 2u, ///< EMB CMP brake flag + EMBFlagOSCFail = 3u, ///< EMB oscillator fail brake flag + EMBPortInState = 4u, ///< EMB port in state + EMBPWMState = 5u, ///< EMB PWM same state +} en_emb_status_t; + +/** + ******************************************************************************* + ** \brief EMB status clear(recover) enumeration + ******************************************************************************/ +typedef enum en_emb_status_clr +{ + EMBPortInFlagClr = 0u, ///< EMB port in brake flag clear + EMBPWMSameFlagCLr = 1u, ///< EMB PWM same brake flag clear + EMBCmpFlagClr = 2u, ///< EMB CMP brake flag clear + EMBOSCFailFlagCLr = 3u, ///< EMB oscillator fail brake flag clear +} en_emb_status_clr_t; + +/** + ******************************************************************************* + ** \brief EMB irq enumeration + ******************************************************************************/ +typedef enum en_emb_irq_type +{ + PORTBrkIrq = 0u, ///< EMB port brake interrupt + PWMSmBrkIrq = 1u, ///< EMB PWM same brake interrupt + CMPBrkIrq = 2u, ///< EMB CMP brake interrupt + OSCFailBrkIrq = 3u, ///< EMB oscillator fail brake interrupt +} en_emb_irq_type_t; + +/** + ******************************************************************************* + ** \brief EMB port in filter enumeration + ******************************************************************************/ +typedef enum en_emb_port_filter +{ + EMBPortFltDiv0 = 0u, ///< EMB port in filter with PCLK clock + EMBPortFltDiv8 = 1u, ///< EMB port in filter with PCLK/8 clock + EMBPortFltDiv32 = 2u, ///< EMB port in filter with PCLK/32 clock + EMBPortFltDiv128 = 3u, ///< EMB port in filter with PCLK/128 clock +} en_emb_port_filter_t; + +/** + ******************************************************************************* + ** \brief EMB CR0 for timer6 config + ** \note + ******************************************************************************/ +typedef struct stc_emb_ctrl_timer6 +{ + bool bEnPortBrake; ///< Enable port brake + bool bEnCmp1Brake; ///< Enable CMP1 brake + bool bEnCmp2Brake; ///< Enable CMP2 brake + bool bEnCmp3Brake; ///< Enable CMP3 brake + bool bEnOSCFailBrake; ///< Enable OSC fail brake + bool bEnTimer61PWMSBrake; ///< Enable tiemr61 PWM same brake + bool bEnTimer62PWMSBrake; ///< Enable tiemr62 PWM same brake + bool bEnTimer63PWMSBrake; ///< Enable tiemr63 PWM same brake + en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection + bool bEnPorInFlt; ///< Enable port in filter + bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel +}stc_emb_ctrl_timer6_t; + +/** + ******************************************************************************* + ** \brief EMB CR1~3 for timer4x config + ** \note + ******************************************************************************/ +typedef struct stc_emb_ctrl_timer4 +{ + bool bEnPortBrake; ///< Enable port brake + bool bEnCmp1Brake; ///< Enable CMP1 brake + bool bEnCmp2Brake; ///< Enable CMP2 brake + bool bEnCmp3Brake; ///< Enable CMP3 brake + bool bEnOSCFailBrake; ///< Enable OS fail brake + bool bEnTimer4xWHLSammeBrake; ///< Enable tiemr4x PWM WH WL same brake + bool bEnTimer4xVHLSammeBrake; ///< Enable tiemr4x PWM VH VL same brake + bool bEnTimer4xUHLSammeBrake; ///< Enable tiemr4x PWM UH UL same brake + en_emb_port_filter_t enPortInFltClkSel; ///< Port in filter clock selection + bool bEnPorInFlt; ///< Enable port in filter + bool bEnPortInLevelSel_Low; ///< Poit input active level 1: LowLevel 0:HighLevel +}stc_emb_ctrl_timer4_t; + + +/** + ******************************************************************************* + ** \brief EMB PWM level detect timer6 config + ** \note + ******************************************************************************/ +typedef struct stc_emb_pwm_level_timer6 +{ + bool bEnTimer61HighLevelDect; ///< Enable tiemr61 active detected level 1:HighLevel 0:LowLevel + bool bEnTimer62HighLevelDect; ///< Enable tiemr62 active detected level 1:HighLevel 0:LowLevel + bool bEnTimer63HighLevelDect; ///< Enable tiemr63 active detected level 1:HighLevel 0:LowLevel +}stc_emb_pwm_level_timer6_t; + +/** + ******************************************************************************* + ** \brief EMB PWM level detect timer4x config + ** \note + ******************************************************************************/ +typedef struct stc_emb_pwm_level_timer4 +{ + bool bEnUHLPhaseHighLevelDect; ///< Enable tiemr4x UH UL active detected level 1:HighLevel 0:LowLevel + bool bEnVHLPhaseHighLevelDect; ///< Enable tiemr4x VH VL active detected level 1:HighLevel 0:LowLevel + bool bEnWHLphaseHighLevelDect; ///< Enable tiemr4x WH WL active detected level 1:HighLevel 0:LowLevel +}stc_emb_pwm_level_timer4_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* IRQ config */ +en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx, + en_emb_irq_type_t enEMBIrq, + bool bEn); +/* Get status(flag) */ +bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus); +/* Status(flag) clear (recover) */ +en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx, + en_emb_status_clr_t enStatusClr); +/* Control Register(CTL) config for timer6 */ +en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR); +/* Control Register(CTL) config for timer4 */ +en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_ctrl_timer4_t* pstcEMBConfigCR); +/* PWM level detect (short detection) selection config for timer6 */ +en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv); +/* PWM level detect (short detection) selection config for timer4 */ +en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv); +/* Software brake */ +en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn); + +//@} // EMBGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EMB_ENABLE */ + +#endif /* __HC32F460_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_event_port.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_event_port.h new file mode 100644 index 0000000000..88338297a6 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_event_port.h @@ -0,0 +1,176 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_event_port.h + ** + ** A detailed description is available at + ** @link EventPortGroup EventPort description @endlink + ** + ** - 2018-12-07 CDT First version for Device Driver Library of EventPort. + ** + ******************************************************************************/ + +#ifndef __HC32F460_EVENT_PORT_H__ +#define __HC32F460_EVENT_PORT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EVENT_PORT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup EventPortGroup Event Port (EventPort) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Event Port Index enumeration + ** + ******************************************************************************/ +typedef enum en_event_port +{ + EventPort1 = 0, ///< Event port 1 + EventPort2 = 1, ///< Event port 2 + EventPort3 = 2, ///< Event port 3 + EventPort4 = 3, ///< Event port 4 +}en_event_port_t; + +/** + ******************************************************************************* + ** \brief Event Port Pin enumeration + ** + ******************************************************************************/ +typedef enum en_event_pin +{ + EventPin00 = 1u << 0, ///< Event port Pin 00 + EventPin01 = 1u << 1, ///< Event port Pin 01 + EventPin02 = 1u << 2, ///< Event port Pin 02 + EventPin03 = 1u << 3, ///< Event port Pin 03 + EventPin04 = 1u << 4, ///< Event port Pin 04 + EventPin05 = 1u << 5, ///< Event port Pin 05 + EventPin06 = 1u << 6, ///< Event port Pin 06 + EventPin07 = 1u << 7, ///< Event port Pin 07 + EventPin08 = 1u << 8, ///< Event port Pin 08 + EventPin09 = 1u << 9, ///< Event port Pin 09 + EventPin10 = 1u << 10, ///< Event port Pin 10 + EventPin11 = 1u << 11, ///< Event port Pin 11 + EventPin12 = 1u << 12, ///< Event port Pin 12 + EventPin13 = 1u << 13, ///< Event port Pin 13 + EventPin14 = 1u << 14, ///< Event port Pin 14 + EventPin15 = 1u << 15, ///< Event port Pin 15 + EventPinAll= 0xFFFF, ///< All event pins are selected +}en_event_pin_t; + +/** + ******************************************************************************* + ** \brief Event Port common trigger source select + ** + ******************************************************************************/ +typedef enum en_event_port_com_trigger +{ + EpComTrigger_1 = 0x1, ///< Select common trigger 1. + EpComTrigger_2 = 0x2, ///< Select common trigger 2. + EpComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_event_port_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Event Port direction enumeration + ** + ******************************************************************************/ +typedef enum en_event_port_dir +{ + EventPortIn = 0, ///< Event Port direction 'IN' + EventPortOut = 1, ///< Event Port direction 'OUT' +}en_event_port_dir_t; + +/** + ******************************************************************************* + ** \brief Enumeration to filter clock setting for Event port detect + ** + ** \note + ******************************************************************************/ +typedef enum en_ep_flt_clk +{ + Pclk1Div1 = 0u, ///< PCLK1 as EP filter clock source + Pclk1Div8 = 1u, ///< PCLK1 div8 as EP filter clock source + Pclk1Div32 = 2u, ///< PCLK1 div32 as EP filter clock source + Pclk1Div64 = 3u, ///< PCLK1 div64 as EP filter clock source +}en_ep_flt_clk_t; + +/** + ******************************************************************************* + ** \brief Event port init structure definition + ******************************************************************************/ +typedef struct stc_event_port_init +{ + en_event_port_dir_t enDirection; ///< Input/Output setting + en_functional_state_t enReset; ///< Corresponding pin reset after triggered + en_functional_state_t enSet; ///< Corresponding pin set after triggered + en_functional_state_t enRisingDetect; ///< Rising edge detect enable + en_functional_state_t enFallingDetect;///< Falling edge detect enable + en_functional_state_t enFilter; ///< Filter clock source select + en_ep_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_ep_flt_clk_t for details +}stc_event_port_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t EVENTPORT_Init(en_event_port_t enEventPort, \ + uint16_t u16EventPin, const stc_event_port_init_t *pstcEventPortInit); +extern en_result_t EVENTPORT_DeInit(void); +extern en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \ + en_event_src_t enTriggerSrc); +void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \ + en_event_port_com_trigger_t enComTrigger, \ + en_functional_state_t enState); +extern uint16_t EVENTPORT_GetData(en_event_port_t enEventPort); +extern en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, \ + en_event_pin_t enEventPin); +extern en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, \ + en_event_pin_t u16EventPin); +extern en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, \ + en_event_pin_t u16EventPin); + +//@} // EventPortGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EVENT_PORT_ENABLE */ + +#endif /* __HC32F460_EVENT_PORT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_exint_nmi_swi.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_exint_nmi_swi.h new file mode 100644 index 0000000000..eeb69fc7fe --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_exint_nmi_swi.h @@ -0,0 +1,257 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_exint_nmi_swi.h + ** + ** A detailed description is available at + ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt. + ** + ******************************************************************************/ + +#ifndef __HC32F460_EXINT_NMI_SWI_H__ +#define __HC32F460_EXINT_NMI_SWI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup ExintNmiSwiGroup External Interrupts (External Interrupt), \ + ** NMI (Non-Maskable Interrupt), SWI (Software Interrupt) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Enumeration to filter clock setting for EXINT and NMI + ** + ** \note + ******************************************************************************/ +typedef enum en_ei_flt_clk +{ + Pclk3Div1 = 0u, ///< PCLK3 as EP filter clock source + Pclk3Div8 = 1u, ///< PCLK3 div8 as EP filter clock source + Pclk3Div32 = 2u, ///< PCLK3 div32 as EP filter clock source + Pclk3Div64 = 3u, ///< PCLK3 div64 as EP filter clock source +}en_ei_flt_clk_t; + +/** + ******************************************************************************* + ** \brief Enumeration to NMI detection + ** + ** \note + ******************************************************************************/ +typedef enum en_nmi_lvl +{ + NmiFallingEdge = 0u, ///< Falling edge detection + NmiRisingEdge = 1u, ///< Rising edge detection +}en_nmi_lvl_t; + +/** + ******************************************************************************* + ** \brief Enumeration to EXTI detection + ** + ** \note + ******************************************************************************/ +typedef enum en_exti_lvl +{ + ExIntFallingEdge = 0u, ///< Falling edge detection + ExIntRisingEdge = 1u, ///< Rising edge detection + ExIntBothEdge = 2u, ///< Falling or Rising edge detection + ExIntLowLevel = 3u, ///< "L" level detection +}en_exti_lvl_t; + +/** + ******************************************************************************* + ** \brief Enumeration to define an index for EXINT + ******************************************************************************/ +typedef enum en_exti_ch +{ + ExtiCh00 = 0u, + ExtiCh01 = 1u, + ExtiCh02 = 2u, + ExtiCh03 = 3u, + ExtiCh04 = 4u, + ExtiCh05 = 5u, + ExtiCh06 = 6u, + ExtiCh07 = 7u, + ExtiCh08 = 8u, + ExtiCh09 = 9u, + ExtiCh10 = 10u, + ExtiCh11 = 11u, + ExtiCh12 = 12u, + ExtiCh13 = 13u, + ExtiCh14 = 14u, + ExtiCh15 = 15u, +}en_exti_ch_t; + +/** + ******************************************************************************* + ** \brief Enumeration to define the SWI channel + ******************************************************************************/ +typedef enum en_swi_ch +{ + SwiCh00 = 1u << 0, + SwiCh01 = 1u << 1, + SwiCh02 = 1u << 2, + SwiCh03 = 1u << 3, + SwiCh04 = 1u << 4, + SwiCh05 = 1u << 5, + SwiCh06 = 1u << 6, + SwiCh07 = 1u << 7, + SwiCh08 = 1u << 8, + SwiCh09 = 1u << 9, + SwiCh10 = 1u << 10, + SwiCh11 = 1u << 11, + SwiCh12 = 1u << 12, + SwiCh13 = 1u << 13, + SwiCh14 = 1u << 14, + SwiCh15 = 1u << 15, + SwiCh16 = 1u << 16, + SwiCh17 = 1u << 17, + SwiCh18 = 1u << 18, + SwiCh19 = 1u << 19, + SwiCh20 = 1u << 20, + SwiCh21 = 1u << 21, + SwiCh22 = 1u << 22, + SwiCh23 = 1u << 23, + SwiCh24 = 1u << 24, + SwiCh25 = 1u << 25, + SwiCh26 = 1u << 26, + SwiCh27 = 1u << 27, + SwiCh28 = 1u << 28, + SwiCh29 = 1u << 29, + SwiCh30 = 1u << 30, + SwiCh31 = 1u << 31, +}en_swi_ch_t; + +/** + ******************************************************************************* + ** \brief External Interrupt configuration + ** + ** \note The EXINT configuration + ******************************************************************************/ +typedef struct stc_exint_config +{ + en_exti_ch_t enExitCh; ///< External Int CH.0~15 ref@ en_exti_ch_t + en_functional_state_t enFilterEn; ///< TRUE: Enable filter function + en_ei_flt_clk_t enFltClk; ///< Filter clock, ref@ en_ei_flt_clk_t for details + en_exti_lvl_t enExtiLvl; ///< Detection level, ref@ en_exti_lvl_t for details +}stc_exint_config_t; + +/** + ******************************************************************************* + ** \brief Enumeration to NMI Trigger source + ** + ** \note + ******************************************************************************/ +typedef enum en_nmi_src +{ + NmiSrcNmi = 1u << 0, ///< NMI pin + NmiSrcSwdt = 1u << 1, ///< Special watch dog timer + NmiSrcVdu1 = 1u << 2, ///< Voltage detect 1 + NmiSrcVdu2 = 1u << 3, ///< Voltage detect 2 + NmiSrcXtalStop = 1u << 5, ///< Xtal stop + NmiSrcSramPE = 1u << 8, ///< SRAM1/2/HS/Ret parity error + NmiSrcSramDE = 1u << 9, ///< SRAM3 ECC error + NmiSrcMpu = 1u << 10, ///< MPU error + NmiSrcWdt = 1u << 11, ///< Watch dog timer +}en_nmi_src_t; + +/** + ******************************************************************************* + ** \brief Enumeration to software interrupt or event + ** + ** \note + ******************************************************************************/ +typedef enum en_swi_type +{ + SwEvent = 0u, ///< software event + SwInt = 1u, ///< software interrupt +}en_swi_type_t; + + +/** + ******************************************************************************* + ** \brief NMI configuration + ** + ** \note The NMI configuration + ******************************************************************************/ +typedef struct stc_nmi_config +{ + en_functional_state_t enFilterEn; ///< TRUE: Enable filter function + en_ei_flt_clk_t enFilterClk; ///< Filter clock, ref@ en_flt_clk_t for details + en_nmi_lvl_t enNmiLvl; ///< Detection level, ref@ en_nmi_lvl_t for details + uint16_t u16NmiSrc; ///< NMI trigger source, ref@ en_nmi_src_t for details + func_ptr_t pfnNmiCallback; ///< Callback pointers +}stc_nmi_config_t; + +/** + ******************************************************************************* + ** \brief SWI configuration + ** + ** \note The SWI configuration + ******************************************************************************/ +typedef struct stc_swi_config +{ + en_swi_ch_t enSwiCh; ///< SWI channel + en_swi_type_t enSwiType; ///< Select software interrupt or event + func_ptr_t pfnSwiCallback; ///< Callback pointers +}stc_swi_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig); +extern en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint); +extern en_result_t EXINT_IrqFlgClr(en_exti_ch_t enExint); +extern en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig); +extern en_result_t NMI_DeInit(void); +extern en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc); +extern en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc); +extern en_result_t SWI_Enable(uint32_t u32SwiCh); +extern en_result_t SWI_Disable(uint32_t u32SwiCh); + +//@} // ExintNmiSwiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +#endif /* __HC32F460_EXINT_NMI_SWI_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_gpio.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_gpio.h new file mode 100644 index 0000000000..b553de1167 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_gpio.h @@ -0,0 +1,294 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_gpio.h + ** + ** A detailed description is available at + ** @link GpioGroup Gpio description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of Gpio. + ** + ******************************************************************************/ + +#ifndef __HC32F460_GPIO_H__ +#define __HC32F460_GPIO_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_GPIO_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup GpioGroup General Purpose Input/Output(GPIO) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief GPIO Configuration Mode enumeration + ** + ******************************************************************************/ +typedef enum en_pin_mode +{ + Pin_Mode_In = 0, ///< GPIO Input mode + Pin_Mode_Out = 1, ///< GPIO Output mode + Pin_Mode_Ana = 2, ///< GPIO Analog mode +}en_pin_mode_t; + +/** + ******************************************************************************* + ** \brief GPIO Drive Capacity enumeration + ** + ******************************************************************************/ +typedef enum en_pin_drv +{ + Pin_Drv_L = 0, ///< Low Drive Capacity + Pin_Drv_M = 1, ///< Middle Drive Capacity + Pin_Drv_H = 2, ///< High Drive Capacity +}en_pin_drv_t; + +/** + ******************************************************************************* + ** \brief GPIO Output Type enumeration + ******************************************************************************/ +typedef enum en_pin_o_type +{ + Pin_OType_Cmos = 0, ///< CMOS + Pin_OType_Od = 1, ///< Open Drain +}en_pin_o_type_t; + + +typedef enum en_debug_port +{ + TCK_SWCLK = 1 << 0, ///< TCK or SWCLK + TMS_SWDIO = 1 << 1, ///< TMS or SWDIO + TDO_SWO = 1 << 2, ///< TOD or SWD + TDI = 1 << 3, ///< TDI + TRST = 1 << 4, ///< TRest + ALL_DBG_PIN = 0x1Fu ///< All above +}en_debug_port_t; +/** + ******************************************************************************* + ** \brief GPIO Port Index enumeration + ******************************************************************************/ +typedef enum en_port +{ + PortA = 0, ///< port group A + PortB = 1, ///< port group B + PortC = 2, ///< port group C + PortD = 3, ///< port group D + PortE = 4, ///< port group E + PortH = 5, ///< port group H +}en_port_t; + +/** + ******************************************************************************* + ** \brief GPIO Pin Index enumeration + ******************************************************************************/ +typedef enum en_pin +{ + Pin00 = (1 << 0), ///< Pin index 00 of each port group + Pin01 = (1 << 1), ///< Pin index 01 of each port group + Pin02 = (1 << 2), ///< Pin index 02 of each port group + Pin03 = (1 << 3), ///< Pin index 03 of each port group + Pin04 = (1 << 4), ///< Pin index 04 of each port group + Pin05 = (1 << 5), ///< Pin index 05 of each port group + Pin06 = (1 << 6), ///< Pin index 06 of each port group + Pin07 = (1 << 7), ///< Pin index 07 of each port group + Pin08 = (1 << 8), ///< Pin index 08 of each port group + Pin09 = (1 << 9), ///< Pin index 09 of each port group + Pin10 = (1 << 10), ///< Pin index 10 of each port group + Pin11 = (1 << 11), ///< Pin index 11 of each port group + Pin12 = (1 << 12), ///< Pin index 12 of each port group + Pin13 = (1 << 13), ///< Pin index 13 of each port group + Pin14 = (1 << 14), ///< Pin index 14 of each port group + Pin15 = (1 << 15), ///< Pin index 15 of each port group + PinAll= 0xFFFF, ///< All pins selected +}en_pin_t; + +/** + ******************************************************************************* + ** \brief GPIO Pin read wait cycle enumeration + ******************************************************************************/ +typedef enum en_read_wait +{ + WaitCycle0 = 0, ///< no wait cycle, operation freq. lower than 42MHz + WaitCycle1 = 1, ///< one wait cycle, operation freq. @[42~84)MHz + WaitCycle2 = 2, ///< two wait cycles, operation freq. @[84~126)MHz + WaitCycle3 = 3, ///< three wait cycles, operation freq. @[126~200)MHz +}en_read_wait_t; + +/** + ******************************************************************************* + ** \brief GPIO Function enumeration + ******************************************************************************/ +typedef enum en_port_func +{ + Func_Gpio = 0u, ///< function set to gpio + Func_Fcmref = 1u, ///< function set to fcm reference + Func_Rtcout = 1u, ///< function set to rtc output + Func_Vcout = 1u, ///< function set to vc output + Func_Adtrg = 1u, ///< function set to adc trigger + Func_Mclkout = 1u, ///< function set to mclk output + Func_Tim4 = 2u, ///< function set to timer4 + Func_Tim6 = 3u, ///< function set to timer6 + Func_Tima0 = 4u, ///< function set to timerA + Func_Tima1 = 5u, ///< function set to timerA + Func_Tima2 = 6u, ///< function set to timerA + Func_Emb = 6u, ///< function set to emb + Func_Usart_Ck = 7u, ///< function set to usart clk + Func_Spi_Nss = 7u, ///< function set to spi nss + Func_Qspi = 7u, ///< function set to qspi + Func_Key = 8u, ///< function set to key + Func_Sdio = 9u, ///< function set to sdio + Func_I2s = 10u, ///< function set to i2s + Func_UsbF = 10u, ///< function set to usb full speed + Func_Evnpt = 14u, ///< function set to event port + Func_Eventout = 15u, ///< function set to event out + Func_Usart1_Tx = 32u, ///< function set to usart tx of ch.1 + Func_Usart3_Tx = 32u, ///< function set to usart tx of ch.3 + Func_Usart1_Rx = 33u, ///< function set to usart rx of ch.1 + Func_Usart3_Rx = 33u, ///< function set to usart rx of ch.3 + Func_Usart1_Rts = 34u, ///< function set to usart rts of ch.1 + Func_Usart3_Rts = 34u, ///< function set to usart rts of ch.3 + Func_Usart1_Cts = 35u, ///< function set to usart cts of ch.1 + Func_Usart3_Cts = 35u, ///< function set to usart cts of ch.3 + Func_Usart2_Tx = 36u, ///< function set to usart tx of ch.2 + Func_Usart4_Tx = 36u, ///< function set to usart tx of ch.4 + Func_Usart2_Rx = 37u, ///< function set to usart rx of ch.2 + Func_Usart4_Rx = 37u, ///< function set to usart rx of ch.4 + Func_Usart2_Rts = 38u, ///< function set to usart rts of ch.2 + Func_Usart4_Rts = 38u, ///< function set to usart rts of ch.4 + Func_Usart2_Cts = 39u, ///< function set to usart cts of ch.2 + Func_Usart4_Cts = 39u, ///< function set to usart cts of ch.4 + Func_Spi1_Mosi = 40u, ///< function set to spi mosi of ch.1 + Func_Spi3_Mosi = 40u, ///< function set to spi mosi of ch.3 + Func_Spi1_Miso = 41u, ///< function set to spi miso of ch.1 + Func_Spi3_Miso = 41u, ///< function set to spi miso of ch.3 + Func_Spi1_Nss0 = 42u, ///< function set to spi nss0 of ch.1 + Func_Spi3_Nss0 = 42u, ///< function set to spi nss0 of ch.3 + Func_Spi1_Sck = 43u, ///< function set to spi sck of ch.1 + Func_Spi3_Sck = 43u, ///< function set to spi sck of ch.3 + Func_Spi2_Mosi = 44u, ///< function set to spi mosi of ch.2 + Func_Spi4_Mosi = 44u, ///< function set to spi mosi of ch.2 + Func_Spi2_Miso = 45u, ///< function set to spi miso of ch.4 + Func_Spi4_Miso = 45u, ///< function set to spi miso of ch.4 + Func_Spi2_Nss0 = 46u, ///< function set to spi nss0 of ch.2 + Func_Spi4_Nss0 = 46u, ///< function set to spi nss0 of ch.4 + Func_Spi2_Sck = 47u, ///< function set to spi sck of ch.2 + Func_Spi4_Sck = 47u, ///< function set to spi sck of ch.4 + Func_I2c1_Sda = 48u, ///< function set to i2c sda of ch.1 + Func_I2c3_Sda = 48u, ///< function set to i2c sda of ch.3 + Func_I2c1_Scl = 49u, ///< function set to i2c scl of ch.1 + Func_I2c3_Scl = 49u, ///< function set to i2c scl of ch.3 + Func_I2c2_Sda = 50u, ///< function set to i2c sda of ch.2 + Func_Can1_Tx = 50u, ///< function set to can tx of ch.1 + Func_I2c2_Scl = 51u, ///< function set to i2c scl of ch.2 + Func_Can1_Rx = 51u, ///< function set to can rx of ch.1 + Func_I2s1_Sd = 52u, ///< function set to i2s sd of ch.1 + Func_I2s3_Sd = 52u, ///< function set to i2s sd of ch.3 + Func_I2s1_Sdin = 53u, ///< function set to i2s sdin of ch.1 + Func_I2s3_Sdin = 53u, ///< function set to i2s sdin of ch.3 + Func_I2s1_Ws = 54u, ///< function set to i2s ws of ch.1 + Func_I2s3_Ws = 54u, ///< function set to i2s ws of ch.3 + Func_I2s1_Ck = 55u, ///< function set to i2s ck of ch.1 + Func_I2s3_Ck = 55u, ///< function set to i2s ck of ch.3 + Func_I2s2_Sd = 56u, ///< function set to i2s sd of ch.2 + Func_I2s4_Sd = 56u, ///< function set to i2s sd of ch.4 + Func_I2s2_Sdin = 57u, ///< function set to i2s sdin of ch.2 + Func_I2s4_Sdin = 57u, ///< function set to i2s sdin of ch.4 + Func_I2s2_Ws = 58u, ///< function set to i2s ws of ch.2 + Func_I2s4_Ws = 58u, ///< function set to i2s ws of ch.4 + Func_I2s2_Ck = 59u, ///< function set to i2s ck of ch.2 + Func_I2s4_Ck = 59u, ///< function set to i2s ck of ch.4 +}en_port_func_t; + +/** + ******************************************************************************* + ** \brief GPIO init structure definition + ******************************************************************************/ +typedef struct stc_port_init +{ + en_pin_mode_t enPinMode; ///< Set pin mode @ref en_pin_mode_t + en_functional_state_t enLatch; ///< Pin output latch enable + en_functional_state_t enExInt; ///< External int enable + en_functional_state_t enInvert; ///< Pin input/output invert enable + en_functional_state_t enPullUp; ///< Internal pull-up resistor enable + en_pin_drv_t enPinDrv; ///< Drive capacity setting @ref en_pin_drv_t + en_pin_o_type_t enPinOType; ///< Output mode setting @ref en_pin_o_type_t + en_functional_state_t enPinSubFunc; ///< Pin sub-function enable +}stc_port_init_t; + +/** + ******************************************************************************* + ** \brief GPIO public setting structure definition + ******************************************************************************/ +typedef struct stc_port_pub_set +{ + en_port_func_t enSubFuncSel; ///< Sub-function setting @ref en_port_func_t + en_read_wait_t enReadWait; ///< Read wait cycle setting @ref en_read_wait_t +}stc_port_pub_set_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, \ + const stc_port_init_t *pstcPortInit); +extern en_result_t PORT_DeInit(void); +extern void PORT_Unlock(void); +extern void PORT_Lock(void); +extern en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc); +extern en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet); +extern uint16_t PORT_GetData(en_port_t enPort); +extern en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin); +extern en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState); +extern en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin); +extern en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, \ + en_port_func_t enFuncSel, en_functional_state_t enSubFunc); +extern en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel); + +//@} // GpioGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_GPIO_ENABLE */ + +#endif /* __HC32F460_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_hash.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_hash.h new file mode 100644 index 0000000000..8ee1ce44db --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_hash.h @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_hash.h + ** + ** A detailed description is available at + ** @link HashGroup Hash description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of Hash. + ** + ******************************************************************************/ +#ifndef __HC32F460_HASH_H__ +#define __HC32F460_HASH_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_HASH_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup HashGroup Hash(HASH) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void HASH_Init(void); +void HASH_DeInit(void); +en_result_t HASH_Start(const uint8_t *pu8SrcData, + uint32_t u32SrcDataSize, + uint8_t *pu8MsgDigest, + uint32_t u32Timeout); + +//@} // HashGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_HASH_ENABLE */ + +#endif /* __HC32F460_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2c.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2c.h new file mode 100644 index 0000000000..dc8ea44b52 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2c.h @@ -0,0 +1,270 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2c.h + ** + ** A detailed description is available at + ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of I2C. + ** + ******************************************************************************/ + +#ifndef __HC32F460_I2C_H__ +#define __HC32F460_I2C_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_I2C_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup I2cGroup Inter-Integrated Circuit (I2C) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief I2c configuration structure + ** + ******************************************************************************/ +typedef struct stc_i2c_init +{ + uint32_t u32ClockDiv; ///< I2C clock division for i2c source clock + uint32_t u32Baudrate; ///< I2C baudrate config + uint32_t u32SclTime; ///< The SCL rising and falling time, count of T(i2c source clock after frequency divider) +}stc_i2c_init_t; + +/** + ******************************************************************************* + ** \brief I2c SMBUS configuration structure + ** + ******************************************************************************/ +typedef struct stc_i2c_smbus_init +{ + en_functional_state_t enHostAdrMatchFunc; ///< SMBUS host address matching function + en_functional_state_t enDefaultAdrMatchFunc; ///< SMBUS default address matching function + en_functional_state_t enAlarmAdrMatchFunc; ///< SMBUS Alarm address matching function +}stc_i2c_smbus_init_t; + +/** + ******************************************************************************* + ** \brief I2c digital filter mode enumeration + ** + ******************************************************************************/ +typedef enum en_i2c_digital_filter_mode +{ + Filter1BaseCycle = 0u, ///< I2C digital filter ability 1 base cycle + Filter2BaseCycle = 1u, ///< I2C digital filter ability 2 base cycle + Filter3BaseCycle = 2u, ///< I2C digital filter ability 3 base cycle + Filter4BaseCycle = 3u, ///< I2C digital filter ability 4 base cycle +}en_i2c_digital_filter_mode_t; + +/** + ******************************************************************************* + ** \brief I2c address bit enumeration + ** + ******************************************************************************/ +typedef enum en_address_bit +{ + Adr7bit = 0u, ///< I2C address length is 7 bits + Adr10bit = 1u, ///< I2C address length is 10 bits +}en_address_bit_t; + +/** + ******************************************************************************* + ** \brief I2c transfer direction enumeration + ** + ******************************************************************************/ +typedef enum en_trans_direction +{ + I2CDirTrans = 0u, + I2CDirReceive = 1u, +}en_trans_direction_t; + +/** + ******************************************************************************* + ** \brief I2c clock timeout switch enumeration + ** + ******************************************************************************/ +typedef enum en_clock_timeout_switch +{ + TimeoutFunOff = 0u, ///< I2C SCL pin time out function off + LowTimerOutOn = 3u, ///< I2C SCL pin high level time out function on + HighTimeOutOn = 5u, ///< I2C SCL pin low level time out function on + BothTimeOutOn = 7u, ///< I2C SCL pin both(low and high) level time out function on +}en_clock_timeout_switch_t; + +/** + ******************************************************************************* + ** \brief I2c clock timeout initialize structure + ** + ******************************************************************************/ +typedef struct stc_clock_timeout_init +{ + en_clock_timeout_switch_t enClkTimeOutSwitch; ///< I2C clock timeout function switch + uint16_t u16TimeOutHigh; ///< I2C clock timeout period for High level + uint16_t u16TimeOutLow; ///< I2C clock timeout period for Low level +}stc_clock_timeout_init_t; + +/** + ******************************************************************************* + ** \brief I2c ACK config enumeration + ** + ******************************************************************************/ +typedef enum en_i2c_ack_config +{ + I2c_ACK = 0u, + I2c_NACK = 1u, +}en_i2c_ack_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* define interrupt enable bit for I2C_CR2 register */ +#define I2C_CR2_STARTIE (0x00000001ul) +#define I2C_CR2_SLADDR0EN (0x00000002ul) +#define I2C_CR2_SLADDR1EN (0x00000004ul) +#define I2C_CR2_TENDIE (0x00000008ul) +#define I2C_CR2_STOPIE (0x00000010ul) +#define I2C_CR2_RFULLIE (0x00000040ul) +#define I2C_CR2_TEMPTYIE (0x00000080ul) +#define I2C_CR2_ARLOIE (0x00000200ul) +#define I2C_CR2_NACKIE (0x00001000ul) +#define I2C_CR2_TMOURIE (0x00004000ul) +#define I2C_CR2_GENCALLIE (0x00100000ul) +#define I2C_CR2_SMBDEFAULTIE (0x00200000ul) +#define I2C_CR2_SMBHOSTIE (0x00400000ul) +#define I2C_CR2_SMBALRTIE (0x00800000ul) + +/* define status bit for I2C_SR register */ +#define I2C_SR_STARTF (0x00000001ul) +#define I2C_SR_SLADDR0F (0x00000002ul) +#define I2C_SR_SLADDR1F (0x00000004ul) +#define I2C_SR_TENDF (0x00000008ul) +#define I2C_SR_STOPF (0x00000010ul) +#define I2C_SR_RFULLF (0x00000040ul) +#define I2C_SR_TEMPTYF (0x00000080ul) +#define I2C_SR_ARLOF (0x00000200ul) +#define I2C_SR_ACKRF (0x00000400ul) +#define I2C_SR_NACKF (0x00001000ul) +#define I2C_SR_TMOUTF (0x00004000ul) +#define I2C_SR_MSL (0x00010000ul) +#define I2C_SR_BUSY (0x00020000ul) +#define I2C_SR_TRA (0x00040000ul) +#define I2C_SR_GENCALLF (0x00100000ul) +#define I2C_SR_SMBDEFAULTF (0x00200000ul) +#define I2C_SR_SMBHOSTF (0x00400000ul) +#define I2C_SR_SMBALRTF (0x00800000ul) + +/* define status clear bit for I2C_CLR register*/ +#define I2C_CLR_STARTFCLR (0x00000001ul) +#define I2C_CLR_SLADDR0FCLR (0x00000002ul) +#define I2C_CLR_SLADDR1FCLR (0x00000004ul) +#define I2C_CLR_TENDFCLR (0x00000008ul) +#define I2C_CLR_STOPFCLR (0x00000010ul) +#define I2C_CLR_RFULLFCLR (0x00000040ul) +#define I2C_CLR_TEMPTYFCLR (0x00000080ul) +#define I2C_CLR_ARLOFCLR (0x00000200ul) +#define I2C_CLR_NACKFCLR (0x00001000ul) +#define I2C_CLR_TMOUTFCLR (0x00004000ul) +#define I2C_CLR_GENCALLFCLR (0x00100000ul) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000ul) +#define I2C_CLR_SMBHOSTFCLR (0x00400000ul) +#define I2C_CLR_SMBALRTFCLR (0x00800000ul) +#define I2C_CLR_MASK (0x00F056DFul) + +/* I2C_Clock_Division I2C clock division */ +#define I2C_CLK_DIV1 (0ul) /* I2c source clock/1 */ +#define I2C_CLK_DIV2 (1ul) /* I2c source clock/2 */ +#define I2C_CLK_DIV4 (2ul) /* I2c source clock/4 */ +#define I2C_CLK_DIV8 (3ul) /* I2c source clock/8 */ +#define I2C_CLK_DIV16 (4ul) /* I2c source clock/16 */ +#define I2C_CLK_DIV32 (5ul) /* I2c source clock/32 */ +#define I2C_CLK_DIV64 (6ul) /* I2c source clock/64 */ +#define I2C_CLK_DIV128 (7ul) /* I2c source clock/128 */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error); +en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx); +en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error); +void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct); +void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); + +//////////////////////////////////////////////////////////////////////////////////////// +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode); +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr); +void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr); +en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit); +void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState); +void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); + +/////////////////////////////////////////////////////////////////////////////////////// +void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState); +void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data); +uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx); +void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig); +en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit); +void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit); + +/* High level functions for reference ********************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout); +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout); +en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout); +en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); +en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); + +//@} // I2cGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_I2C_ENABLE */ + +#endif /* __HC32F460_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2s.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2s.h new file mode 100644 index 0000000000..210cf667e1 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_i2s.h @@ -0,0 +1,206 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2s.h + ** + ** A detailed description is available at + ** @link I2sGroup Inter-IC Sound Bus description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of I2S. + ** + ******************************************************************************/ + +#ifndef __HC32F460_I2S_H__ +#define __HC32F460_I2S_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_I2S_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup I2sGroup Inter-IC Sound(I2S) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief I2S function + ******************************************************************************/ +typedef enum en_i2s_func +{ + TxEn = 0u, ///< Transfer enable function + TxIntEn = 1u, ///< Transfer interrupt enable function + RxEn = 2u, ///< receive enable function + RxIntEn = 3u, ///< receive interrupt enable function + ErrIntEn = 4u, ///< error interrupt enable function +}en_i2s_func_t; + + +/** + ******************************************************************************* + ** \brief I2S status flag + ******************************************************************************/ +typedef enum en_i2s_std +{ + TxBufAlarmFlag = 0u, + RxBufAlarmFlag = 1u, + TxBufEmptFlag = 2u, + TxBufFullFlag = 3u, + RxBufEmptFlag = 4u, + RxBufFullFlag = 5u, +}en_i2s_std_t; + +/** + ******************************************************************************* + ** \brief I2S clr flag + ******************************************************************************/ +typedef enum en_i2s_err_flag +{ + ClrTxErrFlag = 0u, + ClrRxErrFlag = 1u, +}en_i2s_err_flag_t; +/** + ******************************************************************************* + ** \brief I2S mode + ******************************************************************************/ +typedef enum en_i2s_mode +{ + I2sMaster = 0u, ///< I2S Master mode + I2sSlave = 1u, ///< I2S Slave mode +}en_i2s_mode_t; + +/** + ******************************************************************************* + ** \brief I2S full duplex mode + ******************************************************************************/ +typedef enum en_i2s_full_duplex_mode +{ + I2s_HalfDuplex = 0u, ///< I2S half duplex + I2s_FullDuplex = 1u, ///< I2S full duplex +}en_i2s_full_duplex_mode_t; + +/** + ******************************************************************************* + ** \brief I2S standard + ******************************************************************************/ +typedef enum en_i2s_standard +{ + Std_Philips = 0u, ///< I2S Philips standard + Std_MSBJust = 1u, ///< I2S MSB justified standart + Std_LSBJust = 2u, ///< I2S LSB justified standart + Std_PCM = 3u, ///< I2S PCM standart +}en_i2s_standard_t; + +/** + ******************************************************************************* + ** \brief I2S channel data length + ******************************************************************************/ +typedef enum en_i2s_ch_len +{ + I2s_ChLen_16Bit = 0u, + I2s_ChLen_32Bit = 1u, +}en_i2s_ch_len_t; + +/** + ******************************************************************************* + ** \brief I2S data length + ******************************************************************************/ +typedef enum en_i2s_data_len +{ + I2s_DataLen_16Bit = 0u, + I2s_DataLen_24Bit = 1u, + I2s_DataLen_32Bit = 2u, +}en_i2s_data_len_t; + +/** + ******************************************************************************* + ** \brief I2S configuration structure + ******************************************************************************/ +typedef struct stc_i2s_config +{ + en_i2s_mode_t enMode; ///< I2S mode + en_i2s_full_duplex_mode_t enFullDuplexMode; ///< I2S full duplex mode + uint32_t u32I2sInterClkFreq; ///< I2S internal clock frequency + en_i2s_standard_t enStandrad; ///< I2S standard + en_i2s_data_len_t enDataBits; ///< I2S data format, data bits + en_i2s_ch_len_t enChanelLen; ///< I2S channel length + en_functional_state_t enMcoOutEn; ///< I2S MCK output config + en_functional_state_t enExckEn; ///< I2S EXCK function config + uint32_t u32AudioFreq; ///< I2S audio frequecy +}stc_i2s_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* define audio frequency */ +#define I2S_AudioFreq_192k (192000ul) +#define I2S_AudioFreq_96k (96000ul) +#define I2S_AudioFreq_48k (48000ul) +#define I2S_AudioFreq_44k (44100ul) +#define I2S_AudioFreq_32k (32000ul) +#define I2S_AudioFreq_22k (22050ul) +#define I2S_AudioFreq_16k (16000ul) +#define I2S_AudioFreq_11k (11025ul) +#define I2S_AudioFreq_8k (8000ul) +#define I2S_AudioFreq_Default (2ul) + +/* if use external clock open this define */ +#define I2S_EXTERNAL_CLOCK_VAL (12288000ul) + +/* 0,1 or 2 config for tx or tx buffer interrupt warning level */ +#define RXBUF_IRQ_WL (1ul) +#define TXBUF_IRQ_WL (1ul) + +/* 0: Short frame synchronization; 1: Long frame synchronization */ +#define PCM_SYNC_FRAME (0ul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg); +void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data); +uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg); +void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, en_functional_state_t enNewState); +en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd); +en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag); +void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag); +en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg); + +//@} // I2sGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_I2S_ENABLE */ + +#endif /* __HC32F460_I2S_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_icg.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_icg.h new file mode 100644 index 0000000000..d0c4c16636 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_icg.h @@ -0,0 +1,400 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_icg.h + ** + ** A detailed description is available at + ** @link IcgGroup Initialize configure description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of ICG. + ** + ******************************************************************************/ +#ifndef __HC32F460_ICG_H__ +#define __HC32F460_ICG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_ICG_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup IcgGroup Initialize Configure(ICG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT running state after reset + ******************************************************************************/ +#define SWDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< SWDT Auto Start after reset +#define SWDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< SWDT stop after reset + +/** + ******************************************************************************* + ** \brief SWDT count underflow or refresh error trigger event type + ******************************************************************************/ +#define SWDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request +#define SWDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request + +/** + ******************************************************************************* + ** \brief SWDT count underflow cycle + ******************************************************************************/ +#define SWDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle +#define SWDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle + +/** + ******************************************************************************* + ** \brief SWDT count clock division + ******************************************************************************/ +#define SWDT_COUNT_SWDTCLK_DIV1 ((uint16_t)0x0000) ///< SWDTCLK +#define SWDT_COUNT_SWDTCLK_DIV16 ((uint16_t)0x0040) ///< SWDTCLK/16 +#define SWDT_COUNT_SWDTCLK_DIV32 ((uint16_t)0x0050) ///< SWDTCLK/32 +#define SWDT_COUNT_SWDTCLK_DIV64 ((uint16_t)0x0060) ///< SWDTCLK/64 +#define SWDT_COUNT_SWDTCLK_DIV128 ((uint16_t)0x0070) ///< SWDTCLK/128 +#define SWDT_COUNT_SWDTCLK_DIV256 ((uint16_t)0x0080) ///< SWDTCLK/256 +#define SWDT_COUNT_SWDTCLK_DIV2048 ((uint16_t)0x00B0) ///< SWDTCLK/2048 + +/** + ******************************************************************************* + ** \brief SWDT allow refresh percent range + ******************************************************************************/ +#define SWDT_100PCT ((uint16_t)0x0000) ///< 100% +#define SWDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25% +#define SWDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50% +#define SWDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50% +#define SWDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75% +#define SWDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75% +#define SWDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75% +#define SWDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75% +#define SWDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100% +#define SWDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100% +#define SWDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100% +#define SWDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100% +#define SWDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100% +#define SWDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100% +#define SWDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100% +#define SWDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100% + +/** + ******************************************************************************* + ** \brief SWDT count control in the sleep/stop mode + ******************************************************************************/ +#define SWDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< SWDT count continue in the sleep/stop mode +#define SWDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< SWDT count stop in the sleep/stop mode + +/** + ******************************************************************************* + ** \brief WDT running state after reset + ******************************************************************************/ +#define WDT_AUTO_START_AFTER_RESET ((uint16_t)0x0000) ///< WDT Auto Start after reset +#define WDT_STOP_AFTER_RESET ((uint16_t)0x0001) ///< WDT stop after reset + +/** + ******************************************************************************* + ** \brief WDT count underflow or refresh error trigger event type + ******************************************************************************/ +#define WDT_INTERRUPT_REQUEST ((uint16_t)0x0000) ///< WDT trigger interrupt request +#define WDT_RESET_REQUEST ((uint16_t)0x0002) ///< WDT trigger reset request + +/** + ******************************************************************************* + ** \brief WDT count underflow cycle + ******************************************************************************/ +#define WDT_COUNT_UNDERFLOW_CYCLE_256 ((uint16_t)0x0000) ///< 256 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_4096 ((uint16_t)0x0004) ///< 4096 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_16384 ((uint16_t)0x0008) ///< 16384 clock cycle +#define WDT_COUNT_UNDERFLOW_CYCLE_65536 ((uint16_t)0x000C) ///< 65536 clock cycle + +/** + ******************************************************************************* + ** \brief WDT count clock division + ******************************************************************************/ +#define WDT_COUNT_PCLK3_DIV4 ((uint16_t)0x0020) ///< PCLK3/4 +#define WDT_COUNT_PCLK3_DIV64 ((uint16_t)0x0060) ///< PCLK3/64 +#define WDT_COUNT_PCLK3_DIV128 ((uint16_t)0x0070) ///< PCLK3/128 +#define WDT_COUNT_PCLK3_DIV256 ((uint16_t)0x0080) ///< PCLK3/256 +#define WDT_COUNT_PCLK3_DIV512 ((uint16_t)0x0090) ///< PCLK3/512 +#define WDT_COUNT_PCLK3_DIV1024 ((uint16_t)0x00A0) ///< PCLK3/1024 +#define WDT_COUNT_PCLK3_DIV2048 ((uint16_t)0x00B0) ///< PCLK3/2048 +#define WDT_COUNT_PCLK3_DIV8192 ((uint16_t)0x00D0) ///< PCLK3/8192 + +/** + ******************************************************************************* + ** \brief WDT allow refresh percent range + ******************************************************************************/ +#define WDT_100PCT ((uint16_t)0x0000) ///< 100% +#define WDT_0To25PCT ((uint16_t)0x0100) ///< 0%~25% +#define WDT_25To50PCT ((uint16_t)0x0200) ///< 25%~50% +#define WDT_0To50PCT ((uint16_t)0x0300) ///< 0%~50% +#define WDT_50To75PCT ((uint16_t)0x0400) ///< 50%~75% +#define WDT_0To25PCT_50To75PCT ((uint16_t)0x0500) ///< 0%~25% & 50%~75% +#define WDT_25To75PCT ((uint16_t)0x0600) ///< 25%~75% +#define WDT_0To75PCT ((uint16_t)0x0700) ///< 0%~75% +#define WDT_75To100PCT ((uint16_t)0x0800) ///< 75%~100% +#define WDT_0To25PCT_75To100PCT ((uint16_t)0x0900) ///< 0%~25% & 75%~100% +#define WDT_25To50PCT_75To100PCT ((uint16_t)0x0A00) ///< 25%~50% & 75%~100% +#define WDT_0To50PCT_75To100PCT ((uint16_t)0x0B00) ///< 0%~50% & 75%~100% +#define WDT_50To100PCT ((uint16_t)0x0C00) ///< 50%~100% +#define WDT_0To25PCT_50To100PCT ((uint16_t)0x0D00) ///< 0%~25% & 50%~100% +#define WDT_25To100PCT ((uint16_t)0x0E00) ///< 25%~100% +#define WDT_0To100PCT ((uint16_t)0x0F00) ///< 0%~100% + +/** + ******************************************************************************* + ** \brief WDT count control in the sleep mode + ******************************************************************************/ +#define WDT_SPECIAL_MODE_COUNT_CONTINUE ((uint16_t)0x0000) ///< WDT count continue in the sleep mode +#define WDT_SPECIAL_MODE_COUNT_STOP ((uint16_t)0x1000) ///< WDT count stop in the sleep mode + +/** + ******************************************************************************* + ** \brief HRC frequency select + ******************************************************************************/ +#define HRC_FREQUENCY_20MHZ ((uint16_t)0x0000) ///< HRC frequency 20MHZ +#define HRC_FREQUENCY_16MHZ ((uint16_t)0x0001) ///< HRC frequency 16MHZ + +/** + ******************************************************************************* + ** \brief HRC oscillation state control + ******************************************************************************/ +#define HRC_OSCILLATION_START ((uint16_t)0x0000) ///< HRC oscillation start +#define HRC_OSCILLATION_STOP ((uint16_t)0x0100) ///< HRC oscillation stop + +/** + ******************************************************************************* + ** \brief VDU0 threshold voltage select + ******************************************************************************/ +#define VDU0_VOLTAGE_THRESHOLD_1P5 ((uint8_t)0x00) ///< VDU0 voltage threshold 1.9V +#define VDU0_VOLTAGE_THRESHOLD_2P0 ((uint8_t)0x01) ///< VDU0 voltage threshold 2.0V +#define VDU0_VOLTAGE_THRESHOLD_2P1 ((uint8_t)0x02) ///< VDU0 voltage threshold 2.1V +#define VDU0_VOLTAGE_THRESHOLD_2P3 ((uint8_t)0x03) ///< VDU0 voltage threshold 2.3V + +/** + ******************************************************************************* + ** \brief VDU0 running state after reset + ******************************************************************************/ +#define VDU0_START_AFTER_RESET ((uint8_t)0x00) ///< VDU0 start after reset +#define VDU0_STOP_AFTER_RESET ((uint8_t)0x04) ///< VDU0 stop after reset + +/** + ******************************************************************************* + ** \brief NMI pin filter sample clock division + ******************************************************************************/ +#define NMI_PIN_FILTER_PCLK3_DIV1 ((uint8_t)0x00) ///< PCLK3 +#define NMI_PIN_FILTER_PCLK3_DIV8 ((uint8_t)0x04) ///< PCLK3/8 +#define NMI_PIN_FILTER_PCLK3_DIV32 ((uint8_t)0x08) ///< PCLK3/32 +#define NMI_PIN_FILTER_PCLK3_DIV64 ((uint8_t)0x0C) ///< PCLK3/64 + +/** + ******************************************************************************* + ** \brief NMI pin trigger edge type + ******************************************************************************/ +#define NMI_PIN_TRIGGER_EDGE_FALLING ((uint8_t)0x00) ///< Falling edge trigger +#define NMI_PIN_TRIGGER_EDGE_RISING ((uint8_t)0x10) ///< Rising edge trigger + +/** + ******************************************************************************* + ** \brief Enable or disable NMI pin interrupt request + ******************************************************************************/ +#define NMI_PIN_IRQ_DISABLE ((uint8_t)0x00) ///< Disable NMI pin interrupt request +#define NMI_PIN_IRQ_ENABLE ((uint8_t)0x20) ///< Enable NMI pin interrupt request + +/** + ******************************************************************************* + ** \brief Enable or disable NMI digital filter function + ******************************************************************************/ +#define NMI_DIGITAL_FILTER_DISABLE ((uint8_t)0x00) ///< Disable NMI digital filter +#define NMI_DIGITAL_FILTER_ENABLE ((uint8_t)0x40) ///< Enable NMI digital filter + +/** + ******************************************************************************* + ** \brief Enable or disable NMI pin ICG function + ******************************************************************************/ +#define NMI_PIN_ICG_FUNCTION_DISABLE ((uint8_t)0x80) ///< Disable NMI pin ICG function +#define NMI_PIN_ICG_FUNCTION_ENABLE ((uint8_t)0x00) ///< Enable NMI pin ICG function + +/** + ******************************************************************************* + ** \brief ICG start configure function on/off + ******************************************************************************/ +#ifndef ICG_FUNCTION_ON +#define ICG_FUNCTION_ON (1u) +#endif + +#ifndef ICG_FUNCTION_OFF +#define ICG_FUNCTION_OFF (0u) +#endif + +/** + ******************************************************************************* + ** \brief SWDT hardware start configuration + ******************************************************************************/ +/*!< Enable or disable SWDT hardware start */ +#define ICG0_SWDT_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< SWDT register config */ +#define ICG0_SWDT_AUTS (SWDT_STOP_AFTER_RESET) +#define ICG0_SWDT_ITS (SWDT_RESET_REQUEST) +#define ICG0_SWDT_PERI (SWDT_COUNT_UNDERFLOW_CYCLE_16384) +#define ICG0_SWDT_CKS (SWDT_COUNT_SWDTCLK_DIV2048) +#define ICG0_SWDT_WDPT (SWDT_0To100PCT) +#define ICG0_SWDT_SLTPOFF (SWDT_SPECIAL_MODE_COUNT_STOP) + +/*!< SWDT register config value */ +#if ICG0_SWDT_HARDWARE_START == ICG_FUNCTION_ON +#define ICG0_SWDT_REG_CONFIG (ICG0_SWDT_AUTS | ICG0_SWDT_ITS | ICG0_SWDT_PERI | \ + ICG0_SWDT_CKS | ICG0_SWDT_WDPT | ICG0_SWDT_SLTPOFF) +#else +#define ICG0_SWDT_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief WDT hardware start configuration + ******************************************************************************/ +/*!< Enable or disable WDT hardware start */ +#define ICG0_WDT_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< WDT register config */ +#define ICG0_WDT_AUTS (WDT_STOP_AFTER_RESET) +#define ICG0_WDT_ITS (WDT_RESET_REQUEST) +#define ICG0_WDT_PERI (WDT_COUNT_UNDERFLOW_CYCLE_16384) +#define ICG0_WDT_CKS (WDT_COUNT_PCLK3_DIV8192) +#define ICG0_WDT_WDPT (WDT_0To100PCT) +#define ICG0_WDT_SLPOFF (WDT_SPECIAL_MODE_COUNT_STOP) + +/*!< WDT register config value */ +#if ICG0_WDT_HARDWARE_START == ICG_FUNCTION_ON +#define ICG0_WDT_REG_CONFIG (ICG0_WDT_AUTS | ICG0_WDT_ITS | ICG0_WDT_PERI | \ + ICG0_WDT_CKS | ICG0_WDT_WDPT | ICG0_WDT_SLPOFF) +#else +#define ICG0_WDT_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief HRC hardware start configuration + ******************************************************************************/ +/*!< Enable or disable HRC hardware start */ +#define ICG1_HRC_HARDWARE_START (ICG_FUNCTION_ON) + +/*!< HRC register config */ +#define ICG1_HRC_FREQSEL (HRC_FREQUENCY_16MHZ) +#define ICG1_HRC_STOP (HRC_OSCILLATION_START) + +/*!< HRC register config value */ +#if ICG1_HRC_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_HRC_REG_CONFIG (ICG1_HRC_FREQSEL | ICG1_HRC_STOP) +#else +#define ICG1_HRC_REG_CONFIG ((uint16_t)0xFFFF) +#endif + +/** + ******************************************************************************* + ** \brief VDU0 hardware start configuration + ******************************************************************************/ +/*!< Enable or disable VDU0 hardware start */ +#define ICG1_VDU0_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< VDU0 register config */ +#define ICG1_VDU0_BOR_LEV (VDU0_VOLTAGE_THRESHOLD_2P3) +#define ICG1_VDU0_BORDIS (VDU0_STOP_AFTER_RESET) + +/*!< VDU0 register config value */ +#if ICG1_VDU0_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_VDU0_REG_CONFIG (ICG1_VDU0_BOR_LEV | ICG1_VDU0_BORDIS) +#else +#define ICG1_VDU0_REG_CONFIG ((uint8_t)0xFF) +#endif + +/** + ******************************************************************************* + ** \brief NMI hardware start configuration + ******************************************************************************/ +/*!< Enable or disable NMI hardware start */ +#define ICG1_NMI_HARDWARE_START (ICG_FUNCTION_OFF) + +/*!< NMI register config */ +#define ICG1_NMI_SMPCLK (NMI_PIN_FILTER_PCLK3_DIV1) +#define ICG1_NMI_TRG (NMI_PIN_TRIGGER_EDGE_RISING) +#define ICG1_NMI_IMR (NMI_PIN_IRQ_DISABLE) +#define ICG1_NMI_NFEN (NMI_DIGITAL_FILTER_DISABLE) +#define ICG1_NMI_ICGENA (NMI_PIN_ICG_FUNCTION_DISABLE) + +/*!< NMI register config value */ +#if ICG1_NMI_HARDWARE_START == ICG_FUNCTION_ON +#define ICG1_NMI_REG_CONFIG (ICG1_NMI_SMPCLK | ICG1_NMI_TRG | \ + ICG1_NMI_IMR | ICG1_NMI_NFEN | ICG1_NMI_ICGENA) +#else +#define ICG1_NMI_REG_CONFIG ((uint8_t)0xFF) +#endif + +/** + ******************************************************************************* + ** \brief ICG registers configuration + ******************************************************************************/ +/*!< ICG0 register value */ +#define ICG0_REGISTER_CONSTANT (((uint32_t)ICG0_WDT_REG_CONFIG << 16) | \ + ((uint32_t)ICG0_SWDT_REG_CONFIG) | \ + ((uint32_t)0xE000E000ul)) +/*!< ICG1 register value */ +#define ICG1_REGISTER_CONSTANT (((uint32_t)ICG1_NMI_REG_CONFIG << 24) | \ + ((uint32_t)ICG1_VDU0_REG_CONFIG << 16) | \ + ((uint32_t)ICG1_HRC_REG_CONFIG) | \ + ((uint32_t)0x03F8FEFEul)) +/*!< ICG2~7 register reserved value */ +#define ICG2_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG3_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG4_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG5_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG6_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) +#define ICG7_REGISTER_CONSTANT ((uint32_t)0xFFFFFFFFul) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +//@} // IcgGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_ICG_ENABLE */ + +#endif /* __HC32F460_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_interrupts.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_interrupts.h new file mode 100644 index 0000000000..141b1d268e --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_interrupts.h @@ -0,0 +1,570 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_interrupts.h + ** + ** A detailed description is available at + ** @link InterruptGroup Interrupt description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of interrupt. + ** + ******************************************************************************/ +#ifndef __HC32F460_INTERRUPTS_H___ +#define __HC32F460_INTERRUPTS_H___ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup InterruptGroup Interrupt + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief IRQ registration structure definition + ******************************************************************************/ +typedef struct stc_irq_regi_conf +{ + en_int_src_t enIntSrc; + IRQn_Type enIRQn; + func_ptr_t pfnCallback; +}stc_irq_regi_conf_t; + +/** + ******************************************************************************* + ** \brief stop mode interrupt wakeup source enumeration + ******************************************************************************/ +typedef enum en_int_wkup_src +{ + Extint0WU = 1u << 0, + Extint1WU = 1u << 1, + Extint2WU = 1u << 2, + Extint3WU = 1u << 3, + Extint4WU = 1u << 4, + Extint5WU = 1u << 5, + Extint6WU = 1u << 6, + Extint7WU = 1u << 7, + Extint8WU = 1u << 8, + Extint9WU = 1u << 9, + Extint10WU = 1u << 10, + Extint11WU = 1u << 11, + Extint12WU = 1u << 12, + Extint13WU = 1u << 13, + Extint14WU = 1u << 14, + Extint15WU = 1u << 15, + SwdtWU = 1u << 16, + Vdu1WU = 1u << 17, + Vdu2WU = 1u << 18, + CmpWU = 1u << 19, + WakeupTimerWU = 1u << 20, + RtcAlarmWU = 1u << 21, + RtcPeriodWU = 1u << 22, + Timer0WU = 1u << 23, + Usart1RxWU = 1u << 25, +}en_int_wkup_src_t; + +/** + ******************************************************************************* + ** \brief event enumeration + ******************************************************************************/ +typedef enum en_evt +{ + Event0 = 1u << 0, + Event1 = 1u << 1, + Event2 = 1u << 2, + Event3 = 1u << 3, + Event4 = 1u << 4, + Event5 = 1u << 5, + Event6 = 1u << 6, + Event7 = 1u << 7, + Event8 = 1u << 8, + Event9 = 1u << 9, + Event10 = 1u << 10, + Event11 = 1u << 11, + Event12 = 1u << 12, + Event13 = 1u << 13, + Event14 = 1u << 14, + Event15 = 1u << 15, + Event16 = 1u << 16, + Event17 = 1u << 17, + Event18 = 1u << 18, + Event19 = 1u << 19, + Event20 = 1u << 20, + Event21 = 1u << 21, + Event22 = 1u << 22, + Event23 = 1u << 23, + Event24 = 1u << 24, + Event25 = 1u << 25, + Event26 = 1u << 26, + Event27 = 1u << 27, + Event28 = 1u << 28, + Event29 = 1u << 29, + Event30 = 1u << 30, + Event31 = 1u << 31, +}en_evt_t; + +/** + ******************************************************************************* + ** \brief interrupt enumeration + ******************************************************************************/ +typedef enum en_int +{ + Int0 = 1u << 0, + Int1 = 1u << 1, + Int2 = 1u << 2, + Int3 = 1u << 3, + Int4 = 1u << 4, + Int5 = 1u << 5, + Int6 = 1u << 6, + Int7 = 1u << 7, + Int8 = 1u << 8, + Int9 = 1u << 9, + Int10 = 1u << 10, + Int11 = 1u << 11, + Int12 = 1u << 12, + Int13 = 1u << 13, + Int14 = 1u << 14, + Int15 = 1u << 15, + Int16 = 1u << 16, + Int17 = 1u << 17, + Int18 = 1u << 18, + Int19 = 1u << 19, + Int20 = 1u << 20, + Int21 = 1u << 21, + Int22 = 1u << 22, + Int23 = 1u << 23, + Int24 = 1u << 24, + Int25 = 1u << 25, + Int26 = 1u << 26, + Int27 = 1u << 27, + Int28 = 1u << 28, + Int29 = 1u << 29, + Int30 = 1u << 30, + Int31 = 1u << 31, +}en_int_t; +/** + * @defgroup EXINT_Channel_Sel External interrupt channel selection + * @{ + */ +#define EXINT_CH00 (1UL << 0U) +#define EXINT_CH01 (1UL << 1U) +#define EXINT_CH02 (1UL << 2U) +#define EXINT_CH03 (1UL << 3U) +#define EXINT_CH04 (1UL << 4U) +#define EXINT_CH05 (1UL << 5U) +#define EXINT_CH06 (1UL << 6U) +#define EXINT_CH07 (1UL << 7U) +#define EXINT_CH08 (1UL << 8U) +#define EXINT_CH09 (1UL << 9U) +#define EXINT_CH10 (1UL <<10U) +#define EXINT_CH11 (1UL <<11U) +#define EXINT_CH12 (1UL <<12U) +#define EXINT_CH13 (1UL <<13U) +#define EXINT_CH14 (1UL <<14U) +#define EXINT_CH15 (1UL <<15U) +#define EXINT_CH_MASK (EXINT_CH00 | EXINT_CH01 | EXINT_CH02 | EXINT_CH03 | \ + EXINT_CH04 | EXINT_CH05 | EXINT_CH06 | EXINT_CH07 | \ + EXINT_CH08 | EXINT_CH09 | EXINT_CH10 | EXINT_CH11 | \ + EXINT_CH12 | EXINT_CH13 | EXINT_CH14 | EXINT_CH15) +/** + * @} + */ + + +/*! Bit mask definition*/ +#define BIT_MASK_00 (1ul << 0) +#define BIT_MASK_01 (1ul << 1) +#define BIT_MASK_02 (1ul << 2) +#define BIT_MASK_03 (1ul << 3) +#define BIT_MASK_04 (1ul << 4) +#define BIT_MASK_05 (1ul << 5) +#define BIT_MASK_06 (1ul << 6) +#define BIT_MASK_07 (1ul << 7) +#define BIT_MASK_08 (1ul << 8) +#define BIT_MASK_09 (1ul << 9) +#define BIT_MASK_10 (1ul << 10) +#define BIT_MASK_11 (1ul << 11) +#define BIT_MASK_12 (1ul << 12) +#define BIT_MASK_13 (1ul << 13) +#define BIT_MASK_14 (1ul << 14) +#define BIT_MASK_15 (1ul << 15) +#define BIT_MASK_16 (1ul << 16) +#define BIT_MASK_17 (1ul << 17) +#define BIT_MASK_18 (1ul << 18) +#define BIT_MASK_19 (1ul << 19) +#define BIT_MASK_20 (1ul << 20) +#define BIT_MASK_21 (1ul << 21) +#define BIT_MASK_22 (1ul << 22) +#define BIT_MASK_23 (1ul << 23) +#define BIT_MASK_24 (1ul << 24) +#define BIT_MASK_25 (1ul << 25) +#define BIT_MASK_26 (1ul << 26) +#define BIT_MASK_27 (1ul << 27) +#define BIT_MASK_28 (1ul << 28) +#define BIT_MASK_29 (1ul << 29) +#define BIT_MASK_30 (1ul << 30) +#define BIT_MASK_31 (1ul << 31) + +/*! Default Priority for IRQ, Possible values are 0 (high priority) to 15 (low priority) */ +#define DDL_IRQ_PRIORITY_DEFAULT 15u + +/*! Interrupt priority level 00 ~ 15*/ +#define DDL_IRQ_PRIORITY_00 (0u) +#define DDL_IRQ_PRIORITY_01 (1u) +#define DDL_IRQ_PRIORITY_02 (2u) +#define DDL_IRQ_PRIORITY_03 (3u) +#define DDL_IRQ_PRIORITY_04 (4u) +#define DDL_IRQ_PRIORITY_05 (5u) +#define DDL_IRQ_PRIORITY_06 (6u) +#define DDL_IRQ_PRIORITY_07 (7u) +#define DDL_IRQ_PRIORITY_08 (8u) +#define DDL_IRQ_PRIORITY_09 (9u) +#define DDL_IRQ_PRIORITY_10 (10u) +#define DDL_IRQ_PRIORITY_11 (11u) +#define DDL_IRQ_PRIORITY_12 (12u) +#define DDL_IRQ_PRIORITY_13 (13u) +#define DDL_IRQ_PRIORITY_14 (14u) +#define DDL_IRQ_PRIORITY_15 (15u) + +/** + ******************************************************************************* + ** \brief AOS software trigger function + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + bM4_AOS_INT_SFTTRG_STRG = 1u; +} + +/** + ******************************************************************************* + ** \brief AOS common trigger source 1 config. + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_COM_Trigger1(en_event_src_t enTrig) +{ + M4_AOS->COMTRG1 = enTrig; +} + +/** + ******************************************************************************* + ** \brief AOS common trigger source 2 config. + ** + ******************************************************************************/ +__STATIC_INLINE void AOS_COM_Trigger2(en_event_src_t enTrig) +{ + M4_AOS->COMTRG2 = enTrig; +} + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf); +extern en_result_t enIrqResign(IRQn_Type enIRQn); +extern en_result_t enShareIrqEnable(en_int_src_t enIntSrc); +extern en_result_t enShareIrqDisable(en_int_src_t enIntSrc); +extern en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc); +extern en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc); +extern en_result_t enEventEnable(uint32_t u32Event); +extern en_result_t enEventDisable(uint32_t u32Event); +extern en_result_t enIntEnable(uint32_t u32Int); +extern en_result_t enIntDisable(uint32_t u32Int); +extern en_flag_status_t EXINT_GetExIntSrc(uint32_t u32ExIntCh); +extern void EXINT_ClrExIntSrc(uint32_t u32ExIntCh); +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +__WEAKDEF void NMI_IrqHandler(void); +__WEAKDEF void HardFault_IrqHandler(void); +__WEAKDEF void MemManage_IrqHandler(void); +__WEAKDEF void BusFault_IrqHandler(void); +__WEAKDEF void UsageFault_IrqHandler(void); +__WEAKDEF void SVC_IrqHandler(void); +__WEAKDEF void DebugMon_IrqHandler(void); +__WEAKDEF void PendSV_IrqHandler(void); +__WEAKDEF void SysTick_IrqHandler(void); + +__WEAKDEF void Extint00_IrqHandler(void); +__WEAKDEF void Extint01_IrqHandler(void); +__WEAKDEF void Extint02_IrqHandler(void); +__WEAKDEF void Extint03_IrqHandler(void); +__WEAKDEF void Extint04_IrqHandler(void); +__WEAKDEF void Extint05_IrqHandler(void); +__WEAKDEF void Extint06_IrqHandler(void); +__WEAKDEF void Extint07_IrqHandler(void); +__WEAKDEF void Extint08_IrqHandler(void); +__WEAKDEF void Extint09_IrqHandler(void); +__WEAKDEF void Extint10_IrqHandler(void); +__WEAKDEF void Extint11_IrqHandler(void); +__WEAKDEF void Extint12_IrqHandler(void); +__WEAKDEF void Extint13_IrqHandler(void); +__WEAKDEF void Extint14_IrqHandler(void); +__WEAKDEF void Extint15_IrqHandler(void); + +__WEAKDEF void Dma1Tc0_IrqHandler(void); +__WEAKDEF void Dma1Tc1_IrqHandler(void); +__WEAKDEF void Dma1Tc2_IrqHandler(void); +__WEAKDEF void Dma1Tc3_IrqHandler(void); +__WEAKDEF void Dma2Tc0_IrqHandler(void); +__WEAKDEF void Dma2Tc1_IrqHandler(void); +__WEAKDEF void Dma2Tc2_IrqHandler(void); +__WEAKDEF void Dma2Tc3_IrqHandler(void); +__WEAKDEF void Dma1Btc0_IrqHandler(void); +__WEAKDEF void Dma1Btc1_IrqHandler(void); +__WEAKDEF void Dma1Btc2_IrqHandler(void); +__WEAKDEF void Dma1Btc3_IrqHandler(void); +__WEAKDEF void Dma2Btc0_IrqHandler(void); +__WEAKDEF void Dma2Btc1_IrqHandler(void); +__WEAKDEF void Dma2Btc2_IrqHandler(void); +__WEAKDEF void Dma2Btc3_IrqHandler(void); +__WEAKDEF void Dma1Err0_IrqHandler(void); +__WEAKDEF void Dma1Err1_IrqHandler(void); +__WEAKDEF void Dma1Err2_IrqHandler(void); +__WEAKDEF void Dma1Err3_IrqHandler(void); +__WEAKDEF void Dma2Err0_IrqHandler(void); +__WEAKDEF void Dma2Err1_IrqHandler(void); +__WEAKDEF void Dma2Err2_IrqHandler(void); +__WEAKDEF void Dma2Err3_IrqHandler(void); + +__WEAKDEF void EfmPgmEraseErr_IrqHandler(void); +__WEAKDEF void EfmColErr_IrqHandler(void); +__WEAKDEF void EfmOpEnd_IrqHandler(void); +__WEAKDEF void QspiInt_IrqHandler(void); +__WEAKDEF void Dcu1_IrqHandler(void); +__WEAKDEF void Dcu2_IrqHandler(void); +__WEAKDEF void Dcu3_IrqHandler(void); +__WEAKDEF void Dcu4_IrqHandler(void); + +__WEAKDEF void Timer01GCMA_IrqHandler(void); +__WEAKDEF void Timer01GCMB_IrqHandler(void); +__WEAKDEF void Timer02GCMA_IrqHandler(void); +__WEAKDEF void Timer02GCMB_IrqHandler(void); + +__WEAKDEF void MainOscStop_IrqHandler(void); +__WEAKDEF void WakeupTimer_IrqHandler(void); +__WEAKDEF void Swdt_IrqHandler(void); + +__WEAKDEF void Timer61GCMA_IrqHandler(void); +__WEAKDEF void Timer61GCMB_IrqHandler(void); +__WEAKDEF void Timer61GCMC_IrqHandler(void); +__WEAKDEF void Timer61GCMD_IrqHandler(void); +__WEAKDEF void Timer61GCME_IrqHandler(void); +__WEAKDEF void Timer61GCMF_IrqHandler(void); +__WEAKDEF void Timer61GOV_IrqHandler(void); +__WEAKDEF void Timer61GUD_IrqHandler(void); +__WEAKDEF void Timer61GDT_IrqHandler(void); +__WEAKDEF void Timer61SCMA_IrqHandler(void); +__WEAKDEF void Timer61SCMB_IrqHandler(void); + +__WEAKDEF void Timer62GCMA_IrqHandler(void); +__WEAKDEF void Timer62GCMB_IrqHandler(void); +__WEAKDEF void Timer62GCMC_IrqHandler(void); +__WEAKDEF void Timer62GCMD_IrqHandler(void); +__WEAKDEF void Timer62GCME_IrqHandler(void); +__WEAKDEF void Timer62GCMF_IrqHandler(void); +__WEAKDEF void Timer62GOV_IrqHandler(void); +__WEAKDEF void Timer62GUD_IrqHandler(void); +__WEAKDEF void Timer62GDT_IrqHandler(void); +__WEAKDEF void Timer62SCMA_IrqHandler(void); +__WEAKDEF void Timer62SCMB_IrqHandler(void); + +__WEAKDEF void Timer63GCMA_IrqHandler(void); +__WEAKDEF void Timer63GCMB_IrqHandler(void); +__WEAKDEF void Timer63GCMC_IrqHandler(void); +__WEAKDEF void Timer63GCMD_IrqHandler(void); +__WEAKDEF void Timer63GCME_IrqHandler(void); +__WEAKDEF void Timer63GCMF_IrqHandler(void); +__WEAKDEF void Timer63GOV_IrqHandler(void); +__WEAKDEF void Timer63GUD_IrqHandler(void); +__WEAKDEF void Timer63GDT_IrqHandler(void); +__WEAKDEF void Timer63SCMA_IrqHandler(void); +__WEAKDEF void Timer63SCMB_IrqHandler(void); + +__WEAKDEF void TimerA1OV_IrqHandler(void); +__WEAKDEF void TimerA1UD_IrqHandler(void); +__WEAKDEF void TimerA1CMP_IrqHandler(void); +__WEAKDEF void TimerA2OV_IrqHandler(void); +__WEAKDEF void TimerA2UD_IrqHandler(void); +__WEAKDEF void TimerA2CMP_IrqHandler(void); +__WEAKDEF void TimerA3OV_IrqHandler(void); +__WEAKDEF void TimerA3UD_IrqHandler(void); +__WEAKDEF void TimerA3CMP_IrqHandler(void); +__WEAKDEF void TimerA4OV_IrqHandler(void); +__WEAKDEF void TimerA4UD_IrqHandler(void); +__WEAKDEF void TimerA4CMP_IrqHandler(void); +__WEAKDEF void TimerA5OV_IrqHandler(void); +__WEAKDEF void TimerA5UD_IrqHandler(void); +__WEAKDEF void TimerA5CMP_IrqHandler(void); +__WEAKDEF void TimerA6OV_IrqHandler(void); +__WEAKDEF void TimerA6UD_IrqHandler(void); +__WEAKDEF void TimerA6CMP_IrqHandler(void); + +__WEAKDEF void UsbGlobal_IrqHandler(void); + +__WEAKDEF void Usart1RxErr_IrqHandler(void); +__WEAKDEF void Usart1RxEnd_IrqHandler(void); +__WEAKDEF void Usart1TxEmpty_IrqHandler(void); +__WEAKDEF void Usart1TxEnd_IrqHandler(void); +__WEAKDEF void Usart1RxTO_IrqHandler(void); +__WEAKDEF void Usart2RxErr_IrqHandler(void); +__WEAKDEF void Usart2RxEnd_IrqHandler(void); +__WEAKDEF void Usart2TxEmpty_IrqHandler(void); +__WEAKDEF void Usart2TxEnd_IrqHandler(void); +__WEAKDEF void Usart2RxTO_IrqHandler(void); +__WEAKDEF void Usart3RxErr_IrqHandler(void); +__WEAKDEF void Usart3RxEnd_IrqHandler(void); +__WEAKDEF void Usart3TxEmpty_IrqHandler(void); +__WEAKDEF void Usart3TxEnd_IrqHandler(void); +__WEAKDEF void Usart3RxTO_IrqHandler(void); +__WEAKDEF void Usart4RxErr_IrqHandler(void); +__WEAKDEF void Usart4RxEnd_IrqHandler(void); +__WEAKDEF void Usart4TxEmpty_IrqHandler(void); +__WEAKDEF void Usart4TxEnd_IrqHandler(void); +__WEAKDEF void Usart4RxTO_IrqHandler(void); + +__WEAKDEF void Spi1RxEnd_IrqHandler(void); +__WEAKDEF void Spi1TxEmpty_IrqHandler(void); +__WEAKDEF void Spi1Err_IrqHandler(void); +__WEAKDEF void Spi1Idle_IrqHandler(void); +__WEAKDEF void Spi2RxEnd_IrqHandler(void); +__WEAKDEF void Spi2TxEmpty_IrqHandler(void); +__WEAKDEF void Spi2Err_IrqHandler(void); +__WEAKDEF void Spi2Idle_IrqHandler(void); +__WEAKDEF void Spi3RxEnd_IrqHandler(void); +__WEAKDEF void Spi3TxEmpty_IrqHandler(void); +__WEAKDEF void Spi3Err_IrqHandler(void); +__WEAKDEF void Spi3Idle_IrqHandler(void); +__WEAKDEF void Spi4RxEnd_IrqHandler(void); +__WEAKDEF void Spi4TxEmpty_IrqHandler(void); +__WEAKDEF void Spi4Err_IrqHandler(void); +__WEAKDEF void Spi4Idle_IrqHandler(void); + +__WEAKDEF void Timer41GCMUH_IrqHandler(void); +__WEAKDEF void Timer41GCMUL_IrqHandler(void); +__WEAKDEF void Timer41GCMVH_IrqHandler(void); +__WEAKDEF void Timer41GCMVL_IrqHandler(void); +__WEAKDEF void Timer41GCMWH_IrqHandler(void); +__WEAKDEF void Timer41GCMWL_IrqHandler(void); +__WEAKDEF void Timer41GOV_IrqHandler(void); +__WEAKDEF void Timer41GUD_IrqHandler(void); +__WEAKDEF void Timer41ReloadU_IrqHandler(void); +__WEAKDEF void Timer41ReloadV_IrqHandler(void); +__WEAKDEF void Timer41ReloadW_IrqHandler(void); +__WEAKDEF void Timer42GCMUH_IrqHandler(void); +__WEAKDEF void Timer42GCMUL_IrqHandler(void); +__WEAKDEF void Timer42GCMVH_IrqHandler(void); +__WEAKDEF void Timer42GCMVL_IrqHandler(void); +__WEAKDEF void Timer42GCMWH_IrqHandler(void); +__WEAKDEF void Timer42GCMWL_IrqHandler(void); +__WEAKDEF void Timer42GOV_IrqHandler(void); +__WEAKDEF void Timer42GUD_IrqHandler(void); +__WEAKDEF void Timer42ReloadU_IrqHandler(void); +__WEAKDEF void Timer42ReloadV_IrqHandler(void); +__WEAKDEF void Timer42ReloadW_IrqHandler(void); +__WEAKDEF void Timer43GCMUH_IrqHandler(void); +__WEAKDEF void Timer43GCMUL_IrqHandler(void); +__WEAKDEF void Timer43GCMVH_IrqHandler(void); +__WEAKDEF void Timer43GCMVL_IrqHandler(void); +__WEAKDEF void Timer43GCMWH_IrqHandler(void); +__WEAKDEF void Timer43GCMWL_IrqHandler(void); +__WEAKDEF void Timer43GOV_IrqHandler(void); +__WEAKDEF void Timer43GUD_IrqHandler(void); +__WEAKDEF void Timer43ReloadU_IrqHandler(void); +__WEAKDEF void Timer43ReloadV_IrqHandler(void); +__WEAKDEF void Timer43ReloadW_IrqHandler(void); + +__WEAKDEF void Emb1_IrqHandler(void); +__WEAKDEF void Emb2_IrqHandler(void); +__WEAKDEF void Emb3_IrqHandler(void); +__WEAKDEF void Emb4_IrqHandler(void); + +__WEAKDEF void I2s1Tx_IrqHandler(void); +__WEAKDEF void I2s1Rx_IrqHandler(void); +__WEAKDEF void I2s1Err_IrqHandler(void); +__WEAKDEF void I2s2Tx_IrqHandler(void); +__WEAKDEF void I2s2Rx_IrqHandler(void); +__WEAKDEF void I2s2Err_IrqHandler(void); +__WEAKDEF void I2s3Tx_IrqHandler(void); +__WEAKDEF void I2s3Rx_IrqHandler(void); +__WEAKDEF void I2s3Err_IrqHandler(void); +__WEAKDEF void I2s4Tx_IrqHandler(void); +__WEAKDEF void I2s4Rx_IrqHandler(void); +__WEAKDEF void I2s4Err_IrqHandler(void); + +__WEAKDEF void I2c1RxEnd_IrqHandler(void); +__WEAKDEF void I2c1TxEnd_IrqHandler(void); +__WEAKDEF void I2c1TxEmpty_IrqHandler(void); +__WEAKDEF void I2c1Err_IrqHandler(void); +__WEAKDEF void I2c2RxEnd_IrqHandler(void); +__WEAKDEF void I2c2TxEnd_IrqHandler(void); +__WEAKDEF void I2c2TxEmpty_IrqHandler(void); +__WEAKDEF void I2c2Err_IrqHandler(void); +__WEAKDEF void I2c3RxEnd_IrqHandler(void); +__WEAKDEF void I2c3TxEnd_IrqHandler(void); +__WEAKDEF void I2c3TxEmpty_IrqHandler(void); +__WEAKDEF void I2c3Err_IrqHandler(void); + +__WEAKDEF void Pvd1_IrqHandler(void); +__WEAKDEF void Pvd2_IrqHandler(void); + +__WEAKDEF void FcmErr_IrqHandler(void); +__WEAKDEF void FcmEnd_IrqHandler(void); +__WEAKDEF void FcmOV_IrqHandler(void); + +__WEAKDEF void Wdt_IrqHandler(void); + +__WEAKDEF void ADC1A_IrqHandler(void); +__WEAKDEF void ADC1B_IrqHandler(void); +__WEAKDEF void ADC1ChCmp_IrqHandler(void); +__WEAKDEF void ADC1SeqCmp_IrqHandler(void); +__WEAKDEF void ADC2A_IrqHandler(void); +__WEAKDEF void ADC2B_IrqHandler(void); +__WEAKDEF void ADC2ChCmp_IrqHandler(void); +__WEAKDEF void ADC2SeqCmp_IrqHandler(void); + +__WEAKDEF void Sdio1_IrqHandler(void); +__WEAKDEF void Sdio2_IrqHandler(void); + +__WEAKDEF void Can_IrqHandler(void); + +//@} // InterruptGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_INTERRUPTS_ENABLE */ + +#endif /* __HC32F460_INTERRUPTS_H___ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_keyscan.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_keyscan.h new file mode 100644 index 0000000000..a82474b0dc --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_keyscan.h @@ -0,0 +1,191 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_keyscan.h + ** + ** A detailed description is available at + ** @link KeyscanGroup Keyscan description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of keyscan. + ** + ******************************************************************************/ + +#ifndef __HC32F460_KEYSCAN_H__ +#define __HC32F460_KEYSCAN_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + * \defgroup KeyscanGroup Matrix Key Scan Module (KeyScan) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Enumeration to hi-z state cycles of each keyout + ** + ** \note + ******************************************************************************/ +typedef enum en_hiz_cycle +{ + Hiz4 = 0u, + Hiz8 = 1u, + Hiz16 = 2u, + Hiz32 = 3u, + Hiz64 = 4u, + Hiz256 = 5u, + Hiz512 = 6u, + Hiz1K = 7u, +}en_hiz_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to low state cycles of each keyout + ** + ** \note + ******************************************************************************/ +typedef enum en_low_cycle +{ + Low8 = 3u, + Low16 = 4u, + Low32 = 5u, + Low64 = 6u, + Low128 = 7u, + Low256 = 8u, + Low512 = 9u, + Low1K = 10u, + Low2K = 11u, + Low4K = 12u, + Low8K = 13u, + Low16K = 14u, + Low32K = 15u, + Low64K = 16u, + Low128K = 17u, + Low256K = 18u, + Low512K = 19u, + Low1M = 20u, + Low2M = 21u, + Low4M = 22u, + Low8M = 23u, + Low16M = 24u, +}en_low_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to key scan clock + ** + ** \note + ******************************************************************************/ +typedef enum en_keyscan_clk +{ + KeyscanHclk = 0u, ///< use HCLK as scan clock + KeyscanLrc = 1u, ///< use internal Low RC as scan clock + KeyscanXtal32 = 2u, ///< use external XTAL32 as scan clock +}en_keyscan_clk_t; + +/** + ******************************************************************************* + ** \brief Enumeration to KEYOUT combination + ******************************************************************************/ +typedef enum en_keyout_sel +{ + Keyout0To1 = 1u, ///< KEYOUT 0 to 1 are selected + Keyout0To2 = 2u, ///< KEYOUT 0 to 2 are selected + Keyout0To3 = 3u, ///< KEYOUT 0 to 3 are selected + Keyout0To4 = 4u, ///< KEYOUT 0 to 4 are selected + Keyout0To5 = 5u, ///< KEYOUT 0 to 5 are selected + Keyout0To6 = 6u, ///< KEYOUT 0 to 6 are selected + Keyout0To7 = 7u, ///< KEYOUT 0 to 7 are selected +}en_keyout_sel_t; + +/** + ******************************************************************************* + ** \brief Enumeration to KEYIN combination + ******************************************************************************/ +typedef enum en_keyin_sel +{ + Keyin00 = 1u << 0, ///< KEYIN 0 is selected + Keyin01 = 1u << 1, ///< KEYIN 1 is selected + Keyin02 = 1u << 2, ///< KEYIN 2 is selected + Keyin03 = 1u << 3, ///< KEYIN 3 is selected + Keyin04 = 1u << 4, ///< KEYIN 4 is selected + Keyin05 = 1u << 5, ///< KEYIN 5 is selected + Keyin06 = 1u << 6, ///< KEYIN 6 is selected + Keyin07 = 1u << 7, ///< KEYIN 7 is selected + Keyin08 = 1u << 8, ///< KEYIN 8 is selected + Keyin09 = 1u << 9, ///< KEYIN 9 is selected + Keyin10 = 1u << 10, ///< KEYIN 10 is selected + Keyin11 = 1u << 11, ///< KEYIN 11 is selected + Keyin12 = 1u << 12, ///< KEYIN 12 is selected + Keyin13 = 1u << 13, ///< KEYIN 13 is selected + Keyin14 = 1u << 14, ///< KEYIN 14 is selected + Keyin15 = 1u << 15, ///< KEYIN 15 is selected +}en_keyin_sel_t; + +/** + ******************************************************************************* + ** \brief Keyscan configuration + ** + ** \note The Keyscan configuration structure + ******************************************************************************/ +typedef struct stc_keyscan_config +{ + en_hiz_cycle_t enHizCycle; ///< KEYOUT Hiz state cycles, ref @ en_hiz_cycle_t for details + en_low_cycle_t enLowCycle; ///< KEYOUT Low state cycles, ref @ en_low_cycle_t for details + en_keyscan_clk_t enKeyscanClk; ///< Key scan clock, ref @ en_keyscan_clk_t for details + en_keyout_sel_t enKeyoutSel; ///< KEYOUT selection, ref @ en_keyout_sel_t for details + uint16_t u16KeyinSel; ///< KEYIN selection, ref @ en_keyin_sel_t for details +}stc_keyscan_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig); +extern en_result_t KEYSCAN_DeInit(void); +extern en_result_t KEYSCAN_Start(void); +extern en_result_t KEYSCAN_Stop(void); +extern uint8_t KEYSCAN_GetColIdx(void); + +//@} // KeyscanGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_KEYSCAN_ENABLE */ + +#endif /* __HC32F460_KEYSCAN_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_mpu.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_mpu.h new file mode 100644 index 0000000000..b46e6ce7a5 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_mpu.h @@ -0,0 +1,293 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_mpu.h + ** + ** A detailed description is available at + ** @link MpuGroup MPU description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of MPU. + ** + ******************************************************************************/ +#ifndef __HC32F460_MPU_H__ +#define __HC32F460_MPU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_MPU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup MpuGroup Memory Protection Unit(MPU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief MPU region number enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_num +{ + MpuRegionNum0 = 0u, ///< MPU region number 0 + MpuRegionNum1 = 1u, ///< MPU region number 1 + MpuRegionNum2 = 2u, ///< MPU region number 2 + MpuRegionNum3 = 3u, ///< MPU region number 3 + MpuRegionNum4 = 4u, ///< MPU region number 4 + MpuRegionNum5 = 5u, ///< MPU region number 5 + MpuRegionNum6 = 6u, ///< MPU region number 6 + MpuRegionNum7 = 7u, ///< MPU region number 7 + MpuRegionNum8 = 8u, ///< MPU region number 8 + MpuRegionNum9 = 9u, ///< MPU region number 9 + MpuRegionNum10 = 10u, ///< MPU region number 10 + MpuRegionNum11 = 11u, ///< MPU region number 11 + MpuRegionNum12 = 12u, ///< MPU region number 12 + MpuRegionNum13 = 13u, ///< MPU region number 13 + MpuRegionNum14 = 14u, ///< MPU region number 14 + MpuRegionNum15 = 15u, ///< MPU region number 15 +} en_mpu_region_num_t; + +/** + ******************************************************************************* + ** \brief MPU region size enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_size +{ + MpuRegionSize32Byte = 4u, ///< 32 Byte + MpuRegionSize64Byte = 5u, ///< 64 Byte + MpuRegionSize128Byte = 6u, ///< 126 Byte + MpuRegionSize256Byte = 7u, ///< 256 Byte + MpuRegionSize512Byte = 8u, ///< 512 Byte + MpuRegionSize1KByte = 9u, ///< 1K Byte + MpuRegionSize2KByte = 10u, ///< 2K Byte + MpuRegionSize4KByte = 11u, ///< 4K Byte + MpuRegionSize8KByte = 12u, ///< 8K Byte + MpuRegionSize16KByte = 13u, ///< 16K Byte + MpuRegionSize32KByte = 14u, ///< 32K Byte + MpuRegionSize64KByte = 15u, ///< 64K Byte + MpuRegionSize128KByte = 16u, ///< 128K Byte + MpuRegionSize256KByte = 17u, ///< 256K Byte + MpuRegionSize512KByte = 18u, ///< 512K Byte + MpuRegionSize1MByte = 19u, ///< 1M Byte + MpuRegionSize2MByte = 20u, ///< 2M Byte + MpuRegionSize4MByte = 21u, ///< 4M Byte + MpuRegionSize8MByte = 22u, ///< 8M Byte + MpuRegionSize16MByte = 23u, ///< 16M Byte + MpuRegionSize32MByte = 24u, ///< 32M Byte + MpuRegionSize64MByte = 25u, ///< 64M Byte + MpuRegionSize128MByte = 26u, ///< 128M Byte + MpuRegionSize256MByte = 27u, ///< 256M Byte + MpuRegionSize512MByte = 28u, ///< 512M Byte + MpuRegionSize1GByte = 29u, ///< 1G Byte + MpuRegionSize2GByte = 30u, ///< 2G Byte + MpuRegionSize4GByte = 31u, ///< 4G Byte +} en_mpu_region_size_t; + +/** + ******************************************************************************* + ** \brief MPU region enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_region_type +{ + SMPU1Region = 0u, ///< System DMA_1 MPU + SMPU2Region = 1u, ///< System DMA_2 MPU + FMPURegion = 2u, ///< System USBFS_DMA MPU +} en_mpu_region_type_t; + +/** + ******************************************************************************* + ** \brief MPU action selection enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_action_sel +{ + MpuNoneAction = 0u, ///< MPU don't action. + MpuTrigBusError = 1u, ///< MPU trigger bus error + MpuTrigNmi = 2u, ///< MPU trigger bus NMI interrupt + MpuTrigReset = 3u, ///< MPU trigger reset +} en_mpu_action_sel_t; + +/** + ******************************************************************************* + ** \brief MPU IP protection mode enumeration + ** + ******************************************************************************/ +typedef enum en_mpu_ip_prot_mode +{ + AesReadProt = (1ul << 0), ///< AES read protection + AesWriteProt = (1ul << 1), ///< AES write protection + HashReadProt = (1ul << 2), ///< HASH read protection + HashWriteProt = (1ul << 3), ///< HASH write protection + TrngReadProt = (1ul << 4), ///< TRNG read protection + TrngWriteProt = (1ul << 5), ///< TRNG write protection + CrcReadProt = (1ul << 6), ///< CRC read protection + CrcWriteProt = (1ul << 7), ///< CRC write protection + FmcReadProt = (1ul << 8), ///< FMC read protection + FmcWriteProt = (1ul << 9), ///< FMC write protection + WdtReadProt = (1ul << 12), ///< WDT read protection + WdtWriteProt = (1ul << 13), ///< WDT write protection + SwdtReadProt = (1ul << 14), ///< WDT read protection + SwdtWriteProt = (1ul << 15), ///< WDT write protection + BksramReadProt = (1ul << 16), ///< BKSRAM read protection + BksramWriteProt = (1ul << 17), ///< BKSRAM write protection + RtcReadProt = (1ul << 18), ///< RTC read protection + RtcWriteProt = (1ul << 19), ///< RTC write protection + DmpuReadProt = (1ul << 20), ///< DMPU read protection + DmpuWriteProt = (1ul << 21), ///< DMPU write protection + SramcReadProt = (1ul << 22), ///< SRAMC read protection + SramcWriteProt = (1ul << 23), ///< SRAMC write protection + IntcReadProt = (1ul << 24), ///< INTC read protection + IntcWriteProt = (1ul << 25), ///< INTC write protection + SyscReadProt = (1ul << 26), ///< SYSC read protection + SyscWriteProt = (1ul << 27), ///< SYSC write protection + MstpReadProt = (1ul << 28), ///< MSTP read protection + MstpWriteProt = (1ul << 29), ///< MSTP write protection + BusErrProt = (1ul << 31), ///< BUSERR write protection +} en_mpu_ip_prot_mode_t; + +/** + ******************************************************************************* + ** \brief MPU protection region permission + ** + ******************************************************************************/ +typedef struct stc_mpu_prot_region_permission +{ + en_mpu_action_sel_t enAction; ///< Specifies MPU action + + en_functional_state_t enRegionEnable; ///< Disable: Disable region protection; Enable:Enable region protection + + en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write + + en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read + +} stc_mpu_prot_region_permission_t; + +/** + ******************************************************************************* + ** \brief MPU background region permission + ** + ******************************************************************************/ +typedef struct stc_mpu_bkgd_region_permission +{ + en_functional_state_t enWriteEnable; ///< Disable: Prohibited to write; Enable:permitted to write + + en_functional_state_t enReadEnable; ///< Disable: Prohibited to read; Enable:permitted to read +} stc_mpu_bkgd_region_permission_t_t; + +/** + ******************************************************************************* + ** \brief MPU background region initialization configuration + ** + ******************************************************************************/ +typedef struct stc_mpu_bkgd_region_init +{ + stc_mpu_bkgd_region_permission_t_t stcSMPU1BkgdPermission; ///< Specifies SMPU1 background permission and this stuctrue detail refer of @ref stc_mpu_bkgd_region_permission_t_t + + stc_mpu_bkgd_region_permission_t_t stcSMPU2BkgdPermission; ///< Specifies SMPU2 background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t + + stc_mpu_bkgd_region_permission_t_t stcFMPUBkgdPermission; ///< Specifies FMPU background permission and this stuctrue detail refer @ref stc_mpu_bkgd_region_permission_t_t +} stc_mpu_bkgd_region_init_t; + +/** + ******************************************************************************* + ** \brief MPU protect region initialization configuration + ** + ******************************************************************************/ +typedef struct stc_mpu_prot_region_init +{ + uint32_t u32RegionBaseAddress; ///< Specifies region base address + + en_mpu_region_size_t enRegionSize; ///< Specifies region size and This parameter can be a value of @ref en_mpu_region_size_t + + stc_mpu_prot_region_permission_t stcSMPU1Permission; ///< Specifies DMA1 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t + + stc_mpu_prot_region_permission_t stcSMPU2Permission; ///< Specifies DMA2 MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t + + stc_mpu_prot_region_permission_t stcFMPUPermission; ///< Specifies USBFS-DMA MPU region permission and this structure detail refer @ref stc_mpu_prot_region_permission_t +} stc_mpu_prot_region_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum, + const stc_mpu_prot_region_init_t *pstcInitCfg); +en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg); +en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum, + en_mpu_region_size_t enRegionSize); +en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum); +en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum, + uint32_t u32RegionBaseAddr); +uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum); +en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType, + en_mpu_action_sel_t enActionSel); +en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState); +en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType); +en_result_t MPU_WriteProtCmd(en_functional_state_t enState); +en_result_t MPU_IpProtCmd(uint32_t u32ProtMode, + en_functional_state_t enState); + +//@} // MpuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_MPU_ENABLE */ + +#endif /* __HC32F460_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_ots.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_ots.h new file mode 100644 index 0000000000..53a00ff1b2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_ots.h @@ -0,0 +1,139 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_ots.h + ** + ** A detailed description is available at + ** @link OtsGroup Ots description @endlink + ** + ** - 2018-10-26 CDT First version for Device Driver Library of Ots. + ** + ******************************************************************************/ +#ifndef __HC32F460_OTS_H__ +#define __HC32F460_OTS_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_OTS_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup OtsGroup On-chip Temperature Sensor(OTS) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* Automatically turn off the analog temperature sensor after the temperature + measurement is over. */ +typedef enum en_ots_auto_off +{ + OtsAutoOff_Disable = 0x0, ///< Disable automatically turn off OTS. + OtsAutoOff_Enable = 0x1, ///< Enable automatically turn off OTS. +} en_ots_auto_off_t; + +/* Temperature measurement end interrupt request. */ +typedef enum en_ots_ie +{ + OtsInt_Disable = 0x0, ///< Disable OTS interrupt. + OtsInt_Enable = 0x1, ///< Enable OTS interrupt. +} en_ots_ie_t; + +/* OTS clock selection. */ +typedef enum en_ots_clk_sel +{ + OtsClkSel_Xtal = 0x0, ///< Select XTAL as OTS clock. + OtsClkSel_Hrc = 0x1, ///< Select HRC as OTS clock. +} en_ots_clk_sel_t; + +/* OTS OTS initialization structure definition. */ +typedef struct stc_ots_init +{ + en_ots_auto_off_t enAutoOff; ///< @ref en_ots_auto_off_t. + en_ots_clk_sel_t enClkSel; ///< @ref en_ots_clk_sel_t. + float32_t f32SlopeK; ///< K: Temperature slope (calculated by calibration experiment). */ + float32_t f32OffsetM; ///< M: Temperature offset (calculated by calibration experiment). */ +} stc_ots_init_t; + +/* OTS common trigger source select */ +typedef enum en_ots_com_trigger +{ + OtsComTrigger_1 = 0x1, ///< Select common trigger 1. + OtsComTrigger_2 = 0x2, ///< Select common trigger 2. + OtsComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2. +} en_ots_com_trigger_t; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @brief Start OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Start(void) +{ + bM4_OTS_CTL_OTSST = (uint32_t)1u; +} + +/** + * @brief Stop OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Stop(void) +{ + bM4_OTS_CTL_OTSST = (uint32_t)0u; +} + +en_result_t OTS_Init(const stc_ots_init_t *pstcInit); +void OTS_DeInit(void); + +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout); + +void OTS_IntCmd(en_functional_state_t enNewState); +void OTS_SetTriggerSrc(en_event_src_t enEvent); +void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState); + +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout); + +float OTS_CalculateTemp(void); + +//@} // OtsGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_OTS_ENABLE */ + +#endif /* __HC32F460_OTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_pwc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_pwc.h new file mode 100644 index 0000000000..f170784d55 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_pwc.h @@ -0,0 +1,567 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_pwc.h + ** + ** A detailed description is available at + ** @link PwcGroup PWC description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of PWC. + ** + ******************************************************************************/ +#ifndef __HC32F460_PWC_H__ +#define __HC32F460_PWC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_PWC_ENABLE == DDL_ON) + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup PwcGroup Power Control(PWC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The power down mode. + ** + ******************************************************************************/ +typedef enum en_pwc_powerdown_md +{ + PowerDownMd1 = 0u, ///< Power down mode 1. + PowerDownMd2 = 1u, ///< Power down mode 2. + PowerDownMd3 = 2u, ///< Power down mode 3. + PowerDownMd4 = 3u, ///< Power down mode 4. +}en_pwc_powerdown_md_t; + +/** + ******************************************************************************* + ** \brief The IO retain status under power down mode. + ** + ******************************************************************************/ +typedef enum en_pwc_iortn +{ + IoPwrDownRetain = 0u, ///< Io keep under power down mode. + IoPwrRstRetain = 1u, ///< Io keep after power reset. + IoHighImp = 2u, ///< IO high impedance either power down or power reset. +}en_pwc_iortn_t; + +/** + ******************************************************************************* + ** \brief The driver ability while different speed mode enter stop mode. + ** + ******************************************************************************/ +typedef enum en_pwc_stopdas +{ + StopHighspeed = 0u, ///< The driver ability while high speed mode enter stop mode. + StopUlowspeed = 3u, ///< The driver ability while ultra_low speed mode enter stop mode. +}en_pwc_stopdas_t; + +/** + ******************************************************************************* + ** \brief The dynamic power driver voltage select. + ** + ******************************************************************************/ +typedef enum en_pwc_rundrvs +{ + RunUHighspeed = 0u, ///< The ultra_high speed. + RunUlowspeed = 2u, ///< The ultra_low speed. + RunHighspeed = 3u, ///< The high speed. +}en_pwc_rundrvs_t; + +/** + ******************************************************************************* + ** \brief The dynamic power driver ability scaling. + ** + ******************************************************************************/ +typedef enum en_pwc_drvability_sca +{ + Ulowspeed = 8u, ///< The ultra_low speed. + HighSpeed = 15u, ///< The high speed. +}en_pwc_drvability_sca_t; + +/** + ******************************************************************************* + ** \brief The power down wake up time select. + ** + ******************************************************************************/ +typedef enum en_pwc_waketime_sel +{ + Vcap01 = 0u, ///< Wake up while vcap capacitance 2*0.1uf. + Vcap0047 = 1u, ///< Wake up while vcap capacitance 2*0.047uf. +}en_pwc_waketime_sel_t; + +/** + ******************************************************************************* + ** \brief The wait or not wait flash stable while stop mode awake. + ** + ******************************************************************************/ +typedef enum en_pwc_stop_flash_sel +{ + Wait = 0u, ///< wait flash stable. + NotWait = 1u, ///< Not Wait flash stable. +}en_pwc_stop_flash_sel_t; + +/** + ******************************************************************************* + ** \brief The clk value while stop mode awake. + ** + ******************************************************************************/ +typedef enum en_pwc_stop_clk_sel +{ + ClkFix = 0u, ///< clock fix. + ClkMrc = 1u, ///< clock source is MRC, only ram code. +}en_pwc_stop_clk_sel_t; + +/** + ******************************************************************************* + ** \brief The power down wake up event edge select. + ** + ******************************************************************************/ +typedef enum en_pwc_edge_sel +{ + EdgeFalling = 0u, ///< Falling edge. + EdgeRising = 1u, ///< Rising edge. +}en_pwc_edge_sel_t; + +/** + ******************************************************************************* + ** \brief The voltage detect edge select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvdedge_sel +{ + OverVcc = 0u, ///< PVD > VCC. + BelowVcc = 1u, ///< PVD < VCC. +}en_pwc_pvdedge_sel_t; + +/** + ******************************************************************************* + ** \brief The flag of wake_up timer compare result. + ** + ******************************************************************************/ +typedef enum en_pwc_wkover_flag +{ + UnEqual = 0u, ///< Timer value unequal with the wake_up compare value whitch set. + Equal = 1u, ///< Timer value equal with the wake_up compare value whitch set.. +}en_pwc_wkover_flag_t; + +/** + ******************************************************************************* + ** \brief The RAM operating mode. + ** + ******************************************************************************/ +typedef enum en_pwc_ram_op_md +{ + HighSpeedMd = 0x8043, ///< Work at high speed. + UlowSpeedMd = 0x9062, ///< Work at ultra low speed. +}en_pwc_ram_op_md_t; + +/** + ******************************************************************************* + ** \brief The wake up clock select. + ** + ******************************************************************************/ +typedef enum en_pwc_wkclk_sel +{ + Wk64hz = 0u, ///< 64Hz. + WkXtal32 = 1u, ///< Xtal32. + WkLrc = 2u, ///< Lrc. +}en_pwc_wkclk_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd digital filtering sampling clock select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvdfiltclk_sel +{ + PvdLrc025 = 0u, ///< 0.25 LRC cycle. + PvdLrc05 = 1u, ///< 0.5 LRC cycle. + PvdLrc1 = 2u, ///< LRC 1 div. + PvdLrc2 = 3u, ///< LRC 2 div. +}en_pwc_pvdfiltclk_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd2 level select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvd2level_sel +{ + Pvd2Level0 = 0u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode. + Pvd2Level1 = 1u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode. + Pvd2Level2 = 2u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode. + Pvd2Level3 = 3u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode. + Pvd2Level4 = 4u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode. + Pvd2Level5 = 5u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode. + Pvd2Level6 = 6u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode. + Pvd2Level7 = 7u, ///< 1.1V.while high_speed & ultra_low speed mode, 1.15V.while ultra_high speed mode. +}en_pwc_pvd2level_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd1 level select. + ** + ******************************************************************************/ +typedef enum en_pwc_pvd1level_sel +{ + Pvd1Level0 = 0u, ///< 2.0V.while high_speed & ultra_low speed mode, 2.09V.while ultra_high speed mode. + Pvd1Level1 = 1u, ///< 2.1V.while high_speed & ultra_low speed mode, 2.20V.while ultra_high speed mode. + Pvd1Level2 = 2u, ///< 2.3V.while high_speed & ultra_low speed mode, 2.40V.while ultra_high speed mode. + Pvd1Level3 = 3u, ///< 2.5V.while high_speed & ultra_low speed mode, 2.67V.while ultra_high speed mode. + Pvd1Level4 = 4u, ///< 2.6V.while high_speed & ultra_low speed mode, 2.77V.while ultra_high speed mode. + Pvd1Level5 = 5u, ///< 2.7V.while high_speed & ultra_low speed mode, 2.88V.while ultra_high speed mode. + Pvd1Level6 = 6u, ///< 2.8V.while high_speed & ultra_low speed mode, 2.98V.while ultra_high speed mode. + Pvd1Level7 = 7u, ///< 2.9V.while high_speed & ultra_low speed mode, 3.08V.while ultra_high speed mode. +}en_pwc_pvd1level_sel_t; + +/** + ******************************************************************************* + ** \brief The pvd interrupt select. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd_int_sel +{ + NonMskInt = 0u, ///< Non-maskable Interrupt. + MskInt = 1u, ///< Maskable Interrupt. +}en_pwc_pvd_int_sel_t; + +/** + ******************************************************************************* + ** \brief The handle of pvd mode. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd_md +{ + PvdInt = 0u, ///< The handle of pvd is interrupt. + PvdReset = 1u, ///< The handle of pvd is reset. +}en_pwc_pvd_md_t; + +/** + ******************************************************************************* + ** \brief The unit of pvd detect. + ** + ******************************************************************************/ + typedef enum en_pwc_pvd +{ + PvdU1 = 0u, ///< The uint1 of pvd detect. + PvdU2 = 1u, ///< The unit2 of pvd detect. +}en_pwc_pvd_t; + +/** + ******************************************************************************* + ** \brief The power mode configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_pwr_mode_cfg +{ + en_pwc_powerdown_md_t enPwrDownMd; ///< Power down mode. + en_functional_state_t enRLdo; ///< Enable or disable RLDO. + en_functional_state_t enRetSram; ///< Enable or disable Ret_Sram. + en_pwc_iortn_t enIoRetain; ///< IO retain. + en_pwc_waketime_sel_t enPwrDWkupTm; ///< The power down wake up time select. +}stc_pwc_pwr_mode_cfg_t; + +/** + ******************************************************************************* + ** \brief The stop mode configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_stop_mode_cfg +{ + en_pwc_stopdas_t enStpDrvAbi; ///< Driver ability while enter stop mode. + en_pwc_stop_flash_sel_t enStopFlash; ///< Flash mode while stop mode awake. + en_pwc_stop_clk_sel_t enStopClk; ///< Clock value while stop mode awake. + en_functional_state_t enPll; ///< Whether the PLL enable or disable while enter stop mode. +}stc_pwc_stop_mode_cfg_t; + +/** + ******************************************************************************* + ** \brief The power down wake_up timer control. + ** + ******************************************************************************/ +typedef struct stc_pwc_wktm_ctl +{ + uint16_t u16WktmCmp; ///< The wake_up timer compare value. + en_pwc_wkover_flag_t enWkOverFlag; ///< The flag of compare result. + en_pwc_wkclk_sel_t enWkclk; ///< The clock of wake_up timer. + en_functional_state_t enWktmEn; ///< Enable or disable wake_up timer. +}stc_pwc_wktm_ctl_t; + +/** + ******************************************************************************* + ** \brief The pvd control. + ** + ******************************************************************************/ +typedef struct stc_pwc_pvd_ctl +{ + en_functional_state_t enPvdIREn; ///< Enable or disable pvd interrupt(reset). + en_pwc_pvd_md_t enPvdMode; ///< The handle of pvd is interrupt or reset. + en_functional_state_t enPvdCmpOutEn; ///< Enable or disable pvd output compare result . +}stc_pwc_pvd_ctl_t; + +/** + ******************************************************************************* + ** \brief The power down wake_up event configuration. + ** + ******************************************************************************/ +typedef struct stc_pwc_pvd_cfg +{ + stc_pwc_pvd_ctl_t stcPvd1Ctl; ///< Pvd1 control configuration. + stc_pwc_pvd_ctl_t stcPvd2Ctl; ///< Pvd2 control configuration. + en_functional_state_t enPvd1FilterEn; ///< Pvd1 filtering enable or disable. + en_functional_state_t enPvd2FilterEn; ///< Pvd2 filtering enable or disable. + en_pwc_pvdfiltclk_sel_t enPvd1Filtclk; ///< Pvd1 filtering sampling clock. + en_pwc_pvdfiltclk_sel_t enPvd2Filtclk; ///< Pvd2 filtering sampling clock. + en_pwc_pvd1level_sel_t enPvd1Level; ///< Pvd1 voltage. + en_pwc_pvd2level_sel_t enPvd2Level; ///< Pvd2 voltage. + en_pwc_pvd_int_sel_t enPvd1Int; ///< Pvd1 interrupt. + en_pwc_pvd_int_sel_t enPvd2Int; ///< Pvd2 interrupt. +}stc_pwc_pvd_cfg_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define PWC_PDWKEN0_WKUP00 ((uint8_t)0x01) +#define PWC_PDWKEN0_WKUP01 ((uint8_t)0x02) +#define PWC_PDWKEN0_WKUP02 ((uint8_t)0x04) +#define PWC_PDWKEN0_WKUP03 ((uint8_t)0x08) +#define PWC_PDWKEN0_WKUP10 ((uint8_t)0x10) +#define PWC_PDWKEN0_WKUP11 ((uint8_t)0x20) +#define PWC_PDWKEN0_WKUP12 ((uint8_t)0x40) +#define PWC_PDWKEN0_WKUP13 ((uint8_t)0x80) + +#define PWC_PDWKEN1_WKUP20 ((uint8_t)0x01) +#define PWC_PDWKEN1_WKUP21 ((uint8_t)0x02) +#define PWC_PDWKEN1_WKUP22 ((uint8_t)0x04) +#define PWC_PDWKEN1_WKUP23 ((uint8_t)0x08) +#define PWC_PDWKEN1_WKUP30 ((uint8_t)0x10) +#define PWC_PDWKEN1_WKUP31 ((uint8_t)0x20) +#define PWC_PDWKEN1_WKUP32 ((uint8_t)0x40) +#define PWC_PDWKEN1_WKUP33 ((uint8_t)0x80) + +#define PWC_PDWKEN2_PVD1 ((uint8_t)0x01) +#define PWC_PDWKEN2_PVD2 ((uint8_t)0x02) +#define PWC_PDWKEN2_NMI ((uint8_t)0x04) +#define PWC_PDWKEN2_RTCPRD ((uint8_t)0x10) +#define PWC_PDWKEN2_RTCAL ((uint8_t)0x20) +#define PWC_PDWKEN2_WKTM ((uint8_t)0x80) + +#define PWC_PDWKUP_EDGE_WKP0 ((uint8_t)0x01) +#define PWC_PDWKUP_EDGE_WKP1 ((uint8_t)0x02) +#define PWC_PDWKUP_EDGE_WKP2 ((uint8_t)0x04) +#define PWC_PDWKUP_EDGE_WKP3 ((uint8_t)0x08) +#define PWC_PDWKUP_EDGE_PVD1 ((uint8_t)0x10) +#define PWC_PDWKUP_EDGE_PVD2 ((uint8_t)0x20) +#define PWC_PDWKUP_EDGE_NMI ((uint8_t)0x40) + +#define PWC_RAMPWRDOWN_SRAM1 ((uint32_t)0x00000001) +#define PWC_RAMPWRDOWN_SRAM2 ((uint32_t)0x00000002) +#define PWC_RAMPWRDOWN_SRAM3 ((uint32_t)0x00000004) +#define PWC_RAMPWRDOWN_SRAMH ((uint32_t)0x00000008) +#define PWC_RAMPWRDOWN_USBFS ((uint32_t)0x00000010) +#define PWC_RAMPWRDOWN_SDIOC0 ((uint32_t)0x00000020) +#define PWC_RAMPWRDOWN_SDIOC1 ((uint32_t)0x00000040) +#define PWC_RAMPWRDOWN_CAN ((uint32_t)0x00000080) +#define PWC_RAMPWRDOWN_CACHE ((uint32_t)0x00000100) +#define PWC_RAMPWRDOWN_FULL ((uint32_t)0x000001FF) + +#define PWC_STOPWKUPEN_EIRQ0 ((uint32_t)0x00000001) +#define PWC_STOPWKUPEN_EIRQ1 ((uint32_t)0x00000002) +#define PWC_STOPWKUPEN_EIRQ2 ((uint32_t)0x00000004) +#define PWC_STOPWKUPEN_EIRQ3 ((uint32_t)0x00000008) +#define PWC_STOPWKUPEN_EIRQ4 ((uint32_t)0x00000010) +#define PWC_STOPWKUPEN_EIRQ5 ((uint32_t)0x00000020) +#define PWC_STOPWKUPEN_EIRQ6 ((uint32_t)0x00000040) +#define PWC_STOPWKUPEN_EIRQ7 ((uint32_t)0x00000080) +#define PWC_STOPWKUPEN_EIRQ8 ((uint32_t)0x00000100) +#define PWC_STOPWKUPEN_EIRQ9 ((uint32_t)0x00000200) +#define PWC_STOPWKUPEN_EIRQ10 ((uint32_t)0x00000400) +#define PWC_STOPWKUPEN_EIRQ11 ((uint32_t)0x00000800) +#define PWC_STOPWKUPEN_EIRQ12 ((uint32_t)0x00001000) +#define PWC_STOPWKUPEN_EIRQ13 ((uint32_t)0x00002000) +#define PWC_STOPWKUPEN_EIRQ14 ((uint32_t)0x00004000) +#define PWC_STOPWKUPEN_EIRQ15 ((uint32_t)0x00008000) +#define PWC_STOPWKUPEN_SWDT ((uint32_t)0x00010000) +#define PWC_STOPWKUPEN_VDU1 ((uint32_t)0x00020000) +#define PWC_STOPWKUPEN_VDU2 ((uint32_t)0x00040000) +#define PWC_STOPWKUPEN_CMPI0 ((uint32_t)0x00080000) +#define PWC_STOPWKUPEN_WKTM ((uint32_t)0x00100000) +#define PWC_STOPWKUPEN_RTCAL ((uint32_t)0x00200000) +#define PWC_STOPWKUPEN_RTCPRD ((uint32_t)0x00400000) +#define PWC_STOPWKUPEN_TMR0 ((uint32_t)0x00800000) +#define PWC_STOPWKUPEN_USARTRXD ((uint32_t)0x02000000) + +#define PWC_PTWK0_WKUPFLAG ((uint8_t)0x01) +#define PWC_PTWK1_WKUPFLAG ((uint8_t)0x02) +#define PWC_PTWK2_WKUPFLAG ((uint8_t)0x04) +#define PWC_PTWK3_WKUPFLAG ((uint8_t)0x08) +#define PWC_PVD1_WKUPFLAG ((uint8_t)0x10) +#define PWC_PVD2_WKUPFLAG ((uint8_t)0x20) +#define PWC_NMI_WKUPFLAG ((uint8_t)0x40) + +#define PWC_RTCPRD_WKUPFALG ((uint8_t)0x10) +#define PWC_RTCAL_WKUPFLAG ((uint8_t)0x20) +#define PWC_WKTM_WKUPFLAG ((uint8_t)0x80) + +#define PWC_WKTMCMP_MSK ((uint16_t)0x0FFF) + +#define PWC_FCG0_PERIPH_SRAMH ((uint32_t)0x00000001) +#define PWC_FCG0_PERIPH_SRAM12 ((uint32_t)0x00000010) +#define PWC_FCG0_PERIPH_SRAM3 ((uint32_t)0x00000100) +#define PWC_FCG0_PERIPH_SRAMRET ((uint32_t)0x00000400) +#define PWC_FCG0_PERIPH_DMA1 ((uint32_t)0x00004000) +#define PWC_FCG0_PERIPH_DMA2 ((uint32_t)0x00008000) +#define PWC_FCG0_PERIPH_FCM ((uint32_t)0x00010000) +#define PWC_FCG0_PERIPH_AOS ((uint32_t)0x00020000) +#define PWC_FCG0_PERIPH_AES ((uint32_t)0x00100000) +#define PWC_FCG0_PERIPH_HASH ((uint32_t)0x00200000) +#define PWC_FCG0_PERIPH_TRNG ((uint32_t)0x00400000) +#define PWC_FCG0_PERIPH_CRC ((uint32_t)0x00800000) +#define PWC_FCG0_PERIPH_DCU1 ((uint32_t)0x01000000) +#define PWC_FCG0_PERIPH_DCU2 ((uint32_t)0x02000000) +#define PWC_FCG0_PERIPH_DCU3 ((uint32_t)0x04000000) +#define PWC_FCG0_PERIPH_DCU4 ((uint32_t)0x08000000) +#define PWC_FCG0_PERIPH_KEY ((uint32_t)0x80000000) + + +#define PWC_FCG1_PERIPH_CAN ((uint32_t)0x00000001) +#define PWC_FCG1_PERIPH_QSPI ((uint32_t)0x00000008) +#define PWC_FCG1_PERIPH_I2C1 ((uint32_t)0x00000010) +#define PWC_FCG1_PERIPH_I2C2 ((uint32_t)0x00000020) +#define PWC_FCG1_PERIPH_I2C3 ((uint32_t)0x00000040) +#define PWC_FCG1_PERIPH_USBFS ((uint32_t)0x00000100) +#define PWC_FCG1_PERIPH_SDIOC1 ((uint32_t)0x00000400) +#define PWC_FCG1_PERIPH_SDIOC2 ((uint32_t)0x00000800) +#define PWC_FCG1_PERIPH_I2S1 ((uint32_t)0x00001000) +#define PWC_FCG1_PERIPH_I2S2 ((uint32_t)0x00002000) +#define PWC_FCG1_PERIPH_I2S3 ((uint32_t)0x00004000) +#define PWC_FCG1_PERIPH_I2S4 ((uint32_t)0x00008000) +#define PWC_FCG1_PERIPH_SPI1 ((uint32_t)0x00010000) +#define PWC_FCG1_PERIPH_SPI2 ((uint32_t)0x00020000) +#define PWC_FCG1_PERIPH_SPI3 ((uint32_t)0x00040000) +#define PWC_FCG1_PERIPH_SPI4 ((uint32_t)0x00080000) +#define PWC_FCG1_PERIPH_USART1 ((uint32_t)0x01000000) +#define PWC_FCG1_PERIPH_USART2 ((uint32_t)0x02000000) +#define PWC_FCG1_PERIPH_USART3 ((uint32_t)0x04000000) +#define PWC_FCG1_PERIPH_USART4 ((uint32_t)0x08000000) + +#define PWC_FCG2_PERIPH_TIM01 ((uint32_t)0x00000001) +#define PWC_FCG2_PERIPH_TIM02 ((uint32_t)0x00000002) +#define PWC_FCG2_PERIPH_TIMA1 ((uint32_t)0x00000004) +#define PWC_FCG2_PERIPH_TIMA2 ((uint32_t)0x00000008) +#define PWC_FCG2_PERIPH_TIMA3 ((uint32_t)0x00000010) +#define PWC_FCG2_PERIPH_TIMA4 ((uint32_t)0x00000020) +#define PWC_FCG2_PERIPH_TIMA5 ((uint32_t)0x00000040) +#define PWC_FCG2_PERIPH_TIMA6 ((uint32_t)0x00000080) +#define PWC_FCG2_PERIPH_TIM41 ((uint32_t)0x00000100) +#define PWC_FCG2_PERIPH_TIM42 ((uint32_t)0x00000200) +#define PWC_FCG2_PERIPH_TIM43 ((uint32_t)0x00000400) +#define PWC_FCG2_PERIPH_EMB ((uint32_t)0x00008000) +#define PWC_FCG2_PERIPH_TIM61 ((uint32_t)0x00010000) +#define PWC_FCG2_PERIPH_TIM62 ((uint32_t)0x00020000) +#define PWC_FCG2_PERIPH_TIM63 ((uint32_t)0x00040000) + +#define PWC_FCG3_PERIPH_ADC1 ((uint32_t)0x00000001) +#define PWC_FCG3_PERIPH_ADC2 ((uint32_t)0x00000002) +#define PWC_FCG3_PERIPH_CMP ((uint32_t)0x00000100) +#define PWC_FCG3_PERIPH_OTS ((uint32_t)0x00001000) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg); +void PWC_EnterPowerDownMd(void); + +void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState); +void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState); +void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState); +void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge); + +en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag); +en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag); +void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag); +void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag); +void PWC_PwrMonitorCmd(en_functional_state_t enNewState); + +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg); +void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState); + +void PWC_EnterStopMd(void); +void PWC_EnterSleepMd(void); + +void PWC_Xtal32CsCmd(en_functional_state_t enNewState); +void PWC_HrcPwrCmd(en_functional_state_t enNewState); +void PWC_PllPwrCmd(en_functional_state_t enNewState); +void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState); +void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd); + +void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl); + +void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg); +void PWC_Pvd1Cmd(en_functional_state_t enNewState); +void PWC_Pvd2Cmd(en_functional_state_t enNewState); +void PWC_ExVccCmd(en_functional_state_t enNewState); +void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd); +en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd); +en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd); + +void PWC_enNvicBackup(void); +void PWC_enNvicRecover(void); +void PWC_ClkBackup(void); +void PWC_ClkRecover(void); +void PWC_IrqClkBackup(void); +void PWC_IrqClkRecover(void); + +en_result_t PWC_HS2LS(void); +en_result_t PWC_LS2HS(void); +en_result_t PWC_HS2HP(void); +en_result_t PWC_HP2HS(void); +en_result_t PWC_LS2HP(void); +en_result_t PWC_HP2LS(void); + +//@} // PwcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_PWC_ENABLE */ + +#endif /* __HC32F460_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_qspi.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_qspi.h new file mode 100644 index 0000000000..6bcbf6de09 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_qspi.h @@ -0,0 +1,402 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_qspi.h + ** + ** A detailed description is available at + ** @link QspiGroup Queued SPI description @endlink + ** + ** - 2018-11-20 CDT First version for Device Driver Library of Qspi. + ** + ******************************************************************************/ +#ifndef __HC32F460_QSPI_H__ +#define __HC32F460_QSPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_QSPI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup QspiGroup Queued SPI(QSPI) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief QSPI spi protocol enumeration + ******************************************************************************/ +typedef enum en_qspi_spi_protocol +{ + QspiProtocolExtendSpi = 0u, ///< Extend spi protocol + QspiProtocolTwoWiresSpi = 1u, ///< Two wires spi protocol + QspiProtocolFourWiresSpi = 2u, ///< Four wires spi protocol +} en_qspi_spi_protocol_t; + +/** + ******************************************************************************* + ** \brief QSPI spi Mode enumeration + ******************************************************************************/ +typedef enum en_qspi_spi_mode +{ + QspiSpiMode0 = 0u, ///< Spi mode 0(QSCK normalcy is Low level) + QspiSpiMode3 = 1u, ///< Spi mode 3(QSCK normalcy is High level) +} en_qspi_spi_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI bus communication mode enumeration + ******************************************************************************/ +typedef enum en_qspi_bus_mode +{ + QspiBusModeRomAccess = 0u, ///< Rom access mode + QspiBusModeDirectAccess = 1u, ///< Direct communication mode +} en_qspi_bus_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI prefetch data stop config enumeration + ******************************************************************************/ +typedef enum en_qspi_prefetch_config +{ + QspiPrefetchStopComplete = 0u, ///< Stop after prefetch data complete + QspiPrefetchStopImmediately = 1u, ///< Immediately stop prefetch +} en_qspi_prefetch_config_t; + +/** + ******************************************************************************* + ** \brief QSPI read mode enumeration + ******************************************************************************/ +typedef enum en_qspi_read_mode +{ + QspiReadModeStandard = 0u, ///< Standard read + QspiReadModeFast = 1u, ///< Fast read + QspiReadModeTwoWiresOutput = 2u, ///< Two wires output fast read + QspiReadModeTwoWiresIO = 3u, ///< Two wires input/output fast read + QspiReadModeFourWiresOutput = 4u, ///< Four wires output fast read + QspiReadModeFourWiresIO = 5u, ///< Four wires input/output fast read + QspiReadModeCustomStandard = 6u, ///< Custom standard read + QspiReadModeCustomFast = 7u, ///< Custom fast read +} en_qspi_read_mode_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN valid extend time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_valid_extend_time +{ + QspiQssnValidExtendNot = 0u, ///< Don't extend QSSN valid time + QspiQssnValidExtendSck32 = 1u, ///< QSSN valid time extend 32 QSCK cycles + QspiQssnValidExtendSck128 = 2u, ///< QSSN valid time extend 138 QSCK cycles + QspiQssnValidExtendSckEver = 3u, ///< QSSN valid time extend to ever +} en_qspi_qssn_valid_extend_time_t; + +/** + ******************************************************************************* + ** \brief QSPI QSCK duty cycle correction enumeration + ******************************************************************************/ +typedef enum en_qspi_qsck_duty_correction +{ + QspiQsckDutyCorrNot = 0u, ///< Don't correction duty cycle + QspiQsckDutyCorrHalfHclk = 1u, ///< QSCK's rising edge delay 0.5 HCLK cycle when Qsck select HCLK is odd +} en_qspi_qsck_duty_correction_t; + +/** + ******************************************************************************* + ** \brief QSPI WP Pin output level enumeration + ******************************************************************************/ +typedef enum en_qspi_wp_pin_level +{ + QspiWpPinOutputLow = 0u, ///< WP pin(QIO2) output low level + QspiWpPinOutputHigh = 1u, ///< WP pin(QIO2) output high level +} en_qspi_wp_pin_level_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN setup delay time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_setup_delay +{ + QspiQssnSetupDelayHalfQsck = 0u, ///< QSSN setup delay 0.5 QSCK output than QSCK first rising edge + QspiQssnSetupDelay1Dot5Qsck = 1u, ///< QSSN setup delay 1.5 QSCK output than QSCK first rising edge +} en_qspi_qssn_setup_delay_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN hold delay time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_hold_delay +{ + QspiQssnHoldDelayHalfQsck = 0u, ///< QSSN hold delay 0.5 QSCK release than QSCK last rising edge + QspiQssnHoldDelay1Dot5Qsck = 1u, ///< QSSN hold delay 1.5 QSCK release than QSCK last rising edge +} en_qspi_qssn_hold_delay_t; + +/** + ******************************************************************************* + ** \brief QSPI address width enumeration + ******************************************************************************/ +typedef enum en_qspi_addr_width +{ + QspiAddressByteOne = 0u, ///< One byte address + QspiAddressByteTwo = 1u, ///< Two byte address + QspiAddressByteThree = 2u, ///< Three byte address + QspiAddressByteFour = 3u, ///< Four byte address +} en_qspi_addr_width_t; + +/** + ******************************************************************************* + ** \brief QSPI flag type enumeration + ******************************************************************************/ +typedef enum en_qspi_flag_type +{ + QspiFlagBusBusy = 0u, ///< QSPI bus work status flag in direct communication mode + QspiFlagXipMode = 1u, ///< XIP mode status signal + QspiFlagRomAccessError = 2u, ///< Trigger rom access error flag in direct communication mode + QspiFlagPrefetchBufferFull = 3u, ///< Prefetch buffer area status signal + QspiFlagPrefetchStop = 4u, ///< Prefetch action status signal +} en_qspi_flag_type_t; + +/** + ******************************************************************************* + ** \brief QSPI clock division enumeration + ******************************************************************************/ +typedef enum en_qspi_clk_div +{ + QspiHclkDiv2 = 0u, ///< Clock source: HCLK/2 + QspiHclkDiv3 = 2u, ///< Clock source: HCLK/3 + QspiHclkDiv4 = 3u, ///< Clock source: HCLK/4 + QspiHclkDiv5 = 4u, ///< Clock source: HCLK/5 + QspiHclkDiv6 = 5u, ///< Clock source: HCLK/6 + QspiHclkDiv7 = 6u, ///< Clock source: HCLK/7 + QspiHclkDiv8 = 7u, ///< Clock source: HCLK/8 + QspiHclkDiv9 = 8u, ///< Clock source: HCLK/9 + QspiHclkDiv10 = 9u, ///< Clock source: HCLK/10 + QspiHclkDiv11 = 10u, ///< Clock source: HCLK/11 + QspiHclkDiv12 = 11u, ///< Clock source: HCLK/12 + QspiHclkDiv13 = 12u, ///< Clock source: HCLK/13 + QspiHclkDiv14 = 13u, ///< Clock source: HCLK/14 + QspiHclkDiv15 = 14u, ///< Clock source: HCLK/15 + QspiHclkDiv16 = 15u, ///< Clock source: HCLK/16 + QspiHclkDiv17 = 16u, ///< Clock source: HCLK/17 + QspiHclkDiv18 = 17u, ///< Clock source: HCLK/18 + QspiHclkDiv19 = 18u, ///< Clock source: HCLK/19 + QspiHclkDiv20 = 19u, ///< Clock source: HCLK/20 + QspiHclkDiv21 = 20u, ///< Clock source: HCLK/21 + QspiHclkDiv22 = 21u, ///< Clock source: HCLK/22 + QspiHclkDiv23 = 22u, ///< Clock source: HCLK/23 + QspiHclkDiv24 = 23u, ///< Clock source: HCLK/24 + QspiHclkDiv25 = 24u, ///< Clock source: HCLK/25 + QspiHclkDiv26 = 25u, ///< Clock source: HCLK/26 + QspiHclkDiv27 = 26u, ///< Clock source: HCLK/27 + QspiHclkDiv28 = 27u, ///< Clock source: HCLK/28 + QspiHclkDiv29 = 28u, ///< Clock source: HCLK/29 + QspiHclkDiv30 = 29u, ///< Clock source: HCLK/30 + QspiHclkDiv31 = 30u, ///< Clock source: HCLK/31 + QspiHclkDiv32 = 31u, ///< Clock source: HCLK/32 + QspiHclkDiv33 = 32u, ///< Clock source: HCLK/33 + QspiHclkDiv34 = 33u, ///< Clock source: HCLK/34 + QspiHclkDiv35 = 34u, ///< Clock source: HCLK/35 + QspiHclkDiv36 = 35u, ///< Clock source: HCLK/36 + QspiHclkDiv37 = 36u, ///< Clock source: HCLK/37 + QspiHclkDiv38 = 37u, ///< Clock source: HCLK/38 + QspiHclkDiv39 = 38u, ///< Clock source: HCLK/39 + QspiHclkDiv40 = 39u, ///< Clock source: HCLK/40 + QspiHclkDiv41 = 40u, ///< Clock source: HCLK/41 + QspiHclkDiv42 = 41u, ///< Clock source: HCLK/42 + QspiHclkDiv43 = 42u, ///< Clock source: HCLK/43 + QspiHclkDiv44 = 43u, ///< Clock source: HCLK/44 + QspiHclkDiv45 = 44u, ///< Clock source: HCLK/45 + QspiHclkDiv46 = 45u, ///< Clock source: HCLK/46 + QspiHclkDiv47 = 46u, ///< Clock source: HCLK/47 + QspiHclkDiv48 = 47u, ///< Clock source: HCLK/48 + QspiHclkDiv49 = 48u, ///< Clock source: HCLK/49 + QspiHclkDiv50 = 49u, ///< Clock source: HCLK/50 + QspiHclkDiv51 = 50u, ///< Clock source: HCLK/51 + QspiHclkDiv52 = 51u, ///< Clock source: HCLK/52 + QspiHclkDiv53 = 52u, ///< Clock source: HCLK/53 + QspiHclkDiv54 = 53u, ///< Clock source: HCLK/54 + QspiHclkDiv55 = 54u, ///< Clock source: HCLK/55 + QspiHclkDiv56 = 55u, ///< Clock source: HCLK/56 + QspiHclkDiv57 = 56u, ///< Clock source: HCLK/57 + QspiHclkDiv58 = 57u, ///< Clock source: HCLK/58 + QspiHclkDiv59 = 58u, ///< Clock source: HCLK/59 + QspiHclkDiv60 = 59u, ///< Clock source: HCLK/60 + QspiHclkDiv61 = 60u, ///< Clock source: HCLK/61 + QspiHclkDiv62 = 61u, ///< Clock source: HCLK/62 + QspiHclkDiv63 = 62u, ///< Clock source: HCLK/63 + QspiHclkDiv64 = 63u, ///< Clock source: HCLK/64 +} en_qspi_clk_div_t; + +/** + ******************************************************************************* + ** \brief QSPI QSSN minimum interval time enumeration + ******************************************************************************/ +typedef enum en_qspi_qssn_interval_time +{ + QspiQssnIntervalQsck1 = 0u, ///< QSSN signal min interval time 1 QSCK + QspiQssnIntervalQsck2 = 1u, ///< QSSN signal min interval time 2 QSCK + QspiQssnIntervalQsck3 = 2u, ///< QSSN signal min interval time 3 QSCK + QspiQssnIntervalQsck4 = 3u, ///< QSSN signal min interval time 4 QSCK + QspiQssnIntervalQsck5 = 4u, ///< QSSN signal min interval time 5 QSCK + QspiQssnIntervalQsck6 = 5u, ///< QSSN signal min interval time 6 QSCK + QspiQssnIntervalQsck7 = 6u, ///< QSSN signal min interval time 7 QSCK + QspiQssnIntervalQsck8 = 7u, ///< QSSN signal min interval time 8 QSCK + QspiQssnIntervalQsck9 = 8u, ///< QSSN signal min interval time 9 QSCK + QspiQssnIntervalQsck10 = 9u, ///< QSSN signal min interval time 10 QSCK + QspiQssnIntervalQsck11 = 10u, ///< QSSN signal min interval time 11 QSCK + QspiQssnIntervalQsck12 = 11u, ///< QSSN signal min interval time 12 QSCK + QspiQssnIntervalQsck13 = 12u, ///< QSSN signal min interval time 13 QSCK + QspiQssnIntervalQsck14 = 13u, ///< QSSN signal min interval time 14 QSCK + QspiQssnIntervalQsck15 = 14u, ///< QSSN signal min interval time 15 QSCK + QspiQssnIntervalQsck16 = 15u, ///< QSSN signal min interval time 16 QSCK +} en_qspi_qssn_interval_time_t; + +/** + ******************************************************************************* + ** \brief QSPI virtual period enumeration + ******************************************************************************/ +typedef enum en_qspi_virtual_period +{ + QspiVirtualPeriodQsck3 = 0u, ///< Virtual period select 3 QSCK + QspiVirtualPeriodQsck4 = 1u, ///< Virtual period select 4 QSCK + QspiVirtualPeriodQsck5 = 2u, ///< Virtual period select 5 QSCK + QspiVirtualPeriodQsck6 = 3u, ///< Virtual period select 6 QSCK + QspiVirtualPeriodQsck7 = 4u, ///< Virtual period select 7 QSCK + QspiVirtualPeriodQsck8 = 5u, ///< Virtual period select 8 QSCK + QspiVirtualPeriodQsck9 = 6u, ///< Virtual period select 9 QSCK + QspiVirtualPeriodQsck10 = 7u, ///< Virtual period select 10 QSCK + QspiVirtualPeriodQsck11 = 8u, ///< Virtual period select 11 QSCK + QspiVirtualPeriodQsck12 = 9u, ///< Virtual period select 12 QSCK + QspiVirtualPeriodQsck13 = 10u, ///< Virtual period select 13 QSCK + QspiVirtualPeriodQsck14 = 11u, ///< Virtual period select 14 QSCK + QspiVirtualPeriodQsck15 = 12u, ///< Virtual period select 15 QSCK + QspiVirtualPeriodQsck16 = 13u, ///< Virtual period select 16 QSCK + QspiVirtualPeriodQsck17 = 14u, ///< Virtual period select 17 QSCK + QspiVirtualPeriodQsck18 = 15u, ///< Virtual period select 18 QSCK +} en_qspi_virtual_period_t; + +/** + ******************************************************************************* + ** \brief QSPI communication protocol structure definition + ******************************************************************************/ +typedef struct stc_qspi_comm_protocol +{ + en_qspi_spi_protocol_t enReceProtocol; ///< Receive data stage SPI protocol + en_qspi_spi_protocol_t enTransAddrProtocol; ///< Transmit address stage SPI protocol + en_qspi_spi_protocol_t enTransInstrProtocol; ///< Transmit instruction stage SPI protocol + en_qspi_read_mode_t enReadMode; ///< Serial interface read mode +} stc_qspi_comm_protocol_t; + +/** + ******************************************************************************* + ** \brief QSPI init structure definition + ******************************************************************************/ +typedef struct stc_qspi_init +{ + en_qspi_clk_div_t enClkDiv; ///< Clock division + en_qspi_spi_mode_t enSpiMode; ///< Specifies SPI mode + en_qspi_bus_mode_t enBusCommMode; ///< Bus communication mode + en_qspi_prefetch_config_t enPrefetchMode; ///< Config prefetch stop location + en_functional_state_t enPrefetchFuncEn; ///< Disable: disable prefetch function, Enable: enable prefetch function + stc_qspi_comm_protocol_t stcCommProtocol; ///< Qspi communication protocol config + en_qspi_qssn_valid_extend_time_t enQssnValidExtendTime; ///< QSSN valid extend time function select after QSPI access bus + en_qspi_qssn_interval_time_t enQssnIntervalTime; ///< QSSN minimum interval time + en_qspi_qsck_duty_correction_t enQsckDutyCorr; ///< QSCK output duty cycles correction + en_qspi_virtual_period_t enVirtualPeriod; ///< Virtual period config + en_qspi_wp_pin_level_t enWpPinLevel; ///< WP pin(QIO2) level select + en_qspi_qssn_setup_delay_t enQssnSetupDelayTime; ///< QSSN setup delay time choose + en_qspi_qssn_hold_delay_t enQssnHoldDelayTime; ///< QSSN hold delay time choose + en_functional_state_t enFourByteAddrReadEn; ///< Read instruction code select when set address width is four bytes + en_qspi_addr_width_t enAddrWidth; ///< Serial interface address width choose + uint8_t u8RomAccessInstr; ///< Rom access mode instruction +} stc_qspi_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< 4-byte instruction mode using instruction set */ +#define QSPI_4BINSTR_STANDARD_READ 0x13u +#define QSPI_4BINSTR_FAST_READ 0x0Cu +#define QSPI_4BINSTR_TWO_WIRES_OUTPUT_READ 0x3Cu +#define QSPI_4BINSTR_TWO_WIRES_IO_READ 0xBCu +#define QSPI_4BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Cu +#define QSPI_4BINSTR_FOUR_WIRES_IO_READ 0xECu +#define QSPI_4BINSTR_EXIT_4BINSTR_MODE 0xB7u + +/*!< 3-byte instruction mode using instruction set */ +#define QSPI_3BINSTR_STANDARD_READ 0x03u +#define QSPI_3BINSTR_FAST_READ 0x0Bu +#define QSPI_3BINSTR_TWO_WIRES_OUTPUT_READ 0x3Bu +#define QSPI_3BINSTR_TWO_WIRES_IO_READ 0xBBu +#define QSPI_3BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Bu +#define QSPI_3BINSTR_FOUR_WIRES_IO_READ 0xEBu +#define QSPI_3BINSTR_ENTER_4BINSTR_MODE 0xE9u + +/*!< General instruction set */ +#define QSPI_WRITE_MODE_ENABLE 0x06u + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t QSPI_DeInit(void); +en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg); +en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth); +en_result_t QSPI_SetExtendAddress(uint8_t u8Addr); +en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol); +en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta); +en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv); +en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel); + +/* Rom access mode functions */ +en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr); +en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta); + +/* Direct communication mode functions */ +en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val); +uint8_t QSPI_ReadDirectCommValue(void); +en_result_t QSPI_EnterDirectCommMode(void); +en_result_t QSPI_ExitDirectCommMode(void); + +/* Flags and get buffer functions */ +uint8_t QSPI_GetPrefetchBufferNum(void); +en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag); +en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag); + +//@} // QspiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_QSPI_ENABLE */ + +#endif /* __HC32F460_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rmu.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rmu.h new file mode 100644 index 0000000000..1217490bf2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rmu.h @@ -0,0 +1,96 @@ +/***************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rmu.h + ** + ** A detailed description is available at + ** @link RmuGroup RMU description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of RMU + ** + ******************************************************************************/ +#ifndef __HC32F460_RMU_H__ +#define __HC32F460_RMU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_RMU_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup RmuGroup Reset Management Unit(RMU) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief system reset cause flag + ** + ******************************************************************************/ +typedef struct stc_rmu_rstcause +{ + en_flag_status_t enMultiRst; ///< Multiply reset cause + en_flag_status_t enXtalErr; ///< Xtal error reset + en_flag_status_t enClkFreqErr; ///< Clk freqence error reset + en_flag_status_t enRamEcc; ///< Ram ECC reset + en_flag_status_t enRamParityErr; ///< Ram parity error reset + en_flag_status_t enMpuErr; ///< Mpu error reset + en_flag_status_t enSoftware; ///< Software reset + en_flag_status_t enPowerDown; ///< Power down reset + en_flag_status_t enSwdt; ///< Special watchdog timer reset + en_flag_status_t enWdt; ///< Watchdog timer reset + en_flag_status_t enPvd2; ///< Program voltage Dectection 2 reset + en_flag_status_t enPvd1; ///< Program voltage Dectection 1 reset + en_flag_status_t enBrownOut; ///< Brown out reset + en_flag_status_t enRstPin; ///< Reset pin reset + en_flag_status_t enPowerOn; ///< Power on reset +}stc_rmu_rstcause_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData); +en_result_t RMU_ClrResetFlag(void); + +//@} // RmuGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_RMU_ENABLE */ + +#endif /* __HC32F460_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rtc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rtc.h new file mode 100644 index 0000000000..31544f03f4 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_rtc.h @@ -0,0 +1,274 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rtc.h + ** + ** A detailed description is available at + ** @link RtcGroup Real-Time Clock description @endlink + ** + ** - 2018-11-22 CDT First version for Device Driver Library of RTC. + ** + ******************************************************************************/ +#ifndef __HC32F460_RTC_H__ +#define __HC32F460_RTC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_RTC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup RtcGroup Real-Time Clock(RTC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief RTC period interrupt type enumeration + ******************************************************************************/ +typedef enum en_rtc_period_int_type +{ + RtcPeriodIntInvalid = 0u, ///< Period interrupt invalid + RtcPeriodIntHalfSec = 1u, ///< 0.5 second period interrupt + RtcPeriodIntOneSec = 2u, ///< 1 second period interrupt + RtcPeriodIntOneMin = 3u, ///< 1 minute period interrupt + RtcPeriodIntOneHour = 4u, ///< 1 hour period interrupt + RtcPeriodIntOneDay = 5u, ///< 1 day period interrupt + RtcPeriodIntOneMon = 6u ///< 1 month period interrupt +} en_rtc_period_int_type_t; + +/** + ******************************************************************************* + ** \brief RTC time format enumeration + ******************************************************************************/ +typedef enum en_rtc_time_format +{ + RtcTimeFormat12Hour = 0u, ///< 12 hours mode + RtcTimeFormat24Hour = 1u, ///< 24 hours mode +} en_rtc_time_format_t; + +/** + ******************************************************************************* + ** \brief RTC 1Hz output compensation way enumeration + ******************************************************************************/ +typedef enum en_rtc_output_compen +{ + RtcOutputCompenDistributed = 0u, ///< Distributed compensation 1hz output + RtcOutputCompenUniform = 1u, ///< Uniform Compensation 1hz output +} en_rtc_output_compen_t; + +/** + ******************************************************************************* + ** \brief RTC work mode enumeration + ******************************************************************************/ +typedef enum en_rtc_work_mode +{ + RtcModeNormalCount = 0u, ///< Normal count mode + RtcModeReadOrWrite = 1u, ///< Read or write mode +} en_rtc_work_mode_t; + +/** + ******************************************************************************* + ** \brief RTC count clock source enumeration + ******************************************************************************/ +typedef enum en_rtc_clk_source +{ + RtcClkXtal32 = 0u, ///< XTAL32 as clock source + RtcClkLrc = 1u, ///< LRC as clock source +} en_rtc_clk_source_t; + +/** + ******************************************************************************* + ** \brief RTC data format enumeration + ******************************************************************************/ +typedef enum en_rtc_data_format +{ + RtcDataFormatDec = 0u, ///< Decimal format + RtcDataFormatBcd = 1u, ///< BCD format +} en_rtc_data_format_t; + +/** + ******************************************************************************* + ** \brief RTC 12 hour AM/PM enumeration + ******************************************************************************/ +typedef enum en_rtc_hour12_ampm +{ + RtcHour12Am = 0u, ///< Ante meridiem + RtcHour12Pm = 1u, ///< Post meridiem +} en_rtc_hour12_ampm_t; + +/** + ******************************************************************************* + ** \brief RTC month enumeration + ******************************************************************************/ +typedef enum en_rtc_month +{ + RtcMonthJanuary = 1u, ///< January + RtcMonthFebruary = 2u, ///< February + RtcMonthMarch = 3u, ///< March + RtcMonthApril = 4u, ///< April + RtcMonthMay = 5u, ///< May + RtcMonthJune = 6u, ///< June + RtcMonthJuly = 7u, ///< July + RtcMonthAugust = 8u, ///< August + RtcMonthSeptember = 9u, ///< September + RtcMonthOctober = 10u, ///< October + RtcMonthNovember = 11u, ///< November + RtcMonthDecember = 12u, ///< December +} en_rtc_month_t; + +/** + ******************************************************************************* + ** \brief RTC weekday enumeration + ******************************************************************************/ +typedef enum en_rtc_weekday +{ + RtcWeekdaySunday = 0u, ///< Sunday + RtcWeekdayMonday = 1u, ///< Monday + RtcWeekdayTuesday = 2u, ///< Tuesday + RtcWeekdayWednesday = 3u, ///< Wednesday + RtcWeekdayThursday = 4u, ///< Thursday + RtcWeekdayFriday = 5u, ///< Friday + RtcWeekdaySaturday = 6u ///< Saturday +} en_rtc_weekday_t; + +/** + ******************************************************************************* + ** \brief RTC alarm weekday enumeration + ******************************************************************************/ +typedef enum en_rtc_alarm_weekday +{ + RtcAlarmWeekdaySunday = 0x01u, ///< Sunday + RtcAlarmWeekdayMonday = 0x02u, ///< Monday + RtcAlarmWeekdayTuesday = 0x04u, ///< Tuesday + RtcAlarmWeekdayWednesday = 0x08u, ///< Wednesday + RtcAlarmWeekdayThursday = 0x10u, ///< Thursday + RtcAlarmWeekdayFriday = 0x20u, ///< Friday + RtcAlarmWeekdaySaturday = 0x40u, ///< Saturday +} en_rtc_alarm_weekday_t; + +/** + ******************************************************************************* + ** \brief RTC interrupt request type enumeration + ******************************************************************************/ +typedef enum en_rtc_irq_type_ +{ + RtcIrqPeriod = 0u, ///< Period count interrupt request + RtcIrqAlarm = 1u, ///< Alarm interrupt request +} en_rtc_irq_type_t; + +/** + ******************************************************************************* + ** \brief RTC date and time structure definition + ******************************************************************************/ +typedef struct stc_rtc_date_time +{ + uint8_t u8Year; ///< Year (range 0-99) + uint8_t u8Month; ///< Month (range 1-12) + uint8_t u8Day; ///< Day (range 1-31) + uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format) + uint8_t u8Minute; ///< Minutes (range 0-59) + uint8_t u8Second; ///< Seconds (range 0-59) + uint8_t u8Weekday; ///< Weekday (range 0-6) + en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format +} stc_rtc_date_time_t; + +/** + ******************************************************************************* + ** \brief RTC alarm time structure definition + ******************************************************************************/ +typedef struct stc_rtc_alarm_time +{ + uint8_t u8Minute; ///< Minutes (range 0-59) + uint8_t u8Hour; ///< Hours (range 1-12 when 12 hour format; range 0-23 when 24 hour format) + uint8_t u8Weekday; ///< Weekday (range RtcAlarmWeekdaySunday to RtcAlarmWeekdaySaturday) + en_rtc_hour12_ampm_t enAmPm; ///< The value is valid when 12-hour format +} stc_rtc_alarm_time_t; + +/** + ******************************************************************************* + ** \brief RTC init structure definition + ******************************************************************************/ +typedef struct stc_rtc_init +{ + en_rtc_clk_source_t enClkSource; ///< Clock source + en_rtc_period_int_type_t enPeriodInt; ///< Period interrupt condition + en_rtc_time_format_t enTimeFormat; ///< RTC time format + en_rtc_output_compen_t enCompenWay; ///< 1HZ output compensation way + uint16_t u16CompenVal; ///< Clock error compensation value + en_functional_state_t enCompenEn; ///< Enable/Disable clock error compensation +} stc_rtc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t RTC_DeInit(void); +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +en_result_t RTC_Cmd(en_functional_state_t enNewSta); +en_result_t RTC_EnterRwMode(void); +en_result_t RTC_ExitRwMode(void); + +/* Extend functions */ +en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType); +en_result_t RTC_LowPowerSwitch(void); +en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal); +en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta); +en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta); + +/* Date and time functions */ +en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime, + en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn); +en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime); + +/* Alarm functions */ +en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime); +en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime); +en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta); + +/* Interrupt and flags management functions ******************************************/ +en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta); +en_flag_status_t RTC_GetAlarmFlag(void); +en_result_t RTC_ClearAlarmFlag(void); + +//@} // RtcGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_RTC_ENABLE */ + +#endif /* __HC32F460_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sdioc.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sdioc.h new file mode 100644 index 0000000000..2fd546a97a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sdioc.h @@ -0,0 +1,559 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sdioc.h + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-11 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ +#ifndef __HC32F460_SDIOC_H__ +#define __HC32F460_SDIOC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SDIOC_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SdiocGroup Secure Digital Input and Output Controller(SDIOC) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SDIOC mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_mode +{ + SdiocModeSD = 0u, ///< The SD mode + SdiocModeMMC = 1u, ///< The MMC mode +} en_sdioc_mode_t; + +/** + ******************************************************************************* + ** \brief SDIOC transfer bus width enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_bus_width +{ + SdiocBusWidth4Bit = 0u, ///< The SDIOC bus width 4 bit + SdiocBusWidth8Bit = 1u, ///< The SDIOC bus width 8 bit + SdiocBusWidth1Bit = 2u, ///< The SDIOC bus width 1 bit +} en_sdioc_bus_width_t; + +/** + ******************************************************************************* + ** \brief SDIOC clock division enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_clk_div +{ + SdiocClkDiv_1 = 0x00u, ///< EXCLK/1 + SdiocClkDiv_2 = 0x01u, ///< EXCLK/2 + SdiocClkDiv_4 = 0x02u, ///< EXCLK/4 + SdiocClkDiv_8 = 0x04u, ///< EXCLK/8 + SdiocClkDiv_16 = 0x08u, ///< EXCLK/16 + SdiocClkDiv_32 = 0x10u, ///< EXCLK/32 + SdiocClkDiv_64 = 0x20u, ///< EXCLK/64 + SdiocClkDiv_128 = 0x40u, ///< EXCLK/128 + SdiocClkDiv_256 = 0x80u, ///< EXCLK/256 +} en_sdioc_clk_div_t; + +/** + ******************************************************************************* + ** \brief SDIOC response type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_type +{ + SdiocResponseNoneBit = 0u, ///< No Response + SdiocResponse136Bit = 1u, ///< Response Length 136 + SdiocResponse48Bit = 2u, ///< Response Length 48 + SdiocResponse48BitCheckBusy = 3u, ///< Response Length 48 check Busy after response +} en_sdioc_response_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC response index enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_index +{ + SdiocCmdNoRsp = 0u, ///< No Response + SdiocCmdRspR1 = 1u, ///< Command Response 1 + SdiocCmdRspR1b = 2u, ///< Command Response 1 with busy + SdiocCmdRspR2 = 3u, ///< Command Response 2 + SdiocCmdRspR3 = 4u, ///< Command Response 3 + SdiocCmdRspR4 = 5u, ///< Command Response 4 + SdiocCmdRspR5 = 6u, ///< Command Response 5 + SdiocCmdRspR5b = 7u, ///< Command Response 5 with busy + SdiocCmdRspR6 = 8u, ///< Command Response 6 + SdiocCmdRspR7 = 9u, ///< Command Response 7 +} en_sdioc_response_index_t; + +/** + ******************************************************************************* + ** \brief SDIOC command type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_cmd_type +{ + SdiocCmdNormal = 0u, ///< Other commands + SdiocCmdSuspend = 1u, ///< CMD52 for writing "Bus Suspend" in CCCR + SdiocCmdResume = 2u, ///< CMD52 for writing "Function Select" in CCCR + SdiocCmdAbort = 3u, ///< CMD12, CMD52 for writing "I/O Abort" in CCCR +} en_sdioc_cmd_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC data transfer direction enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_transfer_dir +{ + SdiocTransferToCard = 0u, ///< Write (Host to Card) + SdiocTransferToHost = 1u, ///< Read (Card to Host) +} en_sdioc_transfer_dir_t; + +/** + ******************************************************************************* + ** \brief SDIOC data transfer mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_transfer_mode +{ + SdiocTransferSingle = 0u, ///< Single Block transfer + SdiocTransferInfinite = 1u, ///< Infinite Block transfer + SdiocTransferMultiple = 2u, ///< Multiple Block transfer + SdiocTransferStopMultiple = 3u, ///< Stop Multiple Block transfer +} en_sdioc_transfer_mode_t; + +/** + ******************************************************************************* + ** \brief SD data timeout time enumeration + ** + ******************************************************************************/ +typedef enum en_sd_data_timeout +{ + SdiocDtoSdclk_2_13 = 0u, ///< Timeout time: SDCLK*2^13 + SdiocDtoSdclk_2_14 = 1u, ///< Timeout time: SDCLK*2^14 + SdiocDtoSdclk_2_15 = 2u, ///< Timeout time: SDCLK*2^15 + SdiocDtoSdclk_2_16 = 3u, ///< Timeout time: SDCLK*2^16 + SdiocDtoSdclk_2_17 = 4u, ///< Timeout time: SDCLK*2^17 + SdiocDtoSdclk_2_18 = 5u, ///< Timeout time: SDCLK*2^18 + SdiocDtoSdclk_2_19 = 6u, ///< Timeout time: SDCLK*2^19 + SdiocDtoSdclk_2_20 = 7u, ///< Timeout time: SDCLK*2^20 + SdiocDtoSdclk_2_21 = 8u, ///< Timeout time: SDCLK*2^21 + SdiocDtoSdclk_2_22 = 9u, ///< Timeout time: SDCLK*2^22 + SdiocDtoSdclk_2_23 = 10u, ///< Timeout time: SDCLK*2^23 + SdiocDtoSdclk_2_24 = 11u, ///< Timeout time: SDCLK*2^24 + SdiocDtoSdclk_2_25 = 12u, ///< Timeout time: SDCLK*2^25 + SdiocDtoSdclk_2_26 = 13u, ///< Timeout time: SDCLK*2^26 + SdiocDtoSdclk_2_27 = 14u, ///< Timeout time: SDCLK*2^27 +} en_sdioc_data_timeout_t; + +/** + ******************************************************************************* + ** \brief SDIOC dat line type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_dat_line_type +{ + SdiocDat0Line = 0u, ///< DAT0 Line + SdiocDat1Line = 1u, ///< DAT1 Line + SdiocDat2Line = 2u, ///< DAT2 Line + SdiocDat3Line = 3u, ///< DAT3 Line +} en_sdioc_dat_line_type_t; + +/** + ******************************************************************************* + ** \brief SDIOC software reset type enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_sw_reset +{ + SdiocSwResetDatLine = 0u, ///< Only part of data circuit is reset. + SdiocSwResetCmdLine = 1u, ///< Only part of command circuit is reset. + SdiocSwResetAll = 2u, ///< Reset the entire Host Controller except for the card detection circuit. +} en_sdioc_sw_reset_t; + +/** + ******************************************************************************* + ** \brief SDIOC host status enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_host_status +{ + SdiocCommandInhibitCmd = (1u << 0), ///< Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line + SdiocCommandInhibitData = (1u << 1), ///< Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line + SdiocDataLineActive = (1u << 2), ///< 1: DAT Line Active; 0: DAT Line Inactive + SdiocWriteTransferActive = (1u << 8), ///< Write Transfer Active.1: Transferring data; 0: No valid data + SdiocReadTransferActive = (1u << 9), ///< Read Transfer Active.1: Transferring data; 0: No valid data + SdiocBufferWriteEnble = (1u << 10), ///< 1: Write enable; 0: Write Disable + SdiocBufferReadEnble = (1u << 11), ///< 1: Read enable; 0: Read Disable + SdiocCardInserted = (1u << 16), ///< 1: Card Inserted; 0: Reset or Debouncing or No Card + SdiocCardStateStable = (1u << 17), ///< 1: No Card or Inserted; 0: Reset or Debouncing + SdiocCardDetectPinLvl = (1u << 18), ///< 1: Card present; 0: No card present + SdiocWriteProtectPinLvl = (1u << 19), ///< 1: Write enabled; 0: Write protected + SdiocData0PinLvl = (1u << 20), ///< 1: DAT0 line signal level high; 0: DAT0 line signal level low + SdiocData1PinLvl = (1u << 21), ///< 1: DAT1 line signal level high; 0: DAT1 line signal level low + SdiocData2PinLvl = (1u << 22), ///< 1: DAT2 line signal level high; 0: DAT2 line signal level low + SdiocData3PinLvl = (1u << 23), ///< 1: DAT3 line signal level high; 0: DAT3 line signal level low + SdiocCmdPinLvl = (1u << 24), ///< 1: CMD line signal level high; 0: CMD line signal level low +} en_sdioc_host_status_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_nor_int_sel +{ + SdiocCommandComplete = (1u << 0), ///< Command Complete. 1: Command complete; 0:No command complete + SdiocTransferComplete = (1u << 1), ///< Transfer Complete. 1: Data transfer complete; 0:No transfer complete + SdiocBlockGapEvent = (1u << 2), ///< Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + SdiocBufferWriteReady = (1u << 4), ///< Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + SdiocBufferReadReady = (1u << 5), ///< Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + SdiocCardInsertedInt = (1u << 6), ///< Write Transfer Active.1: Transferring data; 0: No valid data + SdiocCardRemoval = (1u << 7), ///< Card Removal. 1: Card removed; 0: Card state stable or Debouncing + SdiocCardInt = (1u << 8), ///< Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + SdiocErrorInt = (1u << 15), ///< Error Interrupt. 1: Error; 0: No Error +} en_sdioc_nor_int_sel_t, en_sdioc_nor_int_flag_t; + +/** + ******************************************************************************* + ** \brief SDIOC error interrupt selection enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_err_int_sel +{ + SdiocCmdTimeoutErr = (1u << 0), ///< Command Timeout Error. 1: Timer out; 0:No Error + SdiocCmdCrcErr = (1u << 1), ///< Command CRC Error. 1: Command CRC Error Generated; 0:No Error + SdiocCmdEndBitErr = (1u << 2), ///< Command End Bit Error. 1: End Bit Error Generated; 0:No Error + SdiocCmdIndexErr = (1u << 3), ///< Command Index Error. 1: Command Index Error Generatedr; 0:No Error + SdiocDataTimeoutErr = (1u << 4), ///< Data Timeout Error. 1: Timer out; 0:No Error + SdiocDataCrcErr = (1u << 5), ///< Data CRC Error. 1: Data CRC Error Generated; 0:No Error + SdiocDataEndBitErr = (1u << 6), ///< Data End Bit Error. 1: End Bit Error Generated; 0:No Error + SdiocAutoCmd12Err = (1u << 8), ///< Auto CMD12 Error. 1: Error; 0:No Error +} en_sdioc_err_int_sel_t, en_sdioc_err_int_flag_t; + +/** + ******************************************************************************* + ** \brief SDIOC auto CMD12 error status enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_atuo_cmd_err_status +{ + SdiocAutoCmd12NotExecuted = (1u << 0), ///< Auto CMD12 Not Executed. 1: Not executed; 0:Executed + SdiocAutoCmd12Timeout = (1u << 1), ///< Auto CMD12 Timeout Error. 1: Time out; 0:No error + SdiocAutoCmd12CrcErr = (1u << 2), ///< Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + SdiocAutoCmd12EndBitErr = (1u << 3), ///< Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + SdiocAutoCmd12IndexErr = (1u << 4), ///< Auto CMD12 Index Error. 1: Error; 0: No error + SdiocCmdNotIssuedErr = (1u << 7), ///< Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error +} en_sdioc_atuo_cmd_err_sel_t, en_sdioc_atuo_cmd_err_status_t; + +/** + ******************************************************************************* + ** \brief SDIOC speed mode enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_speed_mode +{ + SdiocNormalSpeedMode = 0u, ///< Normal speed mode + SdiocHighSpeedMode = 1u, ///< High speed mode +} en_sdioc_speed_mode_t; + +/** + ******************************************************************************* + ** \brief SDIOC response register enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_response_reg +{ + SdiocRegResp01 = 0x00u, ///< Response 0/1 Register + SdiocRegResp23 = 0x04u, ///< Response 2/3 Register + SdiocRegResp45 = 0x08u, ///< Response 4/5 Register + SdiocRegResp67 = 0x0Cu, ///< Response 5/6 Register +} en_sdioc_response_reg_t; + +/** + ****************************************************************************** + ** \brief SDIOC output clock frequency enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_clk_freq +{ + SdiocClk400K = 400000u, ///< SDIOC clock: 40KHz + SdiocClk20M = 20000000u, ///< SDIOC clock: 20MHz + SdiocClk25M = 25000000u, ///< SDIOC clock: 25MHz + SdiocClk40M = 40000000u, ///< SDIOC clock: 40MHz + SdiocClk50M = 50000000u, ///< SDIOC clock: 50MHz +} en_sdioc_clk_freq_t; + +/** + ****************************************************************************** + ** \brief SDIOC detect the source of card enumeration + ** + ******************************************************************************/ +typedef enum en_sdioc_detect_signal +{ + SdiocSdcdPinLevel = 0u, ///< SDCD# is selected (for normal use) + SdiocCardDetectTestLevel = 1u, ///< The Card Detect Test Level is selected(for test purpose) +} en_sdioc_detect_signal_t; + +/** + ******************************************************************************* + ** \brief SDIOC Command configure structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_cmd_cfg +{ + uint8_t u8CmdIndex; ///< Command index + + uint32_t u32Argument; ///< The argument of command + + en_sdioc_cmd_type_t enCmdType; ///< Command type + + en_sdioc_response_index_t enRspIndex; ///< Response index, refer @ref en_sdioc_response_index_t for details + + en_functional_state_t enDataPresentEnable; ///< Enable: Data is present and shall be transferred using the DAT line, Disable: Commands using only CMD line +} stc_sdioc_cmd_cfg_t; + +/** + ******************************************************************************* + ** \brief SDIOC Data configure structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_data_cfg +{ + uint16_t u16BlkSize; ///< Block size + + uint16_t u16BlkCnt; ///< Block count + + en_functional_state_t enAutoCmd12Enable; ///< Enable: Auto CMD12 enable, Disable: Auto CMD12 disable + + en_sdioc_transfer_dir_t enTransferDir; ///< Specifies the data transfer direction of the SDIOC controller. + ///< This parameter can be a value of @ref en_sdioc_transfer_dir_t. + + en_sdioc_data_timeout_t enDataTimeOut; ///< Specifies the data timeout period in card bus clock periods. + ///< This parameter can be a value of @ref en_sdioc_data_timeout_t. + + en_sdioc_transfer_mode_t enTransferMode; ///< Specifies the data transfer mode of the SDIOC controller. + ///< This parameter can be a value of @ref en_sdioc_transfer_mode_t. +} stc_sdioc_data_cfg_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt enable structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_normal_irq_en +{ + union + { + uint16_t u16NormalIntsgEn; ///< SDIOC normal interrupt enable + stc_sdioc_errintsgen_field_t stcNormalIntsgEn; ///< SDIOC normal interrupt enable bit-field structure + }; +} stc_sdioc_normal_irq_en_t; + +/** + ******************************************************************************* + ** \brief SDIOC normal interrupt enable structure + ** + ******************************************************************************/ +typedef struct stc_sdioc_error_irq_en +{ + union + { + uint16_t u16ErrorIntsgEn; ///< SDIOC error interrupt enable + stc_sdioc_errintsgen_field_t stcErrorIntsgEn; ///< SDIOC error interrupt enable bit-field structure + }; +} stc_sdioc_error_irq_en_t; + +/** + ******************************************************************************* + ** \brief SDIOC error status callback functions + ** + ******************************************************************************/ +typedef struct stc_sdioc_normal_irq_cb +{ + func_ptr_t pfnCommandCompleteIrqCb; ///< Pointer to command complete callback function + + func_ptr_t pfnTransferCompleteIrqCb; ///< Pointer to transfer complete callback function + + func_ptr_t pfnBlockGapIrqCb; ///< Pointer to Block gap callback function + + func_ptr_t pfnBufferWriteReadyIrqCb; ///< Pointer to buffer write ready callback function + + func_ptr_t pfnBufferReadReadyIrqCb; ///< Pointer to buffer read ready callback function + + func_ptr_t pfnCardInsertIrqCb; ///< Pointer to card insertion callback function + + func_ptr_t pfnCardRemovalIrqCb; ///< Pointer to card removal callback function + + func_ptr_t pfnCardIrqCb; ///< Pointer to card interrupt callback function +} stc_sdioc_normal_irq_cb_t; + +/** + ******************************************************************************* + ** \brief SDIOC error status callback functions + ** + ******************************************************************************/ +typedef struct stc_sdioc_error_irq_cb +{ + func_ptr_t pfnCmdTimeoutErrIrqCb; ///< Pointer to command timeout error interrupt callback function + + func_ptr_t pfnCmdCrcErrIrqCb; ///< Pointer to command CRC error interrupt callback function + + func_ptr_t pfnCmdEndBitErrIrqCb; ///< Pointer to command end bit error interrupt callback function + + func_ptr_t pfnCmdIndexErrIrqCb; ///< Pointer to command index error interrupt callback function + + func_ptr_t pfnDataTimeoutErrIrqCb; ///< Pointer to data timeout error interrupt callback function + + func_ptr_t pfnDataCrcErrIrqCb; ///< Pointer to data CRC error interrupt callback function + + func_ptr_t pfnDataEndBitErrIrqCb; ///< Pointer to data end bit error interrupt callback function + + func_ptr_t pfnAutoCmdErrIrqCb; ///< Pointer to command error interrupt callback function +} stc_sdioc_error_irq_cb_t; + +/** + ******************************************************************************* + ** \brief SDIOC initialization configuration + ** + ******************************************************************************/ +typedef struct stc_sdioc_init +{ + stc_sdioc_normal_irq_en_t *pstcNormalIrqEn; ///< Pointer to normal interrupt enable structure + + stc_sdioc_normal_irq_cb_t *pstcNormalIrqCb; ///< Pointer to normal interrupt callback function structure + + stc_sdioc_error_irq_en_t *pstcErrorIrqEn; ///< Pointer to error interrupt enable structure + + stc_sdioc_error_irq_cb_t *pstcErrorIrqCb; ///< Pointer to error interrupt callback structure +} stc_sdioc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_init_t *pstcInitCfg); +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx); +void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode); +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_cmd_cfg_t *pstcCmdCfg); +uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_response_reg_t enRespReg); +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len); +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len); +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_data_cfg_t *pstcDataCfg); +en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_clk_div_t enClkDiv); +en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq); +en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_bus_width_t enBusWidth); +en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_speed_mode_t enSpeedMode); +en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_data_timeout_t enTimeout); +en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_detect_signal_t enDetectSignal); +en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd); +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_sw_reset_t enSwResetType); +en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_host_status_t enHostStatus); +en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd); +en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd); +en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt); +en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt); +en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd); +en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd); +en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt); +en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt); +en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt); +en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_status_t enAutoCmdErr); +en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr); + +//@} // SdiocGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SDIOC_ENABLE */ + +#endif /* __HC32F460_SDIOC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_spi.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_spi.h new file mode 100644 index 0000000000..5afbf57b7e --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_spi.h @@ -0,0 +1,426 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_spi.h + ** + ** A detailed description is available at + ** @link SpiGroup Serial Peripheral Interface description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of Spi. + ** + ******************************************************************************/ +#ifndef __HC32F460_SPI_H__ +#define __HC32F460_SPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SPI_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SpiGroup Serial Peripheral Interface(SPI) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SPI parity enumeration + ******************************************************************************/ +typedef enum en_spi_parity +{ + SpiParityEven = 0u, ///< Select even parity send and receive + SpiParityOdd = 1u, ///< Select odd parity send and receive +} en_spi_parity_t; + +/** + ******************************************************************************* + ** \brief SPI master/slave mode enumeration + ******************************************************************************/ +typedef enum en_spi_master_slave_mode +{ + SpiModeSlave = 0u, ///< Spi slave mode + SpiModeMaster = 1u, ///< Spi master mode +} en_spi_master_slave_mode_t; + +/** + ******************************************************************************* + ** \brief SPI transmission mode enumeration + ******************************************************************************/ +typedef enum en_spi_trans_mode +{ + SpiTransFullDuplex = 0u, ///< Full duplex sync serial communication + SpiTransOnlySend = 1u, ///< Only send serial communication +} en_spi_trans_mode_t; + +/** + ******************************************************************************* + ** \brief SPI work mode enumeration + ******************************************************************************/ +typedef enum en_spi_work_mode +{ + SpiWorkMode4Line = 0u, ///< 4 lines spi work mode + SpiWorkMode3Line = 1u, ///< 3 lines spi work mode(clock sync running) +} en_spi_work_mode_t; + +/** + ******************************************************************************* + ** \brief SPI SS interval time enumeration + ******************************************************************************/ +typedef enum en_spi_ss_interval_time +{ + SpiSsIntervalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1 + SpiSsIntervalSck2PlusPck2 = 1u, ///< Spi SS interval time 2 SCK plus 2 PCLK1 + SpiSsIntervalSck3PlusPck2 = 2u, ///< Spi SS interval time 3 SCK plus 2 PCLK1 + SpiSsIntervalSck4PlusPck2 = 3u, ///< Spi SS interval time 4 SCK plus 2 PCLK1 + SpiSsIntervalSck5PlusPck2 = 4u, ///< Spi SS interval time 5 SCK plus 2 PCLK1 + SpiSsIntervalSck6PlusPck2 = 5u, ///< Spi SS interval time 6 SCK plus 2 PCLK1 + SpiSsIntervalSck7PlusPck2 = 6u, ///< Spi SS interval time 7 SCK plus 2 PCLK1 + SpiSsIntervalSck8PlusPck2 = 7u, ///< Spi SS interval time 8 SCK plus 2 PCLK1 +} en_spi_ss_interval_time_t; + +/** + ******************************************************************************* + ** \brief SPI SS setup delay SCK enumeration + ******************************************************************************/ +typedef enum en_spi_ss_setup_delay +{ + SpiSsSetupDelaySck1 = 0u, ///< Spi SS setup delay 1 SCK + SpiSsSetupDelaySck2 = 1u, ///< Spi SS setup delay 2 SCK + SpiSsSetupDelaySck3 = 2u, ///< Spi SS setup delay 3 SCK + SpiSsSetupDelaySck4 = 3u, ///< Spi SS setup delay 4 SCK + SpiSsSetupDelaySck5 = 4u, ///< Spi SS setup delay 5 SCK + SpiSsSetupDelaySck6 = 5u, ///< Spi SS setup delay 6 SCK + SpiSsSetupDelaySck7 = 6u, ///< Spi SS setup delay 7 SCK + SpiSsSetupDelaySck8 = 7u, ///< Spi SS setup delay 8 SCK +} en_spi_ss_setup_delay_t; + +/** + ******************************************************************************* + ** \brief SPI SS hold delay SCK enumeration + ******************************************************************************/ +typedef enum en_spi_ss_hold_delay +{ + SpiSsHoldDelaySck1 = 0u, ///< Spi SS hold delay 1 SCK + SpiSsHoldDelaySck2 = 1u, ///< Spi SS hold delay 2 SCK + SpiSsHoldDelaySck3 = 2u, ///< Spi SS hold delay 3 SCK + SpiSsHoldDelaySck4 = 3u, ///< Spi SS hold delay 4 SCK + SpiSsHoldDelaySck5 = 4u, ///< Spi SS hold delay 5 SCK + SpiSsHoldDelaySck6 = 5u, ///< Spi SS hold delay 6 SCK + SpiSsHoldDelaySck7 = 6u, ///< Spi SS hold delay 7 SCK + SpiSsHoldDelaySck8 = 7u, ///< Spi SS hold delay 8 SCK +} en_spi_ss_hold_delay_t; + +/** + ******************************************************************************* + ** \brief SPI slave select polarity enumeration + ******************************************************************************/ +typedef enum en_spi_ss_polarity +{ + SpiSsLowValid = 0u, ///< SS0~3 signal low level valid + SpiSsHighValid = 1u, ///< SS0~3 signal high level valid +} en_spi_ss_polarity_t; + +/** + ******************************************************************************* + ** \brief SPI data register read object enumeration + ******************************************************************************/ +typedef enum en_spi_read_object +{ + SpiReadReceiverBuffer = 0u, ///< Read receive buffer + SpiReadSendBuffer = 1u, ///< Read send buffer(must be read when TDEF=1) +} en_spi_read_object_t; + +/** + ******************************************************************************* + ** \brief SPI frame number enumeration + ******************************************************************************/ +typedef enum en_spi_frame_number +{ + SpiFrameNumber1 = 0u, ///< 1 frame data + SpiFrameNumber2 = 1u, ///< 2 frame data + SpiFrameNumber3 = 2u, ///< 3 frame data + SpiFrameNumber4 = 3u, ///< 4 frame data +} en_spi_frame_number_t; + +/** + ******************************************************************************* + ** \brief SPI SS setup delay SCK option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_setup_delay_option +{ + SpiSsSetupDelayTypicalSck1 = 0u, ///< SS setup delay 1 SCK + SpiSsSetupDelayCustomValue = 1u, ///< SS setup delay SCKDL register set value +} en_spi_ss_setup_delay_option_t; + +/** + ******************************************************************************* + ** \brief SPI SS hold delay SCK option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_hold_delay_option +{ + SpiSsHoldDelayTypicalSck1 = 0u, ///< SS hold delay 1 SCK + SpiSsHoldDelayCustomValue = 1u, ///< SS hold delay SSDL register set value +} en_spi_ss_hold_delay_option_t; + +/** + ******************************************************************************* + ** \brief SPI SS interval time option enumeration + ******************************************************************************/ +typedef enum en_spi_ss_interval_time_option +{ + SpiSsIntervalTypicalSck1PlusPck2 = 0u, ///< Spi SS interval time 1 SCK plus 2 PCLK1 + SpiSsIntervalCustomValue = 1u, ///< Spi SS interval time NXTDL register set value +} en_spi_ss_interval_time_option_t; + +/** + ******************************************************************************* + ** \brief SPI first bit position enumeration + ******************************************************************************/ +typedef enum en_spi_first_bit_position +{ + SpiFirstBitPositionMSB = 0u, ///< Spi first bit to MSB + SpiFirstBitPositionLSB = 1u, ///< Spi first bit to LSB +} en_spi_first_bit_position_t; + +/** + ******************************************************************************* + ** \brief SPI data length enumeration + ******************************************************************************/ +typedef enum en_spi_data_length +{ + SpiDataLengthBit4 = 0u, ///< 4 bits + SpiDataLengthBit5 = 1u, ///< 5 bits + SpiDataLengthBit6 = 2u, ///< 6 bits + SpiDataLengthBit7 = 3u, ///< 7 bits + SpiDataLengthBit8 = 4u, ///< 8 bits + SpiDataLengthBit9 = 5u, ///< 9 bits + SpiDataLengthBit10 = 6u, ///< 10 bits + SpiDataLengthBit11 = 7u, ///< 11 bits + SpiDataLengthBit12 = 8u, ///< 12 bits + SpiDataLengthBit13 = 9u, ///< 13 bits + SpiDataLengthBit14 = 10u, ///< 14 bits + SpiDataLengthBit15 = 11u, ///< 15 bits + SpiDataLengthBit16 = 12u, ///< 16 bits + SpiDataLengthBit20 = 13u, ///< 20 bits + SpiDataLengthBit24 = 14u, ///< 24 bits + SpiDataLengthBit32 = 15u, ///< 32 bits +} en_spi_data_length_t; + +/** + ******************************************************************************* + ** \brief SPI SS valid channel select enumeration + ******************************************************************************/ +typedef enum en_spi_ss_valid_channel +{ + SpiSsValidChannel0 = 0u, ///< Select SS0 valid + SpiSsValidChannel1 = 1u, ///< Select SS1 valid + SpiSsValidChannel2 = 2u, ///< Select SS2 valid + SpiSsValidChannel3 = 3u, ///< Select SS3 valid +} en_spi_ss_valid_channel_t; + +/** + ******************************************************************************* + ** \brief SPI clock division enumeration + ******************************************************************************/ +typedef enum en_spi_clk_div +{ + SpiClkDiv2 = 0u, ///< Spi pclk1 division 2 + SpiClkDiv4 = 1u, ///< Spi pclk1 division 4 + SpiClkDiv8 = 2u, ///< Spi pclk1 division 8 + SpiClkDiv16 = 3u, ///< Spi pclk1 division 16 + SpiClkDiv32 = 4u, ///< Spi pclk1 division 32 + SpiClkDiv64 = 5u, ///< Spi pclk1 division 64 + SpiClkDiv128 = 6u, ///< Spi pclk1 division 128 + SpiClkDiv256 = 7u, ///< Spi pclk1 division 256 +} en_spi_clk_div_t; + +/** + ******************************************************************************* + ** \brief SPI SCK polarity enumeration + ******************************************************************************/ +typedef enum en_spi_sck_polarity +{ + SpiSckIdleLevelLow = 0u, ///< SCK is low level when SCK idle + SpiSckIdleLevelHigh = 1u, ///< SCK is high level when SCK idle +} en_spi_sck_polarity_t; + +/** + ******************************************************************************* + ** \brief SPI SCK phase enumeration + ******************************************************************************/ +typedef enum en_spi_sck_phase +{ + SpiSckOddSampleEvenChange = 0u, ///< SCK Odd edge data sample,even edge data change + SpiSckOddChangeEvenSample = 1u, ///< SCK Odd edge data change,even edge data sample +} en_spi_sck_phase_t; + +/** + ******************************************************************************* + ** \brief SPI interrupt request type enumeration + ******************************************************************************/ +typedef enum en_spi_irq_type +{ + SpiIrqIdle = 0u, ///< Spi idle interrupt request + SpiIrqReceive = 1u, ///< Spi receive interrupt request + SpiIrqSend = 2u, ///< Spi send interrupt request + SpiIrqError = 3u, ///< Spi error interrupt request +} en_spi_irq_type_t; + +/** + ******************************************************************************* + ** \brief SPI flag type enumeration + ******************************************************************************/ +typedef enum en_spi_flag_type +{ + SpiFlagReceiveBufferFull = 0u, ///< Receive buffer full flag + SpiFlagSendBufferEmpty = 1u, ///< Send buffer empty flag + SpiFlagUnderloadError = 2u, ///< Underload error flag + SpiFlagParityError = 3u, ///< Parity error flag + SpiFlagModeFaultError = 4u, ///< Mode fault error flag + SpiFlagSpiIdle = 5u, ///< SPI idle flag + SpiFlagOverloadError = 6u, ///< Overload error flag +} en_spi_flag_type_t; + +/** + ******************************************************************************* + ** \brief SPI SS channel enumeration + ******************************************************************************/ +typedef enum en_spi_ss_channel +{ + SpiSsChannel0 = 0u, ///< SS0 channel + SpiSsChannel1 = 1u, ///< SS1 channel + SpiSsChannel2 = 2u, ///< SS2 channel + SpiSsChannel3 = 3u, ///< SS3 channel +} en_spi_ss_channel_t; + +/** + ******************************************************************************* + ** \brief SPI bus delay structure definition + ** + ** \note Slave mode stc_spi_delay_config_t is invalid + ******************************************************************************/ +typedef struct stc_spi_delay_config +{ + en_spi_ss_setup_delay_option_t enSsSetupDelayOption; ///< SS setup delay time option + en_spi_ss_setup_delay_t enSsSetupDelayTime; ///< SS setup delay time(the value valid when enSsSetupDelayOption is custom) + en_spi_ss_hold_delay_option_t enSsHoldDelayOption; ///< SS hold delay time option + en_spi_ss_hold_delay_t enSsHoldDelayTime; ///< SS hold delay time(the value valid when enSsHoldDelayOption is custom) + en_spi_ss_interval_time_option_t enSsIntervalTimeOption; ///< SS interval time option + en_spi_ss_interval_time_t enSsIntervalTime; ///< SS interval time(the value valid when enSsIntervalTimeOption is custom) +} stc_spi_delay_config_t; + +/** + ******************************************************************************* + ** \brief SPI SS config structure definition + ** + ** \note 3 lines mode stc_spi_ss_config_t is invalid + ******************************************************************************/ +typedef struct stc_spi_ss_config +{ + en_spi_ss_valid_channel_t enSsValidBit; ///< SS valid channel select + en_spi_ss_polarity_t enSs0Polarity; ///< SS0 signal polarity + en_spi_ss_polarity_t enSs1Polarity; ///< SS1 signal polarity + en_spi_ss_polarity_t enSs2Polarity; ///< SS2 signal polarity + en_spi_ss_polarity_t enSs3Polarity; ///< SS3 signal polarity +} stc_spi_ss_config_t; + +/** + ******************************************************************************* + ** \brief SPI init structure definition + ******************************************************************************/ +typedef struct stc_spi_init_t +{ + stc_spi_delay_config_t stcDelayConfig; ///< SPI delay structure(Slave mode is invalid) + stc_spi_ss_config_t stcSsConfig; ///< SS polarity and channel structure(3 lines mode invalid) + en_spi_read_object_t enReadBufferObject; ///< Data register read object select(must be read when TDEF=1) + en_spi_sck_polarity_t enSckPolarity; ///< Sck polarity + en_spi_sck_phase_t enSckPhase; ///< Sck phase(This value must be SpiSckOddChangeEvenSample in 3-line mode) + en_spi_clk_div_t enClkDiv; ///< SPI clock division + en_spi_data_length_t enDataLength; ///< Data length + en_spi_first_bit_position_t enFirstBitPosition; ///< Data first bit position + en_spi_frame_number_t enFrameNumber; ///< Data frame number + en_spi_work_mode_t enWorkMode; ///< Spi work mode + en_spi_trans_mode_t enTransMode; ///< transmission mode + en_spi_master_slave_mode_t enMasterSlaveMode; ///< Spi master/slave mode + en_functional_state_t enCommAutoSuspendEn; ///< Enable/disable Communication auto suspend + en_functional_state_t enModeFaultErrorDetectEn; ///< Enable/disable Mode fault error detect + en_functional_state_t enParitySelfDetectEn; ///< Enable/disable Parity self detect + en_functional_state_t enParityEn; ///< Enable/disable Parity(if enable parity and SPI_CR1.TXMDS=1, receive data don't parity) + en_spi_parity_t enParity; ///< Parity mode select +} stc_spi_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx); +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg); +en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); +en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); +en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta); + +/* Send and receive data functions */ +en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data); +en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data); +en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data); +uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx); +uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx); +uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx); + +/* Communication configure functions */ +en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel, + en_spi_ss_polarity_t enPolarity); +en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel); +en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject); +en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum); +en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength); +en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition); +en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv); + +/* Interrupt and flags functions */ +en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq, + en_functional_state_t enNewSta); +en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag); +en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag); + +//@} // SpiGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SPI_ENABLE */ + +#endif /* __HC32F460_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sram.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sram.h new file mode 100644 index 0000000000..cc7147d0cf --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_sram.h @@ -0,0 +1,190 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sram.h + ** + ** A detailed description is available at + ** @link SramGroup Internal SRAM description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of SRAM. + ** + ******************************************************************************/ + +#ifndef __HC32F460_SRAM_H__ +#define __HC32F460_SRAM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SRAM_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + * \defgroup SramGroup Internal SRAM + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +///< SRAM wait cycle register, parity/ECC check register protect code definition +#define SRAM_PROTECT_CODE (0x0000003Bu) + +/******************************************************************************* + Start addr. End addr. Size Function + SRAM1 0x20000000 0x2000FFFF 64KB Even Parity Check + SRAM2 0x20010000 0x2001FFFF 64KB Even Parity Check + SRAM3 0x20020000 0x20026FFF 28KB ECC Check + SRAM_Ret 0x200F0000 0x200F0FFF 4KB Even Parity Check + SRAM_HS 0x1FFF8000 0x1FFFFFFF 32KB Even Parity Check + ******************************************************************************/ +///< SRAM1 base address definition +#define SRAM1_BASE_ADDR (*((volatile unsigned int*)(0x20000000UL))) + +///< SRAM2 base address definition +#define SRAM2_BASE_ADDR (*((volatile unsigned int*)(0x20010000UL))) + +///< SRAM3 base address definition +#define SRAM3_BASE_ADDR (*((volatile unsigned int*)(0x20020000UL))) + +///< Retention SRAM base address definition +#define SRAMRET_BASE_ADDR (*((volatile unsigned int*)(0x200F0000UL))) + +///< High speed SRAM base address definition +#define SRAMHS_BASE_ADDR (*((volatile unsigned int*)(0x1FFF8000UL))) + + +typedef enum en_sram_index +{ + Sram12Idx = 1u << 0, + Sram3Idx = 1u << 1, + SramHsIdx = 1u << 2, + SramRetIdx = 1u << 3, +}en_sram_index_t; +/** + ******************************************************************************* + ** \brief Enumeration to the write/read cycles of SRAM + ** + ** \note + ******************************************************************************/ +typedef enum en_sram_rw_cycle +{ + SramCycle1 = 0u, + SramCycle2 = 1u, + SramCycle3 = 2u, + SramCycle4 = 3u, + SramCycle5 = 4u, + SramCycle6 = 5u, + SramCycle7 = 6u, + SramCycle8 = 7u, +}en_sram_rw_cycle_t; + +/** + ******************************************************************************* + ** \brief Enumeration to ECC check mode + ** + ** \note + ******************************************************************************/ +typedef enum en_ecc_mode +{ + EccMode0 = 0u, ///< disable ECC check function + EccMode1 = 1u, ///< no 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected + EccMode2 = 2u, ///< generate 1 bit ECC flag, but no interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected + EccMode3 = 3u, ///< generate 1 bit ECC flag, interrupt/reset if 1 bit-ECC is detected + ///< generate 2 bit ECC flag, interrupt/reset if 2 bit-ECC is detected +}en_ecc_mode_t; + +/** + ******************************************************************************* + ** \brief Enumeration to operation after ECC/Parity error + ** + ** \note + ******************************************************************************/ +typedef enum en_ecc_py_err_op +{ + SramNmi = 0u, ///< Generate NMI after ECC/Parity error detected + SramReset = 1u, ///< Generate Reset after ECC/Parity error detected +}en_ecc_py_err_op_t; + +/** + ******************************************************************************* + ** \brief Enumeration to the ECC/Parity error status of each SRAM + ** + ** \note + ******************************************************************************/ +typedef enum en_sram_err_status +{ + Sram3EccErr1 = 1u << 0, ///< SRAM3 1 bit ECC error + Sram3EccErr2 = 1u << 1, ///< SRAM3 2 bit ECC error + Sram12ParityErr = 1u << 2, ///< SRAM1/2 parity error + SramHSParityErr = 1u << 3, ///< High speed SRAM parity error + SramRetParityErr = 1u << 4, ///< Retention SRAM parity error +}en_sram_err_status_t; + +/** + ******************************************************************************* + ** \brief SRAM configuration + ** + ** \note The SRAM configuration structure + ******************************************************************************/ +typedef struct stc_sram_config +{ + uint8_t u8SramIdx; ///< SRAM index, ref @ en_sram_index_t for details + en_sram_rw_cycle_t enSramRC; ///< SRAM read wait cycle setting + en_sram_rw_cycle_t enSramWC; ///< SRAM write wait cycle setting + en_ecc_mode_t enSramEccMode; ///< SRAM ECC mode setting + en_ecc_py_err_op_t enSramEccOp; ///< SRAM3 ECC error handling setting + en_ecc_py_err_op_t enSramPyOp; ///< SRAM1/2/HS/Ret Parity error handling setting + +}stc_sram_config_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig); +extern en_result_t SRAM_DeInit(void); +extern en_result_t SRAM_WT_Disable(void); +extern en_result_t SRAM_WT_Enable(void); +extern en_result_t SRAM_CK_Disable(void); +extern en_result_t SRAM_CK_Enable(void); +extern en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus); +extern en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus); + +//@} // SramGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SRAM_ENABLE */ + +#endif /* __HC32F460_SRAM_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_swdt.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_swdt.h new file mode 100644 index 0000000000..63d94c4d1e --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_swdt.h @@ -0,0 +1,86 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_swdt.h + ** + ** A detailed description is available at + ** @link SwdtGroup Special Watchdog Counter description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of SWDT. + ** + ******************************************************************************/ +#ifndef __HC32F460_SWDT_H__ +#define __HC32F460_SWDT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_SWDT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup SwdtGroup Special Watchdog Counter(SWDT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT flag type enumeration + ******************************************************************************/ +typedef enum en_swdt_flag_type +{ + SwdtFlagCountUnderflow = 0u, ///< Count underflow flag + SwdtFlagRefreshError = 1u, ///< Refresh error flag +} en_swdt_flag_type_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t SWDT_RefreshCounter(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags functions */ +en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag); +en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag); + +//@} // SwdtGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_SWDT_ENABLE */ + +#endif /* __HC32F460_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer0.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer0.h new file mode 100644 index 0000000000..46b570fe48 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timer0.h @@ -0,0 +1,209 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer0.h + ** + ** A detailed description is available at + ** @link Timer0Group description @endlink + ** + ** - 2018-10-11 CDT First version for Device Driver Library of TIMER0. + ** + ******************************************************************************/ + +#ifndef __HC32F460_TIMER0_H__ +#define __HC32F460_TIMER0_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TIMER0_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup Timer0Group Timer0 + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Timer0 channel enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_channel +{ + Tim0_ChannelA = 0x00u, + Tim0_ChannelB = 0x01u +}en_tim0_channel_t; + +/** + ******************************************************************************* + ** \brief Timer0 Async Mode clock enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_async_clock_src +{ + Tim0_LRC = 0x00u, + Tim0_XTAL32 = 0x01u +}en_tim0_async_clock_src_t; + +/** + ******************************************************************************* + ** \brief Timer0 Sync Mode clock enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_sync_clock_src +{ + Tim0_Pclk1 = 0x00u, + Tim0_InsideHardTrig = 0x01u +}en_tim0_sync_clock_src_t; + +/** + ******************************************************************************* + ** \brief Timer0 counter mode enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_counter_mode +{ + Tim0_Sync = 0x00u, + Tim0_Async = 0x01u +}en_tim0_counter_mode_t; + +/** + ******************************************************************************* + ** \brief Timer0 trigger event mode enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_function +{ + Tim0_OutputCapare = 0x00u, + Tim0_InputCaptrue = 0x01u +}en_tim0_function_t; + +/** + ******************************************************************************* + ** \brief Timer0 clock division enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_clock_div +{ + Tim0_ClkDiv0 = 0u, + Tim0_ClkDiv2, + Tim0_ClkDiv4, + Tim0_ClkDiv8, + Tim0_ClkDiv16, + Tim0_ClkDiv32, + Tim0_ClkDiv64, + Tim0_ClkDiv128, + Tim0_ClkDiv256, + Tim0_ClkDiv512, + Tim0_ClkDiv1024 +}en_tim0_clock_div_t; + +/** + ******************************************************************************* + ** \brief Timer0 common trigger source select enumeration + ** + ******************************************************************************/ +typedef enum en_tim0_com_trigger +{ + Tim0ComTrigger_1 = 1u, ///< Select common trigger 1. + Tim0ComTrigger_2 = 2u, ///< Select common trigger 2. + Tim0ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_tim0_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Timer0 trigger function init structrue definition + ** + ******************************************************************************/ +typedef struct stc_tim0_trigger_init +{ + en_tim0_function_t Tim0_OCMode; ///GCMAR / GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR / GCMDR-->GCMBR + ** Double buffer stransfer: Compare Ouput: GCMER-->GCMCR-->GCMAR / GCMFR-->GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR-->GCMER /GCMFR-->GCMDR-->GCMBR + ** For Period register: + ** Single buffer stransfer: PERBR-->PERAR + ** Double buffer stransfer: PERCR-->PERBR-->PERAR + ******************************************************************************/ +typedef enum en_timer6_buf_gcmp_prd +{ + Timer6GcmpPrdSingleBuf = 0u, ///< Single buffer stransfer + Timer6GcmpPrdDoubleBuf = 1u, ///< Double buffer stransfer +}en_timer6_buf_gcmp_prd_t; + +/** + ****************************************************************************** + ** \brief Timer6 buffer - Special compare register transfer function selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_buf_spcl_cmp +{ + Timer6SpclSingleBuf = 0u, ///< Single buffer stransfer: Compare Ouput: SCMCR-->SCMAR / SCMDR-->SCMBR + Timer6SpclDoubleBuf = 1u, ///< Double buffer stransfer: Compare Ouput: SCMER-->SCMCR-->SCMAR / SCMFR-->SCMDR-->SCMBR +}en_timer6_buf_spcl_cmp_t; + +/** + ****************************************************************************** + ** \brief Timer6 buffer - Special compare register transfer opportunity selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_buf_spcl_opt +{ + Timer6SplcOptNone = 0u, ///< No transfer + Timer6SplcOptOverFlow = 1u, ///< Transfer when over flow (About sawtooth mode,accord to the count direction) + Timer6SplcOptUnderFlow = 2u, ///< Transfer when under flow (About sawtooth mode,accord to the count direction) + Timer6SplcOptBoth = 3u, ///< Transfer when over flow or under flow (About sawtooth mode,accord to the count direction) +}en_timer6_buf_spcl_opt_t; + +/** + ****************************************************************************** + ** \brief ADT dead timer control - PWMx dead timer separate set + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_dconr_sepa +{ + Timer6PWMxDtSeparate = 0u, ///< The dead timer of up count and down count separate set by DTUAR and DTDAR + Timer6PWMxDtEqual = 1u, ///< the values of DTUAR and DTDAR are equal automatically +}en_timer6_dconr_sepa_t; + +/** + ****************************************************************************** + ** \brief ADT filter control- TRIx/PWMx port filter sample clock selection + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_fconr_fltclk +{ + Timer6FltClkPclk0Div1 = 0u, ///< PCLK0 + Timer6FltClkPclk0Div4 = 1u, ///< PCLK0/4 + Timer6FltClkPclk0Div16 = 2u, ///< PCLK0/16 + Timer6FltClkPclk0Div64 = 3u, ///< PCLK0/64 +}en_timer6_fconr_fltclk_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period repeat- TIMx valid period repeat function selection(trigger interrupt or AOS event) + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_vperr_pcnts +{ + Timer6PeriodCnts0 = 0u, ///< Valid period repeat function disable + Timer6PeriodCnts1 = 1u, ///< Enable every other one period + Timer6PeriodCnts2 = 2u, ///< Enable every other two periods + Timer6PeriodCnts3 = 3u, ///< Enable every other three periods + Timer6PeriodCnts4 = 4u, ///< Enable every other four periods + Timer6PeriodCnts5 = 5u, ///< Enable every other five periods + Timer6PeriodCnts6 = 6u, ///< Enable every other six periods + Timer6PeriodCnts7 = 7u, ///< Enable every other seven periods +}en_timer6_vperr_pcnts_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period repeat- Count condition select + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_vperr_pcnte +{ + Timer6PeriodCnteDisable = 0u, ///< Valid period repeat function disable + Timer6PeriodCnteMin = 1u, ///< Over flow and under flow point of Sawtooth wave mode, or under flow point of Triangular wave mode + Timer6PeriodCnteMax = 2u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow point of Triangular wave mode + Timer6PeriodCnteBoth = 3u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow and under flow point of Triangular wave mode +}en_timer6_vperr_pcnte_t; + +/** + ****************************************************************************** + ** \brief Timer6 Hardware(Start/Stop/Clear/Capture) event trigger select + ** + ** \note + ******************************************************************************/ + +typedef enum en_timer6_hw_trig +{ + Timer6HwTrigAos0 = 0u, ///< Hardware trigger event from AOS0(HTSSR0) + Timer6HwTrigAos1 = 1u, ///< Hardware trigger event from AOS1(HTSSR1) + Timer6HwTrigPWMARise = 4u, ///< Hardware trigger event from PWMA rising + Timer6HwTrigPWMAFall = 5u, ///< Hardware trigger event from PWMA falling + Timer6HwTrigPWMBRise = 6u, ///< Hardware trigger event from PWMA rising + Timer6HwTrigPWMBFall = 7u, ///< Hardware trigger event from PWMA falling + Timer6HwTrigTimTriARise = 8u, ///< Hardware trigger event from TRIGA rising + Timer6HwTrigTimTriAFall = 9u, ///< Hardware trigger event from TRIGA falling + Timer6HwTrigTimTriBRise = 10u, ///< Hardware trigger event from TRIGB rising + Timer6HwTrigTimTriBFall = 11u, ///< Hardware trigger event from TRIGB falling + Timer6HwTrigEnd = 16u, +}en_timer6_hw_trig_t; + +/** + ****************************************************************************** + ** \brief Timer6 hardware (up count/down count) event trigger select + ** + ** \note + ******************************************************************************/ + +typedef enum en_timer6_hw_cnt +{ + Timer6HwCntPWMALowPWMBRise = 0u, ///< PWMB Rising trigger when PWMA is low level + Timer6HwCntPWMALowPWMBFall = 1u, ///< PWMB falling trigger when PWMA is low level + Timer6HwCntPWMAHighPWMBRise = 2u, ///< PWMB Rising trigger when PWMA is high level + Timer6HwCntPWMAHighPWMBFall = 3u, ///< PWMB falling trigger when PWMA is high level + Timer6HwCntPWMBLowPWMARise = 4u, ///< PWMA Rising trigger when PWMB is low level + Timer6HwCntPWMBLowPWMAFall = 5u, ///< PWMA falling trigger when PWMB is low level + Timer6HwCntPWMBHighPWMARise = 6u, ///< PWMA Rising trigger when PWMB is high level + Timer6HwCntPWMBHighPWMAFall = 7u, ///< PWMA falling trigger when PWMB is high level + Timer6HwCntTRIGARise = 8u, ///< TRIGA rising trigger + Timer6HwCntTRIGAFall = 9u, ///< TRIGA falling trigger + Timer6HwCntTRIGBRise = 10u, ///< TRIGB rising trigger + Timer6HwCntTRIGBFall = 11u, ///< TRIGB falling trigger + Timer6HwCntAos0 = 16u, ///< AOS0 trigger + Timer6HwCntAos1 = 17u, ///< AOS1 trigger + Timer6HwCntMax = 18u, +}en_timer6_hw_cnt_t; + + +/** + ****************************************************************************** + ** \brief Timer6 interrupt type + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_irq_type +{ + Timer6INTENA = 0u, ///< Interrupt of count equal to GCMA (or capture input A) + Timer6INTENB = 1u, ///< Interrupt of count equal to GCMB (or capture input B) + Timer6INTENC = 2u, ///< Interrupt of count equal to GCMC + Timer6INTEND = 3u, ///< Interrupt of count equal to GCMD + Timer6INTENE = 4u, ///< Interrupt of count equal to GCME + Timer6INTENF = 5u, ///< Interrupt of count equal to GCMF + Timer6INTENOVF = 6u, ///< Interrupt of over flow of sawtooth wave mode or peak point of triangular wave mode + Timer6INTENUDF = 7u, ///< Interrupt of under flow of sawtooth wave mode or valley point of triangular wave mode + Timer6INTENDTE = 8u, ///< Interrupt of dead timer error + Timer6INTENSAU = 16u, ///< Interrupt of count up equally compared with SCMA + Timer6INTENSAD = 17u, ///< Interrupt of count down equally compared with SCMA + Timer6INTENSBU = 18u, ///< Interrupt of count up equally compared with SCMB + Timer6INTENSBD = 19u, ///< Interrupt of count down equally compared with SCMB +}en_timer6_irq_type_t; + + +/** + ****************************************************************************** + ** \brief Timer6 status flag + ** + ** \note + ******************************************************************************/ +typedef enum en_timer6_status +{ + Timer6CMAF = 0u, ///< Status flag of count equal to GCMA (or capture input A) + Timer6CMBF = 1u, ///< Status flag of count equal to GCMB (or capture input B) + Timer6CMCF = 2u, ///< Status flag of count equal to GCMC + Timer6CMDF = 3u, ///< Status flag of count equal to GCMD + Timer6CMEF = 4u, ///< Status flag of count equal to GCME + Timer6CMFF = 5u, ///< Status flag of count equal to GCMF + Timer6OVFF = 6u, ///< Status flag of over flow of sawtooth wave mode or peak point of triangular wave mode + Timer6UDFF = 7u, ///< Status flag of under flow of sawtooth wave mode or valley point of triangular wave mode + Timer6DTEF = 8u, ///< Status flag of dead timer error + Timer6CMSAUF = 9u, ///< Status flag of count up equally compared with SCMA + Timer6CMSADF = 10u, ///< Status flag of count down equally compared with SCMA + Timer6CMSBUF = 11u, ///< Status flag of count up equally compared with SCMB + Timer6CMSBDF = 12u, ///< Status flag of count down equally compared with SCMB + Timer6VPERNUM = 21, ///< Number of valid period + Timer6DIRF = 31, ///< Count direction +}en_timer6_status_t; + +/** + ******************************************************************************* + ** \brief Timer6 common trigger source select enumeration + ** + ******************************************************************************/ +typedef enum en_timer6_com_trigger +{ + Timer6ComTrigger_1 = 1u, ///< Select common trigger 1. + Timer6ComTrigger_2 = 2u, ///< Select common trigger 2. + Timer6ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_timer6_com_trigger_t; + +/** + ****************************************************************************** + ** \brief Timer6 software synchronous config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_sw_sync +{ + bool bTimer61; ///< Timer6 unit1 + bool bTimer62; ///< Timer6 unit2 + bool bTimer63; ///< Timer6 unit3 +}stc_timer6_sw_sync_t; + +/** + ****************************************************************************** + ** \brief Timer6 base init structure definition + ** \note + ******************************************************************************/ +typedef struct stc_timer6_basecnt_cfg +{ + en_timer6_count_mode_t enCntMode; ///< Count mode + en_timer6_count_dir_t enCntDir; ///< Count direction + en_timer6_clk_div_t enCntClkDiv; ///< Count clock division select +}stc_timer6_basecnt_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Trig port config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_port_trig_cfg +{ + bool bFltEn; ///< trig source capture input filter enable + en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock +}stc_tiemr6_port_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 port output config +** \note + ******************************************************************************/ +typedef struct stc_timer6_port_output_cfg +{ + en_timer6_func_mode_t enPortMode; ///< Port mode + bool bOutEn; ///< Output enable / disable + en_timer6_pconr_cmpc_t enPerc; ///< Port state when counter match the period + en_timer6_pconr_cmpc_t enCmpc; ///< Port state when counter match GCMAR(GCMBR) + en_timer6_pconr_stastps_t enStaStp; ///< Post state selection when count start/stop + en_timer6_pconr_port_out_t enStaOut; ///< Port state when count start + en_timer6_pconr_port_out_t enStpOut; ///< port stop when count stop + en_timer6_pconr_disval_t enDisVal; ///< Port output state when brake +}stc_timer6_port_output_cfg_t; + + +/** + ****************************************************************************** + ** \brief Timer6 port input config +** \note + ******************************************************************************/ +typedef struct stc_timer6_port_input_cfg +{ + en_timer6_input_port_t enPortSel; ///< Port select + en_timer6_func_mode_t enPortMode; ///< Port mode + bool bFltEn; ///< trig source capture input filter enable + en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock +}stc_timer6_port_input_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 hardware dead time function config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_deadtime_cfg +{ + bool bEnDeadtime; ///< Enable hardware dead time function + bool bEnDtBufUp; ///< Enable buffer transfer for up count dead time register(DTUBR-->DTUAR) + bool bEnDtBufDwn; ///< Enable buffer transfer for down count dead time register(DTDBR-->DTDAR) + bool bEnDtEqualUpDwn; ///< Enable down count dead time register equal to up count DT register +}stc_timer6_deadtime_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 valid period config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_validper_cfg +{ + en_timer6_vperr_pcnts_t enValidCntNum; ///< Valid period selection + en_timer6_vperr_pcnte_t enValidCdtEn; ///< Count condition of valid period + bool bPeriodSCMA; ///< Sepcial signal A valid period selection enable + bool bPeriodSCMB; ///< Sepcial signal A valid period selection enable +}stc_timer6_validper_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 general compare register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_gcmp_buf_cfg +{ + bool bEnGcmpTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_gcmp_prd_t enGcmpBufTransType; ///< Sigle or double buffer transfer +}stc_timer6_gcmp_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 period register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_period_buf_cfg +{ + bool bEnPeriodTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_gcmp_prd_t enPeriodBufTransType; ///< Sigle or double buffer transfer +}stc_timer6_period_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Specila compare register buffer transfer config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_spcl_buf_cfg +{ + bool bEnSpclTransBuf; ///< Enable/Disable buffer transfer + en_timer6_buf_spcl_cmp_t enSpclBufTransType; ///< Sigle or double buffer transfer + en_timer6_buf_spcl_opt_t enSpclBufOptType; ///< Buffer transfer opportunity +}stc_timer6_spcl_buf_cfg_t; + +/** + ****************************************************************************** + ** \brief Timer6 Z phase input mask config + ** \note + ******************************************************************************/ +typedef struct stc_timer6_zmask_cfg +{ + en_timer6_gconr_zmsk_t enZMaskCycle; ///< Z phase input mask periods selection + bool bFltPosCntMaksEn; ///< As position count timer, position counter clear function enable(TRUE) or disable(FALSE) during the time of Z phase input mask + bool bFltRevCntMaksEn; ///< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) during the time of Z phase input mask +}stc_timer6_zmask_cfg_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* IRQ config */ +en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn); +/* Get status(flag) */ +uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus); + +/* Base functions */ +en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x); +en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg); +/* Timer6 unit start count*/ +en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit stop count*/ +en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit Set Count Value*/ +en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value); +/* Timer6 unit Get Count Value*/ +uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x); +/* Timer6 unit Clear Count Value*/ +en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x); + +/* Timer6 unit Set Period and buffer Value*/ +en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period); +/* Timer6 unit set general compare register value*/ +en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare); +/* Timer6 unit set specoal compare register value*/ +en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp); +/* Timer6 unit get general compare register value*/ +uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare); + +/* Timer6 unit set period buffer transfer function*/ +en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg); +/* Timer6 unit set general compare buffer transfer function*/ +en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg); +/* Timer6 unit set special compare buffer transfer function*/ +en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg); + +/* Timer6 unit Set valid period Value*/ +en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg); + +/* Config Input prot and filter function */ +en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg); +/* Config output prot function */ +en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg); + +/* Set dead time register value */ +en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue); +/* Config dead time function */ +en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg); + +/* Config Software Synchrony Stop */ +en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart); +/* Config Software Synchrony Start */ +en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop); +/* Config Software Synchrony Clear */ +en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear); +/* Get Software Synchrony Status */ +en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState); + +/* Config Hardware up count event */ +en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp); +/* Clear Hardware up count event */ +en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x); +/* Config Hardware down count event */ +en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn); +/* Clear Hardware down count event */ +en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x); + + +/* Config Hardware start event */ +en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart); +/* Clear Hardware start event */ +en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware start event */ +en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x); +/* Dsiable Hardware start event */ +en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x); + +/* Config Hardware stop event */ +en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop); +/* Clear Hardware stop event */ +en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware stop event */ +en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x); +/* Disable Hardware stop event */ +en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x); + +/* Config Hardware clear event */ +en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear); +/* Clear Hardware clear event */ +en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x); +/* Enable Hardware clear event */ +en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x); +/* Dsiable Hardware clear event */ +en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x); + + +/* Config Hardware capture event A */ +en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA); +/* Clear Hardware capture event A */ +en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x); +/* Config Hardware capture event B */ +en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB); +/* Clear Hardware capture event B */ +en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x); + + +/* Set trigger source 0 of hardware event */ +en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc); +/* Set trigger source 1 of hardware event */ +en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc); +/* Enable or disable Timer6 common trigger for Hardware trigger source 0 */ +void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState); +/* Enable or disable Timer6 common trigger for Hardware trigger source 1 */ +void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState); + +/* Z phase input mask config */ +en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg); + +//@} // Timer6Group + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TIMER6_ENABLE */ + +#endif /* __HC32F460_TIMER6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timera.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timera.h new file mode 100644 index 0000000000..5143819fe8 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_timera.h @@ -0,0 +1,493 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timera.h + ** + ** A detailed description is available at + ** @link TimeraGroup Timer A description @endlink + ** + ** - 2018-11-08 CDT First version for Device Driver Library of + ** Timera. + ** + ******************************************************************************/ +#ifndef __HC32F460_TIMERA_H__ +#define __HC32F460_TIMERA_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TIMERA_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup TimeraGroup Timer A(Timera) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Timera channel enumeration + ******************************************************************************/ +typedef enum en_timera_channel +{ + TimeraCh1 = 0u, ///< Timera channel 1 + TimeraCh2 = 1u, ///< Timera channel 2 + TimeraCh3 = 2u, ///< Timera channel 3 + TimeraCh4 = 3u, ///< Timera channel 4 + TimeraCh5 = 4u, ///< Timera channel 5 + TimeraCh6 = 5u, ///< Timera channel 6 + TimeraCh7 = 6u, ///< Timera channel 7 + TimeraCh8 = 7u, ///< Timera channel 8 +} en_timera_channel_t; + +/** + ******************************************************************************* + ** \brief Clock division enumeration + ******************************************************************************/ +typedef enum en_timera_clk_div +{ + TimeraPclkDiv1 = 0u, ///< Count clock: pclk + TimeraPclkDiv2 = 1u, ///< Count clock: pclk/2 + TimeraPclkDiv4 = 2u, ///< Count clock: pclk/4 + TimeraPclkDiv8 = 3u, ///< Count clock: pclk/8 + TimeraPclkDiv16 = 4u, ///< Count clock: pclk/16 + TimeraPclkDiv32 = 5u, ///< Count clock: pclk/32 + TimeraPclkDiv64 = 6u, ///< Count clock: pclk/64 + TimeraPclkDiv128 = 7u, ///< Count clock: pclk/128 + TimeraPclkDiv256 = 8u, ///< Count clock: pclk/256 + TimeraPclkDiv512 = 9u, ///< Count clock: pclk/512 + TimeraPclkDiv1024 = 10u, ///< Count clock: pclk/1024 +} en_timera_clk_div_t; + +/** + ******************************************************************************* + ** \brief Count mode enumeration + ******************************************************************************/ +typedef enum en_timera_count_mode +{ + TimeraCountModeSawtoothWave = 0u, ///< Sawtooth wave mode + TimeraCountModeTriangularWave = 1u, ///< Triangular wave mode +} en_timera_count_mode_t; + +/** + ******************************************************************************* + ** \brief Count direction enumeration + ******************************************************************************/ +typedef enum en_timera_count_dir +{ + TimeraCountDirDown = 0u, ///< Counter counting down + TimeraCountDirUp = 1u, ///< Counter counting up +} en_timera_count_dir_t; + +/** + ******************************************************************************* + ** \brief Input port filter clock division enumeration + ******************************************************************************/ +typedef enum en_timera_filter_clk_div +{ + TimeraFilterPclkDiv1 = 0u, ///< Filter clock: pclk + TimeraFilterPclkDiv4 = 1u, ///< Filter clock: pclk/4 + TimeraFilterPclkDiv16 = 2u, ///< Filter clock: pclk/16 + TimeraFilterPclkDiv64 = 3u, ///< Filter clock: pclk/64 +} en_timera_filter_clk_div_t; + +/** + ******************************************************************************* + ** \brief Input port filter source enumeration + ** + ** \note __ is unit number,range 1~6 + ******************************************************************************/ +typedef enum en_timera_filter_source +{ + TimeraFilterSourceCh1 = 0u, ///< TIMA__PWM1 input port + TimeraFilterSourceCh2 = 1u, ///< TIMA__PWM2 input port + TimeraFilterSourceCh3 = 2u, ///< TIMA__PWM3 input port + TimeraFilterSourceCh4 = 3u, ///< TIMA__PWM4 input port + TimeraFilterSourceCh5 = 4u, ///< TIMA__PWM5 input port + TimeraFilterSourceCh6 = 5u, ///< TIMA__PWM6 input port + TimeraFilterSourceCh7 = 6u, ///< TIMA__PWM7 input port + TimeraFilterSourceCh8 = 7u, ///< TIMA__PWM8 input port + TimeraFilterSourceClkA = 8u, ///< TIMA__CLKA input port + TimeraFilterSourceClkB = 9u, ///< TIMA__CLKB input port + TimeraFilterSourceTrig = 10u, ///< TIMA__TRIG input port +} en_timera_filter_source_t; + +/** + ******************************************************************************* + ** \brief Timera interrupt request type enumeration + ******************************************************************************/ +typedef enum en_timera_irq_type +{ + TimeraIrqCaptureOrCompareCh1 = 0u, ///< Interrupt request when channel 1 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh2 = 1u, ///< Interrupt request when channel 2 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh3 = 2u, ///< Interrupt request when channel 3 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh4 = 3u, ///< Interrupt request when channel 4 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh5 = 4u, ///< Interrupt request when channel 5 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh6 = 5u, ///< Interrupt request when channel 6 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh7 = 6u, ///< Interrupt request when channel 7 trigger capture event or compare value equal count value + TimeraIrqCaptureOrCompareCh8 = 7u, ///< Interrupt request when channel 8 trigger capture event or compare value equal count value + TimeraIrqOverflow = 8u, ///< Count overflow interrupt request + TimeraIrqUnderflow = 9u, ///< Count underflow interrupt request +} en_timera_irq_type_t; + +/** + ******************************************************************************* + ** \brief Timera flag type enumeration + ******************************************************************************/ +typedef enum en_timera_flag_type +{ + TimeraFlagCaptureOrCompareCh1 = 0u, ///< Match flag when channel 1 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh2 = 1u, ///< Match flag when channel 2 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh3 = 2u, ///< Match flag when channel 3 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh4 = 3u, ///< Match flag when channel 4 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh5 = 4u, ///< Match flag when channel 5 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh6 = 5u, ///< Match flag when channel 6 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh7 = 6u, ///< Match flag when channel 7 trigger capture complete or compare value equal count value + TimeraFlagCaptureOrCompareCh8 = 7u, ///< Match flag when channel 8 trigger capture complete or compare value equal count value + TimeraFlagOverflow = 8u, ///< Count overflow flag + TimeraFlagUnderflow = 9u, ///< Count underflow flag +} en_timera_flag_type_t; + +/** + ******************************************************************************* + ** \brief Timera function mode selection enumeration + ******************************************************************************/ +typedef enum en_timera_func_mode +{ + TimeraModeCompareOutput = 0u, ///< Compare output function + TimeraModeCaptureInput = 1u, ///< Capture input function +} en_timera_func_mode_t; + +/** + ******************************************************************************* + ** \brief Timera count start port output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_count_start_output +{ + TimeraCountStartOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCountStartOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCountStartOutputKeep = 2u, ///< TIMA__PWMn port output to keep +} en_timera_count_start_output_t; + +/** + ******************************************************************************* + ** \brief Timera count stop port output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_count_stop_output +{ + TimeraCountStopOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCountStopOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCountStopOutputKeep = 2u, ///< TIMA__PWMn port output to keep +} en_timera_count_stop_output_t; + +/** + ******************************************************************************* + ** \brief Timera compare value match output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_compare_match_output +{ + TimeraCompareMatchOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraCompareMatchOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraCompareMatchOutputKeep = 2u, ///< TIMA__PWMn port output to keep + TimeraCompareMatchOutputReverse = 3u, ///< TIMA__PWMn port output reverse +} en_timera_compare_match_output_t; + +/** + ******************************************************************************* + ** \brief Timera period value match output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_period_match_output +{ + TimeraPeriodMatchOutputLow = 0u, ///< TIMA__PWMn port output low level + TimeraPeriodMatchOutputHigh = 1u, ///< TIMA__PWMn port output high level + TimeraPeriodMatchOutputKeep = 2u, ///< TIMA__PWMn port output to keep + TimeraPeriodMatchOutputReverse = 3u, ///< TIMA__PWMn port output reverse +} en_timera_period_match_output_t; + +/** + ******************************************************************************* + ** \brief Timera specify output status enumeration + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ******************************************************************************/ +typedef enum en_timera_specify_output +{ + TimeraSpecifyOutputInvalid = 0u, ///< TIMA__PWMn port output invalid + TimeraSpecifyOutputLow = 2u, ///< TIMA__PWMn port output low level from next period + TimeraSpecifyOutputHigh = 3u, ///< TIMA__PWMn port output high level from next period +} en_timera_specify_output_t; + +/** + ******************************************************************************* + ** \brief Timera common trigger source enumeration + ******************************************************************************/ +typedef enum en_timera_com_trigger +{ + TimeraComTrigger_1 = 1u, ///< Select common trigger 1. + TimeraComTrigger_2 = 2u, ///< Select common trigger 2. + TimeraComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2. +} en_timera_com_trigger_t; + +/** + ******************************************************************************* + ** \brief Timera base init structure definition + ******************************************************************************/ +typedef struct stc_timera_base_init +{ + en_timera_clk_div_t enClkDiv; ///< Count clock division select,This is invalid when counting internal or external event + en_timera_count_mode_t enCntMode; ///< Timera count mode + en_timera_count_dir_t enCntDir; ///< Timera count direction + en_functional_state_t enSyncStartupEn; ///< Enable/disable synchronization startup when unit 1 startup,unit 1 set bit invalid + uint16_t u16PeriodVal; ///< Period value +} stc_timera_base_init_t; + +/** + ******************************************************************************* + ** \brief Timera compare output init structure definition + ******************************************************************************/ +typedef struct stc_timera_compare_init +{ + uint16_t u16CompareVal; ///< Compare value + en_timera_count_start_output_t enStartCountOutput; ///< Port status set when count start + en_timera_count_stop_output_t enStopCountOutput; ///< Port status set when count stop + en_timera_compare_match_output_t enCompareMatchOutput; ///< Port status set when compare value match + en_timera_period_match_output_t enPeriodMatchOutput; ///< Port status set when period value match + en_timera_specify_output_t enSpecifyOutput; ///< Specify port status,next period valid,priority more than other port status set + en_functional_state_t enCacheEn; ///< Enable/Disable cache，Only unit 1、3、5、7 valid + en_functional_state_t enTriangularTroughTransEn; ///< Enable/Disable triangular wave trough transmit cache value，Only unit 1、3、5、7 valid + en_functional_state_t enTriangularCrestTransEn; ///< Enable/Disable triangular wave crest transmit cache value，Only unit 1、3、5、7 valid + uint16_t u16CompareCacheVal; ///< Compare cache value,Only unit 1、3、5、7 valid +} stc_timera_compare_init_t; + +/** + ******************************************************************************* + ** \brief Timera capture input init structure definition + ******************************************************************************/ +typedef struct stc_timera_capture_init +{ + en_functional_state_t enCapturePwmRisingEn; ///< Enable/Disable capture channel n active when TIMA__PWMn sample rising + en_functional_state_t enCapturePwmFallingEn; ///< Enable/Disable capture channel n active when TIMA__PWMn sample falling + en_functional_state_t enCaptureSpecifyEventEn; ///< Enable/Disable capture channel n active when specify event trigger,event value is TMRA_HTSSR1 + en_timera_filter_clk_div_t enPwmClkDiv; ///< TIMA__PWMn filter clock select + en_functional_state_t enPwmFilterEn; ///< Enable/Disable TIMA__PWMn filter functions + en_functional_state_t enCaptureTrigRisingEn; ///< Enable/Disable capture channel 4 active when TIMA__TRIG sample rising, only CCONR4 valid + en_functional_state_t enCaptureTrigFallingEn; ///< Enable/Disable capture channel 4 active when TIMA__TRIG sample falling, only CCONR4 valid + en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA__TRIG filter clock select, only CCONR4 valid + en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA__TRIG filter functions , only CCONR4 valid +} stc_timera_capture_init_t; + +/** + ******************************************************************************* + ** \brief Timera Orthogonal coding init structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note PWMn is channel of unit,range 1-8 + ** \note n=2、4、6 when m=1、3、5 or n=1、3、5 when m=2、4、6 + ******************************************************************************/ +typedef struct stc_timera_orthogonal_coding_init +{ + en_functional_state_t enIncClkALowAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enIncClkALowAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enIncClkAHighAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enIncClkAHighAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enIncClkBLowAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enIncClkBLowAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enIncClkBHighAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enIncClkBHighAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enIncTrigRisingEn; ///< TIMA__TRIG sample rising edge hardware increase + en_functional_state_t enIncTrigFallingEn; ///< TIMA__TRIG sample falling edge hardware increase + en_functional_state_t enIncSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase + en_functional_state_t enIncAnotherUnitOverflowEn; ///< Unit n generate count overflow hardware increase when current unit is m. + en_functional_state_t enIncAnotherUnitUnderflowEn; ///< Unit n generate count underflow hardware increase when current unit is m. + en_functional_state_t enDecClkALowAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enDecClkALowAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is low level + en_functional_state_t enDecClkAHighAndClkBRisingEn; ///< TIMA__CLKB sample rising edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enDecClkAHighAndClkBFallingEn; ///< TIMA__CLKB sample falling edge hardware increase when TIMA__CLKA is high level + en_functional_state_t enDecClkBLowAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enDecClkBLowAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is low level + en_functional_state_t enDecClkBHighAndClkARisingEn; ///< TIMA__CLKA sample rising edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enDecClkBHighAndClkAFallingEn; ///< TIMA__CLKA sample falling edge hardware increase when TIMA__CLKB is high level + en_functional_state_t enDecTrigRisingEn; ///< TIMA__TRIG sample rising edge hardware increase + en_functional_state_t enDecTrigFallingEn; ///< TIMA__TRIG sample falling edge hardware increase + en_functional_state_t enDecSpecifyEventTriggerEn; ///< TIMA_HTSSR0 register Specify event trigger hardware increase + en_functional_state_t enDecAnotherUnitUnderflowEn; ///< Unit n generate count overflow hardware increase when current unit is m. + en_functional_state_t enDecAnotherUnitOverflowEn; ///< Unit n generate count underflow hardware increase when current unit is m. + en_timera_filter_clk_div_t enClkAClkDiv; ///< TIMA__CLKA filter clock select + en_functional_state_t enClkAFilterEn; ///< Enable/Disable TIMA__CLKA filter functions + en_timera_filter_clk_div_t enClkBClkDiv; ///< TIMA__CLKB filter clock select + en_functional_state_t enClkBFilterEn; ///< Enable/Disable TIMA__CLKB filter functions + en_timera_filter_clk_div_t enTrigClkDiv; ///< TIMA__TRIG filter clock select + en_functional_state_t enTrigFilterEn; ///< Enable/Disable TIMA__TRIG filter functions +} stc_timera_orthogonal_coding_init_t; + +/** + ******************************************************************************* + ** \brief Timera hardware startup config structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note TMRA_HTSSR0 trigger startup only when unit 2~6 valid,unit 1 is invalid + ******************************************************************************/ +typedef struct stc_timera_hw_startup_config +{ + en_functional_state_t enTrigRisingStartupEn; ///< Hardware startup TIMA_ when TIMA__TRIG sample rising edge(sync start valid) + en_functional_state_t enTrigFallingStartupEn; ///< Hardware startup TIMA_ when TIMA__TRIG sample falling edge(sync start valid) + en_functional_state_t enSpecifyEventStartupEn; ///< Hardware startup TIMA_ when TIMA_HTSSR0 register Specify event trigger +} stc_timera_hw_startup_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware stop config structure definition + ** + ** \note __ is unit number,range 1~6 + ******************************************************************************/ +typedef struct stc_timera_hw_stop_config +{ + en_functional_state_t enTrigRisingStopEn; ///< Hardware stop TIMA_ when TIMA__TRIG sample rising edge + en_functional_state_t enTrigFallingStopEn; ///< Hardware stop TIMA_ when TIMA__TRIG sample falling edge + en_functional_state_t enSpecifyEventStopEn; ///< Hardware stop TIMA_ when TIMA_HTSSR0 register Specify event trigger +} stc_timera_hw_stop_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware clear config structure definition + ** + ** \note __ is unit number,range 1~6 + ** \note n=2、4、6 when m=1、3、5 or n=1、3、5 when m=2、4、6 + ******************************************************************************/ +typedef struct stc_timera_hw_clear_config +{ + en_functional_state_t enTrigRisingClearEn; ///< Hardware clear TIMA_ when TIMA__TRIG sample rising edge + en_functional_state_t enTrigFallingClearEn; ///< Hardware clear TIMA_ when TIMA__TRIG sample falling edge + en_functional_state_t enSpecifyEventClearEn; ///< Hardware clear TIMA_ when TIMA_HTSSR0 register Specify event trigger + en_functional_state_t enAnotherUnitTrigRisingClearEn; ///< Hardware clear TIMA_ when unit n TRIG port sample rising when current unit is m. + en_functional_state_t enAnotherUnitTrigFallingClearEn; ///< Hardware clear TIMA_ when unit n TRIG port sample falling when current unit is m. + en_functional_state_t enChannel3RisingClearEn; ///< Hardware clear TIMA_ when TIMA__PWM3 sample rising edge + en_functional_state_t enChannel3FallingClearEn; ///< Hardware clear TIMA_ when TIMA__PWM3 sample falling edge +} stc_timera_hw_clear_config_t; + +/** + ******************************************************************************* + ** \brief Timera hardware trigger init structure definition + ******************************************************************************/ +typedef struct stc_timera_hw_trigger_init +{ + stc_timera_hw_startup_config_t stcHwStartup; ///< Hardware startup condition config + stc_timera_hw_stop_config_t stcHwStop; ///< Hardware stop condition config + stc_timera_hw_clear_config_t stcHwClear; ///< Hardware clear condition config +} stc_timera_hw_trigger_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit); +en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt); +uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period); +uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta); +en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta); + +/* Compare output functions */ +en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_compare_init_t *pstcCompareInit); +en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareVal); +uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel); +en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareCache); +en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); +en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_timera_specify_output_t enOutputSta); +en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); + +/* Capture input functions */ +en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_capture_init_t *pstcCapInit); +en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta); +uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel); + +/* Orthogonal coding functions */ +en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit); +en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt); +uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx); +en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta); + +/* Hardware control functions */ +en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit); +en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup); +en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop); +en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear); + +/* interrupt and flags functions */ +en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq, + en_functional_state_t enNewSta); +en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag); +en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag); + +/* Event config functions */ +en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta); +en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc); +en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc); +en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta); +en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta); + +//@} // TimeraGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TIMERA_ENABLE */ + +#endif /* __HC32F460_TIMERA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_trng.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_trng.h new file mode 100644 index 0000000000..6131a9ca1f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_trng.h @@ -0,0 +1,100 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_trng.h + ** + ** A detailed description is available at + ** @link TrngGroup Trng description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Trng. + ** + ******************************************************************************/ +#ifndef __HC32F460_TRNG_H__ +#define __HC32F460_TRNG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_TRNG_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup TrngGroup True Random Number Generator(TRNG) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* The data register loads the new initial value from the random number + generator before the random number is generated. */ +typedef enum en_trng_load_ctrl +{ + TrngLoadNewInitValue_Disable = 0x0, ///< Disable load new initial values. + TrngLoadNewInitValue_Enable = 0x1, ///< Enable load new initial values. +} en_trng_load_ctrl_t; + +/* Shift n times when capturing random noise. */ +typedef enum en_trng_shift_cnt +{ + TrngShiftCount_32 = 0x3, ///< Shift 32 times when capturing random noise. + TrngShiftCount_64 = 0x4, ///< Shift 64 times when capturing random noise. + TrngShiftCount_128 = 0x5, ///< Shift 128 times when capturing random noise. + TrngShiftCount_256 = 0x6, ///< Shift 256 times when capturing random noise. +} en_trng_shift_cnt_t; + +/* TRNG initialization structure definition. */ +typedef struct stc_trng_init +{ + en_trng_load_ctrl_t enLoadCtrl; ///< @ref en_trng_load_ctrl_t. + en_trng_shift_cnt_t enShiftCount; ///< @ref en_trng_shift_cnt_t. +} stc_trng_init_t; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +en_result_t TRNG_Init(const stc_trng_init_t *pstcInit); +void TRNG_DeInit(void); +en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout); + +void TRNG_StartIT(void); +void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length); + +//@} // TrngGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_TRNG_ENABLE */ + +#endif /* __HC32F460_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_usart.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_usart.h new file mode 100644 index 0000000000..144745581e --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_usart.h @@ -0,0 +1,359 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_usart.h + ** + ** A detailed description is available at + ** @link UsartGroup USART description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of USART. + ** + ******************************************************************************/ +#ifndef __HC32F460_USART_H__ +#define __HC32F460_USART_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_USART_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup UsartGroup Universal Synchronous Asynchronous Receiver \ + ** Transmitter(USART) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief USART tx mode in multiple processor mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_mp_tx_mode +{ + UsartMpTxData = 0u, ///< USART Send data in multiple-processor mode + UsartMpTxId = 1u, ///< USART Send ID in multiple-processor mode +} en_usart_mp_tx_mode_t; + +/** + ******************************************************************************* + ** \brief USART clock prescale enumeration + ** + ******************************************************************************/ +typedef enum en_usart_clk_div +{ + UsartClkDiv_1 = 0u, ///< PCLK/1 + UsartClkDiv_4 = 1u, ///< PCLK/4 + UsartClkDiv_16 = 2u, ///< PCLK/16 + UsartClkDiv_64 = 3u, ///< PCLK/64 +} en_usart_clk_div_t; + +/** + ****************************************************************************** + ** \brief USART mode + ** + ******************************************************************************/ +typedef enum en_usart_mode +{ + UsartUartMode = 0u, ///< UART mode + UsartClkSyncMode = 1u, ///< Clock sync mode + UsartSmartCardMode = 2u, ///< Smart card mode +} en_usart_mode_t; + +/** + ****************************************************************************** + ** \brief USART data direction + ** + ******************************************************************************/ +typedef enum en_usart_data_dir +{ + UsartDataLsbFirst = 0u, ///< LSB first + UsartDataMsbFirst = 1u, ///< MSB first +} en_usart_data_dir_t; + +/** + ****************************************************************************** + ** \brief USART sample mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sample_mode +{ + UsartSampleBit16 = 0u, ///< 16 Bit + UsartSampleBit8 = 1u, ///< 8 Bit +} en_usart_sample_mode_t; + +/** + ****************************************************************************** + ** \brief USART data length enumeration + ** + ******************************************************************************/ +typedef enum en_usart_data_len +{ + UsartDataBits8 = 0u, ///< 8 Bit + UsartDataBits9 = 1u, ///< 9 Bit +} en_usart_data_len_t; + +/** + ****************************************************************************** + ** \brief USART parity format enumeration + ** + ******************************************************************************/ +typedef enum en_usart_parity +{ + UsartParityNone = 0u, ///< No parity bit is used. + UsartParityEven = 1u, ///< Even parity bit is used. + UsartParityOdd = 2u, ///< Odd parity bit is used. +} en_usart_parity_t; + +/** + ****************************************************************************** + ** \brief USART functions enumeration + ** + ******************************************************************************/ +typedef enum en_usart_func +{ + UsartRx = 0u, ///< UART RX function + UsartRxInt = 1u, ///< USART RX interrupt function + UsartTx = 2u, ///< UART TX function + UsartTxEmptyInt = 3u, ///< USART TX empty interrupt function + UsartTimeOut = 4u, ///< UART RX timeout function + UsartTimeOutInt = 5u, ///< UART RX timeout interrupt function + UsartSilentMode = 6u, ///< USART silent function + UsartTxCmpltInt = 7u, ///< USART TX complete interrupt function + UsartTxAndTxEmptyInt = 8u, ///< USART TX function and USART TX empty interrupt function + UsartParityCheck = 9u, ///< USART Parity check function + UsartNoiseFilter = 10u, ///< USART noise filter function + UsartFracBaudrate = 11u, ///< USART fractional baudrate function + UsartMulProcessor = 12u, ///< USART multiple processor function + UsartSmartCard = 13u, ///< USART smart card mode function + UsartCts = 14u, ///< USART CTS function +} en_usart_func_t; + +/** + ******************************************************************************* + ** \brief USART status type enumeration + ** + ******************************************************************************/ +typedef enum en_usart_status +{ + UsartParityErr = (1u << 0), ///< USART parity error + UsartFrameErr = (1u << 1), ///< USART receive frame error + UsartOverrunErr = (1u << 3), ///< USART receive over-run error + UsartRxNoEmpty = (1u << 5), ///< USART data receive register is not empty + UsartTxComplete = (1u << 6), ///< USART transfer completely + UsartTxEmpty = (1u << 7), ///< USART data transfer register is empty + UsartRxTimeOut = (1u << 8), ///< USART data receive timeout + UsartRxMpb = (1u << 16), ///< USART multiple processor id or normal data, 0: receive date; 1: received ID +} en_usart_status_t; + +/** + ******************************************************************************* + ** \brief USART Stop bit length select enumeration + ** + ******************************************************************************/ +typedef enum en_usart_stop_bit +{ + UsartOneStopBit = 0u, ///< 1 Stop Bit + UsartTwoStopBit = 1u, ///< 2 Stop Bit +} en_usart_stop_bit_t; + +/** + ******************************************************************************* + ** \brief USART start bit detect mode enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sb_detect_mode +{ + UsartStartBitLowLvl = 0u, ///< Start bit: RD pin low level + UsartStartBitFallEdge = 1u, ///< Start bit: RD pin falling edge +} en_usart_sb_detect_mode_t; + +/** + ******************************************************************************* + ** \brief USART clock mode selection enumeration + ** + ******************************************************************************/ +typedef enum en_usart_clk_mode +{ + UsartIntClkCkNoOutput = 0u, ///< Select internal clock source and don't output clock. + UsartIntClkCkOutput = 1u, ///< Select internal clock source and output clock. + UsartExtClk = 2u, ///< Select external clock source. +} en_usart_clk_mode_t; + +/** + ******************************************************************************* + ** \brief USART smart-card mode selection enumeration + ** + ******************************************************************************/ +typedef enum en_usart_hw_flow_ctrl +{ + UsartRtsEnable = 0u, ///< Enable RTS function. + UsartCtsEnable = 1u, ///< Enable CTS function. +} en_usart_hw_flow_ctrl_t; + +/** + ****************************************************************************** + ** \brief USART etu clocks of smart card enumeration + ** + ******************************************************************************/ +typedef enum en_usart_sc_etu_clk +{ + UsartScEtuClk32 = 0u, ///< 1 etu = 32/f + UsartScEtuClk64 = 1u, ///< 1 etu = 64/f + UsartScEtuClk128 = 3u, ///< 1 etu = 128/f + UsartScEtuClk256 = 5u, ///< 1 etu = 256/f + UsartScEtuClk372 = 6u, ///< 1 etu = 372/f +} en_usart_sc_etu_clk_t; + +/** + ******************************************************************************* + ** \brief Uart mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_uart_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_len_t enDataLength; ///< 8/9 Bit character length and this parameter can be a value of @ref en_usart_data_len_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t + + en_usart_stop_bit_t enStopBit; ///< Stop bit and this parameter can be a value of @ref en_usart_stop_bit_t + + en_usart_parity_t enParity; ///< Parity format and this parameter can be a value of @ref en_usart_parity_t + + en_usart_sample_mode_t enSampleMode; ///< USART sample mode, and this parameter can be a value of @ref en_usart_sample_mode_t + + en_usart_sb_detect_mode_t enDetectMode; ///< USART start bit detect mode and this parameter can be a value of @ref en_usart_sb_detect_mode_t + + en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t +} stc_usart_uart_init_t; + +/** + ******************************************************************************* + ** \brief Clock sync mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_clksync_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t + + en_usart_hw_flow_ctrl_t enHwFlow; ///< Hardware flow control and this parameter can be a value of @ref en_usart_hw_flow_ctrl_t +} stc_usart_clksync_init_t; + +/** + ******************************************************************************* + ** \brief Smart card mode initialization configuration + ** + ******************************************************************************/ +typedef struct stc_usart_sc_init +{ + en_usart_clk_mode_t enClkMode; ///< Clock mode and this parameter can be a value of @ref en_usart_clk_mode_t + + en_usart_clk_div_t enClkDiv; ///< USART divide PCLK1, and this parameter can be a value of @ref en_usart_clk_div_t + + en_usart_data_dir_t enDirection; ///< UART data direction and this parameter can be a value of @ref en_usart_data_dir_t +} stc_usart_sc_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInitCfg); +en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInitCfg); +en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_sc_init_t *pstcInitCfg); +en_result_t USART_DeInit(M4_USART_TypeDef *USARTx); +en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus); +en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus); +en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx, + en_usart_func_t enFunc, + en_functional_state_t enCmd); +en_result_t USART_SetParity(M4_USART_TypeDef *USARTx, + en_usart_parity_t enParity); +en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx); +en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx, + en_usart_sample_mode_t enSampleMode); +en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx); +en_result_t USART_SetDataDirection(M4_USART_TypeDef *USARTx, + en_usart_data_dir_t enDir); +en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx); +en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx, + en_usart_data_len_t enDataLen); +en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx); +en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx, + en_usart_clk_mode_t enClkMode); +en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetMode(M4_USART_TypeDef *USARTx, + en_usart_mode_t enMode); +en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx, + en_usart_stop_bit_t enStopBit); +en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx); +en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx, + en_usart_sb_detect_mode_t enDetectMode); +en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx); +en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, + en_usart_hw_flow_ctrl_t enHwFlowCtrl); +en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx); +en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx, + en_usart_clk_div_t enClkPrescale); +en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx); +en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx, + en_usart_sc_etu_clk_t enEtuClk); +en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx); +en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data); +uint16_t USART_RecData(M4_USART_TypeDef *USARTx); +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); + +//@} // UsartGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_USART_ENABLE */ + +#endif /* __HC32F460_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_utility.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_utility.h new file mode 100644 index 0000000000..d4eda98617 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_utility.h @@ -0,0 +1,108 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_utility.h + ** + ** A detailed description is available at + ** @link DdlUtilityGroup Ddl Utility description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library Utility. + ** + ******************************************************************************/ +#ifndef __HC32F460_UTILITY_H__ +#define __HC32F460_UTILITY_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_UTILITY_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup DdlUtilityGroup Device Driver Library Utility(DDLUTILITY) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/* A approximate delay */ +void Ddl_Delay1ms(uint32_t u32Cnt); +void Ddl_Delay1us(uint32_t u32Cnt); + +/* Systick functions */ +en_result_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +/*! Ddl assert, you can add your own assert functions by implement the function +Ddl_AssertHook definition follow the function Ddl_AssertHook declaration */ +#ifdef __DEBUG +#define DDL_ASSERT(x) \ +do{ \ + ((x) ? (void)0 : Ddl_AssertHandler((uint8_t *)__FILE__, __LINE__)); \ +}while(0) +/* Exported function */ +void Ddl_AssertHandler(uint8_t *file, int16_t line); +#else +#define DDL_ASSERT(x) (void)(0) +#endif /* __DEBUG */ + +#if (DDL_PRINT_ENABLE == DDL_ON) +#include + +en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx, + uint32_t u32Baudrate, + void (*PortInit)(void)); + +#define DDL_PrintfInit (void)UART_PrintfInit +#define DDL_Printf (void)printf +#else +#define DDL_PrintfInit(x, y, z) +#define DDL_Printf(fmt, ...) +#endif + +//@} // DdlUtilityGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_UTILITY_ENABLE */ + +#endif /* __HC32F460_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_wdt.h b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_wdt.h new file mode 100644 index 0000000000..0ae3521d25 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/inc/hc32f460_wdt.h @@ -0,0 +1,162 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_wdt.h + ** + ** A detailed description is available at + ** @link WdtGroup Watchdog Counter description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of WDT. + ** + ******************************************************************************/ +#ifndef __HC32F460_WDT_H__ +#define __HC32F460_WDT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +#if (DDL_WDT_ENABLE == DDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ******************************************************************************* + ** \defgroup WdtGroup WatchDog Counter(WDT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief WDT count cycle enumeration + ******************************************************************************/ +typedef enum en_wdt_count_cycle +{ + WdtCountCycle256 = 0u, ///< 256 cycle + WdtCountCycle4096 = 1u, ///< 4096 cycle + WdtCountCycle16384 = 2u, ///< 16384 cycle + WdtCountCycle65536 = 3u, ///< 65536 cycle +} en_wdt_count_cycle_t; + +/** + ******************************************************************************* + ** \brief WDT count clock division enumeration + ******************************************************************************/ +typedef enum en_wdt_clk_div +{ + WdtPclk3Div4 = 2u, ///< PCLK3/4 + WdtPclk3Div64 = 6u, ///< PCLK3/64 + WdtPclk3Div128 = 7u, ///< PCLK3/128 + WdtPclk3Div256 = 8u, ///< PCLK3/256 + WdtPclk3Div512 = 9u, ///< PCLK3/512 + WdtPclk3Div1024 = 10u, ///< PCLK3/1024 + WdtPclk3Div2048 = 11u, ///< PCLK3/2048 + WdtPclk3Div8192 = 13u, ///< PCLK3/8192 +} en_wdt_clk_div_t; + +/** + ******************************************************************************* + ** \brief WDT allow refresh percent range enumeration + ******************************************************************************/ +typedef enum en_wdt_refresh_range +{ + WdtRefresh100Pct = 0u, ///< 100% + WdtRefresh0To25Pct = 1u, ///< 0%~25% + WdtRefresh25To50Pct = 2u, ///< 25%~50% + WdtRefresh0To50Pct = 3u, ///< 0%~50% + WdtRefresh50To75Pct = 4u, ///< 50%~75% + WdtRefresh0To25PctAnd50To75Pct = 5u, ///< 0%~25% & 50%~75% + WdtRefresh25To75Pct = 6u, ///< 25%~75% + WdtRefresh0To75Pct = 7u, ///< 0%~75% + WdtRefresh75To100Pct = 8u, ///< 75%~100% + WdtRefresh0To25PctAnd75To100Pct = 9u, ///< 0%~25% & 75%~100% + WdtRefresh25To50PctAnd75To100Pct = 10u, ///< 25%~50% & 75%~100% + WdtRefresh0To50PctAnd75To100Pct = 11u, ///< 0%~50% & 75%~100% + WdtRefresh50To100Pct = 12u, ///< 50%~100% + WdtRefresh0To25PctAnd50To100Pct = 13u, ///< 0%~25% & 50%~100% + WdtRefresh25To100Pct = 14u, ///< 25%~100% + WdtRefresh0To100Pct = 15u, ///< 0%~100% +} en_wdt_refresh_range_t; + +/** + ******************************************************************************* + ** \brief WDT refresh error or count underflow trigger event type enumeration + ******************************************************************************/ +typedef enum en_wdt_event_request_type +{ + WdtTriggerInterruptRequest = 0u, ///< Interrupt request + WdtTriggerResetRequest = 1u, ///< Reset request +} en_wdt_event_request_type_t; + +/** + ******************************************************************************* + ** \brief WDT flag type enumeration + ******************************************************************************/ +typedef enum en_wdt_flag_type +{ + WdtFlagCountUnderflow = 0u, ///< Count underflow flag + WdtFlagRefreshError = 1u, ///< Refresh error flag +} en_wdt_flag_type_t; + +/** + ******************************************************************************* + ** \brief WDT init structure definition + ******************************************************************************/ +typedef struct stc_wdt_init +{ + en_wdt_count_cycle_t enCountCycle; ///< Count cycle + en_wdt_clk_div_t enClkDiv; ///< Count clock division + en_wdt_refresh_range_t enRefreshRange; ///< Allow refresh percent range + en_functional_state_t enSleepModeCountEn; ///< Enable/disable count in the sleep mode + en_wdt_event_request_type_t enRequestType; ///< Refresh error or count underflow trigger event type +} stc_wdt_init_t; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/* Base functions */ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +en_result_t WDT_RefreshCounter(void); +uint16_t WDT_GetCountValue(void); + +/* Flags functions */ +en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag); +en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag); + +//@} // WdtGroup + +#ifdef __cplusplus +} +#endif + +#endif /* DDL_WDT_ENABLE */ + +#endif /* __HC32F460_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_adc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_adc.c new file mode 100644 index 0000000000..da61a4ca93 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_adc.c @@ -0,0 +1,1739 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_adc.c + ** + ** A detailed description is available at + ** @link AdcGroup Adc description @endlink + ** + ** - 2018-11-30 CDT First version for Device Driver Library of Adc. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_adc.h" +#include "hc32f460_utility.h" + +#if (DDL_ADC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for ADC peripherals. */ +#define IS_ADC_PERIPH(ADCx) \ +( ((ADCx) == M4_ADC1) || \ + ((ADCx) == M4_ADC2)) + +/*! Parameter validity check for ADC1 channel index. */ +#define IS_ADC1_CH_INDEX(x) \ +( ((x) < ADC1_CH_COUNT)) + +/*! Parameter validity check for ADC2 channel index. */ +#define IS_ADC2_CH_INDEX(x) \ +( ((x) < ADC2_CH_COUNT)) + +/*! Parameter validity check for ADC average count. */ +#define IS_ADC_AVCNT(AVCNT) \ +( ((AVCNT) == AdcAvcnt_2) || \ + (((AVCNT) >= AdcAvcnt_4) && ((AVCNT) <= AdcAvcnt_256))) + +/*! Parameter validity check for ADC data alignment. */ +#define IS_ADC_DATA_ALIGN(ALIGN) \ +( ((ALIGN) == AdcDataAlign_Right) || \ + ((ALIGN) == AdcDataAlign_Left)) + +/*! Parameter validity check for ADC auto clear DR. */ +#define IS_ADC_CLREN(EN) \ +( ((EN) == AdcClren_Enable) || \ + ((EN) == AdcClren_Disable)) + +/*! Parameter validity check for ADC resolution. */ +#define IS_ADC_RESOLUTION(RESOLUTION) \ +( ((RESOLUTION) == AdcResolution_8Bit) || \ + ((RESOLUTION) == AdcResolution_10Bit) || \ + ((RESOLUTION) == AdcResolution_12Bit)) + +/*! Parameter validity check for ADC scan convert mode. */ +#define IS_ADC_SCAN_MODE(MODE) \ +( ((MODE) == AdcMode_SAOnce) || \ + ((MODE) == AdcMode_SAContinuous) || \ + ((MODE) == AdcMode_SAOnceSBOnce) || \ + ((MODE) == AdcMode_SAContinuousSBOnce)) + +/*! Parameter validity check for ADC RSCHSEL. */ +#define IS_ADC_RSCHSEL(SEL) \ +( ((SEL) == AdcRschsel_Continue) || \ + ((SEL) == AdcRschsel_Restart)) + +/*! Parameter validity check for ADC SA trigger source. */ +#define IS_ADC_TRGEN(EN) \ +( ((EN) == AdcTrgen_Enable) || \ + ((EN) == AdcTrgen_Disable)) + +/*! Parameter validity check for ADC SA trigger source. */ +#define IS_ADC_TRGSEL(SEL) \ +( ((SEL) == AdcTrgsel_ADTRGX) || \ + ((SEL) == AdcTrgsel_TRGX0) || \ + ((SEL) == AdcTrgsel_TRGX1) || \ + ((SEL) == AdcTrgsel_TRGX0_TRGX1)) + +/*! Parameter validity check for ADC common trigger. */ +#define IS_ADC_COM_TRIGGER(x) \ +( ((x) == AdcComTrigger_1) || \ + ((x) == AdcComTrigger_2) || \ + ((x) == AdcComTrigger_1_2)) + +/*! Parameter validity check for ADC EOCAIEN/ENCBIEN. */ +#define IS_ADC_EOCIEN(EN) \ +( ((EN) == AdcEocien_Disable) || \ + ((EN) == AdcEocien_Enable)) + +/*! Parameter validity check for ADC sampling time. */ +#define IS_ADC_SAMPLE_TIME(TIME) \ +( ((TIME) == 255u) || \ + (((TIME) >= 5u) && ((TIME) <= 254u))) + +/*! Parameter validity check for ADC sync trigger mode. */ +#define IS_ADC_SYNC_MODE(MODE) \ +( ((MODE) == AdcSync_SingleSerial) || \ + ((MODE) == AdcSync_SingleParallel) || \ + ((MODE) == AdcSync_ContinuousSerial) || \ + ((MODE) == AdcSync_ContinuousParallel)) + +/*! Parameter validity check for ADC sync able. */ +#define IS_ADC_SYNC_ENABLE(EN) \ +( ((EN) == AdcSync_Disable) || \ + ((EN) == AdcSync_Enable)) + +/*! Parameter validity check for ADC ADWIEN */ +#define IS_ADC_AWDIEN(EN) \ +( ((EN) == AdcAwdInt_Disable) || \ + ((EN) == AdcAwdInt_Enable)) + +/*! Parameter validity check for ADC AWDSS */ +#define IS_ADC_AWDSS(SS) \ +( ((SS) == AdcAwdSel_SA_SB) || \ + ((SS) == AdcAwdSel_SA) || \ + ((SS) == AdcAwdSel_SB) || \ + ((SS) == AdcAwdSel_SB_SA)) + +/*! Parameter validity check for ADC AWDMD */ +#define IS_ADC_AWDMD(MD) \ +( ((MD) == AdcAwdCmpMode_0) || \ + ((MD) == AdcAwdCmpMode_1)) + +/*! Parameter validity check for ADC AWDEN */ +#define IS_ADC_AWDEN(EN) \ +( ((EN) == AdcAwd_Disable) || \ + ((EN) == AdcAwd_Enable)) + +/*! Parameter validity check for ADC PGA control */ +#define IS_ADC_PGA_CTL(CTL) \ +( ((CTL) == AdcPgaCtl_Invalid) || \ + ((CTL) == AdcPgaCtl_Amplify)) + +/*! Parameter validity check for ADC gain factor. */ +#define IS_ADC_PGA_FACTOR(FACTOR) \ +( ((FACTOR) == AdcPgaFactor_2) || \ + (((FACTOR) >= AdcPgaFactor_2P133) && ((FACTOR) <= AdcPgaFactor_32))) + +/*! Parameter validity check for ADC PGA negative. */ +#define IS_ADC_PGA_NEGATIVE(N) \ +( ((N) == AdcPgaNegative_VSSA) || \ + ((N) == AdcPgaNegative_PGAVSS)) + +/*! Parameter validity check for ADC trigger source event . */ +#define IS_ADC_TRIG_SRC_EVENT(x) \ +( ((x) == EVT_PORT_EIRQ0) || \ + (((x) > EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void ADC_ReadAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes an ADC instance. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcInit Pointer to ADC initialization structure. + ** See @ref stc_adc_init_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (NULL != pstcInit)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcInit->enResolution)); + DDL_ASSERT(IS_ADC_DATA_ALIGN(pstcInit->enDataAlign)); + DDL_ASSERT(IS_ADC_CLREN(pstcInit->enAutoClear)); + DDL_ASSERT(IS_ADC_SCAN_MODE(pstcInit->enScanMode)); + DDL_ASSERT(IS_ADC_RSCHSEL(pstcInit->enRschsel)); + + /* Stop ADC conversion. */ + ADCx->STR = 0u; + + ADCx->CR0_f.ACCSEL = pstcInit->enResolution; + ADCx->CR0_f.DFMT = pstcInit->enDataAlign; + ADCx->CR0_f.CLREN = pstcInit->enAutoClear; + ADCx->CR0_f.MS = pstcInit->enScanMode; + ADCx->CR1_f.RSCHSEL = pstcInit->enRschsel; + + /* Disable EOC(End Of Conversion) interrupts default. */ + ADCx->ICR = (uint8_t)0x0; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes an ADC instance. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + /* Set the value of all registers to the reset value. */ + /* Stop ADC conversion. */ + ADCx->STR = 0u; + ADCx->CR0 = 0u; + ADCx->CR1 = 0u; + ADCx->TRGSR = 0u; + ADCx->CHSELRA0 = 0u; + ADCx->CHSELRB0 = 0u; + ADCx->AVCHSELR0 = 0u; + ADCx->AWDCHSR0 = 0u; + ADCx->SSTR0 = (uint8_t)0x0B; + ADCx->SSTR1 = (uint8_t)0x0B; + ADCx->SSTR2 = (uint8_t)0x0B; + ADCx->SSTR3 = (uint8_t)0x0B; + ADCx->SSTR4 = (uint8_t)0x0B; + ADCx->SSTR5 = (uint8_t)0x0B; + ADCx->SSTR6 = (uint8_t)0x0B; + ADCx->SSTR7 = (uint8_t)0x0B; + ADCx->SSTR8 = (uint8_t)0x0B; + ADCx->CHMUXR0 = (uint16_t)0x3210; + ADCx->CHMUXR1 = (uint16_t)0x7654; + ADCx->ISR = 0u; + ADCx->ICR = (uint8_t)0x03; + ADCx->AWDCR = 0u; + ADCx->AWDDR0 = 0u; + ADCx->AWDDR1 = 0u; + ADCx->AWDCHSR0 = 0u; + ADCx->AWDSR0 = 0u; + + if (M4_ADC1 == ADCx) + { + ADCx->CHSELRA1 = 0u; + ADCx->CHSELRB1 = 0u; + ADCx->AVCHSELR1 = 0u; + ADCx->CHMUXR2 = (uint16_t)0xBA98; + ADCx->CHMUXR3 = (uint16_t)0xFEDC; + ADCx->SYNCCR = (uint16_t)0x0C00; + ADCx->AWDCHSR1 = 0u; + ADCx->AWDSR1 = 0u; + ADCx->PGACR = 0u; + ADCx->PGAGSR = 0u; + ADCx->PGAINSR0 = 0u; + ADCx->PGAINSR1 = 0u; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set scan mode. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param[in] enMode See @ref en_adc_scan_mode_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_SCAN_MODE(enMode)); + + ADCx->CR0_f.MS = enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcTrgCfg Pointer to ADC trigger source configuration structure. + ** \arg u8Sequence The sequence which you want to set it's trigger source. + ** \arg enTrgEnable Enable or disable trigger source. + ** \arg enTrgSel The type of trigger source. + ** \arg enInTrg0 Event number @ref en_event_src_t. + ** \arg enInTrg1 Event number @ref en_event_src_t. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** \note Sequence A and Sequence B CAN NOT set the same trigger source. + ** + ******************************************************************************/ +en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, + const stc_adc_trg_cfg_t *pstcTrgCfg) +{ + uint32_t u32TrgSelR; + __IO uint32_t *io32AdcxTrgSelR0; + __IO uint32_t *io32AdcxTrgSelR1; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && + (NULL != pstcTrgCfg) && + (pstcTrgCfg->u8Sequence <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_TRGSEL(pstcTrgCfg->enTrgSel)); + + if (ADC_SEQ_A == pstcTrgCfg->u8Sequence) + { + ADCx->TRGSR_f.TRGSELA = pstcTrgCfg->enTrgSel; + } + else + { + ADCx->TRGSR_f.TRGSELB = pstcTrgCfg->enTrgSel; + } + + if (AdcTrgsel_ADTRGX != pstcTrgCfg->enTrgSel) + { + if (M4_ADC1 == ADCx) + { + io32AdcxTrgSelR0 = &(M4_AOS->ADC1_ITRGSELR0); + io32AdcxTrgSelR1 = &(M4_AOS->ADC1_ITRGSELR1); + } + else + { + io32AdcxTrgSelR0 = &(M4_AOS->ADC2_ITRGSELR0); + io32AdcxTrgSelR1 = &(M4_AOS->ADC2_ITRGSELR1); + } + + if ((pstcTrgCfg->enTrgSel & AdcTrgsel_TRGX0) == AdcTrgsel_TRGX0) + { + DDL_ASSERT(IS_ADC_TRIG_SRC_EVENT(pstcTrgCfg->enInTrg0)); + + u32TrgSelR = *io32AdcxTrgSelR0; + u32TrgSelR &= ~0x1FFul; + u32TrgSelR |= pstcTrgCfg->enInTrg0; + *io32AdcxTrgSelR0 = u32TrgSelR; + } + if ((pstcTrgCfg->enTrgSel & AdcTrgsel_TRGX1) == AdcTrgsel_TRGX1) + { + DDL_ASSERT(IS_ADC_TRIG_SRC_EVENT(pstcTrgCfg->enInTrg1)); + + u32TrgSelR = *io32AdcxTrgSelR1; + u32TrgSelR &= ~0x1FFul; + u32TrgSelR |= pstcTrgCfg->enInTrg1; + *io32AdcxTrgSelR1 = u32TrgSelR; + } + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to set it's trigger source. + ** + ** \param [in] enState Enable or disable trigger source. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, + uint8_t u8Seq, + en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (u8Seq <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (ADC_SEQ_A == u8Seq) + { + ADCx->TRGSR_f.TRGENA = enState; + } + else + { + ADCx->TRGSR_f.TRGENB = enState; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC common trigger. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enTrgSel ADC trigger source type. See @ref en_adc_trgsel_t for details. + ** + ** \param [in] enComTrigger ADC common trigger selection. See @ref en_adc_com_trigger_t for details. + ** + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \ + en_adc_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = enComTrigger; + uint32_t u32ITRGSELRAddr; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_TRGSEL(enTrgSel) && (enTrgSel != AdcTrgsel_ADTRGX)); + DDL_ASSERT(IS_ADC_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (M4_ADC1 == ADCx) + { + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC1_ITRGSELR0; + } + else + { + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC2_ITRGSELR0; + } + + u32ComTrig <<= 30u; + + if ((enTrgSel & AdcTrgsel_TRGX0) == AdcTrgsel_TRGX0) + { + if (enState == Enable) + { + *(__IO uint32_t *)u32ITRGSELRAddr |= u32ComTrig; + } + else + { + *(__IO uint32_t *)u32ITRGSELRAddr &= ~u32ComTrig; + } + } + + if ((enTrgSel & AdcTrgsel_TRGX1) == AdcTrgsel_TRGX1) + { + u32ITRGSELRAddr += 4ul; + if (enState == Enable) + { + *(__IO uint32_t *)u32ITRGSELRAddr |= u32ComTrig; + } + else + { + *(__IO uint32_t *)u32ITRGSELRAddr &= ~u32ComTrig; + } + } +} + +/** + ******************************************************************************* + ** \brief Add ADC channel. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcChCfg Pointer to ADC channel configuration structure. + ** \arg u32Channel The channel(s) you want to configure. + ** \arg u8Sequence The sequence which the channel(s) belong(s) to. + ** \arg pu8SampTime Pointer to sampling time. + ** eg. u32Channel = 1001b + ** pu8SampTime[0] = channel 0's time + ** pu8SampTime[1] = channel 3's time + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** \note Sequence A and Sequence B CAN NOT set the same channel!!! + ** + ******************************************************************************/ +en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t j; + uint32_t u32ChannelSel; + __IO uint8_t *io8Sstr; + + if ((NULL != ADCx) && + (NULL != pstcChCfg) && + (pstcChCfg->u8Sequence <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32ChannelSel = pstcChCfg->u32Channel & ADC1_CH_ALL; + if (ADC_SEQ_A == pstcChCfg->u8Sequence) + { + ADCx->CHSELRA0 |= (uint16_t)u32ChannelSel; + ADCx->CHSELRA1 |= (uint16_t)(u32ChannelSel >> 16u); + } + else + { + ADCx->CHSELRB0 |= (uint16_t)u32ChannelSel; + ADCx->CHSELRB1 |= (uint16_t)(u32ChannelSel >> 16u); + } + } + else + { + u32ChannelSel = pstcChCfg->u32Channel & ADC2_CH_ALL; + if (ADC_SEQ_A == pstcChCfg->u8Sequence) + { + ADCx->CHSELRA0 |= (uint16_t)u32ChannelSel; + } + else + { + ADCx->CHSELRB0 |= (uint16_t)u32ChannelSel; + } + } + + /* Set sampling time */ + i = 0u; + j = 0u; + io8Sstr = &(ADCx->SSTR0); + while (0u != u32ChannelSel) + { + if (u32ChannelSel & 0x1ul) + { + io8Sstr[i] = pstcChCfg->pu8SampTime[j++]; + } + u32ChannelSel >>= 1u; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete ADC channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s) you want to delete. + ** \arg ADC1_CH0 ~ ADC1_CH16 + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note You can use this function to delete ADC channel(s) + ** and then set the corresponding pin(s) of the channel(s) + ** to the other mode you need in your application. + ** + ******************************************************************************/ +en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->CHSELRA0 &= (uint16_t)(~u16ChSelR0); + ADCx->CHSELRB0 &= (uint16_t)(~u16ChSelR0); + + if (M4_ADC1 == ADCx) + { + ADCx->CHSELRA1 &= (uint16_t)(~u16ChSelR1); + ADCx->CHSELRB1 &= (uint16_t)(~u16ChSelR1); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC interrupt configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence to be configured. + ** + ** \param [in] enState Enable or Disable sequence conversion done interrupt. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, + uint8_t u8Seq, + en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8Msk = 0u; + + if ((NULL != ADCx) && (u8Seq <= ADC_SEQ_B)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + u8Msk = (uint8_t)(0x1ul << u8Seq); + ADCx->ISR &= (uint8_t)(~u8Msk); + + if (Enable == enState) + { + ADCx->ICR |= u8Msk; + } + else + { + ADCx->ICR &= (uint8_t)(~u8Msk); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC average conversion configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enAvgCnt Average after enAvgCnt conversions. + ** See @ref en_adc_avcnt_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_AVCNT(enAvgCnt)); + + ADCx->CR0_f.AVCNT = enAvgCnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Add average channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s), which will be set as average channel(s). + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note The channel must first be configured as an analog channel + ** by function ADC_AddAdcChannel. + ** + ******************************************************************************/ +en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16AvgChR0; + uint16_t u16AvgChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel &= ADC1_CH_ALL; + } + else + { + u32Channel &= ADC2_CH_ALL; + } + + u16AvgChR0 = (uint16_t)u32Channel; + u16AvgChR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AVCHSELR0 |= u16AvgChR0; + if (M4_ADC1 == ADCx) + { + ADCx->AVCHSELR1 |= u16AvgChR1; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete average channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The average channel(s) which you want to delete. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16AvgChR0; + uint16_t u16AvgChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16AvgChR0 = (uint16_t)u32Channel; + u16AvgChR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AVCHSELR0 &= (uint16_t)(~u16AvgChR0); + if (M4_ADC1 == ADCx) + { + ADCx->AVCHSELR1 &= (uint16_t)(~u16AvgChR1); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC AWD(analog watch dog) configuration. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] pstcAwdCfg Pointer to the configuration structure. + ** See @ref stc_adc_awd_cfg_t for details. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != ADCx) && (NULL != pstcAwdCfg)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_ADC_AWDMD(pstcAwdCfg->enAwdmd)); + DDL_ASSERT(IS_ADC_AWDSS(pstcAwdCfg->enAwdss)); + + ADCx->AWDCR_f.AWDEN = AdcAwd_Disable; + ADCx->AWDCR_f.AWDIEN = AdcAwdInt_Disable; + ADCx->AWDCR_f.AWDMD = pstcAwdCfg->enAwdmd; + ADCx->AWDCR_f.AWDSS = pstcAwdCfg->enAwdss; + + ADCx->AWDDR0 = pstcAwdCfg->u16AwdDr0; + ADCx->AWDDR1 = pstcAwdCfg->u16AwdDr1; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC AWD(analog watch dog). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enState Enable or disable AWD. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + ADCx->AWDCR_f.AWDEN = enState; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable ADC AWD(analog watch dog) interrupt. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] enState Enable or disable AWD interrupt. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + ADCx->AWDCR_f.AWDIEN = enState; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Add AWD channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The channel(s), which will be set as AWD channel(s). + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note The channel must first be configured as an analog channel + ** by function ADC_AddAdcChannel. + ** + ******************************************************************************/ +en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel &= ADC1_CH_ALL; + } + else + { + u32Channel &= ADC2_CH_ALL; + } + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AWDCHSR0 |= u16ChSelR0; + if (M4_ADC1 == ADCx) + { + ADCx->AWDCHSR1 |= u16ChSelR1; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Delete AWD channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32Channel The AWD channel(s) which you are going to delete. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel) +{ + en_result_t enRet = ErrorInvalidParameter; + uint16_t u16ChSelR0; + uint16_t u16ChSelR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChSelR0 = (uint16_t)u32Channel; + u16ChSelR1 = (uint16_t)(u32Channel >> 16u); + + ADCx->AWDCHSR0 &= (uint16_t)(~u16ChSelR0); + if (M4_ADC1 == ADCx) + { + ADCx->AWDCHSR1 &= (uint16_t)(~u16ChSelR1); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief ADC programmable gain amplifier(PGA) configuration. + ** + ** \param [in] enFactor PGA gain factor. + ** \param [in] enNegativeIn PGA negative input select. + ** + ** \retval None. + ** + ** \note Only ADC1 has PGA. + ** + ******************************************************************************/ +void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn) +{ + DDL_ASSERT(IS_ADC_PGA_FACTOR(enFactor)); + DDL_ASSERT(IS_ADC_PGA_NEGATIVE(enNegativeIn)); + + M4_ADC1->PGAGSR_f.GAIN = enFactor; + M4_ADC1->PGAINSR1_f.PGAVSSEN = enNegativeIn; +} + +/** + ******************************************************************************* + ** \brief Enable or disable PGA. + ** + ** \param [in] enState Enable or disable PGA. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_PgaCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (Enable == enState) + { + M4_ADC1->PGACR_f.PGACTL = AdcPgaCtl_Amplify; + } + else + { + M4_ADC1->PGACR_f.PGACTL = AdcPgaCtl_Invalid; + } +} + +/** + ******************************************************************************* + ** \brief Add PGA channel(s). + ** + ** \param[in] u32Channel The channel(s), which you want to gain. + ** + ** \retval None. + ** + ** \note Only ADC1 has PGA. The channel must first + ** be configured as an analog channel + ** by function ADC_AddAdcChannel + ** + ******************************************************************************/ +void ADC_AddPgaChannel(uint32_t u32Channel) +{ + M4_ADC1->PGAINSR0 |= ((uint16_t)(u32Channel & PGA_CH_ALL)); +} + +/** + ******************************************************************************* + ** \brief Delete PGA channel(s). + ** + ** \param[in] u32Channel The PGA channel(s) which will be deleted. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_DelPgaChannel(uint32_t u32Channel) +{ + M4_ADC1->PGAINSR0 &= (uint16_t)(~u32Channel); +} + +/** + ******************************************************************************* + ** \brief ADC sync mode configuration. + ** + ** \param [in] enMode Synchronous mode types. + ** \param [in] u8TrgDelay ADC2 trigger delay time. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay) +{ + DDL_ASSERT(IS_ADC_SYNC_MODE(enMode)); + + /* Disable synchronous mode first. */ + M4_ADC1->SYNCCR_f.SYNCEN = AdcSync_Disable; + + M4_ADC1->SYNCCR_f.SYNCMD = enMode; + M4_ADC1->SYNCCR_f.SYNCDLY = u8TrgDelay; +} + +/** + ******************************************************************************* + ** \brief Enable or disable sync mode. + ** + ** \param [in] enState Enable or disable sync mode. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_SyncCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + M4_ADC1->SYNCCR_f.SYNCEN = enState; +} + +/** + ******************************************************************************* + ** \brief Start an ADC conversion. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ** \note Software startup only support sequence A. + ** + ******************************************************************************/ +en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->STR = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop an ADC conversion and clear flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Timeout. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32TimeCount = 0u; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + enRet = Ok; + /* Make sure the ADC is really stopped. */ + while (ADCx->STR == 1u) + { + /* Stop ADC conversion. */ + ADCx->STR = 0u; + if (++u32TimeCount > 10000u) + { + enRet = ErrorTimeout; + break; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the conversion status flag. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to get + ** it's conversion status flag. + ** + ** \retval Set ADC converted done. + ** \retval Reset ADC is converting or parameter error. + ** + ******************************************************************************/ +en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq) +{ + en_flag_status_t enFlag = Reset; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (ADCx->ISR & ((uint8_t)(0x1ul << u8Seq))) + { + enFlag = Set; + } + + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear conversion status flag of sequence A or sequence B. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8Seq The sequence which you want to clear + ** it's conversion status flag. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq) +{ + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->ISR &= (uint8_t)(~(0x1ul << u8Seq)); + } +} + +/** + ******************************************************************************* + ** \brief ADC start sequence A, check it's EOC status and get the data. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [out] pu16AdcData The address to store ADC value. + ** The location of the data store depends on + ** the parameter u8Length. + ** u8Length >= ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + ** all of the ADC data regs will be read: + ** pu16AdcData[0] = data of Channel 0, + ** pu16AdcData[1] = data of Channel 1, + ** pu16AdcData[2] = data of Channel 2, + ** ... + ** u8Length < ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + ** only the data of the enabled channles will be read: + ** pu16AdcData[0] = data of the 1st enabled channel, + ** pu16AdcData[1] = data of the 2nd enabled channel, + ** pu16AdcData[2] = data of the 3rd enabled channel, + ** ... + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Timeout. + ** \retval OperationInProgress ADC is converting. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, + uint16_t *pu16AdcData, + uint8_t u8Length, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8AllDataLength = 0u; + uint32_t u32Channel = 0u; + uint32_t u32AdcTimeout = 0u; + __IO uint32_t u32TimeCount = 0u; + + if ((NULL != ADCx) && (NULL != pu16AdcData) && (0u != u8Length)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + if (u8Length >= ADC1_CH_COUNT) + { + u8AllDataLength = ADC1_CH_COUNT; + } + else + { + u32Channel = (uint32_t)ADCx->CHSELRA1; + u32Channel <<= 16u; + u32Channel |= (uint32_t)ADCx->CHSELRA0; + } + } + else + { + if (u8Length >= ADC2_CH_COUNT) + { + u8AllDataLength = ADC2_CH_COUNT; + } + else + { + u32Channel = (uint32_t)M4_ADC1->CHSELRA0; + } + } + + /* Start ADC conversion. */ + ADCx->STR = (uint8_t)0x01; + + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32AdcTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32AdcTimeout) + { + if (ADCx->ISR_f.EOCAF) + { + /* Get ADC data. */ + if (u8AllDataLength) + { + ADC_ReadAllData(ADCx, pu16AdcData, u8AllDataLength); + } + else + { + ADC_GetChData(ADCx, u32Channel, pu16AdcData, u8Length); + } + + /* Clear sequence A flag. */ + ADCx->ISR_f.EOCAF = 0u; + enRet = Ok; + break; + } + u32TimeCount++; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reading all data regs of an ADC. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [out] pu16AdcData The address where the data will be stored. + ** pu16AdcData[0] = data of Channel 0, + ** pu16AdcData[1] = data of Channel 1, + ** pu16AdcData[2] = data of Channel 2, + ** ... + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + if (((M4_ADC1 == ADCx) && (u8Length >= ADC1_CH_COUNT)) || + ((M4_ADC2 == ADCx) && (u8Length >= ADC2_CH_COUNT))) + { + ADC_ReadAllData(ADCx, pu16AdcData, u8Length); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reading the data of the specified channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base + ** \arg M4_ADC1 ADC unit 1 instance register base + ** \arg M4_ADC2 ADC unit 2 instance register base + ** + ** \param [in] u32TargetCh The specified channel(s) + ** + ** \param [out] pu16AdcData The address where the data will be stored. + ** pu16AdcData[0] = data of the 1st enabled channel, + ** pu16AdcData[1] = data of the 2nd enabled channel, + ** pu16AdcData[2] = data of the 3rd enabled channel, + ** eg. u32TargetCh = 1001b + ** pu16AdcData[0] = Channel 0's data, + ** pu16AdcData[1] = Channel 3's data, + ** + ** \param [in] u8Length The length of the ADC data to be read. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, + uint32_t u32TargetCh, + uint16_t *pu16AdcData, + uint8_t u8Length) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t j; + uint32_t u32Channel; + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + if ((NULL != ADCx) && (NULL != pu16AdcData) && (0u != u8Length)) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32Channel = u32TargetCh & ADC1_CH_ALL; + } + else + { + u32Channel = u32TargetCh & ADC2_CH_ALL; + } + + i = 0u; + j = 0u; + while ((0u != u32Channel) && (0u != u8Length)) + { + if (0u != (u32Channel & 0x1ul)) + { + pu16AdcData[j] = pu16DataReg[i]; + j++; + u8Length--; + } + + u32Channel >>= 1u; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the value of a specified channel via channel index. + ** + ** \param [in] ADCx Pointer to ADC instance register base + ** \arg M4_ADC1 ADC unit 1 instance register base + ** \arg M4_ADC2 ADC unit 2 instance register base + ** + ** \param [in] u8ChIndex The index of the specified channel. + ** u8ChIndex < ADC1_CH_COUNT while ADCx == M4_ADC1; + ** u8ChIndex < ADC2_CH_COUNT while ADCx == M4_ADC2. + ** + ** \retval An uint16_t value -- the ADC value of the specified channel. + ** + ******************************************************************************/ +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex) +{ + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + return pu16DataReg[u8ChIndex]; +} + +/** + ******************************************************************************* + ** \brief Get all AWD channels status flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval u32AwdFlag 0 -- No ADC channel meets AWD comparison conditions. + ** !0 -- The bit value of the channel that satisfies the + ** AWD condition is 1. + ** + ******************************************************************************/ +uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx) +{ + uint32_t u32AwdFlag; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + u32AwdFlag = ADCx->AWDSR1; + u32AwdFlag <<= 16u; + u32AwdFlag |= ADCx->AWDSR0; + } + else + { + u32AwdFlag = ADCx->AWDSR0; + } + + return u32AwdFlag; +} + +/** + ******************************************************************************* + ** \brief Clear all AWD channels status flags + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx) +{ + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + ADCx->AWDSR0 = 0u; + if (M4_ADC1 == ADCx) + { + ADCx->AWDSR0 = 0u; + ADCx->AWDSR1 = 0u; + } + } +} + +/** + ******************************************************************************* + ** \brief Clear AWD specified channels status flags. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32AwdCh The channel(s) which you want to clear it's flag(s). + ** + ** \retval None. + ** + ******************************************************************************/ +void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh) +{ + uint16_t u16ChR0; + uint16_t u16ChR1; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + u16ChR0 = (uint16_t)u32AwdCh; + u16ChR1 = (uint16_t)(u32AwdCh >> 16u); + + ADCx->AWDSR0 &= (uint16_t)(~u16ChR0); + if (M4_ADC1 == ADCx) + { + ADCx->AWDSR1 &= (uint16_t)(~u16ChR1); + } + } +} + +/** + ******************************************************************************* + ** \brief Remap an ADC pin to channel(s). + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u32DestChannel Destination channel(s). + ** + ** \param [in] u8AdcPin ADC pin number. + ** + ** \retval ErrorInvalidParameter Parameter error. + ** \retval Ok No error occurred. + ** + ******************************************************************************/ +en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, + uint32_t u32DestChannel, + uint8_t u8AdcPin) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t i; + uint8_t u8OffsetReg; + uint8_t u8ChPos; + uint16_t u16AdcPin = u8AdcPin; + __IO uint16_t *io16Chmuxr = NULL; + + if (NULL != ADCx) + { + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + enRet = Ok; + if (M4_ADC1 == ADCx) + { + if (u16AdcPin <= ADC1_IN15) + { + u32DestChannel &= ADC1_PIN_MASK_ALL; + } + else + { + enRet = ErrorInvalidParameter; + } + } + else + { + if ((u16AdcPin > ADC12_IN4) && (u16AdcPin < ADC12_IN11)) + { + u16AdcPin -= 4u; + u32DestChannel &= ADC2_PIN_MASK_ALL; + } + else + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + i = 0u; + while (0u != u32DestChannel) + { + if (u32DestChannel & 0x1ul) + { + u8OffsetReg = i / 4u; + u8ChPos = (i % 4u) * 4u; + io16Chmuxr = &(ADCx->CHMUXR0) + u8OffsetReg; + *io16Chmuxr &= (uint16_t)(~(0xFul << u8ChPos)); + *io16Chmuxr |= (uint16_t)(u16AdcPin << u8ChPos); + } + + u32DestChannel >>= 1u; + i++; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the number of the pin corresponding to the specified channel. + ** + ** \param [in] ADCx Pointer to ADC instance register base. + ** \arg M4_ADC1 ADC unit 1 instance register base. + ** \arg M4_ADC2 ADC unit 2 instance register base. + ** + ** \param [in] u8ChIndex This channel that you want to get its pin number. + ** + ** \retval [0, 15] The correct ADC pin number. + ** \retval [0xFF] The invalid ADC pin number. + ** + ******************************************************************************/ +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex) +{ + uint8_t u8OffsetPin; + uint8_t u8OffsetReg; + uint8_t u8ChPos; + uint8_t u8AdcPin = ADC_PIN_INVALID; + __IO const uint16_t *io16Chmuxr = NULL; + + DDL_ASSERT(IS_ADC_PERIPH(ADCx)); + + if (M4_ADC1 == ADCx) + { + DDL_ASSERT(IS_ADC1_CH_INDEX(u8ChIndex)); + u8OffsetPin = 0u; + } + else + { + DDL_ASSERT(IS_ADC2_CH_INDEX(u8ChIndex)); + u8OffsetPin = 4u; + } + + u8OffsetReg = u8ChIndex / 4u; + u8ChPos = (u8ChIndex % 4u) * 4u; + io16Chmuxr = &(ADCx->CHMUXR0) + u8OffsetReg; + u8AdcPin = (uint8_t)((*io16Chmuxr >> u8ChPos) & ((uint16_t)0xF)); + u8AdcPin += u8OffsetPin; + + return u8AdcPin; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Read all data of an ADC. pu16AdcData[0] = DR0, pu16AdcData[1] = DR1, ... + ** + ******************************************************************************/ +static void ADC_ReadAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length) +{ + uint8_t i; + __IO const uint16_t *pu16DataReg = &(ADCx->DR0); + + for (i = 0u; i < u8Length; i++) + { + pu16AdcData[i] = pu16DataReg[i]; + } +} + +//@} // AdcGroup + +#endif /* DDL_ADC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_aes.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_aes.c new file mode 100644 index 0000000000..d549d30a87 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_aes.c @@ -0,0 +1,311 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_aes.c + ** + ** A detailed description is available at + ** @link AesGroup Aes description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Aes. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_aes.h" +#include "hc32f460_utility.h" + +#if (DDL_AES_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup AesGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* AES block length in bytes is 16. */ +#define AES_BLOCK_LEN ((uint8_t)16) + +/* Each encryption operation takes 440 system clock cycles. */ +#define AES_ENCRYPT_TIMEOUT (440u) + +/* Each decryption operation takes 580 system clock cycles. */ +#define AES_DECRYPT_TIMEOUT (580u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8SrcData); +static void AES_ReadData(uint8_t *pu8Dest); +static void AES_WriteKey(const uint8_t *pu8Key); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief AES128 encryption(ECB mode). + ** + ** \param [in] pu8Plaintext Pointer to plaintext(the source data which will be encrypted) + ** + ** \param [in] u32PlaintextSize Length of plaintext in bytes. + ** + ** \param [in] pu8Key Pointer to the AES key. + ** + ** \param [out] pu8Ciphertext The destination address to store the result of the encryption. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout AES works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t AES_Encrypt(const uint8_t *pu8Plaintext, + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t *pu8Ciphertext) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32BlockOffset; + uint32_t u32Index; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8Plaintext) && + (0u != u32PlaintextSize) && + (NULL != pu8Key) && + (NULL != pu8Ciphertext) && + (0u == (u32PlaintextSize & 0xFu)) && /* u32PlaintextSize % AES_BLOCK_LEN */ + (0u == ((uint32_t)pu8Plaintext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */ + (0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */ + (0u == ((uint32_t)pu8Ciphertext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */ + { + /* Write the key to the register. */ + AES_WriteKey(pu8Key); + u32BlockOffset = 0u; + while (0u != u32PlaintextSize) + { + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + + /* Write data. */ + u32Index = u32BlockOffset * AES_BLOCK_LEN; + AES_WriteData(&pu8Plaintext[u32Index]); + + /* Set AES encrypt. */ + bM4_AES_CR_MODE = 0u; + + /* Start AES calculating. */ + bM4_AES_CR_START = 1u; + + enRet = ErrorTimeout; + u32TimeCount = 0u; + while (u32TimeCount < AES_ENCRYPT_TIMEOUT) + { + if (bM4_AES_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (enRet == ErrorTimeout) + { + break; + } + + AES_ReadData(&pu8Ciphertext[u32Index]); + u32PlaintextSize -= AES_BLOCK_LEN; + u32BlockOffset++; + } + + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief AES128 decryption(ECB mode). + ** + ** \param [in] pu8Ciphertext Pointer to ciphertext(the source data which will be decrypted) + ** + ** \param [in] u32CiphertextSize Length of ciphertext in bytes. + ** + ** \param [in] pu8Key Pointer to the AES key. + ** + ** \param [out] pu8Plaintext The destination address to store the result of the decryption. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout AES works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t AES_Decrypt(const uint8_t *pu8Ciphertext, + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t *pu8Plaintext) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32BlockOffset; + uint32_t u32Index; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8Ciphertext) && + (0u != u32CiphertextSize) && + (NULL != pu8Key) && + (NULL != pu8Plaintext) && + (0u == (u32CiphertextSize & 0xFu)) && /* u32CiphertextSize % AES_BLOCK_LEN */ + (0u == ((uint32_t)pu8Ciphertext & 0x3u)) && /* (uint32_t)pu8Ciphertext % 4u */ + (0u == ((uint32_t)pu8Key & 0x3u)) && /* (uint32_t)pu8Key % 4u */ + (0u == ((uint32_t)pu8Plaintext & 0x3u))) /* (uint32_t)pu8Plaintext % 4u */ + { + /* Write the key to the register. */ + AES_WriteKey(pu8Key); + u32BlockOffset = 0u; + while (0u != u32CiphertextSize) + { + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + + /* Write data. */ + u32Index = u32BlockOffset * AES_BLOCK_LEN; + AES_WriteData(&pu8Ciphertext[u32Index]); + + /* Set AES decrypt. */ + bM4_AES_CR_MODE = 1u; + + /* Start AES calculating. */ + bM4_AES_CR_START = 1u; + + enRet = ErrorTimeout; + u32TimeCount = 0u; + while (u32TimeCount < AES_DECRYPT_TIMEOUT) + { + if (bM4_AES_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (enRet == ErrorTimeout) + { + break; + } + + AES_ReadData(&pu8Plaintext[u32Index]); + u32CiphertextSize -= AES_BLOCK_LEN; + u32BlockOffset++; + } + + /* Stop AES calculating. */ + bM4_AES_CR_START = 0u; + } + + return enRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Writes the input buffer in data register. + ** + ** \param [in] pu8SrcData Pointer to source data buffer. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + uint32_t u32SrcAddr = (uint32_t)pu8SrcData; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + + for (i = 0u; i < 4u; i++) + { + *(__IO uint32_t *)u32DrAddr = *(uint32_t*)u32SrcAddr; + u32SrcAddr += 4u; + u32DrAddr += 4u; + } +} + +/** + ******************************************************************************* + ** \brief Reads the from data register. + ** + ** \param [out] pu8Dest Pointer to the destination buffer. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_ReadData(uint8_t *pu8Dest) +{ + uint8_t i; + uint32_t u32DestAddr = (uint32_t)pu8Dest; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + + for (i = 0u; i < 4u; i++) + { + *(uint32_t*)u32DestAddr = *(__IO uint32_t *)u32DrAddr; + u32DestAddr += 4u; + u32DrAddr += 4u; + } +} + +/** + ******************************************************************************* + ** \brief Writes the input buffer in key register. + ** + ** \param [in] pu8Key Pointer to AES key. + ** + ** \retval None. + ** + ******************************************************************************/ +static void AES_WriteKey(const uint8_t *pu8Key) +{ + uint8_t i; + uint32_t u32SrcKeyAddr = (uint32_t)pu8Key; + uint32_t u32KeyAddr = (uint32_t)&(M4_AES->KR0); + + for (i = 0u; i < 4u; i++) + { + *(__IO uint32_t *)u32KeyAddr = *(uint32_t*)u32SrcKeyAddr; + u32SrcKeyAddr += 4u; + u32KeyAddr += 4u; + } +} + +//@} // AesGroup + +#endif /* DDL_AES_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_can.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_can.c new file mode 100644 index 0000000000..ff08fe1181 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_can.c @@ -0,0 +1,532 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_can.c + ** + ** A detailed description is available at + ** @link CanGroup CAN description @endlink + ** + ** - 2018-12-13 CDT First version for Device Driver Library of CAN. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_can.h" +#include "hc32f460_utility.h" + +#if (DDL_CAN_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CanGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CAN_RESET_ENABLE() (M4_CAN->CFG_STAT_f.RESET = 1u) +#define CAN_RESET_DISABLE() \ +do{ \ + do{ \ + M4_CAN->CFG_STAT_f.RESET = 0u; \ +}while(M4_CAN->CFG_STAT_f.RESET); \ +}while(0) + +#define CAN_RW_MEM32(addr) (*(__IO uint32_t *)(addr)) + +#define CAN_ACF_ID_REG_SEL ((uint8_t)0x00u) +#define CAN_ACF_MASK_REG_SEL ((uint8_t)0x01u) + + +/*! Parameter validity check for CAN Mode \a CanMode. */ +#define IS_CAN_MODE_VALID(CanMode) \ +( (CanExternalLoopBackMode == (CanMode)) || \ + (CanInternalLoopBackMode == (CanMode)) || \ + (CanTxSignalPrimaryMode == (CanMode)) || \ + (CanTxSignalSecondaryMode == (CanMode)) || \ + (CanListenOnlyMode == (CanMode)) \ +) + +/*! Parameter validity check for CAN Tx Cmd \a TxCmd. */ +#define IS_TX_CMD_VALID(TxCmd) \ +( (CanPTBTxCmd == (TxCmd)) || \ + (CanPTBTxAbortCmd == (TxCmd)) || \ + (CanSTBTxOneCmd == (TxCmd)) || \ + (CanSTBTxAllCmd == (TxCmd)) || \ + (CanSTBTxAbortCmd == (TxCmd)) \ +) + +/*! Parameter validity check for CAN status \a enCanStatus. */ +#define IS_CAN_STATUS_VALID(enCanStatus) \ +( (CanRxActive == (enCanStatus)) || \ + (CanTxActive == (enCanStatus)) || \ + (CanBusoff == (enCanStatus)) \ +) + +/*! Parameter validity check for CAN Irq type \a enCanIrqType. */ +#define IS_CAN_IRQ_TYPE_VALID(enCanIrqType) \ +( (CanRxIrqEn == (enCanIrqType)) || \ + (CanRxOverIrqEn == (enCanIrqType)) || \ + (CanRxBufFullIrqEn == (enCanIrqType)) || \ + (CanRxBufAlmostFullIrqEn == (enCanIrqType)) || \ + (CanTxPrimaryIrqEn == (enCanIrqType)) || \ + (CanTxSecondaryIrqEn == (enCanIrqType)) || \ + (CanErrorIrqEn == (enCanIrqType)) || \ + (CanErrorPassiveIrqEn == (enCanIrqType)) || \ + (CanArbiLostIrqEn == (enCanIrqType)) || \ + (CanBusErrorIrqEn == (enCanIrqType)) \ +) + +/*! Parameter validity check for CAN Irq flag type \a enCanIrqFLg. */ +#define IS_CAN_IRQ_FLAG_VALID(enCanIrqFLg) \ +( (CanTxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxIrqFlg == (enCanIrqFLg)) || \ + (CanRxOverIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufFullIrqFlg == (enCanIrqFLg)) || \ + (CanRxBufAlmostFullIrqFlg == (enCanIrqFLg)) || \ + (CanTxPrimaryIrqFlg == (enCanIrqFLg)) || \ + (CanTxSecondaryIrqFlg == (enCanIrqFLg)) || \ + (CanErrorIrqFlg == (enCanIrqFLg)) || \ + (CanAbortIrqFlg == (enCanIrqFLg)) || \ + (CanErrorWarningIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassivenodeIrqFlg == (enCanIrqFLg)) || \ + (CanErrorPassiveIrqFlg == (enCanIrqFLg)) || \ + (CanArbiLostIrqFlg == (enCanIrqFLg)) || \ + (CanBusErrorIrqFlg == (enCanIrqFLg)) \ +) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the can base functions + ** + ** \param [in] pstcCanInitCfg The can initial config struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_Init(stc_can_init_config_t *pstcCanInitCfg) +{ + if (NULL != pstcCanInitCfg) + { + M4_CAN->RCTRL_f.SACK = pstcCanInitCfg->enCanSAck; + M4_CAN->TCTRL_f.TSMODE = pstcCanInitCfg->enCanSTBMode; + M4_CAN->RCTRL_f.RBALL = pstcCanInitCfg->enCanRxBufAll; + M4_CAN->RCTRL_f.ROM = pstcCanInitCfg->enCanRxBufMode; + + M4_CAN->RTIE = 0x00u; + + CAN_RESET_ENABLE(); + + M4_CAN->BT_f.PRESC = pstcCanInitCfg->stcCanBt.PRESC; + M4_CAN->BT_f.SEG_1 = pstcCanInitCfg->stcCanBt.SEG_1; + M4_CAN->BT_f.SEG_2 = pstcCanInitCfg->stcCanBt.SEG_2; + M4_CAN->BT_f.SJW = pstcCanInitCfg->stcCanBt.SJW; + + M4_CAN->LIMIT_f.AFWL = pstcCanInitCfg->stcWarningLimit.CanWarningLimitVal; + M4_CAN->LIMIT_f.EWL = pstcCanInitCfg->stcWarningLimit.CanErrorWarningLimitVal; + + CAN_RESET_DISABLE(); + } +} + +/** + ******************************************************************************* + ** \brief De-Init (RESET CAN register) + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_DeInit(void) +{ + CAN_RESET_ENABLE(); +} + +/** + ******************************************************************************* + ** \brief Configures the can Mode + ** + ** \param [in] enMode The can mode enum. @ref en_can_mode_t + ** \param [in] enNewState The new state of the can filter chanel. + ** \arg Enable Enable filter. + ** \arg Disable Disable filter. + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_ModeConfig(en_can_mode_t enMode, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_MODE_VALID(enMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(CanListenOnlyMode == enMode) + { + M4_CAN->TCMD_f.LOM = enNewState; + }else + { + if(Enable == enNewState) + { + M4_CAN->CFG_STAT |= enMode; + }else + { + M4_CAN->CFG_STAT &= ~enMode; + } + } + +} + + +/** + ******************************************************************************* + ** \brief Configures the can acceptance filter + ** + ** \param [in] pstcFilter The can filter config struct. + ** @ref stc_can_filter_t + ** \param [in] enNewState The new state of the can filter chanel. + ** \arg Enable Enable filter. + ** \arg Disable Disable filter. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_FilterConfig(const stc_can_filter_t *pstcFilter, en_functional_state_t enNewState) +{ + if(NULL != pstcFilter) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CAN_RESET_ENABLE(); + + //<ACFCTRL_f.ACFADR = pstcFilter->enFilterSel; + + //<ACFCTRL_f.SELMASK = CAN_ACF_ID_REG_SEL; + M4_CAN->ACF = pstcFilter->u32CODE; + + //<ACFCTRL_f.SELMASK = CAN_ACF_MASK_REG_SEL; + M4_CAN->ACF = pstcFilter->u32MASK; + + //<ACF_f.AIDEE = ((pstcFilter->enAcfFormat >> 1ul) & 0x01u); + M4_CAN->ACF_f.AIDE = (pstcFilter->enAcfFormat & 0x01ul); + + if(Enable == enNewState) + { + M4_CAN->ACFEN |= (uint8_t)(1ul << pstcFilter->enFilterSel); + }else + { + M4_CAN->ACFEN &= (uint8_t)(~(1ul << (pstcFilter->enFilterSel))); + } + + CAN_RESET_DISABLE(); + } +} + + +/** + ******************************************************************************* + ** \brief Configures the can Tx frame set + ** + ** \param [in] pstcTxFrame The can Tx frame struct. + ** @ref stc_can_txframe_t + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_SetFrame(stc_can_txframe_t *pstcTxFrame) +{ + uint32_t u32TBUFAddr; + + if(NULL != pstcTxFrame) + { + u32TBUFAddr = (uint32_t)&M4_CAN->TBUF; + M4_CAN->TCMD_f.TBSEL = pstcTxFrame->enBufferSel; + CAN_RW_MEM32(u32TBUFAddr) = pstcTxFrame->TBUF32_0; + CAN_RW_MEM32(u32TBUFAddr+4) = pstcTxFrame->TBUF32_1; + CAN_RW_MEM32(u32TBUFAddr+8) = pstcTxFrame->TBUF32_2[0]; + CAN_RW_MEM32(u32TBUFAddr+12) = pstcTxFrame->TBUF32_2[1]; + + if(CanSTBSel == pstcTxFrame->enBufferSel) + { + M4_CAN->TCTRL_f.TSNEXT = Enable; + } + } +} + +/** + ******************************************************************************* + ** \brief Configures the can Tx Command + ** + ** \param [in] enTxCmd The can Tx Command. + ** + ** \retval Can Tx buffer status @ref en_can_tx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_tx_buf_status_t CAN_TransmitCmd(en_can_tx_cmd_t enTxCmd) +{ + DDL_ASSERT(IS_TX_CMD_VALID(enTxCmd)); + + M4_CAN->TCMD |= enTxCmd; + + return (en_can_tx_buf_status_t)M4_CAN->TCTRL_f.TSSTAT; + +} + +/** + ******************************************************************************* + ** \brief Configures the can Rx frame + ** + ** \param [in] pstcRxFrame The can Rx frame. + ** @ref stc_can_rxframe_t + ** \retval Can rx buffer status @ref en_can_rx_buf_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_can_rx_buf_status_t CAN_Receive(stc_can_rxframe_t *pstcRxFrame) +{ + uint32_t u32RBUFAddr; + + if(NULL != pstcRxFrame) + { + u32RBUFAddr = (uint32_t)&M4_CAN->RBUF; + pstcRxFrame->RBUF32_0 = CAN_RW_MEM32(u32RBUFAddr); + pstcRxFrame->RBUF32_1 = CAN_RW_MEM32(u32RBUFAddr+4); + pstcRxFrame->RBUF32_2[0] = CAN_RW_MEM32(u32RBUFAddr+8); + pstcRxFrame->RBUF32_2[1] = CAN_RW_MEM32(u32RBUFAddr+12); + + M4_CAN->RCTRL_f.RREL = 1u; + } + return (en_can_rx_buf_status_t)M4_CAN->RCTRL_f.RSSTAT; +} + + +/** + ******************************************************************************* + ** \brief Get the can Error Status + ** + ** \param None + ** + ** \retval en_can_error_t The can error status + ** + ** \note None + ** + ******************************************************************************/ +en_can_error_t CAN_ErrorStatusGet(void) +{ + en_can_error_t enRet = UNKOWN_ERROR; + + if(6u > M4_CAN->EALCAP_f.KOER) + { + enRet = (en_can_error_t)M4_CAN->EALCAP_f.KOER; + } + return enRet; + +} + +/** + ******************************************************************************* + ** \brief Get the can Status + ** + ** \param enCanStatus The can status + ** \arg true + ** \arg false + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_StatusGet(en_can_status_t enCanStatus) +{ + bool bRet = false; + DDL_ASSERT(IS_CAN_STATUS_VALID(enCanStatus)); + + if(M4_CAN->CFG_STAT & enCanStatus) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Configures the can Interrupt enable + ** + ** \param [in] enCanIrqType The can interrupt type. + ** \param [in] enNewState The new state of the can interrupt. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqCmd(en_can_irq_type_t enCanIrqType, en_functional_state_t enNewState) +{ + volatile uint32_t *u32pIE; + + DDL_ASSERT(IS_CAN_IRQ_TYPE_VALID(enCanIrqType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if(Enable == enNewState) + { + *u32pIE |= enCanIrqType; + }else + { + *u32pIE &= ~((uint32_t)enCanIrqType); + } + +} + +/** + ******************************************************************************* + ** \brief Get the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt Flag. + ** + ** \retval bool + ** + ** \note None + ** + ******************************************************************************/ +bool CAN_IrqFlgGet(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + bool bRet = false; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + if( *u32pIE & enCanIrqFlgType) + { + bRet = true; + } + return bRet; +} + +/** + ******************************************************************************* + ** \brief Clear the can Interrupt Flag + ** + ** \param [in] enCanIrqFlgType The can interrupt type. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CAN_IrqFlgClr(en_can_irq_flag_type_t enCanIrqFlgType) +{ + volatile uint32_t *u32pIE = NULL; + uint32_t u32IETempMsk = 0xFF2A00FF; + + DDL_ASSERT(IS_CAN_IRQ_FLAG_VALID(enCanIrqFlgType)); + + u32pIE = (volatile uint32_t*)(&M4_CAN->RTIE); + + *u32pIE = (((*u32pIE)&u32IETempMsk) | (uint32_t)enCanIrqFlgType); +} + + +/** + ******************************************************************************* + ** \brief Get the can Rx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_RxErrorCntGet(void) +{ + return M4_CAN->RECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Tx Error Counter + ** + ** \param None + ** + ** \retval Error Counter(0~255) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_TxErrorCntGet(void) +{ + return M4_CAN->TECNT; +} + +/** + ******************************************************************************* + ** \brief Get the can Arbitration lost captrue + ** + ** \param None + ** + ** \retval address(0~31) + ** + ** \note None + ** + ******************************************************************************/ +uint8_t CAN_ArbitrationLostCap(void) +{ + return M4_CAN->EALCAP_f.ALC; +} + + +//@} // CanGroup + +#endif /* DDL_CAN_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_clk.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_clk.c new file mode 100644 index 0000000000..eda867759c --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_clk.c @@ -0,0 +1,1813 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_clk.c + ** + ** A detailed description is available at + ** @link CmuGroup Clock description @endlink + ** + ** - 2018-10-13 CDT First version for Device Driver Library of CMU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_clk.h" +#include "hc32f460_utility.h" + +#if (DDL_CLK_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CmuGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CLK_XTAL_TIMEOUT ((uint16_t)0x1000u) +#define CLK_XTAL32_TIMEOUT ((uint8_t)0x05u) +#define CLK_HRC_TIMEOUT ((uint16_t)0x1000u) +#define CLK_MRC_TIMEOUT ((uint8_t)0x05u) +#define CLK_LRC_TIMEOUT ((uint8_t)0x05u) +#define CLK_MPLL_TIMEOUT ((uint16_t)0x1000u) +#define CLK_UPLL_TIMEOUT ((uint16_t)0x1000u) + +/* TBDs 30us based 200M frequency. */ +#define CLK_FCG_STABLE ((uint16_t)0x200u) +#define CLK_SYSCLK_STABLE ((uint16_t)0x200u) +#define CLK_USBCLK_STABLE ((uint16_t)0x200u) + +#define CLK_PLL_DIV_MIN (2u) +#define CLK_PLL_DIV_MAX (16u) + +#define CLK_PLLQ_DIV_MIN (1u) +#define CLK_PLLQ_DIV_MAX (16u) + +#define CLK_PLLN_MIN (20u) +#define CLK_PLLN_MAX (480u) + +#define CLK_PLLM_MIN (1u) +#define CLK_PLLM_MAX (24u) + +#define CLK_UPLLM_MIN (2u) +#define CLK_UPLLM_MAX (24u) + +#define CLK_PLL_VCO_IN_MIN (1u*1000u*1000u) +#define CLK_PLL_VCO_IN_MAX (24u*1000u*1000u) + +#define CLK_PLL_VCO_OUT_MIN (240u*1000u*1000u) +#define CLK_PLL_VCO_OUT_MAX (480u*1000u*1000u) + +#define ENABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50001u) +#define DISABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50000u) + +#define ENABLE_CLOCK_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa501u) +#define DISABLE_CLOCK_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~1u)))) + +#define ENABLE_CLOCK1_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa502u) +#define DISABLE_CLOCK1_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~2u)))) + + +#define DEFAULT_FCG0 (0xFFFFFAEEul) +#define DEFAULT_FCG1 (0xFFFFFFFFul) +#define DEFAULT_FCG2 (0xFFFFFFFFul) +#define DEFAULT_FCG3 (0xFFFFFFFFul) +#define FCG2_WITHOUT_EMB (0xFFFF7FFFul) + +#define FCG0_OFFSET_FCM (16ul) +#define FCG1_OFFSET_CAN (0ul) +#define FCG1_OFFSET_QSPI (3ul) +#define FCG1_OFFSET_USBFS (8ul) +#define FCG1_OFFSET_SPI1 (16ul) +#define FCG1_OFFSET_SPI2 (17ul) +#define FCG1_OFFSET_SPI3 (18ul) +#define FCG1_OFFSET_SPI4 (19ul) +#define FCG3_OFFSET_ADC1 (0ul) +#define FCG3_OFFSET_ADC2 (1ul) +#define FCG3_OFFSET_DAC (4ul) + +/*! Parameter validity check for XTAL stablization time \a stb. */ +#define IS_XTAL_STB_VALID(stb) \ +( (ClkXtalStbCycle35 <= (stb)) && \ + (ClkXtalStbCycle8163 >= (stb))) + +/*! Parameter validity check for pll source \a src. */ +#define IS_PLL_SOURCE(src) \ +( (ClkPllSrcXTAL == (src)) || \ + (ClkPllSrcHRC == (src))) + +/*! Parameter validity check for mpll div \a pllp, pllr, upll div \a pllp, pllq, pllr*/ +#define IS_PLL_DIV_VALID(pllx) \ +( (CLK_PLL_DIV_MIN <= (pllx)) && \ + (CLK_PLL_DIV_MAX >= (pllx))) + +/*! Parameter validity check for pll div \a pllq. */ +#define IS_PLLQ_DIV_VALID(pllx) \ +( (CLK_PLLQ_DIV_MIN <= (pllx)) && \ + (CLK_PLLQ_DIV_MAX >= (pllx))) + +/*! Parameter validity check for plln \a plln. */ +#define IS_PLLN_VALID(plln) \ +( (CLK_PLLN_MIN <= (plln)) && \ + (CLK_PLLN_MAX >= (plln))) + +/*! Parameter validity check for pllm \a pllm. */ +#define IS_PLLM_VALID(pllm) \ +( (CLK_PLLM_MIN <= (pllm)) && \ + (CLK_PLLM_MAX >= (pllm))) + +/*! Parameter validity check for pllm \a pllm. */ +#define IS_UPLLM_VALID(pllm) \ +( (CLK_UPLLM_MIN <= (pllm)) && \ + (CLK_UPLLM_MAX >= (pllm))) + +/*! Parameter validity check for pllsource/pllm \a vco_in. */ +#define IS_PLL_VCO_IN_VALID(vco_in) \ +( (CLK_PLL_VCO_IN_MIN <= (vco_in)) && \ + (CLK_PLL_VCO_IN_MAX >= (vco_in))) + +/*! Parameter validity check for pllsource/pllm*plln \a vco_out. */ +#define IS_PLL_VCO_OUT_VALID(vco_out) \ +( (CLK_PLL_VCO_OUT_MIN <= (vco_out)) && \ + (CLK_PLL_VCO_OUT_MAX >= (vco_out))) + +/*! Parameter validity check for system clock source \a syssrc. */ +#define IS_SYSCLK_SOURCE(syssrc) \ +( (ClkSysSrcHRC == (syssrc)) || \ + ((ClkSysSrcMRC <= (syssrc)) && \ + (CLKSysSrcMPLL >= (syssrc)))) + +/*! Parameter validity check for usb clock source \a usbsrc. */ +#define IS_USBCLK_SOURCE(usbsrc) \ +( ((ClkUsbSrcSysDiv2 <= (usbsrc)) && \ + (ClkUsbSrcSysDiv4 >= (usbsrc))) || \ + ((ClkUsbSrcMpllp <= (usbsrc)) && \ + (ClkUsbSrcUpllr >= (usbsrc)))) + +/*! Parameter validity check for peripheral(adc/trng/I2S) clock source \a adcsrc. */ +#define IS_PERICLK_SOURCE(adcsrc) \ +( (ClkPeriSrcPclk == (adcsrc)) || \ + ((ClkPeriSrcMpllp <= (adcsrc)) && \ + (ClkPeriSrcUpllr >= (adcsrc)))) + +/*! Parameter validity check for output clock source \a outsrc. */ +#define IS_OUTPUTCLK_SOURCE(outsrc) \ +( (ClkOutputSrcHrc == (outsrc)) || \ + (ClkOutputSrcMrc == (outsrc)) || \ + (ClkOutputSrcLrc == (outsrc)) || \ + (ClkOutputSrcXtal == (outsrc)) || \ + (ClkOutputSrcXtal32 == (outsrc)) || \ + (ClkOutputSrcMpllp == (outsrc)) || \ + (ClkOutputSrcUpllp == (outsrc)) || \ + (ClkOutputSrcMpllq == (outsrc)) || \ + (ClkOutputSrcUpllq == (outsrc)) || \ + (ClkOutputSrcSysclk == (outsrc))) + +/*! Parameter validity check for fcm source \a fcmsrc. */ +#define IS_FCM_SOURCE(fcmsrc) \ +( (ClkFcmSrcXtal == (fcmsrc)) || \ + ((ClkFcmSrcXtal32 <= (fcmsrc)) && \ + (ClkFcmSrcRtcLrc >= (fcmsrc)))) + +/*! Parameter validity check for output clock channel \a outch. */ +#define IS_OUTPUTCLK_CHANNEL(outch) \ +( (ClkOutputCh1 == (outch)) || \ + (ClkOutputCh2 == (outch))) + +/*! Parameter validity check for fcm reference \a ref. */ +#define IS_FCM_REF(ref) \ +( (ClkFcmExtRef == (ref)) || \ + (ClkFcmInterRef == (ref))) + +/*! Parameter validity check for fcm edge \a edge. */ +#define IS_FCM_EDGE(edge) \ +( (ClkFcmEdgeRising == (edge)) || \ + (ClkFcmEdgeFalling == (edge)) || \ + (ClkFcmEdgeBoth == (edge))) + +/*! Parameter validity check for fcm filter clock \a clk. */ +#define IS_FCM_FILTER_CLK(clk) \ +( (ClkFcmFilterClkNone == (clk)) || \ + (ClkFcmFilterClkFcmSrc == (clk)) || \ + (ClkFcmFilterClkFcmSrcDiv4 == (clk)) || \ + (ClkFcmFilterClkFcmSrcDiv16 == (clk))) + +/*! Parameter validity check for fcm abnormal handle \a handle. */ +#define IS_FCM_HANDLE(handle) \ +( (ClkFcmHandleInterrupt == (handle)) || \ + (ClkFcmHandleReset == (handle))) + +/*! Parameter validity check for debug clock division \a div. */ +#define IS_TPIUCLK_DIV_VALID(div) \ +( (ClkTpiuclkDiv1 == (div)) || \ + (ClkTpiuclkDiv2 == (div)) || \ + (ClkTpiuclkDiv4 == (div))) + +/*! Parameter validity check for output clock division \a div. */ +#define IS_OUTPUTCLK_DIV_VALID(div) \ +( (ClkOutputDiv1 == (div)) || \ + ((ClkOutputDiv2 <= (div)) && \ + (ClkOutputDiv128 >= (div)))) + +/*! Parameter validity check for fcm measurement source division \a div. */ +#define IS_FCM_MEASRC_DIV_VALID(div) \ +( (ClkFcmMeaDiv1 == (div)) || \ + (ClkFcmMeaDiv4 == (div)) || \ + (ClkFcmMeaDiv8 == (div)) || \ + (ClkFcmMeaDiv32 == (div))) + +/*! Parameter validity check for internal reference source division \a div. */ +#define IS_FCM_INTREF_DIV_VALID(div) \ +( (ClkFcmIntrefDiv32 == (div)) || \ + (ClkFcmIntrefDiv128 == (div)) || \ + (ClkFcmIntrefDiv1024 == (div)) || \ + (ClkFcmIntrefDiv8192 == (div))) + +/*! Parameter validity check for system clock config \a cfg. */ +#define IS_SYSCLK_CONFIG_VALID(cfg) \ +( ((cfg)->enHclkDiv <= ((cfg)->enPclk1Div)) && \ + ((cfg)->enHclkDiv <= ((cfg)->enPclk3Div)) && \ + ((cfg)->enHclkDiv <= ((cfg)->enPclk4Div)) && \ + ((cfg)->enPclk0Div <= ((cfg)->enPclk1Div)) && \ + ((cfg)->enPclk0Div <= ((cfg)->enPclk3Div)) && \ + (((cfg)->enPclk2Div-(cfg)->enPclk4Div == 3) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 2) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 1) || \ + ((cfg)->enPclk2Div-(cfg)->enPclk4Div == 0) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 1) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 2) || \ + ((cfg)->enPclk4Div-(cfg)->enPclk2Div == 3))) + + +/*! Parameter validity check for clock status \a flag. */ +#define IS_CLK_FLAG(flag) \ +( (ClkFlagHRCRdy == (flag)) || \ + (ClkFlagXTALRdy == (flag)) || \ + (ClkFlagMPLLRdy == (flag)) || \ + (ClkFlagUPLLRdy == (flag)) || \ + (ClkFlagXTALStoppage == (flag))) +/*! Parameter validity check for fcm status \a flag. */ +#define IS_FCM_FLAG(flag) \ +( (ClkFcmFlagOvf == (flag)) || \ + (ClkFcmFlagMendf == (flag)) || \ + (ClkFcmFlagErrf == (flag))) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Configures the external high speed oscillator(XTAL). + ** + ** \param [in] pstcXtalCfg The XTAL configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg) +{ + if(NULL != pstcXtalCfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALCFGR_f.SUPDRV = pstcXtalCfg->enFastStartup; + M4_SYSREG->CMU_XTALCFGR_f.XTALMS = pstcXtalCfg->enMode; + M4_SYSREG->CMU_XTALCFGR_f.XTALDRV = pstcXtalCfg->enDrv; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Configures the XTAL stable time. + ** + ** \param [in] enXtalStb The XTAL stable time. + ** + ** \retval None + ** + ** \note One of the stable clock is 1/8 LRC clock. + ** + ******************************************************************************/ +void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb) +{ + DDL_ASSERT(IS_XTAL_STB_VALID(enXtalStb)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALSTBCR_f.XTALSTB = enXtalStb; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the XTAL stoppage. + ** + ** \param [in] pstcXtalStpCfg The XTAL stoppage configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg) +{ + if(NULL != pstcXtalStpCfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDE = pstcXtalStpCfg->enDetect; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDRIS = pstcXtalStpCfg->enMode; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDRE = pstcXtalStpCfg->enModeReset; + M4_SYSREG->CMU_XTALSTDCR_f.XTALSTDIE = pstcXtalStpCfg->enModeInt; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the XTAL. + ** + ** \param [in] enNewState The new state of the XTAL. + ** \arg Enable Enable XTAL. + ** \arg Disable Disable XTAL. + ** + ** \retval en_result_t + ** + ** \note XTAL can not be stopped if it is used as system clock source or pll + ** clock source. + ** + ******************************************************************************/ +en_result_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0u; + en_flag_status_t status; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcXTAL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else if(ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC) + { + if(0u == M4_SYSREG->CMU_PLLCR_f.MPLLOFF) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTALCR_f.XTALSTP = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagXTALRdy); + timeout++; + }while((timeout < CLK_XTAL_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the external low speed oscillator(XTAL32). + ** + ** \param [in] pstcXtal32Cfg The XTAL32 configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg) +{ + if(NULL != pstcXtal32Cfg) + { + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_XTAL32CFGR_f.XTAL32DRV = pstcXtal32Cfg->enDrv; + M4_SYSREG->CMU_XTAL32NFR_f.XTAL32NF = pstcXtal32Cfg->enFilterMode; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the XTAL32. + ** + ** \param [in] enNewState The new state of the XTAL32. + ** \arg Enable Enable XTAL32. + ** \arg Disable Disable XTAL32. + ** + ** \retval en_result_t + ** + ** \note XTAL32 can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcXTAL32 == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_XTAL32CR_f.XTAL32STP = 1u; + } + } + else + { + M4_SYSREG->CMU_XTAL32CR_f.XTAL32STP = 0u; + do + { + timeout++; + }while(timeout < CLK_XTAL32_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal high speed oscillator(HRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_HrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_HRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the HRC. + ** + ** \param [in] enNewState The new state of the HRC. + ** \arg Enable Enable HRC. + ** \arg Disable Disable HRC. + ** + ** \retval en_result_t + ** + ** \note HRC can not be stopped if it is used as system clock source or pll + ** clock source. + ** + ******************************************************************************/ +en_result_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + en_result_t enRet = Ok; + + ENABLE_CLOCK_REG_WRITE(); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if(Disable == enNewState) + { + if(ClkSysSrcHRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else if(ClkPllSrcHRC == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC) + { + if(0u == M4_SYSREG->CMU_PLLCR_f.MPLLOFF) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_HRCCR_f.HRCSTP = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagHRCRdy); + timeout++; + }while((timeout < CLK_HRC_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal middle speed oscillator(MRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_MrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_MRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the MRC. + ** + ** \param [in] enNewState The new state of the MRC. + ** \arg Enable Enable MRC. + ** \arg Disable Disable MRC. + ** + ** \retval en_result_t + ** + ** \note MRC can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcMRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_MRCCR_f.MRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_MRCCR_f.MRCSTP = 0u; + do + { + timeout++; + }while(timeout < CLK_MRC_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Trim the internal low speed oscillator(LRC). + ** + ** \param [in] trimValue The trim value. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_LrcTrim(int8_t trimValue) +{ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_LRCTRM = trimValue; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the LRC. + ** + ** \param [in] enNewState The new state of the LRC. + ** \arg Enable Enable LRC. + ** \arg Disable Disable LRC. + ** + ** \retval en_result_t + ** + ** \note LRC can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(ClkSysSrcLRC == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_LRCCR_f.LRCSTP = 1u; + } + } + else + { + M4_SYSREG->CMU_LRCCR_f.LRCSTP = 0u; + do + { + timeout++; + }while(timeout < CLK_LRC_TIMEOUT); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Select pll clock source. + ** + ** \param [in] enPllSrc The pll clock source. + ** \arg ClkPllSrcXTAL Select XTAL as pll clock source. + ** \arg ClkPllSrcHRC Select HRC as pll clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetPllSource(en_clk_pll_source_t enPllSrc) +{ + DDL_ASSERT(IS_PLL_SOURCE(enPllSrc)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_PLLCFGR_f.PLLSRC = enPllSrc; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the MPLL. + ** + ** \param [in] pstcMpllCfg The MPLL configures struct. + ** + ** \retval None + ** + ** \note The pllsource/pllm is between 1MHz and 24MHz. + ** The pllsource/pllm*plln is between 240MHz and 480MHz. + ** The maximum of pllsource/pllm*plln/pllp is 200MHz. + ** + ******************************************************************************/ +void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg) +{ +#ifdef __DEBUG + uint32_t vcoIn = 0ul; + uint32_t vcoOut = 0ul; +#endif /* #ifdef __DEBUG */ + + if(NULL != pstcMpllCfg) + { + DDL_ASSERT(IS_PLL_DIV_VALID(pstcMpllCfg->PllpDiv)); + DDL_ASSERT(IS_PLLQ_DIV_VALID(pstcMpllCfg->PllqDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcMpllCfg->PllrDiv)); + DDL_ASSERT(IS_PLLN_VALID(pstcMpllCfg->plln)); + DDL_ASSERT(IS_PLLM_VALID(pstcMpllCfg->pllmDiv)); + +#ifdef __DEBUG + vcoIn = ((ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / pstcMpllCfg->pllmDiv); + vcoOut = vcoIn * pstcMpllCfg->plln; + + DDL_ASSERT(IS_PLL_VCO_IN_VALID(vcoIn)); + DDL_ASSERT(IS_PLL_VCO_OUT_VALID(vcoOut)); +#endif /* #ifdef __DEBUG */ + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_PLLCFGR_f.MPLLP = pstcMpllCfg->PllpDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLQ = pstcMpllCfg->PllqDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLR = pstcMpllCfg->PllrDiv - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLN = pstcMpllCfg->plln - 1ul; + M4_SYSREG->CMU_PLLCFGR_f.MPLLM = pstcMpllCfg->pllmDiv - 1ul; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the MPLL. + ** + ** \param [in] enNewState The new state of the MPLL. + ** \arg Enable Enable MPLL. + ** \arg Disable Disable MPLL. + ** + ** \retval en_result_t + ** + ** \note MPLL can not be stopped if it is used as system clock source. + ** + ******************************************************************************/ +en_result_t CLK_MpllCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + if(Disable == enNewState) + { + if(CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = Error; + } + else + { + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 1u; + } + } + else + { + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 0u; + do + { + status = CLK_GetFlagStatus(ClkFlagMPLLRdy); + timeout++; + }while((timeout < CLK_MPLL_TIMEOUT) && (status != Set)); + } + + DISABLE_CLOCK_REG_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configures the UPLL. + ** + ** \param [in] pstcUpllCfg The UPLL configures struct. + ** + ** \retval None + ** + ** \note The pllsource/pllm is between 1MHz and 24MHz. + ** The pllsource/pllm*plln is between 240MHz and 480MHz. + ** The maximum of pllsource/pllm*plln/pllp is 200MHz. + ** + ******************************************************************************/ +void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg) +{ +#ifdef __DEBUG + uint32_t vcoIn = 0ul; + uint32_t vcoOut = 0ul; +#endif /* #ifdef __DEBUG */ + + if(NULL != pstcUpllCfg) + { + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllpDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllqDiv)); + DDL_ASSERT(IS_PLL_DIV_VALID(pstcUpllCfg->PllrDiv)); + DDL_ASSERT(IS_PLLN_VALID(pstcUpllCfg->plln)); + DDL_ASSERT(IS_UPLLM_VALID(pstcUpllCfg->pllmDiv)); + +#ifdef __DEBUG + vcoIn = ((ClkPllSrcXTAL == M4_SYSREG->CMU_PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / pstcUpllCfg->pllmDiv); + vcoOut = vcoIn * pstcUpllCfg->plln; + + DDL_ASSERT(IS_PLL_VCO_IN_VALID(vcoIn)); + DDL_ASSERT(IS_PLL_VCO_OUT_VALID(vcoOut)); +#endif /* #ifdef __DEBUG */ + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UPLLCFGR_f.UPLLP = pstcUpllCfg->PllpDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLQ = pstcUpllCfg->PllqDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLR = pstcUpllCfg->PllrDiv - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLN = pstcUpllCfg->plln - 1u; + M4_SYSREG->CMU_UPLLCFGR_f.UPLLM = pstcUpllCfg->pllmDiv - 1u; + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the UPLL. + ** + ** \param [in] enNewState The new state of the UPLL. + ** \arg Enable Enable UPLL. + ** \arg Disable Disable UPLL. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t CLK_UpllCmd(en_functional_state_t enNewState) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UPLLCR_f.UPLLOFF = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_CLOCK_REG_WRITE(); + + do + { + status = CLK_GetFlagStatus(ClkFlagUPLLRdy); + timeout++; + }while((timeout < CLK_UPLL_TIMEOUT) && (status != ((Enable == enNewState) ? Set : Reset))); + + return Ok; +} + + +/** + ******************************************************************************* + ** \brief Select system clock source. + ** + ** \param [in] enTargetSysSrc The system clock source. + ** \arg ClkSysSrcHRC Select HRC as system clock source. + ** \arg ClkSysSrcMRC Select MRC as system clock source. + ** \arg ClkSysSrcLRC Select LRC as system clock source. + ** \arg ClkSysSrcXTAL Select XTAL as system clock source. + ** \arg ClkSysSrcXTAL32 Select XTAL32 as system clock source. + ** \arg CLKSysSrcMPLL Select MPLL as system clock source. + ** + ** \retval None + ** + ** \note Must close all of the fcg register before switch system clock source. + ** + ******************************************************************************/ +void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc) +{ + __IO uint32_t timeout = 0ul; + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + DDL_ASSERT(IS_SYSCLK_SOURCE(enTargetSysSrc)); + + ENABLE_FCG0_REG_WRITE(); + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if((CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) || + (CLKSysSrcMPLL == enTargetSysSrc)) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = DEFAULT_FCG0; + M4_MSTP->FCG1 = DEFAULT_FCG1; + M4_MSTP->FCG2 = DEFAULT_FCG2; + M4_MSTP->FCG3 = DEFAULT_FCG3; + + /* Wait stable after close fcg. */ + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + + /* Switch to target system clock source. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_CKSWR_f.CKSW = enTargetSysSrc; + + DISABLE_CLOCK_REG_WRITE(); + + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_SYSCLK_STABLE); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + DISABLE_FCG0_REG_WRITE(); + + /* Wait stable after open fcg. */ + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + + SystemCoreClockUpdate(); +} + +/** + ******************************************************************************* + ** \brief Get system clock source. + ** + ** \param None + ** + ** \retval The system clock source. + ** + ** \note None + ** + ******************************************************************************/ +en_clk_sys_source_t CLK_GetSysClkSource(void) +{ + return (en_clk_sys_source_t)M4_SYSREG->CMU_CKSWR_f.CKSW; +} + + +/** + ******************************************************************************* + ** \brief Configures the division factor for hclk,exck,pclk0,pclk1,pclk2,pclk3, + ** pclk4 from system clock. + ** + ** \param [in] pstcSysclkCfg The system clock configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg) +{ + __IO uint32_t timeout = 0ul; + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + ENABLE_FCG0_REG_WRITE(); + + if(NULL != pstcSysclkCfg) + { + DDL_ASSERT(IS_SYSCLK_CONFIG_VALID(pstcSysclkCfg)); + + /* Only current system clock source is MPLL need to close fcg0~fcg3 and + open fcg0~fcg3 during switch system clock division. + We need to backup fcg0~fcg3 before close them. */ + if(CLKSysSrcMPLL == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = DEFAULT_FCG0; + M4_MSTP->FCG1 = DEFAULT_FCG1; + M4_MSTP->FCG2 = DEFAULT_FCG2; + M4_MSTP->FCG3 = DEFAULT_FCG3; + + /* Wait stable after close fcg. */ + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + + /* Switch to target system clock division. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_SCFGR = ( (uint32_t)pstcSysclkCfg->enPclk0Div | + ((uint32_t)pstcSysclkCfg->enPclk1Div << 4u) | + ((uint32_t)pstcSysclkCfg->enPclk2Div << 8u) | + ((uint32_t)pstcSysclkCfg->enPclk3Div << 12u) | + ((uint32_t)pstcSysclkCfg->enPclk4Div << 16u) | + ((uint32_t)pstcSysclkCfg->enExclkDiv << 20u) | + ((uint32_t)pstcSysclkCfg->enHclkDiv << 24u) | + ((uint32_t)pstcSysclkCfg->enHclkDiv << 28u)); + + DISABLE_CLOCK_REG_WRITE(); + + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_SYSCLK_STABLE); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + DISABLE_FCG0_REG_WRITE(); + + /* Wait stable after open fcg. */ + timeout = 0ul; + do + { + timeout++; + }while(timeout < CLK_FCG_STABLE); + } + else + { + /* code */ + } +} + + +/** + ******************************************************************************* + ** \brief Get clock frequency. + ** + ** \param [in] pstcClkFreq The clock source struct. + ** + ** \retval The clock frequency include system clock,hclk,exck,pclk0,pclk1,pclk2 + ** pclk3,pclk4. + ** + ** \note None + ** + ******************************************************************************/ +void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq) +{ + uint32_t plln = 0u, pllp = 0u, pllm = 0u, pllsource = 0u; + + if(NULL != pstcClkFreq) + { + /* Get system clock. */ + switch(M4_SYSREG->CMU_CKSWR_f.CKSW) + { + case ClkSysSrcHRC: + /* HRC used as system clock. */ + pstcClkFreq->sysclkFreq = HRC_VALUE; + break; + case ClkSysSrcMRC: + /* MRC used as system clock. */ + pstcClkFreq->sysclkFreq = MRC_VALUE; + break; + case ClkSysSrcLRC: + /* LRC used as system clock. */ + pstcClkFreq->sysclkFreq = LRC_VALUE; + break; + case ClkSysSrcXTAL: + /* XTAL used as system clock. */ + pstcClkFreq->sysclkFreq = XTAL_VALUE; + break; + case ClkSysSrcXTAL32: + /* XTAL32 used as system clock. */ + pstcClkFreq->sysclkFreq = XTAL32_VALUE; + break; + default: + /* MPLLP used as system clock. */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + if (ClkPllSrcXTAL == pllsource) + { + pstcClkFreq->sysclkFreq = (XTAL_VALUE)/(pllm+1u)*(plln+1u)/(pllp+1u); + } + else if (ClkPllSrcHRC == pllsource) + { + pstcClkFreq->sysclkFreq = (HRC_VALUE)/(pllm+1u)*(plln+1u)/(pllp+1u); + } + else + { + //else + } + break; + } + + /* Get hclk. */ + pstcClkFreq->hclkFreq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.HCLKS; + + /* Get exck. */ + pstcClkFreq->exckFreq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.EXCKS; + + /* Get pclk0. */ + pstcClkFreq->pclk0Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK0S; + + /* Get pclk1. */ + pstcClkFreq->pclk1Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK1S; + + /* Get pclk2. */ + pstcClkFreq->pclk2Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK2S; + + /* Get pclk3. */ + pstcClkFreq->pclk3Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK3S; + + /* Get pclk4. */ + pstcClkFreq->pclk4Freq = pstcClkFreq->sysclkFreq >> M4_SYSREG->CMU_SCFGR_f.PCLK4S; + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Get PLL clock frequency. + ** + ** \param [in] pstcPllClkFreq The PLL clock source struct. + ** + ** \retval The clock frequency include mpllp, mpllq, mpllr, upllp, upllq, upllr. + ** + ** \note None + ** + ******************************************************************************/ +void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq) +{ + uint32_t pllsource; + uint32_t mplln = 0u, mpllp = 0u, mpllq = 0u, mpllr = 0u, mpllm = 0u; + uint32_t uplln = 0u, upllp = 0u, upllq = 0u, upllr = 0u, upllm = 0u; + + /* Get pll clock source */ + pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC; + + /* Get Mpll parameter value */ + mpllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP; + mpllq = M4_SYSREG->CMU_PLLCFGR_f.MPLLQ; + mpllr = M4_SYSREG->CMU_PLLCFGR_f.MPLLR; + mplln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN; + mpllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM; + + /* Get Upll paramter value */ + upllp = M4_SYSREG->CMU_UPLLCFGR_f.UPLLP; + upllq = M4_SYSREG->CMU_UPLLCFGR_f.UPLLQ; + upllr = M4_SYSREG->CMU_UPLLCFGR_f.UPLLR; + uplln = M4_SYSREG->CMU_UPLLCFGR_f.UPLLN; + upllm = M4_SYSREG->CMU_UPLLCFGR_f.UPLLM; + + /* Get mpllp ,mpllr, mpllq, upllp, upllq, upllr clock frequency */ + if (ClkPllSrcXTAL == pllsource) + { + pstcPllClkFreq->mpllp = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllp+1u); + pstcPllClkFreq->mpllq = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllq+1u); + pstcPllClkFreq->mpllr = (XTAL_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllr+1u); + pstcPllClkFreq->upllp = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllp+1u); + pstcPllClkFreq->upllq = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllq+1u); + pstcPllClkFreq->upllr = (XTAL_VALUE)/(upllm+1u)*(uplln+1u)/(upllr+1u); + } + else if (ClkPllSrcHRC == pllsource) + { + pstcPllClkFreq->mpllp = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllp+1u); + pstcPllClkFreq->mpllq = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllq+1u); + pstcPllClkFreq->mpllr = (HRC_VALUE)/(mpllm+1u)*(mplln+1u)/(mpllr+1u); + pstcPllClkFreq->upllp = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllp+1u); + pstcPllClkFreq->upllq = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllq+1u); + pstcPllClkFreq->upllr = (HRC_VALUE)/(upllm+1u)*(uplln+1u)/(upllr+1u); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Select usb clock source. + ** + ** \param [in] enTargetUsbSrc The usb clock source. + ** \arg ClkUsbSrcSysDiv2 Select 1/2 system clock as usb clock source. + ** \arg ClkUsbSrcSysDiv3 Select 1/3 system clock as usb clock source. + ** \arg ClkUsbSrcSysDiv4 Select 1/4 system clock as usb clock source. + ** \arg ClkUsbSrcMpllp Select MPLLP as usb clock source. + ** \arg ClkUsbSrcMpllq Select MPLLQ as usb clock source. + ** \arg ClkUsbSrcMpllr Select MPLLR as usb clock source. + ** \arg ClkUsbSrcUpllp Select UPLLP as usb clock source. + ** \arg ClkUsbSrcUpllq Select UPLLQ as usb clock source. + ** \arg ClkUsbSrcUpllr Select UPLLR as usb clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc) +{ + + DDL_ASSERT(IS_USBCLK_SOURCE(enTargetUsbSrc)); + + /* Switch to target usb clock source. */ + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_UFSCKCFGR_f.USBCKS = enTargetUsbSrc; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Select peripheral(adc/trng) clock source. + ** + ** \param [in] enTargetPeriSrc The peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcPclk Select PCLK2 as adc analog clok, PCLK4 as adc digital clock. Select PCLK4 as trng clock. + ** \arg ClkPeriSrcMpllp Select MPLLP as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcMpllq Select MPLLQ as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcMpllr Select MPLLR as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllp Select UPLLP as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllq Select UPLLQ as peripheral(adc/trng) clock source. + ** \arg ClkPeriSrcUpllr Select UPLLR as peripheral(adc/trng) clock source. + ** + ** \retval None + ** + ******************************************************************************/ +void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc) +{ + DDL_ASSERT(IS_PERICLK_SOURCE(enTargetPeriSrc)); + + ENABLE_CLOCK1_REG_WRITE(); + + /* Switch to target adc clock source. */ + M4_SYSREG->CMU_PERICKSEL_f.PERICKSEL = enTargetPeriSrc; + + DISABLE_CLOCK1_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Select I2S clock source. + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** \param [in] enTargetPeriSrc The I2S clock source. + ** \arg ClkPeriSrcPclk Select PCLK3 as I2S clock source. + ** \arg ClkPeriSrcMpllp Select MPLLP as I2S clock source. + ** \arg ClkPeriSrcMpllq Select MPLLQ as I2S clock source. + ** \arg ClkPeriSrcMpllr Select MPLLR as I2S clock source. + ** \arg ClkPeriSrcUpllp Select UPLLP as I2S clock source. + ** \arg ClkPeriSrcUpllq Select UPLLQ as I2S clock source. + ** \arg ClkPeriSrcUpllr Select UPLLR as I2S clock source. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc) +{ + DDL_ASSERT(IS_PERICLK_SOURCE(enTargetPeriSrc)); + + ENABLE_CLOCK1_REG_WRITE(); + + if(M4_I2S1 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S1CKSEL = enTargetPeriSrc; + } + else if(M4_I2S2 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S2CKSEL = enTargetPeriSrc; + } + else if(M4_I2S3 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S3CKSEL = enTargetPeriSrc; + } + else if(M4_I2S4 == pstcI2sReg) + { + M4_SYSREG->CMU_I2SCKSEL_f.I2S4CKSEL = enTargetPeriSrc; + } + else + { + /* code */ + } + + DISABLE_CLOCK1_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get I2S clock source. + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** + ** \retval en_clk_peri_source_t The I2S clock source. + ** + ** \note None + ** + ******************************************************************************/ +en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg) +{ + en_clk_peri_source_t enI2sClkSource = ClkPeriSrcPclk; + + if(M4_I2S1 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S1CKSEL; + } + else if(M4_I2S2 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S2CKSEL; + } + else if(M4_I2S3 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S3CKSEL; + } + else if(M4_I2S4 == pstcI2sReg) + { + enI2sClkSource = (en_clk_peri_source_t)M4_SYSREG->CMU_I2SCKSEL_f.I2S4CKSEL; + } + else + { + /* code */ + } + + return enI2sClkSource; +} + +/** + ******************************************************************************* + ** \brief Configures the debug clock. + ** + ** \param [in] enTpiuDiv The division of debug clock from system + ** clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv) +{ + DDL_ASSERT(IS_TPIUCLK_DIV_VALID(enTpiuDiv)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_TPIUCKCFGR_f.TPIUCKS = enTpiuDiv; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the debug clock. + ** + ** \param [in] enNewState The new state of the debug clock. + ** \arg Enable Enable debug clock. + ** \arg Disable Disable debug clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_TpiuClkCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + M4_SYSREG->CMU_TPIUCKCFGR_f.TPIUCKOE = enNewState; + + DISABLE_CLOCK_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configures the output clock. + ** + ** \param [in] enCh The clock output channel. + ** \param [in] pstcOutputCfg The clock output configures struct. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg) +{ + if(NULL != pstcOutputCfg) + { + DDL_ASSERT(IS_OUTPUTCLK_CHANNEL(enCh)); + DDL_ASSERT(IS_OUTPUTCLK_SOURCE(pstcOutputCfg->enOutputSrc)); + DDL_ASSERT(IS_OUTPUTCLK_DIV_VALID(pstcOutputCfg->enOutputDiv)); + + ENABLE_CLOCK_REG_WRITE(); + + switch(enCh) + { + case ClkOutputCh1: + M4_SYSREG->CMU_MCO1CFGR_f.MCO1SEL = pstcOutputCfg->enOutputSrc; + M4_SYSREG->CMU_MCO1CFGR_f.MCO1DIV = pstcOutputCfg->enOutputDiv; + break; + case ClkOutputCh2: + M4_SYSREG->CMU_MCO2CFGR_f.MCO2SEL = pstcOutputCfg->enOutputSrc; + M4_SYSREG->CMU_MCO2CFGR_f.MCO2DIV = pstcOutputCfg->enOutputDiv; + break; + default: + break; + } + + DISABLE_CLOCK_REG_WRITE(); + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the clock output. + ** + ** \param [in] enCh The clock output channel. + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_CLOCK_REG_WRITE(); + + switch(enCh) + { + case ClkOutputCh1: + M4_SYSREG->CMU_MCO1CFGR_f.MCO1EN = enNewState; + break; + case ClkOutputCh2: + M4_SYSREG->CMU_MCO2CFGR_f.MCO2EN = enNewState; + break; + default: + break; + } + + DISABLE_CLOCK_REG_WRITE(); +} + + +/** + ******************************************************************************* + ** \brief Get the specified clock flag status. + ** + ** \param [in] enClkFlag The specified clock flag. + ** \arg ClkFlagHRCRdy HRC is ready or not. + ** \arg ClkFlagXTALRdy XTAL is ready or not. + ** \arg ClkFlagMPLLRdy MPLL is ready or not. + ** \arg ClkFlagUPLLRdy UPLL is ready or not. + ** \arg ClkFlagXTALStoppage XTAL is detected stoppage or not. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag) +{ + en_flag_status_t status; + + DDL_ASSERT(IS_CLK_FLAG(enClkFlag)); + + switch(enClkFlag) + { + case ClkFlagHRCRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.HRCSTBF) ? Set : Reset); + break; + case ClkFlagXTALRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.XTALSTBF) ? Set : Reset); + break; + case ClkFlagMPLLRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.MPLLSTBF) ? Set : Reset); + break; + case ClkFlagUPLLRdy: + status = ((1u == M4_SYSREG->CMU_OSCSTBSR_f.UPLLSTBF) ? Set : Reset); + break; + default: + status = ((1u == M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF) ? Set : Reset); + break; + } + + return status; +} + + +/** + ******************************************************************************* + ** \brief Configures the clock frequency measurement. + ** + ** \param [in] pstcClkFcmCfg The clock frequency measurement configures + ** struct. + ** + ** \retval None + ** + ** \note Configures the window,measurement,reference and interrupt independently. + ** + ******************************************************************************/ +void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg) +{ + if(NULL != pstcClkFcmCfg) + { + /* Window config. */ + if(pstcClkFcmCfg->pstcFcmWindowCfg) + { + /* Set window lower. */ + M4_FCM->LVR = pstcClkFcmCfg->pstcFcmWindowCfg->windowLower; + /* Set window upper. */ + M4_FCM->UVR = pstcClkFcmCfg->pstcFcmWindowCfg->windowUpper; + } + + /* Measure config. */ + if(pstcClkFcmCfg->pstcFcmMeaCfg) + { + DDL_ASSERT(IS_FCM_SOURCE(pstcClkFcmCfg->pstcFcmMeaCfg->enSrc)); + DDL_ASSERT(IS_FCM_MEASRC_DIV_VALID(pstcClkFcmCfg->pstcFcmMeaCfg->enSrcDiv)); + + /* Measure source. */ + M4_FCM->MCCR_f.MCKS = pstcClkFcmCfg->pstcFcmMeaCfg->enSrc; + /* Measure source division. */ + M4_FCM->MCCR_f.MDIVS = pstcClkFcmCfg->pstcFcmMeaCfg->enSrcDiv; + } + + /* Reference config. */ + if(pstcClkFcmCfg->pstcFcmRefCfg) + { + DDL_ASSERT(IS_FCM_REF(pstcClkFcmCfg->pstcFcmRefCfg->enRefSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmRefCfg->enExtRef)); + DDL_ASSERT(IS_FCM_SOURCE(pstcClkFcmCfg->pstcFcmRefCfg->enIntRefSrc)); + DDL_ASSERT(IS_FCM_INTREF_DIV_VALID(pstcClkFcmCfg->pstcFcmRefCfg->enIntRefDiv)); + DDL_ASSERT(IS_FCM_EDGE(pstcClkFcmCfg->pstcFcmRefCfg->enEdge)); + DDL_ASSERT(IS_FCM_FILTER_CLK(pstcClkFcmCfg->pstcFcmRefCfg->enFilterClk)); + + M4_FCM->RCCR_f.INEXS = pstcClkFcmCfg->pstcFcmRefCfg->enRefSel; + M4_FCM->RCCR_f.EXREFE = pstcClkFcmCfg->pstcFcmRefCfg->enExtRef; + M4_FCM->RCCR_f.RCKS = pstcClkFcmCfg->pstcFcmRefCfg->enIntRefSrc; + M4_FCM->RCCR_f.RDIVS = pstcClkFcmCfg->pstcFcmRefCfg->enIntRefDiv; + M4_FCM->RCCR_f.EDGES = pstcClkFcmCfg->pstcFcmRefCfg->enEdge; + M4_FCM->RCCR_f.DNFS = pstcClkFcmCfg->pstcFcmRefCfg->enFilterClk; + } + + /* Interrupt config. */ + if(pstcClkFcmCfg->pstcFcmIntCfg) + { + DDL_ASSERT(IS_FCM_HANDLE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleReset)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enHandleInterrupt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enOvfInterrupt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcClkFcmCfg->pstcFcmIntCfg->enEndInterrupt)); + + M4_FCM->RIER_f.ERRINTRS = pstcClkFcmCfg->pstcFcmIntCfg->enHandleSel; + M4_FCM->RIER_f.ERRE = pstcClkFcmCfg->pstcFcmIntCfg->enHandleReset; + M4_FCM->RIER_f.ERRIE = pstcClkFcmCfg->pstcFcmIntCfg->enHandleInterrupt; + M4_FCM->RIER_f.MENDIE = pstcClkFcmCfg->pstcFcmIntCfg->enEndInterrupt; + M4_FCM->RIER_f.OVFIE = pstcClkFcmCfg->pstcFcmIntCfg->enOvfInterrupt; + } + } + else + { + /* code */ + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the clock frequency measurement. + ** + ** \param [in] enNewState The new state of the clock frequency + ** measurement. + ** \arg Enable Enable clock frequency measurement. + ** \arg Disable Disable clock frequency measurement. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_FcmCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_FCM->STR = enNewState; +} + +/** + ******************************************************************************* + ** \brief Get fcm counter value. + ** + ** \param None + ** + ** \retval The fcm counter value. + ** + ** \note None + ** + ******************************************************************************/ +uint16_t CLK_GetFcmCounter(void) +{ + return (uint16_t)(M4_FCM->CNTR & 0xFFFFu); +} + +/** + ******************************************************************************* + ** \brief Get the specified fcm flag status. + ** + ** \param [in] enFcmFlag The specified fcm flag. + ** \arg ClkFcmFlagOvf The fcm counter overflow or not. + ** \arg ClkFcmFlagMendf The end of the measurement or not. + ** \arg ClkFcmFlagErrf Whether the frequency is abnormal or not. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag) +{ + en_flag_status_t status = Reset; + + DDL_ASSERT(IS_FCM_FLAG(enFcmFlag)); + + switch(enFcmFlag) + { + case ClkFcmFlagOvf: + status = (en_flag_status_t)M4_FCM->SR_f.OVF; + break; + case ClkFcmFlagMendf: + status = (en_flag_status_t)M4_FCM->SR_f.MENDF; + break; + case ClkFcmFlagErrf: + status = (en_flag_status_t)M4_FCM->SR_f.ERRF; + break; + default: + break; + } + + return status; +} + +/** + ******************************************************************************* + ** \brief Clear the specified fcm flag status. + ** + ** \param [in] enFcmFlag The specified fcm flag. + ** \arg ClkFcmFlagOvf Clear the fcm counter overflow flag. + ** \arg ClkFcmFlagMendf Clear the end of the measurement flag. + ** \arg ClkFcmFlagErrf Clear the frequency abnormal flag. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag) +{ + DDL_ASSERT(IS_FCM_FLAG(enFcmFlag)); + + switch(enFcmFlag) + { + case ClkFcmFlagOvf: + M4_FCM->CLR_f.OVFCLR = Set; + break; + case ClkFcmFlagMendf: + M4_FCM->CLR_f.MENDFCLR = Set; + break; + case ClkFcmFlagErrf: + M4_FCM->CLR_f.ERRFCLR = Set; + break; + default: + break; + } +} + +/** + ******************************************************************************* + ** \brief Clear the XTAL error flag. + ** + ** \param None + ** + ** \retval None + ** + ** \note The system clock should not be XTAL before call this function. + ** + ******************************************************************************/ +void CLK_ClearXtalStdFlag(void) +{ + /* Enable register write. */ + ENABLE_CLOCK_REG_WRITE(); + + if(Set == M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF) + { + /* Clear the XTAL STD flag */ + M4_SYSREG->CMU_XTALSTDSR_f.XTALSTDF = Reset; + } + + /* Disbale register write. */ + DISABLE_CLOCK_REG_WRITE(); +} + + +//@} // CmuGroup + +#endif /* DDL_CLK_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_cmp.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_cmp.c new file mode 100644 index 0000000000..dde45b7834 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_cmp.c @@ -0,0 +1,1046 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_cmp.c + ** + ** A detailed description is available at + ** @link CmpGroup CMP @endlink + ** + ** - 2018-10-22 CDT First version for Device Driver Library of CMP. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_cmp.h" +#include "hc32f460_utility.h" + +#if (DDL_CMP_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CmpGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for CMP Instances. */ +#define IS_VALID_CMP(__CMPx__) \ +( (M4_CMP1 == (__CMPx__)) || \ + (M4_CMP2 == (__CMPx__)) || \ + (M4_CMP3 == (__CMPx__))) + +/*!< Parameter valid check for CMP function */ +#define IS_VALID_CMP_FUNCTION(x) \ +( (CmpOutput == (x)) || \ + (CmpOutpuInv == (x)) || \ + (CmpVcoutOutput == (x))) + +/*! Parameter validity check for edge sel. */ +#define IS_VALID_EDGESEL(x) \ +( (CmpNoneEdge == (x)) || \ + (CmpBothEdge == (x)) || \ + (CmpRisingEdge == (x)) || \ + (CmpFaillingEdge == (x))) + +/*!< Parameter CMP FLT validity check for clock division. */ +#define IS_VALID_FLTCLK_DIVISION(x) \ +( (CmpNoneFlt == (x)) || \ + (CmpFltPclk3Div1 == (x)) || \ + (CmpFltPclk3Div2 == (x)) || \ + (CmpFltPclk3Div4 == (x)) || \ + (CmpFltPclk3Div8 == (x)) || \ + (CmpFltPclk3Div16 == (x)) || \ + (CmpFltPclk3Div32 == (x)) || \ + (CmpFltPclk3Div64 == (x))) + +/*!< Parameter validity check for INP4 SEL. */ +#define IS_VALID_INP4SEL(x) \ +( (CmpInp4None == (x)) || \ + (CmpInp4PGAO == (x)) || \ + (CmpInp4PGAO_BP == (x)) || \ + (CmpInp4CMP1_INP4 == (x))) + +/*!< Parameter validity check for INP INPUT SEL. */ +#define IS_VALID_INPSEL(x) \ +( (CmpInpNone == (x)) || \ + (CmpInp1 == (x)) || \ + (CmpInp2 == (x)) || \ + (CmpInp3 == (x)) || \ + (CmpInp4 == (x)) || \ + (CmpInp1_Inp2 == (x)) || \ + (CmpInp1_Inp3 == (x)) || \ + (CmpInp2_Inp3 == (x)) || \ + (CmpInp1_Inp4 == (x)) || \ + (CmpInp2_Inp4 == (x)) || \ + (CmpInp3_Inp4 == (x)) || \ + (CmpInp1_Inp2_Inp3 == (x)) || \ + (CmpInp1_Inp2_Inp4 == (x)) || \ + (CmpInp1_Inp3_Inp4 == (x)) || \ + (CmpInp2_Inp3_Inp4 == (x)) || \ + (CmpInp1_Inp2_Inp3_Inp4 == (x))) + +/*!< Parameter validity check for INM INPUT SEL. */ +#define IS_VALID_INMSEL(x) \ +( (CmpInm1 == (x)) || \ + (CmpInm2 == (x)) || \ + (CmpInm3 == (x)) || \ + (CmpInm4 == (x)) || \ + (CmpInmNone == (x))) + +/*!< Parameter validity check for CMP_CR channel. */ +#define IS_VALID_CMP_CR_CH(x) \ +( (CmpDac1 == (x)) || \ + (CmpDac2 == (x))) + +/*!< Parameter validity check for ADC internal reference voltage path. */ +#define IS_VALID_ADC_REF_VOLT_PATH(x) \ +( (CmpAdcRefVoltPathDac1 == (x)) || \ + (CmpAdcRefVoltPathDac2 == (x)) || \ + (CmpAdcRefVoltPathVref == (x))) + +/*!< RVADC Write Protection Key. */ +#define RVADC_WRITE_PROT_KEY (0x5500u) + +/*!< Timer4x ECER register address. */ +#define CMP_CR_DADRx(__DACx__) \ +( (CmpDac1 == (__DACx__)) ? &M4_CMP_CR->DADR1 : &M4_CMP_CR->DADR2) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes the specified CMP. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] pstcInitCfg Pointer to CMP configure structure + ** \arg This parameter detail refer @ref stc_cmp_init_t + ** + ** \retval Ok CMP is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - CMPx is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t CMP_Init(M4_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx && pstcInitCfg pointer */ + if ((IS_VALID_CMP(CMPx)) && (NULL != pstcInitCfg)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_EDGESEL(pstcInitCfg->enEdgeSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpIntEN)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpInvEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpOutputEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpVcoutOutputEn)); + DDL_ASSERT(IS_VALID_FLTCLK_DIVISION(pstcInitCfg->enFltClkDiv)); + + /* De-Initialize CMP */ + CMPx->CTRL = (uint16_t)0x0000u; + CMPx->VLTSEL = (uint16_t)0x0000u; + CMPx->CVSSTB = (uint16_t)0x0005u; + CMPx->CVSPRD = (uint16_t)0x000Fu; + + CMPx->CTRL_f.IEN = (uint16_t)pstcInitCfg->enCmpIntEN; + CMPx->CTRL_f.INV = (uint16_t)pstcInitCfg->enCmpInvEn; + CMPx->CTRL_f.EDGSL = (uint16_t)pstcInitCfg->enEdgeSel; + CMPx->CTRL_f.FLTSL = (uint16_t)pstcInitCfg->enFltClkDiv; + CMPx->CTRL_f.CMPOE = (uint16_t)pstcInitCfg->enCmpOutputEn; + CMPx->CTRL_f.OUTEN = (uint16_t)pstcInitCfg->enCmpVcoutOutputEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize CMP + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_DeInit(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL = (uint16_t)0x0000u; + CMPx->VLTSEL = (uint16_t)0x0000u; + CMPx->CVSSTB = (uint16_t)0x0005u; + CMPx->CVSPRD = (uint16_t)0x000Fu; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP working + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enCmd The CMP function state + ** \arg Disable Disable CMP working + ** \arg Enable Enable CMP working + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_Cmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + CMPx->CTRL_f.CMPON = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP interrupt request + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enCmd The CMP interrupt function state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ******************************************************************************/ +en_result_t CMP_IrqCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.IEN = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set scan time(scan stable&&period) + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] u8ScanStable CMP scan stable value + ** \arg u8ScanStable < 16 + ** \param [in] u8ScanPeriod CMP scan period value + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ** \note u8ScanStable && u8ScanPeriod value must meet following condition: + ** u8ScanPeriod > u8ScanStable + FLTSL_DIV*4 + 5 + ** FLTSL_DIV is filter sample period division(refer CMPx->CTRL_f.FLTSL) + ** + ******************************************************************************/ +en_result_t CMP_SetScanTime(M4_CMP_TypeDef *CMPx, + uint8_t u8ScanStable, + uint8_t u8ScanPeriod) +{ + uint16_t u16Flts; + uint16_t u16FltslDiv; + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if ((!IS_VALID_CMP(CMPx)) || (u8ScanStable & 0xF0u)) + { + enRet = ErrorInvalidParameter; + } + else + { + u16Flts = CMPx->CTRL_f.FLTSL; + u16FltslDiv = ((uint16_t)1u << (u16Flts - 1u)); + + if ((0u != u16Flts) && + (u8ScanPeriod <= (u8ScanStable + u16FltslDiv * 4u + 5u))) + { + enRet = ErrorInvalidParameter; + } + else + { + CMPx->CVSSTB_f.STB = u8ScanStable; + CMPx->CVSPRD_f.PRD = u8ScanPeriod; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified CMP function. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enFunc CMP function selection + ** \arg CmpVcoutOutput CMP Vcout output enable function + ** \arg CmpOutpuInv CMP output invert enable function + ** \arg CmpOutput CMP output enable function + ** \param [in] enCmd CMP functional state + ** \arg Enable Enable the specified CMP function + ** \arg Disable Disable the specified CMP function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_FuncCmd(M4_CMP_TypeDef *CMPx, + en_cmp_func_t enFunc, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_CMP_FUNCTION(enFunc)); + + if (Enable == enCmd) + { + CMPx->CTRL |= (uint16_t)enFunc; + } + else + { + CMPx->CTRL &= (uint16_t)(~((uint16_t)enFunc)); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start CMP scan + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Start successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_StartScan(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.CVSEN = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop CMP scan + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval Ok Stop successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_StopScan(M4_CMP_TypeDef *CMPx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->CTRL_f.CVSEN = (uint16_t)0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP filter sample clock division. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enFltClkDiv The CMP filter sample clock division selection + ** \arg CmpNoneFlt Unuse filter + ** \arg CmpFltPclk3Div1 PCLK3/1 + ** \arg CmpFltPclk3Div2 PCLK3/2 + ** \arg CmpFltPclk3Div4 PCLK3/4 + ** \arg CmpFltPclk3Div8 PCLK3/8 + ** \arg CmpFltPclk3Div16 PCLK3/16 + ** \arg CmpFltPclk3Div32 PCLK3/32 + ** \arg CmpFltPclk3Div64 PCLK3/64 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetFilterClkDiv(M4_CMP_TypeDef *CMPx, + en_cmp_fltclk_div_t enFltClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_FLTCLK_DIVISION(enFltClkDiv)); + CMPx->CTRL_f.FLTSL = (uint16_t)enFltClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP filter sample clock division. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpNoneFlt Unuse filter + ** \retval CmpFltPclk3Div1 PCLK3/1 + ** \retval CmpFltPclk3Div2 PCLK3/2 + ** \retval CmpFltPclk3Div4 PCLK3/4 + ** \retval CmpFltPclk3Div8 PCLK3/8 + ** \retval CmpFltPclk3Div16 PCLK3/16 + ** \retval CmpFltPclk3Div32 PCLK3/32 + ** \retval CmpFltPclk3Div64 PCLK3/64 + ** + ******************************************************************************/ +en_cmp_fltclk_div_t CMP_GetFilterClkDiv(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_fltclk_div_t)CMPx->CTRL_f.FLTSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP detection edge selection. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enEdgeSel The CMP detection edge selection + ** \arg CmpNoneEdge None edge detection + ** \arg CmpRisingEdge Rising edge detection + ** \arg CmpFaillingEdge Falling edge detection + ** \arg CmpBothEdge Falling or Rising edge detection + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetEdgeSel(M4_CMP_TypeDef *CMPx, + en_cmp_edge_sel_t enEdgeSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_EDGESEL(enEdgeSel)); + CMPx->CTRL_f.EDGSL = (uint16_t)enEdgeSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP detection edge selection. + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpNoneEdge None edge detection + ** \retval CmpRisingEdge Rising edge detection + ** \retval CmpFaillingEdge Falling edge detection + ** \retval CmpBothEdge Falling or Rising edge detection + ** + ******************************************************************************/ +en_cmp_edge_sel_t CMP_GetEdgeSel(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_edge_sel_t)CMPx->CTRL_f.EDGSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP input sel + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] pstcInputSel The CMP input selection structure + ** \arg This parameter detail refer @ref stc_cmp_input_sel_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_InputSel(M4_CMP_TypeDef *CMPx, + const stc_cmp_input_sel_t *pstcInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx && pstcInputSel pointer */ + if ((IS_VALID_CMP(CMPx)) && (NULL != pstcInputSel)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INMSEL(pstcInputSel->enInmSel)); + DDL_ASSERT(IS_VALID_INPSEL(pstcInputSel->enInpSel)); + DDL_ASSERT(IS_VALID_INP4SEL(pstcInputSel->enInp4Sel)); + + if ((CmpInp4PGAO == pstcInputSel->enInp4Sel) || + (CmpInp4PGAO_BP == pstcInputSel->enInp4Sel)) + { + if (M4_CMP3 != CMPx) + { + enRet = Ok; + } + } + else if (CmpInp4CMP1_INP4 == pstcInputSel->enInp4Sel) + { + if (M4_CMP1 == CMPx) + { + enRet = Ok; + } + } + else + { + enRet = Ok; + } + + if (enRet == Ok) + { + CMPx->VLTSEL_f.CVSL = (uint16_t)pstcInputSel->enInpSel; + CMPx->VLTSEL_f.RVSL = (uint16_t)pstcInputSel->enInmSel; + CMPx->VLTSEL_f.C4SL = (uint16_t)pstcInputSel->enInp4Sel; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInpNone None input + ** \arg CmpInp1 INP1 input + ** \arg CmpInp2 INP2 input + ** \arg CmpInp1_Inp2 INP1 INP2 input + ** \arg CmpInp3 INP3 input + ** \arg CmpInp1_Inp3 INP1 INP3 input + ** \arg CmpInp2_Inp3 INP2 INP3 input + ** \arg CmpInp1_Inp2_Inp3 INP1 INP2 INP3 input + ** \arg CmpInp4 INP4 input + ** \arg CmpInp1_Inp4 INP1 INP4 input + ** \arg CmpInp2_Inp4 INP2 INP4 input + ** \arg CmpInp1_Inp2_Inp4 INP1 INP2 INP4 input + ** \arg CmpInp3_Inp4 INP3 INP4 input + ** \arg CmpInp1_Inp3_Inp4 INP1 INP3 INP4 input + ** \arg CmpInp2_Inp3_Inp4 INP2 INP3 INP4 input + ** \arg CmpInp1_Inp2_Inp3_Inp4 INP1 INP2 INP3 INP4 input + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid + ** + ******************************************************************************/ +en_result_t CMP_SetInp(M4_CMP_TypeDef *CMPx, en_cmp_inp_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INPSEL(enInputSel)); + CMPx->VLTSEL_f.CVSL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInpNone None input + ** \retval CmpInp1 INP1 input + ** \retval CmpInp2 INP2 input + ** \retval CmpInp1_Inp2 INP1 INP2 input + ** \retval CmpInp3 INP3 input + ** \retval CmpInp1_Inp3 INP1 INP3 input + ** \retval CmpInp2_Inp3 INP2 INP3 input + ** \retval CmpInp1_Inp2_Inp3 INP1 INP2 INP3 input + ** \retval CmpInp4 INP4 input + ** \retval CmpInp1_Inp4 INP1 INP4 input + ** \retval CmpInp2_Inp4 INP2 INP4 input + ** \retval CmpInp1_Inp2_Inp4 INP1 INP2 INP4 input + ** \retval CmpInp3_Inp4 INP3 INP4 input + ** \retval CmpInp1_Inp3_Inp4 INP1 INP3 INP4 input + ** \retval CmpInp2_Inp3_Inp4 INP2 INP3 INP4 input + ** \retval CmpInp1_Inp2_Inp3_Inp4 INP1 INP2 INP3 INP4 input + ** + ******************************************************************************/ +en_cmp_inp_sel_t CMP_GetInp(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp_sel_t)CMPx->VLTSEL_f.CVSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP INM input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInmNone None input + ** \arg CmpInm1 INM1 input + ** \arg CmpInm2 INM2 input + ** \arg CmpInm3 INM3 input + ** \arg CmpInm4 INM4 input + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ******************************************************************************/ +en_result_t CMP_SetInm(M4_CMP_TypeDef *CMPx, en_cmp_inm_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_INMSEL(enInputSel)); + CMPx->VLTSEL_f.RVSL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP INM input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInmNone None input + ** \retval CmpInm1 INM1 input + ** \retval CmpInm2 INM2 input + ** \retval CmpInm3 INM3 input + ** \retval CmpInm4 INM4 input + ** + ******************************************************************************/ +en_cmp_inm_sel_t CMP_GetInm(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inm_sel_t)CMPx->VLTSEL_f.RVSL; +} + +/** + ******************************************************************************* + ** \brief Set CMP INP4 input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** \param [in] enInputSel The INP input selection + ** \arg CmpInp4None None input + ** \arg CmpInp4PGAO PGAO output + ** \arg CmpInp4PGAO_BP PGAO_BP output + ** \arg CmpInp4CMP1_INP4 CMP1_INP4 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter CMPx is invalid. + ** + ** \note Inp4 Selection is valid only for M4_CMP1 + ** and M4_CMP2. + ** + ******************************************************************************/ +en_result_t CMP_SetInp4(M4_CMP_TypeDef *CMPx,en_cmp_inp4_sel_t enInputSel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + DDL_ASSERT(M4_CMP3 != CMPx); + DDL_ASSERT(IS_VALID_INP4SEL(enInputSel)); + + /* Check CMPx pointer */ + if (IS_VALID_CMP(CMPx)) + { + CMPx->VLTSEL_f.C4SL = (uint16_t)enInputSel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get CMP INP4 input selection + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpInp4None None input + ** \retval CmpInp4PGAO PGAO output + ** \retval CmpInp4PGAO_BP PGAO_BP output + ** \retval CmpInp4CMP1_INP4 CMP1_INP4 + ** + ** \note Inp4 Selection is valid only for M4_CMP1 + ** and M4_CMP2. + ** + ******************************************************************************/ +en_cmp_inp4_sel_t CMP_GetInp4(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp4_sel_t)CMPx->VLTSEL_f.C4SL; +} + +/** + ******************************************************************************* + ** \brief Get CMP output state + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpOutputLow Compare output Low "0" + ** \retval CmpOutputHigh Compare output High "1" + ** + ******************************************************************************/ +en_cmp_output_state_t CMP_GetOutputState(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_output_state_t)(CMPx->MON_f.OMON); +} + +/** + ******************************************************************************* + ** \brief Get CMP INP state + ** + ** \param [in] CMPx Pointer to CMP instance register base + ** \arg M4_CMP1 CMP unit 1 instance register base + ** \arg M4_CMP2 CMP unit 2 instance register base + ** \arg M4_CMP3 CMP unit 3 instance register base + ** + ** \retval CmpOutputLow Compare output Low "0" + ** \retval CmpOutputHigh Compare output High "1" + ** + ******************************************************************************/ +en_cmp_inp_state_t CMP_GetInpState(M4_CMP_TypeDef *CMPx) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP(CMPx)); + + return (en_cmp_inp_state_t)(CMPx->MON_f.CVST); +} + +/** + ******************************************************************************* + ** \brief Initialize CMP DAC + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** \param [in] pstcInitCfg Pointer to CMP DAC configure structure + ** \arg This parameter detail refer @ref stc_cmp_dac_init_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_Init(en_cmp_dac_ch_t enCh, + const stc_cmp_dac_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_CMP_CR_CH(enCh)) && (pstcInitCfg != NULL)) + { + /* Check parameter */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpDacEN)); + + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); /* Disable DAC */ + + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = pstcInitCfg->u8DacData; /* Set DAC data */ + + if (Enable == pstcInitCfg->enCmpDacEN) + { + M4_CMP_CR->DACR |= (uint16_t)(1ul << enCh); /* Enable DAC */ + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize CMP DAC + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_DeInit(en_cmp_dac_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable CMP DAC working + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP DAC channel: DAC1 + ** \arg CmpDac2 CMP DAC channel: DAC2 + ** \param [in] enCmd The CMP DAC function state + ** \arg Disable Disable CMP DAC working + ** \arg Enable Enable CMP DAC working + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_Cmd(en_cmp_dac_ch_t enCh, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + if(Enable == enCmd) + { + M4_CMP_CR->DACR |= (uint16_t)(1ul << enCh); + } + else + { + M4_CMP_CR->DACR &= (uint16_t)(~(1ul << enCh)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DAC data register value + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** \param [in] u8DacData DAC data register value + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enCh is invalid. + ** + ******************************************************************************/ +en_result_t CMP_DAC_SetData(en_cmp_dac_ch_t enCh, uint8_t u8DacData) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_CMP_CR_CH(enCh)) + { + *(__IO uint8_t *)CMP_CR_DADRx(enCh) = u8DacData; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DAC data register value + ** + ** \param [in] enCh CMP DAC channel + ** \arg CmpDac1 CMP CR DAC channel: DAC1 + ** \arg CmpDac2 CMP CR DAC channel: DAC2 + ** + ** \retval DAC data register value + ** + ******************************************************************************/ +uint8_t CMP_DAC_GetData(en_cmp_dac_ch_t enCh) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_CMP_CR_CH(enCh)); + + return *(__IO uint8_t *)CMP_CR_DADRx(enCh); +} + +/** + ******************************************************************************* + ** \brief Set ADC internal reference voltage path + ** + ** \param [in] enRefVoltPath ADC internal reference voltage path + ** \arg CmpAdcRefVoltPathDac1 ADC internal reference voltage path: DAC1 + ** \arg CmpAdcRefVoltPathDac2 ADC internal reference voltage path: DAC2 + ** \arg CmpAdcRefVoltPathVref ADC internal reference voltage path: VREF + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enRefVoltPath is invalid. + ** + ******************************************************************************/ +en_result_t CMP_ADC_SetRefVoltPath(en_cmp_adc_int_ref_volt_path_t enRefVoltPath) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameter */ + if (IS_VALID_ADC_REF_VOLT_PATH(enRefVoltPath)) + { + M4_CMP_CR->RVADC = RVADC_WRITE_PROT_KEY; /* Release write protection */ + M4_CMP_CR->RVADC = enRefVoltPath; /* Set reference voltage path */ + enRet = Ok; + } + + return enRet; +} + +//@} // CmpGroup + +#endif /* DDL_CMP_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_crc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_crc.c new file mode 100644 index 0000000000..1cdf7fb24b --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_crc.c @@ -0,0 +1,327 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_crc.c + ** + ** A detailed description is available at + ** @link CrcGroup Crc description @endlink + ** + ** - 2019-03-07 CDT First version for Device Driver Library of Crc. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_crc.h" +#include "hc32f460_utility.h" + +#if (DDL_CRC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Definition of CRC16 data register. */ +#define M4_CRC16_DAT (*((__IO uint16_t *)&M4_CRC->DAT0)) + +/* Definition of CRC16 checksum register. */ +#define M4_CRC16_RSLT (*((__IO uint16_t *)&M4_CRC->RESLT)) + +/* Definition of CRC16 initial value register. */ +#define M4_CRC16_INIT (M4_CRC16_RSLT) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t CRC_ProcChecksum(uint32_t u32Checksum); +static uint32_t CRC_ReverseBits(uint32_t u32Data); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize the CRC. + ** + ** \param [in] u32Config Bit[1]: CRC_SEL_16B or CRC_SEL_32B. + ** Bit[2]: CRC_REFIN_DISABLE or CRC_REFIN_ENABLE. + ** Bit[3]: CRC_REFOUT_DISABLE or CRC_REFOUT_ENABLE. + ** Bit[4]: CRC_XOROUT_DISABLE or CRC_XOROUT_ENABLE. + ** See the definitions for details. + ** + ** \retval None + ** + ******************************************************************************/ +void CRC_Init(uint32_t u32Config) +{ + u32Config &= CRC_CONFIG_MASK; + + M4_CRC->CR = u32Config; +} + +/** + ******************************************************************************* + ** \brief CRC16 calculation. + ** + ** \param [in] u16InitVal Initial value of CRC16. + ** + ** \param [in] pu16Data Pointer to the buffer containing the data to be computed. + ** + ** \param [in] u32Length Length of the buffer to be computed. + ** + ** \retval 16-bit CRC checksum. + ** + ******************************************************************************/ +uint16_t CRC_Calculate16B(uint16_t u16InitVal, const uint16_t *pu16Data, uint32_t u32Length) +{ + uint16_t u16Ret = 0u; + uint32_t u32Count; + + if (NULL != pu16Data) + { + M4_CRC16_INIT = u16InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC16_DAT = pu16Data[u32Count]; + } + + u16Ret = M4_CRC16_RSLT; + } + + return u16Ret; +} + +/** + ******************************************************************************* + ** \brief CRC32 calculation. + ** + ** \param [in] u32InitVal Initial value of CRC32. + ** + ** \param [in] pu32Data Pointer to the buffer containing the data to be computed. + ** + ** \param [in] u32Length Length of the buffer to be computed. + ** + ** \retval 32-bit CRC checksum. + ** + ******************************************************************************/ +uint32_t CRC_Calculate32B(uint32_t u32InitVal, const uint32_t *pu32Data, uint32_t u32Length) +{ + uint32_t u32Ret = 0u; + uint32_t u32Count; + + M4_CRC->RESLT = u32InitVal; + + if (NULL != pu32Data) + { + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC->DAT0 = pu32Data[u32Count]; + } + + u32Ret = M4_CRC->RESLT; + } + + return u32Ret; +} + +/** + ******************************************************************************* + ** \brief CRC16 check. + ** + ** \param [in] u16InitVal Initial value of CRC16. + ** + ** \param [in] u16Checksum CRC16 checksum of the source data. + ** + ** \param [in] pu16Data Pointer to the buffer containing the data to be checked. + ** + ** \param [in] u32Length Length of the buffer to be checked. + ** + ** \retval true CRC16 checks successfully. + ** \retval false CRC16 checks unsuccessfully. + ** + ******************************************************************************/ +bool CRC_Check16B(uint16_t u16InitVal, uint16_t u16Checksum, const uint16_t *pu16Data, uint32_t u32Length) +{ + bool bRet = false; + uint32_t u32Count; + uint16_t u16CrcChecksum; + + if (NULL != pu16Data) + { + u16CrcChecksum = (uint16_t)CRC_ProcChecksum((uint32_t)u16Checksum); + M4_CRC16_INIT = u16InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC16_DAT = pu16Data[u32Count]; + } + + M4_CRC16_DAT = u16CrcChecksum; + + if (bM4_CRC_FLG_FLAG) + { + bRet = true; + } + } + + return bRet; +} + +/** + ******************************************************************************* + ** \brief CRC32 check. + ** + ** \param [in] u32InitVal Initial value of CRC32. + ** + ** \param [in] u32Checksum CRC32 checksum of the source data. + ** + ** \param [in] pu32Data Pointer to the buffer containing the data to be checked. + ** + ** \param [in] u32Length Length of the buffer to be checked. + ** + ** \retval true CRC32 checks successfully. + ** \retval false CRC32 checks unsuccessfully. + ** + ******************************************************************************/ +bool CRC_Check32B(uint32_t u32InitVal, uint32_t u32Checksum, const uint32_t *pu32Data, uint32_t u32Length) +{ + bool bRet = false; + uint32_t u32Count; + uint32_t u32CrcChecksum; + + if (NULL != pu32Data) + { + u32CrcChecksum = CRC_ProcChecksum(u32Checksum); + M4_CRC->RESLT = u32InitVal; + + for (u32Count = 0u; u32Count < u32Length; u32Count++) + { + M4_CRC->DAT0 = pu32Data[u32Count]; + } + + M4_CRC->DAT0 = u32CrcChecksum; + + if (bM4_CRC_FLG_FLAG) + { + bRet = true; + } + } + + return bRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Processes the checksum of CRC. + ** + ** \param [in] u32Checksum The checksum of CRC16 or CRC32. + ** + ** \retval 32-bit new checksum will be used by CRC checking. + ** + ******************************************************************************/ +static uint32_t CRC_ProcChecksum(uint32_t u32Checksum) +{ + uint8_t i; + uint8_t u8Size = 16u; + uint8_t u8Offset; + uint32_t u32Config; + uint32_t u32FinalChecksum; + uint32_t u32Temp; + + u32Config = M4_CRC->CR; + u32FinalChecksum = u32Checksum; + + if ((u32Config & CRC_SEL_32B) == CRC_SEL_32B) + { + u8Size = 32u; + } + + if ((u32Config & CRC_REFOUT_ENABLE) == CRC_REFOUT_DISABLE) + { + /* Bits reversing. */ + u32FinalChecksum = CRC_ReverseBits(u32Checksum); + if (u8Size == 16u) + { + u32FinalChecksum >>= 16u; + u32FinalChecksum &= 0xFFFFu; + } + } + + if ((u32Config & CRC_XOROUT_ENABLE) == CRC_XOROUT_DISABLE) + { + /* Bits NOT. */ + u32FinalChecksum = ~u32FinalChecksum; + } + + if ((u32Config & CRC_REFIN_ENABLE) == CRC_REFIN_DISABLE) + { + u8Size /= 8u; + /* Bits reversing in bytes. */ + for (i = 0u; i < u8Size; i++) + { + u8Offset = i * 8u; + u32Temp = (u32FinalChecksum >> u8Offset) & 0xFFul; + u32Temp = CRC_ReverseBits(u32Temp); + u32Temp = u32Temp >> (24u - u8Offset); + u32FinalChecksum &= ~((uint32_t)0xFF << u8Offset); + u32FinalChecksum |= u32Temp; + } + } + + return u32FinalChecksum; +} + +/** + ******************************************************************************* + ** \brief Reverse bits. + ** + ** \param [in] u32Data The data to be reversed bits. + ** + ** \retval 32-bit new data. + ** + ******************************************************************************/ +static uint32_t CRC_ReverseBits(uint32_t u32Data) +{ + u32Data = (((u32Data & 0xAAAAAAAAul) >> 1u) | ((u32Data & 0x55555555ul) << 1u)); + u32Data = (((u32Data & 0xCCCCCCCCul) >> 2u) | ((u32Data & 0x33333333ul) << 2u)); + u32Data = (((u32Data & 0xF0F0F0F0ul) >> 4u) | ((u32Data & 0x0F0F0F0Ful) << 4u)); + u32Data = (((u32Data & 0xFF00FF00ul) >> 8u) | ((u32Data & 0x00FF00FFul) << 8u)); + + return ((u32Data >> 16u) | (u32Data << 16u)); +} + +//@} // CrcGroup + +#endif /* DDL_CRC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dcu.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dcu.c new file mode 100644 index 0000000000..71fdbede5e --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dcu.c @@ -0,0 +1,975 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dcu.c + ** + ** A detailed description is available at + ** @link DcuGroup DCU description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of DCU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_dcu.h" +#include "hc32f460_utility.h" + +#if (DDL_DCU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DcuGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for DCU Instances. */ +#define IS_VALID_DCU(__DCUx__) \ +( (M4_DCU1 == (__DCUx__)) || \ + (M4_DCU2 == (__DCUx__)) || \ + (M4_DCU3 == (__DCUx__)) || \ + (M4_DCU4 == (__DCUx__))) + +/*!< Parameter valid check for DCU DATA register. */ +#define IS_VALID_DCU_DATA_REG(x) \ +( (DcuRegisterData0 == (x)) || \ + (DcuRegisterData1 == (x)) || \ + (DcuRegisterData2 == (x))) + +/*!< Parameter valid check for DCU operation mode. */ +#define IS_VALID_DCU_OPERATION(x) \ +( (DcuOpAdd == (x)) || \ + (DcuOpSub == (x)) || \ + (DcuInvalid == (x)) || \ + (DcuOpCompare == (x)) || \ + (DcuHwTrigOpAdd == (x)) || \ + (DcuHwTrigOpSub == (x))) + +/*!< Parameter valid check for DCU data size. */ +#define IS_VALID_DCU_DATAZ_SIZE(x) \ +( (DcuDataBit8 == (x)) || \ + (DcuDataBit16 == (x)) || \ + (DcuDataBit32 == (x))) + +/*!< Parameter valid check for DCU compare trigger mode type. */ +#define IS_VALID_DCU_CMP_TRIG_MODE(x) \ +( (DcuCmpTrigbyData0 == (x)) || \ + (DcuCmpTrigbyData012 == (x))) + +/*!< Parameter valid check for DCU interrupt. */ +#define IS_VALID_DCU_INT(x) \ +( (DcuIntOp == (x)) || \ + (DcuIntLs2 == (x)) || \ + (DcuIntEq2 == (x)) || \ + (DcuIntGt2 == (x)) || \ + (DcuIntLs1 == (x)) || \ + (DcuIntEq1 == (x)) || \ + (DcuIntGt1 == (x))) + +/*!< Parameter valid check for DCU interrupt mode. */ +#define IS_VALID_DCU_INT_WIN_MODE(x) \ +( (DcuIntInvalid == (x)) || \ + (DcuWinIntInvalid == (x)) || \ + (DcuInsideWinCmpInt == (x)) || \ + (DcuOutsideWinCmpInt == (x))) + +/*!< Parameter valid check for external trigger event. */ +#define IS_VALID_TRG_SRC_EVENT(x) \ +( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/*! Parameter valid check for DCU common trigger. */ +#define IS_DCU_COM_TRIGGER(x) \ +( ((x) == DcuComTrigger_1) || \ + ((x) == DcuComTrigger_2) || \ + ((x) == DcuComTrigger_1_2)) + +/*!< Get the specified DATA register address of the specified DCU unit */ +#define DCU_DATAx(__DCUx__, __DATAx__) ((uint32_t)(&(__DCUx__)->DATA0) + ((uint32_t)(__DATAx__)) * 4u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes a DCU. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to DCU configure structure + ** \arg This parameter detail refer @ref stc_dcu_init_t + ** + ** \retval Ok DCU is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - DCUx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx && pstcInitCfg pointer */ + if ((IS_VALID_DCU(DCUx)) && (NULL != pstcInitCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enIntCmd)); + DDL_ASSERT(IS_VALID_DCU_OPERATION(pstcInitCfg->enOperation)); + DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(pstcInitCfg->enDataSize)); + DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(pstcInitCfg->enIntWinMode)); + DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(pstcInitCfg->enCmpTriggerMode)); + + /* De-initialize dcu register value */ + DCUx->CTL = 0ul; + DCUx->INTSEL = 0ul; + DCUx->FLAGCLR = 0x7Ful; + + /* Set dcu operation mode */ + DCUx->CTL_f.MODE = (uint32_t)pstcInitCfg->enOperation; + + /* Set dcu data sieze */ + DCUx->CTL_f.DATASIZE = (uint32_t)pstcInitCfg->enDataSize; + + /* Set dcu compare trigger mode */ + DCUx->CTL_f.COMP_TRG = (uint32_t)pstcInitCfg->enCmpTriggerMode; + + /* Set dcu interrupt window mode */ + DCUx->INTSEL_f.INT_WIN = (uint32_t)pstcInitCfg->enIntWinMode; + + DCUx->INTSEL = pstcInitCfg->u32IntSel; + DCUx->CTL_f.INTEN = (uint32_t)(pstcInitCfg->enIntCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes a DCU. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval Ok De-Initialized successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_DeInit(M4_DCU_TypeDef *DCUx) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* De-initialize dcu register value */ + DCUx->CTL = 0u; + DCUx->INTSEL = 0u; + DCUx->FLAGCLR = 0x7Fu; + *TRGSELx = EVT_MAX; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DCU operation mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enMode DCU operation mode + ** \arg DcuInvalid Invalid + ** \arg DcuOpAdd Operation: Add + ** \arg DcuOpSub Operation: Sub + ** \arg DcuHwTrigOpAdd Operation: Hardware trigger Add + ** \arg DcuHwTrigOpSub Operation: Hardware trigger Sub + ** \arg DcuOpCompare Operation: Compare + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetOperationMode(M4_DCU_TypeDef *DCUx, + en_dcu_operation_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_OPERATION(enMode)); + + DCUx->CTL_f.MODE = (uint32_t)enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU operation mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuInvalid Invalid + ** \retval DcuOpAdd Operation: Add + ** \retval DcuOpSub Operation: Sub + ** \retval DcuHwTrigOpAdd Operation: Hardware trigger Add + ** \retval DcuHwTrigOpSub Operation: Hardware trigger Sub + ** \retval DcuOpCompare Operation: Compare + ** + ******************************************************************************/ +en_dcu_operation_mode_t DCU_GetOperationMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_operation_mode_t)DCUx->CTL_f.MODE; +} + +/** + ******************************************************************************* + ** \brief Set DCU data size. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enSize DCU data size + ** \arg DcuDataBit8 8 bit + ** \arg DcuDataBit16 16 bit + ** \arg DcuDataBit32 32 bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetDataSize(M4_DCU_TypeDef *DCUx, en_dcu_data_size_t enSize) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATAZ_SIZE(enSize)); + + DCUx->CTL_f.DATASIZE = (uint32_t)enSize; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU data size. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuDataBit8 8 bit + ** \retval DcuDataBit16 16 bit + ** \retval DcuDataBit32 32 bit + ** + ******************************************************************************/ +en_dcu_data_size_t DCU_GetDataSize(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_data_size_t)(DCUx->CTL_f.DATASIZE); +} + +/** + ******************************************************************************* + ** \brief Set DCU interrup window. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enIntWinMode Interrupt window mode + ** \arg DcuIntInvalid DCU don't occur interrupt + ** \arg DcuWinIntInvalid DCU window interrupt is invalid. + ** \arg DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2 + ** \arg DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetIntWinMode(M4_DCU_TypeDef *DCUx, + en_dcu_int_win_mode_t enIntWinMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT_WIN_MODE(enIntWinMode)); + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + DCUx->INTSEL_f.INT_WIN = (uint32_t)enIntWinMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU interrup window. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuIntInvalid DCU don't occur interrupt + ** \retval DcuWinIntInvalid DCU window interrupt is invalid. + ** \retval DcuInsideWinCmpInt DCU occur interrupt when DATA2 <= DATA0 <= DATA2 + ** \retval DcuOutsideWinCmpInt DCU occur interrupt when DATA0 > DATA1 or DATA0 < DATA2 + ** + ******************************************************************************/ +en_dcu_int_win_mode_t DCU_GetIntWinMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_int_win_mode_t)(DCUx->INTSEL_f.INT_WIN); +} + +/** + ******************************************************************************* + ** \brief Set DCU compare trigger mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enTriggerMode DCU compare trigger mode + ** \arg DcuCmpTrigbyData0 DCU compare triggered by DATA0 + ** \arg DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetCmpTriggerMode(M4_DCU_TypeDef *DCUx, + en_dcu_cmp_trigger_mode_t enTriggerMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_CMP_TRIG_MODE(enTriggerMode)); + + DCUx->CTL_f.COMP_TRG = (uint32_t)enTriggerMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get DCU compare trigger mode. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DcuCmpTrigbyData0 DCU compare triggered by DATA0 + ** \retval DcuCmpTrigbyData012 DCU compare triggered by DATA0 or DATA1 or DATA2 + ** + ******************************************************************************/ +en_dcu_cmp_trigger_mode_t DCU_GetCmpTriggerMode(M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + + return (en_dcu_cmp_trigger_mode_t)(DCUx->CTL_f.COMP_TRG); +} + +/** + ******************************************************************************* + ** \brief Enable DCU interrupt. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enCmd DCU interrupt state + ** \arg Enable Enable the DCU interrupt function + ** \arg Disable Disable the DCU interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_IrqCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + DCUx->CTL_f.INTEN = (uint32_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the specified DCU flag + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enFlag The specified DCU flag + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enStatus is invalid. + ** + ******************************************************************************/ +en_flag_status_t DCU_GetIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_INT(enFlag)); + + return ((DCUx->FLAG & enFlag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified DCU flag + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enFlag the specified DCU flag + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_ClearIrqFlag(M4_DCU_TypeDef *DCUx, en_dcu_flag_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT(enFlag)); + DCUx->FLAGCLR = (uint32_t)enFlag; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable DCU interrupt. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enIntSel DCU interrupt selection + ** \arg DcuIntOp DCU overflow or underflow + ** \arg DcuIntLs2 DCU DATA0 < DATA2 + ** \arg DcuIntEq2 DCU DATA0 = DATA2 + ** \arg DcuIntGt2 DCU DATA0 > DATA2 + ** \arg DcuIntLs1 DCU DATA0 < DATA1 + ** \arg DcuIntEq1 DCU DATA0 = DATA1 + ** \arg DcuIntGt1 DCU DATA0 > DATA1 + ** \param [in] enCmd DCU interrupt functional state + ** \arg Enable Enable the specified DCU interrupt function + ** \arg Disable Disable the specified DCU interrupt function + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - DCUx is invalid + ** - enIntSel is invalid + ** + ******************************************************************************/ +en_result_t DCU_IrqSelCmd(M4_DCU_TypeDef *DCUx, + en_dcu_int_sel_t enIntSel, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_INT(enIntSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + enRet = Ok; + switch(enIntSel) + { + case DcuIntOp: + DCUx->INTSEL_f.INT_OP = (uint32_t)enCmd; + break; + case DcuIntLs2: + DCUx->INTSEL_f.INT_LS2 = (uint32_t)enCmd; + break; + case DcuIntEq2: + DCUx->INTSEL_f.INT_EQ2 = (uint32_t)enCmd; + break; + case DcuIntGt2: + DCUx->INTSEL_f.INT_GT2 = (uint32_t)enCmd; + break; + case DcuIntLs1: + DCUx->INTSEL_f.INT_LS1 = (uint32_t)enCmd; + break; + case DcuIntEq1: + DCUx->INTSEL_f.INT_EQ1 = (uint32_t)enCmd; + break; + case DcuIntGt1: + DCUx->INTSEL_f.INT_GT1 = (uint32_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint8_t DCU_ReadDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint8_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u8Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataByte(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint8_t u8Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint8_t *)DCU_DATAx(DCUx, enDataReg) = u8Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint16_t DCU_ReadDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint16_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u16Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataHalfWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint16_t u16Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint16_t *)DCU_DATAx(DCUx, enDataReg) = u16Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** + ** \retval DCU register DATAx value + ** + ******************************************************************************/ +uint32_t DCU_ReadDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU(DCUx)); + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + return *(uint32_t *)DCU_DATAx(DCUx, enDataReg); +} + +/** + ******************************************************************************* + ** \brief Write DCU register DATAx + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enDataReg The specified DATA register. + ** \arg DcuRegisterData0 DCU register DATA0 + ** \arg DcuRegisterData1 DCU register DATA1 + ** \arg DcuRegisterData2 DCU register DATA2 + ** \param [in] u32Data The data will be written. + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_WriteDataWord(M4_DCU_TypeDef *DCUx, + en_dcu_data_register_t enDataReg, + uint32_t u32Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for DCUx pointer */ + if (IS_VALID_DCU(DCUx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_DCU_DATA_REG(enDataReg)); + + *(uint32_t *)DCU_DATAx(DCUx, enDataReg) = u32Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set DCU trigger source number + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enTriggerSrc The trigger source. + ** \arg This parameter can be any value of @ref en_event_src_t + ** + ** \retval Ok Write successfully. + ** \retval ErrorInvalidParameter DCUx is invalid + ** + ******************************************************************************/ +en_result_t DCU_SetTriggerSrc(M4_DCU_TypeDef *DCUx, + en_event_src_t enTriggerSrc) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_TRG_SRC_EVENT(enTriggerSrc)); + + *TRGSELx = (*TRGSELx & (~((uint32_t)EVT_MAX))) | (uint32_t)enTriggerSrc; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable DCU common trigger. + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** \param [in] enComTrigger DCU common trigger selection. See @ref en_dcu_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + en_dcu_com_trigger_t enComTrigger, + en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + __IO uint32_t *TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_DCU_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } + } +} + +/** + ******************************************************************************* + ** \brief Get DCU trigger source register address + ** + ** \param [in] DCUx Pointer to DCU instance register base + ** \arg M4_DCU1 DCU unit 1 instance register base + ** \arg M4_DCU2 DCU unit 2 instance register base + ** \arg M4_DCU3 DCU unit 3 instance register base + ** \arg M4_DCU4 DCU unit 4 instance register base + ** + ** \retval DCUx_TRGSEL address DCUx is valid + ** \retval NULL DCUx is invalid + ** + ******************************************************************************/ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx) +{ + __IO uint32_t *TRGSELx = NULL; + + if (M4_DCU1 == DCUx) + { + TRGSELx = &M4_AOS->DCU1_TRGSEL; + } + else if (M4_DCU2 == DCUx) + { + TRGSELx = &M4_AOS->DCU2_TRGSEL; + } + else if (M4_DCU3 == DCUx) + { + TRGSELx = &M4_AOS->DCU3_TRGSEL; + } + else if (M4_DCU4 == DCUx) + { + TRGSELx = &M4_AOS->DCU4_TRGSEL; + } + else + { + TRGSELx = NULL; + } + + return TRGSELx; +} + +//@} // DcuGroup + +#endif /* DDL_DCU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dmac.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dmac.c new file mode 100644 index 0000000000..a4eba02b5b --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_dmac.c @@ -0,0 +1,1827 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_dmac.c + ** + ** A detailed description is available at + ** @link DmacGroup DMAC description @endlink + ** + ** - 2018-11-18 CDT First version for Device Driver Library of DMAC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_dmac.h" +#include "hc32f460_utility.h" + +#if (DDL_DMAC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DmacGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define DMA_CNT (10u) +#define DMA_IDLE (0u) +#define DMA_BUSY (1u) + +#define DMACH0 (0x01u) +#define DMACH1 (0x02u) +#define DMACH2 (0x04u) +#define DMACH3 (0x08u) + +#define DMATIMEOUT1 (0x5000u) +#define DMATIMEOUT2 (0x1000u) + +#define DMA_CHCTL_DEFAULT (0x00001000ul) +#define DMA_DTCTL_DEFAULT (0x00000001ul) +#define DMA_DAR_DEFAULT (0x00000000ul) +#define DMA_SAR_DEFAULT (0x00000000ul) +#define DMA_RPT_DEFAULT (0x00000000ul) +#define DMA_LLP_DEFAULT (0x00000000ul) +#define DMA_SNSEQCTL_DEFAULT (0x00000000ul) +#define DMA_DNSEQCTL_DEFAULT (0x00000000ul) +#define DMA_RCFGCTL_DEFAULT (0x00000000ul) + +/***************** Bits definition for DMA_INTSTAT0 register ****************/ +#define DMA_INTSTAT0_TRNERR_Pos (0U) /*!< DMA_INTSTAT0: TRNERR Position */ +#define DMA_INTSTAT0_REQERR_Pos (16U) /*!< DMA_INTSTAT0: REQERR Position */ + +/***************** Bits definition for DMA_INTSTAT1 register ****************/ +#define DMA_INTSTAT1_TC_Pos (0U) /*!< DMA_INTSTAT1: TC Position */ +#define DMA_INTSTAT1_BTC_Pos (16U) /*!< DMA_INTSTAT1: BTC Position */ + +/***************** Bits definition for DMA_INTMASK0 register ****************/ +#define DMA_INTMASK0_MSKTRNERR_Pos (0U) /*!< DMA_INTMASK0: MSKTRNERR Position */ +#define DMA_INTMASK0_MSKREQERR_Pos (16U) /*!< DMA_INTMASK0: MSKREQERR Position */ + +/***************** Bits definition for DMA_INTMASK1 register ****************/ +#define DMA_INTMASK1_MSKTC_Pos (0U) /*!< DMA_INTMASK1: MSKTC Position */ +#define DMA_INTMASK1_MSKBTC_Pos (16U) /*!< DMA_INTMASK1: MSKBTC Position */ + +/***************** Bits definition for DMA_INTCLR0 register *****************/ +#define DMA_INTCLR0_CLRTRNERR_Pos (0U) /*!< DMA_INTCLR0: CLRTRNERR Position */ +#define DMA_INTCLR0_CLRREQERR_Pos (16U) /*!< DMA_INTCLR0: CLRREQERR Position */ + +/***************** Bits definition for DMA_INTCLR1 register *****************/ +#define DMA_INTCLR1_CLRTC_Pos (0U) /*!< DMA_INTCLR1: CLRTC Position */ +#define DMA_INTCLR1_CLRBTC_Pos (16U) /*!< DMA_INTCLR1: CLRBTC Position */ + +/******************* Bits definition for DMA_CHEN register ******************/ +#define DMA_CHEN_CHEN_Pos (0U) /*!< DMA_CHEN: CHEN Position */ + +/************** Bits definition for DMA_DTCTLx(x=0~3) register **************/ +#define DMA_DTCTL_BLKSIZE_Pos (0ul) /*!< DMA_DTCTLx: BLKSIZE Position */ +#define DMA_DTCTL_BLKSIZE_Msk (0x3FFul << DMA_DTCTL_BLKSIZE_Pos) /*!< DMA_DTCTLx: BLKSIZE Mask 0x000003FF */ +#define DMA_DTCTL_BLKSIZE (DMA_DTCTL_BLKSIZE_Msk) + +#define DMA_DTCTL_CNT_Pos (16ul) /*!< DMA_DTCTLx: CNT Position */ +#define DMA_DTCTL_CNT_Msk (0xFFFFul << DMA_DTCTL_CNT_Pos) /*!< DMA_DTCTLx: CNT Mask 0xFFFF0000 */ +#define DMA_DTCTL_CNT (DMA_DTCTL_CNT_Msk) + +/*************** Bits definition for DMA_RPTx(x=0~3) register ***************/ +#define DMA_RPT_SRPT_Pos (0ul) /*!< DMA_RPTx: SRPT Position */ +#define DMA_RPT_SRPT_Msk (0x3FFul << DMA_RPT_SRPT_Pos) /*!< DMA_RPTx: SRPT Mask 0x000003FF */ +#define DMA_RPT_SRPT (DMA_RPT_SRPT_Msk) + +#define DMA_RPT_DRPT_Pos (16ul) /*!< DMA_RPTx: DRPT Position */ +#define DMA_RPT_DRPT_Msk (0x3FFul << DMA_RPT_DRPT_Pos) /*!< DMA_RPTx: DRPT Mask 0x03FF0000 */ +#define DMA_RPT_DRPT (DMA_RPT_DRPT_Msk) + +/*************** Bits definition for DMA_RPTBx(x=0~3) register ***************/ +#define DMA_RPTB_SRPTB_Pos (0ul) /*!< DMA_RPTBx: SRPTB Position */ +#define DMA_RPTB_SRPTB_Msk (0x3FFul << DMA_RPTB_SRPTB_Pos) /*!< DMA_RPTBx: SRPTB Mask 0x000003FF */ +#define DMA_RPTB_SRPTB (DMA_RPTB_SRPTB_Msk) + +#define DMA_RPTB_DRPTB_Pos (16ul) /*!< DMA_RPTBx: DRPTB Position */ +#define DMA_RPTB_DRPTB_Msk (0x3FFul << DMA_RPTB_DRPTB_Pos) /*!< DMA_RPTBx: DRPTB Mask 0x03FF0000 */ +#define DMA_RPTB_DRPTB (DMA_RPTB_DRPTB_Msk) + +/************* Bits definition for DMA_SNSEQCTLx(x=0~3) register ************/ +#define DMA_SNSEQCTL_SOFFSET_Pos (0ul) /*!< DMA_SNSEQCTLx: SOFFSET Position */ +#define DMA_SNSEQCTL_SOFFSET_Msk (0xFFFFFul << DMA_SNSEQCTL_SOFFSET_Pos) /*!< DMA_SNSEQCTLx: SOFFSET Mask 0x000FFFFF */ +#define DMA_SNSEQCTL_SOFFSET (DMA_SNSEQCTL_SOFFSET_Msk) + +#define DMA_SNSEQCTL_SNSCNT_Pos (20ul) /*!< DMA_SNSEQCTLx: SNSCNT Position */ +#define DMA_SNSEQCTL_SNSCNT_Msk (0xFFFul << DMA_SNSEQCTL_SNSCNT_Pos) /*!< DMA_SNSEQCTLx: SNSCNT Mask 0xFFF00000 */ +#define DMA_SNSEQCTL_SNSCNT (DMA_SNSEQCTL_SNSCNT_Msk) + +/************* Bits definition for DMA_SNSEQCTLBx(x=0~3) register ************/ +#define DMA_SNSEQCTLB_SNSDIST_Pos (0ul) /*!< DMA_SNSEQCTLBx: SNSDIST Position */ +#define DMA_SNSEQCTLB_SNSDIST_Msk (0xFFFFFul << DMA_SNSEQCTLB_SNSDIST_Pos) /*!< DMA_SNSEQCTLBx: SNSDIST Mask 0x000FFFFF */ +#define DMA_SNSEQCTLB_SNSDIST (DMA_SNSEQCTLB_SNSDIST_Msk) + +#define DMA_SNSEQCTLB_SNSCNTB_Pos (20ul) /*!< DMA_SNSEQCTLBx: SNSCNTB Position */ +#define DMA_SNSEQCTLB_SNSCNTB_Msk (0xFFFul << DMA_SNSEQCTLB_SNSCNTB_Pos) /*!< DMA_SNSEQCTLBx: SNSCNTB Mask 0xFFF00000 */ +#define DMA_SNSEQCTLB_SNSCNTB (DMA_SNSEQCTLB_SNSCNTB_Msk) + +/************* Bits definition for DMA_DNSEQCTLx(x=0~3) register ************/ +#define DMA_DNSEQCTL_DOFFSET_Pos (0ul) /*!< DMA_DNSEQCTLx: DOFFSET Position */ +#define DMA_DNSEQCTL_DOFFSET_Msk (0xFFFFFul << DMA_DNSEQCTL_DOFFSET_Pos) /*!< DMA_DNSEQCTLx: DOFFSET Mask 0x000FFFFF */ +#define DMA_DNSEQCTL_DOFFSET (DMA_DNSEQCTL_DOFFSET_Msk) + +#define DMA_DNSEQCTL_DNSCNT_Pos (20ul) /*!< DMA_DNSEQCTLx: DNSCNT Position */ +#define DMA_DNSEQCTL_DNSCNT_Msk (0xFFFul << DMA_DNSEQCTL_DNSCNT_Pos) /*!< DMA_DNSEQCTLx: DNSCNT Mask 0xFFF00000 */ +#define DMA_DNSEQCTL_DNSCNT (DMA_DNSEQCTL_DNSCNT_Msk) + +/************* Bits definition for DMA_DNSEQCTLx(x=0~3) register ************/ +#define DMA_DNSEQCTLB_DNSDIST_Pos (0ul) /*!< DMA_DNSEQCTLBx: DNSDIST Position */ +#define DMA_DNSEQCTLB_DNSDIST_Msk (0xFFFFFul << DMA_DNSEQCTLB_DNSDIST_Pos) /*!< DMA_DNSEQCTLBx: DNSDIST Mask 0x000FFFFF */ +#define DMA_DNSEQCTLB_DNSDIST (DMA_DNSEQCTLB_DNSDIST_Msk) + +#define DMA_DNSEQCTLB_DNSCNTB_Pos (20ul) /*!< DMA_DNSEQCTLBx: DNSCNTB Position */ +#define DMA_DNSEQCTLB_DNSCNTB_Msk (0xFFFul << DMA_DNSEQCTLB_DNSCNTB_Pos) /*!< DMA_DNSEQCTLBx: DNSCNTB Mask 0xFFF00000 */ +#define DMA_DNSEQCTLB_DNSCNTB (DMA_DNSEQCTLB_DNSCNTB_Msk) + +/**************** Bits definition for DMA_LLPx(x=0~7) register **************/ +#define DMA_LLP_LLP_Pos (2ul) /*!< DMA_LLPx: LLP Position */ +#define DMA_LLP_LLP_Msk (0x3FFFFFFFul << DMA_LLP_LLP_Pos) /*!< DMA_LLPx: LLP Mask 0xFFFFFFC */ +#define DMA_LLP_LLP (DMA_LLP_LLP_Msk) + +/*************** Bits definition for DMA_CHxCTL(x=0~3) register *************/ +#define DMA_CHCTL_SINC_Pos (0ul) /*!< DMA_CHxCTL: SINC Position */ +#define DMA_CHCTL_SINC_Msk (0x3ul << DMA_CHCTL_SINC_Pos) /*!< DMA_CHxCTL: SINC Mask 0x00000003 */ +#define DMA_CHCTL_SINC (DMA_CHCTL_SINC_Msk) + +#define DMA_CHCTL_DINC_Pos (2ul) /*!< DMA_CHxCTL: DINC Position */ +#define DMA_CHCTL_DINC_Msk (0x3ul << DMA_CHCTL_DINC_Pos) /*!< DMA_CHxCTL: DINC Mask 0x0000000C */ +#define DMA_CHCTL_DINC (DMA_CHCTL_DINC_Msk) + +#define DMA_CHCTL_SRPTEN_Pos (4ul) /*!< DMA_CHxCTL: SRPTEN Position */ +#define DMA_CHCTL_SRPTEN_Msk (0x1ul << DMA_CHCTL_SRPTEN_Pos) /*!< DMA_CHxCTL: SRPTEN Mask 0x00000010 */ +#define DMA_CHCTL_SRPTEN (DMA_CHCTL_SRPTEN_Msk) + +#define DMA_CHCTL_DRPTEN_Pos (5ul) /*!< DMA_CHxCTL: DRPTEN Position */ +#define DMA_CHCTL_DRPTEN_Msk (0x1ul << DMA_CHCTL_DRPTEN_Pos) /*!< DMA_CHxCTL: DRPTEN Mask 0x00000020 */ +#define DMA_CHCTL_DRPTEN (DMA_CHCTL_DRPTEN_Msk) + +#define DMA_CHCTL_SNSEQEN_Pos (6ul) /*!< DMA_CHxCTL: SNSEQEN Position */ +#define DMA_CHCTL_SNSEQEN_Msk (0x1ul << DMA_CHCTL_SNSEQEN_Pos) /*!< DMA_CHxCTL: SNSEQEN Mask 0x00000040 */ +#define DMA_CHCTL_SNSEQEN (DMA_CHCTL_SNSEQEN_Msk) + +#define DMA_CHCTL_DNSEQEN_Pos (7ul) /*!< DMA_CHxCTL: DNSEQEN Position */ +#define DMA_CHCTL_DNSEQEN_Msk (0x1ul << DMA_CHCTL_DNSEQEN_Pos) /*!< DMA_CHxCTL: DNSEQEN Mask 0x00000080 */ +#define DMA_CHCTL_DNSEQEN (DMA_CHCTL_DNSEQEN_Msk) + +#define DMA_CHCTL_HSIZE_Pos (8ul) /*!< DMA_CHxCTL: HSIZE Position */ +#define DMA_CHCTL_HSIZE_Msk (0x3ul << DMA_CHCTL_HSIZE_Pos) /*!< DMA_CHxCTL: HSIZE Mask 0x00000300 */ +#define DMA_CHCTL_HSIZE (DMA_CHCTL_HSIZE_Msk) + +#define DMA_CHCTL_LLPEN_Pos (10ul) /*!< DMA_CHxCTL: LLPEN Position */ +#define DMA_CHCTL_LLPEN_Msk (0x1ul << DMA_CHCTL_LLPEN_Pos) /*!< DMA_CHxCTL: LLPEN Mask 0x00000400 */ +#define DMA_CHCTL_LLPEN (DMA_CHCTL_LLPEN_Msk) + +#define DMA_CHCTL_LLPRUN_Pos (11ul) /*!< DMA_CHxCTL: LLPRUN Position */ +#define DMA_CHCTL_LLPRUN_Msk (0x1ul << DMA_CHCTL_LLPRUN_Pos) /*!< DMA_CHxCTL: LLPRUN Mask 0x00000800 */ +#define DMA_CHCTL_LLPRUN (DMA_CHCTL_LLPRUN_Msk) + +#define DMA_CHCTL_IE_Pos (12ul) /*!< DMA_CHxCTL: IE Position */ +#define DMA_CHCTL_IE_Msk (0x1ul << DMA_CHCTL_IE_Pos) /*!< DMA_CHxCTL: IE Mask 0x00001000 */ +#define DMA_CHCTL_IE (DMA_CHCTL_IE_Msk) + +/*********************** DMA REGISTERx(x=0~3) register **********************/ +#define _DMA_CH_REG_OFFSET(ch) ((ch) * 0x40ul) +#define _DMA_CH_REG(reg_base, ch) (*(volatile uint32_t *)((uint32_t)(reg_base) + _DMA_CH_REG_OFFSET(ch))) + +#define WRITE_DMA_CH_REG(reg_base, ch, val) (_DMA_CH_REG((reg_base), (ch)) = (val)) +#define READ_DMA_CH_REG(reg_base, ch) (_DMA_CH_REG((reg_base), (ch))) + +#define SET_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) |= (1ul << (pos))) +#define CLR_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) &= (~(1ul << (pos)))) + +#define WRITE_DMA_CH_TRGSEL(reg_base, ch, val) ((*(volatile uint32_t *)((uint32_t)(reg_base) + (ch) * 4ul)) = (val)) + +#define MODIFY_DMA_CH_REG(reg_base, ch, msk, val) {do { \ + WRITE_DMA_CH_REG((reg_base), (ch), ((READ_DMA_CH_REG((reg_base), (ch)) & (~(msk))) | ((val) << (msk##_Pos)))); \ +} while(0);} + +/*! Parameter valid check for Dmac register pointer. */ +#define IS_VALID_DMA_REG(x) \ +( (M4_DMA1 == (x)) || \ + (M4_DMA2 == (x))) + +/*! Parameter valid check for Dmac Channel. */ +#define IS_VALID_CH(x) \ +( (DmaCh0 == (x)) || \ + (DmaCh1 == (x)) || \ + (DmaCh2 == (x)) || \ + (DmaCh3 == (x))) + +/*! Parameter valid check for Dmac irq selection. */ +#define IS_VALID_IRQ_SEL(x) \ +( (TrnErrIrq == (x)) || \ + (TrnReqErrIrq == (x)) || \ + (TrnCpltIrq == (x)) || \ + (BlkTrnCpltIrq == (x))) + +/*! Parameter valid check for Dmac re_config count mode. */ +#define IS_VALID_CNT_MODE(x) \ +( (CntFix == (x)) || \ + (CntSrcAddr == (x)) || \ + (CntDesAddr == (x))) + +/*! Parameter valid check for Dmac re_config source address mode. */ +#define IS_VALID_SADDR_MODE(x) \ +( (SaddrFix == (x)) || \ + (SaddrNseq == (x)) || \ + (SaddrRep == (x))) + +/*! Parameter valid check for Dmac re_config destination address mode. */ +#define IS_VALID_DADDR_MODE(x) \ +( (DaddrFix == (x)) || \ + (DaddrNseq == (x)) || \ + (DaddrRep == (x))) + +/*! Parameter valid check for Dmac status. */ +#define IS_VALID_DMA_STA(x) \ +( (DmaSta == (x)) || \ + (ReCfgSta == (x)) || \ + (DmaCh0Sta == (x)) || \ + (DmaCh1Sta == (x)) || \ + (DmaCh2Sta == (x)) || \ + (DmaCh3Sta == (x))) + +/*! Parameter valid check for Dmac transfer data width. */ +#define IS_VALID_TRN_WIDTH(x) \ +( (Dma8Bit == (x)) || \ + (Dma16Bit == (x)) || \ + (Dma32Bit == (x))) + +/*! Parameter valid check for Dmac address mode. */ +#define IS_VALID_ADDR_MODE(x) \ +( (AddressFix == (x)) || \ + (AddressIncrease == (x)) || \ + (AddressDecrease == (x))) + +/*! Parameter valid check for Dmac link-list-pointer mode. */ +#define IS_VALID_LLP_MODE(x) \ +( (LlpWaitNextReq == (x)) || \ + (LlpRunNow == (x))) + +/*! Parameter validity check for DMA common trigger. */ +#define IS_DMA_COM_TRIGGER(x) \ +( ((x) == DmaComTrigger_1) || \ + ((x) == DmaComTrigger_2) || \ + ((x) == DmaComTrigger_1_2)) + +/*! Parameter valid check for Dmac transfer block size. */ +#define IS_VALID_BLKSIZE(x) \ +( !((x) & (uint16_t)(~(DMA_DTCTL_BLKSIZE_Msk >> DMA_DTCTL_BLKSIZE_Pos)))) + +/*! Parameter valid check for Dmac transfer count. */ +#define IS_VALID_TRNCNT(x) \ +( !((x) & ~(DMA_DTCTL_CNT_Msk >> DMA_DTCTL_CNT_Pos))) + +/*! Parameter valid check for Dmac source repeat size. */ +#define IS_VALID_SRPT_SIZE(x) \ +( !((x) & ~(DMA_RPT_SRPT_Msk >> DMA_RPT_SRPT_Pos))) + +/*! Parameter valid check for Dmac destination repeat size. */ +#define IS_VALID_DRPT_SIZE(x) \ +( !((x) & ~(DMA_RPT_DRPT_Msk >> DMA_RPT_DRPT_Pos))) + +/*! Parameter valid check for Dmac source repeatB size. */ +#define IS_VALID_SRPTB_SIZE(x) \ +( !((x) & ~(DMA_RPTB_SRPTB_Msk >> DMA_RPTB_SRPTB_Pos))) + +/*! Parameter valid check for Dmac destinationB repeat size. */ +#define IS_VALID_DRPTB_SIZE(x) \ +( !((x) & ~(DMA_RPTB_DRPTB_Msk >> DMA_RPTB_DRPTB_Pos))) + +/*! Parameter valid check for Dmac source no-sequence count. */ +#define IS_VALID_SNSCNT(x) \ +( !((x) & ~(DMA_SNSEQCTL_SNSCNT_Msk >> DMA_SNSEQCTL_SNSCNT_Pos))) + +/*! Parameter valid check for Dmac source no-sequence offset. */ +#define IS_VALID_SNSOFFSET(x) \ +( !((x) & ~(DMA_SNSEQCTL_SOFFSET_Msk >> DMA_SNSEQCTL_SOFFSET_Pos))) + +/*! Parameter valid check for Dmac source no-sequence countB. */ +#define IS_VALID_SNSCNTB(x) \ +( !((x) & ~(DMA_SNSEQCTLB_SNSCNTB_Msk >> DMA_SNSEQCTLB_SNSCNTB_Pos))) + +/*! Parameter valid check for Dmac source no-sequence distance. */ +#define IS_VALID_SNSDIST(x) \ +( !((x) & ~(DMA_SNSEQCTLB_SNSDIST_Msk >> DMA_SNSEQCTLB_SNSDIST_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence count. */ +#define IS_VALID_DNSCNT(x) \ +( !((x) & ~(DMA_DNSEQCTL_DNSCNT_Msk >> DMA_DNSEQCTL_DNSCNT_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence offset. */ +#define IS_VALID_DNSOFFSET(x) \ +( !((x) & ~(DMA_DNSEQCTL_DOFFSET_Msk >> DMA_DNSEQCTL_DOFFSET_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence countB. */ +#define IS_VALID_DNSCNTB(x) \ +( !((x) & ~(DMA_DNSEQCTLB_DNSCNTB_Msk >> DMA_DNSEQCTLB_DNSCNTB_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence distance. */ +#define IS_VALID_DNSDIST(x) \ +( !((x) & ~(DMA_DNSEQCTLB_DNSDIST_Msk >> DMA_DNSEQCTLB_DNSDIST_Pos))) + +/*! Parameter valid check for Dmac link-list-pointer. */ +#define IS_VALID_LLP(x) (!((x) & ~DMA_LLP_LLP_Msk)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static volatile uint8_t DmaChEnState = DMA_IDLE; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Enable or disable the dma. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->EN_f.EN = enNewState; +} + +/** + ******************************************************************************* + ** \brief Enable the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Interrupt enabled normally. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, + uint8_t u8Ch, + en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTMASK0 &= ~(1ul << (u8Ch + DMA_INTMASK0_MSKTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTMASK0 &= ~(1ul << (u8Ch + DMA_INTMASK0_MSKREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTMASK1 &= ~(1ul << (u8Ch + DMA_INTMASK1_MSKTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTMASK1 &= ~(1ul << (u8Ch + DMA_INTMASK1_MSKBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Interrupt disabled normally. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, + uint8_t u8Ch, + en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTMASK0 |= (1ul << (u8Ch + DMA_INTMASK0_MSKTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTMASK0 |= (1ul << (u8Ch + DMA_INTMASK0_MSKREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTMASK1 |= (1ul << (u8Ch + DMA_INTMASK1_MSKTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTMASK1 |= (1ul << (u8Ch + DMA_INTMASK1_MSKBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the specified dma interrupt flag status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval the specified dma flag status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + switch(enIrqSel) + { + case TrnErrIrq: + u32IntStat = (pstcDmaReg->INTSTAT0 & (1ul << (u8Ch \ + + DMA_INTSTAT0_TRNERR_Pos))); + break; + case TrnReqErrIrq: + u32IntStat = (pstcDmaReg->INTSTAT0 & (1ul << (u8Ch \ + + DMA_INTSTAT0_REQERR_Pos))); + break; + case TrnCpltIrq: + u32IntStat = (pstcDmaReg->INTSTAT1 & (1ul << (u8Ch \ + + DMA_INTSTAT1_TC_Pos))); + break; + case BlkTrnCpltIrq: + u32IntStat = (pstcDmaReg->INTSTAT1 & (1ul << (u8Ch \ + + DMA_INTSTAT1_BTC_Pos))); + break; + default: + break; + } + + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified dma interrupt. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enIrqSel The specified dma flag. + ** \arg TrnErrIrq The DMA transfer error interrupt. + ** \arg TrnReqErrIrq DMA transfer req over error interrupt. + ** \arg TrnCpltIrq DMA transfer completion interrupt. + ** \arg BlkTrnCpltIrq DMA block completion interrupt. + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter u8Ch or enIrqSel is invalid. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + + if(!IS_VALID_CH(u8Ch)) + { + enRet = ErrorInvalidParameter; + } + else + { + switch(enIrqSel) + { + case TrnErrIrq: + pstcDmaReg->INTCLR0 |= (1ul << (u8Ch + DMA_INTCLR0_CLRTRNERR_Pos)); + break; + case TrnReqErrIrq: + pstcDmaReg->INTCLR0 |= (1ul << (u8Ch + DMA_INTCLR0_CLRREQERR_Pos)); + break; + case TrnCpltIrq: + pstcDmaReg->INTCLR1 |= (1ul << (u8Ch + DMA_INTCLR1_CLRTC_Pos)); + break; + case BlkTrnCpltIrq: + pstcDmaReg->INTCLR1 |= (1ul << (u8Ch + DMA_INTCLR1_CLRBTC_Pos)); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState) +{ + uint16_t u16Timeout = 0u; + uint32_t u32Temp = 0u; + uint32_t u32Cnt; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(DMA_IDLE == DmaChEnState) + { + DmaChEnState = DMA_BUSY; + + /* Read back channel enable register except current channel */ + u32Temp = (pstcDmaReg->CHEN & (~(1ul << u8Ch))); + if(0ul != u32Temp) + { + if(((pstcDmaReg->CHEN & 0x01ul) == 0x01ul) && (u8Ch != DmaCh0)) + { + u32Cnt = pstcDmaReg->DTCTL0_f.CNT; + if(pstcDmaReg->MONDTCTL0_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL0_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x01ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x02ul) == 0x02ul) && (u8Ch != DmaCh1)) + { + u32Cnt = pstcDmaReg->DTCTL1_f.CNT; + if(pstcDmaReg->MONDTCTL1_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL1_f.CNT < u32Cnt) + { + u16Timeout = 0u; + while(Reset != (pstcDmaReg->CHEN & 0x02ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x04ul) == 0x04ul) && (u8Ch != DmaCh2)) + { + u16Timeout = 0u; + u32Cnt = pstcDmaReg->DTCTL2_f.CNT; + if(pstcDmaReg->MONDTCTL2_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL2_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x04ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + if(((pstcDmaReg->CHEN & 0x08ul) == 0x08ul) && (u8Ch != DmaCh3)) + { + u16Timeout = 0u; + u32Cnt = pstcDmaReg->DTCTL3_f.CNT; + if(pstcDmaReg->MONDTCTL3_f.CNT > DMA_CNT) + { + /* not wait. */ + } + else if(pstcDmaReg->MONDTCTL3_f.CNT < u32Cnt) + { + while(Reset != (pstcDmaReg->CHEN & 0x08ul)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT1) + { + DmaChEnState = DMA_IDLE; + return ErrorTimeout; + } + } + } + } + } + + switch(enNewState) + { + case Enable: + pstcDmaReg->CHEN |= (1ul << (u8Ch + DMA_CHEN_CHEN_Pos)) & 0x0fu; + break; + case Disable: + pstcDmaReg->CHEN &= (~(1ul << (u8Ch + DMA_CHEN_CHEN_Pos))) & 0x0fu; + break; + } + + DmaChEnState = DMA_IDLE; + return Ok; + } + + return Error; +} + +/** + ******************************************************************************* + ** \brief DMA repeat & non_sequence Re_Config control configuration. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDmaReCfg The configuration struct of DMA. + ** \arg u16SrcRptBSize The source repeat size. + ** \arg u16SrcRptBSize; The source repeat size. + ** \arg u16DesRptBSize; The destination repeat size. + ** \arg enSaddrMd; DMA re_config source address mode. + ** \arg enDaddrMd; DMA re_config destination address mode. + ** \arg enCntMd; DMA re_config count mode. + ** \arg stcSrcNseqBCfg; The source no_sequence re_config. + ** \arg stcDesNseqBCfg; The destination no_sequence re_config. + ** + ** \retval None + ** + ** \note This function should be used while DMA disable. + ** + ******************************************************************************/ +void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_recfg_ctl_t* pstcDmaReCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_CNT_MODE(pstcDmaReCfg->enCntMd)); + DDL_ASSERT(IS_VALID_DADDR_MODE(pstcDmaReCfg->enDaddrMd)); + DDL_ASSERT(IS_VALID_SADDR_MODE(pstcDmaReCfg->enSaddrMd)); + + pstcDmaReg->RCFGCTL_f.SARMD = pstcDmaReCfg->enSaddrMd; + pstcDmaReg->RCFGCTL_f.DARMD = pstcDmaReCfg->enDaddrMd; + pstcDmaReg->RCFGCTL_f.CNTMD = pstcDmaReCfg->enCntMd; + pstcDmaReg->RCFGCTL_f.RCFGCHS = u8Ch; + + if(SaddrRep == pstcDmaReCfg->enSaddrMd) + { + /* Set DMA source repeat size B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPT_SRPT, (uint32_t)pstcDmaReCfg->u16SrcRptBSize); + } + else if(SaddrNseq == pstcDmaReCfg->enSaddrMd) + { + /* Set DMA source no_sequence B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTL_SOFFSET, pstcDmaReCfg->stcSrcNseqBCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcDmaReCfg->stcSrcNseqBCfg.u16Cnt); + } + else + { + /* */ + } + + if(DaddrRep == pstcDmaReCfg->enDaddrMd) + { + /* Set DMA destination repeat size B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPT_DRPT, (uint32_t)pstcDmaReCfg->u16DesRptBSize); + } + else if(DaddrNseq == pstcDmaReCfg->enDaddrMd) + { + /* Set DMA destination no_sequence B. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDmaReCfg->stcDesNseqBCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDmaReCfg->stcDesNseqBCfg.u16Cnt); + } + else + { + /* */ + } +} + +/** + ******************************************************************************* + ** \brief Disable or enable DMA Re_Config. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->RCFGCTL_f.RCFGEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief Configure DMA Re_Config LLP. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] u8Ch The specified dma channel. + ** + ** \param [in] enNewState The new state of dma + ** \arg Enable Enable dma. + ** \arg Disable Disable dma. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ReCfgLlp(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcDmaReg->RCFGCTL_f.RCFGCHS = u8Ch; + pstcDmaReg->RCFGCTL_f.RCFGLLP = enNewState; +} + +/** + ******************************************************************************* + ** \brief Get the specified dma flag status. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 register + ** \arg M4_DMA2 DMAC unit 2 register + ** + ** \param [in] enDmaChFlag The specified dma flag. + ** \arg DmaSta The DMA status. + ** \arg ReCfgSta The DMA re_config stauts. + ** \arg DmaCh0Sta The DMA channel 0 status. + ** \arg DmaCh1Sta The DMA channel 1 status. + ** \arg DmaCh2Sta The DMA channel 2 status. + ** \arg DmaCh3Sta The DMA channel 3 status. + ** + ** \retval the specified dma flag status + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag) +{ + uint32_t u32IntStat = 0ul; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_DMA_STA(enDmaChFlag)); + + switch(enDmaChFlag) + { + case DmaSta: + u32IntStat = pstcDmaReg->CHSTAT_f.DMAACT; + break; + case ReCfgSta: + u32IntStat = pstcDmaReg->CHSTAT_f.RCFGACT; + break; + case DmaCh0Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH0); + break; + case DmaCh1Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH1); + break; + case DmaCh2Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH2); + break; + case DmaCh3Sta: + u32IntStat = (pstcDmaReg->CHSTAT_f.CHACT & DMACH3); + break; + default: + break; + } + return (u32IntStat ? Set:Reset); +} + +/** + ******************************************************************************* + ** \brief Set the source address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Address The source address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, u32Address); + + /* Ensure the address has been writed */ + while(u32Address != READ_DMA_CH_REG(&pstcDmaReg->MONSAR0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, u32Address); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination address of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 DMAC unit 2 registers + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Address The destination address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, u32Address); + + /* Ensure the address has been writed */ + while(u32Address != READ_DMA_CH_REG(&pstcDmaReg->MONDAR0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, u32Address); + } + } + + return enRet; + +} + + +/** + ******************************************************************************* + ** \brief Set the block size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16BlkSize The block size. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_BLKSIZE(u16BlkSize)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)u16BlkSize); + + /* Ensure the block size has been writed */ + while(u16BlkSize != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_BLKSIZE)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)u16BlkSize); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the transfer count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16TrnCnt The transfer count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_TRNCNT(u16TrnCnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)u16TrnCnt); + + /* Ensure the transfer count has been writed */ + while(u16TrnCnt != ((READ_DMA_CH_REG(&pstcDmaReg->MONDTCTL0, u8Ch) & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)u16TrnCnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The source repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SRPT_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)u16Size); + + /* Ensure the source repeat size has been writed */ + while(u16Size != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_SRPT)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The destination repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DRPT_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)u16Size); + + /* Ensure the destination repeat size has been writed */ + while(u16Size != ((READ_DMA_CH_REG(&pstcDmaReg->MONRPT0, u8Ch) & DMA_RPT_DRPT) >> DMA_RPT_DRPT_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)u16Size); + } + } + + return enRet; +} + + +/** + ******************************************************************************* + ** \brief Set the source repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The source repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SRPTB_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_SRPTB, (uint32_t)u16Size); + + /* Ensure the source repeat size has been writed */ + while(u16Size != (uint16_t)(READ_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch) & DMA_RPTB_SRPTB)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_SRPTB, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination repeat size of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u16Size The destination repeat size. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesRptBSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DRPTB_SIZE(u16Size)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_DRPTB, (uint32_t)u16Size); + + /* Ensure the destination repeat size has been writed */ + while(u16Size != ((READ_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch) & DMA_RPTB_DRPTB) >> DMA_RPTB_DRPTB_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->RPTB0, u8Ch, DMA_RPTB_DRPTB, (uint32_t)u16Size); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcSrcNseqCfg + ** \arg u32offset The source no-sequence offset. + ** \arg u16cnt The source no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseq_cfg_t* pstcSrcNseqCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SNSOFFSET(pstcSrcNseqCfg->u32Offset)); + DDL_ASSERT(IS_VALID_SNSCNT(pstcSrcNseqCfg->u16Cnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SOFFSET, pstcSrcNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcSrcNseqCfg->u16Cnt); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcSrcNseqCfg->u32Offset | ((uint32_t)pstcSrcNseqCfg->u16Cnt << DMA_SNSEQCTL_SNSCNT_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->MONSNSEQCTL0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SOFFSET, pstcSrcNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, + DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcSrcNseqCfg->u16Cnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the source no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcSrcNseqBCfg + ** \arg u32NseqDist The source no-sequence distance. + ** \arg u16cntB The source no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_SNSDIST(pstcSrcNseqBCfg->u32NseqDist)); + DDL_ASSERT(IS_VALID_SNSCNTB(pstcSrcNseqBCfg->u16CntB)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTLB_SNSDIST, pstcSrcNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, DMA_SNSEQCTLB_SNSCNTB, (uint32_t)pstcSrcNseqBCfg->u16CntB); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcSrcNseqBCfg->u32NseqDist | ((uint32_t)pstcSrcNseqBCfg->u16CntB << DMA_SNSEQCTLB_SNSCNTB_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, + DMA_SNSEQCTLB_SNSDIST, pstcSrcNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTLB0, u8Ch, + DMA_SNSEQCTLB_SNSCNTB, (uint32_t)pstcSrcNseqBCfg->u16CntB); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDesNseqCfg + ** \arg u32offset The destination no-sequence offset. + ** \arg u16cnt The destination no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseq_cfg_t* pstcDesNseqCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DNSOFFSET(pstcDesNseqCfg->u32Offset)); + DDL_ASSERT(IS_VALID_DNSCNT(pstcDesNseqCfg->u16Cnt)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDesNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDesNseqCfg->u16Cnt); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcDesNseqCfg->u32Offset | ((uint32_t)pstcDesNseqCfg->u16Cnt << DMA_DNSEQCTL_DNSCNT_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->MONDNSEQCTL0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, + DMA_DNSEQCTL_DOFFSET, pstcDesNseqCfg->u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, + DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDesNseqCfg->u16Cnt); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the destination no-sequence offset & count of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDesNseqBCfg + ** \arg u32offset The destination no-sequence offset. + ** \arg u16cnt The destination no-sequence count. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_nseqb_cfg_t* pstcDesNseqBCfg) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_DNSDIST(pstcDesNseqBCfg->u32NseqDist)); + DDL_ASSERT(IS_VALID_DNSCNTB(pstcDesNseqBCfg->u16CntB)); + + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTLB_DNSDIST, pstcDesNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, DMA_DNSEQCTLB_DNSCNTB, (uint32_t)pstcDesNseqBCfg->u16CntB); + + /* Ensure the no-sequence offset & count has been writed */ + while((pstcDesNseqBCfg->u32NseqDist | ((uint32_t)pstcDesNseqBCfg->u16CntB << DMA_DNSEQCTLB_DNSCNTB_Pos)) + != READ_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, + DMA_DNSEQCTLB_DNSDIST, pstcDesNseqBCfg->u32NseqDist); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTLB0, u8Ch, + DMA_DNSEQCTLB_DNSCNTB, (uint32_t)pstcDesNseqBCfg->u16CntB); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set linked list pointer of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] u32Pointer The decriptor pointer. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer) +{ + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_LLP(u32Pointer)); + + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, u32Pointer); + + /* Ensure the destination repeat size has been writed */ + while(u32Pointer != ((READ_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch) & DMA_LLP_LLP) >> DMA_LLP_LLP_Pos)) + { + u16Timeout++; + if(u16Timeout > DMATIMEOUT2) + { + enRet = ErrorTimeout; + } + else + { + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, u32Pointer); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set The DMA trigger source. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enSrc The DMA trigger source. + ** + ** \retval None. + ** + ** \note Before call this function, shoud ensure enable AOS. + ** + ******************************************************************************/ +void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + + if(M4_DMA1 == pstcDmaReg) + { + WRITE_DMA_CH_TRGSEL(&M4_AOS->DMA1_TRGSEL0,u8Ch,enSrc); + } + else if(M4_DMA2 == pstcDmaReg) + { + WRITE_DMA_CH_TRGSEL(&M4_AOS->DMA2_TRGSEL0,u8Ch,enSrc); + } + else + { + //else + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable DMA common trigger.. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** \param [in] u8Ch The specified dma channel. + ** \param [in] enComTrigger DMA common trigger selection. + ** \arg DmaComTrigger_1 + ** \arg DmaComTrigger_2 + ** \arg DmaComTrigger_1_2 + ** \param [in] enNewState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState) +{ + __IO uint32_t *TRGSELx; + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_DMA_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (M4_DMA1 == pstcDmaReg) + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA1_TRGSEL0) + u8Ch*4UL); + } + else + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA2_TRGSEL0) + u8Ch*4UL); + } + + if (Enable == enNewState) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable DMA re-config common trigger.. + ** + ** \param [in] enComTrigger DMA common trigger selection. + ** \arg DmaComTrigger_1 + ** \arg DmaComTrigger_2 + ** \arg DmaComTrigger_1_2 + ** \param [in] enNewState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_DMA_COM_TRIGGER(enComTrigger)); + + if (Enable == enNewState) + { + M4_AOS->DMA_TRGSELRC |= (u32ComTrig << 30u); + } + else + { + M4_AOS->DMA_TRGSELRC &= ~(u32ComTrig << 30u); + } +} +/** + ******************************************************************************* + ** \brief Set linked list pointer of the specified dma channel. + ** + ** \param [in] enSrc The DMA trigger source. + ** + ** \retval None. + ** + ** \note Before call this function, should ensure enable AOS. + ** + ******************************************************************************/ +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc) +{ + + M4_AOS->DMA_TRGSELRC_f.TRGSEL = enSrc; + +} +/** + ******************************************************************************* + ** \brief The configuration of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcChCfg The configuration pointer. + ** \arg enSrcInc The source address mode. + ** \arg enDesInc The destination address mode. + ** \arg enSrcRptEn The source repeat function(enable or disable). + ** \arg enDesRptEn The destination repeat function(enable or disable). + ** \arg enSrcNseqEn The source no_sequence function(enable or disable). + ** \arg enDesNseqEn The destination no_sequence function(enable or disable). + ** \arg enTrnWidth The transfer data width. + ** \arg enLlpEn The linked list pointer function(enable or disable). + ** \arg enLlpMd The linked list pointer mode. + ** \arg enIntEn The interrupt function(enable or disable). + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_ch_cfg_t* pstcChCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_ADDR_MODE(pstcChCfg->enSrcInc)); + DDL_ASSERT(IS_VALID_ADDR_MODE(pstcChCfg->enDesInc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enSrcRptEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enDesRptEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enSrcNseqEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enDesNseqEn)); + DDL_ASSERT(IS_VALID_TRN_WIDTH(pstcChCfg->enTrnWidth)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enLlpEn)); + DDL_ASSERT(IS_VALID_LLP_MODE(pstcChCfg->enLlpMd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcChCfg->enIntEn)); + + /* Set the source address mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SINC, pstcChCfg->enSrcInc); + /* Set the destination address mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DINC, pstcChCfg->enDesInc); + /* Enable or disable source repeat function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SRPTEN, pstcChCfg->enSrcRptEn); + /* Enable or disable destination repeat function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DRPTEN, pstcChCfg->enDesRptEn); + /* Enable or disable source no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_SNSEQEN, pstcChCfg->enSrcNseqEn); + /* Enable or disable destination no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DNSEQEN, pstcChCfg->enDesNseqEn); + /* Set the transfer data width. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_HSIZE, pstcChCfg->enTrnWidth); + /* Enable or disable linked list pointer no_sequence function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_LLPEN, pstcChCfg->enLlpEn); + /* Set the linked list pointer mode. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_LLPRUN, pstcChCfg->enLlpMd); + /* Enable or disable channel interrupt function. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_IE, pstcChCfg->enIntEn); +} + +/** + ******************************************************************************* + ** \brief The configuration of the specified dma channel. + ** + ** \param [in] pstcDmaReg The pointer to dma register + ** \arg M4_DMA1 DMAC unit 1 registers + ** \arg M4_DMA2 + ** + ** \param [in] u8Ch The specified dma channel. + ** \param [in] pstcDmaCfg The configuration pointer. + ** \arg enSrcInc The source address mode. + ** \arg enDesInc The destination address mode. + ** \arg enSrcRptEn The source repeat function(enable or disable). + ** \arg enDesRptEn The destination repeat function(enable or disable). + ** \arg enSrcNseqEn The source no_sequence function(enable or disable). + ** \arg enDesNseqEn The destination no_sequence function(enable or disable). + ** \arg enTrnWidth The transfer data width. + ** \arg enLlpEn The linked list pointer function(enable or disable). + ** \arg enLlpMd The linked list pointer mode. + ** \arg enIntEn The interrupt function(enable or disable). + ** + ** \retval None. + ** + ** \note This function should be used after enable DMAx clk(PWC_Fcg0PeriphClockCmd) + ** and before channel enable. + ** + ******************************************************************************/ +void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, + const stc_dma_config_t* pstcDmaCfg) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + DDL_ASSERT(IS_VALID_BLKSIZE(pstcDmaCfg->u16BlockSize)); + DDL_ASSERT(IS_VALID_TRNCNT(pstcDmaCfg->u16TransferCnt)); + DDL_ASSERT(IS_VALID_SRPT_SIZE(pstcDmaCfg->u16SrcRptSize)); + DDL_ASSERT(IS_VALID_DRPT_SIZE(pstcDmaCfg->u16DesRptSize)); + + /* Enable DMA. */ + DMA_Cmd(pstcDmaReg, Enable); + /* Disable DMA interrupt */ + CLR_DMA_CH_REG_BIT(&pstcDmaReg->CH0CTL , u8Ch, DMA_CHCTL_IE_Pos); + /* Set DMA source address. */ + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, pstcDmaCfg->u32SrcAddr); + /* Set DMA destination address. */ + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, pstcDmaCfg->u32DesAddr); + /* Set DMA transfer block size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_BLKSIZE, (uint32_t)pstcDmaCfg->u16BlockSize); + /* Set DMA transfer count. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_CNT, (uint32_t)pstcDmaCfg->u16TransferCnt); + /* Set DMA source repeat size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_SRPT, (uint32_t)pstcDmaCfg->u16SrcRptSize); + /* Set DMA destination repeat size. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DRPT, (uint32_t)pstcDmaCfg->u16DesRptSize); + /* Set DMA source no_sequence. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_SOFFSET, pstcDmaCfg->stcSrcNseqCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_SNSCNT, (uint32_t)pstcDmaCfg->stcSrcNseqCfg.u16Cnt); + /* Set DMA destination no_sequence. */ + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DOFFSET, pstcDmaCfg->stcDesNseqCfg.u32Offset); + MODIFY_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DNSCNT, (uint32_t)pstcDmaCfg->stcDesNseqCfg.u16Cnt); + /* Set DMA linked list pointer. */ + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, pstcDmaCfg->u32DmaLlp); + /* Set DMA channel parameter. */ + DMA_ChannelCfg(pstcDmaReg, u8Ch, &pstcDmaCfg->stcDmaChCfg); +} + +void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch) +{ + DDL_ASSERT(IS_VALID_DMA_REG(pstcDmaReg)); + DDL_ASSERT(IS_VALID_CH(u8Ch)); + + /* reset dma channel */ + WRITE_DMA_CH_REG(&pstcDmaReg->CH0CTL, u8Ch, DMA_CHCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DTCTL0, u8Ch, DMA_DTCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DAR0, u8Ch, DMA_DAR_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->SAR0, u8Ch, DMA_SAR_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->SNSEQCTL0, u8Ch, DMA_SNSEQCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->DNSEQCTL0, u8Ch, DMA_DNSEQCTL_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->RPT0, u8Ch, DMA_RPT_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->LLP0, u8Ch, DMA_LLP_DEFAULT); + WRITE_DMA_CH_REG(&pstcDmaReg->RCFGCTL, u8Ch, DMA_RCFGCTL_DEFAULT); + + /* Set trigger source event max */ + DMA_SetTriggerSrc(pstcDmaReg, u8Ch, EVT_MAX); + /* disable channel */ + DMA_ChannelCmd(pstcDmaReg, u8Ch, Disable); +} + +#endif /* DDL_DMAC_ENABLE */ + +//@} // DmacGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_efm.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_efm.c new file mode 100644 index 0000000000..4625f3d391 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_efm.c @@ -0,0 +1,942 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_efm.c + ** + ** A detailed description is available at + ** @link EfmGroup EFM description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of EFM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_efm.h" +#include "hc32f460_utility.h" + +#if (DDL_EFM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EfmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define EFM_LOCK (0x00000000u) +#define EFM_UNLOCK (0x00000001u) +#define EFM_KEY1 (0x0123ul) +#define EFM_KEY2 (0x3210ul) + +#define EFM_PROTECT_ADDR_MSK (0x000FFFFFu) + +/* Parameter validity check for pointer. */ +#define IS_VALID_POINTER(x) (NULL != (x)) + +/* Parameter validity check for flash latency. */ +#define IS_VALID_FLASH_LATENCY(x) \ +( ((x) == EFM_LATENCY_0) || \ + ((x) == EFM_LATENCY_1) || \ + ((x) == EFM_LATENCY_2) || \ + ((x) == EFM_LATENCY_3) || \ + ((x) == EFM_LATENCY_4) || \ + ((x) == EFM_LATENCY_5) || \ + ((x) == EFM_LATENCY_6) || \ + ((x) == EFM_LATENCY_7) || \ + ((x) == EFM_LATENCY_8) || \ + ((x) == EFM_LATENCY_9) || \ + ((x) == EFM_LATENCY_10) || \ + ((x) == EFM_LATENCY_11) || \ + ((x) == EFM_LATENCY_12) || \ + ((x) == EFM_LATENCY_13) || \ + ((x) == EFM_LATENCY_14) || \ + ((x) == EFM_LATENCY_15)) + +/* Parameter validity check for read mode. */ +#define IS_VALID_READ_MD(MD) \ +( ((MD) == NormalRead) || \ + ((MD) == UltraPowerRead)) + +/* Parameter validity check for erase/program mode. */ +#define IS_VALID_ERASE_PGM_MD(MD) \ +( ((MD) == EFM_MODE_READONLY) || \ + ((MD) == EFM_MODE_SINGLEPROGRAM) || \ + ((MD) == EFM_MODE_SINGLEPROGRAMRB) || \ + ((MD) == EFM_MODE_SEQUENCEPROGRAM) || \ + ((MD) == EFM_MODE_SECTORERASE) || \ + ((MD) == EFM_MODE_CHIPERASE)) + +/* Parameter validity check for flash flag. */ +#define IS_VALID_FLASH_FLAG(flag) \ +( ((flag) == EFM_FLAG_WRPERR) || \ + ((flag) == EFM_FLAG_PEPRTERR) || \ + ((flag) == EFM_FLAG_PGSZERR) || \ + ((flag) == EFM_FLAG_PGMISMTCH) || \ + ((flag) == EFM_FLAG_EOP) || \ + ((flag) == EFM_FLAG_COLERR) || \ + ((flag) == EFM_FLAG_RDY)) + +/* Parameter validity check for flash clear flag. */ +#define IS_VALID_CLEAR_FLASH_FLAG(flag) \ +( ((flag) == EFM_FLAG_WRPERR) || \ + ((flag) == EFM_FLAG_PEPRTERR) || \ + ((flag) == EFM_FLAG_PGSZERR) || \ + ((flag) == EFM_FLAG_PGMISMTCH) || \ + ((flag) == EFM_FLAG_EOP) || \ + ((flag) == EFM_FLAG_COLERR)) + +/* Parameter validity check for flash interrupt. */ +#define IS_VALID_EFM_INT_SEL(int) \ +( ((int) == PgmErsErrInt) || \ + ((int) == EndPgmInt) || \ + ((int) == ColErrInt)) + +/* Parameter validity check for flash address. */ +#define IS_VALID_FLASH_ADDR(addr) \ +( ((addr) == 0x00000000u) || \ + (((addr) >= 0x00000001u) && \ + ((addr) <= 0x0007FFDFu))) + +/* Parameter validity check for flash address. */ +#define IS_VALID_OTP_LOCK_ADDR(addr) \ +( ((addr) >= 0x03000FC0u) || \ + ((addr) <= 0x03000FF8u)) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Unlock the flash. + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_Unlock(void) +{ + M4_EFM->FAPRT = EFM_KEY1; + M4_EFM->FAPRT = EFM_KEY2; +} + +/** + ******************************************************************************* + ** \brief Lock the flash. + ** + ** \param None + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_Lock(void) +{ + if(EFM_UNLOCK == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = EFM_KEY2; + M4_EFM->FAPRT = EFM_KEY2; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the flash. + ** + ** \param [in] enNewState The new state of the flash. + ** \arg Enable Enable flash. + ** \arg Disable Stop flash. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_FlashCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FSTP_f.FSTP = ((Enable == enNewState) ? 0ul : 1ul); +} +/** + ******************************************************************************* + ** \brief Sets the code latency value.. + ** + ** \param [in] u32Latency specifies the FLASH Latency value. + ** \arg EFM_LATENCY_0 FLASH 0 Latency cycle + ** \arg EFM_LATENCY_1 FLASH 1 Latency cycle + ** \arg EFM_LATENCY_2 FLASH 2 Latency cycles + ** \arg EFM_LATENCY_3 FLASH 3 Latency cycles + ** \arg EFM_LATENCY_4 FLASH 4 Latency cycles + ** \arg EFM_LATENCY_5 FLASH 5 Latency cycles + ** \arg EFM_LATENCY_6 FLASH 6 Latency cycles + ** \arg EFM_LATENCY_7 FLASH 7 Latency cycles + ** \arg EFM_LATENCY_8 FLASH 8 Latency cycles + ** \arg EFM_LATENCY_9 FLASH 9 Latency cycles + ** \arg EFM_LATENCY_10 FLASH 10 Latency cycles + ** \arg EFM_LATENCY_11 FLASH 11 Latency cycles + ** \arg EFM_LATENCY_12 FLASH 12 Latency cycles + ** \arg EFM_LATENCY_13 FLASH 13 Latency cycles + ** \arg EFM_LATENCY_14 FLASH 14 Latency cycles + ** \arg EFM_LATENCY_15 FLASH 15 Latency cycles + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetLatency(uint32_t u32Latency) +{ + DDL_ASSERT(IS_VALID_FLASH_LATENCY(u32Latency)); + + M4_EFM->FRMC_f.FLWT = u32Latency; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the flash instruction cache. + ** + ** \param [in] enNewState The new state of the flash instruction cache. + ** \arg Enable Enable flash instruction cache. + ** \arg Disable Disable flash instruction cache. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_InstructionCacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FRMC_f.CACHE = enNewState; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the data cache reset. + ** + ** \param [in] enNewState The new state of the data cache reset. + ** \arg Enable Enable data cache reset. + ** \arg Disable Disable data cache reset. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_DataCacheRstCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FRMC_f.CRST = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the flash read mode. + ** + ** \param [in] enReadMD The flash read mode. + ** \arg NormalRead Normal read mode. + ** \arg UltraPowerRead Ultra_Low power read mode. + ** + ** \retval None. + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetReadMode(en_efm_read_md_t enReadMD) +{ + DDL_ASSERT(IS_VALID_READ_MD(enReadMD)); + M4_EFM->FRMC_f.SLPMD = enReadMD; +} + +/** + ******************************************************************************* + ** \brief Enable or disable erase / program. + ** + ** \param [in] enNewState The new state of the erase / program. + ** \arg Enable Enable erase / program. + ** \arg Disable Disable erase / program. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_ErasePgmCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + M4_EFM->FWMC_f.PEMODE = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the flash erase program mode. + ** + ** \param [in] u32Mode The flash erase program mode. + ** \arg EFM_MODE_READONLY The flash read only. + ** \arg EFM_MODE_SINGLEPROGRAM The flash single program. + ** \arg EFM_MODE_SINGLEPROGRAMRB The flash single program with read back. + ** \arg EFM_MODE_SEQUENCEPROGRAM The flash sequence program. + ** \arg EFM_MODE_SECTORERASE The flash sector erase. + ** \arg EFM_MODE_CHIPERASE The flash mass erase. + ** + ** \retval en_result_t. + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SetErasePgmMode(uint32_t u32Mode) +{ + en_result_t enRet = Ok; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_ERASE_PGM_MD(u32Mode)); + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + break; + } + } + if(Ok == enRet) + { + M4_EFM->FWMC_f.PEMODE = Enable; + M4_EFM->FWMC_f.PEMOD = u32Mode; + M4_EFM->FWMC_f.PEMODE = Disable; + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Enable or disable the specified interrupt. + ** + ** \param [in] enInt The specified interrupt. + ** \arg PgmErsErrInt Program erase error interrupt. + ** \arg EndPgmInt End of Program interrupt. + ** \arg ReadErrInt Read collided error flag. + ** + ** \param [in] enNewState The new state of the specified interrupt. + ** \arg Enable Enable the specified interrupt. + ** \arg Disable Disable the specified interrupt. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_InterruptCmd(en_efm_int_sel_t enInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_INT_SEL(enInt)); + + switch(enInt) + { + case PgmErsErrInt: + M4_EFM->FITE_f.PEERRITE = enNewState; + break; + case EndPgmInt: + M4_EFM->FITE_f.OPTENDITE = enNewState; + break; + case ColErrInt: + M4_EFM->FITE_f.COLERRITE = enNewState; + break; + default: + break; + } +} + +/** + ******************************************************************************* + ** \brief Checks whether the specified FLASH flag is set or not.. + ** + ** \param [in] u32flag Specifies the FLASH flag to check. + ** \arg EFM_FLAG_WRPERR Flash write protect error flag. + ** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag. + ** \arg EFM_FLAG_PGSZERR Flash program size error flag. + ** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag. + ** \arg EFM_FLAG_EOP Flash end of program flag. + ** \arg EFM_FLAG_COLERR Flash collision error flag. + ** \arg EFM_FLAG_RDY Flash ready flag. + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t EFM_GetFlagStatus(uint32_t u32flag) +{ + DDL_ASSERT(IS_VALID_FLASH_FLAG(u32flag)); + + return ((0ul == (M4_EFM->FSR & u32flag)) ? Reset :Set); +} + +/** + ******************************************************************************* + ** \brief Checks whether the specified FLASH flag is set or not.. + ** + ** \param [in] u32flag Specifies the FLASH flag to clear. + ** \arg EFM_FLAG_WRPERR Flash write protect error flag. + ** \arg EFM_FLAG_PEPRTERR Flash program protect area error flag. + ** \arg EFM_FLAG_PGSZERR Flash program size error flag. + ** \arg EFM_FLAG_PGMISMTCH Flash program miss match flag. + ** \arg EFM_FLAG_EOP Flash end of program flag. + ** \arg EFM_FLAG_COLERR Flash collision error flag. + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +void EFM_ClearFlag(uint32_t u32flag) +{ + //DDL_ASSERT(IS_VALID_CLEAR_FLASH_FLAG(u32flag)); + + M4_EFM->FSCLR = u32flag; +} +/** + ******************************************************************************* + ** \brief Get the flash status. + ** + ** \param None + ** + ** \retval The flash status. + ** + ** \note None + ** + ******************************************************************************/ +en_efm_flash_status_t EFM_GetStatus(void) +{ + en_efm_flash_status_t enFlashStatus = FlashEOP; + + if(1ul == M4_EFM->FSR_f.RDY ) + { + enFlashStatus = FlashReady; + } + else if(1ul == M4_EFM->FSR_f.COLERR) + { + enFlashStatus = FlashRWErr; + } + else if(1ul == M4_EFM->FSR_f.OPTEND) + { + enFlashStatus = FlashEOP; + } + else if(1ul == M4_EFM->FSR_f.PGMISMTCH) + { + enFlashStatus = FlashPgMissMatch; + } + else if(1ul == M4_EFM->FSR_f.PGSZERR) + { + enFlashStatus = FlashPgSizeErr; + } + else if(1ul == M4_EFM->FSR_f.PEPRTERR) + { + enFlashStatus = FlashPgareaPErr; + } + else if(1ul == M4_EFM->FSR_f.PEWERR) + { + enFlashStatus = FlashWRPErr; + } + else + { + //else + } + + return enFlashStatus; +} + +/** + ******************************************************************************* + ** \brief Set flash the windows protect address. + ** + ** \param [in] stcAddr The specified windows protect address. + ** \arg StartAddr The start of windows protect address. + ** \arg EndAddr The end of windows protect address. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetWinProtectAddr(stc_efm_win_protect_addr_t stcAddr) +{ + M4_EFM->FPMTSW_f.FPMTSW = (stcAddr.StartAddr & EFM_PROTECT_ADDR_MSK); + M4_EFM->FPMTEW_f.FPMTEW = (stcAddr.EndAddr & EFM_PROTECT_ADDR_MSK); +} + +/** + ******************************************************************************* + ** \brief Set bus state while flash program & erase. + ** + ** \param [in] enState The specified bus state while flash program & erase. + ** \arg BusBusy The bus busy. + ** \arg BusRelease The bus release. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void EFM_SetBusState(en_efm_bus_sta_t enState) +{ + M4_EFM->FWMC_f.BUSHLDCTL = enState; +} + +/** + ******************************************************************************* + ** \brief Flash single program without read back. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Data The specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM; + /* program data. */ + *(uint32_t*)u32Addr = u32Data; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + if(u32Data != *(uint32_t*)u32Addr) + { + enRet = Error; + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash single program with read back. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Data The specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SingleProgramRB(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint8_t u8tmp = 0u; + uint16_t u16Timeout = 0u; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program with read back mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAMRB; + /* program data. */ + *(uint32_t*)u32Addr = u32Data; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + if(1ul == M4_EFM->FSR_f.PGMISMTCH) + { + enRet = Error; + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +static void *EFM_Memcpy(void *pvDst, void *pvSrc, uint32_t u32Count) +{ + uint8_t *u8TmpDst = (uint8_t *)pvDst; + uint8_t *u8TmpSrc = (uint8_t *)pvSrc; + + DDL_ASSERT(IS_VALID_POINTER(pvDst)); + DDL_ASSERT(IS_VALID_POINTER(pvSrc)); + + while (u32Count--) + { + *u8TmpDst++ = *u8TmpSrc++; + } + + return pvDst; +} +/** + ******************************************************************************* + ** \brief Flash sequence program. + ** + ** \param [in] u32Addr The specified program address. + ** \param [in] u32Len The len of specified program data. + ** \param [in] *pBuf The pointer of specified program data. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, void *pBuf) +{ + en_result_t enRet = Ok; + uint8_t u8tmp; + uint32_t i; + uint16_t u16Timeout = 0u; + uint32_t u32Tmp = 0xFFFFFFFFul; + uint32_t *u32pSrc = pBuf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32LoopWords = u32Len >> 2ul; + uint32_t u32RemainBytes = u32Len % 4ul; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_POINTER(pBuf)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set sequence program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SEQUENCEPROGRAM; + /* clear read collided error flag.*/ + EFM_ClearFlag(EFM_FLAG_COLERR); + EFM_ClearFlag(EFM_FLAG_WRPERR); + + /* program data. */ + for(i = 0ul; i < u32LoopWords; i++) + { + *u32pDest++ = *u32pSrc++; + /* wait operate end. */ + while(1ul != M4_EFM->FSR_f.OPTEND) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + /* clear end flag. */ + EFM_ClearFlag(EFM_FLAG_EOP); + } + if(u32RemainBytes) + { + EFM_Memcpy(&u32Tmp, u32pSrc, u32RemainBytes); + *u32pDest++ = u32Tmp; + } + + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + + u16Timeout = 0u; + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash sector erase. + ** + ** \param [in] u32Addr The uncertain(random) address in the specified sector. + ** + ** \retval en_result_t + ** + ** \note The address should be word align. + ** + ******************************************************************************/ +en_result_t EFM_SectorErase(uint32_t u32Addr) +{ + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable erase. */ + EFM_ErasePgmCmd(Enable); + /* Set sector erase mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SECTORERASE; + + *(uint32_t*)u32Addr = 0x12345678u; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Flash mass erase. + ** + ** \param [in] u32Addr The uncertain(random) address in the flash. + ** + ** \retval en_result_t + ** + ** \note The address should be word align. + ** + ******************************************************************************/ +en_result_t EFM_MassErase(uint32_t u32Addr) +{ + uint8_t u8tmp; + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_FLASH_ADDR(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_FLAG_WRPERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | + EFM_FLAG_PGMISMTCH | EFM_FLAG_EOP | EFM_FLAG_COLERR); + + /* read back CACHE */ + u8tmp = (uint8_t)M4_EFM->FRMC_f.CACHE; + + M4_EFM->FRMC_f.CACHE = Disable; + + /* Enable erase. */ + EFM_ErasePgmCmd(Enable); + /* Set sector erase mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_CHIPERASE; + + *(uint32_t*)u32Addr = 0x12345678u; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + /* recover CACHE */ + M4_EFM->FRMC_f.CACHE = u8tmp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get flash switch status. + ** + ** \param None. + ** + ** \retval en_flag_status_t + ** \arg Set The flash has switched, the start address is sector1. + ** \arg Reset The flash did not switch, the start address is sector0. + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t EFM_GetSwitchStatus(void) +{ + return ((0u == M4_EFM->FSWP_f.FSWP) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Lock OTP data block. + ** + ** \param u32Addr The addr to lock. + ** + ** \retval en_result_t + ** + ** \note None + ** + ******************************************************************************/ +en_result_t EFM_OtpLock(uint32_t u32Addr) +{ + DDL_ASSERT(IS_VALID_OTP_LOCK_ADDR(u32Addr)); + uint16_t u16Timeout = 0u; + en_result_t enRet = Ok; + + /* Enable program. */ + EFM_ErasePgmCmd(Enable); + /* Set single program mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_SINGLEPROGRAM; + + /* Lock the otp block. */ + *(uint32_t*)u32Addr = 0ul; + + while(1ul != M4_EFM->FSR_f.RDY) + { + u16Timeout++; + if(u16Timeout > 0x1000u) + { + enRet = ErrorTimeout; + } + } + + EFM_ClearFlag(EFM_FLAG_EOP); + /* Set read only mode. */ + M4_EFM->FWMC_f.PEMOD = EFM_MODE_READONLY; + EFM_ErasePgmCmd(Disable); + + return enRet; +} +/** + ******************************************************************************* + ** \brief read unique ID. + ** + ** \param None + ** + ** \retval uint32_t + ** + ** \note None + ** + ******************************************************************************/ +stc_efm_unique_id_t EFM_ReadUID(void) +{ + stc_efm_unique_id_t stcUID; + + stcUID.uniqueID1 = M4_EFM->UQID1; + stcUID.uniqueID2 = M4_EFM->UQID2; + stcUID.uniqueID3 = M4_EFM->UQID3; + + return stcUID; +} + +//@} // EfmGroup + +#endif /* DDL_EFM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_emb.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_emb.c new file mode 100644 index 0000000000..9fe58408a9 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_emb.c @@ -0,0 +1,487 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_emb.c + ** + ** A detailed description is available at + ** @link EMBGroup EMB description @endlink + ** + ** - 2018-11-24 CDT First version for Device Driver Library of EMB. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_emb.h" +#include "hc32f460_utility.h" + +#if (DDL_EMB_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EMBGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for emb unit */ +#define IS_VALID_EMB_UNIT(__EMBx__) \ +( (M4_EMB1 == (__EMBx__)) || \ + (M4_EMB2 == (__EMBx__)) || \ + (M4_EMB3 == (__EMBx__)) || \ + (M4_EMB4 == (__EMBx__))) + +/*!< Parameter valid check for emb status*/ +#define IS_VALID_EMB_STATUS_TYPE(x) \ +( (EMBFlagPortIn == (x)) || \ + (EMBFlagPWMSame == (x)) || \ + (EMBFlagCmp == (x)) || \ + (EMBFlagOSCFail == (x)) || \ + (EMBPortInState == (x)) || \ + (EMBPWMState == (x))) + +/*!< Parameter valid check for emb status clear*/ +#define IS_VALID_EMB_STATUS_CLR(x) \ +( (EMBPortInFlagClr == (x)) || \ + (EMBPWMSameFlagCLr == (x)) || \ + (EMBCmpFlagClr == (x)) || \ + (EMBOSCFailFlagCLr == (x))) + +/*!< Parameter valid check for emb irq enable*/ +#define IS_VALID_EMB_IRQ(x) \ +( (PORTBrkIrq == (x)) || \ + (PWMSmBrkIrq == (x)) || \ + (CMPBrkIrq == (x)) || \ + (OSCFailBrkIrq == (x))) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/******************************************************************************* + * \brief EMB interrupt request enable or disable + * + * \param [in] EMBx EMB unit + * \param [in] enEMBIrq Irq type + * \param [in] bEn true/false + * + * \retval en_result_t Ok: config success + ******************************************************************************/ +en_result_t EMB_ConfigIrq(M4_EMB_TypeDef *EMBx, + en_emb_irq_type_t enEMBIrq, + bool bEn) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_EMB_UNIT(EMBx)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_IRQ(enEMBIrq)); + + enRet = Ok; + switch (enEMBIrq) + { + case PORTBrkIrq: + EMBx->INTEN_f.PORTINTEN = (uint32_t)bEn; + break; + case PWMSmBrkIrq: + EMBx->INTEN_f.PWMINTEN = (uint32_t)bEn; + break; + case CMPBrkIrq: + EMBx->INTEN_f.CMPINTEN = (uint32_t)bEn; + break; + case OSCFailBrkIrq: + EMBx->INTEN_f.OSINTEN = (uint32_t)bEn; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get EMB status + ** + ** \param [in] EMBx EMB unit + ** + ** \param [in] enStatus EMB status type + ** + ** \retval EMB status + ** + ******************************************************************************/ +bool EMB_GetStatus(M4_EMB_TypeDef *EMBx, en_emb_status_t enStatus) +{ + bool status = false; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx)); + DDL_ASSERT(IS_VALID_EMB_STATUS_TYPE(enStatus)); + + switch (enStatus) + { + case EMBFlagPortIn: + status = EMBx->STAT_f.PORTINF; + break; + case EMBFlagPWMSame: + status = EMBx->STAT_f.PWMSF; + break; + case EMBFlagCmp: + status = EMBx->STAT_f.CMPF; + break; + case EMBFlagOSCFail: + status = EMBx->STAT_f.OSF; + break; + case EMBPortInState: + status = EMBx->STAT_f.PORTINST; + break; + case EMBPWMState: + status = EMBx->STAT_f.PWMST; + break; + default: + break; + } + + return status; +} + +/** + ******************************************************************************* + ** \brief EMB clear status(Recover from protection state) + ** + ** \param [in] EMBx EMB unit + ** + ** \param [in] enStatusClr EMB status clear type + ** + ** \retval en_result_t Ok: Config Success + ** + ******************************************************************************/ +en_result_t EMB_ClrStatus(M4_EMB_TypeDef *EMBx, + en_emb_status_clr_t enStatusClr) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_EMB_UNIT(EMBx)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATUS_CLR(enStatusClr)); + + enRet = Ok; + switch (enStatusClr) + { + case EMBPortInFlagClr: + EMBx->STATCLR_f.PORTINFCLR = 1ul; + break; + case EMBPWMSameFlagCLr: + EMBx->STATCLR_f.PWMSFCLR = 1ul; + break; + case EMBCmpFlagClr: + EMBx->STATCLR_f.CMPFCLR = 1ul; + break; + case EMBOSCFailFlagCLr: + EMBx->STATCLR_f.OSFCLR = 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/******************************************************************************* + * \brief EMB Control Register(CR) for timer6 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBConfigCR EMB Config CR pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_Config_CR_Timer6(const stc_emb_ctrl_timer6_t* pstcEMBConfigCR) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcEMBConfigCR) + { + if (pstcEMBConfigCR->bEnPortBrake) + { + u32Val |= 1ul; + } + if (pstcEMBConfigCR->bEnCmp1Brake) + { + u32Val |= 1ul << 1; + } + if (pstcEMBConfigCR->bEnCmp2Brake) + { + u32Val |= 1ul << 2; + } + if (pstcEMBConfigCR->bEnCmp3Brake) + { + u32Val |= 1ul << 3; + } + if (pstcEMBConfigCR->bEnOSCFailBrake) + { + u32Val |= 1ul << 5; + } + if (pstcEMBConfigCR->bEnTimer61PWMSBrake) + { + u32Val |= 1ul << 6; + } + if (pstcEMBConfigCR->bEnTimer62PWMSBrake) + { + u32Val |= 1ul << 7; + } + if (pstcEMBConfigCR->bEnTimer63PWMSBrake) + { + u32Val |= 1ul << 8; + } + if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel) + { + } + if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 1ul << 28; + } + if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 2ul << 28; + } + if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 3ul << 28; + } + if (pstcEMBConfigCR->bEnPorInFlt) + { + u32Val |= 1ul << 30; + } + if (pstcEMBConfigCR->bEnPortInLevelSel_Low) + { + u32Val |= 1ul << 31; + } + + M4_EMB1->CTL = u32Val; + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* + * \brief EMB Control Register(CR) for timer4 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBConfigCR EMB Config CR pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_Config_CR_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_ctrl_timer4_t* pstcEMBConfigCR) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((M4_EMB1 != EMBx) && \ + (IS_VALID_EMB_UNIT(EMBx)) && \ + (NULL != pstcEMBConfigCR)) + { + if (pstcEMBConfigCR->bEnPortBrake) + { + u32Val |= 1ul; + } + if (pstcEMBConfigCR->bEnCmp1Brake) + { + u32Val |= 1ul << 1; + } + if (pstcEMBConfigCR->bEnCmp2Brake) + { + u32Val |= 1ul << 2; + } + if (pstcEMBConfigCR->bEnCmp3Brake) + { + u32Val |= 1ul << 3; + } + if (pstcEMBConfigCR->bEnOSCFailBrake) + { + u32Val |= 1ul << 5; + } + if (pstcEMBConfigCR->bEnTimer4xWHLSammeBrake) + { + u32Val |= 1ul << 6; + } + if (pstcEMBConfigCR->bEnTimer4xVHLSammeBrake) + { + u32Val |= 1ul << 7; + } + if (pstcEMBConfigCR->bEnTimer4xUHLSammeBrake) + { + u32Val |= 1ul << 8; + } + if (EMBPortFltDiv0 == pstcEMBConfigCR->enPortInFltClkSel) + { + } + if (EMBPortFltDiv8 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 1ul << 28; + } + if (EMBPortFltDiv32 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 2ul << 28; + } + if (EMBPortFltDiv128 == pstcEMBConfigCR->enPortInFltClkSel) + { + u32Val |= 3ul << 28; + } + if (pstcEMBConfigCR->bEnPorInFlt) + { + u32Val |= 1ul << 30; + } + if (pstcEMBConfigCR->bEnPortInLevelSel_Low) + { + u32Val |= 1ul << 31; + } + + EMBx->CTL = u32Val; + enRet = Ok; + } + + return enRet; +} + +/******************************************************************************* + * \brief EMB detect PWM atcive level (short detection) selection for timer6 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBPWMlv EMB en detect active level pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_PWMLv_Timer6(const stc_emb_pwm_level_timer6_t* pstcEMBPWMlv) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcEMBPWMlv) + { + if (pstcEMBPWMlv->bEnTimer61HighLevelDect) + { + u32Val |= 0x1ul; + } + if (pstcEMBPWMlv->bEnTimer62HighLevelDect) + { + u32Val |= 0x2ul; + } + if (pstcEMBPWMlv->bEnTimer63HighLevelDect) + { + u32Val |= 0x4ul; + } + + M4_EMB1->PWMLV = u32Val; + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* + * \brief EMB detect PWM atcive level (short detection) selection for timer4 + * + * \param [in] EMBx EMB unit + * \param [in] pstcEMBPWMlv EMB en detect active level pointer + * + * \retval en_result_t Ok: Set successfully + * \retval en_result_t ErrorInvalidParameter: Provided parameter is not valid + ******************************************************************************/ +en_result_t EMB_PWMLv_Timer4(M4_EMB_TypeDef *EMBx, + const stc_emb_pwm_level_timer4_t* pstcEMBPWMlv) +{ + uint32_t u32Val = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + if ((IS_VALID_EMB_UNIT(EMBx)) && \ + (M4_EMB1 != EMBx) && \ + (NULL != pstcEMBPWMlv)) + { + if (pstcEMBPWMlv->bEnWHLphaseHighLevelDect) + { + u32Val |= 0x1ul; + } + if (pstcEMBPWMlv->bEnVHLPhaseHighLevelDect) + { + u32Val |= 0x2ul; + } + if (pstcEMBPWMlv->bEnUHLPhaseHighLevelDect) + { + u32Val |= 0x4ul; + } + + EMBx->PWMLV = u32Val; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief EMB Software brake + ** + ** \param [in] EMBx EMB unit + ** +** \param [in] bEn true: Software Brake Enable / false: Software Brake Disable + ** + ** \retval en_result_t Ok: Config Success + ** + ******************************************************************************/ +en_result_t EMB_SwBrake(M4_EMB_TypeDef *EMBx, bool bEn) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_UNIT(EMBx)); + + EMBx->SOE_f.SOE = (uint32_t)bEn; + + return Ok; +} + +//@} // EMBGroup + +#endif /* DDL_EMB_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_event_port.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_event_port.c new file mode 100644 index 0000000000..fafc2adc71 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_event_port.c @@ -0,0 +1,468 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_event_port.c + ** + ** A detailed description is available at + ** @link EventPortGroup EventPort description @endlink + ** + ** - 2018-12-07 CDT First version for Device Driver Library of EventPort. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_event_port.h" +#include "hc32f460_utility.h" + +#if (DDL_EVENT_PORT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup EventPortGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define EP1_BASE 0x40010800ul + 0x0100ul +#define EP2_BASE 0x40010800ul + 0x011Cul +#define EP3_BASE 0x40010800ul + 0x0138ul +#define EP4_BASE 0x40010800ul + 0x0154ul +#define EP1_DIR_BASE 0x00ul +#define EP1_IDR_BASE 0x04ul +#define EP1_ODR_BASE 0x08ul +#define EP1_ORR_BASE 0x0Cul +#define EP1_OSR_BASE 0x10ul +#define EP1_RISR_BASE 0x14ul +#define EP1_FAL_BASE 0x18ul +#define EP_NFCR_BASE 0x40010800ul + 0x0170ul + + +/*! Parameter validity check for port group. */ +#define IS_VALID_EVENT_PORT(x) \ +( ((x) == EventPort1) || \ + ((x) == EventPort2) || \ + ((x) == EventPort3) || \ + ((x) == EventPort4)) + +/*! Parameter validity check for pin. */ +#define IS_VALID_EVENT_PIN(x) \ +( ((x) == EventPin00) || \ + ((x) == EventPin01) || \ + ((x) == EventPin02) || \ + ((x) == EventPin03) || \ + ((x) == EventPin04) || \ + ((x) == EventPin05) || \ + ((x) == EventPin06) || \ + ((x) == EventPin07) || \ + ((x) == EventPin08) || \ + ((x) == EventPin09) || \ + ((x) == EventPin10) || \ + ((x) == EventPin11) || \ + ((x) == EventPin12) || \ + ((x) == EventPin13) || \ + ((x) == EventPin14) || \ + ((x) == EventPin15)) + +/*! Parameter valid check for Event Port common trigger. */ +#define IS_EP_COM_TRIGGER(x) \ +( ((x) == EpComTrigger_1) || \ + ((x) == EpComTrigger_2) || \ + ((x) == EpComTrigger_1_2)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Event Port init + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \param [in] pstcEventPortInit Structure pointer of event port configuration + ** + ** \retval Ok Init successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_Init(en_event_port_t enEventPort, uint16_t u16EventPin, \ + const stc_event_port_init_t *pstcEventPortInit) +{ + en_result_t enRet = Ok; + + uint32_t *EPDIRx; ///< Direction register + uint32_t *EPORRx; ///< Reset after trigger enable register + uint32_t *EPOSRx; ///< Set after trigger enable register + uint32_t *EPRISRx; ///< Rising edge detect enable register + uint32_t *EPFALx; ///< Falling edge detect enable register + + EPDIRx = (uint32_t *)(EP1_BASE + EP1_DIR_BASE + (0x1C * enEventPort)); + EPORRx = (uint32_t *)(EP1_BASE + EP1_ORR_BASE + (0x1C * enEventPort)); + EPOSRx = (uint32_t *)(EP1_BASE + EP1_OSR_BASE + (0x1C * enEventPort)); + EPRISRx= (uint32_t *)(EP1_BASE + EP1_RISR_BASE+ (0x1C * enEventPort)); + EPFALx = (uint32_t *)(EP1_BASE + EP1_FAL_BASE + (0x1C * enEventPort)); + + /* Direction configure */ + if (EventPortOut == pstcEventPortInit->enDirection) + { + *EPDIRx |= u16EventPin; + } + else + { + *EPDIRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Reset if be triggered */ + if (Enable == pstcEventPortInit->enReset) + { + *EPORRx |= u16EventPin; + } + else + { + *EPORRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Set if be triggered */ + if (Enable == pstcEventPortInit->enSet) + { + *EPOSRx |= u16EventPin; + } + else + { + *EPOSRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Rising edge detect setting */ + if (Enable == pstcEventPortInit->enRisingDetect) + { + *EPRISRx |= u16EventPin; + } + else + { + *EPRISRx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Falling edge detect setting */ + if (Enable == pstcEventPortInit->enFallingDetect) + { + *EPFALx |= u16EventPin; + } + else + { + *EPFALx &= (~(uint32_t)u16EventPin) & 0xFFFFul; + } + + /* Noise filter setting */ + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTNFCR_f.NFEN1 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS1 = pstcEventPortInit->enFilterClk; + break; + case EventPort2: + M4_AOS->PEVNTNFCR_f.NFEN2 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS2 = pstcEventPortInit->enFilterClk; + break; + case EventPort3: + M4_AOS->PEVNTNFCR_f.NFEN3 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS3 = pstcEventPortInit->enFilterClk; + break; + case EventPort4: + M4_AOS->PEVNTNFCR_f.NFEN4 = pstcEventPortInit->enFilter; + M4_AOS->PEVNTNFCR_f.DIVS4 = pstcEventPortInit->enFilterClk; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Event Port de-init, restore all registers to default value + ** + ** \param None + ** + ** \retval Ok De-init successful + ** + ******************************************************************************/ +en_result_t EVENTPORT_DeInit(void) +{ + uint32_t EPDIRx ; + uint32_t EPODRx ; + uint32_t EPORRx ; + uint32_t EPOSRx ; + uint32_t EPRISRx; + uint32_t EPFALx ; + uint8_t u8EPCnt; + + EPDIRx = (uint32_t)(EP1_BASE + EP1_DIR_BASE); + EPODRx = (uint32_t)(EP1_BASE + EP1_ODR_BASE); + EPORRx = (uint32_t)(EP1_BASE + EP1_ORR_BASE); + EPOSRx = (uint32_t)(EP1_BASE + EP1_OSR_BASE); + EPRISRx = (uint32_t)(EP1_BASE + EP1_RISR_BASE); + EPFALx = (uint32_t)(EP1_BASE + EP1_FAL_BASE); + + /* Restore all registers to default value */ + M4_AOS->PORT_PEVNTTRGSR12 = 0x1FFul; + M4_AOS->PORT_PEVNTTRGSR34 = 0x1FFul; + M4_AOS->PEVNTNFCR = 0ul; + for (u8EPCnt = 0u; u8EPCnt < 4u; u8EPCnt++) + { + *(uint32_t *)(EPDIRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPODRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPORRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPOSRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPRISRx + 0x1Cul * u8EPCnt) = 0ul; + *(uint32_t *)(EPFALx + 0x1Cul * u8EPCnt) = 0ul; + } + return Ok; +} + +/** + ******************************************************************************* + ** \brief Event Port trigger source select + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enTriggerSrc Event port trigger source. This parameter + ** can be any value of @ref en_event_src_t + ** \retval Ok Trigger source is set + ** ErrorInvalidParameter Invalid event port enum + ** + ******************************************************************************/ +en_result_t EVENTPORT_SetTriggerSrc(en_event_port_t enEventPort, \ + en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + if ((EventPort1 == enEventPort) || (EventPort2 == enEventPort)) + { + M4_AOS->PORT_PEVNTTRGSR12 = enTriggerSrc; + } + else if ((EventPort3 == enEventPort) || (EventPort4 == enEventPort)) + { + M4_AOS->PORT_PEVNTTRGSR34 = enTriggerSrc; + } + else + { + enRet = ErrorInvalidParameter; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Event Port common trigger. + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enComTrigger Event port common trigger selection. + ** See @ref en_event_port_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void EVENTPORT_ComTriggerCmd(en_event_port_t enEventPort, \ + en_event_port_com_trigger_t enComTrigger, \ + en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + __IO uint32_t *TRGSELx; + + TRGSELx = (__IO uint32_t *)((uint32_t)&M4_AOS->PORT_PEVNTTRGSR12 + (4UL * ((uint32_t)enEventPort/2UL))); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_EP_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + *TRGSELx |= (u32ComTrig << 30u); + } + else + { + *TRGSELx &= ~(u32ComTrig << 30u); + } + } +} + +/** + ******************************************************************************* + ** \brief Read Event Port value after be triggered + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** + ** \retval uint16_t The output port value + ** + ******************************************************************************/ +uint16_t EVENTPORT_GetData(en_event_port_t enEventPort) +{ + uint16_t u16Data = 0u; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + switch (enEventPort) + { + case EventPort1: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR1 & 0xFFFFul); + break; + case EventPort2: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR2 & 0xFFFFul); + break; + case EventPort3: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR3 & 0xFFFFul); + break; + case EventPort4: + u16Data = (uint16_t)(M4_AOS->PEVNTIDR4 & 0xFFFFul); + break; + } + return u16Data; +} + +/** + ******************************************************************************* + ** \brief Read Event Pin value after triggered + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] enEventPin GPIO pin index, This parameter can be + ** any value of @ref en_event_pin_t + ** \retval en_flag_status_t The output port pin value + ** + ******************************************************************************/ +en_flag_status_t EVENTPORT_GetBit(en_event_port_t enEventPort, en_event_pin_t enEventPin) +{ + bool bBitValue = false; + + switch (enEventPort) + { + case EventPort1: + bBitValue = M4_AOS->PEVNTIDR1 & enEventPin; + break; + case EventPort2: + bBitValue = M4_AOS->PEVNTIDR2 & enEventPin; + break; + case EventPort3: + bBitValue = M4_AOS->PEVNTIDR3 & enEventPin; + break; + case EventPort4: + bBitValue = M4_AOS->PEVNTIDR4 & enEventPin; + break; + } + return (en_flag_status_t)(bool)((!!bBitValue)); +} + +/** + ******************************************************************************* + ** \brief Set Event Port Pin + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \retval Ok Set successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_SetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTODR1 |= u16EventPin; + break; + case EventPort2: + M4_AOS->PEVNTODR2 |= u16EventPin; + break; + case EventPort3: + M4_AOS->PEVNTODR3 |= u16EventPin; + break; + case EventPort4: + M4_AOS->PEVNTODR4 |= u16EventPin; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Reset Event Port Pin + ** + ** \param [in] enEventPort Event port index, This parameter can be + ** any value of @ref en_event_port_t + ** \param [in] u16EventPin Event pin index, This parameter can be + ** any composed value of @ref en_event_pin_t + ** \retval Ok Reset successful + ** ErrorInvalidParameter Event port index invalid + ** + ******************************************************************************/ +en_result_t EVENTPORT_ResetBits(en_event_port_t enEventPort, en_event_pin_t u16EventPin) +{ + en_result_t enRet = Ok; + DDL_ASSERT(IS_VALID_EVENT_PORT(enEventPort)); + + switch (enEventPort) + { + case EventPort1: + M4_AOS->PEVNTODR1 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort2: + M4_AOS->PEVNTODR2 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort3: + M4_AOS->PEVNTODR3 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + case EventPort4: + M4_AOS->PEVNTODR4 &= (~(uint32_t)u16EventPin) & 0xFFFFul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + return enRet; +} + +//@} // EventPortGroup + +#endif /* DDL_EVENT_PORT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c new file mode 100644 index 0000000000..56f5e9c187 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c @@ -0,0 +1,337 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_exint_nmi_swi.c + ** + ** A detailed description is available at + ** @link ExintNmiSwiGroup Exint/Nmi/Swi description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of exint, Nmi, SW interrupt. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_exint_nmi_swi.h" +#include "hc32f460_utility.h" + +#if (DDL_EXINT_NMI_SWI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup ExintNmiSwiGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + /*! Parameter validity check for external interrupt channel. */ +#define IS_VALID_CH(x) \ +( ((x) == ExtiCh00) || \ + ((x) == ExtiCh01) || \ + ((x) == ExtiCh02) || \ + ((x) == ExtiCh03) || \ + ((x) == ExtiCh04) || \ + ((x) == ExtiCh05) || \ + ((x) == ExtiCh06) || \ + ((x) == ExtiCh07) || \ + ((x) == ExtiCh08) || \ + ((x) == ExtiCh09) || \ + ((x) == ExtiCh10) || \ + ((x) == ExtiCh11) || \ + ((x) == ExtiCh12) || \ + ((x) == ExtiCh13) || \ + ((x) == ExtiCh14) || \ + ((x) == ExtiCh15)) + +/*! Parameter validity check for null pointer. */ +#define IS_NULL_POINT(x) (NULL != (x)) + +/*! Parameter validity check for external interrupt trigger method. */ +#define IS_VALID_LEVEL(x) \ +( ((x) == ExIntLowLevel) || \ + ((x) == ExIntBothEdge) || \ + ((x) == ExIntRisingEdge) || \ + ((x) == ExIntFallingEdge)) + +/*! Parameter validity check for NMI interrupt source. */ +#define IS_VALID_NMI_SRC(x) \ +( ((x) == NmiSrcNmi) || \ + ((x) == NmiSrcSwdt) || \ + ((x) == NmiSrcVdu1) || \ + ((x) == NmiSrcVdu2) || \ + ((x) == NmiSrcXtalStop) || \ + ((x) == NmiSrcSramPE) || \ + ((x) == NmiSrcSramDE) || \ + ((x) == NmiSrcMpu) || \ + ((x) == NmiSrcWdt)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnNmiCallback; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief External Int initialization + ** + ** \param [in] pstcExtiConfig EXTI configure structure + ** + ** \retval Ok EXTI initialized + ** + ******************************************************************************/ +en_result_t EXINT_Init(const stc_exint_config_t *pstcExtiConfig) +{ + stc_intc_eirqcr_field_t *EIRQCRx; + + DDL_ASSERT(IS_VALID_CH(pstcExtiConfig->enExitCh)); + + EIRQCRx = (stc_intc_eirqcr_field_t *)((uint32_t)(&M4_INTC->EIRQCR0) + \ + (uint32_t)(4ul * (uint32_t)(pstcExtiConfig->enExitCh))); + + /* Set filter function */ + EIRQCRx->EFEN = pstcExtiConfig->enFilterEn; + EIRQCRx->EISMPCLK = pstcExtiConfig->enFltClk; + + /* Set detection level */ + EIRQCRx->EIRQTRG = pstcExtiConfig->enExtiLvl; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get External interrupt request flag + ** + ** \param [in] enExint NMI Int source, This parameter can be + ** any value of @ref en_exti_ch_t + ** + ** \retval Set Corresponding Ex.Int request flag be set + ** Reset Corresponding Ex.Int request flag not be set + ** + ******************************************************************************/ +en_int_status_t EXINT_IrqFlgGet(en_exti_ch_t enExint) +{ + en_int_status_t enRet; + DDL_ASSERT(IS_VALID_CH(enExint)); + + enRet = (1u == !!(M4_INTC->EIFR & (1ul<EICFR |= (uint32_t)(1ul << enExint); + return Ok; +} + +/** + ******************************************************************************* + ** \brief NMI initialization + ** + ** \param [in] pstcNmiConfig NMI configure structure + ** + ** \retval Ok NMI initialized + ** ErrorInvalidParameter NMI configuration pointer is null + ** + ******************************************************************************/ +en_result_t NMI_Init(const stc_nmi_config_t *pstcNmiConfig) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcNmiConfig) + { + /* NMI callback function */ + pfnNmiCallback = pstcNmiConfig->pfnNmiCallback; + /* Set filter function */ + M4_INTC->NMICR_f.NFEN = pstcNmiConfig->enFilterEn; + /* Set filter clock */ + M4_INTC->NMICR_f.NSMPCLK = pstcNmiConfig->enFilterClk; + /* Set detection level */ + M4_INTC->NMICR_f.NMITRG = pstcNmiConfig->enNmiLvl; + /* Set NMI source */ + M4_INTC->NMIENR = (uint32_t)pstcNmiConfig->u16NmiSrc; + enRet = Ok; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Init Non-Maskable Interrupt (NMI) + ** + ** \param None + ** + ** \retval Ok NMI De-initialized + ** + ******************************************************************************/ +en_result_t NMI_DeInit(void) +{ + /* Set internal data */ + pfnNmiCallback = NULL; + + /* clear NMI control register */ + M4_INTC->NMICR = 0u; + + /* clear NMI enable register */ + M4_INTC->NMIENR = 0u; + + /* clear all NMI flags */ + M4_INTC->NMIFR = 0u; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get NMI interrupt request flag + ** + ** \param [in] enNmiSrc NMI Int source, This parameter can be + ** any value of @ref en_nmi_src_t + ** + ** \retval Set Corresponding NMI flag be set + ** Reset Corresponding NMI flag not be set + ** + ******************************************************************************/ +en_int_status_t NMI_IrqFlgGet(en_nmi_src_t enNmiSrc) +{ + DDL_ASSERT(IS_VALID_NMI_SRC(enNmiSrc)); + + en_int_status_t enRet = Reset; + switch (enNmiSrc) + { + case NmiSrcNmi: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.NMIFR); + break; + case NmiSrcSwdt: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.SWDTFR); + break; + case NmiSrcVdu1: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD1FR); + break; + case NmiSrcVdu2: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.PVD2FR); + break; + case NmiSrcXtalStop: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.XTALSTPFR); + break; + case NmiSrcSramPE: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.REPFR); + break; + case NmiSrcSramDE: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.RECCFR); + break; + case NmiSrcMpu: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.BUSMFR); + break; + case NmiSrcWdt: + enRet = (en_int_status_t)(M4_INTC->NMIFR_f.WDTFR); + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear NMI interrupt request flag + ** + ** \param [in] u16NmiSrc NMI Int source, This parameter can be + ** any composited value of @ref en_nmi_src_t + ** + ** \retval Ok Interrupt source be cleared + ** + ******************************************************************************/ +en_result_t NMI_IrqFlgClr(uint16_t u16NmiSrc) +{ + M4_INTC->NMICFR |= u16NmiSrc; + return Ok; +} + +/** + ******************************************************************************* + ** \brief ISR for NMI + ** + ******************************************************************************/ +void NMI_IrqHandler(void) +{ + DDL_ASSERT(IS_NULL_POINT(pfnNmiCallback)); + + pfnNmiCallback(); +} + +/** + ******************************************************************************* + ** \brief Enable Softeware Interrupt (SWI) + ** + * \param [in] u32SwiCh This parameter can be any composited + * value of @ref en_swi_ch_t + ** + ** \retval Ok SWI initialized + ** + ******************************************************************************/ +en_result_t SWI_Enable(uint32_t u32SwiCh) +{ + M4_INTC->SWIER |= u32SwiCh; + return Ok; +} + +/** + ******************************************************************************* + ** \brief De-Init Softeware Interrupt (SWI) + ** + * \param [in] u32SwiCh This parameter can be any composited + * value of @ref en_swi_ch_t + ** + ** \retval Ok SWI de-initialized + ** + ******************************************************************************/ +en_result_t SWI_Disable(uint32_t u32SwiCh) +{ + /* clear software interrupt enable register */ + M4_INTC->SWIER &= ~u32SwiCh; + + return Ok; +} + +//@} // ExintNmiSwiGroup + +#endif /* DDL_EXINT_NMI_SWI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c new file mode 100644 index 0000000000..16b8656f98 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c @@ -0,0 +1,671 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_gpio.c + ** + ** A detailed description is available at + ** @link GpioGroup Gpio description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of Gpio. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_gpio.h" +#include "hc32f460_utility.h" + +#if (DDL_GPIO_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup GpioGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define GPIO_BASE (0x40053800ul) +#define PODR_BASE (0x0004ul) +#define POER_BASE (0x0006ul) +#define POSR_BASE (0x0008ul) +#define PORR_BASE (0x000Aul) +#define PCR_BASE (0x0400ul) +#define PFSR_BASE (0x0402ul) + +/*! Parameter validity check for port group. */ +#define IS_VALID_PORT(x) \ +( ((x) == PortA) || \ + ((x) == PortB) || \ + ((x) == PortC) || \ + ((x) == PortD) || \ + ((x) == PortE) || \ + ((x) == PortH)) + +/*! Parameter validity check for pin. */ +#define IS_VALID_PIN(x) \ +( ((x) == Pin00) || \ + ((x) == Pin01) || \ + ((x) == Pin02) || \ + ((x) == Pin03) || \ + ((x) == Pin04) || \ + ((x) == Pin05) || \ + ((x) == Pin06) || \ + ((x) == Pin07) || \ + ((x) == Pin08) || \ + ((x) == Pin09) || \ + ((x) == Pin10) || \ + ((x) == Pin11) || \ + ((x) == Pin12) || \ + ((x) == Pin13) || \ + ((x) == Pin14) || \ + ((x) == Pin15)) + +/*! Parameter validity check for debug pins. */ +#define IS_VALID_DEBUGPIN(x) ((x) <= 0x1Fu) + +/*! Parameter validity check for pin mode. */ +#define IS_VALID_PINMODE(x) \ +( ((x) == Pin_Mode_In) || \ + ((x) == Pin_Mode_Out) || \ + ((x) == Pin_Mode_Ana)) + +/*! Parameter validity check for pin drive capacity. */ +#define IS_VALID_PINDRV(x) \ +( ((x) == Pin_Drv_L) || \ + ((x) == Pin_Drv_M) || \ + ((x) == Pin_Drv_H)) + +/*! Parameter validity check for pin output type. */ +#define IS_VALID_PINTYPE(x) \ +( ((x) == Pin_OType_Cmos) || \ + ((x) == Pin_OType_Od)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_VALID_READWAIT(x) \ +( ((x) == WaitCycle0) || \ + ((x) == WaitCycle1) || \ + ((x) == WaitCycle2) || \ + ((x) == WaitCycle3)) + +/*! Parameter validity check for pin function */ +#define IS_VALID_FUNC(x) \ +( ((x) == Func_Gpio) || \ + (((x) >= Func_Fcmref) && \ + ((x) <= Func_I2s)) || \ + ((x) == Func_Evnpt) || \ + ((x) == Func_Eventout) || \ + (((x) >= Func_Usart1_Tx) && \ + ((x) <= Func_I2s2_Ck))) + +/*! Parameter validity check for pin sub-function */ +#define IS_VALID_SUBFUNC(x) \ +( ((x) == Func_Gpio) || \ + ((x) == Func_Fcmref) || \ + ((x) == Func_Rtcout) || \ + ((x) == Func_Vcout) || \ + ((x) == Func_Adtrg) || \ + ((x) == Func_Mclkout) || \ + ((x) == Func_Tim4) || \ + ((x) == Func_Tim6) || \ + ((x) == Func_Tima0) || \ + ((x) == Func_Tima1) || \ + ((x) == Func_Tima2) || \ + ((x) == Func_Emb) || \ + ((x) == Func_Usart_Ck) || \ + ((x) == Func_Spi_Nss) || \ + ((x) == Func_Qspi) || \ + ((x) == Func_Key) || \ + ((x) == Func_Sdio) || \ + ((x) == Func_I2s) || \ + ((x) == Func_UsbF) || \ + ((x) == Func_Evnpt) || \ + ((x) == Func_Eventout)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Port init + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \param [in] pstcPortInit Structure pointer of port configuration + ** + ** \retval Ok Port initial successful + ** + ******************************************************************************/ +en_result_t PORT_Init(en_port_t enPort, uint16_t u16Pin, const stc_port_init_t *pstcPortInit) +{ + stc_port_pcr_field_t *PCRx; + stc_port_pfsr_field_t * PFSRx; + uint8_t u8PinPos = 0u; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + DDL_ASSERT(IS_VALID_PINMODE(pstcPortInit->enPinMode)); + DDL_ASSERT(IS_VALID_PINDRV(pstcPortInit->enPinDrv)); + DDL_ASSERT(IS_VALID_PINTYPE(pstcPortInit->enPinOType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enLatch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enExInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enInvert)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPullUp)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPortInit->enPinSubFunc)); + + PORT_Unlock(); + for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++) + { + if (u16Pin & (1ul<PCRA0) + \ + enPort * 0x40ul + u8PinPos * 0x04ul); + PFSRx = (stc_port_pfsr_field_t *)((uint32_t)(&M4_PORT->PFSRA0) + \ + enPort * 0x40ul + u8PinPos * 0x04ul); + + /* Input latch function setting */ + PCRx->LTE = pstcPortInit->enLatch; + + /* External interrupt input enable setting */ + PCRx->INTE = pstcPortInit->enExInt; + + /* In_Out invert setting */ + PCRx->INVE = pstcPortInit->enInvert; + + /* Pin pull-up setting */ + PCRx->PUU = pstcPortInit->enPullUp; + + /* CMOS/OD output setting */ + PCRx->NOD = pstcPortInit->enPinOType; + + /* Pin drive mode setting */ + PCRx->DRV = pstcPortInit->enPinDrv; + + /* Pin mode setting */ + switch (pstcPortInit->enPinMode) + { + case Pin_Mode_In: + PCRx->DDIS = 0u; + PCRx->POUTE = 0u; + break; + case Pin_Mode_Out: + PCRx->DDIS = 0u; + PCRx->POUTE = 1u; + break; + case Pin_Mode_Ana: + PCRx->DDIS = 1u; + break; + default: + break; + } + /* Sub function enable setting */ + PFSRx->BFE = pstcPortInit->enPinSubFunc; + } + } + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port de-init + ** + ** \param None + ** + ** \retval Ok GPIO de-initial successful + ** + ******************************************************************************/ +en_result_t PORT_DeInit(void) +{ + uint8_t u8PortIdx, u8PinIdx; + PORT_Unlock(); + + for (u8PortIdx = (uint8_t)PortA; u8PortIdx <= (uint8_t)PortH; u8PortIdx++) + { + *(uint16_t *)(GPIO_BASE + PODR_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + POER_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + POSR_BASE + u8PortIdx * 0x10ul) = 0u; + *(uint16_t *)(GPIO_BASE + PORR_BASE + u8PortIdx * 0x10ul) = 0u; + for (u8PinIdx = 0u; u8PinIdx < 16u; u8PinIdx++) + { + if (((uint8_t)PortH == u8PortIdx) && (3u == u8PinIdx)) + { + break; + } + *(uint16_t *)(GPIO_BASE + PCR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u; + *(uint16_t *)(GPIO_BASE + PFSR_BASE + u8PortIdx * 0x40ul + u8PinIdx * 0x4ul) = 0u; + } + } + M4_PORT->PCCR = 0u; + M4_PORT->PINAER = 0u; + M4_PORT->PSPCR = 0x1Fu; + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Special control register Setting + ** + ** \param [in] u8DebugPort Debug port setting register, This parameter + ** can be any composed value of @ref en_debug_port_t + ** + ** \param [in] enFunc The new state of the debug ports. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Debug port set successful + ** + ******************************************************************************/ +en_result_t PORT_DebugPortSetting(uint8_t u8DebugPort, en_functional_state_t enFunc) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_DEBUGPIN(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enFunc)); + + PORT_Unlock(); + + if (Enable == enFunc) + { + M4_PORT->PSPCR |= (uint16_t)(u8DebugPort & 0x1Ful); + } + else + { + M4_PORT->PSPCR &= (uint16_t)(~(u8DebugPort & 0x1Ful)); + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port Public Setting + ** + ** \param [in] pstcPortPubSet Structure pointer of public setting (PCCR) + ** + ** \retval Ok Port public register set successful + ** + ******************************************************************************/ +en_result_t PORT_PubSetting(const stc_port_pub_set_t *pstcPortPubSet) +{ + DDL_ASSERT(IS_VALID_FUNC(pstcPortPubSet->enSubFuncSel)); + DDL_ASSERT(IS_VALID_READWAIT(pstcPortPubSet->enReadWait)); + PORT_Unlock(); + + /* PCCR setting */ + /* Sub function setting */ + M4_PORT->PCCR_f.BFSEL = pstcPortPubSet->enSubFuncSel; + + /* PIDRx, PCRxy read wait cycle setting */ + M4_PORT->PCCR_f.RDWT = pstcPortPubSet->enReadWait; + + PORT_Lock(); + return Ok; +} + + +/** + ******************************************************************************* + ** \brief PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PORT_Unlock(void) +{ + M4_PORT->PWPR = 0xA501u; +} + +/** + ******************************************************************************* + ** \brief SPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PORT_Lock(void) +{ + M4_PORT->PWPR = 0xA500u; +} + +/** + ******************************************************************************* + ** \brief Read Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** + ** \retval uint16_t The output port value + ** + ******************************************************************************/ +uint16_t PORT_GetData(en_port_t enPort) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + uint32_t *PIDRx; + PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort); + return (uint16_t)(*PIDRx); +} + +/** + ******************************************************************************* + ** \brief Read Pin value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] enPin GPIO pin index, This parameter can be + ** any value of @ref en_pin_t + ** \retval en_flag_status_t The output port pin value + ** + ******************************************************************************/ +en_flag_status_t PORT_GetBit(en_port_t enPort, en_pin_t enPin) +{ + uint32_t *PIDRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_VALID_PIN(enPin)); + + PIDRx = (uint32_t *)((uint32_t)(&M4_PORT->PIDRA) + 0x10u * enPort); + return (en_flag_status_t)((bool)(!!(*PIDRx & (enPin)))); +} + +/** + ******************************************************************************* + ** \brief Set Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** + ** \retval Ok Data be set to corresponding port + ** + ******************************************************************************/ +en_result_t PORT_SetPortData(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PODRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort); + *PODRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set Port value + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** + ** \retval Ok Data be reset to corresponding port + ** + ******************************************************************************/ +en_result_t PORT_ResetPortData(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PODRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PODRx = (uint16_t *)((uint32_t)(&M4_PORT->PODRA) + 0x10u * enPort); + *PODRx &= (uint16_t)(~u16Pin); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Port Pin Output enable + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \param [in] enNewState The new state of pin direction setting + ** \retval Ok Set successful to corresponding port/pin + ** + ******************************************************************************/ +en_result_t PORT_OE(en_port_t enPort, uint16_t u16Pin, en_functional_state_t enNewState) +{ + uint16_t *POERx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POERx = (uint16_t *)((uint32_t)(&M4_PORT->POERA) + 0x10ul * enPort); + if (Enable == enNewState) + { + *POERx |= u16Pin; + } + else + { + *POERx &= (uint16_t)(~u16Pin); + } + return Ok; + +} + +/** + ******************************************************************************* + ** \brief Set Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetBits(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *POSRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POSRx = (uint16_t *)((uint32_t)(&M4_PORT->POSRA) + 0x10u * enPort); + *POSRx |= u16Pin; + return Ok; + +} + +/** + ******************************************************************************* + ** \brief Reset Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_ResetBits(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *PORRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + PORRx = (uint16_t *)((uint32_t)(&M4_PORT->PORRA) + 0x10u * enPort); + *PORRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Toggle Port Pin + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any composed value of @ref en_pin_t + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_Toggle(en_port_t enPort, uint16_t u16Pin) +{ + uint16_t *POTRx; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + + POTRx = (uint16_t *)((uint32_t)(&M4_PORT->POTRA) + 0x10u * enPort); + *POTRx |= u16Pin; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set port always ON + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] enNewState The new state of the port always ON function. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_AlwaysOn(en_port_t enPort, en_functional_state_t enNewState) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + PORT_Unlock(); + + if (Enable == enNewState) + { + M4_PORT->PINAER |= Enable << (uint8_t)enPort; + } + else + { + M4_PORT->PINAER &= (uint16_t)(~(((1ul << (uint8_t)enPort)) & 0x1Ful)); + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set Port Pin function + ** + ** \param [in] enPort GPIO port index, This parameter can be + ** any value of @ref en_port_t + ** \param [in] u16Pin GPIO pin index, This parameter can be + ** any value of @ref en_pin_t + ** \param [in] enFuncSel Function selection, This parameter can be + ** any value of @ref en_port_func_t + ** + ** \param [in] enSubFunc The new state of the gpio sub-function. + ** \arg Enable Enable. + ** \arg Disable Disable. + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, en_port_func_t enFuncSel, \ + en_functional_state_t enSubFunc) +{ + stc_port_pfsr_field_t *PFSRx; + uint8_t u8PinPos = 0u; + + /* parameter check */ + DDL_ASSERT(IS_VALID_PORT(enPort)); + DDL_ASSERT(IS_VALID_FUNC(enFuncSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enSubFunc)); + + PORT_Unlock(); + + for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++) + { + if (u16Pin & (uint16_t)(1ul<PFSRA0) \ + + 0x40ul * enPort + 0x4ul * u8PinPos); + + /* main function setting */ + PFSRx->FSEL = enFuncSel; + + /* sub function enable setting */ + PFSRx->BFE = (Enable == enSubFunc ? Enable : Disable); + } + } + + PORT_Lock(); + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set global sub-function + ** + ** \param [in] enFuncSel Function selection, This parameter can be + ** some values of @ref en_port_func_t, cannot + ** large than 15u + ** + ** \retval Ok Set successful to corresponding pins + ** + ******************************************************************************/ +en_result_t PORT_SetSubFunc(en_port_func_t enFuncSel) +{ + /* parameter check */ + DDL_ASSERT(IS_VALID_SUBFUNC(enFuncSel)); + + PORT_Unlock(); + + M4_PORT->PCCR_f.BFSEL = enFuncSel; + + PORT_Lock(); + return Ok; +} + +//@} // GpioGroup + +#endif /* DDL_GPIO_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_hash.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_hash.c new file mode 100644 index 0000000000..393736bac6 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_hash.c @@ -0,0 +1,301 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_hash.c + ** + ** A detailed description is available at + ** @link HashGroup HASH description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of HASH. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_hash.h" +#include "hc32f460_utility.h" + +#if (DDL_HASH_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup HashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Constants definitions. */ +#define HASH_GROUP_LEN (64u) +#define LAST_GROUP_MAX_LEN (56u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void HASH_WriteData(const uint8_t *pu8SrcData); +static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize the HASH. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void HASH_Init(void) +{ + /* Stop hash calculating */ + bM4_HASH_CR_START = 0u; +} + +/** + ******************************************************************************* + ** \brief DeInitialize the HASH. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void HASH_DeInit(void) +{ + /* Stop hash calculating */ + bM4_HASH_CR_START = 0u; + + /* Reset register CR. */ + M4_HASH->CR = 0u; +} + +/** + ******************************************************************************* + ** \brief HASH(SHA256) processes pu8SrcData. + ** + ** \param [in] pu8SrcData Pointer to the source data buffer (buffer to + ** be hashed). + ** + ** \param [in] u32SrcDataSize Length of the input buffer in bytes. + ** + ** \param [out] pu8MsgDigest Pointer to the computed digest. Its size + ** must be 32 bytes. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout HASH works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t HASH_Start(const uint8_t *pu8SrcData, + uint32_t u32SrcDataSize, + uint8_t *pu8MsgDigest, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint8_t u8FillBuffer[HASH_GROUP_LEN]; + uint8_t u8FirstGroup = 0u; + uint8_t u8HashEnd = 0u; + uint8_t u8DataEndMark = 0u; + uint32_t u32Index = 0u; + uint32_t u32BitLenHi; + uint32_t u32BitLenLo; + uint32_t u32HashTimeout; + __IO uint32_t u32TimeCount; + + if ((NULL != pu8SrcData) && + (0u != u32SrcDataSize) && + (NULL != pu8MsgDigest) && + (0u != u32Timeout)) + { + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32HashTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + u32BitLenHi = (u32SrcDataSize >> 29u) & 0x7u; + u32BitLenLo = (u32SrcDataSize << 3u); + + while (1u) + { + /* Stop hash calculating. */ + bM4_HASH_CR_START = 0u; + + if (u32SrcDataSize >= HASH_GROUP_LEN) + { + HASH_WriteData(&pu8SrcData[u32Index]); + u32SrcDataSize -= HASH_GROUP_LEN; + u32Index += HASH_GROUP_LEN; + } + else if (u32SrcDataSize >= LAST_GROUP_MAX_LEN) + { + memset(u8FillBuffer, 0, HASH_GROUP_LEN); + memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize); + u8FillBuffer[u32SrcDataSize] = 0x80u; + u8DataEndMark = 1u; + HASH_WriteData(u8FillBuffer); + u32SrcDataSize = 0u; + } + else + { + u8HashEnd = 1u; + } + + if (u8HashEnd != 0u) + { + memset(u8FillBuffer, 0, HASH_GROUP_LEN); + if (u32SrcDataSize > 0u) + { + memcpy(u8FillBuffer, &pu8SrcData[u32Index], u32SrcDataSize); + } + if (u8DataEndMark == 0u) + { + u8FillBuffer[u32SrcDataSize] = 0x80u; + } + u8FillBuffer[63u] = (uint8_t)(u32BitLenLo); + u8FillBuffer[62u] = (uint8_t)(u32BitLenLo >> 8u); + u8FillBuffer[61u] = (uint8_t)(u32BitLenLo >> 16u); + u8FillBuffer[60u] = (uint8_t)(u32BitLenLo >> 24u); + u8FillBuffer[59u] = (uint8_t)(u32BitLenHi); + u8FillBuffer[58u] = (uint8_t)(u32BitLenHi >> 8u); + u8FillBuffer[57u] = (uint8_t)(u32BitLenHi >> 16u); + u8FillBuffer[56u] = (uint8_t)(u32BitLenHi >> 24u); + HASH_WriteData(u8FillBuffer); + } + + /* check if first group */ + if (0u == u8FirstGroup) + { + u8FirstGroup = 1u; + /* Set first group. */ + bM4_HASH_CR_FST_GRP = 1u; + } + else + { + /* Set continuous group. */ + bM4_HASH_CR_FST_GRP = 0u; + } + + /* Start hash calculating. */ + bM4_HASH_CR_START = 1u; + + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32HashTimeout) + { + if (bM4_HASH_CR_START == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if ((ErrorTimeout == enRet) || (u8HashEnd != 0u)) + { + break; + } + } + + if (Ok == enRet) + { + /* HASH calculated done */ + HASH_GetMsgDigest(pu8MsgDigest); + } + + /* Stop hash calculating. */ + bM4_HASH_CR_START = 0u; + } + + return enRet; +} + +/******************************************************************************* + * Function implementation - local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Writes the input buffer in data register. + ** + ** \param [in] pu8SrcData Pointer to source data buffer. + ** + ** \retval None + ** + ******************************************************************************/ +static void HASH_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + uint8_t j; + uint32_t u32Temp; + __IO uint32_t *io32HashDr = &(M4_HASH->DR15); + + for (i = 0u; i < 16u; i++) + { + j = i * 4u + 3u; + u32Temp = (uint32_t)pu8SrcData[j]; + u32Temp |= ((uint32_t)pu8SrcData[j-1u]) << 8u; + u32Temp |= ((uint32_t)pu8SrcData[j-2u]) << 16u; + u32Temp |= ((uint32_t)pu8SrcData[j-3u]) << 24u; + + *io32HashDr = u32Temp; + io32HashDr++; + } +} + +/** + ******************************************************************************* + ** \brief Provides the message digest result. + ** + ** \param [out] pu8MsgDigest Pointer to the message digest. + ** + ** \retval None + ** + ******************************************************************************/ +static void HASH_GetMsgDigest(uint8_t *pu8MsgDigest) +{ + uint8_t i; + uint8_t j; + uint32_t u32Temp; + __IO uint32_t *io32HashHr = &(M4_HASH->HR7); + + for (i = 0u; i < 8u; i++) + { + j = i * 4u + 3u; + u32Temp = *io32HashHr; + + pu8MsgDigest[j] = (uint8_t)u32Temp; + pu8MsgDigest[j-1u] = (uint8_t)(u32Temp >> 8u); + pu8MsgDigest[j-2u] = (uint8_t)(u32Temp >> 16u); + pu8MsgDigest[j-3u] = (uint8_t)(u32Temp >> 24u); + + io32HashHr++; + } +} + +//@} // HashGroup + +#endif /* DDL_HASH_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2c.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2c.c new file mode 100644 index 0000000000..f5b4fddcd2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2c.c @@ -0,0 +1,1318 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2c.c + ** + ** A detailed description is available at + ** @link I2cGroup Inter-Integrated Circuit(I2C) description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of I2C. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_i2c.h" +#include "hc32f460_utility.h" + +#if (DDL_I2C_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup I2cGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Config I2C peripheral */ +#define I2C_SRC_CLK (SystemCoreClock >> M4_SYSREG->CMU_SCFGR_f.PCLK3S) +#define I2C_ANA_FILTER_VALID (1U) +#define I2C_CLK_TIMEOUT_VALID (1U) + +#define I2C_BAUDRATE_MAX (400000ul) + +/*! Parameter validity check for unit. */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_I2C1) || \ + ((x) == M4_I2C2) || \ + ((x) == M4_I2C3)) + +/*! Parameter check for I2C baudrate value !*/ +#define IS_VALID_SPEED(speed) ((speed) <= (I2C_BAUDRATE_MAX)) + +/*! Parameter check for I2C baudrate calculate prccess !*/ +#define IS_VALID_FDIV(x) \ +( ((x) == I2C_CLK_DIV1) || \ + ((x) == I2C_CLK_DIV2) || \ + ((x) == I2C_CLK_DIV4) || \ + ((x) == I2C_CLK_DIV8) || \ + ((x) == I2C_CLK_DIV16) || \ + ((x) == I2C_CLK_DIV32) || \ + ((x) == I2C_CLK_DIV64) || \ + ((x) == I2C_CLK_DIV128)) + +#define IS_VALID_BAUDWIDTH(result) ((result) == true) + +/*! Parameter check for Digital filter config !*/ +#define IS_VALID_DIGITAL_FILTER(x) \ +( ((x) == Filter1BaseCycle) || \ + ((x) == Filter2BaseCycle) || \ + ((x) == Filter3BaseCycle) || \ + ((x) == Filter4BaseCycle)) + +/*! Parameter check for address mode !*/ +#define IS_VALID_ADRMODE(x) \ +( ((x) == Adr7bit) || \ + ((x) == Adr10bit)) + +/*! Parameter check for I2C transfer direction !*/ +#define IS_VALID_TRANS_DIR(x) \ +( ((x) == I2CDirReceive) || \ + ((x) == I2CDirTrans)) + +/*! Parameter check for Time out control switch !*/ +#define IS_VALID_TIMOUT_SWITCH(x) \ +( ((x) == TimeoutFunOff) || \ + ((x) == LowTimerOutOn) || \ + ((x) == HighTimeOutOn) || \ + ((x) == BothTimeOutOn)) + +/*! Parameter check for I2C 7 bit address range !*/ +#define IS_VALID_7BIT_ADR(x) ((x) <= 0x7F) + +/*! Parameter check for I2C 10 bit address range !*/ +#define IS_VALID_10BIT_ADR(x) ((x) <= 0x3FF) + +/*! Parameter check for readable I2C status bit !*/ +#define IS_VALID_RD_STATUS_BIT(x) \ +( ((x) == I2C_SR_STARTF) || \ + ((x) == I2C_SR_SLADDR0F) || \ + ((x) == I2C_SR_SLADDR1F) || \ + ((x) == I2C_SR_TENDF) || \ + ((x) == I2C_SR_STOPF) || \ + ((x) == I2C_SR_RFULLF) || \ + ((x) == I2C_SR_TEMPTYF) || \ + ((x) == I2C_SR_ARLOF) || \ + ((x) == I2C_SR_ACKRF) || \ + ((x) == I2C_SR_NACKF) || \ + ((x) == I2C_SR_TMOUTF) || \ + ((x) == I2C_SR_MSL) || \ + ((x) == I2C_SR_BUSY) || \ + ((x) == I2C_SR_TRA) || \ + ((x) == I2C_SR_GENCALLF) || \ + ((x) == I2C_SR_SMBDEFAULTF) || \ + ((x) == I2C_SR_SMBHOSTF) || \ + ((x) == I2C_SR_SMBALRTF)) + +#define IS_VALID_ACK_CONFIG(x) \ +( ((x) == I2c_ACK) || \ + ((x) == I2c_NACK)) + +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x1F * (float32_t)2) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Try to wait a status of specified flags + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Flag specifies the flag to check, + ** This parameter can be one of the following values: + ** I2C_SR_STARTF + ** I2C_SR_SLADDR0F + ** I2C_SR_SLADDR1F + ** I2C_SR_TENDF + ** I2C_SR_STOPF + ** I2C_SR_RFULLF + ** I2C_SR_TEMPTYF + ** I2C_SR_ARLOF + ** I2C_SR_ACKRF: ACK status + ** I2C_SR_NACKF: NACK Flag + ** I2C_SR_TMOUTF + ** I2C_SR_MSL + ** I2C_SR_BUSY + ** I2C_SR_TRA + ** I2C_SR_GENCALLF + ** I2C_SR_SMBDEFAULTF + ** I2C_SR_SMBHOSTF + ** I2C_SR_SMBALRTF + ** \param [in] enStatus Expected status, This parameter can be one of + ** the following values: + ** Set + ** Reset + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Successfully gotten the expected status of the specified flags + ** \retval ErrorTimeout Failed to get expected status of specified flags. + ******************************************************************************/ +en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *pstcI2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorTimeout; + uint32_t u32RegStatusBit; + + for(;;) + { + u32RegStatusBit = (pstcI2Cx->SR & u32Flag); + if(((enStatus == Set) && (u32Flag == u32RegStatusBit)) + || ((enStatus == Reset) && (0UL == u32RegStatusBit))) + { + enRet = Ok; + } + + if((Ok == enRet) || (0UL == u32Timeout)) + { + break; + } + else + { + u32Timeout--; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2C generate start condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState new state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.START = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C generate restart condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateReStart(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.RESTART = enNewState; + +} + +/** + ******************************************************************************* + ** \brief I2C generate stop condition + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GenerateStop(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.STOP = enNewState; +} + +/** + ******************************************************************************* + ** \brief Set the baudrate for I2C peripheral. + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + ** 1. pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + ** step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + ** I2cSrcClk -- I2c source clock + ** Baudrate -- baudrate of i2c + ** SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + ** according to i2c bus hardware parameter. + ** dnfsum -- 0 if digital filter off; + ** Filter capacity if digital filter on(1 ~ 4) + ** step2: chose a division item which is similar and bigger than div + ** from @ref I2C_Clock_Division. + ** 2. pstcI2cInit->u32Baudrate : Baudrate configuration + ** 3. pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + ** time, should be number of T(i2c clock period time) + ** @param [out] pf32Error Baudrate error + ** @retval en_result_t Enumeration value: + ** @arg Ok: Configurate success + ** @arg ErrorInvalidParameter: Invalid parameter + ******************************************************************************/ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error) +{ + en_result_t enRet = Ok; + uint32_t I2cSrcClk; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t dnfsum = 0UL; + uint32_t divsum = 2UL; + uint32_t TheoryBaudrate; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2cInit) || (NULL == pf32Error)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_VALID_FDIV(pstcI2cInit->u32ClockDiv)); + + /* Get configuration for i2c */ + I2cSrcClk = I2C_SRC_CLK; + I2cDivClk = 1ul << pstcI2cInit->u32ClockDiv; + SclCnt = pstcI2cInit->u32SclTime; + Baudrate = pstcI2cInit->u32Baudrate; + + /* Judge digital filter status */ + if(1u == pstcI2Cx->FLTR_f.DNFEN) + { + dnfsum = pstcI2Cx->FLTR_f.DNF+1ul; + } + + /* Judge if clock divider on*/ + if(I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) + { + divsum = 3ul; + } + + WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = (2.0F*(float32_t)divsum) + (2.0F*(float32_t)dnfsum) + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + /* Integer for WidthTotal, rounding off */ + if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) + { + WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F; + } + else + { + WidthTotal = (float32_t)((uint32_t)WidthTotal); + } + + if(WidthTotal <= SumTotal) + { + /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */ + enRet = ErrorInvalidParameter; + } + else + { + if(WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) + { + /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */ + enRet = ErrorInvalidParameter; + } + else + { + TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk; + fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate; + + /* Write register */ + pstcI2Cx->CCR_f.FREQ = pstcI2cInit->u32ClockDiv; + pstcI2Cx->CCR_f.SLOWW = (uint32_t)WidthHL/2u; + pstcI2Cx->CCR_f.SHIGHW = (uint32_t)WidthHL - ((uint32_t)WidthHL)/2u; + } + } + } + + if((NULL != pf32Error) && (Ok == enRet)) + { + *pf32Error = fErr; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize I2C unit + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \retval Ok Process finished. + ******************************************************************************/ +en_result_t I2C_DeInit(M4_I2C_TypeDef* pstcI2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Reset peripheral register and internal status*/ + pstcI2Cx->CR1_f.PE = 0u; + pstcI2Cx->CR1_f.SWRST = 1u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Initialize I2C peripheral according to the structure + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + ** 1. pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + ** step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + ** I2cSrcClk -- I2c source clock + ** Baudrate -- baudrate of i2c + ** SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + ** according to i2c bus hardware parameter. + ** dnfsum -- 0 if digital filter off; + ** Filter capacity if digital filter on(1 ~ 4) + ** step2: chose a division item which is similar and bigger than div + ** from @ref I2C_Clock_Division. + ** 2. pstcI2cInit->u32Baudrate : Baudrate configuration + ** 3. pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + ** time, should be number of T(i2c clock period time) + ** @param [out] pf32Error Baudrate error + ** @retval en_result_t Enumeration value: + ** @arg Ok: Configurate success + ** @arg ErrorInvalidParameter: Invalid parameter + ******************************************************************************/ +en_result_t I2C_Init(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_init_t* pstcI2cInit, float32_t *pf32Error) +{ + en_result_t enRes = Ok; + if((NULL == pstcI2cInit) || (NULL == pstcI2Cx)) + { + enRes = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_VALID_FDIV(pstcI2cInit->u32ClockDiv)); + + /* Register and internal status reset */ + pstcI2Cx->CR1_f.PE = 0u; + pstcI2Cx->CR1_f.SWRST = 1u; + + pstcI2Cx->CR1_f.PE = 1u; + + enRes = I2C_BaudrateConfig(pstcI2Cx, pstcI2cInit, pf32Error); + + pstcI2Cx->CR1_f.ENGC = 0u; + pstcI2Cx->CR1_f.SWRST = 0u; + pstcI2Cx->CR1_f.PE = 0u; + } + return enRes; +} + +/** + ******************************************************************************* + ** \brief I2C slave address0 config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \param [in] enAdrMode Address mode,can be Adr7bit or Adr10bit + ** \param [in] u32Adr The slave address + ** \retval None + ******************************************************************************/ +void I2C_SlaveAdr0Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_ADRMODE(enAdrMode)); + + pstcI2Cx->SLR0_f.SLADDR0EN = enNewState; + pstcI2Cx->SLR0_f.ADDRMOD0 = enAdrMode; + if(Adr7bit == enAdrMode) + { + DDL_ASSERT(IS_VALID_7BIT_ADR(u32Adr)); + pstcI2Cx->SLR0_f.SLADDR0 = u32Adr << 1ul; + } + else + { + DDL_ASSERT(IS_VALID_10BIT_ADR(u32Adr)); + pstcI2Cx->SLR0_f.SLADDR0 = u32Adr; + } +} + +/** + ******************************************************************************* + ** \brief I2C slave address1 config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \param [in] enAdrMode Address mode,can be Adr7bit or Adr10bit + ** \param [in] u32Adr The slave address + ** \retval None + ******************************************************************************/ +void I2C_SlaveAdr1Config(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState, en_address_bit_t enAdrMode, uint32_t u32Adr) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_ADRMODE(enAdrMode)); + + pstcI2Cx->SLR1_f.SLADDR1EN = enNewState; + pstcI2Cx->SLR1_f.ADDRMOD1 = enAdrMode; + if(Adr7bit == enAdrMode) + { + DDL_ASSERT(IS_VALID_7BIT_ADR(u32Adr)); + pstcI2Cx->SLR1_f.SLADDR1 = u32Adr << 1ul; + } + else + { + DDL_ASSERT(IS_VALID_10BIT_ADR(u32Adr)); + pstcI2Cx->SLR1_f.SLADDR1 = u32Adr; + } +} + +/** + ******************************************************************************* + ** \brief I2C function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_Cmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.PE = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C fast ACK function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the fast ACK function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_FastAckCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR3_f.FACKEN = 0ul; + } + else + { + pstcI2Cx->CR3_f.FACKEN = 1ul; + } +} + +/** + ******************************************************************************* + ** \brief I2C bus wait function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the fast ACK function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_BusWaitCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + uint32_t u32CR4_Reg = ((uint32_t)&pstcI2Cx->CR3) + 4ul; + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + *(__IO uint32_t *)u32CR4_Reg |= (1ul << 10ul); + } + else + { + *(__IO uint32_t *)u32CR4_Reg &= ~(1ul << 10ul); + } +} + +/** + ******************************************************************************* + ** \brief I2C SMBUS function configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcI2C_SmbusInitStruct + ** Pointer to I2C SMBUS configuration structure + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ******************************************************************************/ +en_result_t I2C_SmbusConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_i2c_smbus_init_t* pstcI2C_SmbusInitStruct) +{ + en_result_t enRet = Ok; + if(NULL != pstcI2C_SmbusInitStruct) + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enHostAdrMatchFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enDefaultAdrMatchFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcI2C_SmbusInitStruct->enAlarmAdrMatchFunc)); + + pstcI2Cx->CR1_f.SMBHOSTEN = pstcI2C_SmbusInitStruct->enHostAdrMatchFunc; + pstcI2Cx->CR1_f.SMBDEFAULTEN = pstcI2C_SmbusInitStruct->enDefaultAdrMatchFunc; + pstcI2Cx->CR1_f.SMBALRTEN = pstcI2C_SmbusInitStruct->enAlarmAdrMatchFunc; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2C SMBUS function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_SmBusCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.SMBUS = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C digital filter function configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enDigiFilterMode Chose the digital filter mode, This parameter + ** can be one of the following values: + ** Filter1BaseCycle + ** Filter2BaseCycle + ** Filter3BaseCycle + ** Filter4BaseCycle + ** \retval None + ******************************************************************************/ +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_digital_filter_mode_t enDigiFilterMode) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_DIGITAL_FILTER(enDigiFilterMode)); + + pstcI2Cx->FLTR_f.DNF = enDigiFilterMode; +} + +/** + ******************************************************************************* + ** \brief I2C digital filter function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->FLTR_f.DNFEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C analog filter function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->FLTR_f.ANFEN = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C general call function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_GeneralCallCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.ENGC = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C status bit get + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32StatusBit specifies the flag to check, + ** This parameter can be one of the following values: + ** I2C_SR_STARTF + ** I2C_SR_SLADDR0F + ** I2C_SR_SLADDR1F + ** I2C_SR_TENDF + ** I2C_SR_STOPF + ** I2C_SR_RFULLF + ** I2C_SR_TEMPTYF + ** I2C_SR_ARLOF + ** I2C_SR_ACKRF: ACK status + ** I2C_SR_NACKF: NACK Flag + ** I2C_SR_TMOUTF + ** I2C_SR_MSL + ** I2C_SR_BUSY + ** I2C_SR_TRA + ** I2C_SR_GENCALLF + ** I2C_SR_SMBDEFAULTF + ** I2C_SR_SMBHOSTF + ** I2C_SR_SMBALRTF + ** \retval en_flag_status_t The status of the I2C status flag, may be Set or Reset. + ******************************************************************************/ +en_flag_status_t I2C_GetStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit) +{ + en_flag_status_t enRet = Reset; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_RD_STATUS_BIT(u32StatusBit)); + + if(0ul != (pstcI2Cx->SR & u32StatusBit)) + { + enRet = Set; + } + else + { + enRet = Reset; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear I2C status flag + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32StatusBit specifies the flag to clear, + ** This parameter can be any combination of the following values: + ** I2C_CLR_STARTFCLR + ** I2C_CLR_SLADDR0FCLR + ** I2C_CLR_SLADDR1FCLR + ** I2C_CLR_TENDFCLR + ** I2C_CLR_STOPFCLR + ** I2C_CLR_RFULLFCLR + ** I2C_CLR_TEMPTYFCLR + ** I2C_CLR_ARLOFCLR + ** I2C_CLR_NACKFCLR + ** I2C_CLR_TMOUTFCLR + ** I2C_CLR_GENCALLFCLR + ** I2C_CLR_SMBDEFAULTFCLR + ** I2C_CLR_SMBHOSTFCLR + ** I2C_CLR_SMBALRTFCLR + ** \retval None + ******************************************************************************/ +void I2C_ClearStatus(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32StatusBit) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + pstcI2Cx->CLR |= (u32StatusBit & I2C_CLR_MASK); +} + +/** + ******************************************************************************* + ** \brief I2C software reset function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* pstcI2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + pstcI2Cx->CR1_f.SWRST = enNewState; +} + +/** + ******************************************************************************* + ** \brief I2C interrupt function command + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32IntEn Specifies the I2C interrupts sources to be configuration + ** This parameter can be any combination of the following values: + ** I2C_CR2_STARTIE + ** I2C_CR2_SLADDR0EN + ** I2C_CR2_SLADDR1EN + ** I2C_CR2_TENDIE + ** I2C_CR2_STOPIE + ** I2C_CR2_RFULLIE + ** I2C_CR2_TEMPTYIE + ** I2C_CR2_ARLOIE + ** I2C_CR2_NACKIE + ** I2C_CR2_TMOURIE + ** I2C_CR2_GENCALLIE + ** I2C_CR2_SMBDEFAULTIE + ** I2C_CR2_SMBHOSTIE + ** I2C_CR2_SMBALRTIE + ** \param [in] enNewState New state of the I2Cx function, can be + ** Disable or Enable the function + ** \retval None + ******************************************************************************/ +void I2C_IntCmd(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32IntEn, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + pstcI2Cx->CR2 |= u32IntEn; + } + else + { + pstcI2Cx->CR2 &= ~u32IntEn; + } +} + +/** + ******************************************************************************* + ** \brief I2C write data register + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u8Data The data to be send + ** \retval None + ******************************************************************************/ +void I2C_WriteData(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + pstcI2Cx->DTR = u8Data; +} + +/** + ******************************************************************************* + ** \brief I2C read data register + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \retval uint8_t The value of the received data + ******************************************************************************/ +uint8_t I2C_ReadData(M4_I2C_TypeDef* pstcI2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + return pstcI2Cx->DRR; +} + +/** + ******************************************************************************* + ** \brief I2C ACK status configuration + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32AckConfig I2C ACK configurate. + ** I2c_ACK: Send ACK after date received. + ** I2c_NACK: Send NACK after date received. + ** \retval None + ******************************************************************************/ +void I2C_AckConfig(M4_I2C_TypeDef* pstcI2Cx, en_i2c_ack_config_t u32AckConfig) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_ACK_CONFIG(u32AckConfig)); + + pstcI2Cx->CR1_f.ACK = u32AckConfig; +} + +/** + ******************************************************************************* + ** \brief I2C clock timer out function config + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] pstcTimoutInit Pointer to I2C timeout function structure + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ******************************************************************************/ +en_result_t I2C_ClkTimeOutConfig(M4_I2C_TypeDef* pstcI2Cx, const stc_clock_timeout_init_t* pstcTimoutInit) +{ + en_result_t enRet = Ok; + if(NULL != pstcTimoutInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_TIMOUT_SWITCH(pstcTimoutInit->enClkTimeOutSwitch)); + + pstcI2Cx->SLTR_f.TOUTHIGH = pstcTimoutInit->u16TimeOutHigh; + pstcI2Cx->SLTR_f.TOUTLOW = pstcTimoutInit->u16TimeOutLow; + + pstcI2Cx->CR3 &= ~0x00000007ul; + pstcI2Cx->CR3 |= pstcTimoutInit->enClkTimeOutSwitch; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx start + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Start success + ** \retval ErrorTimeout Start time out + ******************************************************************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_BUSY, Reset, u32Timeout); + + if(Ok == enRet) + { + /* generate start signal */ + I2C_GenerateStart(pstcI2Cx, Enable); + /* Judge if start success*/ + enRet = I2C_WaitStatus(pstcI2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx restart + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok Restart successfully + ** \retval ErrorTimeout Restart time out + ******************************************************************************/ +en_result_t I2C_Restart(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Clear start status flag */ + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STARTFCLR); + /* Send restart condition */ + I2C_GenerateReStart(pstcI2Cx, Enable); + /* Judge if start success*/ + enRet = I2C_WaitStatus(pstcI2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send address + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u8Addr The address to be sent + ** \param [in] enDir Can be I2CDirTrans or I2CDirReceive + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval Error: Send suscessfully and receive NACK + ** \retval ErrorTimeout: Send address time out + ******************************************************************************/ +en_result_t I2C_TransAddr(M4_I2C_TypeDef* pstcI2Cx, uint8_t u8Addr, en_trans_direction_t enDir, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_7BIT_ADR(u8Addr)); + DDL_ASSERT(IS_VALID_TRANS_DIR(enDir)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Send I2C address */ + I2C_WriteData(pstcI2Cx, (u8Addr << 1u) | (uint8_t)enDir); + + if(I2CDirTrans == enDir) + { + /* If in master transfer process, Need wait transfer end */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + } + else + { + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TRA, Reset, u32Timeout); + } + + if(enRet == Ok) + { + /* If receive NACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) == Set) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send address 10 bit + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u16Addr The address to be sent + ** \param [in] enDir Can be I2CDirTrans or I2CDirReceive + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval Error: Send suscessfully and receive NACK + ** \retval ErrorTimeout: Send address time out + ******************************************************************************/ +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* pstcI2Cx, uint16_t u16Addr, en_trans_direction_t enDir, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + DDL_ASSERT(IS_VALID_10BIT_ADR(u16Addr)); + DDL_ASSERT(IS_VALID_TRANS_DIR(enDir)); + + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteData(pstcI2Cx, (uint8_t)((u16Addr>>7u) & 0x06u) | 0xF0u | (uint8_t)I2CDirTrans); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + /* If receive ACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) == Reset) + { + /* Write SLA(bit7:0)*/ + I2C_WriteData(pstcI2Cx, (uint8_t)(u16Addr & 0xFFu)); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + else + { + enRet = Error; + } + } + } + + if((I2CDirReceive == enDir) && (Ok == enRet)) + { + /* Restart */ + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STARTFCLR); + I2C_GenerateReStart(pstcI2Cx, Enable); + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STARTF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteData(pstcI2Cx, (uint8_t)((u16Addr>>7u) & 0x06u) | 0xF0u | (uint8_t)I2CDirReceive); + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TRA, Reset, u32Timeout); + + if(Ok == enRet) + { + /* If receive NACK */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx send data + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] au8TxData The data array to be sent + ** \param [in] u32Size Number of data in array pau8TxData + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Send successfully + ** \retval ErrorTimeout: Send data time out + ** \retval ErrorInvalidParameter: au8TxData is NULL + ******************************************************************************/ +en_result_t I2C_TransData(M4_I2C_TypeDef* pstcI2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + en_result_t enRet = Ok; + __IO uint32_t u32Cnt = 0ul; + + if(au8TxData != NULL) + { + while((u32Cnt != u32Size) && (enRet == Ok)) + { + /* Wait tx buffer empty */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(enRet == Ok) + { + /* Send one byte data */ + I2C_WriteData(pstcI2Cx, au8TxData[u32Cnt]); + + /* Wait transfer end */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_TENDF, Set, u32Timeout); + + /* If receive NACK in slave tx mode */ + if(I2C_GetStatus(pstcI2Cx, I2C_SR_NACKF) == Set) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_NACKFCLR); + /* Exit data transfer */ + break; + } + + u32Cnt++; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx receive data + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [out] au8RxData Array to hold the received data + ** \param [in] u32Size Number of data to be received + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ** \retval ErrorInvalidParameter: au8RxData is NULL + ******************************************************************************/ +en_result_t I2C_ReceiveData(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckDis = (pstcI2Cx->CR3_f.FACKEN); + for(uint32_t i=0ul; i= 2ul) && (i == (u32Size - 2ul))) + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + else + { + if(i != (u32Size - 1ul)) + { + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + + if(enRet == Ok) + { + /* read data from register */ + au8RxData[i] = I2C_ReadData(pstcI2Cx); + } + else + { + break; + } + } + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx master receive data and stop + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [out] au8RxData Array to hold the received data + ** \param [in] u32Size Number of data to be received + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ** \retval ErrorInvalidParameter: au8RxData is NULL + ******************************************************************************/ +en_result_t I2C_MasterDataReceiveAndStop(M4_I2C_TypeDef* pstcI2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckDis = (pstcI2Cx->CR3_f.FACKEN); + for(uint32_t i=0ul; i= 2ul) && (i == (u32Size - 2ul))) + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + else + { + if(i != (u32Size - 1ul)) + { + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + I2C_AckConfig(pstcI2Cx, I2c_NACK); + } + } + + if(enRet == Ok) + { + /* Stop before read last data */ + if(i == (u32Size - 1ul)) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STOPFCLR); + I2C_GenerateStop(pstcI2Cx, Enable); + } + + /* read data from register */ + au8RxData[i] = I2C_ReadData(pstcI2Cx); + + /* Wait stop flag after DRR read */ + if(i == (u32Size - 1ul)) + { + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STOPF, Set, u32Timeout); + } + } + else + { + break; + } + } + I2C_AckConfig(pstcI2Cx, I2c_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief I2Cx stop + ** \param [in] pstcI2Cx Pointer to the I2C peripheral register, can + ** be M4_I2C1,M4_I2C2 or M4_I2C3. + ** \param [in] u32Timeout Maximum count of trying to get a status of a + ** flag in status register + ** \retval Ok: Receive successfully + ** \retval ErrorTimeout: Receive data time out + ******************************************************************************/ +en_result_t I2C_Stop(M4_I2C_TypeDef* pstcI2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(pstcI2Cx)); + + /* Clear stop flag */ + while((Set == I2C_GetStatus(pstcI2Cx, I2C_SR_STOPF)) && (u32Timeout > 0ul)) + { + I2C_ClearStatus(pstcI2Cx, I2C_CLR_STOPFCLR); + u32Timeout--; + } + I2C_GenerateStop(pstcI2Cx, Enable); + /* Wait stop flag */ + enRet = I2C_WaitStatus(pstcI2Cx, I2C_SR_STOPF, Set, u32Timeout); + + return enRet; +} + +//@} // I2cGroup + +#endif /* DDL_I2C_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2s.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2s.c new file mode 100644 index 0000000000..ab18d3a2f2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_i2s.c @@ -0,0 +1,437 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_i2s.c + ** + ** A detailed description is available at + ** @link I2sGroup Inter-IC Sound Bus description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of I2S. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_i2s.h" +#include "hc32f460_utility.h" + +#if (DDL_I2S_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup I2sGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for I2S register pointer */ +#define IS_VALID_I2S_REG(x) \ +( (M4_I2S1 == (x)) || \ + (M4_I2S2 == (x)) || \ + (M4_I2S3 == (x)) || \ + (M4_I2S4 == (x))) + +/*!< Parameter valid check for I2S function */ +#define IS_VALID_I2S_FUNCTION(x) \ +( (TxEn == (x)) || \ + (TxIntEn == (x)) || \ + (RxEn == (x)) || \ + (RxIntEn == (x)) || \ + (ErrIntEn == (x))) + +/*!< Parameter valid check for I2S status bits */ +#define IS_VALID_I2S_STATUS(x) \ +( (TxBufAlarmFlag == (x)) || \ + (RxBufAlarmFlag == (x)) || \ + (TxBufEmptFlag == (x)) || \ + (TxBufFullFlag == (x)) || \ + (RxBufEmptFlag == (x)) || \ + (RxBufFullFlag == (x))) + +/*!< Parameter valid check for I2S error flag */ +#define IS_VALID_I2S_ERR_FLAG(x) \ +( (ClrTxErrFlag == (x)) || \ + (ClrRxErrFlag == (x))) + +/*!< Parameter valid check for I2S mode */ +#define IS_VALID_I2S_MODE(x) \ +( (I2sMaster == (x)) || \ + (I2sSlave == (x))) + +/*!< Parameter valid check for I2S full duplex mode */ +#define IS_VALID_I2S_DUPLEX_MODE(x) \ +( (I2s_HalfDuplex == (x)) || \ + (I2s_FullDuplex == (x))) + +/*!< Parameter valid check for I2S standard */ +#define IS_VALID_I2S_STANDARD(x) \ +( (Std_Philips == (x)) || \ + (Std_MSBJust == (x)) || \ + (Std_LSBJust == (x)) || \ + (Std_PCM == (x))) + +/*!< Parameter valid check for I2S data length */ +#define IS_VALID_I2S_DATA_LEN(x) \ +( (I2s_DataLen_16Bit == (x)) || \ + (I2s_DataLen_24Bit == (x)) || \ + (I2s_DataLen_32Bit == (x))) + +/*!< Parameter valid check for I2S channel data length */ +#define IS_VALID_I2S_CHANNEL_LEN(x) \ +( (I2s_ChLen_16Bit == (x)) || \ + (I2s_ChLen_32Bit == (x))) + +/*!< Parameter valid check for I2S MCK output config */ +#define IS_VALID_I2S_MCKOUT(x) \ +( (Disable == (x)) || \ + (Enable == (x))) + +/*!< Parameter valid check for I2S EXCK config */ +#define IS_VALID_I2S_EXCK(x) \ +( (Disable == (x)) || \ + (Enable == (x))) + +/*!< Parameter valid check for I2S audio frequecy */ +#define IS_I2S_AUDIO_FREQ(FREQ) \ +( (((FREQ) >= I2S_AudioFreq_8k) && ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) + +/*! I2S registers reset value */ +#define I2S_REG_CTRL_RESET_VALUE (0x00002200ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief I2S function command + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enFunc I2S function + ** \arg Refer @ref en_i2s_func_t + ** \param [in] enNewState New status + ** \arg Refer @ref en_functional_state_t + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_FuncCmd(M4_I2S_TypeDef* pstcI2sReg, en_i2s_func_t enFunc, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_FUNCTION(enFunc)); + + if(Enable == enNewState) + { + if(0ul == (pstcI2sReg->CTRL & (1ul << enFunc))) + { + pstcI2sReg->CTRL |= (1ul << enFunc); + } + } + else + { + if(0ul != (pstcI2sReg->CTRL & (1ul << enFunc))) + { + pstcI2sReg->CTRL &= ~(1ul << (uint8_t)enFunc); + } + } +} + +/** + ******************************************************************************* + ** \brief Get I2S status bit + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enStd I2S status bit + ** \arg Refer @ref en_i2s_std_t + ** + ** \retval Set flag is set + ** \retval Reset flag is reset + ** + ******************************************************************************/ +en_flag_status_t I2S_GetStatus(M4_I2S_TypeDef* pstcI2sReg, en_i2s_std_t enStd) +{ + en_flag_status_t enRet = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_STATUS(enStd)); + + if (0ul != ((uint32_t)(pstcI2sReg->SR & (1ul << (uint8_t)enStd)))) + { + enRet = Set; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Clear I2S error flag + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enErrFlag I2S Error flag + ** \arg Refer @ref en_i2s_err_flag_t + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_ClrErrFlag(M4_I2S_TypeDef* pstcI2sReg, en_i2s_err_flag_t enErrFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag)); + + pstcI2sReg->ER |= (1ul << (uint8_t)enErrFlag); +} + +/** + ******************************************************************************* + ** \brief Get I2S error flag + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] enErrFlag I2S Error flag + ** \arg Refer @ref en_i2s_err_flag_t + ** + ** \retval Set flag is set + ** \retval Reset flag is reset + ** + ******************************************************************************/ +en_flag_status_t I2S_GetErrFlag(M4_I2S_TypeDef* pstcI2sReg, + en_i2s_err_flag_t enErrFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_ERR_FLAG(enErrFlag)); + + return (en_flag_status_t)((uint32_t)(pstcI2sReg->ER | (1ul << (uint8_t)enErrFlag))); +} + +/** + ******************************************************************************* + ** \brief Write data to I2s data send register + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \param [in] u32Data Data to be send + ** + ** \retval None + ** + ******************************************************************************/ +void I2S_SendData(M4_I2S_TypeDef* pstcI2sReg, uint32_t u32Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + pstcI2sReg->TXBUF = u32Data; +} + +/** + ******************************************************************************* + ** \brief Read data from I2s data receive register + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** + ** \retval uint32_t The data read out + ** + ******************************************************************************/ +uint32_t I2S_RevData(const M4_I2S_TypeDef* pstcI2sReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + return pstcI2sReg->RXBUF; +} + +/** + ******************************************************************************* + ** \brief Initialize I2S module + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** \param [in] pstcI2sCfg Pointer to I2S configuration structure + ** + ** \retval Ok Initialize successfully done + ** + ******************************************************************************/ +en_result_t I2s_Init(M4_I2S_TypeDef* pstcI2sReg, const stc_i2s_config_t* pstcI2sCfg) +{ + uint32_t i2sclk = 0ul, tmp=0ul; + uint8_t u8ChanelDataBit,u8ChanMul; + uint16_t i2sdiv, i2sodd; + stc_i2s_cfgr_field_t stcCFGR_Tmp = {0}; + stc_i2s_ctrl_field_t stcCTRL_Tmp = {0}; + en_result_t enRes = Ok; + uint32_t u32AdrTmp = 0ul; + + if((NULL == pstcI2sReg)||(NULL == pstcI2sCfg)) + { + enRes = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + DDL_ASSERT(IS_VALID_I2S_MODE(pstcI2sCfg->enMode)); + DDL_ASSERT(IS_VALID_I2S_DUPLEX_MODE(pstcI2sCfg->enFullDuplexMode)); + DDL_ASSERT(IS_VALID_I2S_STANDARD(pstcI2sCfg->enStandrad)); + DDL_ASSERT(IS_VALID_I2S_DATA_LEN(pstcI2sCfg->enDataBits)); + DDL_ASSERT(IS_VALID_I2S_CHANNEL_LEN(pstcI2sCfg->enChanelLen)); + DDL_ASSERT(IS_VALID_I2S_MCKOUT(pstcI2sCfg->enMcoOutEn)); + DDL_ASSERT(IS_VALID_I2S_EXCK(pstcI2sCfg->enExckEn)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sCfg->u32AudioFreq)); + + /* Set config register to default value*/ + pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE; + /* Clear status register*/ + pstcI2sReg->ER_f.TXERR = 1ul; + pstcI2sReg->ER_f.RXERR = 1ul; + + //*(uint32_t*)&stcCTRL_Tmp = pstcI2sReg->CTRL; + u32AdrTmp = (uint32_t)&stcCTRL_Tmp; + *(uint32_t*)u32AdrTmp = pstcI2sReg->CTRL; + + /* ---- config I2s clock source---- */ + if(Enable == pstcI2sCfg->enExckEn) + { + /* Set external clock as I2S clock source */ + stcCTRL_Tmp.CLKSEL = 1ul; + stcCTRL_Tmp.I2SPLLSEL = 0ul; + /* Set the I2S clock to the external clock value */ + i2sclk = I2S_EXTERNAL_CLOCK_VAL; + } + else + { + /* Set internal clock as I2S clock source */ + stcCTRL_Tmp.CLKSEL = 0ul; + stcCTRL_Tmp.I2SPLLSEL = 1ul; + /* Get i2s clock internal frequency */ + i2sclk = pstcI2sCfg->u32I2sInterClkFreq; + } + /* config audio sampple rate */ + if(I2s_ChLen_16Bit == pstcI2sCfg->enChanelLen) + { + u8ChanelDataBit = 16u; + u8ChanMul = 8u; + } + else + { + u8ChanelDataBit = 32u; + u8ChanMul = 4u; + } + + /*config I2S clock*/ + if(true == pstcI2sCfg->enMcoOutEn) + { + /* MCLK output is enabled */ + tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul * u8ChanMul); + } + else + { + /* MCLK output is disabled */ + tmp = i2sclk/(pstcI2sCfg->u32AudioFreq * u8ChanelDataBit * 2ul); + } + i2sodd = (uint16_t)(tmp & 0x0001ul); + i2sdiv = (uint16_t)((tmp - (uint32_t)i2sodd) / 2ul); + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2u) || (i2sdiv > 0xFFu)) + { + /* Set the default values */ + i2sdiv = 2u; + i2sodd = 0u; + } + + /* Write I2SPR register */ + pstcI2sReg->PR_f.I2SDIV = (uint8_t)i2sdiv; + + /* Config and write I2S_CFGR */ + stcCFGR_Tmp.CHLEN = pstcI2sCfg->enChanelLen; + stcCFGR_Tmp.DATLEN = pstcI2sCfg->enDataBits; + stcCFGR_Tmp.I2SSTD = pstcI2sCfg->enStandrad; + stcCFGR_Tmp.PCMSYNC = PCM_SYNC_FRAME; + pstcI2sReg->CFGR_f = stcCFGR_Tmp; + + /* Config CTRL register */ + stcCTRL_Tmp.WMS = pstcI2sCfg->enMode; + stcCTRL_Tmp.DUPLEX = pstcI2sCfg->enFullDuplexMode; + if(I2sMaster == pstcI2sCfg->enMode) + { + stcCTRL_Tmp.CKOE = 1u; + stcCTRL_Tmp.LRCKOE = 1u; + } + stcCTRL_Tmp.SDOE = 1u; + stcCTRL_Tmp.MCKOE = pstcI2sCfg->enMcoOutEn; + stcCTRL_Tmp.ODD = (uint8_t)i2sodd; + stcCTRL_Tmp.RXBIRQWL = RXBUF_IRQ_WL; + stcCTRL_Tmp.TXBIRQWL = TXBUF_IRQ_WL; + //pstcI2sReg->CTRL = *(uint32_t*)&stcCTRL_Tmp; + u32AdrTmp = (uint32_t)&stcCTRL_Tmp; + pstcI2sReg->CTRL = *(uint32_t*)u32AdrTmp; + } + return enRes; +} + +/** + ******************************************************************************* + ** \brief De-Initialize I2S module + ** + ** \param [in] pstcI2sReg Pointer to I2S register + ** \arg M4_I2S1 I2s channel 1 + ** \arg M4_I2S2 I2s channel 2 + ** \arg M4_I2S3 I2s channel 3 + ** \arg M4_I2S4 I2s channel 4 + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t I2s_DeInit(M4_I2S_TypeDef* pstcI2sReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_I2S_REG(pstcI2sReg)); + + /* Set config register to default value*/ + pstcI2sReg->CTRL = I2S_REG_CTRL_RESET_VALUE; + /* Clear status register*/ + pstcI2sReg->ER_f.TXERR = 1u; + pstcI2sReg->ER_f.RXERR = 1u; + + return Ok; +} + +//@} // I2sGroup + +#endif /* DDL_I2S_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_icg.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_icg.c new file mode 100644 index 0000000000..a3033d09b6 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_icg.c @@ -0,0 +1,83 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_icg.c + ** + ** A detailed description is available at + ** @link IcgGroup Initialize Configure description @endlink + ** + ** - 2018-10-15 CDT First version for Device Driver Library of ICG. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_icg.h" + +#if (DDL_ICG_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup IcgGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +const uint32_t u32ICG[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICG[] __attribute__((at(0x400))) = +#elif defined (__ICCARM__) +__root const uint32_t u32ICG[] @ 0x400 = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~ 3 */ + ICG0_REGISTER_CONSTANT, + ICG1_REGISTER_CONSTANT, + ICG2_REGISTER_CONSTANT, + ICG3_REGISTER_CONSTANT, + /* ICG 4~ 7 */ + ICG4_REGISTER_CONSTANT, + ICG5_REGISTER_CONSTANT, + ICG6_REGISTER_CONSTANT, + ICG7_REGISTER_CONSTANT, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +//@} // IcgGroup + +#endif /* DDL_ICG_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c new file mode 100644 index 0000000000..f7565d260a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c @@ -0,0 +1,3844 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/*****************************************************************************/ +/** \file hc32f460_interrupts.c + ** + ** A detailed description is available at + ** @link InterruptGroup Interrupt description @endlink + ** + ** - 2018-10-12 CDT First version for Device Driver Library of interrupt. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_interrupts.h" +#include "hc32f460_utility.h" + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup InterruptGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for null pointer. */ +#define IS_NULL_POINT(x) (NULL != (x)) + +/*! Max IRQ Handler. */ +#define IRQ_NUM_MAX (128u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +func_ptr_t IrqHandler[IRQ_NUM_MAX] = {NULL}; + +/*! Parameter validity check for EXINT channel. */ +#define IS_EXINT_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | EXINT_CH_MASK) == EXINT_CH_MASK)) + +/** + ******************************************************************************* + ** \brief IRQ Registration + ** + ** param [in] pstcIrqRegiConf, IRQ registration + ** configure structure + ** + ** retval Ok, IRQ register successfully. + ** ErrorInvalidParameter, IRQ No. and + ** Vector No. are not match. + ** ErrorUninitialized, Make sure the + ** Interrupt select register (INTSEL) is + ** default value (0x1FFu) before setting. + ** + *****************************************************************************/ +en_result_t enIrqRegistration(const stc_irq_regi_conf_t *pstcIrqRegiConf) +{ + // todo, assert ... + stc_intc_sel_field_t *stcIntSel; + en_result_t enRet = Ok; + + //DDL_ASSERT(NULL != pstcIrqRegiConf->pfnCallback); + DDL_ASSERT(IS_NULL_POINT(pstcIrqRegiConf->pfnCallback)); + + /* IRQ032~127 whether out of range */ + if (((((pstcIrqRegiConf->enIntSrc/32)*6 + 32) > pstcIrqRegiConf->enIRQn) || \ + (((pstcIrqRegiConf->enIntSrc/32)*6 + 37) < pstcIrqRegiConf->enIRQn)) && \ + (pstcIrqRegiConf->enIRQn >= 32)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + \ + (4u * pstcIrqRegiConf->enIRQn)); + if (0x1FFu == stcIntSel->INTSEL) + { + stcIntSel->INTSEL = pstcIrqRegiConf->enIntSrc; + IrqHandler[pstcIrqRegiConf->enIRQn] = pstcIrqRegiConf->pfnCallback; + } + else + { + enRet = ErrorUninitialized; + } + } + return enRet; +} +/** + * @brief Get specified External interrupt trigger source + * @param [in] u32ExIntCh: External interrupt channel, @ref EXINT_Channel_Sel for details + * @arg EXINT_CH00 + * @arg EXINT_CH01 + * @arg EXINT_CH02 + * @arg EXINT_CH03 + * @arg EXINT_CH04 + * @arg EXINT_CH05 + * @arg EXINT_CH06 + * @arg EXINT_CH07 + * @arg EXINT_CH08 + * @arg EXINT_CH09 + * @arg EXINT_CH10 + * @arg EXINT_CH11 + * @arg EXINT_CH12 + * @arg EXINT_CH13 + * @arg EXINT_CH14 + * @arg EXINT_CH15 + * @retval Set: Specified channel of external interrupt is triggered + * Reset: Specified channel of external interrupt is not triggered + */ +en_flag_status_t EXINT_GetExIntSrc(uint32_t u32ExIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXINT_CH(u32ExIntCh)); + + return ((READ_REG16(M4_INTC->EIFR) & u32ExIntCh) != 0U) ? Set : Reset; +} +/** + * @brief Clear specified External interrupt trigger source + * @param [in] u32ExIntCh: External interrupt channel, @ref EXINT_Channel_Sel for details + * @arg EXINT_CH00 + * @arg EXINT_CH01 + * @arg EXINT_CH02 + * @arg EXINT_CH03 + * @arg EXINT_CH04 + * @arg EXINT_CH05 + * @arg EXINT_CH06 + * @arg EXINT_CH07 + * @arg EXINT_CH08 + * @arg EXINT_CH09 + * @arg EXINT_CH10 + * @arg EXINT_CH11 + * @arg EXINT_CH12 + * @arg EXINT_CH13 + * @arg EXINT_CH14 + * @arg EXINT_CH15 + * @retval None + */ +void EXINT_ClrExIntSrc(uint32_t u32ExIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXINT_CH(u32ExIntCh)); + + SET_REG32_BIT(M4_INTC->EICFR, u32ExIntCh); +} +/** + ******************************************************************************* + ** \brief IRQ Resign + ** + ** param [in] enIRQn, IRQ enumunation (Int000_IRQn ~ + ** Int127_IRQn + ** + ** retval Ok, IRQ resign sucessfully. + ** ErrorInvalidParameter, IRQ No. is out + ** of range + ** + *****************************************************************************/ +en_result_t enIrqResign(IRQn_Type enIRQn) +{ + stc_intc_sel_field_t *stcIntSel; + en_result_t enRet = Ok; + + if ((enIRQn < Int000_IRQn) || (enIRQn > Int127_IRQn)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + (4ul * enIRQn)); + stcIntSel->INTSEL = 0x1FFu; + IrqHandler[enIRQn] = NULL; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Share IRQ handler enable + ** + ** param [in] enIntSrc, interrupt souce, This parameter + ** can be any value of @ref en_int_src_t + ** + ** retval Ok + ** + ******************************************************************************/ +en_result_t enShareIrqEnable(en_int_src_t enIntSrc) +{ + uint32_t *VSSELx; + + //todo assert + + VSSELx = (uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4u * (enIntSrc/32u))); + *VSSELx |= (uint32_t)(1ul << (enIntSrc & 0x1Fu)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Share IRQ handler disable + ** + ** param [in] enIntSrc, interrupt souce, This parameter + ** can be any value of @ref en_int_src_t + ** + ** retval Ok + ** + ******************************************************************************/ +en_result_t enShareIrqDisable(en_int_src_t enIntSrc) +{ + uint32_t *VSSELx; + + //todo assert + + VSSELx = (uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4u * (enIntSrc/32u))); + *VSSELx &= ~(uint32_t)(1ul << (enIntSrc & 0x1Fu)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Enable stop mode wakeup source + ** + ** param [in] u32WakeupSrc, This parameter can be any + ** composed value of @ref en_int_wkup_src_t + ** + ** retval Ok, corresponding wakeup source be enabled + ** ErrorInvalidParameter, parameter with + ** non-definition bits + ** + ******************************************************************************/ +en_result_t enIntWakeupEnable(uint32_t u32WakeupSrc) +{ + en_result_t enRet = Ok; + if (0ul != (u32WakeupSrc & 0xFD000000ul)) + { + enRet = ErrorInvalidParameter; + } + else + { + M4_INTC->WUPEN |= u32WakeupSrc; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Disable stop mode wakeup source + ** + ** param [in] u32WakeupSrc, This parameter can be any + ** composed value of @ref en_int_wkup_src_t + ** + ** retval Ok, corresponding wakeup source be disabled + ** ErrorInvalidParameter, parameter with + ** non-definition bits + ** + ******************************************************************************/ +en_result_t enIntWakeupDisable(uint32_t u32WakeupSrc) +{ + en_result_t enRet = Ok; + if (0ul != (u32WakeupSrc & 0xFD000000u)) + { + enRet = ErrorInvalidParameter; + } + else + { + M4_INTC->WUPEN &= ~u32WakeupSrc; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Event enable + ** + ** param [in] u32Event, This parameter can be + ** any composed value of @ref en_evt_t + ** + ** retval Ok, corresponding event Ch. be enabled + ** + ******************************************************************************/ +en_result_t enEventEnable(uint32_t u32Event) +{ + M4_INTC->EVTER |= u32Event; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Event enable + ** + ** param [in] u32Event, This parameter can be + ** any composed value of @ref en_evt_t + ** + ** retval Ok, corresponding event Ch. be disabled + ** + ******************************************************************************/ +en_result_t enEventDisable(uint32_t u32Event) +{ + M4_INTC->EVTER &= ~u32Event; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Interrupt enable + ** + * param [in] u32Int, This parameter can be any composed + * value of @ref en_int_t + ** + ** retval Ok, corresponding interrupt vector be enabled + ** + ******************************************************************************/ +en_result_t enIntEnable(uint32_t u32Int) +{ + M4_INTC->IER |= u32Int; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Interrupt disable + ** + * param [in] u32Int, This parameter can be any composed + * value of @ref en_int_t + ** + ** retval Ok, corresponding interrupt vector be disabled + ** + ******************************************************************************/ +en_result_t enIntDisable(uint32_t u32Int) +{ + M4_INTC->IER &= ~u32Int; + return Ok; +} + +/** + ******************************************************************************* + ** \brief NMI IRQ handler + ** + ******************************************************************************/ +void NMI_Handler(void) +{ + NMI_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Hard Fault IRQ handler + ** + ******************************************************************************/ +//void HardFault_Handler(void) +//{ +// HardFault_IrqHandler(); +//} + +/** + ******************************************************************************* + ** \brief MPU Fault IRQ handler + ** + ******************************************************************************/ +void MemManage_Handler(void) +{ + MemManage_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Bus Fault IRQ handler + ** + ******************************************************************************/ +void BusFault_Handler(void) +{ + BusFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief Usage Fault IRQ handler + ** + ******************************************************************************/ +void UsageFault_Handler(void) +{ + UsageFault_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief SVCall IRQ handler + ** + ******************************************************************************/ +void SVC_Handler(void) +{ + SVC_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief DebugMon IRQ handler + ** + ******************************************************************************/ +void DebugMon_Handler(void) +{ + DebugMon_IrqHandler(); +} + +/** + ******************************************************************************* + ** \brief PendSV IRQ handler + ** + ******************************************************************************/ +//void PendSV_Handler(void) +//{ +// PendSV_IrqHandler(); +//} + +/** + ******************************************************************************* + ** \brief Systick IRQ handler + ** + ******************************************************************************/ +//void SysTick_Handler(void) +//{ +// SysTick_IrqHandler(); +//} + +/** + ******************************************************************************* + ** \brief Int No.000 IRQ handler + ** + ******************************************************************************/ +void IRQ000_Handler(void) +{ + if (NULL != IrqHandler[Int000_IRQn]) + { + IrqHandler[Int000_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.001 IRQ handler + ** + ******************************************************************************/ +void IRQ001_Handler(void) +{ + if (NULL != IrqHandler[Int001_IRQn]) + { + IrqHandler[Int001_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.002 IRQ handler + ** + ******************************************************************************/ +void IRQ002_Handler(void) +{ + if (NULL != IrqHandler[Int002_IRQn]) + { + IrqHandler[Int002_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.003 IRQ handler + ** + ******************************************************************************/ +void IRQ003_Handler(void) +{ + if (NULL != IrqHandler[Int003_IRQn]) + { + IrqHandler[Int003_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.004 IRQ handler + ** + ******************************************************************************/ +void IRQ004_Handler(void) +{ + if (NULL != IrqHandler[Int004_IRQn]) + { + IrqHandler[Int004_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.005 IRQ handler + ** + ******************************************************************************/ +void IRQ005_Handler(void) +{ + if (NULL != IrqHandler[Int005_IRQn]) + { + IrqHandler[Int005_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.006 IRQ handler + ** + ******************************************************************************/ +void IRQ006_Handler(void) +{ + if (NULL != IrqHandler[Int006_IRQn]) + { + IrqHandler[Int006_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.007 IRQ handler + ** + ******************************************************************************/ +void IRQ007_Handler(void) +{ + if (NULL != IrqHandler[Int007_IRQn]) + { + IrqHandler[Int007_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.008 IRQ handler + ** + ******************************************************************************/ +void IRQ008_Handler(void) +{ + if (NULL != IrqHandler[Int008_IRQn]) + { + IrqHandler[Int008_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.009 IRQ handler + ** + ******************************************************************************/ +void IRQ009_Handler(void) +{ + if (NULL != IrqHandler[Int009_IRQn]) + { + IrqHandler[Int009_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.010 IRQ handler + ** + ******************************************************************************/ +void IRQ010_Handler(void) +{ + if (NULL != IrqHandler[Int010_IRQn]) + { + IrqHandler[Int010_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.011 IRQ handler + ** + ******************************************************************************/ +void IRQ011_Handler(void) +{ + if (NULL != IrqHandler[Int011_IRQn]) + { + IrqHandler[Int011_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.012 IRQ handler + ** + ******************************************************************************/ +void IRQ012_Handler(void) +{ + if (NULL != IrqHandler[Int012_IRQn]) + { + IrqHandler[Int012_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.013 IRQ handler + ** + ******************************************************************************/ +void IRQ013_Handler(void) +{ + if (NULL != IrqHandler[Int013_IRQn]) + { + IrqHandler[Int013_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.014 IRQ handler + ** + ******************************************************************************/ +void IRQ014_Handler(void) +{ + if (NULL != IrqHandler[Int014_IRQn]) + { + IrqHandler[Int014_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.015 IRQ handler + ** + ******************************************************************************/ +void IRQ015_Handler(void) +{ + if (NULL != IrqHandler[Int015_IRQn]) + { + IrqHandler[Int015_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.016 IRQ handler + ** + ******************************************************************************/ +void IRQ016_Handler(void) +{ + if (NULL != IrqHandler[Int016_IRQn]) + { + IrqHandler[Int016_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.017 IRQ handler + ** + ******************************************************************************/ +void IRQ017_Handler(void) +{ + if (NULL != IrqHandler[Int017_IRQn]) + { + IrqHandler[Int017_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.018 IRQ handler + ** + ******************************************************************************/ +void IRQ018_Handler(void) +{ + if (NULL != IrqHandler[Int018_IRQn]) + { + IrqHandler[Int018_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.019 IRQ handler + ** + ******************************************************************************/ +void IRQ019_Handler(void) +{ + if (NULL != IrqHandler[Int019_IRQn]) + { + IrqHandler[Int019_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.020 IRQ handler + ** + ******************************************************************************/ +void IRQ020_Handler(void) +{ + if (NULL != IrqHandler[Int020_IRQn]) + { + IrqHandler[Int020_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.021 IRQ handler + ** + ******************************************************************************/ +void IRQ021_Handler(void) +{ + if (NULL != IrqHandler[Int021_IRQn]) + { + IrqHandler[Int021_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.022 IRQ handler + ** + ******************************************************************************/ +void IRQ022_Handler(void) +{ + if (NULL != IrqHandler[Int022_IRQn]) + { + IrqHandler[Int022_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.023 IRQ handler + ** + ******************************************************************************/ +void IRQ023_Handler(void) +{ + if (NULL != IrqHandler[Int023_IRQn]) + { + IrqHandler[Int023_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.024 IRQ handler + ** + ******************************************************************************/ +void IRQ024_Handler(void) +{ + if (NULL != IrqHandler[Int024_IRQn]) + { + IrqHandler[Int024_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.025 IRQ handler + ** + ******************************************************************************/ +void IRQ025_Handler(void) +{ + if (NULL != IrqHandler[Int025_IRQn]) + { + IrqHandler[Int025_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.026 IRQ handler + ** + ******************************************************************************/ +void IRQ026_Handler(void) +{ + if (NULL != IrqHandler[Int026_IRQn]) + { + IrqHandler[Int026_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.027 IRQ handler + ** + ******************************************************************************/ +void IRQ027_Handler(void) +{ + if (NULL != IrqHandler[Int027_IRQn]) + { + IrqHandler[Int027_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.028 IRQ handler + ** + ******************************************************************************/ +void IRQ028_Handler(void) +{ + if (NULL != IrqHandler[Int028_IRQn]) + { + IrqHandler[Int028_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.029 IRQ handler + ** + ******************************************************************************/ +void IRQ029_Handler(void) +{ + if (NULL != IrqHandler[Int029_IRQn]) + { + IrqHandler[Int029_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.030 IRQ handler + ** + ******************************************************************************/ +void IRQ030_Handler(void) +{ + if (NULL != IrqHandler[Int030_IRQn]) + { + IrqHandler[Int030_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.031 IRQ handler + ** + ******************************************************************************/ +void IRQ031_Handler(void) +{ + if (NULL != IrqHandler[Int031_IRQn]) + { + IrqHandler[Int031_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.032 IRQ handler + ** + ******************************************************************************/ +void IRQ032_Handler(void) +{ + if (NULL != IrqHandler[Int032_IRQn]) + { + IrqHandler[Int032_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.033 IRQ handler + ** + ******************************************************************************/ +void IRQ033_Handler(void) +{ + if (NULL != IrqHandler[Int033_IRQn]) + { + IrqHandler[Int033_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.034 IRQ handler + ** + ******************************************************************************/ +void IRQ034_Handler(void) +{ + if (NULL != IrqHandler[Int034_IRQn]) + { + IrqHandler[Int034_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.035 IRQ handler + ** + ******************************************************************************/ +void IRQ035_Handler(void) +{ + if (NULL != IrqHandler[Int035_IRQn]) + { + IrqHandler[Int035_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.036 IRQ handler + ** + ******************************************************************************/ +void IRQ036_Handler(void) +{ + if (NULL != IrqHandler[Int036_IRQn]) + { + IrqHandler[Int036_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.037 IRQ handler + ** + ******************************************************************************/ +void IRQ037_Handler(void) +{ + if (NULL != IrqHandler[Int037_IRQn]) + { + IrqHandler[Int037_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.038 IRQ handler + ** + ******************************************************************************/ +void IRQ038_Handler(void) +{ + if (NULL != IrqHandler[Int038_IRQn]) + { + IrqHandler[Int038_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.039 IRQ handler + ** + ******************************************************************************/ +void IRQ039_Handler(void) +{ + if (NULL != IrqHandler[Int039_IRQn]) + { + IrqHandler[Int039_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.040 IRQ handler + ** + ******************************************************************************/ +void IRQ040_Handler(void) +{ + if (NULL != IrqHandler[Int040_IRQn]) + { + IrqHandler[Int040_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.041 IRQ handler + ** + ******************************************************************************/ +void IRQ041_Handler(void) +{ + if (NULL != IrqHandler[Int041_IRQn]) + { + IrqHandler[Int041_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.042 IRQ handler + ** + ******************************************************************************/ +void IRQ042_Handler(void) +{ + if (NULL != IrqHandler[Int042_IRQn]) + { + IrqHandler[Int042_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.043 IRQ handler + ** + ******************************************************************************/ +void IRQ043_Handler(void) +{ + if (NULL != IrqHandler[Int043_IRQn]) + { + IrqHandler[Int043_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.044 IRQ handler + ** + ******************************************************************************/ +void IRQ044_Handler(void) +{ + if (NULL != IrqHandler[Int044_IRQn]) + { + IrqHandler[Int044_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.045 IRQ handler + ** + ******************************************************************************/ +void IRQ045_Handler(void) +{ + if (NULL != IrqHandler[Int045_IRQn]) + { + IrqHandler[Int045_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.046 IRQ handler + ** + ******************************************************************************/ +void IRQ046_Handler(void) +{ + if (NULL != IrqHandler[Int046_IRQn]) + { + IrqHandler[Int046_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.047 IRQ handler + ** + ******************************************************************************/ +void IRQ047_Handler(void) +{ + if (NULL != IrqHandler[Int047_IRQn]) + { + IrqHandler[Int047_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.048 IRQ handler + ** + ******************************************************************************/ +void IRQ048_Handler(void) +{ + if (NULL != IrqHandler[Int048_IRQn]) + { + IrqHandler[Int048_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.049 IRQ handler + ** + ******************************************************************************/ +void IRQ049_Handler(void) +{ + if (NULL != IrqHandler[Int049_IRQn]) + { + IrqHandler[Int049_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.050 IRQ handler + ** + ******************************************************************************/ +void IRQ050_Handler(void) +{ + if (NULL != IrqHandler[Int050_IRQn]) + { + IrqHandler[Int050_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.051 IRQ handler + ** + ******************************************************************************/ +void IRQ051_Handler(void) +{ + if (NULL != IrqHandler[Int051_IRQn]) + { + IrqHandler[Int051_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.052 IRQ handler + ** + ******************************************************************************/ +void IRQ052_Handler(void) +{ + if (NULL != IrqHandler[Int052_IRQn]) + { + IrqHandler[Int052_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.053 IRQ handler + ** + ******************************************************************************/ +void IRQ053_Handler(void) +{ + if (NULL != IrqHandler[Int053_IRQn]) + { + IrqHandler[Int053_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.054 IRQ handler + ** + ******************************************************************************/ +void IRQ054_Handler(void) +{ + if (NULL != IrqHandler[Int054_IRQn]) + { + IrqHandler[Int054_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.055 IRQ handler + ** + ******************************************************************************/ +void IRQ055_Handler(void) +{ + if (NULL != IrqHandler[Int055_IRQn]) + { + IrqHandler[Int055_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.056 IRQ handler + ** + ******************************************************************************/ +void IRQ056_Handler(void) +{ + if (NULL != IrqHandler[Int056_IRQn]) + { + IrqHandler[Int056_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.057 IRQ handler + ** + ******************************************************************************/ +void IRQ057_Handler(void) +{ + if (NULL != IrqHandler[Int057_IRQn]) + { + IrqHandler[Int057_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.058 IRQ handler + ** + ******************************************************************************/ +void IRQ058_Handler(void) +{ + if (NULL != IrqHandler[Int058_IRQn]) + { + IrqHandler[Int058_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.059 IRQ handler + ** + ******************************************************************************/ +void IRQ059_Handler(void) +{ + if (NULL != IrqHandler[Int059_IRQn]) + { + IrqHandler[Int059_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.060 IRQ handler + ** + ******************************************************************************/ +void IRQ060_Handler(void) +{ + if (NULL != IrqHandler[Int060_IRQn]) + { + IrqHandler[Int060_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.061 IRQ handler + ** + ******************************************************************************/ +void IRQ061_Handler(void) +{ + if (NULL != IrqHandler[Int061_IRQn]) + { + IrqHandler[Int061_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.062 IRQ handler + ** + ******************************************************************************/ +void IRQ062_Handler(void) +{ + if (NULL != IrqHandler[Int062_IRQn]) + { + IrqHandler[Int062_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.063 IRQ handler + ** + ******************************************************************************/ +void IRQ063_Handler(void) +{ + if (NULL != IrqHandler[Int063_IRQn]) + { + IrqHandler[Int063_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.064 IRQ handler + ** + ******************************************************************************/ +void IRQ064_Handler(void) +{ + if (NULL != IrqHandler[Int064_IRQn]) + { + IrqHandler[Int064_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.065 IRQ handler + ** + ******************************************************************************/ +void IRQ065_Handler(void) +{ + if (NULL != IrqHandler[Int065_IRQn]) + { + IrqHandler[Int065_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.066 IRQ handler + ** + ******************************************************************************/ +void IRQ066_Handler(void) +{ + if (NULL != IrqHandler[Int066_IRQn]) + { + IrqHandler[Int066_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.067 IRQ handler + ** + ******************************************************************************/ +void IRQ067_Handler(void) +{ + if (NULL != IrqHandler[Int067_IRQn]) + { + IrqHandler[Int067_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.068 IRQ handler + ** + ******************************************************************************/ +void IRQ068_Handler(void) +{ + if (NULL != IrqHandler[Int068_IRQn]) + { + IrqHandler[Int068_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.069 IRQ handler + ** + ******************************************************************************/ +void IRQ069_Handler(void) +{ + if (NULL != IrqHandler[Int069_IRQn]) + { + IrqHandler[Int069_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.070 IRQ handler + ** + ******************************************************************************/ +void IRQ070_Handler(void) +{ + if (NULL != IrqHandler[Int070_IRQn]) + { + IrqHandler[Int070_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.071 IRQ handler + ** + ******************************************************************************/ +void IRQ071_Handler(void) +{ + if (NULL != IrqHandler[Int071_IRQn]) + { + IrqHandler[Int071_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.072 IRQ handler + ** + ******************************************************************************/ +void IRQ072_Handler(void) +{ + if (NULL != IrqHandler[Int072_IRQn]) + { + IrqHandler[Int072_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.073 IRQ handler + ** + ******************************************************************************/ +void IRQ073_Handler(void) +{ + if (NULL != IrqHandler[Int073_IRQn]) + { + IrqHandler[Int073_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.074 IRQ handler + ** + ******************************************************************************/ +void IRQ074_Handler(void) +{ + if (NULL != IrqHandler[Int074_IRQn]) + { + IrqHandler[Int074_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.075 IRQ handler + ** + ******************************************************************************/ +void IRQ075_Handler(void) +{ + if (NULL != IrqHandler[Int075_IRQn]) + { + IrqHandler[Int075_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.076 IRQ handler + ** + ******************************************************************************/ +void IRQ076_Handler(void) +{ + if (NULL != IrqHandler[Int076_IRQn]) + { + IrqHandler[Int076_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.077 IRQ handler + ** + ******************************************************************************/ +void IRQ077_Handler(void) +{ + if (NULL != IrqHandler[Int077_IRQn]) + { + IrqHandler[Int077_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.078 IRQ handler + ** + ******************************************************************************/ +void IRQ078_Handler(void) +{ + if (NULL != IrqHandler[Int078_IRQn]) + { + IrqHandler[Int078_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.079 IRQ handler + ** + ******************************************************************************/ +void IRQ079_Handler(void) +{ + if (NULL != IrqHandler[Int079_IRQn]) + { + IrqHandler[Int079_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.080 IRQ handler + ** + ******************************************************************************/ +void IRQ080_Handler(void) +{ + if (NULL != IrqHandler[Int080_IRQn]) + { + IrqHandler[Int080_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.081 IRQ handler + ** + ******************************************************************************/ +void IRQ081_Handler(void) +{ + if (NULL != IrqHandler[Int081_IRQn]) + { + IrqHandler[Int081_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.082 IRQ handler + ** + ******************************************************************************/ +void IRQ082_Handler(void) +{ + if (NULL != IrqHandler[Int082_IRQn]) + { + IrqHandler[Int082_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.083 IRQ handler + ** + ******************************************************************************/ +void IRQ083_Handler(void) +{ + if (NULL != IrqHandler[Int083_IRQn]) + { + IrqHandler[Int083_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.084 IRQ handler + ** + ******************************************************************************/ +void IRQ084_Handler(void) +{ + if (NULL != IrqHandler[Int084_IRQn]) + { + IrqHandler[Int084_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.085 IRQ handler + ** + ******************************************************************************/ +void IRQ085_Handler(void) +{ + if (NULL != IrqHandler[Int085_IRQn]) + { + IrqHandler[Int085_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.086 IRQ handler + ** + ******************************************************************************/ +void IRQ086_Handler(void) +{ + if (NULL != IrqHandler[Int086_IRQn]) + { + IrqHandler[Int086_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.087 IRQ handler + ** + ******************************************************************************/ +void IRQ087_Handler(void) +{ + if (NULL != IrqHandler[Int087_IRQn]) + { + IrqHandler[Int087_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.088 IRQ handler + ** + ******************************************************************************/ +void IRQ088_Handler(void) +{ + if (NULL != IrqHandler[Int088_IRQn]) + { + IrqHandler[Int088_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.089 IRQ handler + ** + ******************************************************************************/ +void IRQ089_Handler(void) +{ + if (NULL != IrqHandler[Int089_IRQn]) + { + IrqHandler[Int089_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.090 IRQ handler + ** + ******************************************************************************/ +void IRQ090_Handler(void) +{ + if (NULL != IrqHandler[Int090_IRQn]) + { + IrqHandler[Int090_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.091 IRQ handler + ** + ******************************************************************************/ +void IRQ091_Handler(void) +{ + if (NULL != IrqHandler[Int091_IRQn]) + { + IrqHandler[Int091_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.092 IRQ handler + ** + ******************************************************************************/ +void IRQ092_Handler(void) +{ + if (NULL != IrqHandler[Int092_IRQn]) + { + IrqHandler[Int092_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.093 IRQ handler + ** + ******************************************************************************/ +void IRQ093_Handler(void) +{ + if (NULL != IrqHandler[Int093_IRQn]) + { + IrqHandler[Int093_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.094 IRQ handler + ** + ******************************************************************************/ +void IRQ094_Handler(void) +{ + if (NULL != IrqHandler[Int094_IRQn]) + { + IrqHandler[Int094_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.095 IRQ handler + ** + ******************************************************************************/ +void IRQ095_Handler(void) +{ + if (NULL != IrqHandler[Int095_IRQn]) + { + IrqHandler[Int095_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.096 IRQ handler + ** + ******************************************************************************/ +void IRQ096_Handler(void) +{ + if (NULL != IrqHandler[Int096_IRQn]) + { + IrqHandler[Int096_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.097 IRQ handler + ** + ******************************************************************************/ +void IRQ097_Handler(void) +{ + if (NULL != IrqHandler[Int097_IRQn]) + { + IrqHandler[Int097_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.098 IRQ handler + ** + ******************************************************************************/ +void IRQ098_Handler(void) +{ + if (NULL != IrqHandler[Int098_IRQn]) + { + IrqHandler[Int098_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.099 IRQ handler + ** + ******************************************************************************/ +void IRQ099_Handler(void) +{ + if (NULL != IrqHandler[Int099_IRQn]) + { + IrqHandler[Int099_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.100 IRQ handler + ** + ******************************************************************************/ +void IRQ100_Handler(void) +{ + if (NULL != IrqHandler[Int100_IRQn]) + { + IrqHandler[Int100_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.101 IRQ handler + ** + ******************************************************************************/ +void IRQ101_Handler(void) +{ + if (NULL != IrqHandler[Int101_IRQn]) + { + IrqHandler[Int101_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.102 IRQ handler + ** + ******************************************************************************/ +void IRQ102_Handler(void) +{ + if (NULL != IrqHandler[Int102_IRQn]) + { + IrqHandler[Int102_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.103 IRQ handler + ** + ******************************************************************************/ +void IRQ103_Handler(void) +{ + if (NULL != IrqHandler[Int103_IRQn]) + { + IrqHandler[Int103_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.104 IRQ handler + ** + ******************************************************************************/ +void IRQ104_Handler(void) +{ + if (NULL != IrqHandler[Int104_IRQn]) + { + IrqHandler[Int104_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.105 IRQ handler + ** + ******************************************************************************/ +void IRQ105_Handler(void) +{ + if (NULL != IrqHandler[Int105_IRQn]) + { + IrqHandler[Int105_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.106 IRQ handler + ** + ******************************************************************************/ +void IRQ106_Handler(void) +{ + if (NULL != IrqHandler[Int106_IRQn]) + { + IrqHandler[Int106_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.107 IRQ handler + ** + ******************************************************************************/ +void IRQ107_Handler(void) +{ + if (NULL != IrqHandler[Int107_IRQn]) + { + IrqHandler[Int107_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.108 IRQ handler + ** + ******************************************************************************/ +void IRQ108_Handler(void) +{ + if (NULL != IrqHandler[Int108_IRQn]) + { + IrqHandler[Int108_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.109 IRQ handler + ** + ******************************************************************************/ +void IRQ109_Handler(void) +{ + if (NULL != IrqHandler[Int109_IRQn]) + { + IrqHandler[Int109_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.110 IRQ handler + ** + ******************************************************************************/ +void IRQ110_Handler(void) +{ + if (NULL != IrqHandler[Int110_IRQn]) + { + IrqHandler[Int110_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.111 IRQ handler + ** + ******************************************************************************/ +void IRQ111_Handler(void) +{ + if (NULL != IrqHandler[Int111_IRQn]) + { + IrqHandler[Int111_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.112 IRQ handler + ** + ******************************************************************************/ +void IRQ112_Handler(void) +{ + if (NULL != IrqHandler[Int112_IRQn]) + { + IrqHandler[Int112_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.113 IRQ handler + ** + ******************************************************************************/ +void IRQ113_Handler(void) +{ + if (NULL != IrqHandler[Int113_IRQn]) + { + IrqHandler[Int113_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.114 IRQ handler + ** + ******************************************************************************/ +void IRQ114_Handler(void) +{ + if (NULL != IrqHandler[Int114_IRQn]) + { + IrqHandler[Int114_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.115 IRQ handler + ** + ******************************************************************************/ +void IRQ115_Handler(void) +{ + if (NULL != IrqHandler[Int115_IRQn]) + { + IrqHandler[Int115_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.116 IRQ handler + ** + ******************************************************************************/ +void IRQ116_Handler(void) +{ + if (NULL != IrqHandler[Int116_IRQn]) + { + IrqHandler[Int116_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.117 IRQ handler + ** + ******************************************************************************/ +void IRQ117_Handler(void) +{ + if (NULL != IrqHandler[Int117_IRQn]) + { + IrqHandler[Int117_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.118 IRQ handler + ** + ******************************************************************************/ +void IRQ118_Handler(void) +{ + if (NULL != IrqHandler[Int118_IRQn]) + { + IrqHandler[Int118_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.119 IRQ handler + ** + ******************************************************************************/ +void IRQ119_Handler(void) +{ + if (NULL != IrqHandler[Int119_IRQn]) + { + IrqHandler[Int119_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.120 IRQ handler + ** + ******************************************************************************/ +void IRQ120_Handler(void) +{ + if (NULL != IrqHandler[Int120_IRQn]) + { + IrqHandler[Int120_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.121 IRQ handler + ** + ******************************************************************************/ +void IRQ121_Handler(void) +{ + if (NULL != IrqHandler[Int121_IRQn]) + { + IrqHandler[Int121_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.122 IRQ handler + ** + ******************************************************************************/ +void IRQ122_Handler(void) +{ + if (NULL != IrqHandler[Int122_IRQn]) + { + IrqHandler[Int122_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.123 IRQ handler + ** + ******************************************************************************/ +void IRQ123_Handler(void) +{ + if (NULL != IrqHandler[Int123_IRQn]) + { + IrqHandler[Int123_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.124 IRQ handler + ** + ******************************************************************************/ +void IRQ124_Handler(void) +{ + if (NULL != IrqHandler[Int124_IRQn]) + { + IrqHandler[Int124_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.125 IRQ handler + ** + ******************************************************************************/ +void IRQ125_Handler(void) +{ + if (NULL != IrqHandler[Int125_IRQn]) + { + IrqHandler[Int125_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.126 IRQ handler + ** + ******************************************************************************/ +void IRQ126_Handler(void) +{ + if (NULL != IrqHandler[Int126_IRQn]) + { + IrqHandler[Int126_IRQn](); + } +} + +/** + ******************************************************************************* + ** \brief Int No.127 IRQ handler + ** + ******************************************************************************/ +void IRQ127_Handler(void) +{ + if (NULL != IrqHandler[Int127_IRQn]) + { + IrqHandler[Int127_IRQn](); + } +} + +#if (DDL_INTERRUPTS_SHARE_ENABLE == DDL_ON) +/** + ******************************************************************************* + ** \brief Int No.128 share IRQ handler + ** + ******************************************************************************/ +void IRQ128_Handler(void) +{ + uint32_t VSSEL128 = M4_INTC->VSSEL128; + + /* external interrupt 00 */ + if ((1ul == bM4_INTC_EIFR_EIFR0) && (VSSEL128 & BIT_MASK_00)) + { + Extint00_IrqHandler(); + } + /* external interrupt 01 */ + if ((1ul == bM4_INTC_EIFR_EIFR1) && (VSSEL128 & BIT_MASK_01)) + { + Extint01_IrqHandler(); + } + /* external interrupt 02 */ + if ((1ul == bM4_INTC_EIFR_EIFR2) && (VSSEL128 & BIT_MASK_02)) + { + Extint02_IrqHandler(); + } + /* external interrupt 03 */ + if ((1ul == bM4_INTC_EIFR_EIFR3) && (VSSEL128 & BIT_MASK_03)) + { + Extint03_IrqHandler(); + } + /* external interrupt 04 */ + if ((1ul == bM4_INTC_EIFR_EIFR4) && (VSSEL128 & BIT_MASK_04)) + { + Extint04_IrqHandler(); + } + /* external interrupt 05 */ + if ((1ul == bM4_INTC_EIFR_EIFR5) && (VSSEL128 & BIT_MASK_05)) + { + Extint05_IrqHandler(); + } + /* external interrupt 06 */ + if ((1ul == bM4_INTC_EIFR_EIFR6) && (VSSEL128 & BIT_MASK_06)) + { + Extint06_IrqHandler(); + } + /* external interrupt 07 */ + if ((1ul == bM4_INTC_EIFR_EIFR7) && (VSSEL128 & BIT_MASK_07)) + { + Extint07_IrqHandler(); + } + /* external interrupt 08 */ + if ((1ul == bM4_INTC_EIFR_EIFR8) && (VSSEL128 & BIT_MASK_08)) + { + Extint08_IrqHandler(); + } + /* external interrupt 09 */ + if ((1ul == bM4_INTC_EIFR_EIFR9) && (VSSEL128 & BIT_MASK_09)) + { + Extint09_IrqHandler(); + } + /* external interrupt 10 */ + if ((1ul == bM4_INTC_EIFR_EIFR10) && (VSSEL128 & BIT_MASK_10)) + { + Extint10_IrqHandler(); + } + /* external interrupt 11 */ + if ((1ul == bM4_INTC_EIFR_EIFR11) && (VSSEL128 & BIT_MASK_11)) + { + Extint11_IrqHandler(); + } + /* external interrupt 12 */ + if ((1ul == bM4_INTC_EIFR_EIFR12) && (VSSEL128 & BIT_MASK_12)) + { + Extint12_IrqHandler(); + } + /* external interrupt 13 */ + if ((1ul == bM4_INTC_EIFR_EIFR13) && (VSSEL128 & BIT_MASK_13)) + { + Extint13_IrqHandler(); + } + /* external interrupt 14 */ + if ((1ul == bM4_INTC_EIFR_EIFR14) && (VSSEL128 & BIT_MASK_14)) + { + Extint14_IrqHandler(); + } + /* external interrupt 15 */ + if ((1ul == bM4_INTC_EIFR_EIFR15) && (VSSEL128 & BIT_MASK_15)) + { + Extint15_IrqHandler(); + } +} + + +/** + ******************************************************************************* + ** \brief Int No.129 share IRQ handler + ** + ******************************************************************************/ +void IRQ129_Handler(void) +{ + uint32_t VSSEL129 =M4_INTC->VSSEL129; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + + if (1ul == bM4_DMA1_CH0CTL_IE) + { + /* DMA1 ch.0 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC0) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC0) && (VSSEL129 & BIT_MASK_00)) + { + Dma1Tc0_IrqHandler(); + } + } + /* DMA1 ch.0 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC0) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC0) && (VSSEL129 & BIT_MASK_08)) + { + Dma1Btc0_IrqHandler(); + } + } + /* DMA1 ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00010001ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00010001ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err0_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH1CTL_IE) + { + /* DMA1 ch.1 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC1) && (VSSEL129 & BIT_MASK_01)) + { + Dma1Tc1_IrqHandler(); + } + } + /* DMA1 ch.1 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC1) && (VSSEL129 & BIT_MASK_09)) + { + Dma1Btc1_IrqHandler(); + } + } + /* DMA1 ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00020002ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00020002ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err1_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH2CTL_IE) + { + /* DMA1 ch.2 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC2) && (VSSEL129 & BIT_MASK_02)) + { + Dma1Tc2_IrqHandler(); + } + } + /* DMA1 ch.2 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC2) && (VSSEL129 & BIT_MASK_10)) + { + Dma1Btc2_IrqHandler(); + } + } + /* DMA1 ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00040004ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00040004ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err2_IrqHandler(); + } + } + if (1ul == bM4_DMA1_CH3CTL_IE) + { + /* DMA1 ch.3 Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_TC3) && (VSSEL129 & BIT_MASK_03)) + { + Dma1Tc3_IrqHandler(); + } + } + /* DMA1 ch.3 Block Tx completed */ + if (0ul == bM4_DMA1_INTMASK1_MSKBTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC3) && (VSSEL129 & BIT_MASK_11)) + { + Dma1Btc3_IrqHandler(); + } + } + /* DMA1 ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & 0x00080008ul; + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & 0x00080008ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_16)) + { + Dma1Err3_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH0CTL_IE) + { + /* DMA2 ch.0 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC0) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC0) && (VSSEL129 & BIT_MASK_04)) + { + Dma2Tc0_IrqHandler(); + } + } + /* DMA2 ch.0 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC0) + { + if ((1ul == bM4_DMA2_INTSTAT1_BTC0) && (VSSEL129 & BIT_MASK_12)) + { + Dma2Btc0_IrqHandler(); + } + } + /* DMA2 Ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00010001ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00010001ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err0_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH1CTL_IE) + { + /* DMA2 ch.1 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC1) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC1) && (VSSEL129 & BIT_MASK_05)) + { + Dma2Tc1_IrqHandler(); + } + } + /* DMA2 ch.1 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC1) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC1) && (VSSEL129 & BIT_MASK_13)) + { + Dma2Btc1_IrqHandler(); + } + } + /* DMA2 Ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00020002ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00020002ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err1_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH2CTL_IE) + { + /* DMA2 ch.2 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC2) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC2) && (VSSEL129 & BIT_MASK_06)) + { + Dma2Tc2_IrqHandler(); + } + } + /* DMA2 ch.2 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC2) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC2) && (VSSEL129 & BIT_MASK_14)) + { + Dma2Btc2_IrqHandler(); + } + } + /* DMA2 Ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00040004ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00040004ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err2_IrqHandler(); + } + } + if (1ul == bM4_DMA2_CH3CTL_IE) + { + /* DMA2 ch.3 Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKTC3) + { + if ((1ul == bM4_DMA2_INTSTAT1_TC3) && (VSSEL129 & BIT_MASK_07)) + { + Dma2Tc3_IrqHandler(); + } + } + /* DMA2 ch.3 Block Tx completed */ + if (0ul == bM4_DMA2_INTMASK1_MSKBTC3) + { + if ((1ul == bM4_DMA1_INTSTAT1_BTC3) && (VSSEL129 & BIT_MASK_15)) + { + Dma2Btc3_IrqHandler(); + } + } + /* DMA2 Ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & 0x00080008ul; + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & 0x00080008ul); + if ((u32Tmp1 & u32Tmp2) && (VSSEL129 & BIT_MASK_17)) + { + Dma2Err3_IrqHandler(); + } + } + /* EFM program/erase Error */ + if (1ul == bM4_EFM_FITE_PEERRITE) + { + if ((M4_EFM->FSR & 0x0Fu) && (VSSEL129 & BIT_MASK_18)) + { + EfmPgmEraseErr_IrqHandler(); + } + } + /* EFM collision Error */ + if (1ul == bM4_EFM_FITE_COLERRITE) + { + if ((1ul == bM4_EFM_FSR_COLERR) && (VSSEL129 & BIT_MASK_19)) + { + EfmColErr_IrqHandler(); + } + } + /* EFM operate end */ + if (1ul == bM4_EFM_FITE_OPTENDITE) + { + if ((1ul == bM4_EFM_FSR_OPTEND) && (VSSEL129 & BIT_MASK_20)) + { + EfmOpEnd_IrqHandler(); + } + } + /* QSPI interrupt */ + if ((1ul == M4_QSPI->SR_f.RAER) && (VSSEL129 & BIT_MASK_22)) + { + QspiInt_IrqHandler(); + } + /* DCU ch.1 */ + u32Tmp1 = M4_DCU1->INTSEL; + u32Tmp2 = M4_DCU1->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_23)) + { + Dcu1_IrqHandler(); + } + /* DCU ch.2 */ + u32Tmp1 = M4_DCU2->INTSEL; + u32Tmp2 = M4_DCU2->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_24)) + { + Dcu2_IrqHandler(); + } + /* DCU ch.3 */ + u32Tmp1 = M4_DCU3->INTSEL; + u32Tmp2 = M4_DCU3->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_25)) + { + Dcu3_IrqHandler(); + } + /* DCU ch.4 */ + u32Tmp1 = M4_DCU4->INTSEL; + u32Tmp2 = M4_DCU4->FLAG; + if ((u32Tmp1 & u32Tmp2 & 0x7Ful) && (VSSEL129 & BIT_MASK_26)) + { + Dcu4_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.130 share IRQ handler + ** + ******************************************************************************/ +void IRQ130_Handler(void) +{ + uint32_t VSSEL130 = M4_INTC->VSSEL130; + /* Timer0 Ch. 1 A compare match */ + if (1ul == bM4_TMR01_BCONR_INTENA) + { + if ((1ul == bM4_TMR01_STFLR_CMAF) && (VSSEL130 & BIT_MASK_00)) + { + Timer01GCMA_IrqHandler(); + } + } + /* Timer0 Ch. 1 B compare match */ + if (1ul == bM4_TMR01_BCONR_INTENB) + { + if ((1ul == bM4_TMR01_STFLR_CMBF) && (VSSEL130 & BIT_MASK_01)) + { + Timer01GCMB_IrqHandler(); + } + } + /* Timer0 Ch. 2 A compare match */ + if (1ul == bM4_TMR02_BCONR_INTENA) + { + if ((1ul == bM4_TMR02_STFLR_CMAF) && (VSSEL130 & BIT_MASK_02)) + { + Timer02GCMA_IrqHandler(); + } + } + /* Timer0 Ch. 2 B compare match */ + if (1ul == bM4_TMR02_BCONR_INTENB) + { + if ((1ul == bM4_TMR02_STFLR_CMBF) && (VSSEL130 & BIT_MASK_03)) + { + Timer02GCMB_IrqHandler(); + } + } + /* Main-OSC stop */ + if (1ul == bM4_SYSREG_CMU_XTALSTDCR_XTALSTDIE) + { + if ((1ul == bM4_SYSREG_CMU_XTALSTDSR_XTALSTDF) && (VSSEL130 & BIT_MASK_21)) + { + MainOscStop_IrqHandler(); + } + } + /* Wakeup timer */ + if ((1ul == bM4_WKTM_CR_WKOVF) && (VSSEL130 & BIT_MASK_22)) + { + WakeupTimer_IrqHandler(); + } + /* SWDT */ + if ((M4_SWDT->SR & (BIT_MASK_16 | BIT_MASK_17)) && (VSSEL130 & BIT_MASK_23)) + { + Swdt_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.131 share IRQ handler + ** + ******************************************************************************/ +void IRQ131_Handler(void) +{ + uint32_t VSSEL131 = M4_INTC->VSSEL131; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* Timer6 Ch.1 A compare match */ + if (1ul == bM4_TMR61_ICONR_INTENA) + { + if ((1ul == bM4_TMR61_STFLR_CMAF) && (VSSEL131 & BIT_MASK_00)) + { + Timer61GCMA_IrqHandler(); + } + } + /* Timer6 Ch.1 B compare match */ + if (1ul == bM4_TMR61_ICONR_INTENB) + { + if ((1ul == bM4_TMR61_STFLR_CMBF) && (VSSEL131 & BIT_MASK_01)) + { + Timer61GCMB_IrqHandler(); + } + } + /* Timer6 Ch.1 C compare match */ + if (1ul == bM4_TMR61_ICONR_INTENC) + { + if ((1ul == bM4_TMR61_STFLR_CMCF) && (VSSEL131 & BIT_MASK_02)) + { + Timer61GCMC_IrqHandler(); + } + } + /* Timer6 Ch.1 D compare match */ + if (1ul == bM4_TMR61_ICONR_INTEND) + { + if ((1ul == bM4_TMR61_STFLR_CMDF) && (VSSEL131 & BIT_MASK_03)) + { + Timer61GCMD_IrqHandler(); + } + } + /* Timer6 Ch.1 E compare match */ + if (1ul == bM4_TMR61_ICONR_INTENE) + { + if ((1ul == bM4_TMR61_STFLR_CMEF) && (VSSEL131 & BIT_MASK_04)) + { + Timer61GCME_IrqHandler(); + } + } + /* Timer6 Ch.1 F compare match */ + if (1ul == bM4_TMR61_ICONR_INTENF) + { + if ((1ul == bM4_TMR61_STFLR_CMFF) && (VSSEL131 & BIT_MASK_05)) + { + Timer61GCMF_IrqHandler(); + } + } + /* Timer6 Ch.1 overflow */ + if (1ul == bM4_TMR61_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR61_STFLR_OVFF) && (VSSEL131 & BIT_MASK_06)) + { + Timer61GOV_IrqHandler(); + } + } + /* Timer6 Ch.1 underflow */ + if (1ul == bM4_TMR61_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR61_STFLR_UDFF) && (VSSEL131 & BIT_MASK_07)) + { + Timer61GUD_IrqHandler(); + } + } + /* Timer6 Ch.1 dead time */ + if (1ul == bM4_TMR61_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR61_STFLR_DTEF)) && (VSSEL131 & BIT_MASK_08)) + { + Timer61GDT_IrqHandler(); + } + } + /* Timer6 Ch.1 A up-down compare match */ + u32Tmp1 = (M4_TMR61->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR61->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_11)) + { + Timer61SCMA_IrqHandler(); + } + /* Timer6 Ch.1 B up-down compare match */ + u32Tmp1 = (M4_TMR61->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR61->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_12)) + { + Timer61SCMB_IrqHandler(); + } + /* Timer6 Ch.2 A compare match */ + if (1ul == bM4_TMR62_ICONR_INTENA) + { + if ((1ul == bM4_TMR62_STFLR_CMAF) && (VSSEL131 & BIT_MASK_16)) + { + Timer62GCMA_IrqHandler(); + } + } + /* Timer6 Ch.2 B compare match */ + if (1ul == bM4_TMR62_ICONR_INTENB) + { + if ((1ul == bM4_TMR62_STFLR_CMBF) && (VSSEL131 & BIT_MASK_17)) + { + Timer62GCMB_IrqHandler(); + } + } + /* Timer6 Ch.2 C compare match */ + if (1ul == bM4_TMR62_ICONR_INTENC) + { + if ((1ul == bM4_TMR62_STFLR_CMCF) && (VSSEL131 & BIT_MASK_18)) + { + Timer62GCMC_IrqHandler(); + } + } + /* Timer6 Ch.2 D compare match */ + if (1ul == bM4_TMR62_ICONR_INTEND) + { + if ((1ul == bM4_TMR62_STFLR_CMDF) && (VSSEL131 & BIT_MASK_19)) + { + Timer62GCMD_IrqHandler(); + } + } + /* Timer6 Ch.2 E compare match */ + if (1ul == bM4_TMR62_ICONR_INTENE) + { + if ((1ul == bM4_TMR62_STFLR_CMEF) && (VSSEL131 & BIT_MASK_20)) + { + Timer62GCME_IrqHandler(); + } + } + /* Timer6 Ch.2 F compare match */ + if (1ul == bM4_TMR62_ICONR_INTENF) + { + if ((1ul == bM4_TMR62_STFLR_CMFF) && (VSSEL131 & BIT_MASK_21)) + { + Timer62GCMF_IrqHandler(); + } + } + /* Timer6 Ch.2 overflow */ + if (1ul == bM4_TMR62_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR62_STFLR_OVFF) && (VSSEL131 & BIT_MASK_22)) + { + Timer62GOV_IrqHandler(); + } + } + /* Timer6 Ch.2 underflow */ + if (1ul == bM4_TMR62_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR62_STFLR_UDFF) && (VSSEL131 & BIT_MASK_23)) + { + Timer62GUD_IrqHandler(); + } + } + /* Timer6 Ch.2 dead time */ + if (1ul == bM4_TMR62_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR62_STFLR_DTEF)) && (VSSEL131 & BIT_MASK_24)) + { + Timer62GDT_IrqHandler(); + } + } + /* Timer6 Ch.2 A up-down compare match */ + u32Tmp1 = (M4_TMR62->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR62->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_27)) + { + Timer62SCMA_IrqHandler(); + } + /* Timer6 Ch.2 B up-down compare match */ + u32Tmp1 = (M4_TMR62->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR62->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL131 & BIT_MASK_28)) + { + Timer62SCMB_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.132 share IRQ handler + ** + ******************************************************************************/ +void IRQ132_Handler(void) +{ + uint32_t VSSEL132 = M4_INTC->VSSEL132; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* Timer6 Ch.3 A compare match */ + if (1ul == bM4_TMR63_ICONR_INTENA) + { + if ((1ul == bM4_TMR63_STFLR_CMAF) && (VSSEL132 & BIT_MASK_00)) + { + Timer63GCMA_IrqHandler(); + } + } + /* Timer6 Ch.3 B compare match */ + if (1ul == bM4_TMR63_ICONR_INTENB) + { + if ((1ul == bM4_TMR63_STFLR_CMBF) && (VSSEL132 & BIT_MASK_01)) + { + Timer63GCMB_IrqHandler(); + } + } + /* Timer6 Ch.3 C compare match */ + if (1ul == bM4_TMR63_ICONR_INTENC) + { + if ((1ul == bM4_TMR63_STFLR_CMCF) && (VSSEL132 & BIT_MASK_02)) + { + Timer63GCMC_IrqHandler(); + } + } + /* Timer6 Ch.3 D compare match */ + if (1ul == bM4_TMR63_ICONR_INTEND) + { + if ((1ul == bM4_TMR63_STFLR_CMDF) && (VSSEL132 & BIT_MASK_03)) + { + Timer63GCMD_IrqHandler(); + } + } + /* Timer6 Ch.3 E compare match */ + if (1ul == bM4_TMR63_ICONR_INTENE) + { + if ((1ul == bM4_TMR63_STFLR_CMEF) && (VSSEL132 & BIT_MASK_04)) + { + Timer63GCME_IrqHandler(); + } + } + /* Timer6 Ch.3 F compare match */ + if (1ul == bM4_TMR63_ICONR_INTENF) + { + if ((1ul == bM4_TMR63_STFLR_CMFF) && (VSSEL132 & BIT_MASK_05)) + { + Timer63GCMF_IrqHandler(); + } + } + /* Timer6 Ch.3 overflow */ + if (1ul == bM4_TMR63_ICONR_INTENOVF) + { + if ((1ul == bM4_TMR63_STFLR_OVFF) && (VSSEL132 & BIT_MASK_06)) + { + Timer63GOV_IrqHandler(); + } + } + /* Timer6 Ch.3 underflow */ + if (1ul == bM4_TMR63_ICONR_INTENUDF) + { + if ((1ul == bM4_TMR63_STFLR_UDFF) && (VSSEL132 & BIT_MASK_07)) + { + Timer63GUD_IrqHandler(); + } + } + /* Timer6 Ch.3 dead time */ + if (1ul == bM4_TMR63_ICONR_INTENDTE) + { + if (((1ul == bM4_TMR63_STFLR_DTEF)) && (VSSEL132 & BIT_MASK_08)) + { + Timer63GDT_IrqHandler(); + } + } + /* Timer6 Ch.3 A up-down compare match */ + u32Tmp1 = (M4_TMR63->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7u; + u32Tmp2 = M4_TMR63->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((u32Tmp1 & u32Tmp2) && (VSSEL132 & BIT_MASK_11)) + { + Timer63SCMA_IrqHandler(); + } + /* Timer6 Ch.3 B up-down compare match */ + u32Tmp1 = (M4_TMR63->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7u; + u32Tmp2 = M4_TMR63->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((u32Tmp1 & u32Tmp2) && (VSSEL132 & BIT_MASK_12)) + { + Timer63SCMB_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.136 share IRQ handler + ** + ******************************************************************************/ +void IRQ136_Handler(void) +{ + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + uint32_t VSSEL136 = M4_INTC->VSSEL136; + + u32Tmp1 = M4_TMRA1->BCSTR; + /* TimerA Ch.1 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_00)) + { + TimerA1OV_IrqHandler(); + } + /* TimerA Ch.1 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_01)) + { + TimerA1UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA1->ICONR; + u32Tmp2 = M4_TMRA1->STFLR; + /* TimerA Ch.1 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_02)) + { + TimerA1CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA2->BCSTR; + /* TimerA Ch.2 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_03)) + { + TimerA2OV_IrqHandler(); + } + /* TimerA Ch.2 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_04)) + { + TimerA2UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA2->ICONR; + u32Tmp2 = M4_TMRA2->STFLR; + /* TimerA Ch.2 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_05)) + { + TimerA2CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA3->BCSTR; + /* TimerA Ch.3 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_06)) + { + TimerA3OV_IrqHandler(); + } + /* TimerA Ch.3 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_07)) + { + TimerA3UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA3->ICONR; + u32Tmp2 = M4_TMRA3->STFLR; + /* TimerA Ch.3 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_08)) + { + TimerA3CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA4->BCSTR; + /* TimerA Ch.4 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_09)) + { + TimerA4OV_IrqHandler(); + } + /* TimerA Ch.4 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_10)) + { + TimerA4UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA4->ICONR; + u32Tmp2 = M4_TMRA4->STFLR; + /* TimerA Ch.4 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_11)) + { + TimerA4CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA5->BCSTR; + /* TimerA Ch.5 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_12)) + { + TimerA5OV_IrqHandler(); + } + /* TimerA Ch.5 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_13)) + { + TimerA5UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA5->ICONR; + u32Tmp2 = M4_TMRA5->STFLR; + /* TimerA Ch.5 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_14)) + { + TimerA5CMP_IrqHandler(); + } + + u32Tmp1 = M4_TMRA6->BCSTR; + /* TimerA Ch.6 overflow */ + if ((u32Tmp1 & BIT_MASK_12) && (u32Tmp1 & BIT_MASK_14) && (VSSEL136 & BIT_MASK_16)) + { + TimerA6OV_IrqHandler(); + } + /* TimerA Ch.6 underflow */ + if ((u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_15) && (VSSEL136 & BIT_MASK_17)) + { + TimerA6UD_IrqHandler(); + } + u32Tmp1 = M4_TMRA6->ICONR; + u32Tmp2 = M4_TMRA6->STFLR; + /* TimerA Ch.6 compare match */ + if ((u32Tmp1 & u32Tmp2 & 0xFFul) && (VSSEL136 & BIT_MASK_18)) + { + TimerA6CMP_IrqHandler(); + } + /* USBFS global interrupt */ + if(1ul == bM4_USBFS_GAHBCFG_GINTMSK) + { + u32Tmp1 = M4_USBFS->GINTMSK & 0xF77CFCFBul; + u32Tmp2 = M4_USBFS->GINTSTS & 0xF77CFCFBul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL136 & BIT_MASK_19)) + { + UsbGlobal_IrqHandler(); + } + } + + u32Tmp1 = M4_USART1->SR; + u32Tmp2 = M4_USART1->CR1; + /* USART Ch.1 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL136 & BIT_MASK_22)) + { + Usart1RxErr_IrqHandler(); + } + /* USART Ch.1 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL136 & BIT_MASK_23)) + { + Usart1RxEnd_IrqHandler(); + } + /* USART Ch.1 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL136 & BIT_MASK_24)) + { + Usart1TxEmpty_IrqHandler(); + } + /* USART Ch.1 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL136 & BIT_MASK_25)) + { + Usart1TxEnd_IrqHandler(); + } + /* USART Ch.1 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL136 & BIT_MASK_26)) + { + Usart1RxTO_IrqHandler(); + } + + u32Tmp1 = M4_USART2->SR; + u32Tmp2 = M4_USART2->CR1; + /* USART Ch.2 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL136 & BIT_MASK_27)) + { + Usart2RxErr_IrqHandler(); + } + /* USART Ch.2 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL136 & BIT_MASK_28)) + { + Usart2RxEnd_IrqHandler(); + } + /* USART Ch.2 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL136 & BIT_MASK_29)) + { + Usart2TxEmpty_IrqHandler(); + } + /* USART Ch.2 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL136 & BIT_MASK_30)) + { + Usart2TxEnd_IrqHandler(); + } + /* USART Ch.2 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL136 & BIT_MASK_31)) + { + Usart2RxTO_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.137 share IRQ handler + ** + ******************************************************************************/ +void IRQ137_Handler(void) +{ + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + uint32_t VSSEL137 = M4_INTC->VSSEL137; + + u32Tmp1 = M4_USART3->SR; + u32Tmp2 = M4_USART3->CR1; + /* USART Ch.3 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL137 & BIT_MASK_00)) + { + Usart3RxErr_IrqHandler(); + } + /* USART Ch.3 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_01)) + { + Usart3RxEnd_IrqHandler(); + } + /* USART Ch.3 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_02)) + { + Usart3TxEmpty_IrqHandler(); + } + /* USART Ch.3 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL137 & BIT_MASK_03)) + { + Usart3TxEnd_IrqHandler(); + } + /* USART Ch.3 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL137 & BIT_MASK_04)) + { + Usart3RxTO_IrqHandler(); + } + + u32Tmp1 = M4_USART4->SR; + u32Tmp2 = M4_USART4->CR1; + /* USART Ch.4 Receive error */ + if ((u32Tmp2 & BIT_MASK_05) && (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03)) && (VSSEL137 & BIT_MASK_05)) + { + Usart4RxErr_IrqHandler(); + } + /* USART Ch.4 Receive completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_06)) + { + Usart4RxEnd_IrqHandler(); + } + /* USART Ch.4 Transmit data empty */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_07)) + { + Usart4TxEmpty_IrqHandler(); + } + /* USART Ch.4 Transmit completed */ + if ((u32Tmp2 & u32Tmp1 & BIT_MASK_06) && (VSSEL137 & BIT_MASK_08)) + { + Usart4TxEnd_IrqHandler(); + } + /* USART Ch.4 Receive timeout */ + if ((u32Tmp2 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_08) && (VSSEL137 & BIT_MASK_09)) + { + Usart4RxTO_IrqHandler(); + } + + u32Tmp1 = M4_SPI1->CR1; + u32Tmp2 = M4_SPI1->SR; + /* SPI Ch.1 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_11)) + { + Spi1RxEnd_IrqHandler(); + } + /* SPI Ch.1 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_12)) + { + Spi1TxEmpty_IrqHandler(); + } + /* SPI Ch.1 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_13)) + { + Spi1Idle_IrqHandler(); + } + /* SPI Ch.1 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_14)) + { + Spi1Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI2->CR1; + u32Tmp2 = M4_SPI2->SR; + /* SPI Ch.2 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_16)) + { + Spi2RxEnd_IrqHandler(); + } + /* SPI Ch.2 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_17)) + { + Spi2TxEmpty_IrqHandler(); + } + /* SPI Ch.2 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_18)) + { + Spi2Idle_IrqHandler(); + } + /* SPI Ch.2 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_19)) + { + Spi2Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI3->CR1; + u32Tmp2 = M4_SPI3->SR; + /* SPI Ch.3 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_21)) + { + Spi3RxEnd_IrqHandler(); + } + /* SPI Ch.3 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_22)) + { + Spi3TxEmpty_IrqHandler(); + } + /* SPI Ch.3 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_23)) + { + Spi3Idle_IrqHandler(); + } + /* SPI Ch.3 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_24)) + { + Spi3Err_IrqHandler(); + } + + u32Tmp1 = M4_SPI4->CR1; + u32Tmp2 = M4_SPI4->SR; + /* SPI Ch.4 Receive completed */ + if ((u32Tmp1 & BIT_MASK_10) && (u32Tmp2 & BIT_MASK_07) && (VSSEL137 & BIT_MASK_26)) + { + Spi4RxEnd_IrqHandler(); + } + /* SPI Ch.4 Transmit buf empty */ + if ((u32Tmp1 & BIT_MASK_09) && (u32Tmp2 & BIT_MASK_05) && (VSSEL137 & BIT_MASK_27)) + { + Spi4TxEmpty_IrqHandler(); + } + /* SPI Ch.4 bus idle */ + if ((u32Tmp1 & BIT_MASK_11) && (!(u32Tmp2 & BIT_MASK_01)) && (VSSEL137 & BIT_MASK_28)) + { + Spi4Idle_IrqHandler(); + } + /* SPI Ch.4 parity/overflow/underflow/mode error */ + if ((u32Tmp1 & BIT_MASK_08) && \ + ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04))) && \ + (VSSEL137 & BIT_MASK_29)) + { + Spi4Err_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.138 share IRQ handler + ** + ******************************************************************************/ +void IRQ138_Handler(void) +{ + uint32_t u32Tmp1 = 0u; + uint32_t VSSEL138 = M4_INTC->VSSEL138; + + u32Tmp1 = M4_TMR41->OCSRU; + /* Timer4 Ch.1 U phase higher compare match */ + if ((VSSEL138 & BIT_MASK_00) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMUH_IrqHandler(); + } + /* Timer4 Ch.1 U phase lower compare match */ + if ((VSSEL138 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->OCSRV; + /* Timer4 Ch.1 V phase higher compare match */ + if ((VSSEL138 & BIT_MASK_02) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMVH_IrqHandler(); + } + /* Timer4 Ch.1 V phase lower compare match */ + if ((VSSEL138 & BIT_MASK_03) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->OCSRW; + /* Timer4 Ch.1 W phase higher compare match */ + if ((VSSEL138 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMWH_IrqHandler(); + } + /* Timer4 Ch.1 W phase lower compare match */ + if ((VSSEL138 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->CCSR; + /* Timer4 Ch.1 overflow */ + if ((VSSEL138 & BIT_MASK_06) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer41GOV_IrqHandler(); + } + /* Timer4 Ch.1 underflow */ + if ((VSSEL138 & BIT_MASK_07) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer41GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR41->RCSR; + /* Timer4 Ch.1 U phase reload */ + if ((VSSEL138 & BIT_MASK_08) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer41ReloadU_IrqHandler(); + } + /* Timer4 Ch.1 V phase reload */ + if ((VSSEL138 & BIT_MASK_09) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer41ReloadV_IrqHandler(); + } + /* Timer4 Ch.1 W phase reload */ + if ((VSSEL138 & BIT_MASK_10) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer41ReloadW_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRU; + /* Timer4 Ch.2 U phase higher compare match */ + if ((VSSEL138 & BIT_MASK_16) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer41GCMUH_IrqHandler(); + } + /* Timer4 Ch.2 U phase lower compare match */ + if ((VSSEL138 & BIT_MASK_17) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer41GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRV; + /* Timer4 Ch.2 V phase higher compare match */ + if ((VSSEL138 & BIT_MASK_18) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer42GCMVH_IrqHandler(); + } + /* Timer4 Ch.2 V phase lower compare match */ + if ((VSSEL138 & BIT_MASK_19) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer42GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->OCSRW; + /* Timer4 Ch.2 W phase higher compare match */ + if ((VSSEL138 & BIT_MASK_20) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer42GCMWH_IrqHandler(); + } + /* Timer4 Ch.2 W phase lower compare match */ + if ((VSSEL138 & BIT_MASK_21) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer42GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->CCSR; + /* Timer4 Ch.2 overflow */ + if ((VSSEL138 & BIT_MASK_22) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer42GOV_IrqHandler(); + } + /* Timer4 Ch.2 underflow */ + if ((VSSEL138 & BIT_MASK_23) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer42GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR42->RCSR; + /* Timer4 Ch.2 U phase reload */ + if ((VSSEL138 & BIT_MASK_24) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer42ReloadU_IrqHandler(); + } + /* Timer4 Ch.2 V phase reload */ + if ((VSSEL138 & BIT_MASK_25) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer42ReloadV_IrqHandler(); + } + /* Timer4 Ch.2 W phase reload */ + if ((VSSEL138 & BIT_MASK_26) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer42ReloadW_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.139 share IRQ handler + ** + ******************************************************************************/ +void IRQ139_Handler(void) +{ + uint32_t u32Tmp1 = 0u; + uint32_t VSSEL139 = M4_INTC->VSSEL139; + + u32Tmp1 = M4_TMR43->OCSRU; + /* Timer4 Ch.3 U phase higher compare match */ + if ((VSSEL139 & BIT_MASK_00) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMUH_IrqHandler(); + } + /* Timer4 Ch.3 U phase lower compare match */ + if ((VSSEL139 & BIT_MASK_01) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMUL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->OCSRV; + /* Timer4 Ch.3 V phase higher compare match */ + if ((VSSEL139 & BIT_MASK_02) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMVH_IrqHandler(); + } + /* Timer4 Ch.3 V phase lower compare match */ + if ((VSSEL139 & BIT_MASK_03) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMVL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->OCSRW; + /* Timer4 Ch.3 W phase higher compare match */ + if ((VSSEL139 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_04) && (u32Tmp1 & BIT_MASK_06)) + { + Timer43GCMWH_IrqHandler(); + } + /* Timer4 Ch.3 W phase lower compare match */ + if ((VSSEL139 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_05) && (u32Tmp1 & BIT_MASK_07)) + { + Timer43GCMWL_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->CCSR; + /* Timer4 Ch.3 overflow */ + if ((VSSEL139 & BIT_MASK_06) && (u32Tmp1 & BIT_MASK_08) && (u32Tmp1 & BIT_MASK_09)) + { + Timer43GOV_IrqHandler(); + } + /* Timer4 Ch.3 underflow */ + if ((VSSEL139 & BIT_MASK_07) && (u32Tmp1 & BIT_MASK_13) && (u32Tmp1 & BIT_MASK_14)) + { + Timer43GUD_IrqHandler(); + } + + u32Tmp1 = M4_TMR43->RCSR; + /* Timer4 Ch.3 U phase reload */ + if ((VSSEL139 & BIT_MASK_08) && (~(u32Tmp1 & BIT_MASK_00)) && (u32Tmp1 & BIT_MASK_04)) + { + Timer41ReloadU_IrqHandler(); + } + /* Timer4 Ch.3 V phase reload */ + if ((VSSEL139 & BIT_MASK_09) && (~(u32Tmp1 & BIT_MASK_01)) && (u32Tmp1 & BIT_MASK_08)) + { + Timer43ReloadV_IrqHandler(); + } + /* Timer4 Ch.3 W phase reload */ + if ((VSSEL139 & BIT_MASK_10) && (~(u32Tmp1 & BIT_MASK_02)) && (u32Tmp1 & BIT_MASK_12)) + { + Timer43ReloadW_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.140 share IRQ handler + ** + ******************************************************************************/ +void IRQ140_Handler(void) +{ + uint32_t VSSEL140 = M4_INTC->VSSEL140; + uint32_t u32Tmp1 = 0u; + uint32_t u32Tmp2 = 0u; + /* EMB1 */ + u32Tmp1 = M4_EMB1->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB1->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_06)) + { + Emb1_IrqHandler(); + } + /* EMB2 */ + u32Tmp1 = M4_EMB2->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB2->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_07)) + { + Emb2_IrqHandler(); + } + /* EMB3 */ + u32Tmp1 = M4_EMB3->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB3->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_08)) + { + Emb3_IrqHandler(); + } + /* EMB4*/ + u32Tmp1 = M4_EMB4->STAT & 0x0000000Ful; + u32Tmp2 = M4_EMB4->INTEN & 0x0000000Ful; + if ((u32Tmp1 & u32Tmp2) && (VSSEL140 & BIT_MASK_09)) + { + Emb4_IrqHandler(); + } + + /* I2S Ch.1 Transmit */ + if(1ul == bM4_I2S1_CTRL_TXIE) + { + if ((1ul == bM4_I2S1_SR_TXBA) && (VSSEL140 & BIT_MASK_16)) + { + I2s1Tx_IrqHandler(); + } + } + /* I2S Ch.1 Receive */ + if(1ul == bM4_I2S1_CTRL_RXIE) + { + if ((1ul == bM4_I2S1_SR_RXBA) && (VSSEL140 & BIT_MASK_17)) + { + I2s1Rx_IrqHandler(); + } + } + /* I2S Ch.1 Error */ + if(1ul == bM4_I2S1_CTRL_EIE) + { + if ((M4_I2S1->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_18)) + { + I2s1Err_IrqHandler(); + } + } + /* I2S Ch.2 Transmit */ + if(1ul == bM4_I2S2_CTRL_TXIE) + { + if ((1ul == bM4_I2S2_SR_TXBA) && (VSSEL140 & BIT_MASK_19)) + { + I2s2Tx_IrqHandler(); + } + } + /* I2S Ch.2 Receive */ + if(1ul == bM4_I2S2_CTRL_RXIE) + { + if ((1ul == bM4_I2S2_SR_RXBA) && (VSSEL140 & BIT_MASK_20)) + { + I2s2Rx_IrqHandler(); + } + } + /* I2S Ch.2 Error */ + if(1ul == bM4_I2S2_CTRL_EIE) + { + if ((M4_I2S2->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_21)) + { + I2s2Err_IrqHandler(); + } + } + /* I2S Ch.3 Transmit */ + if(1ul == bM4_I2S3_CTRL_TXIE) + { + if ((1ul == bM4_I2S3_SR_TXBA) && (VSSEL140 & BIT_MASK_22)) + { + I2s3Tx_IrqHandler(); + } + } + /* I2S Ch.3 Receive */ + if(1ul == bM4_I2S3_CTRL_RXIE) + { + if ((1ul == bM4_I2S3_SR_RXBA) && (VSSEL140 & BIT_MASK_23)) + { + I2s3Rx_IrqHandler(); + } + } + /* I2S Ch.3 Error */ + if(1ul == bM4_I2S3_CTRL_EIE) + { + if ((M4_I2S3->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_24)) + { + I2s3Err_IrqHandler(); + } + } + /* I2S Ch.4 Transmit */ + if(1ul == bM4_I2S4_CTRL_TXIE) + { + if ((1ul == bM4_I2S4_SR_TXBA) && (VSSEL140 & BIT_MASK_25)) + { + I2s4Tx_IrqHandler(); + } + } + /* I2S Ch.4 Receive */ + if(1ul == bM4_I2S4_CTRL_RXIE) + { + if ((1ul == bM4_I2S4_SR_RXBA) && (VSSEL140 & BIT_MASK_26)) + { + I2s4Rx_IrqHandler(); + } + } + /* I2S Ch.4 Error */ + if(1ul == bM4_I2S4_CTRL_EIE) + { + if ((M4_I2S4->ER & (BIT_MASK_00 | BIT_MASK_01)) && (VSSEL140 & BIT_MASK_27)) + { + I2s4Err_IrqHandler(); + } + } +} + +/** + ******************************************************************************* + ** \brief Int No.141 share IRQ handler + ** + ******************************************************************************/ +void IRQ141_Handler(void) +{ + uint32_t VSSEL141 = M4_INTC->VSSEL141; + uint32_t u32Tmp1 = 0ul; + uint32_t u32Tmp2 = 0ul; + /* I2C Ch.1 Receive completed */ + if(1ul == bM4_I2C1_CR2_RFULLIE) + { + if ((1ul == bM4_I2C1_SR_RFULLF) && (VSSEL141 & BIT_MASK_04)) + { + I2c1RxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Transmit data empty */ + if(1ul == bM4_I2C1_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C1_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_05)) + { + I2c1TxEmpty_IrqHandler(); + } + } + /* I2C Ch.1 Transmit completed */ + if(1ul == bM4_I2C1_CR2_TENDIE) + { + if ((1ul == bM4_I2C1_SR_TENDF) && (VSSEL141 & BIT_MASK_06)) + { + I2c1TxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Error */ + u32Tmp1 = M4_I2C1->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C1->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_07)) + { + I2c1Err_IrqHandler(); + } + /* I2C Ch.2 Receive completed */ + if(1ul == bM4_I2C2_CR2_RFULLIE) + { + if ((1ul == bM4_I2C2_SR_RFULLF) && (VSSEL141 & BIT_MASK_08)) + { + I2c2RxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Transmit data empty */ + if(1ul == bM4_I2C2_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C2_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_09)) + { + I2c2TxEmpty_IrqHandler(); + } + } + /* I2C Ch.2 Transmit completed */ + if(1ul == bM4_I2C2_CR2_TENDIE) + { + if ((1ul == bM4_I2C2_SR_TENDF) && (VSSEL141 & BIT_MASK_10)) + { + I2c2TxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Error */ + u32Tmp1 = M4_I2C2->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C2->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_11)) + { + I2c2Err_IrqHandler(); + } + /* I2C Ch.3 Receive completed */ + if(1ul == bM4_I2C3_CR2_RFULLIE) + { + if ((1ul == bM4_I2C3_SR_RFULLF) && (VSSEL141 & BIT_MASK_12)) + { + I2c3RxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Transmit data empty */ + if(1ul == bM4_I2C3_CR2_TEMPTYIE) + { + if ((1ul == bM4_I2C3_SR_TEMPTYF) && (VSSEL141 & BIT_MASK_13)) + { + I2c3TxEmpty_IrqHandler(); + } + } + /* I2C Ch.3 Transmit completed */ + if(1ul == bM4_I2C3_CR2_TENDIE) + { + if ((1ul == bM4_I2C3_SR_TENDF) && (VSSEL141 & BIT_MASK_14)) + { + I2c3TxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Error */ + u32Tmp1 = M4_I2C3->CR2 & 0x00F05217ul; + u32Tmp2 = M4_I2C3->SR & 0x00F05217ul; + if ((u32Tmp1 & u32Tmp2) && (VSSEL141 & BIT_MASK_15)) + { + I2c3Err_IrqHandler(); + } + /* PVD Ch.1 detected */ + if (1ul == M4_SYSREG->PWR_PVDDSR_f.PVD1DETFLG) + { + if((1ul == bM4_SYSREG_PWR_PVDDSR_PVD1DETFLG) && (VSSEL141 & BIT_MASK_17)) + { + Pvd1_IrqHandler(); + } + } + if (1ul == M4_SYSREG->PWR_PVDDSR_f.PVD2DETFLG) + { + /* PVD Ch.2 detected */ + if((1ul == bM4_SYSREG_PWR_PVDDSR_PVD2DETFLG) && (VSSEL141 & BIT_MASK_18)) + { + Pvd2_IrqHandler(); + } + } + /* Freq. calculate error detected */ + if(1ul == bM4_FCM_RIER_ERRIE) + { + if((1ul == bM4_FCM_SR_ERRF) && (VSSEL141 & BIT_MASK_20)) + { + FcmErr_IrqHandler(); + } + } + /* Freq. calculate completed */ + if(1ul == bM4_FCM_RIER_MENDIE) + { + if((1ul == bM4_FCM_SR_MENDF) && (VSSEL141 & BIT_MASK_21)) + { + FcmEnd_IrqHandler(); + } + } + /* Freq. calculate overflow */ + if(1ul == bM4_FCM_RIER_OVFIE) + { + if((1ul == bM4_FCM_SR_OVF) && (VSSEL141 & BIT_MASK_22)) + { + FcmOV_IrqHandler(); + } + } + + /* WDT */ + if ((M4_WDT->SR & (BIT_MASK_16 | BIT_MASK_17)) && (VSSEL141 & BIT_MASK_23)) + { + Wdt_IrqHandler(); + } +} + +/** + ******************************************************************************* + ** \brief Int No.142 share IRQ handler + ** + ******************************************************************************/ +void IRQ142_Handler(void) +{ + uint32_t u32VSSEL142 = M4_INTC->VSSEL142; + uint16_t u16Tmp = 0u; + /* ADC unit.1 seq. A */ + if (1ul == bM4_ADC1_ICR_EOCAIEN) + { + if ((1ul == bM4_ADC1_ISR_EOCAF) && (u32VSSEL142 & BIT_MASK_00)) + { + ADC1A_IrqHandler(); + } + } + /* ADC unit.1 seq. B */ + if (1ul == bM4_ADC1_ICR_EOCBIEN) + { + if ((1ul == bM4_ADC1_ISR_EOCBF) && (u32VSSEL142 & BIT_MASK_01)) + { + ADC1B_IrqHandler(); + } + } + /* ADC unit.1 seq. A */ + u16Tmp = M4_ADC1->AWDSR0; + if (1ul == bM4_ADC1_AWDCR_AWDIEN) + { + if (((1ul == bM4_ADC1_AWDSR1_AWDF16) || (u16Tmp)) && (u32VSSEL142 & BIT_MASK_02)) + { + ADC1ChCmp_IrqHandler(); + } + } + /* ADC unit.1 seq. cmp */ + if (1ul == bM4_ADC1_AWDCR_AWDIEN) + { + if (((1ul == bM4_ADC1_AWDSR1_AWDF16) || (u16Tmp)) && (u32VSSEL142 & BIT_MASK_03)) + { + ADC1SeqCmp_IrqHandler(); + } + } + + /* ADC unit.2 seq. A */ + if (1ul == bM4_ADC2_ICR_EOCAIEN) + { + if ((1ul == bM4_ADC2_ISR_EOCAF) && (u32VSSEL142 & BIT_MASK_04)) + { + ADC2A_IrqHandler(); + } + } + /* ADC unit.2 seq. B */ + if (1ul == bM4_ADC2_ICR_EOCBIEN) + { + if ((1ul == bM4_ADC2_ISR_EOCBF) && (u32VSSEL142 & BIT_MASK_05)) + { + ADC2B_IrqHandler(); + } + } + /* ADC unit.2 seq. A */ + if (1ul == bM4_ADC2_AWDCR_AWDIEN) + { + if ((M4_ADC2->AWDSR0 & 0x1FFu) && (u32VSSEL142 & BIT_MASK_06)) + { + ADC2ChCmp_IrqHandler(); + } + } + /* ADC unit.2 seq. cmp */ + if (1ul == bM4_ADC2_AWDCR_AWDIEN) + { + if ((M4_ADC2->AWDSR0 & 0x1FFu) && (u32VSSEL142 & BIT_MASK_07)) + { + ADC2SeqCmp_IrqHandler(); + } + } +} + +/** + ******************************************************************************* + ** \brief Int No.143 share IRQ handler + ** + ******************************************************************************/ +void IRQ143_Handler(void) +{ + uint8_t RTIF = 0u; + uint8_t RTIE = 0u; + uint8_t ERRINT = 0u; + uint8_t TTCFG = 0u; + uint16_t NORINTST = 0u; + uint16_t NORINTSGEN = 0u; + uint16_t ERRINTST = 0u; + uint16_t ERRINTSGEN = 0u; + + /* SDIO Ch.1 */ + if (1ul == bM4_INTC_VSSEL143_VSEL2) + { + NORINTST = M4_SDIOC1->NORINTST; + NORINTSGEN = M4_SDIOC1->NORINTSGEN; + ERRINTST = M4_SDIOC1->ERRINTST; + ERRINTSGEN = M4_SDIOC1->ERRINTSGEN; + + if ((NORINTST & NORINTSGEN & 0x1F7u) || (ERRINTST & ERRINTSGEN & 0x017Fu)) + { + Sdio1_IrqHandler(); + } + } + + /* SDIO Ch.2 */ + if (1ul == bM4_INTC_VSSEL143_VSEL5) + { + NORINTST = M4_SDIOC2->NORINTST; + NORINTSGEN = M4_SDIOC2->NORINTSGEN; + ERRINTST = M4_SDIOC2->ERRINTST; + ERRINTSGEN = M4_SDIOC2->ERRINTSGEN; + + if ((NORINTST & NORINTSGEN & 0x1F7u) || (ERRINTST & ERRINTSGEN & 0x017Fu)) + { + Sdio2_IrqHandler(); + } + } + + /* CAN */ + if (1ul == bM4_INTC_VSSEL143_VSEL6) + { + RTIF = M4_CAN->RTIF; + RTIE = M4_CAN->RTIE; + ERRINT = M4_CAN->ERRINT; + TTCFG = M4_CAN->TTCFG; + if ( (TTCFG & BIT_MASK_05) || \ + (RTIF & BIT_MASK_00) || \ + (RTIF & RTIE & 0xFEu) || \ + ((ERRINT & BIT_MASK_00) && (ERRINT & BIT_MASK_01)) || \ + ((ERRINT & BIT_MASK_02) && (ERRINT & BIT_MASK_03)) || \ + ((ERRINT & BIT_MASK_04) && (ERRINT & BIT_MASK_05)) || \ + ((TTCFG & BIT_MASK_03) && (TTCFG & BIT_MASK_04)) || \ + ((TTCFG & BIT_MASK_06) && (TTCFG & BIT_MASK_07))) + { + Can_IrqHandler(); + } + } +} + +#endif + +//@} // InterruptGroup + +#endif /* DDL_INTERRUPTS_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_keyscan.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_keyscan.c new file mode 100644 index 0000000000..43f2fab5a3 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_keyscan.c @@ -0,0 +1,207 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_keyscan.c + ** + ** A detailed description is available at + ** @link KeyscanGroup Keyscan module description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of keyscan. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_keyscan.h" +#include "hc32f460_utility.h" + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup KeyscanGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for Hiz cycle */ +#define IS_VALID_HIZ_CLCYE(x) \ +( ((x) == Hiz4) || \ + ((x) == Hiz8) || \ + ((x) == Hiz16) || \ + ((x) == Hiz32) || \ + ((x) == Hiz64) || \ + ((x) == Hiz256) || \ + ((x) == Hiz512) || \ + ((x) == Hiz1K)) + +/*! Parameter validity check for Low cycle */ +#define IS_VALID_LOW_CLCYE(x) \ +( ((x) == Low8) || \ + ((x) == Low16) || \ + ((x) == Low32) || \ + ((x) == Low64) || \ + ((x) == Low128) || \ + ((x) == Low256) || \ + ((x) == Low512) || \ + ((x) == Low1K) || \ + ((x) == Low2K) || \ + ((x) == Low4K) || \ + ((x) == Low8K) || \ + ((x) == Low16K) || \ + ((x) == Low32K) || \ + ((x) == Low64K) || \ + ((x) == Low128K) || \ + ((x) == Low256K) || \ + ((x) == Low512K) || \ + ((x) == Low1M) || \ + ((x) == Low2M) || \ + ((x) == Low4M) || \ + ((x) == Low8M) || \ + ((x) == Low16M)) + +/*! Parameter validity check for scan clock */ +#define IS_VALID_SCAN_CLK(x) \ +( ((x) == KeyscanHclk) || \ + ((x) == KeyscanLrc) || \ + ((x) == KeyscanXtal32)) + +/*! Parameter validity check for keyout selection */ +#define IS_VALID_KEY_OUT(x) \ +( ((x) == Keyout0To1) || \ + ((x) == Keyout0To2) || \ + ((x) == Keyout0To3) || \ + ((x) == Keyout0To4) || \ + ((x) == Keyout0To5) || \ + ((x) == Keyout0To6) || \ + ((x) == Keyout0To7)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief KEYSCAN initialization + ** + ** \param [in] pstcKeyscanConfig KEYSCAN configure structure + ** + ** \retval Ok KEYSCAN initialized + ** ErrorInvalidMode Uninitialized, cannot configure it properly + ** + ******************************************************************************/ +en_result_t KEYSCAN_Init(const stc_keyscan_config_t *pstcKeyscanConfig) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_HIZ_CLCYE(pstcKeyscanConfig->enHizCycle)); + DDL_ASSERT(IS_VALID_LOW_CLCYE(pstcKeyscanConfig->enLowCycle)); + DDL_ASSERT(IS_VALID_SCAN_CLK(pstcKeyscanConfig->enKeyscanClk)); + DDL_ASSERT(IS_VALID_KEY_OUT(pstcKeyscanConfig->enKeyoutSel)); + + /* cannot configure keyscan control register when running */ + if (Set == M4_KEYSCAN->SER_f.SEN) + { + enRet = ErrorInvalidMode; + } + else + { + M4_KEYSCAN->SCR_f.T_HIZ = pstcKeyscanConfig->enHizCycle; + M4_KEYSCAN->SCR_f.T_LLEVEL = pstcKeyscanConfig->enLowCycle; + M4_KEYSCAN->SCR_f.CKSEL = pstcKeyscanConfig->enKeyscanClk; + M4_KEYSCAN->SCR_f.KEYOUTSEL = pstcKeyscanConfig->enKeyoutSel; + M4_KEYSCAN->SCR_f.KEYINSEL = pstcKeyscanConfig->u16KeyinSel; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief KEYSCAN de-initialization + ** + ** \param None + ** + ** \retval Ok KEYSCAN de-initialized + ** + ******************************************************************************/ +en_result_t KEYSCAN_DeInit(void) +{ + M4_KEYSCAN->SER = 0ul; + M4_KEYSCAN->SCR = 0ul; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Start keyscan function + ** + ** \param None + ** + ** \retval Ok Keyscan function started + ** + ******************************************************************************/ +en_result_t KEYSCAN_Start(void) +{ + M4_KEYSCAN->SER_f.SEN = Set; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Stop keyscan function + ** + ** \param None + ** + ** \retval Ok Keyscan function stopped + ** + ******************************************************************************/ +en_result_t KEYSCAN_Stop(void) +{ + M4_KEYSCAN->SER_f.SEN = Reset; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get Key column index + ** + ** \param None + ** + ** \retval uint8_t Index of KEYOUT + ** + ******************************************************************************/ +uint8_t KEYSCAN_GetColIdx(void) +{ + return (uint8_t)(M4_KEYSCAN->SSR_f.INDEX); +} + +//@} // KeyscanGroup + +#endif /* DDL_KEYSCAN_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_mpu.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_mpu.c new file mode 100644 index 0000000000..d0b3940727 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_mpu.c @@ -0,0 +1,1057 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_mpu.c + ** + ** A detailed description is available at + ** @link MpuGroup MPU description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of MPU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_mpu.h" +#include "hc32f460_utility.h" + +#if (DDL_MPU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup MpuGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for MPU region number. */ +#define IS_VALID_MPU_REGION_NUM(x) \ +( (MpuRegionNum0 == (x)) || \ + (MpuRegionNum1 == (x)) || \ + (MpuRegionNum2 == (x)) || \ + (MpuRegionNum3 == (x)) || \ + (MpuRegionNum4 == (x)) || \ + (MpuRegionNum5 == (x)) || \ + (MpuRegionNum6 == (x)) || \ + (MpuRegionNum7 == (x)) || \ + (MpuRegionNum8 == (x)) || \ + (MpuRegionNum9 == (x)) || \ + (MpuRegionNum10 == (x)) || \ + (MpuRegionNum11 == (x)) || \ + (MpuRegionNum12 == (x)) || \ + (MpuRegionNum13 == (x)) || \ + (MpuRegionNum14 == (x)) || \ + (MpuRegionNum15 == (x))) + +/*!< Parameter valid check for MPU region size. */ +#define IS_VALID_MPU_REGION_SIZE(x) \ +( (MpuRegionSize32Byte == (x)) || \ + (MpuRegionSize64Byte == (x)) || \ + (MpuRegionSize128Byte == (x)) || \ + (MpuRegionSize256Byte == (x)) || \ + (MpuRegionSize512Byte == (x)) || \ + (MpuRegionSize1KByte == (x)) || \ + (MpuRegionSize2KByte == (x)) || \ + (MpuRegionSize4KByte == (x)) || \ + (MpuRegionSize8KByte == (x)) || \ + (MpuRegionSize16KByte == (x)) || \ + (MpuRegionSize32KByte == (x)) || \ + (MpuRegionSize64KByte == (x)) || \ + (MpuRegionSize128KByte == (x)) || \ + (MpuRegionSize256KByte == (x)) || \ + (MpuRegionSize512KByte == (x)) || \ + (MpuRegionSize1MByte == (x)) || \ + (MpuRegionSize2MByte == (x)) || \ + (MpuRegionSize4MByte == (x)) || \ + (MpuRegionSize8MByte == (x)) || \ + (MpuRegionSize16MByte == (x)) || \ + (MpuRegionSize32MByte == (x)) || \ + (MpuRegionSize64MByte == (x)) || \ + (MpuRegionSize128MByte == (x)) || \ + (MpuRegionSize256MByte == (x)) || \ + (MpuRegionSize512MByte == (x)) || \ + (MpuRegionSize1GByte == (x)) || \ + (MpuRegionSize2GByte == (x)) || \ + (MpuRegionSize4GByte == (x))) + +/*!< Parameter valid check for MPU region type. */ +#define IS_VALID_MPU_REGION_TYPE(x) \ +( (SMPU1Region == (x)) || \ + (SMPU2Region == (x)) || \ + (FMPURegion == (x))) + +/*!< Parameter valid check for MPU action. */ +#define IS_VALID_MPU_ACTION(x) \ +( (MpuTrigNmi == (x)) || \ + (MpuTrigReset == (x)) || \ + (MpuNoneAction == (x)) || \ + (MpuTrigBusError == (x))) + +/******************************************************************************/ +/* MPU */ +/******************************************************************************/ +/*!< Get the RGD register address of the specified MPU region */ +#define MPU_RGDx(__REGION_NUM__) ((uint32_t)(&M4_MPU->RGD0) + ((uint32_t)(__REGION_NUM__)) * 4u) + +/*!< Get the RGCR register address of the specified MPU region */ +#define MPU_RGCRx(__REGION_NUM__) ((uint32_t)(&M4_MPU->RGCR0) + ((uint32_t)(__REGION_NUM__)) * 4u) + +/*!< MPU RGD register: RGADDR position */ +#define MPU_RGD_RGADDR_Pos (5u) /*!< MPU_RGD: RGADDR Position */ + +/*!< MPU write protection key */ +#define MPU_WRITE_PROT_KEY (0x96A4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Configure MPU protect region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] pstcInitCfg Pointer to MPU protection region configuration structure + ** \arg the structure detail refer @ref stc_mpu_prot_region_init_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcInitCfg == NULL + ** - pstcInitCfg->u32RegionBaseAddress is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t MPU_ProtRegionInit(en_mpu_region_num_t enRegionNum, + const stc_mpu_prot_region_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32WriteProt = M4_MPU->WP; + stc_mpu_rgd0_field_t *RGD_f = NULL; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + /* Check pointer parameters */ + if (NULL != pstcInitCfg) + { + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_SIZE(pstcInitCfg->enRegionSize)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcSMPU1Permission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1Permission.enReadEnable)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcSMPU2Permission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2Permission.enReadEnable)); + DDL_ASSERT(IS_VALID_MPU_ACTION(pstcInitCfg->stcFMPUPermission.enAction)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enRegionEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUPermission.enReadEnable)); + + /* Check base address and region size */ + if (!(pstcInitCfg->u32RegionBaseAddress & (~ (0xFFFFFFFFUL << ((uint32_t)pstcInitCfg->enRegionSize + 1UL))))) + { + /* Disable write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | 1ul); + + /* Get RGD && RGCR register address */ + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + /* Disable region protection function */ + RGCR_f->FRG0E = (uint32_t)0ul; + RGCR_f->S1RG0E = (uint32_t)0ul; + RGCR_f->S2RG0E = (uint32_t)0ul; + + /* Set region size */ + RGD_f->MPURG0SIZE = (uint32_t)(pstcInitCfg->enRegionSize); + + /* Set region base address */ + RGD_f->MPURG0ADDR = (pstcInitCfg->u32RegionBaseAddress >> MPU_RGD_RGADDR_Pos); + + /* Set region FMPU */ + RGCR_f->FRG0RP = (pstcInitCfg->stcFMPUPermission.enReadEnable) ? 0ul : 1ul; + RGCR_f->FRG0WP = (pstcInitCfg->stcFMPUPermission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->FRG0E = (uint32_t)(pstcInitCfg->stcFMPUPermission.enRegionEnable); + M4_MPU->CR_f.FMPUACT = (uint32_t)(pstcInitCfg->stcFMPUPermission.enAction); + + /* Set region SMPU1 */ + RGCR_f->S1RG0RP = (pstcInitCfg->stcSMPU1Permission.enReadEnable) ? 0ul : 1ul; + RGCR_f->S1RG0WP = (pstcInitCfg->stcSMPU1Permission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->S1RG0E = (uint32_t)(pstcInitCfg->stcSMPU1Permission.enRegionEnable); + M4_MPU->CR_f.SMPU1ACT = (uint32_t)(pstcInitCfg->stcSMPU1Permission.enAction); + + /* Set region SMPU2 */ + RGCR_f->S2RG0RP = (pstcInitCfg->stcSMPU2Permission.enReadEnable) ? 0ul : 1ul; + RGCR_f->S2RG0WP = (pstcInitCfg->stcSMPU2Permission.enWriteEnable) ? 0ul : 1ul; + RGCR_f->S2RG0E = (uint32_t)(pstcInitCfg->stcSMPU2Permission.enRegionEnable); + M4_MPU->CR_f.SMPU2ACT = (uint32_t)(pstcInitCfg->stcSMPU2Permission.enAction); + + /* Recover write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | u32WriteProt); + enRet = Ok; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure MPU background region. + ** + ** \param [in] pstcInitCfg Pointer to MPU background region configuration structure + ** \arg the structure detail refer @ref stc_mpu_bkgd_region_init_t + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcInitCfg == NULL + ** - pstcInitCfg->u32RegionBaseAddress is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t MPU_BkgdRegionInit(const stc_mpu_bkgd_region_init_t *pstcInitCfg) +{ + uint32_t u32WriteProt = M4_MPU->WP; + en_result_t enRet = ErrorInvalidParameter; + + /* Check pointer parameters */ + if (NULL != pstcInitCfg) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1BkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU1BkgdPermission.enReadEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2BkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcSMPU2BkgdPermission.enReadEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUBkgdPermission.enWriteEnable)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->stcFMPUBkgdPermission.enReadEnable)); + + /* Disable write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | 1ul); + + /* Set SMPU1 */ + M4_MPU->CR_f.SMPU1BWP = (pstcInitCfg->stcSMPU1BkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.SMPU1BRP = (pstcInitCfg->stcSMPU1BkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Set SMPU2 */ + M4_MPU->CR_f.SMPU2BWP = (pstcInitCfg->stcSMPU2BkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.SMPU2BRP = (pstcInitCfg->stcSMPU2BkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Set FMPU */ + M4_MPU->CR_f.FMPUBWP = (pstcInitCfg->stcFMPUBkgdPermission.enWriteEnable) ? 0ul : 1ul; + M4_MPU->CR_f.FMPUBRP = (pstcInitCfg->stcFMPUBkgdPermission.enReadEnable) ? 0ul : 1ul; + + /* Recover write protection of MPU register */ + M4_MPU->WP = (MPU_WRITE_PROT_KEY | u32WriteProt); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU size of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enRegionSize MPU region size + ** \arg This parameter can be a value of @ref en_mpu_region_size_t + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_SetRegionSize(en_mpu_region_num_t enRegionNum, + en_mpu_region_size_t enRegionSize) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_SIZE(enRegionSize)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGD_f->MPURG0SIZE = (uint32_t)enRegionSize; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get MPU size of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** + ** \retval MPU size of the specified region. + ** + ******************************************************************************/ +en_mpu_region_size_t MPU_GetRegionSize(en_mpu_region_num_t enRegionNum) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + + return (en_mpu_region_size_t)(RGD_f->MPURG0SIZE); +} + +/** + ******************************************************************************* + ** \brief Set MPU base address of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] u32RegionBaseAddr the specified base address + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_SetRegionBaseAddress(en_mpu_region_num_t enRegionNum, + uint32_t u32RegionBaseAddr) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + RGD_f->MPURG0ADDR = (u32RegionBaseAddr >> MPU_RGD_RGADDR_Pos); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get MPU base address of the specified region. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t +s ** + ** \retval MPU base address of the specified region. + ** + ******************************************************************************/ +uint32_t MPU_GetRegionBaseAddress(en_mpu_region_num_t enRegionNum) +{ + stc_mpu_rgd0_field_t *RGD_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + + RGD_f = (stc_mpu_rgd0_field_t *)MPU_RGDx(enRegionNum); + + return (RGD_f->MPURG0ADDR << MPU_RGD_RGADDR_Pos); +} + +/** + ******************************************************************************* + ** \brief Set the action of the specified MPU region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enActionSel MPU action + ** \arg MpuNoneAction MPU don't action. + ** \arg MpuTrigBusError MPU trigger bus error + ** \arg MpuTrigNmi MPU trigger bus NMI interrupt + ** \arg MpuTrigReset MPU trigger reset + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enActionSel is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType, + en_mpu_action_sel_t enActionSel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_MPU_ACTION(enActionSel)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1ACT = (uint32_t)enActionSel; + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2ACT = (uint32_t)enActionSel; + break; + case FMPURegion: + M4_MPU->CR_f.FMPUACT = (uint32_t)enActionSel; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the action of the specified MPU region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval MpuNoneAction MPU don't action. + ** \retval MpuTrigBusError MPU trigger bus error + ** \retval MpuTrigNmi MPU trigger bus NMI interrupt + ** \retval MpuTrigReset MPU trigger reset + ** + ******************************************************************************/ +en_mpu_action_sel_t MPU_GetNoPermissionAcessAction(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32ActionSel = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32ActionSel = M4_MPU->CR_f.SMPU1ACT; + break; + case SMPU2Region: + u32ActionSel = M4_MPU->CR_f.SMPU2ACT; + break; + case FMPURegion: + u32ActionSel = M4_MPU->CR_f.FMPUACT; + break; + default: + break; + } + + return (en_mpu_action_sel_t)(u32ActionSel); +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region and type. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region function + ** \arg Disable Disable the specified MPU region function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_ProtRegionCmd(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0E = (uint32_t)enState; + break; + case SMPU2Region: + RGCR_f->S2RG0E = (uint32_t)enState; + break; + case FMPURegion: + RGCR_f->FRG0E = (uint32_t)enState; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region type. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified type region function of MPU + ** \arg Disable Disable the specified type region function of MPU + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_RegionTypeCmd(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1E = (uint32_t)enState; + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2E = (uint32_t)enState; + break; + case FMPURegion: + M4_MPU->CR_f.FMPUE = (uint32_t)enState; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU status + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enMpuRegionType is invalid. + ** + ******************************************************************************/ +en_flag_status_t MPU_GetStatus(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32Flag = 0ul; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32Flag = M4_MPU->SR_f.SMPU1EAF; + break; + case SMPU2Region: + u32Flag = M4_MPU->SR_f.SMPU2EAF; + break; + case FMPURegion: + u32Flag = M4_MPU->SR_f.FMPUEAF; + break; + default: + break; + } + + return (en_flag_status_t)(u32Flag); +} + +/** + ******************************************************************************* + ** \brief Clear MPU status. + ** + ** \param [in] enMpuRegionType the specified region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_ClearStatus(en_mpu_region_type_t enMpuRegionType) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->ECLR_f.SMPU1ECLR = 1u; + break; + case SMPU2Region: + M4_MPU->ECLR_f.SMPU2ECLR = 1u; + break; + case FMPURegion: + M4_MPU->ECLR_f.FMPUECLR = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set MPU read permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region read permission + ** \arg Disable Disable the specified MPU region read permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0RP = (Enable == enState) ? 0ul : 1ul; + break; + case SMPU2Region: + RGCR_f->S2RG0RP = (Enable == enState) ? 0ul : 1ul; + break; + case FMPURegion: + RGCR_f->FRG0RP = (Enable == enState) ? 0ul : 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU read permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetProtRegionReadPermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = RGCR_f->S1RG0RP; + break; + case SMPU2Region: + u32State = RGCR_f->S2RG0RP; + break; + case FMPURegion: + u32State = RGCR_f->FRG0RP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU write permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region write permission + ** \arg Disable Disable the specified MPU region write permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + RGCR_f->S1RG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + RGCR_f->S2RG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + RGCR_f->FRG0WP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU write permission of the specified protection region and enMpuRegionType. + ** + ** \param [in] enRegionNum MPU region number + ** \arg This parameter can be a value of @ref en_mpu_region_num_t + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetProtRegionWritePermission(en_mpu_region_num_t enRegionNum, + en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + stc_mpu_rgcr0_field_t *RGCR_f = NULL; + + DDL_ASSERT(IS_VALID_MPU_REGION_NUM(enRegionNum)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + RGCR_f = (stc_mpu_rgcr0_field_t *)MPU_RGCRx(enRegionNum); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = RGCR_f->S1RG0WP; + break; + case SMPU2Region: + u32State = RGCR_f->S2RG0WP; + break; + case FMPURegion: + u32State = RGCR_f->FRG0WP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU read permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region read permission + ** \arg Disable Disable the specified MPU region read permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1BRP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2BRP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + M4_MPU->CR_f.FMPUBRP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU read permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetBkgdRegionReadPermission(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = M4_MPU->CR_f.SMPU1BRP; + break; + case SMPU2Region: + u32State = M4_MPU->CR_f.SMPU2BRP; + break; + case FMPURegion: + u32State = M4_MPU->CR_f.FMPUBRP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU write permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** \param [in] enState MPU region state + ** \arg Enable Enable the specified MPU region write permission + ** \arg Disable Disable the specified MPU region write permission + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter enMpuRegionType is invalid + ** + ******************************************************************************/ +en_result_t MPU_SetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType, + en_functional_state_t enState) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + M4_MPU->CR_f.SMPU1BWP = ((Enable == enState) ? 0ul : 1ul); + break; + case SMPU2Region: + M4_MPU->CR_f.SMPU2BWP = ((Enable == enState) ? 0ul : 1ul); + break; + case FMPURegion: + M4_MPU->CR_f.FMPUBWP = ((Enable == enState) ? 0ul : 1ul); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get MPU write permission of the specified background region and enMpuRegionType. + ** + ** \param [in] enMpuRegionType MPU region type + ** \arg SMPU1Region System DMA_1 MPU + ** \arg SMPU2Region System DMA_2 MPU + ** \arg FMPURegion System USBFS_DMA MPU + ** + ** \retval Enable Enable the specified MPU region read permission + ** \retval Disable Disable the specified MPU region read permission + ** + ******************************************************************************/ +en_functional_state_t MPU_GetBkgdRegionWritePermission(en_mpu_region_type_t enMpuRegionType) +{ + uint32_t u32State = 0u; + + DDL_ASSERT(IS_VALID_MPU_REGION_TYPE(enMpuRegionType)); + + switch (enMpuRegionType) + { + case SMPU1Region: + u32State = M4_MPU->CR_f.SMPU1BWP; + break; + case SMPU2Region: + u32State = M4_MPU->CR_f.SMPU2BWP; + break; + case FMPURegion: + u32State = M4_MPU->CR_f.FMPUBWP; + break; + default: + break; + } + + return (u32State ? Disable : Enable); +} + +/** + ******************************************************************************* + ** \brief Set MPU function of the specified region and type. + ** + ** \param [in] enState MPU write protection state + ** \arg Enable Enable the write protection function + ** \arg Disable Disable the write protection function + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_WriteProtCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + M4_MPU->WP = (MPU_WRITE_PROT_KEY | ((Enable == enState) ? 0ul : 1ul)); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Enable the specified IP Write/Read protection. + ** + ** \param [in] u32ProtMode Ip protection mode + ** \arg AesReadProt AES read protection + ** \arg AesWriteProt AES write protection + ** \arg HashReadProt HASH read protection + ** \arg HashWriteProt HASH write protection + ** \arg TrngReadProt TRNG read protection + ** \arg TrngWriteProt TRNG write protection + ** \arg CrcReadProt CRC read protection + ** \arg CrcWriteProt CRC write protection + ** \arg FmcReadProt FMC read protection + ** \arg FmcWriteProt FMC write protection + ** \arg WdtReadProt WDT read protection + ** \arg WdtWriteProt WDT write protection + ** \arg SwdtReadProt WDT read protection + ** \arg SwdtWriteProt WDT write protection + ** \arg BksramReadProt BKSRAM read protection + ** \arg BksramWriteProt BKSRAM write protection + ** \arg RtcReadProt RTC read protection + ** \arg RtcWriteProt RTC write protection + ** \arg DmpuReadProt DMPU read protection + ** \arg DmpuWriteProt DMPU write protection + ** \arg SramcReadProt SRAMC read protection + ** \arg SramcWriteProt SRAMC write protection + ** \arg IntcReadProt INTC read protection + ** \arg IntcWriteProt INTC write protection + ** \arg SyscReadProt SYSC read protection + ** \arg SyscWriteProt SYSC write protection + ** \arg MstpWriteProt MSTP write protection + ** \arg MstpWriteProt MSTP write protection + ** \arg BusErrProt BUSERR write protection + ** \param [in] enState MPU IP protection state + ** \arg Enable Enable the IP protection function + ** \arg Disable Disable the IP protection function + ** + ** \retval Ok Set successfully. + ** + ******************************************************************************/ +en_result_t MPU_IpProtCmd(uint32_t u32ProtMode, + en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if(Enable == enState) + { + M4_SYSREG->MPU_IPPR |= u32ProtMode; + } + else + { + M4_SYSREG->MPU_IPPR &= (~u32ProtMode); + } + + return Ok; +} + +//@} // MpuGroup + +#endif /* DDL_MPU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_ots.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_ots.c new file mode 100644 index 0000000000..74ddaba771 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_ots.c @@ -0,0 +1,386 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_ots.c + ** + ** A detailed description is available at + ** @link OtsGroup Ots description @endlink + ** + ** - 2018-10-26 CDT First version for Device Driver Library of Ots. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_ots.h" +#include "hc32f460_utility.h" + +#if (DDL_OTS_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup OtsGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for OTS auto off configuration value. */ +#define IS_OTS_AUTO_OFF(EN) \ +( ((EN) == OtsAutoOff_Disable) || \ + ((EN) == OtsAutoOff_Enable)) + +/*! Parameter validity check for OTS interrupt enable/disable. */ +#define IS_OTS_IE(IE) \ +( ((IE) == OtsInt_Disable) || \ + ((IE) == OtsInt_Enable)) + +/*! Parameter validity check for OTS clock selection configuration value. */ +#define IS_OTS_CLK_SEL(CLK) \ +( ((CLK) == OtsClkSel_Xtal) || \ + ((CLK) == OtsClkSel_Hrc)) + +/*! Parameter validity check for OTS trigger source event . */ +#define IS_OTS_TRIG_SRC_EVENT(x) \ +( (((x) >= EVT_PORT_EIRQ0) && ((x) <= EVT_PORT_EIRQ15)) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW)) || \ + ((x) == EVT_MAX)) + +/*! Parameter validity check for OTS common trigger. */ +#define IS_OTS_COM_TRIGGER(x) \ +( ((x) == OtsComTrigger_1) || \ + ((x) == OtsComTrigger_2) || \ + ((x) == OtsComTrigger_1_2)) + +#define EXPERIMENT_COUNT ((uint8_t)10) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static float32_t m_f32SlopeK = 0.0f; +static float32_t m_f32OffsetM = 0.0f; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief Initializes the OTS. + ** + ** \param [in] pstcInit See @ref stc_ots_init_t for details. + ** + ** \retval Ok No error occurred. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t OTS_Init(const stc_ots_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + DDL_ASSERT(IS_OTS_AUTO_OFF(pstcInit->enAutoOff)); + DDL_ASSERT(IS_OTS_CLK_SEL(pstcInit->enClkSel)); + + /* Stop ots sampling. */ + bM4_OTS_CTL_OTSST = 0u; + /* Disable OTS interrupt default. */ + bM4_OTS_CTL_OTSIE = OtsInt_Disable; + + bM4_OTS_CTL_TSSTP = pstcInit->enAutoOff; + bM4_OTS_CTL_OTSCK = pstcInit->enClkSel; + m_f32SlopeK = pstcInit->f32SlopeK; + m_f32OffsetM = pstcInit->f32OffsetM; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes the TRNG. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_DeInit(void) +{ + /* Stop ots sampling. */ + bM4_OTS_CTL_OTSST = 0u; + + /* Set the value of all registers to the reset value. */ + M4_OTS->CTL = 0u; + M4_OTS->DR1 = 0u; + M4_OTS->DR2 = 0u; + M4_OTS->ECR = 0u; +} + +/** + ******************************************************************************* + ** \brief Get temperature via normal mode. + ** + ** \param [out] pf32Temp The address to store the temperature value. + ** + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout OTS works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pf32Temp != NULL) + { + enRet = ErrorTimeout; + + OTS_Start(); + do + { + if (bM4_OTS_CTL_OTSST == 0ul) + { + *pf32Temp = OTS_CalculateTemp(); + enRet = Ok; + break; + } + } while (u32Timeout-- != 0ul); + OTS_Stop(); + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Enable or disable OTS interrupt. + ** + ** \param [in] enState Enable or disable OTS interrupt. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_IntCmd(en_functional_state_t enState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + bM4_OTS_CTL_OTSIE = (uint32_t)enState; +} + +/** + ******************************************************************************* + ** \brief Set OTS AOS trigger source. + ** + ** \param [in] enEvent See @ref en_event_src_t for details. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_SetTriggerSrc(en_event_src_t enEvent) +{ + uint32_t u32OtrTrg = M4_AOS->OTS_TRG; + + DDL_ASSERT(IS_OTS_TRIG_SRC_EVENT(enEvent) && (EVT_OTS != enEvent)); + + u32OtrTrg &= ~0x1FFul; + u32OtrTrg |= enEvent; + + M4_AOS->OTS_TRG = u32OtrTrg; +} + +/** + ******************************************************************************* + ** \brief Enable or disable OTS common trigger. + ** + ** \param [in] enComTrigger OTS common trigger selection. See @ref en_ots_com_trigger_t for details. + ** + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None. + ** + ******************************************************************************/ +void OTS_ComTriggerCmd(en_ots_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = enComTrigger; + + DDL_ASSERT(IS_OTS_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + u32ComTrig <<= 30u; + + if (enState == Enable) + { + M4_AOS->OTS_TRG |= u32ComTrig; + } + else + { + M4_AOS->OTS_TRG &= ~u32ComTrig; + } +} + +/** +******************************************************************************* +** \brief OTS scaling experiment. If you want to get a more accurate temperature value, +** you need to do a calibration experiment. +** +** \param [out] pu16Dr1 Address to store OTS data register 1. +** +** \param [out] pu16Dr2 Address to store OTS data register 2. +** +** \param [out] pu16Ecr Address to store OTS error compensation register. +** +** \param [out] pf32A Address to store parameter A(for calibration experiments). +** +** \param [in] u32Timeout Timeout value. +** +** \retval Ok No error occurred. +** \retval ErrorTimeout OTS works timeout. +** \retval ErrorInvalidParameter Parameter error. +******************************************************************************/ +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout) +{ + float32_t f32Dr1; + float32_t f32Dr2; + float32_t f32Ecr; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \ + (NULL != pu16Ecr) && (NULL != pf32A)) + { + enRet = ErrorTimeout; + OTS_Start(); + do + { + if (bM4_OTS_CTL_OTSST == 0ul) + { + enRet = Ok; + break; + } + } while (u32Timeout-- != 0ul); + OTS_Stop(); + + if (enRet == Ok) + { + *pu16Dr1 = M4_OTS->DR1; + *pu16Dr2 = M4_OTS->DR2; + + f32Dr1 = (float32_t)(*pu16Dr1); + f32Dr2 = (float32_t)(*pu16Dr2); + + if (bM4_OTS_CTL_OTSCK == OtsClkSel_Hrc) + { + *pu16Ecr = M4_OTS->ECR; + f32Ecr = (float32_t)(*pu16Ecr); + } + else + { + *pu16Ecr = 1U; + f32Ecr = 1.0f; + } + + if ((*pu16Dr1 != 0U) && (*pu16Dr2 != 0U) && (*pu16Ecr != 0U)) + { + *pf32A = ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr; + } + } + } + + return enRet; +} + + +/** +******************************************************************************* +** \brief Calculate the value of temperature. +** +** \retval A float32_t type value of temperature value. +******************************************************************************/ +float OTS_CalculateTemp(void) +{ + float32_t f32Ret = 0.0f; + uint16_t u16Dr1 = M4_OTS->DR1; + uint16_t u16Dr2 = M4_OTS->DR2; + uint16_t u16Ecr = M4_OTS->ECR; + float32_t f32Dr1 = (float32_t)u16Dr1; + float32_t f32Dr2 = (float32_t)u16Dr2; + float32_t f32Ecr = (float32_t)u16Ecr; + + if (bM4_OTS_CTL_OTSCK == OtsClkSel_Xtal) + { + f32Ecr = 1.0f; + } + + if ((u16Dr1 != 0U) && (u16Dr2 != 0U) && (u16Ecr != 0U)) + { + f32Ret = m_f32SlopeK * ((1.0f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr + m_f32OffsetM; + } + + return f32Ret; +} + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +//@} // OtsGroup + +#endif /* DDL_OTS_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c new file mode 100644 index 0000000000..9d0bb35747 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c @@ -0,0 +1,2025 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_pwc.c + ** + ** A detailed description is available at + ** @link PwcGroup PWC description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of PWC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_pwc.h" +#include "hc32f460_utility.h" + +#if (DDL_PWC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup PwcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ENABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50001u) +#define DISABLE_FCG0_REG_WRITE() (M4_MSTP->FCG0PC = 0xa5a50000u) + +#define ENABLE_PWR_REG0_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa503u) +#define DISABLE_PWR_REG0_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~3u)))) + +#define ENABLE_PWR_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa502u) +#define DISABLE_PWR_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~2u)))) + +#define ENABLE_PVD_REG_WRITE() (M4_SYSREG->PWR_FPRC |= 0xa508u) +#define DISABLE_PVD_REG_WRITE() (M4_SYSREG->PWR_FPRC = (0xa500u | (M4_SYSREG->PWR_FPRC & (uint16_t)(~8u)))) + +/*! Parameter validity check for wake up event. */ +#define IS_PWC_WKUP_EVENT(evt) ((0x00u) != ((evt) & (0xFF))) + +/*! Parameter validity check for wake up event. */ +#define IS_PWC_WKUP2_EVENT(evt) ((0x00u) != ((evt) & (0xB7))) + +#define IS_PWC_WKUP_EDGE_EVENT(evt) ((0x00u) != ((evt) & (0x7F))) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP0_FLAG(flag) ((0x00u) != ((flag) & (0x7F))) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP1_FLAG(flag) ((0x07u) != ((flag) & (0xB8))) + +/*! Parameter validity check for power down mode. */ +#define IS_PWC_PWR_DOWN_MODE(md) \ +( ((md) == PowerDownMd1) || \ + ((md) == PowerDownMd2) || \ + ((md) == PowerDownMd3) || \ + ((md) == PowerDownMd4)) + +/*! Parameter validity check for power down wake_up time control. */ +#define IS_PWC_PWR_DOWN_WKUP_TIM(x) \ +( ((x) == Vcap01) || \ + ((x) == Vcap0047)) + +/*! Parameter validity check for IO retain state while power down. */ +#define IS_PWC_PWR_DWON_IO_STATE(x) \ +( ((x) == IoPwrDownRetain) || \ + ((x) == IoPwrRstRetain) || \ + ((x) == IoHighImp)) + +/*! Parameter validity check for driver ability while enter stop mode. */ +#define IS_PWC_STP_DRIVER_ABILITY(x) \ +( ((x) == StopHighspeed) || \ + ((x) == StopUlowspeed)) + +/*! Parameter validity check for driver ability. */ +#define IS_PWC_DRIVER_ABILITY(x) \ +( ((x) == Ulowspeed) || \ + ((x) == HighSpeed)) + +/*! Parameter validity check for dynamic voltage. */ +#define IS_PWC_DYNAMIC_VOLTAGE(val) \ +( ((val) == RunUHighspeed) || \ + ((val) == RunUlowspeed) || \ + ((val) == RunHighspeed)) + +/*! Parameter validity check for wake_up edge. */ +#define IS_PWC_EDGE_SEL(edg) \ +( ((edg) == EdgeFalling) || \ + ((edg) == EdgeRising)) + +/*! Parameter validity check for peripheral in fcg0. */ +#define IS_PWC_FCG0_PERIPH(per) \ +( (((per) & (0x700C3AEEu)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg1. */ +#define IS_PWC_FCG1_PERIPH(per) \ +( (((per) & (0xF0F00286u)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg2. */ +#define IS_PWC_FCG2_PERIPH(per) \ +( (((per) & (0xFFF87800u)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for peripheral in fcg3. */ +#define IS_PWC_FCG3_PERIPH(per) \ +( (((per) & (0xFFFFEEECu)) == (0x00u)) && \ + ((0x00u) != (per))) + +/*! Parameter validity check for clock value while stop mode mode. */ +#define IS_PWC_STOP_MODE_CLK(clk) \ +( ((clk) == ClkFix) || \ + ((clk) == ClkMrc)) + +/*! Parameter validity check for flash mode while stop mode mode. */ +#define IS_PWC_STOP_MODE_FLASH(x) \ +( ((x) == Wait) || \ + ((x) == NotWait)) + +/*! Parameter validity check for wake_up timer over flag. */ +#define IS_PWC_WKTMOVER_FLAG(flag) \ +( ((flag) == UnEqual) || \ + ((flag) == Equal)) + +/*! Parameter validity check for ram operate mode. */ +#define IS_PWC_RAM_OP_MD(x) \ +( ((x) == HighSpeedMd) || \ + ((x) == UlowSpeedMd)) + +/*! Parameter validity check for wake_up timer clock. */ +#define IS_PWC_WKTM_CLK(clk) \ +( ((clk) == Wk64hz) || \ + ((clk) == WkXtal32) || \ + ((clk) == WkLrc)) + + +/*! Parameter validity check for handle of pvd. */ +#define IS_PWC_PVD_MD(x) \ +( ((x) == PvdInt) || \ + ((x) == PvdReset)) + + +/*! Parameter validity check for pvd1 level. */ +#define IS_PWC_PVD_FILTER_CLK(clk) \ +( ((clk) == PvdLrc025) || \ + ((clk) == PvdLrc05) || \ + ((clk) == PvdLrc1) || \ + ((clk) == PvdLrc2)) + +/*! Parameter validity check for pvd2 level. */ +#define IS_PWC_PVD2_LEVEL(lvl) \ +( ((lvl) == Pvd2Level0) || \ + ((lvl) == Pvd2Level1) || \ + ((lvl) == Pvd2Level2) || \ + ((lvl) == Pvd2Level3) || \ + ((lvl) == Pvd2Level4) || \ + ((lvl) == Pvd2Level5) || \ + ((lvl) == Pvd2Level6) || \ + ((lvl) == Pvd2Level7)) + +/*! Parameter validity check for pvd1 level. */ +#define IS_PWC_PVD1_LEVEL(lvl) \ +( ((lvl) == Pvd1Level0) || \ + ((lvl) == Pvd1Level1) || \ + ((lvl) == Pvd1Level2) || \ + ((lvl) == Pvd1Level3) || \ + ((lvl) == Pvd1Level4) || \ + ((lvl) == Pvd1Level5) || \ + ((lvl) == Pvd1Level6) || \ + ((lvl) == Pvd1Level7)) + +/*! Parameter validity check for pvd interrupt. */ +#define IS_PWC_PVD_INT_SEL(x) \ +( ((x) == NonMskInt) || \ + ((x) == MskInt)) + +/*! Parameter validity check for valid wakeup source from stop mode. */ +#define IS_VALID_WKUP_SRC(x) \ +( ((x) == INT_USART1_WUPI) || \ + ((x) == INT_TMR01_GCMA) || \ + ((x) == INT_RTC_ALM) || \ + ((x) == INT_RTC_PRD) || \ + ((x) == INT_WKTM_PRD) || \ + ((x) == INT_ACMP1) || \ + ((x) == INT_PVD_PVD1) || \ + ((x) == INT_PVD_PVD2) || \ + ((x) == INT_SWDT_REFUDF) || \ + ((x) == INT_PORT_EIRQ0) || \ + ((x) == INT_PORT_EIRQ1) || \ + ((x) == INT_PORT_EIRQ2) || \ + ((x) == INT_PORT_EIRQ3) || \ + ((x) == INT_PORT_EIRQ4) || \ + ((x) == INT_PORT_EIRQ5) || \ + ((x) == INT_PORT_EIRQ6) || \ + ((x) == INT_PORT_EIRQ7) || \ + ((x) == INT_PORT_EIRQ8) || \ + ((x) == INT_PORT_EIRQ9) || \ + ((x) == INT_PORT_EIRQ10) || \ + ((x) == INT_PORT_EIRQ11) || \ + ((x) == INT_PORT_EIRQ12) || \ + ((x) == INT_PORT_EIRQ13) || \ + ((x) == INT_PORT_EIRQ14) || \ + ((x) == INT_PORT_EIRQ15)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint32_t NVIC_ISER_BAK[5]; +uint8_t u8HrcState = 0u; +uint8_t u8MrcState = 0u; +uint8_t u8WkupIntCnt = 0u; +uint8_t u8StopFlag = 0u; +uint8_t u8SysClkSrc = 1u; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief The power mode configuration. + ** + ** \param [in] pstcPwrMdCfg The power mode configuration. + ** \arg enPwrDownMd The power down mode. + ** \arg enRLdo Enable or disable RLDO. + ** \arg enRetSram Enable or disable RetSram. + ** \arg enIoRetain The IO state while power down. + ** \arg enPwrDWkupTm The wake_up timer while power down. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PowerModeCfg(const stc_pwc_pwr_mode_cfg_t* pstcPwrMdCfg) +{ + DDL_ASSERT(IS_PWC_PWR_DOWN_MODE(pstcPwrMdCfg->enPwrDownMd )); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPwrMdCfg->enRLdo)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPwrMdCfg->enRetSram)); + DDL_ASSERT(IS_PWC_PWR_DWON_IO_STATE(pstcPwrMdCfg->enIoRetain)); + DDL_ASSERT(IS_PWC_PWR_DOWN_WKUP_TIM(pstcPwrMdCfg->enPwrDWkupTm)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC0 = (pstcPwrMdCfg->enPwrDownMd | + (uint8_t)(((Enable == pstcPwrMdCfg->enRLdo) ? 0u : 1u) << 2u) | + (uint8_t)(((Enable == pstcPwrMdCfg->enRetSram) ? 0u : 1u) << 3u) | + (pstcPwrMdCfg->enIoRetain << 4u)); + + M4_SYSREG->PWR_PWRC3 = (pstcPwrMdCfg->enPwrDWkupTm | (0x03)); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enter power down mode. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be put ram + ** + ******************************************************************************/ +__RAM_FUNC void PWC_EnterPowerDownMd(void) +{ + ENABLE_PVD_REG_WRITE(); + + /* Reset PVD1IRS & PVD2IRS */ + M4_SYSREG->PWR_PVDCR1 &= 0xddu; + + DISABLE_PVD_REG_WRITE(); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 1u; + + __disable_irq(); + M4_SYSREG->PWR_PWRC0_f.PWDN = 1u; + for(uint8_t i = 0u; i < 10u; i++) + { + __NOP(); + } + __enable_irq(); + + DISABLE_PWR_REG_WRITE(); + + __WFI(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup0Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN0_WKUP00 Wake_up 0_0 event + ** \arg PWC_PDWKEN0_WKUP01 Wake_up 0_1 event + ** \arg PWC_PDWKEN0_WKUP02 Wake_up 0_2 event + ** \arg PWC_PDWKEN0_WKUP03 Wake_up 0_3 event + ** \arg PWC_PDWKEN0_WKUP10 Wake_up 1_0 event + ** \arg PWC_PDWKEN0_WKUP11 Wake_up 1_1 event + ** \arg PWC_PDWKEN0_WKUP12 Wake_up 1_2 event + ** \arg PWC_PDWKEN0_WKUP13 Wake_up 1_3 event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup0Cmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP_EVENT(u32Wkup0Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE0 |= (uint8_t)u32Wkup0Event; + } + else + { + M4_SYSREG->PWR_PDWKE0 &= (uint8_t)(~u32Wkup0Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup1Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN1_WKUP20 Wake_up 2_0 event + ** \arg PWC_PDWKEN1_WKUP21 Wake_up 2_1 event + ** \arg PWC_PDWKEN1_WKUP22 Wake_up 2_2 event + ** \arg PWC_PDWKEN1_WKUP23 Wake_up 2_3 event + ** \arg PWC_PDWKEN1_WKUP30 Wake_up 3_0 event + ** \arg PWC_PDWKEN1_WKUP31 Wake_up 3_1 event + ** \arg PWC_PDWKEN1_WKUP32 Wake_up 3_2 event + ** \arg PWC_PDWKEN1_WKUP33 Wake_up 3_3 event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup1Cmd(uint32_t u32Wkup1Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP_EVENT(u32Wkup1Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE1 |= (uint8_t)u32Wkup1Event; + } + else + { + M4_SYSREG->PWR_PDWKE1 &= (uint8_t)(~u32Wkup1Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup2Event The wake_up event in PDWKEN0. + ** \arg PWC_PDWKEN2_PVD1 Wake_up PVD1 event + ** \arg PWC_PDWKEN2_PVD2 Wake_up PVD2 event + ** \arg PWC_PDWKEN2_NMI Wake_up NMI event + ** \arg PWC_PDWKEN2_RTCPRD Wake_up RTCPRD event + ** \arg PWC_PDWKEN2_RTCAL Wake_up RTCAL event + ** \arg PWC_PDWKEN2_WKTM Wake_up WKTM event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeup2Cmd(uint32_t u32Wkup2Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WKUP2_EVENT(u32Wkup2Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_PDWKE2 |= (uint8_t)u32Wkup2Event; + } + else + { + M4_SYSREG->PWR_PDWKE2 &= (uint8_t)(~u32Wkup2Event); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Configure the power down wake up event edge. + ** + ** \param [in] u8WkupEvent The wake_up event in PDWKEN0. + ** \arg PWC_PDWKUP_EDGE_WKP0 Wake_up WKP0 event + ** \arg PWC_PDWKUP_EDGE_WKP1 Wake_up WKP1 event + ** \arg PWC_PDWKUP_EDGE_WKP2 Wake_up WKP2 event + ** \arg PWC_PDWKUP_EDGE_WKP3 Wake_up WKP3 event + ** \arg PWC_PDWKUP_EDGE_PVD1 Wake_up PVD1 event + ** \arg PWC_PDWKUP_EDGE_PVD2 Wake_up PVD2 event + ** \arg PWC_PDWKUP_EDGE_NMI Wake_up NMI event + ** + ** \param [in] enEdge The wake_up event edge select. + ** \arg EdgeRising Wake_up event edge rising. + ** \arg EdgeFalling Wake_up event edge falling. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PdWakeupEvtEdgeCfg(uint8_t u8WkupEvent, en_pwc_edge_sel_t enEdge) +{ + DDL_ASSERT(IS_PWC_WKUP_EDGE_EVENT(u8WkupEvent)); + DDL_ASSERT(IS_PWC_EDGE_SEL(enEdge)); + + ENABLE_PWR_REG_WRITE(); + + if(EdgeRising == enEdge) + { + M4_SYSREG->PWR_PDWKES |= (uint8_t)u8WkupEvent; + } + else + { + M4_SYSREG->PWR_PDWKES &= (uint8_t)(~u8WkupEvent); + } + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get wake_up event in PDWKF0 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF0. + ** \arg PWC_PTWK0_WKUPFLAG Ptwk0 wake_up flag + ** \arg PWC_PTWK1_WKUPFLAG Ptwk1 wake_up flag + ** \arg PWC_PTWK2_WKUPFLAG Ptwk2 wake_up flag + ** \arg PWC_PTWK3_WKUPFLAG Ptwk3 wake_up flag + ** \arg PWC_PVD1_WKUPFLAG Pvd1 wake_up flag + ** \arg PWC_PVD2_WKUPFLAG Pvd2 wake_up flag + ** \arg PWC_NMI_WKUPFLAG Nmi wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetWakeup0Flag(uint8_t u8WkupFlag) +{ + uint8_t u8flag; + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8WkupFlag)); + + u8flag = (M4_SYSREG->PWR_PDWKF0 & u8WkupFlag); + + return ((0u == u8flag) ? Reset : Set); +} + +/** + ******************************************************************************* + ** \brief Get wake_up event in PDWKF1 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF1. + ** \arg PWC_RTCPRD_WKUPFALG Rtcprd wake_up flag + ** \arg PWC_RTCAL_WKUPFLAG Rtcal wake_up flag + ** \arg PWC_WKTM_WKUPFLAG Wktm wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetWakeup1Flag(uint8_t u8WkupFlag) +{ + uint8_t u8flag; + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8WkupFlag)); + + u8flag = (M4_SYSREG->PWR_PDWKF1 & u8WkupFlag); + + return ((0u == u8flag) ? Reset : Set); +} + +/** + ******************************************************************************* + ** \brief clear wake_up event in PDWKF0 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF0. + ** \arg PWC_PTWK0_WKUPFLAG Ptwk0 wake_up flag + ** \arg PWC_PTWK1_WKUPFLAG Ptwk1 wake_up flag + ** \arg PWC_PTWK2_WKUPFLAG Ptwk2 wake_up flag + ** \arg PWC_PTWK3_WKUPFLAG Ptwk3 wake_up flag + ** \arg PWC_PVD1_WKUPFLAG Pvd1 wake_up flag + ** \arg PWC_PVD2_WKUPFLAG Pvd2 wake_up flag + ** \arg PWC_NMI_WKUPFLAG Nmi wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearWakeup0Flag(uint8_t u8WkupFlag) +{ + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8WkupFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PDWKF0 &= (uint8_t)(~u8WkupFlag); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief clear wake_up event in PDWKF1 flag. + ** + ** \param [in] u8WkupFlag The wake_up event in PDWKF1. + ** \arg PWC_RTCPRD_WKUPFALG Rtcprd wake_up flag + ** \arg PWC_RTCAL_WKUPFLAG Rtcal wake_up flag + ** \arg PWC_WKTM_WKUPFLAG Wktm wake_up flag + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearWakeup1Flag(uint8_t u8WkupFlag) +{ + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8WkupFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PDWKF1 &= (uint8_t)(~u8WkupFlag); + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief Enable or disable power monitor . + ** + ** \param [in] enNewState The power monitor state. + ** \arg Enable Enable power monitor. + ** \arg Disable Disable power monitor. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PwrMonitorCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWCMR_f.ADBUFE = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG0 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg0Periph The peripheral in FCG0. + ** \arg PWC_FCG0_PERIPH_SRAMH RAMHS clock + ** \arg PWC_FCG0_PERIPH_SRAM12 RAM0 clock + ** \arg PWC_FCG0_PERIPH_SRAM3 ECCRAM clock + ** \arg PWC_FCG0_PERIPH_SRAMRET RetRAM clock + ** \arg PWC_FCG0_PERIPH_DMA1 DMA1 clock + ** \arg PWC_FCG0_PERIPH_DMA2 DMA2 clock + ** \arg PWC_FCG0_PERIPH_FCM FCM clock + ** \arg PWC_FCG0_PERIPH_AOS PTDIS clock + ** \arg PWC_FCG0_PERIPH_AES AES clock + ** \arg PWC_FCG0_PERIPH_HASH HASH clock + ** \arg PWC_FCG0_PERIPH_TRNG TRNG clock + ** \arg PWC_FCG0_PERIPH_CRC CRC clock + ** \arg PWC_FCG0_PERIPH_DCU1 DCU1 clock + ** \arg PWC_FCG0_PERIPH_DCU2 DCU2 clock + ** \arg PWC_FCG0_PERIPH_DCU3 DCU3 clock + ** \arg PWC_FCG0_PERIPH_DCU4 DCU4 clock + ** \arg PWC_FCG0_PERIPH_KEY KEY clock + + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_FCG0_REG_WRITE(); + + if(Enable == enNewState) + { + M4_MSTP->FCG0 &= ~u32Fcg0Periph; + } + else + { + M4_MSTP->FCG0 |= u32Fcg0Periph; + } + + DISABLE_FCG0_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG1 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg1Periph The peripheral in FCG1. + ** \arg PWC_FCG1_PERIPH_CAN CAN clock + ** \arg PWC_FCG1_PERIPH_QSPI QSPI clock + ** \arg PWC_FCG1_PERIPH_I2C1 I2C1 clock + ** \arg PWC_FCG1_PERIPH_I2C2 I2C2 clock + ** \arg PWC_FCG1_PERIPH_I2C3 I2C3 clock + ** \arg PWC_FCG1_PERIPH_USBFS USBFS clock + ** \arg PWC_FCG1_PERIPH_SDIOC1 SDIOC1 clock + ** \arg PWC_FCG1_PERIPH_SDIOC2 SDIOC2 clock + ** \arg PWC_FCG1_PERIPH_I2S1 I2S1 clock + ** \arg PWC_FCG1_PERIPH_I2S2 I2S2 clock + ** \arg PWC_FCG1_PERIPH_I2S3 I2S3 clock + ** \arg PWC_FCG1_PERIPH_I2S4 I2S4 clock + ** \arg PWC_FCG1_PERIPH_SPI1 SPI1 clock + ** \arg PWC_FCG1_PERIPH_SPI2 SPI2 clock + ** \arg PWC_FCG1_PERIPH_SPI3 SPI3 clock + ** \arg PWC_FCG1_PERIPH_SPI4 SPI4 clock + ** \arg PWC_FCG1_PERIPH_USART1 USART1 clock + ** \arg PWC_FCG1_PERIPH_USART2 USART2 clock + ** \arg PWC_FCG1_PERIPH_USART3 USART3 clock + ** \arg PWC_FCG1_PERIPH_USART4 USART4 clock + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG1 &= ~u32Fcg1Periph; + } + else + { + M4_MSTP->FCG1 |= u32Fcg1Periph; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG2 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg2Periph The peripheral in FCG2. + ** \arg PWC_FCG2_PERIPH_TIM01 TIM01 clock + ** \arg PWC_FCG2_PERIPH_TIM02 TIM02 clock + ** \arg PWC_FCG2_PERIPH_TIMA1 TIMA1 clock + ** \arg PWC_FCG2_PERIPH_TIMA2 TIMA2 clock + ** \arg PWC_FCG2_PERIPH_TIMA3 TIMA3 clock + ** \arg PWC_FCG2_PERIPH_TIMA4 TIMA4 clock + ** \arg PWC_FCG2_PERIPH_TIMA5 TIMA5 clock + ** \arg PWC_FCG2_PERIPH_TIMA6 TIMA6 clock + ** \arg PWC_FCG2_PERIPH_TIM41 TIM41 clock + ** \arg PWC_FCG2_PERIPH_TIM42 TIM42 clock + ** \arg PWC_FCG2_PERIPH_TIM43 TIM43 clock + ** \arg PWC_FCG2_PERIPH_EMB EMB clock + ** \arg PWC_FCG2_PERIPH_TIM61 TIM61 clock + ** \arg PWC_FCG2_PERIPH_TIM62 TIM62 clock + ** \arg PWC_FCG2_PERIPH_TIM63 TIM63 clock + + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG2 &= ~u32Fcg2Periph; + } + else + { + M4_MSTP->FCG2 |= u32Fcg2Periph; + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable the FCG3 peripheral clock. + ** + ** \note After reset,the peripheral clock is disabled and the application + ** software has to enable this clock before using it. + ** + ** \param [in] u32Fcg3Periph The peripheral in FCG3. + ** \arg PWC_FCG3_PERIPH_ADC1 ADC1 clock + ** \arg PWC_FCG3_PERIPH_ADC2 ADC2 clock + ** \arg PWC_FCG3_PERIPH_CMP CMP clock + ** \arg PWC_FCG3_PERIPH_OTS OTS clock + ** + ** \param [in] enNewState The new state of the clock output. + ** \arg Enable Enable clock output. + ** \arg Disable Disable clock output. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_MSTP->FCG3 &= ~u32Fcg3Periph; + } + else + { + M4_MSTP->FCG3 |= u32Fcg3Periph; + } +} + +/** + ******************************************************************************* + ** \brief The stop mode configuration. + ** + ** \param [in] pstcStpMdCfg Pointer to stop mode configuration structure. + ** \arg Enable Enable stop mode. + ** \arg Disable Disable stop mode. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +en_result_t PWC_StopModeCfg(const stc_pwc_stop_mode_cfg_t* pstcStpMdCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_PWC_STOP_MODE_FLASH(pstcStpMdCfg->enStopFlash)); + DDL_ASSERT(IS_PWC_STOP_MODE_CLK(pstcStpMdCfg->enStopClk)); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_STPMCR = (pstcStpMdCfg->enStopFlash | + (pstcStpMdCfg->enStopClk << 1u) | + (1u << 14u)); + + /* if should close HRC & PLL while stop mode, please disable before modifying the register */ + if(Disable == pstcStpMdCfg->enPll) + { + /* PLL is system clock */ + if(5u == M4_SYSREG->CMU_CKSWR_f.CKSW) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Disable PLL */ + M4_SYSREG->CMU_PLLCR_f.MPLLOFF = 1u; + } + } + + /* Hrc power should be enable. */ + M4_SYSREG->PWR_PWRC1_f.VHRCSD = 0u; + M4_SYSREG->PWR_PWRC1_f.VPLLSD = ((Enable == pstcStpMdCfg->enPll) ? 0u : 1u); + M4_SYSREG->PWR_PWRC1_f.STPDAS = pstcStpMdCfg->enStpDrvAbi; + + DISABLE_PWR_REG0_WRITE(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable the power down wake up event. + ** + ** \param [in] u32Wkup0Event The wake_up event in PDWKEN0. + ** \arg PWC_STOPWKUPEN_EIRQ0 EIRQ0 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ1 EIRQ1 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ2 EIRQ2 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ3 EIRQ3 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ4 EIRQ4 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ5 EIRQ5 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ6 EIRQ6 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ7 EIRQ7 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ8 EIRQ8 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ9 EIRQ9 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ10 EIRQ10 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ11 EIRQ11 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ12 EIRQ12 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ13 EIRQ13 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ14 EIRQ14 wake_up event + ** \arg PWC_STOPWKUPEN_EIRQ15 EIRQ15 wake_up event + ** \arg PWC_STOPWKUPEN_SWDT SWDT wake_up event + ** \arg PWC_STOPWKUPEN_VDU1 VDU1 wake_up event + ** \arg PWC_STOPWKUPEN_VDU2 VDU2 wake_up event + ** \arg PWC_STOPWKUPEN_CMPI0 CMPI0 wake_up event + ** \arg PWC_STOPWKUPEN_WKTM WKTM wake_up event + ** \arg PWC_STOPWKUPEN_RTCAL RTCAL wake_up event + ** \arg PWC_STOPWKUPEN_RTCPRD RTCPRD wake_up event + ** \arg PWC_STOPWKUPEN_TMR0 TMR0 wake_up event + ** \arg PWC_STOPWKUPEN_USARTRXD USARTRXD wake_up event + ** + ** \param [in] enNewState The new state of the wake_up event. + ** \arg Enable Enable wake_up event. + ** \arg Disable Disable wake_up event. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_StopWkupCmd(uint32_t u32Wkup0Event, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + M4_INTC->WUPEN |= u32Wkup0Event; + } + else + { + M4_INTC->WUPEN &= ~u32Wkup0Event; + } +} + +/** + ******************************************************************************* + ** \brief Enter sleep mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_EnterSleepMd(void) +{ + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 0u; + M4_SYSREG->PWR_PWRC0_f.PWDN = 0u; + + DISABLE_PWR_REG_WRITE(); + + __WFI(); +} +/** + ******************************************************************************* + ** \brief Ram area power down commond. + ** + ** \param [in] u32RamCtlBit The ram area contol. + ** \arg PWC_RAMPWRDOWN_SRAM1 Ram0(0x20000000-0x2000FFFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAM2 Ram1(0x20010000-0x2001FFFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAM3 Ram2(0x20020000-0x20026FFF) power down control. + ** \arg PWC_RAMPWRDOWN_SRAMH Ram3(0x1FFF8000-0x1FFFFFFF) power down control. + ** \arg PWC_RAMPWRDOWN_USBFS Usbfs power down control. + ** \arg PWC_RAMPWRDOWN_SDIOC0 Sdioc0 power down control. + ** \arg PWC_RAMPWRDOWN_SDIOC1 Sdioc1 power down control. + ** \arg PWC_RAMPWRDOWN_CAN Can power down control. + ** \arg PWC_RAMPWRDOWN_CACHE Cache power down control. + ** \arg PWC_RAMPWRDOWN_FULL Full. + ** + ** \param [in] enNewState The new state of the Ram area. + ** \arg Enable Ten ram area run. + ** \arg Disable The ram area power down. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_RamPwrdownCmd(uint32_t u32RamCtlBit, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + if(Enable == enNewState) + { + M4_SYSREG->PWR_RAMPC0 &= ~u32RamCtlBit; + } + else + { + M4_SYSREG->PWR_RAMPC0 |= u32RamCtlBit; + } + + DISABLE_PWR_REG_WRITE(); +} + +void PWC_RamOpMdConfig(en_pwc_ram_op_md_t enRamOpMd) +{ + DDL_ASSERT(IS_PWC_RAM_OP_MD(enRamOpMd)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_RAMOPM = enRamOpMd; + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief Enable or disable XTAL/RTC/WKTM bias current. + ** + ** \param [in] enNewState The XTAL/RTC/WKTM bias current state. + ** \arg Enable Enable XTAL/RTC/WKTM bias current. + ** \arg Disable Disable XTAL/RTC/WKTM bias current. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Xtal32CsCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_XTAL32CS_f.CSDIS = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief wake_up timer control. + ** + ** \param [in] pstcWktmCtl The wake_up timer configuration. + ** \arg enWktmEn Enable or disable wake_up timer. + ** \arg enWkclk The wake_up timer clock. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_WktmControl(const stc_pwc_wktm_ctl_t* pstcWktmCtl) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcWktmCtl->enWktmEn)); + DDL_ASSERT(IS_PWC_WKTM_CLK(pstcWktmCtl->enWkclk)); + DDL_ASSERT(IS_PWC_WKTMOVER_FLAG(pstcWktmCtl->enWkOverFlag)); + + ENABLE_PWR_REG_WRITE(); + + M4_WKTM->CR = ((pstcWktmCtl->u16WktmCmp & PWC_WKTMCMP_MSK) | + (pstcWktmCtl->enWkOverFlag << 12) | + (pstcWktmCtl->enWkclk << 13) | + (pstcWktmCtl->enWktmEn << 15)); + + DISABLE_PWR_REG_WRITE(); +} +/** + ******************************************************************************* + ** \brief The pvd configuration. + ** + ** \param [in] pstcPvdCfg The pvd configuration. + ** \arg enPtwk0Edge Ptwk0 edge + ** \arg enPtwk1Edge Ptwk1 edge + ** \arg enPtwk2Edge Ptwk2 edge + ** \arg enPtwk3Edge Ptwk3 edge + ** \arg enPvd1Edge Pvd1 edge + ** \arg enPvd1Edge Pvd2 edge + ** \arg enNmiEdge Nmi edge + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_PvdCfg(const stc_pwc_pvd_cfg_t* pstcPvdCfg) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd1Ctl.enPvdIREn)); + DDL_ASSERT(IS_PWC_PVD_MD(pstcPvdCfg->stcPvd1Ctl.enPvdMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd1Ctl.enPvdCmpOutEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd2Ctl.enPvdIREn)); + DDL_ASSERT(IS_PWC_PVD_MD(pstcPvdCfg->stcPvd2Ctl.enPvdMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->stcPvd2Ctl.enPvdCmpOutEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->enPvd1FilterEn)); + DDL_ASSERT(IS_PWC_PVD_FILTER_CLK(pstcPvdCfg->enPvd1Filtclk)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcPvdCfg->enPvd2FilterEn)); + DDL_ASSERT(IS_PWC_PVD_FILTER_CLK(pstcPvdCfg->enPvd2Filtclk)); + DDL_ASSERT(IS_PWC_PVD1_LEVEL(pstcPvdCfg->enPvd1Level)); + DDL_ASSERT(IS_PWC_PVD2_LEVEL(pstcPvdCfg->enPvd2Level)); + DDL_ASSERT(IS_PWC_PVD_INT_SEL(pstcPvdCfg->enPvd1Int)); + DDL_ASSERT(IS_PWC_PVD_INT_SEL(pstcPvdCfg->enPvd2Int)); + + ENABLE_PVD_REG_WRITE(); + + /* Config Pvd control. */ + M4_SYSREG->PWR_PVDCR1 = (pstcPvdCfg->stcPvd1Ctl.enPvdIREn | + (pstcPvdCfg->stcPvd1Ctl.enPvdMode << 1) | + (pstcPvdCfg->stcPvd1Ctl.enPvdCmpOutEn << 2) | + (pstcPvdCfg->stcPvd2Ctl.enPvdIREn<< 4) | + (pstcPvdCfg->stcPvd2Ctl.enPvdMode << 5) | + (pstcPvdCfg->stcPvd2Ctl.enPvdCmpOutEn << 6)); + /* Set pvd filter sampling. */ + M4_SYSREG->PWR_PVDFCR = (~(pstcPvdCfg->enPvd1FilterEn) | + (pstcPvdCfg->enPvd1Filtclk << 1) | + ((~pstcPvdCfg->enPvd2FilterEn) << 4) | + (pstcPvdCfg->enPvd2Filtclk << 5)); + /* Set pvd level. */ + M4_SYSREG->PWR_PVDLCR = (pstcPvdCfg->enPvd1Level | + (pstcPvdCfg->enPvd2Level << 4)); + /* Set pvd interrupt(non_maskable or maskable). */ + M4_SYSREG->PWR_PVDICR = (pstcPvdCfg->enPvd1Int | + (pstcPvdCfg->enPvd2Int << 4)); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable pvd1. + ** + ** \param [in] enNewState The pvd1 state. + ** \arg Enable Enable pvd1. + ** \arg Disable Disable pvd1. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Pvd1Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.PVD1EN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable pvd2. + ** + ** \param [in] enNewState The pvd2 state. + ** \arg Enable Enable pvd2. + ** \arg Disable Disable pvd2. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_Pvd2Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.PVD2EN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable external vcc. + ** + ** \param [in] enNewState The external vcc state. + ** \arg Enable Enable external vcc. + ** \arg Disable Disable external vcc. + ** + ** \retval None + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ExVccCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PVD_REG_WRITE(); + + M4_SYSREG->PWR_PVDCR0_f.EXVCCINEN = ((Enable == enNewState) ? 1u : 0u); + + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Get pvd detection status. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetPvdStatus(en_pwc_pvd_t enPvd) +{ + uint8_t u8flag = 0u; + + switch(enPvd) + { + case PvdU1: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD1MON; + break; + case PvdU2: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD2MON; + break; + default: + break; + } + + return ((1u == u8flag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Get pvd detection flag. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \retval en_flag_status_t + ** + ** \note None + ** + ******************************************************************************/ +en_flag_status_t PWC_GetPvdFlag(en_pwc_pvd_t enPvd) +{ + uint8_t u8flag = 0u; + + switch(enPvd) + { + case PvdU1: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD1DETFLG; + break; + case PvdU2: + u8flag = M4_SYSREG->PWR_PVDDSR_f.PVD2DETFLG; + break; + default: + break; + } + + return ((1u == u8flag) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear pvd detection flag. + ** + ** \param [in] enPvd The unit of pvd detection. + ** \arg PvdU1 The unit1 of pvd detection. + ** \arg PvdU2 The unit2 of pvd detection. + ** + ** \note None + ** + ******************************************************************************/ +void PWC_ClearPvdFlag(en_pwc_pvd_t enPvd) +{ + ENABLE_PVD_REG_WRITE(); + switch(enPvd) + { + case PvdU1: + M4_SYSREG->PWR_PVDDSR_f.PVD1MON = 0u; + break; + case PvdU2: + M4_SYSREG->PWR_PVDDSR_f.PVD2MON = 0u; + break; + default: + break; + } + DISABLE_PVD_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable HRC power. + ** + ** \param [in] enNewState The HRC power state. + ** \arg Enable Enable HRC power. + ** \arg Disable Disable HRC power. + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_HrcPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC1_f.VHRCSD = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Enable or disable PLL power. + ** + ** \param [in] enNewState The PLL power state. + ** \arg Enable Enable PLL power. + ** \arg Disable Disable PLL power. + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_PllPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + ENABLE_PWR_REG_WRITE(); + + M4_SYSREG->PWR_PWRC1_f.VPLLSD = ((Enable == enNewState) ? 0u : 1u); + + DISABLE_PWR_REG_WRITE(); +} + +/** + ******************************************************************************* + ** \brief NVIC backup and disable before entry from stop mode + ** + ** param None + ** + ** retval None + ** + *****************************************************************************/ +void PWC_enNvicBackup(void) +{ + uint8_t u8Cnt; + stc_intc_sel_field_t *stcIntSel; + uint32_t u32WakeupSrc = INT_MAX; + + /* Backup NVIC set enable register for IRQ0~143*/ + for (u8Cnt = 0u; u8Cnt < sizeof(NVIC_ISER_BAK)/sizeof(uint32_t); u8Cnt++) + { + NVIC_ISER_BAK[u8Cnt] = NVIC->ISER[u8Cnt]; + } + + /* Disable share vector */ + for (u8Cnt = 128u; u8Cnt < 144u; u8Cnt++) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + + for (u8Cnt = 0u; u8Cnt < 128u; u8Cnt++) + { + stcIntSel = (stc_intc_sel_field_t *)((uint32_t)(&M4_INTC->SEL0) + (4ul * u8Cnt)); + /* Disable NVIC if it is the wakeup-able source from stop mode */ + u32WakeupSrc = stcIntSel->INTSEL; + if (IS_VALID_WKUP_SRC(u32WakeupSrc)) + { + switch (stcIntSel->INTSEL) + { + case INT_USART1_WUPI: + if (Reset == bM4_INTC_WUPEN_RXWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_TMR01_GCMA: + if (Reset == bM4_INTC_WUPEN_TMR0WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_RTC_ALM: + if (Reset == bM4_INTC_WUPEN_RTCALMWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_RTC_PRD: + if (Reset == bM4_INTC_WUPEN_RTCPRDWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_WKTM_PRD: + if (Reset == bM4_INTC_WUPEN_WKTMWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_ACMP1: + if (Reset == bM4_INTC_WUPEN_CMPI0WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PVD_PVD1: + if (Reset == bM4_INTC_WUPEN_PVD1WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PVD_PVD2: + if (Reset == bM4_INTC_WUPEN_PVD2WUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_SWDT_REFUDF: + if (Reset == bM4_INTC_WUPEN_SWDTWUEN) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ0: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN0) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ1: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN1) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ2: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN2) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ3: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN3) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ4: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN4) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ5: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN5) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ6: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN6) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ7: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN7) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ8: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN8) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ9: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN9) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ10: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN10) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ11: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN11) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ12: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN12) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ13: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN13) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ14: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN14) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + case INT_PORT_EIRQ15: + if (Reset == bM4_INTC_WUPEN_EIRQWUEN15) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + break; + default: + break; + } + } + /* Disable NVIC for all none-wakeup source */ + else if (INT_MAX != stcIntSel->INTSEL) + { + NVIC_DisableIRQ((IRQn_Type)u8Cnt); + } + else + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief NVIC recover after wakeup from stop mode + ** + ** param None + ** + ** retval None + ** + *****************************************************************************/ +void PWC_enNvicRecover(void) +{ + uint8_t u8Cnt; + + for (u8Cnt = 0u; u8Cnt < sizeof(NVIC_ISER_BAK)/sizeof(uint32_t); u8Cnt++) + { + NVIC->ISER[u8Cnt] = NVIC_ISER_BAK[u8Cnt]; + } +} + +/** + ******************************************************************************* + ** \brief Select system clock source. + ** + ** \param [in] u8SysSrc The system clock source. + ** + ** \retval None + ** + ** \note Must close all of the fcg register before switch system clock source. + ** This function only be called in func. PWC_enClockBackup and + ** PWC_enClockRecover. + ** If need to switch system clock please call CLK_SetSysClkSource. + ** + ******************************************************************************/ +static void PWC_SetSysClk(uint8_t u8SysSrc) +{ + __IO uint32_t fcg0 = M4_MSTP->FCG0; + __IO uint32_t fcg1 = M4_MSTP->FCG1; + __IO uint32_t fcg2 = M4_MSTP->FCG2; + __IO uint32_t fcg3 = M4_MSTP->FCG3; + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if((5u == M4_SYSREG->CMU_CKSWR_f.CKSW) || (5u == u8SysSrc)) + { + /* Close fcg0~fcg3. */ + M4_MSTP->FCG0 = 0xFFFFFAEEul; + M4_MSTP->FCG1 = 0xFFFFFFFFul; + M4_MSTP->FCG2 = 0xFFFFFFFFul; + M4_MSTP->FCG3 = 0xFFFFFFFFul; + + Ddl_Delay1us(1ul); + } + + /* Switch to target system clock source. */ + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->CMU_CKSWR_f.CKSW = u8SysSrc; + + DISABLE_PWR_REG0_WRITE(); + + /* update system clock frequency. */ + SystemCoreClockUpdate(); + + Ddl_Delay1us(1ul); + + /* Open fcg0~fcg3. */ + M4_MSTP->FCG0 = fcg0; + M4_MSTP->FCG1 = fcg1; + M4_MSTP->FCG2 = fcg2; + M4_MSTP->FCG3 = fcg3; + + Ddl_Delay1us(1ul); +} +/** + ******************************************************************************* + ** \brief Backup HRC/MRC state and system clock , enable HRC/MRC ,set MRC as + ** system clock before enter stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +static void PWC_enClockBackup(void) +{ + __IO uint32_t timeout = 0ul; + en_flag_status_t status = Reset; + + /* HRC state backup. */ + u8HrcState = (uint8_t)bM4_SYSREG_CMU_HRCCR_HRCSTP; + /* System clock backup*/ + u8SysClkSrc = M4_SYSREG->CMU_CKSWR_f.CKSW; + + ENABLE_PWR_REG0_WRITE(); + + /* Enable HRC before enter stop mode. */ + if(0u != u8HrcState) + { + bM4_SYSREG_CMU_HRCCR_HRCSTP = 0u; + do + { + status = (en_flag_status_t)M4_SYSREG->CMU_OSCSTBSR_f.HRCSTBF; + timeout++; + }while((timeout < 0x1000ul) && (status != Set)); + } + else + { + /* code */ + } + /* When system clock source is HRC and MPLL, set MRC as system clock. . */ + if((0u == u8SysClkSrc) || (5u == u8SysClkSrc)) + { + /* MRC state backup. */ + u8MrcState = (uint8_t)bM4_SYSREG_CMU_MRCCR_MRCSTP; + if(0u != u8MrcState) + { + bM4_SYSREG_CMU_MRCCR_MRCSTP = 0u; + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + PWC_SetSysClk(1u); + } + else + { + /* code */ + } + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Recover HRC/MRC state and system clock after wakeup stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +static void PWC_enClockRecover(void) +{ + ENABLE_PWR_REG0_WRITE(); + + if((0u == u8SysClkSrc) || (5u == u8SysClkSrc)) + { + /* Recover MRC state & system clock source. */ + M4_SYSREG->CMU_MRCCR_f.MRCSTP = u8MrcState; + PWC_SetSysClk(u8SysClkSrc); + } + /* Recover HRC state after wakeup stop mode. */ + M4_SYSREG->CMU_HRCCR_f.HRCSTP = u8HrcState; + + DISABLE_PWR_REG0_WRITE(); +} + +/** + ******************************************************************************* + ** \brief Clock backup before enter stop mode and mark it. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called before func. PWC_EnterStopMd. + ******************************************************************************/ +void PWC_ClkBackup(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* HRC/MRC backup and switch system clock as MRC before entry from stop mode. */ + PWC_enClockBackup(); + + /* Mark the system clock has been switch as MRC, and will enter the stop mode. */ + u8StopFlag = 1u; + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + ******************************************************************************* + ** \brief Clock recover after wakeup stop mode. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called after func. PWC_EnterStopMd. + ******************************************************************************/ +void PWC_ClkRecover(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* Mark the system clock will be switch as MRC, and has waked_up from stop mode. */ + u8StopFlag = 0u; + + /* Recover HRC/MRC state and system clock after wakeup stop mode. */ + PWC_enClockRecover(); + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + ******************************************************************************* + ** \brief Clock backup before exit wakup interrupt. + ** + ** \param None + ** + ** \retval None + ** + ** \note This function should be called before exit wakup interrput. + ******************************************************************************/ +void PWC_IrqClkBackup(void) +{ + if((1ul == u8StopFlag) && (1ul == u8WkupIntCnt)) + { + /* HRC/MRC backup and switch system clock as MRC. */ + PWC_enClockBackup(); + } + u8WkupIntCnt--; +} + +/** + ******************************************************************************* + ** \brief Clock recover after enter wakeup interrupt. + ** + ** \param None + ** + ** \retval None + ** +** \note This function should be called after enter wakup interrput. + ******************************************************************************/ +void PWC_IrqClkRecover(void) +{ + /* The varibale to display how many waked_up interrupt has been occured + simultaneously and to decided whether backup clock before exit wake_up + interrupt. */ + u8WkupIntCnt++; + + if(1ul == u8StopFlag) + { + /* Recover HRC/MRC state and system clock. */ + PWC_enClockRecover(); + } +} + +/** + ******************************************************************************* + ** \brief Enter stop mode. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +void PWC_EnterStopMd(void) +{ + /* NVIC backup and disable before entry from stop mode.*/ + PWC_enNvicBackup(); + /* Clock backup and switch system clock as MRC before entry from stop mode. */ + PWC_ClkBackup(); + + ENABLE_PWR_REG0_WRITE(); + + M4_SYSREG->PWR_STPMCR_f.STOP = 1u; + M4_SYSREG->PWR_PWRC0_f.PWDN = 0u; + + DISABLE_PWR_REG0_WRITE(); + + __WFI(); + + /* Recover HRC/MRC state and system clock after wakeup from stop mode. */ + PWC_ClkRecover(); + /* NVIC recover after wakeup from stop mode. */ + PWC_enNvicRecover(); +} + +/** + ******************************************************************************* + ** \brief Switch MCU from low_speed (HCLK < 8MHz) to high-speed (HCLK > 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HS2LS(void) +{ + uint32_t u32To = 10000ul; + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 1u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 1u; + } + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_RAMOPM = 0x9062u; + while((0x9062 != M4_SYSREG->PWR_RAMOPM) || (1u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + M4_SYSREG->PWR_PWRC2 = 0xE1U; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-speed (HCLK > 8MHz) to low_speed (HCLK < 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_LS2HS(void) +{ + uint32_t u32To = 10000ul; + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xFFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + Ddl_Delay1ms(1ul); + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 0u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 0u; + } + + M4_SYSREG->PWR_RAMOPM = 0x8043u; + while((0x8043 != M4_SYSREG->PWR_RAMOPM) || (0u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + DISABLE_PWR_REG_WRITE(); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-speed (HCLK > 8MHz) to high-performance mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_HS2HP(void) +{ + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xCFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-performance to high-speed (HCLK > 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HP2HS(void) +{ + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xFFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + DISABLE_PWR_REG_WRITE(); + Ddl_Delay1ms(1ul); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from low-speed (HCLK <= 8MHz) to high-performance mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called before clock is ready. + ******************************************************************************/ +en_result_t PWC_LS2HP(void) +{ + uint32_t u32To = 10000ul; + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_PWRC2 = 0xCFU; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + Ddl_Delay1ms(1); + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 0u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 0u; + } + + M4_SYSREG->PWR_RAMOPM = 0x8043u; + while((0x8043 != M4_SYSREG->PWR_RAMOPM) || (0u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + DISABLE_PWR_REG_WRITE(); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Switch MCU from high-performance to low-speed (HCLK <= 8MHz) mode. + ** + ** \param None + ** + ** \retval Ok: Mode switch sucessfully. + ** Error: Mode switch failure. + ** + ** \note Called after clock is ready. + ******************************************************************************/ +en_result_t PWC_HP2LS(void) +{ + uint32_t u32To = 10000ul; + + if(0ul == M4_EFM->FAPRT) + { + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x3210ul; + M4_EFM->FRMC_f.LVM = 1u; + M4_EFM->FAPRT = 0x0123ul; + M4_EFM->FAPRT = 0x0123ul; + } + else + { + M4_EFM->FRMC_f.LVM = 1u; + } + + ENABLE_PWR_REG_WRITE(); + M4_SYSREG->PWR_RAMOPM = 0x9062u; + u32To = 10000ul; + while((0x9062 != M4_SYSREG->PWR_RAMOPM) || (1u != M4_EFM->FRMC_f.LVM)) + { + if (0ul == u32To--) + { + return Error; + } + } + + M4_SYSREG->PWR_PWRC2 = 0xD1U; + M4_SYSREG->PWR_MDSWCR = 0x10U; + + DISABLE_PWR_REG_WRITE(); + + Ddl_Delay1ms(1); + + return Ok; +} + +#endif /* DDL_PWC_ENABLE */ + +//@} // PwcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_qspi.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_qspi.c new file mode 100644 index 0000000000..1f471aa6b0 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_qspi.c @@ -0,0 +1,756 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_qspi.c + ** + ** A detailed description is available at + ** @link QspiGroup Queued SPI description @endlink + ** + ** - 2018-11-20 CDT First version for Device Driver Library of Qspi. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_qspi.h" +#include "hc32f460_utility.h" + +#if (DDL_QSPI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup QspiGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for clock division */ +#define IS_VALID_CLK_DIV(x) \ +( ((x) == QspiHclkDiv2) || \ + (((x) >= QspiHclkDiv3) && ((x) <= QspiHclkDiv64))) + +/*!< Parameter valid check for spi mode */ +#define IS_VALID_SPI_MODE(x) \ +( (QspiSpiMode0 == (x)) || \ + (QspiSpiMode3 == (x))) + +/*!< Parameter valid check for bus communication mode */ +#define IS_VALID_BUS_COMM_MODE(x) \ +( (QspiBusModeRomAccess == (x)) || \ + (QspiBusModeDirectAccess == (x))) + +/*!< Parameter valid check for prefetch stop location */ +#define IS_VALID_PREFETCH_STOP_LOCATION(x) \ +( (QspiPrefetchStopComplete == (x)) || \ + (QspiPrefetchStopImmediately == (x))) + +/*!< Parameter valid check for receive data protocol */ +#define IS_VALID_RECE_DATA_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for transmit address protocol */ +#define IS_VALID_TRANS_ADDR_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for transmit instruction protocol */ +#define IS_VALID_TRANS_INSTRUCT_PROTOCOL(x) \ +( (QspiProtocolExtendSpi == (x)) || \ + (QspiProtocolTwoWiresSpi == (x)) || \ + (QspiProtocolFourWiresSpi == (x))) + +/*!< Parameter valid check for serial interface read mode */ +#define IS_VALID_INTERFACE_READ_MODE(x) \ +( (QspiReadModeStandard == (x)) || \ + (QspiReadModeFast == (x)) || \ + (QspiReadModeTwoWiresOutput == (x)) || \ + (QspiReadModeTwoWiresIO == (x)) || \ + (QspiReadModeFourWiresOutput == (x)) || \ + (QspiReadModeFourWiresIO == (x)) || \ + (QspiReadModeCustomStandard == (x)) || \ + (QspiReadModeCustomFast == (x))) + +/*!< Parameter valid check for QSSN valid extend delay time */ +#define IS_VALID_QSSN_VALID_EXTEND_TIME(x) \ +( (QspiQssnValidExtendNot == (x)) || \ + (QspiQssnValidExtendSck32 == (x)) || \ + (QspiQssnValidExtendSck128 == (x)) || \ + (QspiQssnValidExtendSckEver == (x))) + +/*!< Parameter valid check for QSSN minimum interval time */ +#define IS_VALID_QSSN_INTERVAL_TIME(x) \ +( (QspiQssnIntervalQsck1 == (x)) || \ + (QspiQssnIntervalQsck2 == (x)) || \ + (QspiQssnIntervalQsck3 == (x)) || \ + (QspiQssnIntervalQsck4 == (x)) || \ + (QspiQssnIntervalQsck5 == (x)) || \ + (QspiQssnIntervalQsck6 == (x)) || \ + (QspiQssnIntervalQsck7 == (x)) || \ + (QspiQssnIntervalQsck8 == (x)) || \ + (QspiQssnIntervalQsck9 == (x)) || \ + (QspiQssnIntervalQsck10 == (x)) || \ + (QspiQssnIntervalQsck11 == (x)) || \ + (QspiQssnIntervalQsck12 == (x)) || \ + (QspiQssnIntervalQsck13 == (x)) || \ + (QspiQssnIntervalQsck14 == (x)) || \ + (QspiQssnIntervalQsck15 == (x)) || \ + (QspiQssnIntervalQsck16 <= (x))) + +/*!< Parameter valid check for QSCK duty correction */ +#define IS_VALID_QSCK_DUTY_CORR(x) \ +( (QspiQsckDutyCorrNot == (x)) || \ + (QspiQsckDutyCorrHalfHclk == (x))) + +/*!< Parameter valid check for virtual cycles */ +#define IS_VALID_VIRTUAL_CYCLES(x) \ +( (QspiVirtualPeriodQsck3 == (x)) || \ + (QspiVirtualPeriodQsck4 == (x)) || \ + (QspiVirtualPeriodQsck5 == (x)) || \ + (QspiVirtualPeriodQsck6 == (x)) || \ + (QspiVirtualPeriodQsck7 == (x)) || \ + (QspiVirtualPeriodQsck8 == (x)) || \ + (QspiVirtualPeriodQsck9 == (x)) || \ + (QspiVirtualPeriodQsck10 == (x)) || \ + (QspiVirtualPeriodQsck11 == (x)) || \ + (QspiVirtualPeriodQsck12 == (x)) || \ + (QspiVirtualPeriodQsck13 == (x)) || \ + (QspiVirtualPeriodQsck14 == (x)) || \ + (QspiVirtualPeriodQsck15 == (x)) || \ + (QspiVirtualPeriodQsck16 == (x)) || \ + (QspiVirtualPeriodQsck17 == (x)) || \ + (QspiVirtualPeriodQsck18 == (x))) + +/*!< Parameter valid check for WP pin output level */ +#define IS_VALID_WP_OUTPUT_LEVEL(x) \ +( (QspiWpPinOutputLow == (x)) || \ + (QspiWpPinOutputHigh == (x))) + +/*!< Parameter valid check for QSSN setup delay time */ +#define IS_VALID_QSSN_SETUP_DELAY(x) \ +( (QspiQssnSetupDelayHalfQsck == (x)) || \ + (QspiQssnSetupDelay1Dot5Qsck == (x))) + +/*!< Parameter valid check for QSSN hold delay time */ +#define IS_VALID_QSSN_HOLD_TIME(x) \ +( (QspiQssnHoldDelayHalfQsck == (x)) || \ + (QspiQssnHoldDelay1Dot5Qsck == (x))) + +/*!< Parameter valid check for interface address width */ +#define IS_VALID_INTERFACE_ADDR_WIDTH(x) \ +( (QspiAddressByteOne == (x)) || \ + (QspiAddressByteTwo == (x)) || \ + (QspiAddressByteThree == (x)) || \ + (QspiAddressByteFour == (x))) + +/*!< Parameter valid check for extend address */ +#define IS_VALID_SET_EXTEND_ADDR(x) ((x) <= 0x3Fu) + +/*!< Parameter valid check for get flag type */ +#define IS_VALID_GET_FLAG_TYPE(x) \ +( (QspiFlagBusBusy == (x)) || \ + (QspiFlagXipMode == (x)) || \ + (QspiFlagRomAccessError == (x)) || \ + (QspiFlagPrefetchBufferFull == (x)) || \ + (QspiFlagPrefetchStop == (x))) + +/*!< Parameter valid check for clear flag type */ +#define IS_VALID_CLEAR_FLAG_TYPE(x) (QspiFlagRomAccessError == (x)) + +/*!< QSPI registers reset value */ +#define QSPI_REG_CR_RESET_VALUE (0x003F0000ul) +#define QSPI_REG_CSCR_RESET_VALUE (0x0000000Ful) +#define QSPI_REG_FCR_RESET_VALUE (0x000080B3ul) +#define QSPI_REG_SR_RESET_VALUE (0x00008000ul) +#define QSPI_REG_CCMD_RESET_VALUE (0x00000000ul) +#define QSPI_REG_XCMD_RESET_VALUE (0x000000FFul) +#define QSPI_REG_EXAR_RESET_VALUE (0x00000000ul) +#define QSPI_REG_SR2_RESET_VALUE (0x00000000ul) +#define QSPI_REG_DCOM_RESET_VALUE (0x00000000ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize QSPI unit + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_DeInit(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR = QSPI_REG_CR_RESET_VALUE; + if (1u == M4_QSPI->SR_f.RAER) + { + M4_QSPI->SR2_f.RAERCLR = 1u; + } + M4_QSPI->CSCR = QSPI_REG_CSCR_RESET_VALUE; + M4_QSPI->FCR = QSPI_REG_FCR_RESET_VALUE; + M4_QSPI->EXAR = QSPI_REG_EXAR_RESET_VALUE; + M4_QSPI->SR = QSPI_REG_SR_RESET_VALUE; + M4_QSPI->CCMD = QSPI_REG_CCMD_RESET_VALUE; + M4_QSPI->XCMD = QSPI_REG_XCMD_RESET_VALUE; + M4_QSPI->DCOM = QSPI_REG_DCOM_RESET_VALUE; + M4_QSPI->SR2 = QSPI_REG_SR2_RESET_VALUE; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize QSPI unit + ** + ** \param [in] pstcQspiInitCfg Pointer to qspi configuration + ** \arg See the struct #stc_qspi_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcQspiInitCfg) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CLK_DIV(pstcQspiInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_SPI_MODE(pstcQspiInitCfg->enSpiMode)); + DDL_ASSERT(IS_VALID_BUS_COMM_MODE(pstcQspiInitCfg->enBusCommMode)); + DDL_ASSERT(IS_VALID_PREFETCH_STOP_LOCATION(pstcQspiInitCfg->enPrefetchMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enPrefetchFuncEn)); + DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enReceProtocol)); + DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol)); + DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol)); + DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcQspiInitCfg->stcCommProtocol.enReadMode)); + DDL_ASSERT(IS_VALID_QSSN_VALID_EXTEND_TIME(pstcQspiInitCfg->enQssnValidExtendTime)); + DDL_ASSERT(IS_VALID_QSSN_INTERVAL_TIME(pstcQspiInitCfg->enQssnIntervalTime)); + DDL_ASSERT(IS_VALID_QSCK_DUTY_CORR(pstcQspiInitCfg->enQsckDutyCorr)); + DDL_ASSERT(IS_VALID_VIRTUAL_CYCLES(pstcQspiInitCfg->enVirtualPeriod)); + DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(pstcQspiInitCfg->enWpPinLevel)); + DDL_ASSERT(IS_VALID_QSSN_SETUP_DELAY(pstcQspiInitCfg->enQssnSetupDelayTime)); + DDL_ASSERT(IS_VALID_QSSN_HOLD_TIME(pstcQspiInitCfg->enQssnHoldDelayTime)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcQspiInitCfg->enFourByteAddrReadEn)); + DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(pstcQspiInitCfg->enAddrWidth)); + + /* Configure control register */ + M4_QSPI->CR_f.DIV = pstcQspiInitCfg->enClkDiv; + M4_QSPI->CR_f.SPIMD3 = pstcQspiInitCfg->enSpiMode; + M4_QSPI->CR_f.PFE = pstcQspiInitCfg->enPrefetchFuncEn; + M4_QSPI->CR_f.PFSAE = pstcQspiInitCfg->enPrefetchMode; + M4_QSPI->CR_f.MDSEL = pstcQspiInitCfg->stcCommProtocol.enReadMode; + + /* Custom read mode */ + if ((QspiReadModeCustomFast == pstcQspiInitCfg->stcCommProtocol.enReadMode) || + (QspiReadModeCustomStandard == pstcQspiInitCfg->stcCommProtocol.enReadMode)) + { + M4_QSPI->CR_f.IPRSL = pstcQspiInitCfg->stcCommProtocol.enTransInstrProtocol; + M4_QSPI->CR_f.APRSL = pstcQspiInitCfg->stcCommProtocol.enTransAddrProtocol; + M4_QSPI->CR_f.DPRSL = pstcQspiInitCfg->stcCommProtocol.enReceProtocol; + } + else + { + M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi; + } + + /* Configure chip select control register */ + M4_QSPI->CSCR_f.SSNW = pstcQspiInitCfg->enQssnValidExtendTime; + M4_QSPI->CSCR_f.SSHW = pstcQspiInitCfg->enQssnIntervalTime; + + /* Configure format control register */ + if (((pstcQspiInitCfg->enClkDiv % 2) != 0) && + (pstcQspiInitCfg->enQsckDutyCorr != QspiQsckDutyCorrNot)) + { + M4_QSPI->FCR_f.DUTY = QspiQsckDutyCorrNot; + } + else + { + M4_QSPI->FCR_f.DUTY = pstcQspiInitCfg->enQsckDutyCorr; + } + M4_QSPI->FCR_f.DMCYCN = pstcQspiInitCfg->enVirtualPeriod; + M4_QSPI->FCR_f.WPOL = pstcQspiInitCfg->enWpPinLevel; + M4_QSPI->FCR_f.SSNLD = pstcQspiInitCfg->enQssnSetupDelayTime; + M4_QSPI->FCR_f.SSNHD = pstcQspiInitCfg->enQssnHoldDelayTime; + M4_QSPI->FCR_f.FOUR_BIC = pstcQspiInitCfg->enFourByteAddrReadEn; + M4_QSPI->FCR_f.AWSL = pstcQspiInitCfg->enAddrWidth; + M4_QSPI->CR_f.DCOME = pstcQspiInitCfg->enBusCommMode; + + /* Configure ROM access instruction */ + M4_QSPI->CCMD = pstcQspiInitCfg->u8RomAccessInstr; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Config communication protocol structure + ** + ** \param [in] pstcCommProtocol Pointer to qspi communication protocol configuration + ** \arg See the struct #stc_qspi_comm_protocol_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol) +{ + en_result_t enRet = Ok; + + if (NULL == pstcCommProtocol) + { + enRet = Error; + } + else + { + DDL_ASSERT(IS_VALID_RECE_DATA_PROTOCOL(pstcCommProtocol->enReceProtocol)); + DDL_ASSERT(IS_VALID_TRANS_ADDR_PROTOCOL(pstcCommProtocol->enTransAddrProtocol)); + DDL_ASSERT(IS_VALID_TRANS_INSTRUCT_PROTOCOL(pstcCommProtocol->enTransInstrProtocol)); + DDL_ASSERT(IS_VALID_INTERFACE_READ_MODE(pstcCommProtocol->enReadMode)); + + M4_QSPI->CR_f.MDSEL = pstcCommProtocol->enReadMode; + /* Custom read mode */ + if ((QspiReadModeCustomFast == pstcCommProtocol->enReadMode) || + (QspiReadModeCustomStandard == pstcCommProtocol->enReadMode)) + { + M4_QSPI->CR_f.IPRSL = pstcCommProtocol->enTransInstrProtocol; + M4_QSPI->CR_f.APRSL = pstcCommProtocol->enTransAddrProtocol; + M4_QSPI->CR_f.DPRSL = pstcCommProtocol->enReceProtocol; + } + else + { + M4_QSPI->CR_f.IPRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.APRSL = QspiProtocolExtendSpi; + M4_QSPI->CR_f.DPRSL = QspiProtocolExtendSpi; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable prefetch function + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable prefetch function + ** \arg Enable Enable prefetch function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_QSPI->CR_f.PFE = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set clock division + ** + ** \param [in] enClkDiv Clock division + ** \arg QspiHclkDiv2 Clock source: HCLK/2 + ** \arg QspiHclkDiv3 Clock source: HCLK/3 + ** \arg QspiHclkDiv4 Clock source: HCLK/4 + ** \arg QspiHclkDiv5 Clock source: HCLK/5 + ** \arg QspiHclkDiv6 Clock source: HCLK/6 + ** \arg QspiHclkDiv7 Clock source: HCLK/7 + ** \arg QspiHclkDiv8 Clock source: HCLK/8 + ** \arg QspiHclkDiv9 Clock source: HCLK/9 + ** \arg QspiHclkDiv10 Clock source: HCLK/10 + ** \arg QspiHclkDiv11 Clock source: HCLK/11 + ** \arg QspiHclkDiv12 Clock source: HCLK/12 + ** \arg QspiHclkDiv13 Clock source: HCLK/13 + ** \arg QspiHclkDiv14 Clock source: HCLK/14 + ** \arg QspiHclkDiv15 Clock source: HCLK/15 + ** \arg QspiHclkDiv16 Clock source: HCLK/16 + ** \arg QspiHclkDiv17 Clock source: HCLK/17 + ** \arg QspiHclkDiv18 Clock source: HCLK/18 + ** \arg QspiHclkDiv19 Clock source: HCLK/19 + ** \arg QspiHclkDiv20 Clock source: HCLK/20 + ** \arg QspiHclkDiv21 Clock source: HCLK/21 + ** \arg QspiHclkDiv22 Clock source: HCLK/22 + ** \arg QspiHclkDiv23 Clock source: HCLK/23 + ** \arg QspiHclkDiv24 Clock source: HCLK/24 + ** \arg QspiHclkDiv25 Clock source: HCLK/25 + ** \arg QspiHclkDiv26 Clock source: HCLK/26 + ** \arg QspiHclkDiv27 Clock source: HCLK/27 + ** \arg QspiHclkDiv28 Clock source: HCLK/28 + ** \arg QspiHclkDiv29 Clock source: HCLK/29 + ** \arg QspiHclkDiv30 Clock source: HCLK/30 + ** \arg QspiHclkDiv31 Clock source: HCLK/31 + ** \arg QspiHclkDiv32 Clock source: HCLK/32 + ** \arg QspiHclkDiv33 Clock source: HCLK/33 + ** \arg QspiHclkDiv34 Clock source: HCLK/34 + ** \arg QspiHclkDiv35 Clock source: HCLK/35 + ** \arg QspiHclkDiv36 Clock source: HCLK/36 + ** \arg QspiHclkDiv37 Clock source: HCLK/37 + ** \arg QspiHclkDiv38 Clock source: HCLK/38 + ** \arg QspiHclkDiv39 Clock source: HCLK/39 + ** \arg QspiHclkDiv40 Clock source: HCLK/40 + ** \arg QspiHclkDiv41 Clock source: HCLK/41 + ** \arg QspiHclkDiv42 Clock source: HCLK/42 + ** \arg QspiHclkDiv43 Clock source: HCLK/43 + ** \arg QspiHclkDiv44 Clock source: HCLK/44 + ** \arg QspiHclkDiv45 Clock source: HCLK/45 + ** \arg QspiHclkDiv46 Clock source: HCLK/46 + ** \arg QspiHclkDiv47 Clock source: HCLK/47 + ** \arg QspiHclkDiv48 Clock source: HCLK/48 + ** \arg QspiHclkDiv49 Clock source: HCLK/49 + ** \arg QspiHclkDiv50 Clock source: HCLK/50 + ** \arg QspiHclkDiv51 Clock source: HCLK/51 + ** \arg QspiHclkDiv52 Clock source: HCLK/52 + ** \arg QspiHclkDiv53 Clock source: HCLK/53 + ** \arg QspiHclkDiv54 Clock source: HCLK/54 + ** \arg QspiHclkDiv55 Clock source: HCLK/55 + ** \arg QspiHclkDiv56 Clock source: HCLK/56 + ** \arg QspiHclkDiv57 Clock source: HCLK/57 + ** \arg QspiHclkDiv58 Clock source: HCLK/58 + ** \arg QspiHclkDiv59 Clock source: HCLK/59 + ** \arg QspiHclkDiv60 Clock source: HCLK/60 + ** \arg QspiHclkDiv61 Clock source: HCLK/61 + ** \arg QspiHclkDiv62 Clock source: HCLK/62 + ** \arg QspiHclkDiv63 Clock source: HCLK/63 + ** \arg QspiHclkDiv64 Clock source: HCLK/64 + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv)); + + M4_QSPI->CR_f.DIV = enClkDiv; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set WP Pin level + ** + ** \param [in] enWpLevel WP pin level + ** \arg QspiWpPinOutputLow WP pin(QIO2) output low level + ** \arg QspiWpPinOutputHigh WP pin(QIO2) output high level + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_WP_OUTPUT_LEVEL(enWpLevel)); + + M4_QSPI->FCR_f.WPOL = enWpLevel; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set communication address width + ** + ** \param [in] enAddrWidth Communication address width + ** \arg QspiAddressByteOne One byte address + ** \arg QspiAddressByteTwo Two byte address + ** \arg QspiAddressByteThree Three byte address + ** \arg QspiAddressByteFour Four byte address + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_INTERFACE_ADDR_WIDTH(enAddrWidth)); + + M4_QSPI->FCR_f.AWSL = enAddrWidth; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set extend address value + ** + ** \param [in] u8Addr Extend address value + ** \arg 0~0x3F + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetExtendAddress(uint8_t u8Addr) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_SET_EXTEND_ADDR(u8Addr)); + + M4_QSPI->EXAR_f.EXADR = u8Addr; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set rom access instruction + ** + ** \param [in] u8Instr Rom access instruction + ** \arg 0~0xFF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr) +{ + en_result_t enRet = Ok; + + M4_QSPI->CCMD = u8Instr; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write direct communication value + ** + ** \param [in] u8Val Direct communication value + ** \arg 0~0xFF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val) +{ + en_result_t enRet = Ok; + + M4_QSPI->DCOM = u8Val; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read direct communication value + ** + ** \param [in] None + ** + ** \retval uint8_t Direct communication read value + ** + ******************************************************************************/ +uint8_t QSPI_ReadDirectCommValue(void) +{ + return ((uint8_t)M4_QSPI->DCOM); +} + +/** + ******************************************************************************* + ** \brief Enable or disable xip mode + ** + ** \param [in] u8Instr Enable or disable xip mode instruction + ** \arg 0~0xFF + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable xip mode + ** \arg Enable Enable xip mode + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_QSPI->XCMD = u8Instr; + if (Enable == enNewSta) + { + M4_QSPI->CR_f.XIPE = 1u; + } + else + { + M4_QSPI->CR_f.XIPE = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enter direct communication mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ** \note If you are in XIP mode, you need to exit XIP mode and then start direct communication mode. + ** + ******************************************************************************/ +en_result_t QSPI_EnterDirectCommMode(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR_f.DCOME = 1u; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Exit direct communication mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t QSPI_ExitDirectCommMode(void) +{ + en_result_t enRet = Ok; + + M4_QSPI->CR_f.DCOME = 0u; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get prefetch buffer current byte number + ** + ** \param [in] None + ** + ** \retval uint8_t Current buffer byte number + ** + ******************************************************************************/ +uint8_t QSPI_GetPrefetchBufferNum(void) +{ + return ((uint8_t)M4_QSPI->SR_f.PFNUM); +} + +/** + ******************************************************************************* + ** \brief Get flag status + ** + ** \param [in] enFlag Choose need get status's flag + ** \arg QspiFlagBusBusy QSPI bus work status flag in direct communication mode + ** \arg QspiFlagXipMode XIP mode status signal + ** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode + ** \arg QspiFlagPrefetchBufferFull Prefetch buffer area status signal + ** \arg QspiFlagPrefetchStop Prefetch action status signal + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + DDL_ASSERT(IS_VALID_GET_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case QspiFlagBusBusy: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.BUSY; + break; + case QspiFlagXipMode: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.XIPF; + break; + case QspiFlagRomAccessError: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.RAER; + break; + case QspiFlagPrefetchBufferFull: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFFUL; + break; + case QspiFlagPrefetchStop: + enFlagSta = (en_flag_status_t)M4_QSPI->SR_f.PFAN; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear flag status + ** + ** \param [in] enFlag Choose need get status's flag + ** \arg QspiFlagRomAccessError Trigger rom access error flag in direct communication mode + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter Parameter error + ** + ******************************************************************************/ +en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + if (QspiFlagRomAccessError == enFlag) + { + M4_QSPI->SR2_f.RAERCLR = 1u; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +//@} // QspiGroup + +#endif /* DDL_QSPI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rmu.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rmu.c new file mode 100644 index 0000000000..301f462f9f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rmu.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rmu.c + ** + ** A detailed description is available at + ** @link RmuGroup RMU description @endlink + ** + ** - 2018-10-28 CDT First version for Device Driver Library of RMU. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_rmu.h" +#include "hc32f460_utility.h" + +#if (DDL_RMU_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup RmuGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define ENABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa502u) +#define DISABLE_RMU_REG_WRITE() (M4_SYSREG->PWR_FPRC = 0xa500u) + +#define RMU_FLAG_TIM ((uint16_t)0x1000u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Get the chip reset cause. + ** + ** \param [in] pstcData Pointer to return reset cause structure. + ** + ** \retval Ok Get successfully. + ** + ******************************************************************************/ +en_result_t RMU_GetResetCause(stc_rmu_rstcause_t *pstcData) +{ + uint16_t u16RstCause = 0u; + stc_sysreg_rmu_rstf0_field_t *RMU_RSTF0_f = NULL; + + if(NULL == pstcData) + { + return ErrorInvalidParameter; + } + + u16RstCause = M4_SYSREG->RMU_RSTF0; + RMU_RSTF0_f = (stc_sysreg_rmu_rstf0_field_t *)(&u16RstCause); + + pstcData->enMultiRst = (en_flag_status_t)(RMU_RSTF0_f->MULTIRF == 1u); + pstcData->enXtalErr = (en_flag_status_t)(RMU_RSTF0_f->XTALERF == 1u); + pstcData->enClkFreqErr = (en_flag_status_t)(RMU_RSTF0_f->CKFERF == 1u); + pstcData->enRamEcc = (en_flag_status_t)(RMU_RSTF0_f->RAECRF == 1u); + pstcData->enRamParityErr = (en_flag_status_t)(RMU_RSTF0_f->RAPERF == 1u); + pstcData->enMpuErr = (en_flag_status_t)(RMU_RSTF0_f->MPUERF == 1u); + pstcData->enSoftware = (en_flag_status_t)(RMU_RSTF0_f->SWRF == 1u); + pstcData->enPowerDown = (en_flag_status_t)(RMU_RSTF0_f->PDRF == 1u); + pstcData->enSwdt = (en_flag_status_t)(RMU_RSTF0_f->SWDRF == 1u); + pstcData->enWdt = (en_flag_status_t)(RMU_RSTF0_f->WDRF == 1u); + pstcData->enPvd2 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u); + pstcData->enPvd1 = (en_flag_status_t)(RMU_RSTF0_f->PVD2RF == 1u); + pstcData->enBrownOut = (en_flag_status_t)(RMU_RSTF0_f->BORF == 1u); + pstcData->enRstPin = (en_flag_status_t)(RMU_RSTF0_f->PINRF == 1u); + pstcData->enPowerOn = (en_flag_status_t)(RMU_RSTF0_f->PORF == 1u); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Clear the reset flag. + ** + ** \param None + ** + ** \retval Ok Clear successfully. + ** + ** \note clear reset flag should be done after read RMU_RSTF0 register. + ******************************************************************************/ +en_result_t RMU_ClrResetFlag(void) +{ + uint16_t u16status = 0u; + uint32_t u32timeout = 0u; + + ENABLE_RMU_REG_WRITE(); + + do + { + u32timeout++; + M4_SYSREG->RMU_RSTF0_f.CLRF = 1u; + u16status = M4_SYSREG->RMU_RSTF0; + }while((u32timeout != RMU_FLAG_TIM) && u16status); + + DISABLE_RMU_REG_WRITE(); + + if(u32timeout >= RMU_FLAG_TIM) + { + return ErrorTimeout; + } + + return Ok; +} + + +//@} // RmuGroup + +#endif /* DDL_RMU_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rtc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rtc.c new file mode 100644 index 0000000000..577f46fa64 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_rtc.c @@ -0,0 +1,978 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_rtc.c + ** + ** A detailed description is available at + ** @link RtcGroup Real-Time Clock description @endlink + ** + ** - 2018-11-22 CDT First version for Device Driver Library of RTC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_rtc.h" +#include "hc32f460_utility.h" + +#if (DDL_RTC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup RtcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for clock source type */ +#define IS_VALID_CLK_SOURCE_TYPE(x) \ +( (RtcClkXtal32 == (x)) || \ + (RtcClkLrc == (x))) + +/*!< Parameter valid check for period interrupt condition */ +#define IS_VALID_PERIOD_INT_CONDITION(x) \ +( (RtcPeriodIntInvalid == (x)) || \ + (RtcPeriodIntHalfSec == (x)) || \ + (RtcPeriodIntOneSec == (x)) || \ + (RtcPeriodIntOneMin == (x)) || \ + (RtcPeriodIntOneHour == (x)) || \ + (RtcPeriodIntOneDay == (x)) || \ + (RtcPeriodIntOneMon == (x))) + +/*!< Parameter valid check for time format */ +#define IS_VALID_TIME_FORMAT(x) \ +( (RtcTimeFormat12Hour == (x)) || \ + (RtcTimeFormat24Hour == (x))) + +/*!< Parameter valid check for compensation way */ +#define IS_VALID_COMPEN_WAY(x) \ +( (RtcOutputCompenDistributed == (x)) || \ + (RtcOutputCompenUniform == (x))) + +/*!< Parameter valid check for compensation value range */ +#define IS_VALID_COMPEN_VALUE_RANGE(x) ((x) <= 0x1FFu) + +/*!< Parameter valid check for data format */ +#define IS_VALID_DATA_FORMAT(x) \ +( (RtcDataFormatDec == (x)) || \ + (RtcDataFormatBcd == (x))) + +/*!< Parameter valid check for time second */ +#define IS_VALID_TIME_SECOND(x) ((x) <= 59u) + +/*!< Parameter valid check for time minute */ +#define IS_VALID_TIME_MINUTE(x) ((x) <= 59u) + +/*!< Parameter valid check for time hour */ +#define IS_VALID_TIME_HOUR12(x) (((x) >= 1u) && ((x) <= 12u)) +#define IS_VALID_TIME_HOUR24(x) ((x) <= 23u) + +/*!< Parameter valid check for date weekday */ +#define IS_VALID_DATE_WEEKDAY(x) ((x) <= 6u) + +/*!< Parameter valid check for date day */ +#define IS_VALID_DATE_DAY(x) (((x) >= 1u) && ((x) <= 31u)) + +/*!< Parameter valid check for date month */ +#define IS_VALID_DATE_MONTH(x) (((x) >= 1u) && ((x) <= 12u)) + +/*!< Parameter valid check for date year */ +#define IS_VALID_DATE_YEAR(x) ((x) <= 99u) + +/*!< Parameter valid check for hour12 am/pm */ +#define IS_VALID_HOUR12_AMPM(x) \ +( (RtcHour12Am == (x)) || \ + (RtcHour12Pm == (x))) + +/*!< Parameter valid check for alarm weekday */ +#define IS_VALID_ALARM_WEEKDAY(x) (((x) >= 1u) && ((x) <= 0x7Fu)) + +/*!< Parameter valid check for interrupt request type */ +#define IS_VALID_IRQ_TYPE(x) \ +( (RtcIrqPeriod == (x)) || \ + (RtcIrqAlarm == (x))) + +/*!< 12 hour format am/pm status bit */ +#define RTC_HOUR12_AMPM_MASK (0x20u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize RTC + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout De-Initialize timeout + ** + ******************************************************************************/ +en_result_t RTC_DeInit(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + M4_RTC->CR0_f.RESET = 0u; + /* Waiting for normal count status or end of RTC software reset */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR0_f.RESET; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + /* Initialize all RTC registers */ + M4_RTC->CR0_f.RESET = 1u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize RTC + ** + ** \param [in] pstcRtcInit Pointer to RTC init configuration + ** \arg See the struct #stc_rtc_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcInit) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CLK_SOURCE_TYPE(pstcRtcInit->enClkSource)); + DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(pstcRtcInit->enPeriodInt)); + DDL_ASSERT(IS_VALID_TIME_FORMAT(pstcRtcInit->enTimeFormat)); + DDL_ASSERT(IS_VALID_COMPEN_WAY(pstcRtcInit->enCompenWay)); + DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(pstcRtcInit->u16CompenVal)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcRtcInit->enCompenEn)); + + /* Configure clock */ + if (RtcClkLrc == pstcRtcInit->enClkSource) + { + M4_RTC->CR3_f.LRCEN = 1u; + } + M4_RTC->CR3_f.RCKSEL = pstcRtcInit->enClkSource; + + /* Configure control register */ + M4_RTC->CR1_f.PRDS = pstcRtcInit->enPeriodInt; + M4_RTC->CR1_f.AMPM = pstcRtcInit->enTimeFormat; + M4_RTC->CR1_f.ONEHZSEL = pstcRtcInit->enCompenWay; + + /* Configure clock error compensation register */ + M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)pstcRtcInit->u16CompenVal >> 8u) & 0x01u; + M4_RTC->ERRCRL = (uint32_t)pstcRtcInit->u16CompenVal & 0x00FFu; + M4_RTC->ERRCRH_f.COMPEN = pstcRtcInit->enCompenEn; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enter RTC read/write mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout Enter mode timeout + ** + ******************************************************************************/ +en_result_t RTC_EnterRwMode(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 1u; + /* Waiting for RWEN bit set */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u)); + + if (0u == u8RegSta) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Exit RTC read/write mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorTimeout Exit mode timeout + ** + ******************************************************************************/ +en_result_t RTC_ExitRwMode(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 0u; + /* Waiting for RWEN bit reset */ + u32Timeout = SystemCoreClock >> 8u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC count + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC count + ** \arg Enable Enable RTC count + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_Cmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->CR1_f.START = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief RTC period interrupt config + ** + ** \param [in] enIntType Period interrupt request type + ** \arg RtcPeriodIntInvalid Period interrupt invalid + ** \arg RtcPeriodIntHalfSec 0.5 second period interrupt + ** \arg RtcPeriodIntOneSec 1 second period interrupt + ** \arg RtcPeriodIntOneMin 1 minute period interrupt + ** \arg RtcPeriodIntOneHour 1 hour period interrupt + ** \arg RtcPeriodIntOneDay 1 day period interrupt + ** \arg RtcPeriodIntOneMon 1 month period interrupt + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_PeriodIntConfig(en_rtc_period_int_type_t enIntType) +{ + uint8_t u8RtcSta; + uint8_t u8IntSta; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PERIOD_INT_CONDITION(enIntType)); + + u8RtcSta = (uint8_t)M4_RTC->CR1_f.START; + u8IntSta = (uint8_t)M4_RTC->CR2_f.PRDIE; + /* Disable period interrupt when START=1 and PRDIE=1 */ + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.PRDIE = 0u; + } + M4_RTC->CR1_f.PRDS = enIntType; + + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.PRDIE = 1u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief RTC switch to low power mode + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidMode RTC count not start + ** \retval ErrorTimeout Switch timeout + ** + ******************************************************************************/ +en_result_t RTC_LowPowerSwitch(void) +{ + uint8_t u8RegSta; + uint32_t u32Timeout, u32TimeCnt = 0u; + en_result_t enRet = ErrorInvalidMode; + + /* Check RTC work status */ + if (0u != M4_RTC->CR1_f.START) + { + M4_RTC->CR2_f.RWREQ = 1u; + /* Waiting for RTC RWEN bit set */ + u32Timeout = SystemCoreClock / 100u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 0u)); + + if (0u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + M4_RTC->CR2_f.RWREQ = 0u; + /* Waiting for RTC RWEN bit reset */ + u32TimeCnt = 0u; + do + { + u8RegSta = (uint8_t)M4_RTC->CR2_f.RWEN; + u32TimeCnt++; + } while ((u32TimeCnt < u32Timeout) && (u8RegSta == 1u)); + + if (1u == u8RegSta) + { + enRet = ErrorTimeout; + } + else + { + enRet = Ok; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC 1hz output compensation value + ** + ** \param [in] u16CompenVal Clock compensation value + ** \arg 0~0x1FF + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_SetClkCompenValue(uint16_t u16CompenVal) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COMPEN_VALUE_RANGE(u16CompenVal)); + + M4_RTC->ERRCRH_f.COMP8 = ((uint32_t)u16CompenVal >> 8u) & 0x01u; + M4_RTC->ERRCRL = (uint32_t)u16CompenVal & 0x00FFu; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable clock compensation + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC clock compensation + ** \arg Enable Enable RTC clock compensation + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_ClkCompenCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->ERRCRH_f.COMPEN = enNewSta; + + return enRet; +} + + +/** + ******************************************************************************* + ** \brief Enable or disable RTC 1hz output + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC 1hz output + ** \arg Enable Enable RTC 1hz output + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_OneHzOutputCmd(en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + M4_RTC->CR1_f.ONEHZOE = enNewSta; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC current date and time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [in] pstcRtcDateTime Pointer to RTC date and time configuration + ** \arg See the struct #stc_rtc_date_time_t + ** + ** \param [in] enUpdateDateEn The function new state(Contain year/month/day/weekday) + ** \arg Disable Disable update RTC date + ** \arg Enable Enable update RTC date + ** + ** \param [in] enUpdateTimeEn The function new state(Contain hour/minute/second) + ** \arg Disable Disable update RTC time + ** \arg Enable Enable update RTC time + ** + ** \retval Ok Process successfully done + ** \retval Error Enter or exit read/write mode failed + ** \retval ErrorInvalidParameter Parameter enUpdateDateEn or enUpdateTimeEn invalid + ** + ******************************************************************************/ +en_result_t RTC_SetDateTime(en_rtc_data_format_t enFormat, const stc_rtc_date_time_t *pstcRtcDateTime, + en_functional_state_t enUpdateDateEn, en_functional_state_t enUpdateTimeEn) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateDateEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enUpdateTimeEn)); + + /* Check update status */ + if (((Disable == enUpdateDateEn) && (Disable == enUpdateTimeEn)) || (NULL == pstcRtcDateTime)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check the date parameters */ + if (Enable == enUpdateDateEn) + { + if (RtcDataFormatDec == enFormat) + { + DDL_ASSERT(IS_VALID_DATE_YEAR(pstcRtcDateTime->u8Year)); + DDL_ASSERT(IS_VALID_DATE_MONTH(pstcRtcDateTime->u8Month)); + DDL_ASSERT(IS_VALID_DATE_DAY(pstcRtcDateTime->u8Day)); + } + else + { + DDL_ASSERT(IS_VALID_DATE_YEAR(BCD2DEC(pstcRtcDateTime->u8Year))); + DDL_ASSERT(IS_VALID_DATE_MONTH(BCD2DEC(pstcRtcDateTime->u8Month))); + DDL_ASSERT(IS_VALID_DATE_DAY(BCD2DEC(pstcRtcDateTime->u8Day))); + } + DDL_ASSERT(IS_VALID_DATE_WEEKDAY(pstcRtcDateTime->u8Weekday)); + } + /* Check the time parameters */ + if (Enable == enUpdateTimeEn) + { + if (RtcDataFormatDec == enFormat) + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcDateTime->u8Hour)); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcDateTime->u8Hour)); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcDateTime->u8Minute)); + DDL_ASSERT(IS_VALID_TIME_SECOND(pstcRtcDateTime->u8Second)); + } + else + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcDateTime->u8Hour))); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcDateTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcDateTime->u8Hour))); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcDateTime->u8Minute))); + DDL_ASSERT(IS_VALID_TIME_SECOND(BCD2DEC(pstcRtcDateTime->u8Second))); + } + } + + /* Enter read/write mode */ + if (RTC_EnterRwMode() == ErrorTimeout) + { + enRet = Error; + } + else + { + /* Update date */ + if (Enable == enUpdateDateEn) + { + if (RtcDataFormatDec == enFormat) + { + M4_RTC->YEAR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Year); + M4_RTC->MON = DEC2BCD((uint32_t)pstcRtcDateTime->u8Month); + M4_RTC->DAY = DEC2BCD((uint32_t)pstcRtcDateTime->u8Day); + } + else + { + M4_RTC->YEAR = pstcRtcDateTime->u8Year; + M4_RTC->MON = pstcRtcDateTime->u8Month; + M4_RTC->DAY = pstcRtcDateTime->u8Day; + } + M4_RTC->WEEK = pstcRtcDateTime->u8Weekday; + } + /* Update time */ + if (Enable == enUpdateTimeEn) + { + if (RtcDataFormatDec == enFormat) + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcDateTime->enAmPm)) + { + M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour) | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->HOUR = DEC2BCD((uint32_t)pstcRtcDateTime->u8Hour); + } + M4_RTC->MIN = DEC2BCD((uint32_t)pstcRtcDateTime->u8Minute); + M4_RTC->SEC = DEC2BCD((uint32_t)pstcRtcDateTime->u8Second); + } + else + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcDateTime->enAmPm)) + { + M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->HOUR = (uint32_t)pstcRtcDateTime->u8Hour; + } + M4_RTC->MIN = pstcRtcDateTime->u8Minute; + M4_RTC->SEC = pstcRtcDateTime->u8Second; + } + } + /* Exit read/write mode */ + if (RTC_ExitRwMode() == ErrorTimeout) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC current date and time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [out] pstcRtcDateTime Pointer to RTC date and time configuration + ** \arg See the struct #stc_rtc_date_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Enter or exit read/write mode failed + ** + ******************************************************************************/ +en_result_t RTC_GetDateTime(en_rtc_data_format_t enFormat, stc_rtc_date_time_t *pstcRtcDateTime) +{ + en_result_t enRet = Ok; + + if(NULL == pstcRtcDateTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + /* Enter read/write mode */ + if (RTC_EnterRwMode() == ErrorTimeout) + { + enRet = Error; + } + else + { + /* Get RTC date and time registers */ + pstcRtcDateTime->u8Year = (uint8_t)(M4_RTC->YEAR); + pstcRtcDateTime->u8Month = (uint8_t)(M4_RTC->MON); + pstcRtcDateTime->u8Day = (uint8_t)(M4_RTC->DAY); + pstcRtcDateTime->u8Weekday = (uint8_t)(M4_RTC->WEEK); + pstcRtcDateTime->u8Hour = (uint8_t)(M4_RTC->HOUR); + pstcRtcDateTime->u8Minute = (uint8_t)(M4_RTC->MIN); + pstcRtcDateTime->u8Second = (uint8_t)(M4_RTC->SEC); + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + if (RTC_HOUR12_AMPM_MASK == (pstcRtcDateTime->u8Hour & RTC_HOUR12_AMPM_MASK)) + { + pstcRtcDateTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK); + pstcRtcDateTime->enAmPm = RtcHour12Pm; + } + else + { + pstcRtcDateTime->enAmPm = RtcHour12Am; + } + } + + /* Check decimal format*/ + if (RtcDataFormatDec == enFormat) + { + pstcRtcDateTime->u8Year = BCD2DEC(pstcRtcDateTime->u8Year); + pstcRtcDateTime->u8Month = BCD2DEC(pstcRtcDateTime->u8Month); + pstcRtcDateTime->u8Day = BCD2DEC(pstcRtcDateTime->u8Day); + pstcRtcDateTime->u8Hour = BCD2DEC(pstcRtcDateTime->u8Hour); + pstcRtcDateTime->u8Minute = BCD2DEC(pstcRtcDateTime->u8Minute); + pstcRtcDateTime->u8Second = BCD2DEC(pstcRtcDateTime->u8Second); + } + + /* exit read/write mode */ + if (RTC_ExitRwMode() == ErrorTimeout) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set RTC alarm time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [in] pstcRtcAlarmTime Pointer to RTC alarm time configuration + ** \arg See the struct #stc_rtc_alarm_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_SetAlarmTime(en_rtc_data_format_t enFormat, const stc_rtc_alarm_time_t *pstcRtcAlarmTime) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcAlarmTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + if (RtcDataFormatDec == enFormat) + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(pstcRtcAlarmTime->u8Hour)); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(pstcRtcAlarmTime->u8Hour)); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(pstcRtcAlarmTime->u8Minute)); + } + else + { + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + DDL_ASSERT(IS_VALID_TIME_HOUR12(BCD2DEC(pstcRtcAlarmTime->u8Hour))); + DDL_ASSERT(IS_VALID_HOUR12_AMPM(pstcRtcAlarmTime->enAmPm)); + } + else + { + DDL_ASSERT(IS_VALID_TIME_HOUR24(BCD2DEC(pstcRtcAlarmTime->u8Hour))); + } + DDL_ASSERT(IS_VALID_TIME_MINUTE(BCD2DEC(pstcRtcAlarmTime->u8Minute))); + } + DDL_ASSERT(IS_VALID_ALARM_WEEKDAY(pstcRtcAlarmTime->u8Weekday)); + + /* Configure alarm registers */ + if (RtcDataFormatDec == enFormat) + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcAlarmTime->enAmPm)) + { + M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour) | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->ALMHOUR = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Hour); + } + M4_RTC->ALMMIN = DEC2BCD((uint32_t)pstcRtcAlarmTime->u8Minute); + } + else + { + if ((RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) && + (RtcHour12Pm == pstcRtcAlarmTime->enAmPm)) + { + M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour | RTC_HOUR12_AMPM_MASK; + } + else + { + M4_RTC->ALMHOUR = (uint32_t)pstcRtcAlarmTime->u8Hour; + } + M4_RTC->ALMMIN = pstcRtcAlarmTime->u8Minute; + } + M4_RTC->ALMWEEK = pstcRtcAlarmTime->u8Weekday; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC alarm time + ** + ** \param [in] enFormat Date and time data format + ** \arg RtcDataFormatDec Decimal format + ** \arg RtcDataFormatBcd BCD format + ** + ** \param [out] pstcRtcAlarmTime Pointer to RTC alarm time configuration + ** \arg See the struct #stc_rtc_alarm_time_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t RTC_GetAlarmTime(en_rtc_data_format_t enFormat, stc_rtc_alarm_time_t *pstcRtcAlarmTime) +{ + en_result_t enRet = Ok; + + if(NULL == pstcRtcAlarmTime) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_DATA_FORMAT(enFormat)); + + /* Get RTC date and time register */ + pstcRtcAlarmTime->u8Weekday = (uint8_t)M4_RTC->ALMWEEK; + pstcRtcAlarmTime->u8Minute = (uint8_t)M4_RTC->ALMMIN; + pstcRtcAlarmTime->u8Hour = (uint8_t)M4_RTC->ALMHOUR; + if (RtcTimeFormat12Hour == M4_RTC->CR1_f.AMPM) + { + if ((pstcRtcAlarmTime->u8Hour & RTC_HOUR12_AMPM_MASK) == RTC_HOUR12_AMPM_MASK) + { + pstcRtcAlarmTime->u8Hour &= (uint8_t)(~RTC_HOUR12_AMPM_MASK); + pstcRtcAlarmTime->enAmPm = RtcHour12Pm; + } + else + { + pstcRtcAlarmTime->enAmPm = RtcHour12Am; + } + } + + /* Check decimal format*/ + if (RtcDataFormatDec == enFormat) + { + pstcRtcAlarmTime->u8Hour = BCD2DEC(pstcRtcAlarmTime->u8Hour); + pstcRtcAlarmTime->u8Minute = BCD2DEC(pstcRtcAlarmTime->u8Minute); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC alarm function + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable RTC alarm function + ** \arg Enable Enable RTC alarm function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_AlarmCmd(en_functional_state_t enNewSta) +{ + uint8_t u8RtcSta; + uint8_t u8IntSta; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u8RtcSta = (uint8_t)M4_RTC->CR1_f.START; + u8IntSta = (uint8_t)M4_RTC->CR2_f.ALMIE; + /* Disable alarm interrupt and clear alarm flag when START=1 and ALMIE=1 */ + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR2_f.ALMIE = 0u; + } + M4_RTC->CR2_f.ALME = enNewSta; + + if ((1u == u8IntSta) && (1u == u8RtcSta)) + { + M4_RTC->CR1_f.ALMFCLR = 0u; + M4_RTC->CR2_f.ALMIE = u8IntSta; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable RTC interrupt request + ** + ** \param [in] enIrq RTC interrupt request type + ** \arg RtcIrqPeriod Period count interrupt request + ** \arg RtcIrqAlarm Alarm interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_IrqCmd(en_rtc_irq_type_t enIrq, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + /* enable/disable interrupt */ + switch (enIrq) + { + case RtcIrqPeriod: + M4_RTC->CR2_f.PRDIE = enNewSta; + break; + case RtcIrqAlarm: + M4_RTC->CR2_f.ALMIE = enNewSta; + break; + default: + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get RTC Alarm flag status + ** + ** \param [in] None + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t RTC_GetAlarmFlag(void) +{ + return (en_flag_status_t)(M4_RTC->CR2_f.ALMF); +} + +/** + ******************************************************************************* + ** \brief Clear RTC Alarm flag status + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t RTC_ClearAlarmFlag(void) +{ + en_result_t enRet = Ok; + + M4_RTC->CR1_f.ALMFCLR = 0u; + + return enRet; +} + +//@} // RtcGroup + +#endif /* DDL_RTC_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sdioc.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sdioc.c new file mode 100644 index 0000000000..4a70252039 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sdioc.c @@ -0,0 +1,2222 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sdioc.c + ** + ** A detailed description is available at + ** @link SdiocGroup SDIOC description @endlink + ** + ** - 2018-11-11 CDT First version for Device Driver Library of SDIOC. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_sdioc.h" +#include "hc32f460_utility.h" + +#if (DDL_SDIOC_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SdiocGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SDIOC internal data + ** + ******************************************************************************/ +typedef struct stc_sdioc_intern_data +{ + stc_sdioc_normal_irq_cb_t stcNormalIrqCb; ///< Normal irq callback function structure + + stc_sdioc_error_irq_cb_t stcErrorIrqCb; ///< Error irq callback function structure +} stc_sdioc_intern_data_t; + +/** + ******************************************************************************* + ** \brief SDIOC instance data + ** + ******************************************************************************/ +typedef struct stc_sdioc_instance_data +{ + const M4_SDIOC_TypeDef *SDIOCx; ///< pointer to registers of an instance + + stc_sdioc_intern_data_t stcInternData; ///< module internal data of instance +} stc_sdioc_instance_data_t; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for SDIOC Instances. */ +#define IS_VALID_SDIOC(__SDIOCx__) \ +( (M4_SDIOC1 == (__SDIOCx__)) || \ + (M4_SDIOC2 == (__SDIOCx__))) + +/*!< Parameter valid check for SDIOC mode. */ +#define IS_VALID_SDIOC_MODE(x) \ +( (SdiocModeSD == (x)) || \ + (SdiocModeMMC == (x))) + +/*!< Parameter valid check for SDIOC Response Register. */ +#define IS_VALID_SDIOC_RESP(x) \ +( (SdiocRegResp01 == (x)) || \ + (SdiocRegResp23 == (x)) || \ + (SdiocRegResp45 == (x)) || \ + (SdiocRegResp67 == (x))) + +/*!< Parameter valid check for SDIOC bus width. */ +#define IS_VALID_SDIOC_BUS_WIDTH(x) \ +( (SdiocBusWidth1Bit == (x)) || \ + (SdiocBusWidth4Bit == (x)) || \ + (SdiocBusWidth8Bit == (x))) + +/*!< Parameter valid check for SDIOC speed mode. */ +#define IS_VALID_SDIOC_SPEED_MODE(x) \ +( (SdiocHighSpeedMode == (x)) || \ + (SdiocNormalSpeedMode == (x))) + +/*!< Parameter valid check for SDIOC Clock division. */ +#define IS_VALID_SDIOC_CLK_DIV(x) \ +( (SdiocClkDiv_1 == (x)) || \ + (SdiocClkDiv_2 == (x)) || \ + (SdiocClkDiv_4 == (x)) || \ + (SdiocClkDiv_8 == (x)) || \ + (SdiocClkDiv_16 == (x)) || \ + (SdiocClkDiv_32 == (x)) || \ + (SdiocClkDiv_64 == (x)) || \ + (SdiocClkDiv_128 == (x)) || \ + (SdiocClkDiv_256 == (x))) + +/*!< Parameter valid check for SDIOC command type. */ +#define IS_VALID_SDIOC_CMD_TYPE(x) \ +( (SdiocCmdAbort == (x)) || \ + (SdiocCmdResume == (x)) || \ + (SdiocCmdNormal == (x)) || \ + (SdiocCmdSuspend == (x))) + +/*!< Parameter valid check for SDIOC data transfer direction. */ +#define IS_VALID_SDIOC_TRANSFER_DIR(x) \ +( (SdiocTransferToCard == (x)) || \ + (SdiocTransferToHost == (x))) + +/*!< Parameter valid check for SDIOC software reset type. */ +#define IS_VALID_SDIOC_SWRESETTYPE(x) \ +( (SdiocSwResetAll == (x)) || \ + (SdiocSwResetCmdLine == (x)) || \ + (SdiocSwResetDatLine == (x))) + +/*!< Parameter valid check for SDIOC data transfer mode. */ +#define IS_VALID_SDIOC_TRANSFER_MODE(x) \ +( (SdiocTransferSingle == (x)) || \ + (SdiocTransferInfinite == (x)) || \ + (SdiocTransferMultiple == (x)) || \ + (SdiocTransferStopMultiple == (x))) + +/*!< Parameter valid check for SDIOC data timeout. */ +#define IS_VALID_SDIOC_DATA_TIMEOUT(x) \ +( (SdiocDtoSdclk_2_13 == (x)) || \ + (SdiocDtoSdclk_2_14 == (x)) || \ + (SdiocDtoSdclk_2_15 == (x)) || \ + (SdiocDtoSdclk_2_16 == (x)) || \ + (SdiocDtoSdclk_2_17 == (x)) || \ + (SdiocDtoSdclk_2_18 == (x)) || \ + (SdiocDtoSdclk_2_19 == (x)) || \ + (SdiocDtoSdclk_2_20 == (x)) || \ + (SdiocDtoSdclk_2_21 == (x)) || \ + (SdiocDtoSdclk_2_22 == (x)) || \ + (SdiocDtoSdclk_2_23 == (x)) || \ + (SdiocDtoSdclk_2_24 == (x)) || \ + (SdiocDtoSdclk_2_25 == (x)) || \ + (SdiocDtoSdclk_2_26 == (x)) || \ + (SdiocDtoSdclk_2_27 == (x))) + +/*!< Parameter valid check for SDIOC Response type name. */ +#define IS_VALID_SDIOC_RESP_TYPE_NAME(x) \ +( (SdiocCmdRspR1 == (x)) || \ + (SdiocCmdRspR1b == (x)) || \ + (SdiocCmdRspR2 == (x)) || \ + (SdiocCmdRspR3 == (x)) || \ + (SdiocCmdRspR4 == (x)) || \ + (SdiocCmdRspR5 == (x)) || \ + (SdiocCmdRspR5b == (x)) || \ + (SdiocCmdRspR6 == (x)) || \ + (SdiocCmdRspR7 == (x)) || \ + (SdiocCmdNoRsp == (x))) + +/*!< Parameter valid check for SDIOC data timeout. */ +#define IS_VALID_SDIOC_HOST_STATUS(x) \ +( (SdiocCmdPinLvl == (x)) || \ + (SdiocData0PinLvl == (x)) || \ + (SdiocData1PinLvl == (x)) || \ + (SdiocData2PinLvl == (x)) || \ + (SdiocData3PinLvl == (x)) || \ + (SdiocCardInserted == (x)) || \ + (SdiocDataLineActive == (x)) || \ + (SdiocCardStateStable == (x)) || \ + (SdiocBufferReadEnble == (x)) || \ + (SdiocBufferWriteEnble == (x)) || \ + (SdiocCardDetectPinLvl == (x)) || \ + (SdiocCommandInhibitCmd == (x)) || \ + (SdiocWriteProtectPinLvl == (x)) || \ + (SdiocCommandInhibitData == (x)) || \ + (SdiocReadTransferActive == (x)) || \ + (SdiocWriteTransferActive == (x))) + +/*!< Parameter valid check for SDIOC normal interrupt. */ +#define IS_VALID_SDIOC_NOR_INT(x) \ +( (SdiocCardInt == (x)) || \ + (SdiocErrorInt == (x)) || \ + (SdiocCardRemoval == (x)) || \ + (SdiocBlockGapEvent == (x)) || \ + (SdiocCardInsertedInt == (x)) || \ + (SdiocCommandComplete == (x)) || \ + (SdiocBufferReadReady == (x)) || \ + (SdiocBufferWriteReady == (x)) || \ + (SdiocTransferComplete == (x))) + +/*!< Parameter valid check for SDIOC error interrupt. */ +#define IS_VALID_SDIOC_ERR_INT(x) \ +( (SdiocCmdCrcErr == (x)) || \ + (SdiocDataCrcErr == (x)) || \ + (SdiocCmdIndexErr == (x)) || \ + (SdiocCmdEndBitErr == (x)) || \ + (SdiocAutoCmd12Err == (x)) || \ + (SdiocCmdTimeoutErr == (x)) || \ + (SdiocDataEndBitErr == (x)) || \ + (SdiocDataTimeoutErr == (x))) + +/*!< Parameter valid check for SDIOC auto CMD12 error status. */ +#define IS_VALID_SDIOC_AUTOCMD_ERR(x) \ +( (SdiocCmdNotIssuedErr == (x)) || \ + (SdiocAutoCmd12CrcErr == (x)) || \ + (SdiocAutoCmd12Timeout == (x)) || \ + (SdiocAutoCmd12IndexErr == (x)) || \ + (SdiocAutoCmd12EndBitErr == (x)) || \ + (SdiocAutoCmd12NotExecuted == (x))) + +/*!< Parameter valid check for SDIOC detect card signal. */ +#define IS_VALID_SDIOC_DETECT_SIG(x) \ +( (SdiocSdcdPinLevel == (x)) || \ + (SdiocCardDetectTestLevel == (x))) + +/*!< Parameter valid check for SDIOC data block count value. */ +#define IS_VALID_SDIOC_BLKCNT(x) ((x) != 0u) + +/*!< Parameter valid check for SDIOC data block size value. */ +#define IS_VALID_SDIOC_BLKSIZE(x) (!((x) & 0xF000ul)) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_SDIOC_CMD_VAL(x) (!(0xC0u & (x))) + +/*!< Parameter valid check for buffer address. */ +#define IS_VALID_TRANSFER_BUF_ALIGN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< Parameter valid check for SDIOC command value. */ +#define IS_VALID_TRANSFER_BUF_LEN(x) (!((SDIOC_BUF_ALIGN_SIZE-1ul) & ((uint32_t)(x)))) + +/*!< SDIOC unit max count value. */ +#define SDIOC_UNIT_MAX_CNT (ARRAY_SZ(m_astcSdiocInstanceDataLut)) + +/*!< SDIOC default sdclk frequency. */ +#define SDIOC_SDCLK_400K (400000ul) + +/*!< Get the specified register address of the specified SDIOC unit */ +#define SDIOC_ARG01(__SDIOCx__) ((uint32_t)(&((__SDIOCx__)->ARG0))) +#define SDIOC_BUF01(__SDIOCx__) ((uint32_t)(&((__SDIOCx__)->BUF0))) +#define SDIOC_RESPx(__SDIOCx__, RESP_REG) ((uint32_t)(&((__SDIOCx__)->RESP0)) + (uint32_t)(RESP_REG)) + +/* SDIOC buffer align size */ +#define SDIOC_BUF_ALIGN_SIZE (4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_sdioc_clk_div_t SdiocGetClkDiv(uint32_t u32Exclk, + uint32_t u32SdiocClkFreq); +static stc_sdioc_intern_data_t* SdiocGetInternDataPtr(const M4_SDIOC_TypeDef *SDIOCx); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Get SDIOC clock division. + ** + ** \param [in] u32Exclk Exclk frequency + ** \param [in] u32ClkFreq SDIOC clock frequency + ** + ** \retval SdiocClkDiv_1 EXCLK/1 + ** \retval SdiocClkDiv_2 EXCLK/2 + ** \retval SdiocClkDiv_4 EXCLK/4 + ** \retval SdiocClkDiv_8 EXCLK/8 + ** \retval SdiocClkDiv_16 EXCLK/16 + ** \retval SdiocClkDiv_32 EXCLK/32 + ** \retval SdiocClkDiv_64 EXCLK/64 + ** \retval SdiocClkDiv_128 EXCLK/128 + ** \retval SdiocClkDiv_256 EXCLK/256 + ** + ******************************************************************************/ +static en_sdioc_clk_div_t SdiocGetClkDiv(uint32_t u32Exclk, + uint32_t u32ClkFreq) +{ + uint32_t u32SdClkDiv = 0ul; + en_sdioc_clk_div_t enClockDiv = SdiocClkDiv_256; + + if(0ul != u32ClkFreq) + { + u32SdClkDiv = u32Exclk / u32ClkFreq; + if (u32Exclk % u32ClkFreq) + { + u32SdClkDiv++; + } + + if ((128ul < u32SdClkDiv) && (u32SdClkDiv <= 256ul)) + { + enClockDiv = SdiocClkDiv_256; + } + else if ((64ul < u32SdClkDiv) && (u32SdClkDiv <= 128ul)) + { + enClockDiv = SdiocClkDiv_128; + } + else if ((32ul < u32SdClkDiv) && (u32SdClkDiv <= 64ul)) + { + enClockDiv = SdiocClkDiv_64; + } + else if ((16ul < u32SdClkDiv) && (u32SdClkDiv <= 32ul)) + { + enClockDiv = SdiocClkDiv_32; + } + else if ((16ul < u32SdClkDiv) && (u32SdClkDiv <= 32ul)) + { + enClockDiv = SdiocClkDiv_32; + } + else if ((8ul < u32SdClkDiv) && (u32SdClkDiv <= 16ul)) + { + enClockDiv = SdiocClkDiv_16; + } + else if ((4ul < u32SdClkDiv) && (u32SdClkDiv <= 8ul)) + { + enClockDiv = SdiocClkDiv_8; + } + else if ((2ul < u32SdClkDiv) && (u32SdClkDiv <= 4ul)) + { + enClockDiv = SdiocClkDiv_4; + } + else if ((1ul < u32SdClkDiv) && (u32SdClkDiv <= 2ul)) + { + enClockDiv = SdiocClkDiv_2; + } + else + { + enClockDiv = SdiocClkDiv_1; + } + } + + return enClockDiv; +} + +/** + ******************************************************************************* + ** \brief Return the internal data for a certain SDIOC instance. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_sdioc_intern_data_t* SdiocGetInternDataPtr(const M4_SDIOC_TypeDef *SDIOCx) +{ + uint8_t i; + stc_sdioc_intern_data_t *pstcInternData = NULL; + static stc_sdioc_instance_data_t m_astcSdiocInstanceDataLut[2]; + + m_astcSdiocInstanceDataLut[0].SDIOCx = M4_SDIOC1; + m_astcSdiocInstanceDataLut[1].SDIOCx = M4_SDIOC2; + + if (NULL != SDIOCx) + { + for (i = 0u; i < SDIOC_UNIT_MAX_CNT; i++) + { + if (SDIOCx == m_astcSdiocInstanceDataLut[i].SDIOCx) + { + pstcInternData = &m_astcSdiocInstanceDataLut[i].stcInternData; + break; + } + } + } + + return pstcInternData; +} + +/** + ******************************************************************************* + ** \brief SDIOC instance interrupt service routine + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval None + ** + ******************************************************************************/ +void SDIOC_IrqHandler(M4_SDIOC_TypeDef *SDIOCx) +{ + stc_sdioc_intern_data_t *pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + + /* Check for NULL pointer */ + if (NULL != pstcSdiocInternData) + { + /**************** Normal interrupt handler ****************/ + if (1u == SDIOCx->NORINTST_f.CC) /* Command complete */ + { + SDIOCx->NORINTST_f.CC = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.TC) /* Transfer complete */ + { + SDIOCx->NORINTST_f.TC = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BGE) /* Block gap event */ + { + SDIOCx->NORINTST_f.BGE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BWR) /* Buffer write ready */ + { + SDIOCx->NORINTST_f.BWR = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.BRR) /* Buffer read ready */ + { + SDIOCx->NORINTST_f.BRR = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CIST) /* Card insertion */ + { + SDIOCx->NORINTST_f.CIST = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CRM) /* Card removal */ + { + SDIOCx->NORINTST_f.CRM = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb(); + } + } + + if (1u == SDIOCx->NORINTST_f.CINT) /* Card interrupt */ + { + SDIOCx->NORINTST_f.CINT = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb(); + } + } + + /**************** Error interrupt handler ****************/ + if (1u == SDIOCx->ERRINTST_f.CTOE) /* Command timeout error */ + { + SDIOCx->ERRINTST_f.CTOE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CCE) /* Command CRC error */ + { + SDIOCx->ERRINTST_f.CCE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CEBE) /* Command end bit error */ + { + SDIOCx->ERRINTST_f.CEBE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.CIE) /* Command index error */ + { + SDIOCx->ERRINTST_f.CIE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DTOE) /* Data timeout error */ + { + SDIOCx->ERRINTST_f.DTOE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DEBE) /* Data end bit error */ + { + SDIOCx->ERRINTST_f.DEBE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.DCE) /* Data CRC error */ + { + SDIOCx->ERRINTST_f.DCE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb(); + } + } + + if (1u == SDIOCx->ERRINTST_f.ACE) /* Auto CMD12 error */ + { + SDIOCx->ERRINTST_f.ACE = 1u; /* Clear interrupt flag */ + if (NULL != pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb(); + } + } + } +} + +/** + ******************************************************************************* + ** \brief Initializes a SDIOC. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcInitCfg Pointer to SDIOC configure structure + ** \arg This parameter detail refer @ref stc_sdioc_init_t + ** + ** \retval Ok SDIOC initialized normally + ** \retval ErrorTimeout SDIOCx reset timeout + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_init_t *pstcInitCfg) +{ + __IO uint32_t i = 0ul; + uint32_t u32Exclk = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_intern_data_t *pstcSdiocInternData = NULL; + + /* Get pointer to internal data structure. */ + pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + if (NULL != pstcSdiocInternData) /* Check for instance available or not */ + { + /* Reset all */ + SDIOCx->SFTRST_f.RSTA = 1u; + while (0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + + if (i < u32Cnt) + { + /* Get EXCLK frequency */ + u32Exclk = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.EXCKS); + + SDIOCx->CLKCON_f.FS = SdiocGetClkDiv(u32Exclk, SdiocClk400K); + SDIOCx->CLKCON_f.CE = (uint16_t)1u; + SDIOCx->CLKCON_f.ICE = (uint16_t)1u; + SDIOCx->PWRCON_f.PWON = (uint8_t)1u; /* Power on */ + + /* Enable all status */ + SDIOCx->ERRINTST = (uint16_t)0x017Fu; /* Clear Error interrupt status */ + SDIOCx->ERRINTSTEN = (uint16_t)0x017Fu; /* Enable Error interrupt status */ + SDIOCx->NORINTST = (uint16_t)0x00F7u; /* Clear Normal interrupt status */ + SDIOCx->NORINTSTEN = (uint16_t)0x01F7u; /* Enable Normal interrupt status */ + + /* Enable normal interrupt signal */ + if (NULL != pstcInitCfg) + { + if (NULL != pstcInitCfg->pstcNormalIrqEn) + { + SDIOCx->NORINTSGEN = pstcInitCfg->pstcNormalIrqEn->u16NormalIntsgEn; + } + + /* Set normal interrupt callback functions */ + if (NULL != pstcInitCfg->pstcNormalIrqCb) + { + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCommandCompleteIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnTransferCompleteIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBlockGapIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBufferWriteReadyIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnBufferReadReadyIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardInsertIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardRemovalIrqCb; + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb = pstcInitCfg->pstcNormalIrqCb->pfnCardIrqCb; + } + + /* Enable error interrupt signal */ + if (NULL != pstcInitCfg->pstcErrorIrqEn) + { + SDIOCx->ERRINTSGEN = pstcInitCfg->pstcErrorIrqEn->u16ErrorIntsgEn; + } + + /* Set error interrupt callback functions */ + if (NULL != pstcInitCfg->pstcErrorIrqCb) + { + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdTimeoutErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdCrcErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdEndBitErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnCmdIndexErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataTimeoutErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataEndBitErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnDataCrcErrIrqCb; + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb = pstcInitCfg->pstcErrorIrqCb->pfnAutoCmdErrIrqCb; + } + } + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes the specified SDIOC unit. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorTimeout SDIOCx reset timeout. + ** \retval ErrorInvalidParameter SDIOCx is invalid. + ** + ******************************************************************************/ +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx) +{ + __IO uint32_t i = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + stc_sdioc_intern_data_t *pstcSdiocInternData = NULL; + + /* Get pointer to internal data structure. */ + pstcSdiocInternData = SdiocGetInternDataPtr(SDIOCx); + if (NULL != pstcSdiocInternData) /* Check for instance available or not */ + { + /* Reset all */ + SDIOCx->SFTRST_f.RSTA = 1u; + while (0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + + if (i < u32Cnt) + { + /* Set normal interrupt callback functions */ + pstcSdiocInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBlockGapIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardInsertIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = NULL; + pstcSdiocInternData->stcNormalIrqCb.pfnCardIrqCb = NULL; + + /* Set error interrupt callback functions */ + pstcSdiocInternData->stcErrorIrqCb.pfnCmdTimeoutErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdCrcErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdEndBitErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnCmdIndexErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataTimeoutErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataEndBitErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnDataCrcErrIrqCb = NULL; + pstcSdiocInternData->stcErrorIrqCb.pfnAutoCmdErrIrqCb = NULL; + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + * @brief Set SDIOC mode. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enMode SDIOCx mode + * @arg SdiocModeSD: SD mode + * @arg SdiocModeMMC: MMC mode + */ +void SDIOC_SetMode(const M4_SDIOC_TypeDef *SDIOCx, en_sdioc_mode_t enMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_MODE(enMode)); + + if (M4_SDIOC1 == SDIOCx) + { + M4_PERIC->SDIOC_SYCTLREG_f.SELMMC1 = (uint32_t)enMode; + } + else + { + M4_PERIC->SDIOC_SYCTLREG_f.SELMMC2 = (uint32_t)enMode; + } +} + +/** + ******************************************************************************* + ** \brief Send SD command + ** + ** This function sends command on CMD line + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcCmdCfg Pointer to command transfer configuration structure. + ** \arg This parameter detail refer @ref stc_sdioc_cmd_cfg_t + ** + ** \retval Ok Command sent normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcCmdCfg == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_cmd_cfg_t *pstcCmdCfg) +{ + uint32_t u32Addr; + stc_sdioc_cmd_field_t stcCmdField; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for NULL pointer */ + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pstcCmdCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_CMD_VAL(pstcCmdCfg->u8CmdIndex)); + DDL_ASSERT(IS_VALID_SDIOC_CMD_TYPE(pstcCmdCfg->enCmdType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCmdCfg->enDataPresentEnable)); + DDL_ASSERT(IS_VALID_SDIOC_RESP_TYPE_NAME(pstcCmdCfg->enRspIndex)); + + enRet = Ok; + switch (pstcCmdCfg->enRspIndex) + { + case SdiocCmdNoRsp: + stcCmdField.RESTYP = SdiocResponseNoneBit; + stcCmdField.CCE = 0u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR2: + stcCmdField.RESTYP = SdiocResponse136Bit; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR3: + case SdiocCmdRspR4: + stcCmdField.RESTYP = SdiocResponse48Bit; + stcCmdField.CCE = 0u; + stcCmdField.ICE = 0u; + break; + case SdiocCmdRspR1: + case SdiocCmdRspR5: + case SdiocCmdRspR6: + case SdiocCmdRspR7: + stcCmdField.RESTYP = SdiocResponse48Bit; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 1u; + break; + case SdiocCmdRspR1b: + case SdiocCmdRspR5b: + stcCmdField.RESTYP = SdiocResponse48BitCheckBusy; + stcCmdField.CCE = 1u; + stcCmdField.ICE = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + stcCmdField.RESERVED2 = (uint16_t)0u; + stcCmdField.TYP = (uint16_t)pstcCmdCfg->enCmdType; + stcCmdField.IDX = (uint16_t)pstcCmdCfg->u8CmdIndex; + stcCmdField.DAT = (uint16_t)(pstcCmdCfg->enDataPresentEnable); + + u32Addr = SDIOC_ARG01(SDIOCx); + *(__IO uint32_t *)u32Addr = pstcCmdCfg->u32Argument; + + u32Addr = (uint32_t)&stcCmdField; + SDIOCx->CMD = *(uint16_t *)u32Addr; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the response received from the card for the last command + ** + ** This function sends command on CMD line + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enRespReg Response Specifies the SDIOC response register. + ** \arg SdiocRegResp01 Response0 and Response1 Register + ** \arg SdiocRegResp23 Response2 and Response3 Register + ** \arg SdiocRegResp45 Response4 and Response5 Register + ** \arg SdiocRegResp67 Response6 and Response7 Register + ** + ** \retval The Corresponding response register value + ** + ******************************************************************************/ +uint32_t SDIOC_GetResponse(const M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_response_reg_t enRespReg) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_RESP(enRespReg)); + + return *(__IO uint32_t *)SDIOC_RESPx(SDIOCx, enRespReg) ; +} + +/** + ******************************************************************************* + ** \brief Read data from SDIOCx data buffer + ** + ** This function reads 32-bit data from data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] au8Data Buffer which will store SDIOC_BUFFER data + ** \param [in] u32Len Data length + ** + ** \retval Ok Data is read normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pu32Data == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len) +{ + uint32_t i = 0ul; + uint32_t u32Temp = 0ul;; + __IO uint32_t *SDIO_BUF_REG = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pu8Data pointer */ + if ((NULL != au8Data) && \ + (IS_VALID_SDIOC(SDIOCx)) && \ + (IS_VALID_TRANSFER_BUF_LEN(u32Len))) + { + SDIO_BUF_REG = (__IO uint32_t *)SDIOC_BUF01(SDIOCx); + + while (i < u32Len) + { + u32Temp = *SDIO_BUF_REG; + au8Data[i++] = (uint8_t)((u32Temp >> 0ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 8ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 16ul) & 0x000000FF); + au8Data[i++] = (uint8_t)((u32Temp >> 24ul) & 0x000000FF); + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write data to SDIOCx data buffer + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] au8Data Buffer which will be wrote to SDIOC_BUFFER + ** \param [in] u32Len Data length + ** + ** \retval Ok Data is written normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pu8Data == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, + uint8_t au8Data[], + uint32_t u32Len) +{ + uint32_t i = 0ul; + uint32_t u32Temp = 0ul; + __IO uint32_t *SDIO_BUF_REG = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pu8Data pointer */ + if ((NULL != au8Data) && \ + (IS_VALID_SDIOC(SDIOCx)) && \ + (IS_VALID_TRANSFER_BUF_LEN(u32Len))) + { + SDIO_BUF_REG = (__IO uint32_t *)SDIOC_BUF01(SDIOCx); + + while (i < u32Len) + { + u32Temp = (((uint32_t)au8Data[i++]) << 0ul) & 0x000000FFul; + u32Temp += (((uint32_t)au8Data[i++]) << 8ul) & 0x0000FF00ul; + u32Temp += (((uint32_t)au8Data[i++]) << 16ul) & 0x00FF0000ul; + u32Temp += (((uint32_t)au8Data[i++]) << 24ul) & 0xFF000000ul; + + *SDIO_BUF_REG = u32Temp; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure SDIOCx data parameters + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] pstcDataCfg Pointer to SDIOC data transfer configuration structure + ** \arg This parameter detail refer @ref stc_sdioc_data_cfg_t + ** + ** \retval Ok configure normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SDIOCx is invalid + ** - pstcDataCfg == NULL + ** + ******************************************************************************/ +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, + const stc_sdioc_data_cfg_t *pstcDataCfg) +{ + uint16_t u16BlkCnt = (uint16_t)0; + uint32_t u32Addr; + stc_sdioc_transmode_field_t stcTransModeField = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx && pstcDataCfg pointer */ + if ((IS_VALID_SDIOC(SDIOCx)) && (NULL != pstcDataCfg)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_BLKCNT(pstcDataCfg->u16BlkCnt)); + DDL_ASSERT(IS_VALID_SDIOC_BLKSIZE(pstcDataCfg->u16BlkSize)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcDataCfg->enAutoCmd12Enable)); + DDL_ASSERT(IS_VALID_SDIOC_DATA_TIMEOUT(pstcDataCfg->enDataTimeOut)); + DDL_ASSERT(IS_VALID_SDIOC_TRANSFER_DIR(pstcDataCfg->enTransferDir)); + DDL_ASSERT(IS_VALID_SDIOC_TRANSFER_MODE(pstcDataCfg->enTransferMode)); + + enRet = Ok; + + switch (pstcDataCfg->enTransferMode) + { + case SdiocTransferSingle: + stcTransModeField.MULB = 0u; + stcTransModeField.BCE = 0u; + break; + case SdiocTransferInfinite: + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 0u; + break; + case SdiocTransferMultiple: + u16BlkCnt = pstcDataCfg->u16BlkCnt; + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 1u; + break; + case SdiocTransferStopMultiple: + stcTransModeField.MULB = 1u; + stcTransModeField.BCE = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + stcTransModeField.RESERVED0 = (uint16_t)0u; + stcTransModeField.DDIR = (uint16_t)(pstcDataCfg->enTransferDir); + stcTransModeField.ATCEN = (uint16_t)(pstcDataCfg->enAutoCmd12Enable); + + /* Set the SDIOC Data Transfer Timeout value */ + SDIOCx->TOUTCON = (uint8_t)(pstcDataCfg->enDataTimeOut); + /* Set the SDIOC Block Count value */ + SDIOCx->BLKCNT = u16BlkCnt; + /* Set the SDIOC Block Size value */ + SDIOCx->BLKSIZE = pstcDataCfg->u16BlkSize; + /* Set the SDIOC Data Transfer Mode */ + u32Addr = (uint32_t)&stcTransModeField; + SDIOCx->TRANSMODE = *(uint16_t *)u32Addr; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable SDCLK output + ** + ** SD host drives SDCLK line. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd The SDCLK functional state command + ** \arg Enable Enable SDCLK function + ** \arg Disable Disable SDCLK function + ** + ** \retval Ok SDCLK output of SDIOCx enabled normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SdclkCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + SDIOCx->CLKCON_f.CE = (uint16_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the clock division of SD clock + ** + ** This function changes the SD clock division. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enClkDiv SDIOC clock division value + ** \arg SdiocClkDiv_1 EXCLK/1 + ** \arg SdiocClkDiv_2 EXCLK/2 + ** \arg SdiocClkDiv_4 EXCLK/4 + ** \arg SdiocClkDiv_8 EXCLK/8 + ** \arg SdiocClkDiv_16 EXCLK/16 + ** \arg SdiocClkDiv_32 EXCLK/32 + ** \arg SdiocClkDiv_64 EXCLK/64 + ** \arg SdiocClkDiv_128 EXCLK/128 + ** \arg SdiocClkDiv_256 EXCLK/256 + ** + ** \retval Ok SDIOC clock division is changed normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetClkDiv(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_CLK_DIV(enClkDiv)); + + /* Set clock division */ + SDIOCx->CLKCON_f.FS = (uint16_t)enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the clock division of SD clock + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocClkDiv_1 EXCLK/1 + ** \retval SdiocClkDiv_2 EXCLK/2 + ** \retval SdiocClkDiv_4 EXCLK/4 + ** \retval SdiocClkDiv_8 EXCLK/8 + ** \retval SdiocClkDiv_16 EXCLK/16 + ** \retval SdiocClkDiv_32 EXCLK/32 + ** \retval SdiocClkDiv_64 EXCLK/64 + ** \retval SdiocClkDiv_128 EXCLK/128 + ** + ******************************************************************************/ +en_sdioc_clk_div_t SDIOC_GetClkDiv(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return ((en_sdioc_clk_div_t)SDIOCx->CLKCON_f.FS); +} + +/** + ******************************************************************************* + ** \brief Get the clock division of SD clock + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] u32ClkFreq SDIOC clock frequency + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetClk(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ClkFreq) +{ + uint32_t u32Exclk = 0ul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Get EXCLK frequency */ + u32Exclk = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.EXCKS); + + SDIOCx->CLKCON_f.CE = (uint16_t)0u; + SDIOCx->CLKCON_f.FS = (uint16_t)SdiocGetClkDiv(u32Exclk, u32ClkFreq); + SDIOCx->CLKCON_f.CE = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the bus width of SD Bus + ** + ** This function changes the SD bus width. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enBusWidth Bus width + ** \arg SdiocBusWidth1Bit The SDIOC bus width 1 bit + ** \arg SdiocBusWidth4Bit The SDIOC bus width 4 bit + ** \arg SdiocBusWidth8Bit The SDIOC bus width 8 bit + ** + ** \retval Ok Bus width is set normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - SDIOCx is invalid + ** - enBusWidth is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_bus_width_t enBusWidth) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_BUS_WIDTH(enBusWidth)); + + enRet = Ok; + + switch (enBusWidth) + { + case SdiocBusWidth1Bit: + SDIOCx->HOSTCON_f.EXDW = 0u; + SDIOCx->HOSTCON_f.DW = 0u; + break; + case SdiocBusWidth4Bit: + SDIOCx->HOSTCON_f.EXDW = 0u; + SDIOCx->HOSTCON_f.DW = 1u; + break; + case SdiocBusWidth8Bit: + SDIOCx->HOSTCON_f.EXDW = 1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the bus width of SD Bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocBusWidth1Bit The SDIOC bus width 1 bit + ** \retval SdiocBusWidth4Bit The SDIOC bus width 4 bit + ** \retval SdiocBusWidth8Bit The SDIOC bus width 8 bit + ** + ******************************************************************************/ +en_sdioc_bus_width_t SDIOC_GetBusWidth(M4_SDIOC_TypeDef *SDIOCx) +{ + en_sdioc_bus_width_t enBusWidth = SdiocBusWidth4Bit; + + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + if (0u == SDIOCx->HOSTCON_f.EXDW) + { + if (0u == SDIOCx->HOSTCON_f.DW) + { + enBusWidth = SdiocBusWidth1Bit; + } + } + else + { + enBusWidth = SdiocBusWidth8Bit; + } + + return enBusWidth; +} + +/** + ******************************************************************************* + ** \brief Set the bus speed mode of SD Bus + ** + ** This function changes the SD bus speed mode. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enSpeedMode Speed mode + ** \arg SdiocHighSpeedMode High speed mode + ** \arg SdiocNormalSpeedMode Normal speed mode + ** + ** \retval Ok Bus speed is set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_speed_mode_t enSpeedMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_SPEED_MODE(enSpeedMode)); + + /* Set high speed mode */ + SDIOCx->HOSTCON_f.HSEN = ((SdiocHighSpeedMode == enSpeedMode) ? 1u : 0u); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the bus speed mode of SD Bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocHighSpeedMode High speed mode + ** \retval SdiocNormalSpeedMode Normal speed mode + ** + ******************************************************************************/ +en_sdioc_speed_mode_t SDIOC_GetSpeedMode(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return ((SDIOCx->HOSTCON_f.HSEN) ? SdiocHighSpeedMode : SdiocNormalSpeedMode); +} + +/** + ******************************************************************************* + ** \brief Set data timeout counter value + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enTimeout Data timeout count value + ** \arg SdiocDtoSdclk_2_13 Timeout time: SDCLK*2^13 + ** \arg SdiocDtoSdclk_2_14 Timeout time: SDCLK*2^14 + ** \arg SdiocDtoSdclk_2_15 Timeout time: SDCLK*2^15 + ** \arg SdiocDtoSdclk_2_16 Timeout time: SDCLK*2^16 + ** \arg SdiocDtoSdclk_2_17 Timeout time: SDCLK*2^17 + ** \arg SdiocDtoSdclk_2_18 Timeout time: SDCLK*2^18 + ** \arg SdiocDtoSdclk_2_19 Timeout time: SDCLK*2^19 + ** \arg SdiocDtoSdclk_2_20 Timeout time: SDCLK*2^20 + ** \arg SdiocDtoSdclk_2_21 Timeout time: SDCLK*2^21 + ** \arg SdiocDtoSdclk_2_22 Timeout time: SDCLK*2^22 + ** \arg SdiocDtoSdclk_2_23 Timeout time: SDCLK*2^23 + ** \arg SdiocDtoSdclk_2_24 Timeout time: SDCLK*2^24 + ** \arg SdiocDtoSdclk_2_25 Timeout time: SDCLK*2^25 + ** \arg SdiocDtoSdclk_2_26 Timeout time: SDCLK*2^26 + ** \arg SdiocDtoSdclk_2_27 Timeout time: SDCLK*2^27 + ** + ** \retval Ok Bus speed is set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetDataTimeout(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_data_timeout_t enTimeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_DATA_TIMEOUT(enTimeout)); + + /* Set data timeout */ + SDIOCx->TOUTCON_f.DTO = (uint8_t)enTimeout; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get data timeout counter value + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval SdiocDtoSdclk_2_13 Timeout time: SDCLK*2^13 + ** \retval SdiocDtoSdclk_2_14 Timeout time: SDCLK*2^14 + ** \retval SdiocDtoSdclk_2_15 Timeout time: SDCLK*2^15 + ** \retval SdiocDtoSdclk_2_16 Timeout time: SDCLK*2^16 + ** \retval SdiocDtoSdclk_2_17 Timeout time: SDCLK*2^17 + ** \retval SdiocDtoSdclk_2_18 Timeout time: SDCLK*2^18 + ** \retval SdiocDtoSdclk_2_19 Timeout time: SDCLK*2^19 + ** \retval SdiocDtoSdclk_2_20 Timeout time: SDCLK*2^20 + ** \retval SdiocDtoSdclk_2_21 Timeout time: SDCLK*2^21 + ** \retval SdiocDtoSdclk_2_22 Timeout time: SDCLK*2^22 + ** \retval SdiocDtoSdclk_2_23 Timeout time: SDCLK*2^23 + ** \retval SdiocDtoSdclk_2_24 Timeout time: SDCLK*2^24 + ** \retval SdiocDtoSdclk_2_25 Timeout time: SDCLK*2^25 + ** \retval SdiocDtoSdclk_2_26 Timeout time: SDCLK*2^26 + ** \retval SdiocDtoSdclk_2_27 Timeout time: SDCLK*2^27 + ** + ******************************************************************************/ +en_sdioc_data_timeout_t SDIOC_GetDataTimeout(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return (en_sdioc_data_timeout_t)(SDIOCx->TOUTCON_f.DTO); +} + +/** + ******************************************************************************* + ** \brief Set the card detect signal + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enDetectSignal Card detect signal + ** \arg SdiocSdcdPinLevel SDCD# is selected (for normal use) + ** \arg SdiocCardDetectTestLevel The Card Detect Test Level is selected(for test purpose) + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SetCardDetectSignal(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_detect_signal_t enDetectSignal) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_DETECT_SIG(enDetectSignal)); + SDIOCx->HOSTCON_f.CDSS = (uint8_t)enDetectSignal; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get card inserted or not. + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Set Card Inserted + ** \retval Reset No Card + ** + ** \note This bit is enabled while the Card Detect Signal Selection is set to 1 + ** and it indicates card inserted or not. + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + + return (en_flag_status_t)(SDIOCx->HOSTCON_f.CDTL); +} + +/** + ******************************************************************************* + ** \brief Power on SD bus power + ** + ** This function starts power supply on SD bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Power on normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_BusPowerOn(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->PWRCON_f.PWON = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Power off SD bus power + ** + ** This function stops power supply on SD bus + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Power off normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_BusPowerOff(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->PWRCON_f.PWON = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Stop At Block Gap Request during block gap + ** + ** This function is used to stop data trasnfer of multi-block transfer + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Stop At Block Gap Request functional state + ** \arg Enable Enable the function of Stop At Block Gap Request + ** \arg Disable Disable the function of Stop At Block Gap Request + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_StopAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.SABGR = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Restart data transfer + ** + ** This function is used to restart data transfer when transfer is pending + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + SDIOCx->BLKGPCON_f.CR = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Read Wait Control + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Read Wait Control functional state + ** \arg Enable Enable the Read Wait Control function + ** \arg Disable Disable the Read Wait Control function + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.RWC = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the function of Interrupt At Block Gap + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enCmd SDIOC Interrupt At Block Gap functional state + ** \arg Enable Enable the function of Interrupt At Block Gap + ** \arg Disable Disable the function of Interrupt At Block Gap + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_InterruptAtBlockGapCmd(M4_SDIOC_TypeDef *SDIOCx, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + SDIOCx->BLKGPCON_f.IABG = (uint8_t)(enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Generate software reset to SD card + ** + ** This function generates software reset all command to SD card + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enSwResetType Software reset type + ** \arg SdiocSwResetAll This reset affects the entire Host Controller except for the card detection circuit. + ** \arg SdiocSwResetCmdLine Only part of command circuit is reset. + ** \arg SdiocSwResetDataLine Only part of data circuit is reset. + ** + ** \retval Ok Software reset is done normally + ** \retval ErrorTimeout SDIOCx reset timeout + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - SDIOCx is invalid + ** - enSwResetType is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_sw_reset_t enSwResetType) +{ + __IO uint32_t i = 0ul; + uint32_t u32Cnt = SystemCoreClock / 100ul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_SWRESETTYPE(enSwResetType)); + + enRet = Ok; + switch (enSwResetType) + { + case SdiocSwResetAll: + SDIOCx->SFTRST_f.RSTA = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTA) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + case SdiocSwResetCmdLine: + SDIOCx->SFTRST_f.RSTC = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTC) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + case SdiocSwResetDatLine: + SDIOCx->SFTRST_f.RSTD = (uint8_t)1u; + while(0u != SDIOCx->SFTRST_f.RSTD) /* Wait until reset finish */ + { + if (i++ > u32Cnt) + { + break; + } + } + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (i > u32Cnt) + { + enRet = ErrorTimeout; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the status of SDIOC host controller + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enHostStatus SDIOC host status + ** \arg SdiocCommandInhibitCmd Command Inhibit(CMD). 1: Cannot issue command; 0:Can issue command using only CMD line + ** \arg SdiocCommandInhibitData Command Inhibit(DAT). 1: Cannot issue command which uses the DAT line; 0:Can issue command which uses the DAT line + ** \arg SdiocDataLineActive 1: DAT Line Active; 0: DAT Line Inactive + ** \arg SdiocWriteTransferActive Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocReadTransferActive Read Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocBufferWriteEnble 1: Write enable; 0: Write Disable + ** \arg SdiocBufferReadEnble 1: Read enable; 0: Read Disable + ** \arg SdiocCardInserted 1: Card Inserted; 0: Reset or Debouncing or No Card + ** \arg SdiocCardStateStable 1: No Card or Inserted; 0: Reset or Debouncing + ** \arg SdiocCardDetectPinLvl 1: Card present; 0: No card present + ** \arg SdiocWriteProtectPinLvl 1: Write enabled; 0: Write protected + ** \arg SdiocData0PinLvl 1: DAT0 line signal level high; 0: DAT0 line signal level low + ** \arg SdiocData1PinLvl 1: DAT1 line signal level high; 0: DAT1 line signal level low + ** \arg SdiocData2PinLvl 1: DAT2 line signal level high; 0: DAT2 line signal level low + ** \arg SdiocData3PinLvl 1: DAT3 line signal level high; 0: DAT3 line signal level low + ** \arg SdiocCmdPinLvl 1: CMD line signal level high; 0: CMD line signal level low + ** + ** \retval Set The specified status is set + ** \retval Reset The specified status is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_host_status_t enHostStatus) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_HOST_STATUS(enHostStatus)); + + return ((SDIOCx->PSTAT & ((uint32_t)enHostStatus)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the specified signal of SDIOC normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** \param [in] enCmd SDIOC normal interrupt signal functional state + ** \arg Enable Enable the specified signal of SD normal interrupt + ** \arg Disable Disable the specified signal of SD normal interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_NormalIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + if (Enable == enCmd) + { + SDIOCx->NORINTSGEN |= (uint16_t)enNorInt; + } + else + { + SDIOCx->NORINTSGEN &= (uint16_t)(~((uint16_t)enNorInt)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the status of SDIOC normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** \param [in] enCmd SDIOC normal interrupt status functional state + ** \arg Enable Enable the specified status of SD normal interrupt + ** \arg Disable Disable the specified status of SD normal interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_NormalIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_sel_t enNorInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + if (Enable == enCmd) + { + SDIOCx->NORINTSTEN |= (uint16_t)enNorInt; + } + else + { + SDIOCx->NORINTSTEN &= (uint16_t)(~((uint16_t)enNorInt)); + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the flag of SD normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** + ** \retval Set The specified interupt flag is set + ** \retval Reset The specified interupt flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + + return ((SDIOCx->NORINTST & ((uint16_t)enNorInt)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the flag of SD normal interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enNorInt SDIOC normal interrupt + ** \arg SdiocCommandComplete Command Complete. 1: Command complete; 0:No command complete + ** \arg SdiocTransferComplete Transfer Complete. 1: Data transfer complete; 0:No transfer complete + ** \arg SdiocBlockGapEvent Block Gap Event. 1: Transaction stopped at block gap; 0: No Block Gap Event + ** \arg SdiocBufferWriteReady Buffer Write Ready. 1: Ready to Write buffer; 0: No ready to Write buffer + ** \arg SdiocBufferReadReady Buffer Read Ready. 1: Ready to read buffer; 0: No ready to read buffer + ** \arg SdiocCardInsertedInt Write Transfer Active.1: Transferring data; 0: No valid data + ** \arg SdiocCardRemoval Card Removal. 1: Card removed; 0: Card state stable or Debouncing + ** \arg SdiocCardInt Card Interrupt. 1: Generate Card Interrupt; 0: No Card Interrupt + ** \arg SdiocErrorInt Error Interrupt. 1: Error; 0: No Error + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ClearNormalIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_nor_int_flag_t enNorInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_NOR_INT(enNorInt)); + SDIOCx->NORINTST = (uint16_t)enNorInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the signal of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** \param [in] enCmd SDIOC error interrupt signal functional state + ** \arg Enable Enable the specified signal of SD error interrupt + ** \arg Disable Disable the specified signal of SD error interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ErrIrqSignalCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + if (Enable == enCmd) + { + SDIOCx->ERRINTSGEN |= (uint16_t)enErrInt; + } + else + { + SDIOCx->ERRINTSGEN &= (uint16_t)enErrInt; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable/Disable the status of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** \param [in] enCmd SDIOC error interrupt status functional state + ** \arg Enable Enable the specified status of SD error interrupt + ** \arg Disable Disable the specified status of SD error interrupt + ** + ** \retval Ok Set normally + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ErrIrqStatusCmd(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + if (Enable == enCmd) + { + SDIOCx->ERRINTSTEN |= (uint16_t)enErrInt; + } + else + { + SDIOCx->ERRINTSTEN &= (uint16_t)enErrInt; + } + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the flag of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Set The specified interupt flag is set + ** \retval Reset The specified interupt flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + + return ((SDIOCx->ERRINTST & ((uint16_t)enErrInt)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the flag of SD error interrupt + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ClearErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_flag_t enErrInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + SDIOCx->ERRINTST = (uint16_t)enErrInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Force the specified error interrupt flag + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enErrInt SDIOC error interrupt + ** \arg SdiocCmdTimeoutErr Command Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocCmdCrcErr Command CRC Error. 1: Command CRC Error Generated; 0:No Error + ** \arg SdiocCmdEndBitErr Command End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocCmdIndexErr Command Index Error. 1: Command Index Error Generatedr; 0:No Error + ** \arg SdiocDataTimeoutErr Data Timeout Error. 1: Timer out; 0:No Error + ** \arg SdiocDataCrcErr Data CRC Error. 1: Data CRC Error Generated; 0:No Error + ** \arg SdiocDataEndBitErr Data End Bit Error. 1: End Bit Error Generated; 0:No Error + ** \arg SdiocAutoCmd12Err Auto CMD12 Error. 1: Error; 0:No Error + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ForceErrIrqFlag(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_err_int_sel_t enErrInt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_ERR_INT(enErrInt)); + SDIOCx->FEE |= (uint16_t)enErrInt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the status of auto CMD12 error + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enAutoCmdErr SDIOC auto cmd error status selection + ** \arg SdiocAutoCmd12NotExecuted Auto CMD12 Not Executed. 1: Not executed; 0:Executed + ** \arg SdiocAutoCmd12Timeout Auto CMD12 Timeout Error. 1: Time out; 0:No error + ** \arg SdiocAutoCmd12CrcErr Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + ** \arg SdiocAutoCmd12EndBitErr Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + ** \arg SdiocAutoCmd12IndexErr Auto CMD12 Index Error. 1: Error; 0: No error + ** \arg SdiocCmdNotIssuedErr Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error + ** + ** \retval Set The specified status flag is set + ** \retval Reset The specified status flag is zero + ** + ******************************************************************************/ +en_flag_status_t SDIOC_GetAutoCmdErrStatus(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_status_t enAutoCmdErr) +{ + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC(SDIOCx)); + DDL_ASSERT(IS_VALID_SDIOC_AUTOCMD_ERR(enAutoCmdErr)); + + return ((SDIOCx->ATCERRST & ((uint16_t)enAutoCmdErr)) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Force the specified auto CMD12 error + ** + ** \param [in] SDIOCx Pointer to SDIOC instance register base + ** \arg M4_SDIOC1 SDIOC unit 1 instance register base + ** \arg M4_SDIOC2 SDIOC unit 2 instance register base + ** \param [in] enAutoCmdErr SDIOC auto cmd error selection + ** \arg SdiocAutoCmd12NotExecuted Auto CMD12 Not Executed. 1: Not executed; 0:Executed + ** \arg SdiocAutoCmd12Timeout Auto CMD12 Timeout Error. 1: Time out; 0:No error + ** \arg SdiocAutoCmd12CrcErr Auto CMD12 CRC Error. 1: CRC Error Generated; 0: No error + ** \arg SdiocAutoCmd12EndBitErr Auto CMD12 End Bit Error. 1: End Bit Error Generated; 0: No error to Write buffer + ** \arg SdiocAutoCmd12IndexErr Auto CMD12 Index Error. 1: Error; 0: No error + ** \arg SdiocCmdNotIssuedErr Command Not Issued By Auto CMD12 Error.1: Not Issued; 0: No error + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter SDIOCx is invalid + ** + ******************************************************************************/ +en_result_t SDIOC_ForceAutoCmdErr(M4_SDIOC_TypeDef *SDIOCx, + en_sdioc_atuo_cmd_err_sel_t enAutoCmdErr) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for SDIOCx pointer */ + if (IS_VALID_SDIOC(SDIOCx)) + { + /* Check the parameters */ + DDL_ASSERT(IS_VALID_SDIOC_AUTOCMD_ERR(enAutoCmdErr)); + SDIOCx->FEA |= (uint16_t)enAutoCmdErr; + enRet = Ok; + } + + return enRet; +} + +//@} // SdiocGroup + +#endif /* DDL_SDIOC_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_spi.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_spi.c new file mode 100644 index 0000000000..8d248459fe --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_spi.c @@ -0,0 +1,1132 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_spi.c + ** + ** A detailed description is available at + ** @link SpiGroup Serial Peripheral Interface description @endlink + ** + ** - 2018-10-29 CDT First version for Device Driver Library of Spi. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_spi.h" +#include "hc32f460_utility.h" + +#if (DDL_SPI_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SpiGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for SPI unit */ +#define IS_VALID_SPI_UNIT(x) \ +( (M4_SPI1 == (x)) || \ + (M4_SPI2 == (x)) || \ + (M4_SPI3 == (x)) || \ + (M4_SPI4 == (x))) + +/*!< Parameter valid check for SS setup delay option */ +#define IS_VALID_SS_SETUP_DELAY_OPTION(x) \ +( (SpiSsSetupDelayTypicalSck1 == (x)) || \ + (SpiSsSetupDelayCustomValue == (x))) + +/*!< Parameter valid check for SS setup delay time */ +#define IS_VALID_SS_SETUP_DELAY_TIME(x) \ +( (SpiSsSetupDelaySck1 == (x)) || \ + (SpiSsSetupDelaySck2 == (x)) || \ + (SpiSsSetupDelaySck3 == (x)) || \ + (SpiSsSetupDelaySck4 == (x)) || \ + (SpiSsSetupDelaySck5 == (x)) || \ + (SpiSsSetupDelaySck6 == (x)) || \ + (SpiSsSetupDelaySck7 == (x)) || \ + (SpiSsSetupDelaySck8 == (x))) + +/*!< Parameter valid check for SS hold delay time */ +#define IS_VALID_SS_HOLD_DELAY_TIME(x) \ +( (SpiSsHoldDelaySck1 == (x)) || \ + (SpiSsHoldDelaySck2 == (x)) || \ + (SpiSsHoldDelaySck3 == (x)) || \ + (SpiSsHoldDelaySck4 == (x)) || \ + (SpiSsHoldDelaySck5 == (x)) || \ + (SpiSsHoldDelaySck6 == (x)) || \ + (SpiSsHoldDelaySck7 == (x)) || \ + (SpiSsHoldDelaySck8 == (x))) + +/*!< Parameter valid check for SS hold delay option */ +#define IS_VALID_SS_HOLD_DELAY_OPTION(x) \ +( (SpiSsHoldDelayTypicalSck1 == (x)) || \ + (SpiSsHoldDelayCustomValue == (x))) + +/*!< Parameter valid check for SS interval time option */ +#define IS_VALID_SS_INTERVAL_TIME_OPTION(x) \ +( (SpiSsIntervalTypicalSck1PlusPck2 == (x)) || \ + (SpiSsIntervalCustomValue == (x))) + +/*!< Parameter valid check for SS interval time */ +#define IS_VALID_SS_INTERVAL_TIME(x) \ +( (SpiSsIntervalSck1PlusPck2 == (x)) || \ + (SpiSsIntervalSck2PlusPck2 == (x)) || \ + (SpiSsIntervalSck3PlusPck2 == (x)) || \ + (SpiSsIntervalSck4PlusPck2 == (x)) || \ + (SpiSsIntervalSck5PlusPck2 == (x)) || \ + (SpiSsIntervalSck6PlusPck2 == (x)) || \ + (SpiSsIntervalSck7PlusPck2 == (x)) || \ + (SpiSsIntervalSck8PlusPck2 == (x))) + +/*!< Parameter valid check for SS valid channel select */ +#define IS_VALID_SS_VALID_CHANNEL(x) \ +( (SpiSsValidChannel0 == (x)) || \ + (SpiSsValidChannel1 == (x)) || \ + (SpiSsValidChannel2 == (x)) || \ + (SpiSsValidChannel3 == (x))) + +/*!< Parameter valid check for SS polarity */ +#define IS_VALID_SS_POLARITY(x) \ +( (SpiSsLowValid == (x)) || \ + (SpiSsHighValid == (x))) + +/*!< Parameter valid check for read data register object */ +#define IS_VALID_READ_DATA_REG_OBJECT(x) \ +( (SpiReadReceiverBuffer == (x)) || \ + (SpiReadSendBuffer == (x))) + +/*!< Parameter valid check for SCK polarity */ +#define IS_VALID_SCK_POLARITY(x) \ +( (SpiSckIdleLevelLow == (x)) || \ + (SpiSckIdleLevelHigh == (x))) + +/*!< Parameter valid check for SCK phase */ +#define IS_VALID_SCK_PHASE(x) \ +( (SpiSckOddSampleEvenChange == (x)) || \ + (SpiSckOddChangeEvenSample == (x))) + +/*!< Parameter valid check for clock division */ +#define IS_VALID_CLK_DIV(x) \ +( (SpiClkDiv2 == (x)) || \ + (SpiClkDiv4 == (x)) || \ + (SpiClkDiv8 == (x)) || \ + (SpiClkDiv16 == (x)) || \ + (SpiClkDiv32 == (x)) || \ + (SpiClkDiv64 == (x)) || \ + (SpiClkDiv128 == (x)) || \ + (SpiClkDiv256 == (x))) + +/*!< Parameter valid check for data length */ +#define IS_VALID_DATA_LENGTH(x) \ +( (SpiDataLengthBit4 == (x)) || \ + (SpiDataLengthBit5 == (x)) || \ + (SpiDataLengthBit6 == (x)) || \ + (SpiDataLengthBit7 == (x)) || \ + (SpiDataLengthBit8 == (x)) || \ + (SpiDataLengthBit9 == (x)) || \ + (SpiDataLengthBit10 == (x)) || \ + (SpiDataLengthBit11 == (x)) || \ + (SpiDataLengthBit12 == (x)) || \ + (SpiDataLengthBit13 == (x)) || \ + (SpiDataLengthBit14 == (x)) || \ + (SpiDataLengthBit15 == (x)) || \ + (SpiDataLengthBit16 == (x)) || \ + (SpiDataLengthBit20 == (x)) || \ + (SpiDataLengthBit24 == (x)) || \ + (SpiDataLengthBit32 == (x))) + +/*!< Parameter valid check for first bit position */ +#define IS_VALID_FIRST_BIT_POSITION(x) \ +( (SpiFirstBitPositionMSB == (x)) || \ + (SpiFirstBitPositionLSB == (x))) + +/*!< Parameter valid check for frame number */ +#define IS_VALID_FRAME_NUMBER(x) \ +( (SpiFrameNumber1 == (x)) || \ + (SpiFrameNumber2 == (x)) || \ + (SpiFrameNumber3 == (x)) || \ + (SpiFrameNumber4 == (x))) + +/*!< Parameter valid check for work mode */ +#define IS_VALID_WORK_MODE(x) \ +( (SpiWorkMode4Line == (x)) || \ + (SpiWorkMode3Line == (x))) + +/*!< Parameter valid check for transmission mode */ +#define IS_VALID_COMM_MODE(x) \ +( (SpiTransFullDuplex == (x)) || \ + (SpiTransOnlySend == (x))) + +/*!< Parameter valid check for master slave mode */ +#define IS_VALID_MASTER_SLAVE_MODE(x) \ +( (SpiModeSlave == (x)) || \ + (SpiModeMaster == (x))) + +/*!< Parameter valid check for parity mode */ +#define IS_VALID_PARITY_MODE(x) \ +( (SpiParityEven == (x)) || \ + (SpiParityOdd == (x))) + +/*!< Parameter valid check for SS channel */ +#define IS_VALID_SS_CHANNEL(x) \ +( (SpiSsChannel0 == (x)) || \ + (SpiSsChannel1 == (x)) || \ + (SpiSsChannel2 == (x)) || \ + (SpiSsChannel3 == (x))) + +/*!< Parameter valid check for irq type */ +#define IS_VALID_IRQ_TYPE(x) \ +( (SpiIrqIdle == (x)) || \ + (SpiIrqReceive == (x)) || \ + (SpiIrqSend == (x)) || \ + (SpiIrqError == (x))) + +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (SpiFlagReceiveBufferFull == (x)) || \ + (SpiFlagSendBufferEmpty == (x)) || \ + (SpiFlagUnderloadError == (x)) || \ + (SpiFlagParityError == (x)) || \ + (SpiFlagModeFaultError == (x)) || \ + (SpiFlagSpiIdle == (x)) || \ + (SpiFlagOverloadError == (x))) + +/*!< SPI registers reset value */ +#define SPI_REG_DR_RESET_VALUE 0x00000000ul +#define SPI_REG_CR1_RESET_VALUE 0x00000000ul +#define SPI_REG_CFG1_RESET_VALUE 0x00000010ul +#define SPI_REG_SR_RESET_VALUE 0x00000020ul +#define SPI_REG_CFG2_RESET_VALUE 0x0000031Dul + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize SPI unit + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_DeInit(M4_SPI_TypeDef *SPIx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t regTemp = 0ul; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + regTemp = SPIx->SR; + if (SPI_REG_SR_RESET_VALUE != regTemp) + { + SPIx->SR = SPI_REG_SR_RESET_VALUE; + } + SPIx->CR1 = SPI_REG_CR1_RESET_VALUE; + SPIx->DR = SPI_REG_DR_RESET_VALUE; + SPIx->CFG1 = SPI_REG_CFG1_RESET_VALUE; + SPIx->CFG2 = SPI_REG_CFG2_RESET_VALUE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize SPI unit + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] pstcSpiInitCfg Pointer to SPI init configuration + ** \arg See the struct #stc_spi_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** - pstcSpiInitCfg == NULL + ** + ******************************************************************************/ +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if((IS_VALID_SPI_UNIT(SPIx)) && (NULL != pstcSpiInitCfg)) + { + DDL_ASSERT(IS_VALID_SS_SETUP_DELAY_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayOption)); + DDL_ASSERT(IS_VALID_SS_SETUP_DELAY_TIME(pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayTime)); + DDL_ASSERT(IS_VALID_SS_HOLD_DELAY_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayOption)); + DDL_ASSERT(IS_VALID_SS_HOLD_DELAY_TIME(pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayTime)); + DDL_ASSERT(IS_VALID_SS_INTERVAL_TIME_OPTION(pstcSpiInitCfg->stcDelayConfig.enSsIntervalTimeOption)); + DDL_ASSERT(IS_VALID_SS_INTERVAL_TIME(pstcSpiInitCfg->stcDelayConfig.enSsIntervalTime)); + DDL_ASSERT(IS_VALID_SS_VALID_CHANNEL(pstcSpiInitCfg->stcSsConfig.enSsValidBit)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs0Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs1Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs2Polarity)); + DDL_ASSERT(IS_VALID_SS_POLARITY(pstcSpiInitCfg->stcSsConfig.enSs3Polarity)); + DDL_ASSERT(IS_VALID_READ_DATA_REG_OBJECT(pstcSpiInitCfg->enReadBufferObject)); + DDL_ASSERT(IS_VALID_SCK_POLARITY(pstcSpiInitCfg->enSckPolarity)); + DDL_ASSERT(IS_VALID_SCK_PHASE(pstcSpiInitCfg->enSckPhase)); + DDL_ASSERT(IS_VALID_CLK_DIV(pstcSpiInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_DATA_LENGTH(pstcSpiInitCfg->enDataLength)); + DDL_ASSERT(IS_VALID_FIRST_BIT_POSITION(pstcSpiInitCfg->enFirstBitPosition)); + DDL_ASSERT(IS_VALID_FRAME_NUMBER(pstcSpiInitCfg->enFrameNumber)); + DDL_ASSERT(IS_VALID_WORK_MODE(pstcSpiInitCfg->enWorkMode)); + DDL_ASSERT(IS_VALID_COMM_MODE(pstcSpiInitCfg->enTransMode)); + DDL_ASSERT(IS_VALID_MASTER_SLAVE_MODE(pstcSpiInitCfg->enMasterSlaveMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enCommAutoSuspendEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enModeFaultErrorDetectEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enParitySelfDetectEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcSpiInitCfg->enParityEn)); + DDL_ASSERT(IS_VALID_PARITY_MODE(pstcSpiInitCfg->enParity)); + + /* Master mode */ + if (SpiModeMaster == pstcSpiInitCfg->enMasterSlaveMode) + { + SPIx->CFG2_f.MSSIE = pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayOption; + SPIx->CFG2_f.MSSDLE = pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayOption; + SPIx->CFG2_f.MIDIE = pstcSpiInitCfg->stcDelayConfig.enSsIntervalTimeOption; + SPIx->CFG1_f.MSSI = pstcSpiInitCfg->stcDelayConfig.enSsSetupDelayTime; + SPIx->CFG1_f.MSSDL = pstcSpiInitCfg->stcDelayConfig.enSsHoldDelayTime; + SPIx->CFG1_f.MIDI = pstcSpiInitCfg->stcDelayConfig.enSsIntervalTime; + } + else + { + SPIx->CFG2_f.MSSIE = SpiSsSetupDelayTypicalSck1; + SPIx->CFG2_f.MSSDLE = SpiSsHoldDelayTypicalSck1; + SPIx->CFG2_f.MIDIE = SpiSsIntervalTypicalSck1PlusPck2; + SPIx->CFG1_f.MSSI = SpiSsSetupDelaySck1; + SPIx->CFG1_f.MSSDL = SpiSsHoldDelaySck1; + SPIx->CFG1_f.MIDI = SpiSsIntervalSck1PlusPck2; + } + + /* 4 lines spi mode */ + if (SpiWorkMode4Line == pstcSpiInitCfg->enWorkMode) + { + SPIx->CFG2_f.SSA = pstcSpiInitCfg->stcSsConfig.enSsValidBit; + SPIx->CFG1_f.SS0PV = pstcSpiInitCfg->stcSsConfig.enSs0Polarity; + SPIx->CFG1_f.SS1PV = pstcSpiInitCfg->stcSsConfig.enSs1Polarity; + SPIx->CFG1_f.SS2PV = pstcSpiInitCfg->stcSsConfig.enSs2Polarity; + SPIx->CFG1_f.SS3PV = pstcSpiInitCfg->stcSsConfig.enSs3Polarity; + } + else + { + SPIx->CFG2_f.SSA = SpiSsValidChannel0; + SPIx->CFG1_f.SS0PV = SpiSsLowValid; + SPIx->CFG1_f.SS1PV = SpiSsLowValid; + SPIx->CFG1_f.SS2PV = SpiSsLowValid; + SPIx->CFG1_f.SS3PV = SpiSsLowValid; + } + + /* Configure communication config register 1 */ + SPIx->CFG1_f.SPRDTD = pstcSpiInitCfg->enReadBufferObject; + SPIx->CFG1_f.FTHLV = pstcSpiInitCfg->enFrameNumber; + + /* Configure communication config register 2 */ + SPIx->CFG2_f.LSBF = pstcSpiInitCfg->enFirstBitPosition; + SPIx->CFG2_f.DSIZE = pstcSpiInitCfg->enDataLength; + SPIx->CFG2_f.MBR = pstcSpiInitCfg->enClkDiv; + SPIx->CFG2_f.CPOL = pstcSpiInitCfg->enSckPolarity; + SPIx->CFG2_f.CPHA = pstcSpiInitCfg->enSckPhase; + + /* Configure control register */ + SPIx->CR1_f.SPIMDS = pstcSpiInitCfg->enWorkMode; + SPIx->CR1_f.TXMDS = pstcSpiInitCfg->enTransMode; + SPIx->CR1_f.MSTR = pstcSpiInitCfg->enMasterSlaveMode; + SPIx->CR1_f.CSUSPE = pstcSpiInitCfg->enCommAutoSuspendEn; + SPIx->CR1_f.MODFE = pstcSpiInitCfg->enModeFaultErrorDetectEn; + SPIx->CR1_f.PATE = pstcSpiInitCfg->enParitySelfDetectEn; + SPIx->CR1_f.PAE = pstcSpiInitCfg->enParityEn; + SPIx->CR1_f.PAOE = pstcSpiInitCfg->enParity; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI general loopback + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable general loopback + ** \arg Enable Enable general loopback + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_GeneralLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPLPBK2 = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI reverse loopback + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable reverse loopback + ** \arg Enable Enable reverse loopback + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_ReverseLoopbackCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPLPBK = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI working + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable SPI working + ** \arg Enable Enable SPI working + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_Cmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + SPIx->CR1_f.SPE = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 8bit data or 4/5/6/7 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u8Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData8(M4_SPI_TypeDef *SPIx, uint8_t u8Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u8Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 16bit data or 9/10/11/12/13/14/15 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u16Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData16(M4_SPI_TypeDef *SPIx, uint16_t u16Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u16Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI send 32bit data or 20/24 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] u32Data Send data value + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SendData32(M4_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + SPIx->DR = u32Data; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI receive 8bit data or 4/5/6/7 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint8_t Receive data value + ** + ******************************************************************************/ +uint8_t SPI_ReceiveData8(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint8_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI receive 16bit data or 9/10/11/12/13/14/15 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint16_t Receive data value + ** + ******************************************************************************/ +uint16_t SPI_ReceiveData16(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint16_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI receive 32bit data or 20/24 bit data + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \retval uint32_t Receive data value + ** + ******************************************************************************/ +uint32_t SPI_ReceiveData32(const M4_SPI_TypeDef *SPIx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return ((uint32_t)SPIx->DR); +} + +/** + ******************************************************************************* + ** \brief SPI set SS channel valid level polarity + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enChannel Select Slave channel + ** \arg SpiSsChannel0 SS0 channel + ** \arg SpiSsChannel1 SS1 channel + ** \arg SpiSsChannel2 SS2 channel + ** \arg SpiSsChannel3 SS3 channel + ** + ** \param [in] enPolarity SS channel valid level polarity + ** \arg SpiSsLowValid SS0~3 signal low level valid + ** \arg SpiSsHighValid SS0~3 signal high level valid + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetSsPolarity(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel, + en_spi_ss_polarity_t enPolarity) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_SS_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_SS_POLARITY(enPolarity)); + + switch (enChannel) + { + case SpiSsChannel0: + SPIx->CFG1_f.SS0PV = enPolarity; + break; + case SpiSsChannel1: + SPIx->CFG1_f.SS1PV = enPolarity; + break; + case SpiSsChannel2: + SPIx->CFG1_f.SS2PV = enPolarity; + break; + case SpiSsChannel3: + SPIx->CFG1_f.SS3PV = enPolarity; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set SS valid channel + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enChannel Select Slave channel + ** \arg SpiSsChannel0 SS0 channel + ** \arg SpiSsChannel1 SS1 channel + ** \arg SpiSsChannel2 SS2 channel + ** \arg SpiSsChannel3 SS3 channel + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetSsValidChannel(M4_SPI_TypeDef *SPIx, en_spi_ss_channel_t enChannel) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_SS_CHANNEL(enChannel)); + + SPIx->CFG2_f.SSA = enChannel; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set read data register object + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enObject Read data register object + ** \arg SpiReadReceiverBuffer Read receive buffer + ** \arg SpiReadSendBuffer Read send buffer(must be read when TDEF=1) + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetReadDataRegObject(M4_SPI_TypeDef *SPIx, en_spi_read_object_t enObject) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_READ_DATA_REG_OBJECT(enObject)); + + SPIx->CFG1_f.SPRDTD = enObject; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set frame number + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFrameNum Once read or write frame number + ** \arg SpiFrameNumber1 1 frame data + ** \arg SpiFrameNumber2 2 frame data + ** \arg SpiFrameNumber3 3 frame data + ** \arg SpiFrameNumber4 4 frame data + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetFrameNumber(M4_SPI_TypeDef *SPIx, en_spi_frame_number_t enFrameNum) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FRAME_NUMBER(enFrameNum)); + + SPIx->CFG1_f.FTHLV = enFrameNum; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set data length + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enDataLength Read or write data length + ** \arg SpiDataLengthBit4 4 bits + ** \arg SpiDataLengthBit5 5 bits + ** \arg SpiDataLengthBit6 6 bits + ** \arg SpiDataLengthBit7 7 bits + ** \arg SpiDataLengthBit8 8 bits + ** \arg SpiDataLengthBit9 9 bits + ** \arg SpiDataLengthBit10 10 bits + ** \arg SpiDataLengthBit11 11 bits + ** \arg SpiDataLengthBit12 12 bits + ** \arg SpiDataLengthBit13 13 bits + ** \arg SpiDataLengthBit14 14 bits + ** \arg SpiDataLengthBit15 15 bits + ** \arg SpiDataLengthBit16 16 bits + ** \arg SpiDataLengthBit20 20 bits + ** \arg SpiDataLengthBit24 24 bits + ** \arg SpiDataLengthBit32 32 bits + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetDataLength(M4_SPI_TypeDef *SPIx, en_spi_data_length_t enDataLength) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_DATA_LENGTH(enDataLength)); + + SPIx->CFG2_f.DSIZE = enDataLength; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set first bit position + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enPosition First bit position + ** \arg SpiFirstBitPositionMSB Spi first bit to MSB + ** \arg SpiFirstBitPositionLSB Spi first bit to LSB + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetFirstBitPosition(M4_SPI_TypeDef *SPIx, en_spi_first_bit_position_t enPosition) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FIRST_BIT_POSITION(enPosition)); + + SPIx->CFG2_f.LSBF = enPosition; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief SPI set clock division + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enClkDiv Clock division + ** \arg SpiClkDiv2 Spi pclk1 division 2 + ** \arg SpiClkDiv4 Spi pclk1 division 4 + ** \arg SpiClkDiv8 Spi pclk1 division 8 + ** \arg SpiClkDiv16 Spi pclk1 division 16 + ** \arg SpiClkDiv32 Spi pclk1 division 32 + ** \arg SpiClkDiv64 Spi pclk1 division 64 + ** \arg SpiClkDiv128 Spi pclk1 division 128 + ** \arg SpiClkDiv256 Spi pclk1 division 256 + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_SetClockDiv(M4_SPI_TypeDef *SPIx, en_spi_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_CLK_DIV(enClkDiv)); + + SPIx->CFG2_f.MBR = enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable SPI interrupt request + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enIrq SPI interrupt request type + ** \arg SpiIrqIdle Spi idle interrupt request + ** \arg SpiIrqReceive Spi receive interrupt request + ** \arg SpiIrqSend Spi send interrupt request + ** \arg SpiIrqError Spi error interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable interrupt request + ** \arg Enable Enable interrupt request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_IrqCmd(M4_SPI_TypeDef *SPIx, en_spi_irq_type_t enIrq, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_IRQ_TYPE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enIrq) + { + case SpiIrqIdle: + SPIx->CR1_f.IDIE = enNewSta; + break; + case SpiIrqReceive: + SPIx->CR1_f.RXIE = enNewSta; + break; + case SpiIrqSend: + SPIx->CR1_f.TXIE = enNewSta; + break; + case SpiIrqError: + SPIx->CR1_f.EIE = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SPI flag status + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFlag SPI flag type + ** \arg SpiFlagReceiveBufferFull Receive buffer full flag + ** \arg SpiFlagSendBufferEmpty Send buffer empty flag + ** \arg SpiFlagUnderloadError Underload error flag + ** \arg SpiFlagParityError Parity error flag + ** \arg SpiFlagModeFaultError Mode fault error flag + ** \arg SpiFlagSpiIdle SPI idle flag + ** \arg SpiFlagOverloadErro Overload error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t SPI_GetFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + if (IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SpiFlagReceiveBufferFull: + enFlagSta = (en_flag_status_t)SPIx->SR_f.RDFF; + break; + case SpiFlagSendBufferEmpty: + enFlagSta = (en_flag_status_t)SPIx->SR_f.TDEF; + break; + case SpiFlagUnderloadError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.UDRERF; + break; + case SpiFlagParityError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.PERF; + break; + case SpiFlagModeFaultError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.MODFERF; + break; + case SpiFlagSpiIdle: + enFlagSta = (en_flag_status_t)(bool)(!SPIx->SR_f.IDLNF); + break; + case SpiFlagOverloadError: + enFlagSta = (en_flag_status_t)SPIx->SR_f.OVRERF; + break; + default: + break; + } + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear SPI flag status + ** + ** \param [in] SPIx Pointer to SPI unit configuration address + ** \arg M4_SPI1 SPI unit 1 configuration Address + ** \arg M4_SPI2 SPI unit 2 configuration Address + ** \arg M4_SPI3 SPI unit 3 configuration Address + ** \arg M4_SPI4 SPI unit 4 configuration Address + ** + ** \param [in] enFlag SPI flag type + ** \arg SpiFlagReceiveBufferFull Receive buffer full flag + ** \arg SpiFlagSendBufferEmpty Send buffer empty flag + ** \arg SpiFlagUnderloadError Underload error flag + ** \arg SpiFlagParityError Parity error flag + ** \arg SpiFlagModeFaultError Mode fault error flag + ** \arg SpiFlagSpiIdle SPI empty flag + ** \arg SpiFlagOverloadErro Overload error flag + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - SPIx is invalid + ** + ******************************************************************************/ +en_result_t SPI_ClearFlag(M4_SPI_TypeDef *SPIx, en_spi_flag_type_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SPI_UNIT(SPIx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SpiFlagReceiveBufferFull: + SPIx->SR_f.RDFF = 0u; + break; + case SpiFlagSendBufferEmpty: + SPIx->SR_f.TDEF = 0u; + break; + case SpiFlagUnderloadError: + SPIx->SR_f.UDRERF = 0u; + break; + case SpiFlagParityError: + SPIx->SR_f.PERF = 0u; + break; + case SpiFlagModeFaultError: + SPIx->SR_f.MODFERF = 0u; + break; + case SpiFlagSpiIdle: + SPIx->SR_f.IDLNF = 0u; + break; + case SpiFlagOverloadError: + SPIx->SR_f.OVRERF = 0u; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +//@} // SpiGroup + +#endif /* DDL_SPI_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sram.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sram.c new file mode 100644 index 0000000000..a7f8828d58 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_sram.c @@ -0,0 +1,286 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_sram.c + ** + ** A detailed description is available at + ** @link SramGroup Internal SRAM module description @endlink + ** + ** - 2018-10-17 CDT First version for Device Driver Library of SRAM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_sram.h" +#include "hc32f460_utility.h" + +#if (DDL_SRAM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SramGroup + ******************************************************************************/ +//@{ +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for ECC/Parity error handling. */ +#define IS_VALID_ERR_OP(x) \ +( ((x) == SramNmi) || \ + ((x) == SramReset)) + +/*! Parameter validity check for SRAM ECC mode */ +#define IS_VALID_ECC_MD(x) \ +( ((x) == EccMode0) || \ + ((x) == EccMode1) || \ + ((x) == EccMode2) || \ + ((x) == EccMode3)) + +/*! Parameter validity check for SRAM Index */ +#define IS_VALID_INDEX(x) \ +( ((x) == Sram12Idx) || \ + ((x) == Sram3Idx) || \ + ((x) == SramHsIdx) || \ + ((x) == SramRetIdx)) + +/*! Parameter validity check for SRAM R/W wait cycle */ +#define IS_VALID_WAIT_CYCLE(x) \ +( ((x) == SramCycle1) || \ + ((x) == SramCycle2) || \ + ((x) == SramCycle3) || \ + ((x) == SramCycle4) || \ + ((x) == SramCycle5) || \ + ((x) == SramCycle6) || \ + ((x) == SramCycle7) || \ + ((x) == SramCycle8)) + +/*! Parameter validity check for SRAM error status */ +#define IS_VALID_ERR(x) \ +( ((x) == Sram3EccErr1) || \ + ((x) == Sram3EccErr2) || \ + ((x) == Sram12ParityErr) || \ + ((x) == SramHSParityErr) || \ + ((x) == SramRetParityErr)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SRAM read, write wait cycle register disable function + ** + ** \param None + ** + ** \retval Ok SRAM R/W wait cycle register disabled + ** + ******************************************************************************/ +en_result_t SRAM_WT_Disable(void) +{ + M4_SRAMC->WTPR = 0x76u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM read, write wait cycle register enable function + ** + ** \param None + ** + ** \retval Ok SRAM R/W wait cycle register enabled + ** + ******************************************************************************/ +en_result_t SRAM_WT_Enable(void) +{ + M4_SRAMC->WTPR = 0x77u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM ECC/Parity check register disable function + ** + ** \param None + ** + ** \retval Ok SRAM ECC/Parity check register disabled + ** + ******************************************************************************/ +en_result_t SRAM_CK_Disable(void) +{ + M4_SRAMC->CKPR = 0x76u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM ECC/Parity check register enable function + ** + ** \param None + ** + ** \retval Ok SRAM ECC/Parity check register enabled + ** + ******************************************************************************/ +en_result_t SRAM_CK_Enable(void) +{ + M4_SRAMC->CKPR = 0x77u; + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get SRAM ECC/Parity error status flag + ** + ** \param [in] enSramErrStatus SRAM error status, This parameter can be + ** some values of @ref en_sram_err_status_t + ** + ** \retval Set Corresponding error occurs + ** Reset Corresponding error not occurs + ** + ******************************************************************************/ +en_flag_status_t SRAM_GetStatus(en_sram_err_status_t enSramErrStatus) +{ + DDL_ASSERT(IS_VALID_ERR(enSramErrStatus)); + if (true == !!(enSramErrStatus & M4_SRAMC->CKSR)) + { + return Set; + } + else + { + return Reset; + } +} + +/** + ******************************************************************************* + ** \brief Clear SRAM ECC/Parity error status flag + ** + ** \param [in] enSramErrStatus SRAM error status, This parameter can be + ** some values of @ref en_sram_err_status_t + ** + ** \retval Ok Corresponding error flag be cleared + ** ErrorInvalidParameter Invalid parameter + ** + ******************************************************************************/ +en_result_t SRAM_ClrStatus(en_sram_err_status_t enSramErrStatus) +{ + DDL_ASSERT(IS_VALID_ERR(enSramErrStatus)); + M4_SRAMC->CKSR |= enSramErrStatus; + return Ok; +} + +/** + ******************************************************************************* + ** \brief SRAM initialization + ** + ** \param [in] pstcSramConfig SRAM configure structure + ** + ** \retval Ok SRAM initialized + ** ErrorInvalidParameter Invalid parameter + ** + ******************************************************************************/ +en_result_t SRAM_Init(const stc_sram_config_t *pstcSramConfig) +{ + uint8_t i = 0u; + uint8_t u8TmpIdx; + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramRC)); + DDL_ASSERT(IS_VALID_WAIT_CYCLE(pstcSramConfig->enSramWC)); + DDL_ASSERT(IS_VALID_ECC_MD(pstcSramConfig->enSramEccMode)); + DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramEccOp)); + DDL_ASSERT(IS_VALID_ERR_OP(pstcSramConfig->enSramPyOp)); + + u8TmpIdx = pstcSramConfig->u8SramIdx; + + if (0u == u8TmpIdx) + { + enRet = ErrorInvalidParameter; + } + else + { + SRAM_WT_Enable(); + SRAM_CK_Enable(); + for (i = 0u; i < 4u; i++) + { + if (true == (u8TmpIdx & 0x01u)) + { + M4_SRAMC->WTCR |= (pstcSramConfig->enSramRC | \ + (pstcSramConfig->enSramWC << 4ul)) << (i * 8ul); + } + u8TmpIdx >>= 1u; + } + /* SRAM3 ECC config */ + if (pstcSramConfig->u8SramIdx & Sram3Idx) + { + M4_SRAMC->CKCR_f.ECCMOD = pstcSramConfig->enSramEccMode; + M4_SRAMC->CKCR_f.ECCOAD = pstcSramConfig->enSramEccOp; + } + /* SRAM1/2/HS/Ret parity config */ + else + { + M4_SRAMC->CKCR_f.PYOAD = pstcSramConfig->enSramPyOp; + } + + SRAM_WT_Disable(); + SRAM_CK_Disable(); + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief SRAM de-initialization + ** + ** \param None + ** + ** \retval Ok SRAM de-initialized + ** + ******************************************************************************/ +en_result_t SRAM_DeInit(void) +{ + /* SRAM R/W wait register */ + M4_SRAMC->WTPR = 0x77ul; + M4_SRAMC->WTCR = 0ul; + M4_SRAMC->WTPR = 0x76ul; + + /* SRAM check register */ + M4_SRAMC->CKPR = 0x77ul; + M4_SRAMC->CKCR = 0ul; + M4_SRAMC->CKPR = 0x76ul; + + /* SRAM status register */ + M4_SRAMC->CKSR = 0x1Ful; + + return Ok; +} + +//@} // SramGroup + +#endif /* DDL_SRAM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_swdt.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_swdt.c new file mode 100644 index 0000000000..57d5766fa1 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_swdt.c @@ -0,0 +1,170 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_swdt.c + ** + ** A detailed description is available at + ** @link SwdtGroup Special Watchdog Counter description @endlink + ** + ** - 2018-10-16 CDT First version for Device Driver Library of SWDT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_swdt.h" +#include "hc32f460_utility.h" + +#if (DDL_SWDT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup SwdtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (SwdtFlagCountUnderflow == (x)) || \ + (SwdtFlagRefreshError == (x))) + +/*!< SWDT_RR register refresh key */ +#define SWDT_REFRESH_START_KEY ((uint16_t)0x0123) +#define SWDT_REFRESH_END_KEY_ ((uint16_t)0x3210) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief SWDT refresh counter + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t SWDT_RefreshCounter(void) +{ + en_result_t enRet = Ok; + + M4_SWDT->RR = SWDT_REFRESH_START_KEY; + M4_SWDT->RR = SWDT_REFRESH_END_KEY_; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get SWDT counter current count value + ** + ** \param [in] None + ** + ** \retval uint16_t SWDT counter current count value + ** + ******************************************************************************/ +uint16_t SWDT_GetCountValue(void) +{ + return ((uint16_t)M4_SWDT->SR_f.CNT); +} + +/** + ******************************************************************************* + ** \brief Get SWDT flag status + ** + ** \param [in] enFlag SWDT flag type + ** \arg SwdtFlagCountUnderflow Count underflow flag + ** \arg SwdtFlagRefreshError Refresh error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t SWDT_GetFlag(en_swdt_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SwdtFlagCountUnderflow: + enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.UDF; + break; + case SwdtFlagRefreshError: + enFlagSta = (en_flag_status_t)M4_SWDT->SR_f.REF; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear SWDT flag status + ** + ** \param [in] enFlag SWDT flag type + ** \arg SwdtFlagCountUnderflow Count underflow flag + ** \arg SwdtFlagRefreshError Refresh error flag + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t SWDT_ClearFlag(en_swdt_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case SwdtFlagCountUnderflow: + M4_SWDT->SR_f.UDF = 0u; + break; + case SwdtFlagRefreshError: + M4_SWDT->SR_f.REF = 0u; + break; + default: + break; + } + + return enRet; +} + +//@} // SwdtGroup + +#endif /* DDL_SWDT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer0.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer0.c new file mode 100644 index 0000000000..497f5d97ff --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer0.c @@ -0,0 +1,967 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer0.c + ** + ** A detailed description is available at + ** @link Timer0Group description @endlink + ** + ** - 2018-10-11 CDT First version for Device Driver Library of TIMER0. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer0.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER0_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer0Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Parameter validity check for unit. */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_TMR01) || \ + ((x) == M4_TMR02)) + +/* Parameter validity check for channel. */ +#define IS_VALID_CHANNEL(x) \ +( ((x) == Tim0_ChannelA) || \ + ((x) == Tim0_ChannelB)) + +/* Parameter validity check for command. */ +#define IS_VALID_COMMAND(x) \ +( ((x) == Disable) || \ + ((x) == Enable)) + +/* Parameter validity check for timer0 function mode. */ +#define IS_VALID_FUNCTION(x) \ +( ((x) == Tim0_OutputCapare) || \ + ((x) == Tim0_InputCaptrue)) + +/* Parameter validity check for clock division. */ +#define IS_VALID_CLK_DIVISION(x) \ +( ((x) == Tim0_ClkDiv0) || \ + ((x) == Tim0_ClkDiv2) || \ + ((x) == Tim0_ClkDiv4) || \ + ((x) == Tim0_ClkDiv8) || \ + ((x) == Tim0_ClkDiv16) || \ + ((x) == Tim0_ClkDiv32) || \ + ((x) == Tim0_ClkDiv64) || \ + ((x) == Tim0_ClkDiv128) || \ + ((x) == Tim0_ClkDiv256) || \ + ((x) == Tim0_ClkDiv512) || \ + ((x) == Tim0_ClkDiv1024)) + +/* Parameter validity check for synchronous clock source. */ +#define IS_VALID_CLK_SYN_SRC(x) \ +( ((x) == Tim0_Pclk1) || \ + ((x) == Tim0_InsideHardTrig)) + +/* Parameter validity check for asynchronous clock source. */ +#define IS_VALID_CLK_ASYN_SRC(x) \ +( ((x) == Tim0_LRC) || \ + ((x) == Tim0_XTAL32)) + +/* Parameter validity check for counter clock mode. */ +#define IS_VALID_CLK_MODE(x) \ +( ((x) == Tim0_Sync) || \ + ((x) == Tim0_Async)) + +/* Parameter validity check for counter clock mode for M4_TMR01. */ +#define IS_VALID_CLK_MODE_UNIT01(x) \ +( (x) == Tim0_Async) + +/* Parameter validity check for external trigger event. */ +#define IS_VALID_TRIG_SRC_EVENT(x) \ +( ((x) <= EVT_PORT_EIRQ15) || \ + (((x) >= EVT_DMA1_TC0) && ((x) <= EVT_DMA2_BTC3)) || \ + (((x) >= EVT_EFM_OPTEND) && ((x) <= EVT_USBFS_SOF)) || \ + (((x) >= EVT_DCU1) && ((x) <= EVT_DCU4)) || \ + (((x) >= EVT_TMR01_GCMA) && ((x) <= EVT_TMR02_GCMB)) || \ + (((x) >= EVT_RTC_ALM) && ((x) <= EVT_RTC_PRD)) || \ + (((x) >= EVT_TMR61_GCMA) && ((x) <= EVT_TMR61_GUDF)) || \ + (((x) >= EVT_TMR61_SCMA) && ((x) <= EVT_TMR61_SCMB)) || \ + (((x) >= EVT_TMR62_GCMA) && ((x) <= EVT_TMR62_GUDF)) || \ + (((x) >= EVT_TMR62_SCMA) && ((x) <= EVT_TMR62_SCMB)) || \ + (((x) >= EVT_TMR63_GCMA) && ((x) <= EVT_TMR63_GUDF)) || \ + (((x) >= EVT_TMR63_SCMA) && ((x) <= EVT_TMR63_SCMB)) || \ + (((x) >= EVT_TMRA1_OVF) && ((x) <= EVT_TMRA5_CMP)) || \ + (((x) >= EVT_TMRA6_OVF) && ((x) <= EVT_TMRA6_CMP)) || \ + (((x) >= EVT_USART1_EI) && ((x) <= EVT_USART4_RTO)) || \ + (((x) >= EVT_SPI1_SPRI) && ((x) <= EVT_AOS_STRG)) || \ + (((x) >= EVT_TMR41_SCMUH) && ((x) <= EVT_TMR42_SCMWL)) || \ + (((x) >= EVT_TMR43_SCMUH) && ((x) <= EVT_TMR43_SCMWL)) || \ + (((x) >= EVT_EVENT_PORT1) && ((x) <= EVT_EVENT_PORT4)) || \ + (((x) >= EVT_I2S1_TXIRQOUT) && ((x) <= EVT_I2S1_RXIRQOUT)) || \ + (((x) >= EVT_I2S2_TXIRQOUT) && ((x) <= EVT_I2S2_RXIRQOUT)) || \ + (((x) >= EVT_I2S3_TXIRQOUT) && ((x) <= EVT_I2S3_RXIRQOUT)) || \ + (((x) >= EVT_I2S4_TXIRQOUT) && ((x) <= EVT_I2S4_RXIRQOUT)) || \ + (((x) >= EVT_ACMP1) && ((x) <= EVT_ACMP3)) || \ + (((x) >= EVT_I2C1_RXI) && ((x) <= EVT_I2C3_EEI)) || \ + (((x) >= EVT_PVD_PVD1) && ((x) <= EVT_OTS)) || \ + ((x) == EVT_WDT_REFUDF) || \ + (((x) >= EVT_ADC1_EOCA) && ((x) <= EVT_TRNG_END)) || \ + (((x) >= EVT_SDIOC1_DMAR) && ((x) <= EVT_SDIOC1_DMAW)) || \ + (((x) >= EVT_SDIOC2_DMAR) && ((x) <= EVT_SDIOC2_DMAW))) + +/* Parameter validity check for common trigger. */ +#define IS_VALID_TIM0_COM_TRIGGER(x) \ +( ((x) == Tim0ComTrigger_1) || \ + ((x) == Tim0ComTrigger_2) || \ + ((x) == Tim0ComTrigger_1_2)) + +/* Delay count for time out */ +#define TIMER0_TMOUT (0x5000ul) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Get clock mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval Tim0_Sync: Synchronous clock + ** \retval Tim0_Async: Asynchronous clock + ** + ******************************************************************************/ +static en_tim0_counter_mode_t TIMER0_GetClkMode(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh) +{ + en_tim0_counter_mode_t enMode = Tim0_Sync; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + switch(enCh) + { + case Tim0_ChannelA: + enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSA; + break; + case Tim0_ChannelB: + enMode = (en_tim0_counter_mode_t)pstcTim0Reg->BCONR_f.SYNSB; + break; + default: + break; + } + return enMode; +} + +/** + ******************************************************************************* + ** \brief Time delay for register write in asynchronous mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enIsPublicReg Enable for BCONR and STFLR register delay + ** + ** \retval None + ** + ******************************************************************************/ +static void AsyncDelay(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enIsPublicReg) +{ + en_functional_state_t enDelayEn = Disable; + en_tim0_counter_mode_t enModeA = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelA); + en_tim0_counter_mode_t enModeB = TIMER0_GetClkMode(pstcTim0Reg, Tim0_ChannelB); + + if(Enable == enIsPublicReg) + { + if((Tim0_Async == enModeA) || (Tim0_Async == enModeB)) + { + enDelayEn = Enable; + } + } + else + { + if(Tim0_Async == TIMER0_GetClkMode(pstcTim0Reg, enCh)) + { + enDelayEn = Enable; + } + } + + if(Enable == enDelayEn) + { + for(uint32_t i=0ul; iSTFLR_f.CMAF; + break; + case Tim0_ChannelB: + enFlag = (en_flag_status_t)pstcTim0Reg->STFLR_f.CMBF; + break; + default: + break; + } + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear Timer0 status flag + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_ClearFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->STFLR_f.CMAF =0u; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0u != pstcTim0Reg->STFLR_f.CMAF) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->STFLR_f.CMBF = 0u; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0u != pstcTim0Reg->STFLR_f.CMBF) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Command the timer0 function + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Timer0_ChA or Timer0_ChB + ** + ** \param [in] enCmd Disable or Enable the function + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_Cmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enCmd) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_COMMAND(enCmd)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.CSTA = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.CSTA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.CSTB = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.CSTB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Select the timer0 function mode + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enFunc Timer0 function,Tim0_OutputCapare or Tim0_InputCapture + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_SetFunc(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_tim0_function_t enFunc) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_FUNCTION(enFunc)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.CAPMDA = enFunc; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enFunc != pstcTim0Reg->BCONR_f.CAPMDA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.CAPMDB = enFunc; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enFunc != pstcTim0Reg->BCONR_f.CAPMDB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 interrupt function command + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] enCmd Disable or Enable the function + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_IntCmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + en_functional_state_t enCmd) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_COMMAND(enCmd)); + + switch (enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR_f.INTENA = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.INTENA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + case Tim0_ChannelB: + pstcTim0Reg->BCONR_f.INTENB = enCmd; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(enCmd != pstcTim0Reg->BCONR_f.INTENB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer0 counter register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval uint16_t Count register + ** + ******************************************************************************/ +uint16_t TIMER0_GetCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + uint16_t u16Value = 0u; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + u16Value = (uint16_t)((pstcTim0Reg->CNTAR)&0xFFFFu); + } + else + { + u16Value = (uint16_t)((pstcTim0Reg->CNTBR)&0xFFFFu); + } + + return u16Value; +} + +/** + ******************************************************************************* + ** \brief Write Timer0 counter register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] u16Cnt Data to write + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_WriteCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + uint16_t u16Cnt) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->CNTAR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CNTAR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->CNTBR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CNTBR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer0 base compare count register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval uint16_t Base compare count register + ** + ******************************************************************************/ +uint16_t TIMER0_GetCmpReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + uint16_t u16Value = 0u; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + u16Value = (uint16_t)((pstcTim0Reg->CMPAR)&0xFFFFu); + } + else + { + u16Value = (uint16_t)((pstcTim0Reg->CMPBR)&0xFFFFu); + } + return u16Value; +} + +/** + ******************************************************************************* + ** \brief Wirte Timer0 base compare count register + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] u16Cnt Data to write + ** + ** \retval Ok Success + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_WriteCmpReg(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh, + uint16_t u16Cnt) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + if(Tim0_ChannelA == enCh) + { + pstcTim0Reg->CMPAR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CMPAR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + else + { + pstcTim0Reg->CMPBR = (uint32_t)u16Cnt; + AsyncDelay(pstcTim0Reg, enCh, Disable); + while(u16Cnt != (uint16_t)pstcTim0Reg->CMPBR) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 peripheral base function initialize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] pstcBaseInit Timer0 function base parameter structure + ** + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_BaseInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + const stc_tim0_base_init_t* pstcBaseInit) +{ + stc_tmr0_bconr_field_t stcBconrTmp; + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + if (NULL != pstcBaseInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_CLK_DIVISION(pstcBaseInit->Tim0_ClockDivision)); + DDL_ASSERT(IS_VALID_CLK_SYN_SRC(pstcBaseInit->Tim0_SyncClockSource)); + DDL_ASSERT(IS_VALID_CLK_ASYN_SRC(pstcBaseInit->Tim0_AsyncClockSource)); + DDL_ASSERT(IS_VALID_CLK_MODE(pstcBaseInit->Tim0_CounterMode)); + + if((M4_TMR01 == pstcTim0Reg)&&(Tim0_ChannelA == enCh)) + { + DDL_ASSERT(IS_VALID_CLK_MODE_UNIT01(pstcBaseInit->Tim0_CounterMode)); + } + + /*Read current BCONR register */ + stcBconrTmp = pstcTim0Reg->BCONR_f; + /* Clear current configurate CH */ + if(Tim0_ChannelA == enCh) + { + *(uint32_t *)&stcBconrTmp &= 0xFFFF0000ul; + } + else + { + *(uint32_t *)&stcBconrTmp &= 0x0000FFFFul; + } + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(*(uint32_t *)&stcBconrTmp != *(uint32_t *)&(pstcTim0Reg->BCONR_f)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + switch(enCh) + { + case Tim0_ChannelA: + + switch(pstcBaseInit->Tim0_CounterMode) + { + case Tim0_Sync: + stcBconrTmp.SYNCLKA = pstcBaseInit->Tim0_SyncClockSource; + break; + case Tim0_Async: + stcBconrTmp.ASYNCLKA = pstcBaseInit->Tim0_AsyncClockSource; + break; + default: + break; + } + /*set clock division*/ + stcBconrTmp.CKDIVA = pstcBaseInit->Tim0_ClockDivision; + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer compare value*/ + pstcTim0Reg->CMPAR = pstcBaseInit->Tim0_CmpValue; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer counter mode*/ + pstcTim0Reg->BCONR_f.SYNSA = pstcBaseInit->Tim0_CounterMode; + AsyncDelay(pstcTim0Reg, enCh, Enable); + u32TimeOut = 0ul; + while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSA) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + break; + + case Tim0_ChannelB: + switch(pstcBaseInit->Tim0_CounterMode) + { + case Tim0_Sync: + stcBconrTmp.SYNCLKB = pstcBaseInit->Tim0_SyncClockSource; + break; + case Tim0_Async: + stcBconrTmp.ASYNCLKB = pstcBaseInit->Tim0_AsyncClockSource; + break; + default: + break; + } + /*set clock division*/ + stcBconrTmp.CKDIVB = pstcBaseInit->Tim0_ClockDivision; + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer compare value*/ + pstcTim0Reg->CMPBR = pstcBaseInit->Tim0_CmpValue; + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /*set timer counter mode*/ + pstcTim0Reg->BCONR_f.SYNSB = pstcBaseInit->Tim0_CounterMode; + AsyncDelay(pstcTim0Reg, enCh, Enable); + u32TimeOut = 0ul; + while(pstcBaseInit->Tim0_CounterMode != pstcTim0Reg->BCONR_f.SYNSB) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + break; + + default: + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timer0 peripheral base function initalize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \retval Ok Process finished. + ** \retval ErrorTimeout Process timeout + ** + ******************************************************************************/ +en_result_t TIMER0_DeInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh) +{ + en_result_t enRet = Ok; + uint32_t u32TimeOut = 0ul; + + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + + switch(enCh) + { + case Tim0_ChannelA: + pstcTim0Reg->BCONR &= 0xFFFF0000ul; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0ul != (pstcTim0Reg->BCONR & 0x0000FFFFul)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + pstcTim0Reg->CMPAR = 0x0000FFFFul; + pstcTim0Reg->CNTAR = 0x00000000ul; + pstcTim0Reg->STFLR_f.CMAF =0u; + break; + + case Tim0_ChannelB: + pstcTim0Reg->BCONR &= 0x0000FFFFul; + AsyncDelay(pstcTim0Reg, enCh, Enable); + while(0ul != (pstcTim0Reg->BCONR & 0xFFFF0000ul)) + { + if(u32TimeOut++ > TIMER0_TMOUT) + { + enRet = ErrorTimeout; + break; + } + } + + pstcTim0Reg->CMPBR = 0x0000FFFFul; + pstcTim0Reg->CNTBR = 0x00000000ul; + pstcTim0Reg->STFLR_f.CMBF =0u; + break; + default: + break; + } + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set external trigger source for Timer0 + ** + ** \param [in] enEvent External event source + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER0_SetTriggerSrc(en_event_src_t enEvent) +{ + DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(enEvent)); + + M4_AOS->TMR0_HTSSR_f.TRGSEL = enEvent; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer0 common trigger. + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_tim0_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER0_ComTriggerCmd(en_tim0_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIM0_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR0_HTSSR |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR0_HTSSR &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Timer0 hardware trigger function initalize + ** + ** \param [in] pstcTim0Reg Pointer to Timer0 register + ** + ** \param [in] enCh Timer0 channel, Tim0_ChannelA or Tim0_ChannelB + ** + ** \param [in] pStcInit Timer0 hareware trigger function structure + ** + ** \retval Ok Process finished. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TIMER0_HardTriggerInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh, + const stc_tim0_trigger_init_t* pStcInit) +{ + stc_tmr0_bconr_field_t stcBconrTmp; + en_result_t enRet = Ok; + + if(NULL != pStcInit) + { + DDL_ASSERT(IS_VALID_UNIT(pstcTim0Reg)); + DDL_ASSERT(IS_VALID_CHANNEL(enCh)); + DDL_ASSERT(IS_VALID_FUNCTION(pStcInit->Tim0_OCMode)); + DDL_ASSERT(IS_VALID_TRIG_SRC_EVENT(pStcInit->Tim0_SelTrigSrc)); + + /*Read current BCONR register */ + stcBconrTmp = pstcTim0Reg->BCONR_f; + + switch(enCh) + { + case Tim0_ChannelA: + /*set work on input captrue or output capare*/ + stcBconrTmp.CAPMDA = pStcInit->Tim0_OCMode; + /*enable input capture*/ + stcBconrTmp.HICPA = pStcInit->Tim0_InTrigEnable; + /*enable trigger clear counter*/ + stcBconrTmp.HCLEA = pStcInit->Tim0_InTrigClear; + /*enable trigger start counter*/ + stcBconrTmp.HSTAA = pStcInit->Tim0_InTrigStart; + /*enable trigger stop counter*/ + stcBconrTmp.HSTPA = pStcInit->Tim0_InTrigStop; + + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + break; + case Tim0_ChannelB: + /*set work on input captrue or output capare*/ + stcBconrTmp.CAPMDB = pStcInit->Tim0_OCMode; + /*enable input capture*/ + stcBconrTmp.HICPB = pStcInit->Tim0_InTrigEnable; + /*enable trigger clear counter*/ + stcBconrTmp.HCLEB = pStcInit->Tim0_InTrigClear; + /*enable trigger start counter*/ + stcBconrTmp.HSTAB = pStcInit->Tim0_InTrigStart; + /*enable trigger stop counter*/ + stcBconrTmp.HSTPB = pStcInit->Tim0_InTrigStop; + + /* Write BCONR register */ + pstcTim0Reg->BCONR_f = stcBconrTmp; + break; + default: + break; + } + AsyncDelay(pstcTim0Reg, enCh, Enable); + + /* Set trigger source*/ + M4_AOS->TMR0_HTSSR_f.TRGSEL = pStcInit->Tim0_SelTrigSrc; + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; + +} + +//@} // Timer0Group + +#endif /* DDL_TIMER0_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_cnt.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_cnt.c new file mode 100644 index 0000000000..1b655b4900 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_cnt.c @@ -0,0 +1,842 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_cnt.c + ** + ** A detailed description is available at + ** @link Timer4CntGroup Timer4CNT description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4CNT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_cnt.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_CNT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4CntGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for CNT pclk division */ +#define IS_VALID_CNT_CLK_DIV(x) \ +( (Timer4CntPclkDiv1 == (x)) || \ + (Timer4CntPclkDiv2 == (x)) || \ + (Timer4CntPclkDiv4 == (x)) || \ + (Timer4CntPclkDiv8 == (x)) || \ + (Timer4CntPclkDiv16 == (x)) || \ + (Timer4CntPclkDiv32 == (x)) || \ + (Timer4CntPclkDiv64 == (x)) || \ + (Timer4CntPclkDiv128 == (x)) || \ + (Timer4CntPclkDiv256 == (x)) || \ + (Timer4CntPclkDiv512 == (x)) || \ + (Timer4CntPclkDiv1024 == (x))) + +/*!< Parameter validity check for CNT mode */ +#define IS_VALID_CNT_MODE(x) \ +( (Timer4CntSawtoothWave == (x)) || \ + (Timer4CntTriangularWave == (x))) + +/*!< Parameter validity check for CNT interrupt mask */ +#define IS_VALID_CNT_INT_MSK(x) \ +( (Timer4CntIntMask0 == (x)) || \ + (Timer4CntIntMask1 == (x)) || \ + (Timer4CntIntMask2 == (x)) || \ + (Timer4CntIntMask3 == (x)) || \ + (Timer4CntIntMask4 == (x)) || \ + (Timer4CntIntMask5 == (x)) || \ + (Timer4CntIntMask6 == (x)) || \ + (Timer4CntIntMask7 == (x)) || \ + (Timer4CntIntMask8 == (x)) || \ + (Timer4CntIntMask9 == (x)) || \ + (Timer4CntIntMask10 == (x)) || \ + (Timer4CntIntMask11 == (x)) || \ + (Timer4CntIntMask12 == (x)) || \ + (Timer4CntIntMask13 == (x)) || \ + (Timer4CntIntMask14 == (x)) || \ + (Timer4CntIntMask15 == (x))) + +/*!< Parameter validity check for CNT match interrupt type */ +#define IS_VALID_CNT_INT_TYPE(x) \ +( (Timer4CntZeroMatchInt == (x)) || \ + (Timer4CntPeakMatchInt == (x))) + +/*!< Parameter validity check for CNT clock source */ +#define IS_VALID_CNT_CLK(x) \ +( (Timer4CntPclk == (x)) || \ + (Timer4CntExtclk == (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] pstcInitCfg Pointer to CNT initialization configuration structure + ** \arg This parameter detail refer @ref stc_timer4_cnt_init_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Init(M4_TMR4_TypeDef *TMR4x, + const stc_timer4_cnt_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + stc_tmr4_ccsr_field_t CCSR_f = {0}; + stc_tmr4_cvpr_field_t CVPR_f = {0}; + + /* Check for TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK(pstcInitCfg->enClk)); + DDL_ASSERT(IS_VALID_CNT_MODE(pstcInitCfg->enCntMode)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enBufferCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enZeroIntCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enPeakIntCmd)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enZeroIntMsk)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(pstcInitCfg->enPeakIntMsk)); + + /* Set default value */ + TMR4x->CCSR = (uint16_t)0x0050u; + TMR4x->CNTR = (uint16_t)0x0000u; + TMR4x->CPSR = (uint16_t)0xFFFFu; + TMR4x->CVPR = (uint16_t)0x0000u; + + /* stop count of CNT */ + CCSR_f.STOP = 1u; + + /* set count clock div of CNT */ + CCSR_f.CKDIV = pstcInitCfg->enClkDiv; + + /* set cnt mode */ + CCSR_f.MODE = pstcInitCfg->enCntMode; + + /* set buffer enable bit */ + CCSR_f.BUFEN = (uint16_t)(pstcInitCfg->enBufferCmd); + + /* set external clock enable bit */ + CCSR_f.ECKEN = (Timer4CntExtclk == pstcInitCfg->enClk) ? ((uint16_t)1u) : ((uint16_t)0u); + + /* Set interrupt enable */ + CCSR_f.IRQZEN = (uint16_t)(pstcInitCfg->enZeroIntCmd); + CCSR_f.IRQPEN = (uint16_t)(pstcInitCfg->enPeakIntCmd); + + /* set intterrupt mask times */ + CVPR_f.ZIM = (uint16_t)(pstcInitCfg->enZeroIntMsk); + CVPR_f.PIM = (uint16_t)(pstcInitCfg->enPeakIntMsk); + + /* Set Timer4 register */ + TMR4x->CVPR_f = CVPR_f; + TMR4x->CCSR_f = CCSR_f; + TMR4x->CPSR = pstcInitCfg->u16Cycle; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Set default value */ + TMR4x->CCSR = (uint16_t)0x0050u; + TMR4x->CNTR = (uint16_t)0x0000u; + TMR4x->CPSR = (uint16_t)0xFFFFu; + TMR4x->CVPR = (uint16_t)0x0000u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT clock source + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCntClk Timer4 CNT clock source + ** \arg Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock. + ** \arg Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock. + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_clk_t enCntClk) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK(enCntClk)); + /* set external clock enable bit */ + TMR4x->CCSR_f.ECKEN = (uint16_t)(enCntClk); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT clock source + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntPclk Uses the internal clock (PCLK) as CNT's count clock. + ** \retval Timer4CntExtclk Uses an external input clock (EXCK) as CNT's count clock. + ** + ******************************************************************************/ +en_timer4_cnt_clk_t TIMER4_CNT_GetClock(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_clk_t)(TMR4x->CCSR_f.ECKEN); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT clock division + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enClkDiv Timer4 CNT clock division + ** \arg Timer4CntPclkDiv1 Timer4 CNT clock: PCLK + ** \arg Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2 + ** \arg Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4 + ** \arg Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8 + ** \arg Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16 + ** \arg Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32 + ** \arg Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64 + ** \arg Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128 + ** \arg Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256 + ** \arg Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512 + ** \arg Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024 + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetClockDiv(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_clk_div_t enClkDiv) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(enClkDiv)); + TMR4x->CCSR_f.CKDIV = (uint16_t)enClkDiv; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT clock division + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntPclkDiv1 Timer4 CNT clock: PCLK + ** \retval Timer4CntPclkDiv2 Timer4 CNT clock: PCLK/2 + ** \retval Timer4CntPclkDiv4 Timer4 CNT clock: PCLK/4 + ** \retval Timer4CntPclkDiv8 Timer4 CNT clock: PCLK/8 + ** \retval Timer4CntPclkDiv16 Timer4 CNT clock: PCLK/16 + ** \retval Timer4CntPclkDiv32 Timer4 CNT clock: PCLK/32 + ** \retval Timer4CntPclkDiv64 Timer4 CNT clock: PCLK/64 + ** \retval Timer4CntPclkDiv128 Timer4 CNT clock: PCLK/128 + ** \retval Timer4CntPclkDiv256 Timer4 CNT clock: PCLK/256 + ** \retval Timer4CntPclkDiv512 Timer4 CNT clock: PCLK/512 + ** \retval Timer4CntPclkDiv1024 Timer4 CNT clock: PCLK/1024 + ** + ******************************************************************************/ +en_timer4_cnt_clk_div_t TIMER4_CNT_GetClockDiv(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_clk_div_t)(TMR4x->CCSR_f.CKDIV); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enMode Timer4 CNT mode + ** \arg Timer4CntSawtoothWave Timer4 count mode:sawtooth wave + ** \arg Timer4CntTriangularWave Timer4 count mode:triangular wave + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_MODE(enMode)); + TMR4x->CCSR_f.MODE = (uint16_t)enMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Timer4CntSawtoothWave Timer4 count mode:sawtooth wave + ** \retval Timer4CntTriangularWave Timer4 count mode:triangular wave + ** + ******************************************************************************/ +en_timer4_cnt_mode_t TIMER4_CNT_GetMode(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_cnt_mode_t)(TMR4x->CCSR_f.MODE); +} + +/** + ******************************************************************************* + ** \brief Start Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Start successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Start(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.STOP = (uint16_t)0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop Timer4 CNT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Stop successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_Stop(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.STOP = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT interrupt + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType The specified type of Timer4 CNT interrupt + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** \param [in] enCmd DCU interrupt functional state + ** \arg Enable Enable the specified Timer4 CNT interrupt function + ** \arg Disable Disable the specified Timer4 CNT interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - enIntType is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_IrqCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType, + en_functional_state_t enCmd) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CCSR_f.IRQZEN = (uint16_t)enCmd; + break; + case Timer4CntPeakMatchInt: + TMR4x->CCSR_f.IRQPEN = (uint16_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Reset None interrupt request on Timer4 CNT + ** \retval Set Detection interrupt request on Timer4 CNT + ** + ******************************************************************************/ +en_flag_status_t TIMER4_CNT_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + uint16_t u16Flag = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + switch (enIntType) + { + case Timer4CntZeroMatchInt: + u16Flag = TMR4x->CCSR_f.IRQZF; + break; + case Timer4CntPeakMatchInt: + u16Flag = TMR4x->CCSR_f.IRQPF; + break; + default: + break; + } + + return (en_flag_status_t)u16Flag; +} + +/** + ******************************************************************************* + ** \brief Clear Timer4 CNT interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TMR4x is invalid + ** - enIntType is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CCSR_f.IRQZF = (uint16_t)0u; + break; + case Timer4CntPeakMatchInt: + TMR4x->CCSR_f.IRQPF = (uint16_t)0u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the cycle value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] u16Cycle The Timer4 CNT cycle value + ** \arg number of 16bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Cycle) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CPSR = u16Cycle; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get the cycle value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval The cycle value of the specified Timer4 CNT. + ** + ******************************************************************************/ +uint16_t TIMER4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return TMR4x->CPSR; +} + +/** + ******************************************************************************* + ** \brief Clear Timer4 CNT register CNTR + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok Clear successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CCSR_f.CLEAR = (uint16_t)1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set the current count value of the specified Timer4 CNT. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] u16Count The Timer4 CNT current count value + ** \arg number of 16bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Count) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + TMR4x->CNTR = u16Count; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT current count value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval The current count value of the specified Timer4 CNT. + ** + ******************************************************************************/ +uint16_t TIMER4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return TMR4x->CNTR; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 CNT interrupt mask times + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** \param [in] enMaskTimes Timer4 CNT interrupt mask times + ** \arg Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak. + ** \arg Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count). + ** \arg Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count). + ** \arg Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count). + ** \arg Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count). + ** \arg Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count). + ** \arg Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count). + ** \arg Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count). + ** \arg Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count). + ** \arg Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count). + ** \arg Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count). + ** \arg Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count). + ** \arg Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count). + ** \arg Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count). + ** \arg Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count). + ** \arg Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count). + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType, + en_timer4_cnt_int_mask_t enMaskTimes) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + DDL_ASSERT(IS_VALID_CNT_INT_MSK(enMaskTimes)); + + enRet = Ok; + switch (enIntType) + { + case Timer4CntZeroMatchInt: + TMR4x->CVPR_f.ZIM = (uint16_t)enMaskTimes; + break; + case Timer4CntPeakMatchInt: + TMR4x->CVPR_f.PIM = (uint16_t)enMaskTimes; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 CNT interrupt mask times + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enIntType Timer4 CNT interrupt type + ** \arg Timer4CntZeroMatchIrq Zero match interrupt of Timer4 CNT + ** \arg Timer4CntPeakMatchIrq Peak match interrupt of Timer4 CNT + ** + ** \retval Timer4CntIntMask0 CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak. + ** \retval Timer4CntIntMask1 CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count). + ** \retval Timer4CntIntMask2 CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count). + ** \retval Timer4CntIntMask3 CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count). + ** \retval Timer4CntIntMask4 CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count). + ** \retval Timer4CntIntMask5 CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count). + ** \retval Timer4CntIntMask6 CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count). + ** \retval Timer4CntIntMask7 CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count). + ** \retval Timer4CntIntMask8 CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count). + ** \retval Timer4CntIntMask9 CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count). + ** \retval Timer4CntIntMask10 CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count). + ** \retval Timer4CntIntMask11 CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count). + ** \retval Timer4CntIntMask12 CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count). + ** \retval Timer4CntIntMask13 CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count). + ** \retval Timer4CntIntMask14 CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count). + ** \retval Timer4CntIntMask15 CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count). + ** + ******************************************************************************/ +en_timer4_cnt_int_mask_t TIMER4_CNT_GetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_cnt_int_t enIntType) +{ + uint16_t u16MaskTimes = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_CNT_INT_TYPE(enIntType)); + + switch (enIntType) + { + case Timer4CntZeroMatchInt: + u16MaskTimes = TMR4x->CVPR_f.ZIM; + break; + case Timer4CntPeakMatchInt: + u16MaskTimes = TMR4x->CVPR_f.PIM; + break; + default: + break; + } + + return (en_timer4_cnt_int_mask_t)u16MaskTimes; +} + +//@} // Timer4CntGroup + +#endif /* DDL_TIMER4_CNT_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_emb.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_emb.c new file mode 100644 index 0000000000..b47a0f026f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_emb.c @@ -0,0 +1,278 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_emb.c + ** + ** A detailed description is available at + ** @link Timer4EmbGroup Timer4EMB description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4EMB. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_emb.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_EMB_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4EmbGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter valid check for EMB HOLD mode. */ +#define IS_VALID_EMB_HOLD_MODE(x) \ +( (EmbHoldPwm == (x)) || \ + (EmbChangePwm == (x))) + +/*!< Parameter valid check for EMB state. */ +#define IS_VALID_EMB_STATE(x) \ +( (EmbTrigPwmOutputHiz == (x)) || \ + (EmbTrigPwmOutputNormal == (x)) || \ + (EmbTrigPwmOutputLowLevel == (x)) || \ + (EmbTrigPwmOutputHighLevel == (x))) + +/*!< Timer4x ECER register address. */ +#define TMR4_ECERx(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) ? &M4_TMR4_CR->ECER1 : \ + ((M4_TMR42 == (__TMRx__)) ? &M4_TMR4_CR->ECER2 : &M4_TMR4_CR->ECER3)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize Timer4 EMB + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] pstcInitCfg The pointer of EMB configure structure + ** \arg This parameter detail refer @ref stc_timer4_emb_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_Init(M4_TMR4_TypeDef *TMR4x, + const stc_timer4_emb_init_t *pstcInitCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATE(pstcInitCfg->enEmbState)); + DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(pstcInitCfg->enPwmHold)); + + /* Set EMB HOLD mode */ + TMR4x->ECSR_f.HOLD = (uint16_t)(pstcInitCfg->enPwmHold); + + /* Set EMB state */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)(pstcInitCfg->enEmbState); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-initialize Timer4 EMB + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval Ok De-Initialize successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Set reset value(0x0000) to register ESCR */ + TMR4x->ECSR = 0u; + + /* Set reset value(0x0000) to register ECER */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)0ul; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 EMB HOLD mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enHoldMode EMB HOLD mode + ** \arg EmbChangePwm Don't hold PWM output when EMB signal occurs + ** \arg EmbHoldPwm Hold PWM output when EMB signal occurs + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_SetHoldMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_emb_hold_mode_t enHoldMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_HOLD_MODE(enHoldMode)); + + /* Set EMB HOLD mode */ + TMR4x->ECSR_f.HOLD = (uint16_t)enHoldMode; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 EMB HOLD mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval EmbChangePwm Don't hold PWM output when EMB signal occurs + ** \retval EmbHoldPwm Hold PWM output when EMB signal occurs + ** + ******************************************************************************/ +en_timer4_emb_hold_mode_t TIMER4_EMB_GetHoldMode(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return (en_timer4_emb_hold_mode_t)(TMR4x->ECSR_f.HOLD); +} + +/** + ******************************************************************************* + ** \brief Set Timer4 EMB state + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enEmbState EMB state + ** \arg EmbTrigPwmOutputNormal PWM output signal normally. + ** \arg EmbTrigPwmOutputHiz PWM output Hiz signal. + ** \arg EmbTrigPwmOutputLowLevel PWM output low level signal. + ** \arg EmbTrigPwmOutputHighLevel PWM output high level signal. + ** + ** \retval Ok Set successfully + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_EMB_SetState(const M4_TMR4_TypeDef *TMR4x, + en_timer4_emb_state_t enEmbState) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_STATE(enEmbState)); + + /* Set EMB state */ + *(__IO uint32_t *)TMR4_ECERx(TMR4x) = (uint32_t)enEmbState; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 EMB state + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** + ** \retval EmbTrigPwmOutputNormal PWM output signal normally. + ** \retval EmbTrigPwmOutputHiz PWM output Hiz signal. + ** \retval EmbTrigPwmOutputLowLevel PWM output low level signal. + ** \retval EmbTrigPwmOutputHighLevel PWM output high level signal. + ** + ******************************************************************************/ +en_timer4_emb_state_t TIMER4_EMB_GetState(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + return *(__IO en_timer4_emb_state_t *)TMR4_ECERx(TMR4x); +} + +//@} // Timer4EmbGroup + +#endif /* DDL_TIMER4_EMB_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_oco.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_oco.c new file mode 100644 index 0000000000..25281dfb27 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_oco.c @@ -0,0 +1,1295 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_oco.c + ** + ** A detailed description is available at + ** @link Timer4OcoGroup Timer4OCO description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4OCO. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_oco.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_OCO_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4OcoGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for oco channel */ +#define IS_VALID_OCO_CH(x) \ +( (Timer4OcoOuh == (x)) || \ + (Timer4OcoOul == (x)) || \ + (Timer4OcoOvh == (x)) || \ + (Timer4OcoOvl == (x)) || \ + (Timer4OcoOwh == (x)) || \ + (Timer4OcoOwl == (x))) + +/*!< Parameter validity check for oco low channel */ +#define IS_VALID_OCO_LOW_CH(x) \ +( (Timer4OcoOul == (x)) || \ + (Timer4OcoOvl == (x)) || \ + (Timer4OcoOwl == (x))) + +/*!< Parameter validity check for even high channel */ +#define IS_VALID_OCO_HIGH_CH(x) \ +( (Timer4OcoOuh == (x)) || \ + (Timer4OcoOvh == (x)) || \ + (Timer4OcoOwh == (x))) + +/*!< Parameter validity check for occr buffer mode */ +#define IS_VALID_OCCR_BUF_MODE(x) \ +( (OccrBufDisable == (x)) || \ + (OccrBufTrsfByCntZero == (x)) || \ + (OccrBufTrsfByCntPeak == (x)) || \ + (OccrBufTrsfByCntZeroOrCntPeak == (x)) || \ + (OccrBufTrsfByCntZeroZicZero == (x)) || \ + (OccrBufTrsfByCntPeakPicZero == (x)) || \ + (OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for ocmr buffer mode */ +#define IS_VALID_OCMR_BUF_MODE(x) \ +( (OcmrBufDisable == (x)) || \ + (OcmrBufTrsfByCntZero == (x)) || \ + (OcmrBufTrsfByCntPeak == (x)) || \ + (OcmrBufTrsfByCntZeroOrCntPeak == (x)) || \ + (OcmrBufTrsfByCntZeroZicZero == (x)) || \ + (OcmrBufTrsfByCntPeakPicZero == (x)) || \ + (OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for output level type */ +#define IS_VALID_OP_PORT_LEVEL(x) \ +( (OcPortLevelLow == (x)) || \ + (OcPortLevelHigh == (x))) + +/*!< Parameter validity check for oco OP state */ +#define IS_VALID_OP_STATE(x) \ +( (OcoOpOutputLow == (x)) || \ + (OcoOpOutputHigh == (x)) || \ + (OcoOpOutputHold == (x)) || \ + (OcoOpOutputReverse == (x))) + +/*!< Parameter validity check for oco OCF state */ +#define IS_VALID_OCF_STATE(x) \ +( (OcoOcfSet == (x)) || \ + (OcoOcfHold == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_OCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCCRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_OCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCMRHUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_OCERx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCERU + (((uint32_t)(__CH__))/2ul)*4ul) +#define TMR4_OCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->OCSRU + (((uint32_t)(__CH__))/2ul)*4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize OCO module + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcInitCfg The pointer of OCO configure structure + ** \arg This parameter detail refer @ref stc_timer4_oco_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_timer4_oco_init_t* pstcInitCfg) +{ + __IO stc_tmr4_ocsr_field_t* pstcOCSR = NULL; + __IO stc_tmr4_ocer_field_t* pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enOcoIntCmd)); + DDL_ASSERT(IS_VALID_OP_PORT_LEVEL(pstcInitCfg->enPortLevel)); + DDL_ASSERT(IS_VALID_OCMR_BUF_MODE(pstcInitCfg->enOcmrBufMode)); + DDL_ASSERT(IS_VALID_OCCR_BUF_MODE(pstcInitCfg->enOccrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x,enCh); + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x,enCh); + + /* Set OCMR and OCCR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + pstcOCSR->OCEH = (uint16_t)0u; + pstcOCSR->OCFH = (uint16_t)0u; + + /* OCMR buffer */ + switch (pstcInitCfg->enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + /* OCCR buffer */ + switch (pstcInitCfg->enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (enRet == Ok) + { + /* Set initial OP level */ + pstcOCSR->OCPH = (uint16_t)(pstcInitCfg->enPortLevel); + /* set interrupt enable */ + pstcOCSR->OCIEH = (uint16_t)(pstcInitCfg->enOcoIntCmd); + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + pstcOCSR->OCEL = (uint16_t)0u; + pstcOCSR->OCFL = (uint16_t)0u; + + /* OCMR buffer */ + switch (pstcInitCfg->enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (enRet == Ok) + { + /* OCCR buffer */ + switch (pstcInitCfg->enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + if (enRet == Ok) + { + /* Set initial OP level */ + pstcOCSR->OCPL = (uint16_t)(pstcInitCfg->enPortLevel); + /* set interrupt enable */ + pstcOCSR->OCIEL = (uint16_t)(pstcInitCfg->enOcoIntCmd); + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize OCO module + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO uint16_t* pu16OCCR = NULL; + __IO uint32_t u32OCMR = 0ul; + __IO stc_tmr4_ocsr_field_t* pstcOCSR = NULL; + __IO stc_tmr4_ocer_field_t* pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + u32OCMR = TMR4_OCMRx(TMR4x, enCh); + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set default value */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + pstcOCSR->OCEH = (uint16_t)0u; + pstcOCSR->OCFH = (uint16_t)0u; + pstcOCSR->OCIEH = (uint16_t)0u; + pstcOCSR->OCPH = (uint16_t)0u; + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + pstcOCER->MCECH = (uint16_t)0u; + *pu16OCCR = (uint16_t)0u; + *(__IO uint16_t*)u32OCMR = (uint16_t)0u; + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + pstcOCSR->OCEL = (uint16_t)0u; + pstcOCSR->OCFL = (uint16_t)0u; + pstcOCSR->OCIEL = (uint16_t)0u; + pstcOCSR->OCPL = (uint16_t)0u; + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + pstcOCER->MCECL = (uint16_t)0u; + *pu16OCCR = (uint16_t)0u; + *(__IO uint32_t*)u32OCMR = (uint32_t)0ul; + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set occr buffer mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enOccrBufMode Occr buffer mode + ** \arg OccrBufDisable Disable the register buffer function + ** \arg OccrBufTrsfByCntZero Register buffer transfer when counter value is 0x0000 + ** \arg OccrBufTrsfByCntPeak Register buffer transfer when counter value is CPSR + ** \arg OccrBufTrsfByCntZeroOrCntPeak Register buffer transfer when the value is both 0 and CPSR + ** \arg OccrBufTrsfByCntZeroZicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + ** \arg OccrBufTrsfByCntPeakPicZero Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0 ** + ** \arg OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ** counter value is CPSR and peak value detection mask counter value is 0 + ** \retval Ok OCO occr buffer mode initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** - enOccrBufMode is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOccrBufMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_occr_buf_t enOccrBufMode) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OCCR_BUF_MODE(enOccrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set OCCR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + /* OCCR buffer */ + switch (enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCH = (uint16_t)0u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCH = (uint16_t)1u; + pstcOCER->CHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + /* OCCR buffer */ + switch (enOccrBufMode) + { + case OccrBufDisable: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)0u; + break; + case OccrBufTrsfByCntZero: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMCL = (uint16_t)0u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + case OccrBufTrsfByCntZeroZicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)1u; + break; + case OccrBufTrsfByCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)2u; + break; + case OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMCL = (uint16_t)1u; + pstcOCER->CLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set occr buffer mode + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enOcmrBufMode Occr buffer mode + ** \arg OcmrBufDisable Disable the register buffer function + ** \arg OcmrBufTrsfByCntZero Register buffer transfer when counter value is 0x0000 + ** \arg OcmrBufTrsfByCntPeak Register buffer transfer when counter value is CPSR + ** \arg OcmrBufTrsfByCntZeroOrCntPeak Register buffer transfer when the value is both 0 and CPSR + ** \arg OcmrBufTrsfByCntZeroZicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + ** \arg OcmrBufTrsfByCntPeakPicZero Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0 ** + ** \arg OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ** counter value is CPSR and peak value detection mask counter value is 0 + ** + ** \retval Ok OCO ocmr buffer mode initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh is invalid + ** - enOcmrBufMode is invalid. + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOcmrBufMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_ocmr_buf_t enOcmrBufMode) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OCMR_BUF_MODE(enOcmrBufMode)); + + enRet = Ok; + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + /* Set OCMR buffer mode */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + /* OCMR buffer */ + switch (enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMMH = (uint16_t)0u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMMH = (uint16_t)1u; + pstcOCER->MHBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + /* OCMR buffer */ + switch (enOcmrBufMode) + { + case OcmrBufDisable: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)0u; + break; + case OcmrBufTrsfByCntZero: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroOrCntPeak: + pstcOCER->LMML = (uint16_t)0u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + case OcmrBufTrsfByCntZeroZicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)1u; + break; + case OcmrBufTrsfByCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)2u; + break; + case OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero: + pstcOCER->LMML = (uint16_t)1u; + pstcOCER->MLBUFEN = (uint16_t)3u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Extend the matching determination conditions of OCO channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd Extend the match conditions functional state + ** \arg Enable Extend the match conditions function + ** \arg Disable Don't extend the match conditions function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_ExtMatchCondCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCER->MCECH = (uint16_t)enCmd) : (pstcOCER->MCECL = (uint16_t)enCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set compare mode of OCO high channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcMode pointer to structure of compare mode + ** \arg This parameter detail refer @ref stc_oco_high_ch_compare_mode_t + ** + ** \retval Ok OCO high channel compare mode is set successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcMode pointer is NULL + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetHighChCompareMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_oco_high_ch_compare_mode_t *pstcMode) +{ + uint16_t u16OCMR = 0u; + __IO uint16_t *pu16OCMR = NULL; + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcMode pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcMode)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_HIGH_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroNotMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakNotMatchOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownCntMatchOpState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntZeroMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntUpCntMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntPeakMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntDownCntMatchOcfState)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcMode->enMatchConditionExtendCmd)); + + /* Get pointer of current channel OCO register address */ + pu16OCMR = (__IO uint16_t*)TMR4_OCMRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh); + + pstcOCER->MCECH = (uint16_t)(pstcMode->enMatchConditionExtendCmd); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroMatchOpState << 10u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroNotMatchOpState << 14u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntUpCntMatchOpState << 8u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakMatchOpState << 6u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakNotMatchOpState << 12u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntDownCntMatchOpState << 4u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntZeroMatchOcfState << 3u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntUpCntMatchOcfState << 2u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntPeakMatchOcfState << 1u); + u16OCMR |= (uint16_t)((uint16_t)pstcMode->enCntDownCntMatchOcfState << 0u); + + *pu16OCMR = u16OCMR; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set compare mode of OCO low channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] pstcMode pointer to structure of compare mode + ** \arg This parameter detail refer @ref TIMER4_OCO_SetLowChCompareMode + ** + ** \retval Ok OCO low channel compare mode is set successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcMode pointer is NULL + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetLowChCompareMode(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + const stc_oco_low_ch_compare_mode_t *pstcMode) +{ + uint32_t u32OCMR = 0ul; + __IO uint32_t *pu32OCMR = NULL; + __IO stc_tmr4_ocer_field_t *pstcOCER = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer and pstcMode pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcMode)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_LOW_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntZeroLowNotMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntUpCntLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntPeakLowNotMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowMatchHighNotMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OP_STATE(pstcMode->enCntDownLowNotMatchHighMatchLowChOpState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntZeroMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntUpCntMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntPeakMatchOcfState)); + DDL_ASSERT(IS_VALID_OCF_STATE(pstcMode->enCntDownCntMatchOcfState)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcMode->enMatchConditionExtendCmd)); + + /* Get pointer of current channel OCO register address */ + pu32OCMR = (__IO uint32_t*)TMR4_OCMRx(TMR4x, enCh); + pstcOCER = (__IO stc_tmr4_ocer_field_t*)TMR4_OCERx(TMR4x, enCh);; + + pstcOCER->MCECL = (uint16_t)(pstcMode->enMatchConditionExtendCmd); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowMatchHighMatchLowChOpState << 26u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowMatchHighNotMatchLowChOpState << 10u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowNotMatchHighMatchLowChOpState << 30u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroLowNotMatchHighNotMatchLowChOpState << 14u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowMatchHighMatchLowChOpState << 24u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowMatchHighNotMatchLowChOpState << 8u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntLowNotMatchHighMatchLowChOpState << 18u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowMatchHighMatchLowChOpState << 22u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowMatchHighNotMatchLowChOpState << 6u) ; + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowNotMatchHighMatchLowChOpState << 28u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakLowNotMatchHighNotMatchLowChOpState << 12u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowMatchHighMatchLowChOpState << 20u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowMatchHighNotMatchLowChOpState << 4u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownLowNotMatchHighMatchLowChOpState << 16u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntZeroMatchOcfState << 3u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntUpCntMatchOcfState << 2u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntPeakMatchOcfState << 1u); + u32OCMR |= (uint32_t)((uint32_t)pstcMode->enCntDownCntMatchOcfState << 0u); + + *pu32OCMR = u32OCMR; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set output function + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd The output functional state + ** \arg Enable Enable output function + ** \arg Disable Disable output function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_OutputCompareCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + /* set register */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCEH = (uint16_t)enCmd) : (pstcOCSR->OCEL = (uint16_t)enCmd); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set OCO interrupt function + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enCmd The interrupt functional state + ** \arg Enable Enable interrupt function + ** \arg Disable Disable interrupt function + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_IrqCmd(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_functional_state_t enCmd) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enCmd)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + /* set register */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCIEH = (uint16_t)enCmd) : (pstcOCSR->OCIEL = (uint16_t)enCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OCO interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Reset None interrupt request on Timer4 OCO + ** \retval Set Detection interrupt request on Timer4 OCO + ** + ******************************************************************************/ +en_flag_status_t TIMER4_OCO_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + en_flag_status_t enFlag = Reset; + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + /* set return value */ + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + enFlag = (en_flag_status_t)(pstcOCSR->OCFH); + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + enFlag = (en_flag_status_t)(pstcOCSR->OCFL); + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + return enFlag; +} + +/** + ******************************************************************************* + ** \brief Clear OCO interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval Ok OCO interrupt flag is clear + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + /* set return value */ + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCFH = 0u) : (pstcOCSR->OCFL = 0u); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set OP pin level of OCO + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] enLevel OP port level of OCO + ** \arg OcPortLevelLow Output low level to OC port + ** \arg OcPortLevelHigh Output high level to OC port + ** + ** \retval Ok OCO interrupt flag is clear + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_SetOpPortLevel(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + en_timer4_oco_port_level_t enLevel) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_OP_PORT_LEVEL(enLevel)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + IS_VALID_OCO_HIGH_CH(enCh) ? (pstcOCSR->OCFH = (uint16_t)enLevel) : (pstcOCSR->OCFL = (uint16_t)enLevel); + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OP pin level of OCO + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval OcPortLevelLow Output low level to OC port + ** \retval OcPortLevelHigh Output high level to OC port + ** + ******************************************************************************/ +en_timer4_oco_port_level_t TIMER4_OCO_GetOpPinLevel(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO stc_tmr4_ocsr_field_t *pstcOCSR = NULL; + en_timer4_oco_port_level_t enLevel = OcPortLevelLow; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel OCO register address */ + pstcOCSR = (__IO stc_tmr4_ocsr_field_t*)TMR4_OCSRx(TMR4x, enCh); + + if (IS_VALID_OCO_HIGH_CH(enCh)) /* channel: Timer4OcoOuh, Timer4OcoOvh, Timer4OcoOwh */ + { + enLevel = (en_timer4_oco_port_level_t)(pstcOCSR->OCPH); + } + else if (IS_VALID_OCO_LOW_CH(enCh)) /* channel: Timer4OcoOul, Timer4OcoOvl, Timer4OcoOwl */ + { + enLevel = (en_timer4_oco_port_level_t)(pstcOCSR->OCPL); + } + else + { + /* Do nothing: only avoid MISRA warning */ + } + + return enLevel; +} + +/** + ******************************************************************************* + ** \brief Write OCCR register + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** \param [in] u16Occr The value of occr + ** \arg 16bit value + ** + ** \retval Ok OCCR written + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_OCO_WriteOccr(M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh, + uint16_t u16Occr) +{ + __IO uint16_t *pu16OCCR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + /* set register */ + *pu16OCCR = u16Occr; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get OCCR register value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of OCO + ** \arg Timer4OcoOuh Timer oco channel:OUH + ** \arg Timer4OcoOul Timer oco channel:OUL + ** \arg Timer4OcoOvh Timer oco channel:OVH + ** \arg Timer4OcoOvl Timer oco channel:OVL + ** \arg Timer4OcoOwh Timer oco channel:OWH + ** \arg Timer4OcoOwl Timer oco channel:OWL + ** + ** \retval OCCR register value + ** + ******************************************************************************/ +uint16_t TIMER4_OCO_ReadOccr(const M4_TMR4_TypeDef *TMR4x, + en_timer4_oco_ch_t enCh) +{ + __IO uint16_t* pu16OCCR = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_OCO_CH(enCh)); + + /* Get pointer of current channel OCO register address */ + pu16OCCR = (__IO uint16_t*)TMR4_OCCRx(TMR4x, enCh); + + return (*pu16OCCR); +} + +//@} // Timer4OcoGroup + +#endif /* DDL_TIMER4_OCO_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_pwm.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_pwm.c new file mode 100644 index 0000000000..0a1c9836ef --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_pwm.c @@ -0,0 +1,600 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_pwm.c + ** + ** A detailed description is available at + ** @link Timer4PwmGroup Timer4PWM description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4PWM. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_pwm.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_PWM_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4PwmGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for PWM channel */ +#define IS_VALID_PWM_CH(x) \ +( (Timer4PwmU == (x)) || \ + (Timer4PwmV == (x)) || \ + (Timer4PwmW == (x))) + +/*!< Parameter validity check for PWM mode */ +#define IS_VALID_PWM_MODE(x) \ +( (PwmThroughMode == (x)) || \ + (PwmDeadTimerMode == (x)) || \ + (PwmDeadTimerFilterMode == (x))) + +/*!< Parameter valid check for PWM output state. */ +#define IS_VALID_PWM_OUTPUT_STATE(x) \ +( (PwmHPwmLHold == (x)) || \ + (PwmHPwmLReverse == (x)) || \ + (PwmHReversePwmLHold == (x)) || \ + (PwmHHoldPwmLReverse == (x))) + +/*!< Parameter valid check for PWM clock division. */ +#define IS_VALID_PWM_CLK_DIV(x) \ +( (PwmPlckDiv1 == (x)) || \ + (PwmPlckDiv2 == (x)) || \ + (PwmPlckDiv4 == (x)) || \ + (PwmPlckDiv8 == (x)) || \ + (PwmPlckDiv16 == (x)) || \ + (PwmPlckDiv32 == (x)) || \ + (PwmPlckDiv64 == (x)) || \ + (PwmPlckDiv128 == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_RCSRx(__TMR4x__) ((uint32_t)&(__TMR4x__)->RCSR) +#define TMR4_POCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->POCRU + ((uint32_t)(__CH__))*4ul) +#define TMR4_PDARx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDARU + ((uint32_t)(__CH__))*8ul) +#define TMR4_PDBRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PDBRU + ((uint32_t)(__CH__))*8ul) +#define TMR4_PFSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->PFSRU + ((uint32_t)(__CH__))*8ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize a couple PWM channels + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] pstcInitCfg The pointer of PWM configure structure + ** \arg This parameter detail refer @ref stc_timer4_pwm_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + const stc_timer4_pwm_init_t *pstcInitCfg) +{ + __IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + en_result_t enRet = Ok; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_MODE(pstcInitCfg->enMode)); + DDL_ASSERT(IS_VALID_PWM_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enRtIntMaskCmd)); + DDL_ASSERT(IS_VALID_PWM_OUTPUT_STATE(pstcInitCfg->enOutputState)); + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh); + + /* Configure PWM mode */ + pstcPOCR_f->PWMMD = (uint16_t)(pstcInitCfg->enMode); + + /* Configure PWM mode */ + pstcPOCR_f->LVLS = (uint16_t)(pstcInitCfg->enOutputState); + + /* Set timer clock division */ + pstcPOCR_f->DIVCK = (uint16_t)(pstcInitCfg->enClkDiv); + + /* Set interrupt mask */ + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTIDU = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + case Timer4PwmV: + pstcRCSR_f->RTIDV = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + case Timer4PwmW: + pstcRCSR_f->RTIDW = (uint16_t)(pstcInitCfg->enRtIntMaskCmd); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize a couple PWM channels + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = Ok; + __IO uint16_t *pu16PDAR = NULL; + __IO uint16_t *pu16PDBR = NULL; + __IO uint16_t *pu16PFSR = NULL; + __IO stc_tmr4_pocr_field_t *pstcPOCR_f = NULL; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Get pointer of current channel PWM register address */ + pu16PDAR = (__IO uint16_t*)TMR4_PDARx(TMR4x, enCh); + pu16PDBR = (__IO uint16_t*)TMR4_PDBRx(TMR4x, enCh); + pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh); + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + pstcPOCR_f = (__IO stc_tmr4_pocr_field_t*)TMR4_POCRx(TMR4x, enCh); + + *pu16PDAR = (uint16_t)0u; + *pu16PDBR = (uint16_t)0u; + *pu16PFSR = (uint16_t)0u; + pstcPOCR_f->DIVCK = (uint16_t)0u; + pstcPOCR_f->LVLS = (uint16_t)0u; + pstcPOCR_f->PWMMD = (uint16_t)0u; + + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTIDU = (uint16_t)0u; + break; + case Timer4PwmV: + pstcRCSR_f->RTIDV = (uint16_t)0u; + break; + case Timer4PwmW: + pstcRCSR_f->RTIDW = (uint16_t)0u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok Start timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_StartTimer(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTEU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTEV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTEW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Stop PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok Stop timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_StopTimer(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + enRet = Ok; + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTSU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTSV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTSW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get PWM reload-timer interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Reset None interrupt request on PWM reload-timer + ** \retval Set Detection interrupt request on PWM reload-timer + ** + ******************************************************************************/ +en_flag_status_t TIMER4_PWM_GetIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + uint16_t u16Flag = 0u; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + + switch (enCh) + { + case Timer4PwmU: + u16Flag = pstcRCSR_f->RTIFU; + break; + case Timer4PwmV: + u16Flag = pstcRCSR_f->RTIFV; + break; + case Timer4PwmW: + u16Flag = pstcRCSR_f->RTIFW; + break; + default: + break; + } + + return (en_flag_status_t)u16Flag; +} + +/** + ******************************************************************************* + ** \brief Clear PWM reload-timer interrupt flag + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** + ** \retval Ok PWM reload-timer interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - enCh out of range + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmr4_rcsr_field_t *pstcRCSR_f = NULL; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + enRet = Ok; + /* Get pointer of current channel PWM register address */ + pstcRCSR_f = (__IO stc_tmr4_rcsr_field_t*)TMR4_RCSRx(TMR4x); + switch (enCh) + { + case Timer4PwmU: + pstcRCSR_f->RTICU = (uint16_t)1u; + break; + case Timer4PwmV: + pstcRCSR_f->RTICV = (uint16_t)1u; + break; + case Timer4PwmW: + pstcRCSR_f->RTICW = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write timer count cycle + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] u16PDAR PDAR value + ** \arg 0~65535 + ** \param [in] u16PDBR PDBR value + ** \arg 0~65535 + ** + ** \retval Ok Timer count cycle is written + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_WriteDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t u16PDAR, + uint16_t u16PDBR) +{ + __IO uint16_t *pu16PDAR = NULL; + __IO uint16_t *pu16PDBR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + pu16PDAR = (__IO uint16_t *)TMR4_PDARx(TMR4x, enCh); + pu16PDBR = (__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh); + + /* set the register */ + *pu16PDAR = u16PDAR; + *pu16PDBR = u16PDBR; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read dead region count value + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [out] u16PDAR Pointer of uint16_t type + ** \arg 0~65535 + ** \param [out] u16PDBR Pointer of uint16_t type + ** \arg 0~65535 + ** + ** \retval Ok Read successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_ReadDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t *u16PDAR, + uint16_t *u16PDBR) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + *u16PDAR = *(__IO uint16_t *)TMR4_PDARx(TMR4x, enCh); + *u16PDBR = *(__IO uint16_t *)TMR4_PDBRx(TMR4x, enCh); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set cycle of PWM timer + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Channel of PWM + ** \arg Timer4PwmOuhl Timer4 PWM couple channel OUH&OUL + ** \arg Timer4PwmOvhl Timer4 PWM couple channel OVH&OVL + ** \arg Timer4PwmOwhl Timer4 PWM couple channel OWH&OWL + ** \param [in] u16Count PWM pulse counter value + ** \arg 0~65535 + ** + ** \retval Ok Cycle of PWM timer is set + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_PWM_SetFilterCountValue(M4_TMR4_TypeDef *TMR4x, + en_timer4_pwm_ch_t enCh, + uint16_t u16Count) +{ + __IO uint16_t *pu16PFSR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_PWM_CH(enCh)); + + /* Get pointer of current channel PWM register address */ + pu16PFSR = (__IO uint16_t*)TMR4_PFSRx(TMR4x, enCh); + *pu16PFSR =u16Count; + + enRet = Ok; + } + + return enRet; +} + +//@} // Timer4PwmGroup + +#endif /* DDL_TIMER4_PWM_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_sevt.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_sevt.c new file mode 100644 index 0000000000..e2724a2250 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer4_sevt.c @@ -0,0 +1,593 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer4_sevt.c + ** + ** A detailed description is available at + ** @link Timer4SevtGroup Timer4SEVT description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library of Timer4SEVT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer4_sevt.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER4_SEVT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer4SevtGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter validity check for Timer4 unit */ +#define IS_VALID_TIMER4(__TMRx__) \ +( (M4_TMR41 == (__TMRx__)) || \ + (M4_TMR42 == (__TMRx__)) || \ + (M4_TMR43 == (__TMRx__))) + +/*!< Parameter validity check for SEVT channel */ +#define IS_VALID_SEVT_CH(x) \ +( (Timer4SevtCh0 == (x)) || \ + (Timer4SevtCh1 == (x)) || \ + (Timer4SevtCh2 == (x)) || \ + (Timer4SevtCh3 == (x)) || \ + (Timer4SevtCh4 == (x)) || \ + (Timer4SevtCh5 == (x))) + +/*!< Parameter validity check for adct buffer mode */ +#define IS_VALID_SEVT_BUF_MODE(x) \ +( (SevtBufDisable == (x)) || \ + (SevtBufCntZero == (x)) || \ + (SevtBufCntPeak == (x)) || \ + (SevtBufCntZeroOrCntPeak == (x)) || \ + (SevtBufCntZeroZicZero == (x)) || \ + (SevtBufCntPeakPicZero == (x)) || \ + (SevtBufCntZeroZicZeroOrCntPeakPicZero == (x))) + +/*!< Parameter validity check for SEVT trigger event */ +#define IS_VALID_SEVT_TRG_EVT(x) \ +( (SevtTrgEvtSCMUH == (x)) || \ + (SevtTrgEvtSCMUL == (x)) || \ + (SevtTrgEvtSCMVH == (x)) || \ + (SevtTrgEvtSCMVL == (x)) || \ + (SevtTrgEvtSCMWH == (x)) || \ + (SevtTrgEvtSCMWL == (x))) + +/*!< Parameter validity check for SEVT OCCR selection */ +#define IS_VALID_SEVT_OCCR_SEL(x) \ +( (SevtSelOCCRxh == (x)) || \ + (SevtSelOCCRxl == (x))) + +/*!< Parameter validity check for SEVT running mode */ +#define IS_VALID_SEVT_MODE(x) \ +( (SevtDelayTrigMode == (x)) || \ + (SevtCompareTrigMode == (x))) + +/*!< Parameter validity check for SEVT mask time */ +#define IS_VALID_SEVT_MSK(x) \ +( (Timer4SevtMask0 == (x)) || \ + (Timer4SevtMask1 == (x)) || \ + (Timer4SevtMask2 == (x)) || \ + (Timer4SevtMask3 == (x)) || \ + (Timer4SevtMask4 == (x)) || \ + (Timer4SevtMask5 == (x)) || \ + (Timer4SevtMask6 == (x)) || \ + (Timer4SevtMask7 == (x)) || \ + (Timer4SevtMask8 == (x)) || \ + (Timer4SevtMask9 == (x)) || \ + (Timer4SevtMask10 == (x)) || \ + (Timer4SevtMask11 == (x)) || \ + (Timer4SevtMask12 == (x)) || \ + (Timer4SevtMask13 == (x)) || \ + (Timer4SevtMask14 == (x)) || \ + (Timer4SevtMask15 == (x))) + +/*!< Get the specified register address of the specified Timer4 unit */ +#define TMR4_SCCRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCCRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_SCSRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCSRUH + ((uint32_t)(__CH__))*4ul) +#define TMR4_SCMRx(__TMR4x__, __CH__) ((uint32_t)&(__TMR4x__)->SCMRUH + ((uint32_t)(__CH__))*4ul) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Initialize a Special-Event channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] pstcInitCfg The pointer of SEVT configure structure + ** \arg This parameter detail refer @ref stc_timer4_sevt_init_t + ** + ** \retval Ok Initialize successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - TMR4x is invalid + ** - pstcInitCfg == NULL + ** - enCh is invalid + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_Init(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + const stc_timer4_sevt_init_t *pstcInitCfg) +{ + __IO uint16_t *pu16SCCR = NULL; + __IO stc_tmr4_scsr_field_t stcSCSR_f; + __IO stc_tmr4_scmr_field_t stcSCMR_f; + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x && pstcInitCfg pointer */ + if ((IS_VALID_TIMER4(TMR4x)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_MODE(pstcInitCfg->enMode)); + DDL_ASSERT(IS_VALID_SEVT_BUF_MODE(pstcInitCfg->enBuf)); + DDL_ASSERT(IS_VALID_SEVT_MSK(pstcInitCfg->enMaskTimes)); + DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(pstcInitCfg->enTrigEvt)); + DDL_ASSERT(IS_VALID_SEVT_OCCR_SEL(pstcInitCfg->enOccrSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcZicCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInitCfg->enCmpAmcPicCmd)); + + enRet = Ok; + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + /* Configure default parameter */ + *pu16SCCR = (uint16_t)0u; + *(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u; + *(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u; + + switch (pstcInitCfg->enBuf) + { + case SevtBufDisable: + stcSCSR_f.BUFEN = (uint16_t)0u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZero: + stcSCSR_f.BUFEN = (uint16_t)1u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntPeak: + stcSCSR_f.BUFEN = (uint16_t)2u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZeroOrCntPeak: + stcSCSR_f.BUFEN = (uint16_t)3u; + stcSCSR_f.LMC = (uint16_t)0u; + break; + case SevtBufCntZeroZicZero: + stcSCSR_f.BUFEN = (uint16_t)1u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + case SevtBufCntPeakPicZero: + stcSCSR_f.BUFEN = (uint16_t)2u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + case SevtBufCntZeroZicZeroOrCntPeakPicZero: + stcSCSR_f.BUFEN = (uint16_t)3u; + stcSCSR_f.LMC = (uint16_t)1u; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + if (Ok == enRet) + { + /* Configure start trigger output channel number */ + stcSCSR_f.EVTOS = (uint16_t)(pstcInitCfg->enTrigEvt); + + /* Select SEVT running mode */ + stcSCSR_f.EVTMS = (uint16_t)(pstcInitCfg->enMode); + + /* select OCO OCCR register: OCCR(x) */ + stcSCSR_f.EVTDS = (uint16_t)(pstcInitCfg->enOccrSel); + + /* Set the comparison with CNT interrupt mask counter */ + stcSCMR_f.AMC = (uint16_t)(pstcInitCfg->enMaskTimes); + stcSCMR_f.MZCE = (uint16_t)(pstcInitCfg->enCmpAmcZicCmd); + stcSCMR_f.MPCE = (uint16_t)(pstcInitCfg->enCmpAmcPicCmd); + + *pstcSCSR_f = stcSCSR_f; + *pstcSCMR_f = stcSCMR_f; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initialize a SEVT channel + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Ok De-Initialize successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_DeInit(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO uint16_t *pu16SCCR = NULL; + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + /* Configure default parameter */ + *pu16SCCR = 0u; + *(__IO uint16_t*)pstcSCSR_f = (uint16_t)0x0000u; + *(__IO uint16_t*)pstcSCMR_f = (uint16_t)0xFF00u; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger event. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] enTrgEvt Timer4 Special-EVT Event + ** \arg SevtTrgEvtSCMUH Timer4 Special-EVT Event: TMR4_Ux_SCMUH + ** \arg SevtTrgEvtSCMUL Timer4 Special-EVT Event: TMR4_Ux_SCMUL + ** \arg SevtTrgEvtSCMVH Timer4 Special-EVT Event: TMR4_Ux_SCMVH + ** \arg SevtTrgEvtSCMVL Timer4 Special-EVT Event: TMR4_Ux_SCMVL + ** \arg SevtTrgEvtSCMWH Timer4 Special-EVT Event: TMR4_Ux_SCMWH + ** \arg SevtTrgEvtSCMWL Timer4 Special-EVT Event: TMR4_Ux_SCMWL + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetTriggerEvent(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + en_timer4_sevt_trigger_evt_t enTrgEvt) +{ + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_TRG_EVT(enTrgEvt)); + + /* Get actual address of register list of current channel */ + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCSR_f->EVTOS = (uint16_t)(enTrgEvt); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger condition. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] pstcTrigCond The pointer of SEVT trigger condition structure + ** \arg This parameter detail refer @ref stc_timer4_sevt_trigger_cond_t + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetTriggerCond(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + const stc_timer4_sevt_trigger_cond_t *pstcTrigCond) +{ + __IO stc_tmr4_scsr_field_t *pstcSCSR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enUpMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enZeroMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enDownMatchCmd)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcTrigCond->enPeakMatchCmd)); + + /* Get actual address of register list of current channel */ + pstcSCSR_f = (__IO stc_tmr4_scsr_field_t*)TMR4_SCSRx(TMR4x, enCh); + pstcSCSR_f->PEN = (uint16_t)(pstcTrigCond->enPeakMatchCmd); + pstcSCSR_f->ZEN = (uint16_t)(pstcTrigCond->enZeroMatchCmd); + pstcSCSR_f->UEN = (uint16_t)(pstcTrigCond->enUpMatchCmd); + pstcSCSR_f->DEN = (uint16_t)(pstcTrigCond->enDownMatchCmd); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Write compare or delay value to Timer4 SEVT + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] u16SccrVal Timer4 SEVT compare value + ** + ** \retval Ok Compare or delay value to Timer4 SEVT is set + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_WriteSCCR(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + uint16_t u16SccrVal) +{ + __IO uint16_t *pu16SCCR = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + *pu16SCCR = u16SccrVal; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Read compare value or delay value of ATVR + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Value of register SCCR + ** + ******************************************************************************/ +uint16_t TIMER4_SEVT_ReadSCCR(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO uint16_t *pu16SCCR = NULL; + + /* check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pu16SCCR = (__IO uint16_t*)TMR4_SCCRx(TMR4x, enCh); + + return *pu16SCCR; +} + +/** + ******************************************************************************* + ** \brief Set Timer4 SEVT trigger event. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** \param [in] enMaskTimes Timer4 Special-EVT event mask times + ** \arg Timer4SevtMask0 Mask 0 time. + ** \arg Timer4SevtMask1 Mask 1 times. + ** \arg Timer4SevtMask2 Mask 2 times. + ** \arg Timer4SevtMask3 Mask 3 times. + ** \arg Timer4SevtMask4 Mask 4 times. + ** \arg Timer4SevtMask5 Mask 5 times. + ** \arg Timer4SevtMask6 Mask 6 times. + ** \arg Timer4SevtMask7 Mask 7 times. + ** \arg Timer4SevtMask8 Mask 8 times. + ** \arg Timer4SevtMask9 Mask 9 times. + ** \arg Timer4SevtMask10 Mask 10 times + ** \arg Timer4SevtMask11 Mask 11 times + ** \arg Timer4SevtMask12 Mask 12 times + ** \arg Timer4SevtMask13 Mask 13 times + ** \arg Timer4SevtMask14 Mask 14 times + ** \arg Timer4SevtMask15 Mask 15 times + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter TMR4x is invalid + ** + ******************************************************************************/ +en_result_t TIMER4_SEVT_SetMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh, + en_timer4_sevt_mask_t enMaskTimes) +{ + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check TMR4x pointer */ + if (IS_VALID_TIMER4(TMR4x)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + DDL_ASSERT(IS_VALID_SEVT_MSK(enMaskTimes)); + + /* Get actual address of register list of current channel */ + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + pstcSCMR_f->AMC = (uint16_t)(enMaskTimes); + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timer4 SEVT mask count. + ** + ** \param [in] TMR4x Pointer to Timer4 instance register base + ** \arg M4_TMR41 Timer4 unit 1 instance register base + ** \arg M4_TMR42 Timer4 unit 2 instance register base + ** \arg M4_TMR43 Timer4 unit 3 instance register base + ** \param [in] enCh Timer4 SEVT channel + ** \arg Timer4SevtCh0 Timer4 SEVT channel:0 + ** \arg Timer4SevtCh1 Timer4 SEVT channel:1 + ** \arg Timer4SevtCh2 Timer4 SEVT channel:2 + ** \arg Timer4SevtCh3 Timer4 SEVT channel:3 + ** \arg Timer4SevtCh4 Timer4 SEVT channel:4 + ** \arg Timer4SevtCh5 Timer4 SEVT channel:5 + ** + ** \retval Timer4SevtMask0 Mask 0 time. + ** \retval Timer4SevtMask1 Mask 1 times. + ** \retval Timer4SevtMask2 Mask 2 times. + ** \retval Timer4SevtMask3 Mask 3 times. + ** \retval Timer4SevtMask4 Mask 4 times. + ** \retval Timer4SevtMask5 Mask 5 times. + ** \retval Timer4SevtMask6 Mask 6 times. + ** \retval Timer4SevtMask7 Mask 7 times. + ** \retval Timer4SevtMask8 Mask 8 times. + ** \retval Timer4SevtMask9 Mask 9 times. + ** \retval Timer4SevtMask10 Mask 10 times + ** \retval Timer4SevtMask11 Mask 11 times + ** \retval Timer4SevtMask12 Mask 12 times + ** \retval Timer4SevtMask13 Mask 13 times + ** \retval Timer4SevtMask14 Mask 14 times + ** \retval Timer4SevtMask15 Mask 15 times + ** + ******************************************************************************/ +en_timer4_sevt_mask_t TIMER4_SEVT_GetMaskTimes(M4_TMR4_TypeDef *TMR4x, + en_timer4_sevt_ch_t enCh) +{ + __IO stc_tmr4_scmr_field_t *pstcSCMR_f = NULL; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TIMER4(TMR4x)); + DDL_ASSERT(IS_VALID_SEVT_CH(enCh)); + + /* Get actual address of register list of current channel */ + pstcSCMR_f = (__IO stc_tmr4_scmr_field_t*)TMR4_SCMRx(TMR4x, enCh); + + return (en_timer4_sevt_mask_t)pstcSCMR_f->AMC; +} + +//@} // Timer4SevtGroup + +#endif /* DDL_TIMER4_SEVT_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer6.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer6.c new file mode 100644 index 0000000000..461c25b22f --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timer6.c @@ -0,0 +1,1786 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timer6.c + ** + ** A detailed description is available at + ** @link Timer6Group Timer6 description @endlink + ** + ** - 2018-11-23 CDT First version for Device Driver Library of Timer6. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timer6.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMER6_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup Timer6Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for normal timer6 unit */ +#define IS_VALID_NORMAL_TIMER6_UNIT(__TMR6x__) \ +( (M4_TMR61 == (__TMR6x__)) || \ + (M4_TMR62 == (__TMR6x__)) || \ + (M4_TMR63 == (__TMR6x__))) + +/*!< Parameter valid check for period register*/ +#define IS_VALID_PERIOD_TYPE(x) \ +( (Timer6PeriodA == (x)) || \ + (Timer6PeriodB == (x)) || \ + (Timer6PeriodC == (x))) +/*!< Parameter valid check for General compare register*/ +#define IS_VALID_GEN_CMP_TYPE(x) \ +( (Timer6GenCompareA == (x)) || \ + (Timer6GenCompareB == (x)) || \ + (Timer6GenCompareC == (x)) || \ + (Timer6GenCompareD == (x)) || \ + (Timer6GenCompareE == (x)) || \ + (Timer6GenCompareF == (x))) + +/*!< Parameter valid check for Special compare register*/ +#define IS_VALID_SPECIAL_CMP_TYPE(x) \ +( (Timer6SpclCompA == (x)) || \ + (Timer6SpclCompB == (x)) || \ + (Timer6SpclCompC == (x)) || \ + (Timer6SpclCompD == (x)) || \ + (Timer6SpclCompE == (x)) || \ + (Timer6SpclCompF == (x))) +/*!< Parameter valid check for Count clock division */ +#define IS_VALID_COUNT_CLK_DIV(x) \ +( (Timer6PclkDiv1 == (x)) || \ + (Timer6PclkDiv2 == (x)) || \ + (Timer6PclkDiv4 == (x)) || \ + (Timer6PclkDiv8 == (x)) || \ + (Timer6PclkDiv16 == (x)) || \ + (Timer6PclkDiv64 == (x)) || \ + (Timer6PclkDiv256 == (x)) || \ + (Timer6PclkDiv1024 == (x))) + +/*!< Parameter valid check for count mode */ +#define IS_VALID_COUNT_MODE(x) \ +( (Timer6CntSawtoothMode == (x)) || \ + (Timer6CntTriangularModeA == (x)) || \ + (Timer6CntTriangularModeB == (x))) + +/*!< Parameter valid check for count direction */ +#define IS_VALID_COUNT_DIR(x) \ +( (Timer6CntDirDown == (x)) || \ + (Timer6CntDirUp == (x))) + +/*!< Parameter valid check for timer6 output port */ +#define IS_VALID_TIMER6_OUTPUT_PORT(x) \ +( (Timer6PWMA == (x)) || \ + (Timer6PWMB == (x))) + +/*!< Parameter valid check for timer6 input port */ +#define IS_VALID_TIMER6_INPUT_PORT(x) \ +( (Timer6PWMA == (x)) || \ + (Timer6PWMB == (x)) || \ + (Timer6TrigA == (x)) || \ + (Timer6TrigB == (x))) + +/*!< Parameter valid check for start/stop count output status */ +#define IS_VALID_STA_STP_OUTPUT_STATUS(x) \ +( (Timer6PWMxPortOutLow == (x)) || \ + (Timer6PWMxPortOutHigh == (x))) + +/*!< Parameter valid check for match output status */ +#define IS_VALID_MATCH_OUTPUT_STATUS(x) \ +( (Timer6PWMxCompareLow == (x)) || \ + (Timer6PWMxCompareHigh == (x)) || \ + (Timer6PWMxCompareKeep == (x)) || \ + (Timer6PWMxCompareInv == (x))) + +/*!< Parameter valid check for match output status */ +#define IS_VALID_MATCH_OUTPUT_STATUS(x) \ +( (Timer6PWMxCompareLow == (x)) || \ + (Timer6PWMxCompareHigh == (x)) || \ + (Timer6PWMxCompareKeep == (x)) || \ + (Timer6PWMxCompareInv == (x))) + +/*!< Parameter valid check for port filter clock */ +#define IS_VALID_PORT_FILTER_CLOCK(x) \ +( (Timer6FltClkPclk0Div1 == (x)) || \ + (Timer6FltClkPclk0Div4 == (x)) || \ + (Timer6FltClkPclk0Div16 == (x)) || \ + (Timer6FltClkPclk0Div64 == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_VPERR_PCNT_NUM(x) \ +( (Timer6PeriodCnts0 == (x)) || \ + (Timer6PeriodCnts1 == (x)) || \ + (Timer6PeriodCnts2 == (x)) || \ + (Timer6PeriodCnts3 == (x)) || \ + (Timer6PeriodCnts4 == (x)) || \ + (Timer6PeriodCnts5 == (x)) || \ + (Timer6PeriodCnts6 == (x)) || \ + (Timer6PeriodCnts7 == (x))) +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_VPERR_PCNT_EN_SOURCE(x) \ +( (Timer6PeriodCnteDisable == (x)) || \ + (Timer6PeriodCnteMin == (x)) || \ + (Timer6PeriodCnteMax == (x)) || \ + (Timer6PeriodCnteBoth == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_IRQ_SOURCE(x) \ +( (Timer6INTENA == (x)) || \ + (Timer6INTENB == (x)) || \ + (Timer6INTENC == (x)) || \ + (Timer6INTEND == (x)) || \ + (Timer6INTENE == (x)) || \ + (Timer6INTENF == (x)) || \ + (Timer6INTENOVF == (x)) || \ + (Timer6INTENUDF == (x)) || \ + (Timer6INTENDTE == (x)) || \ + (Timer6INTENSAU == (x)) || \ + (Timer6INTENSAD == (x)) || \ + (Timer6INTENSBU == (x)) || \ + (Timer6INTENSBD == (x))) + +/*!< Parameter valid check for status type */ +#define IS_VALID_STATUS_TYPE(x) \ +( (Timer6CMAF == (x)) || \ + (Timer6CMBF == (x)) || \ + (Timer6CMCF == (x)) || \ + (Timer6CMDF == (x)) || \ + (Timer6CMEF == (x)) || \ + (Timer6CMFF == (x)) || \ + (Timer6OVFF == (x)) || \ + (Timer6UDFF == (x)) || \ + (Timer6DTEF == (x)) || \ + (Timer6CMSAUF == (x)) || \ + (Timer6CMSADF == (x)) || \ + (Timer6CMSBUF == (x)) || \ + (Timer6CMSBDF == (x)) || \ + (Timer6VPERNUM == (x)) || \ + (Timer6DIRF == (x))) + +/*!< Parameter valid check for hardware up count/down count event type */ +#define IS_VALID_HW_COUNT_TYPE(x) \ +( (Timer6HwCntPWMALowPWMBRise == (x)) || \ + (Timer6HwCntPWMALowPWMBFall == (x)) || \ + (Timer6HwCntPWMAHighPWMBRise == (x)) || \ + (Timer6HwCntPWMAHighPWMBFall == (x)) || \ + (Timer6HwCntPWMBLowPWMARise == (x)) || \ + (Timer6HwCntPWMBLowPWMAFall == (x)) || \ + (Timer6HwCntPWMBHighPWMARise == (x)) || \ + (Timer6HwCntPWMBHighPWMAFall == (x)) || \ + (Timer6HwCntTRIGARise == (x)) || \ + (Timer6HwCntTRIGAFall == (x)) || \ + (Timer6HwCntTRIGBRise == (x)) || \ + (Timer6HwCntTRIGBFall == (x)) || \ + (Timer6HwCntAos0 == (x)) || \ + (Timer6HwCntAos1 == (x))) + +/*!< Parameter valid check for hardware up start/stop/clear/capture event type */ +#define IS_VALID_HW_STA_STP_CLR_CAP_TYPE(x) \ +( (Timer6HwTrigAos0 == (x)) || \ + (Timer6HwTrigAos1 == (x)) || \ + (Timer6HwTrigPWMARise == (x)) || \ + (Timer6HwTrigPWMAFall == (x)) || \ + (Timer6HwTrigPWMBRise == (x)) || \ + (Timer6HwTrigPWMBFall == (x)) || \ + (Timer6HwTrigTimTriARise == (x)) || \ + (Timer6HwTrigTimTriAFall == (x)) || \ + (Timer6HwTrigTimTriBRise == (x)) || \ + (Timer6HwTrigTimTriBFall == (x)) || \ + (Timer6HwTrigEnd == (x))) + +/*!< Parameter valid check for timer6 input port type */ +#define IS_VALID_INPUT_PORT_TYPE(x) \ +( (Timer6xCHA == (x)) || \ + (Timer6xCHB == (x)) || \ + (Timer6TrigA == (x)) || \ + (Timer6TrigB == (x))) + +/*!< Parameter valid check for GenCMP and period register buffer transfer type*/ +#define IS_VALID_GCMP_PRD_BUF_TYPE(x) \ +( (Timer6GcmpPrdSingleBuf == (x)) || \ + (Timer6GcmpPrdDoubleBuf == (x))) + +/*!< Parameter valid check for special compare register buffer transfer type */ +#define IS_VALID_SPCL_BUF_TYPE(x) \ +( (Timer6SpclSingleBuf == (x)) || \ + (Timer6SpclDoubleBuf == (x))) + +/*!< Parameter valid check for spcl register transfer opportunity type */ +#define IS_VALID_SPCL_TRANS_OPT_TYPE(x) \ +( (Timer6SplcOptNone == (x)) || \ + (Timer6SplcOptOverFlow == (x)) || \ + (Timer6SplcOptUnderFlow == (x)) || \ + (Timer6SplcOptBoth == (x))) + +/*!< Parameter valid check for dead time register type */ +#define IS_VALID_DEAD_TIME_TYPE(x) \ +( (Timer6DeadTimUpAR == (x)) || \ + (Timer6DeadTimUpBR == (x)) || \ + (Timer6DeadTimDwnAR == (x)) || \ + (Timer6DeadTimDwnBR == (x))) + +/*!< Parameter valid check for Z Phase input mask periods */ +#define IS_VALID_ZPHASE_MASK_PRD(x) \ +( (Timer6ZMaskDis == (x)) || \ + (Timer6ZMask4Cyl == (x)) || \ + (Timer6ZMask8Cyl == (x)) || \ + (Tiemr6ZMask16Cyl == (x))) + +/*!< Parameter valid check for event source */ +#define IS_VALID_EVENT_SOURCE(x) ((x) <= 511) + +/*!< Parameter validity check for common trigger. */ +#define IS_VALID_TIMER6_COM_TRIGGER(x) \ +( (Timer6ComTrigger_1 == (x)) || \ + (Timer6ComTrigger_2 == (x)) || \ + (Timer6ComTrigger_1_2 == (x))) + +/*! TimerA registers reset value */ +#define TIMERA_REG_CNTER_RESET_VALUE (0x0000u) +#define TIMERA_REG_GCONR_RESET_VALUE (0x00000100ul) +#define TIMERA_REG_ICONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_PCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_BCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_DCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_FCONR_RESET_VALUE (0x00000000ul) +#define TIMERA_REG_VPERR_RESET_VALUE (0x00000000ul) + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/******************************************************************************* + * \brief Timer6 interrupt request enable or disable + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Irq Irq type + * \param [in] bEn true/false + * + * \retval Ok: config successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ_SOURCE(enTimer6Irq)); + + switch (enTimer6Irq) + { + case Timer6INTENA: + TMR6x->ICONR_f.INTENA = bEn; + break; + case Timer6INTENB: + TMR6x->ICONR_f.INTENB = bEn; + break; + case Timer6INTENC: + TMR6x->ICONR_f.INTENC = bEn; + break; + case Timer6INTEND: + TMR6x->ICONR_f.INTEND = bEn; + break; + case Timer6INTENE: + TMR6x->ICONR_f.INTENE = bEn; + break; + case Timer6INTENF: + TMR6x->ICONR_f.INTENF = bEn; + break; + case Timer6INTENOVF: + TMR6x->ICONR_f.INTENOVF = bEn; + break; + case Timer6INTENUDF: + TMR6x->ICONR_f.INTENUDF = bEn; + break; + case Timer6INTENDTE: + TMR6x->ICONR_f.INTENDTE = bEn; + break; + case Timer6INTENSAU: + TMR6x->ICONR_f.INTENSAU = bEn; + break; + case Timer6INTENSAD: + TMR6x->ICONR_f.INTENSAD = bEn; + break; + case Timer6INTENSBU: + TMR6x->ICONR_f.INTENSBU = bEn; + break; + case Timer6INTENSBD: + TMR6x->ICONR_f.INTENSBD = bEn; + break; + default: + break; + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Get Timer6 status flag + ** + ** \param [in] TMR6x Timer6 unit + ** + ** \param [in] enStatus Timer6 status type + ** + ** \retval Timer6 status + ** + ******************************************************************************/ +uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus) +{ + uint8_t status = 0u; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STATUS_TYPE(enStatus)); + + switch (enStatus) + { + case Timer6CMAF: + status = (uint8_t)TMR6x->STFLR_f.CMAF; + break; + case Timer6CMBF: + status = (uint8_t)TMR6x->STFLR_f.CMBF; + break; + case Timer6CMCF: + status = (uint8_t)TMR6x->STFLR_f.CMCF; + break; + case Timer6CMDF: + status = (uint8_t)TMR6x->STFLR_f.CMDF; + break; + case Timer6CMEF: + status = (uint8_t)TMR6x->STFLR_f.CMEF; + break; + case Timer6CMFF: + status = (uint8_t)TMR6x->STFLR_f.CMFF; + break; + case Timer6OVFF: + status = (uint8_t)TMR6x->STFLR_f.OVFF; + break; + case Timer6UDFF: + status = (uint8_t)TMR6x->STFLR_f.UDFF; + break; + case Timer6DTEF: + status = (uint8_t)TMR6x->STFLR_f.DTEF; + break; + case Timer6CMSAUF: + status = (uint8_t)TMR6x->STFLR_f.CMSAUF; + break; + case Timer6CMSADF: + status = (uint8_t)TMR6x->STFLR_f.CMSADF; + break; + case Timer6CMSBUF: + status = (uint8_t)TMR6x->STFLR_f.CMSBUF; + break; + case Timer6CMSBDF: + status = (uint8_t)TMR6x->STFLR_f.CMSBDF; + break; + case Timer6VPERNUM: + status = (uint8_t)TMR6x->STFLR_f.VPERNUM; + break; + case Timer6DIRF: + status = (uint8_t)TMR6x->STFLR_f.DIRF; + break; + default: + break; + } + + return status; +} + + + +/** + ******************************************************************************* + ** \brief De-Initialize Timer6 unit + ** + ** \param [in] TMR6x Timer6 unit + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER = TIMERA_REG_CNTER_RESET_VALUE; + TMR6x->GCONR = TIMERA_REG_GCONR_RESET_VALUE; + TMR6x->PCONR = TIMERA_REG_PCONR_RESET_VALUE; + TMR6x->ICONR = TIMERA_REG_ICONR_RESET_VALUE; + TMR6x->BCONR = TIMERA_REG_BCONR_RESET_VALUE; + TMR6x->DCONR = TIMERA_REG_DCONR_RESET_VALUE; + TMR6x->FCONR = TIMERA_REG_FCONR_RESET_VALUE; + TMR6x->VPERR = TIMERA_REG_VPERR_RESET_VALUE; + TMR6x->HSTAR = 0x00000000ul; + TMR6x->HSTPR = 0x00000000ul; + TMR6x->HCLRR = 0x00000000ul; + TMR6x->HCPAR = 0x00000000ul; + TMR6x->HCPBR = 0x00000000ul; + TMR6x->HCUPR = 0x00000000ul; + TMR6x->HCDOR = 0x00000000ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Base Config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6BaseCntCfg Bsee Config Pointer + * + * \retval Ok: Config Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6BaseCntCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_COUNT_MODE(pstcTimer6BaseCntCfg->enCntMode)); + DDL_ASSERT(IS_VALID_COUNT_DIR(pstcTimer6BaseCntCfg->enCntDir)); + DDL_ASSERT(IS_VALID_COUNT_CLK_DIV(pstcTimer6BaseCntCfg->enCntClkDiv)); + + + TMR6x->GCONR_f.MODE = pstcTimer6BaseCntCfg->enCntMode; + TMR6x->GCONR_f.DIR = pstcTimer6BaseCntCfg->enCntDir; + TMR6x->GCONR_f.CKDIV = pstcTimer6BaseCntCfg->enCntClkDiv; + } + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Unit Start Count + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->GCONR_f.START = 1ul; + + return Ok; +} + +/******************************************************************************* + * \brief TImer6 Unit Stop Count + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->GCONR_f.START = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Unit Set Count Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] u16Value Count Value + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER_f.CNT = u16Value; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 Unit Get Count Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] u16Value Count Value + * + * \retval Ok: Config Successfully + * + ******************************************************************************/ +uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x) +{ + uint16_t u16Value; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u16Value = (uint16_t)TMR6x->CNTER_f.CNT; + + return u16Value; +} + +/******************************************************************************* + * \brief Timer6 Unit Clear Count Value + * + * + * \param [in] TMR6x Timer6 unit + * + * + * \retval Ok: Set Successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->CNTER_f.CNT = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 unit set count period and buffer value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Periodx Period register name + * \param [in] u16Period Count period value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_TYPE(enTimer6Periodx)); + + switch (enTimer6Periodx) + { + case Timer6PeriodA: + TMR6x->PERAR = u16Period; + break; + case Timer6PeriodB: + TMR6x->PERBR = u16Period; + break; + case Timer6PeriodC: + TMR6x->PERCR = u16Period; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 unit Set General Compare Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Compare General Compare Register name + * \param [in] u16Compare General Compare Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GEN_CMP_TYPE(enTimer6Compare)); + + switch (enTimer6Compare) + { + case Timer6GenCompareA: + TMR6x->GCMAR = u16Compare; + break; + case Timer6GenCompareB: + TMR6x->GCMBR = u16Compare; + break; + case Timer6GenCompareC: + TMR6x->GCMCR = u16Compare; + break; + case Timer6GenCompareD: + TMR6x->GCMDR = u16Compare; + break; + case Timer6GenCompareE: + TMR6x->GCMER = u16Compare; + break; + case Timer6GenCompareF: + TMR6x->GCMFR = u16Compare; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 unit Set Special Compare Register Value + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6SpclCmp General Compare Register name + * \param [in] u16SpclCmp General Compare Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_SPECIAL_CMP_TYPE(enTimer6SpclCmp)); + + switch (enTimer6SpclCmp) + { + case Timer6SpclCompA: + TMR6x->SCMAR = u16SpclCmp; + break; + case Timer6SpclCompB: + TMR6x->SCMBR = u16SpclCmp; + break; + case Timer6SpclCompC: + TMR6x->SCMCR = u16SpclCmp; + break; + case Timer6SpclCompD: + TMR6x->SCMDR = u16SpclCmp; + break; + case Timer6SpclCompE: + TMR6x->SCMER = u16SpclCmp; + break; + case Timer6SpclCompF: + TMR6x->SCMFR = u16SpclCmp; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config general compare buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort PWM channel of timer6 + * \param [in] pstcTimer6GenBufCfg General Compare Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + DDL_ASSERT(IS_VALID_GCMP_PRD_BUF_TYPE(pstcTimer6GenBufCfg->enGcmpBufTransType)); + + switch (enTimer6PWMPort) + { + case Timer6PWMA: + TMR6x->BCONR_f.BENA = pstcTimer6GenBufCfg->bEnGcmpTransBuf; + TMR6x->BCONR_f.BSEA = pstcTimer6GenBufCfg->enGcmpBufTransType; + break; + case Timer6PWMB: + TMR6x->BCONR_f.BENB = pstcTimer6GenBufCfg->bEnGcmpTransBuf; + TMR6x->BCONR_f.BSEB = pstcTimer6GenBufCfg->enGcmpBufTransType; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config special compare buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6SpclCmp Special Compare Register nameunit + * \param [in] pstcTimer6SpclBufCfg Special Compare Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_SPECIAL_CMP_TYPE(enTimer6SpclCmp)); + DDL_ASSERT(IS_VALID_SPCL_BUF_TYPE(pstcTimer6SpclBufCfg->enSpclBufTransType)); + DDL_ASSERT(IS_VALID_SPCL_TRANS_OPT_TYPE(pstcTimer6SpclBufCfg->enSpclBufOptType)); + + switch (enTimer6SpclCmp) + { + case Timer6SpclCompA: + TMR6x->BCONR_f.BENSPA = pstcTimer6SpclBufCfg->bEnSpclTransBuf; + TMR6x->BCONR_f.BSESPA = pstcTimer6SpclBufCfg->enSpclBufTransType; + TMR6x->BCONR_f.BTRSPA = pstcTimer6SpclBufCfg->enSpclBufOptType; + break; + case Timer6SpclCompB: + TMR6x->BCONR_f.BENSPB = pstcTimer6SpclBufCfg->bEnSpclTransBuf; + TMR6x->BCONR_f.BSESPB = pstcTimer6SpclBufCfg->enSpclBufTransType; + TMR6x->BCONR_f.BTRSPB = pstcTimer6SpclBufCfg->enSpclBufOptType; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 config period buffer transfer function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6PrdBufCfg Period Register Buffer Transfer Type Pointer + * + * \retval Ok: Set Successfully + * + ******************************************************************************/ +en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GCMP_PRD_BUF_TYPE(pstcTimer6PrdBufCfg->enPeriodBufTransType)); + + TMR6x->BCONR_f.BENP = pstcTimer6PrdBufCfg->bEnPeriodTransBuf; + TMR6x->BCONR_f.BSEP = pstcTimer6PrdBufCfg->enPeriodBufTransType; + + return Ok; +} + +/******************************************************************************* + * \brief Timer6 unit get General Compare Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6Compare General Compare Register name + * + * + * \retval u16TempValue: General Compare Register value + * + ******************************************************************************/ +uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare) +{ + uint16_t u16TempValue = 0u; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GEN_CMP_TYPE(enTimer6Compare)); + + switch (enTimer6Compare) + { + case Timer6GenCompareA: + u16TempValue = (uint16_t)TMR6x->GCMAR; + break; + case Timer6GenCompareB: + u16TempValue = (uint16_t)TMR6x->GCMBR; + break; + case Timer6GenCompareC: + u16TempValue = (uint16_t)TMR6x->GCMCR; + break; + case Timer6GenCompareD: + u16TempValue = (uint16_t)TMR6x->GCMDR; + break; + case Timer6GenCompareE: + u16TempValue = (uint16_t)TMR6x->GCMER; + break; + case Timer6GenCompareF: + u16TempValue = (uint16_t)TMR6x->GCMFR; + break; + default: + break; + } + + return u16TempValue; +} + +/*********************************************************************** + * \brief Timer6 Config valid count period + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6ValidPerCfg Valid Count Period Pointer + * + * \retval Ok: Config successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ***********************************************************************/ +en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6ValidPerCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_VPERR_PCNT_EN_SOURCE(pstcTimer6ValidPerCfg->enValidCdtEn)); + DDL_ASSERT(IS_VALID_VPERR_PCNT_NUM(pstcTimer6ValidPerCfg->enValidCntNum)); + + TMR6x->VPERR_f.PCNTS = pstcTimer6ValidPerCfg->enValidCntNum; + TMR6x->VPERR_f.PCNTE = pstcTimer6ValidPerCfg->enValidCdtEn; + TMR6x->VPERR_f.SPPERIA = pstcTimer6ValidPerCfg->bPeriodSCMA; + TMR6x->VPERR_f.SPPERIB = pstcTimer6ValidPerCfg->bPeriodSCMB; + } + return enRet; +} + +/******************************************************************************* + * \brief Port input config(Trig) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6PortInputCfg Point Input Config Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + if (NULL == pstcTimer6PortInputCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (pstcTimer6PortInputCfg->enPortSel) + { + case Timer6xCHA: + TMR6x->PCONR_f.CAPMDA = pstcTimer6PortInputCfg->enPortMode; + TMR6x->FCONR_f.NOFIENGA = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKGA = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6xCHB: + TMR6x->PCONR_f.CAPMDB = pstcTimer6PortInputCfg->enPortMode; + TMR6x->FCONR_f.NOFIENGB = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKGB = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6TrigA: + TMR6x->FCONR_f.NOFIENTA = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKTA = pstcTimer6PortInputCfg->enFltClk; + break; + + case Timer6TrigB: + TMR6x->FCONR_f.NOFIENTB = pstcTimer6PortInputCfg->bFltEn; + TMR6x->FCONR_f.NOFICKTB = pstcTimer6PortInputCfg->enFltClk; + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + } + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Output Port config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6PWMPort Timer6 Port(PWMA/PWMB) + * \param [in] pstcTimer6PortOutCfg timer6 Port Config Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, + en_timer6_chx_port_t enTimer6PWMPort, + const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_TIMER6_OUTPUT_PORT(enTimer6PWMPort)); + + if (NULL == pstcTimer6PortOutCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (enTimer6PWMPort) + { + case Timer6PWMA: + TMR6x->PCONR_f.CAPMDA = pstcTimer6PortOutCfg->enPortMode; + TMR6x->PCONR_f.STACA = pstcTimer6PortOutCfg->enStaOut; + TMR6x->PCONR_f.STPCA = pstcTimer6PortOutCfg->enStpOut; + TMR6x->PCONR_f.STASTPSA = pstcTimer6PortOutCfg->enStaStp; + TMR6x->PCONR_f.CMPCA = pstcTimer6PortOutCfg->enCmpc; + TMR6x->PCONR_f.PERCA = pstcTimer6PortOutCfg->enPerc; + TMR6x->PCONR_f.OUTENA = pstcTimer6PortOutCfg->bOutEn; + TMR6x->PCONR_f.EMBVALA = pstcTimer6PortOutCfg->enDisVal; + break; + + case Timer6PWMB: + TMR6x->PCONR_f.CAPMDB = pstcTimer6PortOutCfg->enPortMode; + TMR6x->PCONR_f.STACB = pstcTimer6PortOutCfg->enStaOut; + TMR6x->PCONR_f.STPCB = pstcTimer6PortOutCfg->enStpOut; + TMR6x->PCONR_f.STASTPSB = pstcTimer6PortOutCfg->enStaStp; + TMR6x->PCONR_f.CMPCB = pstcTimer6PortOutCfg->enCmpc; + TMR6x->PCONR_f.PERCB = pstcTimer6PortOutCfg->enPerc; + TMR6x->PCONR_f.OUTENB = pstcTimer6PortOutCfg->bOutEn; + TMR6x->PCONR_f.EMBVALB = pstcTimer6PortOutCfg->enDisVal; + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + } + return enRet; +} + + +/******************************************************************************* + * \brief Timer6 unit Set DeadTime Register Value(for PWM output) + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6DTReg DeadTime Register name + * \param [in] u16DTValue DeadTime Register value + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEAD_TIME_TYPE(enTimer6DTReg)); + + switch (enTimer6DTReg) + { + case Timer6DeadTimUpAR: + TMR6x->DTUAR = u16DTValue; + break; + case Timer6DeadTimUpBR: + TMR6x->DTUBR = u16DTValue; + break; + case Timer6DeadTimDwnAR: + TMR6x->DTDAR = u16DTValue; + break; + case Timer6DeadTimDwnBR: + TMR6x->DTDBR = u16DTValue; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/******************************************************************************* + * \brief Config DeadTime function + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6DTCfg Timer6 dead time config pointer + * + * \retval Ok: Set Successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + if (NULL == pstcTimer6DTCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + TMR6x->DCONR_f.SEPA = pstcTimer6DTCfg->bEnDtEqualUpDwn; + TMR6x->DCONR_f.DTBENU = pstcTimer6DTCfg->bEnDtBufUp; + TMR6x->DCONR_f.DTBEND = pstcTimer6DTCfg->bEnDtBufDwn; + TMR6x->DCONR_f.DTCEN = pstcTimer6DTCfg->bEnDeadtime; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Start + * + * + * \param [in] pstcTimer6SwSyncStart Software Synchrony Start Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncStart) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncStart->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncStart->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncStart->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SSTAR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Stop + * + * + * \param [in] pstcTimer6SwSyncStop Software Synchrony Stop Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncStop) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncStop->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncStop->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncStop->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SSTPR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Config Software Synchrony Clear + * + * + * \param [in] pstcTimer6SwSyncClear Software Synchrony Clear Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear) +{ + en_result_t enRet = Ok; + uint32_t u32Val = 0ul; + + if (NULL == pstcTimer6SwSyncClear) + { + enRet = ErrorInvalidParameter; + } + else + { + if (pstcTimer6SwSyncClear->bTimer61) + { + u32Val |= 0x1ul; + } + if (pstcTimer6SwSyncClear->bTimer62) + { + u32Val |= 0x2ul; + } + if (pstcTimer6SwSyncClear->bTimer63) + { + u32Val |= 0x4ul; + } + + M4_TMR6_CR->SCLRR = u32Val; + } + return enRet; +} + +/******************************************************************************* + * \brief Get Software Synchrony status + * + * + * \param [in] pstcTimer6SwSyncState Software Synchrony State Pointer + * + * \retval Ok: Set successfully + * \retval ErrorInvalidParameter: Provided parameter is not valid + * + ******************************************************************************/ +en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimer6SwSyncState) + { + enRet = ErrorInvalidParameter; + } + else + { + if (M4_TMR6_CR->SSTAR & 0x1ul) + { + pstcTimer6SwSyncState->bTimer61 = true; + } + else + { + pstcTimer6SwSyncState->bTimer61 = false; + } + if (M4_TMR6_CR->SSTAR & 0x2ul) + { + pstcTimer6SwSyncState->bTimer62 = true; + } + else + { + pstcTimer6SwSyncState->bTimer62 = false; + } + if (M4_TMR6_CR->SSTAR & 0x4ul) + { + pstcTimer6SwSyncState->bTimer63 = true; + } + else + { + pstcTimer6SwSyncState->bTimer63 = false; + } + } + + return enRet; +} + +/******************************************************************************* + * \brief Timer6 Hardware UpCount Event config + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCntUp Hardware UpCount Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_COUNT_TYPE(enTimer6HwCntUp)); + + u32Val = TMR6x->HCUPR; + TMR6x->HCUPR = u32Val | (1ul << enTimer6HwCntUp); + + return Ok; +} + +/************************************************************** + * \brief Clear Timer6 Hardware UpCount Event + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ************************************************************/ +en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCUPR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Set Timer6 Hardware DownCount Event + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCntDwn Hardware DownCount Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_COUNT_TYPE(enTimer6HwCntDwn)); + + u32Val = TMR6x->HCDOR; + TMR6x->HCDOR = u32Val | (1ul << enTimer6HwCntDwn); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Timer6 Hardware DownCount Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCDOR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwStart Hardware Start Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwStart)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val | (1ul << enTimer6HwStart); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HSTAR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val | (1ul << 31u); + + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Start Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTAR; + TMR6x->HSTAR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwStop Hardware Stop Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwStop)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val | (1ul << enTimer6HwStop); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HSTPR = 0ul; + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val | (1ul << 31u); + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Stop Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HSTPR; + TMR6x->HSTPR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwClear Hardware Clear Event + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwClear)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val | (1ul << enTimer6HwClear); + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCLRR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Enable Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val | (1ul << 31u); + + return Ok; +} + +/******************************************************************************* + * \brief Disable Hardware Clear Event + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + u32Val = TMR6x->HCLRR; + TMR6x->HCLRR = u32Val & 0x7FFFFFFFul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Capture Event A + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCaptureA Hardware capture event A selection + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwCaptureA)); + + u32Val = TMR6x->HCPAR; + TMR6x->HCPAR = u32Val | (1ul << enTimer6HwCaptureA); + //TMR6x->PCONR_f.CAPMDA = 1; + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Capture Event A + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCPAR = 0ul; + + return Ok; +} + +/******************************************************************************* + * \brief Config Hardware Capture Event B + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] enTimer6HwCaptureB Hardware capture event B selection + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB) +{ + uint32_t u32Val; + + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_STA_STP_CLR_CAP_TYPE(enTimer6HwCaptureB)); + + u32Val = TMR6x->HCPBR; + TMR6x->HCPBR = u32Val | (1ul << enTimer6HwCaptureB); + //TMR6x->PCONR_f.CAPMDB = 1; + + return Ok; +} + +/******************************************************************************* + * \brief Clear Hardware Capture Event B + * + * + * \param [in] TMR6x Timer6 unit + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + + TMR6x->HCPBR = 0ul; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Set trigger source 0 of hardware event + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement/capture + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMR6_HTSSR1_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set trigger source 1 of hardware event + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement/capture + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMR6_HTSSR2_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer6 common trigger for hardware trigger register 0 + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_timer6_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIMER6_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR6_HTSSR1 |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR6_HTSSR1 &= ~(u32ComTrig << 30u); + } +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timer6 common trigger for hardware trigger register 1 + ** + ** \param [in] enComTrigger Timer0 common trigger selection. See @ref en_timer6_com_trigger_t for details. + ** \param [in] enState Enable or disable the specified common trigger. + ** + ** \retval None + ** + ******************************************************************************/ +void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState) +{ + uint32_t u32ComTrig = (uint32_t)enComTrigger; + + DDL_ASSERT(IS_VALID_TIMER6_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enState)); + + if (enState == Enable) + { + M4_AOS->TMR6_HTSSR2 |= (u32ComTrig << 30u); + } + else + { + M4_AOS->TMR6_HTSSR2 &= ~(u32ComTrig << 30u); + } +} + +/******************************************************************************* + * \brief Z phase input mask config + * + * + * \param [in] TMR6x Timer6 unit + * \param [in] pstcTimer6ZMaskCfg Z phase input mask config pointer + * + * \retval Ok: Set successfully + * + ******************************************************************************/ +en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg) +{ + DDL_ASSERT(IS_VALID_NORMAL_TIMER6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_ZPHASE_MASK_PRD(pstcTimer6ZMaskCfg->enZMaskCycle)); + + TMR6x->GCONR_f.ZMSKVAL = pstcTimer6ZMaskCfg->enZMaskCycle; + TMR6x->GCONR_f.ZMSKPOS = pstcTimer6ZMaskCfg->bFltPosCntMaksEn; + TMR6x->GCONR_f.ZMSKREV = pstcTimer6ZMaskCfg->bFltRevCntMaksEn; + + return Ok; +} + + +//@} // Timer6Group + +#endif /* DDL_TIMER6_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timera.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timera.c new file mode 100644 index 0000000000..d45888621a --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_timera.c @@ -0,0 +1,1972 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_timera.c + ** + ** A detailed description is available at + ** @link TimeraGroup Timer A description @endlink + ** + ** - 2018-11-08 CDT First version for Device Driver Library of + ** Timera. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_timera.h" +#include "hc32f460_utility.h" + +#if (DDL_TIMERA_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup TimeraGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter valid check for normal timera unit */ +#define IS_VALID_NORMAL_TIMERA_UNIT(x) \ +( (M4_TMRA1 == (x)) || \ + (M4_TMRA2 == (x)) || \ + (M4_TMRA3 == (x)) || \ + (M4_TMRA4 == (x)) || \ + (M4_TMRA5 == (x)) || \ + (M4_TMRA6 == (x))) + +/*!< Parameter valid check for sync startup timera unit */ +#define IS_VALID_SYNC_STARTUP_TIMERA_UNIT(x) \ +( (M4_TMRA2 == (x)) || \ + (M4_TMRA3 == (x)) || \ + (M4_TMRA4 == (x)) || \ + (M4_TMRA5 == (x)) || \ + (M4_TMRA6 == (x))) + +/*!< Parameter valid check for Count clock division */ +#define IS_VALID_COUNT_CLK_DIV(x) \ +( (TimeraPclkDiv1 == (x)) || \ + (TimeraPclkDiv2 == (x)) || \ + (TimeraPclkDiv4 == (x)) || \ + (TimeraPclkDiv8 == (x)) || \ + (TimeraPclkDiv16 == (x)) || \ + (TimeraPclkDiv32 == (x)) || \ + (TimeraPclkDiv64 == (x)) || \ + (TimeraPclkDiv128 == (x)) || \ + (TimeraPclkDiv256 == (x)) || \ + (TimeraPclkDiv512 == (x)) || \ + (TimeraPclkDiv1024 == (x))) + +/*!< Parameter valid check for count mode */ +#define IS_VALID_COUNT_MODE(x) \ +( (TimeraCountModeSawtoothWave == (x)) || \ + (TimeraCountModeTriangularWave == (x))) + +/*!< Parameter valid check for count direction */ +#define IS_VALID_COUNT_DIR(x) \ +( (TimeraCountDirUp == (x)) || \ + (TimeraCountDirDown == (x))) + +/*!< Parameter valid check for normal timera channel */ +#define IS_VALID_NORMAL_TIMERA_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh2 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh4 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh6 == (x)) || \ + (TimeraCh7 == (x)) || \ + (TimeraCh8 == (x))) + +/*!< Parameter valid check for set cache channel */ +#define IS_VALID_SET_CACHE_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh7 == (x))) + +/*!< Parameter valid check for enable cache channel */ +#define IS_VALID_ENABLE_CACHE_CHANNEL(x) \ +( (TimeraCh1 == (x)) || \ + (TimeraCh3 == (x)) || \ + (TimeraCh5 == (x)) || \ + (TimeraCh7 == (x))) + +/*!< Parameter valid check for timera count start output status */ +#define IS_VALID_COUNT_START_OUTPUT(x) \ +( (TimeraCountStartOutputLow == (x)) || \ + (TimeraCountStartOutputHigh == (x)) || \ + (TimeraCountStartOutputKeep == (x))) + +/*!< Parameter valid check for timera count stop output status */ +#define IS_VALID_COUNT_STOP_OUTPUT(x) \ +( (TimeraCountStopOutputLow == (x)) || \ + (TimeraCountStopOutputHigh == (x)) || \ + (TimeraCountStopOutputKeep == (x))) + +/*!< Parameter valid check for compare match output status */ +#define IS_VALID_COMPARE_MATCH_OUTPUT(x) \ +( (TimeraCompareMatchOutputLow == (x)) || \ + (TimeraCompareMatchOutputHigh == (x)) || \ + (TimeraCompareMatchOutputKeep == (x)) || \ + (TimeraCompareMatchOutputReverse == (x))) + +/*!< Parameter valid check for period match output status */ +#define IS_VALID_PERIOD_MATCH_OUTPUT(x) \ +( (TimeraPeriodMatchOutputLow == (x)) || \ + (TimeraPeriodMatchOutputHigh == (x)) || \ + (TimeraPeriodMatchOutputKeep == (x)) || \ + (TimeraPeriodMatchOutputReverse == (x))) + +/*!< Parameter valid check for specify output status */ +#define IS_VALID_SPECIFY_OUTPUT_STATUS(x) \ +( (TimeraSpecifyOutputInvalid == (x)) || \ + (TimeraSpecifyOutputLow == (x)) || \ + (TimeraSpecifyOutputHigh == (x))) + +/*!< Parameter valid check for port filter clock */ +#define IS_VALID_PORT_FILTER_CLOCK(x) \ +( (TimeraFilterPclkDiv1 == (x)) || \ + (TimeraFilterPclkDiv4 == (x)) || \ + (TimeraFilterPclkDiv16 == (x)) || \ + (TimeraFilterPclkDiv64 == (x))) + +/*!< Parameter valid check for capture filter port source */ +#define IS_VALID_CAPTURE_FILTER_PORT_SOURCE(x) \ +( (TimeraFilterSourceCh1 == (x)) || \ + (TimeraFilterSourceCh2 == (x)) || \ + (TimeraFilterSourceCh3 == (x)) || \ + (TimeraFilterSourceCh4 == (x)) || \ + (TimeraFilterSourceCh5 == (x)) || \ + (TimeraFilterSourceCh6 == (x)) || \ + (TimeraFilterSourceCh7 == (x)) || \ + (TimeraFilterSourceCh8 == (x)) || \ + (TimeraFilterSourceTrig == (x))) + +/*!< Parameter valid check for coding filter port source */ +#define IS_VALID_CODING_FILTER_PORT_SOURCE(x) \ +( (TimeraFilterSourceClkA == (x)) || \ + (TimeraFilterSourceClkB == (x)) || \ + (TimeraFilterSourceTrig == (x))) + +/*!< Parameter valid check for interrupt request source */ +#define IS_VALID_IRQ_SOURCE(x) \ +( (TimeraIrqCaptureOrCompareCh1 == (x)) || \ + (TimeraIrqCaptureOrCompareCh2 == (x)) || \ + (TimeraIrqCaptureOrCompareCh3 == (x)) || \ + (TimeraIrqCaptureOrCompareCh4 == (x)) || \ + (TimeraIrqCaptureOrCompareCh5 == (x)) || \ + (TimeraIrqCaptureOrCompareCh6 == (x)) || \ + (TimeraIrqCaptureOrCompareCh7 == (x)) || \ + (TimeraIrqCaptureOrCompareCh8 == (x)) || \ + (TimeraIrqOverflow == (x)) || \ + (TimeraIrqUnderflow == (x))) + +/*!< Parameter valid check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (TimeraFlagCaptureOrCompareCh1 == (x)) || \ + (TimeraFlagCaptureOrCompareCh2 == (x)) || \ + (TimeraFlagCaptureOrCompareCh3 == (x)) || \ + (TimeraFlagCaptureOrCompareCh4 == (x)) || \ + (TimeraFlagCaptureOrCompareCh5 == (x)) || \ + (TimeraFlagCaptureOrCompareCh6 == (x)) || \ + (TimeraFlagCaptureOrCompareCh7 == (x)) || \ + (TimeraFlagCaptureOrCompareCh8 == (x)) || \ + (TimeraFlagOverflow == (x)) || \ + (TimeraFlagUnderflow == (x))) + +/*! Parameter valid check for common trigger. */ +#define IS_VALID_COM_TRIGGER(x) \ +( (TimeraComTrigger_1 == (x)) || \ + (TimeraComTrigger_2 == (x)) || \ + (TimeraComTrigger_1_2 == (x))) + +/*!< Parameter valid check for event source */ +#define IS_VALID_EVENT_SOURCE(x) ((x) <= 511u) + +/*!< Timera registers reset value */ +#define TIMERA_REG_CNTER_RESET_VALUE (0x0000u) +#define TIMERA_REG_PERAR_RESET_VALUE (0xFFFFu) +#define TIMERA_REG_CMPAR_RESET_VALUE (0xFFFFu) +#define TIMERA_REG_BCSTR_RESET_VALUE (0x0002u) +#define TIMERA_REG_ICONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_ECONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_FCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_STFLR_RESET_VALUE (0x0000u) +#define TIMERA_REG_BCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_CCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_PCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCONR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCUPR_RESET_VALUE (0x0000u) +#define TIMERA_REG_HCDOR_RESET_VALUE (0x0000u) + +#define TIMERA_REG_HTSSR0_RESET_VALUE (0x000001FFul) +#define TIMERA_REG_HTSSR1_RESET_VALUE (0x000001FFul) + +/*!< Timera calculate register address of channel */ +#define TIMERA_CALC_REG_ADDR(reg, chl) ((uint32_t)(&(reg)) + (chl)*0x4u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief De-Initialize Timera unit + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_DeInit(M4_TMRA_TypeDef *TIMERAx) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32Cnt = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = TIMERA_REG_CNTER_RESET_VALUE; + TIMERAx->PERAR = TIMERA_REG_PERAR_RESET_VALUE; + TIMERAx->BCSTR = TIMERA_REG_BCSTR_RESET_VALUE; + TIMERAx->ICONR = TIMERA_REG_ICONR_RESET_VALUE; + TIMERAx->ECONR = TIMERA_REG_ECONR_RESET_VALUE; + TIMERAx->FCONR = TIMERA_REG_FCONR_RESET_VALUE; + TIMERAx->STFLR = TIMERA_REG_STFLR_RESET_VALUE; + TIMERAx->HCONR = TIMERA_REG_HCONR_RESET_VALUE; + TIMERAx->HCUPR = TIMERA_REG_HCUPR_RESET_VALUE; + TIMERAx->HCDOR = TIMERA_REG_HCDOR_RESET_VALUE; + + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, u32Cnt) = TIMERA_REG_CMPAR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 4u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, u32Cnt * 2u) = TIMERA_REG_BCONR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, u32Cnt) = TIMERA_REG_CCONR_RESET_VALUE; + } + for (u32Cnt = 0u; u32Cnt < 8u; u32Cnt++) + { + *(__IO uint16_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, u32Cnt) = TIMERA_REG_PCONR_RESET_VALUE; + } + + M4_AOS->TMRA_HTSSR0 = TIMERA_REG_HTSSR0_RESET_VALUE; + M4_AOS->TMRA_HTSSR1 = TIMERA_REG_HTSSR1_RESET_VALUE; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit base function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcBaseInit Pointer to timera base init configuration + ** \arg See the struct #stc_timera_base_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidMode Unit 1 sync startup invalid + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcBaseInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_BaseInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_base_init_t *pstcBaseInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcBaseInit)) + { + DDL_ASSERT(IS_VALID_COUNT_CLK_DIV(pstcBaseInit->enClkDiv)); + DDL_ASSERT(IS_VALID_COUNT_MODE(pstcBaseInit->enCntMode)); + DDL_ASSERT(IS_VALID_COUNT_DIR(pstcBaseInit->enCntDir)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcBaseInit->enSyncStartupEn)); + + /* Configure control status register */ + TIMERAx->BCSTR_f.CKDIV = pstcBaseInit->enClkDiv; + TIMERAx->BCSTR_f.MODE = pstcBaseInit->enCntMode; + TIMERAx->BCSTR_f.DIR = pstcBaseInit->enCntDir; + + /* Unit 1 sync startup invalid */ + if ((M4_TMRA1 == TIMERAx) && (Enable == pstcBaseInit->enSyncStartupEn)) + { + enRet = ErrorInvalidMode; + } + else + { + TIMERAx->BCSTR_f.SYNST = pstcBaseInit->enSyncStartupEn; + enRet = Ok; + } + + /* Configure period value register */ + TIMERAx->PERAR = pstcBaseInit->u16PeriodVal; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera current count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16Cnt Timera current count value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCurrCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Cnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = u16Cnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera current count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera current count value + ** + ******************************************************************************/ +uint16_t TIMERA_GetCurrCount(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16CurrCntVal = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16CurrCntVal = (uint16_t)TIMERAx->CNTER; + } + + return u16CurrCntVal; +} + +/** + ******************************************************************************* + ** \brief Set Timera period value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16Period Timera period value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetPeriodValue(M4_TMRA_TypeDef *TIMERAx, uint16_t u16Period) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->PERAR = u16Period; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera period count value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera current period value + ** + ******************************************************************************/ +uint16_t TIMERA_GetPeriodValue(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16PeriodVal = 0u; + + /* Check parameters */ + if (IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16PeriodVal = (uint16_t)TIMERAx->PERAR; + } + + return u16PeriodVal; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera software synchronous startup + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable synchronous startup + ** \arg Enable Enable synchronous startup + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SyncStartupCmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_SYNC_STARTUP_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + TIMERAx->BCSTR_f.SYNST = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera startup + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera startup + ** \arg Enable Enable timera startup + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_Cmd(M4_TMRA_TypeDef *TIMERAx, en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + TIMERAx->BCSTR_f.START = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit compare function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] pstcCompareInit Pointer to timera compare init configuration + ** \arg See the struct #stc_timera_compare_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCompareInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_CompareInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_compare_init_t *pstcCompareInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + __IO stc_tmra_bconr_field_t *pstcTimeraCache; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCompareInit)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_COUNT_START_OUTPUT(pstcCompareInit->enStartCountOutput)); + DDL_ASSERT(IS_VALID_COUNT_STOP_OUTPUT(pstcCompareInit->enStopCountOutput)); + DDL_ASSERT(IS_VALID_COMPARE_MATCH_OUTPUT(pstcCompareInit->enCompareMatchOutput)); + DDL_ASSERT(IS_VALID_PERIOD_MATCH_OUTPUT(pstcCompareInit->enPeriodMatchOutput)); + DDL_ASSERT(IS_VALID_SPECIFY_OUTPUT_STATUS(pstcCompareInit->enSpecifyOutput)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enCacheEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enTriangularCrestTransEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCompareInit->enTriangularTroughTransEn)); + + /* Configure port control register */ + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->STAC = pstcCompareInit->enStartCountOutput; + pstcTimeraPort->STPC = pstcCompareInit->enStopCountOutput; + pstcTimeraPort->CMPC = pstcCompareInit->enCompareMatchOutput; + pstcTimeraPort->PERC = pstcCompareInit->enPeriodMatchOutput; + pstcTimeraPort->FORC = pstcCompareInit->enSpecifyOutput; + + /* Configure cache control register */ + if ((TimeraCh1 == enChannel) || (TimeraCh3 == enChannel) || + (TimeraCh5 == enChannel) || (TimeraCh7 == enChannel)) + { + pstcTimeraCache = (stc_tmra_bconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, enChannel); + pstcTimeraCache->BSE0 = pstcCompareInit->enTriangularCrestTransEn; + pstcTimeraCache->BSE1 = pstcCompareInit->enTriangularTroughTransEn; + pstcTimeraCache->BEN = pstcCompareInit->enCacheEn; + /* Configure compare cache value register */ + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel + 1); + pstcTimeraCompare->CMP = pstcCompareInit->u16CompareCacheVal; + } + + /* Configure compare value register */ + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + pstcTimeraCompare->CMP = pstcCompareInit->u16CompareVal; + + /* Set compare output function */ + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enChannel); + pstcTimeraCapture->CAPMD = 0u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera compare value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] u16CompareVal Timera campare value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareVal) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + pstcTimeraCompare->CMP = u16CompareVal; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera compare value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \retval uint16_t Timera compare value + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +uint16_t TIMERA_GetCompareValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel) +{ + uint16_t u16CompareVal = 0u; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + u16CompareVal = (uint16_t)pstcTimeraCompare->CMP; + } + + return u16CompareVal; +} + +/** + ******************************************************************************* + ** \brief Set Timera compare cache value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh7 Timera channel 7 + ** + ** \param [in] u16CompareCache Timera compare cache value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetCacheValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + uint16_t u16CompareCache) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_SET_CACHE_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel + 1); + pstcTimeraCompare->CMP = u16CompareCache; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera compare cache + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh7 Timera channel 7 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera compare cache + ** \arg Enable Enable timera compare cache + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CompareCacheCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_bconr_field_t *pstcTimeraCache; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_ENABLE_CACHE_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + /* Configure cache control register */ + pstcTimeraCache = (stc_tmra_bconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->BCONR1, enChannel); + pstcTimeraCache->BEN = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Specify Timera port output status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enOutputSta Timera port output status + ** \arg TimeraSpecifyOutputInvalid Port output invalid + ** \arg TimeraSpecifyOutputLow Port output low level from next period + ** \arg TimeraSpecifyOutputHigh Port output high level from next period + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SpecifyOutputSta(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_timera_specify_output_t enOutputSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_VALID_SPECIFY_OUTPUT_STATUS(enOutputSta)); + + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->FORC = enOutputSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera compare function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera compare channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera compare function + ** \arg Enable Enable timera compare function + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CompareCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_pconr_field_t *pstcTimeraPort; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + pstcTimeraPort = (stc_tmra_pconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->PCONR1, enChannel); + pstcTimeraPort->OUTEN = enNewSta; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit capture function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera capture channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] pstcCapInit Pointer to timera capture init configuration + ** \arg See the struct #stc_timera_capture_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCapInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureInit(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + const stc_timera_capture_init_t *pstcCapInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCapInit)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCapturePwmRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCapturePwmFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureSpecifyEventEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enCaptureTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enPwmFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCapInit->enTrigFilterEn)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCapInit->enPwmClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCapInit->enTrigClkDiv)); + + /* Configure capture control register */ + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enChannel); + pstcTimeraCapture->HICP0 = pstcCapInit->enCapturePwmRisingEn; + pstcTimeraCapture->HICP1 = pstcCapInit->enCapturePwmFallingEn; + pstcTimeraCapture->HICP2 = pstcCapInit->enCaptureSpecifyEventEn; + pstcTimeraCapture->NOFICKCP = pstcCapInit->enPwmClkDiv; + pstcTimeraCapture->NOFIENCP = pstcCapInit->enPwmFilterEn; + + /* TIMA__TRIG port capture function only valid for TimeraCh3 */ + if (TimeraCh3 == enChannel) + { + pstcTimeraCapture->HICP3 = pstcCapInit->enCaptureTrigRisingEn; + pstcTimeraCapture->HICP4 = pstcCapInit->enCaptureTrigFallingEn; + /* Configure filter control register */ + TIMERAx->FCONR_f.NOFICKTG = pstcCapInit->enTrigClkDiv; + TIMERAx->FCONR_f.NOFIENTG = pstcCapInit->enTrigFilterEn; + } + + /* Set capture input function */ + pstcTimeraCapture->CAPMD = 1u; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera capture filter + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFilterPort Timera capture filter input port + ** \arg TimeraFilterSourceCh1 TIMA__PWM1 input port + ** \arg TimeraFilterSourceCh2 TIMA__PWM2 input port + ** \arg TimeraFilterSourceCh3 TIMA__PWM3 input port + ** \arg TimeraFilterSourceCh4 TIMA__PWM4 input port + ** \arg TimeraFilterSourceCh5 TIMA__PWM5 input port + ** \arg TimeraFilterSourceCh6 TIMA__PWM6 input port + ** \arg TimeraFilterSourceCh7 TIMA__PWM7 input port + ** \arg TimeraFilterSourceCh8 TIMA__PWM8 input port + ** \arg TimeraFilterSourceTrig TIMA__TRIG input port + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera capture filter + ** \arg Enable Enable timera capture filter + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO stc_tmra_cconr_field_t *pstcTimeraCapture; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_CAPTURE_FILTER_PORT_SOURCE(enFilterPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (TimeraFilterSourceTrig == enFilterPort) + { + TIMERAx->FCONR_f.NOFIENTG = enNewSta; + } + else + { + pstcTimeraCapture = (stc_tmra_cconr_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CCONR1, enFilterPort); + pstcTimeraCapture->NOFIENCP = enNewSta; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera capture value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera capture channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \retval uint16_t Timera capture value + ** + ******************************************************************************/ +uint16_t TIMERA_GetCaptureValue(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel) +{ + uint16_t u16CapVal = 0u; + __IO stc_tmra_cmpar_field_t *pstcTimeraCompare; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + pstcTimeraCompare = (stc_tmra_cmpar_field_t *)TIMERA_CALC_REG_ADDR(TIMERAx->CMPAR1, enChannel); + u16CapVal = (uint16_t)pstcTimeraCompare->CMP; + } + + return u16CapVal; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit orthogonal coding function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcCodingInit Pointer to timera orthogonal coding configuration + ** \arg See the struct #stc_timera_orthogonal_coding_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcCodingInit == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_OrthogonalCodingInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_orthogonal_coding_init_t *pstcCodingInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcCodingInit)) + { + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enTrigClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enClkBClkDiv)); + DDL_ASSERT(IS_VALID_PORT_FILTER_CLOCK(pstcCodingInit->enClkAClkDiv)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enTrigFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enClkBFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enClkAFilterEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkALowAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkALowAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkAHighAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkAHighAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBLowAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBLowAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBHighAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncClkBHighAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncSpecifyEventTriggerEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncAnotherUnitOverflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enIncAnotherUnitUnderflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkALowAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkALowAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkAHighAndClkBRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkAHighAndClkBFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBLowAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBLowAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBHighAndClkARisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecClkBHighAndClkAFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecTrigRisingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecTrigFallingEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecSpecifyEventTriggerEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecAnotherUnitOverflowEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcCodingInit->enDecAnotherUnitUnderflowEn)); + + /* Configure hardware increase event register */ + TIMERAx->HCUPR_f.HCUP0 = pstcCodingInit->enIncClkALowAndClkBRisingEn; + TIMERAx->HCUPR_f.HCUP1 = pstcCodingInit->enIncClkALowAndClkBFallingEn; + TIMERAx->HCUPR_f.HCUP2 = pstcCodingInit->enIncClkAHighAndClkBRisingEn; + TIMERAx->HCUPR_f.HCUP3 = pstcCodingInit->enIncClkAHighAndClkBFallingEn; + TIMERAx->HCUPR_f.HCUP4 = pstcCodingInit->enIncClkBLowAndClkARisingEn; + TIMERAx->HCUPR_f.HCUP5 = pstcCodingInit->enIncClkBLowAndClkAFallingEn; + TIMERAx->HCUPR_f.HCUP6 = pstcCodingInit->enIncClkBHighAndClkARisingEn; + TIMERAx->HCUPR_f.HCUP7 = pstcCodingInit->enIncClkBHighAndClkAFallingEn; + TIMERAx->HCUPR_f.HCUP8 = pstcCodingInit->enIncTrigRisingEn; + TIMERAx->HCUPR_f.HCUP9 = pstcCodingInit->enIncTrigFallingEn; + TIMERAx->HCUPR_f.HCUP10 = pstcCodingInit->enIncSpecifyEventTriggerEn; + TIMERAx->HCUPR_f.HCUP11 = pstcCodingInit->enIncAnotherUnitOverflowEn; + TIMERAx->HCUPR_f.HCUP12 = pstcCodingInit->enIncAnotherUnitUnderflowEn; + + /* Configure hardware decrease event register */ + TIMERAx->HCDOR_f.HCDO0 = pstcCodingInit->enDecClkALowAndClkBRisingEn; + TIMERAx->HCDOR_f.HCDO1 = pstcCodingInit->enDecClkALowAndClkBFallingEn; + TIMERAx->HCDOR_f.HCDO2 = pstcCodingInit->enDecClkAHighAndClkBRisingEn; + TIMERAx->HCDOR_f.HCDO3 = pstcCodingInit->enDecClkAHighAndClkBFallingEn; + TIMERAx->HCDOR_f.HCDO4 = pstcCodingInit->enDecClkBLowAndClkARisingEn; + TIMERAx->HCDOR_f.HCDO5 = pstcCodingInit->enDecClkBLowAndClkAFallingEn; + TIMERAx->HCDOR_f.HCDO6 = pstcCodingInit->enDecClkBHighAndClkARisingEn; + TIMERAx->HCDOR_f.HCDO7 = pstcCodingInit->enDecClkBHighAndClkAFallingEn; + TIMERAx->HCDOR_f.HCDO8 = pstcCodingInit->enDecTrigRisingEn; + TIMERAx->HCDOR_f.HCDO9 = pstcCodingInit->enDecTrigFallingEn; + TIMERAx->HCDOR_f.HCDO10 = pstcCodingInit->enDecSpecifyEventTriggerEn; + TIMERAx->HCDOR_f.HCDO11 = pstcCodingInit->enDecAnotherUnitOverflowEn; + TIMERAx->HCDOR_f.HCDO12 = pstcCodingInit->enDecAnotherUnitUnderflowEn; + + /* Configure filter control register */ + TIMERAx->FCONR_f.NOFICKTG = pstcCodingInit->enTrigClkDiv; + TIMERAx->FCONR_f.NOFIENTG = pstcCodingInit->enTrigFilterEn; + TIMERAx->FCONR_f.NOFICKCB = pstcCodingInit->enClkBClkDiv; + TIMERAx->FCONR_f.NOFIENCB = pstcCodingInit->enClkBFilterEn; + TIMERAx->FCONR_f.NOFICKCA = pstcCodingInit->enClkAClkDiv; + TIMERAx->FCONR_f.NOFIENCA = pstcCodingInit->enClkAFilterEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set Timera orthogonal coding value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] u16CodingCnt Timera orthogonal coding value + ** \arg 0-0xFFFF + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_SetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx, uint16_t u16CodingCnt) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + TIMERAx->CNTER = u16CodingCnt; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera orthogonal coding value + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \retval uint16_t Timera orthogonal coding value + ** + ******************************************************************************/ +uint16_t TIMERA_GetOrthogonalCodingCount(M4_TMRA_TypeDef *TIMERAx) +{ + uint16_t u16CodingCnt = 0u; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + u16CodingCnt = (uint16_t)TIMERAx->CNTER; + } + + return u16CodingCnt; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera orthogonal coding filter + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFilterPort Timera orthogonal coding filter input port + ** \arg TimeraFilterSourceClkA TIMA__CLKA input port + ** \arg TimeraFilterSourceClkB TIMA__CLKB input port + ** \arg TimeraFilterSourceTrig TIMA__TRIG input port + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera orthogonal coding filter + ** \arg Enable Enable timera orthogonal coding filter + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_OrthogonalCodingFilterCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_filter_source_t enFilterPort, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_CODING_FILTER_PORT_SOURCE(enFilterPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enFilterPort) + { + case TimeraFilterSourceClkA: + TIMERAx->FCONR_f.NOFIENCA = enNewSta; + break; + case TimeraFilterSourceClkB: + TIMERAx->FCONR_f.NOFIENCB = enNewSta; + break; + case TimeraFilterSourceTrig: + TIMERAx->FCONR_f.NOFIENTG = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize Timera unit hardware trigger event function + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwTriggerInit Pointer to timera hardware trigger event configuration + ** \arg See the struct #stc_timera_hw_trigger_init_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwTriggerInit == NULL + ** + ** \note If sync startup(BCSTR.SYNST) bit set 1 trigger hardware sync startup when HCONR.HSTA1~0 bit set + ** + ******************************************************************************/ +en_result_t TIMERA_HwTriggerInit(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_trigger_init_t *pstcHwTriggerInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwTriggerInit)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enTrigRisingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enTrigFallingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStartup.enSpecifyEventStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enTrigRisingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enTrigFallingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwStop.enSpecifyEventStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enSpecifyEventClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enChannel3RisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwTriggerInit->stcHwClear.enChannel3FallingClearEn)); + + /* Configure hardware startup conditions */ + TIMERAx->HCONR_f.HSTA0 = pstcHwTriggerInit->stcHwStartup.enTrigRisingStartupEn; + TIMERAx->HCONR_f.HSTA1 = pstcHwTriggerInit->stcHwStartup.enTrigFallingStartupEn; + TIMERAx->HCONR_f.HSTA2 = pstcHwTriggerInit->stcHwStartup.enSpecifyEventStartupEn; + + /* Configure hardware stop conditions */ + TIMERAx->HCONR_f.HSTP0 = pstcHwTriggerInit->stcHwStop.enTrigRisingStopEn; + TIMERAx->HCONR_f.HSTP1 = pstcHwTriggerInit->stcHwStop.enTrigFallingStopEn; + TIMERAx->HCONR_f.HSTP2 = pstcHwTriggerInit->stcHwStop.enSpecifyEventStopEn; + + /* Configure hardware clear conditions */ + TIMERAx->HCONR_f.HCLE0 = pstcHwTriggerInit->stcHwClear.enTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE1 = pstcHwTriggerInit->stcHwClear.enTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE2 = pstcHwTriggerInit->stcHwClear.enSpecifyEventClearEn; + TIMERAx->HCONR_f.HCLE3 = pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE4 = pstcHwTriggerInit->stcHwClear.enAnotherUnitTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE5 = pstcHwTriggerInit->stcHwClear.enChannel3RisingClearEn; + TIMERAx->HCONR_f.HCLE6 = pstcHwTriggerInit->stcHwClear.enChannel3FallingClearEn; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware startup Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwStartup Pointer to timera hardware startup configuration + ** \arg See the struct #stc_timera_hw_startup_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwStartup == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwStartupConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_startup_config_t *pstcHwStartup) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwStartup)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enTrigRisingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enTrigFallingStartupEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStartup->enSpecifyEventStartupEn)); + + TIMERAx->HCONR_f.HSTA0 = pstcHwStartup->enTrigRisingStartupEn; + TIMERAx->HCONR_f.HSTA1 = pstcHwStartup->enTrigFallingStartupEn; + TIMERAx->HCONR_f.HSTA2 = pstcHwStartup->enSpecifyEventStartupEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware stop Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwStop Pointer to timera hardware stop configuration + ** \arg See the struct #stc_timera_hw_stop_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwStop == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwStopConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_stop_config_t *pstcHwStop) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwStop)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enTrigRisingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enTrigFallingStopEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwStop->enSpecifyEventStopEn)); + + TIMERAx->HCONR_f.HSTP0 = pstcHwStop->enTrigRisingStopEn; + TIMERAx->HCONR_f.HSTP1 = pstcHwStop->enTrigFallingStopEn; + TIMERAx->HCONR_f.HSTP2 = pstcHwStop->enSpecifyEventStopEn; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Timera hardware clear Config + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] pstcHwClear Pointer to timera hardware clear configuration + ** \arg See the struct #stc_timera_hw_clear_config_t + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** - pstcHwClear == NULL + ** + ******************************************************************************/ +en_result_t TIMERA_HwClearConfig(M4_TMRA_TypeDef *TIMERAx, const stc_timera_hw_clear_config_t *pstcHwClear) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx) && (NULL != pstcHwClear)) + { + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enSpecifyEventClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enAnotherUnitTrigRisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enAnotherUnitTrigFallingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enChannel3RisingClearEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcHwClear->enChannel3FallingClearEn)); + + TIMERAx->HCONR_f.HCLE0 = pstcHwClear->enTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE1 = pstcHwClear->enTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE2 = pstcHwClear->enSpecifyEventClearEn; + TIMERAx->HCONR_f.HCLE3 = pstcHwClear->enAnotherUnitTrigRisingClearEn; + TIMERAx->HCONR_f.HCLE4 = pstcHwClear->enAnotherUnitTrigFallingClearEn; + TIMERAx->HCONR_f.HCLE5 = pstcHwClear->enChannel3RisingClearEn; + TIMERAx->HCONR_f.HCLE6 = pstcHwClear->enChannel3FallingClearEn; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera interrupt request + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enIrq Timera interrupt request + ** \arg TimeraIrqCaptureOrCompareCh1 Channel 1 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh2 Channel 2 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh3 Channel 3 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh4 Channel 4 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh5 Channel 5 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh6 Channel 6 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh7 Channel 7 interrupt request + ** \arg TimeraIrqCaptureOrCompareCh8 Channel 8 interrupt request + ** \arg TimeraIrqOverflow Count overflow interrupt request + ** \arg TimeraIrqUnderflow Count underflow interrupt request + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera interrupt request + ** \arg Enable Enable timera interrupt request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_IrqCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_irq_type_t enIrq, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_IRQ_SOURCE(enIrq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + switch (enIrq) + { + case TimeraIrqCaptureOrCompareCh1: + TIMERAx->ICONR_f.ITEN1 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh2: + TIMERAx->ICONR_f.ITEN2 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh3: + TIMERAx->ICONR_f.ITEN3 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh4: + TIMERAx->ICONR_f.ITEN4 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh5: + TIMERAx->ICONR_f.ITEN5 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh6: + TIMERAx->ICONR_f.ITEN6 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh7: + TIMERAx->ICONR_f.ITEN7 = enNewSta; + break; + case TimeraIrqCaptureOrCompareCh8: + TIMERAx->ICONR_f.ITEN8 = enNewSta; + break; + case TimeraIrqOverflow: + TIMERAx->BCSTR_f.ITENOVF = enNewSta; + break; + case TimeraIrqUnderflow: + TIMERAx->BCSTR_f.ITENUDF = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable Timera event request + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enChannel Timera event request channel + ** \arg TimeraCh1 Timera channel 1 + ** \arg TimeraCh2 Timera channel 2 + ** \arg TimeraCh3 Timera channel 3 + ** \arg TimeraCh4 Timera channel 4 + ** \arg TimeraCh5 Timera channel 5 + ** \arg TimeraCh6 Timera channel 6 + ** \arg TimeraCh7 Timera channel 7 + ** \arg TimeraCh8 Timera channel 8 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable timera event request + ** \arg Enable Enable timera event request + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_EventCmd(M4_TMRA_TypeDef *TIMERAx, en_timera_channel_t enChannel, + en_functional_state_t enNewSta) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_NORMAL_TIMERA_CHANNEL(enChannel)); + + switch (enChannel) + { + case TimeraCh1: + TIMERAx->ECONR_f.ETEN1 = enNewSta; + break; + case TimeraCh2: + TIMERAx->ECONR_f.ETEN2 = enNewSta; + break; + case TimeraCh3: + TIMERAx->ECONR_f.ETEN3 = enNewSta; + break; + case TimeraCh4: + TIMERAx->ECONR_f.ETEN4 = enNewSta; + break; + case TimeraCh5: + TIMERAx->ECONR_f.ETEN5 = enNewSta; + break; + case TimeraCh6: + TIMERAx->ECONR_f.ETEN6 = enNewSta; + break; + case TimeraCh7: + TIMERAx->ECONR_f.ETEN7 = enNewSta; + break; + case TimeraCh8: + TIMERAx->ECONR_f.ETEN8 = enNewSta; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get Timera flag status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFlag Timera flag type + ** \arg TimeraFlagCaptureOrCompareCh1 Channel 1 match flag + ** \arg TimeraFlagCaptureOrCompareCh2 Channel 2 match flag + ** \arg TimeraFlagCaptureOrCompareCh3 Channel 3 match flag + ** \arg TimeraFlagCaptureOrCompareCh4 Channel 4 match flag + ** \arg TimeraFlagCaptureOrCompareCh5 Channel 5 match flag + ** \arg TimeraFlagCaptureOrCompareCh6 Channel 6 match flag + ** \arg TimeraFlagCaptureOrCompareCh7 Channel 7 match flag + ** \arg TimeraFlagCaptureOrCompareCh8 Channel 8 match flag + ** \arg TimeraFlagOverflow Count overflow flag + ** \arg TimeraFlagUnderflow Count underflow flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t TIMERA_GetFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case TimeraFlagCaptureOrCompareCh1: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF1; + break; + case TimeraFlagCaptureOrCompareCh2: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF2; + break; + case TimeraFlagCaptureOrCompareCh3: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF3; + break; + case TimeraFlagCaptureOrCompareCh4: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF4; + break; + case TimeraFlagCaptureOrCompareCh5: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF5; + break; + case TimeraFlagCaptureOrCompareCh6: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF6; + break; + case TimeraFlagCaptureOrCompareCh7: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF7; + break; + case TimeraFlagCaptureOrCompareCh8: + enFlagSta = (en_flag_status_t)TIMERAx->STFLR_f.CMPF8; + break; + case TimeraFlagOverflow: + enFlagSta = (en_flag_status_t)TIMERAx->BCSTR_f.OVFF; + break; + case TimeraFlagUnderflow: + enFlagSta = (en_flag_status_t)TIMERAx->BCSTR_f.UDFF; + break; + default: + break; + } + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear Timera flag status + ** + ** \param [in] TIMERAx Pointer to timera unit configuration address + ** \arg M4_TMRA1 Timera unit 1 configuration Address + ** \arg M4_TMRA2 Timera unit 2 configuration Address + ** \arg M4_TMRA3 Timera unit 3 configuration Address + ** \arg M4_TMRA4 Timera unit 4 configuration Address + ** \arg M4_TMRA5 Timera unit 5 configuration Address + ** \arg M4_TMRA6 Timera unit 6 configuration Address + ** + ** \param [in] enFlag Timera flag type + ** \arg TimeraFlagCaptureOrCompareCh1 Channel 1 match flag + ** \arg TimeraFlagCaptureOrCompareCh2 Channel 2 match flag + ** \arg TimeraFlagCaptureOrCompareCh3 Channel 3 match flag + ** \arg TimeraFlagCaptureOrCompareCh4 Channel 4 match flag + ** \arg TimeraFlagCaptureOrCompareCh5 Channel 5 match flag + ** \arg TimeraFlagCaptureOrCompareCh6 Channel 6 match flag + ** \arg TimeraFlagCaptureOrCompareCh7 Channel 7 match flag + ** \arg TimeraFlagCaptureOrCompareCh8 Channel 8 match flag + ** \arg TimeraFlagOverflow Count overflow flag + ** \arg TimeraFlagUnderflow Count underflow flag + ** + ** \retval Ok Process successfully done + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - TIMERAx is invalid + ** + ******************************************************************************/ +en_result_t TIMERA_ClearFlag(M4_TMRA_TypeDef *TIMERAx, en_timera_flag_type_t enFlag) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if(IS_VALID_NORMAL_TIMERA_UNIT(TIMERAx)) + { + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case TimeraFlagCaptureOrCompareCh1: + TIMERAx->STFLR_f.CMPF1 = 0u; + break; + case TimeraFlagCaptureOrCompareCh2: + TIMERAx->STFLR_f.CMPF2 = 0u; + break; + case TimeraFlagCaptureOrCompareCh3: + TIMERAx->STFLR_f.CMPF3 = 0u; + break; + case TimeraFlagCaptureOrCompareCh4: + TIMERAx->STFLR_f.CMPF4 = 0u; + break; + case TimeraFlagCaptureOrCompareCh5: + TIMERAx->STFLR_f.CMPF5 = 0u; + break; + case TimeraFlagCaptureOrCompareCh6: + TIMERAx->STFLR_f.CMPF6 = 0u; + break; + case TimeraFlagCaptureOrCompareCh7: + TIMERAx->STFLR_f.CMPF7 = 0u; + break; + case TimeraFlagCaptureOrCompareCh8: + TIMERAx->STFLR_f.CMPF8 = 0u; + break; + case TimeraFlagOverflow: + TIMERAx->BCSTR_f.OVFF = 0u; + break; + case TimeraFlagUnderflow: + TIMERAx->BCSTR_f.UDFF = 0u; + break; + default: + break; + } + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set counter event trigger source + ** + ** \param [in] enTriggerSrc Counter event trigger source + ** \arg 0-511 Used to trigger counter start/stop/clear/increment/decrement + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_SetCountTriggerSrc(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMRA_HTSSR0_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set capture event trigger source + ** + ** \param [in] enTriggerSrc Capture event trigger source + ** \arg 0-511 Used to trigger the capture function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_SetCaptureTriggerSrc(en_event_src_t enTriggerSrc) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_EVENT_SOURCE(enTriggerSrc)); + + M4_AOS->TMRA_HTSSR1_f.TRGSEL = enTriggerSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable TimerA counter common trigger. + ** + ** \param [in] enComTrigger TimerA common trigger selection. + ** \arg TimeraComTrigger_1 Select common trigger 1 + ** \arg TimeraComTrigger_2 Select common trigger 2 + ** \arg TimeraComTrigger_1_2 Select common trigger 1 and 2 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable the specified common trigger. + ** \arg Enable Enable the specified common trigger. + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_CountComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + uint32_t u32ComTrig; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u32ComTrig = (uint32_t)enComTrigger << 30u; + if (enNewSta == Enable) + { + M4_AOS->TMRA_HTSSR0 |= u32ComTrig; + } + else + { + M4_AOS->TMRA_HTSSR0 &= ~u32ComTrig; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Enable or disable TimerA capture common trigger. + ** + ** \param [in] enComTrigger TimerA common trigger selection. + ** \arg TimeraComTrigger_1 Select common trigger 1 + ** \arg TimeraComTrigger_2 Select common trigger 2 + ** \arg TimeraComTrigger_1_2 Select common trigger 1 and 2 + ** + ** \param [in] enNewSta The function new state + ** \arg Disable Disable the specified common trigger. + ** \arg Enable Enable the specified common trigger. + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t TIMERA_CaptureComTriggerCmd(en_timera_com_trigger_t enComTrigger, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + uint32_t u32ComTrig; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_COM_TRIGGER(enComTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u32ComTrig = (uint32_t)enComTrigger << 30u; + if (enNewSta == Enable) + { + M4_AOS->TMRA_HTSSR1 |= u32ComTrig; + } + else + { + M4_AOS->TMRA_HTSSR1 &= ~u32ComTrig; + } + + return enRet; +} + +//@} // TimeraGroup + +#endif /* DDL_TIMERA_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_trng.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_trng.c new file mode 100644 index 0000000000..95a994abe2 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_trng.c @@ -0,0 +1,263 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_trng.c + ** + ** A detailed description is available at + ** @link TrngGroup Trng description @endlink + ** + ** - 2018-10-20 CDT First version for Device Driver Library of Trng. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_trng.h" +#include "hc32f460_utility.h" + +#if (DDL_TRNG_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup TrngGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*! Parameter validity check for TRNG load control. */ +#define IS_TRNG_LOAD_CTRL(CTRL) \ +( ((CTRL) == TrngLoadNewInitValue_Enable) || \ + ((CTRL) == TrngLoadNewInitValue_Disable)) + +/*! Parameter validity check for TRNG shift count. */ +#define IS_TRNG_SHIFT_COUNT(COUNT) \ +( ((COUNT) == TrngShiftCount_32) || \ + ((COUNT) == TrngShiftCount_64) || \ + ((COUNT) == TrngShiftCount_128) || \ + ((COUNT) == TrngShiftCount_256)) + + +#define RANDOM_NUM_LENGTH (2u) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initializes the TRNG. + ** + ** \param [in] pstcInit Pointer to TRNG initialization structure. + ** \arg enLoadCtrl + ** \- TrngLoadNewInitValue_Enable Data register load new initial value before + ** random number is generated. + ** \- TrngLoadNewInitValue_Disable Data register do not load new initial value + ** before random number is generated. + ** + ** \arg enShiftCount Shift count control bit when capturing random noise. + ** \- TrngShiftCount_32 Shift 32 times. + ** \- TrngShiftCount_64 Shift 64 times. + ** \- TrngShiftCount_128 Shift 128 times. + ** \- TrngShiftCount_256 Shift 256 times. + ** + ** \retval Ok No error occurred. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TRNG_Init(const stc_trng_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + /* Parameter validity check */ + DDL_ASSERT(IS_TRNG_LOAD_CTRL(pstcInit->enLoadCtrl)); + DDL_ASSERT(IS_TRNG_SHIFT_COUNT(pstcInit->enShiftCount)); + + /* Stop TRNG generating*/ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + + M4_TRNG->MR_f.LOAD = pstcInit->enLoadCtrl; + M4_TRNG->MR_f.CNT = pstcInit->enShiftCount; + + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Deinitializes the TRNG. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_DeInit(void) +{ + /* Stop TRNG generating*/ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + + /* Set the value of all registers to the reset value. */ + M4_TRNG->CR = 0u; + M4_TRNG->MR = 0x12ul; + M4_TRNG->DR0 = 0x08000000ul; + M4_TRNG->DR0 = 0x08000200ul; +} + +/** + ******************************************************************************* + ** \brief Start TRNG and generate random number. + ** + ** \param [out] pu32Random The destination address where the random + ** number will be stored. + ** \param [in] u8Length Random number length(in word). + ** TRNG generates two random numbers(2 words) at one time. + ** u8Length >= 2, both random numbers will be read. + ** u8Length < 2, only one random number will be read. + ** \param [in] u32Timeout Timeout value. + ** + ** \retval Ok No error occurred. + ** \retval ErrorTimeout TRNG works timeout. + ** \retval ErrorInvalidParameter Parameter error. + ** + ******************************************************************************/ +en_result_t TRNG_Generate(uint32_t *pu32Random, uint8_t u8Length, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32TrngTimeout; + __IO uint32_t u32TimeCount; + + if ((NULL != pu32Random) && (0u != u32Timeout) && (0u != u8Length)) + { + /* 10 is the number of required instructions cycles for the below loop statement. */ + u32TrngTimeout = u32Timeout * (SystemCoreClock / 10u / 1000u); + + /* Turn on TRNG circuit. */ + bM4_TRNG_CR_EN = 1u; + + /* Start TRNG to generate random number. */ + bM4_TRNG_CR_RUN = 1u; + + /* wait generation done and check if timeout. */ + u32TimeCount = 0u; + enRet = ErrorTimeout; + while (u32TimeCount < u32TrngTimeout) + { + if (bM4_TRNG_CR_RUN == 0u) + { + enRet = Ok; + break; + } + u32TimeCount++; + } + + if (Ok == enRet) + { + /* read the random number. */ + pu32Random[0u] = M4_TRNG->DR0; + if (u8Length >= RANDOM_NUM_LENGTH) + { + pu32Random[1u] = M4_TRNG->DR1; + } + } + + /* Stop TRNG generating. */ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit. */ + bM4_TRNG_CR_EN = 0u; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Start TRNG only. + ** + ** \param None. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_StartIT(void) +{ + /* Turn on TRNG circuit. */ + bM4_TRNG_CR_EN = 1u; + + /* Start TRNG to generate random number. */ + bM4_TRNG_CR_RUN = 1u; +} + +/** + ******************************************************************************* + ** \brief Get random number. + ** + ** \param [out] pu32Random The destination address where the random + ** number will be stored. + ** \param [in] u8Length Random number length(in word). + ** TRNG generates two random numbers(2 words) at one time. + ** u8Length >= 2, both random numbers will be read. + ** u8Length < 2, only one random number will be read. + ** + ** \retval None. + ** + ******************************************************************************/ +void TRNG_GetRandomNum(uint32_t *pu32Random, uint8_t u8Length) +{ + if ((NULL != pu32Random) && (0u != u8Length)) + { + pu32Random[0u] = M4_TRNG->DR0; + if (u8Length >= RANDOM_NUM_LENGTH) + { + pu32Random[1u] = M4_TRNG->DR1; + } + + /* Stop TRNG generating */ + bM4_TRNG_CR_RUN = 0u; + + /* Turn off TRNG circuit */ + bM4_TRNG_CR_EN = 0u; + } +} + +//@} // TrngGroup + +#endif /* DDL_TRNG_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_usart.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_usart.c new file mode 100644 index 0000000000..8ad5614496 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_usart.c @@ -0,0 +1,1640 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_usart.c + ** + ** A detailed description is available at + ** @link UsartGroup USART description @endlink + ** + ** - 2018-11-27 CDT First version for Device Driver Library of USART. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_usart.h" +#include "hc32f460_utility.h" + +#if (DDL_USART_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup UsartGroup + ******************************************************************************/ + +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/*!< Parameter valid check for USART Instances. */ +#define IS_VALID_USART(__USARTx__) \ +( (M4_USART1 == (__USARTx__)) || \ + (M4_USART2 == (__USARTx__)) || \ + (M4_USART3 == (__USARTx__)) || \ + (M4_USART4 == (__USARTx__))) + +/*!< Parameter valid check for USART clock prescale. */ +#define IS_VALID_USART_CLK_DIV(x) \ +( (UsartClkDiv_1 == (x)) || \ + (UsartClkDiv_4 == (x)) || \ + (UsartClkDiv_16 == (x)) || \ + (UsartClkDiv_64 == (x))) + +/*!< Parameter valid check for USART function type. */ +#define IS_VALID_USART_FUNC(x) \ +( (UsartRx == (x)) || \ + (UsartTx == (x)) || \ + (UsartCts == (x)) || \ + (UsartRxInt == (x)) || \ + (UsartTimeOut == (x)) || \ + (UsartSmartCard == (x)) || \ + (UsartSilentMode == (x)) || \ + (UsartTxEmptyInt == (x)) || \ + (UsartTimeOutInt == (x)) || \ + (UsartTxCmpltInt == (x)) || \ + (UsartParityCheck == (x)) || \ + (UsartNoiseFilter == (x)) || \ + (UsartFracBaudrate == (x)) || \ + (UsartMulProcessor == (x)) || \ + (UsartTxAndTxEmptyInt == (x))) + +/*!< Parameter valid check for USART function type. */ +#define IS_VALID_USART_STATUS(x) \ +( (UsartRxMpb == (x)) || \ + (UsartTxEmpty == (x)) || \ + (UsartFrameErr == (x)) || \ + (UsartRxNoEmpty == (x)) || \ + (UsartRxTimeOut == (x)) || \ + (UsartParityErr == (x)) || \ + (UsartOverrunErr == (x)) || \ + (UsartTxComplete == (x))) + +/*!< Parameter valid check for USART clock mode. */ +#define IS_VALID_USART_CLK_MODE(x) \ +( (UsartExtClk == (x)) || \ + (UsartIntClkCkOutput == (x)) || \ + (UsartIntClkCkNoOutput == (x))) + +/*!< Parameter valid check for USART stop bit. */ +#define IS_VALID_USART_STOP_BIT(x) \ +( (UsartOneStopBit == (x)) || \ + (UsartTwoStopBit == (x))) + +/*!< Parameter valid check for USART parity bit. */ +#define IS_VALID_USART_PARITY_BIT(x) \ +( (UsartParityOdd == (x)) || \ + (UsartParityEven == (x)) || \ + (UsartParityNone == (x))) + +/*!< Parameter valid check for USART data length. */ +#define IS_VALID_USART_DATA_LEN(x) \ +( (UsartDataBits8 == (x)) || \ + (UsartDataBits9 == (x))) + +/*!< Parameter valid check for USART data direction. */ +#define IS_VALID_USART_DATA_DIR(x) \ +( (UsartDataLsbFirst == (x)) || \ + (UsartDataMsbFirst == (x))) + +/*!< Parameter valid check for USART sample mode. */ +#define IS_VALID_USART_SAMPLE_MODE(x) \ +( (UsartSampleBit8 == (x)) || \ + (UsartSampleBit16 == (x))) + +/*!< Parameter valid check for USART sample mode. */ +#define IS_VALID_USART_HW_FLOW_MODE(x) \ +( (UsartRtsEnable == (x)) || \ + (UsartCtsEnable == (x))) + +/*!< Parameter valid check for USART detect mode. */ +#define IS_VALID_USART_SB_DETECT_MODE(x) \ +( (UsartStartBitLowLvl == (x)) || \ + (UsartStartBitFallEdge == (x))) + +/*!< Parameter valid check for USART mode. */ +#define IS_VALID_USART_MODE(x) \ +( (UsartUartMode == (x)) || \ + (UsartClkSyncMode == (x)) || \ + (UsartSmartCardMode == (x))) + +/*!< Parameter valid check for USART ETU clocks number. */ +#define IS_VALID_USART_ETU_CLK(x) \ +( (UsartScEtuClk32 == (x)) || \ + (UsartScEtuClk64 == (x)) || \ + (UsartScEtuClk128 == (x)) || \ + (UsartScEtuClk256 == (x)) || \ + (UsartScEtuClk372 == (x))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t UsartGetClk(const M4_USART_TypeDef *USARTx); +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +static en_result_t SetClkSyncBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +static en_result_t SetScBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize UART mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to USART mode configure structure + ** \arg This parameter detail refer @ref stc_usart_uart_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_UART_Init(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_STOP_BIT(pstcInitCfg->enStopBit)); + DDL_ASSERT(IS_VALID_USART_PARITY_BIT(pstcInitCfg->enParity)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + DDL_ASSERT(IS_VALID_USART_DATA_LEN(pstcInitCfg->enDataLength)); + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(pstcInitCfg->enHwFlow)); + DDL_ASSERT(IS_VALID_USART_SAMPLE_MODE(pstcInitCfg->enSampleMode)); + DDL_ASSERT(IS_VALID_USART_SB_DETECT_MODE(pstcInitCfg->enDetectMode)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + /* Set USART mode */ + CR3_f.SCEN = (uint32_t)0ul; + CR1_f.MS = (uint32_t)0ul; + + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + CR1_f.M = (uint32_t)(pstcInitCfg->enDataLength); + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + CR2_f.STOP = (uint32_t)(pstcInitCfg->enStopBit); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + + switch(pstcInitCfg->enParity) + { + case UsartParityNone: + CR1_f.PCE = (uint32_t)0ul; + break; + case UsartParityEven: + CR1_f.PS = (uint32_t)0ul; + CR1_f.PCE = (uint32_t)1ul; + break; + case UsartParityOdd: + CR1_f.PS = (uint32_t)1ul; + CR1_f.PCE = (uint32_t)1ul; + break; + default: + break; + } + + CR3_f.CTSE = (uint32_t)(pstcInitCfg->enHwFlow); + CR1_f.SBS = (uint32_t)(pstcInitCfg->enDetectMode); + CR1_f.OVER8 = (uint32_t)(pstcInitCfg->enSampleMode); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} +/** + ******************************************************************************* + ** \brief Initialize clock sync mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to clock sync mode configure structure + ** \arg This parameter detail refer @ref stc_usart_clksync_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_CLKSYNC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(pstcInitCfg->enHwFlow)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + /* Set Clock Sync mode */ + CR3_f.SCEN = (uint32_t)0ul; + CR1_f.MS = (uint32_t)1ul; + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + CR3_f.CTSE = (uint32_t)(pstcInitCfg->enHwFlow); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Initialize smart card mode of the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] pstcInitCfg Pointer to smart card mode configure structure + ** \arg This parameter detail refer @ref stc_usart_sc_init_t + ** + ** \retval Ok USART is initialized normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - pstcInitCfg == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t USART_SC_Init(M4_USART_TypeDef *USARTx, + const stc_usart_sc_init_t *pstcInitCfg) +{ + stc_usart_pr_field_t PR_f = {0}; + stc_usart_cr1_field_t CR1_f = {0}; + stc_usart_cr2_field_t CR2_f = {0}; + stc_usart_cr3_field_t CR3_f = {0}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx && pstcInitCfg pointer */ + if ((IS_VALID_USART(USARTx)) && (NULL != pstcInitCfg)) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(pstcInitCfg->enClkDiv)); + DDL_ASSERT(IS_VALID_USART_CLK_MODE(pstcInitCfg->enClkMode)); + DDL_ASSERT(IS_VALID_USART_DATA_DIR(pstcInitCfg->enDirection)); + + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + + CR1_f.PCE = (uint32_t)1ul; + CR1_f.ML = (uint32_t)(pstcInitCfg->enDirection); + CR2_f.CLKC = (uint32_t)(pstcInitCfg->enClkMode); + CR3_f.SCEN = (uint32_t)1ul; /* Set USART mode */ + CR3_f.BCN = (uint32_t)UsartScEtuClk372; /* ETU = 372 * CK */ + PR_f.PSC = (uint32_t)(pstcInitCfg->enClkDiv); + + USARTx->PR_f = PR_f; + USARTx->CR2_f= CR2_f; + USARTx->CR3_f= CR3_f; + USARTx->CR1_f= CR1_f; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief De-Initializes the specified USART. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval Ok USART is de-initialized normally + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_DeInit(M4_USART_TypeDef *USARTx) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check for USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Set default value */ + USARTx->CR1 = (uint32_t)0x801B0000ul; + USARTx->CR2 = (uint32_t)0x00000000ul; + USARTx->CR3 = (uint32_t)0x00000000ul; + USARTx->BRR = (uint32_t)0x0000FFFFul; + USARTx->PR = (uint32_t)0x00000000ul; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get flag status + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStatus Choose need get status's flag + ** \arg UsartParityError Parity check error + ** \arg UsartFrameError Frame error + ** \arg UsartOverRunError Overrun error + ** \arg UsartRxRegNoEmpty Rx register is no empty + ** \arg UsartTxComplete Transfer completely + ** \arg UsartTxRegNoEmpty Tx register is no empty + ** \arg UsartRxTimeOut Data receive timeout + ** \arg UsartRxDataType Data is multiple processor id or normal data. + ** + ** \retval Set Flag is set. + ** \retval Reset Flag is reset or enStatus is invalid. + ** + ******************************************************************************/ +en_flag_status_t USART_GetStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus) +{ + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + DDL_ASSERT(IS_VALID_USART_STATUS(enStatus)); + + return ((USARTx->SR & enStatus) ? Set : Reset); +} + +/** + ******************************************************************************* + ** \brief Clear the specified USART status + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStatus The specified status + ** \arg UsartParityErr Parity check error + ** \arg UsartFrameErr Frame error + ** \arg UsartOverRunErr Overrun error + ** \arg UsartRxTimeOut Data receive timeout + ** + ** \retval Ok Clear flag successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enStatus is invalid + ** + ******************************************************************************/ +en_result_t USART_ClearStatus(M4_USART_TypeDef *USARTx, + en_usart_status_t enStatus) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch (enStatus) + { + case UsartParityErr: + USARTx->CR1_f.CPE = 1ul; + break; + case UsartFrameErr: + USARTx->CR1_f.CFE = 1ul; + break; + case UsartOverrunErr: + USARTx->CR1_f.CORE = 1ul; + break; + case UsartRxTimeOut: + USARTx->CR1_f.CRTOF = 1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Configure USART function. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enFunc USART function selection + ** \arg UsartTimeOut UART RX timeout function + ** \arg UsartTimeOutInt UART RX timeout interrupt function + ** \arg UsartRx UART RX function + ** \arg UsartTx UART TX function + ** \arg UsartSilentMode USART silent function + ** \arg UsartRxInt USART RX interrupt function + ** \arg UsartTxCmpltInt USART TX complete interrupt function + ** \arg UsartTxEmptyInt USART TX empty interrupt function + ** \arg UsartParityCheck USART Parity check function + ** \arg UsartFracBaudrate USART fractional baudrate function + ** \arg UsartNoiseFilter USART noise filter function + ** \param [in] enCmd USART functional state + ** \arg Enable Enable the specified USART function + ** \arg Disable Disable the specified USART function + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx == NULL + ** + ******************************************************************************/ +en_result_t USART_FuncCmd(M4_USART_TypeDef *USARTx, + en_usart_func_t enFunc, + en_functional_state_t enCmd) +{ + uint32_t u32Addr; + __IO stc_usart_cr1_field_t CR1_f; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enFunc) + { + case UsartRx: + USARTx->CR1_f.RE = (uint32_t)enCmd; + break; + case UsartRxInt: + USARTx->CR1_f.RIE = (uint32_t)enCmd; + break; + case UsartTx: + USARTx->CR1_f.TE = (uint32_t)enCmd; + break; + case UsartTxEmptyInt: + USARTx->CR1_f.TXEIE = (uint32_t)enCmd; + break; + case UsartTimeOut: + USARTx->CR1_f.RTOE = (uint32_t)enCmd; + break; + case UsartTimeOutInt: + USARTx->CR1_f.RTOIE = (uint32_t)enCmd; + break; + case UsartSilentMode: + USARTx->CR1_f.SLME = (uint32_t)enCmd; + break; + case UsartParityCheck: + USARTx->CR1_f.PCE = (uint32_t)enCmd; + break; + case UsartNoiseFilter: + USARTx->CR1_f.NFE = (uint32_t)enCmd; + break; + case UsartTxCmpltInt: + USARTx->CR1_f.TCIE = (uint32_t)enCmd; + break; + case UsartTxAndTxEmptyInt: + CR1_f = USARTx->CR1_f; + CR1_f.TE = (uint32_t)enCmd; + CR1_f.TXEIE = (uint32_t)enCmd; + u32Addr = (uint32_t)&CR1_f; + USARTx->CR1 = *(__IO uint32_t *)u32Addr; + break; + case UsartFracBaudrate: + USARTx->CR1_f.FBME = (uint32_t)enCmd; + break; + case UsartMulProcessor: + USARTx->CR2_f.MPE = (uint32_t)enCmd; + break; + case UsartSmartCard: + USARTx->CR3_f.SCEN = (uint32_t)enCmd; + break; + case UsartCts: + USARTx->CR3_f.CTSE = (uint32_t)enCmd; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set USART parity bit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enParity USART parity selection + ** \arg UsartParityNone USART none parity + ** \arg UsartParityEven USART even parity + ** \arg UsartParityOdd USART odd parity + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enParity is invalid + ** + ******************************************************************************/ +en_result_t USART_SetParity(M4_USART_TypeDef *USARTx, + en_usart_parity_t enParity) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enParity) + { + case UsartParityNone: + USARTx->CR1_f.PCE = (uint32_t)0ul; + break; + case UsartParityEven: + USARTx->CR1_f.PS = (uint32_t)0ul; + USARTx->CR1_f.PCE = (uint32_t)1u; + break; + case UsartParityOdd: + USARTx->CR1_f.PS = (uint32_t)1ul; + USARTx->CR1_f.PCE = (uint32_t)1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART parity bit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartParityNone USART none parity + ** \retval UsartParityEven USART even parity + ** \retval UsartParityOdd USART odd parity + ** + ******************************************************************************/ +en_usart_parity_t USART_GetParity(M4_USART_TypeDef *USARTx) +{ + en_usart_parity_t enParity = UsartParityNone; + + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + if(0ul == USARTx->CR1_f.PCE) + { + enParity = UsartParityNone; + } + else if(0ul == USARTx->CR1_f.PS) + { + enParity = UsartParityEven; + } + else + { + enParity = UsartParityOdd; + } + + return enParity; +} + +/** + ******************************************************************************* + ** \brief Set USART over sampling. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enSampleMode USART parity selection + ** \arg UsartSampleBit16 16 Bit + ** \arg UsartSampleBit8 8 Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetOverSampling(M4_USART_TypeDef *USARTx, + en_usart_sample_mode_t enSampleMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_SAMPLE_MODE(enSampleMode)); + + USARTx->CR1_f.OVER8 = (uint32_t)enSampleMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART over sampling. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartSampleBit16 16 Bit + ** \retval UsartSampleBit8 8 Bit + ** + ******************************************************************************/ +en_usart_sample_mode_t USART_GetOverSampling(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sample_mode_t)USARTx->CR1_f.OVER8; +} + +/** + ******************************************************************************* + ** \brief Set USART data transfer direction. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDir USART data direction selection + ** \arg UsartDataLsbFirst USART data LSB first + ** \arg UsartDataMsbFirst USART data MSB first + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetTransferDirection(M4_USART_TypeDef *USARTx, + en_usart_data_dir_t enDir) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_DATA_DIR(enDir)); + + USARTx->CR1_f.ML = (uint32_t)enDir; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART data transfer direction. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartDataLsbFirst USART data LSB first + ** \retval UsartDataMsbFirst USART data MSB first + ** + ******************************************************************************/ +en_usart_data_dir_t USART_GetTransferDirection(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_data_dir_t)(USARTx->CR1_f.ML); +} + +/** + ******************************************************************************* + ** \brief Set USART data bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDataLen USART data bit length + ** \arg UsartDataBits8 8 Bit + ** \arg UsartDataBits8 9 Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetDataLength(M4_USART_TypeDef *USARTx, + en_usart_data_len_t enDataLen) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_DATA_LEN(enDataLen)); + + USARTx->CR1_f.M = (uint32_t)enDataLen; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART data bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartDataBits8 Data bit length:8 Bits + ** \retval UsartDataBits8 Data bit length:9 Bits + ** + ******************************************************************************/ +en_usart_data_len_t USART_GetDataLength(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_data_len_t)(USARTx->CR1_f.M); +} + +/** + ******************************************************************************* + ** \brief Set USART clock mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enClkMode USART clock mode selection + ** \arg UsartExtClk Select external clock source + ** \arg UsartIntClkCkOutput Select internal clock source and output clock + ** \arg UsartIntClkCkNoOutput Select internal clock source and don't output clock + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetClkMode(M4_USART_TypeDef *USARTx, + en_usart_clk_mode_t enClkMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_CLK_MODE(enClkMode)); + + USARTx->CR2_f.CLKC = (uint32_t)enClkMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartExtClk Select external clock source + ** \retval UsartIntClkCkOutput Select internal clock source and output clock + ** \retval UsartIntClkCkNoOutput Select internal clock source and don't output clock + ** + ******************************************************************************/ +en_usart_clk_mode_t USART_GetClkMode(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_clk_mode_t)(USARTx->CR2_f.CLKC); +} + +/** + ******************************************************************************* + ** \brief Set USART mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enMode USART clock mode selection + ** \arg UsartUartMode UART mode + ** \arg UsartClkSyncMode Clock sync mode + ** \arg UsartSmartCardMode Smart card mode + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - USARTx is invalid + ** - enMode is invalid + ** + ******************************************************************************/ +en_result_t USART_SetMode(M4_USART_TypeDef *USARTx, + en_usart_mode_t enMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if(IS_VALID_USART(USARTx)) + { + enRet = Ok; + switch(enMode) + { + case UsartUartMode: + USARTx->CR3_f.SCEN = (uint32_t)0ul; + USARTx->CR1_f.MS = (uint32_t)0ul; + break; + case UsartClkSyncMode: + USARTx->CR3_f.SCEN = (uint32_t)0ul; + USARTx->CR1_f.MS = (uint32_t)1ul; + break; + case UsartSmartCardMode: + USARTx->CR3_f.SCEN = (uint32_t)1ul; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartUartMode UART mode + ** \retval UsartClkSyncMode Clock sync mode + ** \retval UsartSmartCardMode Smart card mode + ** + ******************************************************************************/ +en_usart_mode_t USART_GetMode(M4_USART_TypeDef *USARTx) +{ + en_usart_mode_t enMode; + + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + if (1ul == USARTx->CR3_f.SCEN) + { + enMode = UsartSmartCardMode; + } + else if (1ul == USARTx->CR1_f.MS) + { + enMode = UsartClkSyncMode; + } + else + { + enMode = UsartUartMode; + } + + return enMode; +} + +/** + ******************************************************************************* + ** \brief Set USART stop bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enStopBit USART stop bit selection + ** \arg UsartOneStopBit 1 Stop Bit + ** \arg UsartTwoStopBits 2 Stop Bit + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetStopBitsLength(M4_USART_TypeDef *USARTx, + en_usart_stop_bit_t enStopBit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_STOP_BIT(enStopBit)); + + USARTx->CR2_f.STOP = (uint32_t)enStopBit; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART stop bit length. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartOneStopBit 1 Stop Bit + ** \retval UsartTwoStopBits 2 Stop Bit + ** + ******************************************************************************/ +en_usart_stop_bit_t USART_GetStopBitsLength(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_stop_bit_t)(USARTx->CR2_f.STOP); +} + +/** + ******************************************************************************* + ** \brief Set USART detect mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enDetectMode USART start bit detect mode + ** \arg UsartStartBitLowLvl Start bit: RD pin low level + ** \arg UsartStartBitFallEdge Start bit: RD pin falling edge + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetSbDetectMode(M4_USART_TypeDef *USARTx, + en_usart_sb_detect_mode_t enDetectMode) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_SB_DETECT_MODE(enDetectMode)); + + USARTx->CR1_f.SBS = (uint32_t)enDetectMode; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART detect mode. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartStartBitLowLvl Start bit: RD pin low level + ** \retval UsartStartBitFallEdge Start bit: RD pin falling edge + ** + ******************************************************************************/ +en_usart_sb_detect_mode_t USART_GetSbDetectMode(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sb_detect_mode_t)(USARTx->CR1_f.SBS); +} + + +/** + ******************************************************************************* + ** \brief Set USART hardware flow control. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enHwFlowCtrl Hardware flow control + ** \arg UsartRtsEnable Enable RTS + ** \arg UsartCtsEnable Enable CTS + ** + ** \retval Ok Set successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, + en_usart_hw_flow_ctrl_t enHwFlowCtrl) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_HW_FLOW_MODE(enHwFlowCtrl)); + + USARTx->CR3_f.CTSE = (uint32_t)enHwFlowCtrl; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART hardware flow control. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartRtsEnable Enable RTS + ** \retval UsartCtsEnable Enable CTS + ** + ******************************************************************************/ +en_usart_hw_flow_ctrl_t USART_GetHwFlowCtrl(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_hw_flow_ctrl_t)(USARTx->CR3_f.CTSE); +} + +/** + ******************************************************************************* + ** \brief Set USART clock prescale. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enClkPrescale USART clock prescale + ** \arg UsartClkDiv_0 PCLK/1 + ** \arg UsartClkDiv_4 PCLK/4 + ** \arg UsartClkDiv_16 PCLK/16 + ** \arg UsartClkDiv_64 PCLK/64 + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetClockDiv(M4_USART_TypeDef *USARTx, + en_usart_clk_div_t enClkPrescale) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_CLK_DIV(enClkPrescale)); + + USARTx->PR_f.PSC = (uint32_t)enClkPrescale; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock division. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartClkDiv_0 PCLK/1 + ** \retval UsartClkDiv_4 PCLK/4 + ** \retval UsartClkDiv_16 PCLK/16 + ** \retval UsartClkDiv_64 PCLK/64 + ** + ******************************************************************************/ +en_usart_clk_div_t USART_GetClockDiv(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_clk_div_t)(USARTx->PR_f.PSC); +} + +/** + ******************************************************************************* + ** \brief Set USART ETU clocks of smart card. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] enEtuClk ETU clocks of smart card + ** \arg UsartScEtuClk32 1 etu = 32/f + ** \arg UsartScEtuClk64 1 etu = 64/f + ** \arg UsartScEtuClk93 1 etu = 93/f + ** \arg UsartScEtuClk128 1 etu = 128/f + ** \arg UsartScEtuClk186 1 etu = 186/f + ** \arg UsartScEtuClk256 1 etu = 256/f + ** \arg UsartScEtuClk372 1 etu = 372/f + ** \arg UsartScEtuClk512 1 etu = 512/f + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetScEtuClk(M4_USART_TypeDef *USARTx, + en_usart_sc_etu_clk_t enEtuClk) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + /* Check parameter */ + DDL_ASSERT(IS_VALID_USART_ETU_CLK(enEtuClk)); + + USARTx->CR3_f.BCN = (uint32_t)enEtuClk; + enRet = Ok; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set USART ETU clocks of smart card. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval UsartScEtuClk32 1 etu = 32/f + ** \retval UsartScEtuClk64 1 etu = 64/f + ** \retval UsartScEtuClk93 1 etu = 93/f + ** \retval UsartScEtuClk128 1 etu = 128/f + ** \retval UsartScEtuClk186 1 etu = 186/f + ** \retval UsartScEtuClk256 1 etu = 256/f + ** \retval UsartScEtuClk372 1 etu = 372/f + ** \retval UsartScEtuClk512 1 etu = 512/f + ** + ******************************************************************************/ +en_usart_sc_etu_clk_t USART_GetScEtuClk(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return (en_usart_sc_etu_clk_t)(USARTx->CR3_f.BCN); +} + +/** + ****************************************************************************** + ** \brief Write UART data buffer + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u16Data Send data + ** + ** \retval Ok Data has been successfully sent + ** + ******************************************************************************/ +en_result_t USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + USARTx->DR_f.TDR = (uint32_t)u16Data; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief Read UART data buffer + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t USART_RecData(M4_USART_TypeDef *USARTx) +{ + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + return ((uint16_t)(USARTx->DR_f.RDR)); +} + +/** + ******************************************************************************* + ** \brief Set USART baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + if(1ul == USARTx->CR3_f.SCEN) + { + enRet = SetScBaudrate(USARTx, u32Baudrate); + } + else if(1ul == USARTx->CR1_f.MS) + { + enRet = SetClkSyncBaudrate(USARTx, u32Baudrate); + } + else + { + enRet = SetUartBaudrate(USARTx, u32Baudrate); + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set UART mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B = 0ul; + uint32_t C = 0ul; + uint32_t OVER8 = 0ul; + float32_t DIV = 0.0f; + uint64_t u64Tmp = 0u; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + + if (C > 0ul) + { + B = u32Baudrate; + OVER8 = USARTx->CR1_f.OVER8; + /* FBME = 0 Calculation formula */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0f * (2.0f - (float)OVER8))) - 1.0f; + DIV_Integer = (uint32_t)(DIV); + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B) / C) - 128 */ + /* E = (C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B)) - 1 */ + /* DIV_Fraction = (((2 - OVER8) * (DIV_Integer + 1) * 2048 * B) / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)2ul - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1ul) * (uint64_t)B); + DIV_Fraction = (uint32_t)(2048ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set smart card mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetScBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B = 0ul; + uint32_t C = 0ul; + uint32_t S = 0ul; + float32_t DIV = 0.0f; + uint64_t u64Tmp = 0u; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + const uint16_t au16EtuClkCnts[] = {32u, 64u, 93u, 128u, 186u, 256u, 372u, 512u}; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + + if (C > 0ul) + { + B = u32Baudrate; + S = au16EtuClkCnts[USARTx->CR3_f.BCN]; + + /* FBME = 0 Calculation formula */ + /* B = C / (2 * S * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * S)) - 1 */ + DIV = ((float)C / ((float)B * (float)S * 2.0f)) - 1.0f; + DIV_Integer = (uint32_t)DIV; + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / ((2 * S) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((2 * S) * (DIV_Integer + 1) * 256 * B / C) - 128 */ + /* DIV_Fraction = ((DIV_Integer + 1) * B * S * 512 / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)DIV_Integer + 1ul) * B * S); + DIV_Fraction = (uint32_t)(512ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set synchronous clock mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetClkSyncBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t C = 0ul; + uint32_t B = 0ul; + uint64_t u64Tmp = 0u; + float32_t DIV = 0.0f; + uint32_t DIV_Integer = 0ul; + uint32_t DIV_Fraction = 0xFFFFFFFFul; + en_result_t enRet = ErrorInvalidParameter; + + /* Check USARTx pointer */ + if (IS_VALID_USART(USARTx)) + { + C = UsartGetClk(USARTx); + if (C > 0ul) + { + B = u32Baudrate; + + /* FBME = 0 Calculation formula */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV = ((float)C / ((float)B * 4.0f)) - 1.0f; + DIV_Integer = (uint32_t)DIV; + + if (!((DIV < 0.0f) || (DIV_Integer > 0xFFul))) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (4 * (DIV_Integer + 1) * 256 * B / C) - 128 */ + /* DIV_Fraction = ((DIV_Integer + 1) * B * 1024 / C) - 128 */ + u64Tmp = (uint64_t)(((uint64_t)DIV_Integer + 1ul) * (uint64_t)B); + DIV_Fraction = (uint32_t)(1024ul * u64Tmp / C - 128ul); + if (DIV_Fraction > 0x7Ful) + { + enRet = ErrorInvalidParameter; + } + } + + if (Ok == enRet) + { + USARTx->CR1_f.FBME = (DIV_Fraction > 0x7Ful) ? 0ul : 1ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + } + } + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get USART clock + ** + ** \param [in] USARTx Pointer to USART instance register base + ** \arg M4_USART1 USART unit 1 instance register base + ** \arg M4_USART2 USART unit 2 instance register base + ** \arg M4_USART3 USART unit 3 instance register base + ** \arg M4_USART4 USART unit 4 instance register base + ** + ** \retval USART clock frequency + ** + ******************************************************************************/ +static uint32_t UsartGetClk(const M4_USART_TypeDef *USARTx) +{ + uint32_t u32PClk1 = 0ul; + uint32_t u32UartClk = 0ul; + + /* Check USARTx pointer */ + DDL_ASSERT(IS_VALID_USART(USARTx)); + + u32PClk1 = SystemCoreClock / (1ul << M4_SYSREG->CMU_SCFGR_f.PCLK1S); + u32UartClk = u32PClk1 / (1ul << (2ul * USARTx->PR_f.PSC)); + + return u32UartClk; +} + +//@} // UsartGroup + +#endif /* DDL_USART_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_utility.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_utility.c new file mode 100644 index 0000000000..e619d64f53 --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_utility.c @@ -0,0 +1,531 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_utility.c + ** + ** A detailed description is available at + ** @link DdlUtilityGroup Ddl Utility description @endlink + ** + ** - 2018-11-02 CDT First version for Device Driver Library Utility. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_utility.h" + +#if (DDL_UTILITY_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup DdlUtilityGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#if (DDL_PRINT_ENABLE == DDL_ON) +/*!< Parameter valid check for USART Instances. */ +#define IS_VALID_UART(x) \ +( (M4_USART1 == (x)) || \ + (M4_USART2 == (x)) || \ + (M4_USART3 == (x)) || \ + (M4_USART4 == (x))) + +#define UART_EnableClk(x) \ +do { \ + if (M4_USART1 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART1 = 0ul; \ + } \ + else if (M4_USART2 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART2 = 0ul; \ + } \ + else if (M4_USART3 == (x)) \ + { \ + M4_MSTP->FCG1_f.USART3 = 0ul; \ + } \ + else \ + { \ + M4_MSTP->FCG1_f.USART4 = 0ul; \ + } \ +} while (0) +#endif + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +#if (DDL_PRINT_ENABLE == DDL_ON) +static M4_USART_TypeDef *m_PrintfDevice; +static uint32_t m_u32PrintfTimeout; +#endif + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +#if (DDL_PRINT_ENABLE == DDL_ON) +/** + ******************************************************************************* + ** \brief UART transmit. + ** + ** \param [in] USARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] cData The data for transmitting + ** + ** \retval An en_result_t enumeration value: + ** - Ok: Send successfully + ** - ErrorTimeout: Send timeout + ** - ErrorInvalidParameter: The parameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t UartPutChar(M4_USART_TypeDef *USARTx, char cData) +{ + uint32_t u32TxEmpty; + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t u32Timeout = m_u32PrintfTimeout; + + if (NULL != USARTx) + { + /* Wait TX data register empty */ + do + { + u32Timeout--; + u32TxEmpty = USARTx->SR_f.TXE; + } while ((u32Timeout > 0ul) && (0ul == u32TxEmpty)); + + if (u32TxEmpty > 0ul) + { + USARTx->DR = (uint32_t)cData; + enRet = Ok; + } + else + { + enRet = ErrorTimeout; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Set synchronous clock mode baudrate + ** + ** \param [in] USARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** + ** \retval Ok Configure successfully. + ** \retval ErrorInvalidParameter USARTx is invalid + ** + ******************************************************************************/ +static en_result_t SetUartBaudrate(M4_USART_TypeDef *USARTx, uint32_t u32Baudrate) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + float32_t DIV; + uint64_t u64Tmp; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + uint32_t u32PClk1; + uint32_t u32UartClk; + en_result_t enRet = ErrorInvalidParameter; + + u32PClk1 = SystemCoreClock / (1ul << (M4_SYSREG->CMU_SCFGR_f.PCLK1S)); + u32UartClk = u32PClk1 / (1ul << (2ul * (USARTx->PR_f.PSC))); + + B = u32Baudrate; + C = u32UartClk; + DIV_Fraction = 0ul; + + if ((0ul != C) && (0ul != B)) + { + OVER8 = USARTx->CR1_f.OVER8; + + /* FBME = 0 Calculation formula */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0f * (2.0f - (float)OVER8))) - 1.0f; + DIV_Integer = (uint32_t)(DIV); + + if ((DIV < 0.0f) || (DIV_Integer > 0xFFul)) + { + enRet = ErrorInvalidParameter; + } + else + { + if ((DIV - (float32_t)DIV_Integer) > 0.00001f) + { + /* FBME = 1 Calculation formula */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = ((8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B) / C) - 128 */ + /* E = (C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256 * B)) - 1 */ + /* DIV_Fraction = (((2 - OVER8) * (DIV_Integer + 1) * 2048 * B) / C) - 128 */ + u64Tmp = (2u - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1u) * (uint64_t)B; + DIV_Fraction = (uint32_t)(2048ul * u64Tmp/C - 128ul); + } + + USARTx->CR1_f.FBME = (DIV_Fraction > 0UL) ? 1ul : 0ul; + USARTx->BRR_f.DIV_FRACTION = DIV_Fraction; + USARTx->BRR_f.DIV_INTEGER = DIV_Integer; + enRet = Ok; + } + } + + return enRet; +} + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + ******************************************************************************* + ** \brief Re-target _write function. + ** + ** \param [in] fd + ** \param [in] data + ** \param [in] size + ** + ** \retval int32_t + ** + ******************************************************************************/ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) + { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) + { + if (Ok != UartPutChar(m_PrintfDevice, data[i])) + { + break; + } + } + } + + return i ? i : -1; +} + +#else +/** + ******************************************************************************* + ** \brief Re-target fputc function. + ** + ** \param [in] ch + ** \param [in] f + ** + ** \retval int32_t + ** + ******************************************************************************/ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (Ok == UartPutChar(m_PrintfDevice, (char)ch)) ? ch: -1; +} +#endif + +/** + ******************************************************************************* + ** \brief Debug printf initialization function + ** + ** \param [in] UARTx Pointer to USART instance register base + ** This parameter can be one of the following values: + ** @arg M4_USART1: USART unit 1 instance register base + ** @arg M4_USART2: USART unit 2 instance register base + ** @arg M4_USART3: USART unit 3 instance register base + ** @arg M4_USART4: USART unit 4 instance register base + ** \param [in] u32Baudrate Baudrate + ** \param [in] PortInit The pointer of printf port initialization function + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t UART_PrintfInit(M4_USART_TypeDef *UARTx, + uint32_t u32Baudrate, + void (*PortInit)(void)) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (IS_VALID_UART(UARTx) && (0ul != u32Baudrate) && (NULL != PortInit)) + { + /* Initialize port */ + PortInit(); + + /* Enable clock */ + UART_EnableClk(UARTx); + + /* Initialize USART */ + UARTx->CR1_f.ML = 0ul; /* LSB */ + UARTx->CR1_f.MS = 0ul; /* UART mode */ + UARTx->CR1_f.OVER8 = 1ul; /* 8bit sampling mode */ + UARTx->CR1_f.M = 0ul; /* 8 bit data length */ + UARTx->CR1_f.PCE = 0ul; /* no parity bit */ + + /* Set baudrate */ + if(Ok != SetUartBaudrate(UARTx, u32Baudrate)) + { + enRet = Error; + } + else + { + UARTx->CR2 = 0ul; /* 1 stop bit, single uart mode */ + UARTx->CR3 = 0ul; /* CTS disable, Smart Card mode disable */ + UARTx->CR1_f.TE = 1ul; /* TX enable */ + + m_PrintfDevice = UARTx; + m_u32PrintfTimeout = (SystemCoreClock / u32Baudrate); + } + } + + return enRet; +} +#endif /* DDL_PRINT_ENABLE */ + +/** + ******************************************************************************* + ** \brief Delay function, delay 1ms approximately + ** + ** \param [in] u32Cnt ms + ** + ** \retval none + ** + ******************************************************************************/ +void Ddl_Delay1ms(uint32_t u32Cnt) +{ + volatile uint32_t i; + uint32_t u32Cyc; + + u32Cyc = SystemCoreClock; + u32Cyc = u32Cyc / 10000ul; + while (u32Cnt-- > 0ul) + { + i = u32Cyc; + while (i-- > 0ul) + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief Delay function, delay 1us approximately + ** + ** \param [in] u32Cnt us + ** + ** \retval none + ** + ******************************************************************************/ +void Ddl_Delay1us(uint32_t u32Cnt) +{ + uint32_t u32Cyc; + volatile uint32_t i; + + if(SystemCoreClock > 10000000ul) + { + u32Cyc = SystemCoreClock / 10000000ul; + while(u32Cnt-- > 0ul) + { + i = u32Cyc; + while (i-- > 0ul) + { + ; + } + } + } + else + { + while(u32Cnt-- > 0ul) + { + ; + } + } +} + +/** + ******************************************************************************* + ** \brief This function Initializes the interrupt frequency of the SysTick. + ** + ** \param [in] u32Freq SysTick interrupt frequency (1 to 1000). + ** + ** \retval Ok SysTick Initializes succeed + ** \retval Error SysTick Initializes failed + ** + ******************************************************************************/ +__WEAKDEF en_result_t SysTick_Init(uint32_t u32Freq) +{ + en_result_t enRet = Error; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) + { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(SystemCoreClock / u32Freq)) + { + enRet = Ok; + } + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief This function provides minimum delay (in milliseconds). + ** + ** \param [in] u32Delay Delay specifies the delay time. + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) + { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) + { + tickEnd = tickMax; + } + else + { + tickEnd = u32Delay + m_u32TickStep; + } + + while ((SysTick_GetTick() - tickStart) < tickEnd) + { + } + } +} + +/** + ******************************************************************************* + ** \brief This function is called to increment a global variable "u32TickCount". + ** \note This variable is incremented in SysTick ISR. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + ******************************************************************************* + ** \brief Provides a tick value in millisecond. + ** + ** \param None + ** + ** \retval Tick value + ** + ******************************************************************************/ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + ******************************************************************************* + ** \brief Suspend SysTick increment. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + ******************************************************************************* + ** \brief Resume SysTick increment. + ** + ** \param None + ** + ** \retval None + ** + ******************************************************************************/ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + ******************************************************************************* + ** \brief ddl assert error handle function + ** + ** \param [in] file Point to the current assert the wrong file + ** \param [in] line Point line assert the wrong file in the current + ** + ******************************************************************************/ +#ifdef __DEBUG +__WEAKDEF void Ddl_AssertHandler(uint8_t *file, int16_t line) +{ + /* Users can re-implement this function to print information */ +#if (DDL_PRINT_ENABLE == DDL_ON) + printf("Wrong parameters value: file %s on line %d\r\n", file, line); +#else + (void)file; + (void)line; +#endif + for (;;) + { + ; + } +} +#endif /* __DEBUG */ + +//@} // DdlUtilityGroup + +#endif /* DDL_UTILITY_ENABLE */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_wdt.c b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_wdt.c new file mode 100644 index 0000000000..c4c56d947c --- /dev/null +++ b/bsp/hc32f460/Libraries/HC32F460_StdPeriph_Driver/src/hc32f460_wdt.c @@ -0,0 +1,254 @@ +/******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + */ +/******************************************************************************/ +/** \file hc32f460_wdt.c + ** + ** A detailed description is available at + ** @link WdtGroup Watchdog Counter description @endlink + ** + ** - 2018-10-18 CDT First version for Device Driver Library of WDT. + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_wdt.h" +#include "hc32f460_utility.h" + +#if (DDL_WDT_ENABLE == DDL_ON) + +/** + ******************************************************************************* + ** \addtogroup WdtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/*!< Parameter validity check for count cycle */ +#define IS_VALID_COUNT_CYCLE(x) \ +( (WdtCountCycle256 == (x)) || \ + (WdtCountCycle4096 == (x)) || \ + (WdtCountCycle16384 == (x)) || \ + (WdtCountCycle65536 == (x))) + +/*!< Parameter validity check for clock division */ +#define IS_VALID_CLOCK_DIV(x) \ +( (WdtPclk3Div4 == (x)) || \ + (WdtPclk3Div64 == (x)) || \ + (WdtPclk3Div128 == (x)) || \ + (WdtPclk3Div256 == (x)) || \ + (WdtPclk3Div512 == (x)) || \ + (WdtPclk3Div1024 == (x)) || \ + (WdtPclk3Div2048 == (x)) || \ + (WdtPclk3Div8192 == (x))) + +/*!< Parameter validity check for allow refresh percent range */ +#define IS_VALID_ALLOW_REFRESH_RANGE(x) \ +( (WdtRefresh100Pct == (x)) || \ + (WdtRefresh0To25Pct == (x)) || \ + (WdtRefresh25To50Pct == (x)) || \ + (WdtRefresh0To50Pct == (x)) || \ + (WdtRefresh50To75Pct == (x)) || \ + (WdtRefresh0To25PctAnd50To75Pct == (x)) || \ + (WdtRefresh25To75Pct == (x)) || \ + (WdtRefresh0To75Pct == (x)) || \ + (WdtRefresh75To100Pct == (x)) || \ + (WdtRefresh0To25PctAnd75To100Pct == (x)) || \ + (WdtRefresh25To50PctAnd75To100Pct == (x)) || \ + (WdtRefresh0To50PctAnd75To100Pct == (x)) || \ + (WdtRefresh50To100Pct == (x)) || \ + (WdtRefresh0To25PctAnd50To100Pct == (x)) || \ + (WdtRefresh25To100Pct == (x)) || \ + (WdtRefresh0To100Pct == (x))) + +/*!< Parameter validity check for event request type */ +#define IS_VALID_EVENT_REQUEST_TYPE(x) \ +( (WdtTriggerInterruptRequest == (x)) || \ + (WdtTriggerResetRequest == (x))) + +/*!< Parameter validity check for flag type */ +#define IS_VALID_FLAG_TYPE(x) \ +( (WdtFlagCountUnderflow == (x)) || \ + (WdtFlagRefreshError == (x))) + +/*!< WDT_RR register refresh key */ +#define WDT_REFRESH_START_KEY ((uint16_t)0x0123) +#define WDT_REFRESH_END_KEY ((uint16_t)0x3210) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief Initialize WDT function + ** + ** \param [in] pstcWdtInit Pointer to WDT init configuration + ** \arg See the struct #stc_wdt_init_t + ** + ** \retval Ok Process successfully done + ** \retval Error Parameter error + ** + ******************************************************************************/ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + en_result_t enRet = Ok; + uint32_t regTemp; + + if (NULL == pstcWdtInit) + { + enRet = Error; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_COUNT_CYCLE(pstcWdtInit->enCountCycle)); + DDL_ASSERT(IS_VALID_CLOCK_DIV(pstcWdtInit->enClkDiv)); + DDL_ASSERT(IS_VALID_ALLOW_REFRESH_RANGE(pstcWdtInit->enRefreshRange)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcWdtInit->enSleepModeCountEn)); + DDL_ASSERT(IS_VALID_EVENT_REQUEST_TYPE(pstcWdtInit->enRequestType)); + + /* software start mode */ + regTemp = ((((uint32_t)pstcWdtInit->enRequestType) << 31) | \ + (((uint32_t)(bool)(!pstcWdtInit->enSleepModeCountEn)) << 16) | \ + (((uint32_t)pstcWdtInit->enRefreshRange) << 8) | \ + (((uint32_t)pstcWdtInit->enClkDiv) << 4) | \ + ((uint32_t)pstcWdtInit->enCountCycle)); + /* store the new value */ + M4_WDT->CR = regTemp; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief WDT refresh counter(First refresh start count when software start) + ** + ** \param [in] None + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t WDT_RefreshCounter(void) +{ + en_result_t enRet = Ok; + + M4_WDT->RR = WDT_REFRESH_START_KEY; + M4_WDT->RR = WDT_REFRESH_END_KEY; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief Get WDT counter current count value + ** + ** \param [in] None + ** + ** \retval uint16_t WDT counter current count value + ** + ******************************************************************************/ +uint16_t WDT_GetCountValue(void) +{ + return ((uint16_t)M4_WDT->SR_f.CNT); +} + +/** + ******************************************************************************* + ** \brief Get WDT flag status + ** + ** \param [in] enFlag WDT flag type + ** \arg WdtFlagCountUnderflow Count underflow flag + ** \arg WdtFlagRefreshError Refresh error flag + ** + ** \retval Set Flag is set + ** \retval Reset Flag is reset + ** + ******************************************************************************/ +en_flag_status_t WDT_GetFlag(en_wdt_flag_type_t enFlag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case WdtFlagCountUnderflow: + enFlagSta = (en_flag_status_t)M4_WDT->SR_f.UDF; + break; + case WdtFlagRefreshError: + enFlagSta = (en_flag_status_t)M4_WDT->SR_f.REF; + break; + default: + break; + } + + return enFlagSta; +} + +/** + ******************************************************************************* + ** \brief Clear WDT flag status + ** + ** \param [in] enFlag WDT flag type + ** \arg WdtFlagCountUnderflow Count underflow flag + ** \arg WdtFlagRefreshError Refresh error flag + ** + ** \retval Ok Process successfully done + ** + ******************************************************************************/ +en_result_t WDT_ClearFlag(en_wdt_flag_type_t enFlag) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_FLAG_TYPE(enFlag)); + + switch (enFlag) + { + case WdtFlagCountUnderflow: + M4_WDT->SR_f.UDF = 0u; + break; + case WdtFlagRefreshError: + M4_WDT->SR_f.REF = 0u; + break; + default: + break; + } + + return enRet; +} + +//@} // WdtGroup + +#endif /* DDL_WDT_ENABLE */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f460/Libraries/LICENSE b/bsp/hc32f460/Libraries/LICENSE new file mode 100644 index 0000000000..72823826b8 --- /dev/null +++ b/bsp/hc32f460/Libraries/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2020, Huada Semiconductor Co., Ltd ("HDSC") +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/hc32f460/Libraries/SConscript b/bsp/hc32f460/Libraries/SConscript new file mode 100644 index 0000000000..d34278922c --- /dev/null +++ b/bsp/hc32f460/Libraries/SConscript @@ -0,0 +1,47 @@ +# RT-Thread building script for bridge + +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +CMSIS/Device/HDSC/HC32F460/Source/system_hc32f460.c +HC32F460_StdPeriph_Driver/src/hc32f460_clk.c +HC32F460_StdPeriph_Driver/src/hc32f460_efm.c +HC32F460_StdPeriph_Driver/src/hc32f460_gpio.c +HC32F460_StdPeriph_Driver/src/hc32f460_icg.c +HC32F460_StdPeriph_Driver/src/hc32f460_interrupts.c +HC32F460_StdPeriph_Driver/src/hc32f460_pwc.c +HC32F460_StdPeriph_Driver/src/hc32f460_sram.c +HC32F460_StdPeriph_Driver/src/hc32f460_utility.c +HC32F460_StdPeriph_Driver/src/hc32f460_exint_nmi_swi.c +""") + +#src += Glob('HC32F460_StdPeriph_Driver/src/*.c') + +if GetDepend(['RT_USING_SERIAL']): + src += ['HC32F460_StdPeriph_Driver/src/hc32f460_usart.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/HDSC/HC32F460/Source/GCC/startup_hc32f460.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/HDSC/HC32F460/Source/ARM/startup_hc32f460.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/HDSC/HC32F460/Source/IAR/startup_hc32f460.s'] + +#add headfile script +path = [cwd + '/CMSIS/Include', + cwd + '/CMSIS/Device/HDSC/HC32F460/Include', + cwd + '/HC32F460_StdPeriph_Driver/inc'] + + +CPPDEFINES = ['USE_DEVICE_DRIVER_LIB', rtconfig.MCU_TYPE, '__DEBUG'] + +group = DefineGroup('HC32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32f460/README.md b/bsp/hc32f460/README.md new file mode 100644 index 0000000000..cd49bd5ea2 --- /dev/null +++ b/bsp/hc32f460/README.md @@ -0,0 +1,59 @@ +# HC32F460PETB# + +## 1. 简介 + +[HC32F460](http://www.hdsc.com.cn/Category83-1487)系列是基于 ARM® Cortex®-M4 32-bit RISC CPU，最高工作频率 200MHz 的高性能MCU。 Cortex-M4 内核集成了浮点运算单元（ FPU） 和 DSP，实现单精度浮点算术运算，支持所有 ARM 单精度数据处理指令和数据类型，支持完整 DSP 指令集。HC32F460 系列集成了高速片上存储器，包括最大 512KB 的 Flash，最大 192KB 的 SRAM。 +主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|CPU| Cortex-M4| +|主频| 100MHz | +|SRAM| 192KB | +|Flash| 512KB | + +## 2. 编译说明 + +目前仅支持支持 MDK5，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| -- | -- | +| MDK5(ARM Compiler 5) | MDK5.31 | + +## 3. 烧写及仿真 + +下载程序：使用板载 J-Link 工具。 + +## 4. 驱动支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | USART1/2/3/4 | +| GPIO | 支持 | | +##5.运行结果 +下载程序成功之后，系统会自动运行，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Sep 3 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +6.进阶使用 +默认只开启了 GPIO 输出、中断和 串口4的功能，更多接口需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 5. 联系人信息 + +维护人： + +- [lizhengyang](https://github.com/GoldBr1987) + diff --git a/bsp/hc32f460/SConscript b/bsp/hc32f460/SConscript new file mode 100644 index 0000000000..24bb4646ab --- /dev/null +++ b/bsp/hc32f460/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32f460/SConstruct b/bsp/hc32f460/SConstruct new file mode 100644 index 0000000000..bb318fb969 --- /dev/null +++ b/bsp/hc32f460/SConstruct @@ -0,0 +1,45 @@ +import os +import sys +import rtconfig + +print "############sconstruct##############" +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +print "RTT_ROOT: " + RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'hc32f460.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +print "######################env:" +print env +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32f460/applications/SConscript b/bsp/hc32f460/applications/SConscript new file mode 100644 index 0000000000..6f66f7ab73 --- /dev/null +++ b/bsp/hc32f460/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f460/applications/main.c b/bsp/hc32f460/applications/main.c new file mode 100644 index 0000000000..617e1e8039 --- /dev/null +++ b/bsp/hc32f460/applications/main.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#include "board.h" +#include +#include + + +/* defined the LED1 pin: PE0 */ +#define LED1_PIN GET_PIN(E,0) +/* defined the LED2 pin: PE0 */ +#define LED2_PIN GET_PIN(E,1) +/* defined the KEY pin: PE13 */ +#define KEY_PIN GET_PIN(E,13) + +#define DELAY_MS (RT_TICK_PER_SECOND) /* 1s */ + +void LED2_Toggle(void *args) +{ + static uint8_t i; + if (i % 2 == 1) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + } + else + { + rt_pin_write(LED2_PIN, PIN_LOW); + } + i++; +} + +int32_t main(void) +{ + /* set LED1_PIN output*/ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + /* set LED2_PIN output*/ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + /*set KEY_PIN intput pullup*/ + rt_pin_mode(KEY_PIN, PIN_MODE_INPUT_PULLUP); + /*attach KEY_PIN irq*/ + rt_pin_attach_irq(KEY_PIN, PIN_IRQ_MODE_FALLING, LED2_Toggle, RT_NULL); + /*enable KEY_PIN irq*/ + rt_pin_irq_enable(KEY_PIN, PIN_IRQ_ENABLE); + + + rt_pin_write(LED1_PIN, PIN_HIGH); + while (1) + { + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_thread_delay(DELAY_MS); + rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_delay(DELAY_MS); + } +} + diff --git a/bsp/hc32f460/board/Kconfig b/bsp/hc32f460/board/Kconfig new file mode 100644 index 0000000000..dec846f03b --- /dev/null +++ b/bsp/hc32f460/board/Kconfig @@ -0,0 +1,41 @@ +menu "Hardware Drivers Config" + +config MCU_HC32F460 + bool + select ARCH_ARM_CORTEX_M4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default y + endif + +endmenu + + +endmenu diff --git a/bsp/hc32f460/board/SConscript b/bsp/hc32f460/board/SConscript new file mode 100644 index 0000000000..402340a1f2 --- /dev/null +++ b/bsp/hc32f460/board/SConscript @@ -0,0 +1,16 @@ + +from building import * + +cwd = GetCurrentDir() + +CPPPATH = [cwd] + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f460/board/board.c b/bsp/hc32f460/board/board.c new file mode 100644 index 0000000000..6eb57a4cdc --- /dev/null +++ b/bsp/hc32f460/board/board.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#include +#include +#include "board.h" + +void rt_os_tick_callback(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + + rt_interrupt_leave(); +} +void SysClkConfig(void) +{ + stc_clk_sysclk_cfg_t stcSysClkCfg; + stc_clk_xtal_cfg_t stcXtalCfg; + stc_clk_mpll_cfg_t stcMpllCfg; + stc_sram_config_t stcSramConfig; + + MEM_ZERO_STRUCT(stcSysClkCfg); + MEM_ZERO_STRUCT(stcXtalCfg); + MEM_ZERO_STRUCT(stcMpllCfg); + + /* Set bus clk div. */ + stcSysClkCfg.enHclkDiv = ClkSysclkDiv1; + stcSysClkCfg.enExclkDiv = ClkSysclkDiv2; + stcSysClkCfg.enPclk0Div = ClkSysclkDiv1; + stcSysClkCfg.enPclk1Div = ClkSysclkDiv2; + stcSysClkCfg.enPclk2Div = ClkSysclkDiv4; + stcSysClkCfg.enPclk3Div = ClkSysclkDiv4; + stcSysClkCfg.enPclk4Div = ClkSysclkDiv2; + CLK_SysClkConfig(&stcSysClkCfg); + + /* Switch system clock source to MPLL. */ + /* Use Xtal as MPLL source. */ + stcXtalCfg.enMode = ClkXtalModeOsc; + stcXtalCfg.enDrv = ClkXtalLowDrv; + + stcXtalCfg.enFastStartup = Enable; + CLK_XtalConfig(&stcXtalCfg); + CLK_XtalCmd(Enable); + + while (Set != CLK_GetFlagStatus(ClkFlagXTALRdy)) + { + ; + } + + /* MPLL config. */ + stcMpllCfg.pllmDiv = 1ul; + stcMpllCfg.plln = 50ul; + stcMpllCfg.PllpDiv = 4ul; + stcMpllCfg.PllqDiv = 4ul; + stcMpllCfg.PllrDiv = 4ul; + CLK_SetPllSource(ClkPllSrcXTAL); + CLK_MpllConfig(&stcMpllCfg); + + /* flash read wait cycle setting */ + EFM_Unlock(); + EFM_SetLatency(5ul); + EFM_Lock(); + + /* sram init include read/write wait cycle setting */ + stcSramConfig.u8SramIdx = Sram12Idx | Sram3Idx | SramHsIdx | SramRetIdx; + stcSramConfig.enSramRC = SramCycle2; + stcSramConfig.enSramWC = SramCycle2; + stcSramConfig.enSramEccMode = EccMode3; + stcSramConfig.enSramEccOp = SramNmi; + stcSramConfig.enSramPyOp = SramNmi; + SRAM_Init(&stcSramConfig); + + /* Enable MPLL. */ + CLK_MpllCmd(Enable); + + /* Wait MPLL ready. */ + while (Set != CLK_GetFlagStatus(ClkFlagMPLLRdy)) + { + ; + } + /* Switch system clock source to MPLL. */ + CLK_SetSysClkSource(CLKSysSrcMPLL); +} +void SysTick_Handler(void) +{ + rt_os_tick_callback(); +} + +/** + * This function will initial your board. + */ +void rt_hw_board_init(void) +{ + SysClkConfig(); + SysTick_Init(RT_TICK_PER_SECOND); + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} diff --git a/bsp/hc32f460/board/board.h b/bsp/hc32f460/board/board.h new file mode 100644 index 0000000000..8530ee7221 --- /dev/null +++ b/bsp/hc32f460/board/board.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ddl.h" +#include "drv_gpio.h" + +/* board configuration */ +#define SRAM_BASE 0x1FFF8000 +#define SRAM_SIZE 32*1024 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) + +/* High speed sram. */ +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN (&__bss_end) +#endif + +#ifdef __ICCARM__ + /* Use *.icf ram symbal, to avoid hardcode.*/ + extern char __ICFEDIT_region_RAM_end__; + #define HEAP_END (&__ICFEDIT_region_RAM_end__) +#else + #define HEAP_END SRAM_END +#endif + +void rt_hw_board_init(void); +void rt_hw_us_delay(rt_uint32_t us); + +#endif diff --git a/bsp/hc32f460/board/board_config.c b/bsp/hc32f460/board/board_config.c new file mode 100644 index 0000000000..4ad881d010 --- /dev/null +++ b/bsp/hc32f460/board/board_config.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#include +#include "board_config.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(M4_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)M4_USART1: + /* Configure USART1 RX/TX pin. */ + PORT_SetFunc(USART1_RX_PORT, USART1_RX_PIN, Func_Usart1_Rx, Disable); + PORT_SetFunc(USART1_TX_PORT, USART1_TX_PIN, Func_Usart1_Tx, Disable); + break; +#endif +#if defined(BSP_USING_UART2) + case (rt_uint32_t)M4_USART2: + /* Configure USART2 RX/TX pin. */ + PORT_SetFunc(USART2_RX_PORT, USART2_RX_PIN, Func_Usart2_Rx, Disable); + PORT_SetFunc(USART2_TX_PORT, USART2_TX_PIN, Func_Usart2_Tx, Disable); + break; +#endif +#if defined(BSP_USING_UART3) + case (rt_uint32_t)M4_USART3: + /* Configure USART3 RX/TX pin. */ + PORT_SetFunc(USART3_RX_PORT, USART3_RX_PIN, Func_Usart3_Rx, Disable); + PORT_SetFunc(USART3_TX_PORT, USART3_TX_PIN, Func_Usart3_Tx, Disable); + break; +#endif +#if defined(BSP_USING_UART4) + case (rt_uint32_t)M4_USART4: + /* Configure USART4 RX/TX pin. */ + PORT_SetFunc(USART4_RX_PORT, USART4_RX_PIN, Func_Usart4_Rx, Disable); + PORT_SetFunc(USART4_TX_PORT, USART4_TX_PIN, Func_Usart4_Tx, Disable); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + diff --git a/bsp/hc32f460/board/board_config.h b/bsp/hc32f460/board/board_config.h new file mode 100644 index 0000000000..0b3c73dda2 --- /dev/null +++ b/bsp/hc32f460/board/board_config.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ddl.h" + +/*********** Port configure *********/ +#if defined(BSP_USING_UART1) + #define USART1_RX_PORT (PortD) + #define USART1_RX_PIN (Pin00) + + #define USART1_TX_PORT (PortD) + #define USART1_TX_PIN (Pin01) +#endif + +#if defined(BSP_USING_UART2) + #define USART2_RX_PORT (PortC) + #define USART2_RX_PIN (Pin11) + + #define USART2_TX_PORT (PortC) + #define USART2_TX_PIN (Pin12) +#endif + +#if defined(BSP_USING_UART3) + #define USART3_RX_PORT (PortB) + #define USART3_RX_PIN (Pin08) + + #define USART3_TX_PORT (PortB) + #define USART3_TX_PIN (Pin09) +#endif + +#if defined(BSP_USING_UART4) + #define USART4_RX_PORT (PortC) + #define USART4_RX_PIN (Pin07) + + #define USART4_TX_PORT (PortC) + #define USART4_TX_PIN (Pin06) +#endif + +/*********** USART configure *********/ +#if defined(BSP_USING_UART1) + #define USART1_RXERR_INT_IRQn (Int001_IRQn) + #define USART1_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define USART1_RX_INT_IRQn (Int002_IRQn) + #define USART1_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) +#endif + +#if defined(BSP_USING_UART2) + #define USART2_RXERR_INT_IRQn (Int003_IRQn) + #define USART2_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define USART2_RX_INT_IRQn (Int004_IRQn) + #define USART2_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) +#endif + +#if defined(BSP_USING_UART3) + #define USART3_RXERR_INT_IRQn (Int005_IRQn) + #define USART3_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define USART3_RX_INT_IRQn (Int006_IRQn) + #define USART3_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) +#endif + +#if defined(BSP_USING_UART4) + #define USART4_RXERR_INT_IRQn (Int007_IRQn) + #define USART4_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define USART4_RX_INT_IRQn (Int008_IRQn) + #define USART4_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) +#endif + + + +/*********** Pin configure *********/ +#if defined(RT_USING_PIN) + + #define EXINT0_INT_IRQn (Int016_IRQn) + #define EXINT0_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT1_INT_IRQn (Int017_IRQn) + #define EXINT1_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT2_INT_IRQn (Int018_IRQn) + #define EXINT2_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT3_INT_IRQn (Int019_IRQn) + #define EXINT3_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT4_INT_IRQn (Int020_IRQn) + #define EXINT4_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT5_INT_IRQn (Int021_IRQn) + #define EXINT5_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT6_INT_IRQn (Int022_IRQn) + #define EXINT6_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT7_INT_IRQn (Int023_IRQn) + #define EXINT7_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT8_INT_IRQn (Int024_IRQn) + #define EXINT8_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT9_INT_IRQn (Int025_IRQn) + #define EXINT9_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT10_INT_IRQn (Int026_IRQn) + #define EXINT10_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT11_INT_IRQn (Int027_IRQn) + #define EXINT11_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT12_INT_IRQn (Int028_IRQn) + #define EXINT12_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT13_INT_IRQn (Int029_IRQn) + #define EXINT13_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT14_INT_IRQn (Int030_IRQn) + #define EXINT14_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + + #define EXINT15_INT_IRQn (Int031_IRQn) + #define EXINT15_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#endif + +#endif diff --git a/bsp/hc32f460/board/linker_scripts/link.icf b/bsp/hc32f460/board/linker_scripts/link.icf new file mode 100644 index 0000000000..397ec88b53 --- /dev/null +++ b/bsp/hc32f460/board/linker_scripts/link.icf @@ -0,0 +1,59 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00; +define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x1FFFFFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x2000FFFF; +define symbol __ICFEDIT_region_IRAM3_start__ = 0x20010000; +define symbol __ICFEDIT_region_IRAM3_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_IRAM4_start__ = 0x20020000; +define symbol __ICFEDIT_region_IRAM4_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM5_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM5_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__] + | mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__] + | mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__] + | mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32f460/board/linker_scripts/link.lds b/bsp/hc32f460/board/linker_scripts/link.lds new file mode 100644 index 0000000000..ab289f41dc --- /dev/null +++ b/bsp/hc32f460/board/linker_scripts/link.lds @@ -0,0 +1,200 @@ +/* +;******************************************************************************* +; * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by HDSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +*/ +/*****************************************************************************/ +/* File hc32f460xe_flash.ld */ +/* Abstract Linker script for HC32F460 Device with */ +/* 512KByte FLASH, 192KByte RAM */ +/* Version V1.0 */ +/* Date 2019-03-13 */ +/*****************************************************************************/ + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K + OTP (rx): ORIGIN = 0x03000C00, LENGTH = 1020 + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K + RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_sec : + { + KEEP(*(.otp_sec)) + } >OTP + + .otp_lock_sec 0x03000FC0 : + { + KEEP(*(.otp_lock_sec)) + } >OTP + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4); + .ret_ram_data : AT (__etext_ret_ram) + { + . = ALIGN(4); + __data_start_ret_ram__ = .; + *(.ret_ram_data) + *(.ret_ram_data*) + . = ALIGN(4); + __data_end_ret_ram__ = .; + } >RET_RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ret_ram_bss : + { + . = ALIGN(4); + __bss_start_ret_ram__ = .; + *(.ret_ram_bss) + *(.ret_ram_bss*) + . = ALIGN(4); + __bss_end_ret_ram__ = .; + } >RET_RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32f460/board/linker_scripts/link.sct b/bsp/hc32f460/board/linker_scripts/link.sct new file mode 100644 index 0000000000..e5fbcf64b3 --- /dev/null +++ b/bsp/hc32f460/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00080000 { ; load region size_region + ER_IROM1 0x00000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } +RW_IRAM1 0x1FFF8000 0x0002F000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32f460/drivers/SConscript b/bsp/hc32f460/drivers/SConscript new file mode 100644 index 0000000000..9325fb936f --- /dev/null +++ b/bsp/hc32f460/drivers/SConscript @@ -0,0 +1,21 @@ + +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(''' +drv_irq.c +''') + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f460/drivers/drv_gpio.c b/bsp/hc32f460/drivers/drv_gpio.c new file mode 100644 index 0000000000..cb647e3de8 --- /dev/null +++ b/bsp/hc32f460/drivers/drv_gpio.c @@ -0,0 +1,488 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ + +#include +#include "rthw.h" + +#ifdef RT_USING_PIN +#include "drv_gpio.h" +#include "drv_irq.h" + +#define GPIO_PCR_INTE (0x1000U) +#define PIN_EXINT_OFF (0U) +#define PIN_EXINT_ON (GPIO_PCR_INTE) + +#define GPIO_PIN_INDEX(pin) ((en_pin_t)((pin) & 0x0F)) +#define GPIO_PORT(pin) ((en_port_t)(((pin) >> 4) & 0x0F)) +#define GPIO_PIN(pin) ((en_pin_t)(0x01U << GPIO_PIN_INDEX(pin))) + +#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F))) +#define PIN_MAX_NUM ((PortH * 16) + (__CLZ(__RBIT(Pin13))) + 1) + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static void exint0_irq_handler(void); +static void exint1_irq_handler(void); +static void exint2_irq_handler(void); +static void exint3_irq_handler(void); +static void exint4_irq_handler(void); +static void exint5_irq_handler(void); +static void exint6_irq_handler(void); +static void exint7_irq_handler(void); +static void exint8_irq_handler(void); +static void exint9_irq_handler(void); +static void exint10_irq_handler(void); +static void exint11_irq_handler(void); +static void exint12_irq_handler(void); +static void exint13_irq_handler(void); +static void exint14_irq_handler(void); +static void exint15_irq_handler(void); + +struct hc32_pin_irq_map +{ + rt_uint16_t pinbit; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; +}; + +#ifndef HC32_PIN_CONFIG +#define HC32_PIN_CONFIG(pin, irq, src, irq_info) \ + { \ + .pinbit = pin, \ + .irq_callback = irq, \ + .irq_config = irq_info, \ + .irq_config.int_src = src, \ + } +#endif /* HC32_PIN_CONFIG */ + +static struct hc32_pin_irq_map pin_irq_map[] = +{ + HC32_PIN_CONFIG(Pin00, exint0_irq_handler, INT_PORT_EIRQ0, EXINT0_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin01, exint1_irq_handler, INT_PORT_EIRQ1, EXINT1_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin02, exint2_irq_handler, INT_PORT_EIRQ2, EXINT2_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin03, exint3_irq_handler, INT_PORT_EIRQ3, EXINT3_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin04, exint4_irq_handler, INT_PORT_EIRQ4, EXINT4_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin05, exint5_irq_handler, INT_PORT_EIRQ5, EXINT5_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin06, exint6_irq_handler, INT_PORT_EIRQ6, EXINT6_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin07, exint7_irq_handler, INT_PORT_EIRQ7, EXINT7_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin08, exint8_irq_handler, INT_PORT_EIRQ8, EXINT8_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin09, exint9_irq_handler, INT_PORT_EIRQ9, EXINT9_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin10, exint10_irq_handler, INT_PORT_EIRQ10, EXINT10_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin11, exint11_irq_handler, INT_PORT_EIRQ11, EXINT11_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin12, exint12_irq_handler, INT_PORT_EIRQ12, EXINT12_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin13, exint13_irq_handler, INT_PORT_EIRQ13, EXINT13_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin14, exint14_irq_handler, INT_PORT_EIRQ14, EXINT14_IRQ_CONFIG), + HC32_PIN_CONFIG(Pin15, exint15_irq_handler, INT_PORT_EIRQ15, EXINT15_IRQ_CONFIG), +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static void pin_irq_handler(rt_uint16_t pinbit) +{ + rt_int32_t irqindex = -1; + + if (Set == EXINT_GetExIntSrc(pinbit)) + { + EXINT_ClrExIntSrc(pinbit); + irqindex = __CLZ(__RBIT(pinbit)); + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } + } +} + +static void exint0_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[0].pinbit); + rt_interrupt_leave(); +} + +static void exint1_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[1].pinbit); + rt_interrupt_leave(); +} + +static void exint2_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[2].pinbit); + rt_interrupt_leave(); +} + +static void exint3_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[3].pinbit); + rt_interrupt_leave(); +} + +static void exint4_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[4].pinbit); + rt_interrupt_leave(); +} + +static void exint5_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[5].pinbit); + rt_interrupt_leave(); +} + +static void exint6_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[6].pinbit); + rt_interrupt_leave(); +} + +static void exint7_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[7].pinbit); + rt_interrupt_leave(); +} + +static void exint8_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[8].pinbit); + rt_interrupt_leave(); +} + +static void exint9_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[9].pinbit); + rt_interrupt_leave(); +} + +static void exint10_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[10].pinbit); + rt_interrupt_leave(); +} + +static void exint11_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[11].pinbit); + rt_interrupt_leave(); +} + +static void exint12_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[12].pinbit); + rt_interrupt_leave(); +} + +static void exint13_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[13].pinbit); + rt_interrupt_leave(); +} + +static void exint14_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[14].pinbit); + rt_interrupt_leave(); +} + +static void exint15_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[15].pinbit); + rt_interrupt_leave(); +} + +static void hc32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + en_port_t gpio_port; + en_pin_t gpio_pin; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (PIN_LOW == value) + { + PORT_ResetBits(gpio_port, gpio_pin); + } + else + { + PORT_SetBits(gpio_port, gpio_pin); + } + } +} + +static int hc32_pin_read(rt_device_t dev, rt_base_t pin) +{ + en_port_t gpio_port; + en_pin_t gpio_pin; + int value = PIN_LOW; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (Reset == PORT_GetBit(gpio_port, gpio_pin)) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + } + + return value; +} + +static void hc32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + en_port_t gpio_port; + en_pin_t gpio_pin; + stc_port_init_t stcGpioInit; + + if (pin >= PIN_MAX_NUM) + { + return; + } + + MEM_ZERO_STRUCT(stcGpioInit); + switch (mode) + { + case PIN_MODE_OUTPUT: + stcGpioInit.enPinMode = Pin_Mode_Out; + stcGpioInit.enPinOType = Pin_OType_Cmos; + break; + case PIN_MODE_INPUT: + stcGpioInit.enPinMode = Pin_Mode_In; + break; + case PIN_MODE_INPUT_PULLUP: + stcGpioInit.enPinMode = Pin_Mode_In; + stcGpioInit.enPullUp = Enable; + break; + case PIN_MODE_INPUT_PULLDOWN: + stcGpioInit.enPinMode = Pin_Mode_In; + stcGpioInit.enPullUp = Disable; + break; + case PIN_MODE_OUTPUT_OD: + stcGpioInit.enPinMode = Pin_Mode_Out; + stcGpioInit.enPinOType = Pin_OType_Od; + break; + default: + break; + } + + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + PORT_Init(gpio_port, gpio_pin, &stcGpioInit); +} + +static void gpio_irq_config(uint8_t u8Port, uint16_t u16Pin, uint16_t u16ExInt) +{ + __IO uint16_t *PCRx; + uint16_t pin_num; + pin_num = __CLZ(__RBIT(u16Pin)); + PCRx = (__IO uint16_t *)((uint32_t)(&M4_PORT->PCRA0) + ((uint32_t)u8Port * 0x40UL) + (pin_num * 4UL)); + + PORT_Unlock(); + MODIFY_REG16(*PCRx, GPIO_PCR_INTE, u16ExInt); + PORT_Lock(); +} +static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) + +{ + struct hc32_pin_irq_map *irq_map; + rt_base_t level; + rt_int32_t irqindex = -1; + en_pin_t gpio_pin; + stc_exint_config_t stcExintInit; + + if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled))) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + irq_map = &pin_irq_map[irqindex]; + gpio_pin = GPIO_PIN(pin); + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + /* Exint config */ + MEM_ZERO_STRUCT(stcExintInit); + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + stcExintInit.enExtiLvl = ExIntRisingEdge; + break; + case PIN_IRQ_MODE_FALLING: + stcExintInit.enExtiLvl = ExIntFallingEdge; + break; + case PIN_IRQ_MODE_RISING_FALLING: + stcExintInit.enExtiLvl = ExIntBothEdge; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + stcExintInit.enExtiLvl = ExIntLowLevel; + break; + } + stcExintInit.enExitCh = (en_exti_ch_t)irqindex;//gpio_pin; + stcExintInit.enFilterEn = Enable; + stcExintInit.enFltClk = Pclk3Div8; + EXINT_Init(&stcExintInit); + /* IRQ sign-in */ + hc32_install_irq_handler(&irq_map->irq_config, irq_map->irq_callback, RT_FALSE); + NVIC_EnableIRQ(irq_map->irq_config.irq); + gpio_irq_config(GPIO_PORT(pin), gpio_pin, PIN_EXINT_ON); + + rt_hw_interrupt_enable(level); + } + else + { + level = rt_hw_interrupt_disable(); + gpio_irq_config(GPIO_PORT(pin), gpio_pin, PIN_EXINT_OFF); + NVIC_DisableIRQ(irq_map->irq_config.irq); + + rt_hw_interrupt_enable(level); + } + + return RT_EOK; +} + +static const struct rt_pin_ops pin_ops = +{ + hc32_pin_mode, + hc32_pin_write, + hc32_pin_read, + hc32_pin_attach_irq, + hc32_pin_detach_irq, + hc32_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ + + diff --git a/bsp/hc32f460/drivers/drv_gpio.h b/bsp/hc32f460/drivers/drv_gpio.h new file mode 100644 index 0000000000..9aa988fc4d --- /dev/null +++ b/bsp/hc32f460/drivers/drv_gpio.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ +#include +#include "board_config.h" + +#ifdef RT_USING_PIN + +#define __HC_PORT(port) Port##port +#define GET_PIN(PORT, PIN) (((rt_uint16_t)__HC_PORT(PORT) * 16) + PIN) + +#ifndef EXINT0_IRQ_CONFIG +#define EXINT0_IRQ_CONFIG \ + { \ + .irq = EXINT0_INT_IRQn, \ + .irq_prio = EXINT0_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT1_IRQ_CONFIG +#define EXINT1_IRQ_CONFIG \ + { \ + .irq = EXINT1_INT_IRQn, \ + .irq_prio = EXINT1_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT2_IRQ_CONFIG +#define EXINT2_IRQ_CONFIG \ + { \ + .irq = EXINT2_INT_IRQn, \ + .irq_prio = EXINT2_INT_PRIO, \ + } +#endif /* EXINT2_IRQ_CONFIG */ + +#ifndef EXINT3_IRQ_CONFIG +#define EXINT3_IRQ_CONFIG \ + { \ + .irq = EXINT3_INT_IRQn, \ + .irq_prio = EXINT3_INT_PRIO, \ + } +#endif /* EXINT3_IRQ_CONFIG */ + +#ifndef EXINT4_IRQ_CONFIG +#define EXINT4_IRQ_CONFIG \ + { \ + .irq = EXINT4_INT_IRQn, \ + .irq_prio = EXINT4_INT_PRIO, \ + } +#endif /* EXINT4_IRQ_CONFIG */ + +#ifndef EXINT5_IRQ_CONFIG +#define EXINT5_IRQ_CONFIG \ + { \ + .irq = EXINT5_INT_IRQn, \ + .irq_prio = EXINT5_INT_PRIO, \ + } +#endif /* EXINT5_IRQ_CONFIG */ + +#ifndef EXINT6_IRQ_CONFIG +#define EXINT6_IRQ_CONFIG \ + { \ + .irq = EXINT6_INT_IRQn, \ + .irq_prio = EXINT6_INT_PRIO, \ + } +#endif /* EXINT6_IRQ_CONFIG */ + +#ifndef EXINT7_IRQ_CONFIG +#define EXINT7_IRQ_CONFIG \ + { \ + .irq = EXINT7_INT_IRQn, \ + .irq_prio = EXINT7_INT_PRIO, \ + } +#endif /* EXINT7_IRQ_CONFIG */ + +#ifndef EXINT8_IRQ_CONFIG +#define EXINT8_IRQ_CONFIG \ + { \ + .irq = EXINT8_INT_IRQn, \ + .irq_prio = EXINT8_INT_PRIO, \ + } +#endif /* EXINT8_IRQ_CONFIG */ + +#ifndef EXINT9_IRQ_CONFIG +#define EXINT9_IRQ_CONFIG \ + { \ + .irq = EXINT9_INT_IRQn, \ + .irq_prio = EXINT9_INT_PRIO, \ + } +#endif /* EXINT9_IRQ_CONFIG */ + +#ifndef EXINT10_IRQ_CONFIG +#define EXINT10_IRQ_CONFIG \ + { \ + .irq = EXINT10_INT_IRQn, \ + .irq_prio = EXINT10_INT_PRIO, \ + } +#endif /* EXINT10_IRQ_CONFIG */ + +#ifndef EXINT11_IRQ_CONFIG +#define EXINT11_IRQ_CONFIG \ + { \ + .irq = EXINT11_INT_IRQn, \ + .irq_prio = EXINT11_INT_PRIO, \ + } +#endif /* EXINT11_IRQ_CONFIG */ + +#ifndef EXINT12_IRQ_CONFIG +#define EXINT12_IRQ_CONFIG \ + { \ + .irq = EXINT12_INT_IRQn, \ + .irq_prio = EXINT12_INT_PRIO, \ + } +#endif /* EXINT12_IRQ_CONFIG */ + +#ifndef EXINT13_IRQ_CONFIG +#define EXINT13_IRQ_CONFIG \ + { \ + .irq = EXINT13_INT_IRQn, \ + .irq_prio = EXINT13_INT_PRIO, \ + } +#endif /* EXINT13_IRQ_CONFIG */ + +#ifndef EXINT14_IRQ_CONFIG +#define EXINT14_IRQ_CONFIG \ + { \ + .irq = EXINT14_INT_IRQn, \ + .irq_prio = EXINT14_INT_PRIO, \ + } +#endif /* EXINT14_IRQ_CONFIG */ + +#ifndef EXINT15_IRQ_CONFIG +#define EXINT15_IRQ_CONFIG \ + { \ + .irq = EXINT15_INT_IRQn, \ + .irq_prio = EXINT15_INT_PRIO, \ + } +#endif /* EXINT15_IRQ_CONFIG */ + +#endif +#endif + diff --git a/bsp/hc32f460/drivers/drv_irq.c b/bsp/hc32f460/drivers/drv_irq.c new file mode 100644 index 0000000000..84c5242780 --- /dev/null +++ b/bsp/hc32f460/drivers/drv_irq.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#include +#include "drv_irq.h" + +rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, + void (*irq_hdr)(void), + rt_bool_t irq_enable) +{ + rt_err_t result = -RT_ERROR; + stc_irq_regi_conf_t irq_signin; + + RT_ASSERT(RT_NULL != irq_config); + RT_ASSERT(RT_NULL != irq_hdr); + + irq_signin.enIRQn = irq_config->irq; + irq_signin.enIntSrc = irq_config->int_src; + irq_signin.pfnCallback = irq_hdr; + if (Ok == enIrqRegistration(&irq_signin)) + { + NVIC_ClearPendingIRQ(irq_signin.enIRQn); + NVIC_SetPriority(irq_signin.enIRQn, irq_config->irq_prio); + + if (RT_TRUE == irq_enable) + { + NVIC_EnableIRQ(irq_signin.enIRQn); + } + else + { + NVIC_DisableIRQ(irq_signin.enIRQn); + } + + result = RT_EOK; + } + + RT_ASSERT(RT_EOK == result); + + return result; +} diff --git a/bsp/hc32f460/drivers/drv_irq.h b/bsp/hc32f460/drivers/drv_irq.h new file mode 100644 index 0000000000..54267b9d97 --- /dev/null +++ b/bsp/hc32f460/drivers/drv_irq.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ + +#ifndef __DRV_IRQ_H__ +#define __DRV_IRQ_H__ + +#include +#include "hc32_ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +struct hc32_irq_config +{ + IRQn_Type irq; + uint32_t irq_prio; + en_int_src_t int_src; +}; + +rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, + void (*irq_hdr)(void), + rt_bool_t irq_enable); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32f460/drivers/drv_usart.c b/bsp/hc32f460/drivers/drv_usart.c new file mode 100644 index 0000000000..01a856c1dc --- /dev/null +++ b/bsp/hc32f460/drivers/drv_usart.c @@ -0,0 +1,527 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#include +#include +#include "drv_usart.h" +#include "board_config.h" + + +#ifdef RT_USING_SERIAL +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) + #error "Please define at least one BSP_USING_UARTx" + /* UART instance can be selected at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable UART */ +#endif + +/* HC32 config uart class */ +struct hc32_uart_config +{ + struct hc32_irq_config rxerr_irq_config; + struct hc32_irq_config rx_irq_config; +}; +/* HC32 UART index */ +struct uart_index +{ + rt_uint32_t index; + M4_USART_TypeDef *Instance; +}; + +/* HC32 UART irq handler */ +struct uart_irq_handler +{ + void (*rxerr_irq_handler)(void); + void (*rx_irq_handler)(void); +}; + +/* HC32 uart dirver class */ +struct hc32_uart +{ + const char *name; + M4_USART_TypeDef *Instance; + struct hc32_uart_config config; + struct rt_serial_device serial; +}; +#ifndef UART_CONFIG +#define UART_CONFIG(uart_name, USART) \ + { \ + .name = uart_name, \ + .Instance = M4_##USART, \ + .config = { \ + .rxerr_irq_config = { \ + .irq = USART##_RXERR_INT_IRQn, \ + .irq_prio = USART##_RXERR_INT_PRIO, \ + .int_src = INT_##USART##_EI, \ + }, \ + .rx_irq_config = { \ + .irq = USART##_RX_INT_IRQn, \ + .irq_prio = USART##_RX_INT_PRIO, \ + .int_src = INT_##USART##_RI, \ + }, \ + }, \ + } +#endif /* UART_CONFIG */ + + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif + UART_INDEX_MAX, +}; + +static const struct uart_index uart_map[] = +{ +#ifdef BSP_USING_UART1 + {UART1_INDEX, M4_USART1}, +#endif +#ifdef BSP_USING_UART2 + {UART2_INDEX, M4_USART2}, +#endif +#ifdef BSP_USING_UART3 + {UART3_INDEX, M4_USART3}, +#endif +#ifdef BSP_USING_UART4 + {UART4_INDEX, M4_USART4}, +#endif +}; +static const struct uart_index uart_clock_map[] = +{ +#ifdef BSP_USING_UART1 + {0, M4_USART1}, +#endif +#ifdef BSP_USING_UART2 + {1, M4_USART2}, +#endif +#ifdef BSP_USING_UART3 + {2, M4_USART3}, +#endif +#ifdef BSP_USING_UART4 + {3, M4_USART4}, +#endif +}; + +static struct hc32_uart uart_obj[] = +{ +#ifdef BSP_USING_UART1 + UART_CONFIG("uart1", USART1), +#endif +#ifdef BSP_USING_UART2 + UART_CONFIG("uart2", USART2), +#endif +#ifdef BSP_USING_UART3 + UART_CONFIG("uart3", USART3), +#endif +#ifdef BSP_USING_UART4 + UART_CONFIG("uart4", USART4), +#endif +}; + +static const struct uart_irq_handler uart_irq_handlers[sizeof(uart_obj) / sizeof(uart_obj[0])]; + +static uint32_t hc32_get_uart_index(M4_USART_TypeDef *Instance) +{ + uint32_t index = UART_INDEX_MAX; + + for (uint8_t i = 0U; i < ARRAY_SZ(uart_map); i++) + { + if (uart_map[i].Instance == Instance) + { + index = uart_map[i].index; + RT_ASSERT(index < UART_INDEX_MAX) + break; + } + } + + return index; +} +static uint32_t hc32_get_uart_clock_index(M4_USART_TypeDef *Instance) +{ + uint32_t index = 4; + + for (uint8_t i = 0U; i < ARRAY_SZ(uart_clock_map); i++) + { + if (uart_clock_map[i].Instance == Instance) + { + index = uart_clock_map[i].index; + RT_ASSERT(index < 4) + break; + } + } + + return index; +} +static uint32_t hc32_get_usart_fcg(M4_USART_TypeDef *Instance) +{ + return (PWC_FCG1_PERIPH_USART1 << hc32_get_uart_clock_index(Instance)); +} + +static rt_err_t hc32_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct hc32_uart *uart; + stc_usart_uart_init_t uart_init; + + RT_ASSERT(RT_NULL != cfg); + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + /* Configure USART initialization structure */ + MEM_ZERO_STRUCT(uart_init); + uart_init.enSampleMode = UsartSampleBit8; + uart_init.enSampleMode = UsartSampleBit8; + uart_init.enDetectMode = UsartStartBitFallEdge; + uart_init.enHwFlow = UsartRtsEnable; + uart_init.enClkMode = UsartIntClkCkNoOutput; + uart_init.enClkDiv = UsartClkDiv_1; + if (BIT_ORDER_LSB == cfg->bit_order) + { + uart_init.enDirection = UsartDataLsbFirst; + } + else + { + uart_init.enDirection = UsartDataMsbFirst; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart_init.enStopBit = UsartOneStopBit; + break; + case STOP_BITS_2: + uart_init.enStopBit = UsartTwoStopBit; + break; + default: + uart_init.enStopBit = UsartOneStopBit; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + uart_init.enParity = UsartParityNone; + break; + case PARITY_EVEN: + uart_init.enParity = UsartParityEven; + break; + case PARITY_ODD: + uart_init.enParity = UsartParityOdd; + break; + default: + uart_init.enParity = UsartParityNone; + break; + } + + switch (cfg->data_bits) + { + case DATA_BITS_8: + uart_init.enDataLength = UsartDataBits8; + break; + default: + return -RT_ERROR; + } + + /* Enable USART clock */ + PWC_Fcg1PeriphClockCmd(hc32_get_usart_fcg(uart->Instance), Enable); + + rt_err_t rt_hw_board_uart_init(M4_USART_TypeDef * USARTx); + if (RT_EOK != rt_hw_board_uart_init(uart->Instance)) + { + return -RT_ERROR; + } + + USART_DeInit(uart->Instance); + if (Error == USART_UART_Init(uart->Instance, &uart_init)) + { + return -RT_ERROR; + } + USART_SetBaudrate(uart->Instance, cfg->baud_rate); + if (RT_EOK != USART_SetBaudrate(uart->Instance, cfg->baud_rate)) + { + return -RT_ERROR; + } + /* Register RX error interrupt */ + hc32_install_irq_handler(&uart->config.rxerr_irq_config, + uart_irq_handlers[hc32_get_uart_index(uart->Instance)].rxerr_irq_handler, + RT_TRUE); + + USART_FuncCmd(uart->Instance, UsartRxInt, Enable); + + if ((serial->parent.flag & RT_DEVICE_FLAG_RDWR) || \ + (serial->parent.flag & RT_DEVICE_FLAG_RDONLY)) + { + USART_FuncCmd(uart->Instance, UsartRx, Enable); + } + + if ((serial->parent.flag & RT_DEVICE_FLAG_RDWR) || \ + (serial->parent.flag & RT_DEVICE_FLAG_WRONLY)) + { + USART_FuncCmd(uart->Instance, UsartTx, Enable); + } + + return RT_EOK; +} + + +static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hc32_uart *uart; + uint32_t uart_index; + RT_ASSERT(RT_NULL != serial); + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + switch (cmd) + { + /* Disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + /* Disable RX irq */ + NVIC_DisableIRQ(uart->config.rx_irq_config.irq); + enIrqResign(uart->config.rx_irq_config.irq); + break; + + /* Enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + uart_index = hc32_get_uart_index(uart->Instance); + /* Install RX irq handler */ + hc32_install_irq_handler(&uart->config.rx_irq_config, + uart_irq_handlers[uart_index].rx_irq_handler, + RT_TRUE); + break; + } + return RT_EOK; +} + +static int hc32_putc(struct rt_serial_device *serial, char c) +{ + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + USART_SendData(uart->Instance, c); + /* Polling mode. */ + while (USART_GetStatus(uart->Instance, UsartTxEmpty) != Set); + return 1; +} + +static int hc32_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + if (Set == USART_GetStatus(uart->Instance, UsartRxNoEmpty)) + { + ch = (rt_uint8_t)USART_RecData(uart->Instance); + } + + return ch; +} + +static void hc32_uart_rx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); +} + +static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + RT_ASSERT(RT_NULL != uart->Instance); + + if (Set == USART_GetStatus(uart->Instance, UsartParityErr) || \ + Set == USART_GetStatus(uart->Instance, UsartFrameErr)) + { + USART_RecData(uart->Instance); + } + USART_ClearStatus(uart->Instance, UsartParityErr); + USART_ClearStatus(uart->Instance, UsartFrameErr); + USART_ClearStatus(uart->Instance, UsartOverrunErr); +} +#if defined(BSP_USING_UART1) +static void hc32_uart1_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +static void hc32_uart2_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +static void hc32_uart2_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +static void hc32_uart3_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart3_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +static void hc32_uart4_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +static void hc32_uart4_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +static const struct uart_irq_handler uart_irq_handlers[] = +{ +#ifdef BSP_USING_UART1 + {hc32_uart1_rxerr_irq_handler, hc32_uart1_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART2 + {hc32_uart2_rxerr_irq_handler, hc32_uart2_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART3 + {hc32_uart3_rxerr_irq_handler, hc32_uart3_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART4 + {hc32_uart4_rxerr_irq_handler, hc32_uart4_rx_irq_handler}, +#endif +}; +static const struct rt_uart_ops hc32_uart_ops = +{ + .configure = hc32_configure, + .control = hc32_control, + .putc = hc32_putc, + .getc = hc32_getc, +}; + +int hc32_hw_uart_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].serial.ops = &hc32_uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].name, + (RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX), + &uart_obj[i]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_BOARD_EXPORT(hc32_hw_uart_init); + +#endif + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32f460/drivers/drv_usart.h b/bsp/hc32f460/drivers/drv_usart.h new file mode 100644 index 0000000000..2de8929a69 --- /dev/null +++ b/bsp/hc32f460/drivers/drv_usart.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021, lizhengyang + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-02 lizhengyang first version + */ +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ +#include +#include "rtdevice.h" + +#include "hc32_ddl.h" +#include "drv_irq.h" + +extern int hc32_hw_uart_init(void); +#endif diff --git a/bsp/hc32f460/project.uvoptx b/bsp/hc32f460/project.uvoptx new file mode 100644 index 0000000000..d107bd32eb --- /dev/null +++ b/bsp/hc32f460/project.uvoptx @@ -0,0 +1,1017 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\..\components\libc\compilers\armlibc\stdio.c + stdio.c + 0 + 0 + + + 9 + 59 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 9 + 60 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\unistd.c + unistd.c + 0 + 0 + + + 9 + 61 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\stdlib.c + stdlib.c + 0 + 0 + + + 9 + 62 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\time.c + time.c + 0 + 0 + + + 9 + 63 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\delay.c + delay.c + 0 + 0 + + + + diff --git a/bsp/hc32f460/project.uvprojx b/bsp/hc32f460/project.uvprojx new file mode 100644 index 0000000000..575d6ef505 --- /dev/null +++ b/bsp/hc32f460/project.uvprojx @@ -0,0 +1,768 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F460PETB + HDSC + HDSC.HC32F460.1.0.7 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) IROM(0x00000000,0x80000) IROM2(0x03000C00,0x003FC) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)) + 0 + $$Device:HC32F460PETB$Device\Include\HC32F460PETB.h + + + + + + + + + + $$Device:HC32F460PETB$SVD\HDSC_HC32F460PETB.svd + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x3000c00 + 0x3fc + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 0 + 0x200f0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + USE_DEVICE_DRIVER_LIB, __CLK_TCK=RT_TICK_PER_SECOND, HC32F460, __RTTHREAD__, __DEBUG, RT_USING_ARM_LIBC + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;board;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\finsh;Libraries\CMSIS\Include;Libraries\CMSIS\Device\HDSC\HC32F460\Include;Libraries\HC32F460_StdPeriph_Driver\inc;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + + + Drivers + + + board_config.c + 1 + board\board_config.c + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_irq.c + 1 + drivers\drv_irq.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + + + Finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + + + HC32_StdPeriph + + + system_hc32f460.c + 1 + Libraries\CMSIS\Device\HDSC\HC32F460\Source\system_hc32f460.c + + + hc32f460_usart.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_usart.c + + + hc32f460_gpio.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_gpio.c + + + hc32f460_clk.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_clk.c + + + hc32f460_efm.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_efm.c + + + hc32f460_sram.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_sram.c + + + hc32f460_utility.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_utility.c + + + hc32f460_exint_nmi_swi.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_exint_nmi_swi.c + + + hc32f460_icg.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_icg.c + + + startup_hc32f460.s + 2 + Libraries\CMSIS\Device\HDSC\HC32F460\Source\ARM\startup_hc32f460.s + + + hc32f460_interrupts.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_interrupts.c + + + hc32f460_pwc.c + 1 + Libraries\HC32F460_StdPeriph_Driver\src\hc32f460_pwc.c + + + + + Kernel + + + irq.c + 1 + ..\..\src\irq.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + clock.c + 1 + ..\..\src\clock.c + + + components.c + 1 + ..\..\src\components.c + + + idle.c + 1 + ..\..\src\idle.c + + + thread.c + 1 + ..\..\src\thread.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + object.c + 1 + ..\..\src\object.c + + + device.c + 1 + ..\..\src\device.c + + + timer.c + 1 + ..\..\src\timer.c + + + mem.c + 1 + ..\..\src\mem.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + unistd.c + 1 + ..\..\components\libc\compilers\common\unistd.c + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + delay.c + 1 + ..\..\components\libc\compilers\common\delay.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/hc32f460/rtconfig.h b/bsp/hc32f460/rtconfig.h new file mode 100644 index 0000000000..cf1179edd1 --- /dev/null +++ b/bsp/hc32f460/rtconfig.h @@ -0,0 +1,188 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x40004 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define MCU_HC32F460 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART4 + +#endif diff --git a/bsp/hc32f460/rtconfig.py b/bsp/hc32f460/rtconfig.py new file mode 100644 index 0000000000..462c2009f6 --- /dev/null +++ b/bsp/hc32f460/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='iar' + +print "############rtconfig##############" + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +print "CROSS_TOOL: " + CROSS_TOOL + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'D:\03_software\Program Files\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'D:\03_software\Program Files\IAR Systems\Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +MCU_TYPE = 'HC32F460' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall -DHC32F460 -D__DEBUG -USE_DEVICE_DRIVER_LIB -D__ASSEMBLY__' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork -USE_DEVICE_DRIVER_LIB -DHC32F460 -D__DEBUG' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board/linker_scripts/link.sct"' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D __DEBUG' + ' -D USE_DEVICE_DRIVER_LIB' + ' -D HC32F460' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/hc32f460/template.uvopt b/bsp/hc32f460/template.uvopt new file mode 100644 index 0000000000..33eee51f0d --- /dev/null +++ b/bsp/hc32f460/template.uvopt @@ -0,0 +1,162 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U788529815 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0AT32F403A_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC800 -FD20000000 -FF0AT32F403A_1024 -FL0100000 -FS08000000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + + + + + diff --git a/bsp/hc32f460/template.uvoptx b/bsp/hc32f460/template.uvoptx new file mode 100644 index 0000000000..a8bf21a9ee --- /dev/null +++ b/bsp/hc32f460/template.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U4294967295 -O78 -S5 -ZTIFSpeedSel1000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F460_512K.FLM -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0AT32F403A_1024 -FL0100000 -FS08000000 -FP0($$Device:AT32F403AVGT7$Flash\AT32F403A_1024.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -U066EFF495056867767222250 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32f460/template.uvprojx b/bsp/hc32f460/template.uvprojx new file mode 100644 index 0000000000..d289d4ffbb --- /dev/null +++ b/bsp/hc32f460/template.uvprojx @@ -0,0 +1,406 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F460PETB + HDSC + HDSC.HC32F460.1.0.7 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) IROM(0x00000000,0x80000) IROM2(0x03000C00,0x003FC) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FF1HC32F460_otp -FS13000C00 -FL13FC -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)) + 0 + $$Device:HC32F460PETB$Device\Include\HC32F460PETB.h + + + + + + + + + + $$Device:HC32F460PETB$SVD\HDSC_HC32F460PETB.svd + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x3000c00 + 0x3fc + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x2f000 + + + 0 + 0x200f0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + __DEBUG,HC32F460,USE_DEVICE_DRIVER_LIB + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + --keep=*Handler + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/hc32l196/.config b/bsp/hc32l196/.config new file mode 100644 index 0000000000..6df319dbd1 --- /dev/null +++ b/bsp/hc32l196/.config @@ -0,0 +1,582 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Hardware Drivers Config +# +CONFIG_MCU_HC32L196=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_USING_UART1=y + +# +# Board extended module Drivers +# diff --git a/bsp/hc32l196/.gitignore b/bsp/hc32l196/.gitignore new file mode 100644 index 0000000000..af2c85848e --- /dev/null +++ b/bsp/hc32l196/.gitignore @@ -0,0 +1,43 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h +.rtt-studio/ diff --git a/bsp/hc32l196/.ignore_format.yml b/bsp/hc32l196/.ignore_format.yml new file mode 100644 index 0000000000..e3b426e2c5 --- /dev/null +++ b/bsp/hc32l196/.ignore_format.yml @@ -0,0 +1,7 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + + +dir_path: +- Libraries diff --git a/bsp/hc32l196/Kconfig b/bsp/hc32l196/Kconfig new file mode 100644 index 0000000000..f4ed99b3fa --- /dev/null +++ b/bsp/hc32l196/Kconfig @@ -0,0 +1,23 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + + + diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/base_types.h b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/base_types.h new file mode 100644 index 0000000000..ab32088421 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/base_types.h @@ -0,0 +1,147 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file base_types.h + ** + ** base type common define. + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0u) +#endif + +/** Returns the minimum value out of two values */ +#define MINIMUM( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAXIMUM( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define ARRAY_SZ( X ) (sizeof(X) / sizeof((X)[0])) + +#ifdef __DEBUG_ASSERT + #define ASSERT(x) do{ assert((x)> 0u) ; }while(0); +#else + #define ASSERT(x) {} +#endif +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCII character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t u8Param); + +/** generic error codes */ +typedef enum en_result +{ + Ok = 0u, ///< No error + Error = 1u, ///< Non-specific error code + ErrorAddressAlignment = 2u, ///< Address alignment does not match + ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4u, ///< Provided parameter is not valid + ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6u, ///< Operation not allowed in current mode + ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10u, ///< A requested final state is not reached + OperationInProgress = 11u ///< Indicator for operation in progress +} en_result_t; + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/board_stkhc32l19x.h b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/board_stkhc32l19x.h new file mode 100644 index 0000000000..fd41609d14 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/board_stkhc32l19x.h @@ -0,0 +1,130 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file stkhc32l19x.h + ** + ** stk board common define. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ +#ifndef __BOARD_STKHC32L19X_H__ +#define __BOARD_STKHC32L19X_H__ + +///< STK GPIO DEFINE +///< USER KEY +#define STK_USER_PORT GpioPortA +#define STK_USER_PIN GpioPin7 + +///< LED +#define STK_LED_PORT GpioPortC +#define STK_LED_PIN GpioPin13 + +///< XTH +#define SYSTEM_XTH (32*1000*1000u) ///< 32MHz + +#define STK_XTHI_PORT GpioPortF +#define STK_XTHI_PIN GpioPin0 +#define STK_XTHO_PORT GpioPortF +#define STK_XTHO_PIN GpioPin1 + +///< XTL +#define SYSTEM_XTL (32768u) ///< 32768Hz +#define STK_XTLI_PORT GpioPortC +#define STK_XTLI_PIN GpioPin14 +#define STK_XTLO_PORT GpioPortC +#define STK_XTLO_PIN GpioPin15 + +///< LCD +#define STK_LCD_COM0_PORT GpioPortA +#define STK_LCD_COM0_PIN GpioPin9 +#define STK_LCD_COM1_PORT GpioPortA +#define STK_LCD_COM1_PIN GpioPin10 +#define STK_LCD_COM2_PORT GpioPortA +#define STK_LCD_COM2_PIN GpioPin11 +#define STK_LCD_COM3_PORT GpioPortA +#define STK_LCD_COM3_PIN GpioPin12 +#define STK_LCD_SEG0_PORT GpioPortA +#define STK_LCD_SEG0_PIN GpioPin8 +#define STK_LCD_SEG1_PORT GpioPortC +#define STK_LCD_SEG1_PIN GpioPin9 +#define STK_LCD_SEG2_PORT GpioPortC +#define STK_LCD_SEG2_PIN GpioPin8 +#define STK_LCD_SEG3_PORT GpioPortC +#define STK_LCD_SEG3_PIN GpioPin7 +#define STK_LCD_SEG4_PORT GpioPortC +#define STK_LCD_SEG4_PIN GpioPin6 +#define STK_LCD_SEG5_PORT GpioPortB +#define STK_LCD_SEG5_PIN GpioPin15 +#define STK_LCD_SEG6_PORT GpioPortB +#define STK_LCD_SEG6_PIN GpioPin14 +#define STK_LCD_SEG7_PORT GpioPortB +#define STK_LCD_SEG7_PIN GpioPin13 + +///< I2C EEPROM +#define EVB_I2C0_EEPROM_SCL_PORT GpioPortB +#define EVB_I2C0_EEPROM_SCL_PIN GpioPin6 +#define EVB_I2C0_EEPROM_SDA_PORT GpioPortB +#define EVB_I2C0_EEPROM_SDA_PIN GpioPin7 + +///< SPI0 +#define STK_SPI0_CS_PORT GpioPortE +#define STK_SPI0_CS_PIN GpioPin12 +#define STK_SPI0_SCK_PORT GpioPortE +#define STK_SPI0_SCK_PIN GpioPin13 +#define STK_SPI0_MISO_PORT GpioPortE +#define STK_SPI0_MISO_PIN GpioPin14 +#define STK_SPI0_MOSI_PORT GpioPortE +#define STK_SPI0_MOSI_PIN GpioPin15 + +///< SPI1 +#define STK_SPI1_CS_PORT GpioPortB +#define STK_SPI1_CS_PIN GpioPin12 +#define STK_SPI1_SCK_PORT GpioPortB +#define STK_SPI1_SCK_PIN GpioPin13 +#define STK_SPI1_MISO_PORT GpioPortB +#define STK_SPI1_MISO_PIN GpioPin14 +#define STK_SPI1_MOSI_PORT GpioPortB +#define STK_SPI1_MOSI_PIN GpioPin15 + +#endif diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/ddl_device.h b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/ddl_device.h new file mode 100644 index 0000000000..c42192bfa0 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/ddl_device.h @@ -0,0 +1,76 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file ddl_device.h + ** + ** Device define + ** @link SampleGroup Some description @endlink + ** + ** - 2018-04-15 + ** + *****************************************************************************/ + +#ifndef __DDL_DEVICE_H__ +#define __DDL_DEVICE_H__ + +/** + ******************************************************************************* + ** \brief Global device series definition + ** + ** \note + ******************************************************************************/ +#define DDL_MCU_SERIES DDL_DEVICE_SERIES_HC32L19X + + +/** + ******************************************************************************* + ** \brief Global package definition + ** + ** \note This definition is used for device package settings + ******************************************************************************/ +#define DDL_MCU_PACKAGE DDL_DEVICE_PACKAGE_HC_K + +#endif /* __DDL_DEVICE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/hc32l19x.h b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/hc32l19x.h new file mode 100644 index 0000000000..7b06a96493 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/hc32l19x.h @@ -0,0 +1,10854 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \\file HC32L19X.h +** +** Auto generate. +** Headerfile for HC32L19X series MCU +** +** History: +** +** - 2019-07-01 0.1 Lux First version. +** +******************************************************************************/ + +#ifndef __HC32L19X_H__ +#define __HC32L19X_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** +* Configuration of the Cortex-M0P Processor and Core Peripherals +******************************************************************************/ +#define __MPU_PRESENT 0 /* No MPU */ +#define __NVIC_PRIO_BITS 2 /* M0P uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +/****************************************************************************** +* Interrupt Number Definition +******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + PORTA_IRQn = 0 , + PORTB_IRQn = 1 , + PORTC_E_IRQn = 2 , + PORTD_F_IRQn = 3 , + DMAC_IRQn = 4 , + TIM3_IRQn = 5 , + UART0_2_IRQn = 6 , + UART1_3_IRQn = 7 , + LPUART0_IRQn = 8 , + LPUART1_IRQn = 9 , + SPI0_IRQn = 10, + SPI1_IRQn = 11, + I2C0_IRQn = 12, + I2C1_IRQn = 13, + TIM0_IRQn = 14, + TIM1_IRQn = 15, + TIM2_IRQn = 16, + LPTIM_0_1_IRQn = 17, + ADTIM4_IRQn = 18, + ADTIM5_IRQn = 19, + ADTIM6_IRQn = 20, + PCA_IRQn = 21, + WDT_IRQn = 22, + RTC_IRQn = 23, + ADC_DAC_IRQn = 24, + PCNT_IRQn = 25, + VC0_IRQn = 26, + VC1_2_IRQn = 27, + LVD_IRQn = 28, + LCD_IRQn = 29, + FLASH_RAM_IRQn = 30, + CLKTRIM_IRQn = 31, + + +} IRQn_Type; + + +#include +#include + +#define SUCCESS (0) +#define ERROR (-1) + +#ifndef NULL +#define NULL (0) +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +typedef struct +{ + __IO uint32_t EN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CLKDIV : 2; + __IO uint32_t SGLMUX : 5; + __IO uint32_t REF : 2; + __IO uint32_t BUF : 1; + __IO uint32_t SAM : 2; + __IO uint32_t INREFEN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adc_cr0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t ALIGN : 1; + __IO uint32_t THCH : 5; + __IO uint32_t DMASQR : 1; + __IO uint32_t DMAJQR : 1; + __IO uint32_t MODE : 1; + __IO uint32_t RACCEN : 1; + __IO uint32_t LTCMP : 1; + __IO uint32_t HTCMP : 1; + __IO uint32_t REGCMP : 1; + __IO uint32_t RACCCLR : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adc_cr1_field_t; + +typedef struct +{ + __IO uint32_t CH0MUX : 5; + __IO uint32_t CH1MUX : 5; + __IO uint32_t CH2MUX : 5; + __IO uint32_t CH3MUX : 5; + __IO uint32_t CH4MUX : 5; + __IO uint32_t CH5MUX : 5; + uint32_t RESERVED30 : 1; + __IO uint32_t RSV : 1; +} stc_adc_sqr0_field_t; + +typedef struct +{ + __IO uint32_t CH6MUX : 5; + __IO uint32_t CH7MUX : 5; + __IO uint32_t CH8MUX : 5; + __IO uint32_t CH9MUX : 5; + __IO uint32_t CH10MUX : 5; + __IO uint32_t CH11MUX : 5; + uint32_t RESERVED30 : 1; + __IO uint32_t RSV : 1; +} stc_adc_sqr1_field_t; + +typedef struct +{ + __IO uint32_t CH12MUX : 5; + __IO uint32_t CH13MUX : 5; + __IO uint32_t CH14MUX : 5; + __IO uint32_t CH15MUX : 5; + __IO uint32_t CNT : 4; + uint32_t RESERVED24 : 7; + __IO uint32_t RSV : 1; +} stc_adc_sqr2_field_t; + +typedef struct +{ + __IO uint32_t CH0MUX : 5; + __IO uint32_t CH1MUX : 5; + __IO uint32_t CH2MUX : 5; + __IO uint32_t CH3MUX : 5; + __IO uint32_t CNT : 2; + uint32_t RESERVED22 : 9; + __IO uint32_t RSV : 1; +} stc_adc_jqr_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult0_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult1_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult2_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult3_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult4_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult5_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult6_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult7_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult8_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult9_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult10_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult11_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult12_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqr_result13_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult14_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_sqrresult15_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_jqrresult0_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_jqrresult1_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_jqrresult2_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_jqrresult3_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_result_field_t; + +typedef struct +{ + __IO uint32_t RESULTACC :20; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adc_resultacc_field_t; + +typedef struct +{ + __IO uint32_t HT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_ht_field_t; + +typedef struct +{ + __IO uint32_t LT :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_adc_lt_field_t; + +typedef struct +{ + __IO uint32_t SGLIF : 1; + __IO uint32_t LTIF : 1; + __IO uint32_t HTIF : 1; + __IO uint32_t REGIF : 1; + __IO uint32_t SQRIF : 1; + __IO uint32_t JQRIF : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_adc_ifr_field_t; + +typedef struct +{ + __IO uint32_t SGLIC : 1; + __IO uint32_t LTIC : 1; + __IO uint32_t HTIC : 1; + __IO uint32_t REGIC : 1; + __IO uint32_t SQRIC : 1; + __IO uint32_t JQRIC : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_adc_icr_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t VC0 : 1; + __IO uint32_t VC1 : 1; + __IO uint32_t RTC : 1; + __IO uint32_t PCA : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t DMA : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PA15 : 1; + __IO uint32_t PB15 : 1; + __IO uint32_t PC15 : 1; +} stc_adc_exttrigger0_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t VC0 : 1; + __IO uint32_t VC1 : 1; + __IO uint32_t RTC : 1; + __IO uint32_t PCA : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t DMA : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PA15 : 1; + __IO uint32_t PB15 : 1; + __IO uint32_t PC15 : 1; +} stc_adc_exttrigger1_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_adc_sglstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_adc_sqrstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_adc_jqrstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_adc_allstart_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_perbr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_scmbr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_dtdar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSK : 2; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adtim_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDE : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t INTENSAML : 1; + __IO uint32_t INTENSAMH : 1; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adtim_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPCA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + __IO uint32_t DISSELA : 2; + __IO uint32_t DISVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPCB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + __IO uint32_t DISSELB : 2; + __IO uint32_t DISVALB : 2; + uint32_t RESERVED29 : 2; + __IO uint32_t RSV : 1; +} stc_adtim_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t BENB : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t BENP : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_adtim_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SEPA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_adtim_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 1; + __IO uint32_t NOFIENTC : 1; + __IO uint32_t NOFICKTC : 2; + uint32_t RESERVED27 : 1; + __IO uint32_t NOFIENTD : 1; + __IO uint32_t NOFICKTD : 2; + __IO uint32_t RSV : 1; +} stc_adtim_fconr_field_t; + +typedef struct +{ + __IO uint32_t GEPERIA : 1; + __IO uint32_t GEPERIB : 1; + __IO uint32_t GEPERIC : 1; + __IO uint32_t GEPERID : 1; + uint32_t RESERVED4 :12; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; + uint32_t RESERVED21 :10; + __IO uint32_t RSV : 1; +} stc_adtim_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_adtim_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + __IO uint32_t HSTA3 : 1; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + __IO uint32_t HSTA12 : 1; + __IO uint32_t HSTA13 : 1; + __IO uint32_t HSTA14 : 1; + __IO uint32_t HSTA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_adtim_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + __IO uint32_t HSTP3 : 1; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + __IO uint32_t HSTP12 : 1; + __IO uint32_t HSTP13 : 1; + __IO uint32_t HSTP14 : 1; + __IO uint32_t HSTP15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STOPS : 1; +} stc_adtim_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCEL0 : 1; + __IO uint32_t HCEL1 : 1; + __IO uint32_t HCEL2 : 1; + __IO uint32_t HCEL3 : 1; + __IO uint32_t HCEL4 : 1; + __IO uint32_t HCEL5 : 1; + __IO uint32_t HCEL6 : 1; + __IO uint32_t HCEL7 : 1; + __IO uint32_t HCEL8 : 1; + __IO uint32_t HCEL9 : 1; + __IO uint32_t HCEL10 : 1; + __IO uint32_t HCEL11 : 1; + __IO uint32_t HCEL12 : 1; + __IO uint32_t HCEL13 : 1; + __IO uint32_t HCEL14 : 1; + __IO uint32_t HCEL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t CLEARS : 1; +} stc_adtim_hcelr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + __IO uint32_t HCPA2 : 1; + __IO uint32_t HCPA3 : 1; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + __IO uint32_t HCPA12 : 1; + __IO uint32_t HCPA13 : 1; + __IO uint32_t HCPA14 : 1; + __IO uint32_t HCPA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + __IO uint32_t HCPB2 : 1; + __IO uint32_t HCPB3 : 1; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + __IO uint32_t HCPB12 : 1; + __IO uint32_t HCPB13 : 1; + __IO uint32_t HCPB14 : 1; + __IO uint32_t HCPB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + __IO uint32_t HCUP13 : 1; + __IO uint32_t HCUP14 : 1; + __IO uint32_t HCUP15 : 1; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + __IO uint32_t HCUP18 : 1; + __IO uint32_t HCUP19 : 1; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adtim_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + __IO uint32_t HCDO13 : 1; + __IO uint32_t HCDO14 : 1; + __IO uint32_t HCDO15 : 1; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + __IO uint32_t HCDO18 : 1; + __IO uint32_t HCDO19 : 1; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_adtim_hcdor_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLF : 1; + __IO uint32_t SAMHF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_ifr_field_t; + +typedef struct +{ + __IO uint32_t CMAC : 1; + __IO uint32_t CMBC : 1; + __IO uint32_t CMCC : 1; + __IO uint32_t CMDC : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFC : 1; + __IO uint32_t UDFC : 1; + __IO uint32_t DTEC : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLC : 1; + __IO uint32_t SAMHC : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_iclr_field_t; + +typedef struct +{ + __IO uint32_t CMAE : 1; + __IO uint32_t CMBE : 1; + __IO uint32_t CMCE : 1; + __IO uint32_t CMDE : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFE : 1; + __IO uint32_t UDFE : 1; + __IO uint32_t DITENA : 1; + __IO uint32_t DITENB : 1; + __IO uint32_t DITENS : 1; + __IO uint32_t CMSAE : 1; + __IO uint32_t CMSBE : 1; + __IO uint32_t DMA_G_CMA : 1; + __IO uint32_t DMA_G_CMB : 1; + __IO uint32_t DMA_G_CMC : 1; + __IO uint32_t DMA_G_CMD : 1; + uint32_t RESERVED17 : 2; + __IO uint32_t DMA_G_OVF : 1; + __IO uint32_t DMA_G_UDF : 1; + __IO uint32_t DMA_S_CMA : 1; + __IO uint32_t DMA_S_CMB : 1; + uint32_t RESERVED23 : 8; + __IO uint32_t RSV : 1; +} stc_adtim_cr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + __IO uint32_t BFILTS : 2; + __IO uint32_t BFILTEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t SOFTBK : 1; + __IO uint32_t SML0 : 1; + __IO uint32_t SML1 : 1; + __IO uint32_t SML2 : 1; + __IO uint32_t SMH0 : 1; + __IO uint32_t SMH1 : 1; + __IO uint32_t SMH2 : 1; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_adtim_aossr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_adtim_aoscl_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_ptbks_field_t; + +typedef struct +{ + __IO uint32_t TRIGAS : 4; + __IO uint32_t TRIGBS : 4; + __IO uint32_t TRIGCS : 4; + __IO uint32_t TRIGDS : 4; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_ttrig_field_t; + +typedef struct +{ + __IO uint32_t IAOS0S : 4; + __IO uint32_t IAOS1S : 4; + __IO uint32_t IAOS2S : 4; + __IO uint32_t IAOS3S : 4; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_itrig_field_t; + +typedef struct +{ + __IO uint32_t POL0 : 1; + __IO uint32_t POL1 : 1; + __IO uint32_t POL2 : 1; + __IO uint32_t POL3 : 1; + __IO uint32_t POL4 : 1; + __IO uint32_t POL5 : 1; + __IO uint32_t POL6 : 1; + __IO uint32_t POL7 : 1; + __IO uint32_t POL8 : 1; + __IO uint32_t POL9 : 1; + __IO uint32_t POL10 : 1; + __IO uint32_t POL11 : 1; + __IO uint32_t POL12 : 1; + __IO uint32_t POL13 : 1; + __IO uint32_t POL14 : 1; + __IO uint32_t POL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_adtim_ptbkp_field_t; + +typedef struct +{ + __IO uint32_t SSTA0 : 1; + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_adtim_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP0 : 1; + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_adtim_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLR0 : 1; + __IO uint32_t SCLR1 : 1; + __IO uint32_t SCLR2 : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_adtim_sclrr_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t KEYSIZE : 2; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_aes_cr_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data0_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data1_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data2_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data3_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key0_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key1_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key2_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key3_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key4_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key5_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key6_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key7_field_t; + +typedef struct +{ + __IO uint32_t BGR_EN : 1; + __IO uint32_t TS_EN : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_bgr_cr_field_t; + +typedef struct +{ + __IO uint32_t TRIM_START : 1; + __IO uint32_t REFCLK_SEL : 3; + __IO uint32_t CALCLK_SEL : 2; + __IO uint32_t MON_EN : 1; + __IO uint32_t IE : 1; + __IO uint32_t CALCLK_SEL2 : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_clk_trim_cr_field_t; + +typedef struct +{ + __IO uint32_t RCNTVAL :32; +} stc_clk_trim_refcon_field_t; + +typedef struct +{ + __IO uint32_t REFCNT :32; +} stc_clk_trim_refcnt_field_t; + +typedef struct +{ + __IO uint32_t CALCNT :32; +} stc_clk_trim_calcnt_field_t; + +typedef struct +{ + __IO uint32_t STOP : 1; + __IO uint32_t CALCNT_OF : 1; + __IO uint32_t XTL_FAULT : 1; + __IO uint32_t XTH_FAULT : 1; + __IO uint32_t PLL_FAULT : 1; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_clk_trim_ifr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t XTL_FAULT_CLR : 1; + __IO uint32_t XTH_FAULT_CLR : 1; + __IO uint32_t PLL_FAULT_CLR : 1; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_clk_trim_iclr_field_t; + +typedef struct +{ + __IO uint32_t CCNTVAL :32; +} stc_clk_trim_calcon_field_t; + +typedef struct +{ + __IO uint32_t CR : 1; + __IO uint32_t FLAG : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_crc_cr_field_t; + +typedef struct +{ + __IO uint32_t RESULT :32; +} stc_crc_result_field_t; + +typedef struct +{ + __IO uint32_t DATA :32; +} stc_crc_data_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t BOFF0 : 1; + __IO uint32_t TEN0 : 1; + __IO uint32_t TSEL0 : 3; + __IO uint32_t WAVE0 : 2; + __IO uint32_t MAMP0 : 4; + __IO uint32_t DMAEN0 : 1; + __IO uint32_t DMAUDRIE0 : 1; + __IO uint32_t SREF0 : 2; +} stc_dac_cr0_field_t; + +typedef struct +{ + __IO uint32_t SWTRIG0 : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_dac_swtrigr_field_t; + +typedef struct +{ + __IO uint32_t DHR0 :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_dac_dhr12r0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 4; + __IO uint32_t DHR0 :12; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_dac_dhr12l0_field_t; + +typedef struct +{ + __IO uint32_t DHR0 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_dac_dhr8r0_field_t; + +typedef struct +{ + __IO uint32_t DOR0 :12; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_dac_dor0_field_t; + +typedef struct +{ + uint32_t RESERVED0 :13; + __IO uint32_t DMAUDR0 : 1; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_dac_sr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 4; + __IO uint32_t PTRIGSEL : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_dac_etrs_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t LPTIM0 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t PCA : 1; + __IO uint32_t WDT : 1; + __IO uint32_t RTC : 1; + uint32_t RESERVED10 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t LPTIM1 : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_debug_active_field_t; + +typedef struct +{ + uint32_t RESERVED0 :24; + __IO uint32_t HALT : 4; + __IO uint32_t PRIO : 1; + uint32_t RESERVED29 : 1; + __IO uint32_t ST : 1; + __IO uint32_t EN : 1; +} stc_dmac_conf_field_t; + +typedef struct +{ + __IO uint32_t TC :16; + __IO uint32_t BC : 4; + uint32_t RESERVED20 : 2; + __IO uint32_t TRI_SEL : 7; + __IO uint32_t ST : 1; + __IO uint32_t PAS : 1; + __IO uint32_t ENS : 1; +} stc_dmac_confa0_field_t; + +typedef struct +{ + __IO uint32_t MSK : 1; + uint32_t RESERVED1 :15; + __IO uint32_t STAT : 3; + __IO uint32_t FIS_IE : 1; + __IO uint32_t ERR_IE : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t WIDTH : 2; + __IO uint32_t MODE : 2; +} stc_dmac_confb0_field_t; + +typedef struct +{ + __IO uint32_t SRCADR :32; +} stc_dmac_srcadr0_field_t; + +typedef struct +{ + __IO uint32_t DSTADR :32; +} stc_dmac_dstadr0_field_t; + +typedef struct +{ + __IO uint32_t TC :16; + __IO uint32_t BC : 4; + uint32_t RESERVED20 : 2; + __IO uint32_t TRI_SEL : 7; + __IO uint32_t ST : 1; + __IO uint32_t PAS : 1; + __IO uint32_t ENS : 1; +} stc_dmac_confa1_field_t; + +typedef struct +{ + __IO uint32_t MSK : 1; + uint32_t RESERVED1 :15; + __IO uint32_t STAT : 3; + __IO uint32_t FIS_IE : 1; + __IO uint32_t ERR_IE : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t WIDTH : 2; + __IO uint32_t MODE : 2; +} stc_dmac_confb1_field_t; + +typedef struct +{ + __IO uint32_t SRCADR :32; +} stc_dmac_srcadr1_field_t; + +typedef struct +{ + __IO uint32_t DSTADR :32; +} stc_dmac_dstadr1_field_t; + +typedef struct +{ + __IO uint32_t TNVS : 9; + __IO uint32_t RSV :23; +} stc_flash_tnvs_field_t; + +typedef struct +{ + __IO uint32_t TPGS : 8; + __IO uint32_t RSV :24; +} stc_flash_tpgs_field_t; + +typedef struct +{ + __IO uint32_t TPROG : 9; + __IO uint32_t RSV :23; +} stc_flash_tprog_field_t; + +typedef struct +{ + __IO uint32_t TSERASE :18; + __IO uint32_t RSV :14; +} stc_flash_tserase_field_t; + +typedef struct +{ + __IO uint32_t TMERASE :21; + __IO uint32_t RSV :11; +} stc_flash_tmerase_field_t; + +typedef struct +{ + __IO uint32_t TPRCV :12; + __IO uint32_t RSV :20; +} stc_flash_tprcv_field_t; + +typedef struct +{ + __IO uint32_t TSRCV :12; + __IO uint32_t RSV :20; +} stc_flash_tsrcv_field_t; + +typedef struct +{ + __IO uint32_t TMRCV :14; + __IO uint32_t RSV :18; +} stc_flash_tmrcv_field_t; + +typedef struct +{ + __IO uint32_t OP : 2; + __IO uint32_t WAIT : 2; + __IO uint32_t BUSY : 1; + __IO uint32_t IE : 2; + uint32_t RESERVED7 : 2; + __IO uint32_t DPSTB_EN : 1; + __IO uint32_t RSV :22; +} stc_flash_cr_field_t; + +typedef struct +{ + __IO uint32_t IF0 : 1; + __IO uint32_t IF1 : 1; + __IO uint32_t RSV :30; +} stc_flash_ifr_field_t; + +typedef struct +{ + __IO uint32_t ICLR0 : 1; + __IO uint32_t ICLR1 : 1; + __IO uint32_t RSV :30; +} stc_flash_iclr_field_t; + +typedef struct +{ + __IO uint32_t BYSEQ :16; + __IO uint32_t RSV :16; +} stc_flash_bypass_field_t; + +typedef struct +{ + __IO uint32_t SLOCK :32; +} stc_flash_slock0_field_t; + +typedef struct +{ + __IO uint32_t SLOCK :32; +} stc_flash_slock1_field_t; + +typedef struct +{ + __IO uint32_t SLOCK :32; +} stc_flash_slock2_field_t; + +typedef struct +{ + __IO uint32_t SLOCK :32; +} stc_flash_slock3_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pa15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pb15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pc15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pd15_sel_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_padir_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pain_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_paout_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_paads_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pabset_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pabclr_field_t; + +typedef struct +{ + __IO uint32_t PABCLR :16; + __IO uint32_t PABSET :16; +} stc_gpio_pabsetclr_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_padr_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_papu_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_papd_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_paod_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pahie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_palie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_parie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pafie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbdir_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbin_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbout_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbads_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbbset_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbbclr_field_t; + +typedef struct +{ + __IO uint32_t PBBCLR :16; + __IO uint32_t PBBSET :16; +} stc_gpio_pbbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbdr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbpu_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbpd_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbod_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbhie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pblie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbrie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pbfie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcdir_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcin_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcout_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcads_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcbset_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcbclr_field_t; + +typedef struct +{ + __IO uint32_t PCBCLR :16; + __IO uint32_t PCBSET :16; +} stc_gpio_pcbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcdr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcpu_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcpd_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcod_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pchie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pclie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcrie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pcfie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pddir_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdin_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdout_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdads_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdbset_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdbclr_field_t; + +typedef struct +{ + __IO uint32_t PDBCLR :16; + __IO uint32_t PDBSET :16; +} stc_gpio_pdbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pddr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdpu_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdpd_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdod_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdhie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdlie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdrie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pdfie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pa_stat_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pa_iclr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pb_stat_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pb_iclr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pc_stat_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pc_iclr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pd_stat_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PD08 : 1; + __IO uint32_t PD09 : 1; + __IO uint32_t PD10 : 1; + __IO uint32_t PD11 : 1; + __IO uint32_t PD12 : 1; + __IO uint32_t PD13 : 1; + __IO uint32_t PD14 : 1; + __IO uint32_t PD15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pd_iclr_field_t; + +typedef struct +{ + __IO uint32_t IESEL : 1; +} stc_gpio_ctrl0_field_t; + +typedef struct +{ + __IO uint32_t EXT_CLK_SEL : 4; + __IO uint32_t SSN0_SEL : 4; + __IO uint32_t PCLK_SEL : 2; + __IO uint32_t HCLK_SEL : 2; + __IO uint32_t PCLK_EN : 1; + __IO uint32_t HCLK_EN : 1; + __IO uint32_t IR_POL : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_gpio_ctrl1_field_t; + +typedef struct +{ + __IO uint32_t SSN1_SEL : 4; + __IO uint32_t TCLK_SEL : 2; + __IO uint32_t TCLK_DIV : 2; + uint32_t RESERVED8 : 7; + __IO uint32_t AHB_SEL : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_ctrl2_field_t; + +typedef struct +{ + __IO uint32_t TIM0_G : 3; + __IO uint32_t TIM1_G : 3; + __IO uint32_t TIM2_G : 3; + __IO uint32_t TIM3_G : 3; + __IO uint32_t LPTIM0_G : 3; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_gpio_timgs_field_t; + +typedef struct +{ + __IO uint32_t TIM0_E : 3; + __IO uint32_t TIM1_E : 3; + __IO uint32_t TIM2_E : 3; + __IO uint32_t TIM3_E : 3; + __IO uint32_t LPTIM0_E : 3; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_gpio_times_field_t; + +typedef struct +{ + __IO uint32_t TIM0_CA : 3; + __IO uint32_t TIM1_CA : 3; + __IO uint32_t TIM2_CA : 3; + __IO uint32_t TIM3_CA : 3; + __IO uint32_t TIM3_CB : 3; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_gpio_timcps_field_t; + +typedef struct +{ + __IO uint32_t PCA_CH0 : 3; + __IO uint32_t PCA_ECI : 3; + __IO uint32_t LPTIM1_G : 3; + __IO uint32_t LPTIM1_E : 3; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pcas_field_t; + +typedef struct +{ + __IO uint32_t PCNT_S0 : 2; + __IO uint32_t PCNT_S1 : 2; + uint32_t RESERVED4 :27; + __IO uint32_t RSV : 1; +} stc_gpio_pcnt_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pe15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_gpio_pf11_sel_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pedir_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pein_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_peout_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_peads_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pebset_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pebclr_field_t; + +typedef struct +{ + __IO uint32_t PEBCLR :16; + __IO uint32_t PEBSET :16; +} stc_gpio_pebsetclr_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pedr_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pepu_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pepd_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_peod_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pehie_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pelie_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_perie_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pefie_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfdir_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfin_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfout_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfads_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfbset_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfbclr_field_t; + +typedef struct +{ + __IO uint32_t PFBCLR :12; + uint32_t RESERVED12 : 4; + __IO uint32_t PFBSET :12; +} stc_gpio_pfbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfdr_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfpu_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfpd_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfod_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfhie_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pflie_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pfrie_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pffie_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pe_stat_field_t; + +typedef struct +{ + __IO uint32_t PE00 : 1; + __IO uint32_t PE01 : 1; + __IO uint32_t PE02 : 1; + __IO uint32_t PE03 : 1; + __IO uint32_t PE04 : 1; + __IO uint32_t PE05 : 1; + __IO uint32_t PE06 : 1; + __IO uint32_t PE07 : 1; + __IO uint32_t PE08 : 1; + __IO uint32_t PE09 : 1; + __IO uint32_t PE10 : 1; + __IO uint32_t PE11 : 1; + __IO uint32_t PE12 : 1; + __IO uint32_t PE13 : 1; + __IO uint32_t PE14 : 1; + __IO uint32_t PE15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_gpio_pe_iclr_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pf_stat_field_t; + +typedef struct +{ + __IO uint32_t PF00 : 1; + __IO uint32_t PF01 : 1; + __IO uint32_t PF02 : 1; + __IO uint32_t PF03 : 1; + __IO uint32_t PF04 : 1; + __IO uint32_t PF05 : 1; + __IO uint32_t PF06 : 1; + __IO uint32_t PF07 : 1; + __IO uint32_t PF08 : 1; + __IO uint32_t PF09 : 1; + __IO uint32_t PF10 : 1; + __IO uint32_t PF11 : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_gpio_pf_iclr_field_t; + +typedef struct +{ + __IO uint32_t TME : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_i2c_tmrun_field_t; + +typedef struct +{ + __IO uint32_t TM : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_i2c_tm_field_t; + +typedef struct +{ + __IO uint32_t H1M : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t AA : 1; + __IO uint32_t SI : 1; + __IO uint32_t STO : 1; + __IO uint32_t STA : 1; + __IO uint32_t ENS : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_i2c_cr_field_t; + +typedef struct +{ + __IO uint32_t DAT : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_i2c_data_field_t; + +typedef struct +{ + __IO uint32_t GC : 1; + __IO uint32_t ADR : 7; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_i2c_addr_field_t; + +typedef struct +{ + __IO uint32_t STA : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_i2c_stat_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t LCDCLK : 2; + __IO uint32_t CPCLK : 2; + __IO uint32_t BIAS : 1; + __IO uint32_t DUTY : 3; + __IO uint32_t BSEL : 3; + __IO uint32_t CONTRAST : 4; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lcd_cr0_field_t; + +typedef struct +{ + __IO uint32_t BLINKCNT : 6; + __IO uint32_t BLINKEN : 1; + __IO uint32_t CLKSRC : 1; + __IO uint32_t MODE : 1; + __IO uint32_t IE : 1; + __IO uint32_t DMAEN : 1; + __IO uint32_t INTF : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_lcd_cr1_field_t; + +typedef struct +{ + uint32_t RESERVED0 :10; + __IO uint32_t INTF : 1; + uint32_t RESERVED11 :20; + __IO uint32_t RSV : 1; +} stc_lcd_intclr_field_t; + +typedef struct +{ + __IO uint32_t S0 : 1; + __IO uint32_t S1 : 1; + __IO uint32_t S2 : 1; + __IO uint32_t S3 : 1; + __IO uint32_t S4 : 1; + __IO uint32_t S5 : 1; + __IO uint32_t S6 : 1; + __IO uint32_t S7 : 1; + __IO uint32_t S8 : 1; + __IO uint32_t S9 : 1; + __IO uint32_t S10 : 1; + __IO uint32_t S11 : 1; + __IO uint32_t S12 : 1; + __IO uint32_t S13 : 1; + __IO uint32_t S14 : 1; + __IO uint32_t S15 : 1; + __IO uint32_t S16 : 1; + __IO uint32_t S17 : 1; + __IO uint32_t S18 : 1; + __IO uint32_t S19 : 1; + __IO uint32_t S20 : 1; + __IO uint32_t S21 : 1; + __IO uint32_t S22 : 1; + __IO uint32_t S23 : 1; + __IO uint32_t S24 : 1; + __IO uint32_t S25 : 1; + __IO uint32_t S26 : 1; + __IO uint32_t S27 : 1; + __IO uint32_t S28 : 1; + __IO uint32_t S29 : 1; + __IO uint32_t S30 : 1; + __IO uint32_t S31 : 1; +} stc_lcd_poen0_field_t; + +typedef struct +{ + __IO uint32_t S32 : 1; + __IO uint32_t S33 : 1; + __IO uint32_t S34 : 1; + __IO uint32_t S35 : 1; + __IO uint32_t S36C7 : 1; + __IO uint32_t S37C6 : 1; + __IO uint32_t S38C5 : 1; + __IO uint32_t S39C4 : 1; + __IO uint32_t S40 : 1; + __IO uint32_t S41 : 1; + __IO uint32_t S42 : 1; + __IO uint32_t S43 : 1; + __IO uint32_t MUX : 1; + __IO uint32_t S44 : 1; + __IO uint32_t S45 : 1; + __IO uint32_t S46 : 1; + __IO uint32_t S47 : 1; + __IO uint32_t S48 : 1; + __IO uint32_t S49 : 1; + __IO uint32_t S50 : 1; + __IO uint32_t S51 : 1; + __IO uint32_t C0 : 1; + __IO uint32_t C1 : 1; + __IO uint32_t C2 : 1; + __IO uint32_t C3 : 1; +} stc_lcd_poen1_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram0_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram1_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram2_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram3_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram4_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram5_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram6_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram7_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ram8_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ram9_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_rama_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ramb_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ramc_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ramd_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_rame_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t RSV : 8; +} stc_lcd_ramf_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lptimer_cnt_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lptimer_arr_field_t; + +typedef struct +{ + __IO uint32_t TR : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOG_EN : 1; + __IO uint32_t TCK_SEL : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t WT_FLAG : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATE_P : 1; + __IO uint32_t IE : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_lptimer_cr_field_t; + +typedef struct +{ + __IO uint32_t TF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_lptimer_ifr_field_t; + +typedef struct +{ + __IO uint32_t TFC : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_lptimer_iclr_field_t; + +typedef struct +{ + __IO uint32_t DATA : 8; + __IO uint32_t DATA8 : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_lpuart_sbuf_field_t; + +typedef struct +{ + __IO uint32_t RCIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t B8CONT : 2; + __IO uint32_t REN : 1; + __IO uint32_t ADRDET : 1; + __IO uint32_t SM : 2; + __IO uint32_t TXEIE : 1; + __IO uint32_t OVER : 2; + __IO uint32_t SCLKSEL : 2; + __IO uint32_t PEIE : 1; + __IO uint32_t STOPBIT : 2; + __IO uint32_t DMARXEN : 1; + __IO uint32_t DMATXEN : 1; + __IO uint32_t RTSEN : 1; + __IO uint32_t CTSEN : 1; + __IO uint32_t CTSIE : 1; + __IO uint32_t FEIE : 1; + __IO uint32_t HDSEL : 1; + uint32_t RESERVED23 : 8; + __IO uint32_t RSV : 1; +} stc_lpuart_scon_field_t; + +typedef struct +{ + __IO uint32_t SADDR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_lpuart_saddr_field_t; + +typedef struct +{ + __IO uint32_t SADEN : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_lpuart_saden_field_t; + +typedef struct +{ + __IO uint32_t RC : 1; + __IO uint32_t TC : 1; + __IO uint32_t FE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t PE : 1; + __IO uint32_t CTSIF : 1; + __IO uint32_t CTS : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_lpuart_isr_field_t; + +typedef struct +{ + __IO uint32_t RCCF : 1; + __IO uint32_t TCCF : 1; + __IO uint32_t FECF : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PECF : 1; + __IO uint32_t CTSIFCF : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_lpuart_icr_field_t; + +typedef struct +{ + __IO uint32_t SCNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lpuart_scnt_field_t; + +typedef struct +{ + __IO uint32_t LVDEN : 1; + __IO uint32_t ACT : 1; + __IO uint32_t SOURCE_SEL : 2; + __IO uint32_t VTDS : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FTEN : 1; + __IO uint32_t RTEN : 1; + __IO uint32_t HTEN : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_lvd_cr_field_t; + +typedef struct +{ + __IO uint32_t INTF : 1; + __IO uint32_t FILTER : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_lvd_ifr_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t AZEN : 1; + __IO uint32_t BUFEN : 1; + __IO uint32_t OEN1 : 1; + __IO uint32_t OEN2 : 1; + __IO uint32_t OEN3 : 1; + __IO uint32_t OEN4 : 1; + __IO uint32_t BIASSEL : 3; + uint32_t RESERVED10 :21; + __IO uint32_t RSV : 1; +} stc_opa_cr0_field_t; + +typedef struct +{ + __IO uint32_t ADCTR_EN : 1; + __IO uint32_t TRIGGER : 1; + __IO uint32_t AZ_PULSE : 1; + __IO uint32_t CLK_SW_SET : 1; + __IO uint32_t CLK_SEL : 4; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_opa_cr1_field_t; + +typedef struct +{ + __IO uint32_t CCF0 : 1; + __IO uint32_t CCF1 : 1; + __IO uint32_t CCF2 : 1; + __IO uint32_t CCF3 : 1; + __IO uint32_t CCF4 : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t CR : 1; + __IO uint32_t CF : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccon_field_t; + +typedef struct +{ + __IO uint32_t CFIE : 1; + __IO uint32_t CPS : 3; + uint32_t RESERVED4 : 2; + __IO uint32_t WDTE : 1; + __IO uint32_t CIDL : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_cmod_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_cnt_field_t; + +typedef struct +{ + __IO uint32_t CCF0 : 1; + __IO uint32_t CCF1 : 1; + __IO uint32_t CCF2 : 1; + __IO uint32_t CCF3 : 1; + __IO uint32_t CCF4 : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t CF : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_iclr_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm0_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm1_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm2_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm3_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pca_ccapm4_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap0h_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap0l_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap1h_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap1l_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap2h_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap2l_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap3h_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap3l_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap4h_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pca_ccap4l_field_t; + +typedef struct +{ + __IO uint32_t CCAPO0 : 1; + __IO uint32_t CCAPO1 : 1; + __IO uint32_t CCAPO2 : 1; + __IO uint32_t CCAPO3 : 1; + __IO uint32_t CCAPO4 : 1; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_pca_ccapo_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap0_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap1_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap2_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap3_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_ccap4_field_t; + +typedef struct +{ + __IO uint32_t CARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pca_carr_field_t; + +typedef struct +{ + __IO uint32_t EPWM : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_pca_epwm_field_t; + +typedef struct +{ + __IO uint32_t RUN : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_pcnt_run_field_t; + +typedef struct +{ + __IO uint32_t MODE : 2; + __IO uint32_t CLKSEL : 2; + __IO uint32_t DIR : 1; + __IO uint32_t S0P : 1; + __IO uint32_t S1P : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_pcnt_ctrl_field_t; + +typedef struct +{ + __IO uint32_t CLKDIV :13; + __IO uint32_t DEBTOP : 3; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_pcnt_flt_field_t; + +typedef struct +{ + __IO uint32_t TH :12; + uint32_t RESERVED12 : 4; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_pcnt_tocr_field_t; + +typedef struct +{ + __IO uint32_t T2C : 1; + __IO uint32_t B2T : 1; + __IO uint32_t B2C : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_pcnt_cmd_field_t; + +typedef struct +{ + __IO uint32_t DIR : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_pcnt_sr1_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pcnt_cnt_field_t; + +typedef struct +{ + __IO uint32_t TOP :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pcnt_top_field_t; + +typedef struct +{ + __IO uint32_t BUF :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_pcnt_buf_field_t; + +typedef struct +{ + __IO uint32_t UF : 1; + __IO uint32_t OV : 1; + __IO uint32_t TO : 1; + __IO uint32_t DIR : 1; + __IO uint32_t FE : 1; + __IO uint32_t BB : 1; + __IO uint32_t S0E : 1; + __IO uint32_t S1E : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pcnt_ifr_field_t; + +typedef struct +{ + __IO uint32_t UF : 1; + __IO uint32_t OV : 1; + __IO uint32_t TO : 1; + __IO uint32_t DIR : 1; + __IO uint32_t FE : 1; + __IO uint32_t BB : 1; + __IO uint32_t S0E : 1; + __IO uint32_t S1E : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pcnt_icr_field_t; + +typedef struct +{ + __IO uint32_t UF : 1; + __IO uint32_t OV : 1; + __IO uint32_t TO : 1; + __IO uint32_t DIR : 1; + __IO uint32_t FE : 1; + __IO uint32_t BB : 1; + __IO uint32_t S0E : 1; + __IO uint32_t S1E : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_pcnt_ien_field_t; + +typedef struct +{ + __IO uint32_t T2C : 1; + __IO uint32_t B2T : 1; + __IO uint32_t B2C : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_pcnt_sr2_field_t; + +typedef struct +{ + __IO uint32_t DBG : 2; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_pcnt_dbg_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t IE : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_ram_cr_field_t; + +typedef struct +{ + __IO uint32_t ERRADDR :15; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_ram_erraddr_field_t; + +typedef struct +{ + __IO uint32_t ERR : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_ram_ifr_field_t; + +typedef struct +{ + __IO uint32_t ERRCLR : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_ram_iclr_field_t; + +typedef struct +{ + __IO uint32_t POR5V : 1; + __IO uint32_t POR15V : 1; + __IO uint32_t LVD : 1; + __IO uint32_t WDT : 1; + __IO uint32_t PCA : 1; + __IO uint32_t LOCKUP : 1; + __IO uint32_t SYSREQ : 1; + __IO uint32_t RSTB : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_reset_flag_field_t; + +typedef struct +{ + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t I2C0 : 1; + __IO uint32_t I2C1 : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t BASETIM : 1; + __IO uint32_t LPTIM0 : 1; + __IO uint32_t ADVTIM : 1; + __IO uint32_t TIM3 : 1; + uint32_t RESERVED12 : 1; + __IO uint32_t OPA : 1; + __IO uint32_t PCA : 1; + uint32_t RESERVED15 : 1; + __IO uint32_t ADC : 1; + __IO uint32_t VC : 1; + __IO uint32_t RNG : 1; + __IO uint32_t PCNT : 1; + __IO uint32_t RTC : 1; + __IO uint32_t TRIM : 1; + __IO uint32_t LCD : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t TICK : 1; + __IO uint32_t SWD : 1; + __IO uint32_t CRC : 1; + __IO uint32_t AES : 1; + __IO uint32_t GPIO : 1; + __IO uint32_t DMA : 1; +} stc_reset_peri_reset0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 3; + __IO uint32_t DAC : 1; + __IO uint32_t LPTIM1 : 1; + uint32_t RESERVED5 : 3; + __IO uint32_t UART2 : 1; + __IO uint32_t UART3 : 1; + uint32_t RESERVED10 :21; + __IO uint32_t RSV : 1; +} stc_reset_peri_reset1_field_t; + +typedef struct +{ + __IO uint32_t PRDS : 3; + __IO uint32_t AMPM : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t HZ1OE : 1; + __IO uint32_t HZ1SEL : 1; + __IO uint32_t START : 1; + __IO uint32_t PRDX : 6; + __IO uint32_t PRDSEL : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_rtc_cr0_field_t; + +typedef struct +{ + __IO uint32_t WAIT : 1; + __IO uint32_t WAITF : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t PRDF : 1; + __IO uint32_t ALMF : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t ALMIE : 1; + __IO uint32_t ALMEN : 1; + __IO uint32_t CKSEL : 3; + uint32_t RESERVED11 :20; + __IO uint32_t RSV : 1; +} stc_rtc_cr1_field_t; + +typedef struct +{ + __IO uint32_t SECL : 4; + __IO uint32_t SECH : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_sec_field_t; + +typedef struct +{ + __IO uint32_t MINL : 4; + __IO uint32_t MINH : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_min_field_t; + +typedef struct +{ + __IO uint32_t HOURL : 4; + __IO uint32_t HOURH : 2; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_rtc_hour_field_t; + +typedef struct +{ + __IO uint32_t WEEK : 3; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_rtc_week_field_t; + +typedef struct +{ + __IO uint32_t DAYL : 4; + __IO uint32_t DAYH : 2; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_rtc_day_field_t; + +typedef struct +{ + __IO uint32_t MON : 5; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_rtc_mon_field_t; + +typedef struct +{ + __IO uint32_t YEARL : 4; + __IO uint32_t YEARH : 4; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_rtc_year_field_t; + +typedef struct +{ + __IO uint32_t ALMMINL : 4; + __IO uint32_t ALMMINH : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_almmin_field_t; + +typedef struct +{ + __IO uint32_t ALMHOURL : 4; + __IO uint32_t ALMHOURH : 2; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_rtc_almhour_field_t; + +typedef struct +{ + __IO uint32_t ALMWEEK : 7; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_almweek_field_t; + +typedef struct +{ + __IO uint32_t CR : 9; + uint32_t RESERVED9 : 6; + __IO uint32_t EN : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_rtc_compen_field_t; + +typedef struct +{ + __IO uint32_t ALMSECL : 4; + __IO uint32_t ALMSECH : 3; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_rtc_almsec_field_t; + +typedef struct +{ + __IO uint32_t SPR0 : 1; + __IO uint32_t SPR1 : 1; + __IO uint32_t CPHA : 1; + __IO uint32_t CPOL : 1; + __IO uint32_t MSTR : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t SPEN : 1; + __IO uint32_t SPR2 : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_spi_cr_field_t; + +typedef struct +{ + __IO uint32_t SSN : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_spi_ssn_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t RXNE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t BUSY : 1; + __IO uint32_t MDF : 1; + __IO uint32_t SSERR : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t SPIF : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_spi_stat_field_t; + +typedef struct +{ + __IO uint32_t DAT : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_spi_data_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t INT_EN : 1; + __IO uint32_t HDMA_RX : 1; + __IO uint32_t HDMA_TX : 1; + __IO uint32_t TXEIE : 1; + __IO uint32_t RXNEIE : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_spi_cr2_field_t; + +typedef struct +{ + __IO uint32_t INT_CLR : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_spi_iclr_field_t; + +typedef struct +{ + __IO uint32_t RCH_EN : 1; + __IO uint32_t XTH_EN : 1; + __IO uint32_t RCL_EN : 1; + __IO uint32_t XTL_EN : 1; + __IO uint32_t PLL_EN : 1; + __IO uint32_t CLKSW : 3; + __IO uint32_t HCLK_PRS : 3; + __IO uint32_t PCLK_PRS : 2; + uint32_t RESERVED13 : 2; + __IO uint32_t WAKEUP_BYRCH : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_sysctrl_sysctrl0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t EXTH_EN : 1; + __IO uint32_t EXTL_EN : 1; + __IO uint32_t XTL_ALWAYS_ON : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t RTC_LPW : 1; + __IO uint32_t LOCKUP_EN : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t SWD_USE_IO : 1; + __IO uint32_t RTC_FREQ_ADJUST : 3; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_sysctrl_sysctrl1_field_t; + +typedef struct +{ + __IO uint32_t SYSCTRL2 :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_sysctrl_sysctrl2_field_t; + +typedef struct +{ + __IO uint32_t TRIM :11; + __IO uint32_t STABLE : 1; + uint32_t RESERVED12 :19; + __IO uint32_t RSV : 1; +} stc_sysctrl_rch_cr_field_t; + +typedef struct +{ + __IO uint32_t DRIVER : 2; + __IO uint32_t XTH_FSEL : 2; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_sysctrl_xth_cr_field_t; + +typedef struct +{ + __IO uint32_t TRIM :10; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_sysctrl_rcl_cr_field_t; + +typedef struct +{ + __IO uint32_t DRIVER : 2; + __IO uint32_t AMP_SEL : 2; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_sysctrl_xtl_cr_field_t; + +typedef struct +{ + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t I2C0 : 1; + __IO uint32_t I2C1 : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t BASETIM : 1; + __IO uint32_t LPTIM0 : 1; + __IO uint32_t ADVTIM : 1; + __IO uint32_t TIM3 : 1; + uint32_t RESERVED12 : 1; + __IO uint32_t OPA : 1; + __IO uint32_t PCA : 1; + __IO uint32_t WDT : 1; + __IO uint32_t ADC : 1; + __IO uint32_t VC : 1; + __IO uint32_t RNG : 1; + __IO uint32_t PCNT : 1; + __IO uint32_t RTC : 1; + __IO uint32_t TRIM : 1; + __IO uint32_t LCD : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t TICK : 1; + __IO uint32_t SWD : 1; + __IO uint32_t CRC : 1; + __IO uint32_t AES : 1; + __IO uint32_t GPIO : 1; + __IO uint32_t DMA : 1; + uint32_t RESERVED30 : 1; + __IO uint32_t FLASH : 1; +} stc_sysctrl_peri_clken0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 3; + __IO uint32_t DAC : 1; + __IO uint32_t LPTIM1 : 1; + uint32_t RESERVED5 : 3; + __IO uint32_t UART2 : 1; + __IO uint32_t UART3 : 1; + uint32_t RESERVED10 :21; + __IO uint32_t RSV : 1; +} stc_sysctrl_peri_clken1_field_t; + +typedef struct +{ + __IO uint32_t REFSEL : 2; + __IO uint32_t FOSC : 3; + __IO uint32_t DIVN : 4; + __IO uint32_t IBSEL : 2; + __IO uint32_t LFSEL : 2; + __IO uint32_t FRSEL : 2; + __IO uint32_t STARTUP : 3; + __IO uint32_t STABLE : 1; + uint32_t RESERVED19 :12; + __IO uint32_t RSV : 1; +} stc_sysctrl_pll_cr_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim0_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim0_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim0_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim0_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VCE : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim0_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim1_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim1_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim1_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim1_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VCE : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim1_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim2_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim2_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim2_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim2_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VCE : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim2_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim3_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + uint32_t RESERVED14 :17; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 :30; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim3_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 :28; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim3_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED28 : 3; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + __IO uint32_t CA1F : 1; + __IO uint32_t CA2F : 1; + __IO uint32_t CB0F : 1; + __IO uint32_t CB1F : 1; + __IO uint32_t CB2F : 1; + __IO uint32_t CA0E : 1; + __IO uint32_t CA1E : 1; + __IO uint32_t CA2E : 1; + __IO uint32_t CB0E : 1; + __IO uint32_t CB1E : 1; + __IO uint32_t CB2E : 1; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + __IO uint32_t CA1F : 1; + __IO uint32_t CA2F : 1; + __IO uint32_t CB0F : 1; + __IO uint32_t CB1F : 1; + __IO uint32_t CB2F : 1; + __IO uint32_t CA0E : 1; + __IO uint32_t CA1E : 1; + __IO uint32_t CA2E : 1; + __IO uint32_t CB0E : 1; + __IO uint32_t CB1E : 1; + __IO uint32_t CB2E : 1; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; + uint32_t RESERVED13 :18; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + __IO uint32_t OCMA1_FLTA1 : 3; + __IO uint32_t CCPA1 : 1; + __IO uint32_t OCMB1_FLTB1 : 3; + __IO uint32_t CCPB1 : 1; + __IO uint32_t OCMA2_FLTA2 : 3; + __IO uint32_t CCPA2 : 1; + __IO uint32_t OCMB2_FLTB2 : 3; + __IO uint32_t CCPB2 : 1; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim3_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + __IO uint32_t CMA1E : 1; + __IO uint32_t CMA2E : 1; + __IO uint32_t CMB0E : 1; + __IO uint32_t CMB1E : 1; + __IO uint32_t CMB2E : 1; + __IO uint32_t ADTE : 1; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_crch1_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_crch2_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VCE : 1; + uint32_t RESERVED15 :16; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t CCR1A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr1a_field_t; + +typedef struct +{ + __IO uint32_t CCR1B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr1b_field_t; + +typedef struct +{ + __IO uint32_t CCR2A :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr2a_field_t; + +typedef struct +{ + __IO uint32_t CCR2B :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_tim3_mode23_ccr2b_field_t; + +typedef struct +{ + __IO uint32_t RNGCIR_EN : 1; + __IO uint32_t RNG_RUN : 1; + uint32_t RESERVED2 :29; + __IO uint32_t RSV : 1; +} stc_trng_cr_field_t; + +typedef struct +{ + __IO uint32_t LOAD : 1; + __IO uint32_t FDBK : 1; + __IO uint32_t CNT : 3; + uint32_t RESERVED5 :26; + __IO uint32_t RSV : 1; +} stc_trng_mode_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_trng_data0_field_t; + +typedef struct +{ + __IO uint32_t DATA1 :32; +} stc_trng_data1_field_t; + +typedef struct +{ + __IO uint32_t DATA : 8; + __IO uint32_t DATA8 : 1; + uint32_t RESERVED9 :22; + __IO uint32_t RSV : 1; +} stc_uart_sbuf_field_t; + +typedef struct +{ + __IO uint32_t RCIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t B8CONT : 2; + __IO uint32_t REN : 1; + __IO uint32_t ADRDET : 1; + __IO uint32_t SM : 2; + __IO uint32_t TXEIE : 1; + __IO uint32_t OVER : 1; + uint32_t RESERVED10 : 3; + __IO uint32_t PEIE : 1; + __IO uint32_t STOPBIT : 2; + __IO uint32_t DMARXEN : 1; + __IO uint32_t DMATXEN : 1; + __IO uint32_t RTSEN : 1; + __IO uint32_t CTSEN : 1; + __IO uint32_t CTSIE : 1; + __IO uint32_t FEIE : 1; + __IO uint32_t HDSEL : 1; + uint32_t RESERVED23 : 8; + __IO uint32_t RSV : 1; +} stc_uart_scon_field_t; + +typedef struct +{ + __IO uint32_t SADDR : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_uart_saddr_field_t; + +typedef struct +{ + __IO uint32_t SADEN : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_uart_saden_field_t; + +typedef struct +{ + __IO uint32_t RC : 1; + __IO uint32_t TC : 1; + __IO uint32_t FE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t PE : 1; + __IO uint32_t CTSIF : 1; + __IO uint32_t CTS : 1; + uint32_t RESERVED7 :24; + __IO uint32_t RSV : 1; +} stc_uart_isr_field_t; + +typedef struct +{ + __IO uint32_t RCCF : 1; + __IO uint32_t TCCF : 1; + __IO uint32_t FECF : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PECF : 1; + __IO uint32_t CTSIFCF : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_uart_icr_field_t; + +typedef struct +{ + __IO uint32_t SCNT :16; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_uart_scnt_field_t; + +typedef struct +{ + __IO uint32_t DIV : 6; + __IO uint32_t DIV_EN : 1; + __IO uint32_t REF2P5_SEL : 1; + __IO uint32_t VC0_BIAS_SEL : 2; + __IO uint32_t VC0_HYS_SEL : 2; + __IO uint32_t VC1_BIAS_SEL : 2; + __IO uint32_t VC1_HYS_SEL : 2; + __IO uint32_t VC2_BIAS_SEL : 2; + __IO uint32_t VC2_HYS_SEL : 2; + uint32_t RESERVED20 :11; + __IO uint32_t RSV : 1; +} stc_vc_cr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_vc_vc0_cr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_vc_vc1_cr_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_vc_vc0_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_vc_vc1_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t VC0_INTF : 1; + __IO uint32_t VC1_INTF : 1; + __IO uint32_t VC0_FILTER : 1; + __IO uint32_t VC1_FILTER : 1; + __IO uint32_t VC2_INTF : 1; + __IO uint32_t VC2_FILTER : 1; + uint32_t RESERVED6 :25; + __IO uint32_t RSV : 1; +} stc_vc_ifr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; + uint32_t RESERVED17 :14; + __IO uint32_t RSV : 1; +} stc_vc_vc2_cr_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_vc_vc2_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t RST : 8; + uint32_t RESERVED8 :23; + __IO uint32_t RSV : 1; +} stc_wdt_rst_field_t; + +typedef struct +{ + __IO uint32_t WOV : 4; + __IO uint32_t R : 1; + __IO uint32_t WINT_EN : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t INT : 1; + __IO uint32_t WCNTL : 8; + uint32_t RESERVED16 :15; + __IO uint32_t RSV : 1; +} stc_wdt_con_field_t; + + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CR0; + stc_adc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_adc_cr1_field_t CR1_f; + }; + uint8_t RESERVED2[52]; + union + { + __IO uint32_t SQR0; + stc_adc_sqr0_field_t SQR0_f; + }; + union + { + __IO uint32_t SQR1; + stc_adc_sqr1_field_t SQR1_f; + }; + union + { + __IO uint32_t SQR2; + stc_adc_sqr2_field_t SQR2_f; + }; + union + { + __IO uint32_t JQR; + stc_adc_jqr_field_t JQR_f; + }; + union + { + __IO uint32_t SQRRESULT0; + stc_adc_sqrresult0_field_t SQRRESULT0_f; + }; + union + { + __IO uint32_t SQRRESULT1; + stc_adc_sqrresult1_field_t SQRRESULT1_f; + }; + union + { + __IO uint32_t SQRRESULT2; + stc_adc_sqrresult2_field_t SQRRESULT2_f; + }; + union + { + __IO uint32_t SQRRESULT3; + stc_adc_sqrresult3_field_t SQRRESULT3_f; + }; + union + { + __IO uint32_t SQRRESULT4; + stc_adc_sqrresult4_field_t SQRRESULT4_f; + }; + union + { + __IO uint32_t SQRRESULT5; + stc_adc_sqrresult5_field_t SQRRESULT5_f; + }; + union + { + __IO uint32_t SQRRESULT6; + stc_adc_sqrresult6_field_t SQRRESULT6_f; + }; + union + { + __IO uint32_t SQRRESULT7; + stc_adc_sqrresult7_field_t SQRRESULT7_f; + }; + union + { + __IO uint32_t SQRRESULT8; + stc_adc_sqrresult8_field_t SQRRESULT8_f; + }; + union + { + __IO uint32_t SQRRESULT9; + stc_adc_sqrresult9_field_t SQRRESULT9_f; + }; + union + { + __IO uint32_t SQRRESULT10; + stc_adc_sqrresult10_field_t SQRRESULT10_f; + }; + union + { + __IO uint32_t SQRRESULT11; + stc_adc_sqrresult11_field_t SQRRESULT11_f; + }; + union + { + __IO uint32_t SQRRESULT12; + stc_adc_sqrresult12_field_t SQRRESULT12_f; + }; + union + { + __IO uint32_t SQR_RESULT13; + stc_adc_sqr_result13_field_t SQR_RESULT13_f; + }; + union + { + __IO uint32_t SQRRESULT14; + stc_adc_sqrresult14_field_t SQRRESULT14_f; + }; + union + { + __IO uint32_t SQRRESULT15; + stc_adc_sqrresult15_field_t SQRRESULT15_f; + }; + union + { + __IO uint32_t JQRRESULT0; + stc_adc_jqrresult0_field_t JQRRESULT0_f; + }; + union + { + __IO uint32_t JQRRESULT1; + stc_adc_jqrresult1_field_t JQRRESULT1_f; + }; + union + { + __IO uint32_t JQRRESULT2; + stc_adc_jqrresult2_field_t JQRRESULT2_f; + }; + union + { + __IO uint32_t JQRRESULT3; + stc_adc_jqrresult3_field_t JQRRESULT3_f; + }; + union + { + __IO uint32_t RESULT; + stc_adc_result_field_t RESULT_f; + }; + union + { + __IO uint32_t RESULTACC; + stc_adc_resultacc_field_t RESULTACC_f; + }; + union + { + __IO uint32_t HT; + stc_adc_ht_field_t HT_f; + }; + union + { + __IO uint32_t LT; + stc_adc_lt_field_t LT_f; + }; + union + { + __IO uint32_t IFR; + stc_adc_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICR; + stc_adc_icr_field_t ICR_f; + }; + union + { + __IO uint32_t EXTTRIGGER0; + stc_adc_exttrigger0_field_t EXTTRIGGER0_f; + }; + union + { + __IO uint32_t EXTTRIGGER1; + stc_adc_exttrigger1_field_t EXTTRIGGER1_f; + }; + union + { + __IO uint32_t SGLSTART; + stc_adc_sglstart_field_t SGLSTART_f; + }; + union + { + __IO uint32_t SQRSTART; + stc_adc_sqrstart_field_t SQRSTART_f; + }; + union + { + __IO uint32_t JQRSTART; + stc_adc_jqrstart_field_t JQRSTART_f; + }; + union + { + __IO uint32_t ALLSTART; + stc_adc_allstart_field_t ALLSTART_f; + }; +}M0P_ADC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_adtim_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_adtim_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_adtim_perbr_field_t PERBR_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t GCMAR; + stc_adtim_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_adtim_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_adtim_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_adtim_gcmdr_field_t GCMDR_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SCMAR; + stc_adtim_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_adtim_scmbr_field_t SCMBR_f; + }; + uint8_t RESERVED9[16]; + union + { + __IO uint32_t DTUAR; + stc_adtim_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_adtim_dtdar_field_t DTDAR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint32_t GCONR; + stc_adtim_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_adtim_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_adtim_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_adtim_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_adtim_dconr_field_t DCONR_f; + }; + uint8_t RESERVED16[4]; + union + { + __IO uint32_t FCONR; + stc_adtim_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_adtim_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_adtim_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_adtim_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_adtim_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCELR; + stc_adtim_hcelr_field_t HCELR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_adtim_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_adtim_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_adtim_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_adtim_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED26[112]; + union + { + __IO uint32_t IFR; + stc_adtim_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_adtim_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CR; + stc_adtim_cr_field_t CR_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t AOSSR; + stc_adtim_aossr_field_t AOSSR_f; + }; + union + { + __IO uint32_t AOSCL; + stc_adtim_aoscl_field_t AOSCL_f; + }; + union + { + __IO uint32_t PTBKS; + stc_adtim_ptbks_field_t PTBKS_f; + }; + union + { + __IO uint32_t TTRIG; + stc_adtim_ttrig_field_t TTRIG_f; + }; + union + { + __IO uint32_t ITRIG; + stc_adtim_itrig_field_t ITRIG_f; + }; + union + { + __IO uint32_t PTBKP; + stc_adtim_ptbkp_field_t PTBKP_f; + }; + uint8_t RESERVED35[716]; + union + { + __IO uint32_t SSTAR; + stc_adtim_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_adtim_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_adtim_sclrr_field_t SCLRR_f; + }; +}M0P_ADTIM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_aes_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + union + { + __IO uint32_t DATA0; + stc_aes_data0_field_t DATA0_f; + }; + union + { + __IO uint32_t DATA1; + stc_aes_data1_field_t DATA1_f; + }; + union + { + __IO uint32_t DATA2; + stc_aes_data2_field_t DATA2_f; + }; + union + { + __IO uint32_t DATA3; + stc_aes_data3_field_t DATA3_f; + }; + union + { + __IO uint32_t KEY0; + stc_aes_key0_field_t KEY0_f; + }; + union + { + __IO uint32_t KEY1; + stc_aes_key1_field_t KEY1_f; + }; + union + { + __IO uint32_t KEY2; + stc_aes_key2_field_t KEY2_f; + }; + union + { + __IO uint32_t KEY3; + stc_aes_key3_field_t KEY3_f; + }; + union + { + __IO uint32_t KEY4; + stc_aes_key4_field_t KEY4_f; + }; + union + { + __IO uint32_t KEY5; + stc_aes_key5_field_t KEY5_f; + }; + union + { + __IO uint32_t KEY6; + stc_aes_key6_field_t KEY6_f; + }; + union + { + __IO uint32_t KEY7; + stc_aes_key7_field_t KEY7_f; + }; +}M0P_AES_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_bgr_cr_field_t CR_f; + }; +}M0P_BGR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_clk_trim_cr_field_t CR_f; + }; + union + { + __IO uint32_t REFCON; + stc_clk_trim_refcon_field_t REFCON_f; + }; + union + { + __IO uint32_t REFCNT; + stc_clk_trim_refcnt_field_t REFCNT_f; + }; + union + { + __IO uint32_t CALCNT; + stc_clk_trim_calcnt_field_t CALCNT_f; + }; + union + { + __IO uint32_t IFR; + stc_clk_trim_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_clk_trim_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CALCON; + stc_clk_trim_calcon_field_t CALCON_f; + }; +}M0P_CLK_TRIM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_crc_cr_field_t CR_f; + }; + union + { + __IO uint32_t RESULT; + stc_crc_result_field_t RESULT_f; + }; + uint8_t RESERVED2[120]; + union + { + __IO uint32_t DATA; + stc_crc_data_field_t DATA_f; + }; +}M0P_CRC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_dac_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t SWTRIGR; + stc_dac_swtrigr_field_t SWTRIGR_f; + }; + union + { + __IO uint32_t DHR12R0; + stc_dac_dhr12r0_field_t DHR12R0_f; + }; + union + { + __IO uint32_t DHR12L0; + stc_dac_dhr12l0_field_t DHR12L0_f; + }; + union + { + __IO uint32_t DHR8R0; + stc_dac_dhr8r0_field_t DHR8R0_f; + }; + uint8_t RESERVED5[24]; + union + { + __IO uint32_t DOR0; + stc_dac_dor0_field_t DOR0_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t SR; + stc_dac_sr_field_t SR_f; + }; + union + { + __IO uint32_t ETRS; + stc_dac_etrs_field_t ETRS_f; + }; +}M0P_DAC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t DEBUG_ACTIVE; + stc_debug_active_field_t DEBUG_ACTIVE_f; + }; +}M0P_DEBUG_ACTIVE_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CONF; + stc_dmac_conf_field_t CONF_f; + }; + uint8_t RESERVED1[12]; + union + { + __IO uint32_t CONFA0; + stc_dmac_confa0_field_t CONFA0_f; + }; + union + { + __IO uint32_t CONFB0; + stc_dmac_confb0_field_t CONFB0_f; + }; + union + { + __IO uint32_t SRCADR0; + stc_dmac_srcadr0_field_t SRCADR0_f; + }; + union + { + __IO uint32_t DSTADR0; + stc_dmac_dstadr0_field_t DSTADR0_f; + }; + union + { + __IO uint32_t CONFA1; + stc_dmac_confa1_field_t CONFA1_f; + }; + union + { + __IO uint32_t CONFB1; + stc_dmac_confb1_field_t CONFB1_f; + }; + union + { + __IO uint32_t SRCADR1; + stc_dmac_srcadr1_field_t SRCADR1_f; + }; + union + { + __IO uint32_t DSTADR1; + stc_dmac_dstadr1_field_t DSTADR1_f; + }; +}M0P_DMAC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t TNVS; + stc_flash_tnvs_field_t TNVS_f; + }; + union + { + __IO uint32_t TPGS; + stc_flash_tpgs_field_t TPGS_f; + }; + union + { + __IO uint32_t TPROG; + stc_flash_tprog_field_t TPROG_f; + }; + union + { + __IO uint32_t TSERASE; + stc_flash_tserase_field_t TSERASE_f; + }; + union + { + __IO uint32_t TMERASE; + stc_flash_tmerase_field_t TMERASE_f; + }; + union + { + __IO uint32_t TPRCV; + stc_flash_tprcv_field_t TPRCV_f; + }; + union + { + __IO uint32_t TSRCV; + stc_flash_tsrcv_field_t TSRCV_f; + }; + union + { + __IO uint32_t TMRCV; + stc_flash_tmrcv_field_t TMRCV_f; + }; + union + { + __IO uint32_t CR; + stc_flash_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_flash_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_flash_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t BYPASS; + stc_flash_bypass_field_t BYPASS_f; + }; + union + { + __IO uint32_t SLOCK0; + stc_flash_slock0_field_t SLOCK0_f; + }; + union + { + __IO uint32_t SLOCK1; + stc_flash_slock1_field_t SLOCK1_f; + }; + uint8_t RESERVED14[8]; + union + { + __IO uint32_t SLOCK2; + stc_flash_slock2_field_t SLOCK2_f; + }; + union + { + __IO uint32_t SLOCK3; + stc_flash_slock3_field_t SLOCK3_f; + }; +}M0P_FLASH_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t PA00_SEL; + stc_gpio_pa00_sel_field_t PA00_SEL_f; + }; + union + { + __IO uint32_t PA01_SEL; + stc_gpio_pa01_sel_field_t PA01_SEL_f; + }; + union + { + __IO uint32_t PA02_SEL; + stc_gpio_pa02_sel_field_t PA02_SEL_f; + }; + union + { + __IO uint32_t PA03_SEL; + stc_gpio_pa03_sel_field_t PA03_SEL_f; + }; + union + { + __IO uint32_t PA04_SEL; + stc_gpio_pa04_sel_field_t PA04_SEL_f; + }; + union + { + __IO uint32_t PA05_SEL; + stc_gpio_pa05_sel_field_t PA05_SEL_f; + }; + union + { + __IO uint32_t PA06_SEL; + stc_gpio_pa06_sel_field_t PA06_SEL_f; + }; + union + { + __IO uint32_t PA07_SEL; + stc_gpio_pa07_sel_field_t PA07_SEL_f; + }; + union + { + __IO uint32_t PA08_SEL; + stc_gpio_pa08_sel_field_t PA08_SEL_f; + }; + union + { + __IO uint32_t PA09_SEL; + stc_gpio_pa09_sel_field_t PA09_SEL_f; + }; + union + { + __IO uint32_t PA10_SEL; + stc_gpio_pa10_sel_field_t PA10_SEL_f; + }; + union + { + __IO uint32_t PA11_SEL; + stc_gpio_pa11_sel_field_t PA11_SEL_f; + }; + union + { + __IO uint32_t PA12_SEL; + stc_gpio_pa12_sel_field_t PA12_SEL_f; + }; + union + { + __IO uint32_t PA13_SEL; + stc_gpio_pa13_sel_field_t PA13_SEL_f; + }; + union + { + __IO uint32_t PA14_SEL; + stc_gpio_pa14_sel_field_t PA14_SEL_f; + }; + union + { + __IO uint32_t PA15_SEL; + stc_gpio_pa15_sel_field_t PA15_SEL_f; + }; + union + { + __IO uint32_t PB00_SEL; + stc_gpio_pb00_sel_field_t PB00_SEL_f; + }; + union + { + __IO uint32_t PB01_SEL; + stc_gpio_pb01_sel_field_t PB01_SEL_f; + }; + union + { + __IO uint32_t PB02_SEL; + stc_gpio_pb02_sel_field_t PB02_SEL_f; + }; + union + { + __IO uint32_t PB03_SEL; + stc_gpio_pb03_sel_field_t PB03_SEL_f; + }; + union + { + __IO uint32_t PB04_SEL; + stc_gpio_pb04_sel_field_t PB04_SEL_f; + }; + union + { + __IO uint32_t PB05_SEL; + stc_gpio_pb05_sel_field_t PB05_SEL_f; + }; + union + { + __IO uint32_t PB06_SEL; + stc_gpio_pb06_sel_field_t PB06_SEL_f; + }; + union + { + __IO uint32_t PB07_SEL; + stc_gpio_pb07_sel_field_t PB07_SEL_f; + }; + union + { + __IO uint32_t PB08_SEL; + stc_gpio_pb08_sel_field_t PB08_SEL_f; + }; + union + { + __IO uint32_t PB09_SEL; + stc_gpio_pb09_sel_field_t PB09_SEL_f; + }; + union + { + __IO uint32_t PB10_SEL; + stc_gpio_pb10_sel_field_t PB10_SEL_f; + }; + union + { + __IO uint32_t PB11_SEL; + stc_gpio_pb11_sel_field_t PB11_SEL_f; + }; + union + { + __IO uint32_t PB12_SEL; + stc_gpio_pb12_sel_field_t PB12_SEL_f; + }; + union + { + __IO uint32_t PB13_SEL; + stc_gpio_pb13_sel_field_t PB13_SEL_f; + }; + union + { + __IO uint32_t PB14_SEL; + stc_gpio_pb14_sel_field_t PB14_SEL_f; + }; + union + { + __IO uint32_t PB15_SEL; + stc_gpio_pb15_sel_field_t PB15_SEL_f; + }; + union + { + __IO uint32_t PC00_SEL; + stc_gpio_pc00_sel_field_t PC00_SEL_f; + }; + union + { + __IO uint32_t PC01_SEL; + stc_gpio_pc01_sel_field_t PC01_SEL_f; + }; + union + { + __IO uint32_t PC02_SEL; + stc_gpio_pc02_sel_field_t PC02_SEL_f; + }; + union + { + __IO uint32_t PC03_SEL; + stc_gpio_pc03_sel_field_t PC03_SEL_f; + }; + union + { + __IO uint32_t PC04_SEL; + stc_gpio_pc04_sel_field_t PC04_SEL_f; + }; + union + { + __IO uint32_t PC05_SEL; + stc_gpio_pc05_sel_field_t PC05_SEL_f; + }; + union + { + __IO uint32_t PC06_SEL; + stc_gpio_pc06_sel_field_t PC06_SEL_f; + }; + union + { + __IO uint32_t PC07_SEL; + stc_gpio_pc07_sel_field_t PC07_SEL_f; + }; + union + { + __IO uint32_t PC08_SEL; + stc_gpio_pc08_sel_field_t PC08_SEL_f; + }; + union + { + __IO uint32_t PC09_SEL; + stc_gpio_pc09_sel_field_t PC09_SEL_f; + }; + union + { + __IO uint32_t PC10_SEL; + stc_gpio_pc10_sel_field_t PC10_SEL_f; + }; + union + { + __IO uint32_t PC11_SEL; + stc_gpio_pc11_sel_field_t PC11_SEL_f; + }; + union + { + __IO uint32_t PC12_SEL; + stc_gpio_pc12_sel_field_t PC12_SEL_f; + }; + union + { + __IO uint32_t PC13_SEL; + stc_gpio_pc13_sel_field_t PC13_SEL_f; + }; + union + { + __IO uint32_t PC14_SEL; + stc_gpio_pc14_sel_field_t PC14_SEL_f; + }; + union + { + __IO uint32_t PC15_SEL; + stc_gpio_pc15_sel_field_t PC15_SEL_f; + }; + union + { + __IO uint32_t PD00_SEL; + stc_gpio_pd00_sel_field_t PD00_SEL_f; + }; + union + { + __IO uint32_t PD01_SEL; + stc_gpio_pd01_sel_field_t PD01_SEL_f; + }; + union + { + __IO uint32_t PD02_SEL; + stc_gpio_pd02_sel_field_t PD02_SEL_f; + }; + union + { + __IO uint32_t PD03_SEL; + stc_gpio_pd03_sel_field_t PD03_SEL_f; + }; + union + { + __IO uint32_t PD04_SEL; + stc_gpio_pd04_sel_field_t PD04_SEL_f; + }; + union + { + __IO uint32_t PD05_SEL; + stc_gpio_pd05_sel_field_t PD05_SEL_f; + }; + union + { + __IO uint32_t PD06_SEL; + stc_gpio_pd06_sel_field_t PD06_SEL_f; + }; + union + { + __IO uint32_t PD07_SEL; + stc_gpio_pd07_sel_field_t PD07_SEL_f; + }; + union + { + __IO uint32_t PD08_SEL; + stc_gpio_pd08_sel_field_t PD08_SEL_f; + }; + union + { + __IO uint32_t PD09_SEL; + stc_gpio_pd09_sel_field_t PD09_SEL_f; + }; + union + { + __IO uint32_t PD10_SEL; + stc_gpio_pd10_sel_field_t PD10_SEL_f; + }; + union + { + __IO uint32_t PD11_SEL; + stc_gpio_pd11_sel_field_t PD11_SEL_f; + }; + union + { + __IO uint32_t PD12_SEL; + stc_gpio_pd12_sel_field_t PD12_SEL_f; + }; + union + { + __IO uint32_t PD13_SEL; + stc_gpio_pd13_sel_field_t PD13_SEL_f; + }; + union + { + __IO uint32_t PD14_SEL; + stc_gpio_pd14_sel_field_t PD14_SEL_f; + }; + union + { + __IO uint32_t PD15_SEL; + stc_gpio_pd15_sel_field_t PD15_SEL_f; + }; + union + { + __IO uint32_t PADIR; + stc_gpio_padir_field_t PADIR_f; + }; + union + { + __IO uint32_t PAIN; + stc_gpio_pain_field_t PAIN_f; + }; + union + { + __IO uint32_t PAOUT; + stc_gpio_paout_field_t PAOUT_f; + }; + union + { + __IO uint32_t PAADS; + stc_gpio_paads_field_t PAADS_f; + }; + union + { + __IO uint32_t PABSET; + stc_gpio_pabset_field_t PABSET_f; + }; + union + { + __IO uint32_t PABCLR; + stc_gpio_pabclr_field_t PABCLR_f; + }; + union + { + __IO uint32_t PABSETCLR; + stc_gpio_pabsetclr_field_t PABSETCLR_f; + }; + union + { + __IO uint32_t PADR; + stc_gpio_padr_field_t PADR_f; + }; + union + { + __IO uint32_t PAPU; + stc_gpio_papu_field_t PAPU_f; + }; + union + { + __IO uint32_t PAPD; + stc_gpio_papd_field_t PAPD_f; + }; + uint8_t RESERVED74[4]; + union + { + __IO uint32_t PAOD; + stc_gpio_paod_field_t PAOD_f; + }; + union + { + __IO uint32_t PAHIE; + stc_gpio_pahie_field_t PAHIE_f; + }; + union + { + __IO uint32_t PALIE; + stc_gpio_palie_field_t PALIE_f; + }; + union + { + __IO uint32_t PARIE; + stc_gpio_parie_field_t PARIE_f; + }; + union + { + __IO uint32_t PAFIE; + stc_gpio_pafie_field_t PAFIE_f; + }; + union + { + __IO uint32_t PBDIR; + stc_gpio_pbdir_field_t PBDIR_f; + }; + union + { + __IO uint32_t PBIN; + stc_gpio_pbin_field_t PBIN_f; + }; + union + { + __IO uint32_t PBOUT; + stc_gpio_pbout_field_t PBOUT_f; + }; + union + { + __IO uint32_t PBADS; + stc_gpio_pbads_field_t PBADS_f; + }; + union + { + __IO uint32_t PBBSET; + stc_gpio_pbbset_field_t PBBSET_f; + }; + union + { + __IO uint32_t PBBCLR; + stc_gpio_pbbclr_field_t PBBCLR_f; + }; + union + { + __IO uint32_t PBBSETCLR; + stc_gpio_pbbsetclr_field_t PBBSETCLR_f; + }; + union + { + __IO uint32_t PBDR; + stc_gpio_pbdr_field_t PBDR_f; + }; + union + { + __IO uint32_t PBPU; + stc_gpio_pbpu_field_t PBPU_f; + }; + union + { + __IO uint32_t PBPD; + stc_gpio_pbpd_field_t PBPD_f; + }; + uint8_t RESERVED89[4]; + union + { + __IO uint32_t PBOD; + stc_gpio_pbod_field_t PBOD_f; + }; + union + { + __IO uint32_t PBHIE; + stc_gpio_pbhie_field_t PBHIE_f; + }; + union + { + __IO uint32_t PBLIE; + stc_gpio_pblie_field_t PBLIE_f; + }; + union + { + __IO uint32_t PBRIE; + stc_gpio_pbrie_field_t PBRIE_f; + }; + union + { + __IO uint32_t PBFIE; + stc_gpio_pbfie_field_t PBFIE_f; + }; + union + { + __IO uint32_t PCDIR; + stc_gpio_pcdir_field_t PCDIR_f; + }; + union + { + __IO uint32_t PCIN; + stc_gpio_pcin_field_t PCIN_f; + }; + union + { + __IO uint32_t PCOUT; + stc_gpio_pcout_field_t PCOUT_f; + }; + union + { + __IO uint32_t PCADS; + stc_gpio_pcads_field_t PCADS_f; + }; + union + { + __IO uint32_t PCBSET; + stc_gpio_pcbset_field_t PCBSET_f; + }; + union + { + __IO uint32_t PCBCLR; + stc_gpio_pcbclr_field_t PCBCLR_f; + }; + union + { + __IO uint32_t PCBSETCLR; + stc_gpio_pcbsetclr_field_t PCBSETCLR_f; + }; + union + { + __IO uint32_t PCDR; + stc_gpio_pcdr_field_t PCDR_f; + }; + union + { + __IO uint32_t PCPU; + stc_gpio_pcpu_field_t PCPU_f; + }; + union + { + __IO uint32_t PCPD; + stc_gpio_pcpd_field_t PCPD_f; + }; + uint8_t RESERVED104[4]; + union + { + __IO uint32_t PCOD; + stc_gpio_pcod_field_t PCOD_f; + }; + union + { + __IO uint32_t PCHIE; + stc_gpio_pchie_field_t PCHIE_f; + }; + union + { + __IO uint32_t PCLIE; + stc_gpio_pclie_field_t PCLIE_f; + }; + union + { + __IO uint32_t PCRIE; + stc_gpio_pcrie_field_t PCRIE_f; + }; + union + { + __IO uint32_t PCFIE; + stc_gpio_pcfie_field_t PCFIE_f; + }; + union + { + __IO uint32_t PDDIR; + stc_gpio_pddir_field_t PDDIR_f; + }; + union + { + __IO uint32_t PDIN; + stc_gpio_pdin_field_t PDIN_f; + }; + union + { + __IO uint32_t PDOUT; + stc_gpio_pdout_field_t PDOUT_f; + }; + union + { + __IO uint32_t PDADS; + stc_gpio_pdads_field_t PDADS_f; + }; + union + { + __IO uint32_t PDBSET; + stc_gpio_pdbset_field_t PDBSET_f; + }; + union + { + __IO uint32_t PDBCLR; + stc_gpio_pdbclr_field_t PDBCLR_f; + }; + union + { + __IO uint32_t PDBSETCLR; + stc_gpio_pdbsetclr_field_t PDBSETCLR_f; + }; + union + { + __IO uint32_t PDDR; + stc_gpio_pddr_field_t PDDR_f; + }; + union + { + __IO uint32_t PDPU; + stc_gpio_pdpu_field_t PDPU_f; + }; + union + { + __IO uint32_t PDPD; + stc_gpio_pdpd_field_t PDPD_f; + }; + uint8_t RESERVED119[4]; + union + { + __IO uint32_t PDOD; + stc_gpio_pdod_field_t PDOD_f; + }; + union + { + __IO uint32_t PDHIE; + stc_gpio_pdhie_field_t PDHIE_f; + }; + union + { + __IO uint32_t PDLIE; + stc_gpio_pdlie_field_t PDLIE_f; + }; + union + { + __IO uint32_t PDRIE; + stc_gpio_pdrie_field_t PDRIE_f; + }; + union + { + __IO uint32_t PDFIE; + stc_gpio_pdfie_field_t PDFIE_f; + }; + union + { + __IO uint32_t PA_STAT; + stc_gpio_pa_stat_field_t PA_STAT_f; + }; + uint8_t RESERVED125[12]; + union + { + __IO uint32_t PA_ICLR; + stc_gpio_pa_iclr_field_t PA_ICLR_f; + }; + uint8_t RESERVED126[44]; + union + { + __IO uint32_t PB_STAT; + stc_gpio_pb_stat_field_t PB_STAT_f; + }; + uint8_t RESERVED127[12]; + union + { + __IO uint32_t PB_ICLR; + stc_gpio_pb_iclr_field_t PB_ICLR_f; + }; + uint8_t RESERVED128[44]; + union + { + __IO uint32_t PC_STAT; + stc_gpio_pc_stat_field_t PC_STAT_f; + }; + uint8_t RESERVED129[12]; + union + { + __IO uint32_t PC_ICLR; + stc_gpio_pc_iclr_field_t PC_ICLR_f; + }; + uint8_t RESERVED130[44]; + union + { + __IO uint32_t PD_STAT; + stc_gpio_pd_stat_field_t PD_STAT_f; + }; + uint8_t RESERVED131[12]; + union + { + __IO uint32_t PD_ICLR; + stc_gpio_pd_iclr_field_t PD_ICLR_f; + }; + uint8_t RESERVED132[44]; + union + { + __IO uint32_t CTRL0; + stc_gpio_ctrl0_field_t CTRL0_f; + }; + union + { + __IO uint32_t CTRL1; + stc_gpio_ctrl1_field_t CTRL1_f; + }; + union + { + __IO uint32_t CTRL2; + stc_gpio_ctrl2_field_t CTRL2_f; + }; + union + { + __IO uint32_t TIMGS; + stc_gpio_timgs_field_t TIMGS_f; + }; + union + { + __IO uint32_t TIMES; + stc_gpio_times_field_t TIMES_f; + }; + union + { + __IO uint32_t TIMCPS; + stc_gpio_timcps_field_t TIMCPS_f; + }; + union + { + __IO uint32_t PCAS; + stc_gpio_pcas_field_t PCAS_f; + }; + union + { + __IO uint32_t PCNT; + stc_gpio_pcnt_field_t PCNT_f; + }; + uint8_t RESERVED140[3296]; + union + { + __IO uint32_t PE00_SEL; + stc_gpio_pe00_sel_field_t PE00_SEL_f; + }; + union + { + __IO uint32_t PE01_SEL; + stc_gpio_pe01_sel_field_t PE01_SEL_f; + }; + union + { + __IO uint32_t PE02_SEL; + stc_gpio_pe02_sel_field_t PE02_SEL_f; + }; + union + { + __IO uint32_t PE03_SEL; + stc_gpio_pe03_sel_field_t PE03_SEL_f; + }; + union + { + __IO uint32_t PE04_SEL; + stc_gpio_pe04_sel_field_t PE04_SEL_f; + }; + union + { + __IO uint32_t PE05_SEL; + stc_gpio_pe05_sel_field_t PE05_SEL_f; + }; + union + { + __IO uint32_t PE06_SEL; + stc_gpio_pe06_sel_field_t PE06_SEL_f; + }; + union + { + __IO uint32_t PE07_SEL; + stc_gpio_pe07_sel_field_t PE07_SEL_f; + }; + union + { + __IO uint32_t PE08_SEL; + stc_gpio_pe08_sel_field_t PE08_SEL_f; + }; + union + { + __IO uint32_t PE09_SEL; + stc_gpio_pe09_sel_field_t PE09_SEL_f; + }; + union + { + __IO uint32_t PE10_SEL; + stc_gpio_pe10_sel_field_t PE10_SEL_f; + }; + union + { + __IO uint32_t PE11_SEL; + stc_gpio_pe11_sel_field_t PE11_SEL_f; + }; + union + { + __IO uint32_t PE12_SEL; + stc_gpio_pe12_sel_field_t PE12_SEL_f; + }; + union + { + __IO uint32_t PE13_SEL; + stc_gpio_pe13_sel_field_t PE13_SEL_f; + }; + union + { + __IO uint32_t PE14_SEL; + stc_gpio_pe14_sel_field_t PE14_SEL_f; + }; + union + { + __IO uint32_t PE15_SEL; + stc_gpio_pe15_sel_field_t PE15_SEL_f; + }; + union + { + __IO uint32_t PF00_SEL; + stc_gpio_pf00_sel_field_t PF00_SEL_f; + }; + union + { + __IO uint32_t PF01_SEL; + stc_gpio_pf01_sel_field_t PF01_SEL_f; + }; + union + { + __IO uint32_t PF02_SEL; + stc_gpio_pf02_sel_field_t PF02_SEL_f; + }; + union + { + __IO uint32_t PF03_SEL; + stc_gpio_pf03_sel_field_t PF03_SEL_f; + }; + union + { + __IO uint32_t PF04_SEL; + stc_gpio_pf04_sel_field_t PF04_SEL_f; + }; + union + { + __IO uint32_t PF05_SEL; + stc_gpio_pf05_sel_field_t PF05_SEL_f; + }; + union + { + __IO uint32_t PF06_SEL; + stc_gpio_pf06_sel_field_t PF06_SEL_f; + }; + union + { + __IO uint32_t PF07_SEL; + stc_gpio_pf07_sel_field_t PF07_SEL_f; + }; + union + { + __IO uint32_t PF08_SEL; + stc_gpio_pf08_sel_field_t PF08_SEL_f; + }; + union + { + __IO uint32_t PF09_SEL; + stc_gpio_pf09_sel_field_t PF09_SEL_f; + }; + union + { + __IO uint32_t PF10_SEL; + stc_gpio_pf10_sel_field_t PF10_SEL_f; + }; + union + { + __IO uint32_t PF11_SEL; + stc_gpio_pf11_sel_field_t PF11_SEL_f; + }; + uint8_t RESERVED168[144]; + union + { + __IO uint32_t PEDIR; + stc_gpio_pedir_field_t PEDIR_f; + }; + union + { + __IO uint32_t PEIN; + stc_gpio_pein_field_t PEIN_f; + }; + union + { + __IO uint32_t PEOUT; + stc_gpio_peout_field_t PEOUT_f; + }; + union + { + __IO uint32_t PEADS; + stc_gpio_peads_field_t PEADS_f; + }; + union + { + __IO uint32_t PEBSET; + stc_gpio_pebset_field_t PEBSET_f; + }; + union + { + __IO uint32_t PEBCLR; + stc_gpio_pebclr_field_t PEBCLR_f; + }; + union + { + __IO uint32_t PEBSETCLR; + stc_gpio_pebsetclr_field_t PEBSETCLR_f; + }; + union + { + __IO uint32_t PEDR; + stc_gpio_pedr_field_t PEDR_f; + }; + union + { + __IO uint32_t PEPU; + stc_gpio_pepu_field_t PEPU_f; + }; + union + { + __IO uint32_t PEPD; + stc_gpio_pepd_field_t PEPD_f; + }; + uint8_t RESERVED178[4]; + union + { + __IO uint32_t PEOD; + stc_gpio_peod_field_t PEOD_f; + }; + union + { + __IO uint32_t PEHIE; + stc_gpio_pehie_field_t PEHIE_f; + }; + union + { + __IO uint32_t PELIE; + stc_gpio_pelie_field_t PELIE_f; + }; + union + { + __IO uint32_t PERIE; + stc_gpio_perie_field_t PERIE_f; + }; + union + { + __IO uint32_t PEFIE; + stc_gpio_pefie_field_t PEFIE_f; + }; + union + { + __IO uint32_t PFDIR; + stc_gpio_pfdir_field_t PFDIR_f; + }; + union + { + __IO uint32_t PFIN; + stc_gpio_pfin_field_t PFIN_f; + }; + union + { + __IO uint32_t PFOUT; + stc_gpio_pfout_field_t PFOUT_f; + }; + union + { + __IO uint32_t PFADS; + stc_gpio_pfads_field_t PFADS_f; + }; + union + { + __IO uint32_t PFBSET; + stc_gpio_pfbset_field_t PFBSET_f; + }; + union + { + __IO uint32_t PFBCLR; + stc_gpio_pfbclr_field_t PFBCLR_f; + }; + union + { + __IO uint32_t PFBSETCLR; + stc_gpio_pfbsetclr_field_t PFBSETCLR_f; + }; + union + { + __IO uint32_t PFDR; + stc_gpio_pfdr_field_t PFDR_f; + }; + union + { + __IO uint32_t PFPU; + stc_gpio_pfpu_field_t PFPU_f; + }; + union + { + __IO uint32_t PFPD; + stc_gpio_pfpd_field_t PFPD_f; + }; + uint8_t RESERVED193[4]; + union + { + __IO uint32_t PFOD; + stc_gpio_pfod_field_t PFOD_f; + }; + union + { + __IO uint32_t PFHIE; + stc_gpio_pfhie_field_t PFHIE_f; + }; + union + { + __IO uint32_t PFLIE; + stc_gpio_pflie_field_t PFLIE_f; + }; + union + { + __IO uint32_t PFRIE; + stc_gpio_pfrie_field_t PFRIE_f; + }; + union + { + __IO uint32_t PFFIE; + stc_gpio_pffie_field_t PFFIE_f; + }; + uint8_t RESERVED198[128]; + union + { + __IO uint32_t PE_STAT; + stc_gpio_pe_stat_field_t PE_STAT_f; + }; + uint8_t RESERVED199[12]; + union + { + __IO uint32_t PE_ICLR; + stc_gpio_pe_iclr_field_t PE_ICLR_f; + }; + uint8_t RESERVED200[44]; + union + { + __IO uint32_t PF_STAT; + stc_gpio_pf_stat_field_t PF_STAT_f; + }; + uint8_t RESERVED201[12]; + union + { + __IO uint32_t PF_ICLR; + stc_gpio_pf_iclr_field_t PF_ICLR_f; + }; +}M0P_GPIO_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t TMRUN; + stc_i2c_tmrun_field_t TMRUN_f; + }; + union + { + __IO uint32_t TM; + stc_i2c_tm_field_t TM_f; + }; + union + { + __IO uint32_t CR; + stc_i2c_cr_field_t CR_f; + }; + union + { + __IO uint32_t DATA; + stc_i2c_data_field_t DATA_f; + }; + union + { + __IO uint32_t ADDR; + stc_i2c_addr_field_t ADDR_f; + }; + union + { + __IO uint32_t STAT; + stc_i2c_stat_field_t STAT_f; + }; +}M0P_I2C_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_lcd_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_lcd_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t INTCLR; + stc_lcd_intclr_field_t INTCLR_f; + }; + union + { + __IO uint32_t POEN0; + stc_lcd_poen0_field_t POEN0_f; + }; + union + { + __IO uint32_t POEN1; + stc_lcd_poen1_field_t POEN1_f; + }; + uint8_t RESERVED5[44]; + union + { + __IO uint32_t RAM0; + stc_lcd_ram0_field_t RAM0_f; + }; + union + { + __IO uint32_t RAM1; + stc_lcd_ram1_field_t RAM1_f; + }; + union + { + __IO uint32_t RAM2; + stc_lcd_ram2_field_t RAM2_f; + }; + union + { + __IO uint32_t RAM3; + stc_lcd_ram3_field_t RAM3_f; + }; + union + { + __IO uint32_t RAM4; + stc_lcd_ram4_field_t RAM4_f; + }; + union + { + __IO uint32_t RAM5; + stc_lcd_ram5_field_t RAM5_f; + }; + union + { + __IO uint32_t RAM6; + stc_lcd_ram6_field_t RAM6_f; + }; + union + { + __IO uint32_t RAM7; + stc_lcd_ram7_field_t RAM7_f; + }; + union + { + __IO uint32_t RAM8; + stc_lcd_ram8_field_t RAM8_f; + }; + union + { + __IO uint32_t RAM9; + stc_lcd_ram9_field_t RAM9_f; + }; + union + { + __IO uint32_t RAMA; + stc_lcd_rama_field_t RAMA_f; + }; + union + { + __IO uint32_t RAMB; + stc_lcd_ramb_field_t RAMB_f; + }; + union + { + __IO uint32_t RAMC; + stc_lcd_ramc_field_t RAMC_f; + }; + union + { + __IO uint32_t RAMD; + stc_lcd_ramd_field_t RAMD_f; + }; + union + { + __IO uint32_t RAME; + stc_lcd_rame_field_t RAME_f; + }; + union + { + __IO uint32_t RAMF; + stc_lcd_ramf_field_t RAMF_f; + }; +}M0P_LCD_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNT; + stc_lptimer_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t ARR; + stc_lptimer_arr_field_t ARR_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t CR; + stc_lptimer_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_lptimer_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_lptimer_iclr_field_t ICLR_f; + }; +}M0P_LPTIMER_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SBUF; + stc_lpuart_sbuf_field_t SBUF_f; + }; + union + { + __IO uint32_t SCON; + stc_lpuart_scon_field_t SCON_f; + }; + union + { + __IO uint32_t SADDR; + stc_lpuart_saddr_field_t SADDR_f; + }; + union + { + __IO uint32_t SADEN; + stc_lpuart_saden_field_t SADEN_f; + }; + union + { + __IO uint32_t ISR; + stc_lpuart_isr_field_t ISR_f; + }; + union + { + __IO uint32_t ICR; + stc_lpuart_icr_field_t ICR_f; + }; + union + { + __IO uint32_t SCNT; + stc_lpuart_scnt_field_t SCNT_f; + }; +}M0P_LPUART_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[40]; + union + { + __IO uint32_t CR; + stc_lvd_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_lvd_ifr_field_t IFR_f; + }; +}M0P_LVD_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[48]; + union + { + __IO uint32_t CR0; + stc_opa_cr0_field_t CR0_f; + }; + uint8_t RESERVED1[8]; + union + { + __IO uint32_t CR1; + stc_opa_cr1_field_t CR1_f; + }; +}M0P_OPA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CCON; + stc_pca_ccon_field_t CCON_f; + }; + union + { + __IO uint32_t CMOD; + stc_pca_cmod_field_t CMOD_f; + }; + union + { + __IO uint32_t CNT; + stc_pca_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t ICLR; + stc_pca_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CCAPM0; + stc_pca_ccapm0_field_t CCAPM0_f; + }; + union + { + __IO uint32_t CCAPM1; + stc_pca_ccapm1_field_t CCAPM1_f; + }; + union + { + __IO uint32_t CCAPM2; + stc_pca_ccapm2_field_t CCAPM2_f; + }; + union + { + __IO uint32_t CCAPM3; + stc_pca_ccapm3_field_t CCAPM3_f; + }; + union + { + __IO uint32_t CCAPM4; + stc_pca_ccapm4_field_t CCAPM4_f; + }; + union + { + __IO uint32_t CCAP0H; + stc_pca_ccap0h_field_t CCAP0H_f; + }; + union + { + __IO uint32_t CCAP0L; + stc_pca_ccap0l_field_t CCAP0L_f; + }; + union + { + __IO uint32_t CCAP1H; + stc_pca_ccap1h_field_t CCAP1H_f; + }; + union + { + __IO uint32_t CCAP1L; + stc_pca_ccap1l_field_t CCAP1L_f; + }; + union + { + __IO uint32_t CCAP2H; + stc_pca_ccap2h_field_t CCAP2H_f; + }; + union + { + __IO uint32_t CCAP2L; + stc_pca_ccap2l_field_t CCAP2L_f; + }; + union + { + __IO uint32_t CCAP3H; + stc_pca_ccap3h_field_t CCAP3H_f; + }; + union + { + __IO uint32_t CCAP3L; + stc_pca_ccap3l_field_t CCAP3L_f; + }; + union + { + __IO uint32_t CCAP4H; + stc_pca_ccap4h_field_t CCAP4H_f; + }; + union + { + __IO uint32_t CCAP4L; + stc_pca_ccap4l_field_t CCAP4L_f; + }; + union + { + __IO uint32_t CCAPO; + stc_pca_ccapo_field_t CCAPO_f; + }; + union + { + __IO uint32_t CCAP0; + stc_pca_ccap0_field_t CCAP0_f; + }; + union + { + __IO uint32_t CCAP1; + stc_pca_ccap1_field_t CCAP1_f; + }; + union + { + __IO uint32_t CCAP2; + stc_pca_ccap2_field_t CCAP2_f; + }; + union + { + __IO uint32_t CCAP3; + stc_pca_ccap3_field_t CCAP3_f; + }; + union + { + __IO uint32_t CCAP4; + stc_pca_ccap4_field_t CCAP4_f; + }; + union + { + __IO uint32_t CARR; + stc_pca_carr_field_t CARR_f; + }; + union + { + __IO uint32_t EPWM; + stc_pca_epwm_field_t EPWM_f; + }; +}M0P_PCA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RUN; + stc_pcnt_run_field_t RUN_f; + }; + union + { + __IO uint32_t CTRL; + stc_pcnt_ctrl_field_t CTRL_f; + }; + union + { + __IO uint32_t FLT; + stc_pcnt_flt_field_t FLT_f; + }; + union + { + __IO uint32_t TOCR; + stc_pcnt_tocr_field_t TOCR_f; + }; + union + { + __IO uint32_t CMD; + stc_pcnt_cmd_field_t CMD_f; + }; + union + { + __IO uint32_t SR1; + stc_pcnt_sr1_field_t SR1_f; + }; + union + { + __IO uint32_t CNT; + stc_pcnt_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t TOP; + stc_pcnt_top_field_t TOP_f; + }; + union + { + __IO uint32_t BUF; + stc_pcnt_buf_field_t BUF_f; + }; + union + { + __IO uint32_t IFR; + stc_pcnt_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICR; + stc_pcnt_icr_field_t ICR_f; + }; + union + { + __IO uint32_t IEN; + stc_pcnt_ien_field_t IEN_f; + }; + union + { + __IO uint32_t SR2; + stc_pcnt_sr2_field_t SR2_f; + }; + union + { + __IO uint32_t DBG; + stc_pcnt_dbg_field_t DBG_f; + }; +}M0P_PCNT_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_ram_cr_field_t CR_f; + }; + union + { + __IO uint32_t ERRADDR; + stc_ram_erraddr_field_t ERRADDR_f; + }; + union + { + __IO uint32_t IFR; + stc_ram_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_ram_iclr_field_t ICLR_f; + }; +}M0P_RAM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RESET_FLAG; + stc_reset_flag_field_t RESET_FLAG_f; + }; + uint8_t RESERVED1[8]; + union + { + __IO uint32_t PERI_RESET0; + stc_reset_peri_reset0_field_t PERI_RESET0_f; + }; + union + { + __IO uint32_t PERI_RESET1; + stc_reset_peri_reset1_field_t PERI_RESET1_f; + }; +}M0P_RESET_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_rtc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_rtc_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t SEC; + stc_rtc_sec_field_t SEC_f; + }; + union + { + __IO uint32_t MIN; + stc_rtc_min_field_t MIN_f; + }; + union + { + __IO uint32_t HOUR; + stc_rtc_hour_field_t HOUR_f; + }; + union + { + __IO uint32_t WEEK; + stc_rtc_week_field_t WEEK_f; + }; + union + { + __IO uint32_t DAY; + stc_rtc_day_field_t DAY_f; + }; + union + { + __IO uint32_t MON; + stc_rtc_mon_field_t MON_f; + }; + union + { + __IO uint32_t YEAR; + stc_rtc_year_field_t YEAR_f; + }; + union + { + __IO uint32_t ALMMIN; + stc_rtc_almmin_field_t ALMMIN_f; + }; + union + { + __IO uint32_t ALMHOUR; + stc_rtc_almhour_field_t ALMHOUR_f; + }; + union + { + __IO uint32_t ALMWEEK; + stc_rtc_almweek_field_t ALMWEEK_f; + }; + union + { + __IO uint32_t COMPEN; + stc_rtc_compen_field_t COMPEN_f; + }; + union + { + __IO uint32_t ALMSEC; + stc_rtc_almsec_field_t ALMSEC_f; + }; +}M0P_RTC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_spi_cr_field_t CR_f; + }; + union + { + __IO uint32_t SSN; + stc_spi_ssn_field_t SSN_f; + }; + union + { + __IO uint32_t STAT; + stc_spi_stat_field_t STAT_f; + }; + union + { + __IO uint32_t DATA; + stc_spi_data_field_t DATA_f; + }; + union + { + __IO uint32_t CR2; + stc_spi_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t ICLR; + stc_spi_iclr_field_t ICLR_f; + }; +}M0P_SPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SYSCTRL0; + stc_sysctrl_sysctrl0_field_t SYSCTRL0_f; + }; + union + { + __IO uint32_t SYSCTRL1; + stc_sysctrl_sysctrl1_field_t SYSCTRL1_f; + }; + union + { + __IO uint32_t SYSCTRL2; + stc_sysctrl_sysctrl2_field_t SYSCTRL2_f; + }; + union + { + __IO uint32_t RCH_CR; + stc_sysctrl_rch_cr_field_t RCH_CR_f; + }; + union + { + __IO uint32_t XTH_CR; + stc_sysctrl_xth_cr_field_t XTH_CR_f; + }; + union + { + __IO uint32_t RCL_CR; + stc_sysctrl_rcl_cr_field_t RCL_CR_f; + }; + union + { + __IO uint32_t XTL_CR; + stc_sysctrl_xtl_cr_field_t XTL_CR_f; + }; + uint8_t RESERVED7[4]; + union + { + __IO uint32_t PERI_CLKEN0; + stc_sysctrl_peri_clken0_field_t PERI_CLKEN0_f; + }; + union + { + __IO uint32_t PERI_CLKEN1; + stc_sysctrl_peri_clken1_field_t PERI_CLKEN1_f; + }; + uint8_t RESERVED9[20]; + union + { + __IO uint32_t PLL_CR; + stc_sysctrl_pll_cr_field_t PLL_CR_f; + }; +}M0P_SYSCTRL_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim0_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim0_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim0_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim0_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim0_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM0_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim0_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim0_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim0_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim0_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim0_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim0_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM0_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim0_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim0_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim0_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim0_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim0_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim0_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim0_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim0_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim0_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim0_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim0_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim0_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM0_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim1_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim1_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim1_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim1_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim1_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM1_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim1_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim1_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim1_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim1_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim1_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim1_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM1_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim1_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim1_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim1_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim1_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim1_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim1_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim1_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim1_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim1_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim1_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim1_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim1_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM1_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim2_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim2_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim2_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim2_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim2_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM2_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim2_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim2_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim2_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim2_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim2_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim2_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM2_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim2_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim2_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim2_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim2_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim2_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim2_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim2_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim2_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim2_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim2_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim2_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim2_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM2_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim3_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim3_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim3_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim3_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim3_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM3_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim3_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim3_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim3_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim3_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim3_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim3_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM3_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim3_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim3_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim3_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim3_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim3_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim3_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim3_mode23_crch0_field_t CRCH0_f; + }; + union + { + __IO uint32_t CRCH1; + stc_tim3_mode23_crch1_field_t CRCH1_f; + }; + union + { + __IO uint32_t CRCH2; + stc_tim3_mode23_crch2_field_t CRCH2_f; + }; + union + { + __IO uint32_t DTR; + stc_tim3_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim3_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim3_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim3_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim3_mode23_ccr0b_field_t CCR0B_f; + }; + union + { + __IO uint32_t CCR1A; + stc_tim3_mode23_ccr1a_field_t CCR1A_f; + }; + union + { + __IO uint32_t CCR1B; + stc_tim3_mode23_ccr1b_field_t CCR1B_f; + }; + union + { + __IO uint32_t CCR2A; + stc_tim3_mode23_ccr2a_field_t CCR2A_f; + }; + union + { + __IO uint32_t CCR2B; + stc_tim3_mode23_ccr2b_field_t CCR2B_f; + }; +}M0P_TIM3_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_trng_cr_field_t CR_f; + }; + union + { + __IO uint32_t MODE; + stc_trng_mode_field_t MODE_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t DATA0; + stc_trng_data0_field_t DATA0_f; + }; + union + { + __IO uint32_t DATA1; + stc_trng_data1_field_t DATA1_f; + }; +}M0P_TRNG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SBUF; + stc_uart_sbuf_field_t SBUF_f; + }; + union + { + __IO uint32_t SCON; + stc_uart_scon_field_t SCON_f; + }; + union + { + __IO uint32_t SADDR; + stc_uart_saddr_field_t SADDR_f; + }; + union + { + __IO uint32_t SADEN; + stc_uart_saden_field_t SADEN_f; + }; + union + { + __IO uint32_t ISR; + stc_uart_isr_field_t ISR_f; + }; + union + { + __IO uint32_t ICR; + stc_uart_icr_field_t ICR_f; + }; + union + { + __IO uint32_t SCNT; + stc_uart_scnt_field_t SCNT_f; + }; +}M0P_UART_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[16]; + union + { + __IO uint32_t CR; + stc_vc_cr_field_t CR_f; + }; + union + { + __IO uint32_t VC0_CR; + stc_vc_vc0_cr_field_t VC0_CR_f; + }; + union + { + __IO uint32_t VC1_CR; + stc_vc_vc1_cr_field_t VC1_CR_f; + }; + union + { + __IO uint32_t VC0_OUT_CFG; + stc_vc_vc0_out_cfg_field_t VC0_OUT_CFG_f; + }; + union + { + __IO uint32_t VC1_OUT_CFG; + stc_vc_vc1_out_cfg_field_t VC1_OUT_CFG_f; + }; + union + { + __IO uint32_t IFR; + stc_vc_ifr_field_t IFR_f; + }; + uint8_t RESERVED6[296]; + union + { + __IO uint32_t VC2_CR; + stc_vc_vc2_cr_field_t VC2_CR_f; + }; + union + { + __IO uint32_t VC2_OUT_CFG; + stc_vc_vc2_out_cfg_field_t VC2_OUT_CFG_f; + }; +}M0P_VC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[128]; + union + { + __IO uint32_t RST; + stc_wdt_rst_field_t RST_f; + }; + union + { + __IO uint32_t CON; + stc_wdt_con_field_t CON_f; + }; +}M0P_WDT_TypeDef; + + + +#define M0P_PERIPH_BASE (0x40000000UL) +#define M0P_ADC_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_ADTIM4_BASE (M0P_PERIPH_BASE + 0x00003000UL) +#define M0P_ADTIM5_BASE (M0P_PERIPH_BASE + 0x00003400UL) +#define M0P_ADTIM6_BASE (M0P_PERIPH_BASE + 0x00003800UL) +#define M0P_AES_BASE (M0P_PERIPH_BASE + 0x00021400UL) +#define M0P_BGR_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_CLK_TRIM_BASE (M0P_PERIPH_BASE + 0x00001800UL) +#define M0P_CRC_BASE (M0P_PERIPH_BASE + 0x00020900UL) +#define M0P_DAC_BASE (M0P_PERIPH_BASE + 0x00002500UL) +#define M0P_DEBUG_ACTIVE_BASE (M0P_PERIPH_BASE + 0x00002038UL) +#define M0P_DMAC_BASE (M0P_PERIPH_BASE + 0x00021000UL) +#define M0P_FLASH_BASE (M0P_PERIPH_BASE + 0x00020000UL) +#define M0P_GPIO_BASE (M0P_PERIPH_BASE + 0x00020C00UL) +#define M0P_I2C0_BASE (M0P_PERIPH_BASE + 0x00000400UL) +#define M0P_I2C1_BASE (M0P_PERIPH_BASE + 0x00004400UL) +#define M0P_LCD_BASE (M0P_PERIPH_BASE + 0x00005C00UL) +#define M0P_LPTIMER0_BASE (M0P_PERIPH_BASE + 0x00000F00UL) +#define M0P_LPTIMER1_BASE (M0P_PERIPH_BASE + 0x00000F40UL) +#define M0P_LPUART0_BASE (M0P_PERIPH_BASE + 0x00000200UL) +#define M0P_LPUART1_BASE (M0P_PERIPH_BASE + 0x00004000UL) +#define M0P_LVD_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_OPA_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_PCA_BASE (M0P_PERIPH_BASE + 0x00001000UL) +#define M0P_PCNT_BASE (M0P_PERIPH_BASE + 0x00005400UL) +#define M0P_RAM_BASE (M0P_PERIPH_BASE + 0x00020400UL) +#define M0P_RESET_BASE (M0P_PERIPH_BASE + 0x0000201CUL) +#define M0P_RTC_BASE (M0P_PERIPH_BASE + 0x00001400UL) +#define M0P_SPI0_BASE (M0P_PERIPH_BASE + 0x00000800UL) +#define M0P_SPI1_BASE (M0P_PERIPH_BASE + 0x00004800UL) +#define M0P_SYSCTRL_BASE (M0P_PERIPH_BASE + 0x00002000UL) +#define M0P_TIM0_MODE0_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM0_MODE1_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM0_MODE23_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM1_MODE0_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM1_MODE1_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM1_MODE23_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM2_MODE0_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM2_MODE1_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM2_MODE23_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM3_MODE0_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM3_MODE1_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM3_MODE23_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TRNG_BASE (M0P_PERIPH_BASE + 0x00004C00UL) +#define M0P_UART0_BASE (M0P_PERIPH_BASE + 0x00000000UL) +#define M0P_UART1_BASE (M0P_PERIPH_BASE + 0x00000100UL) +#define M0P_UART2_BASE (M0P_PERIPH_BASE + 0x00006000UL) +#define M0P_UART3_BASE (M0P_PERIPH_BASE + 0x00006400UL) +#define M0P_VC_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_WDT_BASE (M0P_PERIPH_BASE + 0x00000F00UL) + + +#define M0P_ADC ((M0P_ADC_TypeDef *)0x40002400UL) +#define M0P_ADTIM4 ((M0P_ADTIM_TypeDef *)0x40003000UL) +#define M0P_ADTIM5 ((M0P_ADTIM_TypeDef *)0x40003400UL) +#define M0P_ADTIM6 ((M0P_ADTIM_TypeDef *)0x40003800UL) +#define M0P_AES ((M0P_AES_TypeDef *)0x40021400UL) +#define M0P_BGR ((M0P_BGR_TypeDef *)0x40002400UL) +#define M0P_CLK_TRIM ((M0P_CLK_TRIM_TypeDef *)0x40001800UL) +#define M0P_CRC ((M0P_CRC_TypeDef *)0x40020900UL) +#define M0P_DAC ((M0P_DAC_TypeDef *)0x40002500UL) +#define M0P_DEBUG_ACTIVE ((M0P_DEBUG_ACTIVE_TypeDef *)0x40002038UL) +#define M0P_DMAC ((M0P_DMAC_TypeDef *)0x40021000UL) +#define M0P_FLASH ((M0P_FLASH_TypeDef *)0x40020000UL) +#define M0P_GPIO ((M0P_GPIO_TypeDef *)0x40020C00UL) +#define M0P_I2C0 ((M0P_I2C_TypeDef *)0x40000400UL) +#define M0P_I2C1 ((M0P_I2C_TypeDef *)0x40004400UL) +#define M0P_LCD ((M0P_LCD_TypeDef *)0x40005C00UL) +#define M0P_LPTIMER0 ((M0P_LPTIMER_TypeDef *)0x40000F00UL) +#define M0P_LPTIMER1 ((M0P_LPTIMER_TypeDef *)0x40000F40UL) +#define M0P_LPUART0 ((M0P_LPUART_TypeDef *)0x40000200UL) +#define M0P_LPUART1 ((M0P_LPUART_TypeDef *)0x40004000UL) +#define M0P_LVD ((M0P_LVD_TypeDef *)0x40002400UL) +#define M0P_OPA ((M0P_OPA_TypeDef *)0x40002400UL) +#define M0P_PCA ((M0P_PCA_TypeDef *)0x40001000UL) +#define M0P_PCNT ((M0P_PCNT_TypeDef *)0x40005400UL) +#define M0P_RAM ((M0P_RAM_TypeDef *)0x40020400UL) +#define M0P_RESET ((M0P_RESET_TypeDef *)0x4000201CUL) +#define M0P_RTC ((M0P_RTC_TypeDef *)0x40001400UL) +#define M0P_SPI0 ((M0P_SPI_TypeDef *)0x40000800UL) +#define M0P_SPI1 ((M0P_SPI_TypeDef *)0x40004800UL) +#define M0P_SYSCTRL ((M0P_SYSCTRL_TypeDef *)0x40002000UL) +#define M0P_TIM0_MODE0 ((M0P_TIM0_MODE0_TypeDef *)0x40000C00UL) +#define M0P_TIM0_MODE1 ((M0P_TIM0_MODE1_TypeDef *)0x40000C00UL) +#define M0P_TIM0_MODE23 ((M0P_TIM0_MODE23_TypeDef *)0x40000C00UL) +#define M0P_TIM1_MODE0 ((M0P_TIM1_MODE0_TypeDef *)0x40000D00UL) +#define M0P_TIM1_MODE1 ((M0P_TIM1_MODE1_TypeDef *)0x40000D00UL) +#define M0P_TIM1_MODE23 ((M0P_TIM1_MODE23_TypeDef *)0x40000D00UL) +#define M0P_TIM2_MODE0 ((M0P_TIM2_MODE0_TypeDef *)0x40000E00UL) +#define M0P_TIM2_MODE1 ((M0P_TIM2_MODE1_TypeDef *)0x40000E00UL) +#define M0P_TIM2_MODE23 ((M0P_TIM2_MODE23_TypeDef *)0x40000E00UL) +#define M0P_TIM3_MODE0 ((M0P_TIM3_MODE0_TypeDef *)0x40005800UL) +#define M0P_TIM3_MODE1 ((M0P_TIM3_MODE1_TypeDef *)0x40005800UL) +#define M0P_TIM3_MODE23 ((M0P_TIM3_MODE23_TypeDef *)0x40005800UL) +#define M0P_TRNG ((M0P_TRNG_TypeDef *)0x40004C00UL) +#define M0P_UART0 ((M0P_UART_TypeDef *)0x40000000UL) +#define M0P_UART1 ((M0P_UART_TypeDef *)0x40000100UL) +#define M0P_UART2 ((M0P_UART_TypeDef *)0x40006000UL) +#define M0P_UART3 ((M0P_UART_TypeDef *)0x40006400UL) +#define M0P_VC ((M0P_VC_TypeDef *)0x40002400UL) +#define M0P_WDT ((M0P_WDT_TypeDef *)0x40000F00UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32L19X_H__ */ + diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/interrupts_hc32l19x.h b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/interrupts_hc32l19x.h new file mode 100644 index 0000000000..da5759c311 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/interrupts_hc32l19x.h @@ -0,0 +1,150 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file interrupts_hc32l17x.h + ** + ** Interrupt common define. + ** @link IRQGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ +#ifndef __INTERRUPTS_HC32L17x_H__ +#define __INTERRUPTS_HC32L17x_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "hc32l196_ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define DDL_IRQ_LEVEL_DEFAULT 3u + +//<<此选项会打开interrupt_hc32xxx.c中的中断回调函数，用户如果需要实现中断服务函数， +//<<可在源码文件中定义该文件中用"__WEAK"声明的同名中断服务函数即可。 +#define INT_CALLBACK_ON 1u //<<(默认值) +//<<此选项会关闭interrupt_hc32xxx.c中的中断回调函数，此时用户可在该文件中自行定义中断服务函数的实现。 +#define INT_CALLBACK_OFF 0u +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define INT_CALLBACK_PORTA INT_CALLBACK_ON +#define INT_CALLBACK_PORTB INT_CALLBACK_ON +#define INT_CALLBACK_PORTC INT_CALLBACK_ON +#define INT_CALLBACK_PORTD INT_CALLBACK_ON +#define INT_CALLBACK_PORTE INT_CALLBACK_ON +#define INT_CALLBACK_PORTF INT_CALLBACK_ON +#define INT_CALLBACK_DMAC INT_CALLBACK_ON +#define INT_CALLBACK_TIM3 INT_CALLBACK_ON +#define INT_CALLBACK_UART0 INT_CALLBACK_ON +#define INT_CALLBACK_UART1 INT_CALLBACK_ON +#define INT_CALLBACK_UART2 INT_CALLBACK_ON +#define INT_CALLBACK_UART3 INT_CALLBACK_ON +#define INT_CALLBACK_LPUART0 INT_CALLBACK_ON +#define INT_CALLBACK_LPUART1 INT_CALLBACK_ON +#define INT_CALLBACK_SPI0 INT_CALLBACK_ON +#define INT_CALLBACK_SPI1 INT_CALLBACK_ON +#define INT_CALLBACK_I2C0 INT_CALLBACK_ON +#define INT_CALLBACK_I2C1 INT_CALLBACK_ON +#define INT_CALLBACK_TIM0 INT_CALLBACK_ON +#define INT_CALLBACK_TIM1 INT_CALLBACK_ON +#define INT_CALLBACK_TIM2 INT_CALLBACK_ON +#define INT_CALLBACK_LPTIM0 INT_CALLBACK_ON +#define INT_CALLBACK_LPTIM1 INT_CALLBACK_ON +#define INT_CALLBACK_TIM4 INT_CALLBACK_ON +#define INT_CALLBACK_TIM5 INT_CALLBACK_ON +#define INT_CALLBACK_TIM6 INT_CALLBACK_ON +#define INT_CALLBACK_PCA INT_CALLBACK_ON +#define INT_CALLBACK_WDT INT_CALLBACK_ON +#define INT_CALLBACK_RTC INT_CALLBACK_ON +#define INT_CALLBACK_ADC INT_CALLBACK_ON +#define INT_CALLBACK_DAC INT_CALLBACK_ON +#define INT_CALLBACK_PCNT INT_CALLBACK_ON +#define INT_CALLBACK_VC0 INT_CALLBACK_ON +#define INT_CALLBACK_VC1 INT_CALLBACK_ON +#define INT_CALLBACK_VC2 INT_CALLBACK_ON +#define INT_CALLBACK_LVD INT_CALLBACK_ON +#define INT_CALLBACK_LCD INT_CALLBACK_ON +#define INT_CALLBACK_FLASH INT_CALLBACK_ON +#define INT_CALLBACK_RAM INT_CALLBACK_ON +#define INT_CALLBACK_CLKTRIM INT_CALLBACK_ON + + +/** + ******************************************************************************* + ** \brief 中断优先级数据类型定义 + ** \note + ******************************************************************************/ +typedef enum en_irq_level +{ + IrqLevel0 = 0u, ///< 优先级0 + IrqLevel1 = 1u, ///< 优先级1 + IrqLevel2 = 2u, ///< 优先级2 + IrqLevel3 = 3u, ///< 优先级3 +} en_irq_level_t; + + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +///< 系统中断使能开关 +extern void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn); + + +#ifdef __cplusplus +} +#endif + + +#endif /* __INTERRUPTS_HC32L19x_H__ */ + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/system_hc32l19x.h b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/system_hc32l19x.h new file mode 100644 index 0000000000..bd61c1bd11 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Include/system_hc32l19x.h @@ -0,0 +1,115 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l19x.h + ** + ** A detailed description is available at + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __SYSTEM_HC32L19X_H__ +#define __SYSTEM_HC32L19X_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + +#define HC32L19xPxxx //100PIN +//#define HC32L19xMxxx //80PIN +//#define HC32L19xKxxx //64PIN +//#define HC32L19xJxxx //48PIN +//#define HC32L19xFxxx //32PIN + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32L19X _H__ */ + + + + + + + diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/ARM/startup_hc32l19x.s b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/ARM/startup_hc32l19x.s new file mode 100644 index 0000000000..5a102fcf15 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/ARM/startup_hc32l19x.s @@ -0,0 +1,298 @@ +;/****************************************************************************** +;* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +;* +;* This software is owned and published by: +;* Huada Semiconductor Co.,Ltd ("HDSC"). +;* +;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +;* +;* This software contains source code for use with HDSC +;* components. This software is licensed by HDSC to be adapted only +;* for use in systems utilizing HDSC components. HDSC shall not be +;* responsible for misuse or illegal use of this software for devices not +;* supported herein. HDSC is providing this software "AS IS" and will +;* not be responsible for issues arising from incorrect user implementation +;* of the software. +;* +;* Disclaimer: +;* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +;* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +;* WARRANTY OF NONINFRINGEMENT. +;* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +;* SAVINGS OR PROFITS, +;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +;* FROM, THE SOFTWARE. +;* +;* This software may be replicated in part or whole for the licensed use, +;* with the restriction that this Disclaimer and Copyright notice must be +;* included with each copy of this software, whether used in part or whole, +;* at all times. +;*/ +;/*****************************************************************************/ + +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2019-03-01 */ +;/* Target-mcu {MCU_PN_H} */ +;/*****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + + DCD PORTA_IRQHandler + DCD PORTB_IRQHandler + DCD PORTC_E_IRQHandler + DCD PORTD_F_IRQHandler + DCD DMAC_IRQHandler + DCD TIM3_IRQHandler + DCD UART0_2_IRQHandler + DCD UART1_3_IRQHandler + DCD LPUART0_IRQHandler + DCD LPUART1_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD I2C0_IRQHandler + DCD I2C1_IRQHandler + DCD TIM0_IRQHandler + DCD TIM1_IRQHandler + DCD TIM2_IRQHandler + DCD LPTIM0_1_IRQHandler + DCD TIM4_IRQHandler + DCD TIM5_IRQHandler + DCD TIM6_IRQHandler + DCD PCA_IRQHandler + DCD WDT_IRQHandler + DCD RTC_IRQHandler + DCD ADC_DAC_IRQHandler + DCD PCNT_IRQHandler + DCD VC0_IRQHandler + DCD VC1_2_IRQHandler + DCD LVD_IRQHandler + DCD LCD_IRQHandler + DCD FLASH_RAM_IRQHandler + DCD CLKTRIM_IRQHandler + + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ;reset NVIC if in rom debug + LDR R0, =0x20000000 + LDR R2, =0x0 + MOVS R1, #0 ; for warning, + ADD R1, PC,#0 ; for A1609W, + CMP R1, R0 + BLS RAMCODE + + ; ram code base address. + ADD R2, R0,R2 +RAMCODE + ; reset Vector table address. + LDR R0, =0xE000ED08 + STR R2, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_E_IRQHandler [WEAK] + EXPORT PORTD_F_IRQHandler [WEAK] + EXPORT DMAC_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT UART0_2_IRQHandler [WEAK] + EXPORT UART1_3_IRQHandler [WEAK] + EXPORT LPUART0_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM1_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT LPTIM0_1_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT PCA_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT ADC_DAC_IRQHandler [WEAK] + EXPORT PCNT_IRQHandler [WEAK] + EXPORT VC0_IRQHandler [WEAK] + EXPORT VC1_2_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT FLASH_RAM_IRQHandler [WEAK] + EXPORT CLKTRIM_IRQHandler [WEAK] +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_E_IRQHandler +PORTD_F_IRQHandler +DMAC_IRQHandler +TIM3_IRQHandler +UART0_2_IRQHandler +UART1_3_IRQHandler +LPUART0_IRQHandler +LPUART1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +TIM0_IRQHandler +TIM1_IRQHandler +TIM2_IRQHandler +LPTIM0_1_IRQHandler +TIM4_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +PCA_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +ADC_DAC_IRQHandler +PCNT_IRQHandler +VC0_IRQHandler +VC1_2_IRQHandler +LVD_IRQHandler +LCD_IRQHandler +FLASH_RAM_IRQHandler +CLKTRIM_IRQHandler + + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/GCC/startup_hc32l19x.s b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/GCC/startup_hc32l19x.s new file mode 100644 index 0000000000..60ba02bc55 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/GCC/startup_hc32l19x.s @@ -0,0 +1,167 @@ + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ +/* bl __libc_init_array */ +/* Call the application's entry point.*/ + bl entry + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word PORTA_IRQHandler + .word PORTB_IRQHandler + .word PORTC_E_IRQHandler + .word PORTD_F_IRQHandler + .word DMAC_IRQHandler + .word TIM3_IRQHandler + .word UART0_2_IRQHandler + .word UART1_3_IRQHandler + .word LPUART0_IRQHandler + .word LPUART1_IRQHandler + .word SPI0_IRQHandler + .word SPI1_IRQHandler + .word I2C0_IRQHandler + .word I2C1_IRQHandler + .word TIM0_IRQHandler + .word TIM1_IRQHandler + .word TIM2_IRQHandler + .word LPTIM0_1_IRQHandler + .word TIM4_IRQHandler + .word TIM5_IRQHandler + .word TIM6_IRQHandler + .word PCA_IRQHandler + .word WDT_IRQHandler + .word RTC_IRQHandler + .word ADC_DAC_IRQHandler + .word PCNT_IRQHandler + .word VC0_IRQHandler + .word VC1_2_IRQHandler + .word LVD_IRQHandler + .word LCD_IRQHandler + .word FLASH_RAM_IRQHandler + .word CLKTRIM_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/IAR/startup_hc32l19x.s b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/IAR/startup_hc32l19x.s new file mode 100644 index 0000000000..9088c8f452 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/IAR/startup_hc32l19x.s @@ -0,0 +1,361 @@ +;******************************************************************************* +; Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +; +; This software is owned and published by: +; Huada Semiconductor Co.,Ltd ("HDSC"). +; +; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +; +; This software contains source code for use with HDSC +; components. This software is licensed by HDSC to be adapted only +; for use in systems utilizing HDSC components. HDSC shall not be +; responsible for misuse or illegal use of this software for devices not +; supported herein. HDSC is providing this software "AS IS" and will +; not be responsible for issues arising from incorrect user implementation +; of the software. +; +; Disclaimer: +; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +; WARRANTY OF NONINFRINGEMENT. +; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +; SAVINGS OR PROFITS, +; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +; FROM, THE SOFTWARE. +; +; This software may be replicated in part or whole for the licensed use, +; with the restriction that this Disclaimer and Copyright notice must be +; included with each copy of this software, whether used in part or whole, +; at all times. +;/ +;/*****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2019-03-01 */ +;/* Target-mcu M0+ Device */ +;/*****************************************************************************/ + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + SECTION .intvec:CODE:ROOT(8) + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + +; Numbered IRQ handler vectors + +; Note: renaming to device dependent ISR function names are done in + + DCD PORTA_IRQHandler + DCD PORTB_IRQHandler + DCD PORTC_E_IRQHandler + DCD PORTD_F_IRQHandler + DCD DMAC_IRQHandler + DCD TIM3_IRQHandler + DCD UART0_2_IRQHandler + DCD UART1_3_IRQHandler + DCD LPUART0_IRQHandler + DCD LPUART1_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD I2C0_IRQHandler + DCD I2C1_IRQHandler + DCD TIM0_IRQHandler + DCD TIM1_IRQHandler + DCD TIM2_IRQHandler + DCD LPTIM0_1_IRQHandler + DCD TIM4_IRQHandler + DCD TIM5_IRQHandler + DCD TIM6_IRQHandler + DCD PCA_IRQHandler + DCD WDT_IRQHandler + DCD RTC_IRQHandler + DCD ADC_DAC_IRQHandler + DCD PCNT_IRQHandler + DCD VC0_IRQHandler + DCD VC1_2_IRQHandler + DCD LVD_IRQHandler + DCD LCD_IRQHandler + DCD FLASH_RAM_IRQHandler + DCD CLKTRIM_IRQHandler + + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ;reset NVIC if in rom debug + LDR R0, =0x20000000 + LDR R2, =0x0 ; vector offset + cmp PC, R0 + bls ROMCODE + + ; ram code base address. + ADD R2, R0,R2 +ROMCODE + ; reset Vector table address. + LDR R0, =0xE000ED08 + STR R2, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK PORTA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PORTA_IRQHandler + B PORTA_IRQHandler + + + PUBWEAK PORTB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PORTB_IRQHandler + B PORTB_IRQHandler + + + PUBWEAK PORTC_E_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PORTC_E_IRQHandler + B PORTC_E_IRQHandler + + + PUBWEAK PORTD_F_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PORTD_F_IRQHandler + B PORTD_F_IRQHandler + + + PUBWEAK DMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAC_IRQHandler + B DMAC_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK UART0_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_2_IRQHandler + B UART0_2_IRQHandler + + + PUBWEAK UART1_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_3_IRQHandler + B UART1_3_IRQHandler + + + PUBWEAK LPUART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART0_IRQHandler + B LPUART0_IRQHandler + + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK TIM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM0_IRQHandler + B TIM0_IRQHandler + + + PUBWEAK TIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_IRQHandler + B TIM1_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK LPTIM0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM0_1_IRQHandler + B LPTIM0_1_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK PCA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PCA_IRQHandler + B PCA_IRQHandler + + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK ADC_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_DAC_IRQHandler + B ADC_DAC_IRQHandler + + + PUBWEAK PCNT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PCNT_IRQHandler + B PCNT_IRQHandler + + + PUBWEAK VC0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VC0_IRQHandler + B VC0_IRQHandler + + + PUBWEAK VC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VC1_2_IRQHandler + B VC1_2_IRQHandler + + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK FLASH_RAM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_RAM_IRQHandler + B FLASH_RAM_IRQHandler + + + PUBWEAK CLKTRIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CLKTRIM_IRQHandler + B CLKTRIM_IRQHandler + + + + + + END diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/interrupts_hc32l19x.c b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/interrupts_hc32l19x.c new file mode 100644 index 0000000000..8ffcc70f30 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/interrupts_hc32l19x.c @@ -0,0 +1,770 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file interrupts_hc32l136.c + ** + ** Interrupt management + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-15 1.0 Lux First version. + ** + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_ddl.h" +#include "interrupts_hc32l19x.h" + +/******************************************************************************* + * IRQ WEAK DEFINE + ******************************************************************************/ +__WEAK void SysTick_IRQHandler(void); + +__WEAK void PortA_IRQHandler(void) +{ + +} + +__WEAK void PortB_IRQHandler(void) +{ + +} + +__WEAK void PortC_IRQHandler(void) +{ + +} + +__WEAK void PortD_IRQHandler(void) +{ + +} + +__WEAK void PortE_IRQHandler(void) +{ + +} + +__WEAK void PortF_IRQHandler(void) +{ + +} + +__WEAK void Dmac_IRQHandler(void) +{ + +} + +__WEAK void Tim3_IRQHandler(void) +{ + +} + + +__WEAK void Uart0_IRQHandler(void) +{ + +} + +__WEAK void Uart1_IRQHandler(void) +{ + +} + +__WEAK void Uart2_IRQHandler(void) +{ + +} + +__WEAK void Uart3_IRQHandler(void) +{ + +} + +__WEAK void LpUart0_IRQHandler(void) +{ + +} + +__WEAK void LpUart1_IRQHandler(void) +{ + +} + +__WEAK void Spi0_IRQHandler(void) +{ + +} + +__WEAK void Spi1_IRQHandler(void) +{ + +} + +__WEAK void I2c0_IRQHandler(void) +{ + +} + +__WEAK void I2c1_IRQHandler(void) +{ + +} + +__WEAK void Tim0_IRQHandler(void) +{ + +} + +__WEAK void Tim1_IRQHandler(void) +{ + +} + +__WEAK void Tim2_IRQHandler(void) +{ + +} + +__WEAK void LpTim0_IRQHandler(void) +{ + +} + +__WEAK void LpTim1_IRQHandler(void) +{ + +} + +__WEAK void Tim4_IRQHandler(void) +{ + +} + +__WEAK void Tim5_IRQHandler(void) +{ + +} + +__WEAK void Tim6_IRQHandler(void) +{ + +} + +__WEAK void Pca_IRQHandler(void) +{ + +} + +__WEAK void Wdt_IRQHandler(void) +{ + +} + +__WEAK void Rtc_IRQHandler(void) +{ + +} + +__WEAK void Adc_IRQHandler(void) +{ + +} + +__WEAK void Dac_IRQHandler(void) +{ + +} + +__WEAK void Pcnt_IRQHandler(void) +{ + +} + +__WEAK void Vc0_IRQHandler(void) +{ + +} + +__WEAK void Vc1_IRQHandler(void) +{ + +} + +__WEAK void Vc2_IRQHandler(void) +{ + +} + +__WEAK void Lvd_IRQHandler(void) +{ + +} + +__WEAK void Lcd_IRQHandler(void) +{ + +} + +__WEAK void Flash_IRQHandler(void) +{ + +} + +__WEAK void Ram_IRQHandler(void) +{ + +} + +__WEAK void ClkTrim_IRQHandler(void) +{ + +} + + +/** + ******************************************************************************* + ** \brief NVIC 中断使能 + ** + ** \param [in] enIrq 中断号枚举类型 + ** \param [in] enLevel 中断优先级枚举类型 + ** \param [in] bEn 中断开关 + ** \retval Ok 设置成功 + ** 其他值 设置失败 + ******************************************************************************/ +void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn) +{ + NVIC_ClearPendingIRQ(enIrq); + NVIC_SetPriority(enIrq, enLevel); + if (TRUE == bEn) + { + NVIC_EnableIRQ(enIrq); + } + else + { + NVIC_DisableIRQ(enIrq); + } +} + +/** + ******************************************************************************* + ** \brief NVIC hardware fault 中断实现 + ** + ** + ** \retval + ******************************************************************************/ +//void HardFault_Handler(void) +//{ +// volatile int a = 0; + +// while( 0 == a) +// { +// ; +// } +// +//} + + +/** + ******************************************************************************* + ** \brief NVIC SysTick 中断实现 + ** + ** \retval + ******************************************************************************/ +//void SysTick_Handler(void) +//{ +// SysTick_IRQHandler(); +//} + +/** + ******************************************************************************* + ** \brief GPIO PortA 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void PORTA_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTA) + PortA_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief GPIO PortB 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void PORTB_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTB) + PortB_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief GPIO PortC/E 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void PORTC_E_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTC) + PortC_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTE) + PortE_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief GPIO PortD/F 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void PORTD_F_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTD) + PortD_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_PORTF) + PortF_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief DMAC 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void DMAC_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_DMAC) + Dmac_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM3 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void TIM3_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM3) + Tim3_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief UART0/2 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void UART0_2_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_UART0) + Uart0_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_UART2) + Uart2_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief UART1/3 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void UART1_3_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_UART1) + Uart1_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_UART3) + Uart3_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LPUART0 低功耗串口0 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void LPUART0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LPUART0) + LpUart0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LPUART1 低功耗串口1 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void LPUART1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LPUART1) + LpUart1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief SPI0 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void SPI0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_SPI0) + Spi0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief SPI1 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void SPI1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_SPI1) + Spi1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief I2C0 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void I2C0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_I2C0) + I2c0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief I2C1 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void I2C1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_I2C1) + I2c1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM0 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void TIM0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM0) + Tim0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM1 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void TIM1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM1) + Tim1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM2 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void TIM2_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM2) + Tim2_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LPTIM0/1 低功耗时钟 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void LPTIM0_1_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LPTIM0) + LpTim0_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_LPTIM1) + LpTim1_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM4 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void TIM4_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM4) + Tim4_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM5 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void TIM5_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM5) + Tim5_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief TIM6 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void TIM6_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_TIM6) + Tim6_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief PCA 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void PCA_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PCA) + Pca_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief WDT 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void WDT_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_WDT) + Wdt_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief RTC 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void RTC_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_RTC) + Rtc_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief ADC/DAC 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void ADC_DAC_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_ADC) + Adc_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_DAC) + Dac_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief PCNT 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void PCNT_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_PCNT) + Pcnt_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief VC0 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void VC0_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_VC0) + Vc0_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief VC1/2 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void VC1_2_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_VC1) + Vc1_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_VC2) + Vc2_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LVD 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void LVD_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LVD) + Lvd_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief LCD 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void LCD_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_LCD) + Lcd_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief FLASH/RAM 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void FLASH_RAM_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_FLASH) + Flash_IRQHandler(); +#endif + +#if (INT_CALLBACK_ON == INT_CALLBACK_RAM) + Ram_IRQHandler(); +#endif +} + +/** + ******************************************************************************* + ** \brief CLKTRIM 中断处理函数 + ** + ** \retval + ******************************************************************************/ +void CLKTRIM_IRQHandler(void) +{ +#if (INT_CALLBACK_ON == INT_CALLBACK_CLKTRIM) + ClkTrim_IRQHandler(); +#endif +} + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/system_hc32l19x.c b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/system_hc32l19x.c new file mode 100644 index 0000000000..6d433f15e5 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Device/HDSC/HC32L196/Source/system_hc32l19x.c @@ -0,0 +1,179 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l136.c + ** + ** System clock initialization. + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "base_types.h" +#include "hc32l19x.h" +#include "system_hc32l19x.h" +#include "hc32l196_sysctrl.h" + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t SystemCoreClock = 4000000; + + +//add clock source. +void SystemCoreClockUpdate (void) // Update SystemCoreClock variable +{ + SystemCoreClock = Sysctrl_GetHClkFreq(); +} + +/** + ****************************************************************************** + ** \brief 对MCU未引出IO端口进行默认配置. + ** + ** \param none + ** \return none + ******************************************************************************/ +static void _InitHidePin(void) +{ + uint32_t tmpReg = M0P_SYSCTRL->PERI_CLKEN0; + + M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = 1; + +#if defined(HC32L19xPxxx) //100PIN MCU + M0P_GPIO->PFADS &= 0xFF4F; ///< PF04/PF05/PF07配置为数字端口 + + M0P_GPIO->PFDIR |= 0x00B0; ///< PF04/PF05/PF07配置为端口输入 + + M0P_GPIO->PFPU |= 0x00B0; ///< PF04/PF05/PF07配置为上拉 + +#elif defined(HC32L19xMxxx) //80PIN MCU + M0P_GPIO->PDADS &= 0x0F1F; ///< PD05~07/PD12~15配置为数字端口 + M0P_GPIO->PEADS &= 0x783C; ///< PE00/PE01/PE06~10/PE15配置为数字端口 + M0P_GPIO->PFADS &= 0xF9F3; ///< PF02/PF03/PF09/PF10配置为数字端口 + + M0P_GPIO->PDDIR |= 0xF0E0; ///< PD05~07/PD12~15配置为端口输入 + M0P_GPIO->PEDIR |= 0x87C3; ///< PE00/PE01/PE06~10/PE15配置为端口输入 + M0P_GPIO->PFDIR |= 0x060C; ///< PF02/PF03/PF09/PF10配置为数字端口 + + + M0P_GPIO->PDPU |= 0xF0E0; ///< PD05~07/PD12~15配置为上拉 + M0P_GPIO->PEPU |= 0x87C3; ///< PE00/PE01/PE06~10/PE15配置为上拉 + M0P_GPIO->PFPU |= 0x060C; ///< PF02/PF03/PF09/PF10配置为数字端口 + +#elif defined(HC32L19xKxxx) //64PIN MCU + M0P_GPIO->PDADS &= 0x0004; ///< PD00/PD01/PD03~15配置为数字端口 + M0P_GPIO->PEADS &= 0x0000; ///< PE00~15配置为数字端口 + M0P_GPIO->PFADS &= 0xF9F3; ///< PF02/PF03/PF09/PF10配置为数字端口 + + M0P_GPIO->PDDIR |= 0xFFFB; ///< PD00/PD01/PD03~15配置为端口输入 + M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15配置为端口输入 + M0P_GPIO->PFDIR |= 0x060C; ///< PF02/PF03/PF09/PF10配置为数字端口 + + M0P_GPIO->PDPU |= 0xFFFB; ///< PD00/PD01/PD03~15配置为上拉 + M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15配置为上拉 + M0P_GPIO->PFPU |= 0x060C; ///< PF02/PF03/PF09/PF10配置为数字端口 + +#elif defined(HC32L19xJxxx) //48PIN MCU + M0P_GPIO->PCADS &= 0xE000; ///< PC00~12配置为数字端口 + M0P_GPIO->PDADS &= 0x0000; ///< PD00~15配置为数字端口 + M0P_GPIO->PEADS &= 0x0000; ///< PE00~15配置为数字端口 + M0P_GPIO->PFADS &= 0xF9C3; ///< PF02~05/PF09/PF10配置为数字端口 + + M0P_GPIO->PCDIR |= 0x1FFF; ///< PC00~12配置为端口输入 + M0P_GPIO->PDDIR |= 0xFFFF; ///< PD00~15配置为端口输入 + M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15配置为端口输入 + M0P_GPIO->PFDIR |= 0x063C; ///< PF02~05/PF09/PF10配置为数字端口 + + + M0P_GPIO->PCPU |= 0x1FFF; ///< PC00~12配置为上拉 + M0P_GPIO->PDPU |= 0xFFFF; ///< PD00~15配置为上拉 + M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15配置为上拉 + M0P_GPIO->PFPU |= 0x063C; ///< PF02~05/PF09/PF10配置为数字端口 + +#elif defined(HC32L19xFxxx) //32PIN MCU + M0P_GPIO->PAADS &= 0xFFF4; ///< PA00/PA01/PA03配置为数字端口 + M0P_GPIO->PBADS &= 0x08FB; ///< PB02/PB08~10/PB12~15配置为数字端口 + M0P_GPIO->PCADS &= 0xC000; ///< PC00~13配置为数字端口 + M0P_GPIO->PDADS &= 0x0000; ///< PD00~15配置为数字端口 + M0P_GPIO->PEADS &= 0x0000; ///< PE00~15配置为数字端口 + M0P_GPIO->PFADS &= 0xF903; ///< PF02~07/PF09/PF10配置为数字端口 + + M0P_GPIO->PADIR |= 0x000B; ///< PA00/PA01/PA03配置为端口输入 + M0P_GPIO->PBDIR |= 0xF704; ///< PB02/PB08~10/PB12~15配置为端口输入 + M0P_GPIO->PCDIR |= 0x3FFF; ///< PC00~13配置为端口输入 + M0P_GPIO->PDDIR |= 0xFFFF; ///< PD00~15配置为端口输入 + M0P_GPIO->PEDIR |= 0xFFFF; ///< PE00~15配置为端口输入 + M0P_GPIO->PFDIR |= 0x06FC; ///< PF02~07/PF09/PF10配置为数字端口 + + M0P_GPIO->PAPU |= 0x000B; ///< PA00/PA01/PA03配置为上拉 + M0P_GPIO->PBPU |= 0xF704; ///< PB02/PB08~10/PB12~15配置为上拉 + M0P_GPIO->PCPU |= 0x3FFF; ///< PC00~13配置为上拉 + M0P_GPIO->PDPU |= 0xFFFF; ///< PD00~15配置为上拉 + M0P_GPIO->PEPU |= 0xFFFF; ///< PE00~15配置为上拉 + M0P_GPIO->PFPU |= 0x06FC; ///< PF02~07/PF09/PF10配置为数字端口 + +#endif + + M0P_SYSCTRL->PERI_CLKEN0 = tmpReg; +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit(void) +{ + M0P_SYSCTRL->RCL_CR_f.TRIM = (*((volatile uint16_t*) (0x00100C22ul))); + M0P_SYSCTRL->RCH_CR_f.TRIM = (*((volatile uint16_t*) (0x00100C08ul))); + SystemCoreClockUpdate(); + _InitHidePin(); +} + diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..59f173ac71 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..e917f357a3 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..feec324059 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..3ddcc58b69 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..12d68fd9a6 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_version.h b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..f2e2746626 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_armv81mml.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000000..8441e57fb1 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000..344dca5148 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000..5ddb8aeda7 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm0.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..cafae5a0a7 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..d104965db5 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm1.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm23.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000..b79c6af0b1 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm3.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm33.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000..7fed59a88e --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm35p.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000000..5579c82306 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm4.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..12c023b801 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_cm7.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..c4515d8fa3 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_sc000.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..cf92577b63 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/core_sc300.h b/bsp/hc32l196/Libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..40f3af81be --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/hc32l196/Libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000..66ef59b4a0 --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/hc32l196/Libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000..0041d4dc6f --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32l196/Libraries/CMSIS/Include/tz_context.h b/bsp/hc32l196/Libraries/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/hc32l196/Libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/ahc32l196_dt.h b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/ahc32l196_dt.h new file mode 100644 index 0000000000..fdab155922 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/ahc32l196_dt.h @@ -0,0 +1,878 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adt.h + ** + ** Headerfile for Advance Timer functions + ** @link ADT Group Some description @endlink + ** + ** - 2018-04-19 Husj First Version + ** + ******************************************************************************/ + +#ifndef __ADT_H__ +#define __ADT_H__ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "ddl.h" + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup AdtGroup Advance Timer (ADT) + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + + + /** + ****************************************************************************** + ** \brief ADT CHx通道定义 + *****************************************************************************/ +typedef enum en_adt_CHxX_port +{ + AdtCHxA = 0u, ///< CHx A通道 + AdtCHxB = 1u, ///< CHx B通道 +}en_adt_CHxX_port_t; + + /** + ****************************************************************************** + ** \brief ADT TRIG端口定义 + *****************************************************************************/ +typedef enum en_adt_trig_port +{ + AdtTrigA = 0u, ///< TIMx 触发A端口 + AdtTrigB = 1u, ///< TIMx 触发B端口 + AdtTrigC = 2u, ///< TIMx 触发C端口 + AdtTrigD = 3u, ///< TIMx 触发D端口 +}en_adt_trig_port_t; + +/** + ****************************************************************************** + ** \brief ADT通用控制 - Z相输入屏蔽周期数 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_gconr_zmsk +{ + AdtZMaskDis = 0u, ///< Z相输入屏蔽功能无效 + AdtZMask4Cyl = 1u, ///< 位置计数上溢后或下溢后的4个计数周期内的Z相输入被屏蔽 + AdtZMask8Cyl = 2u, ///< 位置计数上溢后或下溢后的8个计数周期内的Z相输入被屏蔽 + AdtZMask16Cyl = 3u, ///< 位置计数上溢后或下溢后的16个计数周期内的Z相输入被屏蔽 +}en_adt_gconr_zmsk_t; + +/** + ****************************************************************************** + ** \brief ADT通用控制 - 计数时钟选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_cnt_ckdiv +{ + AdtClkPClk0 = 0u, ///< PCLK0 + AdtClkPClk0Div2 = 1u, ///< PCLK0/2 + AdtClkPClk0Div4 = 2u, ///< PCLK0/4 + AdtClkPClk0Div8 = 3u, ///< PCLK0/8 + AdtClkPClk0Div16 = 4u, ///< PCLK0/16 + AdtClkPClk0Div64 = 5u, ///< PCLK0/64 + AdtClkPClk0Div256 = 6u, ///< PCLK0/256 + AdtClkPClk0Div1024 = 7u, ///< PCLK0/1024 +}en_adt_cnt_ckdiv_t; + +/** + ****************************************************************************** + ** \brief ADT计数模式 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_cnt_mode +{ + AdtSawtoothMode = 0u, ///< 锯齿波模式 + AdtTriangleModeA = 4u, ///< 三角波A模式 + AdtTriangleModeB = 5u, ///< 三角波B模式 +}en_adt_cnt_mode_t; + +/** + ****************************************************************************** + ** \brief ADT计数方向 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_cnt_dir +{ + AdtCntDown = 0u, ///< 递减计数 + AdtCntUp = 1u, ///< 递加计数 +}en_adt_cnt_dir_t; + +/** + ****************************************************************************** + ** \brief ADT通用比较基准 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_compare +{ + AdtCompareA = 0u, ///< 通用比较基准A + AdtCompareB = 1u, ///< 通用比较基准B + AdtCompareC = 2u, ///< 通用比较基准C + AdtCompareD = 3u, ///< 通用比较基准D +}en_adt_compare_t; + +/** + ****************************************************************************** + ** \brief ADT专用比较基准 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_special_compare +{ + AdtSpclCompA = 0u, ///< 专用比较基准A + AdtSpclCompB = 1u, ///< 专用比较基准B +}en_adt_special_compare_t; + +/** + ****************************************************************************** + ** \brief ADT端口控制 - TIMx输出状态控制 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_pconr_disval +{ + AdtTIMxDisValNorm = 0u, ///< 强制输出无效条件0~3中被选择的条件成立时，CHx端口正常输出 + AdtTIMxDisValHiZ = 1u, ///< 强制输出无效条件0~3中被选择的条件成立时，CHx端口输出高阻态 + AdtTIMxDisValLow = 2u, ///< 强制输出无效条件0~3中被选择的条件成立时，CHx端口输出低电平 + AdtTIMxDisValHigh = 3u, ///< 强制输出无效条件0~3中被选择的条件成立时，CHx端口输出高电平 +}en_adt_pconr_disval_t; + +/** + ****************************************************************************** + ** \brief ADT端口控制 - CHx强制输出无效条件选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_pconr_dissel +{ + AdtCHxDisSel0 = 0u, ///< 选择强制输出无效条件0 + AdtCHxDisSel1 = 1u, ///< 选择强制输出无效条件1 + AdtCHxDisSel2 = 2u, ///< 选择强制输出无效条件2 + AdtCHxDisSel3 = 3u, ///< 选择强制输出无效条件3 +}en_adt_pconr_dissel_t; + +/** + ****************************************************************************** + ** \brief ADT端口控制 - CHx周期值匹配时端口状态设定 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_pconr_perc +{ + AdtCHxPeriodLow = 0u, ///< 计数器计数值与周期值相等时，CHx端口输出保持为低电平 + AdtCHxPeriodHigh = 1u, ///< 计数器计数值与周期值相等时，CHx端口输出设定为高电平 + AdtCHxPeriodKeep = 2u, ///< 计数器计数值与周期值相等时，CHx端口输出设定为先前状态 + AdtCHxPeriodInv = 3u, ///< 计数器计数值与周期值相等时，CHx端口输出设定为反转电平 +}en_adt_pconr_perc_t; + +/** + ****************************************************************************** + ** \brief ADT端口控制 - CHx比较值匹配时端口状态设定 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_pconr_cmpc +{ + AdtCHxCompareLow = 0u, ///< 计数器计数值与GCMxR相等时，CHx端口输出保持为低电平 + AdtCHxCompareHigh = 1u, ///< 计数器计数值与GCMxR相等时，CHx端口输出设定为高电平 + AdtCHxCompareKeep = 2u, ///< 计数器计数值与GCMxR相等时，CHx端口输出设定为先前状态 + AdtCHxCompareInv = 3u, ///< 计数器计数值与GCMxR相等时，CHx端口输出设定为反转电平 +}en_adt_pconr_cmpc_t; + +/** + ****************************************************************************** + ** \brief ADT端口控制 - CHx端口输出 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_pconr_port_out +{ + AdtCHxPortOutLow = 0u, ///< CHx端口输出设定为低电平 + AdtCHxPortOutHigh = 1u, ///< CHx端口输出设定为高电平 +}en_adt_pconr_port_out_t; + +/** + ****************************************************************************** + ** \brief ADT端口控制 - CHx端口功能模式选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_pconr_capc +{ + AdtCHxCompareOutput = 0u, ///< CHx端口设定为比较输出功能 + AdtCHxCompareInput = 1u, ///< CHx端口设定为捕获输入功能 +}en_adt_pconr_capc_t; + +/** + ****************************************************************************** + ** \brief ADT端口控制 - CHx计数开始停止端口状态选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_pconr_stastps +{ + AdtCHxStateSelSS = 0u, ///< 计数开始或停止时，CHx端口输出由STACB、STPCB决定 + AdtCHxStateSelKeep = 1u, ///< 计数开始或停止时，CHx端口输出设定为先前状态 +}en_adt_pconr_stastps_t; + +/** + ****************************************************************************** + ** \brief ADT死区控制 - CHx死区分离设定 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_dconr_sepa +{ + AdtCHxDtSeperate = 0u, ///< DTUAR和DTDAR分别设定 + AdtCHxDtEqual = 1u, ///< DTDAR的值和DTUAR的值自动相等 +}en_adt_dconr_sepa_t; + +/** + ****************************************************************************** + ** \brief ADT滤波控制 - TRIx/TIMxIx端口滤波采样基准时钟选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_fconr_nofick +{ + AdtFltClkPclk0 = 0u, ///< PCLK0 + AdtFltClkPclk0Div4 = 1u, ///< PCLK0/4 + AdtFltClkPclk0Div16 = 2u, ///< PCLK0/16 + AdtFltClkPclk0Div64 = 3u, ///< PCLK0/64 +}en_adt_fconr_nofick_t; + +/** + ****************************************************************************** + ** \brief ADT有效周期 - TIMx有效周期选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_vperr_pcnts +{ + AdtPeriodCnts0 = 0u, ///< 有效周期选择功能无效 + AdtPeriodCnts1 = 1u, ///< 每隔1个周期有效一次 + AdtPeriodCnts2 = 2u, ///< 每隔2个周期有效一次 + AdtPeriodCnts3 = 3u, ///< 每隔3个周期有效一次 + AdtPeriodCnts4 = 4u, ///< 每隔4个周期有效一次 + AdtPeriodCnts5 = 5u, ///< 每隔5个周期有效一次 + AdtPeriodCnts6 = 6u, ///< 每隔6个周期有效一次 + AdtPeriodCnts7 = 7u, ///< 每隔7个周期有效一次 +}en_adt_vperr_pcnts_t; + +/** + ****************************************************************************** + ** \brief ADT有效周期 - 计数条件选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_vperr_pcnte +{ + AdtPeriodCnteDisable = 0u, ///< 有效周期选择功能无效 + AdtPeriodCnteMin = 1u, ///< 锯齿波计数上、下溢点或三角波波谷做为计数条件 + AdtPeriodCnteMax = 2u, ///< 锯齿波计数上、下溢点或三角波波峰做为计数条件 + AdtPeriodCnteBoth = 3u, ///< 锯齿波计数上、下溢点或三角波波峰，波谷做为计数条件 +}en_adt_vperr_pcnte_t; + +/** + ****************************************************************************** + ** \brief ADT端口触发控制 - 触发源选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_ttrig_trigxs +{ + AdtTrigxSelPA3 = 0u, ///< PA3 + AdtTrigxSelPB3 = 1u, ///< PB3 + AdtTrigxSelPC3 = 2u, ///< PC3 + AdtTrigxSelPD3 = 3u, ///< PD3 + AdtTrigxSelPA7 = 4u, ///< PA7 + AdtTrigxSelPB7 = 5u, ///< PB7 + AdtTrigxSelPC7 = 6u, ///< PC7 + AdtTrigxSelPD7 = 7u, ///< PD7 + AdtTrigxSelPA11 = 8u, ///< PA11 + AdtTrigxSelPB11 = 9u, ///< PB11 + AdtTrigxSelPC11 = 10u, ///< PC11 + AdtTrigxSelPD1 = 11u, ///< PD1 + AdtTrigxSelPA15 = 12u, ///< PA15 + AdtTrigxSelPB15 = 13u, ///< PB15 + AdtTrigxSelPC5 = 14u, ///< PC5 + AdtTrigxSelPD5 = 15u, ///< PD5 +}en_adt_ttrig_trigxs_t; + +/** + ****************************************************************************** + ** \brief ADT AOS触发控制 - AOSx触发源选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_itrig_iaosxs +{ + AdtAosxTrigSelTim0Int = 0u, ///< TIM0_INT + AdtAosxTrigSelTim1Int = 1u, ///< TIM1_INT + AdtAosxTrigSelTim2Int = 2u, ///< TIM2_INT + AdtAosxTrigSelLpTimInt = 3u, ///< LPTIMER_INT + AdtAosxTrigSelTim4Int = 4u, ///< TIM4_INT + AdtAosxTrigSelTim5Int = 5u, ///< TIM5_INT + AdtAosxTrigSelTim6Int = 6u, ///< TIM6_INT + AdtAosxTrigSelUart0Int = 7u, ///< UART0_INT + AdtAosxTrigSelUart1Int = 8u, ///< UART1_INT + AdtAosxTrigSelLpUartInt = 9u, ///< LPUART_INT + AdtAosxTrigSelVc0Int = 10u, ///< VC0_INT + AdtAosxTrigSelVc1Int = 11u, ///< VC1_INT + AdtAosxTrigSelRtcInt = 12u, ///< RTC_INT + AdtAosxTrigSelPcaInt = 13u, ///< PCA_INT + AdtAosxTrigSelSpiInt = 14u, ///< SPI_INT + AdtAosxTrigSelAdcInt = 15u, ///< ADC_INT +}en_adt_itrig_iaosxs_t; + +/** + ****************************************************************************** + ** \brief ADT硬件(启动/停止/清零/捕获)事件触发选择 + ** + ** \note + ******************************************************************************/ + +typedef enum en_adt_hw_trig +{ + AdtHwTrigAos0 = 0u, ///< 从AOS来的事件触发0有效 + AdtHwTrigAos1 = 1u, ///< 从AOS来的事件触发1有效 + AdtHwTrigAos2 = 2u, ///< 从AOS来的事件触发2有效 + AdtHwTrigAos3 = 3u, ///< 从AOS来的事件触发3有效 + AdtHwTrigCHxARise = 4u, ///< CHxA端口上采样到上升沿 + AdtHwTrigCHxAFall = 5u, ///< CHxA端口上采样到下降沿 + AdtHwTrigCHxBRise = 6u, ///< CHxB端口上采样到上升沿 + AdtHwTrigCHxBFall = 7u, ///< CHxB端口上采样到下降沿 + AdtHwTrigTimTriARise = 8u, ///< TIMTRIA端口上采样到上升沿 + AdtHwTrigTimTriAFall = 9u, ///< TIMTRIA端口上采样到下降沿 + AdtHwTrigTimTriBRise = 10u, ///< TIMTRIB端口上采样到上升沿 + AdtHwTrigTimTriBFall = 11u, ///< TIMTRIB端口上采样到下降沿 + AdtHwTrigTimTriCRise = 12u, ///< TIMTRIC端口上采样到上升沿 + AdtHwTrigTimTriCFall = 13u, ///< TIMTRIC端口上采样到下降沿 + AdtHwTrigTimTriDRise = 14u, ///< TIMTRID端口上采样到上升沿 + AdtHwTrigTimTriDFall = 15u, ///< TIMTRID端口上采样到下降沿 + AdtHwTrigEnd = 16u, +}en_adt_hw_trig_t; + +/** + ****************************************************************************** + ** \brief ADT硬件(递加/递减)事件触发选择 + ** + ** \note + ******************************************************************************/ + +typedef enum en_adt_hw_cnt +{ + AdtHwCntCHxALowCHxBRise = 0u, ///< CHxA端口为低电平时，CHxB端口上采样到上升沿 + AdtHwCntCHxALowCHxBFall = 1u, ///< CHxA端口为低电平时，CHxB端口上采样到下降沿 + AdtHwCntCHxAHighCHxBRise = 2u, ///< CHxA端口为高电平时，CHxB端口上采样到上升沿 + AdtHwCntCHxAHighCHxBFall = 3u, ///< CHxA端口为高电平时，CHxB端口上采样到下降沿 + AdtHwCntCHxBLowCHxARise = 4u, ///< CHxB端口为低电平时，CHxA端口上采样到上升沿 + AdtHwCntCHxBLowCHxAFall = 5u, ///< CHxB端口为低电平时，CHxA端口上采样到下降沿 + AdtHwCntCHxBHighChxARise = 6u, ///< CHxB端口为高电平时，CHxA端口上采样到上升沿 + AdtHwCntCHxBHighCHxAFall = 7u, ///< CHxB端口为高电平时，CHxA端口上采样到下降沿 + AdtHwCntTimTriARise = 8u, ///< TIMTRIA端口上采样到上升沿 + AdtHwCntTimTriAFall = 9u, ///< TIMTRIA端口上采样到下降沿 + AdtHwCntTimTriBRise = 10u, ///< TIMTRIB端口上采样到上升沿 + AdtHwCntTimTriBFall = 11u, ///< TIMTRIB端口上采样到下降沿 + AdtHwCntTimTriCRise = 12u, ///< TIMTRIC端口上采样到上升沿 + AdtHwCntTimTriCFall = 13u, ///< TIMTRIC端口上采样到下降沿 + AdtHwCntTimTriDRise = 14u, ///< TIMTRID端口上采样到上升沿 + AdtHwCntTimTriDFall = 15u, ///< TIMTRID端口上采样到下降沿 + AdtHwCntAos0 = 16u, ///< 从AOS来的事件触发0有效 + AdtHwCntAos1 = 17u, ///< 从AOS来的事件触发1有效 + AdtHwCntAos2 = 18u, ///< 从AOS来的事件触发2有效 + AdtHwCntAos3 = 19u, ///< 从AOS来的事件触发3有效 + AdtHwCntMax = 20u, +}en_adt_hw_cnt_t; + +/** + ****************************************************************************** + ** \brief ADT端口刹车极性控制 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_ptbrk_polarity +{ + AdtPtBrkHigh = 0u, ///< 端口刹车极性高电平有效 + AdtPtBrkLow = 1u, ///< 端口刹车极性低电平有效 +}en_adt_ptbrk_polarity_t; + +/** + ****************************************************************************** + ** \brief ADT PWM展频计数选择 + ** + ** \note + ******************************************************************************/ +typedef enum en_adt_pwm_dither_type +{ + AdtPwmDitherUnderFlow = 0u, ///< PWM展频计数下溢出 + AdtPwmDitherOverFlow = 1u, ///< PWM展频计数上溢出 +}en_adt_pwm_dither_type_t; + +/** + ****************************************************************************** + ** \brief ADT中断类型 + ** + ** \note + ******************************************************************************/ + +typedef enum en_adt_irq_type +{ + AdtCMAIrq = 0u, ///< 计数匹配A（或捕获输入）中断 + AdtCMBIrq = 1u, ///< 计数匹配B（或捕获输入）中断 + AdtCMCIrq = 2u, ///< 计数匹配C中断 + AdtCMDIrq = 3u, ///< 计数匹配D中断 + AdtOVFIrq = 6u, ///< 上溢匹配中断 + AdtUDFIrq = 7u, ///< 下溢匹配中断 + AdtDTEIrq = 8u, ///< 死区时间错误中断 + AdtSAMLIrq = 14u, ///< 同低中断 + AdtSAMHIrq = 15u, ///< 同高中断 +}en_adt_irq_type_t; + +typedef enum en_adt_state_type +{ + AdtCMAF = 0, ///< 计数匹配A标志 + AdtCMBF = 1, ///< 计数匹配B标志 + AdtCMCF = 2, ///< 计数匹配C标志 + AdtCMDF = 3, ///< 计数匹配D标志 + AdtOVFF = 6, ///< 上溢匹配标志 + AdtUDFF = 7, ///< 下溢匹配标志 + AdtDTEF = 8, ///< 死区时间错误标志 + AdtCMSAUF = 9, ///< 向上计数专用比较基准值匹配A标志 + AdtCMSADF = 10, ///< 向下计数专用比较基准值匹配B标志 + AdtCMSBUF = 11, ///< 向上计数专用比较基准值匹配A标志 + AdtCMSBDF = 12, ///< 向下计数专用比较基准值匹配B标志 + AdtCntDir = 31, ///< 计数方向 +}en_adt_state_type_t; + +/** + ****************************************************************************** + ** \brief ADT软件同步配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_sw_sync +{ + boolean_t bAdTim4; ///< Timer 4 + boolean_t bAdTim5; ///< Timer 5 + boolean_t bAdTim6; ///< Timer 6 + +}stc_adt_sw_sync_t; + +/** + ****************************************************************************** + ** \brief ADT AOS触发配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_aos_trig_cfg +{ + en_adt_itrig_iaosxs_t enAos0TrigSrc; ///< AOS0触发源选择 + en_adt_itrig_iaosxs_t enAos1TrigSrc; ///< AOS1触发源选择 + en_adt_itrig_iaosxs_t enAos2TrigSrc; ///< AOS2触发源选择 + en_adt_itrig_iaosxs_t enAos3TrigSrc; ///< AOS3触发源选择 +}stc_adt_aos_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT 中断触发配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_irq_trig_cfg +{ + boolean_t bAdtSpecilMatchBTrigDmaEn; ///< 专用比较基准值匹配B使能触发DMA + boolean_t bAdtSpecilMatchATrigDmaEn; ///< 专用比较基准值匹配A使能触发DMA + boolean_t bAdtUnderFlowTrigDmaEn; ///< 下溢匹配使能触发DMA + boolean_t bAdtOverFlowTrigDmaEn; ///< 上溢匹配使能触发DMA + boolean_t bAdtCntMatchDTrigDmaEn; ///< 计数匹配D使能触发DMA + boolean_t bAdtCntMatchCTrigDmaEn; ///< 计数匹配C使能触发DMA + boolean_t bAdtCntMatchBTrigDmaEn; ///< 计数匹配B使能触发DMA + boolean_t bAdtCntMatchATrigDmaEn; ///< 计数匹配A使能触发DMA + boolean_t bAdtSpecilMatchBTrigEn; ///< 专用比较基准值匹配B使能触发ADC + boolean_t bAdtSpecilMatchATrigEn; ///< 专用比较基准值匹配A使能触发ADC + boolean_t bAdtUnderFlowTrigEn; ///< 下溢匹配使能触发ADC + boolean_t bAdtOverFlowTrigEn; ///< 上溢匹配使能触发ADC + boolean_t bAdtCntMatchDTrigEn; ///< 计数匹配D使能触发ADC + boolean_t bAdtCntMatchCTrigEn; ///< 计数匹配C使能触发ADC + boolean_t bAdtCntMatchBTrigEn; ///< 计数匹配B使能触发ADC + boolean_t bAdtCntMatchATrigEn; ///< 计数匹配A使能触发ADC +}stc_adt_irq_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT Trig端口配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_port_trig_cfg +{ + en_adt_ttrig_trigxs_t enTrigSrc; ///< 触发源选择 + boolean_t bFltEn; ///< 触发源捕获输入滤波使能 + en_adt_fconr_nofick_t enFltClk; ///< 滤波采样基准时钟 +}stc_adt_port_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT Z相输入屏蔽功能配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_zmask_cfg +{ + en_adt_gconr_zmsk_t enZMaskCycle; ///< Z相输入屏蔽计数周期选择 + boolean_t bFltPosCntMaksEn; ///< Z相输入时的屏蔽周期内，位置计数器的清零功能不屏蔽（FALSE）或屏蔽(TRUE) + boolean_t bFltRevCntMaksEn; ///< Z相输入时的屏蔽周期内，公转计数器的计数功能不屏蔽（FALSE）或屏蔽(TRUE) +}stc_adt_zmask_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT TIMxX端口配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_TIMxX_port_cfg +{ + en_adt_pconr_capc_t enCap; ///< 端口功能模式 + boolean_t bOutEn; ///< 输出使能 + en_adt_pconr_perc_t enPerc; ///< 周期值匹配时端口状态 + en_adt_pconr_cmpc_t enCmpc; ///< 比较值匹配时端口状态 + en_adt_pconr_stastps_t enStaStp; ///< 计数开始停止端口状态选择 + en_adt_pconr_port_out_t enStaOut; ///< 计数开始端口输出状态 + en_adt_pconr_port_out_t enStpOut; ///< 计数停止端口输出状态 + en_adt_pconr_disval_t enDisVal; ///< 强制输出无效时输出状态控制 + en_adt_pconr_dissel_t enDisSel; ///< 强制输出无效条件选择 + boolean_t bFltEn; ///< 端口捕获输入滤波使能 + en_adt_fconr_nofick_t enFltClk; ///< 端口滤波采样基准时钟 +}stc_adt_CHxX_port_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT刹车端口配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_break_port_cfg +{ + boolean_t bPortEn; ///< 端口使能 + en_adt_ptbrk_polarity_t enPol; ///< 极性选择 +}stc_adt_break_port_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT无效条件3配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_disable_3_cfg +{ + stc_adt_break_port_cfg_t stcBrkPtCfg[16]; ///< 刹车端口配置 + boolean_t bFltEn; ///< 刹车端口滤波使能 + en_adt_fconr_nofick_t enFltClk; ///< 滤波采样基准时钟 +}stc_adt_disable_3_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT无效条件1配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_disable_1_cfg +{ + boolean_t bTim6OutSH; ///< TIM6输出同高 + boolean_t bTim5OutSH; ///< TIM5输出同高 + boolean_t bTim4OutSH; ///< TIM4输出同高 + boolean_t bTim6OutSL; ///< TIM6输出同低 + boolean_t bTim5OutSL; ///< TIM5输出同低 + boolean_t bTim4OutSL; ///< TIM4输出同低 +}stc_adt_disable_1_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT PWM展频计数配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_pwm_dither_cfg +{ + en_adt_pwm_dither_type_t enAdtPDType; ///< PWM展频计数选择 + boolean_t bTimxBPDEn; ///< PWM通道B展频使能 + boolean_t bTimxAPDEn; ///< PWM通道A展频使能 +}stc_adt_pwm_dither_cfg_t; + + +/** + ****************************************************************************** + ** \brief ADT基本计数配置 + ** \note + ******************************************************************************/ +typedef struct stc_adt_basecnt_cfg +{ + en_adt_cnt_mode_t enCntMode; ///< 计数模式 + en_adt_cnt_dir_t enCntDir; ///< 计数方向 + en_adt_cnt_ckdiv_t enCntClkDiv; ///< 计数时钟选择 +}stc_adt_basecnt_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT计数状态 + ** \note + ******************************************************************************/ +typedef struct stc_adt_cntstate_cfg +{ + uint16_t u16Counter; ///< 当前计数器的计数值 + boolean_t enCntDir; ///< 计数方向 + uint8_t u8ValidPeriod; ///< 有效周期计数 + boolean_t bCMSBDF; ///< 向下计数专用比较基准值匹配B标志 + boolean_t bCMSBUF; ///< 向上计数专用比较基准值匹配A标志 + boolean_t bCMSADF; ///< 向下计数专用比较基准值匹配B标志 + boolean_t bCMSAUF; ///< 向上计数专用比较基准值匹配A标志 + boolean_t bDTEF; ///< 死区时间错误标志 + boolean_t bUDFF; ///< 下溢匹配标志 + boolean_t bOVFF; ///< 上溢匹配标志 + boolean_t bCMDF; ///< 计数匹配D标志 + boolean_t bCMCF; ///< 计数匹配C标志 + boolean_t bCMBF; ///< 计数匹配B标志 + boolean_t bCMAF; ///< 计数匹配A标志 +}stc_adt_cntstate_cfg_t; + +/** + ****************************************************************************** + ** \brief ADT有效计数周期 + ** \note + ******************************************************************************/ +typedef struct stc_adt_validper_cfg +{ + en_adt_vperr_pcnts_t enValidCnt; ///< 有效周期选择 + en_adt_vperr_pcnte_t enValidCdt; ///< 有效周期计数条件 + boolean_t bPeriodD; ///< 通用信号有效周期选择D + boolean_t bPeriodC; ///< 通用信号有效周期选择C + boolean_t bPeriodB; ///< 通用信号有效周期选择B + boolean_t bPeriodA; ///< 通用信号有效周期选择A +}stc_adt_validper_cfg_t; + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions ('extern') + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +//配置硬件递加事件 +en_result_t Adt_CfgHwCntUp(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_cnt_t enAdtHwCntUp); +//清除硬件递加事件 +en_result_t Adt_ClearHwCntUp(M0P_ADTIM_TypeDef *ADTx); +//配置硬件递减事件 +en_result_t Adt_CfgHwCntDwn(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_cnt_t enAdtHwCntDwn); +//清除硬件递减事件 +en_result_t Adt_ClearHwCntDwn(M0P_ADTIM_TypeDef *ADTx); +//配置硬件启动事件 +en_result_t Adt_CfgHwStart(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwStart); +//清除硬件启动事件 +en_result_t Adt_ClearHwStart(M0P_ADTIM_TypeDef *ADTx); +//使能硬件启动事件 +en_result_t Adt_EnableHwStart(M0P_ADTIM_TypeDef *ADTx); +//禁止硬件启动事件 +en_result_t Adt_DisableHwStart(M0P_ADTIM_TypeDef *ADTx); +//配置硬件停止事件 +en_result_t Adt_CfgHwStop(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwStop); +//清除硬件停止事件 +en_result_t Adt_ClearHwStop(M0P_ADTIM_TypeDef *ADTx); +//使能硬件停止事件 +en_result_t Adt_EnableHwStop(M0P_ADTIM_TypeDef *ADTx); +//禁止硬件停止事件 +en_result_t Adt_DisableHwStop(M0P_ADTIM_TypeDef *ADTx); +//配置硬件清零事件 +en_result_t Adt_CfgHwClear(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwClear); +//清除硬件清零事件 +en_result_t Adt_ClearHwClear(M0P_ADTIM_TypeDef *ADTx); +//使能硬件清零事件 +en_result_t Adt_EnableHwClear(M0P_ADTIM_TypeDef *ADTx); +//禁止硬件清零事件 +en_result_t Adt_DisableHwClear(M0P_ADTIM_TypeDef *ADTx); +//配置A通道硬件捕获事件 +en_result_t Adt_CfgHwCaptureA(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwCaptureA); +//清除A通道硬件捕获事件 +en_result_t Adt_ClearHwCaptureA(M0P_ADTIM_TypeDef *ADTx); +//配置B通道硬件捕获事件 +en_result_t Adt_CfgHwCaptureB(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwCaptureB); +//清除B通道硬件捕获事件 +en_result_t Adt_ClearHwCaptureB(M0P_ADTIM_TypeDef *ADTx); +//软件同步启动 +en_result_t Adt_SwSyncStart(stc_adt_sw_sync_t* pstcAdtSwSyncStart); +//软件同步停止 +en_result_t Adt_SwSyncStop(stc_adt_sw_sync_t* pstcAdtSwSyncStop); +//软件同步清零 +en_result_t Adt_SwSyncClear(stc_adt_sw_sync_t* pstcAdtSwSyncClear); +//获取软件同步状态 +en_result_t Adt_GetSwSyncState(stc_adt_sw_sync_t* pstcAdtSwSyncState); +//AOS触发配置 +en_result_t Adt_AosTrigCfg(stc_adt_aos_trig_cfg_t* pstcAdtAosTrigCfg); +//中断触发配置 +en_result_t Adt_IrqTrigCfg(M0P_ADTIM_TypeDef *ADTx, + stc_adt_irq_trig_cfg_t* pstcAdtIrqTrigCfg); +//端口触发配置 +en_result_t Adt_PortTrigCfg(en_adt_trig_port_t enAdtTrigPort, + stc_adt_port_trig_cfg_t* pstcAdtPortTrigCfg); +//CHxX端口配置 +en_result_t Adt_CHxXPortCfg(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + stc_adt_CHxX_port_cfg_t* pstcAdtCHxXCfg); +//使能端口刹车 +en_result_t Adt_EnableBrakePort(uint8_t port, stc_adt_break_port_cfg_t* pstcAdtBrkPtCfg); +//清除端口刹车 +void Adt_ClearBrakePort(void); +//无效条件3配置(端口刹车) +en_result_t Adt_Disable3Cfg(stc_adt_disable_3_cfg_t* pstcAdtDisable3); +//软件刹车 Enable/Disable(仅适用于无效条件3使能的情况下) +en_result_t Adt_SwBrake(boolean_t bSwBrk); +//获取端口刹车标志 +boolean_t Adt_GetPortBrakeFlag(void); +//清除端口刹车标志 +void Adt_ClearPortBrakeFlag(void); +//无效条件1配置(同高同低刹车) +en_result_t Adt_Disable1Cfg(stc_adt_disable_1_cfg_t* pstcAdtDisable1); +//获取同高同低刹车标志 +boolean_t Adt_GetSameBrakeFlag(void); +//清除同高同低刹车标志 +void Adt_ClearSameBrakeFlag(void); +//PWM展频配置 +en_result_t Adt_PwmDitherCfg(M0P_ADTIM_TypeDef *ADTx, stc_adt_pwm_dither_cfg_t* pstcAdtPwmDitherCfg); +//AdvTimer初始化 +en_result_t Adt_Init(M0P_ADTIM_TypeDef *ADTx, stc_adt_basecnt_cfg_t* pstcAdtBaseCntCfg); +//AdvTimer去初始化 +en_result_t Adt_DeInit(M0P_ADTIM_TypeDef *ADTx); +//AdvTimert启动 +en_result_t Adt_StartCount(M0P_ADTIM_TypeDef *ADTx); +//AdvTimert停止 +en_result_t Adt_StopCount(M0P_ADTIM_TypeDef *ADTx); +//设置计数值 +en_result_t Adt_SetCount(M0P_ADTIM_TypeDef *ADTx, uint16_t u16Value); +//获取计数值 +uint16_t Adt_GetCount(M0P_ADTIM_TypeDef *ADTx); +//清除计数值 +en_result_t Adt_ClearCount(M0P_ADTIM_TypeDef *ADTx); +//获取有效周期计数值 +uint8_t Adt_GetVperNum(M0P_ADTIM_TypeDef *ADTx); +//获取状态标志 +boolean_t Adt_GetState(M0P_ADTIM_TypeDef *ADTx, en_adt_state_type_t enstate); +//配置计数周期 +en_result_t Adt_SetPeriod(M0P_ADTIM_TypeDef *ADTx, uint16_t u16Period); +//配置计数周期缓冲 +en_result_t Adt_SetPeriodBuf(M0P_ADTIM_TypeDef *ADTx, uint16_t u16PeriodBuf); +//清除计数周期缓冲 +en_result_t Adt_ClearPeriodBuf(M0P_ADTIM_TypeDef *ADTx); +//配置有效计数周期 +en_result_t Adt_SetValidPeriod(M0P_ADTIM_TypeDef *ADTx, + stc_adt_validper_cfg_t* pstcAdtValidPerCfg); +//配置比较输出计数基准值 +en_result_t Adt_SetCompareValue(M0P_ADTIM_TypeDef *ADTx, + en_adt_compare_t enAdtCompare, + uint16_t u16Compare); +//配置通用比较值/捕获值的缓存传送 +en_result_t Adt_EnableValueBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + boolean_t bCompareBufEn); +//清除比较输出计数值/捕获值缓存 +en_result_t Adt_ClearValueBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort); +//获取捕获值 +en_result_t Adt_GetCaptureValue(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16Capture); +//获取捕获缓存值 +en_result_t Adt_GetCaptureBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16CaptureBuf); +//设置死区时间上基准值 +en_result_t Adt_SetDTUA(M0P_ADTIM_TypeDef *ADTx, + uint16_t u16Value); +//设置死区时间下基准值 +en_result_t Adt_SetDTDA(M0P_ADTIM_TypeDef *ADTx, + uint16_t u16Value); +//配置死区时间功能 +en_result_t Adt_CfgDT(M0P_ADTIM_TypeDef *ADTx, + boolean_t bDTEn, + boolean_t bEqual); +//配置中断 +en_result_t Adt_CfgIrq(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq, + boolean_t bEn); +//获取中断标志 +boolean_t Adt_GetIrqFlag(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq); +//清除中断标志 +en_result_t Adt_ClearIrqFlag(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq); +//清除所有中断标志 +en_result_t Adt_ClearAllIrqFlag(M0P_ADTIM_TypeDef *ADTx); +//Z相输入屏蔽设置 +en_result_t Adt_CfgZMask(M0P_ADTIM_TypeDef *ADTx, + stc_adt_zmask_cfg_t* pstcAdtZMaskCfg); + +//@} // ADT Group + +#ifdef __cplusplus +} +#endif + +#endif /* __ADT_H__ */ +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_adc.h b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_adc.h new file mode 100644 index 0000000000..f1eccb9a96 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_adc.h @@ -0,0 +1,470 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adc.h + ** + ** Header file for AD Converter functions + ** @link ADC Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +#ifndef __ADC_H__ +#define __ADC_H__ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup AdcGroup AD Converter (ADC) + ** + ******************************************************************************/ + +//@{ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define ADC_SCAN_CH0_EN (0x1u) /*!< SCAN模式使用ADC CH0 */ +#define ADC_SCAN_CH1_EN (0x1u<<1) /*!< SCAN模式使用ADC CH1 */ +#define ADC_SCAN_CH2_EN (0x1u<<2) /*!< SCAN模式使用ADC CH2 */ +#define ADC_SCAN_CH3_EN (0x1u<<3) /*!< SCAN模式使用ADC CH3 */ +#define ADC_SCAN_CH4_EN (0x1u<<4) /*!< SCAN模式使用ADC CH4 */ +#define ADC_SCAN_CH5_EN (0x1u<<5) /*!< SCAN模式使用ADC CH5 */ +#define ADC_SCAN_CH6_EN (0x1u<<6) /*!< SCAN模式使用ADC CH6 */ +#define ADC_SCAN_CH7_EN (0x1u<<7) /*!< SCAN模式使用ADC CH7 */ + + +/****************************************************************************** + ** Global type definitions + *****************************************************************************/ + + /** + ****************************************************************************** + ** \brief ADC转换模式 + *****************************************************************************/ +typedef enum en_adc_mode +{ + AdcSglMode = 0u, /*!< 单输入通道单次转换模式 */ + AdcScanMode = 1u, /*!< 多输入通道顺序/插队扫描转换模式*/ +}en_adc_mode_t; + +/** + ****************************************************************************** + ** \brief ADC时钟分频选择 + *****************************************************************************/ +typedef enum en_adc_clk_sel +{ + AdcMskClkDiv1 = 0u<<2, /*!< PCLK */ + AdcMskClkDiv2 = 1u<<2, /*!< 1/2 PCLK */ + AdcMskClkDiv4 = 2u<<2, /*!< 1/4 PCLK */ + AdcMskClkDiv8 = 3u<<2, /*!< 1/8 PCLK */ +} en_adc_clk_div_t; + +/** + ****************************************************************************** + ** \brief ADC参考电压 + *****************************************************************************/ +typedef enum en_adc_ref_vol_sel +{ + AdcMskRefVolSelInBgr1p5 = 0u<<9, /*!<内部参考电压1.5V(SPS<=200kHz)*/ + AdcMskRefVolSelInBgr2p5 = 1u<<9, /*!<内部参考电压2.5V(avdd>3V,SPS<=200kHz)*/ + AdcMskRefVolSelExtern1 = 2u<<9, /*!<外部输入(max avdd) PB01*/ + AdcMskRefVolSelAVDD = 3u<<9, /*!>4)*10) + ((x)&0x0F)) + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + ****************************************************************************** + ** Global Device Series List + ******************************************************************************/ +#define DDL_DEVICE_SERIES_HC32L17X (0u) + +/** + ****************************************************************************** + ** Global Device Package List + ******************************************************************************/ +// package definitions of HC device. +#define DDL_DEVICE_PACKAGE_HC_C (0x00u) +#define DDL_DEVICE_PACKAGE_HC_F (0x10u) +#define DDL_DEVICE_PACKAGE_HC_J (0x20u) +#define DDL_DEVICE_PACKAGE_HC_K (0x30u) + +/******************************************************************************/ +/* User Device Setting Include file */ +/******************************************************************************/ +#include "ddl_device.h" // MUST be included here! + +/******************************************************************************/ +/* Global type definitions ('typedef') */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Level + ** + ** Specifies levels. + ** + ******************************************************************************/ +typedef enum en_level +{ + DdlLow = 0u, ///< Low level '0' + DdlHigh = 1u ///< High level '1' +} en_level_t; + +/** + ****************************************************************************** + ** \brief Generic Flag Code + ** + ** Specifies flags. + ** + ******************************************************************************/ +typedef enum en_flag +{ + DdlClr = 0u, ///< Flag clr '0' + DdlSet = 1u ///< Flag set '1' +} en_stat_flag_t, en_irq_flag_t; +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +/******************************************************************************* + * Global function prototypes + ******************************************************************************/ +extern void ddl_memclr(void* pu8Address, uint32_t u32Count); +uint32_t Log2(uint32_t u32Val); +/** + ******************************************************************************* + ** This hook is part of wait loops. + ******************************************************************************/ +void delay1ms(uint32_t u32Cnt); +void delay100us(uint32_t u32Cnt); +void delay10us(uint32_t u32Cnt); +void SetBit(uint32_t addr, uint32_t offset, boolean_t bFlag); +void ClrBit(uint32_t addr, uint32_t offset); +boolean_t GetBit(uint32_t addr, uint32_t offset); +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_debug.h b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_debug.h new file mode 100644 index 0000000000..4f33fde939 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_debug.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file debug.h + ** + ** Headerfile for DEBUG functions + ** @link Debug Group Some description @endlink + ** + ** History: + ** - 2018-04-15 Lux First Version + ** + ******************************************************************************/ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup DebugGroup (DEBUG) + ** + ******************************************************************************/ +//@{ + +/** + ******************************************************************************* + ** function prototypes. + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief 调试模式下各模块工作状态类型定义 + ** \note + ******************************************************************************/ +typedef enum en_debug_module_active +{ + DebugMskTim0 = 0x0001u, ///< TIM0 + DebugMskTim1 = 0x0002u, ///< TIM1 + DebugMskTim2 = 0x0004u, ///< TIM2 + DebugMskLpTim0 = 0x0008u, ///< LPTIM0 + DebugMskTim4 = 0x0010u, ///< TIM4 + DebugMskTim5 = 0x0020u, ///< TIM5 + DebugMskTim6 = 0x0040u, ///< TIM6 + DebugMskPca = 0x0080u, ///< PCA + DebugMskWdt = 0x0100u, ///< WDT + DebugMskRtc = 0x0200u, ///< RTC + DebugMskTim3 = 0x0800u, ///< TIM3 + DebugMskLpTim1 = 0x1000u, ///< LPTIM1 +}en_debug_module_active_t; + +/******************************************************************************* + * Global definitions + ******************************************************************************/ + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +///< 在SWD调试模式下，使能模块计数功能 +en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule); +///< 在SWD调试模式下，暂停模块计数功能 +en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule); + +//@} // Debug Group + +#ifdef __cplusplus +#endif + +#endif /* __DEBUG_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_dmac.h b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_dmac.h new file mode 100644 index 0000000000..bdd93b0ba6 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_dmac.h @@ -0,0 +1,356 @@ +/***************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dma.h +** +** A detailed description is available at +** @link DmacGroup Dmac description @endlink +** +** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac. +** +******************************************************************************/ +#ifndef __DMAC_H__ +#define __DMAC_H__ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + ******************************************************************************* + ** \defgroup DmacGroup Direct Memory Access Control(DMAC) + ** + ******************************************************************************/ + //@{ + + /******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief DMA 通道 + ** + ******************************************************************************/ + typedef enum en_dma_channel + { + DmaCh0 = 0x00, ///< DMA 通道0 + DmaCh1 = 0x04, ///< DMA 通道1 + } en_dma_channel_t; + /** + ******************************************************************************* + ** \brief DMA 优先级 + ** + ******************************************************************************/ + typedef enum en_dma_priority + { + DmaMskPriorityFix = 0x00000000, ///< DMA 各通道优先级固定 (CH0>CH1) + DmaMskPriorityLoop = 0x10000000, ///< DMA 各通道优先级采用轮询方式 + } en_dma_priority_t; + + /** + ******************************************************************************* + ** \brief DMA 传输数据宽度 + ** + ******************************************************************************/ + typedef enum en_dma_transfer_width + { + DmaMsk8Bit = 0x00000000, ///< 8 bit 字节传输 + DmaMsk16Bit = 0x04000000, ///< 16 bit 半字传输 + DmaMsk32Bit = 0x08000000 ///< 32 bit 字传输 + } en_dma_transfer_width_t; + + /** + ******************************************************************************* + ** \brief DMA 传输模式：块(Block)传输或者突发(Burst)传输 + ** + ******************************************************************************/ + typedef enum en_dma_transfer_mode + { + DmaMskBlock = 0x00000000, ///< 块(Block)传输 + DmaMskBurst = 0x10000000, ///< 突发(Burst)传输 + } en_dma_transfer_mode_t; + + /** + ******************************************************************************* + ** \brief DMA传输当前状态 + ** + ******************************************************************************/ + typedef enum en_dma_stat + { + DmaDefault = 0U, ///< 初始值 + DmaAddOverflow = 1U, ///< 传输错误引起中止（地址溢出） + DmaHALT = 2U, ///< 传输停止请求引起中止（外设停止请求引起的停止或者EB/DE位引起的禁止传输） + DmaAccSCRErr = 3U, ///< 传输错误引起中止（传输源地址访问错误） + DmaAccDestErr = 4U, ///< 传输错误引起中止（传输目的地址访问错误） + DmaTransferComplete = 5U, ///< 成功传输完成 + DmaTransferPause = 7U, ///< 传输暂停 + } en_dma_stat_t; + + /** + ******************************************************************************* + ** \brief DMA源地址控制模式：自增或固定 + ** + ******************************************************************************/ + typedef enum en_src_address_mode + { + DmaMskSrcAddrInc = 0x00000000, ///< 地址自增 + DmaMskSrcAddrFix = 0x02000000, ///< 地址固定 + } en_src_address_mode_t; + + /** + ******************************************************************************* + ** \brief DMA目的地址控制模式：自增或固定 + ** + ******************************************************************************/ + typedef enum en_dst_address_mode + { + DmaMskDstAddrInc = 0x00000000, ///< 地址自增 + DmaMskDstAddrFix = 0x01000000, ///< 地址固定 + } en_dst_address_mode_t; + + /** + ******************************************************************************* + ** \brief DMA CONFA:BC[3:0]和CONFA:TC[15:0]的重载功能 + ** + ******************************************************************************/ + typedef enum en_bc_tc_reload_mode + { + DmaMskBcTcReloadDisable = 0x00000000, ///< 禁止重载 + DmaMskBcTcReloadEnable = 0x00800000, ///< 使能重载 + } en_bc_tc_reload_mode_t; + + /** + ******************************************************************************* + ** \brief DMA源地址重载功能：使能或禁止 + ** + ******************************************************************************/ + typedef enum en_src_address_reload_mode + { + DmaMskSrcAddrReloadDisable = 0x00000000, ///< 禁止DMA源地址重载 + DmaMskSrcAddrReloadEnable = 0x00400000, ///< 使能DMA源地址重载 + } en_src_address_reload_mode_t; + + /** + ******************************************************************************* + ** \brief DMA目的地址重载功能：使能或禁止 + ** + ******************************************************************************/ + typedef enum en_dst_address_reload_mode + { + DmaMskDstAddrReloadDisable = 0x00000000, ///< 禁止DMA目的地址重载 + DmaMskDstAddrReloadEnable = 0x00200000, ///< 使能DMA目的地址重载 + } en_dst_address_reload_mode_t; + + + + /** + ******************************************************************************* + ** \brief DMA 连续传输设置 + ** + ******************************************************************************/ + typedef enum en_dma_msk + { + DmaMskOneTransfer = 0x00000000, ///< 传输一次，DMAC传输完成时清除CONFA:ENS位 + DmaMskContinuousTransfer = 0x00000001, ///< 连续传输，DMAC传输完成时不清除CONFA:ENS位 + } en_dma_msk_t; + /** + ******************************************************************************* + ** \brief DMA 触发源选择 + ** + ******************************************************************************/ + typedef enum stc_dma_trig_sel + { + DmaSWTrig = 0U, ///< Select DMA software trig + DmaSPI0RXTrig = 64U, ///< Select DMA hardware trig 0 + DmaSPI0TXTrig = 65U, ///< Select DMA hardware trig 1 + DmaSPI1RXTrig = 66U, ///< Select DMA hardware trig 2 + DmaSPI1TXTrig = 67U, ///< Select DMA hardware trig 3 + DmaADCJQRTrig = 68U, ///< Select DMA hardware trig 4 + DmaADCSQRTrig = 69U, ///< Select DMA hardware trig 5 + DmaLCDTxTrig = 70U, ///< Select DMA hardware trig 6 + DmaUart0RxTrig = 72U, ///< Select DMA hardware trig 8 + DmaUart0TxTrig = 73U, ///< Select DMA hardware trig 9 + DmaUart1RxTrig = 74U, ///< Select DMA hardware trig 10 + DmaUart1TxTrig = 75U, ///< Select DMA hardware trig 11 + DmaLpUart0RxTrig = 76U, ///< Select DMA hardware trig 12 + DmaLpUart0TxTrig = 77U, ///< Select DMA hardware trig 13 + DmaLpUart1RxTrig = 78U, ///< Select DMA hardware trig 14 + DmaLpUart1TxTrig = 79U, ///< Select DMA hardware trig 15 + DmaDAC0Trig = 80U, ///< Select DMA hardware trig 16 + DmaDAC1Trig = 81U, ///< Select DMA hardware trig 17 + DmaTIM0ATrig = 82U, ///< Select DMA hardware trig 18 + DmaTIM0BTrig = 83U, ///< Select DMA hardware trig 19 + DmaTIM1ATrig = 84U, ///< Select DMA hardware trig 20 + DmaTIM1BTrig = 85U, ///< Select DMA hardware trig 21 + DmaTIM2ATrig = 86U, ///< Select DMA hardware trig 22 + DmaTIM2BTrig = 87U, ///< Select DMA hardware trig 23 + DmaTIM3ATrig = 88U, ///< Select DMA hardware trig 24 + DmaTIM3BTrig = 89U, ///< Select DMA hardware trig 25 + DmaTIM4ATrig = 90U, ///< Select DMA hardware trig 26 + DmaTIM4BTrig = 91U, ///< Select DMA hardware trig 27 + DmaTIM5ATrig = 92U, ///< Select DMA hardware trig 28 + DmaTIM5BTrig = 93U, ///< Select DMA hardware trig 29 + DmaTIM6ATrig = 94U, ///< Select DMA hardware trig 30 + DmaTIM6BTrig = 95U, ///< Select DMA hardware trig 31 + DmaUart2RxTrig = 96U, ///< Select DMA hardware trig 32 + DmaUart2TxTrig = 97U, ///< Select DMA hardware trig 33 + DmaUart3RxTrig = 98U, ///< Select DMA hardware trig 34 + DmaUart3TxTrig = 99U, ///< Select DMA hardware trig 35 + }en_dma_trig_sel_t; + + /** + ******************************************************************************* + ** \brief DMA通道初始化配置结构体 + ** + ******************************************************************************/ + typedef struct stc_dma_cfg + { + en_dma_transfer_mode_t enMode; + + uint16_t u16BlockSize; ///< 块传输个数 + uint16_t u16TransferCnt; ///< 传输块次数 + en_dma_transfer_width_t enTransferWidth; ///< 传输数据字节宽度 具体参考枚举定义:en_dma_transfer_width_t + + en_src_address_mode_t enSrcAddrMode; ///< DMA源地址控制模式：自增或固定 + en_dst_address_mode_t enDstAddrMode; ///< DMA目的地址控制模式：自增或固定 + + en_src_address_reload_mode_t enSrcAddrReloadCtl; ///< 源地址重载 具体参考枚举定义:en_src_address_reload_mode_t + en_dst_address_reload_mode_t enDestAddrReloadCtl;///< 目的地址重载 具体参考枚举定义:en_dst_address_reload_mode_t + en_bc_tc_reload_mode_t enSrcBcTcReloadCtl; ///< Bc/Tc值重载功能 具体参考枚举定义:en_bc_tc_reload_mode_t + + uint32_t u32SrcAddress; ///< 源地址> + uint32_t u32DstAddress; ///< 目的地址> + + en_dma_msk_t enTransferMode; ///DMA 连续传输设置 具体参考枚举定义:en_dma_msk_t + en_dma_priority_t enPriority; ///DMA 优先级设定 具体参考枚举定义:en_dma_priority_t + en_dma_trig_sel_t enRequestNum; ///PCLK=HCLK=SystemClk=RCH4MHz +en_result_t Sysctrl_ClkDeInit(void); + +///< 系统时钟模块的基本功能设置 +///< 注意：使能需要使用的时钟源之前，必须优先设置目标内部时钟源的TRIM值或外部时钟源的频率范围 +en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag); + +///<外部晶振驱动配置：系统初始化Sysctrl_ClkInit()之后，可根据需要配置外部晶振的驱动能力，时钟初始化Sysctrl_ClkInit()默认为最大值; +en_result_t Sysctrl_XTHDriverCfg(en_sysctrl_xtal_driver_t enDriver); +en_result_t Sysctrl_XTLDriverCfg(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver); + +///<时钟稳定周期设置:系统初始化Sysctrl_ClkInit()之后，可根据需要配置时钟开启后的稳定之间，默认为最大值; +en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle); +en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle); +en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle); +en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle); + +///<系统时钟源切换并更新系统时钟：如果需要在系统时钟初始化Sysctrl_ClkInit()之后切换主频时钟源，则使用该函数； +///< 时钟切换前后，必须根据目标频率值设置Flash读等待周期，可配置插入周期为0、1、2， +///< 注意!!!：当HCLK大于24MHz时，FLASH等待周期插入必须至少为1,否则程序运行可能产生未知错误 +en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource); + +///< 时钟源频率设定：根据系统情况，单独设置不同时钟源的频率值; +///< 时钟频率设置前，必须根据目标频率值设置Flash读等待周期，可配置插入周期为0、1、2， +///< 其中XTL的时钟由外部晶振决定，无需设置。 +en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq); +en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq); +en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq); +en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_cfg_t *pstcPLLCfg); + +///< 时钟分频设置:根据系统情况，单独设置HCLK、PCLK的分配值; +en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv); +en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv); + +///< 时钟频率获取：根据系统需要，获取当前HCLK及PCLK的频率值 +uint32_t Sysctrl_GetHClkFreq(void); +uint32_t Sysctrl_GetPClkFreq(void); + +///< 外设门控开关/状态获取：用于控制外设模块的使能，使用该模块的功能之前，必须使能该模块的门控时钟； +en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag); +boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral); + +///< 系统功能配置：用于设置其他系统相关特殊功能； +en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag); + +///< RTC高速时钟补偿:用于设置RTC高速时钟下的频率补偿 +en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj); + +//@} // Sysctrl Group + +#ifdef __cplusplus +#endif + +#endif /* __SYSCTRL_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_timer3.h b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_timer3.h new file mode 100644 index 0000000000..fbe59fcd59 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_timer3.h @@ -0,0 +1,781 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file timer3.h + ** + ** 基本定时器数据结构及API声明 + ** @link Timer3 Group Some description @endlink + ** + ** History: + ** - 2019-04-18 Husj First Version + ** + *****************************************************************************/ + +#ifndef __TIMER3_H__ +#define __TIMER3_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup Tim3Group Timer3 (TIM3) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Timer3 通道定义 + *****************************************************************************/ +typedef enum en_tim3_channel +{ + Tim3CH0 = 0u, ///< Timer3通道0 + Tim3CH1 = 1u, ///< Timer3通道1 + Tim3CH2 = 2u, ///< Timer3通道2 +}en_tim3_channel_t; + +/** + ****************************************************************************** + ** \brief 工作模式选择数据类型重定义 (MODE)(模式0/1/23) + *****************************************************************************/ +typedef enum en_tim3_work_mode +{ + Tim3WorkMode0 = 0u, ///< 定时器模式 + Tim3WorkMode1 = 1u, ///< PWC模式 + Tim3WorkMode2 = 2u, ///< 锯齿波模式 + Tim3WorkMode3 = 3u, ///< 三角波模式 +}en_tim3_work_mode_t; + +/** + ****************************************************************************** + ** \brief 极性控制数据类型重定义 (GATE_P)(模式0) + *****************************************************************************/ +typedef enum en_tim3_m0cr_gatep +{ + Tim3GatePositive = 0u, ///< 高电平有效 + Tim3GateOpposite = 1u, ///< 低电平有效 +}en_tim3_m0cr_gatep_t; + +/** + ****************************************************************************** + ** \brief TIM3 预除频选择 (PRS)(模式0/1/23) + *****************************************************************************/ +typedef enum en_tim3_cr_timclkdiv +{ + Tim3PCLKDiv1 = 0u, ///< Div 1 + Tim3PCLKDiv2 = 1u, ///< Div 2 + Tim3PCLKDiv4 = 2u, ///< Div 4 + Tim3PCLKDiv8 = 3u, ///< Div 8 + Tim3PCLKDiv16 = 4u, ///< Div 16 + Tim3PCLKDiv32 = 5u, ///< Div 32 + Tim3PCLKDiv64 = 6u, ///< Div 64 + Tim3PCLKDiv256 = 7u, ///< Div 256 +}en_tim3_cr_timclkdiv_t; + +/** + ****************************************************************************** + ** \brief 计数/定时器功能选择数据类型重定义 (CT)(模式0/1/23) + *****************************************************************************/ +typedef enum en_tim3_cr_ct +{ + Tim3Timer = 0u, ///< 定时器功能，计数时钟为内部PCLK + Tim3Counter = 1u, ///< 计数器功能，计数时钟为外部ETR +}en_tim3_cr_ct_t; + + +/** + ****************************************************************************** + ** \brief 定时器工作模式数据类型重定义 (MD)(模式0) + *****************************************************************************/ +typedef enum en_tim3_m0cr_md +{ + Tim332bitFreeMode = 0u, ///< 32位计数器/定时器 + Tim316bitArrMode = 1u, ///< 自动重装载16位计数器/定时器 +}en_tim3_m0cr_md_t; + +/** + ****************************************************************************** +** \brief TIM3中断类型数据类型重定义(模式0/1/23) + *****************************************************************************/ +typedef enum en_tim3_irq_type +{ + Tim3UevIrq = 0u, ///< 溢出/事件更新中断 + Tim3CA0Irq = 2u, ///< CH0A捕获/比较中断(仅模式1/23存在) + Tim3CA1Irq = 3u, ///< CH1A捕获/比较中断(仅模式23存在) + Tim3CA2Irq = 4u, ///< CH2A捕获/比较中断(仅模式23存在) + Tim3CB0Irq = 5u, ///< CH0B捕获/比较中断(仅模式23存在) + Tim3CB1Irq = 6u, ///< CH1B捕获/比较中断(仅模式23存在) + Tim3CB2Irq = 7u, ///< CH2B捕获/比较中断(仅模式23存在) + Tim3CA0E = 8u, ///< CH0A捕获数据丢失标志(仅模式23存在)(不是中断) + Tim3CA1E = 9u, ///< CH1A捕获数据丢失标志(仅模式23存在)(不是中断) + Tim3CA2E = 10u, ///< CH2A捕获数据丢失标志(仅模式23存在)(不是中断) + Tim3CB0E = 11u, ///< CH0B捕获数据丢失标志(仅模式23存在)(不是中断) + Tim3CB1E = 12u, ///< CH1B捕获数据丢失标志(仅模式23存在)(不是中断) + Tim3CB2E = 13u, ///< CH2B捕获数据丢失标志(仅模式23存在)(不是中断) + Tim3BkIrq = 14u, ///< 刹车中断(仅模式23存在） + Tim3TrigIrq = 15u, ///< 触发中断(仅模式23存在） +}en_tim3_irq_type_t; + +/** + ****************************************************************************** + ** \brief 测量开始结束数据类型重定义 (Edg1stEdg2nd)(模式1) + *****************************************************************************/ +typedef enum en_tim3_m1cr_Edge +{ + Tim3PwcRiseToRise = 0u, ///< 上升沿到上升沿(周期) + Tim3PwcFallToRise = 1u, ///< 下降沿到上升沿(低电平) + Tim3PwcRiseToFall = 2u, ///< 上升沿到下降沿(高电平) + Tim3PwcFallToFall = 3u, ///< 下降沿到下降沿(周期) +}en_tim3_m1cr_Edge_t; + +/** + ****************************************************************************** + ** \brief PWC测量测试模式选择数据类型重定义 (Oneshot)(模式1) + *****************************************************************************/ +typedef enum en_tim3_m1cr_oneshot +{ + Tim3PwcCycleDetect = 0u, ///< PWC循环测量 + Tim3PwcOneShotDetect = 1u, ///< PWC单次测量 +}en_tim3_m1cr_oneshot_t; + +/** + ****************************************************************************** + ** \brief PWC IA0选择数据类型重定义 (IA0S)(模式1) + *****************************************************************************/ +typedef enum en_tim3_m1_mscr_ia0s +{ + Tim3IA0Input = 0u, ///< IAO输入 + Tim3XORInput = 1u, ///< IA0 ETR GATE XOR(TIM0/1/2)/IA0 IA1 IA2 XOR(TIM3) +}en_tim3_m1_mscr_ia0s_t; + +/** + ****************************************************************************** + ** \brief PWC IB0选择数据类型重定义 (IA0S)(模式1) + *****************************************************************************/ +typedef enum en_tim3_m1_mscr_ib0s +{ + Tim3IB0Input = 0u, ///< IBO输入 + Tim3TsInput = 1u, ///< 内部触发TS选择信号 +}en_tim3_m1_mscr_ib0s_t; + +/** + ****************************************************************************** + ** \brief 输出极性、输入相位 数据类型重定义 (CCPA0/CCPB0/ETP/BKP)(模式1/23) + *****************************************************************************/ +typedef enum en_tim3_port_polarity +{ + Tim3PortPositive = 0u, ///< 正常输入输出 + Tim3PortOpposite = 1u, ///< 反向输入输出 +}en_tim3_port_polarity_t; + +/** + ****************************************************************************** + ** \brief 滤波选择数据类型重定义 (FLTET/FLTA0/FLAB0)(模式1/23) + *****************************************************************************/ +typedef enum en_tim3_flt +{ + Tim3FltNone = 0u, ///< 无滤波 + Tim3FltPCLKCnt3 = 4u, ///< PCLK 3个连续有效 + Tim3FltPCLKDiv4Cnt3 = 5u, ///< PCLK/4 3个连续有效 + Tim3FltPCLKDiv16Cnt3 = 6u, ///< PCLK/16 3个连续有效 + Tim3FltPCLKDiv64Cnt3 = 7u, ///< PCLK/64 3个连续有效 +}en_tim3_flt_t; + +/** + ****************************************************************************** + ** \brief 通道比较控制 数据类型重定义 (OCMA/OCMB)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23_fltr_ocm +{ + Tim3ForceLow = 0u, ///< 强制为0 + Tim3ForceHigh = 1u, ///< 强制为1 + Tim3CMPForceLow = 2u, ///< 比较匹配时强制为0 + Tim3CMPForceHigh = 3u, ///< 比较匹配时强制为1 + Tim3CMPInverse = 4u, ///< 比较匹配时翻转电平 + Tim3CMPOnePrdHigh = 5u, ///< 比较匹配时输出一个计数周期的高电平 + Tim3PWMMode1 = 6u, ///< 通道控制为PWM mode 1 + Tim3PWMMode2 = 7u, ///< 通道控制为PWM mode 2 +}en_tim3_m23_fltr_ocm_t; + +/** + ****************************************************************************** + ** \brief 主从模式TS数据类型重定义 (TS)(模式1/23) + *****************************************************************************/ +typedef enum en_tim3_mscr_ts +{ + Tim3Ts0ETR = 0u, ///< ETR外部输入滤波后的相位选择信号 + Tim3Ts1TIM0TRGO = 1u, ///< Timer0的TRGO输出信号 + Tim3Ts2TIM1TRGO = 2u, ///< Timer1的TRGO输出信号 + Tim3Ts3TIM2TRGO = 3u, ///< Timer2的TRGO输出信号 + Tim3Ts4TIM3TRGO = 4u, ///< Timer3的TRGO输出信号 + //Tim3Ts5IA0ED = 5u, ///< 无效 + Tim3Ts6IAFP = 6u, ///< CH0A 外部输输入滤波后的相位选择信号 + Tim3Ts7IBFP = 7u, ///< CH0B 外部输输入滤波后的相位选择信 +}en_tim3_mscr_ts_t; + +/** + ****************************************************************************** + ** \brief PWM输出模式选择数据类型重定义 (COMP)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_comp +{ + Tim3IndependentPWM = 0u, ///< 独立PWM输出 + Tim3ComplementaryPWM = 1u, ///< 互补PWM输出 +}en_tim3_m23cr_comp_t; + +/** + ****************************************************************************** + ** \brief 计数方向选择数据类型重定义 (DIR)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_dir +{ + Tim3CntUp = 0u, ///< 向上计数 + Tim3CntDown = 1u, ///< 向下计数 +}en_tim3_m23cr_dir_t; + +/** + ****************************************************************************** + ** \brief 计数方向选择数据类型重定义 (PWM2S)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_pwm2s +{ + Tim3DoublePointCmp = 0u, ///< 双点比较使能，使用CCRA,CCRB比较控制OCREFA输出 + Tim3SinglePointCmp = 1u, ///< 单点比较使能，使用CCRA比较控制OCREFA输出 +}en_tim3_m23cr_pwm2s_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模式下捕获或比较功能 选择数据类型重定义 (CSG)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_csg +{ + Tim3PWMCompGateCmpOut = 0u, ///< 在PWM互补模式下，Gate作为比较输出 + Tim3PWMCompGateCapIn = 1u, ///< 在PWM互补模式下，Gate作为捕获输入 +}en_tim3_m23cr_csg_t; + + +/** + ****************************************************************************** + ** \brief 比较捕获寄存器 数据类型重定义 (CCR0A,CCR0B)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23_ccrx +{ + Tim3CCR0A = 0u, ///< CCR0A比较捕获寄存器 + Tim3CCR0B = 1u, ///< CCR0B比较捕获寄存器 + Tim3CCR1A = 2u, ///< CCR1A比较捕获寄存器 + Tim3CCR1B = 3u, ///< CCR1B比较捕获寄存器 + Tim3CCR2A = 4u, ///< CCR2A比较捕获寄存器 + Tim3CCR2B = 5u, ///< CCR2B比较捕获寄存器 +}en_tim3_m23_ccrx_t; + +/** + ****************************************************************************** + ** \brief OCREF清除源 选择数据类型重定义 (OCCS)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23ce_occs +{ + Tim3OC_Ref_Clr = 0u, ///< 来自VC的OC_Ref_Clr + Tim3ETRf = 1u, ///< 外部ETRf +}en_tim3_m23ce_occs_t; + +/** + ****************************************************************************** + ** \brief 比较匹配中断模式 选择数据类型重定义 (CIS/CISB)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23_cisa_cisb +{ + Tim3CmpIntNone = 0u, ///< 无比较匹配中断 + Tim3CmpIntRise = 1u, ///< 比较匹配上升沿中断 + Tim3CmpIntFall = 2u, ///< 比较匹配下降沿中断 + Tim3CmpIntRiseFall = 3u, ///< 比较匹配上升沿下降沿中断 +}en_tim3_m23_cisa_cisb_t; + +/** + ****************************************************************************** + ** \brief TIM3端口控制 - 刹车时CHx输出状态控制(BKSA/BKSB)(模式23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crchx_bks +{ + Tim3CHxBksHiZ = 0u, ///< 刹车使能时，CHx端口输出高阻态 + Tim3CHxBksNorm = 1u, ///< 刹车使能时，CHx端口正常输出 + Tim3CHxBksLow = 2u, ///< 刹车使能时，CHx端口输出低电平 + Tim3CHxBksHigh = 3u, ///< 刹车使能时，CHx端口输出高电平 +}en_tim3_m23_crchx_bks_t; + +/** + ****************************************************************************** +** \brief TIM3端口控制 - CHx上升沿下降沿捕获(CRx/CFx)(模式23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crch0_cfx_crx +{ + Tim3CHxCapNone = 0u, ///< CHx通道捕获禁止 + Tim3CHxCapRise = 1u, ///< CHx通道上升沿捕获使能 + Tim3CHxCapFall = 2u, ///< CHx通道下降沿捕获使能 + Tim3CHxCapFallRise = 3u, ///< CHx通道上升沿下降沿捕获都使能 +}en_tim3_m23_crch0_cfx_crx_t; + +/** + ****************************************************************************** +** \brief TIM3端口控制 - CHx比较捕获模式(CSA/CSB)(模式23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crch0_csa_csb +{ + Tim3CHxCmpMode = 0u, ///< CHx通道设置为比较模式 + Tim3CHxCapMode = 1u, ///< CHx通道设置为捕获模式 +}en_tim3_m23_crch0_csa_csb_t; + +/** + ****************************************************************************** + ** \brief 比较模式下 DMA比较触发选择 数据类型重定义 (CCDS)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_ccds +{ + Tim3CmpTrigDMA = 0u, ///< 比较匹配触发DMA + Tim3UEVTrigDMA = 1u, ///< 事件更新代替比较匹配触发DMA +}en_tim3_m23_mscr_ccds_t; + +/** + ****************************************************************************** + ** \brief 主从模式选择 数据类型重定义 (MSM)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_msm +{ + Tim3SlaveMode = 0u, ///< 从模式 + Tim3MasterMode = 1u, ///< 主模式 +}en_tim3_m23_mscr_msm_t; + +/** + ****************************************************************************** + ** \brief 触发主模式输出源 数据类型重定义 (MMS)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_mms +{ + Tim3MasterUG = 0u, ///< UG(软件更新)源 + Tim3MasterCTEN = 1u, ///< CTEN源 + Tim3MasterUEV = 2u, ///< UEV更新源 + Tim3MasterCMPSO = 3u, ///< 比较匹配选择输出源 + Tim3MasterOCA0Ref = 4u, ///< OCA0_Ref源 + Tim3MasterOCB0Ref = 5u, ///< OCB0_Ref源 + //Tim3MasterOCB0Ref = 6u, + //Tim3MasterOCB0Ref = 7u, +}en_tim3_m23_mscr_mms_t; + +/** + ****************************************************************************** + ** \brief 触发从模式选择 数据类型重定义 (SMS)(模式23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_sms +{ + Tim3SlaveIClk = 0u, ///< 使用内部时钟 + Tim3SlaveResetTIM = 1u, ///< 复位功能 + Tim3SlaveTrigMode = 2u, ///< 触发模式 + Tim3SlaveEClk = 3u, ///< 外部时钟模式 + Tim3SlaveCodeCnt1 = 4u, ///< 正交编码计数模式1 + Tim3SlaveCodeCnt2 = 5u, ///< 正交编码计数模式2 + Tim3SlaveCodeCnt3 = 6u, ///< 正交编码计数模式3 + Tim3SlaveGateCtrl = 7u, ///< 门控功能 +}en_tim3_m23_mscr_sms_t; + +/** + ****************************************************************************** + ** \brief 定时器运行控制数据类型重定义 (CTEN) + *****************************************************************************/ +typedef enum en_tim3_start +{ + Tim3CTENDisable = 0u, ///< 停止 + Tim3CTENEnable = 1u, ///< 运行 +}en_tim3_start_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode0 配置结构体定义(模式0) + *****************************************************************************/ +typedef struct stc_tim3_mode0_cfg +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模式设置 + en_tim3_m0cr_gatep_t enGateP; ///< 门控极性控制 + boolean_t bEnGate; ///< 门控使能 + en_tim3_cr_timclkdiv_t enPRS; ///< 预除频配置 + boolean_t bEnTog; ///< 翻转输出使能 + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m0cr_md_t enCntMode; ///< 计数模式配置 +}stc_tim3_mode0_cfg_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode1 配置结构体定义(模式1) + *****************************************************************************/ +typedef struct stc_tim3_mode1_cfg +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模式设置 + en_tim3_cr_timclkdiv_t enPRS; ///< 预除频配置 + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m1cr_oneshot_t enOneShot; ///< 单次测量/循环测量选择 +}stc_tim3_mode1_cfg_t; + +/** + ****************************************************************************** + ** \brief PWC输入配置结构体定义(模式1) + *****************************************************************************/ +typedef struct stc_tim3_pwc_input_cfg +{ + en_tim3_mscr_ts_t enTsSel; ///< 触发输入源选择 + en_tim3_m1_mscr_ia0s_t enIA0Sel; ///< CHA0输入选择 + en_tim3_m1_mscr_ib0s_t enIB0Sel; ///< CHB0输入选择 + en_tim3_port_polarity_t enETRPhase; ///< ETR相位选择 + en_tim3_flt_t enFltETR; ///< ETR滤波设置 + en_tim3_flt_t enFltIA0; ///< CHA0滤波设置 + en_tim3_flt_t enFltIB0; ///< CHB0滤波设置 +}stc_tim3_pwc_input_cfg_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode23 配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_mode23_cfg +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模式设置 + en_tim3_m23cr_dir_t enCntDir; ///< 计数方向 + en_tim3_cr_timclkdiv_t enPRS; ///< 时钟预除频配置 + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m23cr_comp_t enPWMTypeSel; ///< PWM模式选择（独立/互补） + en_tim3_m23cr_pwm2s_t enPWM2sSel; ///< OCREFA双点比较功能选择 + boolean_t bOneShot; ///< 单次触发模式使能/禁止 + boolean_t bURSSel; ///< 更新源选择 +}stc_tim3_mode23_cfg_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模式下捕获或比较功能 配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_gate_cfg +{ + en_tim3_m23cr_csg_t enGateFuncSel; ///< Gate比较、捕获功能选择 + boolean_t bGateRiseCap; ///< GATE作为捕获功能时，上沿捕获有效控制 + boolean_t bGateFallCap; ///< GATE作为捕获功能时，下沿捕获有效控制 +}stc_tim3_m23_gate_cfg_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通道比较控制 配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_compare_cfg +{ + en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/捕获功能选择 + en_tim3_m23_fltr_ocm_t enCHxACmpCtrl; ///< CH0A通道比较控制 + en_tim3_port_polarity_t enCHxAPolarity; ///< CH0A输出极性控制 + boolean_t bCHxACmpBufEn; ///< 比较A缓存功能 使能/禁止 + en_tim3_m23_cisa_cisb_t enCHxACmpIntSel; ///< CHA比较匹配中断选择 + + en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0B比较/捕获功能选择 + en_tim3_m23_fltr_ocm_t enCHxBCmpCtrl; ///< CH0B通道比较控制 + en_tim3_port_polarity_t enCHxBPolarity; ///< CH0B输出极性控制 + boolean_t bCHxBCmpBufEn; ///< 比较B缓存功能 使能/禁止 + en_tim3_m23_cisa_cisb_t enCHxBCmpIntSel; ///< CHB0比较匹配中断选择 +}stc_tim3_m23_compare_cfg_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通道捕获控制 配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_input_cfg +{ + en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/捕获功能选择 + en_tim3_m23_crch0_cfx_crx_t enCHxACapSel; ///< CH0A捕获边沿选择 + en_tim3_flt_t enCHxAInFlt; ///< CH0A通道捕获滤波控制 + en_tim3_port_polarity_t enCHxAPolarity; ///< CH0A输入相位 + + en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0A比较/捕获功能选择 + en_tim3_m23_crch0_cfx_crx_t enCHxBCapSel; ///< CH0B捕获边沿选择 + en_tim3_flt_t enCHxBInFlt; ///< CH0B通道捕获滤波控制 + en_tim3_port_polarity_t enCHxBPolarity; ///< CH0B输入相位 + +}stc_tim3_m23_input_cfg_t; + +/** + ****************************************************************************** + ** \brief ETR输入相位滤波配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_etr_input_cfg +{ + en_tim3_port_polarity_t enETRPolarity; ///< ETR输入极性设置 + en_tim3_flt_t enETRFlt; ///< ETR滤波设置 +}stc_tim3_m23_etr_input_cfg_t; + +/** + ****************************************************************************** + ** \brief 刹车BK输入相位滤波配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_bk_input_cfg +{ + boolean_t bEnBrake; ///< 刹车使能 + boolean_t bEnVCBrake; ///< 使能VC刹车 + boolean_t bEnSafetyBk; ///< 使能safety刹车 + boolean_t bEnBKSync; ///< TIM0/TIM1/TIM2刹车同步使能 + en_tim3_m23_crchx_bks_t enBkCH0AStat; ///< 刹车时CHA端口状态设置 + en_tim3_m23_crchx_bks_t enBkCH0BStat; ///< 刹车时CHB端口状态设置 + en_tim3_m23_crchx_bks_t enBkCH1AStat; ///< 刹车时CHA端口状态设置 + en_tim3_m23_crchx_bks_t enBkCH1BStat; ///< 刹车时CHB端口状态设置 + en_tim3_m23_crchx_bks_t enBkCH2AStat; ///< 刹车时CHA端口状态设置 + en_tim3_m23_crchx_bks_t enBkCH2BStat; ///< 刹车时CHB端口状态设置 + en_tim3_port_polarity_t enBrakePolarity; ///< 刹车BK输入极性设置 + en_tim3_flt_t enBrakeFlt; ///< 刹车BK滤波设置 +}stc_tim3_m23_bk_input_cfg_t; + +/** + ****************************************************************************** +** \brief 死区功能配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_dt_cfg +{ + boolean_t bEnDeadTime; ///< 刹车时CHA端口状态设置 + uint8_t u8DeadTimeValue; ///< 刹车时CHA端口状态设置 +}stc_tim3_m23_dt_cfg_t; + +/** + ****************************************************************************** + ** \brief 触发ADC配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_adc_trig_cfg +{ + boolean_t bEnTrigADC; ///< 触发ADC全局控制 + boolean_t bEnUevTrigADC; ///< 事件更新触发ADC + boolean_t bEnCH0ACmpTrigADC; ///< CH0A比较匹配触发ADC + boolean_t bEnCH0BCmpTrigADC; ///< CH0B比较匹配触发ADC + boolean_t bEnCH1ACmpTrigADC; ///< CH0A比较匹配触发ADC + boolean_t bEnCH1BCmpTrigADC; ///< CH0B比较匹配触发ADC + boolean_t bEnCH2ACmpTrigADC; ///< CH0A比较匹配触发ADC + boolean_t bEnCH2BCmpTrigADC; ///< CH0B比较匹配触发ADC +}stc_tim3_m23_adc_trig_cfg_t; + +/** + ****************************************************************************** + ** \brief DMA触发 配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_trig_dma_cfg +{ + boolean_t bUevTrigDMA; ///< 更新 触发DMA使能 + boolean_t bTITrigDMA; ///< Trig 触发DMA功能 + boolean_t bCmpA0TrigDMA; ///< CH0A捕获比较触发DMA使能 + boolean_t bCmpB0TrigDMA; ///< CH0B捕获比较触发DMA使能 + boolean_t bCmpA1TrigDMA; ///< CH1A捕获比较触发DMA使能 + boolean_t bCmpB1TrigDMA; ///< CH1B捕获比较触发DMA使能 + boolean_t bCmpA2TrigDMA; ///< CH2A捕获比较触发DMA使能 + boolean_t bCmpB2TrigDMA; ///< CH2B捕获比较触发DMA使能 + en_tim3_m23_mscr_ccds_t enCmpUevTrigDMA; ///< 比较模式下DMA比较触发选择 +}stc_tim3_m23_trig_dma_cfg_t; + +/** + ****************************************************************************** + ** \brief 主从模式 配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_master_slave_cfg +{ + en_tim3_m23_mscr_msm_t enMasterSlaveSel; ///< 主从模式选择 + en_tim3_m23_mscr_mms_t enMasterSrc; ///< 主模式触发源选择 + en_tim3_m23_mscr_sms_t enSlaveModeSel; ///< 从模式选择 + en_tim3_mscr_ts_t enTsSel; ///< 触发输入源选择 +}stc_tim3_m23_master_slave_cfg_t; + +/** + ****************************************************************************** + ** \brief OCREF清除功能 配置结构体定义(模式23) + *****************************************************************************/ +typedef struct stc_tim3_m23_OCREF_Clr_cfg +{ + en_tim3_m23ce_occs_t enOCRefClrSrcSel; ///< OCREF清除源选择 + boolean_t bVCClrEn; ///< 是否使能来自VC的OCREF_Clr +}stc_tim3_m23_OCREF_Clr_cfg_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//中断相关函数 + +//中断标志获取 +boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq); +//中断标志清除 +en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq); +//所有中断标志清除 +en_result_t Tim3_ClearAllIntFlag(void); +//模式0中断使能 +en_result_t Tim3_Mode0_EnableIrq(void); +//模式1中断使能 +en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq); +//模式2中断使能 +en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq); +//模式0中断禁止 +en_result_t Tim3_Mode0_DisableIrq(void); +//模式1中断禁止 +en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq); +//模式2中断禁止 +en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq); + + +//模式0初始化及相关功能操作 + +//timer配置及初始化 +en_result_t Tim3_Mode0_Init(stc_tim3_mode0_cfg_t* pstcCfg); +//timer 启动/停止 +en_result_t Tim3_M0_Run(void); +en_result_t Tim3_M0_Stop(void); +//重载值设置 +en_result_t Tim3_M0_ARRSet(uint16_t u16Data); +//16位计数值设置/获取 +en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M0_Cnt16Get(void); +//32位计数值设置/获取 +en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data); +uint32_t Tim3_M0_Cnt32Get(void); +//端口输出使能/禁止设定 +en_result_t Tim3_M0_Enable_Output(boolean_t bEnOutput); +//翻转使能/禁止（低电平）设定 +en_result_t Tim3_M0_EnTOG(boolean_t bEnTOG); + +//模式1初始化及相关功能操作 + +//timer配置及初始化 +en_result_t Tim3_Mode1_Init(stc_tim3_mode1_cfg_t* pstcCfg); +//PWC 输入配置 +en_result_t Tim3_M1_Input_Cfg(stc_tim3_pwc_input_cfg_t* pstcCfg); +//PWC测量边沿起始结束选择 +en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel); +//timer 启动/停止 +en_result_t Tim3_M1_Run(void); +en_result_t Tim3_M1_Stop(void); +//16位计数值设置/获取 +en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M1_Cnt16Get(void); +//脉冲宽度测量结果数值获取 +uint16_t Tim3_M1_PWC_CapValueGet(void); + + +//模式23初始化及相关功能操作 + +//timer配置及初始化 +en_result_t Tim3_Mode23_Init(stc_tim3_mode23_cfg_t* pstcCfg); +//timer 启动/停止 +en_result_t Tim3_M23_Run(void); +en_result_t Tim3_M23_Stop(void); +//PWM输出使能 +en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput); +//重载值设置 +en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn); +//16位计数值设置/获取 +en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M23_Cnt16Get(void); +//比较捕获寄存器CCR0A/CCR0B设置/读取 +en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data); +uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel); +//PWM互补输出模式下，GATE功能选择 +en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_cfg_t* pstcCfg); +//主从模式配置 +en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_cfg_t* pstcCfg); +//CH0A/CH0B比较通道控制 +en_result_t Tim3_M23_PortOutput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_cfg_t* pstcCfg); +//CH0A/CH0B输入控制 +en_result_t Tim3_M23_PortInput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_cfg_t* pstcCfg); +//ERT输入控制 +en_result_t Tim3_M23_ETRInput_Cfg(stc_tim3_m23_etr_input_cfg_t* pstcCfg); +//刹车BK输入控制 +en_result_t Tim3_M23_BrakeInput_Cfg(stc_tim3_m23_bk_input_cfg_t* pstcBkCfg); +//触发ADC控制 +en_result_t Tim3_M23_TrigADC_Cfg(stc_tim3_m23_adc_trig_cfg_t* pstcCfg); +//死区功能 +en_result_t Tim3_M23_DT_Cfg(stc_tim3_m23_dt_cfg_t* pstcCfg); +//重复周期设置 +en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod); +//OCREF清除功能 +en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_cfg_t* pstcCfg); +//使能DMA传输 +en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_cfg_t* pstcCfg); +//捕获比较A软件触发 +en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx); +//捕获比较B软件触发 +en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx); +//软件更新使能 +en_result_t Tim3_M23_EnSwUev(void); +//软件触发使能 +en_result_t Tim3_M23_EnSwTrig(void); +//软件刹车使能 +en_result_t Tim3_M23_EnSwBk(void); + + +//@} // Tim3Group + +#ifdef __cplusplus +#endif + + +#endif /* __BT_H__ */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_trim.h b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_trim.h new file mode 100644 index 0000000000..5b8e7ef062 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/hc32l196_trim.h @@ -0,0 +1,184 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/*****************************************************************************/ +/** \file trim.h + ** + ** TRIM 数据结构及API声明 + ** + ** + ** History: + ** - 2018-04-21 Lux V1.0 + ** + *****************************************************************************/ + +#ifndef __TRIM_H__ +#define __TRIM_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup TrimGroup Clock Trimming (TRIM) + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + ** Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + + /** + ****************************************************************************** + ** \brief 监测模式使能枚举重定义 (MON_EN) + *****************************************************************************/ +typedef enum en_trim_monitor +{ + TrimMonDisable = 0u, ///< 禁止 + TrimMonEnable = 0x40u, ///< 使能 +}en_trim_monitor_t; + + /** + ****************************************************************************** + ** \brief 待校准/监测时钟选择枚举重定义 (CALCLK_SEL) + *****************************************************************************/ +typedef enum en_trim_calclksel +{ + TrimCalMskRCH = 0x000u, ///< RCH + TrimCalMskXTH = 0x010u, ///< XTH + TrimCalMskRCL = 0x020u, ///< RCL + TrimCalMskXTL = 0x030u, ///< XTL + TrimCalMskPLL = 0x100u, ///< PLL +}en_trim_calclksel_t; + +/** + ****************************************************************************** + ** \brief 参考时钟选择枚举重定义 (REFCLK_SEL) + *****************************************************************************/ +typedef enum en_trim_refclksel +{ + TrimRefMskRCH = 0x0u, ///< RCH + TrimRefMskXTH = 0x2u, ///< XTH + TrimRefMskRCL = 0x4u, ///< RCL + TrimRefMskXTL = 0x6u, ///< XTL + TrimRefMskIRC10K = 0x8u, ///< IRC10K + TrimRefMskExtClk = 0xau, ///< 外部输入时钟 +}en_trim_refclksel_t; + +/** + ****************************************************************************** + ** \brief 中断标志类型枚举重定义 + *****************************************************************************/ +typedef enum en_trim_inttype +{ + TrimStop = 0x01u, ///< 参考计数器停止标志 + TrimCalCntOf = 0x02u, ///< 校准计数器溢出标志 + TrimXTLFault = 0x04u, ///< XTL 失效标志 + TrimXTHFault = 0x08u, ///< XTH 失效标志 + TrimPLLFault = 0x10u, ///< PLL 失效标志 +}en_trim_inttype_t; + +/** + ****************************************************************************** + ** \brief TRIM 配置结构体定义 + *****************************************************************************/ +typedef struct stc_trim_cfg +{ + en_trim_monitor_t enMON; ///< 监测模式使能 + en_trim_calclksel_t enCALCLK; ///< 校准时钟选择 + uint32_t u32CalCon; ///< 校准计数器溢出值配置 + en_trim_refclksel_t enREFCLK; ///< 参考时钟选择 + uint32_t u32RefCon; ///< 参考计数器初值配置 +}stc_trim_cfg_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +///<<功能配置及操作函数 +///IFR&enAdcIrq) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + * \brief + * 获取ADC中断状态 + * + * \param [in] enAdcIrq ADC中断类型 @ref en_adc_irq_type_t + * + * \retval Null + */ +void Adc_ClrIrqStatus(en_adc_irq_type_t enAdcIrq) +{ + M0P_ADC->ICR &= ~(uint32_t)enAdcIrq; +} + +/** + * \brief + * ADC中断使能 + * + * \param 无 + * + * \retval 无 + */ +void Adc_EnableIrq(void) +{ + M0P_ADC->CR0_f.IE = 1u; +} + +/** + * \brief + * ADC中断禁止 + * + * \param 无 + * + * \retval 无 + */ +void Adc_DisableIrq(void) +{ + M0P_ADC->CR0_f.IE = 0u; +} + +/** + * \brief + * ADC初始化 + * + * \param [in] pstcAdcCfg ADC配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + */ +en_result_t Adc_Init(stc_adc_cfg_t* pstcAdcCfg) +{ + if (NULL == pstcAdcCfg) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR0 = 0x1u; ///< ADC 使能 + delay10us(2); + + M0P_ADC->CR0 |= (uint32_t)pstcAdcCfg->enAdcClkDiv | + (uint32_t)pstcAdcCfg->enAdcRefVolSel | + (uint32_t)pstcAdcCfg->enAdcOpBuf | + (uint32_t)pstcAdcCfg->enAdcSampCycleSel | + (uint32_t)pstcAdcCfg->enInRef; + + M0P_ADC->CR1_f.MODE = pstcAdcCfg->enAdcMode; + M0P_ADC->CR1_f.ALIGN = pstcAdcCfg->enAdcAlign; + + return Ok; +} + + +/** + * \brief + * ADC单次转换外部中断触发源配置 + * + * \param [in] enAdcTrigSel 触发源 + * + * \retval en_result_t Null + */ +void Adc_SglExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue) +{ + if(TRUE == bValue) + { + M0P_ADC->EXTTRIGGER0 |= (uint32_t)enAdcTrigSel; + } + else + { + M0P_ADC->EXTTRIGGER0 &= ~(uint32_t)enAdcTrigSel; + } + +} + +/** + * \brief + * ADC顺序扫描转换外部中断触发源配置 + * + * \param [in] enAdcTrigSel 触发源 + * \param [in] TRUE or FALSE + * + * \retval en_result_t Null + */ +void Adc_SqrExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue) +{ + if(TRUE == bValue) + { + M0P_ADC->EXTTRIGGER0 |= (uint32_t)enAdcTrigSel; + } + else + { + M0P_ADC->EXTTRIGGER0 &= ~(uint32_t)enAdcTrigSel; + } + +} + +/** + * \brief + * ADC插队扫描转换外部中断触发源配置 + * + * \param [in] enAdcTrigSel 触发源 + * \param [in] TRUE or FALSE + * + * \retval en_result_t Null + */ +void Adc_JqrExtTrigCfg(en_adc_trig_sel_t enAdcTrigSel, boolean_t bValue) +{ + if(TRUE == bValue) + { + M0P_ADC->EXTTRIGGER1 |= (uint32_t)enAdcTrigSel; + } + else + { + M0P_ADC->EXTTRIGGER1 &= ~(uint32_t)enAdcTrigSel; + } + +} + + +/** + * \brief + * ADC 单次转换开始 + * + * \param 无 + * + * \retval 无 + */ + +void Adc_SGL_Start(void) +{ + M0P_ADC->SGLSTART = 1u; +} + +/** + * \brief + * ADC 单次转换停止 + * + * \param 无 + * + * \retval 无 + */ +void Adc_SGL_Stop(void) +{ + M0P_ADC->SGLSTART = 0u; +} + +/** + * \brief + * ADC 单次转换一直转换开始 + * + * \param 无 + * + * \retval 无 + */ + +void Adc_SGL_Always_Start(void) +{ + M0P_ADC->ALLSTART = 1u; +} + +/** + * \brief + * ADC 单次转换一直转换停止 + * + * \param 无 + * + * \retval 无 + */ + +void Adc_SGL_Always_Stop(void) +{ + M0P_ADC->ALLSTART = 0u; +} + +/** + * \brief + * ADC 顺序扫描转换开始 + * + * \param 无 + * + * \retval 无 + */ + +void Adc_SQR_Start(void) +{ + M0P_ADC->SQRSTART = 1u; +} + +/** + * \brief + * ADC 顺序扫描转换停止 + * + * \param 无 + * + * \retval 无 + */ +void Adc_SQR_Stop(void) +{ + M0P_ADC->SQRSTART = 0u; +} +/** + * \brief + * ADC 插队扫描转换开始 + * + * \param 无 + * + * \retval 无 + */ + +void Adc_JQR_Start(void) +{ + M0P_ADC->JQRSTART = 1u; +} + +/** + * \brief + * ADC 插队扫描转换停止 + * + * \param 无 + * + * \retval 无 + */ +void Adc_JQR_Stop(void) +{ + M0P_ADC->JQRSTART = 0u; +} + +/** + * \brief + * ADC使能 + * + * \param 无 + * + * \retval 无 + */ +void Adc_Enable(void) +{ + M0P_ADC->CR0_f.EN = 1u; +} + +/** + * \brief + * ADC除能 + * + * \param 无 + * + * \retval 无 + */ +void Adc_Disable(void) +{ + M0P_ADC->CR0_f.EN = 0u; +} + +/** + * \brief + * 配置顺序扫描转换模式 + * + * \param [in] pstcAdcCfg ADC配置指针 + * \param [in] pstcAdcNormCfg 连续转换模式配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + */ +en_result_t Adc_SqrModeCfg(stc_adc_sqr_cfg_t* pstcAdcSqrCfg) +{ + if ((NULL == pstcAdcSqrCfg) || (pstcAdcSqrCfg->u8SqrCnt > 16)) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.RACCCLR = 0; //ADC转换结果累加寄存器（ADC_ResultAcc）清零 + M0P_ADC->CR1_f.RACCEN = pstcAdcSqrCfg->enResultAcc; + M0P_ADC->CR1_f.DMASQR = pstcAdcSqrCfg->bSqrDmaTrig; + + M0P_ADC->SQR2_f.CNT = pstcAdcSqrCfg->u8SqrCnt - 1; + + return Ok; +} + +/** + * \brief + * 配置插队扫描转换模式 + * + * \param [in] pstcAdcCfg ADC配置指针 + * \param [in] pstcAdcNormCfg 扫描转换模式配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + */ +en_result_t Adc_JqrModeCfg(stc_adc_jqr_cfg_t* pstcAdcJqrCfg) +{ + if ((NULL == pstcAdcJqrCfg) || (pstcAdcJqrCfg->u8JqrCnt > 4)) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.DMASQR = pstcAdcJqrCfg->bJqrDmaTrig; + + M0P_ADC->JQR_f.CNT = pstcAdcJqrCfg->u8JqrCnt - 1; + + return Ok; +} + +/** + * \brief + * 配置单次转换通道 + * + * \param [in]enstcAdcSampCh 转换通道 + * + * \retval en_result_t Ok: 成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + */ +en_result_t Adc_CfgSglChannel( en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + M0P_ADC->CR0_f.SGLMUX = enstcAdcSampCh; + + return Ok; +} + +/** + * \brief + * 配置顺序扫描转换通道 + * + * \param [in]enstcAdcSqrChMux 顺序扫描转换通道顺序 + * \param [in]enstcAdcSampCh 转换通道 + * + * \retval en_result_t Ok: 成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + */ +en_result_t Adc_CfgSqrChannel(en_adc_sqr_chmux_t enstcAdcSqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + en_result_t enResult = Ok; + + switch(enstcAdcSqrChMux) + { + case AdcSQRCH0MUX: + M0P_ADC->SQR0_f.CH0MUX = enstcAdcSampCh; + break; + case AdcSQRCH1MUX: + M0P_ADC->SQR0_f.CH1MUX = enstcAdcSampCh; + break; + case AdcSQRCH2MUX: + M0P_ADC->SQR0_f.CH2MUX = enstcAdcSampCh; + break; + case AdcSQRCH3MUX: + M0P_ADC->SQR0_f.CH3MUX = enstcAdcSampCh; + break; + case AdcSQRCH4MUX: + M0P_ADC->SQR0_f.CH4MUX = enstcAdcSampCh; + break; + case AdcSQRCH5MUX: + M0P_ADC->SQR0_f.CH5MUX = enstcAdcSampCh; + break; + case AdcSQRCH6MUX: + M0P_ADC->SQR1_f.CH6MUX = enstcAdcSampCh; + break; + case AdcSQRCH7MUX: + M0P_ADC->SQR1_f.CH7MUX = enstcAdcSampCh; + break; + case AdcSQRCH8MUX: + M0P_ADC->SQR1_f.CH8MUX = enstcAdcSampCh; + break; + case AdcSQRCH9MUX: + M0P_ADC->SQR1_f.CH9MUX = enstcAdcSampCh; + break; + case AdcSQRCH10MUX: + M0P_ADC->SQR1_f.CH10MUX = enstcAdcSampCh; + break; + case AdcSQRCH11MUX: + M0P_ADC->SQR1_f.CH11MUX = enstcAdcSampCh; + break; + case AdcSQRCH12MUX: + M0P_ADC->SQR2_f.CH12MUX = enstcAdcSampCh; + break; + case AdcSQRCH13MUX: + M0P_ADC->SQR2_f.CH13MUX = enstcAdcSampCh; + break; + case AdcSQRCH14MUX: + M0P_ADC->SQR2_f.CH14MUX = enstcAdcSampCh; + break; + case AdcSQRCH15MUX: + M0P_ADC->SQR2_f.CH15MUX = enstcAdcSampCh; + break; + default: + enResult = ErrorInvalidParameter; + break; + + } + + return enResult; +} +/** + * \brief + * 配置插队扫描转换通道 + * + * \param [in]enstcAdcSqrChMux 插队扫描转换通道顺序 + * \param [in]enstcAdcSampCh 转换通道 + * + * \retval en_result_t Ok: 成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + */ +en_result_t Adc_CfgJqrChannel(en_adc_jqr_chmux_t enstcAdcJqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + en_result_t enResult = Ok; + + switch(enstcAdcJqrChMux) + { + case AdcJQRCH0MUX: + M0P_ADC->JQR_f.CH0MUX = enstcAdcSampCh; + break; + case AdcJQRCH1MUX: + M0P_ADC->JQR_f.CH1MUX = enstcAdcSampCh; + break; + case AdcJQRCH2MUX: + M0P_ADC->JQR_f.CH2MUX = enstcAdcSampCh; + break; + case AdcJQRCH3MUX: + M0P_ADC->JQR_f.CH3MUX = enstcAdcSampCh; + break; + default: + enResult = ErrorInvalidParameter; + break; + } + + return enResult; +} + +/** + * \brief + * 获取采样值 + * + * + * \retval en_result_t 采样值 + */ +uint32_t Adc_GetSglResult(void) +{ + return M0P_ADC->RESULT; +} + +/** + * \brief + * 获取采样值 + * + * \param [in] enstcAdcSqrChMux 顺序扫描通道序号 @ref en_adc_sqr_chmux_t + * + * \retval en_result_t 采样值 + */ +uint32_t Adc_GetSqrResult(en_adc_sqr_chmux_t enstcAdcSqrChMux) +{ + volatile uint32_t *BaseSqrResultAddress = &(M0P_ADC->SQRRESULT0); + + return *(BaseSqrResultAddress + enstcAdcSqrChMux); + +} + +/** + * \brief + * 获取插队扫描采样值 + * + * \param [in] enstcAdcJqrChMux 插队扫描通道序号@ref en_adc_jqr_chmux_t + * + * \retval en_result_t 采样值 + */ +uint32_t Adc_GetJqrResult(en_adc_jqr_chmux_t enstcAdcJqrChMux) +{ + volatile uint32_t *BaseJqrResultAddress = &(M0P_ADC->JQRRESULT0); + + return *(BaseJqrResultAddress + enstcAdcJqrChMux); + +} + +/** + * \brief + * 获取累加采样值 + * + * + * \retval en_result_t 累加采样结果 + */ +uint32_t Adc_GetAccResult(void) +{ + return M0P_ADC->RESULTACC; + +} + +/** + * \brief + * 清零累加采样值 + * + * \param 无 + * + * \retval 无 + */ +void Adc_ClrAccResult(void) +{ + M0P_ADC->CR1_f.RACCCLR = 0u; +} + +/** + * \brief + * ADC比较使能(比较中断) + * + * \param [in] pstcAdcIrqCfg ADC比较配置 @ref stc_adc_threshold_cfg_t + * + * \retval 无 + */ + +void Adc_ThresholdCfg(stc_adc_threshold_cfg_t* pstcAdcThrCfg) +{ + M0P_ADC->HT = pstcAdcThrCfg->u32AdcHighThd; + M0P_ADC->LT = pstcAdcThrCfg->u32AdcLowThd; + + M0P_ADC->CR1_f.THCH = pstcAdcThrCfg->enSampChSel; + + M0P_ADC->CR1_f.REGCMP = pstcAdcThrCfg->bAdcRegCmp; + M0P_ADC->CR1_f.HTCMP = pstcAdcThrCfg->bAdcHtCmp; + M0P_ADC->CR1_f.LTCMP = pstcAdcThrCfg->bAdcLtCmp; + +} + + +//@} // AdcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_adt.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_adt.c new file mode 100644 index 0000000000..8e270ad4f5 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_adt.c @@ -0,0 +1,1657 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adt.c + ** + ** Low Voltage Detect driver API. + ** @link Lvd Group Some description @endlink + ** + ** - 2019-04-19 Husj First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "hc32l196_adt.h" + +/** + ****************************************************************************** + ** \addtogroup AdtGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_ADT_STATE(x) ( AdtCMAF == (x)||\ + AdtCMBF == (x)||\ + AdtCMCF == (x)||\ + AdtCMDF == (x)||\ + AdtOVFF == (x)||\ + AdtUDFF == (x)||\ + AdtDTEF == (x)||\ + AdtCMSAUF == (x)||\ + AdtCMSADF == (x)||\ + AdtCMSBUF == (x)||\ + AdtCMSBDF == (x)||\ + AdtCntDir == (x) ) +#define ADTIM_HW_STASTPCLR_EN 31 +#define ADTIM_HW_STASTPCLR_DIS 0x7FFFFFFF +#define ADTIM_SS_TIM4 1 +#define ADTIM_SS_TIM5 2 +#define ADTIM_SS_TIM6 4 +#define ADTIM_PORT_BKE_NUM 15 +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + + + +/***************************************************************** + * \brief + * 配置中断 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtIrq 中断类型 + * \param [in] bEn 中断使能/禁止 + * + * \retval en_result_t Ok: 配置成功 + * + ****************************************************************/ +en_result_t Adt_CfgIrq(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq, + boolean_t bEn) +{ + uint32_t u32Val; + + u32Val = ADTx->ICONR; + if (bEn) + { + u32Val |= 1u<ICONR = u32Val; + return Ok; +} + +/******************************************************************* + * \brief + * 获取中断标志 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtIrq 中断类型 + * + * + * \retval TRUE/FALSE + * + *****************************************************************/ +boolean_t Adt_GetIrqFlag(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq) +{ + uint32_t u32Val; + boolean_t bEn; + + ASSERT(IS_VALID_ADT_UNIT(enAdtUnit)); + + u32Val = ADTx->IFR; + bEn = (u32Val>>enAdtIrq) & 0x1; + + return bEn; +} + +/**************************************************************** + * \brief + * 清除中断标志 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtIrq 中断类型 + * + * \retval en_result_t Ok: 配置成功 + * + ****************************************************************/ +en_result_t Adt_ClearIrqFlag(M0P_ADTIM_TypeDef *ADTx, + en_adt_irq_type_t enAdtIrq) +{ + ADTx->ICLR = ~(1u<ICLR = 0; + return Ok; +} + +/************************************************************** + * \brief + * 配置硬件递加事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtHwCntUp 硬件递加事件 + * + * \retval en_result_t Ok: 设置成功 + * + ****************************************************************/ +en_result_t Adt_CfgHwCntUp(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_cnt_t enAdtHwCntUp) +{ + uint32_t u32Val; + + + if (AdtHwCntMax <= enAdtHwCntUp) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCUPR; + ADTx->HCUPR = u32Val | (1u<HCUPR = 0; + return Ok; +} + + +/********************************************************** + * \brief + * 配置硬件递减事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtHwCntDwn 硬件递减事件 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ***********************************************************/ +en_result_t Adt_CfgHwCntDwn(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_cnt_t enAdtHwCntDwn) +{ + uint32_t u32Val; + + + if(AdtHwCntMax <= enAdtHwCntDwn) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCDOR; + ADTx->HCDOR = u32Val | (1u<HCDOR = 0; + return Ok; +} + +/****************************************************************** + * \brief + * 配置硬件启动事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtHwStart 硬件启动事件 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *******************************************************************/ +en_result_t Adt_CfgHwStart(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwStart) +{ + uint32_t u32Val; + + + if(AdtHwTrigEnd <= enAdtHwStart) + { + return ErrorInvalidParameter; + } + u32Val = ADTx->HSTAR; + ADTx->HSTAR = u32Val | (1u<HSTAR = 0; + return Ok; +} + +/********************************************************************* + * \brief + * 使能硬件启动 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 设置成功 + * + *********************************************************************/ +en_result_t Adt_EnableHwStart(M0P_ADTIM_TypeDef *ADTx) +{ + uint32_t u32Val; + + u32Val = ADTx->HSTAR; + ADTx->HSTAR = u32Val | (1u<HSTAR; + ADTx->HSTAR = u32Val & ADTIM_HW_STASTPCLR_DIS; + return Ok; +} + +/**************************************************************** + * \brief + * 配置硬件停止事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtHwStop 硬件停止事件 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ***************************************************************/ +en_result_t Adt_CfgHwStop(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwStop) +{ + uint32_t u32Val; + + if(AdtHwTrigEnd <= enAdtHwStop) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HSTPR; + ADTx->HSTPR = u32Val | (1u<HSTPR = 0; + return Ok; +} + +/************************************************************* + * \brief + * 使能硬件停止 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 设置成功 + * + **********************************************************/ +en_result_t Adt_EnableHwStop(M0P_ADTIM_TypeDef *ADTx) +{ + uint32_t u32Val; + + u32Val = ADTx->HSTPR; + ADTx->HSTPR = u32Val | (1u<HSTPR; + ADTx->HSTPR = u32Val & ADTIM_HW_STASTPCLR_DIS; + return Ok; +} + +/************************************************************************** + * \brief + * 配置硬件清零事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtHwClear 硬件清零事件 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *************************************************************************/ +en_result_t Adt_CfgHwClear(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwClear) +{ + uint32_t u32Val; + + + if(AdtHwTrigEnd <= enAdtHwClear) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCELR; + ADTx->HCELR = u32Val | (1u<HCELR = 0; + return Ok; +} + +/*************************************************************************** + * \brief + * 使能硬件清零 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 设置成功 + * + *************************************************************************/ +en_result_t Adt_EnableHwClear(M0P_ADTIM_TypeDef *ADTx) +{ + uint32_t u32Val; + + u32Val = ADTx->HCELR; + ADTx->HCELR = u32Val | (1u<HCELR; + ADTx->HCELR = u32Val & ADTIM_HW_STASTPCLR_DIS; + return Ok; +} + +/******************************************************************* + * \brief + * 配置硬件捕获A事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtHwCaptureA 硬件捕获A事件选择 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *******************************************************************/ +en_result_t Adt_CfgHwCaptureA(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwCaptureA) +{ + uint32_t u32Val; + + + if(AdtHwTrigEnd <= enAdtHwCaptureA) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCPAR; + ADTx->HCPAR = u32Val | (1u<PCONR_f.CAPCA = 1; + return Ok; +} + +/************************************************************************ + * \brief + * 清除硬件捕获A事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 设置成功 + * + ***********************************************************************/ +en_result_t Adt_ClearHwCaptureA(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->HCPAR = 0; + return Ok; +} + +/********************************************************************* + * \brief + * 配置硬件捕获B事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtHwCaptureB 硬件捕获B事件选择 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ********************************************************************/ +en_result_t Adt_CfgHwCaptureB(M0P_ADTIM_TypeDef *ADTx, en_adt_hw_trig_t enAdtHwCaptureB) +{ + uint32_t u32Val; + + + if(AdtHwTrigEnd <= enAdtHwCaptureB) + { + return ErrorInvalidParameter; + } + + u32Val = ADTx->HCPBR; + ADTx->HCPBR = u32Val | (1u<PCONR_f.CAPCB = 1; + return Ok; +} + +/******************************************************************** + * \brief + * 清除硬件捕获B事件 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 设置成功 + * + *******************************************************************/ +en_result_t Adt_ClearHwCaptureB(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->HCPBR = 0; + return Ok; +} + +/***************************************************************** + * \brief + * 软件同步开始 + * + * \param [in] pstcAdtSwSyncStart 软件同步开始指针 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ***************************************************************/ +en_result_t Adt_SwSyncStart(stc_adt_sw_sync_t* pstcAdtSwSyncStart) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncStart) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncStart->bAdTim4) + { + u32Val |= ADTIM_SS_TIM4; + } + if (pstcAdtSwSyncStart->bAdTim5) + { + u32Val |= ADTIM_SS_TIM5; + } + if (pstcAdtSwSyncStart->bAdTim6) + { + u32Val |= ADTIM_SS_TIM6; + } + + M0P_ADTIM4->SSTAR = u32Val; + return Ok; +} + +/*************************************************************** + * \brief + * 软件同步停止 + * + * \param [in] pstcAdtSwSyncStop 软件同步停止指针 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ***************************************************************/ +en_result_t Adt_SwSyncStop(stc_adt_sw_sync_t* pstcAdtSwSyncStop) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncStop) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncStop->bAdTim4) + { + u32Val |= ADTIM_SS_TIM4; + } + if (pstcAdtSwSyncStop->bAdTim5) + { + u32Val |= ADTIM_SS_TIM5; + } + if (pstcAdtSwSyncStop->bAdTim6) + { + u32Val |= ADTIM_SS_TIM6; + } + + M0P_ADTIM4->SSTPR = u32Val; + return Ok; +} + +/***************************************************************** + * \brief + * 软件同步清零 + * + * \param [in] pstcAdtSwSyncClear 软件同步清零指针 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *******************************************************************/ +en_result_t Adt_SwSyncClear(stc_adt_sw_sync_t* pstcAdtSwSyncClear) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncClear) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncClear->bAdTim4) + { + u32Val |= ADTIM_SS_TIM4; + } + if (pstcAdtSwSyncClear->bAdTim5) + { + u32Val |= ADTIM_SS_TIM5; + } + if (pstcAdtSwSyncClear->bAdTim6) + { + u32Val |= ADTIM_SS_TIM6; + } + + M0P_ADTIM4->SCLRR = u32Val; + return Ok; +} + +/******************************************************************* + * \brief + * 获取软件同步运行状态 + * + * \param [in] pstcAdtSwSyncState ADV Timer软件同步运行状态指针 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *******************************************************************/ +en_result_t Adt_GetSwSyncState(stc_adt_sw_sync_t* pstcAdtSwSyncState) +{ + if (NULL == pstcAdtSwSyncState) + { + return ErrorInvalidParameter; + } + + if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM4) + { + pstcAdtSwSyncState->bAdTim4 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim4 = FALSE; + } + if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM5) + { + pstcAdtSwSyncState->bAdTim5 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim5 = FALSE; + } + if (M0P_ADTIM4->SSTAR & ADTIM_SS_TIM6) + { + pstcAdtSwSyncState->bAdTim6 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim6 = FALSE; + } + return Ok; +} + +/************************************************************************ + * \brief + * AOS触发配置 + * + * \param [in] pstcAdtAosTrigCfg 触发配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ************************************************************************/ +en_result_t Adt_AosTrigCfg(stc_adt_aos_trig_cfg_t* pstcAdtAosTrigCfg) +{ + if (NULL == pstcAdtAosTrigCfg) + { + return ErrorInvalidParameter; + } + + M0P_ADTIM4->ITRIG_f.IAOS0S = pstcAdtAosTrigCfg->enAos0TrigSrc; + M0P_ADTIM4->ITRIG_f.IAOS1S = pstcAdtAosTrigCfg->enAos1TrigSrc; + M0P_ADTIM4->ITRIG_f.IAOS2S = pstcAdtAosTrigCfg->enAos2TrigSrc; + M0P_ADTIM4->ITRIG_f.IAOS3S = pstcAdtAosTrigCfg->enAos3TrigSrc; + return Ok; +} + +/********************************************************************** + * \brief + * 中断触发配置 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] pstcAdtIrqTrigCfg 触发配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ***********************************************************************/ +en_result_t Adt_IrqTrigCfg(M0P_ADTIM_TypeDef *ADTx, + stc_adt_irq_trig_cfg_t* pstcAdtIrqTrigCfg) +{ + if(NULL == pstcAdtIrqTrigCfg) + { + return ErrorInvalidParameter; + } + + ADTx->CR_f.CMAE = pstcAdtIrqTrigCfg->bAdtCntMatchATrigEn; + ADTx->CR_f.CMBE = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigEn; + ADTx->CR_f.CMCE = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigEn; + ADTx->CR_f.CMDE = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigEn; + ADTx->CR_f.OVFE = pstcAdtIrqTrigCfg->bAdtOverFlowTrigEn; + ADTx->CR_f.UDFE = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigEn; + ADTx->CR_f.DMA_G_CMA = pstcAdtIrqTrigCfg->bAdtCntMatchATrigDmaEn; + ADTx->CR_f.DMA_G_CMB = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigDmaEn; + ADTx->CR_f.DMA_G_CMC = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigDmaEn; + ADTx->CR_f.DMA_G_CMD = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigDmaEn; + ADTx->CR_f.DMA_G_OVF = pstcAdtIrqTrigCfg->bAdtOverFlowTrigDmaEn; + ADTx->CR_f.DMA_G_UDF = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigDmaEn; + ADTx->CR_f.DMA_S_CMA = pstcAdtIrqTrigCfg->bAdtSpecilMatchATrigDmaEn; + ADTx->CR_f.DMA_S_CMB = pstcAdtIrqTrigCfg->bAdtSpecilMatchBTrigDmaEn; + + return Ok; +} + +/************************************************************************* + * \brief + * 端口触发配置 + * + * \param [in] enAdtTrigPort 触发端口 + * \param [in] pstcAdtPortTrigCfg 触发配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *************************************************************************/ +en_result_t Adt_PortTrigCfg(en_adt_trig_port_t enAdtTrigPort, + stc_adt_port_trig_cfg_t* pstcAdtPortTrigCfg) +{ + if (NULL == pstcAdtPortTrigCfg) + { + return ErrorInvalidParameter; + } + + switch (enAdtTrigPort) + { + case AdtTrigA: + M0P_ADTIM4->TTRIG_f.TRIGAS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_ADTIM4->FCONR_f.NOFIENTA = pstcAdtPortTrigCfg->bFltEn; + M0P_ADTIM4->FCONR_f.NOFICKTA = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigB: + M0P_ADTIM4->TTRIG_f.TRIGBS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_ADTIM4->FCONR_f.NOFIENTB = pstcAdtPortTrigCfg->bFltEn; + M0P_ADTIM4->FCONR_f.NOFICKTB = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigC: + M0P_ADTIM4->TTRIG_f.TRIGCS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_ADTIM4->FCONR_f.NOFIENTC = pstcAdtPortTrigCfg->bFltEn; + M0P_ADTIM4->FCONR_f.NOFICKTC = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigD: + M0P_ADTIM4->TTRIG_f.TRIGDS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_ADTIM4->FCONR_f.NOFIENTD = pstcAdtPortTrigCfg->bFltEn; + M0P_ADTIM4->FCONR_f.NOFICKTD = pstcAdtPortTrigCfg->enFltClk; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * CHxX端口配置 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtCHxXPort CHxX端口 + * \param [in] pstcAdtCHxXCfg CHxX端口配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *********************************************************************/ +en_result_t Adt_CHxXPortCfg(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + stc_adt_CHxX_port_cfg_t* pstcAdtCHxXCfg) +{ + if(NULL == pstcAdtCHxXCfg) + { + return ErrorInvalidParameter; + } + + switch (enAdtCHxXPort) + { + case AdtCHxA: + ADTx->PCONR_f.CAPCA = pstcAdtCHxXCfg->enCap; + ADTx->PCONR_f.STACA = pstcAdtCHxXCfg->enStaOut; + ADTx->PCONR_f.STPCA = pstcAdtCHxXCfg->enStpOut; + ADTx->PCONR_f.STASTPSA = pstcAdtCHxXCfg->enStaStp; + ADTx->PCONR_f.CMPCA = pstcAdtCHxXCfg->enCmpc; + ADTx->PCONR_f.PERCA = pstcAdtCHxXCfg->enPerc; + ADTx->PCONR_f.OUTENA = pstcAdtCHxXCfg->bOutEn; + ADTx->PCONR_f.DISSELA = pstcAdtCHxXCfg->enDisSel; + ADTx->PCONR_f.DISVALA = pstcAdtCHxXCfg->enDisVal; + ADTx->FCONR_f.NOFIENGA = pstcAdtCHxXCfg->bFltEn; + ADTx->FCONR_f.NOFICKGA = pstcAdtCHxXCfg->enFltClk; + break; + + case AdtCHxB: + ADTx->PCONR_f.CAPCB = pstcAdtCHxXCfg->enCap; + ADTx->PCONR_f.STACB = pstcAdtCHxXCfg->enStaOut; + ADTx->PCONR_f.STPCB = pstcAdtCHxXCfg->enStpOut; + ADTx->PCONR_f.STASTPSB = pstcAdtCHxXCfg->enStaStp; + ADTx->PCONR_f.CMPCB = pstcAdtCHxXCfg->enCmpc; + ADTx->PCONR_f.PERCB = pstcAdtCHxXCfg->enPerc; + ADTx->PCONR_f.OUTENB = pstcAdtCHxXCfg->bOutEn; + ADTx->PCONR_f.DISSELB = pstcAdtCHxXCfg->enDisSel; + ADTx->PCONR_f.DISVALB = pstcAdtCHxXCfg->enDisVal; + ADTx->FCONR_f.NOFIENGB = pstcAdtCHxXCfg->bFltEn; + ADTx->FCONR_f.NOFICKGB = pstcAdtCHxXCfg->enFltClk; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/************************************************************************ + * \brief + * 使能端口刹车 + * + * \param [in] port 端口 + * \param [in] pstcAdtBrkPtCfg 端口刹车配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ************************************************************************/ +en_result_t Adt_EnableBrakePort(uint8_t port, stc_adt_break_port_cfg_t* pstcAdtBrkPtCfg) +{ + uint32_t u32Val; + + if (NULL == pstcAdtBrkPtCfg) + { + return ErrorInvalidParameter; + } + + u32Val = M0P_ADTIM4->PTBKP; + u32Val &= ~(1u<PTBKP = u32Val | (pstcAdtBrkPtCfg->enPol<PTBKS; + M0P_ADTIM4->PTBKS = u32Val | (1u<PTBKS = 0; +} + +/********************************************************************* + * \brief + * 无效条件3配置 + * + * \param [in] pstcAdtDisable3 无效条件3配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ********************************************************************/ +en_result_t Adt_Disable3Cfg(stc_adt_disable_3_cfg_t* pstcAdtDisable3) +{ + uint8_t i; + + if (NULL == pstcAdtDisable3) + { + return ErrorInvalidParameter; + } + + Adt_ClearBrakePort(); + for (i = 0; i <= ADTIM_PORT_BKE_NUM; i++) + { + if (TRUE == pstcAdtDisable3->stcBrkPtCfg[i].bPortEn) + { + Adt_EnableBrakePort(i, &pstcAdtDisable3->stcBrkPtCfg[i]); + } + } + + M0P_ADTIM4->AOSSR_f.BFILTEN = pstcAdtDisable3->bFltEn; + M0P_ADTIM4->AOSSR_f.BFILTS = pstcAdtDisable3->enFltClk; + + return Ok; +} + +/********************************************************************* + * \brief 软件刹车 Enable/Disable(仅适用于无效条件3使能的情况下) + * + * \param [in] bSwBrk 软件刹车使能/禁止 + * + * \retval en_result_t Ok: 配置成功 + ********************************************************************/ +en_result_t Adt_SwBrake(boolean_t bSwBrk) +{ + M0P_ADTIM4->AOSSR_f.SOFTBK = bSwBrk; + + return Ok; +} + +/******************************************************************* + * \brief + * 获取端口刹车标志 + * + * \param none + * + * \retval TRUE or FALSE + ******************************************************************/ +boolean_t Adt_GetPortBrakeFlag(void) +{ + return M0P_ADTIM4->AOSSR_f.FBRAKE; +} + +/****************************************************************** + * \brief + * 清除端口刹车标志 + * + * \param none + * + * \retval none + ******************************************************************/ +void Adt_ClearPortBrakeFlag(void) +{ + M0P_ADTIM4->AOSCL_f.FBRAKE = 0; +} + +/******************************************************************** + * \brief + * 无效条件1配置 + * + * \param [in] pstcAdtDisable1 无效条件1配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ********************************************************************/ +en_result_t Adt_Disable1Cfg(stc_adt_disable_1_cfg_t* pstcAdtDisable1) +{ + + if (NULL == pstcAdtDisable1) + { + return ErrorInvalidParameter; + } + + M0P_ADTIM4->AOSSR_f.SMH2 = pstcAdtDisable1->bTim6OutSH; + M0P_ADTIM4->AOSSR_f.SMH1 = pstcAdtDisable1->bTim5OutSH; + M0P_ADTIM4->AOSSR_f.SMH0 = pstcAdtDisable1->bTim4OutSH; + M0P_ADTIM4->AOSSR_f.SML2 = pstcAdtDisable1->bTim6OutSL; + M0P_ADTIM4->AOSSR_f.SML1 = pstcAdtDisable1->bTim5OutSL; + M0P_ADTIM4->AOSSR_f.SML0 = pstcAdtDisable1->bTim4OutSL; + + return Ok; +} + +/******************************************************************** + * \brief + * 获取同高同低刹车标志 + * + * \param none + * + * \retval TRUE or FALSE + ********************************************************************/ +boolean_t Adt_GetSameBrakeFlag(void) +{ + return M0P_ADTIM4->AOSSR_f.FSAME; +} + +/********************************************************************* + * \brief + * 清除同高同低刹车标志 + * + * \param none + * + * \retval none + *********************************************************************/ +void Adt_ClearSameBrakeFlag(void) +{ + M0P_ADTIM4->AOSCL_f.FSAME = 0; +} + +/******************************************************************** + * \brief + * PWM展频配置 + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] pstcAdtPwmDitherCfg PWM展频配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *********************************************************************/ +en_result_t Adt_PwmDitherCfg(M0P_ADTIM_TypeDef *ADTx, stc_adt_pwm_dither_cfg_t* pstcAdtPwmDitherCfg) +{ + + + if (NULL == pstcAdtPwmDitherCfg) + { + return ErrorInvalidParameter; + } + + ADTx->CR_f.DITENS = pstcAdtPwmDitherCfg->enAdtPDType; + ADTx->CR_f.DITENB = pstcAdtPwmDitherCfg->bTimxBPDEn; + ADTx->CR_f.DITENA = pstcAdtPwmDitherCfg->bTimxAPDEn; + + return Ok; +} + +/********************************************************************** + * \brief + * ADT初始化 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] pstcAdtBaseCntCfg 计数配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + **********************************************************************/ +en_result_t Adt_Init(M0P_ADTIM_TypeDef *ADTx, stc_adt_basecnt_cfg_t* pstcAdtBaseCntCfg) +{ + + + if(NULL == pstcAdtBaseCntCfg) + { + return ErrorInvalidParameter; + } + + if (AdtTriangleModeB < pstcAdtBaseCntCfg->enCntMode) + { + return ErrorInvalidParameter; + } + + ADTx->GCONR_f.MODE = pstcAdtBaseCntCfg->enCntMode; + ADTx->GCONR_f.DIR = pstcAdtBaseCntCfg->enCntDir; + ADTx->GCONR_f.CKDIV = pstcAdtBaseCntCfg->enCntClkDiv; + + return Ok; +} + +/************************************************************************ + * \brief + * ADT Deinit + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 配置成功 + * + ***********************************************************************/ +en_result_t Adt_DeInit(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->GCONR_f.START = 0; + ADTx->CNTER = 0; + ADTx->PCONR = 0; + ADTx->GCONR = 0x00000100; + ADTx->DCONR = 0; + ADTx->ICONR = 0; + ADTx->BCONR = 0; + ADTx->FCONR = 0; + ADTx->VPERR = 0; + ADTx->PERAR = 0xFFFF; + ADTx->PERBR = 0xFFFF; + ADTx->GCMAR = 0xFFFF; + ADTx->GCMBR = 0xFFFF; + ADTx->GCMCR = 0xFFFF; + ADTx->GCMDR = 0xFFFF; + ADTx->DTDAR = 0xFFFF; + ADTx->DTUAR = 0xFFFF; + ADTx->HSTAR = 0; + ADTx->HSTPR = 0; + ADTx->HCELR = 0; + ADTx->HCPAR = 0; + ADTx->HCPBR = 0; + ADTx->HCUPR = 0; + ADTx->HCDOR = 0; + ADTx->SSTAR = 0; + ADTx->SSTPR = 0; + ADTx->SCLRR = 0; + ADTx->IFR = 0; + ADTx->CR = 0x00000300; + ADTx->AOSSR = 0; + ADTx->AOSCL = 0; + ADTx->PTBKS = 0; + ADTx->PTBKP = 0; + ADTx->TTRIG = 0; + ADTx->ITRIG = 0; + + return Ok; +} + +/*********************************************************************** + * \brief + * 开始计数 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 配置成功 + * + ***********************************************************************/ +en_result_t Adt_StartCount(M0P_ADTIM_TypeDef *ADTx) +{ + + ADTx->GCONR_f.START = 1; + + return Ok; +} + +/*********************************************************************** + * \brief + * 停止计数 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 配置成功 + * + **********************************************************************/ +en_result_t Adt_StopCount(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->GCONR_f.START = 0; + + return Ok; +} + +/******************************************************************** + * \brief + * 设置计数值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] u16Value 计数值 + * + * \retval en_result_t Ok: 配置成功 + * + *******************************************************************/ +en_result_t Adt_SetCount(M0P_ADTIM_TypeDef *ADTx, uint16_t u16Value) +{ + ADTx->CNTER_f.CNT = u16Value; + return Ok; +} + +/******************************************************************** + * \brief + * 获取计数值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * + * \retval uint16_t u16Value: 当前计数值 + * + *******************************************************************/ +uint16_t Adt_GetCount(M0P_ADTIM_TypeDef *ADTx) +{ + uint16_t u16Value; + + ASSERT(IS_VALID_ADT_UNIT(enAdtUnit)); + + u16Value = ADTx->CNTER_f.CNT; + + return u16Value; +} + +/************************************************************************** + * \brief + * 清除计数值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * + * \retval en_result_t Ok: 配置成功 + * + **************************************************************************/ +en_result_t Adt_ClearCount(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->CNTER_f.CNT = 0; + return Ok; +} + +/************************************************************************* + * \brief + * 获取有效周期计数值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval uint8_t u8TempCnt: 有效周期值 + * + *************************************************************************/ +uint8_t Adt_GetVperNum(M0P_ADTIM_TypeDef *ADTx) +{ + uint8_t u8TempCnt; + + + ASSERT(IS_VALID_ADT_UNIT(enAdtUnit)); + + u8TempCnt = ADTx->STFLR_f.VPERNUM; + + return u8TempCnt; +} + +/************************************************************************* + * \brief + * 获取状态标志 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) +* \param [in] enstate 状态标志类型 + * + * \retval TURE/FALSE + * + *************************************************************************/ +boolean_t Adt_GetState(M0P_ADTIM_TypeDef *ADTx, en_adt_state_type_t enstate) +{ + + + ASSERT(IS_VALID_ADT_UNIT(enAdtUnit)); + ASSERT(IS_VALID_ADT_STATE(enstate)); + + return GetBit(((uint32_t)&ADTx->STFLR), enstate); +} + +/*********************************************************************** + * \brief + * 配置计数周期 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] u16Period 计数周期值 + * + * \retval en_result_t Ok: 配置成功 + * + ***********************************************************************/ +en_result_t Adt_SetPeriod(M0P_ADTIM_TypeDef *ADTx, uint16_t u16Period) +{ + ADTx->PERAR = u16Period; + + return Ok; +} + +/*********************************************************************** + * \brief + * 配置计数周期缓冲 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] u16PeriodBuf 计数周期缓冲值 + * + * \retval en_result_t Ok: 配置成功 + * + ***********************************************************************/ +en_result_t Adt_SetPeriodBuf(M0P_ADTIM_TypeDef *ADTx, uint16_t u16PeriodBuf) +{ + ADTx->PERBR = u16PeriodBuf; + ADTx->BCONR_f.BENP = 1u; + + return Ok; +} + +/********************************************************************** + * \brief + * 清除计数周期缓冲 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * + * \retval en_result_t Ok: 配置成功 + * + **********************************************************************/ +en_result_t Adt_ClearPeriodBuf(M0P_ADTIM_TypeDef *ADTx) +{ + ADTx->BCONR_f.BENP = 0; + ADTx->PERBR = 0; + + return Ok; +} + +/*********************************************************************** + * \brief + * 配置有效计数周期 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] pstcAdtValidPerCfg 有效计数周期配置指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ***********************************************************************/ +en_result_t Adt_SetValidPeriod(M0P_ADTIM_TypeDef *ADTx, + stc_adt_validper_cfg_t* pstcAdtValidPerCfg) +{ + + + if(NULL == pstcAdtValidPerCfg) + { + return ErrorInvalidParameter; + } + + ADTx->VPERR_f.PCNTS = pstcAdtValidPerCfg->enValidCnt; + ADTx->VPERR_f.PCNTE = pstcAdtValidPerCfg->enValidCdt; + ADTx->VPERR_f.GEPERID = pstcAdtValidPerCfg->bPeriodD; + ADTx->VPERR_f.GEPERIC = pstcAdtValidPerCfg->bPeriodC; + ADTx->VPERR_f.GEPERIB = pstcAdtValidPerCfg->bPeriodB; + ADTx->VPERR_f.GEPERIA = pstcAdtValidPerCfg->bPeriodA; + + return Ok; +} + +/************************************************************************ + * \brief + * 配置比较输出计数基准值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtCompare 通用比较基准寄存器 + * \param [in] u16Compare 比较基准值 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *************************************************************************/ +en_result_t Adt_SetCompareValue(M0P_ADTIM_TypeDef *ADTx, + en_adt_compare_t enAdtCompare, + uint16_t u16Compare) +{ + if (AdtCompareA == enAdtCompare) + { + ADTx->GCMAR = u16Compare; + } + else if (AdtCompareB == enAdtCompare) + { + ADTx->GCMBR = u16Compare; + } + else if (AdtCompareC == enAdtCompare) + { + ADTx->GCMCR = u16Compare; + } + else if (AdtCompareD == enAdtCompare) + { + ADTx->GCMDR = u16Compare; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/************************************************************************ + * \brief + * 配置专用比较计数基准值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtSpclCmp 专用比较基准值寄存器 + * \param [in] u16SpclCmp 比较基准值 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + *************************************************************************/ +en_result_t Adt_SetSpecilCompareValue(M0P_ADTIM_TypeDef *ADTx, + en_adt_special_compare_t enAdtSpclCmp, + uint16_t u16SpclCmp) +{ + if (AdtSpclCompA == enAdtSpclCmp) + { + ADTx->SCMAR_f.SCMA = u16SpclCmp; + } + else if (AdtSpclCompB == enAdtSpclCmp) + { + ADTx->SCMBR_f.SCMB = u16SpclCmp; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/********************************************************************** + * \brief + * 配置通用比较值/捕获值缓存传送 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtCHxXPort TIMxX通道 + * \param [in] bCompareBufEn 通用比较值缓存传送使能 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + **********************************************************************/ +en_result_t Adt_EnableValueBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + boolean_t bCompareBufEn) +{ + if (AdtCHxA == enAdtCHxXPort) + { + ADTx->BCONR_f.BENA = bCompareBufEn; + } + else if (AdtCHxB == enAdtCHxXPort) + { + ADTx->BCONR_f.BENB = bCompareBufEn; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 清除比较输出计数值/捕获值缓存 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtCHxXPort TIMxX通道 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + **********************************************************************/ +en_result_t Adt_ClearValueBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort) +{ + if (AdtCHxA == enAdtCHxXPort) + { + ADTx->GCMCR = 0; + } + else if (AdtCHxB == enAdtCHxXPort) + { + ADTx->GCMDR = 0; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 获取捕获值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtCHxXPort TIMxX通道 + * \param [in] pu16Capture 捕获值指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ***********************************************************************/ +en_result_t Adt_GetCaptureValue(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16Capture) +{ + if (AdtCHxA == enAdtCHxXPort) + { + *pu16Capture = ADTx->GCMAR_f.GCMA; + } + else if (AdtCHxB == enAdtCHxXPort) + { + *pu16Capture = ADTx->GCMBR_f.GCMB; + } + else + { + return ErrorInvalidParameter; + } + return Ok; +} + +/********************************************************************** + * \brief + * 获取捕获缓存值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] enAdtCHxXPort TIMxX通道 + * \param [in] pu16CaptureBuf 捕获缓存值指针 + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + ***********************************************************************/ +en_result_t Adt_GetCaptureBuf(M0P_ADTIM_TypeDef *ADTx, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16CaptureBuf) +{ + if (AdtCHxA == enAdtCHxXPort) + { + *pu16CaptureBuf = ADTx->GCMCR_f.GCMC; + } + else if (AdtCHxB == enAdtCHxXPort) + { + *pu16CaptureBuf = ADTx->GCMDR_f.GCMD; + } + else + { + return ErrorInvalidParameter; + } + return Ok; +} + +/*********************************************************************** + * \brief + * 设置死区时间上基准值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] u16Value 死区时间上基准值 + * + * \retval en_result_t Ok: 配置成功 + * + ************************************************************************/ +en_result_t Adt_SetDTUA(M0P_ADTIM_TypeDef *ADTx, + uint16_t u16Value) +{ + ADTx->DTUAR = u16Value; + + return Ok; +} + +/*********************************************************************** + * \brief + * 设置死区时间下基准值 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] u16Value 死区时间下基准值 + * + * \retval en_result_t Ok: 配置成功 + * + ***********************************************************************/ +en_result_t Adt_SetDTDA(M0P_ADTIM_TypeDef *ADTx, + uint16_t u16Value) +{ + ADTx->DTDAR = u16Value; + + return Ok; +} + +/****************************************************************** + * \brief + * 配置死区时间功能 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] bDTEn 死区功能使能 + * \param [in] bEqual DTDAR的值和DTUAR的值自动相等 + * + * \retval en_result_t Ok: 配置成功 + * + *****************************************************************/ +en_result_t Adt_CfgDT(M0P_ADTIM_TypeDef *ADTx, + boolean_t bDTEn, + boolean_t bEqual) +{ + ADTx->DCONR_f.DTCEN = bDTEn; + ADTx->DCONR_f.SEPA = bEqual; + + return Ok; +} + +/************************************************************************* + * \brief + * Z相输入屏蔽设置 + * + * \param [in] ADTx ADV Timer通道选择(M0P_ADTIM4、M0P_ADTIM5、M0P_ADTIM6) + * \param [in] pstcAdtZMaskCfg Z相输入屏蔽功能配置指针 + * + * \retval en_result_t Ok: 配置成功 + * + *************************************************************************/ +en_result_t Adt_CfgZMask(M0P_ADTIM_TypeDef *ADTx, stc_adt_zmask_cfg_t* pstcAdtZMaskCfg) +{ + if(NULL == pstcAdtZMaskCfg) + { + return ErrorInvalidParameter; + } + + ADTx->GCONR_f.ZMSK = pstcAdtZMaskCfg->enZMaskCycle; + ADTx->GCONR_f.ZMSKPOS = pstcAdtZMaskCfg->bFltPosCntMaksEn; + ADTx->GCONR_f.ZMSKREV = pstcAdtZMaskCfg->bFltRevCntMaksEn; + + return Ok; +} + +//@} // AdtGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_aes.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_aes.c new file mode 100644 index 0000000000..6ad7b95d34 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_aes.c @@ -0,0 +1,206 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file aes.c + ** + ** Common API of AES. + ** @link AesGroup Some description @endlink + ** + ** - 2019-04-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_aes.h" +/** + ******************************************************************************* + ** \addtogroup AesGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * \brief + * AES 加密 + * + * \param [in] pstcAesCfg AES 配置结构体 @ref stc_aes_cfg_t + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + */ +en_result_t AES_Encrypt(stc_aes_cfg_t* pstcAesCfg) +{ + if (NULL == pstcAesCfg) + { + return ErrorInvalidParameter; + } + + M0P_AES->CR_f.KEYSIZE = pstcAesCfg->enKeyLen; + + //Key cfg + M0P_AES->KEY0 = pstcAesCfg->pu32Key[0]; + M0P_AES->KEY1 = pstcAesCfg->pu32Key[1]; + M0P_AES->KEY2 = pstcAesCfg->pu32Key[2]; + M0P_AES->KEY3 = pstcAesCfg->pu32Key[3]; + + if(AesKey192 == pstcAesCfg->enKeyLen) + { + M0P_AES->KEY4 = pstcAesCfg->pu32Key[4]; + M0P_AES->KEY5 = pstcAesCfg->pu32Key[5]; + } + + if(AesKey256 == pstcAesCfg->enKeyLen) + { + M0P_AES->KEY4 = pstcAesCfg->pu32Key[4]; + M0P_AES->KEY5 = pstcAesCfg->pu32Key[5]; + M0P_AES->KEY6 = pstcAesCfg->pu32Key[6]; + M0P_AES->KEY7 = pstcAesCfg->pu32Key[7]; + } + + //Data cfg + M0P_AES->DATA0 = pstcAesCfg->pu32Plaintext[0]; + M0P_AES->DATA1 = pstcAesCfg->pu32Plaintext[1]; + M0P_AES->DATA2 = pstcAesCfg->pu32Plaintext[2]; + M0P_AES->DATA3 = pstcAesCfg->pu32Plaintext[3]; + + M0P_AES->CR_f.MODE = 0;//Encry + M0P_AES->CR_f.START = 1; + while(M0P_AES->CR_f.START == 1) + { + ; + } + pstcAesCfg->pu32Cipher[0] = M0P_AES->DATA0; + pstcAesCfg->pu32Cipher[1] = M0P_AES->DATA1; + pstcAesCfg->pu32Cipher[2] = M0P_AES->DATA2; + pstcAesCfg->pu32Cipher[3] = M0P_AES->DATA3; + return Ok; +} + + +/** + * \brief + * AES 解密 + * + * \param [in] pstcAesCfg AES 配置结构体 @ref stc_aes_cfg_t + * + * \retval en_result_t Ok: 配置成功 + * \retval en_result_t ErrorInvalidParameter: 无效参数 + */ +en_result_t AES_Decrypt(stc_aes_cfg_t* pstcAesCfg) +{ + if (NULL == pstcAesCfg) + { + return ErrorInvalidParameter; + } + + M0P_AES->CR_f.KEYSIZE = pstcAesCfg->enKeyLen; + + //Key cfg + M0P_AES->KEY0 = pstcAesCfg->pu32Key[0]; + M0P_AES->KEY1 = pstcAesCfg->pu32Key[1]; + M0P_AES->KEY2 = pstcAesCfg->pu32Key[2]; + M0P_AES->KEY3 = pstcAesCfg->pu32Key[3]; + + if(AesKey192 == pstcAesCfg->enKeyLen) + { + M0P_AES->KEY4 = pstcAesCfg->pu32Key[4]; + M0P_AES->KEY5 = pstcAesCfg->pu32Key[5]; + } + + if(AesKey256 == pstcAesCfg->enKeyLen) + { + M0P_AES->KEY4 = pstcAesCfg->pu32Key[4]; + M0P_AES->KEY5 = pstcAesCfg->pu32Key[5]; + M0P_AES->KEY6 = pstcAesCfg->pu32Key[6]; + M0P_AES->KEY7 = pstcAesCfg->pu32Key[7]; + } + + //Data cfg + M0P_AES->DATA0 = pstcAesCfg->pu32Cipher[0]; + M0P_AES->DATA1 = pstcAesCfg->pu32Cipher[1]; + M0P_AES->DATA2 = pstcAesCfg->pu32Cipher[2]; + M0P_AES->DATA3 = pstcAesCfg->pu32Cipher[3]; + + M0P_AES->CR_f.MODE = 1;//UnEncry + M0P_AES->CR_f.START = 1; + while(M0P_AES->CR_f.START == 1) + { + ; + } + pstcAesCfg->pu32Plaintext[0] = M0P_AES->DATA0; + pstcAesCfg->pu32Plaintext[1] = M0P_AES->DATA1; + pstcAesCfg->pu32Plaintext[2] = M0P_AES->DATA2; + pstcAesCfg->pu32Plaintext[3] = M0P_AES->DATA3; + return Ok; +} + +//@} // AesGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_bgr.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_bgr.c new file mode 100644 index 0000000000..1657ff6d55 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_bgr.c @@ -0,0 +1,143 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file bgr.c + ** + ** Common API of bgr. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_bgr.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief BGR 使能 + ** + ** + ** \retval Null + *****************************************************************************/ +void Bgr_BgrEnable(void) +{ + M0P_BGR->CR |= 0x1u; + + delay10us(2); +} + +/** + ***************************************************************************** + ** \brief BGR 禁止 + ** + ** + ** \retval Null + *****************************************************************************/ +void Bgr_BgrDisable(void) +{ + M0P_BGR->CR &= 0x2u; +} + +/** + ***************************************************************************** + ** \brief BGR 温度传感器使能(需要先开启BGR) + ** + ** + ** \retval Null + *****************************************************************************/ +void Bgr_TempSensorEnable(void) +{ + M0P_BGR->CR |= 0x2u; + + delay10us(2); +} + +/** + ***************************************************************************** + ** \brief BGR 温度传感器禁止 + ** + ** + ** \retval Null + *****************************************************************************/ +void Bgr_TempSensorDisable(void) +{ + M0P_BGR->CR &= 0x1u; +} + + +//@} // BgrGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_bt.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_bt.c new file mode 100644 index 0000000000..82852eaf8d --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_bt.c @@ -0,0 +1,1381 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file bt.c + ** + ** Common API of base timer. + ** @link btGroup Some description @endlink + ** + ** - 2019-04-15 Husj First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_bt.h" +/** + ******************************************************************************* + ** \addtogroup BtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_TIM(x) (TIM0 == (x) ||\ + TIM1 == (x) ||\ + TIM2 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Base Timer 中断标志获取(模式0/1/23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enBtIrq 中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Bt_GetIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u32Val = pstcM0PBt->IFR; + bRetVal = (u32Val>>enBtIrq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断标志清除(模式0/1/23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enBtIrq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_ClearIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ICLR = ~(1u<ICLR = 0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_EnableIrq(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断禁止(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_DisableIrq(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enBtIrq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M1CR_f.UIE = TRUE; + break; + case BtCA0Irq: + pstcM0PBt->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断禁止(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enBtIrq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M1CR_f.UIE = FALSE; + break; + case BtCA0Irq: + pstcM0PBt->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enBtIrq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M23CR_f.UIE = TRUE; + break; + case BtCA0Irq: + pstcM0PBt->CRCH0_f.CIEA = TRUE; + break; + case BtCB0Irq: + pstcM0PBt->CRCH0_f.CIEB = TRUE; + break; + case BtBkIrq: + pstcM0PBt->M23CR_f.BIE = TRUE; + break; + case BtTrigIrq: + pstcM0PBt->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断禁止(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enBtIrq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M23CR_f.UIE = FALSE; + break; + case BtCA0Irq: + pstcM0PBt->CRCH0_f.CIEA = FALSE; + break; + case BtCB0Irq: + pstcM0PBt->CRCH0_f.CIEB = FALSE; + break; + case BtBkIrq: + pstcM0PBt->M23CR_f.BIE = FALSE; + break; + case BtTrigIrq: + pstcM0PBt->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 初始化配置(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_Init(en_bt_unit_t enUnit, stc_bt_mode0_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.MODE = pstcCfg->enWorkMode; + pstcM0PBt->M0CR_f.GATEP = pstcCfg->enGateP; + pstcM0PBt->M0CR_f.GATE = pstcCfg->bEnGate; + pstcM0PBt->M0CR_f.PRS = pstcCfg->enPRS; + pstcM0PBt->M0CR_f.TOGEN = pstcCfg->bEnTog; + pstcM0PBt->M0CR_f.CT = pstcCfg->enCT; + pstcM0PBt->M0CR_f.MD = pstcCfg->enCntMode; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 启动运行(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 停止运行(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 翻转输出使能/禁止（低电平）设定(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] bEnTOG 翻转输出设定 TRUE:使能, FALSE:禁止 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_EnTOG_Output(en_bt_unit_t enUnit, boolean_t bEnTOG) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.TOGEN = bEnTOG; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 端口输出使能/禁止设定(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] bEnOutput 端口输出设定 TRUE:使能, FALSE:禁止 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Enable_Output(en_bt_unit_t enUnit, boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16位计数器初值设置(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] u16Data 16位初值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16位计数值获取(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M0_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u16CntData = pstcM0PBt->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 重载值设置(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] u16Data 16bits重载值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ARR_f.ARR = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 32位计数器初值设置(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] u32Data 32位初值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Cnt32Set(en_bt_unit_t enUnit, uint32_t u32Data) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT32_f.CNT32 = u32Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 32位计数值获取(模式0) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval 32bits计数值 + *****************************************************************************/ +uint32_t Bt_M0_Cnt32Get(en_bt_unit_t enUnit) +{ + uint32_t u32CntData = 0; + + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u32CntData = pstcM0PBt->CNT32_f.CNT32; + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 初始化配置(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_Init(en_bt_unit_t enUnit, stc_bt_mode1_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.MODE = pstcCfg->enWorkMode; + pstcM0PBt->M1CR_f.PRS = pstcCfg->enPRS; + pstcM0PBt->M1CR_f.CT = pstcCfg->enCT; + pstcM0PBt->M1CR_f.ONESHOT = pstcCfg->enOneShot; + + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWC 输入配置(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Input_Cfg(en_bt_unit_t enUnit, stc_bt_pwc_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->MSCR_f.TS = pstcCfg->enTsSel; + pstcM0PBt->MSCR_f.IA0S = pstcCfg->enIA0Sel; + pstcM0PBt->MSCR_f.IB0S = pstcCfg->enIB0Sel; + pstcM0PBt->FLTR_f.ETP = pstcCfg->enETRPhase; + pstcM0PBt->FLTR_f.FLTET = pstcCfg->enFltETR; + pstcM0PBt->FLTR_f.FLTA0 = pstcCfg->enFltIA0; + pstcM0PBt->FLTR_f.FLTB0 = pstcCfg->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWC测量边沿起始结束选择(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enEdgeSel pwc测量起始终止电平 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_PWC_Edge_Sel(en_bt_unit_t enUnit,en_bt_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enEdgeSel) + { + case 0: ///< 上升沿到上升沿(周期) + pstcM0PBt->M1CR_f.EDG1ST = 0; //上升沿 + pstcM0PBt->M1CR_f.EDG2ND = 0; //上升沿 + break; + case 1: ///< 下降沿到上升沿(低电平) + pstcM0PBt->M1CR_f.EDG1ST = 1; //下降沿 + pstcM0PBt->M1CR_f.EDG2ND = 0; //上升沿 + break; + case 2: ///< 上升沿到下降沿(高电平) + pstcM0PBt->M1CR_f.EDG1ST = 0; //上升沿 + pstcM0PBt->M1CR_f.EDG2ND = 1; //下降沿 + break; + case 3: ///< 下降沿到下降沿(周期) + pstcM0PBt->M1CR_f.EDG1ST = 1; //下降沿 + pstcM0PBt->M1CR_f.EDG2ND = 1; //下降沿 + break; + default: + ; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 启动运行(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 停止运行(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16位计数器初值设置(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] u16Data 16位初值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16位计数值获取(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M1_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u16CntData = pstcM0PBt->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 脉冲宽度测量结果数值获取(模式1) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval 16bits脉冲宽度测量结果 + *****************************************************************************/ +uint16_t Bt_M1_PWC_CapValueGet(en_bt_unit_t enUnit) +{ + uint16_t u16CapData = 0; + + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u16CapData = pstcM0PBt->CCR0A_f.CCR0A; + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 初始化配置(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_Init(en_bt_unit_t enUnit, stc_bt_mode23_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.MODE = pstcCfg->enWorkMode; + + pstcM0PBt->M23CR_f.PRS = pstcCfg->enPRS; + pstcM0PBt->M23CR_f.CT = pstcCfg->enCT; + pstcM0PBt->M23CR_f.COMP = pstcCfg->enPWMTypeSel; + pstcM0PBt->M23CR_f.PWM2S = pstcCfg->enPWM2sSel; + pstcM0PBt->M23CR_f.ONESHOT = pstcCfg->bOneShot; + pstcM0PBt->M23CR_f.URS = pstcCfg->bURSSel; + pstcM0PBt->M23CR_f.DIR = pstcCfg->enCntDir; + + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWM输出使能/禁止(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] bEnOutput PWM输出使能/禁止设定 + ** \param [in] bEnAutoOutput PWM自动输出使能/禁止设定 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnPWM_Output(en_bt_unit_t enUnit, boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.MOE = bEnOutput; + pstcM0PBt->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Base Timer 启动运行(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 停止运行(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 重载值设置(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] u16Data 16bits重载值 + ** \param [in] bArrBufEn ARR重载缓存使能TRUE/禁止FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ARR_f.ARR = u16Data; + pstcM0PBt->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16位计数器初值设置(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] u16Data 16位初值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16位计数值获取(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M23_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + u16CntData = pstcM0PBt->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 比较捕获寄存器CCR0A/CCR0B设置(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enCCRSel CCR0A/CCR0B设定 + ** \param [in] u16Data CCR0A/CCR0B 16位初始值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_CCR_Set(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + if(BtCCR0A == enCCRSel) + { + pstcM0PBt->CCR0A_f.CCR0A = u16Data; + } + else if(BtCCR0B == enCCRSel) + { + pstcM0PBt->CCR0B_f.CCR0B = u16Data; + } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 比较捕获寄存器CCR0A/CCR0B读取(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] enCCRSel CCR0A/CCR0B设定 + ** + ** \retval 16bitsCCR0A捕获值 + *****************************************************************************/ +uint16_t Bt_M23_CCR_Get(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + if(BtCCR0A == enCCRSel) + { + u16Data = pstcM0PBt->CCR0A_f.CCR0A; + } + else if(BtCCR0B == enCCRSel) + { + u16Data = pstcM0PBt->CCR0B_f.CCR0B; + } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWM互补输出模式下，GATE功能选择(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_GateFuncSel(en_bt_unit_t enUnit,stc_bt_m23_gate_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CSG = pstcCfg->enGateFuncSel; + pstcM0PBt->M23CR_f.CRG = pstcCfg->bGateRiseCap; + pstcM0PBt->M23CR_f.CFG = pstcCfg->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 主从模式配置(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_MasterSlave_Set(en_bt_unit_t enUnit, stc_bt_m23_master_slave_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->MSCR_f.MSM = pstcCfg->enMasterSlaveSel; + pstcM0PBt->MSCR_f.MMS = pstcCfg->enMasterSrc; + pstcM0PBt->MSCR_f.SMS = pstcCfg->enSlaveModeSel; + pstcM0PBt->MSCR_f.TS = pstcCfg->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer CH0A/CH0B比较通道输出控制(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_PortOutput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_compare_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CSA = 0; + pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCH0ACmpCtrl; + pstcM0PBt->FLTR_f.CCPA0 = pstcCfg->enCH0APolarity; + pstcM0PBt->CRCH0_f.BUFEA = pstcCfg->bCh0ACmpBufEn; + pstcM0PBt->M23CR_f.CIS = pstcCfg->enCh0ACmpIntSel; + + pstcM0PBt->CRCH0_f.CSB = 0; + pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCH0BCmpCtrl; + pstcM0PBt->FLTR_f.CCPB0 = pstcCfg->enCH0BPolarity; + pstcM0PBt->CRCH0_f.BUFEB = pstcCfg->bCH0BCmpBufEn; + pstcM0PBt->CRCH0_f.CISB = pstcCfg->enCH0BCmpIntSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer CH0A/CH0B输入控制(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_PortInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CSA = 1; + pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enCH0ACapSel; + pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCH0AInFlt; + pstcM0PBt->FLTR_f.CCPA0 = pstcCfg->enCH0APolarity; + + pstcM0PBt->CRCH0_f.CSB = 1; + pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enCH0BCapSel; + pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCH0BInFlt; + pstcM0PBt->FLTR_f.CCPB0 = pstcCfg->enCH0BPolarity; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer ERT输入控制(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_ETRInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_etr_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->FLTR_f.ETP = pstcCfg->enETRPolarity; + pstcM0PBt->FLTR_f.FLTET = pstcCfg->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 刹车BK输入控制(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_BrakeInput_Cfg(en_bt_unit_t enUnit, stc_bt_m23_bk_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.BKE = pstcCfg->bEnBrake; + pstcM0PBt->DTR_f.VCE = pstcCfg->bEnVCBrake; + pstcM0PBt->DTR_f.SAFEEN = pstcCfg->bEnSafetyBk; + pstcM0PBt->DTR_f.BKSEL = pstcCfg->bEnBKSync; + pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enBkCH0AStat; + pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enBkCH0BStat; + pstcM0PBt->FLTR_f.BKP = pstcCfg->enBrakePolarity; + pstcM0PBt->FLTR_f.FLTBK = pstcCfg->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 触发ADC控制(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_TrigADC_Cfg(en_bt_unit_t enUnit, stc_bt_m23_adc_trig_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ADTR_f.ADTE = pstcCfg->bEnTrigADC; + pstcM0PBt->ADTR_f.UEVE = pstcCfg->bEnUevTrigADC; + pstcM0PBt->ADTR_f.CMA0E = pstcCfg->bEnCH0ACmpTrigADC; + pstcM0PBt->ADTR_f.CMB0E = pstcCfg->bEnCH0BCmpTrigADC; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer 死区功能(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_DT_Cfg(en_bt_unit_t enUnit, stc_bt_m23_dt_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.DTEN = pstcCfg->bEnDeadTime; + pstcM0PBt->DTR_f.DTR = pstcCfg->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer 重复周期设置(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] u8ValidPeriod 重复周期值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_SetValidPeriod(en_bt_unit_t enUnit, uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer OCREF清除功能(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_OCRefClr(en_bt_unit_t enUnit, stc_bt_m23_OCREF_Clr_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.OCCS = pstcCfg->enOCRefClrSrcSel; + pstcM0PBt->M23CR_f.OCCE = pstcCfg->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 使能DMA传输(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnDMA(en_bt_unit_t enUnit, stc_bt_m23_trig_dma_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.UDE = pstcCfg->bUevTrigDMA; + pstcM0PBt->M23CR_f.TDE = pstcCfg->bTITrigDMA; + pstcM0PBt->CRCH0_f.CDEA = pstcCfg->bCmpATrigDMA; + pstcM0PBt->CRCH0_f.CDEB = pstcCfg->bCmpBTrigDMA; + pstcM0PBt->MSCR_f.CCDS = pstcCfg->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 捕获比较A软件触发(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrigCapCmpA(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CCGA = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 捕获比较B软件触发(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrigCapCmpB(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CCGB = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件更新使能(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwUev(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件触发使能(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrig(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件刹车使能(模式23) + ** + ** + ** \param [in] enUnit Timer通道选择（TIM0、TIM1、TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwBk(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // BtGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_crc.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_crc.c new file mode 100644 index 0000000000..06e98806c6 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_crc.c @@ -0,0 +1,438 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file crc.c + ** + ** Common API of crc. + ** @link crcGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_crc.h" +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief CRC16 编码(字节填充方式) + ** + ** 该函数主要用于生成CRC16编码. + ** + ** \param [in] pu8Data 待编码数据指针（字节方式输入） + ** \param [in] u32Len 待编码数据长度（字节数） + ** + ** \retval CRC16 CRC16编码值. + *****************************************************************************/ +uint16_t CRC16_Get8(uint8_t* pu8Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT = 0xFFFF; + for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 编码(半字填充方式) + ** + ** 该函数主要用于生成CRC16编码. + ** + ** \param [in] pu16Data 待编码数据指针（半字方式输入） + ** \param [in] u32Len 待编码数据长度（半字数） + ** + ** \retval CRC16 CRC16编码值. + *****************************************************************************/ +uint16_t CRC16_Get16(uint16_t* pu16Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 编码(字填充方式) + ** + ** 该函数主要用于生成CRC16编码. + ** + ** \param [in] pu32Data 待编码数据指针（字方式输入） + ** \param [in] u32Len 待编码数据长度（字数） + ** + ** \retval CRC16 CRC16编码值. + *****************************************************************************/ +uint16_t CRC16_Get32(uint32_t* pu32Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(字节填充方式) + ** + ** 该函数主要用于对数据及CRC16值进行校验. + ** + ** \param [in] pu8Data 待校验数据指针（字节方式输入） + ** \param [in] u32Len 待校验数据长度（字节数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check8(uint8_t* pu8Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index]; + } + + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((((uint32_t)u16CRC)>>0)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)(((uint32_t)u16CRC>>8)&0xFF); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(半字填充方式) + ** + ** 该函数主要用于对数据及CRC16值进行校验. + ** + ** \param [in] pu16Data 待校验数据指针（半字方式输入） + ** \param [in] u32Len 待校验数据长度（半字数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check16(uint16_t* pu16Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = u16CRC; + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(字填充方式) + ** + ** 该函数主要用于对数据及CRC16值进行校验. + ** + ** \param [in] pu32Data 待校验数据指针（字方式输入） + ** \param [in] u32Len 待校验数据长度（字数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check32(uint32_t* pu32Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = ((uint16_t)u16CRC); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 编码(字节填充方式) + ** + ** 该函数主要用于生成CRC16编码. + ** + ** \param [in] pu8Data 待编码数据指针（字节方式输入） + ** \param [in] u32Len 待编码数据长度（字节数） + ** + ** \retval CRC16 CRC16编码值. + *****************************************************************************/ +uint32_t CRC32_Get8(uint8_t* pu8Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT = 0xFFFFFFFFu; + for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 编码(半字填充方式) + ** + ** 该函数主要用于生成CRC16编码. + ** + ** \param [in] pu16Data 待编码数据指针（半字方式输入） + ** \param [in] u32Len 待编码数据长度（半字数） + ** + ** \retval CRC16 CRC16编码值. + *****************************************************************************/ +uint32_t CRC32_Get16(uint16_t* pu16Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 编码(字填充方式) + ** + ** 该函数主要用于生成CRC16编码. + ** + ** \param [in] pu32Data 待编码数据指针（字方式输入） + ** \param [in] u32Len 待编码数据长度（字数） + ** + ** \retval CRC16 CRC16编码值. + *****************************************************************************/ +uint32_t CRC32_Get32(uint32_t* pu32Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(字节填充方式) + ** + ** 该函数主要用于对数据及CRC16值进行校验. + ** + ** \param [in] pu8Data 待校验数据指针（字节方式输入） + ** \param [in] u32Len 待校验数据长度（字节数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check8(uint8_t* pu8Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index]; + } + + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>0)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>8)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>16)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>24)&0xFF); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(半字填充方式) + ** + ** 该函数主要用于对数据及CRC16值进行校验. + ** + ** \param [in] pu16Data 待校验数据指针（半字方式输入） + ** \param [in] u32Len 待校验数据长度（半字数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check16(uint16_t* pu16Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>0)&0xFFFF); + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>16)&0xFFFF); + + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(字填充方式) + ** + ** 该函数主要用于对数据及CRC16值进行校验. + ** + ** \param [in] pu32Data 待校验数据指针（字方式输入） + ** \param [in] u32Len 待校验数据长度（字数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check32(uint32_t* pu32Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index]; + } + + *((volatile uint32_t*)(&(M0P_CRC->DATA))) = u32CRC; + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} +//@} // CrcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_dac.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_dac.c new file mode 100644 index 0000000000..7249e4c87d --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_dac.c @@ -0,0 +1,253 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dac.c + ** + ** dac driver API. + ** + ** - 2019-04-10 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "hc32l196_dac.h" + +/** + ****************************************************************************** + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief 使能相关通道的DMA DMA_CR0中的DMAEN0 + ** + ** @param NewState : TRUE 或者 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Dac_DmaCmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_DAC->CR0)), 12, NewState); +} + +/** +****************************************************************************** + ** \brief 配置DAC的DMA下溢中断， DMA_CR0中的DMAUDRIE0 + ** + ** @param NewState : TRUE 或者 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Dac_DmaITCfg(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_DAC->CR0)), 13, NewState); +} + +/** +****************************************************************************** + ** \brief 获取DAC的DMA下溢中断标志位状态， DMA_SR中的DMAUDR0 + ** + ** @param 无 + ** \retval TRUE 或 FALSE + ** +******************************************************************************/ +boolean_t Dac_GetITStatus(void) +{ + return GetBit((uint32_t)(&(M0P_DAC->SR)), 13); +} + +/** +****************************************************************************** + ** \brief 配置DAC的使能与禁止， DMA_CR0中的EN0 + ** + ** @param NewState : TRUE 或者 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Dac_Cmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_DAC->CR0)), 0, NewState); +} + +/** +****************************************************************************** + ** \brief 软件触发寄存器，触发DAC转换 DMA_SWTRIGR中的SWTRIG0 + ** + ** @param 无 + ** \retval 无 + ** +******************************************************************************/ +void Dac_SoftwareTriggerCmd(void) +{ + SetBit((uint32_t)(&(M0P_DAC->SWTRIGR)), 0, 1); +} + +/** +****************************************************************************** +** \brief 初始化DAC0 + ** + ** @param DAC_InitStruct : 用于初始化DAC0的结构体 + ** \retval 无 + ** +******************************************************************************/ +void Dac_Init(stc_dac_cfg_t* DAC_InitStruct) +{ + M0P_DAC->CR0_f.BOFF0 = DAC_InitStruct->boff_t; + M0P_DAC->CR0_f.TEN0 = DAC_InitStruct->ten_t; + M0P_DAC->CR0_f.TSEL0 = DAC_InitStruct->tsel_t; + M0P_DAC->CR0_f.WAVE0 = DAC_InitStruct->wave_t; + M0P_DAC->CR0_f.MAMP0 = DAC_InitStruct->mamp_t; + M0P_DAC->CR0_f.SREF0 = DAC_InitStruct->sref_t; + + if(DAC_InitStruct->align == DacLeftAlign) + { + M0P_DAC->DHR12L0_f.DHR0 = DAC_InitStruct->dhr12; + } + else if(DAC_InitStruct->align == DacRightAlign) + { + M0P_DAC->DHR12R0_f.DHR0 = DAC_InitStruct->dhr12; + } + else + { + M0P_DAC->DHR8R0_f.DHR0 = DAC_InitStruct->dhr8; + } +} + +/** +****************************************************************************** +** \brief 向DAC0的数据保持寄存器写数据 + ** + ** @param DAC_Channel: Dac_0 + ** @param DAC_Align : Right_Align 与Left_Align + ** @param DAC_Bit : Bit8 与Bit12 + ** @param Data : 所要发送的数据 + ** \retval 无 + ** +******************************************************************************/ +void Dac_SetChannelData(en_align_t DAC_Align, en_bitno_t DAC_Bit, uint16_t Data) +{ + if(DAC_Align == DacRightAlign) + { + if(DAC_Bit == DacBit8) + { + M0P_DAC->DHR8R0_f.DHR0 = (uint8_t)Data; + } + else if(DAC_Bit == DacBit12) + { + M0P_DAC->DHR12R0_f.DHR0 = Data; + } + else + { + return; + } + } + else if(DAC_Align == DacLeftAlign) + { + if(DAC_Bit == DacBit8) + { + return; + } + else if(DAC_Bit == DacBit12) + { + M0P_DAC->DHR12L0_f.DHR0 = Data; + } + else + { + return; + } + } + else + { + return; + } +} + + + +/** +****************************************************************************** + ** \brief 获取DAC数据输出寄存器DAC_DOR0 + ** + ** @param 无 + ** \retval DAC_DOR0的值 + ** +******************************************************************************/ +uint16_t Dac_GetDataOutputValue(void) +{ + uint16_t tmp; + + tmp = M0P_DAC->DOR0_f.DOR0; + return tmp&0x0fff; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_ddl.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_ddl.c new file mode 100644 index 0000000000..d6d8f6968c --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_ddl.c @@ -0,0 +1,250 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file ddl.c + ** + ** Common API of DDL. + ** @link ddlGroup Some description @endlink + ** + ** - 2019-03-03 + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "hc32l196_ddl.h" + +/** + ****************************************************************************** + ** \addtogroup DDL Common Functions + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#ifndef __DEBUG +#define __DEBUG +//#define __CC_ARM +#endif + +uint32_t Log2(uint32_t u32Val) +{ + uint32_t u32V1 = 0; + + if(0u == u32Val) + { + return 0; + } + + while(u32Val > 1u) + { + u32V1++; + u32Val /=2; + } + + return u32V1; +} + + +/** + ******************************************************************************* + ** \brief Memory clear function for DDL_ZERO_STRUCT() + ******************************************************************************/ +void ddl_memclr(void *pu8Address, uint32_t u32Count) +{ + uint8_t *pu8Addr = (uint8_t *)pu8Address; + + if(NULL == pu8Addr) + { + return; + } + + while (u32Count--) + { + *pu8Addr++ = 0; + } +} + +/** + * \brief delay1ms + * delay approximately 1ms. + * \param [in] u32Cnt + * \retval void + */ +void delay1ms(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + u32end = 0x1000000 - SystemCoreClock/1000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief delay100us + * delay approximately 100us. + * \param [in] u32Cnt + * \retval void + */ +void delay100us(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + + u32end = 0x1000000 - SystemCoreClock/10000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief delay10us + * delay approximately 10us. + * \param [in] u32Cnt + * \retval void + */ +void delay10us(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + + u32end = 0x1000000 - SystemCoreClock/100000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief set register bit + * + * \param [in] addr + * \param [in] offset + * \retval void + */ +void SetBit(uint32_t addr, uint32_t offset, boolean_t bFlag) +{ + if(TRUE == bFlag) + { + *((volatile uint32_t *)(addr)) |= ((1UL)<<(offset)); + } + else + { + *((volatile uint32_t *)(addr)) &= (~(1UL<<(offset))); + } + + +} + + +/** + * \brief get register bit + * + * \param [in] addr + * \param [in] offset + * \retval void + */ +boolean_t GetBit(uint32_t addr, uint32_t offset) +{ + return ((((*((volatile uint32_t *)(addr))) >> (offset)) & 1u) > 0) ? TRUE : FALSE; +} +//@} // DDL Functions + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_debug.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_debug.c new file mode 100644 index 0000000000..0e35c8b2cd --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_debug.c @@ -0,0 +1,119 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file debug.c + ** + ** Common API of debug. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_debug.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief 调试模式下模块功能计数使能 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule) +{ + M0P_DEBUG_ACTIVE->DEBUG_ACTIVE &= ~(uint32_t)enModule; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 调试模式下模块功能计数暂停 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule) +{ + M0P_DEBUG_ACTIVE->DEBUG_ACTIVE |= (uint32_t)enModule; + + return Ok; +} + + +//@} // BgrGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_dmac.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_dmac.c new file mode 100644 index 0000000000..85f72c2241 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_dmac.c @@ -0,0 +1,624 @@ +/****************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dmac.c +** +** A detailed description is available at +** @link DmacGroup Dmac description @endlink +** +** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac. +** +******************************************************************************/ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "hc32l196_dmac.h" + +/** +******************************************************************************* +** \addtogroup DmacGroup +******************************************************************************/ +//@{ + +/******************************************************************************* +* Local type definitions ('typedef') +******************************************************************************/ + +/******************************************************************************* +* Local pre-processor symbols/macros ('#define') +******************************************************************************/ + +/******************************************************************************/ +/* DMA */ +/******************************************************************************/ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_TRANSFER_WIDTH_Pos (26U) /*!< DMAC_CONFBx: ERR_IE Position */ +#define DMA_TRANSFER_WIDTH_Msk (0x03U << DMA_TRANSFER_WIDTH_Pos) /*!< DMAC_CONFBx: ERR_IE Mask 0x0C000000 */ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_ERR_IE_Pos (20U) /*!< DMAC_CONFBx: ERR_IE Position */ +#define DMA_ERR_IE_Msk (0x01U << DMA_ERR_IE_Pos) /*!< DMAC_CONFBx: ERR_IE Mask 0x00000010 */ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_FIS_IE_Pos (19U) /*!< DMAC_CONFBx: FIS_IE Position */ +#define DMA_FIS_IE_Msk (0x01U << DMA_FIS_IE_Pos) /*!< DMAC_CONFBx: FIS_IE Mask 0x00000010 */ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_STAT_Pos (16U) /*!< DMAC_CONFBx: STAT Position */ +#define DMA_STAT_Msk (0x07U << DMA_STAT_Pos) /*!< DMAC_CONFBx: STAT Mask 0x00070000 */ + +/************** Bits definition for DMA_CONFBx(x=0~1) register *************/ +#define DMA_TRANSFER_RELOAD_Pos (0U) /*!< DMAC_CONFBx: MSK Position */ +#define DMA_TRANSFER_RELOAD_Msk (0x01U << DMA_TRANSFER_RELOAD_Pos) /*!< DMAC_CONFBx: MSK Mask 0x00000010 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_CH_ENABLE_Pos (31U) /*!< DMAC_CONFAx: ENS Position */ +#define DMA_CH_ENABLE_Msk (0x01U << DMA_CH_ENABLE_Pos) /*!< DMAC_CONFAx: ENS Mask 0x80000000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_CH_PAUSE_Pos (30U) /*!< DMAC_CONFAx: PAS Position */ +#define DMA_CH_PAUSE_Msk (0x01U << DMA_CH_PAUSE_Pos) /*!< DMAC_CONFAx: PAS Mask 0x40000000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_SOFTWARE_START_Pos (29U) /*!< DMAC_CONFAx: ENS Position */ +#define DMA_SOFTWARE_START_Msk (0x01U << DMA_SOFTWARE_START_Pos) /*!< DMAC_CONFAx: ENS Mask 0x20000000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_TRI_SEL_Pos (22U) /*!< DMAC_CONFAx: TRISEL Position */ +#define DMA_TRI_SEL_Msk (0x7FU << DMA_TRI_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x1FC00000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_BC_SEL_Pos (16U) /*!< DMAC_CONFAx: TRISEL Position */ +#define DMA_BC_SEL_Msk (0x0FU << DMA_BC_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x000F0000 */ + +/************** Bits definition for DMA_CONFAx(x=0~1) register *************/ +#define DMA_TC_SEL_Pos (0U) /*!< DMAC_CONFAx: TRISEL Position */ +#define DMA_TC_SEL_Msk (0xFFFFU << DMA_TC_SEL_Pos) /*!< DMAC_CONFAx: TRISEL Mask 0x0000FFFF */ + +/************** Bits definition for DMA_CONF register *************/ +#define DMA_ENABLE_Pos (31U) /*!< DMAC_CONF: TRISEL Position */ +#define DMA_ENABLE_Msk (0x01U << DMA_ENABLE_Pos) /*!< DMAC_CONF: TRISEL Mask 0x80000000 */ + +/************** Bits definition for DMA_CONF register *************/ +#define DMA_PRIORITY_Pos (28U) /*!< DMAC_CONF: TRISEL Position */ +#define DMA_PRIORITY_Msk (0x01U << DMA_PRIORITY_Pos) /*!< DMAC_CONF: TRISEL Mask 0x10000000 */ + + +/*! Dmac通道参数有效性检查. */ +#define IS_VALID_CH(x) \ +( (DmaCh0 == (x)) || \ + (DmaCh1 == (x))) + +/*! DMA 传输数据宽度，参数有效性检查. */ +#define IS_VALID_TRN_WIDTH(x) \ +( (DmaMsk8Bit == (x)) || \ + (DmaMsk16Bit == (x)) || \ + (DmaMsk32Bit == (x))) + +/*! DMA源地址控制模式，参数有效性检查. */ +#define IS_VALID_SRC_ADDR_MODE(x) \ +( (DmaMskSrcAddrFix == (x)) || \ + (DmaMskSrcAddrInc == (x))) + +/*! DMA目的地址控制模式，参数有效性检查. */ +#define IS_VALID_DST_ADDR_MODE(x) \ +( (DmaMskDstAddrFix == (x)) || \ + (DmaMskDstAddrInc == (x))) + +/*! DMA 优先级, 参数有效性检查. */ +#define IS_VALID_PRIO_MODE(x) \ +( (DmaMskPriorityFix == (x)) || \ + (DmaMskPriorityLoop == (x))) + +/*! DMA 传输模式，参数有效性检查. */ +#define IS_VALID_TRANSFER_MODE(x) \ +( (DmaMskOneTransfer == (x)) || \ + (DmaMskContinuousTransfer == (x))) + +/*! 块传输大小，参数有效性检查. */ +#define IS_VALID_BLKSIZE(x) ((!((x) & ~(DMA_BC_SEL_Msk >> DMA_BC_SEL_Pos)))&&((x)>0)) + +/*! 块传输次数，参数有效性检查. */ +#define IS_VALID_TRNCNT(x) (!((x) & ~(DMA_TC_SEL_Msk >> DMA_TC_SEL_Pos))) + +/******************************************************************************* +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + +/******************************************************************************* +* Local function prototypes ('static') +******************************************************************************/ + +/******************************************************************************* +* Local variable definitions ('static') +******************************************************************************/ + +/******************************************************************************* +* Function implementation - global ('extern') and local ('static') +******************************************************************************/ + +/** +******************************************************************************* +** \brief 初始化DMAC通道 +** +** \param [in] enCh 指定通道. +** \param [in] pstcCfg DMAC通道初始化配置结构体指针. +** +** \retval Ok 初始化成功. +** \retval ErrorInvalidParameter pstcCfg是空指针. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_cfg_t* pstcCfg) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(NULL != pstcCfg); + ASSERT(IS_VALID_BLKSIZE(pstcCfg->u16BlockSize)); + ASSERT(IS_VALID_TRNCNT(pstcCfg->u16TransferCnt)); + ASSERT(IS_VALID_TRN_WIDTH(pstcCfg->enTransferWidth)); + ASSERT(IS_VALID_SRC_ADDR_MODE(pstcCfg->enSrcAddrMode)); + ASSERT(IS_VALID_DST_ADDR_MODE(pstcCfg->enDstAddrMode)); + ASSERT(IS_VALID_PRIO_MODE(pstcCfg->enPriority)); + ASSERT(IS_VALID_TRANSFER_MODE(pstcCfg->enTransferMode)); + + /* 检查通道值有效性和pstcCfg是否空指针 */ + if (NULL == pstcCfg) + { + return ErrorInvalidParameter; + } + + *(&M0P_DMAC->CONFB0+enCh) = 0; + *(&M0P_DMAC->CONFB0+enCh) = (uint32_t)pstcCfg->enMode | + (uint32_t)pstcCfg->enTransferWidth | + (uint32_t)pstcCfg->enSrcAddrMode | + (uint32_t)pstcCfg->enDstAddrMode | + (uint32_t)pstcCfg->enSrcAddrReloadCtl | + (uint32_t)pstcCfg->enDestAddrReloadCtl| + (uint32_t)pstcCfg->enSrcBcTcReloadCtl | + (uint32_t)pstcCfg->enTransferMode; + + /*首先把TRI_SEL[6:0] BC[3:0] TC[15:0]这些位清零，然后再赋值*/ + *(&M0P_DMAC->CONFA0+enCh) &= ((uint32_t)~(DMA_TRI_SEL_Msk | DMA_BC_SEL_Msk | DMA_TC_SEL_Msk)); + *(&M0P_DMAC->CONFA0+enCh) |= (uint32_t)(pstcCfg->u16TransferCnt - 1) | + ((uint32_t)(pstcCfg->u16BlockSize - 1)<<16)| + (uint32_t)(pstcCfg->enRequestNum<<22); + + M0P_DMAC->CONF |= (uint32_t)(pstcCfg->enPriority); + + *(&M0P_DMAC->SRCADR0+enCh) = (uint32_t)(pstcCfg->u32SrcAddress); + *(&M0P_DMAC->DSTADR0+enCh) = (uint32_t)(pstcCfg->u32DstAddress); + + return Ok; +} +/** +******************************************************************************* +** \brief DMA模块使能函数，使能所有通道的操作，每个通道按照各自设置工作. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Enable(void) +{ + M0P_DMAC->CONF |= DMA_ENABLE_Msk; +} + +/** +******************************************************************************* +** \brief DMA模块功能禁止函数，所有通道禁止工作. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Disable(void) +{ + M0P_DMAC->CONF &= (~DMA_ENABLE_Msk); +} +/** +******************************************************************************* +** \brief 触发指定DMA通道软件传输功能. +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SwStart(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) |= DMA_SOFTWARE_START_Msk; +} + +/** +******************************************************************************* +** \brief 停止指定DMA通道软件传输功能. +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SwStop(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_SOFTWARE_START_Msk); +} +/** +******************************************************************************* +** \brief 使能指定dma通道的（传输完成）中断. +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_EnableChannelIrq(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) |= DMA_FIS_IE_Msk; +} + +/** +******************************************************************************* +** \brief 禁用指定dma通道的（传输完成）中断. +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_DisableChannelIrq(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_FIS_IE_Msk); +} +/** +******************************************************************************* +** \brief 使能指定dma通道的（传输错误）中断.. +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_EnableChannelErrIrq(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) |= DMA_ERR_IE_Msk; +} + +/** +******************************************************************************* +** \brief 禁用指定dma通道的（传输错误）中断.. +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_DisableChannelErrIrq(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_ERR_IE_Msk); +} + +/** +******************************************************************************* +** \brief 使能指定dma通道 +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_EnableChannel(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) |= DMA_CH_ENABLE_Msk; +} + +/** +******************************************************************************* +** \brief 禁用指定dma通道 +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_DisableChannel(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_CH_ENABLE_Msk); +} + +/** +******************************************************************************* +** \brief 设定指定通道的块(Block)尺寸 +** +** \param [输入] enCh 指定通道 +** \param [输入] u16BlkSize 块(Block)尺寸. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize) +{ + volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh); + + *pReg = ((*pReg) & ((uint32_t)~DMA_BC_SEL_Msk)) | ((((uint32_t)u16BlkSize-1)&0x0f)<CONFA0+enCh); + + *pReg = ((*pReg)&((uint32_t)~DMA_TC_SEL_Msk))|(((uint32_t)(u16TrnCnt-1)<CONFB0+enCh) |= DMA_TRANSFER_RELOAD_Msk; +} + +/** +******************************************************************************* +** \brief 禁止指定通道连续传输，即DMAC在传输完成时清除. +** +** \param [输入] enCh 指定通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_DisableContinusTranfer(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_TRANSFER_RELOAD_Msk); +} +/** +******************************************************************************* +** \brief 暂停所有dma通道. +** +** \param None +** +** \retval None. +** +** \note None +** +******************************************************************************/ +void Dma_HaltTranfer(void) +{ + M0P_DMAC->CONF_f.HALT = 0x1; +} +/** +******************************************************************************* +** \brief 恢复（之前暂停的）所有dma通道. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_RecoverTranfer(void) +{ + M0P_DMAC->CONF_f.HALT = 0x0; +} +/** +******************************************************************************* +** \brief 暂停指定dma通道. +** +** \param [输入] enCh 指定通道. +** +** \retval void +** +** \note None +** +******************************************************************************/ +void Dma_PauseChannelTranfer(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) |= DMA_CH_PAUSE_Msk; +} +/** +******************************************************************************* +** \brief 恢复（之前暂定的）指定dma通道. +** +** \param [输入] enCh 指定通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_RecoverChannelTranfer(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFA0+enCh) &= (~DMA_CH_PAUSE_Msk); +} +/** +******************************************************************************* +** \brief 设定指定通道传输数据宽度. +** +** \param [输入] enCh 指定dma通道. +** \param [输入] enWidth 指定数据宽度. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth) +{ + volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh); + + *pReg = ((*pReg)&((uint32_t)~DMA_TRANSFER_WIDTH_Msk))|((uint32_t)enWidth); +} +/** +******************************************************************************* +** \brief 设定dma通道优先级. +** +** \param [输入] enPrio 通道优先级设定参数. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetChPriority(en_dma_priority_t enPrio) +{ + M0P_DMAC->CONF = ((M0P_DMAC->CONF)&((uint32_t)~DMA_PRIORITY_Msk))|((uint32_t)enPrio); +} +/** +******************************************************************************* +** \brief 获取指定DMA通道的状态. +** +** \param [输入] enCh 指定dma通道. +** +** \retval en_dma_stat_t DMA传输当前状态 +** +** \note None +** +******************************************************************************/ +en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh) +{ + return (en_dma_stat_t)((*(&M0P_DMAC->CONFB0+enCh)&(DMA_STAT_Msk))>>DMA_STAT_Pos); +} +/** +******************************************************************************* +** \brief 清除指定DMA通道的状态值. +** +** \param [输入] enCh 指定dma通道. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_ClrStat(en_dma_channel_t enCh) +{ + *(&M0P_DMAC->CONFB0+enCh) &= (~DMA_STAT_Msk); +} + + +/** +******************************************************************************* +** \brief 设定指定通道源地址 +** +** \param [输入] enCh 指定dma通道. +** \param [输入] u32Address 传输源地址. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address) +{ + *(&M0P_DMAC->SRCADR0+enCh) = u32Address; +} + +/** +******************************************************************************* +** \brief 设定指定通道目标地址. +** +** \param [输入] enCh 指定dma通道. +** \param [输入] u32Address 传输目标地址. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address) +{ + *(&M0P_DMAC->DSTADR0+enCh) = u32Address; +} + +//@} // DmacGroup + +/******************************************************************************* +* EOF (not truncated) +******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_flash.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_flash.c new file mode 100644 index 0000000000..2678d8d873 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_flash.c @@ -0,0 +1,704 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file flash.c + ** + ** Common API of flash. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_flash.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define FLASH_END_ADDR (0x0003FFFFu) +#define FLASH_BYPASS() M0P_FLASH->BYPASS = 0x5A5A;\ + M0P_FLASH->BYPASS = 0xA5A5; +#define FLASH_IE_TRUE (0x03) +#define FLASH_IE_FALSE (0x00) + +#define FLASH_TIMEOUT_INIT (0xFFFFFFu) +#define FLASH_TIMEOUT_PGM (0xFFFFFFu) +#define FLASH_TIMEOUT_ERASE (0xFFFFFFu) + +#define FLASH_LOCK_ALL (0u) +#define FLASH_UNLOCK_ALL (0xFFFFFFFFu) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief FLASH OP + ** + ** Flash 操作控制数据类型重定义 + ******************************************************************************/ +typedef enum en_flash_op +{ + Read = 0u, ///<读配置值 + Program = 1u, ///<编程配置值 + SectorErase = 2u, ///<扇区擦除配置值 + ChipErase = 3u, ///<全片擦除配置值 +} en_flash_op_t; + +/** + ****************************************************************************** + ** \brief FLASH 编程时间参数配置 + ** + ** FLASH编程时间参数配置数组定义 (4MHz) + ******************************************************************************/ +const uint32_t pu32PcgTimer4M[] = { + 0x20u, //Tnvs + 0x17u, //Tpgs + 0x1Bu, //Tprog + 0x4650u, //Tserase + 0x222E0u, //Tmerase + 0x18u, //Tprcv + 0xF0u, //Tsrcv + 0x3E8u //Tmrcv + }; +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Flash中断标志获取 + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Flash_GetIntFlag(en_flash_int_type_t enFlashIntType) +{ + boolean_t bRetVal = FALSE; + + if(M0P_FLASH->IFR & enFlashIntType) + { + bRetVal = TRUE; + } + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Flash中断标志清除 + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_ClearIntFlag(en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + M0P_FLASH->ICLR &= ~(uint32_t)enFlashIntType; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Flash中断使能 + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_EnableIrq (en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE |= enFlashIntType; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Flash中断禁止 + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_DisableIrq(en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE &= ~(uint32_t)enFlashIntType; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH 初始化函数——中断服务程序、编程时间配置及低功耗模式 + ** + ** 该函数用于配置中断服务函数、低功耗模式、根据系统时钟配置FLASH编程时间相关寄存器. + ** + ** \param [in] u8FreqCfg FLASH编程时钟频率配置(根据HCLK的频率选择配置值)： + ** 1 - 4MHz; + ** 2 - 8MHz; + ** 4 - 16MHz; + ** 6 - 24MHz; + ** 8 - 32MHz; + ** 12 - 48MHz; + ** other - 无效值 + ** \param [in] bDpstbEn TRUE - 当系统进入DeepSleep模式，FLASH进入低功耗模式; + ** FALSE - 当系统进入DeepSleep模式，FLASH不进入低功耗模式; + ** + ** \retval Ok 操作成功. + ** \retval ErrorInvalidParameter 参数无效. + ** \retval ErrorUninitialized 初始化失败。 + *****************************************************************************/ +en_result_t Flash_Init(uint8_t u8FreqCfg, boolean_t bDpstbEn) +{ + uint32_t u32Index = 0; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_INIT; + en_result_t enResult = Ok; + uint32_t u32PrgTimer[8] = {0}; + volatile uint32_t *pu32PrgTimerReg = (volatile uint32_t*)M0P_FLASH; + + if ((1 != u8FreqCfg) && (2 != u8FreqCfg) && + (4 != u8FreqCfg) && (6 != u8FreqCfg) && + (8 != u8FreqCfg) && (12 != u8FreqCfg)) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + M0P_FLASH->CR_f.DPSTB_EN = bDpstbEn; + + //flash时间参数配置值计算 + for(u32Index=0; u32Index<8; u32Index++) + { + u32PrgTimer[u32Index] = u8FreqCfg * pu32PcgTimer4M[u32Index]; + } + + //flash时间参数寄存器配置 + for(u32Index=0; u32Index<8; u32Index++) + { + u32TimeOut = FLASH_TIMEOUT_INIT; + while(pu32PrgTimerReg[u32Index] != u32PrgTimer[u32Index]) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + pu32PrgTimerReg[u32Index] = u32PrgTimer[u32Index]; + } + else + { + return ErrorUninitialized; + } + } + } + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 字节写 + ** + ** 用于向FLASH写入1字节数据. + ** + ** \param [in] u32Addr Flash地址 + ** \param [in] u8Data 1字节数据 + ** + ** \retval Ok 写入成功. + ** \retval ErrorInvalidParameter FLASH地址无效 + ** \retval ErrorTimeout 操作超时 + *****************************************************************************/ +en_result_t Flash_WriteByte(uint32_t u32Addr, uint8_t u8Data) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM; + + if (FLASH_END_ADDR < u32Addr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //set OP + u32TimeOut = FLASH_TIMEOUT_PGM; + while(Program != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + } + else + { + return ErrorTimeout; + } + } + + //Flash 解锁 + Flash_UnlockAll(); + + //write data + *((volatile uint8_t*)u32Addr) = u8Data; + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 加锁 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 半字写 + ** + ** 用于向FLASH写入半字（2字节）数据. + ** + ** \param [in] u32Addr Flash地址 + ** \param [in] u16Data 半字（2字节）数据 + ** + ** \retval Ok 写入成功. + ** \retval ErrorInvalidParameter FLASH地址无效 + ** \retval ErrorTimeout 操作超时 + *****************************************************************************/ +en_result_t Flash_WriteHalfWord(uint32_t u32Addr, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM; + + if (FLASH_END_ADDR < u32Addr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //set OP + u32TimeOut = FLASH_TIMEOUT_PGM; + while(Program != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + } + else + { + return ErrorTimeout; + } + } + + //Flash 解锁 + Flash_UnlockAll(); + + //write data + *((volatile uint16_t*)u32Addr) = u16Data; + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 加锁 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 字写 + ** + ** 用于向FLASH写入1个字的数据. + ** + ** \param [in] u32Addr Flash地址 + ** \param [in] u32Data 1个字数据 + ** + ** \retval Ok 写入成功. + ** \retval ErrorInvalidParameter FLASH地址无效 + ** \retval ErrorTimeout 操作超时 + *****************************************************************************/ +en_result_t Flash_WriteWord(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_PGM; + + if (FLASH_END_ADDR < u32Addr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 解锁 + Flash_UnlockAll(); + + //set OP + u32TimeOut = FLASH_TIMEOUT_PGM; + while(Program != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + } + else + { + return ErrorTimeout; + } + } + + //write data + *((volatile uint32_t*)u32Addr) = u32Data; + + //busy? + u32TimeOut = FLASH_TIMEOUT_PGM; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 加锁 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 扇区擦除 + ** + ** FLASH 扇区擦除. + ** + ** \param [in] u32SectorAddr 所擦除扇区内的地址 + ** + ** \retval Ok 擦除成功. + ** \retval ErrorInvalidParameter FLASH地址无效 + ** \retval ErrorTimeout 操作超时 + *****************************************************************************/ +en_result_t Flash_SectorErase(uint32_t u32SectorAddr) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_ERASE; + + if (FLASH_END_ADDR < u32SectorAddr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //busy? + u32TimeOut = FLASH_TIMEOUT_ERASE; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 解锁 + Flash_UnlockAll(); + + //set OP + u32TimeOut = FLASH_TIMEOUT_ERASE; + while(SectorErase != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = SectorErase; + } + else + { + return ErrorTimeout; + } + } + + //write data + *((volatile uint8_t*)u32SectorAddr) = 0; + + //busy? + u32TimeOut = FLASH_TIMEOUT_ERASE; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 加锁 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 全片擦除(该函数仅限RAM中运行！！！) + ** + ** FLASH 全片擦除. + ** + ** + ** \retval Ok 擦除成功. + ** \retval ErrorTimeout 操作超时 + ** + *****************************************************************************/ +en_result_t Flash_ChipErase(void) +{ + en_result_t enResult = Ok; + volatile uint32_t u32TimeOut = FLASH_TIMEOUT_ERASE; + + //busy? + u32TimeOut = FLASH_TIMEOUT_ERASE; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //set OP + u32TimeOut = FLASH_TIMEOUT_ERASE; + while(ChipErase != M0P_FLASH->CR_f.OP) + { + if(u32TimeOut--) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = ChipErase; + } + else + { + return ErrorTimeout; + } + } + + //Flash 解锁 + Flash_UnlockAll(); + + //write data + *((volatile uint8_t*)0) = 0; + + //busy? + u32TimeOut = FLASH_TIMEOUT_ERASE; + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + if(0 == u32TimeOut--) + { + return ErrorTimeout; + } + } + + //Flash 加锁 + Flash_LockAll(); + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 编程保护加锁 + ** + ** + ** \retval Null + *****************************************************************************/ +void Flash_LockAll(void) +{ + FLASH_BYPASS(); + M0P_FLASH->SLOCK0 = FLASH_LOCK_ALL; + FLASH_BYPASS(); + M0P_FLASH->SLOCK1 = FLASH_LOCK_ALL; + FLASH_BYPASS(); + M0P_FLASH->SLOCK2 = FLASH_LOCK_ALL; + FLASH_BYPASS(); + M0P_FLASH->SLOCK3 = FLASH_LOCK_ALL; + +} + +/** + ***************************************************************************** + ** \brief FLASH 编程保护解锁 + ** + ** + ** \retval Null + *****************************************************************************/ +void Flash_UnlockAll(void) +{ + + FLASH_BYPASS(); + M0P_FLASH->SLOCK0 = FLASH_UNLOCK_ALL; + FLASH_BYPASS(); + M0P_FLASH->SLOCK1 = FLASH_UNLOCK_ALL; + FLASH_BYPASS(); + M0P_FLASH->SLOCK2 = FLASH_UNLOCK_ALL; + FLASH_BYPASS(); + M0P_FLASH->SLOCK3 = FLASH_UNLOCK_ALL; + +} + +/** + ***************************************************************************** + ** \brief FLASH 读等待周期设置 + ** + ** \param [in] enWaitCycle 插入FLASH读等待周期数枚举类型 + ** + ** \retval Ok 解锁成功 + ** \retval ErrorInvalidParameter 参数错误 + *****************************************************************************/ +en_result_t Flash_WaitCycle(en_flash_waitcycle_t enWaitCycle) +{ + en_result_t enResult = Ok; + + FLASH_BYPASS(); + M0P_FLASH->CR_f.WAIT = enWaitCycle; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH LOCK 设置 + ** + ** \param [in] enLock @ref en_flash_lock_t + ** \param [in] u32LockValue 32bits，对应bit=0：加锁，对应Sector不允许擦写；对应bit=1：解锁。 + ** \note 加解锁范围Sector：[enLock*128 + i*4, enLock*128 + i*4+3] + ** (i表示u32LockValue的bit位置，0~31) + ** 例如：enLock = FlashLock1, u32LockValue = 0x00000002, + ** 则加解锁范围为：[Sector128,Sector131] + ** \retval Ok 解锁成功 + ** \retval ErrorInvalidParameter 参数错误 + *****************************************************************************/ +en_result_t Flash_LockSet(en_flash_lock_t enLock, uint32_t u32LockValue) +{ + FLASH_BYPASS(); + *((&M0P_FLASH->SLOCK0) + enLock) = u32LockValue; + + return Ok; +} +//@} // FlashGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_gpio.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_gpio.c new file mode 100644 index 0000000000..e922051af3 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_gpio.c @@ -0,0 +1,582 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file Gpio.c + ** + ** GPIO driver API. + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-22 1.0 Lux First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_gpio.h" + +/** + ******************************************************************************* + ** \addtogroup GpioGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_PIN(port,pin) ( ) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief GPIO 初始化 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** \param [in] pstcGpioCfg IO 配置结构体指针 + ** + ** \retval Ok 设置成功 + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_Init(en_gpio_port_t enPort, en_gpio_pin_t enPin, stc_gpio_cfg_t *pstcGpioCfg) +{ + //配置为默认值,GPIO功能 + SetBit((uint32_t)&M0P_GPIO->PAADS + enPort, enPin, FALSE); + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = GpioAf0; + + //默认输出值配置 + SetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin, pstcGpioCfg->bOutputVal); + //方向配置 + SetBit(((uint32_t)&M0P_GPIO->PADIR + enPort), enPin, (boolean_t)(pstcGpioCfg->enDir)); + //驱动能力配置 + SetBit(((uint32_t)&M0P_GPIO->PADR + enPort), enPin, (boolean_t)(pstcGpioCfg->enDrv)); + //上拉/下拉配置 + SetBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, (boolean_t)(pstcGpioCfg->enPu)); + SetBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, (boolean_t)(pstcGpioCfg->enPd)); + //开漏输出功能 + SetBit(((uint32_t)&M0P_GPIO->PAOD + enPort), enPin, (boolean_t)(pstcGpioCfg->enOD)); + + M0P_GPIO->CTRL2_f.AHB_SEL = pstcGpioCfg->enCtrlMode; + + return Ok; +} + + + +/** + ******************************************************************************* + ** \brief GPIO IO输入值获取 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** + ** \retval boolean_t IO电平高低 + ******************************************************************************/ +boolean_t Gpio_GetInputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return GetBit(((uint32_t)&M0P_GPIO->PAIN + enPort), enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port输入数据获取 + ** + ** \param [in] enPort IO Port + ** + ** \retval boolean_t IO Port数据 + ******************************************************************************/ +uint16_t Gpio_GetInputData(en_gpio_port_t enPort) +{ + return (uint16_t)(*((uint32_t *)((uint32_t)&M0P_GPIO->PAIN + enPort))); +} + +/** + ******************************************************************************* + ** \brief GPIO IO输出值写入 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** \param [out] bVal 输出值 + ** + ** \retval en_result_t Ok 设置成功 + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_WriteOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin, boolean_t bVal) +{ + SetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin, bVal); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO输出值获取 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** + ** \retval boolean_t IO电平高低 + ******************************************************************************/ +boolean_t Gpio_ReadOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return GetBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port设置，可同时设置一组Port中的多个PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u16ValMsk 该Port的16个PIN掩码值,将需要设置的PIN对应的bit写1有效 + ** + ** \retval boolean_t IO Port数据 + ******************************************************************************/ +en_result_t Gpio_SetPort(en_gpio_port_t enPort, uint16_t u16ValMsk) +{ + *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABSET)) + enPort)) = u16ValMsk; + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO设置 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** + ** \retval en_result_t Ok 设置成功 + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + SetBit(((uint32_t)&M0P_GPIO->PABSET + enPort), enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port清零，可同时清零一组Port中的多个PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u16ValMsk 该Port的16个PIN掩码值,将需要清零的PIN对应的bit写1有效 + ** + ** \retval boolean_t IO Port数据 + ******************************************************************************/ +en_result_t Gpio_ClrPort(en_gpio_port_t enPort, uint16_t u16ValMsk) +{ + *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABCLR)) + enPort)) = u16ValMsk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO清零 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** + ** \retval en_result_t Ok 设置成功 + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_ClrIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + SetBit(((uint32_t)&M0P_GPIO->PABCLR + enPort), enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port置位/清零，可同时置位/清零一组Port中的多个PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u32ValMsk 高16bits表示该Port的16个PIN置位掩码值, + ** 低16bits表示该Port的16个PIN清零掩码值, + ** 将需要设置的PIN对应的bit写1,同一个PIN的掩码同时为1,则该PIN清零。 + ** + ** \retval en_result_t Ok 设置成功 + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetClrPort(en_gpio_port_t enPort, uint32_t u32ValMsk) +{ + *((uint32_t*)(((uint32_t)&(M0P_GPIO->PABSETCLR)) + enPort)) = u32ValMsk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO配置为模拟功能模式 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** + ** \retval Ok 设置成功 + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetAnalogMode(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + SetBit((uint32_t)&M0P_GPIO->PAADS + enPort, enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* +** \brief GPIO IO复用功能设置 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** \param [in] enAf 复用功能枚举类型选择 + ** \retval Ok 设置成功 + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetAfMode(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_af_t enAf) +{ + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = enAf; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO复用功能设置 + ** + ** \param [in] PinMux 复用功能宏定义 + ** \retval Null + ** + ******************************************************************************/ +void Gpio_SetAfMode_Lite(GpioPinMux PinMux) +{ + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + ((PinMux>>16u)&0xFFFFu)) + (((uint32_t)((PinMux>>8u)&0xFFu))<<2))) = (uint32_t)(PinMux&0x7u); +} + +/** + ******************************************************************************* + ** \brief GPIO IO中断使能 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** \param [in] enType 中断使能类型 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_EnableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType) +{ + uint32_t u32PieAddr; + + u32PieAddr = ((uint32_t)((&M0P_GPIO->PAHIE) + enType)) + enPort; + + SetBit(u32PieAddr, enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO中断关闭 + ** + ** \param [in] enPort IO Port口 + ** \param [in] enPin IO Pin脚 + ** \param [in] enType 中断使能类型 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_DisableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType) +{ + uint32_t u32PieAddr; + + u32PieAddr = ((uint32_t)((&M0P_GPIO->PAHIE) + enType)) + enPort; + + SetBit(u32PieAddr, enPin, FALSE); + + return Ok; +} + + +/** + ******************************************************************************* + ** \brief GPIO 获得IO中断状态 + ** + ** \param [in] u8Port IO Port口 + ** \param [in] u8Pin IO Pin脚 + ** + ** \retval IO中断状态开关 + ******************************************************************************/ +boolean_t Gpio_GetIrqStatus(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return GetBit((uint32_t)&M0P_GPIO->PA_STAT + enPort, enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO 清除IO中断状态 + ** + ** \param [in] u8Port IO Port口 + ** \param [in] u8Pin IO Pin脚 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_ClearIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + SetBit((uint32_t)&M0P_GPIO->PA_ICLR + enPort, enPin, FALSE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端口辅助功能配置——中断模式配置 + ** + ** \param [in] enIrqMode 端口中断模式（深度休眠是否响应中断） + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_SfIrqModeCfg(en_gpio_sf_irqmode_t enIrqMode) +{ + M0P_GPIO->CTRL0_f.IESEL = enIrqMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端口辅助功能配置——IR输出极性配置 + ** + ** \param [in] enIrPolMode IR输出极性配置枚举 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_SfIrPolCfg(en_gpio_sf_irpol_t enIrPolMode) +{ + M0P_GPIO->CTRL1_f.IR_POL = enIrPolMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端口辅助功能配置——HCLK输出配置 + ** + ** \param [in] enGate HCLK输出使能 + ** \param [in] enDiv 输出分频枚举值 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_SfHClkOutputCfg(en_gpio_sf_hclkout_g_t enGate, en_gpio_sf_hclkout_div_t enDiv) +{ + M0P_GPIO->CTRL1_f.HCLK_EN = enGate; + M0P_GPIO->CTRL1_f.HCLK_SEL = enDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端口辅助功能配置——PCLK输出配置 + ** + ** \param [in] enGate PCLK输出使能 + ** \param [in] enDiv 输出分频枚举值 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_SfPClkOutputCfg(en_gpio_sf_pclkout_g_t enGate, en_gpio_sf_pclkout_div_t enDiv) +{ + M0P_GPIO->CTRL1_f.PCLK_EN = enGate; + M0P_GPIO->CTRL1_f.PCLK_SEL = enDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端口辅助功能配置——外部时钟输入来源配置 + ** + ** \param [in] enExtClk 外部时钟信号来源选择枚举 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_SfExtClkCfg(en_gpio_sf_ssn_extclk_t enExtClk) +{ + M0P_GPIO->CTRL1_f.EXT_CLK_SEL = enExtClk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端口辅助功能配置——SSN 通道信号来源配置 + ** + ** \param [in] enSpi SSN SPI通道选择枚举 + ** \param [in] enSsn SSN 信号来源选择枚举 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_SfSsnCfg(en_gpio_sf_ssnspi_t enSpi, en_gpio_sf_ssn_extclk_t enSsn) +{ + //SPI0 + if(enSpi == GpioSpi0) + { + M0P_GPIO->CTRL1_f.SSN0_SEL = enSsn; + } + //SPI1 + if(enSpi == GpioSpi1) + { + M0P_GPIO->CTRL2_f.SSN1_SEL = enSsn; + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端口辅助功能配置——Timer 门控输入配置 + ** + ** \param [in] enTimG Timer类型选择枚举 + ** \param [in] enSf Timer互联功能选择枚举 + ** + ** \retval Ok 设置成功 + ******************************************************************************/ +en_result_t Gpio_SfTimGCfg(en_gpio_sf_tim_g_t enTimG, en_gpio_sf_t enSf) +{ + if(enTimG&0x20u) + { + enTimG &= ~0x20u; + M0P_GPIO->PCAS &= (uint32_t)(~(0x07U<PCAS |= (uint32_t)(enSf<TIMGS &= (uint32_t)(~(0x07U<TIMGS |= (uint32_t)(enSf<PCAS &= (uint32_t)(~(0x07U<PCAS |= (uint32_t)(enSf<TIMES &= (uint32_t)(~(0x07U<TIMES |= (uint32_t)(enSf<TIMCPS &= (uint32_t)(~(0x07u<TIMCPS |= (uint32_t)(enSf<PCAS &= (uint32_t)(~(0x07u<PCAS |= (uint32_t)(enSf<TM = u8Tm; + + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C功能设置相关函数 + ** + ** \param [in] enFunc功能参数 + ** + ** \retval enRet 成功或失败 + ** + ******************************************************************************/ +en_result_t I2C_SetFunc(M0P_I2C_TypeDef* I2Cx, en_i2c_func_t enFunc) +{ + en_result_t enRet = Error; + + SetBit((uint32_t)&I2Cx->CR, enFunc, TRUE); + + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief I2C功能清除相关函数 + ** + ** \param [in] enFunc功能参数 + ** + ** \retval enRet 成功或失败 + ** + ******************************************************************************/ + en_result_t I2C_ClearFunc(M0P_I2C_TypeDef* I2Cx, en_i2c_func_t enFunc) + { + en_result_t enRet = Error; + + SetBit((uint32_t)&I2Cx->CR, enFunc, FALSE); + + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C获取中断标记函数 + ** + ** \param 无 + ** + ** \retval bIrq中断标记 + ** + ******************************************************************************/ +boolean_t I2C_GetIrq(M0P_I2C_TypeDef* I2Cx) +{ + if(I2Cx->CR&0x8) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + ****************************************************************************** + ** \brief I2C清除中断标记函数 + ** + ** \param 无 + ** + ** \retval bIrq中断标记 + ** + ******************************************************************************/ +en_result_t I2C_ClearIrq(M0P_I2C_TypeDef* I2Cx) +{ + en_result_t enRet = Error; + + I2Cx->CR &= ~0x8u; + + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief I2C获取相关状态 + ** + ** \param 无 + ** + ** \retval I2C状态 + ** + ******************************************************************************/ +uint8_t I2C_GetState(M0P_I2C_TypeDef* I2Cx) +{ + uint8_t u8State = 0; + + u8State = I2Cx->STAT; + + return u8State; +} + +/** + ****************************************************************************** + ** \brief 字节数据写函数 + ** + ** \param u8Data写数据 + ** + ** \retval 写数据是否成功 + ** + ******************************************************************************/ +en_result_t I2C_WriteByte(M0P_I2C_TypeDef* I2Cx, uint8_t u8Data) +{ + en_result_t enRet = Error; + + I2Cx->DATA = u8Data; + + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief 字节数据读函数 + ** + ** \param 无 + ** + ** \retval 读取数据 + ** + ******************************************************************************/ +uint8_t I2C_ReadByte(M0P_I2C_TypeDef* I2Cx) +{ + uint8_t u8Data = 0; + + u8Data = I2Cx->DATA; + + return u8Data; +} + +/** + ****************************************************************************** + ** \brief I2C模块初始化 + ** + ** \param pstcI2CCfg初始化配置结构体 + ** + ** \retval 初始化是否成功 + ** + ******************************************************************************/ +en_result_t I2C_Init(M0P_I2C_TypeDef* I2Cx, stc_i2c_cfg_t *pstcI2CCfg) +{ + en_result_t enRet = Error; + uint8_t u8Tm; + + if(M0P_I2C0 == I2Cx) + { + M0P_RESET->PERI_RESET0 &= ~(uint32_t)0x10u; + M0P_RESET->PERI_RESET0 |= (uint32_t)0x10u; + } + else + { + M0P_RESET->PERI_RESET0 &= ~(uint32_t)0x20u; + M0P_RESET->PERI_RESET0 |= (uint32_t)0x20u; + } + + I2Cx->CR = 0; + I2Cx->CR = pstcI2CCfg->enMode; + + if((pstcI2CCfg->u32Baud<<4) > pstcI2CCfg->u32Pclk) + { + return Error; + } + + if(I2cMasterMode == pstcI2CCfg->enMode) + { + I2Cx->TMRUN = TRUE; + ///< Fsck = Fpclk/8*(Tm+1) + u8Tm = ((pstcI2CCfg->u32Pclk / pstcI2CCfg->u32Baud) >> 3) - 1; + if(9 > u8Tm) + { + I2C_SetFunc(I2Cx,I2cHlm_En); + } + enRet = I2C_SetBaud(I2Cx, u8Tm); + } + else + { + I2Cx->TMRUN = FALSE; + pstcI2CCfg->u8SlaveAddr = (uint8_t)(((uint32_t)pstcI2CCfg->u8SlaveAddr<<1)|(pstcI2CCfg->bGc)); + I2Cx->ADDR = pstcI2CCfg->u8SlaveAddr; + } + + return enRet; +} + +//@} // I2cGroup diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lcd.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lcd.c new file mode 100644 index 0000000000..0725437752 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lcd.c @@ -0,0 +1,289 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lcd.c + ** + ** lcd driver API. + ** + ** - 2019-04-02 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "hc32l196_lcd.h" + + +/** + ****************************************************************************** + ** \addtogroup AdcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief 获取LCD中断标志位INTF + ** + ** @param 无 + ** \retval 无 + ** +******************************************************************************/ +boolean_t Lcd_GetItStatus(void) +{ + return (((M0P_LCD->CR1)>>11)&0x01)? TRUE : FALSE; +} + +/** +****************************************************************************** + ** \brief 清除中断标志位INTF + ** + ** @param 无 + ** \retval 无 + ** +******************************************************************************/ +void Lcd_ClearItPendingBit(void) +{ + SetBit((uint32_t)(&(M0P_LCD->INTCLR)), 10, 0); +} + +/** +****************************************************************************** + ** \brief 根据LCD显示模式获取端口配置 + ** + ** \param pstcSegComPara：显示方式， stcSegCom获取端口参数 + ** + ** \retval enRet 成功或失败 + ** +******************************************************************************/ +en_result_t Lcd_GetSegCom(stc_lcd_segcompara_t *pstcSegComPara,stc_lcd_segcom_t *pstcSegCom) +{ + en_result_t enRet = Error; + pstcSegCom->stc_seg32_51_com0_8_t.seg32_51_com0_8 = 0xffffffffu; + pstcSegCom->u32Seg0_31 = 0xffffffffu; + if(pstcSegComPara->u8MaxSeg>51) + { + return ErrorInvalidParameter; + } + switch(pstcSegComPara->LcdBiasSrc) + { + case LcdInResHighPower: + case LcdInResLowPower: + case LcdInResMidPower: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Mux = 1; + break; + case LcdExtCap: + case LcdExtRes: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Mux = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg32_35 = 0; + break; + default: + return ErrorInvalidParameter; + } + switch(pstcSegComPara->LcdDuty) + { + case LcdStatic: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~1u)&0x0fu; + break; + case LcdDuty2: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~3u)&0x0fu; + break; + case LcdDuty3: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~7u)&0x0fu; + break; + case LcdDuty4: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = (~15u)&0x0fu; + break; + case LcdDuty6: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg39Com4 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg38Com5 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg37Com6 = 1; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg36Com7 = 1; + break; + case LcdDuty8: + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Com0_3 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg39Com4 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg38Com5 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg37Com6 = 0; + pstcSegCom->stc_seg32_51_com0_8_t.segcom_bit.Seg36Com7 = 0; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} + +/** +****************************************************************************** + ** \brief LCD COMSEG端口配置，使用该函数之前需要先使能相应的Seg + ** + ** \param [in] pstcSegCom端口配置结构体 + ** + ** \retval enRet 成功或失败 + ** +******************************************************************************/ +void Lcd_SetSegCom(stc_lcd_segcom_t *pstcSegCom) +{ + M0P_LCD->POEN0 = pstcSegCom->u32Seg0_31; + M0P_LCD->POEN1 = pstcSegCom->stc_seg32_51_com0_8_t.seg32_51_com0_8; +} + +/** +****************************************************************************** + ** \brief LCD模块初始化函数 + ** + ** \param stcLcdCfg配置初始化结构体 + ** + ** \retval 无 + ** +******************************************************************************/ +void Lcd_Init(stc_lcd_cfg_t *pstcLcdCfg) +{ + M0P_LCD->CR0_f.BSEL = pstcLcdCfg->LcdBiasSrc; + M0P_LCD->CR0_f.DUTY = pstcLcdCfg->LcdDuty; + M0P_LCD->CR0_f.BIAS = pstcLcdCfg->LcdBias; + M0P_LCD->CR0_f.CPCLK = pstcLcdCfg->LcdCpClk; + M0P_LCD->CR0_f.LCDCLK = pstcLcdCfg->LcdScanClk; + M0P_LCD->CR1_f.MODE = pstcLcdCfg->LcdMode; + M0P_LCD->CR1_f.CLKSRC = pstcLcdCfg->LcdClkSrc; + M0P_LCD->CR0_f.EN = pstcLcdCfg->LcdEn; +} + +/** +****************************************************************************** + ** \brief 液晶全显 + ** + ** \param 无 + ** + ** \retval 无 + ** +******************************************************************************/ +void Lcd_FullDisp(void) +{ + uint8_t tmp; + volatile uint32_t *ram = NULL; + ram = &M0P_LCD->RAM0; + for(tmp=0;tmp<16;tmp++) + { + *ram = 0xffffffffu; + ram++; + } +} + +/** +****************************************************************************** + ** \brief 清屏 + ** + ** \param 无 + ** + ** \retval 无 + ** +******************************************************************************/ +void Lcd_ClearDisp(void) +{ + uint8_t tmp; + volatile uint32_t *ram = NULL; + ram = &M0P_LCD->RAM0; + for(tmp=0;tmp<16;tmp++) + { + *ram = 0; + ram++; + } +} + +/** + ****************************************************************************** + ** \brief LCD RAM 0-f寄存器设置函数 + ** + ** \param u8Row RAM地址索引，范围：0-15，u8Data写入寄存器数值 + ** + ** \retval enRet 成功或失败 + ** + ******************************************************************************/ +en_result_t Lcd_WriteRam(uint8_t u8Row,uint32_t u32Data) +{ + en_result_t enRet = Error; + volatile uint32_t *ram = NULL; + ram = (volatile uint32_t*)&M0P_LCD->RAM0; + + if (u8Row > 15) + { + enRet = ErrorInvalidParameter; + return enRet; + } + + ram += u8Row; + *ram = u32Data; + enRet = Ok; + return enRet; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lpm.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lpm.c new file mode 100644 index 0000000000..fad63101eb --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lpm.c @@ -0,0 +1,122 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file lpm.c + ** + ** Common API of lpm. + ** @link LpmGroup Some description @endlink + ** + ** - 2017-06-06 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_lpm.h" +/** + ******************************************************************************* + ** \addtogroup LpmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief 进入深度睡眠模式 + ** + ** \input bOnExit - TRUE:当退出异常处理后，自动再次进入休眠； + ** FALSE：唤醒后不再自动进入休眠 + ** + ** \retval NULL + *****************************************************************************/ +void Lpm_GotoDeepSleep(boolean_t bOnExit) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SCB->SCR |= 1u<SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + SCB->SCR |= 1u<CR)), 10, NewStatus); +} + +/** +****************************************************************************** + ** \brief 定时器LPTIMx的启动/停止控制 + ** @param Lptimx : LPTIM0 或LPTIM1 + ** @param NewStatus : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Lptim_Cmd(M0P_LPTIMER_TypeDef* Lptimx, boolean_t NewStatus) +{ + SetBit((uint32_t)(&(Lptimx->CR)), 0, NewStatus); +} + +/** +****************************************************************************** + ** \brief 定时器LPTIMx的中断标志位获取 + ** @param Lptimx : LPTIM0 或LPTIM1 + ** \retval TRUE 或 FALSE + ** +******************************************************************************/ +boolean_t Lptim_GetItStatus(M0P_LPTIMER_TypeDef* Lptimx) +{ + return GetBit((uint32_t)(&(Lptimx->IFR)), 0); +} + +/** +****************************************************************************** + ** \brief 定时器LPTIMx的中断标志位清除 + ** @param Lptimx : LPTIM0 或LPTIM1 + ** \retval 无 + ** +******************************************************************************/ +void Lptim_ClrItStatus(M0P_LPTIMER_TypeDef* Lptimx) +{ + SetBit((uint32_t)(&(Lptimx->ICLR)), 0, 0); +} + +/** +****************************************************************************** + ** \brief 定时器LPTIMx的初始化配置 + ** @param Lptimx : LPTIM0 或LPTIM1 + ** @param InitStruct : 初始化LPTIMx的结构体 + ** \retval en_result_t类型数据 + ** +******************************************************************************/ +en_result_t Lptim_Init(M0P_LPTIMER_TypeDef* Lptimx, stc_lptim_cfg_t* InitStruct) +{ + uint16_t u16TimeOut; + u16TimeOut = 1000; + Lptimx->CR_f.PRS = InitStruct->enPrs; + Lptimx->CR_f.TCK_SEL = InitStruct->enTcksel; + Lptimx->CR_f.GATE_P = InitStruct->enGatep; + Lptimx->CR_f.GATE = InitStruct->enGate; + Lptimx->CR_f.TOG_EN = InitStruct->enTogen; + Lptimx->CR_f.CT = InitStruct->enCt; + Lptimx->CR_f.MD = InitStruct->enMd; + while(u16TimeOut--) + { + if(Lptimx->CR_f.WT_FLAG) + { + break; + } + } + if(u16TimeOut == 0) + { + return ErrorTimeout; + } + Lptimx->ARR_f.ARR = InitStruct->u16Arr; + return Ok; +} + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lpuart.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lpuart.c new file mode 100644 index 0000000000..5a4a9429d2 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lpuart.c @@ -0,0 +1,409 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lpuart.c + ** + ** LPUART function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "hc32l196_lpuart.h" +/** + ****************************************************************************** + ** \addtogroup LPUartGroup + ******************************************************************************/ +//@{ +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief LPUART通信中断使能函数设置 + ** + ** \param [in] LPUARTx通道号，enIrqSel发送or接收中断使能 + ** + ** \retval OK配置成功 + **\retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t LPUart_EnableIrq(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_irq_sel_t enIrqSel) +{ + + SetBit((uint32_t)(&(LPUARTx->SCON)), enIrqSel, TRUE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通信中断禁止函数设置 + ** + ** \param [in] LPUARTx通道号，enIrqSel发送or接收中断禁止 + ** + ** \retval OK配置成功 + **\retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t LPUart_DisableIrq(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_irq_sel_t enIrqSel) +{ + + SetBit((uint32_t)(&(LPUARTx->SCON)), enIrqSel, FALSE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief lpuart通信时钟源选择 + ** + ** \param [in] LPUARTx通道号，enClk 时钟源选项 + ** + ** \retval Ok 设置成功 + **\retval ErrorInvalidParameter设置失败 + ******************************************************************************/ +en_result_t LPUart_SelSclk(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_sclksel_t enSclk) +{ + ASSERT(IS_VALID_CLK(enSclk)); + + LPUARTx->SCON_f.SCLKSEL = enSclk; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART通道多主机模式配置 + ** + ** \param [in] LPUARTx通道号，stcMultiCfg多主机模式结构 + ** + ** \retval OK配置成功 + **\retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t LPUart_SetMultiMode(M0P_LPUART_TypeDef* LPUARTx, stc_lpuart_multimode_t* pstcMultiCfg) +{ + + if(NULL != pstcMultiCfg) + { + LPUARTx->SCON_f.ADRDET = TRUE; + LPUARTx->SADDR = pstcMultiCfg->u8SlaveAddr; + LPUARTx->SADEN = pstcMultiCfg->u8SaddEn; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART单线半双工模式使能 + ** + ** \param [in] LPUARTx 通道号 + ** + ** \retval Null + ******************************************************************************/ +void LPUart_HdModeEnable(M0P_LPUART_TypeDef* LPUARTx) +{ + LPUARTx->SCON_f.HDSEL = TRUE; +} + + +/** + ****************************************************************************** + ** \brief LPUART单线半双工模式关闭 + ** + ** \param [in] LPUARTx 通道号 + ** + ** \retval Null + ******************************************************************************/ +void LPUart_HdModeDisable(M0P_LPUART_TypeDef* LPUARTx) +{ + LPUARTx->SCON_f.HDSEL = FALSE; +} + +/** + ****************************************************************************** + ** \brief LPUART通道多机模式发送数据/地址帧配置TB8 + ** + ** \param [in] LPUARTx 通道号 + ** \param [in] TRUE-TB8为地址帧标志；FALSE-TB8为数据帧标志； + ** + ** \retval Null + ******************************************************************************/ +void LPUart_SetTb8(M0P_LPUART_TypeDef* LPUARTx, boolean_t bTB8Value) +{ + LPUARTx->SCON_f.B8CONT = bTB8Value; + +} + +/** + ****************************************************************************** + ** \brief 获取RB8数值 + ** + ** \param [in] LPUARTx 通道号 + ** + ** \retval RB8 + **\retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +boolean_t LPUart_GetRb8(M0P_LPUART_TypeDef* LPUARTx) +{ + return (LPUARTx->SBUF_f.DATA8); +} +/** + ****************************************************************************** + ** \brief LPUART通道多主机模式从机地址配置函数 + ** + ** \param [in] LPUARTx 通道号，addr地址 + ** + ** \retval OK配置成功 + **\retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t LPUart_SetSaddr(M0P_LPUART_TypeDef* LPUARTx,uint8_t u8Addr) +{ + LPUARTx->SADDR = u8Addr; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART通道发送或接收等功能使能设置 + ** + ** \param [in] u8Idx通道号，enFunc功能 + ** + ** \retval OK配置成功 + **\retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t LPUart_EnableFunc(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_func_t enFunc) +{ + SetBit((uint32_t)(&(LPUARTx->SCON)), enFunc, TRUE); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART通道发送或接收等功能禁止设置 + ** + ** \param [in] u8Idx通道号，enFunc功能 + ** + ** \retval OK配置成功 + **\retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t LPUart_DisableFunc(M0P_LPUART_TypeDef* LPUARTx, en_lpuart_func_t enFunc) +{ + SetBit((uint32_t)(&(LPUARTx->SCON)), enFunc, FALSE); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART通道通信状态获取 + ** + ** \param [in] u8Idx通道号 + ** + ** \retval 状态值 + ******************************************************************************/ +uint8_t LPUart_GetIsr(M0P_LPUART_TypeDef* LPUARTx) +{ + return (LPUARTx->ISR); +} + +/** + ****************************************************************************** + ** \brief LPUART通道通信状态获取 + ** + ** \param [in] u8Idx通道号，enStatus获取哪个状态 + ** + ** \retval 状态值 + **\retval ErrorInvalidParameter获取失败 + ******************************************************************************/ +boolean_t LPUart_GetStatus(M0P_LPUART_TypeDef* LPUARTx,en_lpuart_status_t enStatus) +{ + boolean_t bStatus = FALSE; + + ASSERT(IS_VALID_STATUS(enStatus)); + + bStatus = GetBit((uint32_t)(&(LPUARTx->ISR)), enStatus); + + return bStatus; +} + +/** + ****************************************************************************** + ** \brief LPUART通道通信状态全部清除 + ** + ** \param [in] u8Idx通道号 + ** + ** \retval OK + ******************************************************************************/ +en_result_t LPUart_ClrIsr(M0P_LPUART_TypeDef* LPUARTx) +{ + LPUARTx->ICR = 0u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART通道通信状态清除 + ** + ** \param [in] u8Idx通道号，enStatus清除哪个状态 + ** + ** \retval 状态值 + **\retval ErrorInvalidParameter清除失败 + ******************************************************************************/ +en_result_t LPUart_ClrStatus(M0P_LPUART_TypeDef* LPUARTx,en_lpuart_status_t enStatus) +{ + ASSERT(IS_VALID_STATUS(enStatus)); + + SetBit((uint32_t)(&(LPUARTx->ICR)), enStatus, FALSE); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART通道发送数据函数,查询方式调用此函数，中断方式发送不适用 + ** + ** \param [in] u8Idx通道号，Data发送数据 + ** + ** \retval Ok发送成功 + **\retval ErrorInvalidParameter发送失败 + ******************************************************************************/ +en_result_t LPUart_SendData(M0P_LPUART_TypeDef* LPUARTx, uint8_t u8Data) +{ + while(FALSE == LPUart_GetStatus(LPUARTx,LPUartTxe)) + {} + LPUARTx->SBUF_f.DATA = u8Data; + while(FALSE == LPUart_GetStatus(LPUARTx,LPUartTC)) + {} + LPUart_ClrStatus(LPUARTx,LPUartTC); + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART通道发送数据函数,中断方式调用此函数 + ** + ** \param [in] u8Idx通道号，Data发送数据 + ** + ** \retval Ok发送成功 + **\retval ErrorInvalidParameter发送失败 + ******************************************************************************/ +en_result_t LPUart_SendDataIt(M0P_LPUART_TypeDef* LPUARTx, uint8_t u8Data) +{ + LPUARTx->SBUF_f.DATA = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LPUART通道接收数据函数 + ** + ** \param [in] u8Idx通道号 + ** + ** \retval 接收数据 + **\retval ErrorInvalidParameter接收失败 + ******************************************************************************/ +uint8_t LPUart_ReceiveData(M0P_LPUART_TypeDef* LPUARTx) +{ + return (LPUARTx->SBUF_f.DATA); +} + +/** + ****************************************************************************** + ** \brief LPUART通道初始化函数 + ** + ** \param [in] u8Idx通道号，pstcCfg初始化结构体 @ref stc_lpuart_cfg_t + ** + ** \retval OK配置成功 + **\retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t LPUart_Init(M0P_LPUART_TypeDef* LPUARTx,stc_lpuart_cfg_t* pstcCfg) +{ + en_result_t enRet = Error; + const uint32_t u32Over[3] = {0x4, 0x3, 0x2}; + uint16_t u16OverShift; + float32_t f32Scnt=0; + + if(NULL == pstcCfg) + { + return ErrorInvalidParameter; + } + + LPUARTx->SCON = 0; + + LPUARTx->SCON = (uint32_t)pstcCfg->enStopBit | + (uint32_t)pstcCfg->enMmdorCk | + (uint32_t)pstcCfg->stcBaud.enSclkDiv | + (uint32_t)pstcCfg->stcBaud.enSclkSel | + (uint32_t)pstcCfg->enRunMode; + + if((LPUartMskMode1 == pstcCfg->enRunMode) || (LPUartMskMode3 == pstcCfg->enRunMode)) + { + u16OverShift = u32Over[pstcCfg->stcBaud.enSclkDiv/LPUartMsk8Or16Div]; + f32Scnt = (float32_t)(pstcCfg->stcBaud.u32Sclk)/(float32_t)(pstcCfg->stcBaud.u32Baud<SCNT = (uint16_t)(float32_t)(f32Scnt + 0.5f); + LPUart_EnableFunc(LPUARTx,LPUartRenFunc); ///<使能收发 + } + + + + enRet = Ok; + return enRet; +} +//@} // LPUartGroup diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lvd.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lvd.c new file mode 100644 index 0000000000..b5068949aa --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_lvd.c @@ -0,0 +1,216 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lvd.c + ** + ** Low Voltage Detect driver API. + ** @link Lvd Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "hc32l196_lvd.h" + +/** + ****************************************************************************** + ** \addtogroup LvdGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_INPUT(x) ( (x) <= LvdInputPB07 ) + +#define IS_VALID_THRESHOLD(x) ( (x) <= LvdTH3p3V ) + +#define IS_VALID_FILTER(x) ( (x) <= LvdFilter29ms ) + +#define IS_VALID_IRQTYPE(x) ( (x) <= LvdIrqFall ) + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +// static void LvdEnableNvic(void); +// static void LvdDisableNvic(void); +// static en_result_t LvdEnable(en_lvd_type_t enType, boolean_t bFlag); + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ +/** + * \brief + * 使能LVD中断 + * + * \param [in] enType LVD中断类型 + * + * \retval en_result_t Ok: 设置成功 + * \retval en_result_t ErrorInvalidParameter: 无效类型 + */ +void Lvd_EnableIrq(void) +{ + M0P_LVD->CR_f.IE = TRUE; +} + +/** + * \brief + * 除能LVD中断 + * + * \param 无 + * + * \retval 无 + */ +void Lvd_DisableIrq(void) +{ + M0P_LVD->CR_f.IE = FALSE; +} + +/** + * \brief + * LVD初始化 + * + * \param [in] pstcCfg LVD配置指针 + * + * \retval 无 + */ +void Lvd_Init(stc_lvd_cfg_t *pstcCfg) +{ + M0P_LVD->CR = 0; + + M0P_LVD->CR = (uint32_t)pstcCfg->enAct | + (uint32_t)pstcCfg->enFilter | + (uint32_t)pstcCfg->enFilterTime | + (uint32_t)pstcCfg->enInputSrc | + (uint32_t)pstcCfg->enIrqType | + (uint32_t)pstcCfg->enThreshold; +} + +/** + * \brief + * 使能LVD + * + * \param 无 + * + * \retval 无 + * + */ +void Lvd_Enable(void) +{ + M0P_LVD->CR_f.LVDEN = 1u; +} + +/** + * \brief + * 除能LVD + * + * \param 无 + * + * \retval 无 + */ +void Lvd_Disable(void) +{ + M0P_LVD->CR_f.LVDEN = 0u; +} + +/** + * \brief + * 获取LVD中断标志 + * + * \param 无 + * + * \retval boolean_t 中断标志 + */ +boolean_t Lvd_GetIrqStat(void) +{ + return M0P_LVD->IFR_f.INTF; + +} + +/** + * \brief + * 清除LVD中断标志 + * + * \param 无 + * + * \retval 无 + */ +void Lvd_ClearIrq(void) +{ + M0P_LVD->IFR_f.INTF = 0u; +} + +/** + * \brief + * 获取Filter结果 + * + * \param 无 + * + * \retval boolean_t Fliter结果 + */ +boolean_t Lvd_GetFilterResult(void) +{ + return (boolean_t)M0P_LVD->IFR_f.FILTER; +} +//@} // LvdGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_opa.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_opa.c new file mode 100644 index 0000000000..668e4d3e35 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_opa.c @@ -0,0 +1,153 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file opa.c + ** + ** opa driver API. + ** @link opa Group Some description @endlink + ** + ** - 2019-04-11 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "hc32l196_opa.h" + +/** + ****************************************************************************** + ** \addtogroup OPAGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief OPA 通道使能 + ** + ** \param NewStatus : TRUE FALSE + ** \retval 无 + ** +******************************************************************************/ +void Opa_Cmd(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_OPA->CR0)), 0, NewStatus); +} + +void Opa_CmdBuf(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_OPA->CR0)), 2, NewStatus); +} + +/** +****************************************************************************** + ** \brief OPA零点校准配置 + ** + ** \param InitZero : + ** \retval 无 + ** +******************************************************************************/ +void Opa_SetZero(stc_opa_zcfg_t* InitZero) +{ + M0P_OPA->CR0_f.AZEN = InitZero->bAzen; + M0P_OPA->CR1_f.CLK_SW_SET = InitZero->bClk_sw_set; + M0P_OPA->CR1_f.AZ_PULSE = InitZero->bAz_pulse; + M0P_OPA->CR1_f.TRIGGER = InitZero->bTrigger; + M0P_OPA->CR1_f.ADCTR_EN = InitZero->bAdctr_en; +} + +/** +****************************************************************************** + ** \brief 使能输出OUTX + ** + ** \param onex : en_opa_oenx_t定义的元素 + ** \retval 无 + ** +******************************************************************************/ +void Opa_CmdOnex(en_opa_oenx_t onex, boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_OPA->CR0)), onex, NewState); //使能OP3输出X使能 +} + +/** +****************************************************************************** + ** \brief 配置校零相关的位 + ** + ** \param CtrlBit : en_opa_set0ctrl_t定义的元素 + ** \param NewState: TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Opa_ZeroBitCtrl(en_opa_set0ctrl_t CtrlBit, boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_OPA->CR1)), CtrlBit, NewState); +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_pca.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_pca.c new file mode 100644 index 0000000000..e22d9b07dc --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_pca.c @@ -0,0 +1,555 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file pca.c + ** + ** pca driver API. + ** @link pcnt Group Some description @endlink + ** + ** - 2019-04-09 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "hc32l196_pca.h" + +/** + ****************************************************************************** + ** \addtogroup PCNTGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/** +****************************************************************************** + ** \brief 获取中断源的标志位 + ** @param IT_Src : 中断源标志位 + ** \retval FALSE 或TRUE + ** +******************************************************************************/ +boolean_t Pca_GetItStatus(en_pca_ccficlr_t It_Src) +{ + return (((M0P_PCA->CCON)>>It_Src) & 1) > 0? TRUE : FALSE; +} + +/** +****************************************************************************** + ** \brief 清除中断源的标志位 + ** @param IT_Src : 中断源标志位 + ** \retval 无 + ** +******************************************************************************/ +void Pca_ClrItStatus(en_pca_ccficlr_t It_Src) +{ + M0P_PCA->ICLR &= ~(uint32_t)(1<CCON)), 6, NewStatus); +} + +/** +****************************************************************************** + ** \brief PCA 空闲模式IDLE下，PCA是否停止工作设置 + ** @param NewStatus : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Pca_SetCidl(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_PCA->CMOD)), 7, NewStatus); +} + +/** +****************************************************************************** + ** \brief PCA 模块4的看门狗使能控制 + ** @param NewStatus : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Pca_Set4Wdte(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_PCA->CMOD)), 6, NewStatus); +} + +/** +****************************************************************************** + ** \brief PCA 计数器中断控制PCA_CMOD中CFIE，对应的控制中断位PCA_CCON中的CF与PCA_ICLR中的CF + ** @param NewStatus : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Pca_ConfPcaIt(boolean_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_PCA->CMOD)), 0, NewStatus); +} + +/** +****************************************************************************** + ** \brief PCA 比较捕获中断使能控制 PCA_CCAPMx的CCIE + ** @param Modulex : pca_module0~4 + ** @param NewStatus : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Pca_ConfModulexIt(en_pca_module_t Modulex, boolean_t NewStatus) +{ + switch(Modulex) + { + case PcaModule0: + SetBit((uint32_t)(&(M0P_PCA->CCAPM0)), 0, NewStatus); + break; + case PcaModule1: + SetBit((uint32_t)(&(M0P_PCA->CCAPM1)), 0, NewStatus); + break; + case PcaModule2: + SetBit((uint32_t)(&(M0P_PCA->CCAPM2)), 0, NewStatus); + break; + case PcaModule3: + SetBit((uint32_t)(&(M0P_PCA->CCAPM3)), 0, NewStatus); + break; + case PcaModule4: + SetBit((uint32_t)(&(M0P_PCA->CCAPM4)), 0, NewStatus); + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief PCA 模块0的初始化 + ** @param InitStruct : PCA初始化配置的结构体 + ** \retval 无 + ** +******************************************************************************/ +void Pca_M0Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM0_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM0_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM0_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM0_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM0_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM0_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP0L_f.CCAP0 = InitStruct->pca_ccapl; + M0P_PCA->CCAP0H_f.CCAP0 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP0_f.CCAP0 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 模块1的初始化 + ** @param InitStruct : PCA初始化配置的结构体 + ** \retval 无 + ** +******************************************************************************/ +void Pca_M1Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM1_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM1_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM1_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM1_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM1_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM1_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP1L_f.CCAP1 = InitStruct->pca_ccapl; + M0P_PCA->CCAP1H_f.CCAP1 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP1_f.CCAP1 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 模块2的初始化 + ** @param InitStruct : PCA初始化配置的结构体 + ** \retval 无 + ** +******************************************************************************/ +void Pca_M2Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM2_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM2_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM2_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM2_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM2_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM2_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP2L_f.CCAP2 = InitStruct->pca_ccapl; + M0P_PCA->CCAP2H_f.CCAP2 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP2_f.CCAP2 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 模块3的初始化 + ** @param InitStruct : PCA初始化配置的结构体 + ** \retval 无 + ** +******************************************************************************/ +void Pca_M3Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM3_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM3_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM3_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM3_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM3_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM3_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP3L_f.CCAP3 = InitStruct->pca_ccapl; + M0P_PCA->CCAP3H_f.CCAP3 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP3_f.CCAP3 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 模块4的初始化 + ** @param InitStruct : PCA初始化配置的结构体 + ** \retval 无 + ** +******************************************************************************/ +void Pca_M4Init(stc_pcacfg_t* InitStruct) +{ + M0P_PCA->CMOD_f.CPS = InitStruct->pca_clksrc; + M0P_PCA->CMOD_f.CIDL = InitStruct->pca_cidl; + M0P_PCA->CCAPM4_f.ECOM = InitStruct->pca_ecom; + M0P_PCA->CCAPM4_f.CAPP = InitStruct->pca_capp; + M0P_PCA->CCAPM4_f.CAPN = InitStruct->pca_capn; + M0P_PCA->CCAPM4_f.MAT = InitStruct->pca_mat; + M0P_PCA->CCAPM4_f.TOG = InitStruct->pca_tog; + M0P_PCA->CCAPM4_f.PWM = InitStruct->pca_pwm; + M0P_PCA->EPWM_f.EPWM = InitStruct->pca_epwm; + if(InitStruct->pca_pwm == PcaPwm8bitEnable) + { + M0P_PCA->CCAP4L_f.CCAP4 = InitStruct->pca_ccapl; + M0P_PCA->CCAP4H_f.CCAP4 = InitStruct->pca_ccaph; + } + else + { + M0P_PCA->CCAP4_f.CCAP4 = InitStruct->pca_ccap; + } + M0P_PCA->CARR_f.CARR = InitStruct->pca_carr; +} + +/** +****************************************************************************** + ** \brief PCA 读取CNT寄存器的数值 + ** @param 无 + ** \retval CNT的低半字值 + ** +******************************************************************************/ +uint16_t Pca_GetCnt(void) +{ + return (uint16_t)(M0P_PCA->CNT); +} + +/** +****************************************************************************** + ** \brief PCA 向CNT寄存器写入数值 + ** @param cnt : 所要写入的数值 + ** \retval 无 + ** +******************************************************************************/ +void Pca_SetCnt(uint16_t cnt) +{ + if(GetBit((uint32_t)(&(M0P_PCA->CCON)), 6)==TRUE) + { + Pca_StartPca(FALSE); + M0P_PCA->CNT_f.CNT = cnt; + Pca_StartPca(TRUE); + } + else + { + M0P_PCA->CNT_f.CNT = cnt; + } + +} + +/** +****************************************************************************** + ** \brief PCA 返回指定通道比较高速输出标志寄存器的值 + ** @param Modulex : 通道号x=0、1、2、3、4 + ** \retval TRUE 或 FALSE + ** +******************************************************************************/ +boolean_t Pca_GetOut(en_pca_module_t Modulex) +{ + return GetBit((uint32_t)(&(M0P_PCA->CCAPO)), Modulex); +} + +/** +****************************************************************************** + ** \brief PCA 设置比较捕获16位寄存器CCAPx数值 + ** @param Modulex : 通道号x=0、1、2、3、4 + ** @param Value: 所要设置的值 + ** \retval 无 + ** +******************************************************************************/ +void Pca_SetCcap(en_pca_module_t Modulex, uint16_t Value) +{ + switch(Modulex) + { + case 0: + M0P_PCA->CCAP0_f.CCAP0 = Value; + break; + case 1: + M0P_PCA->CCAP1_f.CCAP1 = Value; + break; + case 2: + M0P_PCA->CCAP2_f.CCAP2 = Value; + break; + case 3: + M0P_PCA->CCAP3_f.CCAP3 = Value; + break; + case 4: + M0P_PCA->CCAP4_f.CCAP4 = Value; + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief PCA 读取比较捕获16位寄存器CCAPx数值 + ** @param Modulex : 通道号x=0、1、2、3、4 + ** \retval CCAPx的值，x=0、1、2、3、4 + ** +******************************************************************************/ +uint16_t Pca_GetCcap(en_pca_module_t Modulex) +{ + uint16_t tmp; + switch(Modulex) + { + case 0: + tmp = M0P_PCA->CCAP0_f.CCAP0; + break; + case 1: + tmp = M0P_PCA->CCAP1_f.CCAP1; + break; + case 2: + tmp = M0P_PCA->CCAP2_f.CCAP2; + break; + case 3: + tmp = M0P_PCA->CCAP3_f.CCAP3; + break; + case 4: + tmp = M0P_PCA->CCAP4_f.CCAP4; + break; + default: + break; + } + return tmp; +} + +/** +****************************************************************************** + ** \brief PCA 设置自动重装载寄存器数值 + ** @param 无 + ** \retval 无 + ** +******************************************************************************/ +void Pca_SetCarr(uint16_t Value) +{ + M0P_PCA->CARR_f.CARR = Value; +} + +/** +****************************************************************************** + ** \brief PCA 获取自动重装载寄存器数值 + ** @param 无 + ** \retval 无 + ** +******************************************************************************/ +uint16_t Pca_GetCarr(void) +{ + return M0P_PCA->CARR_f.CARR; +} + +/** +****************************************************************************** + ** \brief PCA 设置比较捕获寄存器的高8位和低8位 + ** @param Modulex : 通道号x=0、1、2、3、4 + ** @param ValueH : 要写入高8位的数值 + ** @param ValueL : 要写入低8位的数值 + ** \retval 无 + ** +******************************************************************************/ +void Pca_SetCcapHL(en_pca_module_t Modulex, uint8_t ValueH, uint8_t ValueL) +{ + switch(Modulex) + { + case 0: + M0P_PCA->CCAP0H_f.CCAP0 = ValueH; + M0P_PCA->CCAP0L_f.CCAP0 = ValueL; + break; + case 1: + M0P_PCA->CCAP1H_f.CCAP1 = ValueH; + M0P_PCA->CCAP1L_f.CCAP1 = ValueL; + break; + case 2: + M0P_PCA->CCAP2H_f.CCAP2 = ValueH; + M0P_PCA->CCAP2L_f.CCAP2 = ValueL; + break; + case 3: + M0P_PCA->CCAP3H_f.CCAP3 = ValueH; + M0P_PCA->CCAP3L_f.CCAP3 = ValueL; + break; + case 4: + M0P_PCA->CCAP4H_f.CCAP4 = ValueH; + M0P_PCA->CCAP4L_f.CCAP4 = ValueL; + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief PCA 读取比较捕获寄存器的高8位和低8位 + ** @param Modulex : 通道号x=0、1、2、3、4 + ** @param ValueH : CCAPx高8位的数值 + ** @param ValueL : CCAPx低8位的数值 + ** \retval 无 + ** +******************************************************************************/ +void Pca_GetCcapHL(en_pca_module_t Modulex, uint8_t *ValueH, uint8_t *ValueL) +{ + switch(Modulex) + { + case 0: + *ValueH = M0P_PCA->CCAP0H_f.CCAP0; + *ValueL = M0P_PCA->CCAP0L_f.CCAP0; + break; + case 1: + *ValueH = M0P_PCA->CCAP1H_f.CCAP1; + *ValueL = M0P_PCA->CCAP1L_f.CCAP1; + break; + case 2: + *ValueH = M0P_PCA->CCAP2H_f.CCAP2; + *ValueL = M0P_PCA->CCAP2L_f.CCAP2; + break; + case 3: + *ValueH = M0P_PCA->CCAP3H_f.CCAP3; + *ValueL = M0P_PCA->CCAP3L_f.CCAP3; + break; + case 4: + *ValueH = M0P_PCA->CCAP4H_f.CCAP4; + *ValueL = M0P_PCA->CCAP4L_f.CCAP4; + break; + default: + break; + } +} +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + + + + + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_pcnt.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_pcnt.c new file mode 100644 index 0000000000..a00f964523 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_pcnt.c @@ -0,0 +1,316 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file pcnt.c + ** + ** pcnt driver API. + ** @link pcnt Group Some description @endlink + ** + ** - 2019-04-08 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "hc32l196_pcnt.h" + +/** + ****************************************************************************** + ** \addtogroup PCNTGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + + +/** +****************************************************************************** + ** \brief PCNT的启动和停止控制 + ** @param NewState : Run_Enable 或者 Run_Disable + ** @param NewState : FALSE或者TRUE + ** \retval 无 + ** +******************************************************************************/ +boolean_t Pcnt_Cmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_PCNT->RUN)), 0, NewState); + return GetBit((uint32_t)(&(M0P_PCNT->RUN)), 0); +} + + +/** +****************************************************************************** + ** \brief 将BUF中的值同步到CNT + ** @param value : 要同步到TOP的数值 + ** \retval ok 或 ErrorTimeout + ** +******************************************************************************/ +en_result_t Pcnt_SetB2T(uint16_t value) +{ + uint16_t u16TimeOut; + + u16TimeOut = 1000; + M0P_PCNT->BUF = value; + M0P_PCNT->CMD_f.B2T = 1; + + while(u16TimeOut--) + { + if(M0P_PCNT->SR2_f.B2T == FALSE) + { + break; + } + } + if(u16TimeOut == 0) + { + return ErrorTimeout; + } + return Ok; +} + +/** +****************************************************************************** + ** \brief 将BUF中的值同步到CNT + ** @param value : 要同步到CNT的数值 + ** \retval ok 或 ErrorTimeout + ** +******************************************************************************/ +en_result_t Pcnt_SetB2C(uint16_t value) +{ + uint16_t u16TimeOut; + u16TimeOut = 1000; + M0P_PCNT->BUF = value; + M0P_PCNT->CMD_f.B2C = 1; + + while(u16TimeOut--) + { + if(M0P_PCNT->SR2_f.B2C == FALSE) + { + break; + } + } + if(u16TimeOut == 0) + { + return ErrorTimeout; + } + return Ok; +} + +/** +****************************************************************************** + ** \brief 将TOP中的值同步到CNT + ** @param value : 要同步到CNT的数值 + ** \retval ok 或 ErrorTimeout + ** +******************************************************************************/ +en_result_t Pcnt_SetT2C(void) +{ + uint16_t u16TimeOut; + u16TimeOut = 1000; + M0P_PCNT->CMD_f.T2C = 1; + while(u16TimeOut--) + { + if(M0P_PCNT->SR2_f.T2C == FALSE) + { + break; + } + } + if(u16TimeOut == 0) + { + return ErrorTimeout; + } + return Ok; +} + + +/** +****************************************************************************** + ** \brief 赋值BUF + ** @param value : 要赋值给BUF的数值 + ** \retval 无 + ** +******************************************************************************/ +void Pcnt_SetBuf(uint16_t value) +{ + M0P_PCNT->TOP_f.TOP = value; +} + +/** +****************************************************************************** + ** \brief 初始化 + ** @param start : 要同步到TOP的数值 + ** @param end : 要同步到CNT的数值 + ** \retval ok 或 ErrorTimeout + ** +******************************************************************************/ +void Pcnt_Init(stc_pcnt_initstruct_t* InitStruct) +{ + M0P_PCNT->CTRL_f.S1P = InitStruct->Pcnt_S1Sel; + M0P_PCNT->CTRL_f.S0P = InitStruct->Pcnt_S0Sel; + M0P_PCNT->CTRL_f.CLKSEL = InitStruct->Pcnt_Clk; + M0P_PCNT->CTRL_f.MODE = InitStruct->Pcnt_Mode; + if(InitStruct->Pcnt_Mode == PcntDoubleMode)//如果是双通道正交脉冲计数模式 + { + M0P_PCNT->SR1_f.DIR = InitStruct->Pcnt_Dir; + } + else + { + M0P_PCNT->CTRL_f.DIR = InitStruct->Pcnt_Dir; + } + M0P_PCNT->FLT_f.EN = InitStruct->Pcnt_FltEn; + M0P_PCNT->FLT_f.DEBTOP = InitStruct->Pcnt_DebTop; + M0P_PCNT->FLT_f.CLKDIV = InitStruct->Pcnt_ClkDiv; + M0P_PCNT->TOCR_f.EN = InitStruct->Pcnt_TocrEn; + M0P_PCNT->TOCR_f.TH = InitStruct->Pcnt_TocrTh; + + M0P_PCNT->DBG_f.DBG = InitStruct->Pcnt_Dbg; +} + +/** +****************************************************************************** + ** \brief 配置中断源的使能 + ** @param IT_Src : 中断源再PCNT_IEN内部的位位置 + ** @param NewState : FALSE 或TRUE + ** \retval 无 + ** +******************************************************************************/ +void Pcnt_ItCfg(en_pcnt_itfce_t IT_Src, boolean_t NewState) +{ + if(NewState == TRUE) + { + M0P_PCNT->IEN |= (uint32_t)(1<IEN &= ~(uint32_t)(1<IFR >> IT_Src) & 1u) > 0 ? TRUE : FALSE; +} + +/** +****************************************************************************** + ** \brief 清除中断源的标志位 + ** @param IT_Src : 中断源标志位 + ** \retval 无 + ** +******************************************************************************/ +void Pcnt_ClrItStatus(en_pcnt_itfce_t IT_Src) +{ + M0P_PCNT->ICR &= ~(uint32_t)(1<<(uint32_t)IT_Src); +} + + +/** +****************************************************************************** + ** \brief 获取PCNT_CNT寄存器的数值 + ** @param 无 + ** \retval PCNT_CNT数值 + ** +******************************************************************************/ +uint16_t Pcnt_GetCnt(void) +{ + return (uint16_t)(M0P_PCNT->CNT); +} + +/** +****************************************************************************** + ** \brief 获取PCNT_TOP寄存器的数值 + ** @param 无 + ** \retval PCNT_TOP数值 + ** +******************************************************************************/ +uint16_t Pcnt_GetTop(void) +{ + return (uint16_t)(M0P_PCNT->TOP); +} + +/** +****************************************************************************** + ** \brief 获取PCNT_BUF寄存器的数值 + ** @param 无 + ** \retval PCNT_BUF数值 + ** +******************************************************************************/ +uint16_t Pcnt_GetBuf(void) +{ + return (uint16_t)(M0P_PCNT->BUF); +} + +//@} // Group +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_ram.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_ram.c new file mode 100644 index 0000000000..9d3c45976f --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_ram.c @@ -0,0 +1,156 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file ram.c + ** + ** Common API of ram. + ** @link RamGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_ram.h" +/** + ******************************************************************************* + ** \addtogroup ramGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Ram奇偶校验出错地址获取 + ** + ** + ** \retval ERROR ADDRESS + *****************************************************************************/ +uint32_t Ram_ErrAddrGet(void) +{ + return M0P_RAM->ERRADDR; +} + +/** + ***************************************************************************** + ** \brief Ram中断标志获取 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Ram_GetIntFlag(void) +{ + if(M0P_RAM->IFR & 0x1) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ***************************************************************************** + ** \brief Ram中断标志清除 + ** + ** + ** \retval Null + *****************************************************************************/ +void Ram_ClearIntFlag(void) +{ + M0P_RAM->ICLR = 0u; +} + +/** + ***************************************************************************** + ** \brief Ram中断使能 + ** + ** \retval Null + *****************************************************************************/ +void Ram_EnableIrq (void) +{ + M0P_RAM->CR |= 0x2u; +} + +/** + ***************************************************************************** + ** \brief ram中断禁止 + ** + ** \retval Null + *****************************************************************************/ +void Ram_DisableIrq(void) +{ + M0P_RAM->CR &= 0x1; +} + + +//@} // RamGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_reset.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_reset.c new file mode 100644 index 0000000000..32846b9c3b --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_reset.c @@ -0,0 +1,184 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file reset.c + ** + ** Common API of reset. + ** @link resetGroup Some description @endlink + ** + ** - 2017-05-04 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_reset.h" + +/** + ******************************************************************************* + ** \addtogroup ResetGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief 获取复位源类型. + ** + ** \param [out] enRstFlg @ref en_reset_flag_t + ** + ** \retval TRUE or FALSE + ******************************************************************************/ +boolean_t Reset_GetFlag(en_reset_flag_t enRstFlg) +{ + if(M0P_RESET->RESET_FLAG&enRstFlg) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ******************************************************************************* + ** \brief 清除复位源类型. + ** + ** \param [in] pstcFlag @ref en_reset_flag_t + ** + ** \retval Null + ******************************************************************************/ +void Reset_ClearFlag(en_reset_flag_t enRstFlg) +{ + M0P_RESET->RESET_FLAG &= ~(uint32_t)enRstFlg; +} + +/** + ******************************************************************************* + ** \brief 清除所有复位源类型. + ** + ** \param Null + ** + ** \retval Null + ******************************************************************************/ +void Reset_ClearFlagAll(void) +{ + M0P_RESET->RESET_FLAG = 0; +} + +/** + ******************************************************************************* + ** \brief 所有模块进行一次复位. + ** + ** + ** \retval Null + ******************************************************************************/ +void Reset_RstPeripheralAll(void) +{ + M0P_RESET->PERI_RESET0 = 0u; + M0P_RESET->PERI_RESET0 = 0xFFFFFFFFu; + M0P_RESET->PERI_RESET1 = 0u; + M0P_RESET->PERI_RESET1 = 0xFFFFFFFFu; +} + +/** + ******************************************************************************* + ** \brief 对外设源0模块进行一次复位. + ** + ** \param [in] enPeri @ref en_reset_peripheral0_t + ** + ** \retval Null + ******************************************************************************/ +void Reset_RstPeripheral0(en_reset_peripheral0_t enPeri) +{ + M0P_RESET->PERI_RESET0 &= ~(uint32_t)enPeri; + M0P_RESET->PERI_RESET0 |= (uint32_t)enPeri; +} + +/** + ******************************************************************************* + ** \brief 对外设源1模块进行一次复位. + ** + ** \param [in] enPeri @ref en_reset_peripheral1_t + ** + ** \retval Null + ******************************************************************************/ +void Reset_RstPeripheral1(en_reset_peripheral1_t enPeri) +{ + M0P_RESET->PERI_RESET1 &= ~(uint32_t)enPeri; + M0P_RESET->PERI_RESET1 |= (uint32_t)enPeri; +} + +//@} // ResetGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_rtc.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_rtc.c new file mode 100644 index 0000000000..c23f6180a5 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_rtc.c @@ -0,0 +1,520 @@ +/************************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file rtc.c + ** + ** RTC function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2019-04-10 First version + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "hc32l196_rtc.h" +/** + ****************************************************************************** + ** \addtogroup RtcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('const') */ +/******************************************************************************/ +const uint8_t Leap_Month_Base[] = {3,6,0,3,5,1,3,6,2,4,0,2}; +const uint8_t NonLeap_Month_Base[] = {4,0,0,3,5,1,3,6,2,4,0,2}; +const uint8_t Cnst_Month_Tbl[12]={0x31,0x28,0x31,0x30,0x31,0x30,0x31,0x31,0x30,0x31,0x30,0x31}; +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable prototypes ('static') */ +/******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief RTC计数器的使能或停止 + ** + ** @param NewState : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Rtc_Cmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_RTC->CR0)), 7, NewState); +} + +/** +****************************************************************************** + ** \brief RTC计数器启动等待函数，如启动RTC计数器后立即进入低功耗模式， + ** 进入低功耗模式之前需执行此函数，以确保RTC已启动完成 + ** + ** @param NewState : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Rtc_StartWait(void) +{ + M0P_RTC->CR1_f.WAIT = 1; + while (M0P_RTC->CR1_f.WAITF != 1) //等待直到WAITF=1 + { + ; + } + M0P_RTC->CR1_f.WAIT = 0; + while (M0P_RTC->CR1_f.WAITF != 0) //等待直到WAITF=0 + { + ; + } +} + +/** +****************************************************************************** + ** \brief RTC的1Hz输出的使能或停止 + ** @param pricision : RtcHz1selGeneralPricision 或 RtcHz1selHighPricision + ** @param NewState : Hz1o_Disable 或 HZ1o_Enable + ** \retval 无 + ** +******************************************************************************/ +void Rtc_Hz1Cmd(en_rtc_hz1sel_t pricision, boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_RTC->CR0)), 6, pricision); //设置普通精度或者高精度1Hz输出 + SetBit((uint32_t)(&(M0P_RTC->CR0)), 5, NewState); //设置1Hz输出使能或禁止 +} + +/** +****************************************************************************** + ** \brief 设置周期中断的类型(PRDSEL)及其所选类型的时间(PRDS或PRDX) + ** + ** @param pstCyc: 根据结构体的定义设置PRDSEL、PRDS与PRDX + ** \retval Ok、Error 或 ErrorInvalidParameter + ** +******************************************************************************/ +en_result_t Rtc_SetCyc(stc_rtc_cyccfg_t* pstCyc) +{ + en_result_t enRet = Error; + M0P_RTC->CR0_f.PRDSEL = pstCyc->rtcPrdsel; + if(pstCyc->rtcPrdsel == RtcPrds) + { + M0P_RTC->CR0_f.PRDS = pstCyc->rtcPrds; + } + else if(pstCyc->rtcPrdsel == RtcPrdx) + { + if(pstCyc->rtcPrdx>=64) + { + enRet = ErrorInvalidParameter; + return enRet; + } + M0P_RTC->CR0_f.PRDX = pstCyc->rtcPrdx; + } + else + { + ; + } + enRet = Ok; + return enRet; +} + +/** +****************************************************************************** + ** \brief RTC闹钟中断的使能或停止 + ** + ** @param NewState : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Rtc_AlmIeCmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_RTC->CR1)), 3, 0); //清除周期中断标志位 + SetBit((uint32_t)(&(M0P_RTC->CR1)), 4, 0); //清除周期中断标志位 + SetBit((uint32_t)(&(M0P_RTC->CR1)), 6, NewState); +} + +/** +****************************************************************************** + ** \brief RTC闹钟的使能或停止 + ** + ** @param NewState : Almen_Disable 或 Almen_Enable + ** \retval 无 + ** +******************************************************************************/ +void Rtc_AlmEnCmd(boolean_t NewState) +{ + SetBit((uint32_t)(&(M0P_RTC->CR1)), 7, NewState); +} + +/** +****************************************************************************** + ** \brief 获取RTC闹钟中断状态位 + ** + ** @param 无 + ** \retval TRUE 或 FALSE + ** +******************************************************************************/ +boolean_t Rtc_GetAlmfItStatus(void) +{ + return GetBit((uint32_t)(&(M0P_RTC->CR1)), 4); +} + +/** +****************************************************************************** + ** \brief 清除RTC闹钟中断状态位 + ** + ** @param 无 + ** \retval 无 + ** +******************************************************************************/ +void Rtc_ClearAlmfItStatus(void) +{ + SetBit((uint32_t)(&(M0P_RTC->CR1)), 4, 0); +} + +/** +****************************************************************************** + ** \brief 清除RTC周期中断状态位 + ** + ** @param 无 + ** \retval 无 + ** +******************************************************************************/ +void Rtc_ClearPrdfItStatus(void) +{ + SetBit((uint32_t)(&(M0P_RTC->CR1)), 3, 0); +} + +/** +****************************************************************************** + ** \brief 获取RTC周期中断状态位 + ** + ** @param 无 + ** \retval TRUE 或 FALSE + ** +******************************************************************************/ +boolean_t Rtc_GetPridItStatus(void) +{ + return GetBit((uint32_t)(&(M0P_RTC->CR1)), 3); +} + +/** +****************************************************************************** + ** \brief 配置RTC的误差补偿寄存器 + ** + ** @param CompValue:数值的范围为：32-256 + ** @param NewStatus: RtcCompenDisable 或 RtcAmCompenEnable + ** \retval Ok ErrorInvalidParameter + ** +******************************************************************************/ +en_result_t Rtc_CompCfg(uint16_t CompVlue, en_rtc_compen_t NewStatus) +{ + en_result_t enRet = Error; + if(CompVlue<=256) + { + M0P_RTC->COMPEN_f.EN = NewStatus; + M0P_RTC->COMPEN_f.CR = CompVlue; + } + else + { + enRet = ErrorInvalidParameter; + } + return enRet; +} + +/** + ****************************************************************************** + ** \brief RTC根据日期计算周数 + ** + ** \param pu8buf时间数据 + ** \param u8limit_min最小值 + ** \param u8limit_max最大值 + ** + ** \retval Error 错误，Ok校验正确 + ** + ******************************************************************************/ +en_result_t Check_BCD_Format(uint8_t u8data,uint8_t u8limit_min, uint8_t u8limit_max) +{ + + if (((u8data & 0x0F) > 0x09) || ((u8data & 0xF0) > 0x90) + ||(u8data > u8limit_max) || (u8data < u8limit_min)) + { + return Error; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief RTC 平、闰年检测 + ** +** \param u8year:年十进制低两位:0-99 + ** + ** \retval 1:闰年 0：平年 + ** + ******************************************************************************/ +uint8_t Rtc_CheckLeapYear(uint8_t u8year) +{ + uint16_t tmp; + tmp=2000+u8year; + if((((tmp % 4)==0) && ((tmp % 100) !=0))|| ((tmp % 400) ==0)) + { + return 1; + } + else + { + return 0; + } +} + +/** + ****************************************************************************** + ** \brief RTC根据年获取二月的天数 + ** + ** \param [in] u8month月份，u8year年份 + ** +** \retval u8day天数:28或29 + ** + ******************************************************************************/ +uint8_t Get_Month2_Day( uint8_t u8year) +{ + uint8_t u8day = 0; + + u8day = 28; + if(Rtc_CheckLeapYear(u8year) == 1) + { + u8day++; + } + return u8day; +} + +/** + ****************************************************************************** + ** \brief RTC获取时间函数 + ** + ** \param time: 用于存放读取自时间寄存器的时间数据，格式为BCD码格式 + ** + ** \retval Ok 获取正常 + ** \retval ErrorTimeout 时间溢出错误 + ******************************************************************************/ +en_result_t Rtc_ReadDateTime(stc_rtc_time_t* time) +{ + uint32_t u32TimeOut; + ASSERT(NULL != pstcTimeDate); + u32TimeOut = 1000; + if(1 == M0P_RTC->CR0_f.START) + { + M0P_RTC->CR1_f.WAIT = 1; + while(u32TimeOut--) + { + if(M0P_RTC->CR1_f.WAITF) + { + break; + } + } + if(u32TimeOut==0) + { + return ErrorTimeout; + } + } + time->u8Second = M0P_RTC->SEC; + time->u8Minute = M0P_RTC->MIN; + if(1 == M0P_RTC->CR0_f.AMPM) + { + time->u8Hour = M0P_RTC->HOUR; + } + else + { + time->u8Hour = M0P_RTC->HOUR&0x1f; + } + time->u8Day = M0P_RTC->DAY; + time->u8DayOfWeek = M0P_RTC->WEEK; + time->u8Month = M0P_RTC->MON; + time->u8Year = M0P_RTC->YEAR; + + M0P_RTC->CR1_f.WAIT = 0; + if(1 == M0P_RTC->CR0_f.START) + { + while(M0P_RTC->CR1_f.WAITF) + {} + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief 向RTC时间寄存器写入时间 + ** + ** \param time： 存放时间的结构体，各个时间均为BCD码格式 + ** + ** \retval ErrorTimeout 或 Ok + ** + ******************************************************************************/ +en_result_t Rtc_SetTime(stc_rtc_time_t* time) +{ + en_result_t enRet = Ok; + uint16_t u16TimeOut; + u16TimeOut = 1000; + if(M0P_RTC->CR0_f.START == 1) + { + M0P_RTC->CR1_f.WAIT = 1; + while(--u16TimeOut) + { + if(M0P_RTC->CR1_f.WAITF) + { + break; + } + } + if(u16TimeOut==0) + { + return ErrorTimeout; + } + } + M0P_RTC->SEC = time->u8Second; + M0P_RTC->MIN = time->u8Minute; + M0P_RTC->HOUR = time->u8Hour; + M0P_RTC->DAY = time->u8Day; + M0P_RTC->MON = time->u8Month; + M0P_RTC->YEAR = time->u8Year; + M0P_RTC->WEEK = time->u8DayOfWeek; + + M0P_RTC->CR1_f.WAIT = 0; + if(M0P_RTC->CR0_f.START == 1) + { + while(M0P_RTC->CR1_f.WAITF) + {} + } + enRet = Ok; + return enRet; +} + +/** + ****************************************************************************** + ** \brief RTC闹钟中断时间获取 + ** + ** \param pstcAlarmTime：存放闹钟时间寄存器数据：秒 分 时 周 + ** + ** \retval 无 + ** + ******************************************************************************/ +void Rtc_GetAlarmTime(stc_rtc_alarmtime_t* pstcAlarmTime) +{ + pstcAlarmTime->RtcAlarmSec = M0P_RTC->ALMSEC; + pstcAlarmTime->RtcAlarmMinute = M0P_RTC->ALMMIN; + pstcAlarmTime->RtcAlarmHour = M0P_RTC->ALMHOUR; + pstcAlarmTime->RtcAlarmWeek = M0P_RTC->ALMWEEK; +} + +/** + ****************************************************************************** + ** \brief RTC闹钟设置 + ** + ** \param [in] pstcAlarmTime闹钟时间：秒 分 时 周 + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_SetAlarmTime(stc_rtc_alarmtime_t* pstcAlarmTime) +{ + en_result_t enRet = Ok; +// ASSERT(NULL != pstcAlarmTime); + Rtc_AlmEnCmd(FALSE); //闹钟禁止以后再设置闹钟时间 + enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmSec,0x00,0x59); + if(M0P_RTC->CR0_f.AMPM == RtcAm) + { + enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmHour,0x00,0x12); + } + else + { + enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmHour,0x00,0x24); + } + if(enRet != Ok) + { + return enRet; + } + enRet = Check_BCD_Format(pstcAlarmTime->RtcAlarmMinute,0x00,0x59); + if(enRet != Ok) + { + return enRet; + } + + if(enRet != Ok) + { + return enRet; + } + M0P_RTC->ALMSEC = pstcAlarmTime->RtcAlarmSec & 0x7f; + M0P_RTC->ALMMIN = pstcAlarmTime->RtcAlarmMinute & 0x7f; + M0P_RTC->ALMHOUR = pstcAlarmTime->RtcAlarmHour & 0x3f; + M0P_RTC->ALMWEEK = pstcAlarmTime->RtcAlarmWeek; + Rtc_AlmEnCmd(TRUE); //闹钟许可 + enRet = Ok; + return enRet; +} + +/** +****************************************************************************** + ** \brief 初始化RTC + ** + ** @param Rtc_InitStruct 存放stc_rtc_initstruct_t类型的结构体 + ** \retval 无 + ** +******************************************************************************/ +void Rtc_Init(stc_rtc_initstruct_t* Rtc_InitStruct) +{ + Rtc_Cmd(FALSE); + M0P_RTC->CR0_f.AMPM = Rtc_InitStruct->rtcAmpm; //实时时钟小时的时制 + Rtc_SetCyc(&Rtc_InitStruct->rtcPrdsel); //设置周期中断的类型(PRDSEL)及其所选类型的时间(PRDS或PRDX) + M0P_RTC->CR1_f.CKSEL = Rtc_InitStruct->rtcClksrc; //实时时钟RTC的时钟源 + Rtc_CompCfg(Rtc_InitStruct->rtcCompValue, Rtc_InitStruct->rtcCompen); //配置时钟误差补偿寄存器 + Rtc_SetTime(&Rtc_InitStruct->rtcTime); //设置初始时钟 +} + + + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_spi.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_spi.c new file mode 100644 index 0000000000..b13177a85e --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_spi.c @@ -0,0 +1,352 @@ +/****************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with eaenCh copy of this software, whether used in part or whole, +* at all times. +*/ +/*****************************************************************************/ +/** \file spi.c + ** + ** SPI driver API. + ** @link Driver Group Some description @endlink + ** + ** - 2018-05-17 1.0 Devi First version for Device Driver Library of + ** Module. + ** + *****************************************************************************/ + +/****************************************************************************** + * Include files + *****************************************************************************/ +#include "hc32l196_spi.h" + +/** + ****************************************************************************** + ** \addtogroup SpiGroup + *****************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + *****************************************************************************/ + +#define IS_VALID_STAT(x) ( SpiIf == (x)||\ + SpiSserr == (x)||\ + SpiBusy == (x)||\ + SpiMdf == (x)||\ + SpiTxe == (x)||\ + SpiRxne == (x)) + + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable prototypes ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief SPI 请求状态获取 + ** + ** \param [in]SPIx 通道， enStatus 获取请求 + ** + ** \retval 请求状态 + ** + ******************************************************************************/ +boolean_t Spi_GetStatus(M0P_SPI_TypeDef* SPIx, en_spi_status_t enStatus) +{ + ASSERT(IS_VALID_STAT(enStatus)); + + if(SPIx->STAT&enStatus) + { + return TRUE; + } + else + { + return FALSE; + } + +} +/** + ****************************************************************************** + ** \brief SPI中断清除 + ** + ** \param [in]SPIx 通道选择 + ** + ** \retval 请求状态 + ** + ******************************************************************************/ +en_result_t Spi_ClearStatus(M0P_SPI_TypeDef* SPIx) +{ + SPIx->ICLR = 0; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 中断使能函数 + ** + ** \param [in] SPIx 通道 + ** + ** \retval Ok成功 + ** + ******************************************************************************/ +en_result_t Spi_IrqEnable(M0P_SPI_TypeDef* SPIx) +{ + SPIx->CR2 |= 0x4u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 中断禁止函数 + ** + ** \param [in] enCh通道 + ** + ** \retval Ok成功 + ** + ******************************************************************************/ +en_result_t Spi_IrqDisable(M0P_SPI_TypeDef* SPIx) +{ + SPIx->CR2 &= ~0x4u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 功能使能函数 + ** + ** \param [in] SPIx 通道，enFunc功能 + ** + ** \retval Ok初始化成功 + ** + ******************************************************************************/ +en_result_t Spi_FuncEnable(M0P_SPI_TypeDef* SPIx, en_spi_func_t enFunc) +{ + SPIx->CR2 |= enFunc; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 功能禁止函数 + ** + ** \param [in] SPIx 通道，enFunc功能 + ** + ** \retval Ok初始化成功 + ** + ******************************************************************************/ +en_result_t Spi_FuncDisable(M0P_SPI_TypeDef* SPIx, en_spi_func_t enFunc) +{ + SPIx->CR2 &= ~(uint32_t)enFunc; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 总体初始化函数 + ** + ** \param [in] SPIx 通道 + ** \param [in] pstcSpiCfg 初始化结构体 + ** + ** \retval Ok初始化成功 + ** \retval ErrorInvalidParameter 初始化错误 + ******************************************************************************/ +en_result_t Spi_Init(M0P_SPI_TypeDef* SPIx, stc_spi_cfg_t *pstcSpiCfg) +{ + ASSERT(NULL != pstcSpiCfg); + + SPIx->CR = 0; + + SPIx->SSN = TRUE; + + SPIx->CR = (uint32_t)pstcSpiCfg->enSpiMode | + (uint32_t)pstcSpiCfg->enPclkDiv | + (uint32_t)pstcSpiCfg->enCPOL | + (uint32_t)pstcSpiCfg->enCPHA | + (uint32_t)0x40; + + SPIx->STAT = 0x00; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 配置主发送的电平 + ** + ** \param [in] SPIx 通道选择，bFlag高低电平 + ** + ** \retval 无 + ** + ******************************************************************************/ +void Spi_SetCS(M0P_SPI_TypeDef* SPIx, boolean_t bFlag) +{ + SPIx->SSN = bFlag; +} +/** + ****************************************************************************** + ** \brief SPI 发送一字节函数 + ** + ** \param [in] SPIx 通道选择，u8Data发送字节 + ** + ** \retval Ok发送成功 + ** + ******************************************************************************/ +en_result_t Spi_SendData(M0P_SPI_TypeDef* SPIx, uint8_t u8Data) +{ + SPIx->DATA = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 读/写一字节函数 + ** + ** \param [in] SPIx 通道选择 + ** \param [in] u8Data 发送一字节数据 + ** + ** \retval 接收一字节数据 + ** + ******************************************************************************/ +uint8_t Spi_RWByte(M0P_SPI_TypeDef* SPIx, uint8_t u8Data) +{ + while(FALSE == SPIx->STAT_f.TXE){;} + SPIx->DATA = u8Data; + while(FALSE == SPIx->STAT_f.RXNE){;} + return SPIx->DATA; +} + +/** + ****************************************************************************** +** \brief SPI 从机预准备第一字节数据 + ** + ** \param [in] SPIx 通道选择 + ** \param [in] u8Data 预准备第一字节数据 + ** + ** \retval None + ** + ******************************************************************************/ +void Spi_Slave_DummyWriteData(M0P_SPI_TypeDef* SPIx, uint8_t u8Data) +{ + while(FALSE == SPIx->STAT_f.TXE){;} + SPIx->DATA = u8Data; +} + +/** + ****************************************************************************** + ** \brief SPI 连续发送多字节函数 + ** + ** \param [in] SPIx 通道选择 + ** \param [in] pu8Buf 发送数据指针 + ** + ** \retval Ok发送成功 + ** + ******************************************************************************/ +en_result_t Spi_SendBuf(M0P_SPI_TypeDef* SPIx, uint8_t* pu8Buf, uint32_t u32Len) +{ + uint32_t u32Index=0; + + for(u32Index=0; u32IndexSTAT_f.TXE){;} + SPIx->DATA = pu8Buf[u32Index]; + while(FALSE == SPIx->STAT_f.RXNE){;} + pu8Buf[u32Index] = SPIx->DATA; + } + + while(FALSE == SPIx->STAT_f.TXE){;} + while(TRUE == SPIx->STAT_f.BUSY){;} + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 接收一字节函数 + ** + ** \param [in] SPIx接收通道 + ** + ** \retval 接收一字节数据 + ** + ******************************************************************************/ +uint8_t Spi_ReceiveData(M0P_SPI_TypeDef* SPIx) +{ + return SPIx->DATA; +} + +/** + ****************************************************************************** + ** \brief SPI 连续接收多字节函数 + ** + ** \param [in] SPIx 通道选择 + ** \param [in] pu8Buf 发送数据指针 + ** + ** \retval Ok发送成功 + ** + ******************************************************************************/ +en_result_t Spi_ReceiveBuf(M0P_SPI_TypeDef* SPIx, uint8_t* pu8Buf, uint32_t u32Len) +{ + uint32_t u32Index=0; + + for(u32Index=0; u32IndexSTAT_f.TXE){;} + SPIx->DATA = 0x00; + while(FALSE == SPIx->STAT_f.RXNE){;} + pu8Buf[u32Index] = SPIx->DATA; + } + + while(TRUE == SPIx->STAT_f.BUSY){;} + + return Ok; +} + +//@} // SpiGroup +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_sysctrl.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_sysctrl.c new file mode 100644 index 0000000000..1ac727d38c --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_sysctrl.c @@ -0,0 +1,746 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file sysctrl.c + ** + ** Common API of sysctrl. + ** @link SysctrlGroup Some description @endlink + ** + ** - 2018-04-22 Lux + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_sysctrl.h" + +/** + ******************************************************************************* + ** \addtogroup SysctrlGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CLK_TIMEOUT (1000000u) + +#define IS_VALID_SRC(x) ( ClkRCH == (x)||\ + ClkXTH == (x)||\ + ClkRCL == (x)||\ + ClkXTL == (x) ) + + +#define IS_VALID_FUNC(x) ( ClkFuncWkupRCH == (x)||\ + ClkFuncXTHEn == (x)||\ + ClkFuncXTLEn == (x)||\ + ClkFuncXTLAWSON == (x)||\ + ClkFuncFaultEn == (x)||\ + ClkFuncRtcLPWEn == (x)||\ + ClkFuncLockUpEn == (x)||\ + ClkFuncRstPinIOEn == (x)||\ + ClkFuncSwdPinIOEn == (x) ) + +#define RC_TRIM_BASE_ADDR ((volatile uint16_t*) (0x00100C00ul)) +#define RCH_CR_TRIM_24M_VAL (*((volatile uint16_t*) (0x00100C00ul))) +#define RCH_CR_TRIM_22_12M_VAL (*((volatile uint16_t*) (0x00100C02ul))) +#define RCH_CR_TRIM_16M_VAL (*((volatile uint16_t*) (0x00100C04ul))) +#define RCH_CR_TRIM_8M_VAL (*((volatile uint16_t*) (0x00100C06ul))) +#define RCH_CR_TRIM_4M_VAL (*((volatile uint16_t*) (0x00100C08ul))) + +#define RCL_CR_TRIM_38400_VAL (*((volatile uint16_t*) (0x00100C20ul))) +#define RCL_CR_TRIM_32768_VAL (*((volatile uint16_t*) (0x00100C22ul))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern uint32_t SystemCoreClock; +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SYSCTRL0\SYSCTRL1寄存器操作解锁 + ** + ** \retval None + ******************************************************************************/ +static void _SysctrlUnlock(void) +{ + M0P_SYSCTRL->SYSCTRL2 = 0x5A5A; + M0P_SYSCTRL->SYSCTRL2 = 0xA5A5; +} + +/** + ******************************************************************************* + ** \brief 系统时钟源使能 + ** \param [in] enSource 目标时钟源 + ** \param [in] bFlag 使能1-开/0-关 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag) +{ + en_result_t enRet = Ok; + uint32_t u32Temp; + + _SysctrlUnlock(); + bFlag = !!bFlag; + + u32Temp = M0P_SYSCTRL->PERI_CLKEN0; + switch (enSource) + { + case SysctrlClkRCH: + M0P_SYSCTRL->SYSCTRL0_f.RCH_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->RCH_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkXTH: + M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = TRUE; + M0P_GPIO->PFADS |= 3u; + M0P_SYSCTRL->SYSCTRL0_f.XTH_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->XTH_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkRCL: + + M0P_SYSCTRL->SYSCTRL0_f.RCL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->RCL_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkXTL: + M0P_SYSCTRL->PERI_CLKEN0_f.GPIO = TRUE; + M0P_GPIO->PCADS |= 0xC000; + M0P_SYSCTRL->SYSCTRL0_f.XTL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->XTL_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkPLL: + M0P_SYSCTRL->PERI_CLKEN0_f.ADC = TRUE; + M0P_BGR->CR_f.BGR_EN = TRUE; + delay10us(20); + M0P_SYSCTRL->SYSCTRL0_f.PLL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->PLL_CR_f.STABLE)) + { + ; + } + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + M0P_SYSCTRL->PERI_CLKEN0 = u32Temp; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部高速晶振驱动配置 + ** \param [in] enFreq 外部高速晶振频率范围选择 + ** \param [in] enDriver 外部高速晶振驱动能力选择 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_XTHDriverCfg(en_sysctrl_xtal_driver_t enDriver) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTH_CR_f.DRIVER = enDriver; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部低速晶振驱动配置 + ** \param [in] enFreq 外部低速晶振频率范围选择 + ** \param [in] enDriver 外部低速晶振驱动能力选择 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_XTLDriverCfg(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTL_CR_f.AMP_SEL = enAmp; + M0P_SYSCTRL->XTL_CR_f.DRIVER = enDriver; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部高速时钟稳定周期配置 + ** \param [in] enCycle 外部高速时钟稳定周期设置 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->XTH_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部低速时钟稳定周期配置 + ** \param [in] enCycle 内部低速时钟稳定周期设置 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->RCL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部低速时钟稳定周期配置 + ** \param [in] enCycle 外部低速时钟稳定周期设置 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->XTL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief PLL稳定周期配置 + ** \param [in] enCycle PLL稳定周期设置 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->PLL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 时钟源切换，该函数执行后会开启新时钟源 + ** \note 选择时钟源之前，需根据需要配置目标时钟源的频率/驱动参数/使能时钟源等 + ** \param [in] enSource 新时钟源 + ** + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource) +{ + en_result_t enRet = Ok; + + en_sysctrl_clk_source_t ClkNew = enSource; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.CLKSW = ClkNew; + + //更新Core时钟（HCLK） + SystemCoreClockUpdate(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 获得系统时钟（HCLK）频率值 + ** \retval uint32_t HCLK频率值 + ** + ******************************************************************************/ +uint32_t Sysctrl_GetHClkFreq(void) +{ + uint32_t u32Val = 0; + const uint32_t u32hcr_tbl[] = { 4000000, 8000000, 16000000, 22120000, 24000000}; + const uint16_t u32lcr_tbl[] = { 32768, 38400}; + en_sysctrl_clk_source_t enSrc; + uint16_t u16Trim[5] = {0}; + u16Trim[4] = RCH_CR_TRIM_24M_VAL; + u16Trim[3] = RCH_CR_TRIM_22_12M_VAL; + u16Trim[2] = RCH_CR_TRIM_16M_VAL; + u16Trim[1] = RCH_CR_TRIM_8M_VAL; + u16Trim[0] = RCL_CR_TRIM_38400_VAL; + + //获取当前系统时钟 + enSrc = (en_sysctrl_clk_source_t)(M0P_SYSCTRL->SYSCTRL0_f.CLKSW); + + switch (enSrc) + { + case SysctrlClkRCH: + { + + if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[4])) + { + u32Val = u32hcr_tbl[4]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[3])) + { + u32Val = u32hcr_tbl[3]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[2])) + { + u32Val = u32hcr_tbl[2]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[1])) + { + u32Val = u32hcr_tbl[1]; + } + else + { + u32Val = u32hcr_tbl[0]; + } + } + break; + case SysctrlClkXTH: + u32Val = SYSTEM_XTH; + break; + case SysctrlClkRCL: + { + if(u16Trim[0] == (M0P_SYSCTRL->RCL_CR_f.TRIM)) + { + u32Val = u32lcr_tbl[1]; + } + else + { + u32Val = u32lcr_tbl[0]; + } + } + break; + case SysctrlClkXTL: + u32Val = SYSTEM_XTL; + break; + case SysctrlClkPLL: + { + if (SysctrlPllRch == M0P_SYSCTRL->PLL_CR_f.REFSEL) + { + if(u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[4]; + } + else if(u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[3]; + } + else if(u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[2]; + } + else if(u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[1]; + } + else + { + u32Val = u32hcr_tbl[0]; + } + } + else + { + u32Val = SYSTEM_XTH; + } + + u32Val = (u32Val * M0P_SYSCTRL->PLL_CR_f.DIVN); + } + break; + default: + u32Val = 0u; + break; + } + + u32Val = (u32Val >> M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS); + + return u32Val; +} + +/** + ******************************************************************************* + ** \brief 获得外设时钟（PCLK）频率值 + ** \retval uint32_t PCLK频率值(Hz) + ** + ******************************************************************************/ +uint32_t Sysctrl_GetPClkFreq(void) +{ + uint32_t u32Val = 0; + + u32Val = Sysctrl_GetHClkFreq(); + u32Val = (u32Val >> (M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS)); + + return u32Val; +} + + +/** + ******************************************************************************* + ** \brief 时钟初始化函数 + ** \param [in] pstcCfg 初始化配置参数 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkInit(stc_sysctrl_clk_cfg_t *pstcCfg) +{ + en_result_t enRet = Ok; + + //系统时钟参数配置 + switch(pstcCfg->enClkSrc) + { + case SysctrlClkRCH: + + break; + case SysctrlClkXTH: + Sysctrl_XTHDriverCfg(SysctrlXtalDriver3); + Sysctrl_SetXTHStableTime(SysctrlXthStableCycle16384); + break; + case SysctrlClkRCL: + Sysctrl_SetRCLStableTime(SysctrlRclStableCycle256); + break; + case SysctrlClkXTL: + Sysctrl_XTLDriverCfg(SysctrlXtlAmp3, SysctrlXtalDriver3); + Sysctrl_SetXTLStableTime(SysctrlXtlStableCycle16384); + break; + case SysctrlClkPLL: + Sysctrl_SetPLLStableTime(SysctrlPllStableCycle16384); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + //时钟源使能 + Sysctrl_ClkSourceEnable(pstcCfg->enClkSrc, TRUE); + + //时钟源切换 + Sysctrl_SysClkSwitch(pstcCfg->enClkSrc); + + //时钟分频设置 + Sysctrl_SetHCLKDiv(pstcCfg->enHClkDiv); + Sysctrl_SetPCLKDiv(pstcCfg->enPClkDiv); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 时钟去初始化函数 + ** \param [in] + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkDeInit(void) +{ + en_result_t enRet = Ok; + + //配置RCH为内部4Hz + Sysctrl_SetRCHTrim(SysctrlRchFreq4MHz); + + //时钟源使能 + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); + + //时钟源切换 + Sysctrl_SysClkSwitch(SysctrlClkRCH); + + //其它时钟源使能关闭 + Sysctrl_ClkSourceEnable(SysctrlClkXTH, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkRCL, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkXTL, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkPLL, FALSE); + + //时钟分频设置 + Sysctrl_SetHCLKDiv(SysctrlHclkDiv1); + Sysctrl_SetPCLKDiv(SysctrlPclkDiv1); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部高速时钟频率TRIM值加载 + ** \param [in] enRCHFreq 设定的RCH目标频率值 + ** \retval Ok 设定成功 + ** 其他 设定失败或时钟未稳定 + ******************************************************************************/ +en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq) +{ + //加载RCH Trim值 + M0P_SYSCTRL->RCH_CR_f.TRIM = *(RC_TRIM_BASE_ADDR + enRCHFreq); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 外部高速时钟频率范围设定 + ** \param [in] enXTHFreq 设定的频率值 + ** \retval Ok 设定成功 + ** 其他 设定失败或时钟未稳定 + ******************************************************************************/ +en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTH_CR_f.XTH_FSEL = enXTHFreq; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief PLL时钟配置 + ** \param [in] pstcPLLCfg PLL配置结构体指针 + ** \retval Ok 设定成功 + ** 其他 设定失败或参数值不匹配 + ******************************************************************************/ +en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_cfg_t *pstcPLLCfg) +{ + en_result_t enRet = Ok; + + uint16_t u16Trim[5] = {0}; + u16Trim[4] = RCH_CR_TRIM_24M_VAL; + u16Trim[3] = RCH_CR_TRIM_22_12M_VAL; + u16Trim[2] = RCH_CR_TRIM_16M_VAL; + u16Trim[1] = RCH_CR_TRIM_8M_VAL; + + ////PLL最高时钟不能超过48MHz + //RCH作为PLL输入 + if (SysctrlPllRch == pstcPLLCfg->enPllClkSrc) + { + if( ((u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) || + ((u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) || + ((u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 3)) || + ((u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 6))) + { + return ErrorInvalidMode; + } + } + else //XTH作为PLL输入 + { + if ((SYSTEM_XTH * pstcPLLCfg->enPllMul) > 48*1000*1000) + { + return ErrorInvalidMode; + } + } + + M0P_SYSCTRL->PLL_CR_f.FRSEL = pstcPLLCfg->enInFreq; + M0P_SYSCTRL->PLL_CR_f.FOSC = pstcPLLCfg->enOutFreq; + M0P_SYSCTRL->PLL_CR_f.DIVN = pstcPLLCfg->enPllMul; + M0P_SYSCTRL->PLL_CR_f.REFSEL = pstcPLLCfg->enPllClkSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部低速时钟频率TRIM值加载 + ** \param [in] enRCLFreq 设定的RCL目标频率值 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq) +{ + M0P_SYSCTRL->RCL_CR_f.TRIM = *(RC_TRIM_BASE_ADDR + enRCLFreq); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 系统时钟（HCLK）分频设定 + ** \param [in] enHCLKDiv 分频设定值 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv) +{ + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS = enHCLKDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 外设时钟（PCLK）分频设定 + ** \param [in] enPCLKDiv 分频设定值 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv) +{ + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS = enPCLKDiv; + + return Ok; +} + +///<< for Sysctrl_SetPeripheralGate() & Sysctrl_GetPeripheralGate() +static volatile boolean_t bDacPeriBac = FALSE; + +/** + ******************************************************************************* + ** \brief 设置外设时钟门控开关 + ** \param [in] enPeripheral 目标外设 + ** \param [in] bFlag 使能开关 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag) +{ + if(enPeripheral&0x20u) + { + enPeripheral &= ~0x20u; + SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), enPeripheral, bFlag); + + if((SysctrlPeripheralDac & ~0x20u) == enPeripheral) + { + bDacPeriBac = bFlag; + } + else + { + SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), (SysctrlPeripheralDac & ~0x20u), bDacPeriBac); + } + } + else + { + SetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN0)), enPeripheral, bFlag); + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 获得外设时钟门控开关状态 + ** \param [in] enPeripheral 目标外设 + ** \retval TRUE 开 + ** FALSE 关 + ******************************************************************************/ +boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral) +{ + if(enPeripheral&0x20u) + { + if(SysctrlPeripheralDac == enPeripheral) + { + return bDacPeriBac; + } + else + { + enPeripheral &= ~0x20u; + return GetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN1)), enPeripheral); + } + + } + else + { + return GetBit((uint32_t)(&(M0P_SYSCTRL->PERI_CLKEN0)), enPeripheral); + } + +} + +/** + ******************************************************************************* + ** \brief 系统功能设定 + ** \param [in] enFunc 系统功能枚举类型 + ** \param [in] bFlag 1-开/0-关 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag) +{ + _SysctrlUnlock(); + SetBit((uint32_t)(&(M0P_SYSCTRL->SYSCTRL1)), enFunc, bFlag); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 设定RTC校准时钟频率 + ** \param [in] enRtcAdj 校准频率值 + ** \retval Ok 设定成功 + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj) +{ + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL1_f.RTC_FREQ_ADJUST = enRtcAdj; + + return Ok; +} + +//@} // SysctrlGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_timer3.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_timer3.c new file mode 100644 index 0000000000..907743ac54 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_timer3.c @@ -0,0 +1,1368 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file timer3.c + ** + ** Common API of base timer. + ** @link Tiemr3 Group Some description @endlink + ** + ** - 2019-04-18 Husj First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_timer3.h" +/** + ******************************************************************************* + ** \addtogroup Tim3Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Timer3 中断标志获取(模式0/1/23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + + u32Val = M0P_TIM3_MODE23->IFR; + bRetVal = (u32Val>>enTim3Irq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Timer3 中断标志清除(模式0/1/23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ICLR = ~(1u<ICLR = 0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 中断使能(模式0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_EnableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 中断禁止(模式0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_DisableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 中断使能(模式1) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE1->M1CR_f.UIE = TRUE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE1->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 中断禁止(模式1) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE1->M1CR_f.UIE = FALSE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE1->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 中断使能(模式23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE23->M23CR_f.UIE = TRUE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEA = TRUE; + break; + case Tim3CB0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEB = TRUE; + break; + case Tim3CA1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEA = TRUE; + break; + case Tim3CB1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEB = TRUE; + break; + case Tim3CA2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEA = TRUE; + break; + case Tim3CB2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEB = TRUE; + break; + case Tim3BkIrq: + M0P_TIM3_MODE23->M23CR_f.BIE = TRUE; + break; + case Tim3TrigIrq: + M0P_TIM3_MODE23->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 中断禁止(模式23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE23->M23CR_f.UIE = FALSE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEA = FALSE; + break; + case Tim3CB0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEB = FALSE; + break; + case Tim3CA1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEA = FALSE; + break; + case Tim3CB1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEB = FALSE; + break; + case Tim3CA2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEA = FALSE; + break; + case Tim3CB2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEB = FALSE; + break; + case Tim3BkIrq: + M0P_TIM3_MODE23->M23CR_f.BIE = FALSE; + break; + case Tim3TrigIrq: + M0P_TIM3_MODE23->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 初始化配置(模式0) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_Init(stc_tim3_mode0_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.MODE = pstcCfg->enWorkMode; + M0P_TIM3_MODE0->M0CR_f.GATEP = pstcCfg->enGateP; + M0P_TIM3_MODE0->M0CR_f.GATE = pstcCfg->bEnGate; + M0P_TIM3_MODE0->M0CR_f.PRS = pstcCfg->enPRS; + M0P_TIM3_MODE0->M0CR_f.TOGEN = pstcCfg->bEnTog; + M0P_TIM3_MODE0->M0CR_f.CT = pstcCfg->enCT; + M0P_TIM3_MODE0->M0CR_f.MD = pstcCfg->enCntMode; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 启动运行(模式0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 停止运行(模式0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 端口输出使能/禁止设定(模式0) + ** + ** + ** \param [in] bEnOutput 翻转输出设定 TRUE:使能, FALSE:禁止 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Enable_Output(boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + + + M0P_TIM3_MODE0->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 翻转使能/禁止（低电平）设定(模式0) + ** + ** + ** \param [in] bEnTOG 翻转输出设定 TRUE:使能, FALSE:禁止 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_EnTOG(boolean_t bEnTOG) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.TOGEN = bEnTOG; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16位计数器初值设置(模式0) + ** + ** + ** \param [in] u16Data CNT 16位初值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16位计数值获取(模式0) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M0_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE0->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Timer3 重载值设置(模式0) + ** + ** + ** \param [in] u16Data 16bits重载值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_ARRSet(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->ARR_f.ARR = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 32位计数器初值设置(模式0) + ** + ** + ** \param [in] u32Data 32位初值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->CNT32_f.CNT32 = u32Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 32位计数值获取(模式0) + ** + ** + ** \param [in] none + ** + ** \retval 32bits计数值 + *****************************************************************************/ +uint32_t Tim3_M0_Cnt32Get(void) +{ + uint32_t u32CntData = 0; + + u32CntData = M0P_TIM3_MODE0->CNT32_f.CNT32; + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Timer3 初始化配置(模式1) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_Init(stc_tim3_mode1_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.MODE = pstcCfg->enWorkMode; + M0P_TIM3_MODE1->M1CR_f.PRS = pstcCfg->enPRS; + M0P_TIM3_MODE1->M1CR_f.CT = pstcCfg->enCT; + M0P_TIM3_MODE1->M1CR_f.ONESHOT = pstcCfg->enOneShot; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 PWC 输入配置(模式1) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Input_Cfg(stc_tim3_pwc_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->MSCR_f.TS = pstcCfg->enTsSel; + M0P_TIM3_MODE1->MSCR_f.IA0S = pstcCfg->enIA0Sel; + M0P_TIM3_MODE1->MSCR_f.IB0S = pstcCfg->enIB0Sel; + M0P_TIM3_MODE1->FLTR_f.ETP = pstcCfg->enETRPhase; + M0P_TIM3_MODE1->FLTR_f.FLTET = pstcCfg->enFltETR; + M0P_TIM3_MODE1->FLTR_f.FLTA0 = pstcCfg->enFltIA0; + M0P_TIM3_MODE1->FLTR_f.FLTB0 = pstcCfg->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 PWC测量边沿起始结束选择(模式1) + ** + ** + ** \param [in] enEdgeSel pwc测量起始终止电平 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + + switch (enEdgeSel) + { + case 0: ///< 上升沿到上升沿(周期) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //上升沿 + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //上升沿 + break; + case 1: ///< 下降沿到上升沿(低电平) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //下降沿 + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //上升沿 + break; + case 2: ///< 上升沿到下降沿(高电平) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //上升沿 + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //下降沿 + break; + case 3: ///< 下降沿到下降沿(周期) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //下降沿 + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //下降沿 + break; + default: + ; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 启动运行(模式1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 停止运行(模式1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16位计数器初值设置(模式1) + ** + ** + ** \param [in] u16Data 16位初值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16位计数值获取(模式1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M1_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE1->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Timer3 脉冲宽度测量结果数值获取(模式1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits脉冲宽度测量结果 + *****************************************************************************/ +uint16_t Tim3_M1_PWC_CapValueGet(void) +{ + uint16_t u16CapData = 0; + + u16CapData = M0P_TIM3_MODE1->CCR0A_f.CCR0A; + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Timer3 初始化配置(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_Init(stc_tim3_mode23_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.MODE = pstcCfg->enWorkMode; + + M0P_TIM3_MODE23->M23CR_f.PRS = pstcCfg->enPRS; + M0P_TIM3_MODE23->M23CR_f.CT = pstcCfg->enCT; + M0P_TIM3_MODE23->M23CR_f.COMP = pstcCfg->enPWMTypeSel; + M0P_TIM3_MODE23->M23CR_f.PWM2S = pstcCfg->enPWM2sSel; + M0P_TIM3_MODE23->M23CR_f.ONESHOT = pstcCfg->bOneShot; + M0P_TIM3_MODE23->M23CR_f.URS = pstcCfg->bURSSel; + M0P_TIM3_MODE23->M23CR_f.DIR = pstcCfg->enCntDir; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 PWM输出使能(模式23) + ** + ** + ** \param [in] bEnOutput PWM输出使能/禁止设定 + ** \param [in] bEnAutoOutput PWM自动输出使能/禁止设定 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.MOE = bEnOutput; + M0P_TIM3_MODE23->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Timer3 启动运行(模式23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 停止运行(模式23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 重载值设置(模式23) + ** + ** + ** \param [in] u16Data 16bits重载值 + ** \param [in] bArrBufEn ARR重载缓存使能TRUE/禁止FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ARR_f.ARR = u16Data; + M0P_TIM3_MODE23->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16位计数器初值设置(模式23) + ** + ** + ** \param [in] u16Data 16位初值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 16位计数值获取(模式23) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M23_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE23->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Timer3 比较捕获寄存器CCRxA/CCRxB设置(模式23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** \param [in] u16Data CCRxA/CCRxB 16位初始值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + if(Tim3CCR0A == enCCRSel) + { + M0P_TIM3_MODE23->CCR0A_f.CCR0A = u16Data; + } + else if(Tim3CCR0B == enCCRSel) + { + M0P_TIM3_MODE23->CCR0B_f.CCR0B = u16Data; + } + else if(Tim3CCR1A == enCCRSel) + { + M0P_TIM3_MODE23->CCR1A_f.CCR1A = u16Data; + } + else if(Tim3CCR1B == enCCRSel) + { + M0P_TIM3_MODE23->CCR1B_f.CCR1B = u16Data; + } + else if(Tim3CCR2A == enCCRSel) + { + M0P_TIM3_MODE23->CCR2A_f.CCR2A = u16Data; + } + else if(Tim3CCR2B == enCCRSel) + { + M0P_TIM3_MODE23->CCR2B_f.CCR2B = u16Data; + } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 比较捕获寄存器CCRxA/CCRxB读取(模式23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** + ** \retval 16bitsCCRxA/CCRxB捕获值 + *****************************************************************************/ +uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + + if(Tim3CCR0A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR0A_f.CCR0A; + } + else if(Tim3CCR0B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR0B_f.CCR0B; + } + else if(Tim3CCR1A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR1A_f.CCR1A; + } + else if(Tim3CCR1B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR1B_f.CCR1B; + } + else if(Tim3CCR2A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR2A_f.CCR2A; + } + else if(Tim3CCR2B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR2B_f.CCR2B; + } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Timer3 PWM互补输出模式下，GATE功能选择(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CSG = pstcCfg->enGateFuncSel; + M0P_TIM3_MODE23->M23CR_f.CRG = pstcCfg->bGateRiseCap; + M0P_TIM3_MODE23->M23CR_f.CFG = pstcCfg->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 主从模式配置(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->MSCR_f.MSM = pstcCfg->enMasterSlaveSel; + M0P_TIM3_MODE23->MSCR_f.MMS = pstcCfg->enMasterSrc; + M0P_TIM3_MODE23->MSCR_f.SMS = pstcCfg->enSlaveModeSel; + M0P_TIM3_MODE23->MSCR_f.TS = pstcCfg->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 CHxA/CHxB比较通道控制(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** \param [in] enTim3Chx Timer3通道(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_PortOutput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + switch (enTim3Chx) + { + case Tim3CH0: + M0P_TIM3_MODE23->CRCH0_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcCfg->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH0_f.BUFEA = pstcCfg->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH0_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcCfg->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH0_f.BUFEB = pstcCfg->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH0_f.CISB = pstcCfg->enCHxBCmpIntSel; + break; + case Tim3CH1: + M0P_TIM3_MODE23->CRCH1_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcCfg->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcCfg->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH1_f.BUFEA = pstcCfg->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH1_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcCfg->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcCfg->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH1_f.BUFEB = pstcCfg->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH1_f.CISB = pstcCfg->enCHxBCmpIntSel; + break; + case Tim3CH2: + M0P_TIM3_MODE23->CRCH2_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcCfg->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcCfg->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH2_f.BUFEA = pstcCfg->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcCfg->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH2_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcCfg->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcCfg->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH2_f.BUFEB = pstcCfg->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH2_f.CISB = pstcCfg->enCHxBCmpIntSel; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 CHxA/CHxB输入控制(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** \param [in] enTim3Chx Timer3通道(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_PortInput_Cfg(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + switch (enTim3Chx) + { + case Tim3CH0: + M0P_TIM3_MODE23->CRCH0_f.CSA = 1; + M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcCfg->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcCfg->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH0_f.CSB = 1; + M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcCfg->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcCfg->enCHxBPolarity; + break; + case Tim3CH1: + M0P_TIM3_MODE23->CRCH1_f.CSA = 1; + M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcCfg->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcCfg->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH1_f.CSB = 1; + M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcCfg->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcCfg->enCHxBPolarity; + break; + case Tim3CH2: + M0P_TIM3_MODE23->CRCH2_f.CSA = 1; + M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcCfg->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcCfg->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcCfg->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH2_f.CSB = 1; + M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcCfg->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcCfg->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcCfg->enCHxBPolarity; + break; + default: + enResult = Error; + break; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 ERT输入控制(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_ETRInput_Cfg(stc_tim3_m23_etr_input_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->FLTR_f.ETP = pstcCfg->enETRPolarity; + M0P_TIM3_MODE23->FLTR_f.FLTET = pstcCfg->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 刹车BK输入控制(模式23) + ** + ** + ** \param [in] pstcBkCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_BrakeInput_Cfg(stc_tim3_m23_bk_input_cfg_t* pstcBkCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.BKE = pstcBkCfg->bEnBrake; + M0P_TIM3_MODE23->DTR_f.VCE = pstcBkCfg->bEnVCBrake; + M0P_TIM3_MODE23->DTR_f.SAFEEN = pstcBkCfg->bEnSafetyBk; + M0P_TIM3_MODE23->DTR_f.BKSEL = pstcBkCfg->bEnBKSync; + M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH0AStat; + M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH0BStat; + M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH1AStat; + M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH1BStat; + M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcBkCfg->enBkCH2AStat; + M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcBkCfg->enBkCH2BStat; + M0P_TIM3_MODE23->FLTR_f.BKP = pstcBkCfg->enBrakePolarity; + M0P_TIM3_MODE23->FLTR_f.FLTBK = pstcBkCfg->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 触发ADC控制(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_TrigADC_Cfg(stc_tim3_m23_adc_trig_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ADTR_f.ADTE = pstcCfg->bEnTrigADC; + M0P_TIM3_MODE23->ADTR_f.UEVE = pstcCfg->bEnUevTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA0E = pstcCfg->bEnCH0ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB0E = pstcCfg->bEnCH0BCmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA1E = pstcCfg->bEnCH1ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB1E = pstcCfg->bEnCH1BCmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA2E = pstcCfg->bEnCH2ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB2E = pstcCfg->bEnCH2BCmpTrigADC; + return enResult; +} + +/** + ***************************************************************************** +** \brief Timer3 死区功能(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_DT_Cfg(stc_tim3_m23_dt_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.DTEN = pstcCfg->bEnDeadTime; + M0P_TIM3_MODE23->DTR_f.DTR = pstcCfg->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Timer3 重复周期设置(模式23) + ** + ** + ** \param [in] u8ValidPeriod 重复周期值 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 OCREF清除功能(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.OCCS = pstcCfg->enOCRefClrSrcSel; + M0P_TIM3_MODE23->M23CR_f.OCCE = pstcCfg->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 使能DMA传输(模式23) + ** + ** + ** \param [in] pstcCfg 初始化配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_cfg_t* pstcCfg) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.UDE = pstcCfg->bUevTrigDMA; + M0P_TIM3_MODE23->M23CR_f.TDE = pstcCfg->bTITrigDMA; + M0P_TIM3_MODE23->CRCH0_f.CDEA = pstcCfg->bCmpA0TrigDMA; + M0P_TIM3_MODE23->CRCH0_f.CDEB = pstcCfg->bCmpB0TrigDMA; + M0P_TIM3_MODE23->CRCH1_f.CDEA = pstcCfg->bCmpA1TrigDMA; + M0P_TIM3_MODE23->CRCH1_f.CDEB = pstcCfg->bCmpB1TrigDMA; + M0P_TIM3_MODE23->CRCH2_f.CDEA = pstcCfg->bCmpA2TrigDMA; + M0P_TIM3_MODE23->CRCH2_f.CDEB = pstcCfg->bCmpB2TrigDMA; + M0P_TIM3_MODE23->MSCR_f.CCDS = pstcCfg->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 捕获比较A软件触发(模式23) + ** + ** + ** \param [in] enTim3Chx Timer3通道(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx) +{ + en_result_t enResult = Ok; + if(Tim3CH0 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH0_f.CCGA = TRUE; + } + else if(Tim3CH1 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH1_f.CCGA = TRUE; + } + else if(Tim3CH2 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH2_f.CCGA = TRUE; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 捕获比较B软件触发(模式23) + ** + ** + ** \param [in] enTim3Chx Timer3通道(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx) +{ + en_result_t enResult = Ok; + if(Tim3CH0 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH0_f.CCGB = TRUE; + } + else if(Tim3CH1 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH1_f.CCGB = TRUE; + } + else if(Tim3CH2 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH2_f.CCGB = TRUE; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 软件更新使能(模式23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwUev(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 软件触发使能(模式23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrig(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Timer3 软件刹车使能(模式23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwBk(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // Tim3Group + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_trim.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_trim.c new file mode 100644 index 0000000000..e21d0e27db --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_trim.c @@ -0,0 +1,248 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file trim.c + ** + ** Common API of trim. + ** @link trimGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_trim.h" +/** + ******************************************************************************* + ** \addtogroup TrimGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#define IS_VALID_TRIMINT(x) (TrimStop == (x) ||\ + TrimCalCntOf == (x) ||\ + TrimXTLFault == (x) ||\ + TrimXTHFault == (x) ||\ + TrimPLLFault == (x)) + + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ***************************************************************************** + ** \brief Trim中断标志获取 + ** + ** + ** \param [in] enIntType 中断类型（RefStop、CalCntOf、XTAL32KFault、XTAL32MFault） + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Trim_GetIntFlag(en_trim_inttype_t enIntType) +{ + ASSERT(IS_VALID_TRIMINT(enIntType)); + + if(M0P_CLK_TRIM->IFR&enIntType) + { + return TRUE; + } + else + { + return FALSE; + } + +} + +/** + ***************************************************************************** + ** \brief Trim中断标志清除 + ** + ** + ** \param [in] enIntType 中断类型（RefStop、CalCntOf、XTAL32KFault、XTAL32MFault） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_ClearIntFlag(en_trim_inttype_t enIntType) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_TRIMINT(enIntType)); + + M0P_CLK_TRIM->ICLR &= ~(uint32_t)enIntType; + + return enResult; +} + + + +/** + ***************************************************************************** + ** \brief Trim中断使能 + ** + ** + ** + ** \retval Null + *****************************************************************************/ +void Trim_EnableIrq (void) +{ + M0P_CLK_TRIM->CR_f.IE = TRUE; +} + +/** + ***************************************************************************** + ** \brief Trim中断禁止 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +void Trim_DisableIrq(void) +{ + M0P_CLK_TRIM->CR_f.IE = FALSE; +} + +/** + ***************************************************************************** + ** \brief Trim初始化配置 + ** + ** + ** \param [in] pstcCfg Trim配置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_Init(stc_trim_cfg_t* pstcCfg) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR = 0; + + M0P_CLK_TRIM->CR = (uint32_t)pstcCfg->enCALCLK | + (uint32_t)pstcCfg->enREFCLK | + (uint32_t)pstcCfg->enMON; + + M0P_CLK_TRIM->REFCON = pstcCfg->u32RefCon; + M0P_CLK_TRIM->CALCON = pstcCfg->u32CalCon; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim校准/监测启动运行 + ** + ** + ** + ** \retval Null + *****************************************************************************/ +void Trim_Run(void) +{ + M0P_CLK_TRIM->CR_f.TRIM_START = TRUE; +} + +/** + ***************************************************************************** + ** \brief Trim校准/监测停止 + ** + ** + ** + ** + ** \retval Null + *****************************************************************************/ +void Trim_Stop(void) +{ + M0P_CLK_TRIM->CR_f.TRIM_START = FALSE; +} + +/** + ***************************************************************************** + ** \brief Trim参考计数器计数值获取 + ** + ** + ** \retval u32Data 参考计数器计数值 + *****************************************************************************/ +uint32_t Trim_RefCntGet(void) +{ + return (uint32_t)M0P_CLK_TRIM->REFCNT; +} + +/** + ***************************************************************************** + ** \brief Trim校准计数器计数值获取 + ** + ** + ** + ** + ** \retval u32Data 校准计数器计数值 + *****************************************************************************/ +uint32_t Trim_CalCntGet(void) +{ + return (uint32_t)M0P_CLK_TRIM->CALCNT; +} + +//@} // TrimGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_trng.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_trng.c new file mode 100644 index 0000000000..4ebf27ec20 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_trng.c @@ -0,0 +1,191 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file rng.c + ** + ** Common API of rng. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32l196_trng.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief 随机数初始化(上电第一次生成随机数） + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Trng_Init(void) +{ + //==>>生成64bits随机数（上电第一次） + M0P_TRNG->CR_f.RNGCIR_EN = 1; + //模式配置0 + M0P_TRNG->MODE_f.LOAD = 1; + M0P_TRNG->MODE_f.FDBK = 1; + M0P_TRNG->MODE_f.CNT = 6; + //生成随机数0 + M0P_TRNG->CR_f.RNG_RUN = 1; + while(M0P_TRNG->CR_f.RNG_RUN) + { + ; + } + + //模式配置1 + M0P_TRNG->MODE_f.LOAD = 0; + M0P_TRNG->MODE_f.FDBK = 0; + M0P_TRNG->MODE_f.CNT = 4; + //生成随机数1 + M0P_TRNG->CR_f.RNG_RUN = 1; + while(M0P_TRNG->CR_f.RNG_RUN) + { + ; + } + + //关闭随机源电路，节省功耗 + M0P_TRNG->CR_f.RNGCIR_EN = 0; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 生成随机数（非上电第一次生成随机数） + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Trng_Generate(void) +{ + //==>>生成64bits随机数（非上电第一次生成） + M0P_TRNG->CR_f.RNGCIR_EN = 1; + + //模式配置0 + M0P_TRNG->MODE_f.LOAD = 0; + M0P_TRNG->MODE_f.FDBK = 1; + M0P_TRNG->MODE_f.CNT = 6; + //生成随机数0 + M0P_TRNG->CR_f.RNG_RUN = 1; + while(M0P_TRNG->CR_f.RNG_RUN) + { + ; + } + + //模式配置1 + M0P_TRNG->MODE_f.FDBK = 0; + M0P_TRNG->MODE_f.CNT = 4; + M0P_TRNG->MODE_f.CNT = 4; + //生成随机数1 + M0P_TRNG->CR_f.RNG_RUN = 1; + while(M0P_TRNG->CR_f.RNG_RUN) + { + ; + } + + //关闭随机源电路，节省功耗 + M0P_TRNG->CR_f.RNGCIR_EN = 0; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 随机数获取 + ** + ** \retval data0 + *****************************************************************************/ +uint32_t Trng_GetData0(void) +{ + return M0P_TRNG->DATA0; +} + +/** + ***************************************************************************** + ** \brief 随机数获取 + ** + ** \retval data1 + *****************************************************************************/ +uint32_t Trng_GetData1(void) +{ + return M0P_TRNG->DATA1; +} + +//@} // TrngGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_uart.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_uart.c new file mode 100644 index 0000000000..8a3d43b6b8 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_uart.c @@ -0,0 +1,383 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file uart.c + ** + ** UART function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "hc32l196_uart.h" +/** + ****************************************************************************** + ** \addtogroup UartGroup + ******************************************************************************/ +//@{ +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief UART通信中断使能函数设置 + ** + ** \param [in] UARTx通道号，enIrqSel发送or接收中断使能 + ** + ** \retval OK配置成功 + ** \retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t Uart_EnableIrq(M0P_UART_TypeDef* UARTx, en_uart_irq_sel_t enIrqSel) +{ + SetBit((uint32_t)(&(UARTx->SCON)), enIrqSel, TRUE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通信中断禁止函数设置 + ** + ** \param [in] UARTx通道号，enIrqSel发送or接收中断禁止 + ** + ** \retval OK配置成功 + ** \retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t Uart_DisableIrq(M0P_UART_TypeDef* UARTx, en_uart_irq_sel_t enIrqSel) +{ + SetBit((uint32_t)(&(UARTx->SCON)), enIrqSel, FALSE); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART通道多主机模式配置 + ** + ** \param [in] UARTx通道号，stcMultiCfg多主机模式结构 + ** + ** \retval OK配置成功 + ** \retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t Uart_SetMultiMode(M0P_UART_TypeDef* UARTx, stc_uart_multimode_t* pstcMultiCfg) +{ + if(NULL != pstcMultiCfg) + { + UARTx->SCON_f.ADRDET = TRUE; + UARTx->SADDR = pstcMultiCfg->u8SlaveAddr; + UARTx->SADEN = pstcMultiCfg->u8SaddEn; + + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART单线半双工模式使能 + ** + ** \param [in] UARTx 通道号 + ** + ** \retval Null + ******************************************************************************/ +void Uart_HdModeEnable(M0P_UART_TypeDef* UARTx) +{ + UARTx->SCON_f.HDSEL = TRUE; +} + +/** + ****************************************************************************** + ** \brief UART单线半双工模式关闭 + ** + ** \param [in] UARTx 通道号 + ** + ** \retval Null + ******************************************************************************/ +void Uart_HdModeDisable(M0P_UART_TypeDef* UARTx) +{ + UARTx->SCON_f.HDSEL = FALSE; +} + +/** + ****************************************************************************** + ** \brief UART通道多机模式发送数据/地址帧配置TB8 + ** + ** \param [in] UARTx 通道号 + ** \param [in] TRUE-TB8为地址帧标志；FALSE-TB8为数据帧标志； + ** + ** \retval Null + ******************************************************************************/ +void Uart_SetTb8(M0P_UART_TypeDef* UARTx, boolean_t bTB8Value) +{ + UARTx->SCON_f.B8CONT = bTB8Value; + +} + +/** + ****************************************************************************** + ** \brief 获取RB8数值 + ** + ** \param [in] UARTx通道号 + ** + ** \retval RB8 + ******************************************************************************/ +boolean_t Uart_GetRb8(M0P_UART_TypeDef* UARTx) +{ + return (UARTx->SBUF_f.DATA8); +} + +/** + ****************************************************************************** + ** \brief UART通道多主机模式从机地址配置函数 + ** + ** \param [in] UARTx通道号，addr地址 + ** + ** \retval OK配置成功 + ** \retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t Uart_SetSaddr(M0P_UART_TypeDef* UARTx,uint8_t u8Addr) +{ + UARTx->SADDR = u8Addr; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART通道发送或接收等功能使能设置 + ** + ** \param [in] UARTx通道号，enFunc功能 + ** + ** \retval OK配置成功 + ** \retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t Uart_EnableFunc(M0P_UART_TypeDef* UARTx, en_uart_func_t enFunc) +{ + SetBit((uint32_t)(&(UARTx->SCON)), enFunc, TRUE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通道发送或接收等功能禁止设置 + ** + ** \param [in] UARTx通道号，enFunc功能 + ** + ** \retval OK配置成功 + ** \retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t Uart_DisableFunc(M0P_UART_TypeDef* UARTx, en_uart_func_t enFunc) +{ + SetBit((uint32_t)(&(UARTx->SCON)), enFunc, FALSE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通道通信状态获取 + ** + ** \param [in] UARTx通道号 + ** + ** \retval 状态值 + ******************************************************************************/ +uint8_t Uart_GetIsr(M0P_UART_TypeDef* UARTx) +{ + return (UARTx->ISR); +} + +/** + ****************************************************************************** + ** \brief UART通道通信状态获取 + ** + ** \param [in] UARTx通道号，enStatus获取哪个状态 + ** + ** \retval 状态值 + ******************************************************************************/ +boolean_t Uart_GetStatus(M0P_UART_TypeDef* UARTx, en_uart_status_t enStatus) +{ + boolean_t bStatus = FALSE; + + + ASSERT(IS_VALID_STATUS(enStatus)); + + bStatus = GetBit((uint32_t)(&(UARTx->ISR)), enStatus); + + return bStatus; +} +/** + ****************************************************************************** + ** \brief UART通道通信状态清除 + ** + ** \param [in] UARTx通道号 + ** + ** \retval OK + ** \retval ErrorInvalidParameter清除失败 + ******************************************************************************/ +en_result_t Uart_ClrIsr(M0P_UART_TypeDef* UARTx) +{ + UARTx->ICR = 0u; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通道通信状态清除 + ** + ** \param [in] UARTx通道号，enStatus清除哪个状态 + ** + ** \retval OK + ** \retval ErrorInvalidParameter清除失败 + ******************************************************************************/ +en_result_t Uart_ClrStatus(M0P_UART_TypeDef* UARTx,en_uart_status_t enStatus) +{ + ASSERT(IS_VALID_STATUS(enStatus)); + + SetBit((uint32_t)(&(UARTx->ICR)), enStatus, FALSE); + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通道发送数据函数,查询方式调用此函数，中断方式发送不适用 + ** + ** \param [in] UARTx通道号，Data发送数据 + ** + ** \retval Ok发送成功 + ** \retval ErrorInvalidParameter发送失败 + ******************************************************************************/ +en_result_t Uart_SendDataPoll(M0P_UART_TypeDef* UARTx, uint8_t u8Data) +{ + while(FALSE == Uart_GetStatus(UARTx,UartTxe)) + {} + UARTx->SBUF_f.DATA = u8Data; + while(FALSE == Uart_GetStatus(UARTx,UartTC)) + {} + Uart_ClrStatus(UARTx,UartTC); + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART通道发送数据函数,中断方式调用此函数 + ** + ** \param [in] UARTx通道号，Data发送数据 + ** + ** \retval Ok发送成功 + ** \retval ErrorInvalidParameter发送失败 + ******************************************************************************/ +en_result_t Uart_SendDataIt(M0P_UART_TypeDef* UARTx, uint8_t u8Data) +{ + UARTx->SBUF_f.DATA = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART通道接收数据函数 + ** + ** \param [in] UARTx通道号 + ** + ** \retval 接收数据 + ******************************************************************************/ +uint8_t Uart_ReceiveData(M0P_UART_TypeDef* UARTx) +{ + return (UARTx->SBUF_f.DATA); +} + +/** + ****************************************************************************** + ** \brief UART通道初始化函数 + ** + ** \param [in] UARTx通道号，pstcCfg初始化结构体 @ref stc_uart_cfg_t + ** + ** \retval OK配置成功 + ** \retval ErrorInvalidParameter配置失败 + ******************************************************************************/ +en_result_t Uart_Init(M0P_UART_TypeDef* UARTx, stc_uart_cfg_t* pstcCfg) +{ + en_result_t enRet = Error; + uint32_t u32Over[2] = {0x4, 0x3}; + uint16_t u16OverShift; + float32_t f32Scnt=0; + + if(NULL == pstcCfg) + { + return ErrorInvalidParameter; + } + + UARTx->SCON = 0; + + UARTx->SCON = (uint32_t)pstcCfg->enStopBit | + (uint32_t)pstcCfg->enMmdorCk | + (uint32_t)pstcCfg->stcBaud.enClkDiv | + (uint32_t)pstcCfg->enRunMode; + + if((UartMskMode1 == pstcCfg->enRunMode) || (UartMskMode3 == pstcCfg->enRunMode)) + { + u16OverShift = u32Over[pstcCfg->stcBaud.enClkDiv/UartMsk8Or16Div]; + f32Scnt = (float32_t)(pstcCfg->stcBaud.u32Pclk)/(float32_t)(pstcCfg->stcBaud.u32Baud<SCNT = (uint16_t)(float32_t)(f32Scnt + 0.5f); + Uart_EnableFunc(UARTx,UartRenFunc); ///<使能收发 + } + + + + enRet = Ok; + return enRet; +} +//@} // UartGroup diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_vc.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_vc.c new file mode 100644 index 0000000000..46c43e9bf0 --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_vc.c @@ -0,0 +1,298 @@ +/****************************************************************************** +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file vc.c + ** + ** voltage comparator driver API. + ** @link VC Group Some description @endlink + ** + ** - 2019-04-10 First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "hc32l196_vc.h" + +/** + ****************************************************************************** + ** \addtogroup VcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** +****************************************************************************** + ** \brief 配置VC中断触发方式 + ** + ** @param Channelx : VcChannelx x=0、1、2 + ** @param enSel : VcIrqRise、VcIrqFall、VcIrqHigh + ** \retval 无 + ** +******************************************************************************/ +void Vc_CfgItType(en_vc_channel_t Channelx, en_vc_irq_sel_t ItType) +{ + stc_vc_vc0_cr_field_t *stcVcnCr; + switch(Channelx) + { + case VcChannel0: + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC0_CR_f; + break; + case VcChannel1: + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC1_CR_f; + break; + case VcChannel2: + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC2_CR_f; + break; + default: + break; + } + switch (ItType) + { + case VcIrqNone: + stcVcnCr->RISING = 0u; + stcVcnCr->FALLING = 0u; + stcVcnCr->LEVEL = 0u; + break; + case VcIrqRise: + stcVcnCr->RISING = 1u; + break; + case VcIrqFall: + stcVcnCr->FALLING = 1u; + break; + case VcIrqHigh: + stcVcnCr->LEVEL = 1u; + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief VC 中断使能与禁止 + ** + ** @param Channelx : VcChannelx x=0、1、2 + ** @param NewStatus : TRUE 或 FALSE + ** \retval 无 + ** +******************************************************************************/ +void Vc_ItCfg(en_vc_channel_t Channelx, boolean_t NewStatus) +{ + switch(Channelx) + { + case VcChannel0: + SetBit((uint32_t)(&(M0P_VC->VC0_CR)), 15, NewStatus); + break; + case VcChannel1: + SetBit((uint32_t)(&(M0P_VC->VC1_CR)), 15, NewStatus); + break; + case VcChannel2: + SetBit((uint32_t)(&(M0P_VC->VC2_CR)), 15, NewStatus); + break; + default: + break; + } +} + +/** +****************************************************************************** + ** \brief VC 比较结果获取，包含中断标志位和滤波结果 + ** + ** @param Result : 所要读取的结果 + ** \retval TRUE 或 FALSE + ** +******************************************************************************/ +boolean_t Vc_GetItStatus(en_vc_ifr_t Result) +{ + boolean_t bFlag; + bFlag = GetBit((uint32_t)(&(M0P_VC->IFR)), Result); + return bFlag; +} + +/** +****************************************************************************** + ** \brief VC 清除中断标志位 + ** + ** @param NewStatus : Vc0_Intf、Vc1_Intf、Vc2_Intf + ** \retval 无 + ** +******************************************************************************/ +void Vc_ClearItStatus(en_vc_ifr_t NewStatus) +{ + SetBit((uint32_t)(&(M0P_VC->IFR)), NewStatus, 0); +} + +/** +****************************************************************************** + ** \brief VC 配置DAC相关的内容 VC_CR中 VC_REF2P5_SEL VC_DIV_EN VC_DIV + ** + ** @param pstcDacCfg : + ** \retval Ok 或 ErrorInvalidParameter + ** +******************************************************************************/ +en_result_t Vc_DacInit(stc_vc_dac_cfg_t *pstcDacCfg) +{ + if (NULL == pstcDacCfg) + { + return ErrorInvalidParameter; + } + + M0P_VC->CR_f.DIV_EN = pstcDacCfg->bDivEn; + M0P_VC->CR_f.REF2P5_SEL = pstcDacCfg->enDivVref; + + if (pstcDacCfg->u8DivVal < 0x40) + { + M0P_VC->CR_f.DIV = pstcDacCfg->u8DivVal; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** +****************************************************************************** + ** \brief VC通道初始化 + ** + ** @param pstcDacCfg : + ** \retval 无 + ** +******************************************************************************/ +void Vc_Init(stc_vc_channel_cfg_t *pstcChannelCfg) +{ + if (VcChannel0 == pstcChannelCfg->enVcChannel) + { + M0P_VC->CR_f.VC0_HYS_SEL = pstcChannelCfg->enVcCmpDly; + M0P_VC->CR_f.VC0_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent; + M0P_VC->VC0_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime; + M0P_VC->VC0_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P; + M0P_VC->VC0_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N; + M0P_VC->VC0_CR_f.FLTEN = pstcChannelCfg->bFlten; + M0P_VC->VC0_OUT_CFG = 1<enVcOutCfg; + } + else if (VcChannel1 == pstcChannelCfg->enVcChannel) + { + M0P_VC->CR_f.VC1_HYS_SEL = pstcChannelCfg->enVcCmpDly; + M0P_VC->CR_f.VC1_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent; + M0P_VC->VC1_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime; + M0P_VC->VC1_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P; + M0P_VC->VC1_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N; + M0P_VC->VC1_CR_f.FLTEN = pstcChannelCfg->bFlten; + M0P_VC->VC1_OUT_CFG = 1<enVcOutCfg; + } + else if(VcChannel2 == pstcChannelCfg->enVcChannel) + { + M0P_VC->CR_f.VC2_HYS_SEL = pstcChannelCfg->enVcCmpDly; + M0P_VC->CR_f.VC2_BIAS_SEL = pstcChannelCfg->enVcBiasCurrent; + M0P_VC->VC2_CR_f.DEBOUNCE_TIME = pstcChannelCfg->enVcFilterTime; + M0P_VC->VC2_CR_f.P_SEL = pstcChannelCfg->enVcInPin_P; + M0P_VC->VC2_CR_f.N_SEL = pstcChannelCfg->enVcInPin_N; + M0P_VC->VC2_CR_f.FLTEN = pstcChannelCfg->bFlten; + M0P_VC->VC2_OUT_CFG = 1<enVcOutCfg; + } + else + { + ; + } +} + +/** +****************************************************************************** + ** \brief VC 通道使能 + ** + ** \param enChannel : 通道号VcChannel0 VcChannel1 VcChannel2 + ** \param NewStatus : TRUE FALSE + ** \retval NewStatus : TRUE FALSE + ** +******************************************************************************/ +void Vc_Cmd(en_vc_channel_t enChannel, boolean_t NewStatus) +{ + switch(enChannel) + { + case VcChannel0: + SetBit((uint32_t)(&(M0P_VC->VC0_CR)), 16, NewStatus); + break; + case VcChannel1: + SetBit((uint32_t)(&(M0P_VC->VC1_CR)), 16, NewStatus); + break; + case VcChannel2: + SetBit((uint32_t)(&(M0P_VC->VC2_CR)), 16, NewStatus); + break; + default: + break; + } +} + +//@} // VcGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_wdt.c b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_wdt.c new file mode 100644 index 0000000000..3c8f8f08dc --- /dev/null +++ b/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/hc32l196_wdt.c @@ -0,0 +1,203 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file wdt.c + ** + ** WDT function driver API. + ** @link WdtGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "hc32l196_wdt.h" + +/** + ****************************************************************************** + ** \defgroup WdtGroup + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief WDT溢出时间设置函数 + ** + ** \param [in] u8LoadValue 溢出时间 + ** + ** \retval 无 + ** + ******************************************************************************/ +void Wdt_WriteWdtLoad(uint8_t u8LoadValue) +{ + M0P_WDT->CON_f.WOV = u8LoadValue; +} +/** + ****************************************************************************** + ** \brief WDT初始化函数 + ** + ** \param [in] enFunc @ref en_wdt_func_t + ** \param [in] enTime @ref en_wdt_time_t + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Wdt_Init(en_wdt_func_t enFunc, en_wdt_time_t enTime) +{ + en_result_t enRet = Error; + + Wdt_WriteWdtLoad(enTime); + M0P_WDT->CON_f.WINT_EN = enFunc; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief WDT复位及启动函数 + ** + ** \param [in] 无 + ** + ** \retval 无 + ** + ******************************************************************************/ +void Wdt_Start(void) +{ + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; +} + +/** + ****************************************************************************** + ** \brief WDT喂狗 + ** + ** \param [in] 无 + ** + ** \retval Ok + ** + ******************************************************************************/ +void Wdt_Feed(void) +{ + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; +} + +/** + ****************************************************************************** + ** \brief WDT中断标志清除 + ** + ** \param [in] 无 + ** + ** \retval Ok + ** + ******************************************************************************/ +void Wdt_IrqClr(void) +{ + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; +} + +/** + ****************************************************************************** + ** \brief WDT读取当前计数值函数 + ** + ** \param [in] 无 + ** + ** \retval 计数值 + ** + ******************************************************************************/ +uint8_t Wdt_ReadWdtValue(void) +{ + uint8_t u8Count; + + u8Count = M0P_WDT->CON_f.WCNTL; + + return u8Count; +} +/** + ****************************************************************************** + ** \brief WDT读取当前运行状态 + ** + ** \param [in] 无 + ** + ** \retval 状态值 + ** + ******************************************************************************/ +boolean_t Wdt_ReadwdtStatus(void) +{ + if(M0P_WDT->CON&0x10u) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ******************************************************************************* + ** \brief WDT 中断状态标记获取 + ** + ** + ** \retval 中断状态 + ******************************************************************************/ +boolean_t Wdt_GetIrqStatus(void) +{ + if(M0P_WDT->CON&0x80u) + { + return TRUE; + } + else + { + return FALSE; + } +} + + +//@} // WdtGroup diff --git a/bsp/hc32l196/Libraries/LICENSE b/bsp/hc32l196/Libraries/LICENSE new file mode 100644 index 0000000000..72823826b8 --- /dev/null +++ b/bsp/hc32l196/Libraries/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2020, Huada Semiconductor Co., Ltd ("HDSC") +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/hc32l196/Libraries/SConscript b/bsp/hc32l196/Libraries/SConscript new file mode 100644 index 0000000000..2e4b5bf169 --- /dev/null +++ b/bsp/hc32l196/Libraries/SConscript @@ -0,0 +1,40 @@ +# RT-Thread building script for bridge + +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +CMSIS/Device/HDSC/HC32L196/Source/system_hc32l19x.c +CMSIS/Device/HDSC/HC32L196/Source/interrupts_hc32l19x.c +HC32L196_StdPeriph_Driver/src/hc32l196_ddl.c +HC32L196_StdPeriph_Driver/src/hc32l196_gpio.c +HC32L196_StdPeriph_Driver/src/hc32l196_sysctrl.c +HC32L196_StdPeriph_Driver/src/hc32l196_flash.c +""") + +if GetDepend(['RT_USING_SERIAL']): + src += ['HC32L196_StdPeriph_Driver/src/hc32l196_uart.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/HDSC/HC32L196/Source/GCC/startup_hc32l19x.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/HDSC/HC32L196/Source/ARM/startup_hc32l19x.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/HDSC/HC32L196/Source/IAR/startup_hc32l19x.s'] + +#add headfile script +path = [cwd + '/CMSIS/Include', + cwd + '/CMSIS/Device/HDSC/HC32L196/Include', + cwd + '/HC32L196_StdPeriph_Driver/inc'] + +CPPDEFINES = [] + +group = DefineGroup('HC32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32l196/README.md b/bsp/hc32l196/README.md new file mode 100644 index 0000000000..fe5452c935 --- /dev/null +++ b/bsp/hc32l196/README.md @@ -0,0 +1,103 @@ +# HDSC HC32L196 核心板 BSP 说明 + +## 简介 + +本文档为 HC32L196 核心板 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP ，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +HC32L196 核心板搭载 HC32L196 芯片，基于 ARM Cortex-M0+ 内核，最高主频 48MHz。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +HC32L196 核心板 **板载资源** 如下： + +- MCU: HC32L196JCTA，晶振8MHz，主频 48MHz，256KB FLASH ，32KB RAM +- 常用外设 + - LED: 用户 D2，电源指示灯 D1 + - 按键: RESET +- 调试接口: 标准 SWD +- 供电接口: MicroUSB + +开发板更多详细信息请参考[HC32L196 核心板资料，提取码: vtl9](https://pan.baidu.com/s/1WzSHr_Vl2aIVbZ-WJDAHZg)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... PF15 ---> PIN: 0, 1...95 | +| UART | 支持 | UART0, UART1 | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 MicroUSB 线连接核心板和 PC 供电， D1 会点亮。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 J-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果， D2 会周期性闪烁。 + +使用USB转TTL串口模块连接 PA9(TX) 和 PA10(RX)，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Sep 7 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口0串口1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 注意事项 + +## 联系人信息 + +维护人: + +- 闻波东, 邮箱：<815611030@qq.com> diff --git a/bsp/hc32l196/SConscript b/bsp/hc32l196/SConscript new file mode 100644 index 0000000000..24bb4646ab --- /dev/null +++ b/bsp/hc32l196/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32l196/SConstruct b/bsp/hc32l196/SConstruct new file mode 100644 index 0000000000..7314792045 --- /dev/null +++ b/bsp/hc32l196/SConstruct @@ -0,0 +1,43 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +print("RTT_ROOT: " + RTT_ROOT) + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32l196/applications/SConscript b/bsp/hc32l196/applications/SConscript new file mode 100644 index 0000000000..6f66f7ab73 --- /dev/null +++ b/bsp/hc32l196/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l196/applications/main.c b/bsp/hc32l196/applications/main.c new file mode 100644 index 0000000000..81bf06f8dd --- /dev/null +++ b/bsp/hc32l196/applications/main.c @@ -0,0 +1,42 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-05 DongBowen first version + */ + +#include "board.h" + +#include +#include + +#define LED_PIN GET_PIN(C, 13) +#define LED_PERIOD (RT_TICK_PER_SECOND / 5) + +#define KEY_PIN GET_PIN(B, 12) + +void key_handle(void *args) +{ + rt_kprintf("key pressed!\n"); +} + +int main(void) +{ + rt_pin_mode(KEY_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(KEY_PIN, PIN_IRQ_MODE_FALLING, key_handle, RT_NULL); + rt_pin_irq_enable(KEY_PIN, PIN_IRQ_ENABLE); + + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_delay(LED_PERIOD / 2); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_delay(LED_PERIOD / 2); + }; + +} + diff --git a/bsp/hc32l196/board/Kconfig b/bsp/hc32l196/board/Kconfig new file mode 100644 index 0000000000..09644d608d --- /dev/null +++ b/bsp/hc32l196/board/Kconfig @@ -0,0 +1,40 @@ +menu "Hardware Drivers Config" + +config MCU_HC32L196 + bool + select ARCH_ARM_CORTEX_M0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default y + + config BSP_USING_UART1 + bool "Enable UART1" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32l196/board/SConscript b/bsp/hc32l196/board/SConscript new file mode 100644 index 0000000000..e06723028f --- /dev/null +++ b/bsp/hc32l196/board/SConscript @@ -0,0 +1,15 @@ +from building import * + +cwd = GetCurrentDir() + +CPPPATH = [cwd] + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l196/board/board.c b/bsp/hc32l196/board/board.c new file mode 100644 index 0000000000..a60000b1ae --- /dev/null +++ b/bsp/hc32l196/board/board.c @@ -0,0 +1,127 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 DongBowen first version + */ + +#include +#include + +#include "board.h" +#include "hc32l196_sysctrl.h" +#include "hc32l196_flash.h" + +/** + * @brief BSP clock initialize. + * Set board system clock to PLL@48MHz by RCH + * @param None + * @retval None + */ +void rt_hw_board_clock_init(void) +{ + stc_sysctrl_pll_cfg_t stcPLLCfg; + + Sysctrl_SetHCLKDiv(SysctrlHclkDiv1); + Sysctrl_SetPCLKDiv(SysctrlPclkDiv1); + + /* switch clock to RCL before changing RCH */ + Sysctrl_SetRCLTrim(SysctrlRclFreq32768); + Sysctrl_SetRCLStableTime(SysctrlRclStableCycle64); + Sysctrl_ClkSourceEnable(SysctrlClkRCL, TRUE); + Sysctrl_SysClkSwitch(SysctrlClkRCL); + + /* set RCH to 4MHz */ + Sysctrl_SetRCHTrim(SysctrlRchFreq4MHz); + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); + + stcPLLCfg.enInFreq = SysctrlPllInFreq4_6MHz; + stcPLLCfg.enOutFreq = SysctrlPllOutFreq36_48MHz; + stcPLLCfg.enPllClkSrc = SysctrlPllRch; /* input clock: RCH */ + stcPLLCfg.enPllMul = SysctrlPllMul12; /* 4MHz x 12 = 48MHz */ + Sysctrl_SetPLLFreq(&stcPLLCfg); + + /* + * When the used clock source HCLK is greater than 24M, + * set the FLASH read wait cycle to 1 cycle. + */ + Flash_WaitCycle(FlashWaitCycle1); + + /* enable PLL */ + Sysctrl_ClkSourceEnable(SysctrlClkPLL, TRUE); + /* switch clock to PLL */ + Sysctrl_SysClkSwitch(SysctrlClkPLL); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + rt_uint32_t cnts; + + cnts = Sysctrl_GetHClkFreq() / RT_TICK_PER_SECOND; + + SysTick_Config(cnts); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initialize HC32 board. + */ +void rt_hw_board_init() +{ + /* Configure the System clock */ + rt_hw_board_clock_init(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} diff --git a/bsp/hc32l196/board/board.h b/bsp/hc32l196/board/board.h new file mode 100644 index 0000000000..b6fef40983 --- /dev/null +++ b/bsp/hc32l196/board/board.h @@ -0,0 +1,45 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 DongBowen first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32l196_ddl.h" +#include "drv_gpio.h" + +/* board configuration */ +#define SRAM_BASE 0x20000000 +#define SRAM_SIZE 0x8000 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) + +/* High speed sram. */ +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN (&__bss_end) +#endif + +#ifdef __ICCARM__ + // Use *.icf ram symbal, to avoid hardcode. + extern char __ICFEDIT_region_RAM_end__; + #define HEAP_END (&__ICFEDIT_region_RAM_end__) +#else + #define HEAP_END SRAM_END +#endif + +void rt_hw_board_init(void); +void rt_hw_us_delay(rt_uint32_t us); + +#endif diff --git a/bsp/hc32l196/board/board_config.c b/bsp/hc32l196/board/board_config.c new file mode 100644 index 0000000000..c6c6e17dbf --- /dev/null +++ b/bsp/hc32l196/board/board_config.c @@ -0,0 +1,14 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-01 DongBowen first version + */ +#include +#include "board_config.h" + +/** + * The below functions will initialize HC32 board. + */ diff --git a/bsp/hc32l196/board/board_config.h b/bsp/hc32l196/board/board_config.h new file mode 100644 index 0000000000..075346d718 --- /dev/null +++ b/bsp/hc32l196/board/board_config.h @@ -0,0 +1,40 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-05 DongBowen first version + */ + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32l196_ddl.h" +#include "hc32l196_gpio.h" +#include "hc32l196_uart.h" +#include "hc32l196_sysctrl.h" + +/*********** Port configure *********/ +#if defined(BSP_USING_UART0) + #define UART0_RX_PORT GpioPortA + #define UART0_RX_PIN GpioPin10 + #define UART0_RX_AF GpioAf1 + + #define UART0_TX_PORT GpioPortA + #define UART0_TX_PIN GpioPin9 + #define UART0_TX_AF GpioAf1 +#endif + +#if defined(BSP_USING_UART1) + #define UART1_RX_PORT GpioPortA + #define UART1_RX_PIN GpioPin3 + #define UART1_RX_AF GpioAf1 + + #define UART1_TX_PORT GpioPortA + #define UART1_TX_PIN GpioPin2 + #define UART1_TX_AF GpioAf1 +#endif + +#endif diff --git a/bsp/hc32l196/board/linker_scripts/link.lds b/bsp/hc32l196/board/linker_scripts/link.lds new file mode 100644 index 0000000000..fc5b6197af --- /dev/null +++ b/bsp/hc32l196/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for HC32L196 with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 256k /* 256KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 32k /* 32KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } > RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } > RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/hc32l196/board/linker_scripts/link.sct b/bsp/hc32l196/board/linker_scripts/link.sct new file mode 100644 index 0000000000..f11623dfce --- /dev/null +++ b/bsp/hc32l196/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x8000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32l196/drivers/SConscript b/bsp/hc32l196/drivers/SConscript new file mode 100644 index 0000000000..086e1c5db3 --- /dev/null +++ b/bsp/hc32l196/drivers/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" + +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l196/drivers/drv_gpio.c b/bsp/hc32l196/drivers/drv_gpio.c new file mode 100644 index 0000000000..acd82e9035 --- /dev/null +++ b/bsp/hc32l196/drivers/drv_gpio.c @@ -0,0 +1,362 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-05 DongBowen first version + */ + +#include +#include "rthw.h" + +#include "drv_gpio.h" +#include "hc32l196_sysctrl.h" + +#ifdef RT_USING_PIN +#ifdef BSP_USING_GPIO + +#define __GPIO_PORT(pin) (((pin) & 0xf0) * 4) +#define __GPIO_PORT_L(pin) (__GPIO_PORT(pin)) +#define __GPIO_PORT_H(pin) ((__GPIO_PORT(pin) & 0xff) + 0x1000) +#define PE0_PIN (4 * 15) +#define GPIO_PORT(pin) (en_gpio_port_t)((pin) < PE0_PIN ? __GPIO_PORT_L((pin)) : __GPIO_PORT_H((pin))) +#define GPIO_PIN(pin) (en_gpio_pin_t)((pin) & 0x0f) + +/* Port: PA-PF, Pin: 0-15 */ +#define PIN_MAX_NUM (6 * 16) + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[PIN_MAX_NUM]; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + en_gpio_port_t gpio_port; + en_gpio_pin_t gpio_pin; + stc_gpio_cfg_t gpio_cfg; + + if (pin >= PIN_MAX_NUM) + { + return; + } + + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + + gpio_cfg.bOutputVal = 0; + gpio_cfg.enDrv = GpioDrvH; + gpio_cfg.enPu = GpioPuDisable; + gpio_cfg.enPd = GpioPdDisable; + gpio_cfg.enOD = GpioOdDisable; + gpio_cfg.enCtrlMode = GpioAHB; + + switch (mode) + { + case PIN_MODE_OUTPUT: + gpio_cfg.enDir = GpioDirOut; + break; + case PIN_MODE_INPUT: + gpio_cfg.enDir = GpioDirIn; + break; + case PIN_MODE_INPUT_PULLUP: + gpio_cfg.enDir = GpioDirIn; + gpio_cfg.enPu = GpioPuEnable; + break; + case PIN_MODE_INPUT_PULLDOWN: + gpio_cfg.enDir = GpioDirIn; + gpio_cfg.enPd = GpioPdEnable; + break; + case PIN_MODE_OUTPUT_OD: + gpio_cfg.enDir = GpioDirOut; + gpio_cfg.enOD = GpioOdEnable; + break; + default: + break; + } + + Gpio_Init(gpio_port, gpio_pin, &gpio_cfg); +} + +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + en_gpio_port_t gpio_port; + en_gpio_pin_t gpio_pin; + + if (pin >= PIN_MAX_NUM) + { + return; + } + + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + + if (PIN_LOW == value) + { + Gpio_ClrIO(gpio_port, gpio_pin); + } + else + { + Gpio_SetIO(gpio_port, gpio_pin); + } +} + +static int _pin_read(rt_device_t dev, rt_base_t pin) +{ + en_gpio_port_t gpio_port; + en_gpio_pin_t gpio_pin; + + if (pin >= PIN_MAX_NUM) + { + return PIN_LOW; + } + + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + + return Gpio_GetInputIO(gpio_port, gpio_pin) ? PIN_HIGH : PIN_LOW; +} + +static rt_err_t _pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + void (*hdr)(void *args), + void *args) +{ + rt_base_t level; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[pin].pin == pin && + pin_irq_hdr_tab[pin].mode == mode && + pin_irq_hdr_tab[pin].hdr == hdr && + pin_irq_hdr_tab[pin].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[pin].pin = pin; + pin_irq_hdr_tab[pin].mode = mode; + pin_irq_hdr_tab[pin].hdr = hdr; + pin_irq_hdr_tab[pin].args = args; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + pin_irq_hdr_tab[pin].mode = 0; + pin_irq_hdr_tab[pin].hdr = RT_NULL; + pin_irq_hdr_tab[pin].args = RT_NULL; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static IRQn_Type get_irqn(rt_base_t pin) +{ + en_gpio_port_t gpio_port; + IRQn_Type irqn = (IRQn_Type)0xff; + + if (pin >= PIN_MAX_NUM) + { + return irqn; + } + + gpio_port = GPIO_PORT(pin); + switch (gpio_port) + { + case GpioPortA: + irqn = PORTA_IRQn; + break; + case GpioPortB: + irqn = PORTB_IRQn; + break; + case GpioPortC: + case GpioPortE: + irqn = PORTC_E_IRQn; + break; + case GpioPortD: + case GpioPortF: + irqn = PORTD_F_IRQn; + break; + } + + return irqn; +} + +static rt_err_t _pin_irq_enable(struct rt_device *device, + rt_base_t pin, + rt_uint32_t enabled) +{ + rt_base_t level = 0; + en_gpio_port_t gpio_port; + en_gpio_pin_t gpio_pin; + IRQn_Type irqn; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + irqn = get_irqn(pin); + + if (enabled == PIN_IRQ_ENABLE) + { + switch (pin_irq_hdr_tab[pin].mode) + { + case PIN_IRQ_MODE_RISING: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqRising); + break; + case PIN_IRQ_MODE_FALLING: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqFalling); + break; + case PIN_IRQ_MODE_RISING_FALLING: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqRising); + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqFalling); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqHigh); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqLow); + break; + default: + return -RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + NVIC_ClearPendingIRQ(irqn); + NVIC_EnableIRQ(irqn); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + switch (pin_irq_hdr_tab[pin].mode) + { + case PIN_IRQ_MODE_RISING: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqRising); + break; + case PIN_IRQ_MODE_FALLING: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqFalling); + break; + case PIN_IRQ_MODE_RISING_FALLING: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqRising); + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqFalling); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqHigh); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqLow); + break; + default: + break; + } + + level = rt_hw_interrupt_disable(); + NVIC_ClearPendingIRQ(irqn); + NVIC_DisableIRQ(irqn); + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops _pin_ops = +{ + .pin_mode = _pin_mode, + .pin_write = _pin_write, + .pin_read = _pin_read, + .pin_attach_irq = _pin_attach_irq, + .pin_detach_irq = _pin_detach_irq, + .pin_irq_enable = _pin_irq_enable, +}; + +static void pin_isr(en_gpio_port_t gpio_port) +{ + en_gpio_pin_t gpio_pin = GpioPin0; + int pin = __GET_PIN(gpio_port, 0); + + for (; gpio_pin <= GpioPin15; gpio_pin++, pin++) + { + if (Gpio_GetIrqStatus(gpio_port, gpio_pin)) + { + if (pin_irq_hdr_tab[pin].hdr) + { + pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args); + } + Gpio_ClearIrq(gpio_port, gpio_pin); + } + } +} + +void PortA_IRQHandler(void) +{ + rt_interrupt_enter(); + pin_isr(GpioPortA); + rt_interrupt_leave(); +} + +void PortB_IRQHandler(void) +{ + rt_interrupt_enter(); + pin_isr(GpioPortB); + rt_interrupt_leave(); +} + +void PortC_IRQHandler(void) +{ + rt_interrupt_enter(); + pin_isr(GpioPortC); + rt_interrupt_leave(); +} + +void PortD_IRQHandler(void) +{ + rt_interrupt_enter(); + pin_isr(GpioPortD); + rt_interrupt_leave(); +} + +void PortE_IRQHandler(void) +{ + rt_interrupt_enter(); + pin_isr(GpioPortE); + rt_interrupt_leave(); +} + +void PortF_IRQHandler(void) +{ + rt_interrupt_enter(); + pin_isr(GpioPortF); + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE); + return rt_device_pin_register("pin", &_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* BSP_USING_GPIO */ +#endif /* RT_USING_PIN */ diff --git a/bsp/hc32l196/drivers/drv_gpio.h b/bsp/hc32l196/drivers/drv_gpio.h new file mode 100644 index 0000000000..33269eb516 --- /dev/null +++ b/bsp/hc32l196/drivers/drv_gpio.h @@ -0,0 +1,26 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-05 DongBowen first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include "hc32l196_ddl.h" +#include "hc32l196_gpio.h" + +#ifdef RT_USING_PIN + +#define __HC_PORT(port) GpioPort##port +#define __HC_PORT_ADJUST(port) ((port) <= GpioPortD ? (port) : ((port) & 0xff) + 0x100) +#define GET_PIN(PORT, PIN) (((rt_uint16_t)__HC_PORT_ADJUST(__HC_PORT(PORT)) / 4) + PIN) +#define __GET_PIN(PORT, PIN) (((rt_uint16_t)__HC_PORT_ADJUST(PORT) / 4) + PIN) + +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/hc32l196/drivers/drv_usart.c b/bsp/hc32l196/drivers/drv_usart.c new file mode 100644 index 0000000000..cef082c91e --- /dev/null +++ b/bsp/hc32l196/drivers/drv_usart.c @@ -0,0 +1,299 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-9-1 DongBowen first version + */ + +#include "drv_usart.h" +#include +#include +#include "board.h" + +#ifdef RT_USING_SERIAL +#ifdef BSP_USING_UART + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \ + !defined(BSP_USING_UART3) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +enum +{ +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +}; + +static struct hc_uart_cfg uart_cfg[] = +{ +#ifdef BSP_USING_UART0 + UART0_CFG, +#endif +#ifdef BSP_USING_UART1 + UART1_CFG, +#endif +#ifdef BSP_USING_UART2 + UART2_CFG, +#endif +#ifdef BSP_USING_UART3 + UART3_CFG, +#endif +}; + +static struct hc_uart uart_drv[sizeof(uart_cfg) / sizeof(uart_cfg[0])] = {0}; + +static rt_err_t _uart_init(struct rt_serial_device *serial_device, struct serial_configure *configure) +{ + stc_gpio_cfg_t stcGpioCfg; + stc_uart_cfg_t stcCfg; + + struct hc_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + RT_ASSERT(configure != RT_NULL); + cfg = serial_device->parent.user_data; + + /* configure rx and tx gpio */ + rt_memset(&stcGpioCfg, 0, sizeof(stcGpioCfg)); + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE); + stcGpioCfg.enDir = GpioDirOut; + Gpio_Init(cfg->tx_port, cfg->tx_pin, &stcGpioCfg); + Gpio_SetAfMode(cfg->tx_port, cfg->tx_pin, cfg->tx_af); + stcGpioCfg.enDir = GpioDirIn; + Gpio_Init(cfg->rx_port, cfg->rx_pin, &stcGpioCfg); + Gpio_SetAfMode(cfg->rx_port, cfg->rx_pin, cfg->rx_af); + + /* configure uart */ + rt_memset(&stcCfg, 0, sizeof(stcCfg)); + + Sysctrl_SetPeripheralGate(cfg->uart_periph, TRUE); + + stcCfg.stcBaud.u32Baud = configure->baud_rate; + stcCfg.stcBaud.enClkDiv = UartMsk8Or16Div; + stcCfg.stcBaud.u32Pclk = Sysctrl_GetPClkFreq(); + + switch (configure->data_bits) + { + case DATA_BITS_8: + break; + default: + break; + } + + switch (configure->stop_bits) + { + case STOP_BITS_1: + stcCfg.enStopBit = UartMsk1bit; + break; + case STOP_BITS_2: + stcCfg.enStopBit = UartMsk2bit; + break; + default: + stcCfg.enStopBit = UartMsk1bit; + break; + } + + switch (configure->parity) + { + case PARITY_NONE: + stcCfg.enMmdorCk = UartMskDataOrAddr; + stcCfg.enRunMode = UartMskMode1; + break; + case PARITY_ODD: + stcCfg.enMmdorCk = UartMskOdd; + stcCfg.enRunMode = UartMskMode3; + break; + case PARITY_EVEN: + stcCfg.enMmdorCk = UartMskEven; + stcCfg.enRunMode = UartMskMode3; + break; + default: + stcCfg.enMmdorCk = UartMskDataOrAddr; + stcCfg.enRunMode = UartMskMode1; + break; + } + + Uart_Init(cfg->uart, &stcCfg); + + Uart_ClrStatus(cfg->uart, UartRC); + Uart_ClrStatus(cfg->uart, UartTC); + + rt_hw_us_delay(2); + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial_device, int cmd, void *arg) +{ + struct hc_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + Uart_DisableIrq(cfg->uart, UartRxIrq); + EnableNvic(cfg->irqn, IrqLevel3, FALSE); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + Uart_EnableIrq(cfg->uart, UartRxIrq); + EnableNvic(cfg->irqn, IrqLevel3, TRUE); + break; + } + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial_device, char c) +{ + struct hc_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + Uart_SendDataPoll(cfg->uart, (uint8_t)c); + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial_device) +{ + int ch; + struct hc_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + ch = -1; + + if (Uart_GetStatus(cfg->uart, UartRC)) + { + Uart_ClrStatus(cfg->uart, UartRC); + ch = Uart_ReceiveData(cfg->uart); + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + .configure = _uart_init, + .control = _uart_control, + .putc = _uart_putc, + .getc = _uart_getc, + .dma_transmit = RT_NULL +}; + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void rt_hw_uart_isr(struct rt_serial_device *serial_device) +{ + struct hc_uart_cfg *cfg; + uint32_t status; + RT_ASSERT(serial_device != RT_NULL); + + cfg = serial_device->parent.user_data; + status = cfg->uart->ISR; + + /* UART in mode Receiver -------------------------------------------------*/ + if (status & (1 << UartFE)) + { + Uart_ClrStatus(cfg->uart, UartFE); + } + if (status & (1 << UartPE)) + { + Uart_ClrStatus(cfg->uart, UartPE); + } + if (status & (1 << UartRC)) + { + rt_hw_serial_isr(serial_device, RT_SERIAL_EVENT_RX_IND); + } +} + +#if defined(BSP_USING_UART0) +void Uart0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART0_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +void Uart1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART1_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void Uart2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART2_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void Uart3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART3_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +int rt_hw_uart_init(void) +{ + struct serial_configure cfg = RT_SERIAL_CONFIG_DEFAULT; + int i = 0; + rt_err_t result = RT_EOK; + + for (i = 0; i < sizeof(uart_cfg) / sizeof(uart_cfg[0]); i++) + { + uart_drv[i].cfg = &uart_cfg[i]; + uart_drv[i].serial_device.ops = &_uart_ops; + uart_drv[i].serial_device.config = cfg; + /* register UART device */ + result = rt_hw_serial_register(&uart_drv[i].serial_device, uart_drv[i].cfg->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart_drv[i].cfg); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* BSP_USING_UART */ +#endif /* RT_USING_SERIAL */ diff --git a/bsp/hc32l196/drivers/drv_usart.h b/bsp/hc32l196/drivers/drv_usart.h new file mode 100644 index 0000000000..490ae14389 --- /dev/null +++ b/bsp/hc32l196/drivers/drv_usart.h @@ -0,0 +1,80 @@ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-9-1 DongBowen first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include "rtdevice.h" + +#include "board_config.h" + +/* hc config class */ +struct hc_uart_cfg +{ + const char *name; + M0P_UART_TypeDef *uart; + en_sysctrl_peripheral_gate_t uart_periph; + IRQn_Type irqn; + + en_gpio_port_t rx_port; + en_gpio_pin_t rx_pin; + en_gpio_af_t rx_af; + + en_gpio_port_t tx_port; + en_gpio_pin_t tx_pin; + en_gpio_af_t tx_af; +}; + +/* hc uart dirver class */ +struct hc_uart +{ + struct hc_uart_cfg *cfg; + struct rt_serial_device serial_device; +}; + +#ifdef BSP_USING_UART0 +#ifndef UART0_CFG +#define UART0_CFG \ + { \ + .name = "uart0", \ + .uart = M0P_UART0, \ + .uart_periph = SysctrlPeripheralUart0, \ + .irqn = UART0_2_IRQn, \ + .rx_port = UART0_RX_PORT, \ + .rx_pin = UART0_RX_PIN, \ + .rx_af = UART0_RX_AF, \ + .tx_port = UART0_TX_PORT, \ + .tx_pin = UART0_TX_PIN, \ + .tx_af = UART0_TX_AF, \ + } +#endif /* UART0_CFG */ +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +#ifndef UART1_CFG +#define UART1_CFG \ + { \ + .name = "uart1", \ + .uart = M0P_UART1, \ + .uart_periph = SysctrlPeripheralUart1, \ + .irqn = UART1_3_IRQn, \ + .rx_port = UART1_RX_PORT, \ + .rx_pin = UART1_RX_PIN, \ + .rx_af = UART1_RX_AF, \ + .tx_port = UART1_TX_PORT, \ + .tx_pin = UART1_TX_PIN, \ + .tx_af = UART1_TX_AF, \ + } +#endif /* UART1_CFG */ +#endif /* BSP_USING_UART1 */ + +int rt_hw_uart_init(void); + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/hc32l196/figures/board.jpg b/bsp/hc32l196/figures/board.jpg new file mode 100644 index 0000000000..bc79053403 Binary files /dev/null and b/bsp/hc32l196/figures/board.jpg differ diff --git a/bsp/hc32l196/project.uvoptx b/bsp/hc32l196/project.uvoptx new file mode 100644 index 0000000000..f3b5b34b19 --- /dev/null +++ b/bsp/hc32l196/project.uvoptx @@ -0,0 +1,813 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060061::V5.06 update 1 (build 61)::ARMCC + + + HC32L196JCTA + HDSC + HDSC.HC32L19X.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x40000) IRAM(0x20000000,0x8000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L19X_256K -FS00 -FL040000 -FP0($$Device:HC32L196JCTA$Flash\FlashHC32L19X_256K.FLM)) + 0 + $$Device:HC32L196JCTA$Device\Include\HC32L196JCTA.h + + + + + + + + + + $$Device:HC32L196JCTA$SVD\HC32L196JCTA.sfr + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + + + RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;board;drivers;..\..\components\finsh;Libraries\CMSIS\Include;Libraries\CMSIS\Device\HDSC\HC32L196\Include;Libraries\HC32L196_StdPeriph_Driver\inc;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m0\cpuport.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + + + Drivers + + + board_config.c + 1 + board\board_config.c + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + + + HC32_StdPeriph + + + startup_hc32l19x.s + 2 + Libraries\CMSIS\Device\HDSC\HC32L196\Source\ARM\startup_hc32l19x.s + + + system_hc32l19x.c + 1 + Libraries\CMSIS\Device\HDSC\HC32L196\Source\system_hc32l19x.c + + + hc32l196_uart.c + 1 + Libraries\HC32L196_StdPeriph_Driver\src\hc32l196_uart.c + + + hc32l196_flash.c + 1 + Libraries\HC32L196_StdPeriph_Driver\src\hc32l196_flash.c + + + interrupts_hc32l19x.c + 1 + Libraries\CMSIS\Device\HDSC\HC32L196\Source\interrupts_hc32l19x.c + + + hc32l196_ddl.c + 1 + Libraries\HC32L196_StdPeriph_Driver\src\hc32l196_ddl.c + + + hc32l196_sysctrl.c + 1 + Libraries\HC32L196_StdPeriph_Driver\src\hc32l196_sysctrl.c + + + hc32l196_gpio.c + 1 + Libraries\HC32L196_StdPeriph_Driver\src\hc32l196_gpio.c + + + + + Kernel + + + mem.c + 1 + ..\..\src\mem.c + + + clock.c + 1 + ..\..\src\clock.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + idle.c + 1 + ..\..\src\idle.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + irq.c + 1 + ..\..\src\irq.c + + + timer.c + 1 + ..\..\src\timer.c + + + components.c + 1 + ..\..\src\components.c + + + object.c + 1 + ..\..\src\object.c + + + device.c + 1 + ..\..\src\device.c + + + thread.c + 1 + ..\..\src\thread.c + + + + + libc + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + + + + + + diff --git a/bsp/hc32l196/rtconfig.h b/bsp/hc32l196/rtconfig.h new file mode 100644 index 0000000000..048c8d291b --- /dev/null +++ b/bsp/hc32l196/rtconfig.h @@ -0,0 +1,188 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40004 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define MCU_HC32L196 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/hc32l196/rtconfig.py b/bsp/hc32l196/rtconfig.py new file mode 100644 index 0000000000..cd1789c846 --- /dev/null +++ b/bsp/hc32l196/rtconfig.py @@ -0,0 +1,143 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0plus -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + diff --git a/bsp/hc32l196/template.uvoptx b/bsp/hc32l196/template.uvoptx new file mode 100644 index 0000000000..0ee00e8aa3 --- /dev/null +++ b/bsp/hc32l196/template.uvoptx @@ -0,0 +1,173 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0FlashHC32L19X_256K -FL040000 -FS00 -FP0($$Device:HC32L196JCTA$Flash\FlashHC32L19X_256K.FLM) + + + 0 + JL2CM3 + -U59408124 -O111 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC8000 -FN1 -FF0FlashHC32L19X_256K.FLM -FS00 -FL040000 -FP0($$Device:HC32L196JCTA$Flash\FlashHC32L19X_256K.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + + 1 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32l196/template.uvprojx b/bsp/hc32l196/template.uvprojx new file mode 100644 index 0000000000..df16394f24 --- /dev/null +++ b/bsp/hc32l196/template.uvprojx @@ -0,0 +1,377 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + + + HC32L196JCTA + HDSC + HDSC.HC32L19X.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x40000) IRAM(0x20000000,0x8000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L19X_256K -FS00 -FL040000 -FP0($$Device:HC32L196JCTA$Flash\FlashHC32L19X_256K.FLM)) + 0 + $$Device:HC32L196JCTA$Device\Include\HC32L196JCTA.h + + + + + + + + + + $$Device:HC32L196JCTA$SVD\HC32L196JCTA.sfr + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep=*Handler + + + + + + + + + diff --git a/bsp/hk32/.ignore_format.yml b/bsp/hk32/.ignore_format.yml new file mode 100644 index 0000000000..8fa57def6e --- /dev/null +++ b/bsp/hk32/.ignore_format.yml @@ -0,0 +1,9 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: + + +dir_path: +- libraries diff --git a/bsp/hk32/hk32f030c8-mini/board/board.c b/bsp/hk32/hk32f030c8-mini/board/board.c index e659a2f718..8d3aeaf117 100644 --- a/bsp/hk32/hk32f030c8-mini/board/board.c +++ b/bsp/hk32/hk32f030c8-mini/board/board.c @@ -21,7 +21,7 @@ static void reboot(uint8_t argc, char **argv) { rt_hw_cpu_reset(); } -FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System); +MSH_CMD_EXPORT(reboot, reboot system); #endif /* RT_USING_FINSH */ /** System Clock Configuration diff --git a/bsp/lpc1114/driver/drv_uart.c b/bsp/lpc1114/driver/drv_uart.c index 10956140c1..515310ed5f 100644 --- a/bsp/lpc1114/driver/drv_uart.c +++ b/bsp/lpc1114/driver/drv_uart.c @@ -8,7 +8,7 @@ * 2013-05-18 Bernard The first version for LPC40xx * 2019-05-05 jg1uaa port to LPC1114 */ - +#include #include #include #include diff --git a/bsp/ls1bdev/.config b/bsp/ls1bdev/.config new file mode 100644 index 0000000000..8cc34aa66c --- /dev/null +++ b/bsp/ls1bdev/.config @@ -0,0 +1,593 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart5" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set +CONFIG_SOC_LS=y +CONFIG_SOC_LS1B=y +CONFIG_RT_MEM_SIZE=256 +CONFIG_RT_OSC_CLK=25000000 +# CONFIG_RT_USING_UART0 is not set +# CONFIG_RT_USING_UART1 is not set +# CONFIG_RT_USING_UART2 is not set +# CONFIG_RT_USING_UART3 is not set +# CONFIG_RT_USING_UART4 is not set +CONFIG_RT_USING_UART5=y +CONFIG_RT_UART_RX_BUFFER_SIZE=64 diff --git a/bsp/ls1bdev/Kconfig b/bsp/ls1bdev/Kconfig index b02aee337a..c9196af29d 100644 --- a/bsp/ls1bdev/Kconfig +++ b/bsp/ls1bdev/Kconfig @@ -18,6 +18,10 @@ config PKGS_DIR source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" +config SOC_LS + bool + default y + config SOC_LS1B bool select RT_USING_COMPONENTS_INIT diff --git a/bsp/ls1bdev/rtconfig.h b/bsp/ls1bdev/rtconfig.h index aede85d795..cb81b4ac56 100644 --- a/bsp/ls1bdev/rtconfig.h +++ b/bsp/ls1bdev/rtconfig.h @@ -15,7 +15,13 @@ #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 1024 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + #define RT_DEBUG /* Inter-Thread communication */ @@ -38,7 +44,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart5" -#define RT_VER_NUM 0x40003 +#define RT_VER_NUM 0x40004 /* RT-Thread Components */ @@ -53,24 +59,25 @@ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 /* Device virtual file system */ #define RT_USING_DFS #define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 #define DFS_FD_MAX 16 #define RT_USING_DFS_DEVFS @@ -79,6 +86,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN @@ -90,6 +98,7 @@ #define RT_USING_LIBC #define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 /* Network */ @@ -111,6 +120,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -141,15 +153,26 @@ /* system packages */ +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + /* peripheral libraries and drivers */ -/* miscellaneous packages */ +/* AI packages */ +/* miscellaneous packages */ + /* samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_LS #define SOC_LS1B #define RT_MEM_SIZE 256 #define RT_OSC_CLK 25000000 diff --git a/bsp/ls1cdev/.config b/bsp/ls1cdev/.config index 28414b5870..e553870302 100644 --- a/bsp/ls1cdev/.config +++ b/bsp/ls1cdev/.config @@ -21,6 +21,13 @@ CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -66,7 +73,8 @@ CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -87,19 +95,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # @@ -136,8 +144,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set # CONFIG_RT_USING_DFS_NFS is not set # @@ -147,6 +153,8 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 CONFIG_RT_USING_CAN=y @@ -200,6 +208,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Network @@ -222,6 +231,7 @@ CONFIG_NETDEV_USING_PING=y CONFIG_RT_USING_LWIP=y CONFIG_RT_USING_LWIP141=y # CONFIG_RT_USING_LWIP202 is not set +# CONFIG_RT_USING_LWIP203 is not set # CONFIG_RT_USING_LWIP212 is not set CONFIG_RT_LWIP_MEM_ALIGNMENT=4 CONFIG_RT_LWIP_IGMP=y @@ -290,6 +300,12 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set # # RT-Thread MIPS CPU @@ -343,6 +359,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set # # IoT Cloud @@ -363,8 +380,6 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -379,6 +394,13 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set # # security packages @@ -395,6 +417,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set # # multimedia packages @@ -404,9 +427,13 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set # CONFIG_PKG_USING_HELIX is not set # CONFIG_PKG_USING_AZUREGUIX is not set # CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set # # tools packages @@ -415,6 +442,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set @@ -436,32 +464,30 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_GBK2UTF8 is not set # CONFIG_PKG_USING_VCONSOLE is not set # CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set # # system packages # -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_CMSIS is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set # # Micrium: Micrium software products porting for RT-Thread @@ -472,10 +498,39 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_PPOOL is not set # CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_RT_PRINTF is not set -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set # # peripheral libraries and drivers @@ -500,7 +555,6 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set @@ -538,10 +592,56 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set # CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages # + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -552,42 +652,26 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set - -# -# games: games run on RT-Thread console -# -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set # CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set +CONFIG_SOC_LS=y CONFIG_SOC_LS1C300=y CONFIG_RT_LS1C_OPENLOONGSON=y # CONFIG_RT_LS1C_BAICAIBOARD is not set @@ -599,9 +683,9 @@ CONFIG_RT_UART_RX_BUFFER_SIZE=64 CONFIG_RT_USING_GMAC_INT_MODE=y # CONFIG_RT_USING_SPI0 is not set # CONFIG_RT_USING_SPI1 is not set -CONFIG_RT_USING_I2C1=y -CONFIG_RT_USING_I2C2=y -CONFIG_USING_BXCAN0=y -CONFIG_USING_BXCAN1=y +# CONFIG_RT_USING_I2C1 is not set +# CONFIG_RT_USING_I2C2 is not set +# CONFIG_USING_BXCAN0 is not set +# CONFIG_USING_BXCAN1 is not set CONFIG_NO_TOUCH=y # CONFIG_TINA_USING_TOUCH is not set diff --git a/bsp/ls1cdev/Kconfig b/bsp/ls1cdev/Kconfig index 3fb6e3bbdf..59f7c43323 100644 --- a/bsp/ls1cdev/Kconfig +++ b/bsp/ls1cdev/Kconfig @@ -19,6 +19,10 @@ source "$RTT_DIR/Kconfig" source "$RTT_DIR/libcpu/mips/common/Kconfig" source "$PKGS_DIR/Kconfig" +config SOC_LS + bool + default y + config SOC_LS1C300 bool select RT_USING_COMPONENTS_INIT diff --git a/bsp/ls1cdev/rtconfig.h b/bsp/ls1cdev/rtconfig.h index 34be0a928c..d4075e371a 100644 --- a/bsp/ls1cdev/rtconfig.h +++ b/bsp/ls1cdev/rtconfig.h @@ -16,6 +16,9 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + #define RT_DEBUG #define RT_DEBUG_COLOR @@ -41,7 +44,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart2" -#define RT_VER_NUM 0x40003 +#define RT_VER_NUM 0x40004 /* RT-Thread Components */ @@ -56,16 +59,17 @@ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -96,6 +100,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_CAN @@ -114,6 +119,7 @@ #define RT_USING_PTHREADS #define PTHREAD_NUM_MAX 8 #define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 /* Network */ @@ -177,6 +183,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread MIPS CPU */ @@ -210,6 +219,8 @@ /* system packages */ +/* acceleration: Assembly language or algorithmic acceleration packages */ + /* Micrium: Micrium software products porting for RT-Thread */ @@ -217,24 +228,23 @@ /* peripheral libraries and drivers */ -/* miscellaneous packages */ +/* AI packages */ +/* miscellaneous packages */ + /* samples: kernel and components samples */ -/* games: games run on RT-Thread console */ +/* entertainment: terminal games and other interesting software packages */ +#define SOC_LS #define SOC_LS1C300 #define RT_LS1C_OPENLOONGSON #define RT_USING_UART2 #define RT_USING_UART1 #define RT_UART_RX_BUFFER_SIZE 64 #define RT_USING_GMAC_INT_MODE -#define RT_USING_I2C1 -#define RT_USING_I2C2 -#define USING_BXCAN0 -#define USING_BXCAN1 #define NO_TOUCH #endif diff --git a/bsp/ls2kdev/.config b/bsp/ls2kdev/.config index 2d89bcb80b..133b7dca3a 100644 --- a/bsp/ls2kdev/.config +++ b/bsp/ls2kdev/.config @@ -21,6 +21,13 @@ CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=16384 # CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -64,8 +71,9 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" -CONFIG_RT_VER_NUM=0x40003 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 CONFIG_ARCH_CPU_64BIT=y # CONFIG_RT_USING_CPU_FFS is not set CONFIG_ARCH_MIPS64=y @@ -88,19 +96,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=16384 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=16384 -CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # @@ -108,8 +116,8 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=10 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=10 +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y @@ -124,6 +132,11 @@ CONFIG_RT_DFS_ELM_WORD_ACCESS=y # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set CONFIG_RT_DFS_ELM_USE_LFN_3=y CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 CONFIG_RT_DFS_ELM_MAX_LFN=255 CONFIG_RT_DFS_ELM_DRIVES=9 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 @@ -132,8 +145,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set # CONFIG_RT_USING_DFS_NFS is not set # @@ -145,6 +156,8 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=16384 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=5 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set @@ -193,6 +206,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Network @@ -202,6 +216,7 @@ CONFIG_RT_USING_POSIX=y # Socket abstraction layer # CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y # # protocol stack implement @@ -229,6 +244,7 @@ CONFIG_NETDEV_IPV6=0 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP203 is not set # CONFIG_RT_USING_LWIP212 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set CONFIG_RT_LWIP_MEM_ALIGNMENT=8 @@ -298,6 +314,12 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set # # RT-Thread MIPS CPU @@ -351,6 +373,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set # # IoT Cloud @@ -371,8 +394,6 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -387,6 +408,13 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set # # security packages @@ -403,6 +431,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set # # multimedia packages @@ -412,9 +441,13 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set # CONFIG_PKG_USING_HELIX is not set # CONFIG_PKG_USING_AZUREGUIX is not set # CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set # # tools packages @@ -423,9 +456,12 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set @@ -441,34 +477,31 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_CPU_USAGE is not set # CONFIG_PKG_USING_GBK2UTF8 is not set # CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set # # system packages # -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_LWEXT4_LATEST_VERSION is not set -# CONFIG_PKG_USING_LWEXT4_V100 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_CMSIS is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set # # Micrium: Micrium software products porting for RT-Thread @@ -479,8 +512,39 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_PPOOL is not set # CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set # # peripheral libraries and drivers @@ -489,6 +553,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -504,7 +569,6 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set @@ -541,10 +605,57 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_NES is not set # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages # + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -555,39 +666,26 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set - -# -# games: games run on RT-Thread console -# -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set +CONFIG_SOC_LS=y CONFIG_SOC_LS2K1000=y +CONFIG_RT_USING_UART0=y +CONFIG_RT_USING_UART4=y diff --git a/bsp/ls2kdev/Kconfig b/bsp/ls2kdev/Kconfig index fc2dfe1328..57dd99e53a 100644 --- a/bsp/ls2kdev/Kconfig +++ b/bsp/ls2kdev/Kconfig @@ -22,6 +22,10 @@ source "$RTT_DIR/Kconfig" source "$RTT_DIR/libcpu/mips/common/Kconfig" source "$PKGS_DIR/Kconfig" +config SOC_LS + bool + default y + config SOC_LS2K1000 bool select ARCH_MIPS64 diff --git a/bsp/ls2kdev/rtconfig.h b/bsp/ls2kdev/rtconfig.h index 4fd46f8874..90dcf2ad91 100644 --- a/bsp/ls2kdev/rtconfig.h +++ b/bsp/ls2kdev/rtconfig.h @@ -16,6 +16,9 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 16384 + +/* kservice optimization */ + #define RT_DEBUG /* Inter-Thread communication */ @@ -38,7 +41,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x40003 +#define RT_VER_NUM 0x40004 #define ARCH_CPU_64BIT #define ARCH_MIPS64 @@ -55,24 +58,25 @@ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 16384 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 16384 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 /* Device virtual file system */ #define RT_USING_DFS #define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 10 -#define DFS_FILESYSTEM_TYPES_MAX 10 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 #define DFS_FD_MAX 16 #define RT_USING_DFS_ELMFAT @@ -98,6 +102,7 @@ #define RT_SYSTEM_WORKQUEUE_STACKSIZE 16384 #define RT_SYSTEM_WORKQUEUE_PRIORITY 5 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN @@ -110,6 +115,7 @@ #define RT_USING_LIBC #define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 /* Network */ @@ -189,6 +195,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread MIPS CPU */ @@ -222,15 +231,26 @@ /* system packages */ +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + /* peripheral libraries and drivers */ -/* miscellaneous packages */ +/* AI packages */ +/* miscellaneous packages */ + /* samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_LS #define SOC_LS2K1000 #define RT_USING_UART0 #define RT_USING_UART4 diff --git a/bsp/mb9bf506r/drivers/nand.c b/bsp/mb9bf506r/drivers/nand.c index fcd8cf42d4..1c03120d14 100644 --- a/bsp/mb9bf506r/drivers/nand.c +++ b/bsp/mb9bf506r/drivers/nand.c @@ -646,7 +646,7 @@ void nand_readoob(int block, int page) } FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]); -void nand_erase_chip() +void nand_erase_chip(void) { int i; unsigned char id; diff --git a/bsp/mini2440/drivers/uart.c b/bsp/mini2440/drivers/uart.c index 6226a3cb17..5c83d1f238 100644 --- a/bsp/mini2440/drivers/uart.c +++ b/bsp/mini2440/drivers/uart.c @@ -1,29 +1,32 @@ /* - * File : uart.c - * Drivers for s3c2440 uarts. + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2020-04-09 Jonne Code refactoring for new bsp */ +#include #include #include #include -#define ULCON_OFS 0x00 -#define UCON_OFS 0x04 -#define UFCON_OFS 0x08 -#define UMCON_OFS 0x0c -#define UTRSTAT_OFS 0x10 -#define UERSTAT_OFS 0x14 -#define UFSTAT_OFS 0x18 -#define UMSTAT_OFS 0x1c -#define UTXH_OFS 0x20 -#define URXH_OFS 0x24 -#define UBRDIV_OFS 0x28 +#define ULCON_OFS 0x00 +#define UCON_OFS 0x04 +#define UFCON_OFS 0x08 +#define UMCON_OFS 0x0c +#define UTRSTAT_OFS 0x10 +#define UERSTAT_OFS 0x14 +#define UFSTAT_OFS 0x18 +#define UMSTAT_OFS 0x1c +#define UTXH_OFS 0x20 +#define URXH_OFS 0x24 +#define UBRDIV_OFS 0x28 #define readl(addr) (*(volatile unsigned long *)(addr)) -#define writel(addr, value) (*(volatile unsigned long *)(addr) = value) +#define writel(addr, value) (*(volatile unsigned long *)(addr) = value) #define PCLK_HZ 50000000 @@ -33,9 +36,9 @@ struct hw_uart_device rt_uint32_t irqno; }; -static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct hw_uart_device* uart = serial->parent.user_data; + struct hw_uart_device *uart = serial->parent.user_data; writel(uart->hw_base + UBRDIV_OFS, PCLK_HZ / (cfg->baud_rate * 16)); @@ -44,22 +47,22 @@ static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct writel(uart->hw_base + UFCON_OFS, 0x00); writel(uart->hw_base + UMCON_OFS, 0x00); - return RT_EOK; + return RT_EOK; } static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct hw_uart_device *uart; + struct hw_uart_device *uart; int mask; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); uart = (struct hw_uart_device *)serial->parent.user_data; - if(uart->irqno == INTUART0) + if (uart->irqno == INTUART0) { mask = BIT_SUB_RXD0; } - else if(uart->irqno == INTUART1) + else if (uart->irqno == INTUART1) { mask = BIT_SUB_RXD1; } @@ -73,7 +76,7 @@ static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd, case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ INTSUBMSK |= mask; - + break; case RT_DEVICE_CTRL_SET_INT: @@ -86,28 +89,28 @@ static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd, } static int s3c2440_putc(struct rt_serial_device *serial, char c) { - struct hw_uart_device* uart = serial->parent.user_data; + struct hw_uart_device *uart = serial->parent.user_data; - while(!(readl(uart->hw_base + UTRSTAT_OFS) & (1<<2))) + while (!(readl(uart->hw_base + UTRSTAT_OFS) & (1 << 2))) { } writel(uart->hw_base + UTXH_OFS, c); - + return 0; - + } static int s3c2440_getc(struct rt_serial_device *serial) { - struct hw_uart_device* uart = serial->parent.user_data; + struct hw_uart_device *uart = serial->parent.user_data; int ch = -1; - if(readl(uart->hw_base + UTRSTAT_OFS) & (1<<0)) + if (readl(uart->hw_base + UTRSTAT_OFS) & (1 << 0)) { ch = readl(uart->hw_base + URXH_OFS) & 0x000000FF; } - + return ch; } @@ -116,61 +119,68 @@ static void rt_hw_uart_isr(int irqno, void *param) struct rt_serial_device *serial = (struct rt_serial_device *)param; rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - - /*clear SUBSRCPND*/ - if(irqno == INTUART0) + + /*clear SUBSRCPND*/ + if (irqno == INTUART0) { SUBSRCPND = BIT_SUB_RXD0; - } - else if(irqno == INTUART1) + } + else if (irqno == INTUART1) { SUBSRCPND = BIT_SUB_RXD1; } - else + else { SUBSRCPND = BIT_SUB_RXD2; } } -static struct rt_uart_ops s3c2440_uart_ops = { - .configure = s3c2440_serial_configure, - .control = s3c2440_serial_control, - .putc = s3c2440_putc, - .getc = s3c2440_getc +static struct rt_uart_ops s3c2440_uart_ops = +{ + .configure = s3c2440_serial_configure, + .control = s3c2440_serial_control, + .putc = s3c2440_putc, + .getc = s3c2440_getc }; -static struct rt_serial_device _serial0 = { - .ops = &s3c2440_uart_ops, - .config = RT_SERIAL_CONFIG_DEFAULT, - .serial_rx = NULL, - .serial_tx = NULL +static struct rt_serial_device _serial0 = +{ + .ops = &s3c2440_uart_ops, + .config = RT_SERIAL_CONFIG_DEFAULT, + .serial_rx = NULL, + .serial_tx = NULL }; -static struct hw_uart_device _hwserial0 = { - .hw_base = 0x50000000, - .irqno = INTUART0 +static struct hw_uart_device _hwserial0 = +{ + .hw_base = 0x50000000, + .irqno = INTUART0 }; -static struct rt_serial_device _serial1 = { - .ops = &s3c2440_uart_ops, - .config = RT_SERIAL_CONFIG_DEFAULT, - .serial_rx = NULL, - .serial_tx = NULL +static struct rt_serial_device _serial1 = +{ + .ops = &s3c2440_uart_ops, + .config = RT_SERIAL_CONFIG_DEFAULT, + .serial_rx = NULL, + .serial_tx = NULL }; -static struct hw_uart_device _hwserial1 = { - .hw_base = 0x50004000, - .irqno = INTUART1 +static struct hw_uart_device _hwserial1 = +{ + .hw_base = 0x50004000, + .irqno = INTUART1 }; -static struct rt_serial_device _serial2 = { - .ops = &s3c2440_uart_ops, - .config = RT_SERIAL_CONFIG_DEFAULT, - .serial_rx = NULL, - .serial_tx = NULL +static struct rt_serial_device _serial2 = +{ + .ops = &s3c2440_uart_ops, + .config = RT_SERIAL_CONFIG_DEFAULT, + .serial_rx = NULL, + .serial_tx = NULL }; -static struct hw_uart_device _hwserial2 = { - .hw_base = 0x50008000, - .irqno = INTUART2 +static struct hw_uart_device _hwserial2 = +{ + .hw_base = 0x50008000, + .irqno = INTUART2 }; @@ -185,7 +195,7 @@ int rt_hw_uart_init(void) rt_hw_serial_register(&_serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial0); rt_hw_interrupt_install(_hwserial0.irqno, rt_hw_uart_isr, &_serial0, "uart0"); rt_hw_interrupt_umask(INTUART0); - + /* register UART1 device */ rt_hw_serial_register(&_serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial1); rt_hw_interrupt_install(_hwserial1.irqno, rt_hw_uart_isr, &_serial1, "uart1"); @@ -198,5 +208,5 @@ int rt_hw_uart_init(void) return RT_EOK; } - INIT_BOARD_EXPORT(rt_hw_uart_init); + diff --git a/bsp/mm32f103x/.config b/bsp/mm32f103x/.config new file mode 100644 index 0000000000..42d5c54619 --- /dev/null +++ b/bsp/mm32f103x/.config @@ -0,0 +1,634 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=1024 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_WATCH_APP_FWK is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set +# CONFIG_PKG_USING_LWRDP is not set + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# + +# +# GPIO Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +CONFIG_SOC_MM32L373=y diff --git a/bsp/mm32f103x/.ignore_format.yml b/bsp/mm32f103x/.ignore_format.yml new file mode 100644 index 0000000000..69fcc99b1c --- /dev/null +++ b/bsp/mm32f103x/.ignore_format.yml @@ -0,0 +1,4 @@ +# files format check exclude path, please follow the instructions below to modify; + +dir_path: +- Libraries diff --git a/bsp/mm32f103x/Kconfig b/bsp/mm32f103x/Kconfig new file mode 100644 index 0000000000..b6f921f99a --- /dev/null +++ b/bsp/mm32f103x/Kconfig @@ -0,0 +1,26 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "drivers/Kconfig" + +config SOC_MM32L373 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_common_tables.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_common_tables.h new file mode 100644 index 0000000000..31e6005c3c --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +//extern const q31_t realCoefAQ31[1024]; +//extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_const_structs.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_const_structs.h new file mode 100644 index 0000000000..2033c5e375 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_math.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_math.h new file mode 100644 index 0000000000..1fb2c2580d --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_math.h @@ -0,0 +1,7435 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) +#include "core_cm7.h" +#elif defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + +/** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + +/** + * @brief Macros required for SINE and COSINE Controller functions + */ +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE +#define ALIGN4 +#else +#if defined (__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) +#else +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ +} arm_status; + +/** + * @brief 8-bit fractional data type in 1.7 format. + */ +typedef int8_t q7_t; + +/** + * @brief 16-bit fractional data type in 1.15 format. + */ +typedef int16_t q15_t; + +/** + * @brief 32-bit fractional data type in 1.31 format. + */ +typedef int32_t q31_t; + +/** + * @brief 64-bit fractional data type in 1.63 format. + */ +typedef int64_t q63_t; + +/** + * @brief 32-bit floating-point type definition. + */ +typedef float float32_t; + +/** + * @brief 64-bit floating-point type definition. + */ +typedef double float64_t; + +/** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) +/** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + +/** +* @brief definition to pack four 8 bit values. +*/ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + +/** + * @brief Clips Q63 to Q31 values. + */ +static __INLINE q31_t clip_q63_to_q31( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; +} + +/** + * @brief Clips Q63 to Q15 values. + */ +static __INLINE q15_t clip_q63_to_q15( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); +} + +/** + * @brief Clips Q31 to Q7 values. + */ +static __INLINE q7_t clip_q31_to_q7( + q31_t x) +{ + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; +} + +/** + * @brief Clips Q31 to Q15 values. + */ +static __INLINE q15_t clip_q31_to_q15( + q31_t x) +{ + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; +} + +/** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + +static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) +{ + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); +} + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + +static __INLINE uint32_t __CLZ( + q31_t data); + + +static __INLINE uint32_t __CLZ( + q31_t data) +{ + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) { + count += 1u; + mask = mask >> 1u; + } + + return (count); + +} + +#endif + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + +static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t* dst, + q31_t* pRecipTable) +{ + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) { + signBits = __CLZ(in) - 1; + } + else { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + +} + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ +static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t* dst, + q15_t* pRecipTable) +{ + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) { + signBits = __CLZ(in) - 17; + } + else { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + +} + + +/* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + +static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if(x > 0) { + posMax = (posMax - 1); + + if(x > posMax) { + x = posMax; + } + } + else { + negMin = -posMax; + + if(x < negMin) { + x = negMin; + } + } + return (x); + + +} + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + +/* + * @brief C custom defined QADD8 for M3 and M0 processors + */ +static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) +{ + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + +} + +/* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ +static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; +} + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ +static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + +} + +/* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ +static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + +} + +/* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ +static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ +static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) +{ + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; +} + +/* + * @brief C custom defined QASX for M3 and M0 processors + */ +static __INLINE q31_t __QASX( + q31_t x, + q31_t y) +{ + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; +} + +/* + * @brief C custom defined SHASX for M3 and M0 processors + */ +static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + + +/* + * @brief C custom defined QSAX for M3 and M0 processors + */ +static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) +{ + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; +} + +/* + * @brief C custom defined SHSAX for M3 and M0 processors + */ +static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ +static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) +{ + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); +} + +/* + * @brief C custom defined SMUADX for M3 and M0 processors + */ +static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) +{ + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); +} + +/* + * @brief C custom defined QADD for M3 and M0 processors + */ +static __INLINE q31_t __QADD( + q31_t x, + q31_t y) +{ + return clip_q63_to_q31((q63_t) x + y); +} + +/* + * @brief C custom defined QSUB for M3 and M0 processors + */ +static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) +{ + return clip_q63_to_q31((q63_t) x - y); +} + +/* + * @brief C custom defined SMLAD for M3 and M0 processors + */ +static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) +{ + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); +} + +/* + * @brief C custom defined SMLADX for M3 and M0 processors + */ +static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) +{ + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); +} + +/* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ +static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) +{ + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); +} + +/* + * @brief C custom defined SMLALD for M3 and M0 processors + */ +static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) +{ + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); +} + +/* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ +static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) +{ + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); +} + +/* + * @brief C custom defined SMUAD for M3 and M0 processors + */ +static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) +{ + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +/* + * @brief C custom defined SMUSD for M3 and M0 processors + */ +static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) +{ + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + + +/* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ +static __INLINE q31_t __SXTB16( + q31_t x) +{ + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); +} + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + +/** + * @brief Instance structure for the Q7 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q7; + +/** + * @brief Instance structure for the Q15 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f32; + + +/** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q7( + const arm_fir_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ +void arm_fir_init_q7( + arm_fir_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_fast_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + +arm_status arm_fir_init_q15( + arm_fir_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_fast_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ +void arm_fir_init_q31( + arm_fir_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_f32( + const arm_fir_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ +void arm_fir_init_f32( + arm_fir_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ +typedef struct { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + +} arm_biquad_casd_df1_inst_q15; + + +/** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + +} arm_biquad_casd_df1_inst_q31; + +/** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + +} arm_biquad_casd_df1_inst_f32; + + + +/** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15* S, + uint8_t numStages, + q15_t* pCoeffs, + q15_t* pState, + int8_t postShift); + + +/** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q31_t* pState, + int8_t postShift); + +/** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f32; + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f64; + +/** + * @brief Instance structure for the Q15 matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t* pData; /**< points to the data of the matrix. */ + +} arm_matrix_instance_q15; + +/** + * @brief Instance structure for the Q31 matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t* pData; /**< points to the data of the matrix. */ + +} arm_matrix_instance_q31; + + + +/** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + +/** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + +/** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pScratch); + +/** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32* pSrc, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15* pSrc, + arm_matrix_instance_q15* pDst); + +/** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31* pSrc, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + +/** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + +/** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + +/** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + +/** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + +/** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32* pSrc, + float32_t scale, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15* pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15* pDst); + +/** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31* pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_q31( + arm_matrix_instance_q31* S, + uint16_t nRows, + uint16_t nColumns, + q31_t* pData); + +/** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_q15( + arm_matrix_instance_q15* S, + uint16_t nRows, + uint16_t nColumns, + q15_t* pData); + +/** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_f32( + arm_matrix_instance_f32* S, + uint16_t nRows, + uint16_t nColumns, + float32_t* pData); + + + +/** + * @brief Instance structure for the Q15 PID Control. + */ +typedef struct { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q15; + +/** + * @brief Instance structure for the Q31 PID Control. + */ +typedef struct { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + +} arm_pid_instance_q31; + +/** + * @brief Instance structure for the floating-point PID Control. + */ +typedef struct { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} arm_pid_instance_f32; + + + +/** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_f32( + arm_pid_instance_f32* S, + int32_t resetStateFlag); + +/** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ +void arm_pid_reset_f32( + arm_pid_instance_f32* S); + + +/** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_q31( + arm_pid_instance_q31* S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31* S); + +/** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_q15( + arm_pid_instance_q15* S, + int32_t resetStateFlag); + +/** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ +void arm_pid_reset_q15( + arm_pid_instance_q15* S); + + +/** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ +typedef struct { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t* pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f32; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f32; + +/** +* @brief Instance structure for the Q31 bilinear interpolation function. +*/ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q31; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q15; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q7; + + +/** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + + + + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q15; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15* S, + q15_t* pSrc); + + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q15; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15* S, + q15_t* pSrc); + +/** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q31; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31* S, + q31_t* pSrc); + +/** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q31; + +/* Deprecated */ +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31* S, + q31_t* pSrc); + +/* Deprecated */ +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32* S, + float32_t* pSrc); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32* S, + float32_t* pSrc); + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15* S, + q15_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31* S, + q31_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_f32; + +void arm_cfft_f32( + const arm_cfft_instance_f32* S, + float32_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q15; + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15* S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q15( + const arm_rfft_instance_q15* S, + q15_t* pSrc, + q15_t* pDst); + +/** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q31; + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31* S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q31( + const arm_rfft_instance_q31* S, + q31_t* pSrc, + q31_t* pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_f32; + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32* S, + arm_cfft_radix4_instance_f32* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_f32( + const arm_rfft_instance_f32* S, + float32_t* pSrc, + float32_t* pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32* S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32* S, + float32_t* p, float32_t* pOut, + uint8_t ifftFlag); + +/** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t* pTwiddle; /**< points to the twiddle factor table. */ + float32_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_f32; + +/** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32* S, + arm_rfft_instance_f32* S_RFFT, + arm_cfft_radix4_instance_f32* S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + +/** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_f32( + const arm_dct4_instance_f32* S, + float32_t* pState, + float32_t* pInlineBuffer); + +/** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + q31_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q31; + +/** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31* S, + arm_rfft_instance_q31* S_RFFT, + arm_cfft_radix4_instance_q31* S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + +/** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_q31( + const arm_dct4_instance_q31* S, + q31_t* pState, + q31_t* pInlineBuffer); + +/** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + q15_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q15; + +/** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15* S, + arm_rfft_instance_q15* S_RFFT, + arm_cfft_radix4_instance_q15* S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + +/** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_q15( + const arm_dct4_instance_q15* S, + q15_t* pState, + q15_t* pInlineBuffer); + +/** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_f32( + float32_t* pSrc, + float32_t scale, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q7( + q7_t* pSrc, + q7_t scaleFract, + int8_t shift, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q15( + q15_t* pSrc, + q15_t scaleFract, + int8_t shift, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q31( + q31_t* pSrc, + q31_t scaleFract, + int8_t shift, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t blockSize, + float32_t* result); + +/** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q7( + q7_t* pSrcA, + q7_t* pSrcB, + uint32_t blockSize, + q31_t* result); + +/** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t blockSize, + q63_t* result); + +/** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t blockSize, + q63_t* result); + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q7( + q7_t* pSrc, + int8_t shiftBits, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q15( + q15_t* pSrc, + int8_t shiftBits, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q31( + q31_t* pSrc, + int8_t shiftBits, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_f32( + float32_t* pSrc, + float32_t offset, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q7( + q7_t* pSrc, + q7_t offset, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q15( + q15_t* pSrc, + q15_t offset, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q31( + q31_t* pSrc, + q31_t offset, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); +/** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); +/** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_f32( + float32_t value, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q7( + q7_t value, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q15( + q15_t value, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q31( + q31_t value, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + +void arm_conv_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + +void arm_conv_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + + +/** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + +/** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** +* @brief Convolution of Q7 sequences. +* @param[in] *pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] *pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. +* @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). +* @return none. +*/ + +void arm_conv_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + + +/** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + +/** +* @brief Partial convolution of Q15 sequences. +* @param[in] *pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] *pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] *pDst points to the block of output data +* @param[in] firstIndex is the first output sample to start with. +* @param[in] numPoints is the number of output points to be computed. +* @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). +* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + +/** + * @brief Instance structure for the Q15 FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + +} arm_fir_decimate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + +} arm_fir_decimate_instance_f32; + + + +/** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32* S, + uint16_t numTaps, + uint8_t M, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + + +/** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15* S, + uint16_t numTaps, + uint8_t M, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31* S, + uint16_t numTaps, + uint8_t M, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + + +/** + * @brief Instance structure for the Q15 FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} arm_fir_interpolate_instance_f32; + + +/** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15* S, + uint8_t L, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31* S, + uint8_t L, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32* S, + uint8_t L, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + +/** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + +} arm_biquad_cas_df1_32x64_ins_q31; + + +/** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q63_t* pState, + uint8_t postShift); + + + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f32; + + + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_stereo_df2T_instance_f32; + + + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f64; + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64* S, + float64_t* pSrc, + float64_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + +void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + +void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64* S, + uint8_t numStages, + float64_t* pCoeffs, + float64_t* pState); + + + +/** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_f32; + +/** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pCoeffs, + q15_t* pState); + + +/** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pCoeffs, + q31_t* pState); + + +/** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pCoeffs, + float32_t* pState); + +/** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_f32; + +/** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pkCoeffs, + float32_t* pvCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pkCoeffs, + q31_t* pvCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pkCoeffs, + q15_t* pvCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + * @brief Instance structure for the floating-point LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} arm_lms_instance_f32; + +/** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_f32( + const arm_lms_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_init_f32( + arm_lms_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q15; + + +/** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_init_q15( + arm_lms_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + +/** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_q15( + const arm_lms_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + +} arm_lms_instance_q31; + +/** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_q31( + const arm_lms_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_init_q31( + arm_lms_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + +/** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_f32; + +/** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_f32( + arm_lms_norm_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t* recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q31; + +/** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_q31( + arm_lms_norm_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + +/** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t* recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q15; + +/** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_q15( + arm_lms_norm_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + +/** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** +* @brief Correlation of Q15 sequences +* @param[in] *pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] *pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. +* @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @return none. +*/ +void arm_correlate_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + + +/** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + +void arm_correlate_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + +/** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + +/** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + +void arm_correlate_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + * @brief Instance structure for the floating-point sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_f32; + +/** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q31; + +/** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q15; + +/** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q7; + +/** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + float32_t* pScratchIn, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + q31_t* pScratchIn, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + q15_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + q7_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + +void arm_sin_cos_f32( + float32_t theta, + float32_t* pSinVal, + float32_t* pCcosVal); + +/* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + +void arm_sin_cos_q31( + q31_t theta, + q31_t* pSinVal, + q31_t* pCosVal); + + +/** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + + +/** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + +static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32* S, + float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + +static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31* S, + q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15* S, + q15_t in) +{ + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE* vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) * vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @} end of PID group + */ + + +/** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32* src, + arm_matrix_instance_f32* dst); + + +/** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + +arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64* src, + arm_matrix_instance_f64* dst); + + + +/** + * @ingroup groupController + */ + + +/** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup clarke + * @{ + */ + +/** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + +static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t* pIalpha, + float32_t* pIbeta) +{ + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + +} + +/** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + +static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t* pIalpha, + q31_t* pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); +} + +/** + * @} end of clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_q7_to_q31( + q7_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_clarke + * @{ + */ + +/** +* @brief Floating-point Inverse Clarke transform +* @param[in] Ialpha input two-phase orthogonal vector axis alpha +* @param[in] Ibeta input two-phase orthogonal vector axis beta +* @param[out] *pIa points to output three-phase coordinate a +* @param[out] *pIb points to output three-phase coordinate b +* @return none. +*/ + + +static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pIa, + float32_t* pIb) +{ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 * Ibeta; + +} + +/** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + +static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pIa, + q31_t* pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + +} + +/** + * @} end of inv_clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_q7_to_q15( + q7_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup park + * @{ + */ + +/** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + +static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pId, + float32_t* pIq, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + +} + +/** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + +static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pId, + q31_t* pIq, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +} + +/** + * @} end of park group + */ + +/** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q7_to_float( + q7_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_park + * @{ + */ + +/** +* @brief Floating-point Inverse Park transform +* @param[in] Id input coordinate of rotor reference frame d +* @param[in] Iq input coordinate of rotor reference frame q +* @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha +* @param[out] *pIbeta points to output two-phase orthogonal vector axis beta +* @param[in] sinVal sine value of rotation angle theta +* @param[in] cosVal cosine value of rotation angle theta +* @return none. +*/ + +static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t* pIalpha, + float32_t* pIbeta, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + +} + + +/** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + +static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t* pIalpha, + q31_t* pIbeta, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + +} + +/** + * @} end of Inverse park group + */ + + +/** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_float( + q31_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + +/** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + +static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32* S, + float32_t x) +{ + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t* pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); +} + +/** +* +* @brief Process function for the Q31 Linear Interpolation Function. +* @param[in] *pYData pointer to Q31 Linear Interpolation table +* @param[in] x input sample to process +* @param[in] nValues number of table values +* @return y processed output sample. +* +* \par +* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. +* This function can support maximum of table size 2^12. +* +*/ + + +static __INLINE q31_t arm_linear_interp_q31( + q31_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } + else if(index < 0) { + return (pYData[0]); + } + else { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + +} + +/** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + +static __INLINE q15_t arm_linear_interp_q15( + q15_t* pYData, + q31_t x, + uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } + else if(index < 0) { + return (pYData[0]); + } + else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + +} + +/** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + +static __INLINE q7_t arm_linear_interp_q7( + q7_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) { + return (pYData[nValues - 1]); + } + else { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + +} +/** + * @} end of LinearInterpolate group + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + +float32_t arm_sin_f32( + float32_t x); + +/** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + +q31_t arm_sin_q31( + q31_t x); + +/** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + +q15_t arm_sin_q15( + q15_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + +float32_t arm_cos_f32( + float32_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + +q31_t arm_cos_q31( + q31_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + +q15_t arm_cos_q15( + q15_t x); + + +/** + * @ingroup groupFastMath + */ + + +/** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+ *      x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ *
+ */ + + +/** + * @addtogroup SQRT + * @{ + */ + +/** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + +static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t* pOut) +{ + if(in > 0) { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + +} + + +/** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t* pOut); + +/** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t* pOut); + +/** + * @} end of SQRT group + */ + + + + + + +/** + * @brief floating-point Circular write function. + */ + +static __INLINE void arm_circularWrite_f32( + int32_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const int32_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + * @brief floating-point Circular Read function. + */ +static __INLINE void arm_circularRead_f32( + int32_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + int32_t* dst, + int32_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + +/** + * @brief Q15 Circular write function. + */ + +static __INLINE void arm_circularWrite_q15( + q15_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q15_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + * @brief Q15 Circular Read function. + */ +static __INLINE void arm_circularRead_q15( + q15_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q15_t* dst, + q15_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Q7 Circular write function. + */ + +static __INLINE void arm_circularWrite_q7( + q7_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q7_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + * @brief Q7 Circular Read function. + */ +static __INLINE void arm_circularRead_q7( + q7_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q7_t* dst, + q7_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q31( + q31_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + +/** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q15( + q15_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + +/** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q7( + q7_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_mean_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult); + +/** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + +/** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t numSamples, + q31_t* realResult, + q31_t* imagResult); + +/** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t numSamples, + q63_t* realResult, + q63_t* imagResult); + +/** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t numSamples, + float32_t* realResult, + float32_t* imagResult); + +/** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_q15( + q15_t* pSrcCmplx, + q15_t* pSrcReal, + q15_t* pCmplxDst, + uint32_t numSamples); + +/** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_q31( + q31_t* pSrcCmplx, + q31_t* pSrcReal, + q31_t* pCmplxDst, + uint32_t numSamples); + +/** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_f32( + float32_t* pSrcCmplx, + float32_t* pSrcReal, + float32_t* pCmplxDst, + uint32_t numSamples); + +/** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* result, + uint32_t* index); + +/** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + +/** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ +void arm_min_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + +/** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult, + uint32_t* pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + +/** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t numSamples); + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ +void arm_float_to_q31( + float32_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ +void arm_float_to_q15( + float32_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ +void arm_float_to_q7( + float32_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_q15( + q31_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_q7( + q31_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_float( + q15_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_q31( + q15_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_q7( + q15_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+ *     XF = floor(x)
+ *     YF = floor(y)
+ *
+ * \par + * The interpolated output point is computed as: + * 
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + +/** +* +* @brief Floating-point bilinear interpolation. +* @param[in,out] *S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate. +* @param[in] Y interpolation coordinate. +* @return out interpolated value. +*/ + + +static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32* S, + float32_t X, + float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t* pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + +} + +/** +* +* @brief Q31 bilinear interpolation. +* @param[in,out] *S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ + +static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31* S, + q31_t X, + q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + +} + +/** +* @brief Q15 bilinear interpolation. +* @param[in,out] *S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ + +static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + +} + +/** +* @brief Q7 bilinear interpolation. +* @param[in,out] *S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ + +static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + +} + +/** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +//Exit low optimization region - place directly after end of function definition +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") +#else +#define LOW_OPTIMIZATION_EXIT +#endif + +//Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +//Exit low optimization region - place directly after end of function definition +#define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition +#ifdef ARM_MATH_CM4 +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") +#else +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#endif + +//Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + +#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + +#define LOW_OPTIMIZATION_EXIT + +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm0.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm0.h new file mode 100644 index 0000000000..e326d90b1d --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm0.h @@ -0,0 +1,704 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus +extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) /* Cosmic */ +#if ( __CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0_REV +#define __CM0_REV 0x0000 +#warning "__CM0_REV not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm0plus.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm0plus.h new file mode 100644 index 0000000000..160e7ed3a0 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm0plus.h @@ -0,0 +1,814 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus +extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) /* Cosmic */ +#if ( __CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0PLUS_REV +#define __CM0PLUS_REV 0x0000 +#warning "__CM0PLUS_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0 +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm3.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm3.h new file mode 100644 index 0000000000..a4bffa490f --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm3.h @@ -0,0 +1,1638 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus +extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) /* Cosmic */ +#if ( __CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM3_REV +#define __CM3_REV 0x0200 +#warning "__CM3_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm4.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm4.h new file mode 100644 index 0000000000..bcc47d507d --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm4.h @@ -0,0 +1,1789 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus +extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __CSMC__ ) /* Cosmic */ +#if ( __CSMC__ & 0x400) // FPU present for parser +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM4_REV +#define __CM4_REV 0x0000 +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm7.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm7.h new file mode 100644 index 0000000000..5a8a76559c --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm7.h @@ -0,0 +1,2208 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 01. September 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus +extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __CSMC__ ) /* Cosmic */ +#if ( __CSMC__ & 0x400) // FPU present for parser +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM7_REV +#define __CM7_REV 0x0000 +#warning "__CM7_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 0 +#warning "__ICACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 0 +#warning "__DCACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DTCM_PRESENT +#define __DTCM_PRESENT 0 +#warning "__DTCM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); +#endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); +#endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); +#endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); +#endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); +#endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); +#endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); +#endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); +#endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmFunc.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmFunc.h new file mode 100644 index 0000000000..a74961ebf6 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmInstr.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmInstr.h new file mode 100644 index 0000000000..070512493e --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmSimd.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmSimd.h new file mode 100644 index 0000000000..7d5ca568f3 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_sc000.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_sc000.h new file mode 100644 index 0000000000..0aeb79dd0f --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_sc000.h @@ -0,0 +1,833 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#ifdef __cplusplus +extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) /* Cosmic */ +#if ( __CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC000_REV +#define __SC000_REV 0x0000 +#warning "__SC000_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_sc300.h b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_sc300.h new file mode 100644 index 0000000000..01e9bda96a --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_sc300.h @@ -0,0 +1,1618 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#ifdef __cplusplus +extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) /* Cosmic */ +#if ( __CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC300_REV +#define __SC300_REV 0x0000 +#warning "__SC300_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_common_tables.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_common_tables.h new file mode 100644 index 0000000000..7a59b5923e --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_common_tables.h @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_const_structs.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_const_structs.h new file mode 100644 index 0000000000..cbd1795c2b --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_const_structs.h @@ -0,0 +1,85 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH +}; + +#endif diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_math.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_math.h new file mode 100644 index 0000000000..25ec5e010d --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_math.h @@ -0,0 +1,7207 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Copyright Notice + * + * Copyright (C) 2010-2013 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + +/** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + +/** + * @brief Macros required for SINE and COSINE Controller functions + */ +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE +#define ALIGN4 +#else +#if defined (__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) +#else +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ +} arm_status; + +/** + * @brief 8-bit fractional data type in 1.7 format. + */ +typedef int8_t q7_t; + +/** + * @brief 16-bit fractional data type in 1.15 format. + */ +typedef int16_t q15_t; + +/** + * @brief 32-bit fractional data type in 1.31 format. + */ +typedef int32_t q31_t; + +/** + * @brief 64-bit fractional data type in 1.63 format. + */ +typedef int64_t q63_t; + +/** + * @brief 32-bit floating-point type definition. + */ +typedef float float32_t; + +/** + * @brief 64-bit floating-point type definition. + */ +typedef double float64_t; + +/** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) +/** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + +/** +* @brief definition to pack four 8 bit values. +*/ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + +/** + * @brief Clips Q63 to Q31 values. + */ +static __INLINE q31_t clip_q63_to_q31( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; +} + +/** + * @brief Clips Q63 to Q15 values. + */ +static __INLINE q15_t clip_q63_to_q15( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); +} + +/** + * @brief Clips Q31 to Q7 values. + */ +static __INLINE q7_t clip_q31_to_q7( + q31_t x) +{ + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; +} + +/** + * @brief Clips Q31 to Q15 values. + */ +static __INLINE q15_t clip_q31_to_q15( + q31_t x) +{ + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; +} + +/** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + +static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) +{ + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); +} + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + +static __INLINE uint32_t __CLZ( + q31_t data); + + +static __INLINE uint32_t __CLZ( + q31_t data) +{ + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) { + count += 1u; + mask = mask >> 1u; + } + + return (count); + +} + +#endif + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + +static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t* dst, + q31_t* pRecipTable) +{ + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) { + signBits = __CLZ(in) - 1; + } + else { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + +} + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ +static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t* dst, + q15_t* pRecipTable) +{ + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) { + signBits = __CLZ(in) - 17; + } + else { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + +} + + +/* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + +static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if(x > 0) { + posMax = (posMax - 1); + + if(x > posMax) { + x = posMax; + } + } + else { + negMin = -posMax; + + if(x < negMin) { + x = negMin; + } + } + return (x); + + +} + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + +/* + * @brief C custom defined QADD8 for M3 and M0 processors + */ +static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) +{ + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + +} + +/* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ +static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; +} + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ +static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + +} + +/* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ +static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + +} + +/* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ +static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ +static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) +{ + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; +} + +/* + * @brief C custom defined QASX for M3 and M0 processors + */ +static __INLINE q31_t __QASX( + q31_t x, + q31_t y) +{ + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; +} + +/* + * @brief C custom defined SHASX for M3 and M0 processors + */ +static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + + +/* + * @brief C custom defined QSAX for M3 and M0 processors + */ +static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) +{ + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; +} + +/* + * @brief C custom defined SHSAX for M3 and M0 processors + */ +static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) +{ + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ +static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) +{ + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); +} + +/* + * @brief C custom defined SMUADX for M3 and M0 processors + */ +static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) +{ + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); +} + +/* + * @brief C custom defined QADD for M3 and M0 processors + */ +static __INLINE q31_t __QADD( + q31_t x, + q31_t y) +{ + return clip_q63_to_q31((q63_t) x + y); +} + +/* + * @brief C custom defined QSUB for M3 and M0 processors + */ +static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) +{ + return clip_q63_to_q31((q63_t) x - y); +} + +/* + * @brief C custom defined SMLAD for M3 and M0 processors + */ +static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) +{ + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); +} + +/* + * @brief C custom defined SMLADX for M3 and M0 processors + */ +static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) +{ + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); +} + +/* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ +static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) +{ + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); +} + +/* + * @brief C custom defined SMLALD for M3 and M0 processors + */ +static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) +{ + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); +} + +/* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ +static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) +{ + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); +} + +/* + * @brief C custom defined SMUAD for M3 and M0 processors + */ +static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) +{ + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +/* + * @brief C custom defined SMUSD for M3 and M0 processors + */ +static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) +{ + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + + +/* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ +static __INLINE q31_t __SXTB16( + q31_t x) +{ + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); +} + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + +/** + * @brief Instance structure for the Q7 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q7; + +/** + * @brief Instance structure for the Q15 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f32; + + +/** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q7( + const arm_fir_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ +void arm_fir_init_q7( + arm_fir_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_fast_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + +arm_status arm_fir_init_q15( + arm_fir_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_fast_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ +void arm_fir_init_q31( + arm_fir_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_f32( + const arm_fir_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ +void arm_fir_init_f32( + arm_fir_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ +typedef struct { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + +} arm_biquad_casd_df1_inst_q15; + + +/** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + +} arm_biquad_casd_df1_inst_q31; + +/** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + +} arm_biquad_casd_df1_inst_f32; + + + +/** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15* S, + uint8_t numStages, + q15_t* pCoeffs, + q15_t* pState, + int8_t postShift); + + +/** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q31_t* pState, + int8_t postShift); + +/** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f32; + +/** + * @brief Instance structure for the Q15 matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t* pData; /**< points to the data of the matrix. */ + +} arm_matrix_instance_q15; + +/** + * @brief Instance structure for the Q31 matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t* pData; /**< points to the data of the matrix. */ + +} arm_matrix_instance_q31; + + + +/** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + +/** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32* pSrc, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15* pSrc, + arm_matrix_instance_q15* pDst); + +/** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31* pSrc, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + +/** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + +/** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + +/** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + +/** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + +/** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32* pSrc, + float32_t scale, + arm_matrix_instance_f32* pDst); + +/** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15* pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15* pDst); + +/** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31* pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_q31( + arm_matrix_instance_q31* S, + uint16_t nRows, + uint16_t nColumns, + q31_t* pData); + +/** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_q15( + arm_matrix_instance_q15* S, + uint16_t nRows, + uint16_t nColumns, + q15_t* pData); + +/** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_f32( + arm_matrix_instance_f32* S, + uint16_t nRows, + uint16_t nColumns, + float32_t* pData); + + + +/** + * @brief Instance structure for the Q15 PID Control. + */ +typedef struct { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q15; + +/** + * @brief Instance structure for the Q31 PID Control. + */ +typedef struct { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + +} arm_pid_instance_q31; + +/** + * @brief Instance structure for the floating-point PID Control. + */ +typedef struct { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} arm_pid_instance_f32; + + + +/** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_f32( + arm_pid_instance_f32* S, + int32_t resetStateFlag); + +/** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ +void arm_pid_reset_f32( + arm_pid_instance_f32* S); + + +/** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_q31( + arm_pid_instance_q31* S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31* S); + +/** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_q15( + arm_pid_instance_q15* S, + int32_t resetStateFlag); + +/** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ +void arm_pid_reset_q15( + arm_pid_instance_q15* S); + + +/** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ +typedef struct { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t* pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f32; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f32; + +/** +* @brief Instance structure for the Q31 bilinear interpolation function. +*/ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q31; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q15; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q7; + + +/** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + + + + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q15; + +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15* S, + q15_t* pSrc); + + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q15; + +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15* S, + q15_t* pSrc); + +/** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q31; + +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31* S, + q31_t* pSrc); + +/** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q31; + + +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31* S, + q31_t* pSrc); + +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32* S, + float32_t* pSrc); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32* S, + float32_t* pSrc); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_f32; + +void arm_cfft_f32( + const arm_cfft_instance_f32* S, + float32_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q15; + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15* S, + arm_cfft_radix4_instance_q15* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q15( + const arm_rfft_instance_q15* S, + q15_t* pSrc, + q15_t* pDst); + +/** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q31; + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31* S, + arm_cfft_radix4_instance_q31* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q31( + const arm_rfft_instance_q31* S, + q31_t* pSrc, + q31_t* pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_f32; + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32* S, + arm_cfft_radix4_instance_f32* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_f32( + const arm_rfft_instance_f32* S, + float32_t* pSrc, + float32_t* pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32* S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32* S, + float32_t* p, float32_t* pOut, + uint8_t ifftFlag); + +/** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t* pTwiddle; /**< points to the twiddle factor table. */ + float32_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_f32; + +/** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32* S, + arm_rfft_instance_f32* S_RFFT, + arm_cfft_radix4_instance_f32* S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + +/** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_f32( + const arm_dct4_instance_f32* S, + float32_t* pState, + float32_t* pInlineBuffer); + +/** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + q31_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q31; + +/** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31* S, + arm_rfft_instance_q31* S_RFFT, + arm_cfft_radix4_instance_q31* S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + +/** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_q31( + const arm_dct4_instance_q31* S, + q31_t* pState, + q31_t* pInlineBuffer); + +/** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + q15_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q15; + +/** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15* S, + arm_rfft_instance_q15* S_RFFT, + arm_cfft_radix4_instance_q15* S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + +/** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_q15( + const arm_dct4_instance_q15* S, + q15_t* pState, + q15_t* pInlineBuffer); + +/** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_f32( + float32_t* pSrc, + float32_t scale, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q7( + q7_t* pSrc, + q7_t scaleFract, + int8_t shift, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q15( + q15_t* pSrc, + q15_t scaleFract, + int8_t shift, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q31( + q31_t* pSrc, + q31_t scaleFract, + int8_t shift, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t blockSize, + float32_t* result); + +/** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q7( + q7_t* pSrcA, + q7_t* pSrcB, + uint32_t blockSize, + q31_t* result); + +/** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t blockSize, + q63_t* result); + +/** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t blockSize, + q63_t* result); + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q7( + q7_t* pSrc, + int8_t shiftBits, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q15( + q15_t* pSrc, + int8_t shiftBits, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q31( + q31_t* pSrc, + int8_t shiftBits, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_f32( + float32_t* pSrc, + float32_t offset, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q7( + q7_t* pSrc, + q7_t offset, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q15( + q15_t* pSrc, + q15_t offset, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q31( + q31_t* pSrc, + q31_t offset, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); +/** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); +/** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_f32( + float32_t value, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q7( + q7_t value, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q15( + q15_t value, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q31( + q31_t value, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + +void arm_conv_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + +void arm_conv_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + + +/** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + +/** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** +* @brief Convolution of Q7 sequences. +* @param[in] *pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] *pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. +* @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). +* @return none. +*/ + +void arm_conv_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + + +/** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + +/** +* @brief Partial convolution of Q15 sequences. +* @param[in] *pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] *pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] *pDst points to the block of output data +* @param[in] firstIndex is the first output sample to start with. +* @param[in] numPoints is the number of output points to be computed. +* @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). +* @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + +/** + * @brief Instance structure for the Q15 FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + +} arm_fir_decimate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + +} arm_fir_decimate_instance_f32; + + + +/** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32* S, + uint16_t numTaps, + uint8_t M, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + + +/** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15* S, + uint16_t numTaps, + uint8_t M, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31* S, + uint16_t numTaps, + uint8_t M, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + + +/** + * @brief Instance structure for the Q15 FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} arm_fir_interpolate_instance_f32; + + +/** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15* S, + uint8_t L, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31* S, + uint8_t L, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32* S, + uint8_t L, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + +/** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + +} arm_biquad_cas_df1_32x64_ins_q31; + + +/** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q63_t* pState, + uint8_t postShift); + + + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f32; + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + + +/** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_f32; + +/** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pCoeffs, + q15_t* pState); + + +/** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pCoeffs, + q31_t* pState); + + +/** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pCoeffs, + float32_t* pState); + +/** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_f32; + +/** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pkCoeffs, + float32_t* pvCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pkCoeffs, + q31_t* pvCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pkCoeffs, + q15_t* pvCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + * @brief Instance structure for the floating-point LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} arm_lms_instance_f32; + +/** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_f32( + const arm_lms_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_init_f32( + arm_lms_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q15; + + +/** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_init_q15( + arm_lms_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + +/** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_q15( + const arm_lms_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + +} arm_lms_instance_q31; + +/** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_q31( + const arm_lms_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_init_q31( + arm_lms_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + +/** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_f32; + +/** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_f32( + arm_lms_norm_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t* recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q31; + +/** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_q31( + arm_lms_norm_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + +/** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t* recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q15; + +/** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_q15( + arm_lms_norm_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + +/** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** +* @brief Correlation of Q15 sequences +* @param[in] *pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] *pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. +* @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @return none. +*/ +void arm_correlate_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + + +/** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + +void arm_correlate_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + +/** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + +/** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + +void arm_correlate_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + * @brief Instance structure for the floating-point sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_f32; + +/** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q31; + +/** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q15; + +/** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q7; + +/** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + float32_t* pScratchIn, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + q31_t* pScratchIn, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + q15_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + q7_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + +void arm_sin_cos_f32( + float32_t theta, + float32_t* pSinVal, + float32_t* pCcosVal); + +/* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + +void arm_sin_cos_q31( + q31_t theta, + q31_t* pSinVal, + q31_t* pCosVal); + + +/** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + + +/** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + +static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32* S, + float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + +static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31* S, + q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15* S, + q15_t in) +{ + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE* vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) * vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @} end of PID group + */ + + +/** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32* src, + arm_matrix_instance_f32* dst); + + + +/** + * @ingroup groupController + */ + + +/** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup clarke + * @{ + */ + +/** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + +static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t* pIalpha, + float32_t* pIbeta) +{ + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + +} + +/** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + +static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t* pIalpha, + q31_t* pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); +} + +/** + * @} end of clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_q7_to_q31( + q7_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_clarke + * @{ + */ + +/** +* @brief Floating-point Inverse Clarke transform +* @param[in] Ialpha input two-phase orthogonal vector axis alpha +* @param[in] Ibeta input two-phase orthogonal vector axis beta +* @param[out] *pIa points to output three-phase coordinate a +* @param[out] *pIb points to output three-phase coordinate b +* @return none. +*/ + + +static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pIa, + float32_t* pIb) +{ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 * Ibeta; + +} + +/** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + +static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pIa, + q31_t* pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + +} + +/** + * @} end of inv_clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_q7_to_q15( + q7_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup park + * @{ + */ + +/** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + +static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pId, + float32_t* pIq, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + +} + +/** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + +static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pId, + q31_t* pIq, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +} + +/** + * @} end of park group + */ + +/** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q7_to_float( + q7_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_park + * @{ + */ + +/** +* @brief Floating-point Inverse Park transform +* @param[in] Id input coordinate of rotor reference frame d +* @param[in] Iq input coordinate of rotor reference frame q +* @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha +* @param[out] *pIbeta points to output two-phase orthogonal vector axis beta +* @param[in] sinVal sine value of rotation angle theta +* @param[in] cosVal cosine value of rotation angle theta +* @return none. +*/ + +static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t* pIalpha, + float32_t* pIbeta, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + +} + + +/** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + +static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t* pIalpha, + q31_t* pIbeta, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + +} + +/** + * @} end of Inverse park group + */ + + +/** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_float( + q31_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + +/** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + +static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32* S, + float32_t x) +{ + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t* pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); +} + +/** +* +* @brief Process function for the Q31 Linear Interpolation Function. +* @param[in] *pYData pointer to Q31 Linear Interpolation table +* @param[in] x input sample to process +* @param[in] nValues number of table values +* @return y processed output sample. +* +* \par +* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. +* This function can support maximum of table size 2^12. +* +*/ + + +static __INLINE q31_t arm_linear_interp_q31( + q31_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } + else if(index < 0) { + return (pYData[0]); + } + else { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + +} + +/** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + +static __INLINE q15_t arm_linear_interp_q15( + q15_t* pYData, + q31_t x, + uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } + else if(index < 0) { + return (pYData[0]); + } + else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + +} + +/** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + +static __INLINE q7_t arm_linear_interp_q7( + q7_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) { + return (pYData[nValues - 1]); + } + else { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + +} +/** + * @} end of LinearInterpolate group + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + +float32_t arm_sin_f32( + float32_t x); + +/** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + +q31_t arm_sin_q31( + q31_t x); + +/** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + +q15_t arm_sin_q15( + q15_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + +float32_t arm_cos_f32( + float32_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + +q31_t arm_cos_q31( + q31_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + +q15_t arm_cos_q15( + q15_t x); + + +/** + * @ingroup groupFastMath + */ + + +/** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+ *      x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ *
+ */ + + +/** + * @addtogroup SQRT + * @{ + */ + +/** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + +static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t* pOut) +{ + if(in > 0) { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + +} + + +/** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t* pOut); + +/** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t* pOut); + +/** + * @} end of SQRT group + */ + + + + + + +/** + * @brief floating-point Circular write function. + */ + +static __INLINE void arm_circularWrite_f32( + int32_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const int32_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + * @brief floating-point Circular Read function. + */ +static __INLINE void arm_circularRead_f32( + int32_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + int32_t* dst, + int32_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + +/** + * @brief Q15 Circular write function. + */ + +static __INLINE void arm_circularWrite_q15( + q15_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q15_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + * @brief Q15 Circular Read function. + */ +static __INLINE void arm_circularRead_q15( + q15_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q15_t* dst, + q15_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Q7 Circular write function. + */ + +static __INLINE void arm_circularWrite_q7( + q7_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q7_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + * @brief Q7 Circular Read function. + */ +static __INLINE void arm_circularRead_q7( + q7_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q7_t* dst, + q7_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q31( + q31_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + +/** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q15( + q15_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + +/** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q7( + q7_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_mean_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult); + +/** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_q31( + q31_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + +/** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_q15( + q15_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + +/** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t numSamples, + q31_t* realResult, + q31_t* imagResult); + +/** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t numSamples, + q63_t* realResult, + q63_t* imagResult); + +/** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t numSamples, + float32_t* realResult, + float32_t* imagResult); + +/** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_q15( + q15_t* pSrcCmplx, + q15_t* pSrcReal, + q15_t* pCmplxDst, + uint32_t numSamples); + +/** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_q31( + q31_t* pSrcCmplx, + q31_t* pSrcReal, + q31_t* pCmplxDst, + uint32_t numSamples); + +/** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_f32( + float32_t* pSrcCmplx, + float32_t* pSrcReal, + float32_t* pCmplxDst, + uint32_t numSamples); + +/** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* result, + uint32_t* index); + +/** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + +/** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ +void arm_min_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + +/** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult, + uint32_t* pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + +/** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t numSamples); + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ +void arm_float_to_q31( + float32_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ +void arm_float_to_q15( + float32_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ +void arm_float_to_q7( + float32_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_q15( + q31_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_q7( + q31_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_float( + q15_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_q31( + q15_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_q7( + q15_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+ *     XF = floor(x)
+ *     YF = floor(y)
+ *
+ * \par + * The interpolated output point is computed as: + * 
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + +/** +* +* @brief Floating-point bilinear interpolation. +* @param[in,out] *S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate. +* @param[in] Y interpolation coordinate. +* @return out interpolated value. +*/ + + +static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32* S, + float32_t X, + float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t* pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + +} + +/** +* +* @brief Q31 bilinear interpolation. +* @param[in,out] *S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ + +static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31* S, + q31_t X, + q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + +} + +/** +* @brief Q15 bilinear interpolation. +* @param[in,out] *S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ + +static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + +} + +/** +* @brief Q7 bilinear interpolation. +* @param[in,out] *S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ + +static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + +} + +/** + * @} end of BilinearInterpolate group + */ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition +#define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR +//SMMLA +#define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition +#define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) +//SMMLA +#define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + +#define LOW_OPTIMIZATION_EXIT + +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm0.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm0.h new file mode 100644 index 0000000000..42f2e58597 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm0.h @@ -0,0 +1,660 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.02 + * @date 16. July 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ +#define __NVIC_PRIO_BITS 2 +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0_REV +#define __CM0_REV 0x0000 +#warning "__CM0_REV not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm0plus.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm0plus.h new file mode 100644 index 0000000000..563845ea05 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm0plus.h @@ -0,0 +1,785 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0PLUS_REV +#define __CM0PLUS_REV 0x0000 +#warning "__CM0PLUS_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0 +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm3.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm3.h new file mode 100644 index 0000000000..be7d945b27 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm3.h @@ -0,0 +1,1615 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM3_REV +#define __CM3_REV 0x0200 +#warning "__CM3_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm4.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm4.h new file mode 100644 index 0000000000..d3fb1d3133 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm4.h @@ -0,0 +1,1759 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM4_REV +#define __CM4_REV 0x0000 +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm4_simd.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm4_simd.h new file mode 100644 index 0000000000..1831d75ab3 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm4_simd.h @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cmFunc.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cmFunc.h new file mode 100644 index 0000000000..763407aa2f --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2016 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2016 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cmInstr.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cmInstr.h new file mode 100644 index 0000000000..ae4d62a80e --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2016 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2016 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_sc000.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_sc000.h new file mode 100644 index 0000000000..40c121cc61 --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_sc000.h @@ -0,0 +1,804 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (0) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC000_REV +#define __SC000_REV 0x0000 +#warning "__SC000_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_sc300.h b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_sc300.h new file mode 100644 index 0000000000..0ddecfd47a --- /dev/null +++ b/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_sc300.h @@ -0,0 +1,1586 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC300_REV +#define __SC300_REV 0x0000 +#warning "__SC300_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_adc.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_adc.h new file mode 100644 index 0000000000..1fae4e798b --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_adc.h @@ -0,0 +1,412 @@ +/** +****************************************************************************** +* @file HAL_adc.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the ADC firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_ADC_H +#define __HAL_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup ADC +* @{ +*/ + +/** @defgroup ADC_Exported_Types +* @{ +*/ + +/** +* @brief ADC Init structure definition +*/ + +/* +typedef struct +{ +uint32_t ADC_Mode; +FunctionalState ADC_ScanConvMode; +FunctionalState ADC_ContinuousConvMode; +uint32_t ADC_ExternalTrigConv; +uint32_t ADC_DataAlign; +uint8_t ADC_NbrOfChannel; +}ADC_InitTypeDef; +*/ +typedef struct +{ + uint32_t ADC_Resolution; + uint32_t ADC_PRESCARE; + uint32_t ADC_Mode; + FunctionalState ADC_ContinuousConvMode; + uint32_t ADC_ExternalTrigConv; + uint32_t ADC_DataAlign; +} ADC_InitTypeDef; +/** +* @} +*/ + +/** @defgroup ADC_Exported_Constants +* @{ +*/ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == ADC2_BASE)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == ADC2_BASE)) + +/** @defgroup ADC_Resolution +* @{ +*/ +#define ADC_Resolution_12b ((uint32_t)0x00000000) +#define ADC_Resolution_11b ((uint32_t)0x00000080) +#define ADC_Resolution_10b ((uint32_t)0x00000100) +#define ADC_Resolution_9b ((uint32_t)0x00000180) +#define ADC_Resolution_8b ((uint32_t)0x00000200) +/** +* @brief for ADC1, ADC2 +*/ + +#define ADC_PCLK2_PRESCARE_2 ((uint32_t)0x00000000) +#define ADC_PCLK2_PRESCARE_4 ((uint32_t)0x00000010) +#define ADC_PCLK2_PRESCARE_6 ((uint32_t)0x00000020) +#define ADC_PCLK2_PRESCARE_8 ((uint32_t)0x00000030) +#define ADC_PCLK2_PRESCARE_10 ((uint32_t)0x00000040) +#define ADC_PCLK2_PRESCARE_12 ((uint32_t)0x00000050) +#define ADC_PCLK2_PRESCARE_14 ((uint32_t)0x00000060) +#define ADC_PCLK2_PRESCARE_16 ((uint32_t)0x00000070) + + +/** @defgroup ADC_dual_mode +* @{ +*/ + +#define ADC_Mode_Single ((uint32_t)0x00000000) +#define ADC_Mode_Single_Period ((uint32_t)0x00000200) +#define ADC_Mode_Continuous_Scan ((uint32_t)0x00000400) + + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Single) || \ + ((MODE) == ADC_Mode_Single_Period) || \ + ((MODE) == ADC_Mode_Continuous_Scan)) +/** +* @} +*/ + + + +/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion +* @{ +*/ + +/** +* @brief for ADC1 +*/ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00000010) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00000020) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00000030) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00000040) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x00000050) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060) +#define ADC_ExternalTrigConv_EXTI_11 ((uint32_t)0x00000070) + +/** +* @brief for ADC2 +*/ + +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC4 ((uint32_t)0x00000010) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00000020) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00000030) +#define ADC_ExternalTrigConv_T3_CC4 ((uint32_t)0x00000040) +#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x00000050) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060) +#define ADC_ExternalTrigConv_EXTI_15 ((uint32_t)0x00000070) + + + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_EXTI_11) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_EXTI_15)) +/** +* @} +*/ + +/** @defgroup ADC_data_align +* @{ +*/ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** +* @} +*/ + +/** @defgroup ADC_channels +* @{ +*/ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_All ((uint8_t)0x0f) + + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_All)) +/** +* @} +*/ + +#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */ +#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +/** @defgroup ADC_sampling_times +* @{ +*/ + +#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000) +#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001) +#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002) +#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003) +#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004) +#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005) +#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006) +#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007) + +/** @defgroup ADC_injected_channel_selection +* @{ +*/ + +#define ADC_InjectedChannel_0 ((uint8_t)0x18) +#define ADC_InjectedChannel_1 ((uint8_t)0x1C) +#define ADC_InjectedChannel_2 ((uint8_t)0x20) +#define ADC_InjectedChannel_3 ((uint8_t)0x24) +#define ADC_InjectedChannel_4 ((uint8_t)0x28) +#define ADC_InjectedChannel_5 ((uint8_t)0x2C) +#define ADC_InjectedChannel_6 ((uint8_t)0x30) +#define ADC_InjectedChannel_7 ((uint8_t)0x34) +#define ADC_InjectedChannel_8 ((uint8_t)0x38) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4) || \ + ((CHANNEL) == ADC_InjectedChannel_5) || \ + ((CHANNEL) == ADC_InjectedChannel_6) || \ + ((CHANNEL) == ADC_InjectedChannel_7) || \ + ((CHANNEL) == ADC_InjectedChannel_8)) +/** +* @} +*/ + +/** @defgroup ADC_analog_watchdog_selection +* @{ +*/ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00000002) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** +* @} +*/ + +/** @defgroup ADC_interrupts_definition +* @{ +*/ + +#define ADC_IT_EOC ((uint16_t)0x0001) +#define ADC_IT_AWD ((uint16_t)0x0002) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xFFFC) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD)) + +/** +* @} +*/ + +/** @defgroup ADC_flags_definition +* @{ +*/ + +#define ADC_FLAG_AWD ((uint8_t)0x02) +#define ADC_FLAG_EOC ((uint8_t)0x01) +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC)) + +/** +* @} +*/ + +/** @defgroup ADC_thresholds +* @{ +*/ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** +* @} +*/ + +/** @defgroup ADC_injected_offset +* @{ +*/ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** +* @} +*/ + +/** @defgroup ADC_injected_length +* @{ +*/ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** +* @} +*/ + +/** @defgroup ADC_injected_rank +* @{ +*/ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** +* @} +*/ + + +/** @defgroup ADC_regular_length +* @{ +*/ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** +* @} +*/ + +/** @defgroup ADC_regular_rank +* @{ +*/ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** +* @} +*/ + +/** @defgroup ADC_regular_discontinuous_mode_number +* @{ +*/ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Exported_Functions +* @{ +*/ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); + +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#endif /*__HAL_ADC_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_bkp.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_bkp.h new file mode 100644 index 0000000000..c9f23993d5 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_bkp.h @@ -0,0 +1,186 @@ +/** +****************************************************************************** +* @file HAL_bkp.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the BKP firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_BKP_H +#define __HAL_BKP_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup BKP +* @{ +*/ + +/** @defgroup BKP_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup BKP_Exported_Constants +* @{ +*/ + +/** @defgroup Tamper_Pin_active_level +* @{ +*/ + +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) +/** +* @} +*/ + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin +* @{ +*/ + +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) +/** +* @} +*/ + +/** @defgroup Data_Backup_Register +* @{ +*/ + +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup BKP_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup BKP_Exported_Functions +* @{ +*/ + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#endif /* __HAL_BKP_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_can.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_can.h new file mode 100644 index 0000000000..f9e9af634a --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_can.h @@ -0,0 +1,392 @@ +/** +****************************************************************************** +* @file HAL_can.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the BKP firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_CAN_H +#define __HAL_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + + +/** @defgroup CAN_sleep_constants +* @{ +*/ + +#define CANINITFAILED ((uint8_t)0x00) /* CAN initialization failed */ +#define CANINITOK ((uint8_t)0x01) /* CAN initialization ok */ + +/** +* @} +*/ + + + +/** @defgroup CAN_sleep_constants +* @{ +*/ + +#define CANSLEEPFAILED ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CANSLEEPOK ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/** +* @} +*/ + + +/** @defgroup CAN_wake_up_constants +* @{ +*/ + +#define CANWAKEUPFAILED ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/** +* @} +*/ + +/** +* @brief parasmeter of CAN Mode +*/ +#define CAN_BASICMode ((uint32_t)0x0) +#define CAN_PELIMode ((uint32_t)0x80) +#define CAN_WorkMode ((uint32_t)0x80) +#define CAN_ResetMode ((uint32_t)0x1) +#define CAN_ListenOnlyMode ((uint32_t)0x2) +#define CAN_SeftTestMode ((uint32_t)0x4) +#define CAN_FilterMode_Singal ((uint32_t)0x8) +#define CAN_FilterMode_Double ((uint32_t)0xf7) +#define CAN_SleepMode ((uint32_t)0x10) + +/** +* @} +*/ + +/** +* @brief parasmeter of BASIC CAN interrupt +*/ +#define CAN_IT_RIE ((uint32_t)0x2) +#define CAN_IT_TIE ((uint32_t)0x4) +#define CAN_IT_EIE ((uint32_t)0x8) +#define CAN_IT_OIE ((uint32_t)0x10) + +/** +* @} +*/ + +/** +* @brief parasmeter of PELI CAN interrupt +*/ +#define CAN_IT_RI ((uint32_t)0x1) +#define CAN_IT_TI ((uint32_t)0x2) +#define CAN_IT_EI ((uint32_t)0x4) +#define CAN_IT_DOI ((uint32_t)0x8) +#define CAN_IT_WUI ((uint32_t)0x10) +#define CAN_IT_EPI ((uint32_t)0x20) +#define CAN_IT_ALI ((uint32_t)0x40) +#define CAN_IT_BEI ((uint32_t)0x80) +#define CAN_IT_ALL ((uint32_t)0xff) + +/** +* @} +*/ + +/** +* @brief parasmeter of CAN Status +*/ +#define CAN_STATUS_RBS ((uint32_t)0x1) +#define CAN_STATUS_DOS ((uint32_t)0x2) +#define CAN_STATUS_TBS ((uint32_t)0x4) +#define CAN_STATUS_TCS ((uint32_t)0x8) +#define CAN_STATUS_RS ((uint32_t)0x10) +#define CAN_STATUS_TS ((uint32_t)0x20) +#define CAN_STATUS_ES ((uint32_t)0x40) +#define CAN_STATUS_BS ((uint32_t)0x80) + +/** +* @} +*/ + +/** +* @brief parasmeter of CAN Command register +*/ +#define CAN_TR 0x1 +#define CAN_AT 0x2 +#define CAN_RRB 0x4 +#define CAN_CDO 0x8 + +/** +* @} +*/ + +/** +* @brief CAN_Basic init structure definition +*/ +typedef struct +{ + uint8_t SJW; + uint8_t BRP; + FlagStatus SAM; + uint8_t TESG2; + uint8_t TESG1; + FunctionalState GTS; + uint8_t CDCLK; + uint8_t CLOSE_OPEN_CLK; + uint8_t RXINTEN; + uint8_t CBP; +} CAN_Basic_InitTypeDef; + +/** +* @} +*/ + +/** +* @brief CAN_Peli init structure definition +*/ +typedef struct +{ + uint8_t SJW; + uint8_t BRP; + FlagStatus SAM; + uint8_t TESG2; + uint8_t TESG1; + FunctionalState LOM; + FunctionalState STM; + FunctionalState SM; + FunctionalState SRR; + uint32_t EWLR; +} CAN_Peli_InitTypeDef; + +/** +* @} +*/ + +/** +* @brief CAN_Basic filter init structure definition +*/ +typedef struct +{ + uint8_t CAN_FilterId; /*!< Specifies the filter identification number . + This parameter can be a value between 0x00 and 0xFF */ + + uint8_t CAN_FilterMaskId; /*!< Specifies the filter mask number or identification number, + This parameter can be a value between 0x00 and 0xFF */ +} CAN_Basic_FilterInitTypeDef; + +/** +* @} +*/ + +/** +* @brief CAN_Peli filter init structure definition +*/ +typedef struct +{ + uint8_t AFM; + uint8_t CAN_FilterId0; /*!< Specifies the filter identification number + This parameter can be a value between 0x00 and 0xFF */ + uint8_t CAN_FilterId1; + uint8_t CAN_FilterId2; + uint8_t CAN_FilterId3; + + uint8_t CAN_FilterMaskId0; /*!< Specifies the filter mask number or identification number, + This parameter can be a value between 0x00 and 0xFF */ + uint8_t CAN_FilterMaskId1; + uint8_t CAN_FilterMaskId2; + uint8_t CAN_FilterMaskId3; +} CAN_Peli_FilterInitTypeDef; + +/** +* @} +*/ + +/** +* @brief CAN_Peli transmit frame definition +*/ +typedef enum {DataFrame = 0, RemoteFrame = !DataFrame} TransFrame; + +/** +* @} +*/ + +/** +* @brief CAN_Basic Tx message structure definition +*/ +typedef struct +{ + uint8_t IDH; /*!< Specifies the standard high identifier. + This parameter can be a value between 0 to 0xFF. */ + uint8_t IDL; /*!< Specifies the standard low identifier. + This parameter can be a value between 0 to 0x7. */ + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be @TransFrame */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanBasicTxMsg; + +/** +* @} +*/ + +/** +* @brief CAN_Basic Rx message structure definition +*/ +typedef struct +{ + uint16_t ID; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref TransFrame */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + +} CanBasicRxMsg; + +/** +* @} +*/ + +/** +* @brief CAN_Peli_Tx message structure definition +*/ +typedef struct +{ + uint8_t IDLL; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0xFF. */ + uint8_t IDLH; + uint8_t IDHL; + uint8_t IDHH; + uint8_t FF; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref TransFrame */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanPeliTxMsg; + +/** +* @} +*/ + +/** +* @brief CAN Rx message structure definition +*/ +typedef struct +{ + uint32_t ID; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + uint8_t FF; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref TransFrame */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + +} CanPeliRxMsg; + + + + +#define CANTXFAILED ((uint8_t)0x00) /* CAN transmission failed */ +#define CANTXOK ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CANTXPENDING ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_NO_MB ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + + +/************************ Basic and Peli Work all need function ********************/ + +void CAN_Mode_Cmd(CAN_TypeDef* CANx, uint32_t CAN_MODE); +void CAN_ResetMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_ClearDataOverflow(CAN_TypeDef* CANx); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx); + + +/************************ Basic Work function ********************/ +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_Basic_InitTypeDef* CAN_Basic_InitStruct); +void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* CAN_Basic_FilterInitStruct); +void CAN_StructInit(CAN_Basic_InitTypeDef* CAN_Basic_InitStruct); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState Newstate); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanBasicTxMsg* BasicTxMessage); +void CAN_CancelTransmit(CAN_TypeDef* CANx); +void CAN_FIFORelease(CAN_TypeDef* CANx); +void CAN_Receive(CAN_TypeDef* CANx, CanBasicRxMsg* BasicRxMessage); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); + + +/************************ Peli Work function *********************/ +void CAN_Peli_SleepMode_Cmd(FunctionalState NewState); +void CAN_Peli_Init(CAN_Peli_InitTypeDef* CAN_InitStruct); +void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct); +void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct); +void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct); +void CAN_Peli_Transmit(CanPeliTxMsg* PeliTxMessage); +void CAN_Peli_TransmitRepeat(CanPeliTxMsg* PeliTxMessage); +void CAN_Peli_Receive(CanPeliRxMsg* PeliRxMessage); +uint32_t CAN_Peli_GetRxFIFOInfo(void); +uint8_t CAN_Peli_GetLastErrorCode(void); +uint8_t CAN_Peli_GetReceiveErrorCounter(void); +uint8_t CAN_Peli_GetLSBTransmitErrorCounter(void); +void CAN_Peli_ITConfig(uint32_t CAN_IT, FunctionalState NewState); +ITStatus CAN_Peli_GetITStatus(uint32_t CAN_IT); +void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef *CAN_Peli_InitStruct, unsigned int SrcClk, unsigned int baud ); +#endif /* __HAL_CAN_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ + diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_conf.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_conf.h new file mode 100644 index 0000000000..c3dad2ab07 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_conf.h @@ -0,0 +1,48 @@ +/** +****************************************************************************** +* @file HAL_conf.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains Header file for generic microcontroller. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ +#ifndef __HAL_CONF_H__ +#define __HAL_CONF_H__ + +/*´Ë´¦¿ÉÌí¼Ó»òɾ³ýÍâÉè*/ +#include "HAL_device.h" + + +#include "HAL_adc.h" +#include "HAL_bkp.h" +#include "HAL_can.h" +#include "HAL_crc.h" +#include "HAL_dma.h" +#include "HAL_exti.h" +#include "HAL_flash.h" +#include "HAL_gpio.h" +#include "HAL_i2c.h" +#include "HAL_iwdg.h" +#include "HAL_pwr.h" +#include "HAL_rcc.h" +#include "HAL_rtc.h" +#include "HAL_spi.h" +#include "HAL_tim.h" +#include "HAL_uart.h" +#include "HAL_wwdg.h" +#include "HAL_misc.h" + +#endif /* __HAL_CONF_H__ */ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_crc.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_crc.h new file mode 100644 index 0000000000..cf4c3f1ded --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_crc.h @@ -0,0 +1,85 @@ +/** +****************************************************************************** +* @file HAL_crc.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the CRC firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_CRC_H +#define __HAL_CRC_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup CRC +* @{ +*/ + +/** @defgroup CRC_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup CRC_Exported_Constants +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup CRC_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup CRC_Exported_Functions +* @{ +*/ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#endif /* __HAL_CRC_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_dma.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_dma.h new file mode 100644 index 0000000000..1ade62a3a6 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_dma.h @@ -0,0 +1,354 @@ +/** +****************************************************************************** +* @file HAL_dma.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the DMA firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_DMA_H +#define __HAL_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup DMA +* @{ +*/ + +/** @defgroup DMA_Exported_Types +* @{ +*/ + +/** +* @brief DMA Init structure definition +*/ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; + uint32_t DMA_MemoryBaseAddr; + uint32_t DMA_DIR; + uint32_t DMA_BufferSize; + uint32_t DMA_PeripheralInc; + uint32_t DMA_MemoryInc; + uint32_t DMA_PeripheralDataSize; + uint32_t DMA_MemoryDataSize; + uint32_t DMA_Mode; + uint32_t DMA_Priority; + uint32_t DMA_M2M; +} DMA_InitTypeDef; + +/** +* @} +*/ + +/** @defgroup DMA_Exported_Constants +* @{ +*/ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == DMA1_Channel1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel3_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel5_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel6_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel7_BASE)) + + +/** @defgroup DMA_data_transfer_direction +* @{ +*/ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) //mtop +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) //ptom +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** +* @} +*/ + +/** @defgroup DMA_peripheral_incremented_mode +* @{ +*/ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** +* @} +*/ + +/** @defgroup DMA_memory_incremented_mode +* @{ +*/ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** +* @} +*/ + +/** @defgroup DMA_peripheral_data_size +* @{ +*/ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** +* @} +*/ + +/** @defgroup DMA_memory_data_size +* @{ +*/ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** +* @} +*/ + +/** @defgroup DMA_circular_normal_mode +* @{ +*/ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** +* @} +*/ + +/** @defgroup DMA_priority_level +* @{ +*/ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** +* @} +*/ + +/** @defgroup DMA_memory_to_memory +* @{ +*/ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** +* @} +*/ + +/** @defgroup DMA_interrupts_definition +* @{ +*/ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +/** +* @brief For DMA1 +*/ + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + +/** +* @} +*/ + +/** @defgroup DMA_flags_definition +* @{ +*/ + +/** +* @brief For DMA1 +*/ + +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + + + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7)) + +/** +* @} +*/ + +/** @defgroup DMA_Buffer_Size +* @{ +*/ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Exported_Functions +* @{ +*/ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); +void DMA_ClearFlag(uint32_t DMA_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMA_IT); +void DMA_ClearITPendingBit(uint32_t DMA_IT); + +#endif /*__HAL_DMA_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*------------------ (C) COPYRIGHT 2019 MindMotion ------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_exti.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_exti.h new file mode 100644 index 0000000000..a41f0c7ebd --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_exti.h @@ -0,0 +1,170 @@ +/** +****************************************************************************** +* @file HAL_exti.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the EXTI +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_EXTI_H +#define __HAL_EXTI_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup EXTI +* @{ +*/ + +/** @defgroup EXTI_Exported_Types +* @{ +*/ + +/** +* @brief EXTI mode enumeration +*/ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** +* @brief EXTI Trigger enumeration +*/ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** +* @brief EXTI Init Structure definition +*/ + +typedef struct +{ + uint32_t EXTI_Line; + EXTIMode_TypeDef EXTI_Mode; + EXTITrigger_TypeDef EXTI_Trigger; + FunctionalState EXTI_LineCmd; +} EXTI_InitTypeDef; + +/** +* @} +*/ + +/** @defgroup EXTI_Exported_Constants +* @{ +*/ + +/** @defgroup EXTI_Lines +* @{ +*/ + +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 +Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 +Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 +Connected to the USB Wakeup from +suspend event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF80000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Exported_Functions +* @{ +*/ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#endif /* __HAL_EXTI_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_flash.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_flash.h new file mode 100644 index 0000000000..41beb6e836 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_flash.h @@ -0,0 +1,307 @@ +/** +****************************************************************************** +* @file HAL_flash.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the FLASH +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_FLASH_H +#define __HAL_FLASH_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup FLASH +* @{ +*/ + +/** @defgroup FLASH_Exported_Types +* @{ +*/ + +/** +* @brief FLASH Status +*/ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +} FLASH_Status; + +/** +* @} +*/ + +/** @defgroup FLASH_Exported_Constants +* @{ +*/ + +/** @defgroup Flash_Latency +* @{ +*/ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint32_t)0x00000003) /* FLASH Three Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3)) +/** +* @} +*/ + +/** @defgroup Half_Cycle_Enable_Disable +* @{ +*/ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** +* @} +*/ + +/** @defgroup Prefetch_Buffer_Enable_Disable +* @{ +*/ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** +* @} +*/ + +/** @defgroup Option_Bytes_Write_Protection +* @{ +*/ + +/* Values to be used with microcontroller Medium-density devices: FLASH memory density +ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */ + +/* Values to be used with microcontroller High-density devices: FLASH memory density +ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** +* @} +*/ + +/** @defgroup Option_Bytes_IWatchdog +* @{ +*/ + +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** +* @} +*/ + +/** @defgroup Option_Bytes_nRST_STOP +* @{ +*/ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** +* @} +*/ + +/** @defgroup Option_Bytes_nRST_STDBY +* @{ +*/ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/** +* @} +*/ + +/** @defgroup FLASH_Interrupts +* @{ +*/ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) + +/** +* @} +*/ + +/** @defgroup FLASH_Flags +* @{ +*/ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Exported_Functions +* @{ +*/ + +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG); +void FLASH_ClearFlag(uint16_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +#endif /* __HAL_FLASH_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_gpio.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_gpio.h new file mode 100644 index 0000000000..9fb49c48c6 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_gpio.h @@ -0,0 +1,325 @@ +/** +****************************************************************************** +* @file HAL_gpio.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the GPIO +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_GPIO_H +#define __HAL_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup GPIO +* @{ +*/ + +/** @defgroup GPIO_Exported_Types +* @{ +*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == GPIOA_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOB_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOC_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOD_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOE_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOF_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOG_BASE)) + +/** +* @brief Output Maximum frequency selection +*/ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/** +* @brief Configuration Mode enumeration +*/ + +typedef enum +{ + GPIO_Mode_AIN = 0x0, //ģ + GPIO_Mode_IN_FLOATING = 0x04, // + GPIO_Mode_IPD = 0x28, // + GPIO_Mode_IPU = 0x48, // + GPIO_Mode_Out_OD = 0x14,//ͨÿ© + GPIO_Mode_Out_PP = 0x10,//ͨ + GPIO_Mode_AF_OD = 0x1C, // ÿ© + GPIO_Mode_AF_PP = 0x18 // +} GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** +* @brief GPIO Init structure definition +*/ + +typedef struct +{ + uint16_t GPIO_Pin; + GPIOSpeed_TypeDef GPIO_Speed; + GPIOMode_TypeDef GPIO_Mode; +} GPIO_InitTypeDef; + +/** +* @brief Bit_SET and Bit_RESET enumeration +*/ + +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** +* @} +*/ + +/** @defgroup GPIO_Exported_Constants +* @{ +*/ + +/** @defgroup GPIO_pins_define +* @{ +*/ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** +* @} +*/ + +/** @defgroup GPIO_Remap_define +* @{ +*/ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_UART1 ((uint32_t)0x00000004) /* UART1 Alternate Function mapping */ +#define GPIO_Remap_UART2 ((uint32_t)0x00000008) /* UART2 Alternate Function mapping */ +#define GPIO_PartialRemap_UART3 ((uint32_t)0x00140010) /* UART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_UART3 ((uint32_t)0x00140030) /* UART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D0000) /* CAN Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_UART1) || ((REMAP) == GPIO_Remap_UART2) || \ + ((REMAP) == GPIO_PartialRemap_UART3) || ((REMAP) == GPIO_FullRemap_UART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \ + ((REMAP) == GPIO_Remap_SWJ_Disable)) + +/** +* @} +*/ + +/** @defgroup GPIO_Port_Sources +* @{ +*/ + +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/** +* @} +*/ + +/** @defgroup GPIO_Pin_sources +* @{ +*/ + +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Exported_Functions +* @{ +*/ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); + +#endif /* __HAL_GPIO_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_i2c.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_i2c.h new file mode 100644 index 0000000000..c6e5fe4fd0 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_i2c.h @@ -0,0 +1,333 @@ +/** +****************************************************************************** +* @file HAL_i2c.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the I2C firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_I2C_H +#define __HAL_I2C_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup I2C +* @{ +*/ + +/** @defgroup I2C_Exported_Types +* @{ +*/ + +/** +* @brief I2C Init structure definition +*/ +/* +typedef struct +{ +uint16_t I2C_Mode; +uint16_t I2C_DutyCycle; +uint16_t I2C_OwnAddress1; +uint16_t I2C_Ack; +uint16_t I2C_AcknowledgedAddress; +uint32_t I2C_ClockSpeed; +}I2C_InitTypeDef; +*/ +typedef struct +{ + uint16_t I2C_Mode; + uint16_t I2C_Speed; + uint16_t I2C_OwnAddress; + uint32_t I2C_ClockSpeed; +} I2C_InitTypeDef; + +/** +* @} +*/ + + +/** @defgroup I2C_Exported_Constants +* @{ +*/ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == I2C1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == I2C2_BASE)) +/** @defgroup I2C_modes +* @{ +*/ + +#define TX_EMPTY_CTRL (0x0001<<8) +#define IC_SLAVE_DISABLE (0x0001<<6) +#define IC_SLAVE_ENABLE (0x0000<<6) +#define IC_RESTART_EN (0x0001<<5) +#define IC_7BITADDR_MASTER (0x0000<<4) +#define IC_7BITADDR_SLAVE (0x0000<<3) + +#define I2C_Speed_STANDARD ((uint16_t)0x0002) +#define I2C_Speed_FAST ((uint16_t)0x0004) +#define I2C_Mode_MASTER ((uint16_t)0x0001) +#define I2C_Mode_SLAVE ((uint16_t)0x0000) + +#define TDMAE_SET ((uint16_t)0x0002) +#define RDMAE_SET ((uint16_t)0x0001) + +#define CMD_READ ((uint16_t)0x0100) +#define CMD_WRITE ((uint16_t)0x0000) + + + + +#define I2C_Mode_I2C ((uint16_t)0x0000) + +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C)) + +/** +* @} +*/ + + +/** @defgroup I2C_transfer_direction +* @{ +*/ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** +* @} +*/ + +/** @defgroup I2C_acknowledged_address_defines +* @{ +*/ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) + +/** +* @} +*/ + +/** @defgroup I2C_interrupts_definition +* @{ +*/ + + +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** +* @} +*/ + +/** @defgroup I2C_interrupts_definition +* @{ +*/ + +#define I2C_IT_RX_UNDER ((uint16_t)0x0001) +#define I2C_IT_RX_OVER ((uint16_t)0x0002) +#define I2C_IT_RX_FULL ((uint16_t)0x0004) +#define I2C_IT_TX_OVER ((uint16_t)0x0008) +#define I2C_IT_TX_EMPTY ((uint16_t)0x0010) +#define I2C_IT_RD_REQ ((uint16_t)0x0020) +#define I2C_IT_TX_ABRT ((uint16_t)0x0040) +#define I2C_IT_RX_DONE ((uint16_t)0x0080) +#define I2C_IT_ACTIVITY ((uint16_t)0x0100) +#define I2C_IT_STOP_DET ((uint16_t)0x0200) +#define I2C_IT_START_DET ((uint16_t)0x0400) +#define I2C_IT_GEN_CALL ((uint16_t)0x0800) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0xF000) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RX_UNDER) || ((IT) == I2C_IT_RX_OVER) || \ + ((IT) == I2C_IT_RX_FULL) || ((IT) == I2C_IT_TX_OVER) || \ + ((IT) == I2C_IT_TX_EMPTY) || ((IT) == I2C_IT_RD_REQ) || \ + ((IT) == I2C_IT_TX_ABRT) || ((IT) == I2C_IT_RX_DONE) || \ + ((IT) == I2C_IT_ACTIVITY) || ((IT) == I2C_IT_STOP_DET) || \ + ((IT) == I2C_IT_START_DET) || ((IT) == I2C_IT_GEN_CALL)) +/** +* @} +*/ + +/** @defgroup I2C_flags_definition +* @{ +*/ + + + +#define I2C_FLAG_RX_UNDER ((uint16_t)0x0001) +#define I2C_FLAG_RX_OVER ((uint16_t)0x0002) +#define I2C_FLAG_RX_FULL ((uint16_t)0x0004) +#define I2C_FLAG_TX_OVER ((uint16_t)0x0008) +#define I2C_FLAG_TX_EMPTY ((uint16_t)0x0010) +#define I2C_FLAG_RD_REQ ((uint16_t)0x0020) +#define I2C_FLAG_TX_ABRT ((uint16_t)0x0040) +#define I2C_FLAG_RX_DONE ((uint16_t)0x0080) +#define I2C_FLAG_ACTIVITY ((uint16_t)0x0100) +#define I2C_FLAG_STOP_DET ((uint16_t)0x0200) +#define I2C_FLAG_START_DET ((uint16_t)0x0400) +#define I2C_FLAG_GEN_CALL ((uint16_t)0x0800) + + + + + + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF000) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_RX_UNDER) || ((FLAG) == I2C_FLAG_RX_OVER) || \ + ((FLAG) == I2C_FLAG_RX_FULL) || ((FLAG) == I2C_FLAG_TX_OVER) || \ + ((FLAG) == I2C_FLAG_TX_EMPTY) || ((FLAG) == I2C_FLAG_RD_REQ) || \ + ((FLAG) == I2C_FLAG_TX_ABRT) || ((FLAG) == I2C_FLAG_RX_DONE) || \ + ((FLAG) == I2C_FLAG_ACTIVITY) || ((FLAG) == I2C_FLAG_STOP_DET) || \ + ((FLAG) == I2C_FLAG_START_DET) || ((FLAG) == I2C_FLAG_GEN_CALL)) + + +/** @defgroup I2C_Statusflags_definition +* @{ +*/ + +#define I2C_STATUS_FLAG_ACTIVITY ((uint16_t)0x8001) +#define I2C_STATUS_FLAG_TFNF ((uint16_t)0x8002) +#define I2C_STATUS_FLAG_TFE ((uint16_t)0x8004) +#define I2C_STATUS_FLAG_RFNE ((uint16_t)0x8008) +#define I2C_STATUS_FLAG_RFF ((uint16_t)0x8010) +#define I2C_STATUS_FLAG_M_ACTIVITY ((uint16_t)0x8020) +#define I2C_STATUS_FLAG_S_ACTIVITY ((uint16_t)0x8040) + + +/** +* @} +*/ + +/** @defgroup I2C_Events +* @{ +*/ + + +#define I2C_EVENT_RX_UNDER ((uint32_t)0x0001) +#define I2C_EVENT_RX_OVER ((uint32_t)0x0002) +#define I2C_EVENT_RX_FULL ((uint32_t)0x0004) +#define I2C_EVENT_TX_OVER ((uint32_t)0x0008) +#define I2C_EVENT_TX_EMPTY ((uint32_t)0x0010) +#define I2C_EVENT_RD_REQ ((uint32_t)0x0020) +#define I2C_EVENT_TX_ABRT ((uint32_t)0x0040) +#define I2C_EVENT_RX_DONE ((uint32_t)0x0080) +#define I2C_EVENT_ACTIVITY ((uint32_t)0x0100) +#define I2C_EVENT_STOP_DET ((uint32_t)0x0200) +#define I2C_EVENT_START_DET ((uint32_t)0x0400) +#define I2C_EVENT_GEN_CALL ((uint32_t)0x0800) + + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_RX_UNDER) || \ + ((EVENT) == I2C_EVENT_RX_OVER) || \ + ((EVENT) == I2C_EVENT_RX_FULL) || \ + ((EVENT) == I2C_EVENT_TX_OVER) || \ + ((EVENT) == I2C_EVENT_RD_REQ) || \ + ((EVENT) == I2C_EVENT_TX_ABRT) || \ + ((EVENT) == I2C_EVENT_RX_DONE) || \ + ((EVENT) == (I2C_EVENT_ACTIVITY | I2C_EVENT_STOP_DET)) || \ + ((EVENT) == (I2C_EVENT_START_DET | I2C_EVENT_GEN_CALL))) + +/** +* @} +*/ + +/** @defgroup I2C_own_address1 +* @{ +*/ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** +* @} +*/ + +/** @defgroup I2C_clock_speed +* @{ +*/ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Exported_Functions +* @{ +*/ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); + +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +void I2C_SendLastDataOrStop(I2C_TypeDef* I2Cx, uint8_t Data); +void I2C_ReadCmd(I2C_TypeDef* I2Cx); +uint8_t I2C_ReadLastDataOrStop(I2C_TypeDef* I2Cx); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); + +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + + + +#endif /*__HAL_I2C_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_iwdg.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_iwdg.h new file mode 100644 index 0000000000..1490ddbcc7 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_iwdg.h @@ -0,0 +1,131 @@ +/** +****************************************************************************** +* @file HAL_iwdg.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the IWDG +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_IWDG_H +#define __HAL_IWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup IWDG +* @{ +*/ + +/** @defgroup IWDG_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Exported_Constants +* @{ +*/ + +/** @defgroup Write_access_to_IWDG_PR_and_IWDG_RLR_registers +* @{ +*/ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** +* @} +*/ + +/** @defgroup IWDG_prescaler +* @{ +*/ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** +* @} +*/ + +/** @defgroup IWDG_Flag +* @{ +*/ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Exported_Functions +* @{ +*/ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#endif /* __HAL_IWDG_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_misc.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_misc.h new file mode 100644 index 0000000000..4146d6c554 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_misc.h @@ -0,0 +1,166 @@ +/** +****************************************************************************** +* @file HAL_misc.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the +* miscellaneous firmware library functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup MISC +* @{ +*/ + +/** @defgroup MISC_Exported_Types +* @{ +*/ + +/** +* @brief NVIC Init Structure definition +*/ + +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/** +* @} +*/ + +/** @defgroup MISC_Exported_Constants +* @{ +*/ + +/** @defgroup Vector_Table_Base +* @{ +*/ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** +* @} +*/ + +/** @defgroup System_Low_Power +* @{ +*/ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** +* @} +*/ + +/** @defgroup Preemption_Priority_Group +* @{ +*/ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /* 0 bits for pre-emption priority +4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /* 1 bits for pre-emption priority +3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /* 2 bits for pre-emption priority +2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /* 3 bits for pre-emption priority +1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /* 4 bits for pre-emption priority +0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) + +/** +* @} +*/ + +/** @defgroup SysTick_clock_source +* @{ +*/ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Exported_Functions +* @{ +*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#endif /* __MISC_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_pwr.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_pwr.h new file mode 100644 index 0000000000..5ae14c71e9 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_pwr.h @@ -0,0 +1,155 @@ +/** +****************************************************************************** +* @file HAL_pwr.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the PWR firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_PWR_H +#define __HAL_PWR_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup PWR +* @{ +*/ + +/** @defgroup PWR_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Exported_Constants +* @{ +*/ + + +/** @defgroup PVD_detection_level +* @{ +*/ + +#define PWR_PVDLevel_1V8 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V1 ((uint32_t)0x00000200) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000400) +#define PWR_PVDLevel_2V7 ((uint32_t)0x00000600) +#define PWR_PVDLevel_3V0 ((uint32_t)0x00000800) +#define PWR_PVDLevel_3V3 ((uint32_t)0x00000A00) +#define PWR_PVDLevel_3V6 ((uint32_t)0x00000C00) +#define PWR_PVDLevel_3V9 ((uint32_t)0x00000E00) +#define PWR_PVDLevel_4V2 ((uint32_t)0x00001000) +#define PWR_PVDLevel_4V5 ((uint32_t)0x00001200) +#define PWR_PVDLevel_4V8 ((uint32_t)0x00001400) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_1V8) || ((LEVEL) == PWR_PVDLevel_2V1)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_3V0) || ((LEVEL) == PWR_PVDLevel_3V3)|| \ + ((LEVEL) == PWR_PVDLevel_3V6) || ((LEVEL) == PWR_PVDLevel_3V9)|| \ + ((LEVEL) == PWR_PVDLevel_4V2) || ((LEVEL) == PWR_PVDLevel_4V5)|| \ + ((LEVEL) == PWR_PVDLevel_4V8)) + + +/** +* @} +*/ + +/** @defgroup Regulator_state_is_STOP_mode +* @{ +*/ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000002) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** +* @} +*/ + +/** @defgroup STOP_mode_entry +* @{ +*/ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** +* @} +*/ + +/** @defgroup PWR_Flag +* @{ +*/ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Exported_Functions +* @{ +*/ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#endif /* __HAL_PWR_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_rcc.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_rcc.h new file mode 100644 index 0000000000..5d99b6428e --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_rcc.h @@ -0,0 +1,425 @@ +/** +****************************************************************************** +* @file HAL_rcc.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the RCC firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_RCC_H +#define __HAL_RCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup RCC +* @{ +*/ + +/** @defgroup RCC_Exported_Types +* @{ +*/ + +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK1_Frequency; + uint32_t PCLK2_Frequency; + uint32_t ADCCLK_Frequency; +} RCC_ClocksTypeDef; + +/** +* @} +*/ + +/** @defgroup RCC_Exported_Constants +* @{ +*/ + +/** @defgroup HSE_configuration +* @{ +*/ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** +* @} +*/ + +/** @defgroup PLL_entry_clock_source +* @{ +*/ + +#define RCC_PLLSource_HSI_Div4 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +/** +* @} +*/ + + +/** @defgroup System_clock_source +* @{ +*/ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** +* @} +*/ + +/** @defgroup AHB_clock_source +* @{ +*/ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** +* @} +*/ + +/** @defgroup APB1_APB2_clock_source +* @{ +*/ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) + +/** +* @} +*/ + +/** @defgroup PLL_multiplication_factor +* @{ +*/ + +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + + +/** +* @} +*/ + +/** @defgroup RCC_Interrupt_source +* @{ +*/ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +/** +* @} +*/ + +/** @defgroup USB_clock_source +* @{ +*/ + + +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x00) +#define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01) +#define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02) +#define RCC_USBCLKSource_PLLCLK_Div4 ((uint8_t)0x03) +#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2)) +/** +* @} +*/ + +/** @defgroup ADC_clock_source +* @{ +*/ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** +* @} +*/ + +/** @defgroup LSE_configuration +* @{ +*/ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** +* @} +*/ + +/** @defgroup RTC_clock_source +* @{ +*/ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** +* @} +*/ + +/** @defgroup AHB_peripheral +* @{ +*/ + +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +//#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +/** +* @} +*/ + +/** @defgroup APB2_peripheral +* @{ +*/ + +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) + +#define RCC_APB2Periph_UART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ALL ((uint32_t)0x0003FFFD) +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFC0002) == 0x00) && ((PERIPH) != 0x00)) +/** +* @} +*/ + +/** @defgroup APB1_peripheral +* @{ +*/ + +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) + +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) + +#define RCC_APB1Periph_UART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_UART3 ((uint32_t)0x00040000) + +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_ALL ((uint32_t)0x3AFEC83F) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) +/** +* @} +*/ + +/** @defgroup Clock_source_to_output_on_MCO_pin +* @{ +*/ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) +#define RCC_MCO_LSI ((uint8_t)0x02) +#define RCC_MCO_LSE ((uint8_t)0x03) +#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)||((MCO) == RCC_MCO_LSI)||\ + ((MCO) == RCC_MCO_LSE)) +/** +* @} +*/ + +/** @defgroup RCC_Flag +* @{ +*/ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Exported_Functions +* @{ +*/ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#endif /* __HAL_RCC_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_rtc.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_rtc.h new file mode 100644 index 0000000000..a1d3f37ecb --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_rtc.h @@ -0,0 +1,135 @@ +/** +****************************************************************************** +* @file HAL_rtc.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the RTC firmware +* library. +****************************************************************************** +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+****************************************************************************** +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_RTC_H +#define __HAL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup +* @{ +*/ + +/** @addtogroup RTC +* @{ +*/ + +/** @defgroup RTC_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RTC_Exported_Constants +* @{ +*/ + +/** @defgroup RTC_interrupts_define +* @{ +*/ + +#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ +#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) +/** +* @} +*/ + +/** @defgroup RTC_interrupts_flags +* @{ +*/ + +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup RTC_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RTC_Exported_Functions +* @{ +*/ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __HAL_RTC_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_spi.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_spi.h new file mode 100644 index 0000000000..8e732b3828 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_spi.h @@ -0,0 +1,418 @@ +/** +****************************************************************************** +* @file HAL_spi.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the SPI firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_SPI_H +#define __HAL_SPI_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup SPI +* @{ +*/ + +/** @defgroup SPI_Exported_Types +* @{ +*/ + +/** +* @brief SPI Init structure definition +*/ + +typedef struct +{ + uint16_t SPI_Mode; + uint16_t SPI_DataSize; + uint16_t SPI_DataWidth; + uint16_t SPI_CPOL; + uint16_t SPI_CPHA; + uint16_t SPI_NSS; + uint16_t SPI_BaudRatePrescaler; + uint16_t SPI_FirstBit; +} SPI_InitTypeDef; + + +/** +* @} +*/ + +/** @defgroup SPI_Exported_Constants +* @{ +*/ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI0_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == SPI1_BASE)) + +#define IS_SPI_2_PERIPH(PERIPH) ((*(uint32_t*)&(PERIPH)) == SPI1_BASE) + + +/** +* @} +*/ + +/** @defgroup SPI_master_slave_mode +* @{ +*/ + +#define SPI_Mode_Master ((uint16_t)0x0004) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** +* @} +*/ + +/** @defgroup SPI_data_size +* @{ +*/ + +#define SPI_DataSize_32b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_32b) || \ + ((DATASIZE) == SPI_DataSize_8b)) + +/** +* @} +*/ + + +/** @defgroup SPI_7bit_8bit data width +* @{ +*/ + +#define SPI_DataWidth_1b ((uint16_t)0x0001) +#define SPI_DataWidth_2b ((uint16_t)0x0002) +#define SPI_DataWidth_3b ((uint16_t)0x0003) +#define SPI_DataWidth_4b ((uint16_t)0x0004) +#define SPI_DataWidth_5b ((uint16_t)0x0005) +#define SPI_DataWidth_6b ((uint16_t)0x0006) +#define SPI_DataWidth_7b ((uint16_t)0x0007) +#define SPI_DataWidth_8b ((uint16_t)0x0008) +#define SPI_DataWidth_9b ((uint16_t)0x0009) +#define SPI_DataWidth_10b ((uint16_t)0x000a) +#define SPI_DataWidth_11b ((uint16_t)0x000b) +#define SPI_DataWidth_12b ((uint16_t)0x000c) +#define SPI_DataWidth_13b ((uint16_t)0x000d) +#define SPI_DataWidth_14b ((uint16_t)0x000e) +#define SPI_DataWidth_15b ((uint16_t)0x000f) +#define SPI_DataWidth_16b ((uint16_t)0x0010) +#define SPI_DataWidth_17b ((uint16_t)0x0011) +#define SPI_DataWidth_18b ((uint16_t)0x0012) +#define SPI_DataWidth_19b ((uint16_t)0x0013) +#define SPI_DataWidth_20b ((uint16_t)0x0014) +#define SPI_DataWidth_21b ((uint16_t)0x0015) +#define SPI_DataWidth_22b ((uint16_t)0x0016) +#define SPI_DataWidth_23b ((uint16_t)0x0017) +#define SPI_DataWidth_24b ((uint16_t)0x0018) +#define SPI_DataWidth_25b ((uint16_t)0x0019) +#define SPI_DataWidth_26b ((uint16_t)0x001a) +#define SPI_DataWidth_27b ((uint16_t)0x001b) +#define SPI_DataWidth_28b ((uint16_t)0x001c) +#define SPI_DataWidth_29b ((uint16_t)0x001d) +#define SPI_DataWidth_30b ((uint16_t)0x001e) +#define SPI_DataWidth_31b ((uint16_t)0x001f) +#define SPI_DataWidth_32b ((uint16_t)0x0000) +#define IS_SPI_DATAWIDRH(WIDTH) (((WIDTH) == SPI_DataWidth_1b) || ((WIDTH) == SPI_DataWidth_2b)||\ + ((WIDTH) == SPI_DataWidth_3b)||((WIDTH) == SPI_DataWidth_4b)||\ + ((WIDTH) == SPI_DataWidth_5b)||((WIDTH) == SPI_DataWidth_6b)||\ + ((WIDTH) == SPI_DataWidth_7b)||((WIDTH) == SPI_DataWidth_8b)||\ + ((WIDTH) == SPI_DataWidth_9b)||((WIDTH) == SPI_DataWidth_10b)||\ + ((WIDTH) == SPI_DataWidth_11b)||((WIDTH) == SPI_DataWidth_12b)||\ + ((WIDTH) == SPI_DataWidth_13b)||((WIDTH) == SPI_DataWidth_14b)||\ + ((WIDTH) == SPI_DataWidth_15b)||((WIDTH) == SPI_DataWidth_16b)||\ + ((WIDTH) == SPI_DataWidth_17b)||((WIDTH) == SPI_DataWidth_18b)||\ + ((WIDTH) == SPI_DataWidth_19b)||((WIDTH) == SPI_DataWidth_20b)||\ + ((WIDTH) == SPI_DataWidth_21b)||((WIDTH) == SPI_DataWidth_22b)||\ + ((WIDTH) == SPI_DataWidth_23b)||((WIDTH) == SPI_DataWidth_24b)||\ + ((WIDTH) == SPI_DataWidth_25b)||((WIDTH) == SPI_DataWidth_26b)||\ + ((WIDTH) == SPI_DataWidth_27b)||((WIDTH) == SPI_DataWidth_28b)||\ + ((WIDTH) == SPI_DataWidth_29b)||((WIDTH) == SPI_DataWidth_30b)||\ + ((WIDTH) == SPI_DataWidth_31b)||((WIDTH) == SPI_DataWidth_32b)||) +/** +* @} +*/ + + +/** @defgroup SPI_Clock_Polarity +* @{ +*/ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** +* @} +*/ + +/** @defgroup SPI_Clock_Phase +* @{ +*/ + +#define SPI_CPHA_1Edge ((uint16_t)0x0001) +#define SPI_CPHA_2Edge ((uint16_t)0x0000) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** +* @} +*/ + +/** @defgroup SPI_Slave_Select_management +* @{ +*/ + +#define SPI_NSS_Soft ((uint16_t)0x0000) +#define SPI_NSS_Hard ((uint16_t)0x0400) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) + + +/** +* @} +*/ + +/** @defgroup SPI_NSS_internal_software_mangement +* @{ +*/ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0001) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFFFE) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup SPI_BaudRate_Prescaler_ +* @{ +*/ + + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0002) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0004) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0040) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0080) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0100) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** +* @} +*/ + +/** @defgroup SPI_MSB_LSB_transmission +* @{ +*/ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0004) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) + + +/** +* @} +*/ + +/** @defgroup SPI_DMA_transfer_requests +* @{ +*/ + +#define SPI_DMAReq_EN ((uint16_t)0x0200) +#define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ) == SPI_DMAReq_EN) + + +/** +* @} +*/ + +/** @defgroup SPI TX Fifo and RX Fifo trigger level +* @{ +*/ +#define SPI_TXTLF ((uint16_t)0x0080) +#define SPI_RXTLF ((uint16_t)0x0020) +#define IS_SPI_FIFOTRIGGER(TRIGGER) (((TRIGGER) == SPI_TXTLF) && ((TRIGGER) == SPI_RXTLF)) + + + + + + + +/** +* @} +*/ + +/** @defgroup SPI_NSS_internal_software_mangement +* @{ +*/ + +#define SPI_CS_BIT0 ((uint16_t)0xfffe) +#define SPI_CS_BIT1 ((uint16_t)0xfffd) +#define SPI_CS_BIT2 ((uint16_t)0xfffb) +#define SPI_CS_BIT3 ((uint16_t)0xfff7) +#define SPI_CS_BIT4 ((uint16_t)0xffef) +#define SPI_CS_BIT5 ((uint16_t)0xffdf) +#define SPI_CS_BIT6 ((uint16_t)0xffbf) +#define SPI_CS_BIT7 ((uint16_t)0xff7f) +#define IS_SPI_CS(CS) (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\ + ((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\ + ((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\ + ((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7)) +/** +* @} +*/ + + +/** @defgroup SPI_direction_transmit_receive +* @{ +*/ + +#define SPI_Direction_Rx ((uint16_t)0x0010) +#define SPI_Direction_Tx ((uint16_t)0x0008) +#define SPI_Disable_Tx ((uint16_t)0xfff7) +#define SPI_Disable_Rx ((uint16_t)0xffef) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx) || \ + ((DIRECTION) == SPI_Disable_Tx) || \ + ((DIRECTION) == SPI_Disable_Rx)) +/** +* @} +*/ + +/** @defgroup SPI_interrupts_definition +* @{ +*/ +#define SPI_INT_EN ((uint16_t)0x0002) + +#define SPI_IT_TX ((uint8_t)0x01) +#define SPI_IT_RX ((uint8_t)0x02) + +#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_IT_TX) || \ + ((IT) == SPI_IT_RX)) + +#define SPI_IT_UNDERRUN ((uint8_t)0x04) +#define SPI_IT_RXOVER ((uint8_t)0x08) +#define SPI_IT_RXMATCH ((uint8_t)0x10) +#define SPI_IT_RXFULL ((uint8_t)0x20) +#define SPI_IT_TXEPT ((uint8_t)0x40) + +#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TX) || ((IT) == SPI_IT_RX) || \ + ((IT) == SPI_IT_UNDERRUN) || ((IT) == SPI_IT_RXOVER) || \ + ((IT) == SPI_IT_RXMATCH) || ((IT) == SPI_IT_RXFULL) || \ + ((IT) == SPI_IT_TXEPT)) +/** +* @} +*/ + +/** @defgroup SPI_flags_definition +* @{ +*/ + + +#define SPI_FLAG_RXAVL ((uint16_t)0x0002) +#define SPI_FLAG_TXEPT ((uint16_t)0x0001) + +#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_RXAVL) || \ + ((FLAG) == SPI_FLAG_TXEPT)) + +/** +* @} +*/ + +/** @defgroup SPI mode tx data transmit phase adjust set +*in slave mode according to txedge bit of CCTL register +* @{ +*/ + + +#define SPI_SlaveAdjust_FAST ((uint16_t)0x0020) +#define SPI_SlaveAdjust_LOW ((uint16_t)0xffdf) + +#define IS_SPI_SlaveAdjust(ADJUST) (((ADJUST) == SPI_SlaveAdjust_FAST) || \ + ((ADJUST) == SPI_SlaveAdjust_LOW)) + + +/** +* @} +*/ + +/** @defgroup SPI_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Exported_Functions +* @{ +*/ + +void SPI_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState); +void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState); +void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState); +void SPI_SendData(SPI_TypeDef* SPIx, uint32_t Data); +uint32_t SPI_ReceiveData(SPI_TypeDef* SPIx); +void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected, FunctionalState NewState); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT); +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT); +void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number); +void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue); +#endif /*__HAL_SPI_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_tim.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_tim.h new file mode 100644 index 0000000000..8bb746729a --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_tim.h @@ -0,0 +1,1036 @@ +/** +****************************************************************************** +* @file HAL_tim.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the TIM firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_TIM_H +#define __HAL_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup TIM +* @{ +*/ + +/** @defgroup TIM_Exported_Types +* @{ +*/ + +/** +* @brief TIM Time Base Init structure definition +*/ + +typedef struct +{ + uint16_t TIM_Prescaler; + uint16_t TIM_CounterMode; + uint16_t TIM_Period; + uint16_t TIM_ClockDivision; + uint8_t TIM_RepetitionCounter; +} TIM_TimeBaseInitTypeDef; + +/** +* @brief TIM Output Compare Init structure definition +*/ + +typedef struct +{ + uint16_t TIM_OCMode; + uint16_t TIM_OutputState; + uint16_t TIM_OutputNState; + uint16_t TIM_Pulse; + uint16_t TIM_OCPolarity; + uint16_t TIM_OCNPolarity; + uint16_t TIM_OCIdleState; + uint16_t TIM_OCNIdleState; +} TIM_OCInitTypeDef; + +/** +* @brief TIM Input Capture Init structure definition +*/ + +typedef struct +{ + uint16_t TIM_Channel; + uint16_t TIM_ICPolarity; + uint16_t TIM_ICSelection; + uint16_t TIM_ICPrescaler; + uint16_t TIM_ICFilter; +} TIM_ICInitTypeDef; + +/** +* @brief BDTR structure definition +*/ + +typedef struct +{ + uint16_t TIM_OSSRState; + uint16_t TIM_OSSIState; + uint16_t TIM_LOCKLevel; + uint16_t TIM_DeadTime; + uint16_t TIM_Break; + uint16_t TIM_BreakPolarity; + uint16_t TIM_AutomaticOutput; +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants +* @{ +*/ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) + +#define IS_TIM_18_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE)) +#define IS_TIM_123458_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) + +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_and_PWM_modes +* @{ +*/ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** +* @} +*/ + +/** @defgroup TIM_One_Pulse_Mode +* @{ +*/ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** +* @} +*/ + +/** @defgroup TIM_Channel +* @{ +*/ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** +* @} +*/ + +/** @defgroup TIM_Clock_Division_CKD +* @{ +*/ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** +* @} +*/ + +/** @defgroup TIM_Counter_Mode +* @{ +*/ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_Polarity +* @{ +*/ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_N_Polarity +* @{ +*/ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_states +* @{ +*/ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_N_States +* @{ +*/ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** +* @} +*/ + +/** @defgroup TIM_Capture_Compare_States +* @{ +*/ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Capture_Compare_N_States +* @{ +*/ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** +* @} +*/ + +/** @defgroup Break_Input_enable_disable +* @{ +*/ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** +* @} +*/ + +/** @defgroup Break_Polarity +* @{ +*/ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** +* @} +*/ + +/** @defgroup TIM_AOE_Bit_Set_Reset +* @{ +*/ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** +* @} +*/ + +/** @defgroup Lock_levels +* @{ +*/ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** +* @} +*/ + +/** @defgroup OSSI:_Off-State_Selection_for_Idle_mode_states +* @{ +*/ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** +* @} +*/ + +/** @defgroup OSSR:_Off-State_Selection_for_Run_mode_states +* @{ +*/ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_Idle_State +* @{ +*/ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_N_Idle_State +* @{ +*/ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** +* @} +*/ + +/** @defgroup TIM_Input_Capture_Polarity +* @{ +*/ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) +/** +* @} +*/ + +/** @defgroup TIM_Input_Capture_Selection +* @{ +*/ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) +#define TIM_ICSelection_TRC ((uint16_t)0x0003) +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** +* @} +*/ + +/** @defgroup TIM_Input_Capture_Prescaler +* @{ +*/ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** +* @} +*/ + +/** @defgroup TIM_interrupt_sources +* @{ +*/ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) +#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \ + (((TIM_IT) & (uint16_t)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\ + (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \ + (((TIM_IT) & (uint16_t)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\ + (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \ + (((TIM_IT) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000))) +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** +* @} +*/ + +/** @defgroup TIM_DMA_Base_address +* @{ +*/ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) +/** +* @} +*/ + +/** @defgroup TIM_DMA_Burst_Length +* @{ +*/ + +#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ + ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_18Bytes)) +/** +* @} +*/ + +/** @defgroup TIM_DMA_sources +* @{ +*/ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) +#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \ + (((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\ + (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \ + (((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\ + (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \ + (((SOURCE) & (uint16_t)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000))) +/** +* @} +*/ + +/** @defgroup TIM_External_Trigger_Prescaler +* @{ +*/ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** +* @} +*/ + +/** @defgroup TIM_Internal_Trigger_Selection +* @{ +*/ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** +* @} +*/ + +/** @defgroup TIM_TIx_External_Clock_Source +* @{ +*/ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) +/** +* @} +*/ + +/** @defgroup TIM_External_Trigger_Polarity +* @{ +*/ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** +* @} +*/ + +/** @defgroup TIM_Prescaler_Reload_Mode +* @{ +*/ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** +* @} +*/ + +/** @defgroup TIM_Forced_Action +* @{ +*/ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** +* @} +*/ + +/** @defgroup TIM_Encoder_Mode +* @{ +*/ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** +* @} +*/ + + +/** @defgroup TIM_Event_Source +* @{ +*/ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) +#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \ + (((EVENT) & (uint16_t)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\ + (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \ + (((EVENT) & (uint16_t)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\ + (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \ + (((EVENT) & (uint16_t)0xFFFE) == 0x0000) && ((EVENT) != 0x0000))) +/** +* @} +*/ + +/** @defgroup TIM_Update_Source +* @{ +*/ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** +* @} +*/ + +/** @defgroup TIM_Ouput_Compare_Preload_State +* @{ +*/ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Ouput_Compare_Fast_State +* @{ +*/ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** +* @} +*/ + +/** @defgroup TIM_Ouput_Compare_Clear_State +* @{ +*/ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Trigger_Output_Source +* @{ +*/ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_Reset)) ||\ + ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_Enable)) ||\ + ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_Update)) ||\ + ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC1)) ||\ + ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\ + ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\ + ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\ + ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ + (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ + ((TRGO) == TIM_TRGOSource_OC4Ref))) +/** +* @} +*/ + +/** @defgroup TIM_Slave_Mode +* @{ +*/ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** +* @} +*/ + +/** @defgroup TIM_Master_Slave_Mode +* @{ +*/ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Flags +* @{ +*/ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) +#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\ + (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \ + (((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\ + (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \ + (((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\ + (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \ + (((TIM_FLAG) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000))) +#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) ||\ + ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || \ + ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) &&\ + (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\ + ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \ + ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\ + ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) ||\ + ((*(uint32_t*)&(PERIPH))==TIM1_BASE)|| ((*(uint32_t*)&(PERIPH))==TIM8_BASE) || \ + ((*(uint32_t*)&(PERIPH))==TIM7_BASE) || ((*(uint32_t*)&(PERIPH))==TIM6_BASE)) && \ + (((TIM_FLAG) == TIM_FLAG_Update))) ||\ + ((((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM8_BASE)) &&\ + (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\ + ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || \ + ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) &&\ + (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\ + ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF)))) + +/** +* @} +*/ + +/** @defgroup TIM_Input_Capture_Filer_Value +* @{ +*/ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** +* @} +*/ + +/** @defgroup TIM_External_Trigger_Filter +* @{ +*/ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup TIM_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup TIM_Exported_Functions +* @{ +*/ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#endif /*__HAL_TIM_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ + diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_uart.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_uart.h new file mode 100644 index 0000000000..2a34454f15 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_uart.h @@ -0,0 +1,247 @@ +/** +****************************************************************************** +* @file HAL_uart.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the UART +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_UART_H +#define __HAL_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup UART +* @{ +*/ + +/** @defgroup UART_Exported_Types +* @{ +*/ + +/** +* @brief UART Init Structure definition +*/ + +typedef struct +{ + uint32_t UART_BaudRate; + uint16_t UART_WordLength; + uint16_t UART_StopBits; + uint16_t UART_Parity; + uint16_t UART_Mode; + uint16_t UART_HardwareFlowControl; +} UART_InitTypeDef; + + +/** +* @} +*/ + +/** @defgroup UART_Exported_Constants +* @{ +*/ + +#define IS_UART_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == UART3_BASE)) +#define IS_UART_123_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == UART3_BASE)) + +/** @defgroup UART_Word_Length +* @{ +*/ + +#define UART_WordLength_5b ((uint16_t)0x0000) +#define UART_WordLength_6b ((uint16_t)0x0010) +#define UART_WordLength_7b ((uint16_t)0x0020) +#define UART_WordLength_8b ((uint16_t)0x0030) + + +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_5b) || \ + ((LENGTH) == UART_WordLength_6b) || \ + ((LENGTH) == UART_WordLength_7b) || \ + ((LENGTH) == UART_WordLength_8b)) +/** +* @} +*/ + +/** @defgroup UART_Stop_Bits +* @{ +*/ + +#define UART_StopBits_1 ((uint16_t)0x0000) +#define UART_StopBits_2 ((uint16_t)0x0004) + +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \ + ((STOPBITS) == UART_StopBits_2)) + +/** +* @} +*/ + +/** @defgroup UART_Parity +* @{ +*/ + +#define UART_Parity_No ((uint16_t)0x0000) +#define UART_Parity_Even ((uint16_t)0x0003) +#define UART_Parity_Odd ((uint16_t)0x0001) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \ + ((PARITY) == UART_Parity_Even) || \ + ((PARITY) == UART_Parity_Odd)) +/** +* @} +*/ + +/** @defgroup UART_Mode +* @{ +*/ + +#define UART_Mode_Rx ((uint16_t)0x0008) +#define UART_Mode_Tx ((uint16_t)0x0010) +#define IS_UART_MODE(MODE) ((((MODE) & (uint16_t)0xFFE7) == 0x00) && ((MODE) != (uint16_t)0x00)) + +#define UART_EN ((uint16_t)0x0001) + +/** +* @} +*/ + +/** @defgroup UART_Hardware_Flow_Control +* @{ +*/ +#define UART_HardwareFlowControl_None ((uint16_t)0x0000) + +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HardwareFlowControl_None) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS) || \ + ((CONTROL) == UART_HardwareFlowControl_CTS) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS_CTS)) + +/** @defgroup UART_Interrupt_definition +* @{ +*/ + + +#define UART_IT_ERR ((uint16_t)0x0020) +#define UART_IT_PE ((uint16_t)0x0010) +#define UART_OVER_ERR ((uint16_t)0x0008) +#define UART_TIMEOUT_ERR ((uint16_t)0x0004) +#define UART_IT_RXIEN ((uint16_t)0x0002) +#define UART_IT_TXIEN ((uint16_t)0x0001) + +#define IS_UART_CONFIG_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_TXIEN) || \ + ((IT) == UART_IT_RXIEN) || ((IT) == UART_IT_ERR)) + +#define IS_UART_GET_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_TXIEN) || \ + ((IT) == UART_IT_ERR) || ((IT) == UART_IT_RXIEN) || \ + ((IT) == UART_OVER_ERR) || ((IT) == UART_TIMEOUT_ERR)) + +#define IS_UART_CLEAR_IT(IT) ((IT) == UART_IT_RXIEN) + + +/** +* @} +*/ + +/** @defgroup UART_DMA_Requests +* @{ +*/ +#define UART_DMAReq_EN ((uint16_t)0x0002) + +#define IS_UART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFD) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** +* @} +*/ + + +/** @defgroup UART_Flags +* @{ +*/ + + +#define UART_FLAG_TXEMPTY ((uint16_t)0x0008) +#define UART_FLAG_TXFULL ((uint16_t)0x0004) +#define UART_FLAG_RXAVL ((uint16_t)0x0002) +#define UART_FLAG_TXEPT ((uint16_t)0x0001) + + +#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_TXEMPTY) || ((FLAG) == UART_FLAG_TXFULL) || \ + ((FLAG) == UART_FLAG_RXAVL) || ((FLAG) == UART_FLAG_TXEPT)) + + +#define IS_UART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x00FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_UART_DATA(DATA) ((DATA) <= 0x1FF) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup UART_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Exported_Functions +* @{ +*/ + +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState); +void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState); +void UART_SendData(UART_TypeDef* UARTx, uint16_t Data); +uint16_t UART_ReceiveData(UART_TypeDef* UARTx); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT); + +#endif /* __HAL_UART_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_wwdg.h b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_wwdg.h new file mode 100644 index 0000000000..19fa1de1b5 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_wwdg.h @@ -0,0 +1,106 @@ +/** +****************************************************************************** +* @file HAL_wwdg.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the functions prototypes for the WWDG +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_WWDG_H +#define __HAL_WWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup WWDG +* @{ +*/ + +/** @defgroup WWDG_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Exported_Constants +* @{ +*/ + +/** @defgroup WWDG_Prescaler +* @{ +*/ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Exported_Macros +* @{ +*/ +/** +* @} +*/ + +/** @defgroup WWDG_Exported_Functions +* @{ +*/ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#endif /* __HAL_WWDG_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_adc.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_adc.c new file mode 100644 index 0000000000..2d823182bd --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_adc.c @@ -0,0 +1,785 @@ +/** +****************************************************************************** +* @file HAL_adc.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the ADC firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_adc.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup ADC +* @brief ADC driver modules +* @{ +*/ + +/** @defgroup ADC_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Private_Defines +* @{ +*/ + + +/* ADCR register Mask */ +#define ADCR_CLEAR_Mask ((uint32_t)0xFFFFF183) + +/* ADCFG register Mask */ +#define ADCFG_CLEAR_Mask ((uint32_t)0xFFFFFF8F) + +/* ADC ADEN mask */ +#define ADCFG_ADEN_Set ((uint32_t)0x00000001) +#define ADCFG_ADEN_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define ADCR_DMA_Set ((uint32_t)0x00000008) +#define ADCR_DMA_Reset ((uint32_t)0xFFFFFFF7) + +/* ADC Software start mask */ +#define ADCR_SWSTART_Set ((uint32_t)0x00000100) +#define ADCR_SWSTART_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC EXTTRIG mask */ +#define ADCR_EXTTRIG_Set ((uint32_t)0x00000004) +#define ADCR_EXTTRIG_Reset ((uint32_t)0xFFFFFFFB) + +/*seletec channle enable */ +#define CHEN0_ENABLE ((uint32_t)0x00000001) +#define CHEN1_ENABLE ((uint32_t)0x00000002) +#define CHEN2_ENABLE ((uint32_t)0x00000004) +#define CHEN3_ENABLE ((uint32_t)0x00000008) +#define CHEN4_ENABLE ((uint32_t)0x00000010) +#define CHEN5_ENABLE ((uint32_t)0x00000020) +#define CHEN6_ENABLE ((uint32_t)0x00000040) +#define CHEN7_ENABLE ((uint32_t)0x00000080) +#define CHEN8_ENABLE ((uint32_t)0x00000100) +#define CHALL_ENABLE ((uint32_t)0x000001ff) + +#define CHEN_DISABLE ((uint32_t)0xFFFFFE00) + +/* ADC EXTSEL mask */ +#define ADCR_EXTSEL_Reset ((uint32_t)0xFFFFFF8F) + +/* ADC Analog watchdog enable mode mask */ +#define ADCFG_AWDMode_Reset ((uint32_t)0xFFFFFFFD) + +/* ADC AWDCH mask */ +#define ADCR_AWDCH_Reset ((uint32_t)0xFFFF0FFF) + +/* ADC TSPD mask */ +#define ADCHS_TSVREFE_Set ((uint32_t)0x00000100) +#define ADCHS_TSVREFE_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC1 DATA register base address */ +#define ADDATA_ADDRESS ((uint32_t)0x40012400) +/** +* @} +*/ + +/** @defgroup ADC_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the ADCx peripheral registers to their default +* reset values. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @retval : None +*/ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + switch (*(uint32_t*)&ADCx) + { + case ADC1_BASE: + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + break; + + case ADC2_BASE: + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + break; + + default: + break; + } +} + +/** +* @brief Initializes the ADCx peripheral according to the specified parameters +* in the ADC_InitStruct. +* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that +* contains the configuration information for the specified +* ADC peripheral. +* @retval : None +*/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + /*---------------------------- ADCx ADCFG Configuration -----------------*/ + /* Get the ADCx ADCFG value */ + tmpreg1 = ADCx->ADCFG; + /* Clear ADCPRE bits */ + tmpreg1 &= ADCFG_CLEAR_Mask; + /* Configure ADCx: AD convertion prescare*/ + /* Set ADCPRE bit according to ADC_PRESCARE value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_PRESCARE) | ADC_InitStruct->ADC_Resolution; + /* Write to ADCx ADCFG */ + ADCx->ADCFG = tmpreg1; + + /*---------------------------- ADCx ADCR Configuration -----------------*/ + /* Get the ADCx ADCR value */ + tmpreg1 = ADCx->ADCR; + /* Clear ALIGN , ADMD, and TRGEN and TRGSEL bits */ + tmpreg1 &= ADCR_CLEAR_Mask; + /* Configure ADCx: external trigger event and AD conversion mode and ALIGN*/ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set TRGEN bits according to ADC_ContinuousConvMode value */ + /* Set TRGSEL bits according to ADC_ExternalTrigConv value */ + + tmpreg1 |= ((uint32_t)ADC_InitStruct->ADC_DataAlign) | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_Mode) ; + + /* Write to ADCx ADCR */ + ADCx->ADCR = tmpreg1; + +} + +/** +* @brief Fills each ADC_InitStruct member with its default value. +* @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Initialize the ADC_Resolution values */ + ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; + /* Initialize the ADC_PRESCARE values */ + ADC_InitStruct->ADC_PRESCARE = ADC_PCLK2_PRESCARE_2; + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Single; + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + /* Initialize the ADC_NbrOfChannel member */ + +} + +/** +* @brief Enables or disables the specified ADC peripheral. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param NewState: new state of the ADCx peripheral. This parameter +* can be: ENABLE or DISABLE. +* @retval : None +*/ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADEN bit */ + ADCx->ADCFG |= ADCFG_ADEN_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->ADCFG &= ADCFG_ADEN_Reset; + } +} + +/** +* @brief Enables or disables the specified ADC DMA request. +* @param ADCx: where x can be 1 or 2 to select the ADC peripheral. +* @param NewState: new state of the selected ADC DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->ADCR |= ADCR_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->ADCR &= ADCR_DMA_Reset; + } +} + +/** +* @brief Enables or disables the specified ADC interrupts. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param ADC_IT: specifies the ADC interrupt sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* @arg ADC_IT_EOC: End of conversion interrupt mask +* @arg ADC_IT_AWD: Analog watchdog interrupt mask +* @param NewState: new state of the specified ADC interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + //itmask = (uint8_t)ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->ADCR |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->ADCR &= (~(uint32_t)ADC_IT); + } +} + +/** +* @brief Enables or disables the selected ADC software start conversion . +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param NewState: new state of the selected ADC software start conversion. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + /*Set ADST bit*/ + ADCx->ADCR |= ADCR_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->ADCR &= ADCR_SWSTART_Reset; + } +} + +/** +* @brief Gets the selected ADC Software start conversion Status. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @retval : The new state of ADC software start conversion (SET or RESET). +*/ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of ADST bit */ + if ((ADCx->ADCR & ADCR_SWSTART_Set) != (uint32_t)RESET) + { + /* ADST bit is set */ + bitstatus = SET; + } + else + { + /* ADST bit is reset */ + bitstatus = RESET; + } + /* Return the ADST bit status */ + return bitstatus; +} + +/** +* @brief Configures for the selected ADC channel its corresponding +* rank in the sequencer and its sample time. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param ADC_Channel: the ADC channel to configure. +* This parameter can be one of the following values: +* @arg ADC_Channel_0: ADC Channel0 selected +* @arg ADC_Channel_1: ADC Channel1 selected +* @arg ADC_Channel_2: ADC Channel2 selected +* @arg ADC_Channel_3: ADC Channel3 selected +* @arg ADC_Channel_4: ADC Channel4 selected +* @arg ADC_Channel_5: ADC Channel5 selected +* @arg ADC_Channel_6: ADC Channel6 selected +* @arg ADC_Channel_7: ADC Channel7 selected +* @arg ADC_Channel_8: ADC Channel8 selected +* @retval : None +*/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + tmpreg = ADCx->ADCFG; + tmpreg &= ~(ADC_SMPR_SMP << 10); + ADCx->ADCFG = tmpreg | ((ADC_SampleTime & ADC_SMPR_SMP) << 10); + switch(ADC_Channel) + { + /* set the CHEN0 bit for channel 0 enable*/ + case ADC_Channel_0: ADCx->ADCHS |= CHEN0_ENABLE; + break; + /* set the CHEN1 bit for channel 1 enable*/ + case ADC_Channel_1: ADCx->ADCHS |= CHEN1_ENABLE; + break; + /* set the CHEN2 bit for channel 2 enable*/ + case ADC_Channel_2: ADCx->ADCHS |= CHEN2_ENABLE; + break; + /* set the CHEN3 bit for channel 3 enable*/ + case ADC_Channel_3: ADCx->ADCHS |= CHEN3_ENABLE; + break; + /* set the CHEN4 bit for channel 4 enable*/ + case ADC_Channel_4: ADCx->ADCHS |= CHEN4_ENABLE; + break; + /* set the CHEN5 bit for channel 5 enable*/ + case ADC_Channel_5: ADCx->ADCHS |= CHEN5_ENABLE; + break; + /* set the CHEN6 bit for channel 6 enable*/ + case ADC_Channel_6: ADCx->ADCHS |= CHEN6_ENABLE; + break; + /* set the CHEN7 bit for channel 7 enable*/ + case ADC_Channel_7: ADCx->ADCHS |= CHEN7_ENABLE; + break; + /* set the SENSOREN bit for channel 8 enable*/ + case ADC_Channel_8: ADCx->ADCHS |= CHEN8_ENABLE; //SENSOREN or VREFINT + break; + case ADC_Channel_All: ADCx->ADCHS |= CHALL_ENABLE; //SENSOREN or VREFINT + break; + default: + ADCx->ADCHS &= CHEN_DISABLE; + break; + } +} + +/** +* @brief Enables or disables the ADCx conversion through external trigger. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param NewState: new state of the selected ADC external trigger +* start of conversion. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->ADCR |= ADCR_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->ADCR &= ADCR_EXTTRIG_Reset; + } +} + +/** +* @brief Returns the last ADCx conversion result data for regular channel. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @retval : The Data conversion value. +*/ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->ADDATA; +} + +/** +* @brief Returns the last ADC conversion result data in dual mode. +* @retval : The Data conversion value. +*/ +uint32_t ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(__IO uint32_t *) ADDATA_ADDRESS); +} + +/** +* @brief Configures the ADCx external trigger for injected channels conversion. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to +* start injected conversion. +* This parameter can be one of the following values: +* @arg ADC_ExternalTrigConv_T1_CC1: Timer1 capture +* compare1 selected (for ADC1) +* @arg ADC_ExternalTrigConv_T1_CC2: Timer1 capture +* compare2 selected (for ADC1) +* @arg ADC_ExternalTrigConv_T1_CC3: Timer1 capture +* compare3 selected (for ADC1) +* @arg ADC_ExternalTrigConv_T2_CC2: Timer2 capture +* compare2 selected (for ADC1) +* @arg ADC_ExternalTrigConv_T3_TRGO: Timer3 TRGO event +* selected (for ADC1) +* @arg ADC_ExternalTrigConv_T4_CC4: Timer4 capture +* compare4 selected (for ADC1) +* @arg ADC_ExternalTrigConv_T3_CC1: Timer3 capture +* compare1 selected (for ADC1) +* @arg ADC_ExternalTrigConv_EXTI_11: EXTI line 11 event +* cselected (for ADC1) +* @arg ADC_ExternalTrigConv_T1_TRGO: Timer1 TRGO event +* selected (for ADC2) +* @arg ADC_ExternalTrigConv_T1_CC4: Timer1 capture +* compare4 selected (for ADC2) +* @arg ADC_ExternalTrigConv_T2_TRGO: Timer2 TRGO event +* selected (for ADC2) +* @arg ADC_ExternalTrigConv_T2_CC1: Timer2 capture +* compare1 selected (for ADC2) +* @arg ADC_ExternalTrigConv_T3_CC4: Timer3 capture +* compare4 selected (for ADC2) +* @arg ADC_ExternalTrigConv_T4_TRGO: Timer4 TRGO event +* selected (for ADC2) +* @arg ADC_ExternalTrigConv_T3_CC1: Timer3 capture +* compare1 selected (for ADC2) +* @arg ADC_ExternalTrigConv_EXTI_15: EXTI line 15 event +* cselected (for ADC2) +* @retval : None +*/ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpreg = ADCx->ADCR; + /* Clear the old external event selection for injected group */ + tmpreg &= ADCR_EXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->ADCR = tmpreg; +} + +/** +* @brief Enables or disables the ADCx injected channels conversion +* through external trigger +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param NewState: new state of the selected ADC external trigger +* start of injected conversion. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->ADCR |= ADCR_EXTTRIG_Set; + } + else + { + ADCx->ADCR &= ADCR_EXTTRIG_Reset; + } +} + +/** +* @brief Enables or disables the analog watchdog on single/all regular +* or injected channels +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. +* This parameter can be one of the following values: +* @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on +* a single regular channel +* @arg ADC_AnalogWatchdog_None: No channel guarded by the +* analog watchdog +* analog watchdog +* @retval : None +*/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpreg = ADCx->ADCFG; + /* Clear ADWEN bit */ + tmpreg &= ADCFG_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->ADCFG = tmpreg; +} + +/** +* @brief Configures the high and low thresholds of the analog watchdog. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param HighThreshold: the ADC analog watchdog High threshold value. +* This parameter must be a 12bit value. +* @param LowThreshold: the ADC analog watchdog Low threshold value. +* This parameter must be a 12bit value. +* @retval : None +*/ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + uint32_t tempThreshold; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + /* Get the ADCx high threshold */ + tempThreshold = HighThreshold; + /* Set the ADCx high threshold and the ADCx low threshold */ + ADCx->ADCMPR = (tempThreshold << 16) | LowThreshold; +} + +/** +* @brief Configures the analog watchdog guarded single channel +* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* @param ADC_Channel: the ADC channel to configure for the analog +* watchdog. +* This parameter can be one of the following values: +* @arg ADC_Channel_0: ADC Channel0 selected +* @arg ADC_Channel_1: ADC Channel1 selected +* @arg ADC_Channel_2: ADC Channel2 selected +* @arg ADC_Channel_3: ADC Channel3 selected +* @arg ADC_Channel_4: ADC Channel4 selected +* @arg ADC_Channel_5: ADC Channel5 selected +* @arg ADC_Channel_6: ADC Channel6 selected +* @arg ADC_Channel_7: ADC Channel7 selected +* @arg ADC_Channel_8: ADC Channel8 selected +* @arg ADC_Channel_All: ADC all Channel selected +* @retval : None +*/ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + /* Get the old register value */ + tmpreg = ADCx->ADCR; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= ADCR_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= (ADC_Channel << 12); + /* Store the new register value */ + ADCx->ADCR = tmpreg; +} + +/** +* @brief Enables or disables the temperature sensor and Vrefint channel. +* @param NewState: new state of the temperature sensor. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->ADCFG |= ADCFG_TVSEN ; + ADC2->ADCFG |= ADCFG_TVSEN ;//next + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->ADCFG &= ~ ADCFG_TVSEN; + ADC2->ADCFG &= ~ ADCFG_TVSEN; + } +} + +/** +* @brief Checks whether the specified ADC flag is set or not. +* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* @param ADC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg ADC_FLAG_AWD: Analog watchdog flag +* @arg ADC_FLAG_EOC: End of conversion flag +* @arg ADC_FLAG_BUSY: AD conversion busy flag +* @retval : The new state of ADC_FLAG (SET or RESET). +*/ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->ADSTA & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** +* @brief Clears the ADCx's pending flags. +* @param ADCx: where x can be 1, 2 to select the ADC peripheral. +* @param ADC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* @arg ADC_FLAG_AWD: Analog watchdog flag +* @arg ADC_FLAG_EOC: End of conversion flag +* @retval : None +*/ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->ADSTA |= ADC_FLAG; +} + +/** +* @brief Checks whether the specified ADC interrupt has occurred or not. +* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* @param ADC_IT: specifies the ADC interrupt source to check. +* This parameter can be one of the following values: +* @arg ADC_IT_EOC: End of conversion interrupt mask +* @arg ADC_IT_AWD: Analog watchdog interrupt mask +* @retval : The new state of ADC_IT (SET or RESET). +*/ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->ADSTA & ADC_IT)) != (uint32_t)RESET) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** +* @brief Clears the ADCxs interrupt pending bits. +* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. +* @param ADC_IT: specifies the ADC interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* @arg ADC_IT_EOC: End of conversion interrupt mask +* @arg ADC_IT_AWD: Analog watchdog interrupt mask +* @retval : None +*/ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Clear the selected ADC interrupt pending bits */ + ADCx->ADSTA = ADC_IT; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_bkp.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_bkp.c new file mode 100644 index 0000000000..c2afb00b9b --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_bkp.c @@ -0,0 +1,300 @@ +/** +****************************************************************************** +* @file HAL_bkp.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the BKP firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_bkp.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup BKP +* @brief BKP driver modules +* @{ +*/ + +/** @defgroup BKP_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup BKP_Private_Defines +* @{ +*/ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ----*/ + +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + +/* ---------------------- BKP registers bit mask ------------------------ */ + +/* RTCCR register bit mask */ +#define RTCCR_CAL_Mask ((uint16_t)0xFF80) +#define RTCCR_Mask ((uint16_t)0xFC7F) + +/* CSR register bit mask */ +#define CSR_CTE_Set ((uint16_t)0x0001) +#define CSR_CTI_Set ((uint16_t)0x0002) + +/** +* @} +*/ + + +/** @defgroup BKP_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup BKP_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup BKP_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup BKP_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the BKP peripheral registers to their default +* reset values. +* @param None +* @retval : None +*/ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/** +* @brief Configures the Tamper Pin active level. +* @param BKP_TamperPinLevel: specifies the Tamper Pin active level. +* This parameter can be one of the following values: +* @arg BKP_TamperPinLevel_High: Tamper pin active on high level +* @arg BKP_TamperPinLevel_Low: Tamper pin active on low level +* @retval : None +*/ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/** +* @brief Enables or disables the Tamper Pin activation. +* @param NewState: new state of the Tamper Pin activation. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; +} + +/** +* @brief Enables or disables the Tamper Pin Interrupt. +* @param NewState: new state of the Tamper Pin Interrupt. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; +} + +/** +* @brief Select the RTC output source to output on the Tamper pin. +* @param BKP_RTCOutputSource: specifies the RTC output source. +* This parameter can be one of the following values: +* @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. +* @arg BKP_RTCOutputSource_CalibClock: output the RTC clock +* with frequency divided by 64 on the Tamper pin. +* @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse +* signal on the Tamper pin. +* @arg BKP_RTCOutputSource_Second: output the RTC Second pulse +* signal on the Tamper pin. +* @retval : None +*/ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + tmpreg = BKP->RTCCR; + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_Mask; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** +* @brief Sets RTC Clock Calibration value. +* @param CalibrationValue: specifies the RTC Clock Calibration value. +* This parameter must be a number between 0 and 0x7F. +* @retval : None +*/ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + tmpreg = BKP->RTCCR; + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_Mask; + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** +* @brief Writes user data to the specified Data Backup Register. +* @param BKP_DR: specifies the Data Backup Register. +* This parameter can be BKP_DRx where x:[1, 42] +* @param Data: data to write +* @retval : None +*/ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + *(__IO uint16_t *) (BKP_BASE + BKP_DR) = Data; +} + +/** +* @brief Reads data from the specified Data Backup Register. +* @param BKP_DR: specifies the Data Backup Register. +* This parameter can be BKP_DRx where x:[1, 42] +* @retval : The content of the specified Data Backup Register +*/ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + return (*(__IO uint16_t *) (BKP_BASE + BKP_DR)); +} + +/** +* @brief Checks whether the Tamper Pin Event flag is set or not. +* @param None +* @retval : The new state of the Tamper Pin Event flag (SET or RESET). +*/ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); +} + +/** +* @brief Clears Tamper Pin Event pending flag. +* @param None +* @retval : None +*/ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= CSR_CTE_Set; +} + +/** +* @brief Checks whether the Tamper Pin Interrupt has occurred or not. +* @param None +* @retval : The new state of the Tamper Pin Interrupt (SET or RESET). +*/ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); +} + +/** +* @brief Clears Tamper Pin Interrupt pending bit. +* @param None +* @retval : None +*/ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= CSR_CTI_Set; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_can.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_can.c new file mode 100644 index 0000000000..49978356c1 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_can.c @@ -0,0 +1,971 @@ +/** +****************************************************************************** +* @file HAL_can.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the CAN firmware functions. +****************************************************************************** +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_can.h" +#include "HAL_rcc.h" + +/** +* @brief: Deinitialinzes the CAN registers to their default reset values +* @retval: None +*/ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + break; + default: + break; + } + +} + +/** +* @brief Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* @retval : Constant indicates initialization succeed which will be +* CANINITFAILED or CANINITOK. +*/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_Basic_InitTypeDef* CAN_Basic_InitStruct) +{ + uint8_t InitStatus = CANINITFAILED; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->SJW)); + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->BRP)); + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->SAM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->TESG2)); + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->TESG1)); + + CANx->BTR0 = ((uint32_t)(CAN_Basic_InitStruct->SJW) << 6) | ((uint32_t)(CAN_Basic_InitStruct->BRP)); + CANx->BTR1 = ((uint32_t)(CAN_Basic_InitStruct->SAM) << 7) | ((uint32_t)(CAN_Basic_InitStruct->TESG2) << 4) | \ + ((uint32_t)(CAN_Basic_InitStruct->TESG1)); + if(CAN_Basic_InitStruct->GTS == ENABLE) + { + CANx->CMR |= (uint32_t)CAN_SleepMode; + } + else + { + CANx->CMR &= ~(uint32_t)CAN_SleepMode; + } + + CANx->CDR |= ((CAN_Basic_InitStruct->CBP) << 6) | ((CAN_Basic_InitStruct->RXINTEN) << 5) | \ + ((CAN_Basic_InitStruct->CLOSE_OPEN_CLK) << 3) | (CAN_Basic_InitStruct->CDCLK); + + InitStatus = CANINITOK; + return InitStatus; +} + +/** +* @brief Configures the CAN_Basic reception filter according to the specified +* parameters in the CAN_Basic_FilterInitStruct. +* @param CAN_Basic_FilterInitStruct: pointer to a CAN_Basic_FilterInitTypeDef structure that +* contains the configuration information. +* @retval None +*/ +void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* CAN_Basic_FilterInitStruct) +{ + /* Filter Mode */ + CAN1->ACR = CAN_Basic_FilterInitStruct->CAN_FilterId; + CAN1->AMR = CAN_Basic_FilterInitStruct->CAN_FilterMaskId; +} + + +/** +* @brief Fills each CAN_Basic_InitStruct member with its default value. +* @param CAN_Basic_InitStruct : pointer to a CAN_Basic_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void CAN_StructInit(CAN_Basic_InitTypeDef* CAN_Basic_InitStruct) +{ + /*--------------- Reset CAN_Basic init structure parameters values -----------------*/ + + + /* initialize the BRP member(where can be set with (0..63))*/ + CAN_Basic_InitStruct->BRP = 0x0; + /* initialize the SJW member(where can be set with (0..3)) */ + CAN_Basic_InitStruct->SJW = 0x0; + /* Initialize the TESG1 member(where can be set with (0..15)) */ + CAN_Basic_InitStruct->TESG1 = 0x0; + /* Initialize the TESG2 member(where can be set with(0..7)) */ + CAN_Basic_InitStruct->TESG2 = 0x0; + /* Initialize the SAM member(where can be set (SET or RESET)) */ + CAN_Basic_InitStruct->SAM = RESET; + /* Initialize the GTS member to Sleep Mode(where can be set (ENABLE or DISABLE)) */ + CAN_Basic_InitStruct->GTS = DISABLE; + /* Initialize the external pin CLKOUT frequence */ + CAN_Basic_InitStruct->CDCLK = 0x0; + /* Initialize the external clk is open or close */ + CAN_Basic_InitStruct->CLOSE_OPEN_CLK = 0x0; + /* Initialize the TX1 pin work as rx interrupt output */ + CAN_Basic_InitStruct->RXINTEN = 0x0; + /* Initialize the CBP of CDR register */ + CAN_Basic_InitStruct->CBP = 0x0; +} + +/** +* @brief Enables or disables the specified CAN interrupts. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param CAN_IT: specifies the CAN interrupt sources to be enabled or +* disabled. +* This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE, +* CAN_IT_RIE,. +* @param Newstate: new state of the CAN interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None. +*/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState Newstate) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITConfig(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(Newstate)); + if (Newstate != DISABLE) + { + /* Enable the selected CAN interrupt */ + CANx->CR |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CANx->CR &= ~CAN_IT; + } +} + + +/** +* @brief Initiates and transmits a CAN frame message. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. +* @retval CANTXOK if the CAN driver transmits the message +*/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanBasicTxMsg* BasicTxMessage) +{ + /* TXOK and TME bits */ + uint8_t state = 0; + /* Check the parameters */ + assert_param(IS_CAN_RTR(BasicTxMessage->RTR)); + assert_param(IS_CAN_DLC(BasicTxMessage->DLC)); + + CANx->TXID0 = (BasicTxMessage->IDH); + CANx->TXID1 = (BasicTxMessage->IDL << 5) | (BasicTxMessage->RTR << 4) | (BasicTxMessage->DLC); + if((FunctionalState)(BasicTxMessage->RTR) != ENABLE) + { + CANx->TXDR0 = BasicTxMessage->Data[0]; + CANx->TXDR1 = BasicTxMessage->Data[1]; + CANx->TXDR2 = BasicTxMessage->Data[2]; + CANx->TXDR3 = BasicTxMessage->Data[3]; + CANx->TXDR4 = BasicTxMessage->Data[4]; + CANx->TXDR5 = BasicTxMessage->Data[5]; + CANx->TXDR6 = BasicTxMessage->Data[6]; + CANx->TXDR7 = BasicTxMessage->Data[7]; + } + + CANx->CMR = CAN_CMR_TR; + + return state; +} + +/** +* @brief Cancels a transmit request. +* @param CANx: where x can be 1 to select the CAN peripheral. + +* @retval None +*/ +void CAN_CancelTransmit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + CANx->CMR = CAN_AT; + +} + +/** +* @brief Releases the specified receive FIFO. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @retval None +*/ +void CAN_FIFORelease(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Release FIFO */ + CANx->CMR |= (uint32_t)CAN_RRB; + +} + +/** +* @brief Receives a correct CAN frame. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param RxMessage: pointer to a structure receive frame which contains CAN Id, +* CAN DLC, CAN data and FMI number. +* @retval None +*/ +void CAN_Receive(CAN_TypeDef* CANx, CanBasicRxMsg* BasicRxMessage) +{ + uint16_t tempid; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + BasicRxMessage->RTR = (uint8_t)((CANx->RXID1) >> 4) & 0x1; + BasicRxMessage->DLC = (uint8_t)((CANx->RXID1) & 0xf); + tempid = (uint16_t)(((CANx->RXID1) & 0xe0) >> 5); + tempid |= (uint16_t)(CANx->RXID0 << 3); + BasicRxMessage->ID = tempid; + BasicRxMessage->Data[0] = CAN1->RXDR0; + BasicRxMessage->Data[1] = CAN1->RXDR1; + BasicRxMessage->Data[2] = CAN1->RXDR2; + BasicRxMessage->Data[3] = CAN1->RXDR3; + BasicRxMessage->Data[4] = CAN1->RXDR4; + BasicRxMessage->Data[5] = CAN1->RXDR5; + BasicRxMessage->Data[6] = CAN1->RXDR6; + BasicRxMessage->Data[7] = CAN1->RXDR7; + CAN_FIFORelease( CANx); +} + +/** +* @brief: Select the Sleep mode or not in Basic workmode +* @param: NewState to go into the Sleep mode or go out +* @retval: None +*/ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CANSLEEPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + CANx->CMR |= CAN_SleepMode; + if((CANx->CMR & 0x10) == CAN_SleepMode) + { + sleepstatus = CANSLEEPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)sleepstatus; + +} + +/** +* @brief Wakes the CAN up. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @retval : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other +* case. +*/ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint8_t wakeupstatus = CANWAKEUPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->CMR &= ~CAN_SleepMode; + + /* Sleep mode status */ + if((CANx->CMR & 0x01) == 0) + { + /* Sleep mode exited */ + wakeupstatus = CANWAKEUPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)wakeupstatus; +} + + +/** +* @brief Checks whether the specified CAN flag is set or not. +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @param CAN_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg CAN_STATUS_RBS: Receive buffer status +* @arg CAN_STATUS_DOS: Data overflow status +* @arg CAN_STATUS_TBS: Transmit buffer status +* @arg CAN_STATUS_TCS: Transmit complete status +* @arg CAN_STATUS_RS: Receiving status +* @arg CAN_STATUS_TS: Transmiting status +* @arg CAN_STATUS_ES: Error status +* @arg CAN_STATUS_BS: bus status, close or open +* @retval The new state of CAN_FLAG (SET or RESET). +*/ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CANx->SR & CAN_FLAG) == CAN_FLAG) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** +* @brief Checks whether the specified CAN interrupt has occurred or not. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param CAN_IT: specifies the CAN interrupt source to check. +* This parameter can be one of the following values: +* @arg CAN_IT_RI: Receive FIFO not empty Interrupt +* @arg CAN_IT_TI: Transmit Interrupt +* @arg CAN_IT_EI: ERROR Interrupt +* @arg CAN_IT_DOI: Data voerflow Interrupt +* @arg CAN_IT_WUI: Wakeup Interrupt +* @arg CAN_IT_ALL: use it can enble all Interrupt +* @retval The current state of CAN_IT (SET or RESET). +*/ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the interrupt enable bit */ + if((CANx->IR & CAN_IT) != CAN_IT) + { + itstatus = RESET; + } + else + { + itstatus = SET; + } + + return itstatus; +} + + +/** +* @brief: Select the can work as peli mode or basic mode +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @param CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode +* @retval: None +*/ +void CAN_Mode_Cmd(CAN_TypeDef* CANx, uint32_t CAN_MODE) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + CANx->CDR |= CAN_MODE; +} + + +/** +* @brief: Select the Reset mode or not +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @param: NewState to go into the Reset mode or go out +* @retval: None +*/ +void CAN_ResetMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if(NewState == ENABLE) + { + CANx->CR |= CAN_ResetMode; + } + else + { + CANx->CR &= ~CAN_ResetMode; + } +} + +/** +* @brief Clear the data overflow. +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @retval None +*/ +void CAN_ClearDataOverflow(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + CANx->CMR |= (uint32_t)CAN_CDO; + +} + +/** +* @brief Clears the CAN's IT pending. +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @retval None +*/ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx) +{ + uint32_t temp = 0; + temp = temp; + temp = CANx->IR; //read this register clear all interrupt + +} + + + +/** +* @brief: Select the Sleep mode or not in Peli workmode +* @param: NewState to go into the Sleep mode or go out +* @retval: None +*/ +void CAN_Peli_SleepMode_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + CAN1_PELI->MOD |= CAN_SleepMode; + else + CAN1_PELI->MOD &= ~CAN_SleepMode; +} + + +/** +* @brief Fills each CAN1_PELI_InitStruct member with its default value. +* @param CAN_Peli_InitStruct : pointer to a CAN_Peli_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct) +{ + /*--------------- Reset CAN_Peli init structure parameters values -----------------*/ + + /* initialize the BRP member(where can be set with (0..63))*/ + CAN_Peli_InitStruct->BRP = 0x0; + /* initialize the SJW member(where can be set with (0..3)) */ + CAN_Peli_InitStruct->SJW = 0x0; + /* Initialize the TESG1 member(where can be set with (0..15)) */ + CAN_Peli_InitStruct->TESG1 = 0x0; + /* Initialize the TESG2 member(where can be set with(0..7)) */ + CAN_Peli_InitStruct->TESG2 = 0x0; + /* Initialize the SAM member(where can be set (SET or RESET)) */ + CAN_Peli_InitStruct->SAM = RESET; + /* Initialize the LOM member*/ + CAN_Peli_InitStruct->LOM = DISABLE; + /* Initialize the STM member*/ + CAN_Peli_InitStruct->STM = DISABLE; + /* Initialize the SM member*/ + CAN_Peli_InitStruct->SM = DISABLE; + CAN_Peli_InitStruct->SRR = DISABLE; + CAN_Peli_InitStruct->EWLR = 0x96; +} + +/** +* @brief Initializes the CAN_Peli peripheral according to the specified +* parameters in the CAN_Peli_InitStruct. +* @param CAN_Basic_InitStruct: pointer to a CAN_Peli_InitTypeDef structure that contains +* the configuration information for the CAN peripheral in the peli workmode. +* @retval None +*/ +void CAN_Peli_Init(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->SJW)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->BRP)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->SAM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->TESG2)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->TESG1)); + + CAN1_PELI->BTR0 = ((uint32_t)CAN_Peli_InitStruct->SJW << 6) | ((uint32_t)CAN_Peli_InitStruct->BRP); + CAN1_PELI->BTR1 = ((uint32_t)CAN_Peli_InitStruct->SAM << 7) | ((uint32_t)CAN_Peli_InitStruct->TESG2 << 4) | \ + ((uint32_t)CAN_Peli_InitStruct->TESG1); + if(CAN_Peli_InitStruct->LOM == ENABLE) + CAN1_PELI->MOD |= (uint32_t)CAN_ListenOnlyMode; + else + CAN1_PELI->MOD &= ~(uint32_t)CAN_ListenOnlyMode; + if(CAN_Peli_InitStruct->STM == ENABLE) + CAN1_PELI->MOD |= (uint32_t)CAN_SeftTestMode; + else + CAN1_PELI->MOD &= ~(uint32_t)CAN_SeftTestMode; + if(CAN_Peli_InitStruct->SM == ENABLE) + CAN1_PELI->MOD |= (uint32_t)CAN_SleepMode; + else + CAN1_PELI->MOD &= ~(uint32_t)CAN_SleepMode; + CAN1_PELI->EWLR = (uint32_t)CAN_Peli_InitStruct->EWLR; +} + + + +/** +* @brief Configures the CAN_Peli reception filter according to the specified +* parameters in the CAN_Peli_FilterInitStruct. +* @param CAN_Peli_FilterInitStruct: pointer to a CAN_Peli_FilterInitTypeDef structure that +* contains the configuration information. +* @retval None +*/ +void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct) +{ + if(CAN_Peli_FilterInitStruct->AFM == CAN_FilterMode_Singal) + CAN1_PELI->MOD |= (uint32_t)CAN_FilterMode_Singal; + else + CAN1_PELI->MOD &= (uint32_t)CAN_FilterMode_Double; + + CAN1_PELI->FF = CAN_Peli_FilterInitStruct->CAN_FilterId0; + CAN1_PELI->ID0 = CAN_Peli_FilterInitStruct->CAN_FilterId1; + CAN1_PELI->ID1 = CAN_Peli_FilterInitStruct->CAN_FilterId2; + CAN1_PELI->DATA0 = CAN_Peli_FilterInitStruct->CAN_FilterId3; + + CAN1_PELI->DATA1 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId0; + CAN1_PELI->DATA2 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId1; + CAN1_PELI->DATA3 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId2; + CAN1_PELI->DATA4 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId3; +} + +/** +* @brief Fills each CAN_Peli_FilterInitStruct member with its default value. +* @param CAN_Peli_FilterInitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. +* @retval None +*/ +void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct) +{ + CAN_Peli_FilterInitStruct->CAN_FilterId0 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterId1 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterId2 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterId3 = 0; + + CAN_Peli_FilterInitStruct->CAN_FilterMaskId0 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterMaskId1 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterMaskId2 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterMaskId3 = 0; +} + + +/** +* @brief Initiates and transmits a CAN frame message. +* @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. +* @retval None +*/ +void CAN_Peli_Transmit(CanPeliTxMsg* PeliTxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_RTR(PeliTxMessage->RTR)); + assert_param(IS_CAN_DLC(PeliTxMessage->DLC)); + + CAN1_PELI->FF = (PeliTxMessage->FF << 7) | (PeliTxMessage->RTR << 6) | (PeliTxMessage->DLC); + if(((FunctionalState)PeliTxMessage->FF) != ENABLE) + { + CAN1_PELI->ID0 = (PeliTxMessage->IDHH); + // CAN1_PELI->ID1 = ((PeliTxMessage->IDHL)<<5); + CAN1_PELI->ID1 = (PeliTxMessage->IDHL & 0xE0); + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN1_PELI->DATA0 = PeliTxMessage->Data[0]; + CAN1_PELI->DATA1 = PeliTxMessage->Data[1]; + CAN1_PELI->DATA2 = PeliTxMessage->Data[2]; + CAN1_PELI->DATA3 = PeliTxMessage->Data[3]; + CAN1_PELI->DATA4 = PeliTxMessage->Data[4]; + CAN1_PELI->DATA5 = PeliTxMessage->Data[5]; + CAN1_PELI->DATA6 = PeliTxMessage->Data[6]; + CAN1_PELI->DATA7 = PeliTxMessage->Data[7]; + } + } + else + { + CAN1_PELI->ID0 = PeliTxMessage->IDHH; + CAN1_PELI->ID1 = PeliTxMessage->IDHL; + CAN1_PELI->DATA0 = PeliTxMessage->IDLH; + CAN1_PELI->DATA1 = PeliTxMessage->IDLL; + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN1_PELI->DATA2 = PeliTxMessage->Data[0]; + CAN1_PELI->DATA3 = PeliTxMessage->Data[1]; + CAN1_PELI->DATA4 = PeliTxMessage->Data[2]; + CAN1_PELI->DATA5 = PeliTxMessage->Data[3]; + CAN1_PELI->DATA6 = PeliTxMessage->Data[4]; + CAN1_PELI->DATA7 = PeliTxMessage->Data[5]; + CAN1_PELI->DATA8 = PeliTxMessage->Data[6]; + CAN1_PELI->DATA9 = PeliTxMessage->Data[7]; + } + } + if(CAN1_PELI->MOD & CAN_MOD_STM) + { + CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT; + } + else + { + CAN1->CMR = CAN_TR | CAN_AT; + } + +} + + + +/** +* @brief Initiates and transmits a CAN frame message. +* @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. +* @retval None +*/ +void CAN_Peli_TransmitRepeat(CanPeliTxMsg* PeliTxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_RTR(PeliTxMessage->RTR)); + assert_param(IS_CAN_DLC(PeliTxMessage->DLC)); + + CAN1_PELI->FF = (PeliTxMessage->FF << 7) | (PeliTxMessage->RTR << 6) | (PeliTxMessage->DLC); + if(((FunctionalState)PeliTxMessage->FF) != ENABLE) + { + CAN1_PELI->ID0 = (PeliTxMessage->IDHH); + CAN1_PELI->ID1 = ((PeliTxMessage->IDHL) << 5); + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN1_PELI->DATA0 = PeliTxMessage->Data[0]; + CAN1_PELI->DATA1 = PeliTxMessage->Data[1]; + CAN1_PELI->DATA2 = PeliTxMessage->Data[2]; + CAN1_PELI->DATA3 = PeliTxMessage->Data[3]; + CAN1_PELI->DATA4 = PeliTxMessage->Data[4]; + CAN1_PELI->DATA5 = PeliTxMessage->Data[5]; + CAN1_PELI->DATA6 = PeliTxMessage->Data[6]; + CAN1_PELI->DATA7 = PeliTxMessage->Data[7]; + } + } + else + { + CAN1_PELI->ID0 = PeliTxMessage->IDHH; + CAN1_PELI->ID1 = PeliTxMessage->IDHL; + CAN1_PELI->DATA0 = PeliTxMessage->IDLH; + CAN1_PELI->DATA1 = PeliTxMessage->IDLL; + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN1_PELI->DATA2 = PeliTxMessage->Data[0]; + CAN1_PELI->DATA3 = PeliTxMessage->Data[1]; + CAN1_PELI->DATA4 = PeliTxMessage->Data[2]; + CAN1_PELI->DATA5 = PeliTxMessage->Data[3]; + CAN1_PELI->DATA6 = PeliTxMessage->Data[4]; + CAN1_PELI->DATA7 = PeliTxMessage->Data[5]; + CAN1_PELI->DATA8 = PeliTxMessage->Data[6]; + CAN1_PELI->DATA9 = PeliTxMessage->Data[7]; + } + } + + if(CAN1_PELI->MOD & CAN_MOD_STM) + { + CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT; + } + else + { + CAN1->CMR = CAN_CMR_TR; + } +} + +/** @defgroup CAN_Group3 CAN Frames Reception functions +* @brief CAN Frames Reception functions +* +@verbatim +=============================================================================== +##### CAN Frames Reception functions ##### +=============================================================================== +[..] This section provides functions allowing to +(+) Receive a correct CAN frame. +(+) Release a specified receive FIFO +(+) Return the number of the pending received CAN frames. + +@endverbatim +* @{ +*/ + + +/** +* @brief Receives a correct CAN frame. +* @param RxMessage: pointer to a structure receive frame which contains CAN Id, +* CAN DLC, CAN data and FMI number. +* @retval None +*/ +void CAN_Peli_Receive(CanPeliRxMsg* PeliRxMessage) +{ + uint32_t tempid; + PeliRxMessage->FF = (CAN1_PELI->FF) >> 7; + PeliRxMessage->RTR = ((CAN1_PELI->FF) >> 6) & 0x1; + PeliRxMessage->DLC = (CAN1_PELI->FF) & 0xf; + + if(((FunctionalState)PeliRxMessage->FF) != ENABLE) + { + tempid = (uint32_t)(CAN1_PELI->ID1 >> 5); + tempid |= (uint32_t)(CAN1_PELI->ID0 << 3); + PeliRxMessage->ID = tempid; + PeliRxMessage->Data[0] = CAN1_PELI->DATA0; + PeliRxMessage->Data[1] = CAN1_PELI->DATA1; + PeliRxMessage->Data[2] = CAN1_PELI->DATA2; + PeliRxMessage->Data[3] = CAN1_PELI->DATA3; + PeliRxMessage->Data[4] = CAN1_PELI->DATA4; + PeliRxMessage->Data[5] = CAN1_PELI->DATA5; + PeliRxMessage->Data[6] = CAN1_PELI->DATA6; + PeliRxMessage->Data[7] = CAN1_PELI->DATA7; + } + else + { + tempid = (uint32_t)((CAN1_PELI->DATA1 & 0xf8) >> 3); + tempid |= (uint32_t)(CAN1_PELI->DATA0 << 5); + tempid |= (uint32_t)(CAN1_PELI->ID1 << 13); + tempid |= (uint32_t)(CAN1_PELI->ID0 << 21); + PeliRxMessage->ID = tempid; + PeliRxMessage->Data[0] = CAN1_PELI->DATA2; + PeliRxMessage->Data[1] = CAN1_PELI->DATA3; + PeliRxMessage->Data[2] = CAN1_PELI->DATA4; + PeliRxMessage->Data[3] = CAN1_PELI->DATA5; + PeliRxMessage->Data[4] = CAN1_PELI->DATA6; + PeliRxMessage->Data[5] = CAN1_PELI->DATA7; + PeliRxMessage->Data[6] = CAN1_PELI->DATA8; + PeliRxMessage->Data[7] = CAN1_PELI->DATA9; + } + CAN_FIFORelease( CAN1); +} + + +/** +* @brief Get available current informatoin in receive FIFO only in Peli workmode. +* @retval The value in reg RMC +*/ +uint32_t CAN_Peli_GetRxFIFOInfo(void) +{ + return CAN1_PELI->RMC; +} + + +/** @defgroup CAN_Group5 CAN Bus Error management functions +* @brief CAN Bus Error management functions +* +@verbatim +=============================================================================== +##### CAN Bus Error management functions ##### +=============================================================================== + +@endverbatim +* @{ +*/ + +/** +* @brief Returns the CAN's last error code (LEC). +* @retval Error code: +* - CAN_ERRORCODE_NoErr: No Error +* - CAN_ERRORCODE_StuffErr: Stuff Error +* - CAN_ERRORCODE_FormErr: Form Error +* - CAN_ERRORCODE_ACKErr : Acknowledgment Error +* - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error +* - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error +* - CAN_ERRORCODE_CRCErr: CRC Error +* - CAN_ERRORCODE_SoftwareSetErr: Software Set Error +*/ +uint8_t CAN_Peli_GetLastErrorCode(void) +{ + uint8_t errorcode = 0; + + /* Get the error code*/ + errorcode = ((uint8_t)CAN1_PELI->ECC); + + /* Return the error code*/ + return errorcode; +} +/** +* @brief Returns the CAN Receive Error Counter (REC). +* @note In case of an error during reception, this counter is incremented +* by 1 or by 8 depending on the error condition as defined by the CAN +* standard. After every successful reception, the counter is +* decremented by 1 or reset to 120 if its value was higher than 128. +* When the counter value exceeds 127, the CAN controller enters the +* error passive state. +* @retval CAN Receive Error Counter. +*/ +uint8_t CAN_Peli_GetReceiveErrorCounter(void) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)(CAN1_PELI->RXERR); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** +* @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). +* @retval LSB of the 8-bit CAN Transmit Error Counter. +*/ +uint8_t CAN_Peli_GetLSBTransmitErrorCounter(void) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 8-bit CAN Transmit Error Counter(TEC) */ + counter = (uint8_t)(CAN1_PELI->TXERR); + + /* Return the LSB of the 8-bit CAN Transmit Error Counter(TEC) */ + return counter; +} +/** @defgroup CAN_Group6 Interrupts and flags management functions +* @brief Interrupts and flags management functions +* +@verbatim +=============================================================================== +##### Interrupts and flags management functions ##### +=============================================================================== +[..] This section provides functions allowing to configure the CAN Interrupts +and to get the status and clear flags and Interrupts pending bits. +[..] The CAN provides 14 Interrupts sources and 15 Flags: + +*** Flags *** +============= +*/ +/** +* @brief Enables or disables the specified CAN interrupts in peli workmode. +* @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. +* This parameter can be: +* @arg CAN_IT_RI: Receive FIFO not empty Interrupt +* @arg CAN_IT_TI: Transmit Interrupt +* @arg CAN_IT_EI: ERROR Interrupt +* @arg CAN_IT_DOI: Data voerflow Interrupt +* @arg CAN_IT_WUI: Wakeup Interrupt +* @arg CAN_IT_EPI(only Peli): passive error Interrupt +* @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt +* @arg CAN_IT_BEI(only Peli): bus error Interrupt +@arg CAN_IT_ALL: use it can enble all Interrupt +* @param NewState: new state of the CAN interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void CAN_Peli_ITConfig(uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CAN1_PELI->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CAN1_PELI->IER &= ~CAN_IT; + } +} + + +/** +* @brief Checks whether the specified CAN interrupt has occurred or not. +* @param CAN_IT: specifies the CAN interrupt source to check. +* This parameter can be one of the following values: +* @arg CAN_IT_RI: Receive FIFO not empty Interrupt +* @arg CAN_IT_TI: Transmit Interrupt +* @arg CAN_IT_EI: ERROR Interrupt +* @arg CAN_IT_DOI: Data voerflow Interrupt +* @arg CAN_IT_WUI: Wakeup Interrupt +* @arg CAN_IT_EPI(only Peli): passive error Interrupt +* @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt +* @arg CAN_IT_BEI(only Peli): bus error Interrupt +@arg CAN_IT_ALL: use it can enble all Interrupt +* @retval The current state of CAN_IT (SET or RESET). +*/ +ITStatus CAN_Peli_GetITStatus(uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the interrupt enable bit */ + if((CAN1_PELI->IR & CAN_IT) != CAN_IT) + { + itstatus = RESET; + } + else + { + itstatus = SET; + } + + return itstatus; +} + +/** +* @brief Config CAN_Peli_InitTypeDef baud parameter. +* @param CAN_Peli_InitTypeDef: CAN struct. +* @param SrcClk: CAN module clock. +* @param baud: specified baud. +* @retval The current state of CAN_IT (SET or RESET). +*/ +void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef *CAN_Peli_InitStruct, unsigned int SrcClk, unsigned int baud ) +{ + unsigned int i, value = baud, record = 1; + unsigned int remain = 0, sumPrescaler = 0; + while(( baud == 0 ) || ( SrcClk == 0 )); //ֹʼʱΪ0 + sumPrescaler = SrcClk / baud; //ܷƵ + sumPrescaler = sumPrescaler / 2; // + for( i = 25; i > 3; i -- ) + { + remain = sumPrescaler - ((sumPrescaler / i) * i); + if( remain == 0 ) // + { + record = i; + break; + } + else + { + if(remain < value) + { + value = remain; + record = i; + } + } + } + CAN_Peli_InitStruct->SJW = 0; + CAN_Peli_InitStruct->BRP = (sumPrescaler / record) - 1; + CAN_Peli_InitStruct->TESG2 = (record - 3) / 3; + CAN_Peli_InitStruct->TESG1 = (record - 3) - CAN_Peli_InitStruct->TESG2; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + + + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ + diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_crc.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_crc.c new file mode 100644 index 0000000000..49b30441f0 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_crc.c @@ -0,0 +1,164 @@ +/** +****************************************************************************** +* @file HAL_crc.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the CRC firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_crc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup CRC +* @brief CRC driver modules +* @{ +*/ + +/** @defgroup CRC_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup CRC_Private_Defines +* @{ +*/ + +/* CR register bit mask */ + +#define CR_RESET_Set ((uint32_t)0x00000001) + +/** +* @} +*/ + +/** @defgroup CRC_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup CRC_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup CRC_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup CRC_Private_Functions +* @{ +*/ + +/** +* @brief Resets the CRC Data register (DR). +* @param None +* @retval : None +*/ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CR_RESET_Set; +} + +/** +* @brief Computes the 32-bit CRC of a given data word(32-bit). +* @param Data: data word(32-bit) to compute its CRC +* @retval : 32-bit CRC +*/ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + CRC->DR = CRC_GetCRC();//__NOP();// + return (CRC->DR); +} + +/** +* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). +* @param pBuffer: pointer to the buffer containing the data to be +* computed +* @param BufferLength: length of the buffer to be computed +* @retval : 32-bit CRC +*/ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** +* @brief Returns the current CRC value. +* @param None +* @retval : 32-bit CRC +*/ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** +* @brief Stores a 8-bit data in the Independent Data(ID) register. +* @param IDValue: 8-bit value to be stored in the ID register +* @retval : None +*/ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** +* @brief Returns the 8-bit data stored in the Independent Data(ID) register +* @param None +* @retval : 8-bit value of the ID register +*/ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_dma.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_dma.c new file mode 100644 index 0000000000..6fe71125d5 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_dma.c @@ -0,0 +1,545 @@ +/** +****************************************************************************** +* @file HAL_dma.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the DMA firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_dma.h" + + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup DMA +* @brief DMA driver modules +* @{ +*/ + +/** @defgroup DMA_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + +/** @defgroup DMA_Private_Defines +* @{ +*/ + +/* DMA ENABLE mask */ +#define CCR_ENABLE_Set ((uint32_t)0x00000001) +#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) +#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) +#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) +#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) +#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) +#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000) +#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000) + + + + + + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** +* @} +*/ + +/** @defgroup DMA_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the DMAy Channelx registers to their default reset +* values. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @retval : None +*/ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + switch (*(uint32_t*)&DMAy_Channelx) + { + case DMA1_Channel1_BASE: + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + break; + case DMA1_Channel2_BASE: + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + break; + case DMA1_Channel3_BASE: + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + break; + case DMA1_Channel4_BASE: + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + break; + case DMA1_Channel5_BASE: + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + break; + case DMA1_Channel6_BASE: + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + break; + case DMA1_Channel7_BASE: + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + break; + + default: + break; + } +} + +/** +* @brief Initializes the DMAy Channelx according to the specified +* parameters in the DMA_InitStruct. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that +* contains the configuration information for the specified +* DMA Channel. +* @retval : None +*/ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + /*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** +* @brief Fills each DMA_InitStruct member with its default value. +* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** +* @brief Enables or disables the specified DMAy Channelx. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @param NewState: new state of the DMAy Channelx. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= CCR_ENABLE_Set; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + } +} + +/** +* @brief Enables or disables the specified DMAy Channelx interrupts. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @param DMA_IT: specifies the DMA interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* @arg DMA_IT_TC: Transfer complete interrupt mask +* @arg DMA_IT_HT: Half transfer interrupt mask +* @arg DMA_IT_TE: Transfer error interrupt mask +* @param NewState: new state of the specified DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** +* @brief Returns the number of remaining data units in the current +* DMAy Channelx transfer. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @retval : The number of remaining data units in the current DMAy Channelx +* transfer. +*/ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** +* @brief Checks whether the specified DMAy Channelx flag is set or not. +* @param DMA_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. +* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. +* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. +* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. +* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. +* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. +* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. +* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. +* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. +* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. +* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. +* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. +* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. +* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. +* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. +* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. +* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. +* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. +* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. +* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. +* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. +* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. +* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. +* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. +* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. +* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. +* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. +* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. +* @retval : The new state of DMA_FLAG (SET or RESET). +*/ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** +* @brief Clears the DMAy Channelx's pending flags. +* @param DMA_FLAG: specifies the flag to clear. +* This parameter can be any combination (for the same DMA) of +* the following values: +* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. +* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. +* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. +* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. +* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. +* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. +* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. +* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. +* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. +* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. +* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. +* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. +* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. +* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. +* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. +* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. +* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. +* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. +* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. +* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. +* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. +* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. +* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. +* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. +* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. +* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. +* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. +* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. +* @retval : None +*/ +void DMA_ClearFlag(uint32_t DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Clear the selected DMA flags */ + DMA1->IFCR = DMA_FLAG; +} + +/** +* @brief Checks whether the specified DMAy Channelx interrupt has +* occurred or not. +* @param DMA_IT: specifies the DMA interrupt source to check. +* This parameter can be one of the following values: +* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. +* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. +* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. +* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. +* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. +* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. +* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. +* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. +* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. +* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. +* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. +* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. +* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. +* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. +* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. +* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. +* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. +* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. +* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. +* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. +* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. +* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. +* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. +* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. +* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. +* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. +* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. +* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. +* @retval : The new state of DMA_IT (SET or RESET). +*/ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + + /* Check the status of the specified DMA interrupt */ + if ((tmpreg & DMA_IT) != (uint32_t)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** +* @brief Clears the DMAy Channelxs interrupt pending bits. +* @param DMA_IT: specifies the DMA interrupt pending bit to clear. +* This parameter can be any combination (for the same DMA) of +* the following values: +* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. +* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. +* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. +* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. +* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. +* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. +* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. +* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. +* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. +* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. +* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. +* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. +* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. +* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. +* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. +* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. +* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. +* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. +* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. +* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. +* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. +* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. +* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. +* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. +* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. +* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. +* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. +* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. +* @retval : None +*/ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Clear the selected DMA interrupt pending bits */ + DMA1->IFCR = DMA_IT; + +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_exti.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_exti.c new file mode 100644 index 0000000000..093dc09930 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_exti.c @@ -0,0 +1,262 @@ +/** +****************************************************************************** +* @file HAL_exti.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the EXTI firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_exti.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup EXTI +* @brief EXTI driver modules +* @{ +*/ + +/** @defgroup EXTI_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_Defines +* @{ +*/ + +#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the EXTI peripheral registers to their default +* reset values. +* @param None +* @retval : None +*/ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x001FFFFF; +} + +/** +* @brief Initializes the EXTI peripheral according to the specified +* parameters in the EXTI_InitStruct. +* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* that contains the configuration information for the EXTI +* peripheral. +* @retval : None +*/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Mode) |= EXTI_InitStruct->EXTI_Line; + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Trigger) |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + /* Disable the selected external lines */ + *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Mode) &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** +* @brief Fills each EXTI_InitStruct member with its reset value. +* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LineNone; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** +* @brief Generates a Software interrupt. +* @param EXTI_Line: specifies the EXTI lines to be enabled or +* disabled. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* @retval : None +*/ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** +* @brief Checks whether the specified EXTI line flag is set or not. +* @param EXTI_Line: specifies the EXTI line flag to check. +* This parameter can be: +* @arg EXTI_Linex: External interrupt line x where x(0..18) +* @retval : The new state of EXTI_Line (SET or RESET). +*/ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the EXTIs line pending flags. +* @param EXTI_Line: specifies the EXTI lines flags to clear. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* @retval : None +*/ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** +* @brief Checks whether the specified EXTI line is asserted or not. +* @param EXTI_Line: specifies the EXTI line to check. +* This parameter can be: +* @arg EXTI_Linex: External interrupt line x where x(0..18) +* @retval : The new state of EXTI_Line (SET or RESET). +*/ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the EXTIs line pending bits. +* @param EXTI_Line: specifies the EXTI lines to clear. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* @retval : None +*/ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_flash.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_flash.c new file mode 100644 index 0000000000..4d94ad7f69 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_flash.c @@ -0,0 +1,930 @@ +/** +****************************************************************************** +* @file HAL_flash.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the FLASH firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_flash.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup FLASH +* @brief FLASH driver modules +* @{ +*/ + +/** @defgroup FLASH_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Private_Defines +* @{ +*/ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x00000FFF) +#define ProgramTimeout ((uint32_t)0x0000000F) + +/** +* @} +*/ + +/** @defgroup FLASH_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Private_FunctionPrototypes +* @{ +*/ + +static void delay(void); +/** +* @} +*/ + +/** @defgroup FLASH_Private_Functions +* @{ +*/ + +/** +* @brief Sets the code latency value. +* @param FLASH_Latency: specifies the FLASH Latency value. +* This parameter can be one of the following values: +* @arg FLASH_Latency_0: FLASH Zero Latency cycle +* @arg FLASH_Latency_1: FLASH One Latency cycle +* @arg FLASH_Latency_2: FLASH Two Latency cycles +* @arg FLASH_Latency_3: FLASH Three Latency cycles +* @retval : None +*/ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** +* @brief Enables or disables the Half cycle flash access. +* @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. +* This parameter can be one of the following values: +* @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable +* @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable +* @retval : None +*/ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** +* @brief Enables or disables the Prefetch Buffer. +* @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. +* This parameter can be one of the following values: +* @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable +* @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable +* @retval : None +*/ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** +* @brief Unlocks the FLASH Program Erase Controller. +* @param None +* @retval : None +*/ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/** +* @brief Locks the FLASH Program Erase Controller. +* @param None +* @retval : None +*/ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the FCR */ + FLASH->CR |= CR_LOCK_Set; +} + +/** +* @brief Erases a specified FLASH page. +* @param Page_Address: The page address to be erased. +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR |= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_BUSY) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + + /* Return the Erase Status */ + return status; +} + +/** +* @brief Erases all FLASH pages. +* @param None +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->AR = 0x08000000; + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_BUSY) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } + + /* Return the Erase Status */ + return status; +} + +/** +* @brief Erases the FLASH option bytes. +* @param None +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->AR = 0x1FFFF800; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + /* Enable the readout access */ + OB->RDP = RDP_Key; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_BUSY) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** +* @brief Programs a word at a specified address. +* @param Address: specifies the address to be programmed. +* @param Data: specifies the data to be programmed. +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + *(__IO uint16_t*)(Address + 2) = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_BUSY) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + + + /* Return the Program Status */ + return status; +} + +/** +* @brief Programs a half word at a specified address. +* @param Address: specifies the address to be programmed. +* @param Data: specifies the data to be programmed. +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + + + /* Return the Program Status */ + return status; +} + +/** +* @brief Programs a half word at a specified Option Byte Data address. +* @param Address: specifies the address to be programmed. +* This parameter can be 0x1FFFF804 or 0x1FFFF806. +* @param Data: specifies the data to be programmed. +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + + + + /* Return the Option Byte Data Program Status */ + return status; +} + +/** +* @brief Write protects the desired pages +* @param FLASH_Pages: specifies the address of the pages to be +* write protected. This parameter can be: +* @arg For microcontroller Medium-density devices (FLASH page size equal to 1 KB) +* A value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages124to127 +* @arg For microcontroller High-density devices (FLASH page size equal to 2 KB) +* A value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 +* or FLASH_WRProt_Pages62to255 +* @arg FLASH_WRProt_AllPages +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + + + + /* Return the write protection operation Status */ + return status; +} + +/** +* @brief Enables or disables the read out protection. +* If the user has already programmed the other option bytes before +* calling this function, he must re-program them since this +* function erases all option bytes. +* @param Newstate: new state of the ReadOut Protection. +* This parameter can be: ENABLE or DISABLE. +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->AR = 0x1ffff800; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_BUSY) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + + + + /* Return the protection operation Status */ + return status; +} + +/** +* @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / +* RST_STDBY. +* @param OB_IWDG: Selects the IWDG mode +* This parameter can be one of the following values: +* @arg OB_IWDG_SW: Software IWDG selected +* @arg OB_IWDG_HW: Hardware IWDG selected +* @param OB_STOP: Reset event when entering STOP mode. +* This parameter can be one of the following values: +* @arg OB_STOP_NoRST: No reset generated when entering in STOP +* @arg OB_STOP_RST: Reset generated when entering in STOP +* @param OB_STDBY: Reset event when entering Standby mode. +* This parameter can be one of the following values: +* @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY +* @arg OB_STDBY_RST: Reset generated when entering in STANDBY +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = ( OB_IWDG | OB_STOP | OB_STDBY) | (uint16_t)0xF8; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + + + + /* Return the Option Byte program Status */ + return status; +} + +/** +* @brief Returns the FLASH User Option Bytes values. +* @param None +* @retval : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) +* and RST_STDBY(Bit2). +*/ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** +* @brief Returns the FLASH Write Protection Option Bytes Register value. +* @param None +* @retval : The FLASH Write Protection Option Bytes Register value +*/ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Falsh write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** +* @brief Checks whether the FLASH Read Out Protection Status is set +* or not. +* @param None +* @retval : FLASH ReadOut Protection Status(SET or RESET) +*/ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** +* @brief Checks whether the FLASH Prefetch Buffer status is set or not. +* @param None +* @retval : FLASH Prefetch Buffer Status (SET or RESET). +*/ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** +* @brief Enables or disables the specified FLASH interrupts. +* @param FLASH_IT: specifies the FLASH interrupt sources to be +* enabled or disabled. +* This parameter can be any combination of the following values: +* @arg FLASH_IT_ERROR: FLASH Error Interrupt +* @arg FLASH_IT_EOP: FLASH end of operation Interrupt +* @param NewState: new state of the specified Flash interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +} + +/** +* @brief Checks whether the specified FLASH flag is set or not. +* @param FLASH_FLAG: specifies the FLASH flag to check. +* This parameter can be one of the following values: +* @arg FLASH_FLAG_BSY: FLASH Busy flag +* @arg FLASH_FLAG_PGERR: FLASH Program error flag +* @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag +* @arg FLASH_FLAG_EOP: FLASH End of Operation flag +* @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag +* @retval : The new state of FLASH_FLAG (SET or RESET). +*/ +FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** +* @brief Clears the FLASHs pending flags. +* @param FLASH_FLAG: specifies the FLASH flags to clear. +* This parameter can be any combination of the following values: +* @arg FLASH_FLAG_BSY: FLASH Busy flag +* @arg FLASH_FLAG_PGERR: FLASH Program error flag +* @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag +* @arg FLASH_FLAG_EOP: FLASH End of Operation flag +* @retval : None +*/ +void FLASH_ClearFlag(uint16_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/** +* @brief Returns the FLASH Status. +* @param None +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE +*/ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if(FLASH->SR & FLASH_FLAG_PGERR) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if(FLASH->SR & FLASH_FLAG_WRPRTERR) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** +* @brief Waits for a Flash operation to complete or a TIMEOUT to occur. +* @param Timeout: FLASH progamming Timeout +* @retval : FLASH Status: The returned value can be: FLASH_BUSY, +* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or +* FLASH_TIMEOUT. +*/ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + + + /* Check for the Flash Status */ + status = FLASH_GetStatus(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + delay(); + status = FLASH_GetStatus(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + + + + /* Return the operation status */ + return status; +} + +/** +* @brief Inserts a time delay. +* @param None +* @retval : None +*/ +static void delay(void) +{ + __IO uint32_t i = 0; + for(i = 0xFF; i != 0; i--) + { + } +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_gpio.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_gpio.c new file mode 100644 index 0000000000..999b8720b8 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_gpio.c @@ -0,0 +1,574 @@ +/** +****************************************************************************** +* @file HAL_gpio.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the GPIO firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_gpio.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup GPIO +* @brief GPIO driver modules +* @{ +*/ + +/** @defgroup GPIO_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Defines +* @{ +*/ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xFFFFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the GPIOx peripheral registers to their default +* reset values. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @retval : None +*/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + switch (*(uint32_t*)&GPIOx) + { + case GPIOA_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + break; + case GPIOB_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + break; + case GPIOC_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + break; + case GPIOD_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + break; + + default: + break; + } +} + +/** +* @brief Deinitializes the Alternate Functions (remap, event control +* and EXTI configuration) registers to their default reset +* values. +* @param None +* @retval : None +*/ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/** +* @brief Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* @retval : None +*/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + + /*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + /*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } + /*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/** +* @brief Fills each GPIO_InitStruct member with its default value. +* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** +* @brief Reads the specified input port pin. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* @retval : The input port pin value. +*/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** +* @brief Reads the specified GPIO input data port. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @retval : GPIO input data port value. +*/ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** +* @brief Reads the specified output data port bit. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* @retval : The output port pin value. +*/ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** +* @brief Reads the specified GPIO output data port. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @retval : GPIO output data port value. +*/ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** +* @brief Sets the selected data port bits. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bits to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* @retval : None +*/ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** +* @brief Clears the selected data port bits. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bits to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* @retval : None +*/ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** +* @brief Sets or clears the selected data port bit. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bit to be written. +* This parameter can be one of GPIO_Pin_x where x can be (0..15). +* @param BitVal: specifies the value to be written to the selected bit. +* This parameter can be one of the BitAction enum values: +* @arg Bit_RESET: to clear the port pin +* @arg Bit_SET: to set the port pin +* @retval : None +*/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** +* @brief Writes data to the specified GPIO data port. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param PortVal: specifies the value to be written to the port output +* data register. +* @retval : None +*/ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bit to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* @retval : None +*/ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** +* @brief Selects the GPIO pin used as Event output. +* @param GPIO_PortSource: selects the GPIO port to be used as source +* for Event output. +* This parameter can be GPIO_PortSourceGPIOx where x can be +* (A..E). +* @param GPIO_PinSource: specifies the pin for the Event output. +* This parameter can be GPIO_PinSourcex where x can be (0..15). +* @retval : None +*/ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->EVCR = tmpreg; +} + +/** +* @brief Enables or disables the Event Output. +* @param NewState: new state of the Event output. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; +} + +/** +* @brief Changes the mapping of the specified pin. +* @param GPIO_Remap: selects the pin to remap. +* This parameter can be one of the following values: +* @arg GPIO_Remap_SPI1 +* @arg GPIO_Remap_I2C1 +* @arg GPIO_Remap_UART1 +* @arg GPIO_Remap_UART2 +* @arg GPIO_PartialRemap_UART3 +* @arg GPIO_FullRemap_UART3 +* @arg GPIO_PartialRemap_TIM1 +* @arg GPIO_FullRemap_TIM1 +* @arg GPIO_PartialRemap1_TIM2 +* @arg GPIO_PartialRemap2_TIM2 +* @arg GPIO_FullRemap_TIM2 +* @arg GPIO_PartialRemap_TIM3 +* @arg GPIO_FullRemap_TIM3 +* @arg GPIO_Remap_TIM4 +* @arg GPIO_Remap1_CAN1 +* @arg GPIO_Remap2_CAN1 +* @arg GPIO_Remap_PD01 +* @arg GPIO_Remap_TIM5CH4_LSI +* @arg GPIO_Remap_ADC1_ETRGINJ +* @arg GPIO_Remap_ADC1_ETRGREG +* @arg GPIO_Remap_ADC2_ETRGINJ +* @arg GPIO_Remap_ADC2_ETRGREG +* @arg GPIO_Remap_SWJ_NoJTRST +* @arg GPIO_Remap_SWJ_JTAGDisable +* @arg GPIO_Remap_SWJ_Disable +* @param NewState: new state of the port pin remapping. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = AFIO->MAPR; + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + AFIO->MAPR = tmpreg; +} + +/** +* @brief Selects the GPIO pin used as EXTI Line. +* @param GPIO_PortSource: selects the GPIO port to be used as +* source for EXTI lines. +* This parameter can be GPIO_PortSourceGPIOx where x can be +* (A..G). +* @param GPIO_PinSource: specifies the EXTI line to be configured. +* This parameter can be GPIO_PinSourcex where x can be (0..15). +* @retval : None +*/ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_i2c.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_i2c.c new file mode 100644 index 0000000000..4e70f643a8 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_i2c.c @@ -0,0 +1,818 @@ +/** +****************************************************************************** +* @file HAL_i2c.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the I2C firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_i2c.h" +#include "HAL_rcc.h" + + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup I2C +* @brief I2C driver modules +* @{ +*/ + +/** @defgroup I2C_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Private_Defines +* @{ +*/ + +/*I2c Enable disable*/ +#define IC_ENABLE_Reset ((uint16_t)0xFFFE) +#define IC_ENABLE_Set ((uint16_t)0x0001) +#define IC_CON_RESET ((uint16_t)0xFE8A) +#define INTR_MASK ((uint16_t)0xC000) + +/*I2c DMA reset*/ +#define DMA_CR_TDMAE_RDMAE_Reset ((uint16_t)0xFFFC) + +/* I2C START mask */ +#define IC_CON_START_Set ((uint16_t)0x0020) +#define IC_CON_START_Reset ((uint16_t)0xFFDF) + +/* I2C STOP mask */ +#define IC_DATA_CMD_STOP_Set ((uint16_t)0x0200) +#define IC_DATA_CMD_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ADD2 mask */ +#define IC_TAR_Reset ((uint16_t)0xFF00) + +/* I2C IC_10BITADDR_MASTER bit mask */ +#define IC_TAR_ENDUAL_Set ((uint16_t)0x1000) +#define IC_TAR_ENDUAL_Reset ((uint16_t)0xEFFF) + +/* I2C SPECIALGC_OR_START bits mask */ +#define IC_TAR_GC_Set ((uint16_t)0x0800) +#define IC_TAR_GC_Reset ((uint16_t)0xF7FF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00793FFF) + + +static uint8_t I2C_CMD_DIR = 0; + +/*ӵûⲿʱҪ¸ñֵ*/ +uint16_t I2C_DMA_DIR = 0; + +/** +* @} +*/ + +/** @defgroup I2C_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the I2Cx peripheral registers to their default +* reset values. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @retval : None +*/ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + switch (*(uint32_t*)&I2Cx) + { + case I2C1_BASE: + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + break; + case I2C2_BASE: + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + break; + default: + break; + } +} + +/** +* @brief Initializes the I2Cx peripheral according to the specified +* parameters in the I2C_InitStruct. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that +* contains the configuration information for the specified +* I2C peripheral. +* @retval : None +*/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + + uint16_t tmpreg = 0; + uint32_t pclk1 = 8000000; + uint32_t minSclLowTime = 0; + uint32_t i2cPeriod = 0; + uint32_t pclk1Period = 0; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + /*---------------------------- I2Cx IC_ENABLE Configuration ------------------------*/ + /* Disable the selected I2C peripheral */ + I2Cx->IC_ENABLE &= IC_ENABLE_Reset; + + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + + /* Set pclk1 period value */ + pclk1Period = 1000000000 / pclk1; + + i2cPeriod = 1000000000 / I2C_InitStruct->I2C_ClockSpeed; //ns unit + tmpreg = 0; + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + minSclLowTime = 4700; //ns unit + tmpreg = minSclLowTime / pclk1Period; + /* Write to I2Cx IC_SS_SCL_LCNT */ + I2Cx->IC_SS_SCL_LCNT = tmpreg; + tmpreg = (i2cPeriod - pclk1Period * I2Cx->IC_SS_SCL_LCNT) / pclk1Period; + /* Write to I2Cx IC_SS_SCL_HCNT */ + I2Cx->IC_SS_SCL_HCNT = tmpreg; + + + } + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + /* Configure speed in fast mode */ + minSclLowTime = 1300; //ns unit + tmpreg = minSclLowTime / pclk1Period; + /* Write to I2Cx IC_FS_SCL_LCNT */ + I2Cx->IC_FS_SCL_LCNT = tmpreg; + tmpreg = (i2cPeriod - pclk1Period * I2Cx->IC_FS_SCL_LCNT) / pclk1Period; + /* Write to I2Cx IC_FS_SCL_HCNT */ + I2Cx->IC_FS_SCL_HCNT = tmpreg; + } + + /*Get the I2Cx IC_CON value */ + tmpreg = I2Cx->IC_CON; + /*Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/ + tmpreg &= IC_CON_RESET; + /*Set TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/ + tmpreg = TX_EMPTY_CTRL | IC_SLAVE_DISABLE | IC_RESTART_EN | IC_7BITADDR_MASTER | I2C_InitStruct->I2C_Speed | I2C_InitStruct->I2C_Mode; + /* Write to I2Cx IC_CON */ + I2Cx->IC_CON = tmpreg; + + /*---------------------------- I2Cx IC_INTR_MASK Configuration ------------------------*/ + /* Get the I2Cx IC_INTR_MASK value */ + tmpreg = I2Cx->IC_INTR_MASK; + /* clear the I2Cx IC_INTR_MASK value */ + tmpreg &= INTR_MASK; + /* Write to IC_INTR_MASK */ + I2Cx->IC_INTR_MASK = tmpreg; + + /* Write to IC_RX_TL */ + I2Cx->IC_RX_TL = 0x0; //rxfifo depth is 1 + /* Write to IC_TX_TL */ + I2Cx->IC_TX_TL = 0x1; //tcfifo depth is 1 + +} + +/** +* @brief Fills each I2C_InitStruct member with its default value. +* @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values ----------------*/ + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_MASTER; + /* Initialize the I2C_OwnAddress member */ + I2C_InitStruct->I2C_OwnAddress = 0xA8; + /* Initialize the I2C_Speed member */ + I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD; + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 100000; +} + +/** +* @brief Enables or disables the specified I2C peripheral. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2Cx peripheral. This parameter +* can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->IC_ENABLE |= IC_ENABLE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->IC_ENABLE &= IC_ENABLE_Reset; + } +} + +/** +* @brief Enables or disables the specified I2C DMA requests. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param DMA_Direcction : TDMAE_SET,RDMAE_SET +* This parameter can be any combination of the following values: +* @arg TDMAE_SET :DMA TX set +* @arg RDMAE_SET :DMA RX set +* @param NewState: new state of the I2C DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + if(I2C_DMA_DIR == TDMAE_SET) + { + /* Enable the selected I2C TX DMA requests */ + I2Cx->IC_DMA_CR |= TDMAE_SET; + } + else if(I2C_DMA_DIR == RDMAE_SET) + { + /* Enable the selected I2C TX DMA requests */ + I2Cx->IC_DMA_CR |= RDMAE_SET; + } + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->IC_DMA_CR &= DMA_CR_TDMAE_RDMAE_Reset; + } +} + + +/** +* @brief Generates I2Cx communication START condition. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2C START condition generation. +* This parameter can be: ENABLE or DISABLE. +* @retval : None. +*/ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->IC_CON |= IC_CON_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->IC_CON &= IC_CON_START_Reset; + } +} + +/** +* @brief Generates I2Cx communication STOP condition. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2C STOP condition generation. +* This parameter can be: ENABLE or DISABLE. +* @retval : None. +*/ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + u16 overTime = 3000; + I2Cx->IC_ENABLE |= 0x02; + while(I2Cx->IC_ENABLE & 0x02) + { + if(0 == overTime --) + { + break; + } + } + I2Cx->IC_CLR_TX_ABRT; +} + +/** +* @brief Configures the specified I2C own address2. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param Address: specifies the 7bit I2C own address2. +* @retval : None. +*/ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +//void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Get the old register value */ + tmpreg = I2Cx->IC_TAR; + /* Reset I2Cx Own address2 bit [7:0] */ + tmpreg &= IC_TAR_Reset; + /* Set I2Cx Own address2 */ + tmpreg |= Address >> 1; + /* Store the new register value */ + I2Cx->IC_TAR = tmpreg; +} + +/** +* @brief Enables or disables the specified I2C dual addressing mode. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2C dual addressing mode. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->IC_TAR |= IC_TAR_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->IC_TAR &= IC_TAR_ENDUAL_Reset; + } +} + +/** +* @brief Enables or disables the specified I2C general call feature. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2C General call. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->IC_TAR |= IC_TAR_GC_Set; + } + else + { + /* Disable generall call */ + I2Cx->IC_TAR &= IC_TAR_GC_Reset; + } +} + +/** +* @brief Enables or disables the specified I2C interrupts. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_IT: specifies the I2C interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt mask +* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask +* @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask +* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask +* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask +* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask +* @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode) +* @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode) +* @arg I2C_IT_ACTIVITY : I2C activity interrupt mask +* @arg I2C_IT_STOP_DET : stop condition interrupt mask +* @arg I2C_IT_START_DET : start condition interrupt mask +* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask +* @param NewState: new state of the specified I2C interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if(I2C_IT == I2C_IT_RX_FULL) + { + I2Cx->IC_DATA_CMD = CMD_READ; + } + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->IC_INTR_MASK |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT; + } +} + +/** +* @brief Sends a data byte through the I2Cx peripheral. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param Data: Byte to be transmitted.. +* @retval : None +*/ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the IC_DATA_CMD register the data to be sent */ + I2Cx->IC_DATA_CMD = CMD_WRITE | Data; +} + +/** +* @brief Returns the most recent received data by the I2Cx peripheral. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @retval : The value of the received data. + +*/ +void I2C_ReadCmd(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + I2Cx->IC_DATA_CMD = CMD_READ; +} + +/** +* @brief Returns the most recent received data by the I2Cx peripheral. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @retval : The value of the received data. +*/ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + I2C_CMD_DIR = 0; + /* Return the data in the IC_DATA_CMD register */ + return (uint8_t)I2Cx->IC_DATA_CMD; +} + +/** +* @brief Transmits the address byte to select the slave device. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param Address: specifies the slave address which will be transmitted +* @param I2C_Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. +* This parameter can be one of the following values +* @arg I2C_Direction_Transmitter: Transmitter mode +* @arg I2C_Direction_Receiver: Receiver mode +* @retval : None. +*/ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Store the new register value */ + I2Cx->IC_TAR = Address >> 1; +} + +/** +* @brief Reads the specified I2C register and returns its value. +* @param I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* @retval : The value of the read register. +*/ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + /* Return the selected register value */ + return (*(__IO uint16_t *)(*((__IO uint32_t *)&I2Cx) + I2C_Register)); +} + +/** +* @brief Returns the last I2Cx Event. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @retval : The last event +*/ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Read the I2Cx status register */ + flag1 = I2Cx->IC_RAW_INTR_STAT; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 ) & FLAG_Mask; + /* Return status */ + return lastevent; +} + + + +/** +* @brief Checks whether the last I2Cx Event is equal to the one passed +* as parameter. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_EVENT: specifies the event to be checked. +* This parameter can be one of the following values: +* @arg I2C_EVENT_RX_UNDER: Rx Buffer is empty event +* @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event +* @arg I2C_EVENTT_RX_FULL : Rx buffer full event +* @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event +* @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event +* @arg I2C_EVENT_RD_REQ : I2C work as slave or master event +* @arg I2C_EVENT_TX_ABRT : TX error event(Master mode) +* @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode) +* @arg I2C_EVENT_ACTIVITY : I2C activity event +* @arg I2C_EVENT_STOP_DET : stop condition event +* @arg I2C_EVENT_START_DET : start condition event +* @arg I2C_EVENT_GEN_CALL : a general call address and ack event +* - SUCCESS: Last event is equal to the I2C_EVENT +* - ERROR: Last event is different from the I2C_EVENT +*/ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0; + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + if((I2C_EVENT == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0)) + { + I2Cx->IC_DATA_CMD = CMD_READ; + I2C_CMD_DIR = 1; + } + /* Read the I2Cx status register */ + flag1 = I2Cx->IC_RAW_INTR_STAT; + //flag1 = I2Cx->IC_INTR_STAT; + /* Get the last event value from I2C status register */ + lastevent = (flag1 ) & I2C_EVENT; + + /* Check whether the last event is equal to I2C_EVENT */ + if (lastevent == I2C_EVENT ) + //if((I2Cx->IC_RAW_INTR_STAT & I2C_EVENT) != (uint32_t)RESET) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; + +} + +/** +* @brief Checks whether the specified I2C flag is set or not. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg I2C_FLAG_RX_UNDER: Rx Buffer is empty flag +* @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag +* @arg I2C_FLAG_RX_FULL : Rx buffer full flag +* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag +* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag +* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag +* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) +* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) +* @arg I2C_FLAG_ACTIVITY: I2C activity flag +* @arg I2C_FLAG_STOP_DET: stop condition flag +* @arg I2C_FLAG_START_DET: start condition flag +* @arg I2C_FLAG_GEN_CALL : a general call address and ack flag +* @retval : The new state of I2C_FLAG (SET or RESET). +*/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + if(I2C_FLAG & 0x8000) + { + if((I2Cx->IC_STATUS & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + } + else + { + if((I2C_FLAG == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0)) + { + I2Cx->IC_DATA_CMD = CMD_READ; + I2C_CMD_DIR = 1; + } + /* Check the status of the specified I2C flag */ + if((I2Cx->IC_RAW_INTR_STAT & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** +* @brief Clears the I2Cx's pending flags. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* @arg I2C_FLAG_RX_UNDER: Rx Buffer is empty flag +* @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag +* @arg I2C_FLAG_RX_FULL : Rx buffer full flag +* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag +* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag +* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag +* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) +* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) +* @arg I2C_FLAG_ACTIVITY: I2C activity flag +* @arg I2C_FLAG_STOP_DET: stop condition flag +* @arg I2C_FLAG_START_DET: start condition flag +* @arg I2C_FLAG_GEN_CALL : a general call address and ack flag +* @retval : None +*/ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + + if((I2C_FLAG & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER) {I2Cx->IC_CLR_RX_UNDER;} + if((I2C_FLAG & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER) {I2Cx->IC_CLR_RX_OVER;} + if((I2C_FLAG & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER) {I2Cx->IC_CLR_TX_OVER;} + if((I2C_FLAG & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ) {I2Cx->IC_CLR_RD_REQ;} + if((I2C_FLAG & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT) {I2Cx->IC_CLR_TX_ABRT;} + if((I2C_FLAG & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE) {I2Cx->IC_CLR_RX_DONE;} + if((I2C_FLAG & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY) {I2Cx->IC_CLR_ACTIVITY;} + if((I2C_FLAG & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET) {I2Cx->IC_CLR_STOP_DET;} + if((I2C_FLAG & I2C_FLAG_START_DET) == I2C_FLAG_START_DET) {I2Cx->IC_CLR_START_DET;} + if((I2C_FLAG & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL) {I2Cx->IC_CLR_GEN_CALL;} +} + +/** +* @brief Checks whether the specified I2C interrupt has occurred or not. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt +* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt +* @arg I2C_IT_RX_FULL : Rx buffer full interrupt +* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt +* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt +* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt +* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) +* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) +* @arg I2C_IT_ACTIVITY : I2C activity interrupt +* @arg I2C_IT_STOP_DET : stop condition interrupt +* @arg I2C_IT_START_DET : start condition interrupt +* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt +* @retval : The new state of I2C_IT (SET or RESET). +*/ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check the status of the specified I2C flag */ + if((I2Cx->IC_RAW_INTR_STAT & I2C_IT) != (uint32_t)RESET) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + + /* Return the I2C_IT status */ + return bitstatus; +} + +/** +* @brief Clears the I2Cx interrupt pending bits. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt +* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt +* @arg I2C_IT_RX_FULL : Rx buffer full interrupt +* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt +* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt +* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt +* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) +* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) +* @arg I2C_IT_ACTIVITY : I2C activity interrupt +* @arg I2C_IT_STOP_DET : stop condition interrupt +* @arg I2C_IT_START_DET : start condition interrupt +* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt +* @retval : None +*/ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + if((I2C_IT & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER) {I2Cx->IC_CLR_RX_UNDER;} + if((I2C_IT & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER) {I2Cx->IC_CLR_RX_OVER;} + if((I2C_IT & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER) {I2Cx->IC_CLR_TX_OVER;} + if((I2C_IT & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ) {I2Cx->IC_CLR_RD_REQ;} + if((I2C_IT & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT) {I2Cx->IC_CLR_TX_ABRT;} + if((I2C_IT & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE) {I2Cx->IC_CLR_RX_DONE;} + if((I2C_IT & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY) {I2Cx->IC_CLR_ACTIVITY;} + if((I2C_IT & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET) {I2Cx->IC_CLR_STOP_DET;} + if((I2C_IT & I2C_IT_START_DET) == I2C_FLAG_START_DET) {I2Cx->IC_CLR_START_DET;} + if((I2C_IT & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL) {I2Cx->IC_CLR_GEN_CALL;} +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_iwdg.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_iwdg.c new file mode 100644 index 0000000000..4999a96e30 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_iwdg.c @@ -0,0 +1,194 @@ +/** +****************************************************************************** +* @file HAL_iwdg.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the IWDG firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_iwdg.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup IWDG +* @brief IWDG driver modules +* @{ +*/ + +/** @defgroup IWDG_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Private_Defines +* @{ +*/ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** +* @} +*/ + +/** @defgroup IWDG_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Private_Functions +* @{ +*/ + +/** +* @brief Enables or disables write access to IWDG_PR and IWDG_RLR +* registers. +* @param IWDG_WriteAccess: new state of write access to IWDG_PR and +* IWDG_RLR registers. +* This parameter can be one of the following values: +* @arg IWDG_WriteAccess_Enable: Enable write access to +* IWDG_PR and IWDG_RLR registers +* @arg IWDG_WriteAccess_Disable: Disable write access to +* IWDG_PR and IWDG_RLR registers +* @retval : None +*/ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** +* @brief Sets IWDG Prescaler value. +* @param IWDG_Prescaler: specifies the IWDG Prescaler value. +* This parameter can be one of the following values: +* @arg IWDG_Prescaler_4: IWDG prescaler set to 4 +* @arg IWDG_Prescaler_8: IWDG prescaler set to 8 +* @arg IWDG_Prescaler_16: IWDG prescaler set to 16 +* @arg IWDG_Prescaler_32: IWDG prescaler set to 32 +* @arg IWDG_Prescaler_64: IWDG prescaler set to 64 +* @arg IWDG_Prescaler_128: IWDG prescaler set to 128 +* @arg IWDG_Prescaler_256: IWDG prescaler set to 256 +* @retval : None +*/ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** +* @brief Sets IWDG Reload value. +* @param Reload: specifies the IWDG Reload value. +* This parameter must be a number between 0 and 0x0FFF. +* @retval : None +*/ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** +* @brief Reloads IWDG counter with value defined in the reload register +* (write access to IWDG_PR and IWDG_RLR registers disabled). +* @param None +* @retval : None +*/ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** +* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers +* disabled). +* @param None +* @retval : None +*/ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** +* @brief Checks whether the specified IWDG flag is set or not. +* @param IWDG_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg IWDG_FLAG_PVU: Prescaler Value Update on going +* @arg IWDG_FLAG_RVU: Reload Value Update on going +* @retval : The new state of IWDG_FLAG (SET or RESET). +*/ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_misc.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_misc.c new file mode 100644 index 0000000000..d56238252d --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_misc.c @@ -0,0 +1,217 @@ +/** +****************************************************************************** +* @file HAL_misc.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the miscellaneous firmware functions (add-on +* to CMSIS functions). +****************************************************************************** +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_misc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup MISC +* @brief MISC driver modules +* @{ +*/ + +/** @defgroup MISC_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Private_Defines +* @{ +*/ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** +* @} +*/ + +/** @defgroup MISC_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Private_Functions +* @{ +*/ + +/** +* @brief Configures the priority grouping: pre-emption priority and subpriority. +* @param NVIC_PriorityGroup: specifies the priority grouping bits length. +* This parameter can be one of the following values: +* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority +* 4 bits for subpriority +* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority +* 3 bits for subpriority +* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority +* 2 bits for subpriority +* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority +* 1 bits for subpriority +* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority +* 0 bits for subpriority +* @retval None +*/ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** +* @brief Initializes the NVIC peripheral according to the specified +* parameters in the NVIC_InitStruct. +* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains +* the configuration information for the specified NVIC peripheral. +* @retval None +*/ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + + tmppre = NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05]; +} + +/** +* @brief Sets the vector table location and Offset. +* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. +* This parameter can be one of the following values: +* @arg NVIC_VectTab_RAM +* @arg NVIC_VectTab_FLASH +* @param Offset: Vector Table base offset field. This value must be a multiple +* of 0x200. +* @retval None +*/ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** +* @brief Selects the condition for the system to enter low power mode. +* @param LowPowerMode: Specifies the new mode for the system to enter low power mode. +* This parameter can be one of the following values: +* @arg NVIC_LP_SEVONPEND +* @arg NVIC_LP_SLEEPDEEP +* @arg NVIC_LP_SLEEPONEXIT +* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** +* @brief Configures the SysTick clock source. +* @param SysTick_CLKSource: specifies the SysTick clock source. +* This parameter can be one of the following values: +* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. +* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. +* @retval None +*/ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_pwr.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_pwr.c new file mode 100644 index 0000000000..da846c618c --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_pwr.c @@ -0,0 +1,346 @@ +/** +****************************************************************************** +* @file HAL_pwr.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the PWR firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_pwr.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup PWR +* @brief PWR driver modules +* @{ +*/ + +/** @defgroup PWR_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Private_Defines +* @{ +*/ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_PDDS_Set ((uint32_t)0x00000002) +#define CR_DS_Mask ((uint32_t)0xFFFFFFFC) +#define CR_CWUF_Set ((uint32_t)0x00000004) +#define CR_PLS_Mask ((uint32_t)0xFFFFE1FF) + +/* --------- Cortex System Control register bit mask ---------------- */ + +/* Cortex System Control register address */ +#define SCB_SysCtrl ((uint32_t)0xE000ED10) + +/* SLEEPDEEP bit mask */ +#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) +/** +* @} +*/ + +/** @defgroup PWR_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the PWR peripheral registers to their default +* reset values. +* @param None +* @retval : None +*/ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** +* @brief Enables or disables access to the RTC and backup registers. +* @param NewState: new state of the access to the RTC and backup +* registers. This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + //*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; + if(NewState != DISABLE) + { + PWR->CR |= 0x00000100; + } + else + { + PWR->CR &= 0xfffffeff; + } + +} + +/** +* @brief Enables or disables the Power Voltage Detector(PVD). +* @param NewState: new state of the PVD. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState == ENABLE) + { + PWR->CR |= 0x00000010; + } + else + { + PWR->CR &= 0xffffffef; + } + +} + +/** +* @brief Configures the voltage threshold detected by the Power Voltage +* Detector(PVD). +* @param PWR_PVDLevel: specifies the PVD detection level +* This parameter can be one of the following values: +* @arg PWR_PVDLevel_1V8: PVD detection level set to 2.8V +* @arg PWR_PVDLevel_2V1: PVD detection level set to 2.1V +* @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V +* @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V +* @arg PWR_PVDLevel_3V0: PVD detection level set to 3.0V +* @arg PWR_PVDLevel_3V3: PVD detection level set to 3.3V +* @arg PWR_PVDLevel_3V6: PVD detection level set to 3.6V +* @arg PWR_PVDLevel_3V9: PVD detection level set to 3.9V +* @arg PWR_PVDLevel_4V2: PVD detection level set to 4.2V +* @arg PWR_PVDLevel_4V5: PVD detection level set to 4.5V +* @arg PWR_PVDLevel_4V8: PVD detection level set to 4.8V +* @retval : None +*/ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[12:9] bits */ + tmpreg &= CR_PLS_Mask; + /* Set PLS[12:9] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** +* @brief Enables or disables the WakeUp Pin functionality. +* @param NewState: new state of the WakeUp Pin functionality. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + PWR->CSR |= 0x00000100; + } + else + { + PWR->CSR &= 0xfffffeff; + } +} + +/** +* @brief Enters STOP mode. +* @param PWR_Regulator: specifies the regulator state in STOP mode. +* This parameter can be one of the following values: +* @arg PWR_Regulator_ON: STOP mode with regulator ON +* @arg PWR_Regulator_LowPower: STOP mode with +* regulator in low power mode +* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or +* WFE instruction. +* This parameter can be one of the following values: +* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction +* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction +* @retval : None +*/ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_Mask; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + SCB->SCR |= SysCtrl_SLEEPDEEP_Set; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } +} + +/** +* @brief Enters STANDBY mode. +* @param None +* @retval : None +*/ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= CR_CWUF_Set; + /* Select STANDBY mode */ + PWR->CR |= CR_PDDS_Set; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + SCB->SCR |= SysCtrl_SLEEPDEEP_Set; + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** +* @brief Checks whether the specified PWR flag is set or not. +* @param PWR_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg PWR_FLAG_WU: Wake Up flag +* @arg PWR_FLAG_SB: StandBy flag +* @arg PWR_FLAG_PVDO: PVD Output +* @retval : The new state of PWR_FLAG (SET or RESET). +*/ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** +* @brief Clears the PWR's pending flags. +* @param PWR_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* @arg PWR_FLAG_WU: Wake Up flag +* @arg PWR_FLAG_SB: StandBy flag +* @retval : None +*/ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rcc.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rcc.c new file mode 100644 index 0000000000..d17fc6a445 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rcc.c @@ -0,0 +1,1149 @@ +/** +****************************************************************************** +* @file HAL_rcc.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the RCC firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup RCC +* @brief RCC driver modules +* @{ +*/ + +/** @defgroup RCC_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Private_Defines +* @{ +*/ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) +#define USBPRE_BitNumber 0x16 +#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +#ifndef HSEStartUp_TimeOut +/* Time out for HSE start up */ +#define HSEStartUp_TimeOut ((uint16_t)0x0500) +#endif + +/** +* @} +*/ + +/** @defgroup RCC_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Private_Variables +* @{ +*/ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** +* @} +*/ + +/** @defgroup RCC_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Private_Functions +* @{ +*/ + +/** +* @brief Resets the RCC clock configuration to the default reset state. +* @param None +* @retval : None +*/ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FF0000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** +* @brief Configures the External High Speed oscillator (HSE). +* HSE can not be stopped if it is used directly or through the +* PLL as system clock. +* @param RCC_HSE: specifies the new state of the HSE. +* This parameter can be one of the following values: +* @arg RCC_HSE_OFF: HSE oscillator OFF +* @arg RCC_HSE_ON: HSE oscillator ON +* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external +* clock +* @retval : None +*/ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** +* @brief Waits for HSE start-up. +* @param None +* @retval : An ErrorStatus enumuration value: +* - SUCCESS: HSE oscillator is stable and ready to use +* - ERROR: HSE oscillator not yet ready +*/ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } + while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut)); + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** +* @brief Adjusts the Internal High Speed oscillator (HSI) calibration +* value. +* @param HSICalibrationValue: specifies the calibration trimming value. +* This parameter must be a number between 0 and 0x1F. +* @retval : None +*/ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** +* @brief Enables or disables the Internal High Speed oscillator (HSI). +* HSI can not be stopped if it is used directly or through the +* PLL as system clock. +* @param NewState: new state of the HSI. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState == ENABLE) + { + RCC->CR |= 0x01; + } + else + { + RCC->CR &= 0xfffffffe; + } +} +/** +* @brief Configures the PLL clock source and DM DN factor. +* This function must be used only when the PLL is disabled. +* @param RCC_PLLSource: specifies the PLL entry clock source. +* This parameter can be one of the following values: +* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided +* by 2 selected as PLL clock entry +* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected +* as PLL clock entry +* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided +* by 2 selected as PLL clock entry +* @param RCC_PLLDN: specifies the PLL multiplication factor. +* This parameter can be RCC_PLLMul_x where x:[31:26] +* @param RCC_PLLDM: specifies the PLL Divsior factor. +* This parameter can be RCC_Divsior_x where x:[22:20] +* @retval : None +*/ +void RCC_PLLDMDNConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLDN, uint32_t RCC_PLLDM) +{ + uint32_t tmpreg0 = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + tmpreg0 = RCC->CR; + + /* Clear PLLDN, PLLDM bits */ + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg0 &= 0x038fffff; + + /* Set the PLL configuration bits */ + tmpreg0 |= (RCC_PLLDN << 26) | (RCC_PLLDM << 20); + + RCC->CR = tmpreg0; +} + + +/** +* @brief Configures the PLL clock source and multiplication factor. +* This function must be used only when the PLL is disabled. +* @param RCC_PLLSource: specifies the PLL entry clock source. +* This parameter can be one of the following values: +* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided +* by 2 selected as PLL clock entry +* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected +* as PLL clock entry +* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided +* by 2 selected as PLL clock entry +* @param RCC_PLLMul: specifies the PLL multiplication factor. +* This parameter can be RCC_PLLMul_x where x:[31:26][22:20] +* @retval : None +*/ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource; + /* Store the new value */ + RCC->CFGR = tmpreg; + + if(RCC_PLLMul == RCC_PLLMul_2) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000003); //Frclk*8/4 + } + if(RCC_PLLMul == RCC_PLLMul_3) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000005, 0x00000001);//Frclk*6/2 + } + if(RCC_PLLMul == RCC_PLLMul_4) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000001);//Frclk*8/2 + } + if(RCC_PLLMul == RCC_PLLMul_5) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000009, 0x00000001);//Frclk*10/2 + } + if(RCC_PLLMul == RCC_PLLMul_6) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000B, 0x00000001);//Frclk*12/2 + } + if(RCC_PLLMul == RCC_PLLMul_7) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000D, 0x00000001);//Frclk*14/2 + } + if(RCC_PLLMul == RCC_PLLMul_8) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000F, 0x00000001);//Frclk*16/2 + } + if(RCC_PLLMul == RCC_PLLMul_9) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000011, 0x00000001);//Frclk*18/2 + } + if(RCC_PLLMul == RCC_PLLMul_10) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000001);//Frclk*20/2 + } + if(RCC_PLLMul == RCC_PLLMul_11) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000015, 0x00000001);//Frclk*22/2 + } + if(RCC_PLLMul == RCC_PLLMul_12) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000017, 0x00000001);//Frclk*24/2 + } + if(RCC_PLLMul == RCC_PLLMul_13) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000019, 0x00000001);//Frclk*26/2 + } + if(RCC_PLLMul == RCC_PLLMul_14) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000001B, 0x00000001);//Frclk*28/2 + } + if(RCC_PLLMul == RCC_PLLMul_15) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000001D, 0x00000001);//Frclk*30/2 + } + if(RCC_PLLMul == RCC_PLLMul_16) + { + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000001F, 0x00000001);//Frclk*32/2 + } +} + + +/** +* @brief Enables or disables the PLL. +* The PLL can not be disabled if it is used as system clock. +* @param NewState: new state of the PLL. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= 0x01000000; + } + else + { + RCC->CR &= 0xfeffffff; + } +} + +/** +* @brief Configures the system clock (SYSCLK). +* @param RCC_SYSCLKSource: specifies the clock source used as system +* clock. This parameter can be one of the following values: +* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock +* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock +* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock +* @retval : None +*/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Returns the clock source used as system clock. +* @param None +* @retval : The clock source used as system clock. The returned value can +* be one of the following: +* - 0x00: HSI/6 used as system clock +* - 0x04: HSE used as system clock +* - 0x08: PLL used as system clock +*/ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** +* @brief Configures the AHB clock (HCLK). +* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from +* the system clock (SYSCLK). +* This parameter can be one of the following values: +* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK +* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 +* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 +* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 +* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 +* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 +* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 +* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 +* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 +* @retval : None +*/ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Configures the Low Speed APB clock (PCLK1). +* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from +* the AHB clock (HCLK). +* This parameter can be one of the following values: +* @arg RCC_HCLK_Div1: APB1 clock = HCLK +* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 +* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 +* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 +* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 +* @retval : None +*/ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Configures the High Speed APB clock (PCLK2). +* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from +* the AHB clock (HCLK). +* This parameter can be one of the following values: +* @arg RCC_HCLK_Div1: APB2 clock = HCLK +* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 +* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 +* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 +* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 +* @retval : None +*/ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Enables or disables the specified RCC interrupts. +* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. +* This parameter can be any combination of the following values: +* @arg RCC_IT_LSIRDY: LSI ready interrupt +* @arg RCC_IT_LSERDY: LSE ready interrupt +* @arg RCC_IT_HSIRDY: HSI ready interrupt +* @arg RCC_IT_HSERDY: HSE ready interrupt +* @arg RCC_IT_PLLRDY: PLL ready interrupt +* @param NewState: new state of the specified RCC interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */ + RCC->CIR &= ~((uint32_t)0x1f) << 8; + RCC->CIR |= ((uint32_t)RCC_IT) << 8; + } + else + { + /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */ + RCC->CIR &= ~((uint32_t)RCC_IT << 8); + } +} + +/** +* @brief Configures the USB clock (USBCLK). +* @param RCC_USBCLKSource: specifies the USB clock source. This clock is +* derived from the PLL output. +* This parameter can be one of the following values: +* @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB +* clock source +* @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source +* @retval : None +*/ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + RCC->CFGR &= ~(3 << 22); + RCC->CFGR |= RCC_USBCLKSource << 22; +} + +/** +* @brief Configures the ADC clock (ADCCLK). +* @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from +* the APB2 clock (PCLK2). +* This parameter can be one of the following values: +* @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 +* @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 +* @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 +* @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 +* @retval : None +*/ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Configures the External Low Speed oscillator (LSE). +* @param RCC_LSE: specifies the new state of the LSE. +* This parameter can be one of the following values: +* @arg RCC_LSE_OFF: LSE oscillator OFF +* @arg RCC_LSE_ON: LSE oscillator ON +* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external +* clock +* @retval : None +*/ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + RCC->BDCR |= RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + RCC->BDCR |= RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** +* @brief Enables or disables the Internal Low Speed oscillator (LSI). +* LSI can not be disabled if the IWDG is running. +* @param NewState: new state of the LSI. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CSR |= 0x00000001; + } + else + { + RCC->CSR &= 0xfffffffe; + } +} + +/** +* @brief Configures the RTC clock (RTCCLK). +* Once the RTC clock is selected it cant be changed unless the +* Backup domain is reset. +* @param RCC_RTCCLKSource: specifies the RTC clock source. +* This parameter can be one of the following values: +* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock +* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock +* @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 +* selected as RTC clock +* @retval : None +*/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** +* @brief Enables or disables the RTC clock. +* This function must be used only after the RTC clock was +* selected using the RCC_RTCCLKConfig function. +* @param NewState: new state of the RTC clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= 0x00008000; + } + else + { + RCC->BDCR &= 0xffff7fff; + } +} + +/** +* @brief Returns the frequencies of different on chip clocks. +* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which +* will hold the clocks frequencies. +* @retval : None +*/ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull1 = 0, pllmull2 = 0, pllsource = 0, presc = 0; + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_Value; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + //pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + //pllmull = ( pllmull >> 18) + 2; + pllmull1 = ((RCC->CR & 0xfc000000) >> 26) + 1; + pllmull2 = ((RCC->CR & 0x00700000) >> 20) + 1; + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = 2 * (HSI_Value_Pll_ON >> 1) * pllmull1 / pllmull2; + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) + { + /* HSE oscillator clock divided by 2 */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull1 / pllmull2; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull1 / pllmull2; + } + } + break; + default: + RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF; + break; + } + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** +* @brief Enables or disables the AHB peripheral clock. +* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. +* This parameter can be any combination of the following values: +* @arg RCC_AHBPeriph_DMA1 +* @arg RCC_AHBPeriph_DMA2 +* @arg RCC_AHBPeriph_SRAM +* @arg RCC_AHBPeriph_FLITF +* @arg RCC_AHBPeriph_CRC +* @arg RCC_AHBPeriph_FSMC +* @arg RCC_AHBPeriph_SDIO +* SRAM and FLITF clock can be disabled only during sleep mode. +* @param NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** +* @brief Enables or disables the High Speed APB (APB2) peripheral clock. +* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, +* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, +* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, +* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, +* RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1, +* RCC_APB2Periph_ALL +* @param NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** +* @brief Enables or disables the Low Speed APB (APB1) peripheral clock. +* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, +* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, +* RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4, +* RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, +* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL +* @param NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** +* @brief Forces or releases High Speed APB (APB2) peripheral reset. +* @param RCC_APB2Periph: specifies the APB2 peripheral to reset. +* This parameter can be any combination of the following values: +* @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, +* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_ADC1, +* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, +* RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1, RCC_APB2Periph_ADC3, +* RCC_APB2Periph_ALL +* @param NewState: new state of the specified peripheral reset. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** +* @brief Forces or releases Low Speed APB (APB1) peripheral reset. +* @param RCC_APB1Periph: specifies the APB1 peripheral to reset. +* This parameter can be any combination of the following values: +* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, +* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, +* RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4, +* RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, +* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL +* @param NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** +* @brief Forces or releases the Backup domain reset. +* @param NewState: new state of the Backup domain reset. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** +* @brief Enables or disables the Clock Security System. +* @param NewState: new state of the Clock Security System.. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** +* @brief Selects the clock source to output on MCO pin. +* @param RCC_MCO: specifies the clock source to output. +* This parameter can be one of the following values: +* @arg RCC_MCO_NoClock: No clock selected +* @arg RCC_MCO_SYSCLK: System clock selected +* @arg RCC_MCO_HSI: HSI oscillator clock selected +* @arg RCC_MCO_HSE: HSE oscillator clock selected +* @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected +* @retval : None +*/ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + /* Perform Byte access to MCO[2:0] bits to select the MCO source */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/** +* @brief Checks whether the specified RCC flag is set or not. +* @param RCC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready +* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready +* @arg RCC_FLAG_PLLRDY: PLL clock ready +* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready +* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready +* @arg RCC_FLAG_PINRST: Pin reset +* @arg RCC_FLAG_PORRST: POR/PDR reset +* @arg RCC_FLAG_SFTRST: Software reset +* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset +* @arg RCC_FLAG_WWDGRST: Window Watchdog reset +* @arg RCC_FLAG_LPWRRST: Low Power reset +* @retval : The new state of RCC_FLAG (SET or RESET). +*/ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** +* @brief Clears the RCC reset flags. +* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, +* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, +* RCC_FLAG_LPWRRST +* @param None +* @retval : None +*/ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** +* @brief Checks whether the specified RCC interrupt has occurred or not. +* @param RCC_IT: specifies the RCC interrupt source to check. +* This parameter can be one of the following values: +* @arg RCC_IT_LSIRDY: LSI ready interrupt +* @arg RCC_IT_LSERDY: LSE ready interrupt +* @arg RCC_IT_HSIRDY: HSI ready interrupt +* @arg RCC_IT_HSERDY: HSE ready interrupt +* @arg RCC_IT_PLLRDY: PLL ready interrupt +* @arg RCC_IT_CSS: Clock Security System interrupt +* @retval : The new state of RCC_IT (SET or RESET). +*/ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** +* @brief Clears the RCCs interrupt pending bits. +* @param RCC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* @arg RCC_IT_LSIRDY: LSI ready interrupt +* @arg RCC_IT_LSERDY: LSE ready interrupt +* @arg RCC_IT_HSIRDY: HSI ready interrupt +* @arg RCC_IT_HSERDY: HSE ready interrupt +* @arg RCC_IT_PLLRDY: PLL ready interrupt +* @arg RCC_IT_CSS: Clock Security System interrupt +* @retval : None +*/ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + + RCC->CIR |= (uint32_t)RCC_IT << 16; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rtc.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rtc.c new file mode 100644 index 0000000000..dae87cdf58 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rtc.c @@ -0,0 +1,339 @@ +/** +****************************************************************************** +* @file HAL_rtc.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the RTC firmware functions. +****************************************************************************** +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_rtc.h" + +/** @addtogroup +* @{ +*/ + +/** @defgroup RTC +* @brief RTC driver modules +* @{ +*/ + +/** @defgroup RTC_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + +/** @defgroup RTC_Private_Defines +* @{ +*/ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ + +/** +* @} +*/ + +/** @defgroup RTC_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RTC_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RTC_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RTC_Private_Functions +* @{ +*/ + +/** +* @brief Enables or disables the specified RTC interrupts. +* @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. +* This parameter can be any combination of the following values: +* @arg RTC_IT_OW: Overflow interrupt +* @arg RTC_IT_ALR: Alarm interrupt +* @arg RTC_IT_SEC: Second interrupt +* @param NewState: new state of the specified RTC interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (uint16_t)~RTC_IT; + } +} + +/** +* @brief Enters the RTC configuration mode. +* @param None +* @retval None +*/ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= RTC_CRL_CNF; +} + +/** +* @brief Exits from the RTC configuration mode. +* @param None +* @retval None +*/ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); +} + +/** +* @brief Gets the RTC counter value. +* @param None +* @retval RTC counter value. +*/ +uint32_t RTC_GetCounter(void) +{ + uint16_t tmp = 0; + tmp = RTC->CNTL; + return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; +} + +/** +* @brief Sets the RTC counter value. +* @param CounterValue: RTC counter new value. +* @retval None +*/ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** +* @brief Sets the RTC prescaler value. +* @param PrescalerValue: RTC prescaler new value. +* @retval None +*/ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** +* @brief Sets the RTC alarm value. +* @param AlarmValue: RTC alarm new value. +* @retval None +*/ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** +* @brief Gets the RTC divider value. +* @param None +* @retval RTC Divider value. +*/ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/** +* @brief Waits until last write operation on RTC registers has finished. +* @note This function must be called before any write to RTC registers. +* @param None +* @retval None +*/ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/** +* @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) +* are synchronized with RTC APB clock. +* @note This function must be called before any read operation after an APB reset +* or an APB clock stop. +* @param None +* @retval None +*/ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/** +* @brief Checks whether the specified RTC flag is set or not. +* @param RTC_FLAG: specifies the flag to check. +* This parameter can be one the following values: +* @arg RTC_FLAG_RTOFF: RTC Operation OFF flag +* @arg RTC_FLAG_RSF: Registers Synchronized flag +* @arg RTC_FLAG_OW: Overflow flag +* @arg RTC_FLAG_ALR: Alarm flag +* @arg RTC_FLAG_SEC: Second flag +* @retval The new state of RTC_FLAG (SET or RESET). +*/ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the RTC's pending flags. +* @param RTC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after +* an APB reset or an APB Clock stop. +* @arg RTC_FLAG_OW: Overflow flag +* @arg RTC_FLAG_ALR: Alarm flag +* @arg RTC_FLAG_SEC: Second flag +* @retval None +*/ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the corresponding RTC flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG; +} + +/** +* @brief Checks whether the specified RTC interrupt has occurred or not. +* @param RTC_IT: specifies the RTC interrupts sources to check. +* This parameter can be one of the following values: +* @arg RTC_IT_OW: Overflow interrupt +* @arg RTC_IT_ALR: Alarm interrupt +* @arg RTC_IT_SEC: Second interrupt +* @retval The new state of the RTC_IT (SET or RESET). +*/ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the RTC's interrupt pending bits. +* @param RTC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* @arg RTC_IT_OW: Overflow interrupt +* @arg RTC_IT_ALR: Alarm interrupt +* @arg RTC_IT_SEC: Second interrupt +* @retval None +*/ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the corresponding RTC pending bit */ + RTC->CRL &= (uint16_t)~RTC_IT; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_spi.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_spi.c new file mode 100644 index 0000000000..f02e9c4516 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_spi.c @@ -0,0 +1,693 @@ +/** +****************************************************************************** +* @file HAL_spi.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the SPI firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_spi.h" + + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup SPI +* @brief SPI driver modules +* @{ +*/ + +/** @defgroup SPI_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup SPI_Private_Defines +* @{ +*/ + + + +/* SPI SPIENE mask */ +#define GCTL_SPIEN_Set ((uint16_t)0x0001) +#define GCTL_SPIEN_Reset ((uint16_t)0xFFFE) +/* SPI registers Masks */ +#define GCTL_CLEAR_Mask ((uint16_t)0xF000) +#define CCTL_CLEAR_Mask ((uint16_t)0xFFC0) +#define SPBRG_CLEAR_Mask ((uint16_t)0x0000) +#define SPI_DataSize_Mask ((uint16_t)0xFCFF) +/** +* @} +*/ + +/** @defgroup SPI_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the SPIx peripheral registers to their default +* reset values . +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @retval : None +*/ +void SPI_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + switch (*(uint32_t*)&SPIx) + { + case SPI1_BASE: + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + break; + case SPI2_BASE: + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + break; + + + default: + break; + } +} + +/** +* @brief Initializes the SPIx peripheral according to the specified +* parameters in the SPI_InitStruct. +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that +* contains the configuration information for the specified +* SPI peripheral. +* @retval : None +*/ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint32_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_DATAWIDRH(SPI_InitStruct->SPI_DataWidth)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + /*---------------------------- SPIx GCTL Configuration ------------------------*/ + /* Get the SPIx GCTL value */ + tmpreg = SPIx->GCTL; + /* Clear csn_sel, dmamode, txtlf, rxtlf,data_sel, rxen, txen, mm, int_en, spien bits */ + tmpreg &= GCTL_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set dat_sel bits according to SPI_DataSize value */ + /* Set csn and csn_sel bits according to SPI_NSS value */ + /* Set mm bit according to SPI_Mode value */ + tmpreg |= (uint32_t)((uint32_t) SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_Mode ); + /* Write to SPIx GCTL */ + SPIx->GCTL = tmpreg; + /*---------------------------- SPIx CCTL Configuration ------------------------*/ + tmpreg = SPIx->CCTL; + /* Clear spilen, lsbfe, CPOL, CPHA bits */ + tmpreg &= CCTL_CLEAR_Mask; + /* Set Spilen bit according to SPI_DataWidth value */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)( SPI_InitStruct->SPI_FirstBit | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA) ; + + /* Write to SPIx CCTL */ + SPIx->CCTL = tmpreg | 0x18; + /*---------------------------- SPIx SPBRG Configuration ------------------------*/ + tmpreg = SPIx->SPBRG; + /* Clear spbrg bits */ + tmpreg &= (uint16_t)SPBRG_CLEAR_Mask; + /* Set BR bits according to SPI_BaudRatePrescaler value */ + tmpreg |= (uint16_t) SPI_InitStruct->SPI_BaudRatePrescaler; + /* Write to SPIx SPBRG */ + SPIx->SPBRG = tmpreg; + + if((SPI_InitStruct->SPI_DataWidth) != SPI_DataWidth_8b) + { + SPIx->CCTL |= 1 << 2; //lsbfe + SPIx->CCTL |= 1 << 3; //spilen + } + SPIx->EXTCTL = SPI_InitStruct->SPI_DataWidth; +} + +/** +* @brief Fills each SPI_InitStruct member with its default value. +* @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /*--------------- Reset SPI init structure parameters values -----------------*/ + + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPILEN member */ + SPI_InitStruct->SPI_DataWidth = SPI_DataWidth_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Soft; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + +} + + +/** +* @brief Enables or disables the specified SPI peripheral. +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param NewState: new state of the SPIx peripheral. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->GCTL |= GCTL_SPIEN_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->GCTL &= GCTL_SPIEN_Reset; + } +} + + +/** +* @brief Enables or disables the specified SPIinterrupts. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_IT: specifies the SPI interrupt source to be +* enabled or disabled. +* This parameter can be one of the following values: +* @arg SPI_IT_TX: Tx buffer empty interrupt mask +* @arg SPI_IT_RX: Rx buffer interrupt mask +* @arg SPI_IT_UNDERRUN: under Error interrupt mask in slave mode +* @arg SPI_IT_RXOVER: RX OVER Error interrupt mask +* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt mask +* @arg SPI_IT_RXFULL: Rx buffer full interrupt mask +* @arg SPI_IT_TXEPT: Tx buffer empty interrupt mask +* @param NewState: new state of the specified SPI interrupt. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_CONFIG_IT(SPI_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI Global interrupt */ + SPIx->GCTL |= SPI_INT_EN; + /* Enable the selected SPI interrupt */ + SPIx->INTEN |= SPI_IT; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->INTEN &= (uint16_t)~SPI_IT; + /* Disable the selected SPI Global interrupt */ + SPIx->GCTL &= (uint16_t)~SPI_INT_EN; + } + +} + +/** +* @brief Enables or disables the SPIx DMA interface. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_DMAReq: specifies the SPI DMA transfer request +* to be enabled or disabled. +* This parameter can be any combination of the following values: +* @arg SPI_DMAReq_EN: DMA transfer request enable +* @param NewState: new state of the selected SPI DMA transfer +* request. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_DMAREQ(SPI_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->GCTL |= SPI_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->GCTL &= (uint32_t)~SPI_DMAReq; + } +} + +/** +* @brief configure tn Fifo trigger level bit. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_FifoTriggerValue: specifies the Fifo trigger level +* This parameter can be any combination of the following values: +* SPI_TXTLF : SPI TX FIFO Trigger value set +* SPI_RXTLF : SPI RX FIFO Trigger value set +* @param NewState: new state of the selected SPI DMA transfer +* request. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_FIFOTRIGGER(SPI_FifoTriggerValue)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->GCTL |= SPI_FifoTriggerValue; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->GCTL &= (uint32_t)~SPI_FifoTriggerValue; + } +} + +/** +* @brief Transmits a Data through the SPIx peripheral. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param Data : Data to be transmitted.. +* @retval : None +*/ +void SPI_SendData(SPI_TypeDef* SPIx, uint32_t Data) +{ + uint8_t temp; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the TXREG register the data to be sent */ + temp = SPIx->EXTCTL; + SPIx->TXREG = Data; + if(temp > 0x8 || temp == 0) SPIx->TXREG = Data >> 8; + if(temp > 0x10 || temp == 0) SPIx->TXREG = Data >> 16; + if(temp > 0x18 || temp == 0) SPIx->TXREG = Data >> 24; +} + + +/** +* @brief Returns the most recent received data by the SPIx peripheral. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @retval : The value of the received data. +*/ +uint32_t SPI_ReceiveData(SPI_TypeDef* SPIx) +{ + + uint32_t temp = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + temp = temp; + temp |= (uint32_t)SPIx->RXREG; + if(SPIx->EXTCTL > 8 || SPIx->EXTCTL == 0) temp |= (uint32_t) (SPIx->RXREG) << 8; + if(SPIx->EXTCTL > 16 || SPIx->EXTCTL == 0) temp |= (uint32_t)( SPIx->RXREG) << 16; + if(SPIx->EXTCTL > 24 || SPIx->EXTCTL == 0) temp |= (uint32_t)( SPIx->RXREG) << 24; + + return temp; +} + +/** +* @brief Slave chip csn single by selected +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param SPI_CSInternalSelected: specifies the SPI CS internal selected. +* This parameter can be one of the following values: +* @arg SPI_CS_BIT0: cs bit 0 selected +* @arg SPI_CS_BIT1: cs bit 1 selected +* @arg SPI_CS_BIT2: cs bit 2 selected +* @arg SPI_CS_BIT3: cs bit 3 selected +* @arg SPI_CS_BIT4: cs bit 4 selected +* @arg SPI_CS_BIT5: cs bit 5 selected +* @arg SPI_CS_BIT6: cs bit 6 selected +* @arg SPI_CS_BIT7: cs bit 7 selected +* @param NewState: new state of the selected SPI CS pin +* request. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CS(SPI_CSInternalSelected)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + + if (NewState != DISABLE) + { + /* selected cs pin according SCSR Value */ + SPIx->SCSR &= SPI_CSInternalSelected; + } + else + { + /* release cs pin according SCSR Value*/ + SPIx->SCSR |= ~SPI_CSInternalSelected; + } +} + + +/** +* @brief Configures internally by software the NSS pin for the selected +* SPI. +* @param SPIx: where x can be 1, 2 to select the SPI peripheral. +* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. +* This parameter can be one of the following values: +* @arg SPI_NSSInternalSoft_Set: Set NSS pin internally +* @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally +* @retval : None +*/ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->GCTL |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->GCTL &= SPI_NSSInternalSoft_Reset; + } +} + + + +/** +* @brief Configures the data size for the selected SPI. +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param SPI_DataSize: specifies the SPI data size. +* This parameter can be one of the following values: +* @arg SPI_DataSize_32b: Set data frame format to 32bit +* @arg SPI_DataSize_16b: Set data frame format to 16bit +* @arg SPI_DataSize_8b: Set data frame format to 8bit +* @retval : None +*/ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear data_sel bit */ + SPIx->GCTL &= SPI_DataSize_Mask; + /* Set new data_sel bit value */ + SPIx->GCTL |= SPI_DataSize; +} + + + +/** +* @brief Selects the data transfer direction in bi-directional mode +* for the specified SPI. +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param SPI_Direction: specifies the data transfer direction in +* bi-directional mode. +* This parameter can be one of the following values: +* @arg SPI_Direction_Tx: Selects Tx transmission direction +* @arg SPI_Direction_Rx: Selects Rx receive direction +@arg SPI_Disable_Tx: Selects Rx receive direction +@arg SPI_Disable_Rx: Selects Rx receive direction +* @retval : None +*/ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + + /* Set the Tx only mode */ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->GCTL |= SPI_Direction_Tx; + } + /* Set the Rx only mode */ + if(SPI_Direction == SPI_Direction_Rx) + { + SPIx->GCTL |= SPI_Direction_Rx; + } + /* Disable the Tx only mode */ + if(SPI_Direction == SPI_Disable_Tx) + { + SPIx->GCTL &= SPI_Disable_Tx; + } + /* Disable the Rx only mode */ + if(SPI_Direction == SPI_Disable_Rx) + { + SPIx->GCTL &= SPI_Disable_Rx; + } +} + +/** +* @brief Checks whether the specified SPI flag is set or not. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_FLAG: specifies the SPI flag to check. +* This parameter can be one of the following values: +* @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag +* @arg SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag +* @retval : The new state of SPI_FLAG (SET or RESET). +*/ +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_GET_FLAG(SPI_FLAG)); + if(SPIx->EXTCTL == 8) + { + /* Check the status of the specified SPI flag */ + if ((SPIx->CSTAT & SPI_FLAG) != (uint16_t)RESET) + { + /* SPI_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_FLAG status */ + return bitstatus; + } + else + { + uint8_t number; + if(SPIx->EXTCTL > 0 && SPIx->EXTCTL <= 8) + number = 1; + else if(SPIx->EXTCTL <= 16) + number = 2; + else if(SPIx->EXTCTL <= 24) + number = 3; + else if(SPIx->EXTCTL <= 31 || SPIx->EXTCTL == 0) + number = 4; + if(((SPIx->CSTAT & 0xf00) >> 8) >= number) + { + return SET; + } + else + { + return RESET; + } + } +} + +/** +* @brief Checks whether the specified SPI interrupt has occurred or not. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_IT: specifies the SPI interrupt source to check. +* This parameter can be one of the following values: +* @arg SPI_IT_TX: Tx buffer empty interrupt +* @arg SPI_IT_RX: Rx buffer interrupt +* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode +* @arg SPI_IT_RXOVER: RX OVER Error interrupt +* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt +* @arg SPI_IT_RXFULL: Rx buffer full interrupt +* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt +* @retval : The new state of SPI_IT (SET or RESET). +*/ +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_GET_IT(SPI_IT)); + /* Check the status of the specified SPI interrupt */ + if ((SPIx->INTSTAT & SPI_IT) != (uint16_t)RESET) + { + /* SPI_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_IT status */ + return bitstatus; +} + +/** +* @brief Clears the SPIx Error interrupt pending bit. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_IT: specifies the SPI interrupt pending bit to clear. +* @arg SPI_IT_TX: Tx buffer empty interrupt +* @arg SPI_IT_RX: Rx buffer interrupt +* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode +* @arg SPI_IT_RXOVER: RX OVER Error interrupt +* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt +* @arg SPI_IT_RXFULL: Rx buffer full interrupt +* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt +* This function clears only ERR intetrrupt pending bit. +* @retval : None +*/ +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_IT(SPI_IT)); + + /* Clear the selected SPI IT INTERRUPT */ + SPIx->INTCLR |= (uint16_t)SPI_IT; +} + + +/** +* @brief SPI Hole a count Received bytes in next receive process. +* @param SPIx: where x can be 0, 1 in SPI mode +* @param Number: specifies the SPI receive Number. +* This parament can be 1-65535. +* This function can use only in SPI master single receive mode. +* @retval : None +*/ +void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + /*set the received bytes in next receive process */ + SPIx->RXDNR = Number; +} + +/** +* @brief slave mode tx data transmit phase adjust set. +* @param SPIx: where x can be 0, 1 in SPI mode +* @param AdjustValue: specifies the SPI receive Number. +* This parament can be : +* SPI_SlaveAdjust_FAST: fast speed use +* SPI_SlaveAdjust_LOW: low speed use +* This function can use only in SPI master single receive mode. +* @retval : None +*/ +void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_SlaveAdjust(AdjustValue)); + /*set the AdjustValue according to txedge bit of CCTL register*/ + SPIx->CCTL |= AdjustValue; +} + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_tim.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_tim.c new file mode 100644 index 0000000000..0d0d4584ae --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_tim.c @@ -0,0 +1,2838 @@ +/** +****************************************************************************** +* @file HAL_tim.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the TIM firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_tim.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup TIM +* @brief TIM driver modules +* @{ +*/ + +/** @defgroup TIM_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup TIM_Private_Defines +* @{ +*/ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define CR1_CEN_Set ((uint16_t)0x0001) +#define CR1_CEN_Reset ((uint16_t)0x03FE) +#define CR1_UDIS_Set ((uint16_t)0x0002) +#define CR1_UDIS_Reset ((uint16_t)0x03FD) +#define CR1_URS_Set ((uint16_t)0x0004) +#define CR1_URS_Reset ((uint16_t)0x03FB) +#define CR1_OPM_Reset ((uint16_t)0x03F7) +#define CR1_CounterMode_Mask ((uint16_t)0x038F) +#define CR1_ARPE_Set ((uint16_t)0x0080) +#define CR1_ARPE_Reset ((uint16_t)0x037F) +#define CR1_CKD_Mask ((uint16_t)0x00FF) +#define CR2_CCPC_Set ((uint16_t)0x0001) +#define CR2_CCPC_Reset ((uint16_t)0xFFFE) +#define CR2_CCUS_Set ((uint16_t)0x0004) +#define CR2_CCUS_Reset ((uint16_t)0xFFFB) +#define CR2_CCDS_Set ((uint16_t)0x0008) +#define CR2_CCDS_Reset ((uint16_t)0xFFF7) +#define CR2_MMS_Mask ((uint16_t)0xFF8F) +#define CR2_TI1S_Set ((uint16_t)0x0080) +#define CR2_TI1S_Reset ((uint16_t)0xFF7F) +#define CR2_OIS1_Reset ((uint16_t)0x7EFF) +#define CR2_OIS1N_Reset ((uint16_t)0x7DFF) +#define CR2_OIS2_Reset ((uint16_t)0x7BFF) +#define CR2_OIS2N_Reset ((uint16_t)0x77FF) +#define CR2_OIS3_Reset ((uint16_t)0x6FFF) +#define CR2_OIS3N_Reset ((uint16_t)0x5FFF) +#define CR2_OIS4_Reset ((uint16_t)0x3FFF) +#define SMCR_SMS_Mask ((uint16_t)0xFFF8) +#define SMCR_ETR_Mask ((uint16_t)0x00FF) +#define SMCR_TS_Mask ((uint16_t)0xFF8F) +#define SMCR_MSM_Reset ((uint16_t)0xFF7F) +#define SMCR_ECE_Set ((uint16_t)0x4000) +#define CCMR_CC13S_Mask ((uint16_t)0xFFFC) +#define CCMR_CC24S_Mask ((uint16_t)0xFCFF) +#define CCMR_TI13Direct_Set ((uint16_t)0x0001) +#define CCMR_TI24Direct_Set ((uint16_t)0x0100) +#define CCMR_OC13FE_Reset ((uint16_t)0xFFFB) +#define CCMR_OC24FE_Reset ((uint16_t)0xFBFF) +#define CCMR_OC13PE_Reset ((uint16_t)0xFFF7) +#define CCMR_OC24PE_Reset ((uint16_t)0xF7FF) +#define CCMR_OC13M_Mask ((uint16_t)0xFF8F) +#define CCMR_OC24M_Mask ((uint16_t)0x8FFF) +#define CCMR_OC13CE_Reset ((uint16_t)0xFF7F) +#define CCMR_OC24CE_Reset ((uint16_t)0x7FFF) +#define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3) +#define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF) +#define CCMR_IC13F_Mask ((uint16_t)0xFF0F) +#define CCMR_IC24F_Mask ((uint16_t)0x0FFF) +#define CCMR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) +#define CCER_CC1P_Reset ((uint16_t)0xFFFD) +#define CCER_CC2P_Reset ((uint16_t)0xFFDF) +#define CCER_CC3P_Reset ((uint16_t)0xFDFF) +#define CCER_CC4P_Reset ((uint16_t)0xDFFF) +#define CCER_CC1NP_Reset ((uint16_t)0xFFF7) +#define CCER_CC2NP_Reset ((uint16_t)0xFF7F) +#define CCER_CC3NP_Reset ((uint16_t)0xF7FF) +#define CCER_CC1E_Set ((uint16_t)0x0001) +#define CCER_CC1E_Reset ((uint16_t)0xFFFE) +#define CCER_CC1NE_Reset ((uint16_t)0xFFFB) +#define CCER_CC2E_Set ((uint16_t)0x0010) +#define CCER_CC2E_Reset ((uint16_t)0xFFEF) +#define CCER_CC2NE_Reset ((uint16_t)0xFFBF) +#define CCER_CC3E_Set ((uint16_t)0x0100) +#define CCER_CC3E_Reset ((uint16_t)0xFEFF) +#define CCER_CC3NE_Reset ((uint16_t)0xFBFF) +#define CCER_CC4E_Set ((uint16_t)0x1000) +#define CCER_CC4E_Reset ((uint16_t)0xEFFF) +#define BDTR_MOE_Set ((uint16_t)0x8000) +#define BDTR_MOE_Reset ((uint16_t)0x7FFF) +/** +* @} +*/ + +/** @defgroup TIM_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup TIM_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup TIM_Private_FunctionPrototypes +* @{ +*/ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/** +* @} +*/ + +/** @defgroup TIM_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup TIM_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup TIM_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup TIM_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the TIMx peripheral registers to their default +* reset values. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @retval : None +*/ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + switch (*(uint32_t*)&TIMx) + { + case TIM1_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + break; + + case TIM2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + break; + + case TIM3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + break; + + case TIM4_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + break; + + default: + break; + } +} + +/** +* @brief Initializes the TIMx Time Base Unit peripheral according to +* the specified parameters in the TIM_TimeBaseInitStruct. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure that contains the configuration information for +* the specified TIM peripheral. +* @retval : None +*/ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + /* Select the Counter Mode and set the clock division */ + TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision | + TIM_TimeBaseInitStruct->TIM_CounterMode; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if(*(uint32_t*)&TIMx == TIM1_BASE) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler value immediatly */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** +* @brief Initializes the TIMx Channel1 according to the specified +* parameters in the TIM_OCInitStruct. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* @retval : None +*/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= CCER_CC1E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC13M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC1P_Reset; + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + if(*(uint32_t*)&TIMx == TIM1_BASE) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC1NP_Reset; + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + /* Reset the Output N State */ + tmpccer &= CCER_CC1NE_Reset; + + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS1_Reset; + tmpcr2 &= CR2_OIS1N_Reset; + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Initializes the TIMx Channel2 according to the specified +* parameters in the TIM_OCInitStruct. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* @retval : None +*/ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC2E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC24M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC2P_Reset; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + if(*(uint32_t*)&TIMx == TIM1_BASE) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC2NP_Reset; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + /* Reset the Output N State */ + tmpccer &= CCER_CC2NE_Reset; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS2_Reset; + tmpcr2 &= CR2_OIS2N_Reset; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Initializes the TIMx Channel3 according to the specified +* parameters in the TIM_OCInitStruct. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* @retval : None +*/ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC3E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC13M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC3P_Reset; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + if(*(uint32_t*)&TIMx == TIM1_BASE) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC3NP_Reset; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= CCER_CC3NE_Reset; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS3_Reset; + tmpcr2 &= CR2_OIS3N_Reset; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Initializes the TIMx Channel4 according to the specified +* parameters in the TIM_OCInitStruct. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* @retval : None +*/ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= CCER_CC4E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC24M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC4P_Reset; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + if(*(uint32_t*)&TIMx == TIM1_BASE) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= CR2_OIS4_Reset; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Initializes the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* @retval : None +*/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** +* @brief Configures the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct to measure an external PWM +* signal. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* @retval : None +*/ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** +* @brief Configures the: Break feature, dead time, Lock level, the OSSI, +* the OSSR State and the AOE(automatic output enable). +* @param TIMx: where x can be 1 to select the TIM +* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef +* structure that contains the BDTR Register configuration +* information for the TIM peripheral. +* @retval : None +*/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** +* @brief Fills each TIM_TimeBaseInitStruct member with its default value. +* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef +* structure which will be initialized. +* @retval : None +*/ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** +* @brief Fills each TIM_OCInitStruct member with its default value. +* @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** +* @brief Fills each TIM_ICInitStruct member with its default value. +* @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** +* @brief Fills each TIM_BDTRInitStruct member with its default value. +* @param TIM_BDTRInitStruct : pointer to a TIM_BDTRInitTypeDef +* structure which will be initialized. +* @retval : None +*/ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** +* @brief Enables or disables the specified TIM peripheral. +* @param TIMx: where x can be 1 to 4 to select the TIMx peripheral. +* @param NewState: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + + if (NewState != DISABLE) + { + + /* Enable the TIM Counter */ + TIMx->CR1 |= CR1_CEN_Set; + + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= CR1_CEN_Reset; + } + +} + +/** +* @brief Enables or disables the TIM peripheral Main Outputs. +* @param TIMx: where x can be 1 to select the TIMx peripheral. +* @param NewState: new state of the TIM peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= BDTR_MOE_Set; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= BDTR_MOE_Reset; + } +} + +/** +* @brief Enables or disables the specified TIM interrupts. +* @param TIMx: where x can be 1 to 4 to select the TIMx peripheral. +* @param TIM_IT: specifies the TIM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* @arg TIM_IT_Update: TIM update Interrupt source +* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* @arg TIM_IT_COM: TIM Commutation Interrupt source +* @arg TIM_IT_Trigger: TIM Trigger Interrupt source +* @arg TIM_IT_Break: TIM Break Interrupt source +* @param NewState: new state of the TIM interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + unsigned int temp = 0; + temp = temp; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_TIM_PERIPH_IT((TIMx), (TIM_IT))); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + temp = TIMx->DIER; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } + +} + +/** +* @brief Configures the TIMx event to be generate by software. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_EventSource: specifies the event source. +* This parameter can be one or more of the following values: +* @arg TIM_EventSource_Update: Timer update Event source +* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source +* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source +* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source +* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source +* @arg TIM_EventSource_Trigger: Timer Trigger Event source +* @retval : None +*/ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + assert_param(IS_TIM_PERIPH_EVENT((TIMx), (TIM_EventSource))); + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** +* @brief Configures the TIMxs DMA interface. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_DMABase: DMA Base address. +* This parameter can be one of the following values: +* @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, +* TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, +* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, +* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, +* TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, +* TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, +* TIM_DMABase_DCR. +* @param TIM_DMABurstLength: DMA Burst length. +* This parameter can be one value between: +* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. +* @retval : None +*/ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** +* @brief Enables or disables the TIMxs DMA Requests. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_DMASource: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* @arg TIM_DMA_Update: TIM update Interrupt source +* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +* @arg TIM_DMA_COM: TIM Commutation DMA source +* @arg TIM_DMA_Trigger: TIM Trigger DMA source +* @param NewState: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_TIM_PERIPH_DMA(TIMx, TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** +* @brief Configures the TIMx interrnal Clock +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @retval : None +*/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= SMCR_SMS_Mask; +} + +/** +* @brief Configures the TIMx Internal Trigger as External Clock +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ITRSource: Trigger source. +* This parameter can be one of the following values: +* @param TIM_TS_ITR0: Internal Trigger 0 +* @param TIM_TS_ITR1: Internal Trigger 1 +* @param TIM_TS_ITR2: Internal Trigger 2 +* @param TIM_TS_ITR3: Internal Trigger 3 +* @retval : None +*/ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** +* @brief Configures the TIMx Trigger as External Clock +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_TIxExternalCLKSource: Trigger source. +* This parameter can be one of the following values: +* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector +* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 +* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 +* @param TIM_ICPolarity: specifies the TIx Polarity. +* This parameter can be: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param ICFilter : specifies the filter value. +* This parameter must be a value between 0x0 and 0xF. +* @retval : None +*/ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** +* @brief Configures the External clock Mode1 +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* @arg TIM_ExtTRGPSC_OFF +* @arg TIM_ExtTRGPSC_DIV2 +* @arg TIM_ExtTRGPSC_DIV4 +* @arg TIM_ExtTRGPSC_DIV8. +* @param TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* @arg TIM_ExtTRGPolarity_Inverted +* @arg TIM_ExtTRGPolarity_NonInverted +* @param ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* @retval : None +*/ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= SMCR_SMS_Mask; + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= SMCR_TS_Mask; + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** +* @brief Configures the External clock Mode2 +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* @arg TIM_ExtTRGPSC_OFF +* @arg TIM_ExtTRGPSC_DIV2 +* @arg TIM_ExtTRGPSC_DIV4 +* @arg TIM_ExtTRGPSC_DIV8 +* @param TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* @arg TIM_ExtTRGPolarity_Inverted +* @arg TIM_ExtTRGPolarity_NonInverted +* @param ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* @retval : None +*/ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= SMCR_ECE_Set; +} + +/** +* @brief Configures the TIMx External Trigger (ETR). +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* @arg TIM_ExtTRGPSC_OFF +* @arg TIM_ExtTRGPSC_DIV2 +* @arg TIM_ExtTRGPSC_DIV4 +* @arg TIM_ExtTRGPSC_DIV8 +* @param TIM_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* @arg TIM_ExtTRGPolarity_Inverted +* @arg TIM_ExtTRGPolarity_NonInverted +* @param ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval : None +*/ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << 8); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** +* @brief Configures the TIMx Prescaler. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param Prescaler: specifies the Prescaler Register value +* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode +* This parameter can be one of the following values: +* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at +* the update event. +* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded +* immediatly. +* @retval : None +*/ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** +* @brief Specifies the TIMx Counter Mode to be used. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* @arg TIM_CounterMode_Up: TIM Up Counting Mode +* @arg TIM_CounterMode_Down: TIM Down Counting Mode +* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* @retval : None +*/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= CR1_CounterMode_Mask; + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; + +} + +/** +* @brief Selects the Input Trigger source +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_InputTriggerSource: The Input Trigger source. +* This parameter can be one of the following values: +* @arg TIM_TS_ITR0: Internal Trigger 0 +* @arg TIM_TS_ITR1: Internal Trigger 1 +* @arg TIM_TS_ITR2: Internal Trigger 2 +* @arg TIM_TS_ITR3: Internal Trigger 3 +* @arg TIM_TS_TI1F_ED: TI1 Edge Detector +* @arg TIM_TS_TI1FP1: Filtered Timer Input 1 +* @arg TIM_TS_TI2FP2: Filtered Timer Input 2 +* @arg TIM_TS_ETRF: External Trigger input +* @retval : None +*/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= SMCR_TS_Mask; + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** +* @brief Configures the TIMx Encoder Interface. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_EncoderMode: specifies the TIMx Encoder Mode. +* This parameter can be one of the following values: +* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge +* depending on TI2FP2 level. +* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge +* depending on TI1FP1 level. +* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and +* TI2FP2 edges depending on the level of the other input. +* @param TIM_IC1Polarity: specifies the IC1 Polarity +* This parmeter can be one of the following values: +* @arg TIM_ICPolarity_Falling: IC Falling edge. +* @arg TIM_ICPolarity_Rising: IC Rising edge. +* @param TIM_IC2Polarity: specifies the IC2 Polarity +* This parmeter can be one of the following values: +* @arg TIM_ICPolarity_Falling: IC Falling edge. +* @arg TIM_ICPolarity_Rising: IC Rising edge. +* @retval : None +*/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Set the encoder Mode */ + tmpsmcr &= SMCR_SMS_Mask; + tmpsmcr |= TIM_EncoderMode; + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; + tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset; + tmpccer |= (TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << 4)); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Forces the TIMx output 1 waveform to active or inactive level. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* @arg TIM_ForcedAction_Active: Force active level on OC1REF +* @arg TIM_ForcedAction_InActive: Force inactive level on +* OC1REF. +* @retval : None +*/ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= CCMR_OC13M_Mask; + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Forces the TIMx output 2 waveform to active or inactive level. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* @arg TIM_ForcedAction_Active: Force active level on OC2REF +* @arg TIM_ForcedAction_InActive: Force inactive level on +* OC2REF. +* @retval : None +*/ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= CCMR_OC24M_Mask; + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Forces the TIMx output 3 waveform to active or inactive level. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* @arg TIM_ForcedAction_Active: Force active level on OC3REF +* @arg TIM_ForcedAction_InActive: Force inactive level on +* OC3REF. +* @retval : None +*/ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= CCMR_OC13M_Mask; + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Forces the TIMx output 4 waveform to active or inactive level. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* @arg TIM_ForcedAction_Active: Force active level on OC4REF +* @arg TIM_ForcedAction_InActive: Force inactive level on +* OC4REF. +* @retval : None +*/ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= CCMR_OC24M_Mask; + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Enables or disables TIMx peripheral Preload register on ARR. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param NewState: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= CR1_ARPE_Set; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= CR1_ARPE_Reset; + } + +} + +/** +* @brief Selects the TIM peripheral Commutation event. +* @param TIMx: where x can be 1 to select the TIMx peripheral +* @param NewState: new state of the Commutation event. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= CR2_CCUS_Set; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= CR2_CCUS_Reset; + } +} + +/** +* @brief Selects the TIMx peripheral Capture Compare DMA source. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param NewState: new state of the Capture Compare DMA source +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= CR2_CCDS_Set; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= CR2_CCDS_Reset; + } +} + +/** +* @brief Sets or Resets the TIM peripheral Capture Compare Preload +* Control bit. +* @param TIMx: where x can be 1 to select the TIMx peripheral +* @param NewState: new state of the Capture Compare Preload Control bit +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= CR2_CCPC_Set; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= CR2_CCPC_Reset; + } +} + +/** +* @brief Enables or disables the TIMx peripheral Preload register on CCR1. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* @arg TIM_OCPreload_Enable +* @arg TIM_OCPreload_Disable +* @retval : None +*/ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= CCMR_OC13PE_Reset; + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Enables or disables the TIMx peripheral Preload register on CCR2. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* @arg TIM_OCPreload_Enable +* @arg TIM_OCPreload_Disable +* @retval : None +*/ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= CCMR_OC24PE_Reset; + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Enables or disables the TIMx peripheral Preload register on CCR3. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* @arg TIM_OCPreload_Enable +* @arg TIM_OCPreload_Disable +* @retval : None +*/ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= CCMR_OC13PE_Reset; + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Enables or disables the TIMx peripheral Preload register on CCR4. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* @arg TIM_OCPreload_Enable +* @arg TIM_OCPreload_Disable +* @retval : None +*/ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= CCMR_OC24PE_Reset; + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Configures the TIMx Output Compare 1 Fast feature. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCFast_Enable: TIM output compare fast enable +* @arg TIM_OCFast_Disable: TIM output compare fast disable +* @retval : None +*/ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= CCMR_OC13FE_Reset; + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Configures the TIMx Output Compare 2 Fast feature. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCFast_Enable: TIM output compare fast enable +* @arg TIM_OCFast_Disable: TIM output compare fast disable +* @retval : None +*/ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= CCMR_OC24FE_Reset; + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Configures the TIMx Output Compare 3 Fast feature. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCFast_Enable: TIM output compare fast enable +* @arg TIM_OCFast_Disable: TIM output compare fast disable +* @retval : None +*/ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= CCMR_OC13FE_Reset; + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Configures the TIMx Output Compare 4 Fast feature. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCFast_Enable: TIM output compare fast enable +* @arg TIM_OCFast_Disable: TIM output compare fast disable +* @retval : None +*/ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= CCMR_OC24FE_Reset; + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Clears or safeguards the OCREF1 signal on an external event +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCClear_Enable: TIM Output clear enable +* @arg TIM_OCClear_Disable: TIM Output clear disable +* @retval : None +*/ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1CE Bit */ + tmpccmr1 &= CCMR_OC13CE_Reset; + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Clears or safeguards the OCREF2 signal on an external event +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCClear_Enable: TIM Output clear enable +* @arg TIM_OCClear_Disable: TIM Output clear disable +* @retval : None +*/ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= CCMR_OC24CE_Reset; + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Clears or safeguards the OCREF3 signal on an external event +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCClear_Enable: TIM Output clear enable +* @arg TIM_OCClear_Disable: TIM Output clear disable +* @retval : None +*/ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= CCMR_OC13CE_Reset; + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Clears or safeguards the OCREF4 signal on an external event +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCClear_Enable: TIM Output clear enable +* @arg TIM_OCClear_Disable: TIM Output clear disable +* @retval : None +*/ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= CCMR_OC24CE_Reset; + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Configures the TIMx channel 1 polarity. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCPolarity: specifies the OC1 Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCPolarity_High: Output Compare active high +* @arg TIM_OCPolarity_Low: Output Compare active low +* @retval : None +*/ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= CCER_CC1P_Reset; + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx Channel 1N polarity. +* @param TIMx: where x can be 1 to select the TIM peripheral. +* @param TIM_OCNPolarity: specifies the OC1N Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCNPolarity_High: Output Compare active high +* @arg TIM_OCNPolarity_Low: Output Compare active low +* @retval : None +*/ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= CCER_CC1NP_Reset; + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx channel 2 polarity. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCPolarity: specifies the OC2 Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCPolarity_High: Output Compare active high +* @arg TIM_OCPolarity_Low: Output Compare active low +* @retval : None +*/ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= CCER_CC2P_Reset; + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx Channel 2N polarity. +* @param TIMx: where x can be 1 to select the TIM peripheral. +* @param TIM_OCNPolarity: specifies the OC2N Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCNPolarity_High: Output Compare active high +* @arg TIM_OCNPolarity_Low: Output Compare active low +* @retval : None +*/ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= CCER_CC2NP_Reset; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx channel 3 polarity. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCPolarity: specifies the OC3 Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCPolarity_High: Output Compare active high +* @arg TIM_OCPolarity_Low: Output Compare active low +* @retval : None +*/ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= CCER_CC3P_Reset; + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx Channel 3N polarity. +* @param TIMx: where x can be 1 to select the TIM peripheral. +* @param TIM_OCNPolarity: specifies the OC3N Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCNPolarity_High: Output Compare active high +* @arg TIM_OCNPolarity_Low: Output Compare active low +* @retval : None +*/ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= CCER_CC3NP_Reset; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx channel 4 polarity. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_OCPolarity: specifies the OC4 Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCPolarity_High: Output Compare active high +* @arg TIM_OCPolarity_Low: Output Compare active low +* @retval : None +*/ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= CCER_CC4P_Reset; + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Enables or disables the TIM Capture Compare Channel x. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_Channel: specifies the TIM Channel +* This parmeter can be one of the following values: +* @arg TIM_Channel_1: TIM Channel 1 +* @arg TIM_Channel_2: TIM Channel 2 +* @arg TIM_Channel_3: TIM Channel 3 +* @arg TIM_Channel_4: TIM Channel 4 +* @param TIM_CCx: specifies the TIM Channel CCxE bit new state. +* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. +* @retval : None +*/ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)(CCER_CCE_Set << TIM_Channel))); + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** +* @brief Enables or disables the TIM Capture Compare Channel xN. +* @param TIMx: where x can be 1 to select the TIM peripheral. +* @param TIM_Channel: specifies the TIM Channel +* This parmeter can be one of the following values: +* @arg TIM_Channel_1: TIM Channel 1 +* @arg TIM_Channel_2: TIM Channel 2 +* @arg TIM_Channel_3: TIM Channel 3 +* @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. +* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. +* @retval : None +*/ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)(CCER_CCNE_Set << TIM_Channel))); + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** +* @brief Selects the TIM Ouput Compare Mode. +* This function disables the selected channel before changing +* the Ouput Compare Mode. User has to enable this channel using +* TIM_CCxCmd and TIM_CCxNCmd functions. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_Channel: specifies the TIM Channel +* This parmeter can be one of the following values: +* @arg TIM_Channel_1: TIM Channel 1 +* @arg TIM_Channel_2: TIM Channel 2 +* @arg TIM_Channel_3: TIM Channel 3 +* @arg TIM_Channel_4: TIM Channel 4 +* @param TIM_OCMode: specifies the TIM Output Compare Mode. +* This paramter can be one of the following values: +* @arg TIM_OCMode_Timing +* @arg TIM_OCMode_Active +* @arg TIM_OCMode_Toggle +* @arg TIM_OCMode_PWM1 +* @arg TIM_OCMode_PWM2 +* @arg TIM_ForcedAction_Active +* @arg TIM_ForcedAction_InActive +* @retval : None +*/ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)(CCER_CCE_Set << TIM_Channel))); + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + /* Reset the OCxM bits in the CCMRx register */ + *((__IO uint32_t *)((*(uint32_t*)&TIMx) + CCMR_Offset + (TIM_Channel >> 1))) &= CCMR_OC13M_Mask; + + /* Configure the OCxM bits in the CCMRx register */ + *((__IO uint32_t *)((*(uint32_t*)&TIMx) + CCMR_Offset + (TIM_Channel >> 1))) |= TIM_OCMode; + } + else + { + /* Reset the OCxM bits in the CCMRx register */ + *((__IO uint32_t *)((*(uint32_t*)&TIMx) + CCMR_Offset + ((uint16_t)(TIM_Channel - 4) >> 1))) &= CCMR_OC24M_Mask; + + /* Configure the OCxM bits in the CCMRx register */ + *((__IO uint32_t *)((*(uint32_t*)&TIMx) + CCMR_Offset + ((uint16_t)(TIM_Channel - 4) >> 1))) |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** +* @brief Enables or Disables the TIMx Update event. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param NewState: new state of the TIMx UDIS bit +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= CR1_UDIS_Set; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= CR1_UDIS_Reset; + } +} + +/** +* @brief Configures the TIMx Update Request Interrupt source. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_UpdateSource: specifies the Update source. +* This parameter can be one of the following values: +* @arg TIM_UpdateSource_Regular +* @arg TIM_UpdateSource_Global +* @retval : None +*/ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= CR1_URS_Set; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= CR1_URS_Reset; + } +} + +/** +* @brief Enables or disables the TIMxs Hall sensor interface. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM peripheral. +* @param NewState: new state of the TIMx Hall sensor interface. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= CR2_TI1S_Set; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= CR2_TI1S_Reset; + } +} + +/** +* @brief Selects the TIMxs One Pulse Mode. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_OPMode: specifies the OPM Mode to be used. +* This parameter can be one of the following values: +* @arg TIM_OPMode_Single +* @arg TIM_OPMode_Repetitive +* @retval : None +*/ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CR1 &= CR1_OPM_Reset; + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** +* @brief Selects the TIMx Trigger Output Mode. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_TRGOSource: specifies the Trigger Output source. +* This paramter can be as follow: +* 1/ For TIM1 to TIM8: +* @arg TIM_TRGOSource_Reset +* @arg TIM_TRGOSource_Enable +* @arg TIM_TRGOSource_Update +* 2/ These parameters are available for all TIMx +* @arg TIM_TRGOSource_OC1 +* @arg TIM_TRGOSource_OC1Ref +* @arg TIM_TRGOSource_OC2Ref +* @arg TIM_TRGOSource_OC3Ref +* @arg TIM_TRGOSource_OC4Ref +* @retval : None +*/ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + assert_param(IS_TIM_PERIPH_TRGO(TIMx, TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CR2 &= CR2_MMS_Mask; + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** +* @brief Selects the TIMx Slave Mode. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_SlaveMode: specifies the Timer Slave Mode. +* This paramter can be one of the following values: +* @arg TIM_SlaveMode_Reset +* @arg TIM_SlaveMode_Gated +* @arg TIM_SlaveMode_Trigger +* @arg TIM_SlaveMode_External1 +* @retval : None +*/ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCR &= SMCR_SMS_Mask; + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** +* @brief Sets or Resets the TIMx Master/Slave Mode. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. +* This paramter can be one of the following values: +* @arg TIM_MasterSlaveMode_Enable: synchronization between the +* current timer and its slaves (through TRGO). +* @arg TIM_MasterSlaveMode_Disable: No action +* @retval : None +*/ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCR &= SMCR_MSM_Reset; + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** +* @brief Sets the TIMx Counter Register value +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param Counter: specifies the Counter register new value. +* @retval : None +*/ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** +* @brief Sets the TIMx Autoreload Register value +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param Autoreload: specifies the Autoreload register new value. +* @retval : None +*/ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** +* @brief Sets the TIMx Capture Compare1 Register value +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param Compare1: specifies the Capture Compare1 register new value. +* @retval : None +*/ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** +* @brief Sets the TIMx Capture Compare2 Register value +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param Compare2: specifies the Capture Compare2 register new value. +* @retval : None +*/ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** +* @brief Sets the TIMx Capture Compare3 Register value +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param Compare3: specifies the Capture Compare3 register new value. +* @retval : None +*/ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** +* @brief Sets the TIMx Capture Compare4 Register value +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param Compare4: specifies the Capture Compare4 register new value. +* @retval : None +*/ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** +* @brief Sets the TIMx Input Capture 1 prescaler. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICPSC: specifies the Input Capture1 prescaler +* new value. +* This parameter can be one of the following values: +* @arg TIM_ICPSC_DIV1: no prescaler +* @arg TIM_ICPSC_DIV2: capture is done once every 2 events +* @arg TIM_ICPSC_DIV4: capture is done once every 4 events +* @arg TIM_ICPSC_DIV8: capture is done once every 8 events +* @retval : None +*/ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= CCMR_IC13PSC_Mask; + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** +* @brief Sets the TIMx Input Capture 2 prescaler. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICPSC: specifies the Input Capture2 prescaler +* new value. +* This parameter can be one of the following values: +* @arg TIM_ICPSC_DIV1: no prescaler +* @arg TIM_ICPSC_DIV2: capture is done once every 2 events +* @arg TIM_ICPSC_DIV4: capture is done once every 4 events +* @arg TIM_ICPSC_DIV8: capture is done once every 8 events +* @retval : None +*/ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= CCMR_IC24PSC_Mask; + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** +* @brief Sets the TIMx Input Capture 3 prescaler. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICPSC: specifies the Input Capture3 prescaler +* new value. +* This parameter can be one of the following values: +* @arg TIM_ICPSC_DIV1: no prescaler +* @arg TIM_ICPSC_DIV2: capture is done once every 2 events +* @arg TIM_ICPSC_DIV4: capture is done once every 4 events +* @arg TIM_ICPSC_DIV8: capture is done once every 8 events +* @retval : None +*/ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= CCMR_IC13PSC_Mask; + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** +* @brief Sets the TIMx Input Capture 4 prescaler. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICPSC: specifies the Input Capture4 prescaler +* new value. +* This parameter can be one of the following values: +* @arg TIM_ICPSC_DIV1: no prescaler +* @arg TIM_ICPSC_DIV2: capture is done once every 2 events +* @arg TIM_ICPSC_DIV4: capture is done once every 4 events +* @arg TIM_ICPSC_DIV8: capture is done once every 8 events +* @retval : None +*/ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= CCMR_IC24PSC_Mask; + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** +* @brief Sets the TIMx Clock Division value. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_CKD: specifies the clock division value. +* This parameter can be one of the following value: +* @arg TIM_CKD_DIV1: TDTS = Tck_tim +* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim +* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim +* @retval : None +*/ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CR1 &= CR1_CKD_Mask; + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; + +} + +/** +* @brief Gets the TIMx Input Capture 1 value. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @retval : Capture Compare 1 Register value. +*/ +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** +* @brief Gets the TIMx Input Capture 2 value. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @retval : Capture Compare 2 Register value. +*/ +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** +* @brief Gets the TIMx Input Capture 3 value. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @retval : Capture Compare 3 Register value. +*/ +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** +* @brief Gets the TIMx Input Capture 4 value. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @retval : Capture Compare 4 Register value. +*/ +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** +* @brief Gets the TIMx Counter value. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @retval : Counter Register value. +*/ +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** +* @brief Gets the TIMx Prescaler value. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @retval : Prescaler Register value. +*/ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** +* @brief Checks whether the specified TIM flag is set or not. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg TIM_FLAG_Update: TIM update Flag +* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag +* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag +* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag +* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag +* @arg TIM_FLAG_COM: TIM Commutation Flag +* @arg TIM_FLAG_Trigger: TIM Trigger Flag +* @arg TIM_FLAG_Break: TIM Break Flag +* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag +* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag +* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag +* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag +* @retval : The new state of TIM_FLAG (SET or RESET). +*/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + assert_param(IS_TIM_PERIPH_FLAG(TIMx, TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the TIMx's pending flags. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* @arg TIM_FLAG_Update: TIM update Flag +* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag +* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag +* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag +* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag +* @arg TIM_FLAG_COM: TIM Commutation Flag +* @arg TIM_FLAG_Trigger: TIM Trigger Flag +* @arg TIM_FLAG_Break: TIM Break Flag +* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag +* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag +* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag +* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag +* @retval : None +*/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIMx, TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** +* @brief Checks whether the TIM interrupt has occurred or not. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* @arg TIM_IT_Update: TIM update Interrupt source +* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* @arg TIM_IT_COM: TIM Commutation Interrupt +* source +* @arg TIM_IT_Trigger: TIM Trigger Interrupt source +* @arg TIM_IT_Break: TIM Break Interrupt source +* @retval : The new state of the TIM_IT(SET or RESET). +*/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the TIMx's interrupt pending bits. +* @param TIMx: where x can be 1 to 4 to select the TIM peripheral. +* @param TIM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* @arg TIM_IT_Update: TIM1 update Interrupt source +* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* @arg TIM_IT_COM: TIM Commutation Interrupt +* source +* @arg TIM_IT_Trigger: TIM Trigger Interrupt source +* @arg TIM_IT_Break: TIM Break Interrupt source +* @retval : None +*/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** +* @brief Configure the TI1 as Input. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to +* be connected to IC1. +* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to +* be connected to IC2. +* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be +* connected to TRC. +* @param TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval : None +*/ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= CCER_CC1E_Reset; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr1 |= TIM_ICSelection | (uint16_t)(TIM_ICFilter << 4); + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= CCER_CC1P_Reset; + tmpccer |= TIM_ICPolarity | CCER_CC1E_Set; + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** +* @brief Configure the TI2 as Input. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to +* be connected to IC2. +* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to +* be connected to IC1. +* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be +* connected to TRC. +* @param TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval : None +*/ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC2E_Reset; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= CCER_CC2P_Reset; + tmpccer |= tmp | CCER_CC2E_Set; + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** +* @brief Configure the TI3 as Input. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to +* be connected to IC3. +* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to +* be connected to IC4. +* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be +* connected to TRC. +* @param TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval : None +*/ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= CCER_CC3E_Reset; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr2 |= TIM_ICSelection | (uint16_t)(TIM_ICFilter << 4); + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= CCER_CC3P_Reset; + tmpccer |= tmp | CCER_CC3E_Set; + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** +* @brief Configure the TI1 as Input. +* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM +* peripheral. +* @param TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to +* be connected to IC4. +* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to +* be connected to IC3. +* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be +* connected to TRC. +* @param TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval : None +*/ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= CCER_CC4E_Reset; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= CCER_CC4P_Reset; + tmpccer |= tmp | CCER_CC4E_Set; + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_uart.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_uart.c new file mode 100644 index 0000000000..7a8101dc17 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_uart.c @@ -0,0 +1,463 @@ +/** +****************************************************************************** +* @file HAL_UART.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the UART firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_uart.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup UART +* @brief UART driver modules +* @{ +*/ + +/** @defgroup UART_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Private_Defines +* @{ +*/ + + + +/* UART UE Mask */ +#define GCR_UE_Set ((uint16_t)0x0001) /* UART Enable Mask */ +#define GCR_UE_Reset ((uint16_t)0xFFFE) /* UART Disable Mask */ + +//#define CCR_CLEAR_Mask ((uint32_t)0xFFFFFF30) /* UART CCR Mask */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFFFFC9) /* UART CCR Mask */ +#define GCR_CLEAR_Mask ((uint32_t)0xFFFFFFE0) /* UART GCR Mask */ +/** +* @} +*/ + +/** @defgroup UART_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the UARTx peripheral registers to their +* default reset values. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @retval : None +*/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + switch (*(uint32_t*)&UARTx) + { + case UART1_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART1, DISABLE); + break; + case UART2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART2, DISABLE); + break; + case UART3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART3, DISABLE); + break; + default: + break; + } +} + +/** +* @brief Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* @retval : None +*/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t tmpreg1 = 0x00; + uint32_t UARTxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_BAUDRATE(UART_InitStruct->UART_BaudRate)); + assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength)); + assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); + assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); + assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); + + UARTxbase = (*(uint32_t*)&UARTx); + /*---------------------------- UART CCR Configuration -----------------------*/ + /* get UART CCR values */ + tmpreg = UARTx->CCR; + /* Clear spb,psel,pen bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure the UART Word Length,the UART Stop Bits,Parity ------------*/ + /* Set the char bits according to UART_WordLength value */ + /* Set spb bit according to UART_StopBits value */ + /* Set PEN bit according to UART_Parity value */ + tmpreg |= (uint32_t)UART_InitStruct->UART_WordLength | (uint32_t)UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity; + + /* Write to UART CCR */ + UARTx->CCR = tmpreg; + + /*---------------------------- UART GCR Configuration -----------------------*/ + /* get UART GCR values */ + tmpreg = UARTx->GCR; + /* Clear TXEN and RXEN ,autoflowen, mode ,uarten bits */ + tmpreg &= GCR_CLEAR_Mask; + /* Set autorlowen bit according to UART_HardwareFlowControl value */ + /* Set rxen,txen bits according to UART_Mode value */ + tmpreg |= UART_InitStruct->UART_HardwareFlowControl | UART_InitStruct->UART_Mode ; + /* Write to UART GCR */ + UARTx->GCR = tmpreg; + /*---------------------------- UART BRR Configuration -----------------------*/ + /* Configure the UART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (UARTxbase == UART1_BASE) + { + + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + + } + else + { + + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + /* Determine the UART_baud*/ + + tmpreg = (apbclock / UART_InitStruct->UART_BaudRate) / 16; + tmpreg1 = (apbclock / UART_InitStruct->UART_BaudRate) % 16; + UARTx->BRR = tmpreg; + UARTx->FRA = tmpreg1; +} + +/** +* @brief Fills each UART_InitStruct member with its default value. +* @param UART_InitStruct: pointer to a UART_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_WordLength = UART_WordLength_8b; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_No ; + UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; +} + + +/** +* @brief Enables or disables the specified UART peripheral. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected UART by setting the uarten bit in the GCR register */ + UARTx->GCR |= GCR_UE_Set; + } + else + { + /* Disable the selected UART by clearing the uarten bit in the GCR register */ + UARTx->GCR &= GCR_UE_Reset; + } +} + +/** +* @brief Enables or disables the specified UART interrupts. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param UART_IT: specifies the UART interrupt sources to be +* enabled or disabled. +* This parameter can be one of the following values: +* +* @arg UART_IT_ERR: Error interrupt(Frame error,) +* @arg UART_IT_PE: Parity Error interrupt +* @arg UART_OVER_ERR: overrun Error interrupt +* @arg UART_TIMEOUT_ERR: timeout Error interrupt +* @arg UART_IT_RXIEN: Receive Data register interrupt +* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt +* @param NewState: new state of the specified UARTx interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CONFIG_IT(UART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the UART_IT interrupt */ + UARTx->IER |= UART_IT; + } + else + { + /* Disable the UART_IT interrupt */ + UARTx->IER &= ~ UART_IT; + } +} + +/** +* @brief Enables or disables the UARTs DMA interface. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3 . +* @param UART_DMAReq: specifies the DMA request. +* This parameter can be any combination of the following values: +* @arg UART_DMAReq_EN: UART DMA transmit request +* +* @param NewState: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* @note The DMA mode is not available for UART5. +* @retval : None +*/ +void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_1234_PERIPH(UARTx)); + assert_param(IS_UART_DMAREQ(UART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer */ + UARTx->GCR |= UART_DMAReq; + } + else + { + /* Disable the DMA transfer */ + UARTx->GCR &= ~UART_DMAReq; + } +} + + +/** +* @brief Transmits single data through the UARTx peripheral. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param Data: the data to transmit. +* @retval : None +*/ +void UART_SendData(UART_TypeDef* UARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_DATA(Data)); + + /* Transmit Data */ + UARTx->TDR = (Data & (uint16_t)0x00FF); +} + +/** +* @brief Returns the most recent received data by the UARTx peripheral. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @retval : The received data. +*/ +uint16_t UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + /* Receive Data */ + return (uint16_t)(UARTx->RDR & (uint16_t)0x00FF); +} + + +/** +* @brief Checks whether the specified UART flag is set or not. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg UART_FLAG_TXEMPTY:Transmit data register empty flag +* @arg UART_FLAG_TXFULL:Transmit data buffer full +* @arg UART_FLAG_RXAVL:RX Buffer has a byte flag +* @arg UART_FLAG_OVER:OverRun Error flag +* @arg UART_FLAG_TXEPT: tx and shifter are emptys flag +* @retval : The new state of UART_FLAG (SET or RESET). +*/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_FLAG(UART_FLAG)); + if ((UARTx->CSR & UART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the UARTx's pending flags. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3, UART4 or UART5. +* @param UART_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* @arg UART_FLAG_TXEMPTY:Transmit data register empty flag +* @arg UART_FLAG_TXFULL:Transmit data buffer full +* @arg UART_FLAG_RXAVL:RX Buffer has a byte flag +* @arg UART_FLAG_OVER:OverRun Error flag +* @arg UART_FLAG_TXEPT: tx and shifter are emptys flag +* @retval : None +*/ +void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + +} + +/** +* @brief Checks whether the specified UART interrupt has occurred or not. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param UART_IT: specifies the UART interrupt source to check. +* This parameter can be one of the following values: +* @arg UART_IT_ERR: Error interrupt(Frame error,) +* @arg UART_IT_PE: Parity Error interrupt +* @arg UART_OVER_ERR: overrun Error interrupt +* @arg UART_TIMEOUT_ERR: timeout Error interrupt +* @arg UART_IT_RXIEN: Receive Data register interrupt +* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt +* @retval : The new state of UART_IT (SET or RESET). +*/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_FLAG(UART_FLAG)); + assert_param(IS_UART_PERIPH_FLAG(UARTx, UART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ + if ((UARTx->ISR & UART_IT) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the UARTxs interrupt pending bits. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3, UART4 or UART5. +* @param UART_IT: specifies the interrupt pending bit to clear. +* This parameter can be one of the following values: +* @arg UART_IT_ERR: Error interrupt(Frame error,) +* @arg UART_IT_PE: Parity Error interrupt +* @arg UART_OVER_ERR: overrun Error interrupt +* @arg UART_TIMEOUT_ERR: timeout Error interrupt +* @arg UART_IT_RXIEN: Receive Data register interrupt +* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt + +* @retval : None +*/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CLEAR_IT(UART_IT)); + assert_param(IS_UART_PERIPH_IT(UARTx, UART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ + /*clear UART_IT pendings bit*/ + UARTx->ICR = UART_IT; +} +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_wwdg.c b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_wwdg.c new file mode 100644 index 0000000000..ca4853362d --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_wwdg.c @@ -0,0 +1,221 @@ +/** +****************************************************************************** +* @file HAL_wwdg.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file provides all the WWDG firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT,MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_wwdg.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup WWDG +* @brief WWDG driver modules +* @{ +*/ + +/** @defgroup WWDG_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Private_Defines +* @{ +*/ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** +* @} +*/ + +/** @defgroup WWDG_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the WWDG peripheral registers to their default +* reset values. +* @param None +* @retval : None +*/ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** +* @brief Sets the WWDG Prescaler. +* @param WWDG_Prescaler: specifies the WWDG Prescaler. +* This parameter can be one of the following values: +* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 +* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 +* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 +* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 +* @retval : None +*/ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** +* @brief Sets the WWDG window value. +* @param WindowValue: specifies the window value to be compared to +* the downcounter. +* This parameter value must be lower than 0x80. +* @retval : None +*/ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + tmpreg = WWDG->CFR & CFR_W_Mask; + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & BIT_Mask; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** +* @brief Enables the WWDG Early Wakeup interrupt(EWI). +* @param None +* @retval : None +*/ +void WWDG_EnableIT(void) +{ + WWDG->CFR |= (uint32_t)0x200; +} + +/** +* @brief Sets the WWDG counter value. +* @param Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* @retval : None +*/ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** +* @brief Enables WWDG and load the counter value. +* @param Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* @retval : None +*/ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** +* @brief Checks whether the Early Wakeup interrupt flag is set or not. +* @param None +* @retval : The new state of the Early Wakeup interrupt flag (SET or RESET) +*/ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** +* @brief Clears Early Wakeup interrupt flag. +* @param None +* @retval : None +*/ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/MM32F103/Include/HAL_device.h b/bsp/mm32f103x/Libraries/MM32F103/Include/HAL_device.h new file mode 100644 index 0000000000..bfb4e6bd8a --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/Include/HAL_device.h @@ -0,0 +1,37 @@ +/** +****************************************************************************** +* @file HAL_device.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief This file contains all the Device inc file for the library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __HAL_device_H +#define __HAL_device_H + + +#define MM32F103 + +#if defined(MM32F103) +#include "MM32F103.h" +#include "SYSTEM_MM32F103.h" +#else +#error "HAL_device.h: PART NUMBER undefined" +#endif +#endif /* __HAL_device_H */ +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ + diff --git a/bsp/mm32f103x/Libraries/MM32F103/Include/MM32F103.h b/bsp/mm32f103x/Libraries/MM32F103/Include/MM32F103.h new file mode 100644 index 0000000000..0bc29e2546 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/Include/MM32F103.h @@ -0,0 +1,4404 @@ +/** +****************************************************************************** +* @file MM32F103.h +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. +* This file contains all the peripheral register's definitions, bits +* definitions and memory mapping for MM32F103 High Density, Medium +* Density and Low Density devices. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+*/ +/** @addtogroup CMSIS +* @{ +*/ + +/** @addtogroup MM32F103 +* @{ +*/ + +#ifndef __MM32F103_H +#define __MM32F103_H + +/** @addtogroup Library_configuration_section +* @{ +*/ + + + +#if !defined USE_STDPERIPH_DRIVER +/** +* @brief Comment the line below if you will not use the peripherals drivers. +In this case, these drivers will not be included and the application code will +be based on direct access to peripherals registers +*/ +/*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** +* @brief In the following line adjust the value of External High Speed oscillator (HSE) +used in your application +*/ +#define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ +#define HSE_VALUE HSE_Value +/** +* @brief In the following line adjust the External High Speed oscillator (HSE) Startup +Timeout value +*/ +#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#define HSE_STARTUP_TIMEOUT HSEStartUp_TimeOut + +#define HSI_Value_Pll_ON ((uint32_t)48000000/4) /*!< Value of the Internal oscillator in Hz*/ +#define HSI_VALUE_PLL_ON HSI_Value_Pll_ON + +#define HSI_Value_Pll_OFF ((uint32_t)48000000/6) /*!< Value of the Internal oscillator in Hz*/ +#define HSI_VALUE_PLL_OFF HSI_Value_Pll_OFF + +/*!< [31:16] MM32F103 Standard Peripheral Library main version */ +#define __MM32F103_STDPERIPH_VERSION_MAIN (0x01) +/*!< [15:8] MM32F103 Standard Peripheral Library sub1 version */ +#define __MM32F103_STDPERIPH_VERSION_SUB1 (0x00) +/*!< [7:0] MM32F103 Standard Peripheral Library sub2 version */ +#define __MM32F103_STDPERIPH_VERSION_SUB2 (0x00) +/*!< MM32F103 Standard Peripheral Library version number */ +#define __MM32F103_STDPERIPH_VERSION ((__MM32F103_STDPERIPH_VERSION_MAIN << 16)\ + | (__MM32F103_STDPERIPH_VERSION_SUB1 << 8)\ + | __MM32F103_STDPERIPH_VERSION_SUB2) + +/** +* @} +*/ + +/** @addtogroup Configuration_section_for_CMSIS +* @{ +*/ + +/** +* @brief Configuration of the Cortex-M3 Processor and Core Peripherals +*/ +#define __MPU_PRESENT 0 /*!< MM32F103 does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< MM32F103 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + + /****** MM32F103 CM3 specific Interrupt Numbers *********************************************************/ + + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 et ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB High Priority or CAN1 TX Interrupts */ + + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + UART1_IRQn = 37, /*!< UART1 global Interrupt */ + UART2_IRQn = 38, /*!< UART2 global Interrupt */ + UART3_IRQn = 39, /*!< UART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB WakeUp from suspend through EXTI Line Interrupt */ + + +} IRQn_Type; + + + + +/** +* @} +*/ + +#include + +#include + +/** @addtogroup Exported_types +* @{ +*/ + +/*!< MM32F103 Standard Peripheral Library old types (maintained for legacy prupose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** +* @} +*/ + +typedef struct +{ + __IO uint32_t SHCSR; //0XE000DE24 + __IO uint8_t MFSR; //0XE000DE28 + __IO uint8_t BFSR; //0XE000DE29 + __IO uint16_t UFSR; //0XE000DE2A + __IO uint32_t HFSR; //0XE000DE2C + __IO uint32_t DFSR; //0XE000DE30 + __IO uint32_t MMAR; //0XE000DE34 + __IO uint32_t BFAR; //0XE000DE38 +} HARD_FAULT_TypeDef; + + +/** @addtogroup Peripheral_registers_structures +* @{ +*/ + +/** +* @brief Analog to Digital Converter +*/ + +typedef struct +{ + __IO uint32_t ADDATA; + __IO uint32_t ADCFG; + __IO uint32_t ADCR; + __IO uint32_t ADCHS; + __IO uint32_t ADCMPR; + __IO uint32_t ADSTA; + __IO uint32_t ADDR0; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t ADDR3; + __IO uint32_t ADDR4; + __IO uint32_t ADDR5; + __IO uint32_t ADDR6; + __IO uint32_t ADDR7; + __IO uint32_t ADDR8; +} ADC_TypeDef; + +/** +* @brief Backup Registers +*/ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; +} BKP_TypeDef; + +/** +* @brief CAN basic +*/ +typedef struct +{ + __IO uint32_t CR; //0x00 + __IO uint32_t CMR; //0x04 + __IO uint32_t SR; //0x08 + __IO uint32_t IR; //0x0c + __IO uint32_t ACR; //0x10 + __IO uint32_t AMR; //0x14 + __IO uint32_t BTR0; //0x18 + __IO uint32_t BTR1; //0x1C + __IO uint32_t RESERVED0; //0x20 + uint32_t RESERVED1; //0x24 + __IO uint32_t TXID0; //0x28 + __IO uint32_t TXID1; //0x2c + __IO uint32_t TXDR0; //0x30 + __IO uint32_t TXDR1; //0x34 + __IO uint32_t TXDR2; //0x38 + __IO uint32_t TXDR3; //0x3c + __IO uint32_t TXDR4; //0x40 + __IO uint32_t TXDR5; //0x44 + __IO uint32_t TXDR6; //0x48 + __IO uint32_t TXDR7; //0x4c + __IO uint32_t RXID0; //0x50 + __IO uint32_t RXID1; //0x54 + __IO uint32_t RXDR0; //0x58 + __IO uint32_t RXDR1; //0x5C + __IO uint32_t RXDR2; //0x60 + __IO uint32_t RXDR3; + __IO uint32_t RXDR4; + __IO uint32_t RXDR5; //0x6c + __IO uint32_t RXDR6; //0x70 + __IO uint32_t RXDR7; //0x74 + uint32_t RESERVED2; + __IO uint32_t CDR; //0x7c +} CAN_TypeDef; + +/** +* @brief CAN Peli +*/ +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t CMR; + __IO uint32_t SR; + __IO uint32_t IR; + __IO uint32_t IER; //0x10h + uint32_t RESERVED0; + __IO uint32_t BTR0; + __IO uint32_t BTR1; + uint32_t RESERVED1; //0x20h + uint32_t RESERVED2; + uint32_t RESERVED3; + __IO uint32_t ALC; + __IO uint32_t ECC; //0x30h + __IO uint32_t EWLR; + __IO uint32_t RXERR; + __IO uint32_t TXERR; + __IO uint32_t FF; //0x40 + __IO uint32_t ID0; + __IO uint32_t ID1; + __IO uint32_t DATA0; + __IO uint32_t DATA1; //0x50 + __IO uint32_t DATA2; + __IO uint32_t DATA3; + __IO uint32_t DATA4; + __IO uint32_t DATA5; //0x60 + __IO uint32_t DATA6; + __IO uint32_t DATA7; + __IO uint32_t DATA8; + __IO uint32_t DATA9; //0x70 + __IO uint32_t RMC; + __IO uint32_t RBSA; + __IO uint32_t CDR; +} CAN_Peli_TypeDef; + + +/** +* @brief CRC calculation unit +*/ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** +* @brief Digital to Analog Converter +*/ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + + +/** +* @brief Debug MCU +*/ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +} DBGMCU_TypeDef; + +/** +* @brief DMA Controller +*/ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** +* @brief External Interrupt/Event Controller +*/ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** +* @brief FLASH Registers +*/ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** +* @brief Option Bytes Registers +*/ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + + + +/** +* @brief General Purpose IO +*/ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** +* @brief Alternate Function IO +*/ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; +} AFIO_TypeDef; +/** +* @brief Inter-integrated Circuit Interface +*/ + +typedef struct +{ + __IO uint16_t IC_CON; + uint16_t RESERVED0; + __IO uint16_t IC_TAR; + uint16_t RESERVED1; + __IO uint16_t IC_SAR; + uint16_t RESERVED2; + __IO uint16_t IC_HS_MADDR; + uint16_t RESERVED3; + __IO uint16_t IC_DATA_CMD; + uint16_t RESERVED4; + __IO uint16_t IC_SS_SCL_HCNT; + uint16_t RESERVED5; + __IO uint16_t IC_SS_SCL_LCNT; + uint16_t RESERVED6; + __IO uint16_t IC_FS_SCL_HCNT; + uint16_t RESERVED7; + __IO uint16_t IC_FS_SCL_LCNT; + uint16_t RESERVED8; + __IO uint16_t IC_HS_SCL_HCNT; + uint16_t RESERVED9; + __IO uint16_t IC_HS_SCL_LCNT; + uint16_t RESERVED10; + __IO uint16_t IC_INTR_STAT; + uint16_t RESERVED11; + __IO uint16_t IC_INTR_MASK; + uint16_t RESERVED12; + __IO uint16_t IC_RAW_INTR_STAT; + uint16_t RESERVED13; + __IO uint16_t IC_RX_TL; + uint16_t RESERVED14; + __IO uint16_t IC_TX_TL; + uint16_t RESERVED15; + __IO uint16_t IC_CLR_INTR; + uint16_t RESERVED16; + __IO uint16_t IC_CLR_RX_UNDER; + uint16_t RESERVED17; + __IO uint16_t IC_CLR_RX_OVER; + uint16_t RESERVED18; + __IO uint16_t IC_CLR_TX_OVER; + uint16_t RESERVED19; + __IO uint16_t IC_CLR_RD_REQ; + uint16_t RESERVED20; + __IO uint16_t IC_CLR_TX_ABRT; + uint16_t RESERVED21; + __IO uint16_t IC_CLR_RX_DONE; + uint16_t RESERVED22; + __IO uint16_t IC_CLR_ACTIVITY; + uint16_t RESERVED23; + __IO uint16_t IC_CLR_STOP_DET; + uint16_t RESERVED24; + __IO uint16_t IC_CLR_START_DET; + uint16_t RESERVED25; + __IO uint16_t IC_CLR_GEN_CALL; + uint16_t RESERVED26; + __IO uint16_t IC_ENABLE; //RESERVED + uint16_t RESERVED27; + + __IO uint32_t IC_STATUS; + __IO uint32_t IC_TXFLR; //RESERVED + __IO uint32_t IC_RXFLR; //RESERVED + __IO uint32_t IC_SDA_HOLD; //RESERVED + __IO uint32_t IC_TX_ABRT_SOURCE; //RESERVED + __IO uint32_t IC_SLV_DATA_NACK_ONLY; //RESERVED + __IO uint32_t IC_DMA_CR; //RESERVED + __IO uint32_t IC_DMA_TDLR; //RESERVED + __IO uint32_t IC_DMA_RDLR; //RESERVED + __IO uint32_t IC_SDA_SETUP; //RESERVED + __IO uint32_t IC_ACK_GENERAL_CALL; //RESERVED + + __IO uint32_t IC_FS_SPKLEN; + __IO uint32_t IC_HS_SPKLEN; + + __IO uint16_t IC_CLR_RESTART_DET; + uint16_t RESERVED28; + __IO uint32_t IC_COMP_PARAM_1; + __IO uint32_t IC_COMP_VERSION; + __IO uint32_t IC_COMP_TYPE; + +} I2C_TypeDef; + +/** +* @brief Independent WATCHDOG +*/ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** +* @brief Power Control +*/ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** +* @brief Reset and Clock Control +*/ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; +} RCC_TypeDef; + +/** +* @brief Real-Time Clock +*/ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + + +/** +* @brief Serial Peripheral Interface +*/ + + +typedef struct +{ + __IO uint32_t TXREG; + __IO uint32_t RXREG; + __IO uint16_t CSTAT; + uint16_t RESERVED0; + __IO uint16_t INTSTAT; + uint16_t RESERVED1; + __IO uint16_t INTEN; + uint16_t RESERVED2; + __IO uint16_t INTCLR; + uint16_t RESERVED3; + __IO uint16_t GCTL; + uint16_t RESERVED4; + __IO uint16_t CCTL; + uint16_t RESERVED5; + __IO uint16_t SPBRG; + uint16_t RESERVED6; + __IO uint16_t RXDNR; + uint16_t RESERVED7; + __IO uint16_t SCSR; + uint16_t RESERVED8; + __IO uint16_t EXTCTL; + uint16_t RESERVED9; +} SPI_TypeDef; + + + + +/** +* @brief TIM +*/ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** +* @brief Universal Synchronous Asynchronous Receiver Transmitter +*/ + +typedef struct +{ + __IO uint32_t TDR; + __IO uint32_t RDR; + __IO uint32_t CSR; + __IO uint32_t ISR; + __IO uint32_t IER; + __IO uint32_t ICR; + __IO uint32_t GCR; + __IO uint32_t CCR; + __IO uint32_t BRR; + __IO uint32_t FRA; + +} UART_TypeDef; + +/** +* @brief Window WATCHDOG +*/ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + + +/** +* @brief USB +*/ +typedef struct +{ + __IO uint32_t rTOP; /*! Address offset: 0x00 */ + __IO uint32_t rINT_STATE; /*! Address offset: 0x04 */ + __IO uint32_t rEP_INT_STATE; /*! Address offset: 0x08 */ + __IO uint32_t rEP0_INT_STATE; /*! Address offset: 0x0C */ + __IO uint32_t rINT_EN; /*! Address offset: 0x10 */ + __IO uint32_t rEP_INT_EN; /*! Address offset: 0x14 */ + __IO uint32_t rEP0_INT_EN; /*! Address offset: 0x18 */ + + __IO uint32_t RESERVED0; + + //__IO uint32_t rEP1_4_INT_STATE[4]; /*! Address offset: 0x20 */ + + __IO uint32_t rEP1_INT_STATE; /*! Address offset: 0x20 */ + __IO uint32_t rEP2_INT_STATE; /*! Address offset: 0x24 */ + __IO uint32_t rEP3_INT_STATE; /*! Address offset: 0x28 */ + __IO uint32_t rEP4_INT_STATE; /*! Address offset: 0x2C */ + + __IO uint32_t RESERVED1; /*! Address offset: 0x30 */ + __IO uint32_t RESERVED2; /*! Address offset: 0x34 */ + __IO uint32_t RESERVED3; /*! Address offset: 0x38 */ + __IO uint32_t RESERVED4; /*! Address offset: 0x3C */ + + __IO uint32_t rEP1_INT_EN; /*! Address offset: 0x40 */ + __IO uint32_t rEP2_INT_EN; /*! Address offset: 0x44 */ + __IO uint32_t rEP3_INT_EN; /*! Address offset: 0x48 */ + __IO uint32_t rEP4_INT_EN; /*! Address offset: 0x4C */ + + __IO uint32_t RESERVED5; /*! Address offset: 0x50 */ + __IO uint32_t RESERVED6; /*! Address offset: 0x54 */ + __IO uint32_t RESERVED7; /*! Address offset: 0x58 */ + __IO uint32_t RESERVED8; /*! Address offset: 0x5C */ + + __IO uint32_t rADDR; /*! Address offset: 0x60 */ + __IO uint32_t rEP_EN; /*! Address offset: 0x64 */ + + __IO uint32_t RESERVED9; /*! Address offset: 0x68 */ + __IO uint32_t RESERVED10; /*! Address offset: 0x6C */ + __IO uint32_t RESERVED11; /*! Address offset: 0x70 */ + __IO uint32_t RESERVED12; /*! Address offset: 0x74 */ + + __IO uint32_t rTOG_CTRL1_4; /*! Address offset: 0x78 */ + + __IO uint32_t RESERVED13; /*! Address offset: 0x7C */ + + __IO uint32_t rSETUP[8]; /*! Address offset: 0x80 */ + //__IO uint32_t rSETUP0; /*! Address offset: 0x80 */ + //__IO uint32_t rSETUP1; /*! Address offset: 0x84 */ + //__IO uint32_t rSETUP2; /*! Address offset: 0x88 */ + //__IO uint32_t rSETUP3; /*! Address offset: 0x8C */ + //__IO uint32_t rSETUP4; /*! Address offset: 0x90 */ + //__IO uint32_t rSETUP5; /*! Address offset: 0x94 */ + //__IO uint32_t rSETUP6; /*! Address offset: 0x98 */ + //__IO uint32_t rSETUP7; /*! Address offset: 0x9C */ + __IO uint32_t rPAKET_SIZE0; /*! Address offset: 0xA0 */ + __IO uint32_t rPAKET_SIZE1; /*! Address offset: 0xA4 */ + + __IO uint32_t RESERVED14; /*! Address offset: 0xA8 */ + __IO uint32_t RESERVED15; /*! Address offset: 0xAC */ + + __IO uint32_t RESERVED16; /*! Address offset: 0xB0 */ + __IO uint32_t RESERVED17; /*! Address offset: 0xB4 */ + __IO uint32_t RESERVED18; /*! Address offset: 0xB8 */ + __IO uint32_t RESERVED19; /*! Address offset: 0xBC */ + + __IO uint32_t RESERVED20; /*! Address offset: 0xC0 */ + __IO uint32_t RESERVED21; /*! Address offset: 0xC4 */ + __IO uint32_t RESERVED22; /*! Address offset: 0xC8 */ + __IO uint32_t RESERVED23; /*! Address offset: 0xCC */ + + __IO uint32_t RESERVED24; /*! Address offset: 0xD0 */ + __IO uint32_t RESERVED25; /*! Address offset: 0xD4 */ + __IO uint32_t RESERVED26; /*! Address offset: 0xD8 */ + __IO uint32_t RESERVED27; /*! Address offset: 0xDC */ + + __IO uint32_t RESERVED28; /*! Address offset: 0xE0 */ + __IO uint32_t RESERVED29; /*! Address offset: 0xE4 */ + __IO uint32_t RESERVED30; /*! Address offset: 0xE8 */ + __IO uint32_t RESERVED31; /*! Address offset: 0xEC */ + + __IO uint32_t RESERVED32; /*! Address offset: 0xF0 */ + __IO uint32_t RESERVED33; /*! Address offset: 0xF4 */ + __IO uint32_t RESERVED34; /*! Address offset: 0xF8 */ + __IO uint32_t RESERVED35; /*! Address offset: 0xFC */ + + __IO uint32_t rEP0_AVIL; /*! Address offset: 0x100 */ + __IO uint32_t rEP1_AVIL; /*! Address offset: 0x104 */ + __IO uint32_t rEP2_AVIL; /*! Address offset: 0x108 */ + __IO uint32_t rEP3_AVIL; /*! Address offset: 0x10C */ + __IO uint32_t rEP4_AVIL; /*! Address offset: 0x110 */ + + __IO uint32_t RESERVED36; /*! Address offset: 0x114 */ + __IO uint32_t RESERVED37; /*! Address offset: 0x118 */ + __IO uint32_t RESERVED38; /*! Address offset: 0x11C */ + __IO uint32_t RESERVED39; /*! Address offset: 0x120 */ + + __IO uint32_t RESERVED40; /*! Address offset: 0x124 */ + __IO uint32_t RESERVED41; /*! Address offset: 0x128 */ + __IO uint32_t RESERVED42; /*! Address offset: 0x12C */ + __IO uint32_t RESERVED43; /*! Address offset: 0x130 */ + + __IO uint32_t RESERVED44; /*! Address offset: 0x134 */ + __IO uint32_t RESERVED45; /*! Address offset: 0x138 */ + __IO uint32_t RESERVED46; /*! Address offset: 0x13C */ + + __IO uint32_t rEP0_CTRL; /*! Address offset: 0x140 */ + __IO uint32_t rEP1_CTRL; /*! Address offset: 0x144 */ + __IO uint32_t rEP2_CTRL; /*! Address offset: 0x148 */ + __IO uint32_t rEP3_CTRL; /*! Address offset: 0x14C */ + __IO uint32_t rEP4_CTRL; /*! Address offset: 0x150 */ + + __IO uint32_t RESERVED47; /*! Address offset: 0x154 */ + __IO uint32_t RESERVED48; /*! Address offset: 0x158 */ + __IO uint32_t RESERVED49; /*! Address offset: 0x15C */ + //__IO uint32_t RESERVED50; /*! Address offset: 0x15C */ + + //__IO uint32_t rEPn_FIFO[5]; /*! Address offset: 0x160 */ + + __IO uint32_t rEP0_FIFO; /*! Address offset: 0x160 */ + __IO uint32_t rEP1_FIFO; /*! Address offset: 0x164 */ + __IO uint32_t rEP2_FIFO; /*! Address offset: 0x168 */ + __IO uint32_t rEP3_FIFO; /*! Address offset: 0x16C */ + __IO uint32_t rEP4_FIFO; /*! Address offset: 0x170 */ + + __IO uint32_t RESERVED51; /*! Address offset: 0x174 */ + __IO uint32_t RESERVED52; /*! Address offset: 0x178 */ + __IO uint32_t RESERVED53; /*! Address offset: 0x17C */ + + __IO uint32_t RESERVED54; /*! Address offset: 0x180 */ + + __IO uint32_t rEP_DMA; /*! Address offset: 0x184 */ + __IO uint32_t rEP_HALT; /*! Address offset: 0x188 */ + __IO uint32_t RESERVED55; /*! Address offset: 0x18C */ + + __IO uint32_t RESERVED56; /*! Address offset: 0x190 */ + __IO uint32_t RESERVED57; /*! Address offset: 0x194 */ + __IO uint32_t RESERVED58; /*! Address offset: 0x198 */ + __IO uint32_t RESERVED59; /*! Address offset: 0x19C */ + + __IO uint32_t RESERVED60; /*! Address offset: 0x1A0 */ + __IO uint32_t RESERVED61; /*! Address offset: 0x1A4 */ + __IO uint32_t RESERVED62; /*! Address offset: 0x1A8 */ + __IO uint32_t RESERVED63; /*! Address offset: 0x1AC */ + + __IO uint32_t RESERVED64; /*! Address offset: 0x1B0 */ + __IO uint32_t RESERVED65; /*! Address offset: 0x1B4 */ + __IO uint32_t RESERVED66; /*! Address offset: 0x1B8 */ + __IO uint32_t RESERVED67; /*! Address offset: 0x1BC */ + __IO uint32_t rPOWER; /*! Address offset: 0x1C0 */ +} USB_TypeDef; + +/** +* @} +*/ + +#define HARD_FAULT_MM ((HARD_FAULT_TypeDef*)0xE000DE24) + +/** @addtogroup Peripheral_memory_map +* @{ +*/ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ + +#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */ + + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) + +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) + +#define UART2_BASE (APB1PERIPH_BASE + 0x4400) +#define UART3_BASE (APB1PERIPH_BASE + 0x4800) + +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) //RESERVED +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) //RESERVED +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) //RESERVED +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) + +#define UART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) + +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + + + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +#define USB_BASE ((uint32_t)0x40005C00) + +/** +* @} +*/ + +/** @addtogroup Peripheral_declaration +* @{ +*/ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) + +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define UART3 ((UART_TypeDef *) UART3_BASE) + +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN1_PELI ((CAN_Peli_TypeDef *) CAN1_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)//RESERVED +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)//RESERVED +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)//RESERVED +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + + + +#define USB ((USB_TypeDef*) USB_BASE )//usb_base + +/** +* @} +*/ + +/** @addtogroup Exported_constants +* @{ +*/ + +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ + +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x1E00) /*!< PLS[3:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0400) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0800) /*!< Bit 2 */ +#define PWR_CR_PLS_3 ((uint16_t)0x1000) /*!< Bit 3 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0000) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x0200) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_3V0 ((uint16_t)0x0400) /*!< PVD level 3.0V */ +#define PWR_CR_PLS_3V2 ((uint16_t)0x0600) /*!< PVD level 3.2V */ +#define PWR_CR_PLS_3V4 ((uint16_t)0x0800) /*!< PVD level 3.4V */ +#define PWR_CR_PLS_3V6 ((uint16_t)0x0A00) /*!< PVD level 3.6V */ +#define PWR_CR_PLS_3V8 ((uint16_t)0x0C00) /*!< PVD level 3.8V */ +#define PWR_CR_PLS_4V0 ((uint16_t)0x0E00) /*!< PVD level 4.0V */ +#define PWR_CR_PLS_4V2 ((uint16_t)0x1000) /*!< PVD level 4.2V */ +#define PWR_CR_PLS_4V4 ((uint16_t)0x1200) /*!< PVD level 4.4V */ +#define PWR_CR_PLS_4V6 ((uint16_t)0x1400) /*!< PVD level 4.6V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#define RCC_CR_PLLDN ((uint32_t)0xFC000000) /*!< PLLDN[5:0] bits */ +#define RCC_CR_PLLDN_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define RCC_CR_PLLDN_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define RCC_CR_PLLDN_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define RCC_CR_PLLDN_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define RCC_CR_PLLDN_4 ((uint32_t)0x40000000) /*!< Bit 4 */ +#define RCC_CR_PLLDN_5 ((uint32_t)0x80000000) /*!< Bit 5 */ + +#define RCC_CR_PLLDM ((uint32_t)0x00700000) /*!< PLLDM[2:0] bits */ +#define RCC_CR_PLLDM_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define RCC_CR_PLLDM_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define RCC_CR_PLLDM_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +/******************* Bit definition for RCC_CFGR register *******************/ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +/*!< SW configuration */ +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +#define RCC_CFGR_USBPRE ((uint32_t)0x00C00000) /*!< USB prescaler BIT[1:0] */ +#define RCC_CFGR_USBPRE_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define RCC_CFGR_USBPRE_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +/*!< MCO configuration */ +#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) // +#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) +#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected */ +#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< Internal 48 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected*/ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< IO port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< IO port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< IO port D reset */ +#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< IO port E reset *///RESERVED +#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< IO port F reset *///RESERVED +#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< IO port G reset *///RESERVED +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_UART1RST ((uint32_t)0x00004000) /*!< UART1 reset */ +#define RCC_APB2RSTR_CPTRST ((uint32_t)0x0008000) /*!< CPT interface reset */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ +#define RCC_APB1RSTR_UART2RST ((uint32_t)0x00020000) /*!< UART 2 reset */ +#define RCC_APB1RSTR_UART3RST ((uint32_t)0x00040000) /*!< UART 3 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */ +#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */ +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ +#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMAEN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable *///RESERVED +#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable *///RESERVED +#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable *///RESERVED +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_UART1EN ((uint32_t)0x00004000) /*!< UART1 clock enable */ + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ +#define RCC_APB1ENR_UART2EN ((uint32_t)0x00020000) /*!< UART 2 clock enable */ +#define RCC_APB1ENR_UART3EN ((uint32_t)0x00040000) /*!< UART 3 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */ +#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */ +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ +#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function IO */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + + + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1 _REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_UART1_REMAP ((uint32_t)0x00000004) /*!< UART1 remapping */ + +#define AFIO_MAPR_UART3_REMAP ((uint32_t)0x00000030) /*!< UART3_REMAP[1:0] bits (UART3 remapping) */ +#define AFIO_MAPR_UART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + +/* UART3_REMAP configuration */ +#define AFIO_MAPR_UART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_UART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin *///RESERVED +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin *///RESERVED +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin *///RESERVED + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin *///RESERVED +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin *///RESERVED +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin *///RESERVED + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin *///RESERVED +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin *///RESERVED +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin *///RESERVED + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin *///RESERVED +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin *///RESERVED +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin *///RESERVED + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin *///RESERVED +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin *///RESERVED +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin *///RESERVED + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin *///RESERVED +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin *///RESERVED +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin *///RESERVED + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin *///RESERVED +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin *///RESERVED +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin *///RESERVED + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin *///RESERVED +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin *///RESERVED +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin *///RESERVED + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin *///RESERVED +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin *///RESERVED +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin *///RESERVED + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin *///RESERVED +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin *///RESERVED +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin *///RESERVED + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin *///RESERVED +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin *///RESERVED +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin *///RESERVED + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin *///RESERVED +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin *///RESERVED +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin *///RESERVED + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin *///RESERVED +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin *///RESERVED +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin *///RESERVED + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin *///RESERVED +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin *///RESERVED +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin *///RESERVED + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin *///RESERVED +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin *///RESERVED +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin *///RESERVED + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin *///RESERVED +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin *///RESERVED +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin *///RESERVED + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for NVIC_PRI8 register *******************/ +#define NVIC_IPR7_PRI_32 ((uint32_t)0x000000FF) /*!< Priority of interrupt 32 */ +#define NVIC_IPR7_PRI_33 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 33 */ +#define NVIC_IPR7_PRI_34 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 34 */ +#define NVIC_IPR7_PRI_35 ((uint32_t)0xFF000000) /*!< Priority of interrupt 35 */ + +/****************** Bit definition for NVIC_PRI9 register *******************/ +#define NVIC_IPR7_PRI_36 ((uint32_t)0x000000FF) /*!< Priority of interrupt 36 */ +#define NVIC_IPR7_PRI_37 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 37 */ +#define NVIC_IPR7_PRI_38 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 38 */ +#define NVIC_IPR7_PRI_39 ((uint32_t)0xFF000000) /*!< Priority of interrupt 39 */ + +/****************** Bit definition for NVIC_PRI10 register *******************/ +#define NVIC_IPR7_PRI_40 ((uint32_t)0x000000FF) /*!< Priority of interrupt 40 */ +#define NVIC_IPR7_PRI_41 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 41 */ +#define NVIC_IPR7_PRI_42 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 42 */ +#define NVIC_IPR7_PRI_43 ((uint32_t)0xFF000000) /*!< Priority of interrupt 43 */ + +/****************** Bit definition for NVIC_PRI11 register *******************/ +#define NVIC_IPR7_PRI_44 ((uint32_t)0x000000FF) /*!< Priority of interrupt 44 */ +#define NVIC_IPR7_PRI_45 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 45 */ +#define NVIC_IPR7_PRI_46 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 46 */ +#define NVIC_IPR7_PRI_47 ((uint32_t)0xFF000000) /*!< Priority of interrupt 47 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ +#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Trigger request occurred on the external interrupt line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) +#define EXTI_PR_PR20 ((uint32_t)0x00100000) +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!
© COPYRIGHT 2019 MindMotion
+*/ +#ifndef __SYSTEM_MM32F103_H__ +#define __SYSTEM_MM32F103_H__ + + +extern uint32_t SystemCoreClock; +void SystemInit (void); + +#endif /* __SYSTEM_MM32F103_H__ */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ + diff --git a/bsp/mm32f103x/Libraries/MM32F103/Source/IAR_StartAsm/startup_MM32F103.s b/bsp/mm32f103x/Libraries/MM32F103/Source/IAR_StartAsm/startup_MM32F103.s new file mode 100644 index 0000000000..385be18a40 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/Source/IAR_StartAsm/startup_MM32F103.s @@ -0,0 +1,333 @@ +;******************** (C) COPYRIGHT 2019 MindMotion ******************** +;* File Name : startup_MM32F103.s +;* Author : AE Team +;* Version : V1.1.0 +;* Date : 28/08/2019 +;* Description : MM32F103 Medium-density devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD UART1_IRQHandler ; UART1 + DCD UART2_IRQHandler ; UART2 + DCD UART3_IRQHandler ; UART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + END +;******************** (C) COPYRIGHT 2019 MindMotion ******************** diff --git a/bsp/mm32f103x/Libraries/MM32F103/Source/KEIL_StartAsm/startup_MM32F103.s b/bsp/mm32f103x/Libraries/MM32F103/Source/KEIL_StartAsm/startup_MM32F103.s new file mode 100644 index 0000000000..e9b9c0af67 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/Source/KEIL_StartAsm/startup_MM32F103.s @@ -0,0 +1,299 @@ +;******************** (C) COPYRIGHT 2019 MindMotion ******************** +;* File Name : startup_MM32F103.s +;* Author : AE Team +;* Version : V1.1.0 +;* Date : 28/08/2019 +;* Description : MM32F103 Medium-density devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD UART1_IRQHandler ; UART1 + DCD UART2_IRQHandler ; UART2 + DCD UART3_IRQHandler ; UART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line 17 + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************** (C) COPYRIGHT 2019 MindMotion ******************** diff --git a/bsp/mm32f103x/Libraries/MM32F103/Source/system_MM32F103.c b/bsp/mm32f103x/Libraries/MM32F103/Source/system_MM32F103.c new file mode 100644 index 0000000000..3b3312b516 --- /dev/null +++ b/bsp/mm32f103x/Libraries/MM32F103/Source/system_MM32F103.c @@ -0,0 +1,965 @@ +/** +****************************************************************************** +* @file system_MM32F103.c +* @author AE Team +* @version V1.1.0 +* @date 28/08/2019 +* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. +* +* 1. This file provides two functions and one global variable to be called from +* user application: +* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier +* factors, AHB/APBx prescalers and Flash settings). +* This function is called at startup just after reset and +* before branch to main program. This call is made inside +* the "startup_MM32F103.s" file. +* +* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used +* by the user application to setup the SysTick +* timer or configure other parameters. +* +* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must +* be called whenever the core clock is changed +* during program execution. +* +* 2. After each device reset the HSI (8 MHz) is used as system clock source. +* Then SystemInit() function is casslled, in "startup_MM32F103.s" file, to +* configure the system clock before to branch to main program. +* +* 3. If the system clock source selected by user fails to startup, the SystemInit() +* function will do nothing and HSI still used as system clock source. User can +* add some code to deal with this issue inside the SetSysClock() function. +* +* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on +* the product used), refer to "HSE_VALUE" define in "MM32F103.h" file. +* When HSE is used as system clock source, directly or through PLL, and you +* are using different crystal you have to adapt the HSE value to your own +* configuration. +* +****************************************************************************** +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2019 MindMotion

+****************************************************************************** +*/ + +/** @addtogroup CMSIS +* @{ +*/ +#include "HAL_device.h" + + +/** +* @} +*/ + +/** +* @} +*/ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) +frequency (after reset the HSI is used as SYSCLK source) + +IMPORTANT NOTE: +============== +1. After each device reset the HSI is used as System clock source. + +2. Please make sure that the selected System clock doesn't exceed your device's +maximum frequency. + +3. If none of the define below is enabled, the HSI is used as System clock +source. + +4. The System clock configuration functions provided within this file assume that: +- For Low, Medium and High density Value line devices an external 8MHz +crystal is used to drive the System clock. +- For Low, Medium and High density devices an external 8MHz crystal is +used to drive the System clock. +- For Connectivity line devices an external 25MHz crystal is used to drive +the System clock. +If you are using different crystal you have to adapt those functions accordingly. +*/ + +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_24MHz 24000000 +//#define SYSCLK_FREQ_36MHz 36000000 +//#define SYSCLK_FREQ_48MHz 48000000 +//#define SYSCLK_FREQ_56MHz 56000000 +//#define SYSCLK_FREQ_72MHz 72000000 +//#define SYSCLK_FREQ_96MHz 96000000 + +//#define SYSCLK_HSI_48MHz 48000000 +//#define SYSCLK_HSI_72MHz 72000000 +#define SYSCLK_HSI_96MHz 96000000 + +/*!< Uncomment the following line if you need to relocate your vector Table in +Internal SRAM. */ +//#define VECT_TAB_SRAM +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +This value must be a multiple of 0x200. */ + +/** +* @} +*/ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz +uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz +uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_HSI_48MHz +uint32_t SystemCoreClock = SYSCLK_HSI_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_HSI_72MHz +uint32_t SystemCoreClock = SYSCLK_HSI_72MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_HSI_96MHz +uint32_t SystemCoreClock = SYSCLK_HSI_96MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ +uint32_t SystemCoreClock = HSI_VALUE_PLL_OFF; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** +* @} +*/ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz +static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz +static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz +static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz +static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz +static void SetSysClockTo72(void); +#elif defined SYSCLK_FREQ_96MHz +static void SetSysClockTo96(void); + +#elif defined SYSCLK_HSI_48MHz +static void SetSysClockTo48_HSI(void); +#elif defined SYSCLK_HSI_72MHz +static void SetSysClockTo72_HSI(void); +#elif defined SYSCLK_HSI_96MHz +static void SetSysClockTo96_HSI(void); +#endif + +#ifdef DATA_IN_ExtSRAM +static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** +* @} +*/ + +/** +* @brief Setup the microcontroller system +* Initialize the Embedded Flash Interface, the PLL and update the +* SystemCoreClock variable. +* @note This function should be used only after reset. +* @param None +* @retval None +*/ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ + RCC->CFGR &= (uint32_t)0xF8FF000C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + RCC->CR &= (uint32_t)0x000FFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** +* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. +* @param None +* @retval None +*/ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#elif defined SYSCLK_FREQ_96MHz + SetSysClockTo96(); + +#elif defined SYSCLK_HSI_48MHz + SetSysClockTo48_HSI(); +#elif defined SYSCLK_HSI_72MHz + SetSysClockTo72_HSI(); +#elif defined SYSCLK_HSI_96MHz + SetSysClockTo96_HSI(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +#ifdef SYSCLK_FREQ_HSE +/** +* @brief Selects HSE as System clock source and configure HCLK, PCLK2 +* and PCLK1 prescalers. +* @note This function should be used only after reset. +* @param None +* @retval None +*/ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + u16 i = 0; + int nTime = 2; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } + while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + /*delay more than 2ms*/ + while(nTime--) + { + i = 750; + while(i--); + } + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state ,bit0~2*/ + FLASH->ACR &= ~0x07; + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** +* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 +* and PCLK1 prescalers. +* @note This function should be used only after reset. +* @param None +* @retval None +*/ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + u16 i = 0; + int nTime = 2; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } + while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + /*delay more than 2ms*/ + while(nTime--) + { + i = 750; + while(i--); + } + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + /* Flash 0 wait state ,bit0~2*/ + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x01; + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* PLL configuration: = (HSE ) * (2+1) = 24 MHz */ + RCC->CFGR &= (uint32_t)0xFFFCFFFF; + RCC->CR &= (uint32_t)0x000FFFFF; + + RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ; + RCC->CR |= 0x08000000;//pll=3/1 + //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** +* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 +* and PCLK1 prescalers. +* @note This function should be used only after reset. +* @param None +* @retval None +*/ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + u16 i = 0; + int nTime = 2; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } + while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + /*delay more than 2ms*/ + while(nTime--) + { + i = 750; + while(i--); + } + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state ,bit0~2*/ + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x01; + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* PLL configuration: = (HSE ) * (8+1)/(1+1) = 36 MHz */ + RCC->CFGR &= (uint32_t)0xFFFCFFFF; + RCC->CR &= (uint32_t)0x000FFFFF; + + RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ; + RCC->CR |= 0x20100000;//pll = 9/2 + //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** +* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 +* and PCLK1 prescalers. +* @note This function should be used only after reset. +* @param None +* @retval None +*/ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + u16 i = 0; + int nTime = 2; + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } + while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + /*delay more than 2ms*/ + while(nTime--) + { + i = 750; + while(i--); + } + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + /* Flash 0 wait state ,bit0~2*/ + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x01; + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration: = (HSE ) * (5+1) = 48MHz */ + RCC->CFGR &= (uint32_t)0xFFFCFFFF; + RCC->CR &= (uint32_t)0x000FFFFF; + + RCC->CFGR |= (uint32_t ) RCC_CFGR_PLLSRC ; + RCC->CR |= 0x14000000;//pll = 6/1 + //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** +* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 +* and PCLK1 prescalers. +* @note This function should be used only after reset. +* @param None +* @retval None +*/ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + u16 i = 0; + int nTime = 2; + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } + while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + /*delay more than 2ms*/ + while(nTime--) + { + i = 750; + while(i--); + } + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state ,bit0~2*/ + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x02; + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration: = (HSE ) * (6+1) = 56 MHz */ + RCC->CFGR &= (uint32_t)0xFFFCFFFF; + RCC->CR &= (uint32_t)0x000FFFFF; + + RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ; + RCC->CR |= 0x18000000;//pll = 7/1 + //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** +* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 +* and PCLK1 prescalers. +* @note This function should be used only after reset. +* @param None +* @retval None +*/ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + u16 i = 0; + int nTime = 2; + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } + while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + /*delay more than 2ms*/ + while(nTime--) + { + i = 750; + while(i--); + } + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + /* Flash 0 wait state ,bit0~2*/ + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x03; + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration: = (HSE ) * (8+1) = 72 MHz */ + RCC->CFGR &= (uint32_t)0xFFFCFFFF; + RCC->CR &= (uint32_t)0x000FFFFF; + + RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ; + // RCC->CR |= 0x20000000;//pll = 9/1 + RCC->CR |= (1 << 20) | (17 << 26); //pll = 9/1 + //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_96MHz +/** +* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 +* and PCLK1 prescalers. +* @note This function should be used only after reset. +* @param None +* @retval None +*/ +static void SetSysClockTo96(void) +{ + int i = 100000; + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + int nTime = 2; + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } + while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + /*delay more than 2ms*/ + while(nTime--) + { + i = 1500; + while(i--); + } + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + i = 10000; while(i--); + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + /* Flash 0 wait state ,bit0~2*/ + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x03; + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration: = (HSE ) * (11+1) = 96 MHz */ + RCC->CFGR &= (uint32_t)0xFFFCFFFF; + RCC->CR &= (uint32_t)0x000FFFFF; + + RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ; + RCC->CR |= 0x2C000000;//pll = 12/1 + //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + + + +#elif defined SYSCLK_HSI_48MHz +void SetSysClockTo48_HSI() +{ + unsigned char temp = 0; + + RCC->CR |= RCC_CR_HSION; + while(!(RCC->CR & RCC_CR_HSIRDY)); + RCC->CFGR = RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1; + + RCC->CFGR &= ~RCC_CFGR_PLLSRC; //PLLSRC ON + + RCC->CR &= ~(RCC_CR_PLLON); //PLL// RCC->CR &=~(7<<20); //PLL + + RCC->CR &= ~(0x1f << 26); + RCC->CR |= (4 - 1) << 26; //PLLֵ 2~16 + + FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE; //FLASH 2ʱ + + RCC->CR |= RCC_CR_PLLON; //PLLON + while(!(RCC->CR & RCC_CR_PLLRDY)); //ȴPLL + RCC->CFGR &= ~RCC_CFGR_SW; + RCC->CFGR |= RCC_CFGR_SW_PLL; //PLLΪϵͳʱ + while(temp != 0x02) //ȴPLLΪϵͳʱóɹ + { + temp = RCC->CFGR >> 2; + temp &= 0x03; + } +} +#elif defined SYSCLK_HSI_72MHz +void SetSysClockTo72_HSI() +{ + unsigned char temp = 0; + RCC->CR |= RCC_CR_HSION; + while(!(RCC->CR & RCC_CR_HSIRDY)); + RCC->CFGR = RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1; + + RCC->CFGR &= ~RCC_CFGR_PLLSRC; //PLLSRC ON + + RCC->CR &= ~(RCC_CR_PLLON); //PLL// RCC->CR &=~(7<<20); //PLL + + RCC->CR &= ~(0x1f << 26); + RCC->CR |= (6 - 1) << 26; //PLLֵ 2~16 + + FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE; //FLASH 2ʱ + + RCC->CR |= RCC_CR_PLLON; //PLLON + while(!(RCC->CR & RCC_CR_PLLRDY)); //ȴPLL + RCC->CFGR &= ~RCC_CFGR_SW; + RCC->CFGR |= RCC_CFGR_SW_PLL; //PLLΪϵͳʱ + while(temp != 0x02) //ȴPLLΪϵͳʱóɹ + { + temp = RCC->CFGR >> 2; + temp &= 0x03; + } +} +#elif defined SYSCLK_HSI_96MHz +void SetSysClockTo96_HSI() +{ + unsigned char temp = 0; + RCC->CR |= RCC_CR_HSION; + while(!(RCC->CR & RCC_CR_HSIRDY)); + RCC->CFGR = RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1; + + RCC->CFGR &= ~RCC_CFGR_PLLSRC; //PLLSRC ON + + RCC->CR &= ~(RCC_CR_PLLON); //PLL// RCC->CR &=~(7<<20); //PLL + + RCC->CR &= ~(0x1f << 26); + RCC->CR |= (8 - 1) << 26; //PLLֵ 2~16 + + FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_PRFTBE; //FLASH 2ʱ + + RCC->CR |= RCC_CR_PLLON; //PLLON + while(!(RCC->CR & RCC_CR_PLLRDY)); //ȴPLL + RCC->CFGR &= ~RCC_CFGR_SW; + RCC->CFGR |= RCC_CFGR_SW_PLL; //PLLΪϵͳʱ + while(temp != 0x02) //ȴPLLΪϵͳʱóɹ + { + temp = RCC->CFGR >> 2; + temp &= 0x03; + } +} +#endif + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ +/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/ diff --git a/bsp/mm32f103x/Libraries/SConscript b/bsp/mm32f103x/Libraries/SConscript new file mode 100644 index 0000000000..507afb073b --- /dev/null +++ b/bsp/mm32f103x/Libraries/SConscript @@ -0,0 +1,16 @@ +from building import * +import rtconfig +cwd = GetCurrentDir() +src = ['MM32F103/Source/system_MM32F103.c'] +CPPPATH = [cwd + '/CMSIS/KEIL_CORE', cwd + '/MM32F103/Include', cwd + '/MM32F103/Source', cwd + '/MM32F103/HAL_lib/inc'] + +src += Glob('MM32F103/HAL_lib/src/*.c') +CPPDEFINES = ['USE_STDPERIPH_DRIVER'] + +if rtconfig.CROSS_TOOL == 'keil': + src += ['MM32F103/Source/KEIL_StartAsm/startup_MM32F103.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['MM32F103/Source/IAR_StartAsm/startup_MM32F103.s'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/mm32f103x/README.md b/bsp/mm32f103x/README.md new file mode 100644 index 0000000000..a0330fb27d --- /dev/null +++ b/bsp/mm32f103x/README.md @@ -0,0 +1,112 @@ +# MM32F103xx 芯片BSP 说明 + +标签： MM32、Cortex-M3、MM32F103、国产MCU + +--- + +## 1. 简介 + +本文档使用 MM32 MiniBoard 开发板提供BSP(板级支持包) 支持。通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +MM32 MiniBoard 是为了用户快速上手、了解学习MM32系列MCU的一块入门级开发板，可满足基础测试及高端开发需求。 + +开发板外观如下图所示： + +MM32 MiniBoard + +![MM32 MiniBoard Rev.D2](figures/MM32%20MiniBoard%20Rev.D2_1.jpg) + +MM32 MiniBoard 开发板板载资源如下： + +- MCU：MM32F103RB ARM 32-bit Cortex-M3，主频 96MHz，128KB FLASH ，20KB SRAM +- 常用外设 + - LED：4个4色LED，可用于测试GPIO功能 + - 按键：1个复位按键、 1个WakeUp按键、两个普通按键 + - SPI Flash W25P80，容量8M bit，速度50MHz + - I2C接口EEPROM芯片，AT24C02，容量256字节 + - 1个旋转式电位计（变阻器），用于ADC测试 + - 能耗测试开关：待机模式和运行模式 +- 常用接口：Micro-USB接口，RS-232接口，UART接口 +- 调试接口：SWD，支持J-Link、U-LINK2、MM32-LINK调试器 + +更多信息可以访问：[灵动微电子官方网站][https://www.mindmotion.com.cn] + +### 1.2 MCU 简介 + +MM32F103RB 是上海灵动微电子股份有限公司的一款面向电机驱动、工业应用、消费电子、白色家电等领域的低功耗芯片。包括如下硬件特性： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| MM32F103RB | +|CPU| ARM Cortex-M3 | +|主频| 96MHz | +|片内SRAM| 20KB | +|片内Flash| 128KB | + +## 2. 编译说明 + +本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板到 PC 的基础上，点击下载按钮即可下载程序到开发板 + +推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到 `bsp/mm32f103` 目录中，运行以下命令： + +`scons` + +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中 rtthread.bin 可以烧写到设备中运行。 + +## 3. 烧写及执行 + +### 3.1 硬件连接 + +使用MM32-LINK或Jlink等调试工具连接开发板到PC，通过调试调试工具供电或使用Micro-USB供电。若使用Jlink等调试工具，还需要将UART1_TX(PA9)、UART1_RX(PA10)、GND接到串口工具上。 + +使用MM32-LINK连接开发板如下图所示： + +MM32-LINK+MiniBoard + +![MM32-LINK+MiniBoard Rev.D2](figures/MM32%20MiniBoard%20Rev.D2_2.jpg) + +*你也可以使用 J-Link 或者 DAP-Link 实现下载调试。 + +### 3.2 运行结果 + +如果编译 & 烧写无误，当复位设备后，会看到板子上的1个LED闪烁。串口打印RT-Thread的启动logo信息： + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Dec 11 2018 + 2006 - 2018 Copyright by rt-thread team +msh /> +``` + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ---------- | :------: | :--------------------------: | +| UART | 支持 | UART1/2 | +| GPIO | 支持 | / | + +## 5. 联系人信息 + +维护人： + +-[StackRyan](https://github.com/StackRyan) email: yuanjyjyj@outlook.com + +## 6. 参考 + +- [MM32F103xx 系列数据手册](https://www.mindmotion.com.cn/userfiles/images/MM32F103XiLieWenDang/DS_MM32F103xx_n_V1.09_SC.pdf) + +- [MM32F103xx 系列用户手册](https://www.mindmotion.com.cn/userfiles/images/MM32F103XiLieWenDang/UM_MM32F103xx_n_V1.69_SC.pdf) + +- [MiniBoardStartKit资料包](https://www.mindmotion.com.cn/download.aspx?cid=2545) + +- [keil pack安装包](https://www.mindmotion.com.cn/download.aspx?cid=2546) + +- [MM32 支持工具包](https://www.mindmotion.com.cn/download.aspx?cid=2547) + diff --git a/bsp/mm32f103x/SConscript b/bsp/mm32f103x/SConscript new file mode 100644 index 0000000000..1b1c7506a4 --- /dev/null +++ b/bsp/mm32f103x/SConscript @@ -0,0 +1,11 @@ +from building import * + +cwd = GetCurrentDir() + +objs = [] +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +Return('objs') diff --git a/bsp/mm32f103x/SConstruct b/bsp/mm32f103x/SConstruct new file mode 100644 index 0000000000..8418d596c0 --- /dev/null +++ b/bsp/mm32f103x/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/mm32f103x/applications/SConscript b/bsp/mm32f103x/applications/SConscript new file mode 100644 index 0000000000..6452d39145 --- /dev/null +++ b/bsp/mm32f103x/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/mm32f103x/drivers/Kconfig b/bsp/mm32f103x/drivers/Kconfig new file mode 100644 index 0000000000..ae70f1800e --- /dev/null +++ b/bsp/mm32f103x/drivers/Kconfig @@ -0,0 +1,23 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + menu "GPIO Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default n + endmenu + menu "UART Drivers" + config BSP_USING_UART1 + bool "Enable UART1 PA9/10(T/R)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Enable UART2 PA2/3(T/R)" + select RT_USING_SERIAL + default y + endmenu + endmenu + +endmenu diff --git a/bsp/mm32f103x/drivers/SConscript b/bsp/mm32f103x/drivers/SConscript new file mode 100644 index 0000000000..e7e064caf1 --- /dev/null +++ b/bsp/mm32f103x/drivers/SConscript @@ -0,0 +1,24 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +""") + +# add serial driver code +if GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2'): + src += ['drv_uart.c'] + +# add gpio driver code +if GetDepend(['BSP_USING_GPIO']): + src += ['drv_gpio.c'] + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/mm32f103x/drivers/board.c b/bsp/mm32f103x/drivers/board.c new file mode 100644 index 0000000000..89c3c47bac --- /dev/null +++ b/bsp/mm32f103x/drivers/board.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2017-2019, MindMotion AE Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 stackRyan first version + */ +#include +#include +#include +#include +extern uint32_t SystemCoreClock; +extern void SystemInit(void); + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +static void bsp_clock_config(void) +{ + SystemInit(); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; +} +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void rt_hw_board_init() +{ + bsp_clock_config(); +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + volatile uint16_t i=0; + rt_hw_uart_init(); + i = UINT16_MAX; + while(i--); //wait for a while after uart initiated. +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/mm32f103x/drivers/board.h b/bsp/mm32f103x/drivers/board.h new file mode 100644 index 0000000000..60c0f4ff66 --- /dev/null +++ b/bsp/mm32f103x/drivers/board.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017-2019, MindMotion AE Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-13 henryhuang first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ +#include +#include + +#define SRAM_SIZE 0x5000 + +#define SRAM_END (SRAM_BASE + SRAM_SIZE) +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section = "HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END SRAM_END +#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) +extern void rt_hw_board_init(void); +#endif diff --git a/bsp/mm32f103x/drivers/drv_gpio.c b/bsp/mm32f103x/drivers/drv_gpio.c new file mode 100644 index 0000000000..4f87ee3f59 --- /dev/null +++ b/bsp/mm32f103x/drivers/drv_gpio.c @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 stackRyan first version + */ +#include +#include +#include +#include + +#define MM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, GPIO_PortSourceGPIO##gpio, GPIO_PinSource##gpio_index} +#define MM32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0} +/* MM32 GPIO driver */ +struct pin_index +{ + int index; + uint32_t rcc; + GPIO_TypeDef *gpio; + uint32_t pin; + uint8_t port_source; + uint8_t pin_source; +}; +static const struct pin_index mm32_pin_map[] = +{ + MM32_PIN_DEFAULT, + MM32_PIN(1, APB2, A, 0), + MM32_PIN(2, APB2, A, 1), + MM32_PIN(3, APB2, A, 2), + MM32_PIN(4, APB2, A, 3), + MM32_PIN(5, APB2, A, 4), + MM32_PIN(6, APB2, A, 5), + MM32_PIN(7, APB2, A, 6), + MM32_PIN(8, APB2, A, 7), + MM32_PIN(9, APB2, A, 8), + MM32_PIN(10, APB2, A, 9), + MM32_PIN(11, APB2, A, 10), + MM32_PIN(12, APB2, A, 11), + MM32_PIN(13, APB2, A, 12), + MM32_PIN(14, APB2, A, 13), + MM32_PIN(15, APB2, A, 14), + MM32_PIN(16, APB2, A, 15), + MM32_PIN(17, APB2, B, 0), + MM32_PIN(18, APB2, B, 1), + MM32_PIN(19, APB2, B, 2), + MM32_PIN(20, APB2, B, 3), + MM32_PIN(21, APB2, B, 4), + MM32_PIN(22, APB2, B, 5), + MM32_PIN(23, APB2, B, 6), + MM32_PIN(24, APB2, B, 7), + MM32_PIN(25, APB2, B, 8), + MM32_PIN(26, APB2, B, 9), + MM32_PIN(27, APB2, B, 10), + MM32_PIN(28, APB2, B, 11), + MM32_PIN(29, APB2, B, 12), + MM32_PIN(30, APB2, B, 13), + MM32_PIN(31, APB2, B, 14), + MM32_PIN(32, APB2, B, 15), + MM32_PIN(33, APB2, C, 0), + MM32_PIN(34, APB2, C, 1), + MM32_PIN(35, APB2, C, 2), + MM32_PIN(36, APB2, C, 3), + MM32_PIN(37, APB2, C, 4), + MM32_PIN(38, APB2, C, 5), + MM32_PIN(39, APB2, C, 6), + MM32_PIN(40, APB2, C, 7), + MM32_PIN(41, APB2, C, 8), + MM32_PIN(42, APB2, C, 9), + MM32_PIN(43, APB2, C, 10), + MM32_PIN(44, APB2, C, 11), + MM32_PIN(45, APB2, C, 12), + MM32_PIN(46, APB2, C, 13), + MM32_PIN(47, APB2, C, 14), + MM32_PIN(48, APB2, C, 15), + MM32_PIN(49, APB2, D, 0), + MM32_PIN(50, APB2, D, 1), + MM32_PIN(51, APB2, D, 2), + MM32_PIN(52, APB2, D, 3), + MM32_PIN(53, APB2, D, 4), + MM32_PIN(54, APB2, D, 5), + MM32_PIN(55, APB2, D, 6), + MM32_PIN(56, APB2, D, 7), + MM32_PIN(57, APB2, D, 8), + MM32_PIN(58, APB2, D, 9), + MM32_PIN(59, APB2, D, 10), + MM32_PIN(60, APB2, D, 11), + MM32_PIN(61, APB2, D, 12), + MM32_PIN(62, APB2, D, 13), + MM32_PIN(63, APB2, D, 14), + MM32_PIN(64, APB2, D, 15), +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + rt_uint32_t irqbit; + enum IRQn irqno; +}; +const struct pin_irq_map mm32_pin_irq_map[] = +{ + {GPIO_Pin_0, EXTI_Line0, EXTI0_IRQn }, + {GPIO_Pin_1, EXTI_Line1, EXTI1_IRQn }, + {GPIO_Pin_2, EXTI_Line2, EXTI2_IRQn }, + {GPIO_Pin_3, EXTI_Line3, EXTI3_IRQn }, + {GPIO_Pin_4, EXTI_Line4, EXTI4_IRQn }, + {GPIO_Pin_5, EXTI_Line5, EXTI9_5_IRQn }, + {GPIO_Pin_6, EXTI_Line6, EXTI9_5_IRQn }, + {GPIO_Pin_7, EXTI_Line7, EXTI9_5_IRQn }, + {GPIO_Pin_8, EXTI_Line8, EXTI9_5_IRQn }, + {GPIO_Pin_9, EXTI_Line9, EXTI9_5_IRQn }, + {GPIO_Pin_10, EXTI_Line10, EXTI15_10_IRQn}, + {GPIO_Pin_11, EXTI_Line11, EXTI15_10_IRQn}, + {GPIO_Pin_12, EXTI_Line12, EXTI15_10_IRQn}, + {GPIO_Pin_13, EXTI_Line13, EXTI15_10_IRQn}, + {GPIO_Pin_14, EXTI_Line14, EXTI15_10_IRQn}, + {GPIO_Pin_15, EXTI_Line15, EXTI15_10_IRQn}, +}; +struct rt_pin_irq_hdr mm32_pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(mm32_pin_map)) + { + index = &mm32_pin_map[pin]; + if (index->gpio == 0) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + if (value == PIN_LOW) + { + GPIO_ResetBits(index->gpio, index->pin); + } + else + { + GPIO_SetBits(index->gpio, index->pin); + } +} + +int mm32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + index = get_pin(pin); + if (index == RT_NULL) + { + return PIN_LOW; + } + if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + return value; +} + +void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitTypeDef GPIO_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + /* GPIO Periph clock enable */ + RCC_APB2PeriphClockCmd(index->rcc, ENABLE); + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + } + else + { + /* input setting:default. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + } + GPIO_Init( index->gpio, &GPIO_InitStructure); +} +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(mm32_pin_irq_map)) + { + return RT_NULL; + } + return &mm32_pin_irq_map[mapindex]; +}; +rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (mm32_pin_irq_hdr_tab[irqindex].pin == pin && + mm32_pin_irq_hdr_tab[irqindex].hdr == hdr && + mm32_pin_irq_hdr_tab[irqindex].mode == mode && + mm32_pin_irq_hdr_tab[irqindex].args == args + ) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (mm32_pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + mm32_pin_irq_hdr_tab[irqindex].pin = pin; + mm32_pin_irq_hdr_tab[irqindex].hdr = hdr; + mm32_pin_irq_hdr_tab[irqindex].mode = mode; + mm32_pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (mm32_pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + mm32_pin_irq_hdr_tab[irqindex].pin = -1; + mm32_pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + mm32_pin_irq_hdr_tab[irqindex].mode = 0; + mm32_pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) + { + return -RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (mm32_pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + irqmap = &mm32_pin_irq_map[irqindex]; + /* GPIO Periph clock enable */ + RCC_APB2PeriphClockCmd(index->rcc, ENABLE); + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(index->gpio, &GPIO_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + GPIO_EXTILineConfig(index->port_source, index->pin_source); + EXTI_InitStructure.EXTI_Line = irqmap->irqbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + switch (mm32_pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + } + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return -RT_ENOSYS; + } + EXTI_InitStructure.EXTI_Line = irqmap->irqbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = DISABLE; + EXTI_Init(&EXTI_InitStructure); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _mm32_pin_ops = +{ + mm32_pin_mode, + mm32_pin_write, + mm32_pin_read, + mm32_pin_attach_irq, + mm32_pin_detach_irq, + mm32_pin_irq_enable, + RT_NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_mm32_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + EXTI_ClearITPendingBit(mm32_pin_irq_map[irqno].irqbit); + if (mm32_pin_irq_hdr_tab[irqno].hdr) + { + mm32_pin_irq_hdr_tab[irqno].hdr(mm32_pin_irq_hdr_tab[irqno].args); + } +} +void EXTI0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(0); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(1); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(2); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(3); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(4); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI9_5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if (EXTI_GetITStatus(EXTI_Line5) != RESET) + { + pin_irq_hdr(5); + } + if (EXTI_GetITStatus(EXTI_Line6) != RESET) + { + pin_irq_hdr(6); + } + if (EXTI_GetITStatus(EXTI_Line7) != RESET) + { + pin_irq_hdr(7); + } + if (EXTI_GetITStatus(EXTI_Line8) != RESET) + { + pin_irq_hdr(8); + } + if (EXTI_GetITStatus(EXTI_Line9) != RESET) + { + pin_irq_hdr(9); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI15_10_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if (EXTI_GetITStatus(EXTI_Line10) != RESET) + { + pin_irq_hdr(10); + } + if (EXTI_GetITStatus(EXTI_Line11) != RESET) + { + pin_irq_hdr(11); + } + if (EXTI_GetITStatus(EXTI_Line12) != RESET) + { + pin_irq_hdr(12); + } + if (EXTI_GetITStatus(EXTI_Line13) != RESET) + { + pin_irq_hdr(13); + } + if (EXTI_GetITStatus(EXTI_Line14) != RESET) + { + pin_irq_hdr(14); + } + if (EXTI_GetITStatus(EXTI_Line15) != RESET) + { + pin_irq_hdr(15); + } + /* leave interrupt */ + rt_interrupt_leave(); +} diff --git a/bsp/mm32f103x/drivers/drv_gpio.h b/bsp/mm32f103x/drivers/drv_gpio.h new file mode 100644 index 0000000000..09de5d6e9b --- /dev/null +++ b/bsp/mm32f103x/drivers/drv_gpio.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-02 henryhuang the first version + */ +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/mm32f103x/drivers/drv_uart.c b/bsp/mm32f103x/drivers/drv_uart.c new file mode 100644 index 0000000000..22a80a1b33 --- /dev/null +++ b/bsp/mm32f103x/drivers/drv_uart.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-04 stackRyan first version + */ +#include +#include +#include "drv_uart.h" + +/* UART1 */ +#define UART1_GPIO_TX GPIO_Pin_9 +#define UART1_GPIO_TX_SOURCE GPIO_PinSource9 +#define UART1_GPIO_RX GPIO_Pin_10 +#define UART1_GPIO_RX_SOURCE GPIO_PinSource10 +#define UART1_GPIO_AF GPIO_AF_1 +#define UART1_GPIO GPIOA + +/* UART2 */ +#define UART2_GPIO_TX GPIO_Pin_2 +#define UART2_GPIO_TX_SOURCE GPIO_PinSource2 +#define UART2_GPIO_RX GPIO_Pin_3 +#define UART2_GPIO_RX_SOURCE GPIO_PinSource3 +#define UART2_GPIO_AF GPIO_AF_1 +#define UART2_GPIO GPIOA + +/* uart driver */ +struct mm32_uart +{ + UART_TypeDef *uart; + IRQn_Type irq; +}; + +static rt_err_t mm32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct mm32_uart *uart; + UART_InitTypeDef UART_InitStructure; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct mm32_uart *)serial->parent.user_data; + UART_InitStructure.UART_BaudRate = cfg->baud_rate; + if (cfg->data_bits == DATA_BITS_8) + UART_InitStructure.UART_WordLength = UART_WordLength_8b; + if (cfg->stop_bits == STOP_BITS_1) + UART_InitStructure.UART_StopBits = UART_StopBits_1; + else if (cfg->stop_bits == STOP_BITS_2) + UART_InitStructure.UART_StopBits = UART_StopBits_2; + UART_InitStructure.UART_Parity = UART_Parity_No; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(uart->uart, &UART_InitStructure); + /* Enable UART */ + UART_Cmd(uart->uart, ENABLE); + return RT_EOK; +} + +static rt_err_t mm32_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct mm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct mm32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE); + break; + } + return RT_EOK; +} + +static int mm32_uart_putc(struct rt_serial_device *serial, char c) +{ + struct mm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct mm32_uart *)serial->parent.user_data; + while ((uart->uart->CSR & UART_IT_TXIEN) == 0); + uart->uart->TDR = (c & (uint16_t)0x00FF); + return 1; +} + +static int mm32_uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct mm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct mm32_uart *)serial->parent.user_data; + ch = -1; + if (uart->uart->CSR & UART_FLAG_RXAVL) + { + ch = uart->uart->RDR & 0xff; + } + return ch; +} + +static const struct rt_uart_ops mm32_uart_ops = +{ + mm32_uart_configure, + mm32_uart_control, + mm32_uart_putc, + mm32_uart_getc, +}; + +#if defined(BSP_USING_UART1) +/* UART1 device driver structure */ +static struct mm32_uart uart1; +struct rt_serial_device serial1; +void UART1_IRQHandler(void) +{ + struct mm32_uart *uart; + uart = &uart1; + /* enter interrupt */ + rt_interrupt_enter(); + if (UART_GetITStatus(uart->uart, UART_IT_RXIEN) != RESET) + { + UART_ClearITPendingBit(uart->uart, UART_IT_RXIEN); + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + if (UART_GetITStatus(uart->uart, UART_IT_TXIEN) != RESET) + { + /* clear interrupt */ + UART_ClearITPendingBit(uart->uart, UART_IT_TXIEN); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +/* UART2 device driver structure */ +static struct mm32_uart uart2; +struct rt_serial_device serial2; +void UART2_IRQHandler(void) +{ + struct mm32_uart *uart; + uart = &uart2; + /* enter interrupt */ + rt_interrupt_enter(); + if (UART_GetITStatus(uart->uart, UART_IT_RXIEN) != RESET) + { + UART_ClearITPendingBit(uart->uart, UART_IT_RXIEN); + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + } + if (UART_GetITStatus(uart->uart, UART_IT_TXIEN) != RESET) + { + /* clear interrupt */ + UART_ClearITPendingBit(uart->uart, UART_IT_TXIEN); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART1 +static void UART1PINconfigStepA(void) +{ + /* Enable UART clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1 | RCC_APB2Periph_GPIOA, ENABLE); +} + +static void UART1PINconfigStepB(void) +{ + + GPIO_InitTypeDef GPIO_InitStructure; + /* Configure USART Rx/tx PIN */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +} +#endif + +#ifdef BSP_USING_UART2 +static void UART2PINconfigStepA(void) +{ + /* Enable UART clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); +} + +static void UART2PINconfigStepB(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + /* Configure USART Rx/tx PIN */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +} +#endif + +int rt_hw_uart_init(void) +{ + struct mm32_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef BSP_USING_UART1 + UART1PINconfigStepA(); + uart = &uart1; + uart->uart = UART1; + uart->irq = UART1_IRQn; + config.baud_rate = BAUD_RATE_115200; + serial1.ops = &mm32_uart_ops; + serial1.config = config; + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + UART1PINconfigStepB(); +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 + UART2PINconfigStepA(); + uart = &uart2; + uart->uart = UART2; + uart->irq = UART2_IRQn; + config.baud_rate = BAUD_RATE_115200; + serial2.ops = &mm32_uart_ops; + serial2.config = config; + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + UART2PINconfigStepB(); +#endif /* BSP_USING_UART2 */ + return 0; +} +//INIT_BOARD_EXPORT(rt_hw_uart_init); +//attention: uart init hardware problems occure on mm32f103 +//recommand manually initialize uart in rt_hw_board_init() +//see in rt_hw_board_init() learn more on rt_hw_uart_init() detials. diff --git a/bsp/mm32f103x/drivers/drv_uart.h b/bsp/mm32f103x/drivers/drv_uart.h new file mode 100644 index 0000000000..5f0d14b485 --- /dev/null +++ b/bsp/mm32f103x/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2017-2019, MindMotion AE Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-13 henryhuang first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/mm32f103x/drivers/linker_scripts/link.icf b/bsp/mm32f103x/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000..a2e05e53a6 --- /dev/null +++ b/bsp/mm32f103x/drivers/linker_scripts/link.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_IROM_end__ = 0x0001FFFF; +define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM_end__ = 0x20004FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0800; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x0800; +/**** End of ICF editor section. ###ICF###*/ +define memory mem with size = 4G; +define region IROM_region = mem:[from __ICFEDIT_region_IROM_start__ to __ICFEDIT_region_IROM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; +initialize by copy { readwrite }; +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in IROM_region { readonly }; +place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; diff --git a/bsp/mm32f103x/drivers/linker_scripts/link.lds b/bsp/mm32f103x/drivers/linker_scripts/link.lds new file mode 100644 index 0000000000..aad42bdb39 --- /dev/null +++ b/bsp/mm32f103x/drivers/linker_scripts/link.lds @@ -0,0 +1,137 @@ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 20k /* 8K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/mm32f103x/drivers/linker_scripts/link.sct b/bsp/mm32f103x/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000..f67cd68761 --- /dev/null +++ b/bsp/mm32f103x/drivers/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00005000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/mm32f103x/figures/MM32 MiniBoard Rev.D2_1.jpg b/bsp/mm32f103x/figures/MM32 MiniBoard Rev.D2_1.jpg new file mode 100644 index 0000000000..8251e21964 Binary files /dev/null and b/bsp/mm32f103x/figures/MM32 MiniBoard Rev.D2_1.jpg differ diff --git a/bsp/mm32f103x/figures/MM32 MiniBoard Rev.D2_2.jpg b/bsp/mm32f103x/figures/MM32 MiniBoard Rev.D2_2.jpg new file mode 100644 index 0000000000..0bce34d8bd Binary files /dev/null and b/bsp/mm32f103x/figures/MM32 MiniBoard Rev.D2_2.jpg differ diff --git a/bsp/stm32/stm32f072-st-nucleo/project.ewd b/bsp/mm32f103x/project.ewd similarity index 98% rename from bsp/stm32/stm32f072-st-nucleo/project.ewd rename to bsp/mm32f103x/project.ewd index ff5dc49169..0046d0832c 100644 --- a/bsp/stm32/stm32f072-st-nucleo/project.ewd +++ b/bsp/mm32f103x/project.ewd @@ -11,7 +11,7 @@ C-SPY 2 - 30 + 31 1 1 - - + + @@ -292,7 +292,7 @@ @@ -2913,6 +2913,10 @@ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin 0 + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin 0 @@ -2945,10 +2949,6 @@ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin 0 - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 diff --git a/bsp/stm32/stm32f072-st-nucleo/project.ewp b/bsp/mm32f103x/project.ewp similarity index 84% rename from bsp/stm32/stm32f072-st-nucleo/project.ewp rename to bsp/mm32f103x/project.ewp index 97aaf49588..3ef301928c 100644 --- a/bsp/stm32/stm32f072-st-nucleo/project.ewp +++ b/bsp/mm32f103x/project.ewp @@ -65,7 +65,7 @@ @@ -1276,9 +1292,8 @@ @@ -2113,223 +2145,190 @@ CPU - $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m0\cpuport.c + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m0\context_iar.S + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + $PROJ_DIR$\..\..\components\drivers\misc\pin.c - $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + $PROJ_DIR$\..\..\components\drivers\serial\serial.c - $PROJ_DIR$\..\..\..\components\drivers\src\completion.c + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c + $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c + $PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c + $PROJ_DIR$\..\..\components\drivers\src\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + $PROJ_DIR$\..\..\components\drivers\src\completion.c Drivers - $PROJ_DIR$\board\board.c + $PROJ_DIR$\drivers\drv_gpio.c - $PROJ_DIR$\board\CubeMX_Config\Src\stm32f0xx_hal_msp.c + $PROJ_DIR$\drivers\drv_uart.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\CMSIS\Device\ST\STM32F0xx\Source\Templates\iar\startup_stm32f072xb.s - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + $PROJ_DIR$\drivers\board.c - finsh + Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_error.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_heap.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_init.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_node.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_ops.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_parser.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_var.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_vm.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_token.c + $PROJ_DIR$\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\device.c + $PROJ_DIR$\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\src\timer.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\src\device.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\src\scheduler.c - $PROJ_DIR$\..\..\..\src\scheduler.c + $PROJ_DIR$\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\signal.c + $PROJ_DIR$\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\src\object.c + + + + libc + + $PROJ_DIR$\..\..\components\libc\compilers\common\time.c Libraries - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\CMSIS\Device\ST\STM32F0xx\Source\Templates\system_stm32f0xx.c + $PROJ_DIR$\Libraries\MM32F103\Source\system_MM32F103.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_dma.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_flash.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_cortex.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_spi.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_crc.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_wwdg.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_crc_ex.c + $PROJ_DIR$\Libraries\MM32F103\Source\IAR_StartAsm\startup_MM32F103.s - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_pwr.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_gpio.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_rcc.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_adc.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_rcc_ex.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_tim.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_exti.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_ll_crc.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_rcc.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_ll_dma.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_rtc.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_ll_exti.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_pwr.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_ll_gpio.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_misc.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_ll_pwr.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_iwdg.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_ll_rcc.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_bkp.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_ll_utils.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_can.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_gpio.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_dma.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_uart.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_uart.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_uart_ex.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_i2c.c - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_hal_usart.c - - - $PROJ_DIR$\..\libraries\STM32F0xx_HAL\STM32F0xx_HAL_Driver\Src\stm32f0xx_ll_usart.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_crc.c + + utestcases + diff --git a/bsp/mm32f103x/project.eww b/bsp/mm32f103x/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/mm32f103x/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/mm32f103x/rtconfig.h b/bsp/mm32f103x/rtconfig.h new file mode 100644 index 0000000000..485b4815d3 --- /dev/null +++ b/bsp/mm32f103x/rtconfig.h @@ -0,0 +1,186 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 1024 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 1024 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +/* GPIO Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART1 +#define SOC_MM32L373 + +#endif diff --git a/bsp/mm32f103x/rtconfig.py b/bsp/mm32f103x/rtconfig.py new file mode 100644 index 0000000000..1e87cf72e0 --- /dev/null +++ b/bsp/mm32f103x/rtconfig.py @@ -0,0 +1,135 @@ +# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D) + +import os +import sys +# toolchains options +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +# device options +ARCH = 'arm' +CPU = 'cortex-m3' + + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/Users/zhangyihong/.env/gcc-arm-none-eabi-5_4-2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wall' + CFLAGS = DEVICE + ' -std=c99' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/LIB' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/arm/armcc/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' # + ' -D' + PART_TYPE + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + #LFLAGS += ' --silent' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/mm32f103x/template.ewp b/bsp/mm32f103x/template.ewp new file mode 100644 index 0000000000..a2d6a9d1d5 --- /dev/null +++ b/bsp/mm32f103x/template.ewp @@ -0,0 +1,2106 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/mm32f103x/template.eww b/bsp/mm32f103x/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/mm32f103x/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/mm32f103x/template.uvopt b/bsp/mm32f103x/template.uvopt new file mode 100644 index 0000000000..0a9bea69e4 --- /dev/null +++ b/bsp/mm32f103x/template.uvopt @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + + 0 + Datasheet + DATASHTS\ST\STM32F4xx\DM00053488.pdf + + + 1 + Reference Manual + DATASHTS\ST\STM32F4xx\DM00031020.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/mm32f103x/template.uvoptx b/bsp/mm32f103x/template.uvoptx new file mode 100644 index 0000000000..f9da8a8ebf --- /dev/null +++ b/bsp/mm32f103x/template.uvoptx @@ -0,0 +1,182 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U69614099 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0MM32F103_128.FLM -FS08000000 -FL020000 -FP0($$Device:MM32F103RBT$Flash\MM32F103_128.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MM32F103_128 -FS08000000 -FL020000 -FP0($$Device:MM32F103RBT$Flash\MM32F103_128.FLM)) + + + 0 + MM32LINKCM3 + -U6175B4CC7 -O206 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0MM32L3xx_128.FLM -FS08000000 -FL020000 -FP0($$Device:MM32L373PF$Flash\MM32L3xx_128.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/mm32f103x/template.uvprojx b/bsp/mm32f103x/template.uvprojx new file mode 100644 index 0000000000..12e9ccd961 --- /dev/null +++ b/bsp/mm32f103x/template.uvprojx @@ -0,0 +1,406 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + MM32F103RBT + MindMotion + MindMotion.MM32F103x8xB_DFP.1.4.7 + http://www.mindmotion.com.cn/Download/MDK_KEIL/ + IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MM32F103_128 -FS08000000 -FL020000 -FP0($$Device:MM32F103RBT$Flash\MM32F103_128.FLM)) + 0 + $$Device:MM32F103RBT$Device\MM32F103\Include\HAL_device.h + + + + + + + + + + $$Device:MM32F103RBT$SVD\MM32F103.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_STDPERIPH_DRIVER + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/n32g452xx/.ignore_format.yml b/bsp/n32g452xx/.ignore_format.yml new file mode 100644 index 0000000000..8b73f834c0 --- /dev/null +++ b/bsp/n32g452xx/.ignore_format.yml @@ -0,0 +1,7 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- Libraries/N32_Std_Driver + diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_common_tables.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_common_tables.h new file mode 100644 index 0000000000..dfea7460e9 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_const_structs.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_const_structs.h new file mode 100644 index 0000000000..80a3e8bbe7 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_math.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_math.h new file mode 100644 index 0000000000..d6b5b2b1ce --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_armcc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_armcc.h new file mode 100644 index 0000000000..a4c67e0268 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_armclang.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_armclang.h new file mode 100644 index 0000000000..a1722f87a8 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_compiler.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_compiler.h new file mode 100644 index 0000000000..94212eb87a --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_gcc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_gcc.h new file mode 100644 index 0000000000..cd374afaef --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_iccarm.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_iccarm.h new file mode 100644 index 0000000000..b82874d0e4 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict//__restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_version.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_version.h new file mode 100644 index 0000000000..660f612aa3 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/core_cm4.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/core_cm4.h new file mode 100644 index 0000000000..7d56873532 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/mpu_armv7.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/mpu_armv7.h new file mode 100644 index 0000000000..be73de161f --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/n32g45x.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/n32g45x.h new file mode 100644 index 0000000000..6a3d59d12d --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/n32g45x.h @@ -0,0 +1,9961 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_H__ +#define __N32G45X_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup N32G45x_Library_Basic + * @{ + */ + +#if !defined USE_STDPERIPH_DRIVER +/* + * Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_STDPERIPH_DRIVER +#endif + +/* + * In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE +#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/* + * In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x8000) /*!< Time out for HSE start up */ + +#define HSI_VALUE (8000000) /*!< Value of the Internal oscillator in Hz*/ + +#define __N32G45X_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */ +#define __N32G45X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __N32G45X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __N32G45X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ + +/** + * @brief N32G45X Standard Peripheral Library version number + */ +#define __N32G45X_STDPERIPH_VERSION \ + ((__N32G45X_STDPERIPH_VERSION_MAIN << 24) | (__N32G45X_STDPERIPH_VERSION_SUB1 << 16) \ + | (__N32G45X_STDPERIPH_VERSION_SUB2 << 8) | (__N32G45X_STDPERIPH_VERSION_RC)) + +/* + * Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#ifdef N32G45X +#define __MPU_PRESENT 1 /*!< N32G45X devices does not provide an MPU */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#endif /* N32G45X */ +#define __NVIC_PRIO_BITS 4 /*!< N32G45X uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief N32G45X Interrupt Number Definition + */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** N32G45X specific Interrupt Numbers ********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_4_IRQn = 47, /*!< ADC3 and ADC4 global Interrupt */ + XFMC_IRQn = 48, /*!< XFMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI Line interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + QSPI_IRQn = 67, /*!< QSPI global Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global Interrupt */ + I2C3_EV_IRQn = 70, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 71, /*!< I2C3 Error Interrupt */ + I2C4_EV_IRQn = 72, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 73, /*!< I2C4 Error Interrupt */ + UART6_IRQn = 74, /*!< UART6 global Interrupt */ + UART7_IRQn = 75, /*!< UART7 global Interrupt */ + DMA1_Channel8_IRQn = 76, /*!< DMA1 Channel 8 global Interrupt */ + DMA2_Channel8_IRQn = 77, /*!< DMA2 Channel 8 global Interrupt */ + DVP_IRQn = 78, /*!< DVP global Interrupt */ + SAC_IRQn = 79, /*!< SAC global Interrupt */ + MMU_IRQn = 80, /*!< MMU global Interrupt */ + TSC_IRQn = 81, /*!< TSC global Interrupt */ + COMP_1_2_3_IRQn = 82, /*!< COMP1 & COMP2 & COMP3 global Interrupt */ + COMP_4_5_6_IRQn = 83, /*!< COMP4 & COMP5 & COMP6 global Interrupt */ + COMP7_IRQn = 84 /*!< COMP7 global Interrupt */ + +} IRQn_Type; + +#include "core_cm4.h" +#include "system_n32g45x.h" +#include +#include + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, + INTStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/* N32G45X Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t STS; + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t SAMPT1; + __IO uint32_t SAMPT2; + __IO uint32_t JOFFSET1; + __IO uint32_t JOFFSET2; + __IO uint32_t JOFFSET3; + __IO uint32_t JOFFSET4; + __IO uint32_t WDGHIGH; + __IO uint32_t WDGLOW; + __IO uint32_t RSEQ1; + __IO uint32_t RSEQ2; + __IO uint32_t RSEQ3; + __IO uint32_t JSEQ; + __IO uint32_t JDAT1; + __IO uint32_t JDAT2; + __IO uint32_t JDAT3; + __IO uint32_t JDAT4; + __IO uint32_t DAT; + __IO uint32_t DIFSEL; + __IO uint32_t CALFACT; + __IO uint32_t CTRL3; + __IO uint32_t SAMPT3; +} ADC_Module; + +/** + * @brief OPAMP + */ +typedef struct +{ + __IO uint32_t CS1; + __IO uint32_t RES1[3]; + __IO uint32_t CS2; + __IO uint32_t RES2[3]; + __IO uint32_t CS3; + __IO uint32_t RES3[3]; + __IO uint32_t CS4; + __IO uint32_t RES4[3]; + __IO uint32_t LOCK; +} OPAMP_Module; + +/** + * @brief COMP_Single + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t FILC; + __IO uint32_t FILP; + __IO uint32_t RES; +} COMP_SingleType; + +/** + * @brief COMP + */ +typedef struct +{ + __IO uint32_t RES4[4]; + COMP_SingleType Cmp[7]; + __IO uint32_t WINMODE; + __IO uint32_t LOCK; + __IO uint32_t RES; + __IO uint32_t INTEN; + __IO uint32_t INTSTS; + __IO uint32_t VREFSCL; +} COMP_Module; + +/** + * @brief AFEC + */ + +typedef struct +{ + __IO uint32_t TRIMR0; + __IO uint32_t TRIMR1; + __IO uint32_t TRIMR2; + __IO uint32_t TRIMR3; + __IO uint32_t TRIMR4; + __IO uint32_t TRIMR5; + __IO uint32_t TRIMR6; + uint32_t RESERVED0; + __IO uint32_t TESTR0; + __IO uint32_t TESTR1; +} AFEC_Module; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DAT1; + uint16_t RESERVED1; + __IO uint16_t DAT2; + uint16_t RESERVED2; + __IO uint16_t DAT3; + uint16_t RESERVED3; + __IO uint16_t DAT4; + uint16_t RESERVED4; + __IO uint16_t DAT5; + uint16_t RESERVED5; + __IO uint16_t DAT6; + uint16_t RESERVED6; + __IO uint16_t DAT7; + uint16_t RESERVED7; + __IO uint16_t DAT8; + uint16_t RESERVED8; + __IO uint16_t DAT9; + uint16_t RESERVED9; + __IO uint16_t DAT10; + uint16_t RESERVED10; + __IO uint16_t RESERVED; + uint16_t RESERVED11; + __IO uint16_t CTRL; + uint16_t RESERVED12; + __IO uint16_t CTRLSTS; + uint16_t RESERVED13[5]; + __IO uint16_t DAT11; + uint16_t RESERVED14; + __IO uint16_t DAT12; + uint16_t RESERVED15; + __IO uint16_t DAT13; + uint16_t RESERVED16; + __IO uint16_t DAT14; + uint16_t RESERVED17; + __IO uint16_t DAT15; + uint16_t RESERVED18; + __IO uint16_t DAT16; + uint16_t RESERVED19; + __IO uint16_t DAT17; + uint16_t RESERVED20; + __IO uint16_t DAT18; + uint16_t RESERVED21; + __IO uint16_t DAT19; + uint16_t RESERVED22; + __IO uint16_t DAT20; + uint16_t RESERVED23; + __IO uint16_t DAT21; + uint16_t RESERVED24; + __IO uint16_t DAT22; + uint16_t RESERVED25; + __IO uint16_t DAT23; + uint16_t RESERVED26; + __IO uint16_t DAT24; + uint16_t RESERVED27; + __IO uint16_t DAT25; + uint16_t RESERVED28; + __IO uint16_t DAT26; + uint16_t RESERVED29; + __IO uint16_t DAT27; + uint16_t RESERVED30; + __IO uint16_t DAT28; + uint16_t RESERVED31; + __IO uint16_t DAT29; + uint16_t RESERVED32; + __IO uint16_t DAT30; + uint16_t RESERVED33; + __IO uint16_t DAT31; + uint16_t RESERVED34; + __IO uint16_t DAT32; + uint16_t RESERVED35; + __IO uint16_t DAT33; + uint16_t RESERVED36; + __IO uint16_t DAT34; + uint16_t RESERVED37; + __IO uint16_t DAT35; + uint16_t RESERVED38; + __IO uint16_t DAT36; + uint16_t RESERVED39; + __IO uint16_t DAT37; + uint16_t RESERVED40; + __IO uint16_t DAT38; + uint16_t RESERVED41; + __IO uint16_t DAT39; + uint16_t RESERVED42; + __IO uint16_t DAT40; + uint16_t RESERVED43; + __IO uint16_t DAT41; + uint16_t RESERVED44; + __IO uint16_t DAT42; + uint16_t RESERVED45; +} BKP_Module; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMDT; + __IO uint32_t TMDL; + __IO uint32_t TMDH; +} CAN_TxMailBox_Param; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RMI; + __IO uint32_t RMDT; + __IO uint32_t RMDL; + __IO uint32_t RMDH; +} CAN_FIFOMailBox_Param; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_Param; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; + __IO uint32_t MSTS; + __IO uint32_t TSTS; + __IO uint32_t RFF0; + __IO uint32_t RFF1; + __IO uint32_t INTE; + __IO uint32_t ESTS; + __IO uint32_t BTIM; + uint32_t RESERVED0[88]; + CAN_TxMailBox_Param sTxMailBox[3]; + CAN_FIFOMailBox_Param sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMC; + __IO uint32_t FM1; + uint32_t RESERVED2; + __IO uint32_t FS1; + uint32_t RESERVED3; + __IO uint32_t FFA1; + uint32_t RESERVED4; + __IO uint32_t FA1; + uint32_t RESERVED5[8]; + CAN_FilterRegister_Param sFilterRegister[14]; +} CAN_Module; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t CRC32DAT; /*!< CRC data register */ + __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/ + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CRC32CTRL; /*!< CRC control register */ + __IO uint32_t CRC16CTRL; + __IO uint8_t CRC16DAT; + uint8_t RESERVED2; + uint16_t RESERVED3; + __IO uint16_t CRC16D; + uint16_t RESERVED4; + __IO uint8_t LRC; + uint8_t RESERVED5; + uint16_t RESERVED6; +} CRC_Module; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t SOTTR; + __IO uint32_t DR12CH1; + __IO uint32_t DL12CH1; + __IO uint32_t DR8CH1; + __IO uint32_t DR12CH2; + __IO uint32_t DL12CH2; + __IO uint32_t DR8CH2; + __IO uint32_t DR12DCH; + __IO uint32_t DL12DCH; + __IO uint32_t DR8DCH; + __IO uint32_t DATO1; + __IO uint32_t DATO2; +} DAC_Module; +/** + * @brief USB + */ + +typedef struct +{ + __IO uint32_t EP0; + __IO uint32_t EP1; + __IO uint32_t EP2; + __IO uint32_t EP3; + __IO uint32_t EP4; + __IO uint32_t EP5; + __IO uint32_t EP6; + __IO uint32_t EP7; + __IO uint32_t Reserve20h; + __IO uint32_t Reserve24h; + __IO uint32_t Reserve28h; + __IO uint32_t Reserve2Ch; + __IO uint32_t Reserve30h; + __IO uint32_t Reserve34h; + __IO uint32_t Reserve38h; + __IO uint32_t Reserve3Ch; + __IO uint32_t CTRL; + __IO uint32_t STS; + __IO uint32_t FN; + __IO uint32_t ADDR; + __IO uint32_t BUFTAB; +} USB_Module; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t ID; + __IO uint32_t CTRL; +} DBG_Module; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CHCFG; + __IO uint32_t TXNUM; + __IO uint32_t PADDR; + __IO uint32_t MADDR; + __IO uint32_t CHSEL; + +} DMA_ChannelType; + +typedef struct +{ + __IO uint32_t INTSTS; + __IO uint32_t INTCLR; + __IO DMA_ChannelType DMA_Channel[8]; + __IO uint32_t CHMAPEN; +} DMA_Module; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCFG; + __IO uint32_t MACFFLT; + __IO uint32_t MACHASHHI; + __IO uint32_t MACHASHLO; + __IO uint32_t MACMIIADDR; + __IO uint32_t MACMIIDAT; + __IO uint32_t MACFLWCTRL; + __IO uint32_t MACVLANTAG; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRMTWUFRMFLT; /* 11 */ + __IO uint32_t MACPMTCTRLSTS; + uint32_t RESERVED1[2]; + __IO uint32_t MACINTSTS; /* 15 */ + __IO uint32_t MACINTMSK; + __IO uint32_t MACADDR0HI; + __IO uint32_t MACADDR0LO; + __IO uint32_t MACADDR1HI; + __IO uint32_t MACADDR1LO; + __IO uint32_t MACADDR2HI; + __IO uint32_t MACADDR2LO; + __IO uint32_t MACADDR3HI; + __IO uint32_t MACADDR3LO; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCTRL; /* 65 */ + __IO uint32_t MMCRXINT; + __IO uint32_t MMCTXINT; + __IO uint32_t MMCRXINTMSK; + __IO uint32_t MMCTXINTMSK; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTXGFASCCNT; /* 84 */ + __IO uint32_t MMCTXGFAMSCCNT; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTXGFCNT; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRXFCECNT; + __IO uint32_t MMCRXFAECNT; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRXGUFCNT; + uint32_t RESERVED7[14]; + __IO uint32_t MMCRXCOINTMSK; + uint32_t RESERVED8[319]; + __IO uint32_t PTPTSCTRL; + __IO uint32_t PTPSSINC; + __IO uint32_t PTPSEC; + __IO uint32_t PTPNS; + __IO uint32_t PTPSECUP; + __IO uint32_t PTPNSUP; + __IO uint32_t PTPTSADD; + __IO uint32_t PTPTTSEC; + __IO uint32_t PTPTTNS; + uint32_t RESERVED9[567]; + __IO uint32_t DMABUSMOD; + __IO uint32_t DMATXPD; + __IO uint32_t DMARXPD; + __IO uint32_t DMARXDLADDR; + __IO uint32_t DMATXDLADDR; + __IO uint32_t DMASTS; + __IO uint32_t DMAOPMOD; + __IO uint32_t DMAINTEN; + __IO uint32_t DMAMFBOCNT; + uint32_t RESERVED10[9]; + __IO uint32_t DMACHTXDESC; + __IO uint32_t DMACHRXDESC; + __IO uint32_t DMACHTXBADDR; + __IO uint32_t DMACHRXBADDR; +} ETH_Module; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMASK; + __IO uint32_t EMASK; + __IO uint32_t RT_CFG; + __IO uint32_t FT_CFG; + __IO uint32_t SWIE; + __IO uint32_t PEND; + __IO uint32_t TSSEL; +} EXTI_Module; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t AC; + __IO uint32_t KEY; + __IO uint32_t OPTKEY; + __IO uint32_t STS; + __IO uint32_t CTRL; + __IO uint32_t ADD; + __IO uint32_t RESERVED0; + __IO uint32_t OBR; + __IO uint32_t WRP; + __IO uint32_t RESERVED1; + __IO uint32_t RESERVED2; + __IO uint32_t RDN; + __IO uint32_t CAHR; +} FLASH_Module; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t USER_RDP; + __IO uint32_t Data1_Data0; + __IO uint32_t WRP1_WRP0; + __IO uint32_t WRP3_WRP2; + __IO uint32_t RDP2; +} OB_Module; + +/** + * @brief Extended Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BANK1_CR1; /*offset = 0x00*/ + __IO uint32_t BANK1_TR1; /*offset = 0x04*/ + __IO uint32_t BANK1_CR2; /*offset = 0x08*/ + __IO uint32_t BANK1_TR2; /*offset = 0x0C*/ + + uint32_t RESERVED0[20]; /*offset = 0x10*/ + + __IO uint32_t CTRL2; /*offset = 0x60*/ + __IO uint32_t STS2; /*offset = 0x64*/ + __IO uint32_t CMEMTM2; /*offset = 0x68*/ + __IO uint32_t ATTMEMTM2; /*offset = 0x6C*/ + uint32_t RESERVED1; /*offset = 0x70*/ + __IO uint32_t ECC2; /*offset = 0x74*/ + + uint32_t RESERVED2[2]; /*offset = 0x78*/ + + __IO uint32_t CTRL3; /*offset = 0x80*/ + __IO uint32_t STS3; /*offset = 0x84*/ + __IO uint32_t CMEMTM3; /*offset = 0x88*/ + __IO uint32_t ATTMEMTM3; /*offset = 0x8C*/ + uint32_t RESERVED3; /*offset = 0x90*/ + __IO uint32_t ECC3; /*offset = 0x94*/ + + uint32_t RESERVED4[27]; /*offset = 0x98*/ + + __IO uint32_t BANK1_WTR1; /*offset = 0x104*/ + uint32_t RESERVED5; /*offset = 0x108*/ + __IO uint32_t BANK1_WTR2; /*offset = 0x10C*/ + +} XFMC_Module; + + +/** + * @brief Extended Flexible Memory Controller BANK1 + */ +typedef struct +{ + __IO uint32_t CRx; /*offset = 0x00*/ + __IO uint32_t TRx; /*offset = 0x04*/ + uint32_t RESERVED0[63]; /*offset = 0x08*/ + __IO uint32_t WTRx; /*offset = 0x104*/ +} XFMC_Bank1_Block; + +/** + * @brief Extended Flexible Memory Controller BANK2/3 + */ + +typedef struct +{ + __IO uint32_t CTRLx; + __IO uint32_t STSx; + __IO uint32_t CMEMTMx; + __IO uint32_t ATTMEMTMx; + uint32_t RESERVED0; + __IO uint32_t ECCx; +} XFMC_Bank23_Module; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t PL_CFG; + __IO uint32_t PH_CFG; + __IO uint32_t PID; + __IO uint32_t POD; + __IO uint32_t PBSC; + __IO uint32_t PBC; + __IO uint32_t PLOCK_CFG; + uint32_t RESERVED0; + __IO uint32_t DS_CFG; + __IO uint32_t SR_CFG; +} GPIO_Module; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t ECTRL; + __IO uint32_t RMP_CFG; + __IO uint32_t EXTI_CFG[4]; + uint32_t RESERVED0; + __IO uint32_t RMP_CFG2; + __IO uint32_t RMP_CFG3; + __IO uint32_t RMP_CFG4; + __IO uint32_t RMP_CFG5; +} AFIO_Module; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DAT; + uint16_t RESERVED4; + __IO uint16_t STS1; + uint16_t RESERVED5; + __IO uint16_t STS2; + uint16_t RESERVED6; + __IO uint16_t CLKCTRL; + uint16_t RESERVED7; + __IO uint16_t TMRISE; + uint16_t RESERVED8; +} I2C_Module; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KEY; + __IO uint32_t PREDIV; /*!< IWDG PREDIV */ + __IO uint32_t RELV; + __IO uint32_t STS; +} IWDG_Module; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CTRLSTS; + __IO uint32_t CTRL2; + __IO uint32_t CTRL3; +} PWR_Module; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CFG; + __IO uint32_t CLKINT; + __IO uint32_t APB2PRST; + __IO uint32_t APB1PRST; + __IO uint32_t AHBPCLKEN; + __IO uint32_t APB2PCLKEN; + __IO uint32_t APB1PCLKEN; + __IO uint32_t BDCTRL; + __IO uint32_t CTRLSTS; + + __IO uint32_t AHBPRST; + __IO uint32_t CFG2; + __IO uint32_t CFG3; +} RCC_Module; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved0; /*!< Reserved */ + __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */ + uint32_t reserved6; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */ + uint32_t reserved1; /*!< Reserved Address offset: 0x50 */ + uint32_t reserved2; /*!< Reserved Address offset: 0x54 */ + uint32_t reserved3; /*!< Reserved Address offset: 0x58 */ + uint32_t reserved4; /*!< Reserved Address offset: 0x5C */ + uint32_t reserved5; /*!< Reserved Address offset: 0x60 */ + __IO uint32_t TSCWKUPCTRL; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t TSCWKUPCNT; /*!< RTC backup register 6, Address offset: 0x68 */ +} RTC_Module; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t PWRCTRL; + __IO uint32_t CLKCTRL; + __IO uint32_t CMDARG; + __IO uint32_t CMDCTRL; + __I uint32_t CMDRESP; + __I uint32_t RESPONSE1; + __I uint32_t RESPONSE2; + __I uint32_t RESPONSE3; + __I uint32_t RESPONSE4; + __IO uint32_t DTIMER; + __IO uint32_t DATLEN; + __IO uint32_t DATCTRL; + __I uint32_t DATCOUNT; + __I uint32_t STS; + __IO uint32_t INTCLR; + __IO uint32_t INTEN; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCOUNT; + uint32_t RESERVED1[13]; + __IO uint32_t DATFIFO; +} SDIO_Module; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t STS; + uint16_t RESERVED2; + __IO uint16_t DAT; + uint16_t RESERVED3; + __IO uint16_t CRCPOLY; + uint16_t RESERVED4; + __IO uint16_t CRCRDAT; + uint16_t RESERVED5; + __IO uint16_t CRCTDAT; + uint16_t RESERVED6; + __IO uint16_t I2SCFG; + uint16_t RESERVED7; + __IO uint16_t I2SPREDIV; + uint16_t RESERVED8; +} SPI_Module; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint16_t SMCTRL; + uint16_t RESERVED1; + __IO uint16_t DINTEN; + uint16_t RESERVED2; + __IO uint32_t STS; + __IO uint16_t EVTGEN; + uint16_t RESERVED3; + __IO uint16_t CCMOD1; + uint16_t RESERVED4; + __IO uint16_t CCMOD2; + uint16_t RESERVED5; + __IO uint32_t CCEN; + __IO uint16_t CNT; + uint16_t RESERVED6; + __IO uint16_t PSC; + uint16_t RESERVED7; + __IO uint16_t AR; + uint16_t RESERVED8; + __IO uint16_t REPCNT; + uint16_t RESERVED9; + __IO uint16_t CCDAT1; + uint16_t RESERVED10; + __IO uint16_t CCDAT2; + uint16_t RESERVED11; + __IO uint16_t CCDAT3; + uint16_t RESERVED12; + __IO uint16_t CCDAT4; + uint16_t RESERVED13; + __IO uint16_t BKDT; + uint16_t RESERVED14; + __IO uint16_t DCTRL; + uint16_t RESERVED15; + __IO uint16_t DADDR; + uint16_t RESERVED16; + uint32_t RESERVED17; + __IO uint16_t CCMOD3; + uint16_t RESERVED18; + __IO uint16_t CCDAT5; + uint16_t RESERVED19; + __IO uint16_t CCDAT6; + uint16_t RESERVED20; +} TIM_Module; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t STS; + uint16_t RESERVED0; + __IO uint16_t DAT; + uint16_t RESERVED1; + __IO uint16_t BRCF; + uint16_t RESERVED2; + __IO uint16_t CTRL1; + uint16_t RESERVED3; + __IO uint16_t CTRL2; + uint16_t RESERVED4; + __IO uint16_t CTRL3; + uint16_t RESERVED5; + __IO uint16_t GTP; + uint16_t RESERVED6; +} USART_Module; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CFG; + __IO uint32_t STS; +} WWDG_Module; + +/** + * @brief QSPI + */ +typedef struct +{ + __IO uint32_t CTRL0; + __IO uint32_t CTRL1; + __IO uint32_t EN; + __IO uint32_t MW_CTRL; + __IO uint32_t SLAVE_EN; + __IO uint32_t BAUD; + __IO uint32_t TXFT; + __IO uint32_t RXFT; + __IO uint32_t TXFN; + __IO uint32_t RXFN; + __IO uint32_t STS; + __IO uint32_t IMASK; + __IO uint32_t ISTS; + __IO uint32_t RISTS; + __IO uint32_t TXFOI_CLR; + __IO uint32_t RXFOI_CLR; + __IO uint32_t RXFUI_CLR; + __IO uint32_t MMC_CLR; + __IO uint32_t ICLR; + __IO uint32_t DMA_CTRL; + __IO uint32_t DMATDL_CTRL; + __IO uint32_t DMARDL_CTRL; + __IO uint32_t IDCODE; + __IO uint32_t RESERVED; + __IO uint32_t DAT0; + __IO uint32_t DAT1; + __IO uint32_t DAT2; + __IO uint32_t DAT3; + __IO uint32_t DAT4; + __IO uint32_t DAT5; + __IO uint32_t DAT6; + __IO uint32_t DAT7; + __IO uint32_t DAT8; + __IO uint32_t DAT9; + __IO uint32_t DAT10; + __IO uint32_t DAT11; + __IO uint32_t DAT12; + __IO uint32_t DAT13; + __IO uint32_t DAT14; + __IO uint32_t DAT15; + __IO uint32_t DAT16; + __IO uint32_t DAT17; + __IO uint32_t DAT18; + __IO uint32_t DAT19; + __IO uint32_t DAT20; + __IO uint32_t DAT21; + __IO uint32_t DAT22; + __IO uint32_t DAT23; + __IO uint32_t DAT24; + __IO uint32_t DAT25; + __IO uint32_t DAT26; + __IO uint32_t DAT27; + __IO uint32_t DAT28; + __IO uint32_t DAT29; + __IO uint32_t DAT30; + __IO uint32_t DAT31; + __IO uint32_t RESERVED2; /*DAT32-DAT35 is reserved*/ + __IO uint32_t RESERVED3; /*DAT32-DAT35 is reserved*/ + __IO uint32_t RESERVED4; /*DAT32-DAT35 is reserved*/ + __IO uint32_t RESERVED5; /*DAT32-DAT35 is reserved*/ + __IO uint32_t RS_DELAY; + __IO uint32_t ENH_CTRL0; + __IO uint32_t DDR_TXDE; + __IO uint32_t XIP_MODE; + __IO uint32_t XIP_INCR_TOC; + __IO uint32_t XIP_WRAP_TOC; + __IO uint32_t XIP_CTRL; + __IO uint32_t XIP_SLAVE_EN; + __IO uint32_t XIP_RXFOI_CLR; + __IO uint32_t XIP_TOUT; + +} QSPI_Module; + +/** + * @brief Touch Sensor Controller + */ +#ifndef TSC_USED_NEW_SDK +#define TSC_USED_NEW_SDK 1 +#endif + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CHNEN; + __IO uint32_t STS; + __IO uint32_t RESERVED; + __IO uint32_t ANA_CTRL; + __IO uint32_t ANA_SEL; + +#if (TSC_USED_NEW_SDK) + __IO uint32_t RESR[3]; + __IO uint32_t THRHD[24]; +#else + __IO uint32_t RESR0; + __IO uint32_t RESR1; + __IO uint32_t RESR2; + __IO uint32_t THRHD0; + __IO uint32_t THRHD1; + __IO uint32_t THRHD2; + __IO uint32_t THRHD3; + __IO uint32_t THRHD4; + __IO uint32_t THRHD5; + __IO uint32_t THRHD6; + __IO uint32_t THRHD7; + __IO uint32_t THRHD8; + __IO uint32_t THRHD9; + __IO uint32_t THRHD10; + __IO uint32_t THRHD11; + __IO uint32_t THRHD12; + __IO uint32_t THRHD13; + __IO uint32_t THRHD14; + __IO uint32_t THRHD15; + __IO uint32_t THRHD16; + __IO uint32_t THRHD17; + __IO uint32_t THRHD18; + __IO uint32_t THRHD19; + __IO uint32_t THRHD20; + __IO uint32_t THRHD21; + __IO uint32_t THRHD22; + __IO uint32_t THRHD23; +#endif +} TSC_Module; + +/** + * @brief DVP + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< DVP control register*/ + __IO uint32_t STS; /*!< DVP status register*/ + __IO uint32_t INTSTS; /*!< DVP interrupt status register*/ + __IO uint32_t INTEN; /*!< DVP interrupt enable register*/ + __IO uint32_t MINTSTS; /*!< DVP interrupt mask status register */ + __IO uint32_t WST; /*!< DVP start register */ + __IO uint32_t WSIZE; /*!< DVP size register */ + __IO uint32_t FIFO; /*!< DVP FIFO register */ +} DVP_Module; + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define XFMC_REG_BASE ((uint32_t)0xA0000000) /*!< XFMC registers base address */ + +#define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */ +#define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */ +#define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */ +#define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */ +#define DBGMCU_ID_BASE ((uint32_t)0xE0042000) /*!< DBGMCU_ID Address */ +#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x18000) + +/* APB1 */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define AFEC_BASE (APB1PERIPH_BASE + 0x1800) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x2000) +#define COMP_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define TSC_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00) +#define USB_CAN1_SRAM_BASE (APB1PERIPH_BASE + 0x6000) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/* APB2 */ +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define I2C3_BASE (APB2PERIPH_BASE + 0x4400) +#define I2C4_BASE (APB2PERIPH_BASE + 0x4800) +#define DVP_BASE (APB2PERIPH_BASE + 0x4C00) +#define UART6_BASE (APB2PERIPH_BASE + 0x5000) +#define UART7_BASE (APB2PERIPH_BASE + 0x5400) + +/* AHB */ +#define SDIO_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_BASE (AHBPERIPH_BASE + 0x8000) +#define DMA1_CH1_BASE (AHBPERIPH_BASE + 0x8008) +#define DMA1_CH2_BASE (AHBPERIPH_BASE + 0x801C) +#define DMA1_CH3_BASE (AHBPERIPH_BASE + 0x8030) +#define DMA1_CH4_BASE (AHBPERIPH_BASE + 0x8044) +#define DMA1_CH5_BASE (AHBPERIPH_BASE + 0x8058) +#define DMA1_CH6_BASE (AHBPERIPH_BASE + 0x806C) +#define DMA1_CH7_BASE (AHBPERIPH_BASE + 0x8080) +#define DMA1_CH8_BASE (AHBPERIPH_BASE + 0x8094) +#define DMA2_BASE (AHBPERIPH_BASE + 0x8400) +#define DMA2_CH1_BASE (AHBPERIPH_BASE + 0x8408) +#define DMA2_CH2_BASE (AHBPERIPH_BASE + 0x841C) +#define DMA2_CH3_BASE (AHBPERIPH_BASE + 0x8430) +#define DMA2_CH4_BASE (AHBPERIPH_BASE + 0x8444) +#define DMA2_CH5_BASE (AHBPERIPH_BASE + 0x8458) +#define DMA2_CH6_BASE (AHBPERIPH_BASE + 0x846C) +#define DMA2_CH7_BASE (AHBPERIPH_BASE + 0x8480) +#define DMA2_CH8_BASE (AHBPERIPH_BASE + 0x8494) +#define ADC1_BASE (AHBPERIPH_BASE + 0x8800) +#define ADC2_BASE (AHBPERIPH_BASE + 0x8C00) +#define RCC_BASE (AHBPERIPH_BASE + 0x9000) +#define ADC3_BASE (AHBPERIPH_BASE + 0x9800) +#define ADC4_BASE (AHBPERIPH_BASE + 0x9C00) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0xB000) +#define SAC_BASE (AHBPERIPH_BASE + 0xC000) +#define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400) +#define MMU_BASE (AHBPERIPH_BASE + 0xCC00) +#define ETH_BASE (AHBPERIPH_BASE + 0x10000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define XFMC_BANK1_BASE (XFMC_REG_BASE + 0x0000) /*!< XFMC Bank1 registers base address */ +#define XFMC_BANK2_BASE (XFMC_REG_BASE + 0x0060) /*!< XFMC Bank2 registers base address */ +#define XFMC_BANK3_BASE (XFMC_REG_BASE + 0x0080) /*!< XFMC Bank3 registers base address */ + +#define QSPI_BASE (XFMC_REG_BASE + 0x1000) + +#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +#define TIM2 ((TIM_Module*)TIM2_BASE) +#define TIM3 ((TIM_Module*)TIM3_BASE) +#define TIM4 ((TIM_Module*)TIM4_BASE) +#define TIM5 ((TIM_Module*)TIM5_BASE) +#define TIM6 ((TIM_Module*)TIM6_BASE) +#define TIM7 ((TIM_Module*)TIM7_BASE) +#define AFEC ((AFEC_Module*)AFEC_BASE) +#define OPAMP ((OPAMP_Module*)OPAMP_BASE) +#define COMP ((COMP_Module*)COMP_BASE) +#define RTC ((RTC_Module*)RTC_BASE) +#define WWDG ((WWDG_Module*)WWDG_BASE) +#define IWDG ((IWDG_Module*)IWDG_BASE) +#define TSC ((TSC_Module*)TSC_BASE) +#define SPI2 ((SPI_Module*)SPI2_BASE) +#define SPI3 ((SPI_Module*)SPI3_BASE) +#define USART2 ((USART_Module*)USART2_BASE) +#define USART3 ((USART_Module*)USART3_BASE) +#define UART4 ((USART_Module*)UART4_BASE) +#define UART5 ((USART_Module*)UART5_BASE) +#define I2C1 ((I2C_Module*)I2C1_BASE) +#define I2C2 ((I2C_Module*)I2C2_BASE) +#define USB ((USB_Module*)USB_BASE) +#define CAN1 ((CAN_Module*)CAN1_BASE) +#define CAN2 ((CAN_Module*)CAN2_BASE) +#define BKP ((BKP_Module*)BKP_BASE) +#define PWR ((PWR_Module*)PWR_BASE) +#define DAC ((DAC_Module*)DAC_BASE) +#define AFIO ((AFIO_Module*)AFIO_BASE) +#define EXTI ((EXTI_Module*)EXTI_BASE) +#define GPIOA ((GPIO_Module*)GPIOA_BASE) +#define GPIOB ((GPIO_Module*)GPIOB_BASE) +#define GPIOC ((GPIO_Module*)GPIOC_BASE) +#define GPIOD ((GPIO_Module*)GPIOD_BASE) +#define GPIOE ((GPIO_Module*)GPIOE_BASE) +#define GPIOF ((GPIO_Module*)GPIOF_BASE) +#define GPIOG ((GPIO_Module*)GPIOG_BASE) +#define TIM1 ((TIM_Module*)TIM1_BASE) +#define SPI1 ((SPI_Module*)SPI1_BASE) +#define TIM8 ((TIM_Module*)TIM8_BASE) +#define USART1 ((USART_Module*)USART1_BASE) +#define I2C3 ((I2C_Module*)I2C3_BASE) +#define I2C4 ((I2C_Module*)I2C4_BASE) +#define DVP ((DVP_Module*)DVP_BASE) +#define UART6 ((USART_Module*)UART6_BASE) +#define UART7 ((USART_Module*)UART7_BASE) +#define SDIO ((SDIO_Module*)SDIO_BASE) +#define DMA1 ((DMA_Module*)DMA1_BASE) +#define DMA2 ((DMA_Module*)DMA2_BASE) +#define DMA1_CH1 ((DMA_ChannelType*)DMA1_CH1_BASE) +#define DMA1_CH2 ((DMA_ChannelType*)DMA1_CH2_BASE) +#define DMA1_CH3 ((DMA_ChannelType*)DMA1_CH3_BASE) +#define DMA1_CH4 ((DMA_ChannelType*)DMA1_CH4_BASE) +#define DMA1_CH5 ((DMA_ChannelType*)DMA1_CH5_BASE) +#define DMA1_CH6 ((DMA_ChannelType*)DMA1_CH6_BASE) +#define DMA1_CH7 ((DMA_ChannelType*)DMA1_CH7_BASE) +#define DMA1_CH8 ((DMA_ChannelType*)DMA1_CH8_BASE) +#define DMA2_CH1 ((DMA_ChannelType*)DMA2_CH1_BASE) +#define DMA2_CH2 ((DMA_ChannelType*)DMA2_CH2_BASE) +#define DMA2_CH3 ((DMA_ChannelType*)DMA2_CH3_BASE) +#define DMA2_CH4 ((DMA_ChannelType*)DMA2_CH4_BASE) +#define DMA2_CH5 ((DMA_ChannelType*)DMA2_CH5_BASE) +#define DMA2_CH6 ((DMA_ChannelType*)DMA2_CH6_BASE) +#define DMA2_CH7 ((DMA_ChannelType*)DMA2_CH7_BASE) +#define DMA2_CH8 ((DMA_ChannelType*)DMA2_CH8_BASE) +#define ADC1 ((ADC_Module*)ADC1_BASE) +#define ADC2 ((ADC_Module*)ADC2_BASE) +#define RCC ((RCC_Module*)RCC_BASE) +#define ADC3 ((ADC_Module*)ADC3_BASE) +#define ADC4 ((ADC_Module*)ADC4_BASE) +#define FLASH ((FLASH_Module*)FLASH_R_BASE) +#define OB ((OB_Module*)OB_BASE) +#define CRC ((CRC_Module*)CRC_BASE) +#define ETH ((ETH_Module*)ETH_BASE) +#define XFMC ((XFMC_Module*)XFMC_REG_BASE) +#define XFMC_BANK1_BLOCK1 ((XFMC_Bank1_Block*)XFMC_BANK1_BASE) +#define XFMC_BANK1_BLOCK2 ((XFMC_Bank1_Block*)(XFMC_BANK1_BASE+0x0008)) +#define XFMC_BANK2 ((XFMC_Bank23_Module*)XFMC_BANK2_BASE) +#define XFMC_BANK3 ((XFMC_Bank23_Module*)XFMC_BANK3_BASE) + +#define QSPI ((QSPI_Module*)QSPI_BASE) + +#define DBG ((DBG_Module*)DBG_BASE) + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_CRC32DAT register *********************/ +#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_CRC32IDAT register ********************/ +#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CRC32CTRL register ********************/ +#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************** Bit definition for CRC16_CR register ********************/ +#define CRC16_CTRL_LITTLE ((uint8_t)0x02) +#define CRC16_CTRL_BIG ((uint8_t)0xFD) + +#define CRC16_CTRL_RESET ((uint8_t)0x04) +#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB) + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTRL register ********************/ +#define PWR_CTRL_LPS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CTRL_PDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CTRL_CWKUP ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CTRL_CSBVBAT ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CTRL_PVDEN ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CTRL_PRS ((uint16_t)0x00E0) /*!< PRS[2:0] bits (PVD Level Selection) */ +#define PWR_CTRL_PRS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CTRL_PRS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CTRL_PRS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CTRL_PRS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CTRL_PRS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CTRL_PRS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CTRL_PRS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CTRL_PRS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CTRL_PRS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CTRL_PRS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CTRL_PRS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CTRL_DBKP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ +#define PWR_CTRL_MSB ((uint16_t)0x0200) /*!< Bit 9 */ + +/******************* Bit definition for PWR_CTRLSTS register ********************/ +#define PWR_CTRLSTS_WKUPF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CTRLSTS_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CTRLSTS_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CTRLSTS_VBATF ((uint16_t)0x0008) /*!< VBAT Flag */ +#define PWR_CTRLSTS_WKUPEN ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************* Bit definition for PWR_CTRL2 register ********************/ +#define PWR_CTRL2_STOP2S ((uint16_t)0x0001) /*!< Enable STOP2 */ +#define PWR_CTRL2_SR2VBRET ((uint16_t)0x0002) /*!< VBAT mode SRAM2 retention */ +#define PWR_CTRL2_SR2STBRET ((uint16_t)0x0004) /*!< Standby mode SRAM2 retention */ +#define PWR_CTRL2_TMPWPEN ((uint16_t)0x0008) /*!< Enable Tamper WakeUp */ +#define PWR_CTRL2_LSITRIM ((uint16_t)0x01F0) /*!< config the LSI trimming value */ +#define PWR_CTRL2_IWDGWPEN ((uint16_t)0x0200) /*!< Enable IWDG WakeUp */ +#define PWR_CTRL2_IWDGRSTEN ((uint16_t)0x0400) /*!< Enable IWDG RST WakeUp */ + +/******************* Bit definition for PWR_CTRL3 register ********************/ +#define PWR_CTRL3_EXMODE ((uint16_t)0x0001) /*!< BKPM Mode */ +#define PWR_CTRL3_EXMODE_EXTEND ((uint16_t)0x0001) /*!< EXTEND Mode */ +#define PWR_CTRL3_EXMODE_NORMAL ((uint16_t)0x0000) /*!< NORMAL Mode */ + + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DAT1 register ********************/ +#define BKP_DAT1_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT2 register ********************/ +#define BKP_DAT2_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT3 register ********************/ +#define BKP_DAT3_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT4 register ********************/ +#define BKP_DAT4_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT5 register ********************/ +#define BKP_DAT5_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT6 register ********************/ +#define BKP_DAT6_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT7 register ********************/ +#define BKP_DAT7_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT8 register ********************/ +#define BKP_DAT8_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT9 register ********************/ +#define BKP_DAT9_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT10 register *******************/ +#define BKP_DAT10_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT11 register *******************/ +#define BKP_DAT11_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT12 register *******************/ +#define BKP_DAT12_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT13 register *******************/ +#define BKP_DAT13_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT14 register *******************/ +#define BKP_DAT14_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT15 register *******************/ +#define BKP_DAT15_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT16 register *******************/ +#define BKP_DAT16_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT17 register *******************/ +#define BKP_DAT17_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DAT18 register ********************/ +#define BKP_DAT18_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT19 register *******************/ +#define BKP_DAT19_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT20 register *******************/ +#define BKP_DAT20_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT21 register *******************/ +#define BKP_DAT21_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT22 register *******************/ +#define BKP_DAT22_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT23 register *******************/ +#define BKP_DAT23_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT24 register *******************/ +#define BKP_DAT24_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT25 register *******************/ +#define BKP_DAT25_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT26 register *******************/ +#define BKP_DAT26_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT27 register *******************/ +#define BKP_DAT27_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT28 register *******************/ +#define BKP_DAT28_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT29 register *******************/ +#define BKP_DAT29_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT30 register *******************/ +#define BKP_DAT30_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT31 register *******************/ +#define BKP_DAT31_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT32 register *******************/ +#define BKP_DAT32_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT33 register *******************/ +#define BKP_DAT33_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT34 register *******************/ +#define BKP_DAT34_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT35 register *******************/ +#define BKP_DAT35_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT36 register *******************/ +#define BKP_DAT36_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT37 register *******************/ +#define BKP_DAT37_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT38 register *******************/ +#define BKP_DAT38_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT39 register *******************/ +#define BKP_DAT39_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT40 register *******************/ +#define BKP_DAT40_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT41 register *******************/ +#define BKP_DAT41_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DAT42 register *******************/ +#define BKP_DAT42_DAT ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************** Bit definition for BKP_CTRL register ********************/ +#define BKP_CTRL_TP_EN ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CTRL_TP_ALEV ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CTRLSTS register ********************/ +#define BKP_CTRLSTS_CLRTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CTRLSTS_CLRTINT ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CTRLSTS_TPINT_EN ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CTRLSTS_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CTRLSTS_TINTF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTRL register ********************/ +#define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CTRL_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CTRL_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +/******************* Bit definition for RCC_CFG register *******************/ +/*!< SW configuration */ +#define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< PLLSRC configuration */ +#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +/*!< PLLXTPRE configuration */ +#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */ +#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */ +#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */ + +#define RCC_CFG_PLLSRC_HSI_DIV2 \ + ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source \ + */ +#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + +#define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ +#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ +#define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ +#define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ +#define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ +#define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ +#define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ +#define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ +#define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ +#define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ +#define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */ +#define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ +#define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ +#define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ +#define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ +#define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ +#define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ +#define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */ +#define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */ +#define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */ +#define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */ +#define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */ +#define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */ +#define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */ +#define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */ +#define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */ +#define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */ +#define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */ +#define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */ +#define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */ +#define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */ +#define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */ +#define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */ +#define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */ + +/*!< USBPRES configuration */ +#define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */ +#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */ +#define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */ +#define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock is divided by 3 */ +#define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 2 */ + +/*!< MCO configuration */ +#define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ +#define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ +#define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ +#define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + +/*!< MCOPRE configuration */ +#define RCC_CFG_MCOPRES \ + ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by software to generate MCOPRE \ + clock.) */ +#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */ +#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */ +#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */ + +#define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x20000000) /*!< PLL clock is divided by 2 */ +#define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x30000000) /*!< PLL clock is divided by 3 */ +#define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x40000000) /*!< PLL clock is divided by 4 */ +#define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x50000000) /*!< PLL clock is divided by 5 */ +#define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x60000000) /*!< PLL clock is divided by 6 */ +#define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x70000000) /*!< PLL clock is divided by 7 */ +#define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x80000000) /*!< PLL clock is divided by 8 */ +#define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x90000000) /*!< PLL clock is divided by 9 */ +#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 10 */ +#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 11 */ +#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 12 */ +#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 13 */ +#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 14 */ +#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 15 */ + +/*!<****************** Bit definition for RCC_CLKINT register ********************/ +#define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRST register *****************/ +#define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2PRST_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#define RCC_APB2PRST_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ +#define RCC_APB2PRST_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ +#define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ +#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ +#define RCC_APB2PRST_DVPRST ((uint32_t)0x00010000) /*!< DVP reset */ +#define RCC_APB2PRST_UART6RST ((uint32_t)0x00020000) /*!< UART6 reset */ +#define RCC_APB2PRST_UART7RST ((uint32_t)0x00040000) /*!< UART7 reset */ +#define RCC_APB2PRST_I2C3RST ((uint32_t)0x00080000) /*!< I2C3 reset */ +#define RCC_APB2PRST_I2C4RST ((uint32_t)0x00100000) /*!< I2C4 reset */ + +/***************** Bit definition for RCC_APB1PRST register *****************/ +#define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ +#define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ +#define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ +#define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ +#define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */ +#define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1PRST_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ +#define RCC_APB1PRST_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ +#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ +#define RCC_APB1PRST_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ +#define RCC_APB1PRST_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ +#define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#define RCC_APB1PRST_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#define RCC_APB1PRST_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#define RCC_APB1PRST_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ +#define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + +/****************** Bit definition for RCC_AHBPCLKEN register ******************/ +#define RCC_AHBPCLKEN_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ +#define RCC_AHBPCLKEN_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */ +#define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ +#define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ +#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ +#define RCC_AHBPCLKEN_XFMCEN ((uint32_t)0x00000100) /*!< XFMC clock enable */ +#define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */ +#define RCC_AHBPCLKEN_SDIOEN ((uint32_t)0x00000400) /*!< SDIO clock enable */ +#define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */ +#define RCC_AHBPCLKEN_ADC1EN ((uint32_t)0x00001000) /*!< ADC1 clock enable */ +#define RCC_AHBPCLKEN_ADC2EN ((uint32_t)0x00002000) /*!< ADC2 clock enable */ +#define RCC_AHBPCLKEN_ADC3EN ((uint32_t)0x00004000) /*!< ADC3 clock enable */ +#define RCC_AHBPCLKEN_ADC4EN ((uint32_t)0x00008000) /*!< ADC4 clock enable */ +#define RCC_AHBPCLKEN_ETHMACEN ((uint32_t)0x00010000) /*!< ETHMAC clock enable */ +#define RCC_AHBPCLKEN_QSPIEN ((uint32_t)0x00020000) /*!< QSPI clock enable */ + +/****************** Bit definition for RCC_APB2PCLKEN register *****************/ +#define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2PCLKEN_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#define RCC_APB2PCLKEN_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ +#define RCC_APB2PCLKEN_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ +#define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ +#define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ +#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ +#define RCC_APB2PCLKEN_DVPEN ((uint32_t)0x00010000) /*!< DVP clock enable */ +#define RCC_APB2PCLKEN_UART6EN ((uint32_t)0x00020000) /*!< UART6 clock enable */ +#define RCC_APB2PCLKEN_UART7EN ((uint32_t)0x00040000) /*!< UART7 clock enable */ +#define RCC_APB2PCLKEN_I2C3EN ((uint32_t)0x00080000) /*!< I2C3 clock enable */ +#define RCC_APB2PCLKEN_I2C4EN ((uint32_t)0x00100000) /*!< I2C4 clock enable */ + +/***************** Bit definition for RCC_APB1PCLKEN register ******************/ +#define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ +#define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ +#define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ +#define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ +#define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */ +#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */ +#define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */ +#define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1PCLKEN_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ +#define RCC_APB1PCLKEN_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ +#define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ +#define RCC_APB1PCLKEN_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ +#define RCC_APB1PCLKEN_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ +#define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ +#define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#define RCC_APB1PCLKEN_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#define RCC_APB1PCLKEN_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#define RCC_APB1PCLKEN_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ +#define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#define RCC_APB1ENR_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */ + +/******************* Bit definition for RCC_BDCTRL register *******************/ +#define RCC_BDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCTRL_BDSFTRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CTRLSTS register ********************/ +#define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CTRLSTS_BORRSTF ((uint32_t)0x00080000) /*!< BOR reset flag */ +#define RCC_CTRLSTS_RETEMCF ((uint32_t)0x00100000) /*!< RET_EMC reset flag */ +#define RCC_CTRLSTS_BKPEMCF ((uint32_t)0x00200000) /*!< BKP_EMC reset flag */ +#define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */ +#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */ +#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBPRST register ****************/ +#define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */ +#define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */ +#define RCC_AHBRST_ADC1RST ((uint32_t)0x00001000) /*!< ADC1 reset */ +#define RCC_AHBRST_ADC2RST ((uint32_t)0x00002000) /*!< ADC2 reset */ +#define RCC_AHBRST_ADC3RST ((uint32_t)0x00004000) /*!< ADC3 reset */ +#define RCC_AHBRST_ADC4RST ((uint32_t)0x00008000) /*!< ADC4 reset */ +#define RCC_AHBRST_ETHMACRST ((uint32_t)0x00010000) /*!< ETHMAC reset */ +#define RCC_AHBRST_QSPIRST ((uint32_t)0x00020000) /*!< QSPI reset */ + +/******************* Bit definition for RCC_CFG2 register ******************/ +/*!< ADCHPRE configuration */ +#define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */ +#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */ +#define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */ +#define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */ +#define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */ +#define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */ +#define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */ +#define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */ +#define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */ +#define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ +#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */ + +/*!< ADCPLLPRES configuration */ +#define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */ +#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */ +#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */ + +#define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */ +#define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */ +#define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */ +#define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */ +#define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */ +#define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */ +#define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */ +#define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */ +#define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */ +#define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */ +#define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */ +#define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */ +#define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */ +#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */ + +/*!< ADC1MSEL configuration */ +#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00000400) /*!< ADC1M clock source select */ + +#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */ +#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00000400) /*!< HSE clock selected as ADC1M input clock */ + +/*!< ADC1MPRE configuration */ +#define RCC_CFG2_ADC1MPRES ((uint32_t)0x0000F800) /*!< ADC1MPRE[4:0] bits */ +#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ +#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */ +#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */ + +#define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */ +#define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00000800) /*!< ADC1M source clock is divided by 2 */ +#define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 3 */ +#define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00001800) /*!< ADC1M source clock is divided by 4 */ +#define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 5 */ +#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00002800) /*!< ADC1M source clock is divided by 6 */ +#define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 7 */ +#define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00003800) /*!< ADC1M source clock is divided by 8 */ +#define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 9 */ +#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00004800) /*!< ADC1M source clock is divided by 10 */ +#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 11 */ +#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x00005800) /*!< ADC1M source clock is divided by 12 */ +#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 13 */ +#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x00006800) /*!< ADC1M source clock is divided by 14 */ +#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 15 */ +#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x00007800) /*!< ADC1M source clock is divided by 16 */ +#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 17 */ +#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00008800) /*!< ADC1M source clock is divided by 18 */ +#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 19 */ +#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00009800) /*!< ADC1M source clock is divided by 20 */ +#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 21 */ +#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x0000A800) /*!< ADC1M source clock is divided by 22 */ +#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 23 */ +#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x0000B800) /*!< ADC1M source clock is divided by 24 */ +#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 25 */ +#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x0000C800) /*!< ADC1M source clock is divided by 26 */ +#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 27 */ +#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0000D800) /*!< ADC1M source clock is divided by 28 */ +#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 29 */ +#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0000E800) /*!< ADC1M source clock is divided by 30 */ +#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 31 */ +#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0000F800) /*!< ADC1M source clock is divided by 32 */ + +/*!< RNGCPRE configuration */ +#define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */ +#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */ + +#define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */ +#define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */ +#define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */ +#define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */ +#define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */ +#define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */ +#define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */ +#define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */ +#define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */ +#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */ +#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */ +#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */ +#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */ +#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */ +#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */ +#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */ +#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */ +#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */ +#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */ +#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */ +#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */ +#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */ +#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */ +#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */ +#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */ +#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */ +#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */ +#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */ +#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */ +#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */ +#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */ +#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */ + +/*!< TIMCLK_SEL configuration */ +#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */ + +#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */ +#define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */ + +/******************* Bit definition for RCC_CFG3 register ******************/ +/*!< BORRSTEN configuration */ +#define RCC_CFG3_BORRSTEN ((uint32_t)0x00000040) /*!< BOR reset enable */ + +#define RCC_CFG3_BORRSTEN_ENABLE ((uint32_t)0x00000040) /*!< BOR reset enable */ +#define RCC_CFG3_BORRSTEN_DISABLE ((uint32_t)0x00000000) /*!< BOR reset disable */ + +/*!< TRNG1MPRE configuration */ +#define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */ +#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */ +#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */ +#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */ + +#define RCC_CFG3_TRNG1MPRES_VAL1 ((uint32_t)0x00000000) /*!< TRNG 1M source clock is divided by 2 */ +#define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */ +#define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */ +#define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 4 */ +#define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 6 */ +#define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 6 */ +#define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 8 */ +#define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 8 */ +#define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 10 */ +#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 10 */ +#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 12 */ +#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 12 */ +#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 14 */ +#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 14 */ +#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 16 */ +#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 16 */ +#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 18 */ +#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 18 */ +#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 20 */ +#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 20 */ +#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 22 */ +#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 22 */ +#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 24 */ +#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 24 */ +#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 26 */ +#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 26 */ +#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 28 */ +#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 28 */ +#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 30 */ +#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 30 */ +#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 32 */ +#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 32 */ + +/*!< TRNG1MSEL configuration */ +#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */ + +#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */ +#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */ + +/*!< TRNG1MEN configuration */ +#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ + +#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */ +#define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */ + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_PL_CFG register *******************/ +#define GPIO_PL_CFG_PMODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_PL_CFG_PMODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_PL_CFG_PMODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_PL_CFG_PMODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PMODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_PL_CFG_PMODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_PL_CFG_PMODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PMODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_PL_CFG_PMODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_PL_CFG_PMODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PMODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_PL_CFG_PMODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PMODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PMODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_PL_CFG_PMODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PMODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PMODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_PL_CFG_PMODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PMODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PMODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_PL_CFG_PMODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PMODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PMODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_PL_CFG_PMODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PMODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PCFG ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_PL_CFG_PCFG0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_PL_CFG_PCFG0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_PL_CFG_PCFG0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PCFG1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_PL_CFG_PCFG1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_PL_CFG_PCFG1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PCFG2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_PL_CFG_PCFG2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_PL_CFG_PCFG2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PCFG3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_PL_CFG_PCFG3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PCFG3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PCFG4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_PL_CFG_PCFG4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PCFG4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PCFG5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_PL_CFG_PCFG5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PCFG5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PCFG6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_PL_CFG_PCFG6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PCFG6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_PL_CFG_PCFG7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_PL_CFG_PCFG7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_PL_CFG_PCFG7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_PH_CFG register *******************/ +#define GPIO_PH_CFG_PMODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_PH_CFG_PMODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_PH_CFG_PMODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_PH_CFG_PMODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PMODE1 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_PH_CFG_PMODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_PH_CFG_PMODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PMODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_PH_CFG_PMODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_PH_CFG_PMODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PMODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_PH_CFG_PMODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PMODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PMODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_PH_CFG_PMODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PMODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PMODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_PH_CFG_PMODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PMODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PMODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_PH_CFG_PMODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PMODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PMODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_PH_CFG_PMODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PMODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PCFG ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_PH_CFG_PCFG8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_PH_CFG_PCFG8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_PH_CFG_PCFG8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PCFG9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_PH_CFG_PCFG9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_PH_CFG_PCFG9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PCFG10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_PH_CFG_PCFG10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_PH_CFG_PCFG10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PCFG11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_PH_CFG_PCFG11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PCFG11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PCFG12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_PH_CFG_PCFG12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PCFG12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PCFG13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_PH_CFG_PCFG13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PCFG13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PCFG14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_PH_CFG_PCFG14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PCFG14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_PH_CFG_PCFG15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_PH_CFG_PCFG15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_PH_CFG_PCFG15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_PID register *******************/ +#define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_POD register *******************/ +#define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_PBSC register *******************/ +#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_PBC register *******************/ +#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_PLOCK_CFG register *******************/ +#define GPIO_PLOCK_CFG_PLOCK_CFG0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_PLOCK_CFG_PLOCK_CFG15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_PLOCK_CFG_PLOCKK_CFG ((uint32_t)0x00010000) /*!< Lock key */ + +/******************* Bit definition for GPIO_DS_CFG register *******************/ +#define GPIO_DS_CFG0 ((uint16_t)0x0001) /*!< Port x Drive bit 0 */ +#define GPIO_DS_CFG1 ((uint16_t)0x0002) /*!< Port x Drive bit 1 */ +#define GPIO_DS_CFG2 ((uint16_t)0x0004) /*!< Port x Drive bit 2 */ +#define GPIO_DS_CFG3 ((uint16_t)0x0008) /*!< Port x Drive bit 3 */ +#define GPIO_DS_CFG4 ((uint16_t)0x0010) /*!< Port x Drive bit 4 */ +#define GPIO_DS_CFG5 ((uint16_t)0x0020) /*!< Port x Drive bit 5 */ +#define GPIO_DS_CFG6 ((uint16_t)0x0040) /*!< Port x Drive bit 6 */ +#define GPIO_DS_CFG7 ((uint16_t)0x0080) /*!< Port x Drive bit 7 */ +#define GPIO_DS_CFG8 ((uint16_t)0x0100) /*!< Port x Drive bit 8 */ +#define GPIO_DS_CFG9 ((uint16_t)0x0200) /*!< Port x Drive bit 9 */ +#define GPIO_DS_CFG10 ((uint16_t)0x0400) /*!< Port x Drive bit 10 */ +#define GPIO_DS_CFG11 ((uint16_t)0x0800) /*!< Port x Drive bit 11 */ +#define GPIO_DS_CFG12 ((uint16_t)0x1000) /*!< Port x Drive bit 12 */ +#define GPIO_DS_CFG13 ((uint16_t)0x2000) /*!< Port x Drive bit 13 */ +#define GPIO_DS_CFG14 ((uint16_t)0x4000) /*!< Port x Drive bit 14 */ +#define GPIO_DS_CFG15 ((uint16_t)0x8000) /*!< Port x Drive bit 15 */ + +/******************* Bit definition for GPIO_SR_CFG register *******************/ +#define GPIO_SR_CFG0 ((uint16_t)0x0001) /*!< Port x Turn bit 0 */ +#define GPIO_SR_CFG1 ((uint16_t)0x0002) /*!< Port x Turn bit 1 */ +#define GPIO_SR_CFG2 ((uint16_t)0x0004) /*!< Port x Turn bit 2 */ +#define GPIO_SR_CFG3 ((uint16_t)0x0008) /*!< Port x Turn bit 3 */ +#define GPIO_SR_CFG4 ((uint16_t)0x0010) /*!< Port x Turn bit 4 */ +#define GPIO_SR_CFG5 ((uint16_t)0x0020) /*!< Port x Turn bit 5 */ +#define GPIO_SR_CFG6 ((uint16_t)0x0040) /*!< Port x Turn bit 6 */ +#define GPIO_SR_CFG7 ((uint16_t)0x0080) /*!< Port x Turn bit 7 */ +#define GPIO_SR_CFG8 ((uint16_t)0x0100) /*!< Port x Turn bit 8 */ +#define GPIO_SR_CFG9 ((uint16_t)0x0200) /*!< Port x Turn bit 9 */ +#define GPIO_SR_CFG10 ((uint16_t)0x0400) /*!< Port x Turn bit 10 */ +#define GPIO_SR_CFG11 ((uint16_t)0x0800) /*!< Port x Turn bit 11 */ +#define GPIO_SR_CFG12 ((uint16_t)0x1000) /*!< Port x Turn bit 12 */ +#define GPIO_SR_CFG13 ((uint16_t)0x2000) /*!< Port x Turn bit 13 */ +#define GPIO_SR_CFG14 ((uint16_t)0x4000) /*!< Port x Turn bit 14 */ +#define GPIO_SR_CFG15 ((uint16_t)0x8000) /*!< Port x Turn bit 15 */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_ECTRL register *******************/ +#define AFIO_ECTRL_PIN_SEL ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_ECTRL_PIN_SEL_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_ECTRL_PIN_SEL_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_ECTRL_PIN_SEL_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_ECTRL_PIN_SEL_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_ECTRL_PIN_SEL_PIN0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_ECTRL_PIN_SEL_PIN15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_ECTRL_PORT_SEL ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_ECTRL_PORT_SEL_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_ECTRL_PORT_SEL_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_ECTRL_PORT_SEL_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_ECTRL_PORT_SEL_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_ECTRL_PORT_SEL_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_ECTRL_PORT_SEL_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_ECTRL_PORT_SEL_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_ECTRL_PORT_SEL_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_ECTRL_EOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_RMP_CFG register *******************/ +#define AFIO_RMP_CFG_SPI1_RMP_0 ((uint32_t)0x00000001) /*!< SPI1_RMP_0 remapping */ +#define AFIO_RMP_CFG_I2C1_RMP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_RMP_CFG_USART1_RMP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_RMP_CFG_USART2_RMP_0 ((uint32_t)0x00000008) /*!< USART2_RMP_0 remapping */ + +#define AFIO_RMP_CFG_USART3_RMP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_RMP_CFG_USART3_RMP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_RMP_CFG_USART3_RMP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_RMP_CFG_USART3_RMP_NONE \ + ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_RMP_CFG_USART3_RMP_PART \ + ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_RMP_CFG_USART3_RMP_ALL \ + ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_RMP_CFG_TIM1_RMP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_RMP_CFG_TIM1_RMP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_RMP_CFG_TIM1_RMP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_RMP_CFG_TIM1_RMP_NONE \ + ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, \ + CH2N/PB14, CH3N/PB15) */ +#define AFIO_RMP_CFG_TIM1_RMP_PART \ + ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, \ + CH2N/PB0, CH3N/PB1) */ +#define AFIO_RMP_CFG_TIM1_RMP_ALL \ + ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, \ + CH2N/PE10, CH3N/PE12) */ + +#define AFIO_RMP_CFG_TIM2_RMP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_RMP_CFG_TIM2_RMP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_RMP_CFG_TIM2_RMP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_RMP_CFG_TIM2_RMP_NONE ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_RMP_CFG_TIM2_RMP_PART1 \ + ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_RMP_CFG_TIM2_RMP_PART2 \ + ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_RMP_CFG_TIM2_RMP_ALL \ + ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) \ + */ + +#define AFIO_RMP_CFG_TIM3_RMP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_RMP_CFG_TIM3_RMP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_RMP_CFG_TIM3_RMP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_RMP_CFG_TIM3_RMP_NONE ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_RMP_CFG_TIM3_RMP_PART ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_RMP_CFG_TIM3_RMP_ALL ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_RMP_CFG_TIM4_RMP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_RMP_CFG_CAN1_RMP ((uint32_t)0x00006000) /*!< CAN1_RMP[1:0] bits (CAN1 Alternate function remapping) */ +#define AFIO_RMP_CFG_CAN1_RMP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_RMP_CFG_CAN1_RMP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN1_REMAP configuration */ +#define AFIO_RMP_CFG_CAN1_RMP_RMP1 ((uint32_t)0x00000000) /*!< CAN1RX mapped to PA11, CAN1TX mapped to PA12 */ +#define AFIO_RMP_CFG_CAN1_RMP_RMP2 ((uint32_t)0x00004000) /*!< CAN1RX mapped to PB8, CAN1TX mapped to PB9 */ +#define AFIO_RMP_CFG_CAN1_RMP_RMP3 ((uint32_t)0x00006000) /*!< CAN1RX mapped to PD0, CAN1TX mapped to PD1 */ +#define AFIO_RMP_CFG_CAN1_RMP_RMP4 ((uint32_t)0x00002000) /*!< CAN1RX mapped to PD12, CAN1TX mapped to PD13 */ + +#define AFIO_RMP_CFG_PD01_RMP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_RMP_CFG_TIM5CH4_RMP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_RMP_CFG_ADC1_ETRI_RMP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_RMP_CFG_ADC1_ETRR_RMP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_RMP_CFG_ADC2_ETRI_RMP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_RMP_CFG_ADC2_ETRR_RMP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ +#define AFIO_RMP_CFG_MII_RMII_SEL ((uint32_t)0x00800000) /*!< ETH MAC MII_RMII_SEL remapping */ +/*!< SWJ_CFG configuration */ +#define AFIO_RMP_CFG_SW_JTAG_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_RMP_CFG_SW_JTAG_CFG0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_RMP_CFG_SW_JTAG_CFG1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_RMP_CFG_SW_JTAG_CFG2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_RMP_CFG_SW_JTAG_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_RMP_CFG_SW_JTAG_CFG_NO_NJTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST \ + */ +#define AFIO_RMP_CFG_SW_JTAG_CFG_SW_ENABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_RMP_CFG_SW_JTAG_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +/***************** Bit definition for AFIO_EXTI_CFG1 register *****************/ +#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTI_CFG1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTI_CFG1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTI_CFG1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTI_CFG1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTI_CFG2 register *****************/ +#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTI_CFG2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTI_CFG2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTI_CFG2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTI_CFG2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTI_CFG3 register *****************/ +#define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTI_CFG3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTI_CFG3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTI_CFG3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTI_CFG3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTI_CFG4 register *****************/ +#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTI_CFG4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTI_CFG4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTI_CFG4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTI_CFG4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +/****************** Bit definition for AFIO_RMP_CFG2 register *******************/ +#define AFIO_RMP_CFG2_XFMC_NADV ((uint32_t)0x80000400) /*!< XFMC_NADV Alternate Function mapping */ + +/****************** Bit definition for AFIO_RMP_CFG3 register *******************/ +#define AFIO_RMP_CFG3_SDIO_RMP ((uint32_t)0x00000001) /*!< SDIO remapping */ +#define AFIO_RMP_CFG3_CAN2_RMP ((uint32_t)0x00000006) /*! Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_WKUP_IRQHandler ; RTC_WKUP + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_4_IRQHandler ; ADC3 & ADC4 + DCD XFMC_IRQHandler ; XFMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet global interrupt + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD QSPI_IRQHandler ; QSPI + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel7 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD UART6_IRQHandler ; UART6 + DCD UART7_IRQHandler ; UART7 + DCD DMA1_Channel8_IRQHandler ; DMA1 Channel8 + DCD DMA2_Channel8_IRQHandler ; DMA2 Channel8 + DCD DVP_IRQHandler ; DVP + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD COMP_1_2_3_IRQHandler ; COMP1 & COMP2 & COMP3 + DCD COMP_4_5_6_IRQHandler ; COMP4 & COMP5 & COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD RSRAM_IRQHandler ; R-SRAM parity error interrupt +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_4_IRQHandler [WEAK] + EXPORT XFMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT UART6_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT DMA1_Channel8_IRQHandler [WEAK] + EXPORT DMA2_Channel8_IRQHandler [WEAK] + EXPORT DVP_IRQHandler [WEAK] + EXPORT SAC_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT COMP_1_2_3_IRQHandler [WEAK] + EXPORT COMP_4_5_6_IRQHandler [WEAK] + EXPORT COMP7_IRQHandler [WEAK] + EXPORT RSRAM_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_4_IRQHandler +XFMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +QSPI_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +UART6_IRQHandler +UART7_IRQHandler +DMA1_Channel8_IRQHandler +DMA2_Channel8_IRQHandler +DVP_IRQHandler +SAC_IRQHandler +MMU_IRQHandler +TSC_IRQHandler +COMP_1_2_3_IRQHandler +COMP_4_5_6_IRQHandler +COMP7_IRQHandler +RSRAM_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/startup/startup_n32g45x_EWARM.s b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/startup/startup_n32g45x_EWARM.s new file mode 100755 index 0000000000..8d53925ab1 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/startup/startup_n32g45x_EWARM.s @@ -0,0 +1,643 @@ +; **************************************************************************** +; Copyright (c) 2019, Nations Technologies Inc. +; +; All rights reserved. +; **************************************************************************** +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright notice, +; this list of conditions and the disclaimer below. +; +; Nations name may not be used to endorse or promote products derived from +; this software without specific prior written permission. +; +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; **************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_4_IRQHandler ; ADC3 & ADC4 + DCD XFMC_IRQHandler ; XFMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet global interrupt + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD QSPI_IRQHandler ; QSPI + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel7 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD UART6_IRQHandler ; UART6 + DCD UART7_IRQHandler ; UART7 + DCD DMA1_Channel8_IRQHandler ; DMA1 Channel8 + DCD DMA2_Channel8_IRQHandler ; DMA2 Channel8 + DCD DVP_IRQHandler ; DVP + DCD SAC_IRQHandler ; SAC + DCD MMU_IRQHandler ; MMU + DCD TSC_IRQHandler ; TSC + DCD COMP_1_2_3_IRQHandler ; COMP1 & COMP2 & COMP3 + DCD COMP_4_5_6_IRQHandler ; COMP4 & COMP5 & COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD RSRAM_IRQHandler ; R-SRAM parity error interrupt +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_4_IRQHandler + B ADC3_4_IRQHandler + + PUBWEAK XFMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +XFMC_IRQHandler + B XFMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK QSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QSPI_IRQHandler + B QSPI_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK UART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART6_IRQHandler + B UART6_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK DMA1_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel8_IRQHandler + B DMA1_Channel8_IRQHandler + + PUBWEAK DMA2_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel8_IRQHandler + B DMA2_Channel8_IRQHandler + + PUBWEAK DVP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP_IRQHandler + B DVP_IRQHandler + + PUBWEAK SAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAC_IRQHandler + B SAC_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK COMP_1_2_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_1_2_3_IRQHandler + B COMP_1_2_3_IRQHandler + + PUBWEAK COMP_4_5_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_4_5_6_IRQHandler + B COMP_4_5_6_IRQHandler + + PUBWEAK COMP7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP7_IRQHandler + B COMP7_IRQHandler + + PUBWEAK RSRAM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RSRAM_IRQHandler + B RSRAM_IRQHandler + + + END + diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/startup/startup_n32g45x_gcc.S b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/startup/startup_n32g45x_gcc.S new file mode 100755 index 0000000000..b09b7a2ee2 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/startup/startup_n32g45x_gcc.S @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file startup_n32g45x.S + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ +/* bl __libc_init_array */ +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1, ADC2 */ + .word USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word ADC3_4_IRQHandler /* ADC3 & ADC4 */ + .word XFMC_IRQHandler /* XFMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel5 */ + .word ETH_IRQHandler /* Ethernet global interrupt */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word QSPI_IRQHandler /* QSPI */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel7 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word I2C4_EV_IRQHandler /* I2C4 event */ + .word I2C4_ER_IRQHandler /* I2C4 error */ + .word UART6_IRQHandler /* UART6 */ + .word UART7_IRQHandler /* UART7 */ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel8 */ + .word DVP_IRQHandler /* DVP */ + .word SAC_IRQHandler /* SAC */ + .word MMU_IRQHandler /* MMU */ + .word TSC_IRQHandler /* TSC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_4_IRQHandler + .thumb_set ADC3_4_IRQHandler,Default_Handler + + .weak XFMC_IRQHandler + .thumb_set XFMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak QSPI_IRQHandler + .thumb_set QSPI_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak UART6_IRQHandler + .thumb_set UART6_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak DMA1_Channel8_IRQHandler + .thumb_set DMA1_Channel8_IRQHandler,Default_Handler + + .weak DMA2_Channel8_IRQHandler + .thumb_set DMA2_Channel8_IRQHandler,Default_Handler + + .weak DVP_IRQHandler + .thumb_set DVP_IRQHandler,Default_Handler + + .weak SAC_IRQHandler + .thumb_set SAC_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/system_n32g45x.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/system_n32g45x.c new file mode 100644 index 0000000000..f92d3b6b8a --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/system_n32g45x.c @@ -0,0 +1,421 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file system_n32g45x.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x.h" + +/* Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your + device's maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume + that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to + drive the System clock. If you are using different crystal you have to adapt + those functions accordingly. + */ + +#define SYSCLK_USE_HSI 0 +#define SYSCLK_USE_HSE 1 +#define SYSCLK_USE_HSI_PLL 2 +#define SYSCLK_USE_HSE_PLL 3 + +#ifndef SYSCLK_FREQ +#define SYSCLK_FREQ 144000000 +#endif + +#ifndef SYSCLK_SRC +#define SYSCLK_SRC SYSCLK_USE_HSE_PLL +#endif + +#if SYSCLK_SRC == SYSCLK_USE_HSI + +#if SYSCLK_FREQ != HSI_VALUE +#error SYSCL_FREQ must be set to HSI_VALUE +#endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSE + +#ifndef HSE_VALUE +#error HSE_VALUE must be defined! +#endif + +#if SYSCLK_FREQ != HSE_VALUE +#error SYSCL_FREQ must be set to HSE_VALUE +#endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL + +#if (SYSCLK_FREQ % (HSI_VALUE / 2) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \ + && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32) + +#define PLLSRC_DIV 2 +#define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2)) + +#else +#error Cannot make a PLL multiply factor to SYSCLK_FREQ. +#endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL + +#ifndef HSE_VALUE +#error HSE_VALUE must be defined! +#endif + +#if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \ + && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32) + +#define PLLSRC_DIV 2 +#define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2)) + +#elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32) + +#define PLLSRC_DIV 1 +#define PLL_MUL (SYSCLK_FREQ / HSE_VALUE) + +#else +#error Cannot make a PLL multiply factor to SYSCLK_FREQ. +#endif + +#else +#error wrong value for SYSCLK_SRC +#endif + +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ + +/******************************************************************************* + * Clock Definitions + *******************************************************************************/ +uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */ + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +static void SetSysClock(void); + +#ifdef DATA_IN_ExtSRAM +static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + */ +void SystemInit(void) +{ + /* FPU settings + * ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSIEN bit */ + RCC->CTRL |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ + RCC->CFG &= (uint32_t)0xF8FFC000; + + /* Reset HSEON, CLKSSEN and PLLEN bits */ + RCC->CTRL &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CTRL &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES/OTGFSPRE bits */ + RCC->CFG &= (uint32_t)0xF700FFFF; + + /* Reset CFG2 register */ + RCC->CFG2 = 0x00000000; + + /* Reset CFG3 register */ + RCC->CFG3 = 0x00000000; + + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT = 0x009F0000; + + /* Enable ex mode */ + RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN; + PWR->CTRL3 |= 0x00000001; + RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN); + + /* Enable ICACHE and Prefetch Buffer */ + FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN); + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or + * configure other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any + * configuration based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the + * HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the + * HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the + * HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in n32g45x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in N32G45X.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to + * ensure that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using + * fractional value for HSE crystal. + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + + /* Get SYSCLK source + * -------------------------------------------------------*/ + tmp = RCC->CFG & RCC_CFG_SCLKSTS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor + * ----------------------*/ + pllmull = RCC->CFG & RCC_CFG_PLLMULFCT; + pllsource = RCC->CFG & RCC_CFG_PLLSRC; + + if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0) + { + pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0 + } + else + { + pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1 + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET) + { /* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 + * prescalers. + */ +static void SetSysClock(void) +{ + uint32_t rcc_cfgr = 0; + bool HSEStatus = 0; + uint32_t StartUpCounter = 0; + +#if SYSCLK_SRC == SYSCLK_USE_HSE || SYSCLK_SRC == SYSCLK_USE_HSE_PLL + + /* Enable HSE */ + RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF; + StartUpCounter++; + } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET); + if (!HSEStatus) + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error */ + SystemCoreClock = HSI_VALUE; + return; + } +#endif + + /* Flash wait state + 0: HCLK <= 32M + 1: HCLK <= 64M + 2: HCLK <= 96M + 3: HCLK <= 128M + 4: HCLK <= 144M + */ + FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY); + FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000); + + /* HCLK = SYSCLK */ + RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1; + + /* PCLK2 max 72M */ + if (SYSCLK_FREQ > 72000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2; + } + else + { + RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1; + } + + /* PCLK1 max 36M */ + if (SYSCLK_FREQ > 72000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4; + } + else if (SYSCLK_FREQ > 36000000) + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2; + } + else + { + RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1; + } + +#if SYSCLK_SRC == SYSCLK_USE_HSE + /* Select HSE as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04) + { + } +#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL + + /* clear bits */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT)); + + /* set PLL source */ + rcc_cfgr = RCC->CFG; + rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE); + +#if SYSCLK_SRC == SYSCLK_USE_HSE_PLL + rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); +#endif + + /* set PLL multiply factor */ +#if PLL_MUL <= 16 + rcc_cfgr |= (PLL_MUL - 2) << 18; +#else + rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27); +#endif + + RCC->CFG = rcc_cfgr; + + /* Enable PLL */ + RCC->CTRL |= RCC_CTRL_PLLEN; + + /* Wait till PLL is ready */ + while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW)); + RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08) + { + } +#endif +} diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/system_n32g45x.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/system_n32g45x.h new file mode 100644 index 0000000000..b94db8ba4c --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/system_n32g45x.h @@ -0,0 +1,59 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file system_n32g45x.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __SYSTEM_N32G45X_H__ +#define __SYSTEM_N32G45X_H__ + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup N32G45X_System + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_N32G45X_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/SConscript b/bsp/n32g452xx/Libraries/N32_Std_Driver/SConscript new file mode 100755 index 0000000000..4d5ff3f778 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/SConscript @@ -0,0 +1,54 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +# src = Split(""" +# n32g45x_std_periph_driver/src/misc.c +# n32g45x_std_periph_driver/src/n32g45x_adc.c +# n32g45x_std_periph_driver/src/n32g45x_bkp.c +# n32g45x_std_periph_driver/src/n32g45x_can.c +# n32g45x_std_periph_driver/src/n32g45x_comp.c +# n32g45x_std_periph_driver/src/n32g45x_crc.c +# n32g45x_std_periph_driver/src/n32g45x_dac.c +# n32g45x_std_periph_driver/src/n32g45x_dbg.c +# n32g45x_std_periph_driver/src/n32g45x_dma.c +# n32g45x_std_periph_driver/src/n32g45x_dvp.c +# n32g45x_std_periph_driver/src/n32g45x_eth.c +# n32g45x_std_periph_driver/src/n32g45x_exti.c +# n32g45x_std_periph_driver/src/n32g45x_flash.c +# n32g45x_std_periph_driver/src/n32g45x_gpio.c +# n32g45x_std_periph_driver/src/n32g45x_i2c.c +# n32g45x_std_periph_driver/src/n32g45x_iwdg.c +# n32g45x_std_periph_driver/src/n32g45x_opamp.c +# n32g45x_std_periph_driver/src/n32g45x_pwr.c +# n32g45x_std_periph_driver/src/n32g45x_qspi.c +# n32g45x_std_periph_driver/src/n32g45x_rcc.c +# n32g45x_std_periph_driver/src/n32g45x_rtc.c +# n32g45x_std_periph_driver/src/n32g45x_sdio.c +# n32g45x_std_periph_driver/src/n32g45x_spi.c +# n32g45x_std_periph_driver/src/n32g45x_tim.c +# n32g45x_std_periph_driver/src/n32g45x_tsc.c +# n32g45x_std_periph_driver/src/n32g45x_usart.c +# n32g45x_std_periph_driver/src/n32g45x_wwdg.c +# n32g45x_std_periph_driver/src/n32g45x_xfmc.c +# """) +src = Glob('n32g45x_std_periph_driver/src/*.c') +src += [cwd + '/CMSIS/device/system_n32g45x.c'] + +path = [ + cwd + '/CMSIS/core', + cwd + '/CMSIS/device', + cwd + '/n32g45x_std_periph_driver/inc',] + +if GetDepend(['RT_USING_BSP_USB']): + path += [cwd + '/n32g45x_usbfs_driver/inc'] + src += [cwd + '/n32g45x_usbfs_driver/src'] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_aes.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_aes.h new file mode 100644 index 0000000000..3c6210773b --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_aes.h @@ -0,0 +1,126 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_aes.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_AES_H__ +#define __N32G45X_AES_H__ + +#include +/** @addtogroup N32G45X_Algorithm_Library + * @{ + */ + +/** @addtogroup AES + * @brief AES symmetrical cipher algorithm + * @{ + */ + +#define AES_ECB (0x11111111) +#define AES_CBC (0x22222222) +#define AES_CTR (0x33333333) + +#define AES_ENC (0x44444444) +#define AES_DEC (0x55555555) + +enum +{ + AES_Crypto_OK = 0x0, //AES opreation success + AES_Init_OK = 0x0, //AES Init opreation success + AES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC nor CTR) + AES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption) + AES_Crypto_ParaNull, // the part of input(output/iv) Null + AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero; + //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError + + AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError + AES_Crypto_UnInitError, //AES uninitialized +}; + +typedef struct +{ + uint32_t *in; // the part of input to be encrypted or decrypted + uint32_t *iv; // the part of initial vector + uint32_t *out; // the part of out + uint32_t *key; // the part of key + uint32_t keyWordLen; // the length(by word) of key + uint32_t inWordLen; // the length(by word) of plaintext or cipher + uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt + uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR +}AES_PARM; + + /** + * @brief AES_Init + * @return AES_Init_OK, AES Init success; othets: AES Init fail + * @note + */ + +uint32_t AES_Init(AES_PARM *parm); + +/** + * @brief AES crypto + * @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h + * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation) + * @note 1.Please refer to the demo in user guidance before using this function + * 2.Input and output can be the same buffer + * 3. IV can be NULL when ECB mode + * 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero; + * if Working mode is CTR,the length of input message cannot be zero; + * 5. If the input is in byte, make sure align by word. + */ +uint32_t AES_Crypto(AES_PARM *parm); + +/** + * @brief AES close + * @return none + * @note if you want to close AES algorithm, this function can be recalled. + */ +void AES_Close(void); + +/** + * @brief Get AES lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get AES lib information + */ +void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version); + + + + +#endif + + diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_algo_common.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_algo_common.h new file mode 100644 index 0000000000..2c8901426d --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_algo_common.h @@ -0,0 +1,154 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_algo_common.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_ALGO_COMMON_H__ +#define __N32G45X_ALGO_COMMON_H__ + +#include +/** @addtogroup N32G45X_Algorithm_Library + * @{ + */ +enum{ + Cpy_OK=0,//copy success + SetZero_OK = 0,//set zero success + XOR_OK = 0, //XOR success + Reverse_OK = 0, //Reverse success + Cmp_EQUAL = 0, //Two big number are equal + Cmp_UNEQUAL = 1, //Two big number are not equal + +}; + +/** + * @brief disturb the sequence order + * @param[in] order pointer to the sequence to be disturbed + * @param[in] rand pointer to random number + * @param[in] the length of order + * @return RandomSort_OK: disturb order success; Others: disturb order fail; + * @note + */ +uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len); + +/** + * @brief Copy data by byte + * @param[in] dst pointer to destination data + * @param[in] src pointer to source data + * @param[in] byte length + * @return Cpy_OK: success; others: fail. + * @note 1. dst and src cannot be same + */ +uint32_t Cpy_U8(uint8_t *dst, uint8_t *src, uint32_t byteLen); + +/** + * @brief Copy data by word + * @param[in] dst pointer to destination data + * @param[in] src pointer to source data + * @param[in] word length + * @return Cpy_OK: success; others: fail. + * @note 1. dst and src must be aligned by word + */ +uint32_t Cpy_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen); + + /** + * @brief XOR + * @param[in] a pointer to one data to be XORed + * @param[in] b pointer to another data to be XORed + * @param[in] the length of order + * @return XOR_OK: operation success; Others: operation fail; + * @note + */ +uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen); + + /** + * @brief XORed two u32 arrays + * @param[in] a pointer to one data to be XORed + * @param[in] b pointer to another data to be XORed + * @param[in] the length of order + * @return XOR_OK: operation success; Others: operation fail; + * @note + */ +uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen); + +/** + * @brief set zero by byte + * @param[in] dst pointer to the address to be set zero + * @param[in] byte length + * @return SetZero_OK: success; others: fail. + * @note + */ +uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen); + +/** + * @brief set zero by word + * @param[in] dst pointer to the address to be set zero + * @param[in] word length + * @return SetZero_OK: success; others: fail. + * @note + */ +uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen); + +/** + * @brief reverse byte order of every word, the words stay the same + * @param[in] dst pointer to the destination address + * @param[in] src pointer to the source address + * @param[in] word length + * @return Reverse_OK: success; others: fail. + * @note 1.dst and src can be same + */ +uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen); + +/** + * @brief compare two big number + * @param[in] a pointer to one big number + * @param[in] word length of a + * @param[in] b pointer to another big number + * @param[in] word length of b + * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b. + * + */ +int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen); + +/** + * @brief compare two big number + * @param[in] a pointer to one big number + * @param[in] word length of a + * @param[in] b pointer to another big number + * @param[in] word length of b + * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b. + * + */ +int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen); + + +#endif + diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_des.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_des.h new file mode 100644 index 0000000000..289d33bd44 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_des.h @@ -0,0 +1,121 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_des.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_DES_H__ +#define __N32G45X_DES_H__ + +#include + +/** @addtogroup N32G45X_Algorithm_Library + * @{ + */ + +/** @addtogroup DES + * @brief DES symmetrical cipher algorithm + * @{ + */ +#define DES_ECB (0x11111111) +#define DES_CBC (0x22222222) + + +#define DES_ENC (0x33333333) +#define DES_DEC (0x44444444) + +#define DES_KEY (0x55555555) +#define TDES_2KEY (0x66666666) +#define TDES_3KEY (0x77777777) + +enum DES +{ + DES_Crypto_OK = 0x0, // DES/TDES opreation success + DES_Init_OK = 0x0, // DES/TDES Init opreation success + DES_Crypto_ModeError = 0x5a5a5a5a, // Working mode error(Neither ECB nor CBC) + DES_Crypto_EnOrDeError, // En&De error(Neither encryption nor decryption) + DES_Crypto_ParaNull, // the part of input(output/iv) Null + DES_Crypto_LengthError, // the length of input message must be 2 times and cannot be zero + DES_Crypto_KeyError, // keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY) + DES_Crypto_UnInitError, // DES/TDES uninitialized +}; + +typedef struct +{ + uint32_t* in; // the part of input to be encrypted or decrypted + uint32_t* iv; // the part of initial vector + uint32_t* out; // the part of out + uint32_t* key; // the part of key + uint32_t inWordLen; // the length(by word) of plaintext or cipher + uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt + uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC + uint32_t keyMode; // TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key +} DES_PARM; + + /** + * @brief DES_Init + * @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail + * @note + */ +uint32_t DES_Init(DES_PARM* parm); + +/** + * @brief DES crypto + * @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h + * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation) + * @note 1.Please refer to the demo in user guidance before using this function + * 2.Input and output can be the same buffer + * 3. IV can be NULL when ECB mode + * 4. The word lengrh of message must be as times as 2. + * 5. If the input is in byte, make sure align by word. + */ +uint32_t DES_Crypto(DES_PARM* parm); + +/** + * @brief DES close + * @return none + * @note if you want to close DES algorithm, this function can be recalled. + */ +void DES_Close(void); + +/** + * @brief Get DES/TDES lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get DES/TDES lib information + */ +void DES_Version(uint8_t* type, uint8_t* customer, uint8_t date[3], uint8_t* version); + +#endif diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_hash.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_hash.h new file mode 100644 index 0000000000..19ac4ebdbe --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_hash.h @@ -0,0 +1,218 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_hash.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_HASH_H__ +#define __N32G45X_HASH_H__ + +#include +/** @addtogroup N32G45X_Algorithm_Library + * @{ + */ + +/** @addtogroup HASH + * @brief Message digest algorithms + * @{ + */ +#define ALG_SHA1 (uint16_t)(0x0004) +#define ALG_SHA224 (uint16_t)(0x000A) +#define ALG_SHA256 (uint16_t)(0x000B) +#define ALG_MD5 (uint16_t)(0x000C) +#define ALG_SM3 (uint16_t)(0x0012) + +enum +{ + HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV + HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV + HASH_Init_OK = 0,//hash init success + HASH_Start_OK = 0,//hash update success + HASH_Update_OK = 0,//hash update success + HASH_Complete_OK = 0,//hash complete success + HASH_Close_OK = 0,//hash close success + HASH_ByteLenPlus_OK = 0,//byte length plus success + HASH_PadMsg_OK = 0,//message padding success + HASH_ProcMsgBuf_OK = 0, //message processing success + SHA1_Hash_OK = 0,//sha1 operation success + SM3_Hash_OK = 0,//sm3 operation success + SHA224_Hash_OK = 0,//sha224 operation success + SHA256_Hash_OK = 0,//sha256 operation success + MD5_Hash_OK = 0,//MD5 operation success + + HASH_Init_ERROR = 0x01044400,//hash init error + HASH_Start_ERROR, //hash start error + HASH_Update_ERROR, //hash update error + HASH_ByteLenPlus_ERROR,//hash byte plus error +}; + +typedef struct _HASH_CTX_ HASH_CTX; + +typedef struct +{ + const uint16_t HashAlgID;//choice hash algorithm + const uint32_t * const K, KLen;//K and word length of K + const uint32_t * const IV, IVLen;//IV and word length of IV + const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers + const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block + const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest + const uint32_t Cycle; //interation times + uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer + uint32_t (* const PadMsg)(HASH_CTX *); //function pointer +}HASH_ALG; + +typedef struct _HASH_CTX_ +{ + const HASH_ALG *hashAlg;//pointer to HASH_ALG + uint32_t sequence; // TRUE if the IV should be saved + uint32_t IV[16]; + uint32_t msgByteLen[4]; + uint8_t msgBuf[128+4]; + uint32_t msgIdx; +}HASH_CTX; + +extern const HASH_ALG HASH_ALG_SHA1[1]; +extern const HASH_ALG HASH_ALG_SHA224[1]; +extern const HASH_ALG HASH_ALG_SHA256[1]; +extern const HASH_ALG HASH_ALG_MD5[1]; +extern const HASH_ALG HASH_ALG_SM3[1]; + +/** + * @brief Hash init + * @param[in] ctx pointer to HASH_CTX struct + * @return HASH_Init_OK, Hash init success; othets: Hash init fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t HASH_Init(HASH_CTX *ctx); + +/** + * @brief Hash start + * @param[in] ctx pointer to HASH_CTX struct + * @return HASH_Start_OK, Hash start success; othets: Hash start fail + * @note 1.Please refer to the demo in user guidance before using this function + * 2.HASH_Init() should be recalled before use this function + */ +uint32_t HASH_Start(HASH_CTX *ctx); + +/** + * @brief Hash update + * @param[in] ctx pointer to HASH_CTX struct + * @param[in] in pointer to message + * @param[out] out pointer tohash result,digest + * @return HASH_Update_OK, Hash update success; othets: Hash update fail + * @note 1.Please refer to the demo in user guidance before using this function + * 2.HASH_Init() and HASH_Start() should be recalled before use this function + */ +uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen); + +/** + * @brief Hash complete + * @param[in] ctx pointer to HASH_CTX struct + * @param[out] out pointer tohash result,digest + * @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail + * @note 1.Please refer to the demo in user guidance before using this function + * 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function + */ +uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out); + +/** + * @brief Hash close + * @return HASH_Close_OK, Hash close success; othets: Hash close fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t HASH_Close(void); + +/** + * @brief SM3 Hash for 256bits digest + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[out] out pointer tohash result,digest + * @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + + +/** + * @brief SHA1 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[out] out pointer tohash result,digest + * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + +/** + * @brief SHA224 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[out] out pointer tohash result,digest + * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + + +/** + * @brief SHA256 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[out] out pointer tohash result,digest + * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + +/** + * @brief MD5 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[in] out pointer tohash result,digest + * @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + +/** + * @brief Get HASH lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get RSA lib information + */ +void HASH_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version); + + +#endif diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_rng.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_rng.h new file mode 100644 index 0000000000..0d4ee0c1df --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_rng.h @@ -0,0 +1,93 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_rng.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_RNG_H__ +#define __N32G45X_RNG_H__ + +#include + +/** @addtogroup N32G45X_Algorithm_Library + * @{ + */ + +/** @addtogroup RNG + * @brief Random number generator + * @{ + */ + + + +enum{ + RNG_OK = 0x5a5a5a5a, + LENError = 0x311ECF50, //RNG generation of key length error + ADDRNULL = 0x7A9DB86C, // This address is empty +}; + + +//u32 RNG_init(void); +/** + * @brief Get pseudo random number + * @param[out] rand pointer to random number + * @param[in] the wordlen of random number + * @param[in] the seed, can be NULL + * @return RNG_OK:get random number success; othets: get random number fail + * @note + */ +uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]); + + +/** + * @brief Get true random number + * @param[out] rand pointer to random number + * @param[in] the wordlen of random number + * @return RNG_OK:get random number success; othets: get random number fail + * @note + */ +uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen); + +/** + * @brief Get RNG lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get RSA lib information + */ +void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version); + +#endif + + diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/misc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/misc.h new file mode 100644 index 0000000000..543e4d1533 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/misc.h @@ -0,0 +1,229 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file misc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __MISC_H__ +#define __MISC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @addtogroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete N32G45X Devices IRQ Channels list, please + refer to n32g45x.h file) */ + + uint8_t + NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitType; + +/** + * @} + */ + +/** @addtogroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption +priority | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption +priority | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption +priority | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption +priority | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption +priority | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Constants + * @{ + */ + +/** @addtogroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @addtogroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @addtogroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 \ + ((uint32_t)0x700) /*!< 0 bits for pre-emption priority \ + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 \ + ((uint32_t)0x600) /*!< 1 bits for pre-emption priority \ + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 \ + ((uint32_t)0x500) /*!< 2 bits for pre-emption priority \ + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 \ + ((uint32_t)0x400) /*!< 3 bits for pre-emption priority \ + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 \ + ((uint32_t)0x300) /*!< 4 bits for pre-emption priority \ + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) \ + (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \ + || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @addtogroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) \ + (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitType* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_adc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_adc.h new file mode 100644 index 0000000000..f2ca17812b --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_adc.h @@ -0,0 +1,657 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_adc.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_ADC_H__ +#define __N32G45X_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" +#include + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ +#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x20)) +#define _EnVref1p2() do{VREF1P2_CTRL|=(1<<10);}while(0); +#define _DisVref1p2() do{VREF1P2_CTRL&=~(1<<10);}while(0); +/** @addtogroup ADC + * @{ + */ + +/** @addtogroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ +typedef struct +{ + uint32_t WorkMode; /*!< Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref + ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitType; +/** + * @} + */ + +/** @addtogroup ADC_Exported_Constants + * @{ + */ + +#define IsAdcModule(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC2) || ((PERIPH) == ADC3) || ((PERIPH) == ADC4)) + +#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC3)) + +/** @addtogroup ADC_mode + * @{ + */ + +#define ADC_WORKMODE_INDEPENDENT ((uint32_t)0x00000000) +#define ADC_WORKMODE_SEQ_INJECT_SIMULT ((uint32_t)0x00010000) +#define ADC_WORKMODE_SEQ_SIMULT_ALTER_TRIG ((uint32_t)0x00020000) +#define ADC_WORKMODE_INJ_SIMULT_FAST_INTERL ((uint32_t)0x00030000) +#define ADC_WORKMODE_INT_SIMULT_SLOW_INTERL ((uint32_t)0x00040000) +#define ADC_WORKMODE_INJ_SIMULT ((uint32_t)0x00050000) +#define ADC_WORKMODE_REG_SIMULT ((uint32_t)0x00060000) +#define ADC_WORKMODE_FAST_INTERL ((uint32_t)0x00070000) +#define ADC_WORKMODE_SLOW_INTERL ((uint32_t)0x00080000) +#define ADC_WORKMODE_ALTER_TRIG ((uint32_t)0x00090000) + +#define IsAdcWorkMode(MODE) \ + (((MODE) == ADC_WORKMODE_INDEPENDENT) || ((MODE) == ADC_WORKMODE_SEQ_INJECT_SIMULT) \ + || ((MODE) == ADC_WORKMODE_SEQ_SIMULT_ALTER_TRIG) || ((MODE) == ADC_WORKMODE_INJ_SIMULT_FAST_INTERL) \ + || ((MODE) == ADC_WORKMODE_INT_SIMULT_SLOW_INTERL) || ((MODE) == ADC_WORKMODE_INJ_SIMULT) \ + || ((MODE) == ADC_WORKMODE_REG_SIMULT) || ((MODE) == ADC_WORKMODE_FAST_INTERL) \ + || ((MODE) == ADC_WORKMODE_SLOW_INTERL) || ((MODE) == ADC_WORKMODE_ALTER_TRIG)) +/** + * @} + */ + +/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ + +#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 , ADC3 and ADC4 */ +#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 , ADC3 and ADC4 */ + +#define ADC_EXT_TRIGCONV_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIGCONV_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIGCONV_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIGCONV_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIGCONV_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIGCONV_EXT_INT10_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 and ADC4 */ + +#define IsAdcExtTrig(REGTRIG) \ + (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC3) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T8_TRGO) \ + || ((REGTRIG) == ADC_EXT_TRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT10_T5_CC3)) +/** + * @} + */ + +/** @addtogroup ADC_data_align + * @{ + */ + +#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000) +#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800) +#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L)) +/** + * @} + */ + +/** @addtogroup ADC_channels + * @{ + */ + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1 ((uint8_t)0x01) +#define ADC_CH_2 ((uint8_t)0x02) +#define ADC_CH_3 ((uint8_t)0x03) +#define ADC_CH_4 ((uint8_t)0x04) +#define ADC_CH_5 ((uint8_t)0x05) +#define ADC_CH_6 ((uint8_t)0x06) +#define ADC_CH_7 ((uint8_t)0x07) +#define ADC_CH_8 ((uint8_t)0x08) +#define ADC_CH_9 ((uint8_t)0x09) +#define ADC_CH_10 ((uint8_t)0x0A) +#define ADC_CH_11 ((uint8_t)0x0B) +#define ADC_CH_12 ((uint8_t)0x0C) +#define ADC_CH_13 ((uint8_t)0x0D) +#define ADC_CH_14 ((uint8_t)0x0E) +#define ADC_CH_15 ((uint8_t)0x0F) +#define ADC_CH_16 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) + +#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_16) +#define ADC_CH_INT_VREF ((uint8_t)ADC_CH_18) + +#define IsAdcChannel(CHANNEL) \ + (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \ + || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \ + || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \ + || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \ + || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18)) +/** + * @} + */ + +/** @addtogroup ADC_sampling_time + * @{ + */ + +#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00) +#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01) +#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02) +#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03) +#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04) +#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05) +#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06) +#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07) +#define IsAdcSampleTime(TIME) \ + (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \ + || ((TIME) == ADC_SAMP_TIME_239CYCLES5)) +/** + * @} + */ + +/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ +#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ + +#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2, ADC3 and ADC4 */ +#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2, ADC3 and ADC4 */ +#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000) /*!< For ADC1, ADC2, ADC3 and ADC4 */ + +#define ADC_EXT_TRIG_INJ_CONV_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIG_INJ_CONV_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIG_INJ_CONV_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIG_INJ_CONV_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 and ADC4 */ +#define ADC_EXT_TRIG_INJ_CONV_EXT_INT14_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 and ADC4 */ + +#define IsAdcExtInjTrig(INJTRIG) \ + (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_CC3) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T8_CC2) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T5_TRGO) \ + || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT14_T5_CC4)) +/** + * @} + */ + +/** @addtogroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_INJ_CH_1 ((uint8_t)0x14) +#define ADC_INJ_CH_2 ((uint8_t)0x18) +#define ADC_INJ_CH_3 ((uint8_t)0x1C) +#define ADC_INJ_CH_4 ((uint8_t)0x20) +#define IsAdcInjCh(CHANNEL) \ + (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \ + || ((CHANNEL) == ADC_INJ_CH_4)) +/** + * @} + */ + +/** @addtogroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200) +#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200) +#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200) +#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000) +#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000) +#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000) +#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000) + +#define IsAdcAnalogWatchdog(WATCHDOG) \ + (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \ + || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE)) +/** + * @} + */ + +/** @addtogroup ADC_interrupts_definition + * @{ + */ + +#define ADC_INT_ENDC ((uint16_t)0x0220) +#define ADC_INT_AWD ((uint16_t)0x0140) +#define ADC_INT_JENDC ((uint16_t)0x0480) + +#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC)) +/** + * @} + */ + +/** @addtogroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWDG ((uint8_t)0x01) +#define ADC_FLAG_ENDC ((uint8_t)0x02) +#define ADC_FLAG_JENDC ((uint8_t)0x04) +#define ADC_FLAG_JSTR ((uint8_t)0x08) +#define ADC_FLAG_STR ((uint8_t)0x10) +#define ADC_FLAG_EOC_ANY ((uint8_t)0x20) +#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40) +#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00)) +#define IsAdcGetFlag(FLAG) \ + (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \ + || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY)) +/** + * @} + */ + +/** @addtogroup ADC_thresholds + * @{ + */ +#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + +/** @addtogroup ADC_injected_offset + * @{ + */ + +#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @addtogroup ADC_injected_length + * @{ + */ + +#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @addtogroup ADC_injected_rank + * @{ + */ + +#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + +/** @addtogroup ADC_regular_length + * @{ + */ + +#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @addtogroup ADC_regular_rank + * @{ + */ + +#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @addtogroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/************************** fllowing bit seg in ex register **********************/ +/**@addtogroup ADC_channels_ex_style + * @{ + */ +#define ADC1_Channel_01_PA0 ((uint8_t)0x01) +#define ADC1_Channel_02_PA1 ((uint8_t)0x02) +#define ADC1_Channel_03_PA6 ((uint8_t)0x03) +#define ADC1_Channel_04_PA3 ((uint8_t)0x04) +#define ADC1_Channel_05_PF4 ((uint8_t)0x05) +#define ADC1_Channel_06_PC0 ((uint8_t)0x06) +#define ADC1_Channel_07_PC1 ((uint8_t)0x07) +#define ADC1_Channel_08_PC2 ((uint8_t)0x08) +#define ADC1_Channel_09_PC3 ((uint8_t)0x09) +#define ADC1_Channel_10_PF2 ((uint8_t)0x0A) +#define ADC1_Channel_11_PA2 ((uint8_t)0x0B) + +#define ADC2_Channel_01_PA4 ((uint8_t)0x01) +#define ADC2_Channel_02_PA5 ((uint8_t)0x02) +#define ADC2_Channel_03_PB1 ((uint8_t)0x03) +#define ADC2_Channel_04_PA7 ((uint8_t)0x04) +#define ADC2_Channel_05_PC4 ((uint8_t)0x05) +#define ADC2_Channel_06_PC0 ((uint8_t)0x06) +#define ADC2_Channel_07_PC1 ((uint8_t)0x07) +#define ADC2_Channel_08_PC2 ((uint8_t)0x08) +#define ADC2_Channel_09_PC3 ((uint8_t)0x09) +#define ADC2_Channel_10_PF2 ((uint8_t)0x0A) +#define ADC2_Channel_11_PA2 ((uint8_t)0x0B) +#define ADC2_Channel_12_PC5 ((uint8_t)0x0C) +#define ADC2_Channel_13_PB2 ((uint8_t)0x0D) + +#define ADC3_Channel_01_PB11 ((uint8_t)0x01) +#define ADC3_Channel_02_PE9 ((uint8_t)0x02) +#define ADC3_Channel_03_PE13 ((uint8_t)0x03) +#define ADC3_Channel_04_PE12 ((uint8_t)0x04) +#define ADC3_Channel_05_PB13 ((uint8_t)0x05) +#define ADC3_Channel_06_PE8 ((uint8_t)0x06) +#define ADC3_Channel_07_PD10 ((uint8_t)0x07) +#define ADC3_Channel_08_PD11 ((uint8_t)0x08) +#define ADC3_Channel_09_PD12 ((uint8_t)0x09) +#define ADC3_Channel_10_PD13 ((uint8_t)0x0A) +#define ADC3_Channel_11_PD14 ((uint8_t)0x0B) +#define ADC3_Channel_12_PB0 ((uint8_t)0x0C) +#define ADC3_Channel_13_PE7 ((uint8_t)0x0D) +#define ADC3_Channel_14_PE10 ((uint8_t)0x0E) +#define ADC3_Channel_15_PE11 ((uint8_t)0x0F) + +#define ADC4_Channel_01_PE14 ((uint8_t)0x01) +#define ADC4_Channel_02_PE15 ((uint8_t)0x02) +#define ADC4_Channel_03_PB12 ((uint8_t)0x03) +#define ADC4_Channel_04_PB14 ((uint8_t)0x04) +#define ADC4_Channel_05_PB15 ((uint8_t)0x05) +#define ADC4_Channel_06_PE8 ((uint8_t)0x06) +#define ADC4_Channel_07_PD10 ((uint8_t)0x07) +#define ADC4_Channel_08_PD11 ((uint8_t)0x08) +#define ADC4_Channel_09_PD12 ((uint8_t)0x09) +#define ADC4_Channel_10_PD13 ((uint8_t)0x0A) +#define ADC4_Channel_11_PD14 ((uint8_t)0x0B) +#define ADC4_Channel_12_PD8 ((uint8_t)0x0C) +#define ADC4_Channel_13_PD9 ((uint8_t)0x0D) + +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1 ((uint8_t)0x01) +#define ADC_CH_2 ((uint8_t)0x02) +#define ADC_CH_3 ((uint8_t)0x03) +#define ADC_CH_4 ((uint8_t)0x04) +#define ADC_CH_5 ((uint8_t)0x05) +#define ADC_CH_6 ((uint8_t)0x06) +#define ADC_CH_7 ((uint8_t)0x07) +#define ADC_CH_8 ((uint8_t)0x08) +#define ADC_CH_9 ((uint8_t)0x09) +#define ADC_CH_10 ((uint8_t)0x0A) +#define ADC_CH_11 ((uint8_t)0x0B) +#define ADC_CH_12 ((uint8_t)0x0C) +#define ADC_CH_13 ((uint8_t)0x0D) +#define ADC_CH_14 ((uint8_t)0x0E) +#define ADC_CH_15 ((uint8_t)0x0F) +#define ADC_CH_16 ((uint8_t)0x10) +#define ADC_CH_17 ((uint8_t)0x11) +#define ADC_CH_18 ((uint8_t)0x12) +/** + * @} + */ + +/**@addtogroup ADC_dif_sel_ch_definition + * @{ + */ +#define ADC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFE) +#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002) +#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004) +#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008) +#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010) +#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020) +#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040) +#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080) +#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100) +#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200) +#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400) +#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800) +#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000) +#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000) +#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000) +#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000) +#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000) +#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000) +#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000) +/** + * @} + */ + +/**@addtogroup ADC_calfact_definition + * @{ + */ +#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16) +#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0) +/** + * @} + */ + +/**@addtogroup ADC_ctrl3_definition + * @{ + */ +#define ADC_CTRL3_VABTMEN_MSK ((uint32_t)0x01L << 11) +#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10) +#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9) +#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8) +#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7) +#define ADC_CTRL3_PDRDY_MSK ((uint32_t)0x01L << 6) +#define ADC_CTRL3_RDY_MSK ((uint32_t)0x01L << 5) +#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4) +#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3) +#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2) +#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0) +/** + * @} + */ + +/**@addtogroup ADC_sampt3_definition + * @{ + */ +#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3) +/** + * @} + */ + +typedef enum +{ + ADC_CTRL3_CKMOD_AHB = 0, + ADC_CTRL3_CKMOD_PLL = 1, +} ADC_CTRL3_CKMOD; +typedef enum +{ + ADC_CTRL3_RES_12BIT = 3, + ADC_CTRL3_RES_10BIT = 2, + ADC_CTRL3_RES_8BIT = 1, + ADC_CTRL3_RES_6BIT = 0, +} ADC_CTRL3_RES; +typedef struct +{ + FunctionalState VbatMinitEn; + FunctionalState DeepPowerModEn; + FunctionalState JendcIntEn; + FunctionalState EndcIntEn; + ADC_CTRL3_CKMOD ClkMode; + FunctionalState CalAtuoLoadEn; + bool DifModCal; + ADC_CTRL3_RES ResBit; + bool SampSecondStyle; +} ADC_InitTypeEx; +/** + * @} + */ + +/*ADC_SAMPT3 only have samp time and smp18[2:0],samp18 is refint ch, change to row function*/ +/*ADC_IPTST reseverd register ,not to do it*/ + +/**@addtogroup ADC_bit_num_definition + * @{ + */ +#define ADC_RST_BIT_12 ((uint32_t)0x03) +#define ADC_RST_BIT_10 ((uint32_t)0x02) +#define ADC_RST_BIT_8 ((uint32_t)0x01) +#define ADC_RESULT_BIT_6 ((uint32_t)0x00) +/** + * @} + */ + +/** @addtogroup ADC_flags_ex_definition + * @{ + */ +#define ADC_FLAG_RDY ((uint8_t)0x20) +#define ADC_FLAG_PD_RDY ((uint8_t)0x40) +#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_Module* ADCx); +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct); +void ADC_InitStruct(ADC_InitType* ADC_InitStruct); +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd); +void ADC_StartCalibration(ADC_Module* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx); +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx); +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number); +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd); +uint16_t ADC_GetDat(ADC_Module* ADCx); +uint32_t ADC_GetDualModeConversionDat(ADC_Module* ADCx); +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx); +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length); +void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel); +void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel); +void ADC_EnableTempSensorVrefint(FunctionalState Cmd); +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG); +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT); +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT); + +void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx); +void ADC_SetDifChs(ADC_Module* ADCx,uint32_t DifChs); +FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW); +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en); +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum); + +void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_ADC_H__ */ + +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_bkp.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_bkp.h new file mode 100644 index 0000000000..7b47b97337 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_bkp.h @@ -0,0 +1,182 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_bkp.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_BKP_H__ +#define __N32G45X_BKP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @{ + */ + +/** @addtogroup BKP_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup BKP_Exported_Constants + * @{ + */ + +/** @addtogroup Tamper_Pin_active_level + * @{ + */ + +#define BKP_TP_HIGH ((uint16_t)0x0000) +#define BKP_TP_LOW ((uint16_t)0x0001) +#define IS_BKP_TP_LEVEL(LEVEL) (((LEVEL) == BKP_TP_HIGH) || ((LEVEL) == BKP_TP_LOW)) +/** + * @} + */ + +/** @addtogroup Data_Backup_Register + * @{ + */ + +#define BKP_DAT1 ((uint16_t)0x0004) +#define BKP_DAT2 ((uint16_t)0x0008) +#define BKP_DAT3 ((uint16_t)0x000C) +#define BKP_DAT4 ((uint16_t)0x0010) +#define BKP_DAT5 ((uint16_t)0x0014) +#define BKP_DAT6 ((uint16_t)0x0018) +#define BKP_DAT7 ((uint16_t)0x001C) +#define BKP_DAT8 ((uint16_t)0x0020) +#define BKP_DAT9 ((uint16_t)0x0024) +#define BKP_DAT10 ((uint16_t)0x0028) +#define BKP_DAT11 ((uint16_t)0x0040) +#define BKP_DAT12 ((uint16_t)0x0044) +#define BKP_DAT13 ((uint16_t)0x0048) +#define BKP_DAT14 ((uint16_t)0x004C) +#define BKP_DAT15 ((uint16_t)0x0050) +#define BKP_DAT16 ((uint16_t)0x0054) +#define BKP_DAT17 ((uint16_t)0x0058) +#define BKP_DAT18 ((uint16_t)0x005C) +#define BKP_DAT19 ((uint16_t)0x0060) +#define BKP_DAT20 ((uint16_t)0x0064) +#define BKP_DAT21 ((uint16_t)0x0068) +#define BKP_DAT22 ((uint16_t)0x006C) +#define BKP_DAT23 ((uint16_t)0x0070) +#define BKP_DAT24 ((uint16_t)0x0074) +#define BKP_DAT25 ((uint16_t)0x0078) +#define BKP_DAT26 ((uint16_t)0x007C) +#define BKP_DAT27 ((uint16_t)0x0080) +#define BKP_DAT28 ((uint16_t)0x0084) +#define BKP_DAT29 ((uint16_t)0x0088) +#define BKP_DAT30 ((uint16_t)0x008C) +#define BKP_DAT31 ((uint16_t)0x0090) +#define BKP_DAT32 ((uint16_t)0x0094) +#define BKP_DAT33 ((uint16_t)0x0098) +#define BKP_DAT34 ((uint16_t)0x009C) +#define BKP_DAT35 ((uint16_t)0x00A0) +#define BKP_DAT36 ((uint16_t)0x00A4) +#define BKP_DAT37 ((uint16_t)0x00A8) +#define BKP_DAT38 ((uint16_t)0x00AC) +#define BKP_DAT39 ((uint16_t)0x00B0) +#define BKP_DAT40 ((uint16_t)0x00B4) +#define BKP_DAT41 ((uint16_t)0x00B8) +#define BKP_DAT42 ((uint16_t)0x00BC) + +#define IS_BKP_DAT(DAT) \ + (((DAT) == BKP_DAT1) || ((DAT) == BKP_DAT2) || ((DAT) == BKP_DAT3) || ((DAT) == BKP_DAT4) || ((DAT) == BKP_DAT5) \ + || ((DAT) == BKP_DAT6) || ((DAT) == BKP_DAT7) || ((DAT) == BKP_DAT8) || ((DAT) == BKP_DAT9) \ + || ((DAT) == BKP_DAT10) || ((DAT) == BKP_DAT11) || ((DAT) == BKP_DAT12) || ((DAT) == BKP_DAT13) \ + || ((DAT) == BKP_DAT14) || ((DAT) == BKP_DAT15) || ((DAT) == BKP_DAT16) || ((DAT) == BKP_DAT17) \ + || ((DAT) == BKP_DAT18) || ((DAT) == BKP_DAT19) || ((DAT) == BKP_DAT20) || ((DAT) == BKP_DAT21) \ + || ((DAT) == BKP_DAT22) || ((DAT) == BKP_DAT23) || ((DAT) == BKP_DAT24) || ((DAT) == BKP_DAT25) \ + || ((DAT) == BKP_DAT26) || ((DAT) == BKP_DAT27) || ((DAT) == BKP_DAT28) || ((DAT) == BKP_DAT29) \ + || ((DAT) == BKP_DAT30) || ((DAT) == BKP_DAT31) || ((DAT) == BKP_DAT32) || ((DAT) == BKP_DAT33) \ + || ((DAT) == BKP_DAT34) || ((DAT) == BKP_DAT35) || ((DAT) == BKP_DAT36) || ((DAT) == BKP_DAT37) \ + || ((DAT) == BKP_DAT38) || ((DAT) == BKP_DAT39) || ((DAT) == BKP_DAT40) || ((DAT) == BKP_DAT41) \ + || ((DAT) == BKP_DAT42)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup BKP_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup BKP_Exported_Functions + * @{ + */ + +void BKP_DeInit(void); +void BKP_ConfigTPLevel(uint16_t BKP_TamperPinLevel); +void BKP_TPEnable(FunctionalState Cmd); +void BKP_TPIntEnable(FunctionalState Cmd); +void BKP_WriteBkpData(uint16_t BKP_DAT, uint16_t Data); +uint16_t BKP_ReadBkpData(uint16_t BKP_DAT); +FlagStatus BKP_GetTEFlag(void); +void BKP_ClrTEFlag(void); +INTStatus BKP_GetTINTFlag(void); +void BKP_ClrTINTFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_BKP_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_can.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_can.h new file mode 100644 index 0000000000..ef4fc0080d --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_can.h @@ -0,0 +1,671 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_can.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_CAN_H__ +#define __N32G45X_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @addtogroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t OperatingMode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t RSJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t TBS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t TBS2; /*!< Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TTCM; /*!< Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState ABOM; /*!< Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState NART; /*!< Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitType; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t Filter_Scale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState Filter_Act; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitType; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMessage; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMessage; + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Constants + * @{ + */ + +/** @addtogroup CAN_sleep_constants + * @{ + */ + +#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + +/** + * @} + */ + +/** @addtogroup OperatingMode + * @{ + */ + +#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */ +#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) \ + (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \ + || ((MODE) == CAN_Silent_LoopBack_Mode)) +/** + * @} + */ + +/** + * @addtogroup CAN_operating_mode + * @{ + */ +#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */ + +#define IS_CAN_OPERATING_MODE(MODE) \ + (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode)) +/** + * @} + */ + +/** + * @addtogroup CAN_Mode_Status + * @{ + */ + +#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */ + +/** + * @} + */ + +/** @addtogroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_RSJW(SJW) \ + (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq)) +/** + * @} + */ + +/** @addtogroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq) +/** + * @} + */ + +/** @addtogroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq) + +/** + * @} + */ + +/** @addtogroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @addtogroup CAN_filter_number + * @{ + */ +#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13) +/** + * @} + */ + +/** @addtogroup CAN_filter_mode + * @{ + */ + +#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode)) +/** + * @} + */ + +/** @addtogroup CAN_filter_scale + * @{ + */ + +#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale)) + +/** + * @} + */ + +/** @addtogroup CAN_filter_FIFO + * @{ + */ + +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1)) +/** + * @} + */ + +/** @addtogroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @addtogroup CAN_identifier_type + * @{ + */ + +#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id)) +/** + * @} + */ + +/** @addtogroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote)) + +/** + * @} + */ + +/** @addtogroup CAN_transmit_constants + * @{ + */ + +#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @addtogroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */ + +#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @addtogroup CAN_sleep_constants + * @{ + */ + +#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @addtogroup CAN_wake_up_constants + * @{ + */ + +#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** + * @addtogroup CAN_Error_Code_constants + * @{ + */ + +#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */ + +/** + * @} + */ + +/** @addtogroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */ +#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */ +#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */ +#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */ +#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */ +#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) \ + (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \ + || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \ + || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \ + || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \ + || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK)) + +#define IS_CAN_CLEAR_FLAG(FLAG) \ + (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \ + || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \ + || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \ + || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + +/** @addtogroup CAN_interrupts + * @{ + */ + +#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/ +#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/ +#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/ +#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/ +#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/ +#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_INT_RQCPM0 CAN_INT_TME +#define CAN_INT_RQCPM1 CAN_INT_TME +#define CAN_INT_RQCPM2 CAN_INT_TME + +#define IS_CAN_INT(IT) \ + (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \ + || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \ + || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \ + || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK)) + +#define IS_CAN_CLEAR_INT(IT) \ + (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \ + || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \ + || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK)) + +/** + * @} + */ + +/** @addtogroup CAN_Legacy + * @{ + */ +#define CANINITSTSFAILED CAN_InitSTS_Failed +#define CANINITSTSOK CAN_InitSTS_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Standard_Id +#define CAN_ID_EXT CAN_Extended_Id +#define CAN_RTRQ_DATA CAN_RTRQ_Data +#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote +#define CANTXSTSFAILE CAN_TxSTS_Failed +#define CANTXSTSOK CAN_TxSTS_Ok +#define CANTXSTSPENDING CAN_TxSTS_Pending +#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox +#define CANSLEEPFAILED CAN_SLEEP_Failed +#define CANSLEEPOK CAN_SLEEP_Ok +#define CANWKUFAILED CAN_WKU_Failed +#define CANWKUOK CAN_WKU_Ok + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions + * @{ + */ +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_Module* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam); +void CAN1_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct); +void CAN2_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct); +void CAN_InitStruct(CAN_InitType* CAN_InitParam); +void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd); +void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd); + +/* Transmit functions *********************************************************/ +uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage); +uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox); + +/* Receive functions **********************************************************/ +void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage); +void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum); +uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum); + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_EnterSleep(CAN_Module* CANx); +uint8_t CAN_WakeUp(CAN_Module* CANx); + +/* Error management functions *************************************************/ +uint8_t CAN_GetLastErrCode(CAN_Module* CANx); +uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx); +uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd); +FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG); +INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT); +void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_CAN_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_comp.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_comp.h new file mode 100644 index 0000000000..ae6079af33 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_comp.h @@ -0,0 +1,385 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_comp.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_COMP_H__ +#define __N32G45X_COMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" +#include + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @{ + */ + +/** @addtogroup COMP_Exported_Constants + * @{ + */ +typedef enum +{ + COMP1 = 0, + COMP2 = 1, + COMP3 = 2, + COMP4 = 3, + COMP5 = 4, + COMP6 = 5, + COMP7 = 6 +} COMPX; + +// COMPx_CTRL +#define COMP1_CTRL_INPDAC_MASK (0x01L << 18) +#define COMP_CTRL_OUT_MASK (0x01L << 17) +#define COMP_CTRL_BLKING_MASK (0x07L << 14) +typedef enum +{ + COMP_CTRL_BLKING_NO = (0x0L << 14), + COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 14), + COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 14), +} COMP_CTRL_BLKING; +#define COMPx_CTRL_HYST_MASK (0x03L << 12) +typedef enum +{ + COMP_CTRL_HYST_NO = (0x0L << 12), + COMP_CTRL_HYST_LOW = (0x1L << 12), + COMP_CTRL_HYST_MID = (0x2L << 12), + COMP_CTRL_HYST_HIGH = (0x3L << 12), +} COMP_CTRL_HYST; + +#define COMP_POL_MASK (0x01L << 11) +#define COMP_CTRL_OUTSEL_MASK (0x0FL << 7) +typedef enum +{ + COMPX_CTRL_OUTSEL_NC = (0x0L << 7), + // comp1 out trig + COMP1_CTRL_OUTSEL_NC = (0x0L << 7), + COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7), + COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7), + COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7), + COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 7), + COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7), + COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 7), + COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 7), + COMP1_CTRL_OUTSEL_TIM4_IC1 = (0x8L << 7), + COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x9L << 7), + COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7), + COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7), + // comp2 out trig + COMP2_CTRL_OUTSEL_NC = (0x0L << 7), + COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7), + COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7), + COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7), + COMP2_CTRL_OUTSEL_TIM2_IC2 = (0x4L << 7), + COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7), + COMP2_CTRL_OUTSEL_TIM3_IC2 = (0x6L << 7), + COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 7), + COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 7), ////(0x9L << 7) + COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7), + COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7), + // comp3 out trig + COMP3_CTRL_OUTSEL_NC = (0x0L << 7), + COMP3_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7), + COMP3_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7), + COMP3_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7), + COMP3_CTRL_OUTSEL_TIM2_IC3 = (0x4L << 7), + COMP3_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7), + COMP3_CTRL_OUTSEL_TIM4_IC2 = (0x6L << 7), + COMP3_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 7), + COMP3_CTRL_OUTSEL_TIM5_IC2 = (0x8L << 7), //(0x9L << 7) + COMP3_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7), + COMP3_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7), + // comp4 out trig + COMP4_CTRL_OUTSEL_NC = (0x0L << 7), + COMP4_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7), + COMP4_CTRL_OUTSEL_TIM3_IC3 = (0x2L << 7), + COMP4_CTRL_OUTSEL_TIM3_OCrefclear = (0x3L << 7), + COMP4_CTRL_OUTSEL_TIM4_IC3 = (0x4L << 7), + COMP4_CTRL_OUTSEL_TIM4_OCrefclear = (0x5L << 7), + COMP4_CTRL_OUTSEL_TIM5_IC3 = (0x6L << 7), //(0x7L << 7) + COMP4_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7), + COMP4_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7), + COMP4_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7), + COMP4_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7), + // comp5 out trig + COMP5_CTRL_OUTSEL_NC = (0x0L << 7), + COMP5_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7), + COMP5_CTRL_OUTSEL_TIM2_IC4 = (0x2L << 7), + COMP5_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7), + COMP5_CTRL_OUTSEL_TIM3_IC4 = (0x4L << 7), + COMP5_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7), + COMP5_CTRL_OUTSEL_TIM4_IC4 = (0x6L << 7), + COMP5_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 7), + COMP5_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7), + COMP5_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7), + COMP5_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7), + COMP5_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7), + // comp6 out trig + COMP6_CTRL_OUTSEL_NC = (0x0L << 7), + COMP6_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7), + COMP6_CTRL_OUTSEL_TIM2_IC1 = (0x2L << 7), + COMP6_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7), + COMP6_CTRL_OUTSEL_TIM3_IC1 = (0x4L << 7), + COMP6_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7), + COMP6_CTRL_OUTSEL_TIM5_IC1 = (0x6L << 7), //(0x7L << 7) + COMP6_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7), + COMP6_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7), + COMP6_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7), + COMP6_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7), + // comp7 out trig + COMP7_CTRL_OUTSEL_NC = (0x0L << 7), + COMP7_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7), + COMP7_CTRL_OUTSEL_TIM2_IC1 = (0x2L << 7), + COMP7_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7), + COMP7_CTRL_OUTSEL_TIM3_IC1 = (0x4L << 7), + COMP7_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7), + COMP7_CTRL_OUTSEL_TIM5_IC1 = (0x6L << 7), //(0x7L << 7) + COMP7_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7), + COMP7_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7), + COMP7_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7), + COMP7_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7), +} COMP_CTRL_OUTTRIG; + +#define COMP_CTRL_INPSEL_MASK (0x07L<<4) +typedef enum { + COMPX_CTRL_INPSEL_RES = (0x7L << 4), + //comp1 inp sel + COMP1_CTRL_INPSEL_PA1 = (0x0L << 4), + COMP1_CTRL_INPSEL_PB10 = (0x1L << 4), + //comp2 inp sel, need recheck maybe wrong + COMP2_CTRL_INPSEL_PA1 = (0x0L << 4), + COMP2_CTRL_INPSEL_PB11 = (0x1L << 4), + COMP2_CTRL_INPSEL_PA7 = (0x2L << 4), + //comp3 inp sel + COMP3_CTRL_INPSEL_PB14 = (0x0L << 4), + COMP3_CTRL_INPSEL_PB0 = (0x1L << 4), + //comp4 inp sel, need recheck maybe wrong + COMP4_CTRL_INPSEL_PB14 = (0x0L << 4), + COMP4_CTRL_INPSEL_PB0 = (0x1L << 4), + COMP4_CTRL_INPSEL_PC9 = (0x2L << 4), + COMP4_CTRL_INPSEL_PB15 = (0x3L << 4), + //comp5 inp sel + COMP5_CTRL_INPSEL_PC4 = (0x0L << 4), + COMP5_CTRL_INPSEL_PC3 = (0x1L << 4), + COMP5_CTRL_INPSEL_PA3 = (0x2L << 4), + //comp6 inp sel, need recheck maybe wrong + COMP6_CTRL_INPSEL_PC4 = (0x0L << 4), + COMP6_CTRL_INPSEL_PC3 = (0x1L << 4), + COMP6_CTRL_INPSEL_PC5 = (0x2L << 4), + COMP6_CTRL_INPSEL_PD9 = (0x3L << 4), + //comp7 inp sel + COMP7_CTRL_INPSEL_PC1 = (0x0L << 4), +}COMP_CTRL_INPSEL; + +#define COMP_CTRL_INMSEL_MASK (0x07L<<1) +typedef enum { + COMPX_CTRL_INMSEL_RES = (0x7L << 1), + //comp1 inm sel + COMP1_CTRL_INMSEL_PA0 = (0x0L << 1), + COMP1_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1), + COMP1_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1), + COMP1_CTRL_INMSEL_VERF1 = (0x3L << 1), + COMP1_CTRL_INMSEL_VERF2 = (0x4L << 1), + //comp2 inm sel + COMP2_CTRL_INMSEL_PB1 = (0x0L << 1), + COMP2_CTRL_INMSEL_PE8 = (0x1L << 1), + COMP2_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), + COMP2_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), + COMP2_CTRL_INMSEL_VERF1 = (0x4L << 1), + COMP2_CTRL_INMSEL_VERF2 = (0x5L << 1), + //comp3 inm sel + COMP3_CTRL_INMSEL_PB12 = (0x0L << 1), + COMP3_CTRL_INMSEL_PE7 = (0x1L << 1), + COMP3_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), + COMP3_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), + COMP3_CTRL_INMSEL_VERF1 = (0x4L << 1), + COMP3_CTRL_INMSEL_VERF2 = (0x5L << 1), + //comp4 inm sel + COMP4_CTRL_INMSEL_PC4 = (0x0L << 1), + COMP4_CTRL_INMSEL_PB13 = (0x1L << 1), + COMP4_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), + COMP4_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), + COMP4_CTRL_INMSEL_VERF1 = (0x4L << 1), + COMP4_CTRL_INMSEL_VERF2 = (0x5L << 1), + //comp5 inm sel + COMP5_CTRL_INMSEL_PB10 = (0x0L << 1), + COMP5_CTRL_INMSEL_PD10 = (0x1L << 1), + COMP5_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), + COMP5_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), + COMP5_CTRL_INMSEL_VERF1 = (0x4L << 1), + COMP5_CTRL_INMSEL_VERF2 = (0x5L << 1), + //comp6 inm sel + COMP6_CTRL_INMSEL_PA7 = (0x0L << 1), + COMP6_CTRL_INMSEL_PD8 = (0x1L << 1), + COMP6_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1), + COMP6_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1), + COMP6_CTRL_INMSEL_VERF1 = (0x4L << 1), + COMP6_CTRL_INMSEL_VERF2 = (0x5L << 1), + //comp7 inm sel + COMP7_CTRL_INMSEL_PC0 = (0x0L << 1), + COMP7_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1), + COMP7_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1), + COMP7_CTRL_INMSEL_VERF1 = (0x3L << 1), + COMP7_CTRL_INMSEL_VERF2 = (0x4L << 1), +}COMP_CTRL_INMSEL; + +#define COMP_CTRL_EN_MASK (0x01L << 0) + +//COMPx_FILC +#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1. +#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2. +#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable. + +//COMPx_FILCLKCR +#define COMP_FILCLKCR_CLKPSC_MASK (0xFFFFL<<0)//Low filter sample clock prescale. Number of system clocks between samples = CLK_PRE_CYCLE + 1, e.g. + +//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD +#define COMP_WINMODE_CMPMD_MSK (0x07L <<0) +#define COMP_WINMODE_CMP56MD (0x01L <<2)//1: Comparators 5 and 6 can be used in window mode. +#define COMP_WINMODE_CMP34MD (0x01L <<1)//1: Comparators 3 and 4 can be used in window mode. +#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode. + +//COMPx_LOCK +#define COMP_LOCK_CMPLK_MSK (0x7FL <<0) +#define COMP_LOCK_CMP1LK_MSK (0x01L <<0)//1: COMx Lock bit +#define COMP_LOCK_CMP2LK_MSK (0x01L <<1)//1: COMx Lock bit +#define COMP_LOCK_CMP3LK_MSK (0x01L <<2)//1: COMx Lock bit +#define COMP_LOCK_CMP4LK_MSK (0x01L <<3)//1: COMx Lock bit +#define COMP_LOCK_CMP5LK_MSK (0x01L <<4)//1: COMx Lock bit +#define COMP_LOCK_CMP6LK_MSK (0x01L <<5)//1: COMx Lock bit +#define COMP_LOCK_CMP7LK_MSK (0x01L <<6)//1: COMx Lock bit + +// COMP_INTEN @addtogroup COMP_INTEN_CMPIEN +#define COMP_INTEN_CMPIEN_MSK (0x7FL << 0) +#define COMP_INTEN_CMP7IEN (0x01L << 6) // This bit control Interrput enable of COMP. +#define COMP_INTEN_CMP6IEN (0x01L << 5) +#define COMP_INTEN_CMP5IEN (0x01L << 4) +#define COMP_INTEN_CMP4IEN (0x01L << 3) +#define COMP_INTEN_CMP3IEN (0x01L << 2) +#define COMP_INTEN_CMP2IEN (0x01L << 1) +#define COMP_INTEN_CMP1IEN (0x01L << 0) + +// COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS +#define COMP_INTSTS_INTSTS_MSK (0x7FL << 0) +#define COMP_INTSTS_CMP7IS (0x01L << 6) // This bit control Interrput enable of COMP. +#define COMP_INTSTS_CMP6IS (0x01L << 5) +#define COMP_INTSTS_CMP5IS (0x01L << 4) +#define COMP_INTSTS_CMP4IS (0x01L << 3) +#define COMP_INTSTS_CMP3IS (0x01L << 2) +#define COMP_INTSTS_CMP2IS (0x01L << 1) +#define COMP_INTSTS_CMP1IS (0x01L << 0) + +// COMP_VREFSCL @addtogroup COMP_VREFSCL +#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value. +#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7) +#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value. +#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0) +/** + * @} + */ + +/** + * @brief COMP Init structure definition + */ + +typedef struct +{ + // ctrl + bool InpDacConnect; // only COMP1 have this bit + + COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */ + + COMP_CTRL_HYST Hyst; + + bool PolRev; // out polarity reverse + + COMP_CTRL_OUTTRIG OutSel; + COMP_CTRL_INPSEL InpSel; + COMP_CTRL_INMSEL InmSel; + + bool En; + + // filter + uint8_t SampWindow; // 5bit + uint8_t Thresh; // 5bit ,need > SampWindow/2 + bool FilterEn; + + // filter psc + uint16_t ClkPsc; +} COMP_InitType; + +/** @addtogroup COMP_Exported_Functions + * @{ + */ + +void COMP_DeInit(void); +void COMP_StructInit(COMP_InitType* COMP_InitStruct); +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct); +void COMP_Enable(COMPX COMPx, FunctionalState en); +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel); +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel); +void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig); +void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK +void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN +uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS +void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL +FlagStatus COMP_GetOutStatus(COMPX COMPx); +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx); +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal); +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW); +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST); +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK); + + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_ADC_H */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_crc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_crc.h new file mode 100644 index 0000000000..0721f38cd4 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_crc.h @@ -0,0 +1,105 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_crc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_CRC_H__ +#define __N32G45X_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @addtogroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions + * @{ + */ + +void CRC32_ResetCrc(void); +uint32_t CRC32_CalcCrc(uint32_t Data); +uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC32_GetCrc(void); +void CRC32_SetIDat(uint8_t IDValue); +uint8_t CRC32_GetIDat(void); + +uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength); +uint16_t CRC16_CalcCRC(uint8_t Data); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_CRC_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dac.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dac.h new file mode 100644 index 0000000000..6542d3004e --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dac.h @@ -0,0 +1,307 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_dac.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_DAC_H__ +#define __N32G45X_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @addtogroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t + LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +} DAC_InitType; + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Constants + * @{ + */ + +/** @addtogroup DAC_trigger_selection + * @{ + */ + +#define DAC_TRG_NONE \ + ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \ + has been loaded, and not by external trigger */ +#define DAC_TRG_T6_TRGO \ + ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T8_TRGO \ + ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \ + only in High-density devices*/ +#define DAC_TRG_T3_TRGO \ + ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \ + only in Connectivity line, Medium-density and Low-density Value Line devices */ +#define DAC_TRG_T7_TRGO \ + ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T5_TRGO \ + ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T15_TRGO \ + ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel \ + only in Medium-density and Low-density Value Line devices*/ +#define DAC_TRG_T2_TRGO \ + ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_T4_TRGO \ + ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \ + */ +#define DAC_TRG_EXT_IT9 \ + ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) \ + (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \ + || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \ + || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE)) + +/** + * @} + */ + +/** @addtogroup DAC_wave_generation + * @{ + */ + +#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000) +#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040) +#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) \ + (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE)) +/** + * @} + */ + +/** @addtogroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_UNMASK_LFSRBITS1_0 \ + ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS2_0 \ + ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS3_0 \ + ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS4_0 \ + ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS5_0 \ + ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS6_0 \ + ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS7_0 \ + ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS8_0 \ + ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS9_0 \ + ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \ + */ +#define DAC_UNMASK_LFSRBITS10_0 \ + ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_UNMASK_LFSRBITS11_0 \ + ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \ + (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \ + || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \ + || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \ + || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \ + || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \ + || ((VALUE) == DAC_TRIAMP_4095)) +/** + * @} + */ + +/** @addtogroup DAC_output_buffer + * @{ + */ + +#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002) +#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE)) +/** + * @} + */ + +/** @addtogroup DAC_Channel_selection + * @{ + */ + +#define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || ((CHANNEL) == DAC_CHANNEL_2)) +/** + * @} + */ + +/** @addtogroup DAC_data_alignment + * @{ + */ + +#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000) +#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004) +#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) \ + (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT)) +/** + * @} + */ + +/** @addtogroup DAC_wave_generation + * @{ + */ + +#define DAC_WAVE_NOISE ((uint32_t)0x00000040) +#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE)) +/** + * @} + */ + +/** @addtogroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct); +void DAC_ClearStruct(DAC_InitType* DAC_InitStruct); +void DAC_Enable(uint32_t DAC_Channel, FunctionalState Cmd); + +void DAC_DmaEnable(uint32_t DAC_Channel, FunctionalState Cmd); +void DAC_SoftTrgEnable(uint32_t DAC_Channel, FunctionalState Cmd); +void DAC_DualSoftwareTrgEnable(FunctionalState Cmd); +void DAC_WaveGenerationEnable(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState Cmd); +void DAC_SetCh1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetCh2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetOutputDataVal(uint32_t DAC_Channel); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_DAC_H__ */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dbg.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dbg.h new file mode 100644 index 0000000000..c59d8b3635 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dbg.h @@ -0,0 +1,124 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_dbg.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_DBG_H__ +#define __N32G45X_DBG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBG + * @{ + */ + +/** @addtogroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBG_SLEEP ((uint32_t)0x00000001) +#define DBG_STOP ((uint32_t)0x00000002) +#define DBG_STDBY ((uint32_t)0x00000004) +#define DBG_IWDG_STOP ((uint32_t)0x00000100) +#define DBG_WWDG_STOP ((uint32_t)0x00000200) +#define DBG_TIM1_STOP ((uint32_t)0x00000400) +#define DBG_TIM2_STOP ((uint32_t)0x00000800) +#define DBG_TIM3_STOP ((uint32_t)0x00001000) +#define DBG_TIM4_STOP ((uint32_t)0x00002000) +#define DBG_CAN1_STOP ((uint32_t)0x00004000) +#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBG_TIM8_STOP ((uint32_t)0x00020000) +#define DBG_TIM5_STOP ((uint32_t)0x00040000) +#define DBG_TIM6_STOP ((uint32_t)0x00080000) +#define DBG_TIM7_STOP ((uint32_t)0x00100000) +#define DBG_CAN2_STOP ((uint32_t)0x00200000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Functions + * @{ + */ + +void GetUCID(uint8_t *UCIDbuf); +void GetUID(uint8_t *UIDbuf); +void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf); +uint32_t DBG_GetRevNum(void); +uint32_t DBG_GetDevNum(void); +void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd); + +uint32_t DBG_GetFlashSize(void); +uint32_t DBG_GetSramSize(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_DBG_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dma.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dma.h new file mode 100644 index 0000000000..9dce8ab231 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dma.h @@ -0,0 +1,569 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_dma.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_DMA_H__ +#define __N32G45X_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @addtogroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t Direction; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in PeriphDataSize + or MemDataSize members depending in the transfer direction. */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t MemDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitType; + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) \ + (((PERIPH) == DMA1_CH1) || ((PERIPH) == DMA1_CH2) || ((PERIPH) == DMA1_CH3) || ((PERIPH) == DMA1_CH4) \ + || ((PERIPH) == DMA1_CH5) || ((PERIPH) == DMA1_CH6) || ((PERIPH) == DMA1_CH7) || ((PERIPH) == DMA1_CH8) \ + || ((PERIPH) == DMA2_CH1) || ((PERIPH) == DMA2_CH2) || ((PERIPH) == DMA2_CH3) || ((PERIPH) == DMA2_CH4) \ + || ((PERIPH) == DMA2_CH5) || ((PERIPH) == DMA2_CH6) || ((PERIPH) == DMA2_CH7) || ((PERIPH) == DMA2_CH8)) + +/** @addtogroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010) +#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC)) +/** + * @} + */ + +/** @addtogroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040) +#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE)) +/** + * @} + */ + +/** @addtogroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080) +#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE)) +/** + * @} + */ + +/** @addtogroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000) +#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100) +#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200) +#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \ + (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \ + || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD)) +/** + * @} + */ + +/** @addtogroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \ + (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \ + || ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @addtogroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020) +#define DMA_MODE_NORMAL ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL)) +/** + * @} + */ + +/** @addtogroup DMA_priority_level + * @{ + */ + +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000) +#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000) +#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000) +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \ + || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW)) +/** + * @} + */ + +/** @addtogroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_ENABLE ((uint32_t)0x00004000) +#define DMA_M2M_DISABLE ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE)) + +/** + * @} + */ + +/** @addtogroup DMA_interrupts_definition + * @{ + */ + +#define DMA_INT_TXC ((uint32_t)0x00000002) +#define DMA_INT_HTX ((uint32_t)0x00000004) +#define DMA_INT_ERR ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_INT_GLB1 ((uint32_t)0x00000001) +#define DMA1_INT_TXC1 ((uint32_t)0x00000002) +#define DMA1_INT_HTX1 ((uint32_t)0x00000004) +#define DMA1_INT_ERR1 ((uint32_t)0x00000008) +#define DMA1_INT_GLB2 ((uint32_t)0x00000010) +#define DMA1_INT_TXC2 ((uint32_t)0x00000020) +#define DMA1_INT_HTX2 ((uint32_t)0x00000040) +#define DMA1_INT_ERR2 ((uint32_t)0x00000080) +#define DMA1_INT_GLB3 ((uint32_t)0x00000100) +#define DMA1_INT_TXC3 ((uint32_t)0x00000200) +#define DMA1_INT_HTX3 ((uint32_t)0x00000400) +#define DMA1_INT_ERR3 ((uint32_t)0x00000800) +#define DMA1_INT_GLB4 ((uint32_t)0x00001000) +#define DMA1_INT_TXC4 ((uint32_t)0x00002000) +#define DMA1_INT_HTX4 ((uint32_t)0x00004000) +#define DMA1_INT_ERR4 ((uint32_t)0x00008000) +#define DMA1_INT_GLB5 ((uint32_t)0x00010000) +#define DMA1_INT_TXC5 ((uint32_t)0x00020000) +#define DMA1_INT_HTX5 ((uint32_t)0x00040000) +#define DMA1_INT_ERR5 ((uint32_t)0x00080000) +#define DMA1_INT_GLB6 ((uint32_t)0x00100000) +#define DMA1_INT_TXC6 ((uint32_t)0x00200000) +#define DMA1_INT_HTX6 ((uint32_t)0x00400000) +#define DMA1_INT_ERR6 ((uint32_t)0x00800000) +#define DMA1_INT_GLB7 ((uint32_t)0x01000000) +#define DMA1_INT_TXC7 ((uint32_t)0x02000000) +#define DMA1_INT_HTX7 ((uint32_t)0x04000000) +#define DMA1_INT_ERR7 ((uint32_t)0x08000000) +#define DMA1_INT_GLB8 ((uint32_t)0x10000000) +#define DMA1_INT_TXC8 ((uint32_t)0x20000000) +#define DMA1_INT_HTX8 ((uint32_t)0x40000000) +#define DMA1_INT_ERR8 ((uint32_t)0x80000000) + +#define DMA2_INT_GLB1 ((uint32_t)0x00000001) +#define DMA2_INT_TXC1 ((uint32_t)0x00000002) +#define DMA2_INT_HTX1 ((uint32_t)0x00000004) +#define DMA2_INT_ERR1 ((uint32_t)0x00000008) +#define DMA2_INT_GLB2 ((uint32_t)0x00000010) +#define DMA2_INT_TXC2 ((uint32_t)0x00000020) +#define DMA2_INT_HTX2 ((uint32_t)0x00000040) +#define DMA2_INT_ERR2 ((uint32_t)0x00000080) +#define DMA2_INT_GLB3 ((uint32_t)0x00000100) +#define DMA2_INT_TXC3 ((uint32_t)0x00000200) +#define DMA2_INT_HTX3 ((uint32_t)0x00000400) +#define DMA2_INT_ERR3 ((uint32_t)0x00000800) +#define DMA2_INT_GLB4 ((uint32_t)0x00001000) +#define DMA2_INT_TXC4 ((uint32_t)0x00002000) +#define DMA2_INT_HTX4 ((uint32_t)0x00004000) +#define DMA2_INT_ERR4 ((uint32_t)0x00008000) +#define DMA2_INT_GLB5 ((uint32_t)0x00010000) +#define DMA2_INT_TXC5 ((uint32_t)0x00020000) +#define DMA2_INT_HTX5 ((uint32_t)0x00040000) +#define DMA2_INT_ERR5 ((uint32_t)0x00080000) +#define DMA2_INT_GLB6 ((uint32_t)0x00100000) +#define DMA2_INT_TXC6 ((uint32_t)0x00200000) +#define DMA2_INT_HTX6 ((uint32_t)0x00400000) +#define DMA2_INT_ERR6 ((uint32_t)0x00800000) +#define DMA2_INT_GLB7 ((uint32_t)0x01000000) +#define DMA2_INT_TXC7 ((uint32_t)0x02000000) +#define DMA2_INT_HTX7 ((uint32_t)0x04000000) +#define DMA2_INT_ERR7 ((uint32_t)0x08000000) +#define DMA2_INT_GLB8 ((uint32_t)0x10000000) +#define DMA2_INT_TXC8 ((uint32_t)0x20000000) +#define DMA2_INT_HTX8 ((uint32_t)0x40000000) +#define DMA2_INT_ERR8 ((uint32_t)0x80000000) + +#define IS_DMA_CLR_INT(IT) (((((IT)&0xF0000000) == 0x00) || (((IT)&0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) \ + (((IT) == DMA1_INT_GLB1) || ((IT) == DMA1_INT_TXC1) || ((IT) == DMA1_INT_HTX1) || ((IT) == DMA1_INT_ERR1) \ + || ((IT) == DMA1_INT_GLB2) || ((IT) == DMA1_INT_TXC2) || ((IT) == DMA1_INT_HTX2) || ((IT) == DMA1_INT_ERR2) \ + || ((IT) == DMA1_INT_GLB3) || ((IT) == DMA1_INT_TXC3) || ((IT) == DMA1_INT_HTX3) || ((IT) == DMA1_INT_ERR3) \ + || ((IT) == DMA1_INT_GLB4) || ((IT) == DMA1_INT_TXC4) || ((IT) == DMA1_INT_HTX4) || ((IT) == DMA1_INT_ERR4) \ + || ((IT) == DMA1_INT_GLB5) || ((IT) == DMA1_INT_TXC5) || ((IT) == DMA1_INT_HTX5) || ((IT) == DMA1_INT_ERR5) \ + || ((IT) == DMA1_INT_GLB6) || ((IT) == DMA1_INT_TXC6) || ((IT) == DMA1_INT_HTX6) || ((IT) == DMA1_INT_ERR6) \ + || ((IT) == DMA1_INT_GLB7) || ((IT) == DMA1_INT_TXC7) || ((IT) == DMA1_INT_HTX7) || ((IT) == DMA1_INT_ERR7) \ + || ((IT) == DMA1_INT_GLB8) || ((IT) == DMA1_INT_TXC8) || ((IT) == DMA1_INT_HTX8) || ((IT) == DMA1_INT_ERR8) \ + || ((IT) == DMA2_INT_GLB1) || ((IT) == DMA2_INT_TXC1) || ((IT) == DMA2_INT_HTX1) || ((IT) == DMA2_INT_ERR1) \ + || ((IT) == DMA2_INT_GLB2) || ((IT) == DMA2_INT_TXC2) || ((IT) == DMA2_INT_HTX2) || ((IT) == DMA2_INT_ERR2) \ + || ((IT) == DMA2_INT_GLB3) || ((IT) == DMA2_INT_TXC3) || ((IT) == DMA2_INT_HTX3) || ((IT) == DMA2_INT_ERR3) \ + || ((IT) == DMA2_INT_GLB4) || ((IT) == DMA2_INT_TXC4) || ((IT) == DMA2_INT_HTX4) || ((IT) == DMA2_INT_ERR4) \ + || ((IT) == DMA2_INT_GLB5) || ((IT) == DMA2_INT_TXC5) || ((IT) == DMA2_INT_HTX5) || ((IT) == DMA2_INT_ERR5) \ + || ((IT) == DMA2_INT_GLB6) || ((IT) == DMA2_INT_TXC6) || ((IT) == DMA2_INT_HTX6) || ((IT) == DMA2_INT_ERR6) \ + || ((IT) == DMA2_INT_GLB7) || ((IT) == DMA2_INT_TXC7) || ((IT) == DMA2_INT_HTX7) || ((IT) == DMA2_INT_ERR7) \ + || ((IT) == DMA2_INT_GLB8) || ((IT) == DMA2_INT_TXC8) || ((IT) == DMA2_INT_HTX8) || ((IT) == DMA2_INT_ERR8)) + +/** + * @} + */ + +/** @addtogroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA2_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA2_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA2_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA2_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA2_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA2_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA2_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA2_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA2_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA2_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA2_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA2_FLAG_TE8 ((uint32_t)0x80000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG)&0xF0000000) == 0x00) || (((FLAG)&0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) \ + (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) \ + || ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || ((FLAG) == DMA1_FLAG_HT2) \ + || ((FLAG) == DMA1_FLAG_TE2) || ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) \ + || ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || ((FLAG) == DMA1_FLAG_GL4) \ + || ((FLAG) == DMA1_FLAG_TC4) || ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) \ + || ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || ((FLAG) == DMA1_FLAG_HT5) \ + || ((FLAG) == DMA1_FLAG_TE5) || ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) \ + || ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || ((FLAG) == DMA1_FLAG_GL7) \ + || ((FLAG) == DMA1_FLAG_TC7) || ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) \ + || ((FLAG) == DMA1_FLAG_GL8) || ((FLAG) == DMA1_FLAG_TC8) || ((FLAG) == DMA1_FLAG_HT8) \ + || ((FLAG) == DMA1_FLAG_TE8) || ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) \ + || ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || ((FLAG) == DMA2_FLAG_GL2) \ + || ((FLAG) == DMA2_FLAG_TC2) || ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) \ + || ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || ((FLAG) == DMA2_FLAG_HT3) \ + || ((FLAG) == DMA2_FLAG_TE3) || ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) \ + || ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || ((FLAG) == DMA2_FLAG_GL5) \ + || ((FLAG) == DMA2_FLAG_TC5) || ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5) \ + || ((FLAG) == DMA2_FLAG_GL6) || ((FLAG) == DMA2_FLAG_TC6) || ((FLAG) == DMA2_FLAG_HT6) \ + || ((FLAG) == DMA2_FLAG_TE6) || ((FLAG) == DMA2_FLAG_GL7) || ((FLAG) == DMA2_FLAG_TC7) \ + || ((FLAG) == DMA2_FLAG_HT7) || ((FLAG) == DMA2_FLAG_TE7) || ((FLAG) == DMA2_FLAG_GL8) \ + || ((FLAG) == DMA2_FLAG_TC8) || ((FLAG) == DMA2_FLAG_HT8) || ((FLAG) == DMA2_FLAG_TE8)) +/** + * @} + */ + +/** @addtogroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** @addtogroup DMA_remap_request_definition + * @{ + */ +#define DMA1_REMAP_ADC1 ((uint32_t)0x00000000) +#define DMA1_REMAP_UART5_TX ((uint32_t)0x00000001) +#define DMA1_REMAP_I2C3_TX ((uint32_t)0x00000002) +#define DMA1_REMAP_TIM2_CH3 ((uint32_t)0x00000003) +#define DMA1_REMAP_TIM4_CH1 ((uint32_t)0x00000004) +#define DMA1_REMAP_USART3_TX ((uint32_t)0x00000005) +#define DMA1_REMAP_I2C3_RX ((uint32_t)0x00000006) +#define DMA1_REMAP_TIM1_CH1 ((uint32_t)0x00000007) +#define DMA1_REMAP_TIM2_UP ((uint32_t)0x00000008) +#define DMA1_REMAP_TIM3_CH3 ((uint32_t)0x00000009) +#define DMA1_REMAP_SPI1_RX ((uint32_t)0x0000000A) +#define DMA1_REMAP_USART3_RX ((uint32_t)0x0000000B) +#define DMA1_REMAP_TIM1_CH2 ((uint32_t)0x0000000C) +#define DMA1_REMAP_TIM3_CH4 ((uint32_t)0x0000000D) +#define DMA1_REMAP_TIM3_UP ((uint32_t)0x0000000E) +#define DMA1_REMAP_SPI1_TX ((uint32_t)0x0000000F) +#define DMA1_REMAP_USART1_TX ((uint32_t)0x00000010) +#define DMA1_REMAP_TIM1_CH4 ((uint32_t)0x00000011) +#define DMA1_REMAP_TIM1_TRIG ((uint32_t)0x00000012) +#define DMA1_REMAP_TIM1_COM ((uint32_t)0x00000013) +#define DMA1_REMAP_TIM4_CH2 ((uint32_t)0x00000014) +#define DMA1_REMAP_SPI_I2S2_RX ((uint32_t)0x00000015) +#define DMA1_REMAP_I2C2_TX ((uint32_t)0x00000016) +#define DMA1_REMAP_USART1_RX ((uint32_t)0x00000017) +#define DMA1_REMAP_TIM1_UP ((uint32_t)0x00000018) +#define DMA1_REMAP_SPI_I2S2_TX ((uint32_t)0x00000019) +#define DMA1_REMAP_TIM4_CH3 ((uint32_t)0x0000001B) +#define DMA1_REMAP_I2C2_RX ((uint32_t)0x0000001C) +#define DMA1_REMAP_TIM2_CH1 ((uint32_t)0x0000001A) +#define DMA1_REMAP_USART2_RX ((uint32_t)0x0000001D) +#define DMA1_REMAP_TIM1_CH3 ((uint32_t)0x0000001E) +#define DMA1_REMAP_TIM3_CH1 ((uint32_t)0x0000001F) +#define DMA1_REMAP_TIM3_TRIG ((uint32_t)0x00000020) +#define DMA1_REMAP_I2C1_TX ((uint32_t)0x00000021) +#define DMA1_REMAP_USART2_TX ((uint32_t)0x00000022) +#define DMA1_REMAP_TIM2_CH2 ((uint32_t)0x00000023) +#define DMA1_REMAP_TIM2_CH4 ((uint32_t)0x00000024) +#define DMA1_REMAP_TIM4_UP ((uint32_t)0x00000025) +#define DMA1_REMAP_I2C1_RX ((uint32_t)0x00000026) +#define DMA1_REMAP_ADC2 ((uint32_t)0x00000027) +#define DMA1_REMAP_UART5_RX ((uint32_t)0x00000028) +#define DMA2_REMAP_TIM5_CH4 ((uint32_t)0x00000000) +#define DMA2_REMAP_TIM5_TRIG ((uint32_t)0x00000001) +#define DMA2_REMAP_TIM8_CH3 ((uint32_t)0x00000002) +#define DMA2_REMAP_TIM8_UP ((uint32_t)0x00000003) +#define DMA2_REMAP_SPI_I2S3_RX ((uint32_t)0x00000004) +#define DMA2_REMAP_UART6_RX ((uint32_t)0x00000005) +#define DMA2_REMAP_TIM8_CH4 ((uint32_t)0x00000006) +#define DMA2_REMAP_TIM8_TRIG ((uint32_t)0x00000007) +#define DMA2_REMAP_TIM8_COM ((uint32_t)0x00000008) +#define DMA2_REMAP_TIM5_CH3 ((uint32_t)0x00000009) +#define DMA2_REMAP_TIM5_UP ((uint32_t)0x0000000A) +#define DMA2_REMAP_SPI_I2S3_TX ((uint32_t)0x0000000B) +#define DMA2_REMAP_UART6_TX ((uint32_t)0x0000000C) +#define DMA2_REMAP_TIM8_CH1 ((uint32_t)0x0000000D) +#define DMA2_REMAP_UART4_RX ((uint32_t)0x0000000E) +#define DMA2_REMAP_TIM6_UP ((uint32_t)0x0000000F) +#define DMA2_REMAP_DAC1 ((uint32_t)0x00000010) +#define DMA2_REMAP_TIM5_CH2 ((uint32_t)0x00000011) +#define DMA2_REMAP_SDIO ((uint32_t)0x00000012) +#define DMA2_REMAP_TIM7_UP ((uint32_t)0x00000013) +#define DMA2_REMAP_DAC2 ((uint32_t)0x00000014) +#define DMA2_REMAP_ADC3 ((uint32_t)0x00000015) +#define DMA2_REMAP_TIM8_CH2 ((uint32_t)0x00000016) +#define DMA2_REMAP_TIM5_CH1 ((uint32_t)0x00000017) +#define DMA2_REMAP_UART4_TX ((uint32_t)0x00000018) +#define DMA2_REMAP_QSPI_RX ((uint32_t)0x00000019) +#define DMA2_REMAP_I2C4_TX ((uint32_t)0x0000001A) +#define DMA2_REMAP_UART7_RX ((uint32_t)0x0000001B) +#define DMA2_REMAP_QSPI_TX ((uint32_t)0x0000001C) +#define DMA2_REMAP_I2C4_RX ((uint32_t)0x0000001D) +#define DMA2_REMAP_UART7_TX ((uint32_t)0x0000001E) +#define DMA2_REMAP_ADC4 ((uint32_t)0x0000001F) +#define DMA2_REMAP_DVP ((uint32_t)0x00000020) + +#define IS_DMA_REMAP(FLAG) \ + (((FLAG) == DMA1_REMAP_ADC1) || ((FLAG) == DMA1_REMAP_UART5_TX) || ((FLAG) == DMA1_REMAP_I2C3_TX) \ + || ((FLAG) == DMA1_REMAP_TIM2_CH3) || ((FLAG) == DMA1_REMAP_TIM4_CH1) || ((FLAG) == DMA1_REMAP_USART3_TX) \ + || ((FLAG) == DMA1_REMAP_I2C3_RX) || ((FLAG) == DMA1_REMAP_TIM1_CH1) || ((FLAG) == DMA1_REMAP_TIM2_UP) \ + || ((FLAG) == DMA1_REMAP_TIM3_CH3) || ((FLAG) == DMA1_REMAP_SPI1_RX) || ((FLAG) == DMA1_REMAP_USART3_RX) \ + || ((FLAG) == DMA1_REMAP_TIM1_CH2) || ((FLAG) == DMA1_REMAP_TIM3_CH4) || ((FLAG) == DMA1_REMAP_TIM3_UP) \ + || ((FLAG) == DMA1_REMAP_SPI1_TX) || ((FLAG) == DMA1_REMAP_USART1_TX) || ((FLAG) == DMA1_REMAP_TIM1_CH4) \ + || ((FLAG) == DMA1_REMAP_TIM1_TRIG) || ((FLAG) == DMA1_REMAP_TIM1_COM) || ((FLAG) == DMA1_REMAP_TIM4_CH2) \ + || ((FLAG) == DMA1_REMAP_SPI_I2S2_RX) || ((FLAG) == DMA1_REMAP_I2C2_TX) || ((FLAG) == DMA1_REMAP_USART1_RX) \ + || ((FLAG) == DMA1_REMAP_TIM1_UP) || ((FLAG) == DMA1_REMAP_SPI_I2S2_TX) || ((FLAG) == DMA1_REMAP_TIM4_CH3) \ + || ((FLAG) == DMA1_REMAP_I2C2_RX) || ((FLAG) == DMA1_REMAP_TIM2_CH1) || ((FLAG) == DMA1_REMAP_USART2_RX) \ + || ((FLAG) == DMA1_REMAP_TIM1_CH3) || ((FLAG) == DMA1_REMAP_TIM3_CH1) || ((FLAG) == DMA1_REMAP_TIM3_TRIG) \ + || ((FLAG) == DMA1_REMAP_I2C1_TX) || ((FLAG) == DMA1_REMAP_USART2_TX) || ((FLAG) == DMA1_REMAP_TIM2_CH2) \ + || ((FLAG) == DMA1_REMAP_TIM2_CH4) || ((FLAG) == DMA1_REMAP_TIM4_UP) || ((FLAG) == DMA1_REMAP_I2C1_RX) \ + || ((FLAG) == DMA1_REMAP_ADC2) || ((FLAG) == DMA1_REMAP_UART5_RX) || ((FLAG) == DMA2_REMAP_TIM5_CH4) \ + || ((FLAG) == DMA2_REMAP_TIM5_TRIG) || ((FLAG) == DMA2_REMAP_TIM8_CH3) || ((FLAG) == DMA2_REMAP_TIM8_UP) \ + || ((FLAG) == DMA2_REMAP_SPI_I2S3_RX) || ((FLAG) == DMA2_REMAP_UART6_RX) || ((FLAG) == DMA2_REMAP_TIM8_CH4) \ + || ((FLAG) == DMA2_REMAP_TIM8_TRIG) || ((FLAG) == DMA2_REMAP_TIM8_COM) || ((FLAG) == DMA2_REMAP_TIM5_CH3) \ + || ((FLAG) == DMA2_REMAP_TIM5_UP) || ((FLAG) == DMA2_REMAP_SPI_I2S3_TX) || ((FLAG) == DMA2_REMAP_UART6_TX) \ + || ((FLAG) == DMA2_REMAP_TIM8_CH1) || ((FLAG) == DMA2_REMAP_UART4_RX) || ((FLAG) == DMA2_REMAP_TIM6_UP) \ + || ((FLAG) == DMA2_REMAP_DAC1) || ((FLAG) == DMA2_REMAP_TIM5_CH2) || ((FLAG) == DMA2_REMAP_SDIO) \ + || ((FLAG) == DMA2_REMAP_TIM7_UP) || ((FLAG) == DMA2_REMAP_DAC2) || ((FLAG) == DMA2_REMAP_ADC3) \ + || ((FLAG) == DMA2_REMAP_TIM8_CH2) || ((FLAG) == DMA2_REMAP_TIM5_CH1) || ((FLAG) == DMA2_REMAP_UART4_TX) \ + || ((FLAG) == DMA2_REMAP_QSPI_RX) || ((FLAG) == DMA2_REMAP_I2C4_TX) || ((FLAG) == DMA2_REMAP_UART7_RX) \ + || ((FLAG) == DMA2_REMAP_QSPI_TX) || ((FLAG) == DMA2_REMAP_I2C4_RX) || ((FLAG) == DMA2_REMAP_UART7_TX) \ + || ((FLAG) == DMA2_REMAP_ADC4) || ((FLAG) == DMA2_REMAP_DVP)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_ChannelType* DMAyChx); +void DMA_Init(DMA_ChannelType* DMAyChx, DMA_InitType* DMA_InitParam); +void DMA_StructInit(DMA_InitType* DMA_InitParam); +void DMA_EnableChannel(DMA_ChannelType* DMAyChx, FunctionalState Cmd); +void DMA_ConfigInt(DMA_ChannelType* DMAyChx, uint32_t DMAInt, FunctionalState Cmd); +void DMA_SetCurrDataCounter(DMA_ChannelType* DMAyChx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAyChx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAyFlag, DMA_Module* DMAy); +void DMA_ClearFlag(uint32_t DMAyFlag, DMA_Module* DMAy); +INTStatus DMA_GetIntStatus(uint32_t DMAy_IT, DMA_Module* DMAy); +void DMA_ClrIntPendingBit(uint32_t DMAy_IT, DMA_Module* DMAy); +void DMA_RequestRemap(uint32_t DMAy_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAyChx, FunctionalState Cmd); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_DMA_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dvp.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dvp.h new file mode 100644 index 0000000000..7d04d77668 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dvp.h @@ -0,0 +1,593 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_dvp.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ + +#ifndef __N32G45X_DVP_H__ +#define __N32G45X_DVP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DVP + * @brief DVP driver modules + * @{ + */ + +/** @addtogroup DVP_Exported_Types + * @{ + */ +/** + * @brief DVP Init Structure definition + */ +typedef struct +{ + uint32_t FifoWatermark; /*!< Specifies the max number of fifo data which will request INT or DMA + This parameter can be a value of @ref DVP_FifoWatermark */ + + uint16_t LineCapture; /*!< Specifies the number of data line captuered in x lines. + This parameter can be a value of @ref DVP_LineSelect_Mode */ + + uint16_t ByteCapture; /*!< Specifies the number of stop byte captuered in x bytes. + This parameter can be a value of @ref DVP_ByteSelect_Mode */ + + uint16_t DataInvert; /*!< Specifies the data invert. + This parameter can be a value of @ref DVP_DATA_INVERT */ + + uint16_t PixelClkPolarity; /*!< Specifies the pixel clock polarity + This parameter can be a value of @ref DVP_Pixel_Polarity */ + + uint16_t VsyncPolarity; /*!< Specifies the vertical synchronization polarity + This parameter can be a value of @ref DVP_Vsync_Polarity */ + + uint16_t HsyncPolarity; /*!< Specifies the Horizontal synchronization polarity + This parameter can be a value of @ref DVP_Hsync_Polarity */ + + uint16_t CaptureMode; /*!< Specifies the capture mode. + This parameter can be a value of @ref DVP_Capture_Mode */ + + uint16_t RowStart; /*!< Specifies the startint row of the pixel array in a frame */ + + uint16_t ColumnStart; /*!< Specifies the starting column of the pixel array row in a frame */ + + uint16_t ImageHeight; /*!< Specifies the image's height in a frame */ + + uint16_t ImageWidth; /*!< Specifies the image's width in a frame */ + +} DVP_InitType; +/** + * @} + */ + +/** @addtogroup DVP_Exported_Constants + * @{ + */ + +/** @addtogroup DVP_FIFO_SOFT_RESET + * @{ + */ +#define DVP_FIFO_SOFT_RESET (DVP_CTRL_FFSWRST) +/** + * @} + */ + +/** @addtogroup DVP_LineSelect_Mode + * @{ + */ +#define DVP_LINE_CAPTURE_ALL (0x00000000) +#define DVP_LINE_CAPTURE_1_2 (0x1UL << DVP_CTRL_LSM_SHIFT) +#define DVP_LINE_CAPTURE_1_3 (0x2UL << DVP_CTRL_LSM_SHIFT) +#define DVP_LINE_CAPTURE_1_4 (0x3UL << DVP_CTRL_LSM_SHIFT) +#define DVP_LINE_CAPTURE_1_5 (0x4UL << DVP_CTRL_LSM_SHIFT) +#define DVP_LINE_CAPTURE_1_6 (0x5UL << DVP_CTRL_LSM_SHIFT) +#define DVP_LINE_CAPTURE_1_7 (0x6UL << DVP_CTRL_LSM_SHIFT) +#define DVP_LINE_CAPTURE_1_8 (0x7UL << DVP_CTRL_LSM_SHIFT) +#define IS_DVP_LINE_CAPTURE(_LSM_) (((_LSM_) & (~DVP_CTRL_LSM_MASK) )==0) +/** + * @} + */ + +/** @addtogroup DVP_ByteSelect_Mode + * @{ + */ +#define DVP_BYTE_CAPTURE_ALL (0x00000000) +#define DVP_BYTE_CAPTURE_1_2 (0x1UL << DVP_CTRL_BSM_SHIFT) +#define DVP_BYTE_CAPTURE_1_3 (0x2UL << DVP_CTRL_BSM_SHIFT) +#define DVP_BYTE_CAPTURE_1_4 (0x3UL << DVP_CTRL_BSM_SHIFT) +#define DVP_BYTE_CAPTURE_1_5 (0x4UL << DVP_CTRL_BSM_SHIFT) +#define DVP_BYTE_CAPTURE_1_6 (0x5UL << DVP_CTRL_BSM_SHIFT) +#define DVP_BYTE_CAPTURE_1_7 (0x6UL << DVP_CTRL_BSM_SHIFT) +#define DVP_BYTE_CAPTURE_1_8 (0x7UL << DVP_CTRL_BSM_SHIFT) +#define IS_DVP_BYTE_CAPTURE(_BSM_) (((_BSM_) & (~DVP_CTRL_BSM_MASK) )==0) + +/** + * @} + */ + +/** @addtogroup DVP_DATA_INVERT + * @{ + */ +#define DVP_DATA_INVERT (DVP_CTRL_DATINV) +#define DVP_DATA_NOTINVERT (0x00000000) +#define IS_DVP_DATA_INVERT(_INV_) (((_INV_) & (~DVP_CTRL_DATINV_MASK) )==0) +/** + * @} + */ + +/** @addtogroup DVP_Pixel_Polarity + * @{ + */ +#define DVP_PIXEL_POLARITY_FALLING (0x00000000) +#define DVP_PIXEL_POLARITY_RISING (DVP_CTRL_PCKPOL) +#define IS_DVP_PIXEL_POLARITY(_POL_) (((_POL_) & (~DVP_CTRL_PCKPOL_MASK) )==0) +/** + * @} + */ + +/** @addtogroup DVP_FifoWatermark + * @{ + */ +#define DVP_WATER_MARK_1 (0x1UL << DVP_CTRL_FWM_SHIFT) +#define DVP_WATER_MARK_2 (0x2UL << DVP_CTRL_FWM_SHIFT) +#define DVP_WATER_MARK_3 (0x3UL << DVP_CTRL_FWM_SHIFT) +#define DVP_WATER_MARK_4 (0x4UL << DVP_CTRL_FWM_SHIFT) +#define IS_DVP_FIFOWATERMARK(_WATER_) (((_WATER_) >= DVP_WATER_MARK_1) && ((_WATER_) <= DVP_WATER_MARK_4)) + +/** @addtogroup DVP_Vsync_Polarity + * @{ + */ +#define DVP_VSYNC_POLARITY_HIGH (DVP_CTRL_VSPOL) +#define DVP_VSYNC_POLARITY_LOW (0x00000000) +#define IS_DVP_VSYNC_POLARITY(_POL_) (((_POL_) == DVP_VSYNC_POLARITY_HIGH) || ((_POL_) == DVP_VSYNC_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup DVP_Hsync_Polarity + * @{ + */ +#define DVP_HSYNC_POLARITY_HIGH (DVP_CTRL_HSPOL) +#define DVP_HSYNC_POLARITY_LOW (0x00000000) +#define IS_DVP_HSYNC_POLARITY(_POL_) (((_POL_) == DVP_HSYNC_POLARITY_HIGH) || ((_POL_) == DVP_HSYNC_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup DVP_Capture_Mode + * @{ + */ +#define DVP_CAPTURE_MODE_SINGLE (0x00000000) +#define DVP_CAPTURE_MODE_CONTINUE (DVP_CTRL_CM) +#define IS_DVP_CAPTURE_MODE(_MODE_) (((_MODE_) == DVP_CAPTURE_MODE_SINGLE) || ((_MODE_) == DVP_CAPTURE_MODE_CONTINUE)) +/** + * @} + */ + +/** @addtogroup DVP_CAPTURE_ENABLE + * @{ + */ +#define DVP_CAPTURE_DISABLE (0x00000000) +#define DVP_CAPTURE_ENABLE (DVP_CTRL_CAPTURE) +#define IS_DVP_CAPTURE(_CAPTURE_) (((_CAPTURE_) == DVP_CAPTURE_DISABLE) || ((_CAPTURE_) == DVP_CAPTURE_ENABLE)) +/** + * @} + */ + +/** @addtogroup DVP_DMA + * @{ + */ +#define DVP_DMA_DISABLE (0x00000000) +#define DVP_DMA_ENABLE (DVP_INTEN_DMAEN) +/** + * @} + */ + +/** @addtogroup DVP_StatusFlag + * @{ + */ +#define DVP_FLAG_HERR (DVP_INTSTS_HERRIS) +#define DVP_FLAG_VERR (DVP_INTSTS_VERRIS) +#define DVP_FLAG_FO (DVP_INTSTS_FOIS) +#define DVP_FLAG_FW (DVP_INTSTS_FWIS) +#define DVP_FLAG_FF (DVP_INTSTS_FFIS) +#define DVP_FLAG_FE (DVP_INTSTS_FEIS) +#define DVP_FLAG_LE (DVP_INTSTS_LEIS) +#define DVP_FLAG_LS (DVP_INTSTS_LSIS) +#define DVP_FLAG_FME (DVP_INTSTS_FMEIS) +#define DVP_FLAG_FMS (DVP_INTSTS_FMSIS) +#define DVP_FLAG_MASK (DVP_FLAG_HERR |DVP_FLAG_VERR |DVP_FLAG_FO \ + |DVP_FLAG_FW |DVP_FLAG_FF |DVP_FLAG_FE \ + |DVP_FLAG_LE |DVP_FLAG_LS |DVP_FLAG_FME \ + |DVP_FLAG_FMS) +#define IS_DVP_FLAG(_FLAG_) (((_FLAG_) & (~DVP_FLAG_MASK))==0) + +/** @addtogroup DVP_ClearFlag + * @{ + */ +#define DVP_CLEAR_FLAG_HERR (DVP_INTSTS_HERRIS) +#define DVP_CLEAR_FLAG_VERR (DVP_INTSTS_VERRIS) +#define DVP_CLEAR_FLAG_FO (DVP_INTSTS_FOIS) +#define DVP_CLEAR_FLAG_FE (DVP_INTSTS_FEIS) +#define DVP_CLEAR_FLAG_LE (DVP_INTSTS_LEIS) +#define DVP_CLEAR_FLAG_LS (DVP_INTSTS_LSIS) +#define DVP_CLEAR_FLAG_FME (DVP_INTSTS_FMEIS) +#define DVP_CLEAR_FLAG_FMS (DVP_INTSTS_FMSIS) +#define DVP_CLEAR_FLAG_MASK (DVP_CLEAR_FLAG_HERR |DVP_CLEAR_FLAG_VERR \ + |DVP_CLEAR_FLAG_FO |DVP_CLEAR_FLAG_FE \ + |DVP_CLEAR_FLAG_LE |DVP_CLEAR_FLAG_LS \ + |DVP_CLEAR_FLAG_FME |DVP_CLEAR_FLAG_FMS) +#define IS_DVP_CLEAR_FLAG(_FLAG_) (((_FLAG_) & (~DVP_CLEAR_FLAG_MASK))==0) + + +/** + * @} + */ + +/** @addtogroup DVP_IntEnable + * @{ + */ +#define DVP_INTEN_HERR (DVP_INTEN_HERRIE) +#define DVP_INTEN_VERR (DVP_INTEN_VERRIE) +#define DVP_INTEN_FO (DVP_INTEN_FOIE) +#define DVP_INTEN_FW (DVP_INTEN_FWIE) +#define DVP_INTEN_FF (DVP_INTEN_FFIE) +#define DVP_INTEN_FE (DVP_INTEN_FEIE) +#define DVP_INTEN_LE (DVP_INTEN_LEIE) +#define DVP_INTEN_LS (DVP_INTEN_LSIE) +#define DVP_INTEN_FME (DVP_INTEN_FMEIE) +#define DVP_INTEN_FMS (DVP_INTEN_FMSIE) +#define DVP_INTEN_MASK (DVP_INTEN_HERR |DVP_INTEN_VERR |DVP_INTEN_FO |DVP_INTEN_FW \ + |DVP_INTEN_FF |DVP_INTEN_FE |DVP_INTEN_LE |DVP_INTEN_LS \ + |DVP_INTEN_FME |DVP_INTEN_FMS) +#define IS_DVP_INTEN(_INT_) (((_INT_) & (~DVP_INTEN_MASK))==0) +/** + * @} + */ + +/** @addtogroup DVP_IntMark + * @{ + */ +#define DVP_MINT_HERR (DVP_MINTSTS_HERRMIS) +#define DVP_MINT_VERR (DVP_MINTSTS_VERRMIS) +#define DVP_MINT_FO (DVP_MINTSTS_FOMIS) +#define DVP_MINT_FW (DVP_MINTSTS_FWMIS) +#define DVP_MINT_FF (DVP_MINTSTS_FFMIS) +#define DVP_MINT_FE (DVP_MINTSTS_FEMIS) +#define DVP_MINT_LE (DVP_MINTSTS_LEMIS) +#define DVP_MINT_LS (DVP_MINTSTS_LSMIS) +#define DVP_MINT_FME (DVP_MINTSTS_FMEMIS) +#define DVP_MINT_FMS (DVP_MINTSTS_FMSMIS) +#define DVP_MINT_MASK (DVP_MINT_HERR |DVP_MINT_VERR |DVP_MINT_FO |DVP_MINT_FW \ + |DVP_MINT_FF |DVP_MINT_FE |DVP_MINT_LE |DVP_MINT_LS \ + |DVP_MINT_FME |DVP_MINT_FMS) +#define IS_DVP_MINT(_MINT_) (((_MINT_) & (~DVP_MINT_MASK))==0) +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @addtogroup DVP_Exported_Macros + * @{ + */ + +/** + * @brief Config the water mark of FIFO. + * @param _Watermark_ Select the new water mark of FIFO. + * This parameter can be one of the following values: + * @arg DVP_WATER_MARK_1 + * @arg DVP_WATER_MARK_2 + * @arg DVP_WATER_MARK_3 + * @arg DVP_WATER_MARK_4 + * @retval None + */ +#define __DVP_SetFifoWatermark(_Watermark_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_FWM_MASK, _Watermark_)) + +/** + * @brief Config the line capture mode. + * @param _LSM_ Specifies the new mode of line capture. + * This parameter can be one of the following values: + * @arg DVP_LINE_CAPTURE_ALL Capture all lines + * @arg DVP_LINE_CAPTURE_1_2 Capture 1 line of each 2 lines + * @arg DVP_LINE_CAPTURE_1_3 Capture 1 line of each 3 lines + * @arg DVP_LINE_CAPTURE_1_4 Capture 1 line of each 4 lines + * @arg DVP_LINE_CAPTURE_1_5 Capture 1 line of each 5 lines + * @arg DVP_LINE_CAPTURE_1_6 Capture 1 line of each 6 lines + * @arg DVP_LINE_CAPTURE_1_7 Capture 1 line of each 7 lines + * @arg DVP_LINE_CAPTURE_1_8 Capture 1 line of each 8 lines + * @retval None + */ +#define __DVP_SetLineCaptureMode(_LSM_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_LSM_MASK, _LSM_)) + +/** + * @brief Config the byte capture mode. + * @param _BSM_ Specifies the new mode of byte capture. + * This parameter can be one of the following values: + * @arg DVP_BYTE_CAPTURE_ALL Capture all pixels + * @arg DVP_BYTE_CAPTURE_1_2 Capture 1 pixel of each 2 pixels + * @arg DVP_BYTE_CAPTURE_1_3 Capture 1 pixel of each 3 pixels + * @arg DVP_BYTE_CAPTURE_1_4 Capture 1 pixel of each 4 pixels + * @arg DVP_BYTE_CAPTURE_1_5 Capture 1 pixel of each 5 pixels + * @arg DVP_BYTE_CAPTURE_1_6 Capture 1 pixel of each 6 pixels + * @arg DVP_BYTE_CAPTURE_1_7 Capture 1 pixel of each 7 pixels + * @arg DVP_BYTE_CAPTURE_1_8 Capture 1 pixel of each 8 pixels + * @retval None + */ +#define __DVP_SetByteCaptureMode(_BSM_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_BSM_MASK, _BSM_)) + +/** + * @brief Config the data invert function. + * @param _INV_ Specifies the data invert or not. + * This parameter can be one of the following values: + * @arg DVP_DATA_INVERT Invert capture data + * @arg DVP_DATA_NOTINVERT Capture data not invert + * @retval None + */ +#define __DVP_SetDataInvert(_INV_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_DATINV_MASK, _INV_)) + +/** + * @brief Config the pixel clock polarity. + * @param _POL_ Specifies the clock edge of pixel clock. + * This parameter can be one of the following values: + * @arg DVP_PIXEL_POLARITY_FALLING Get data at falling edge + * @arg DVP_PIXEL_POLARITY_RISING Get data at rising edge + * @retval None + */ +#define __DVP_SetPclkPol(_POL_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_PCKPOL_MASK, _POL_)) + +/** + * @brief Config the VSYNC polarity. + * @param _POL_ Specifies the active polarity of VSYNC pin. + * This parameter can be one of the following values: + * @arg DVP_VSYNC_POLARITY_HIGH VSYNC active high + * @arg DVP_VSYNC_POLARITY_LOW VSYNC active low + * @retval None + */ +#define __DVP_SetVsyncPol(_POL_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_VSPOL_MASK, _POL_)) + +/** + * @brief Config the HSYNC polarity. + * @param _POL_ Specifies the active polarity of HSYNC pin. + * This parameter can be one of the following values: + * @arg DVP_HSYNC_POLARITY_HIGH VSYNC active high + * @arg DVP_HSYNC_POLARITY_LOW VSYNC active low + * @retval None + */ +#define __DVP_SetHsyncPol(_POL_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_HSPOL_MASK, _POL_)) + +/** + * @brief Config the capture mode. + * @param _POL_ Specifies the new capture mode. + * This parameter can be one of the following values: + * @arg DVP_CAPTURE_MODE_SINGLE Capture one frame + * @arg DVP_CAPTURE_MODE_CONTINUE Capture many frames + * @retval None + */ +#define __DVP_SetCaptureMode(_MODE_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_CM_MASK, _MODE_)) + +/** + * @brief Enable DVP interface. + * @param None + * @retval None + */ +#define __DVP_StartCapture() (SET_BIT(DVP->CTRL, DVP_CAPTURE_ENABLE)) + +/** + * @brief Disable DVP interface. + * @param None + * @retval None + */ +#define __DVP_StopCapture() (CLEAR_BIT(DVP->CTRL, DVP_CAPTURE_ENABLE)) + +/** + * @brief Disable DVP interface. + * @param None + * @retval None + */ +#define __FIFOIsNotEmpty() (READ_BIT(DVP->STS, DVP_STS_FNE)) + +/** + * @brief Checks whether the specified DVP flag is set. + * @param _FLAG_ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg DVP_FLAG_HERR Hsync error interrupt flag + * @arg DVP_FLAG_VERR Vsync error interrupt flag + * @arg DVP_FLAG_FO FIFO overflow intterrupt flag + * @arg DVP_FLAG_FW FIFO watermark interrupt flag + * @arg DVP_FLAG_FF FIFO full interrupt flag + * @arg DVP_FLAG_FE FIFO empty interrupt flag + * @arg DVP_FLAG_LE Line end interrupt flag + * @arg DVP_FLAG_LS Line start interrupt flag + * @arg DVP_FLAG_FME Frame end interrupt flag + * @arg DVP_FLAG_FMS Frame start interrupt flag + * @retval true or false. + */ +#define __DVP_FlagIsSet(_FLAG_) (((DVP->INTSTS) & (_FLAG_))==(_FLAG_)) + +/** + * @brief Checks whether the specified DVP flag is not set. + * @param _FLAG_ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg DVP_FLAG_HERR Hsync error interrupt flag + * @arg DVP_FLAG_VERR Vsync error interrupt flag + * @arg DVP_FLAG_FO FIFO overflow intterrupt flag + * @arg DVP_FLAG_FW FIFO watermark interrupt flag + * @arg DVP_FLAG_FF FIFO full interrupt flag + * @arg DVP_FLAG_FE FIFO empty interrupt flag + * @arg DVP_FLAG_LE Line end interrupt flag + * @arg DVP_FLAG_LS Line start interrupt flag + * @arg DVP_FLAG_FME Frame end interrupt flag + * @arg DVP_FLAG_FMS Frame start interrupt flag + * @retval true or false. + */ +#define __DVP_FlagIsNotSet(_FLAG_) (((DVP->INTSTS) & (_FLAG_))!=(_FLAG_)) + +/** + * @brief Clears the DVP flags. + * @param _FLAG_ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DVP_CLEAR_FLAG_HERR Hsync error interrupt flag clear + * @arg DVP_CLEAR_FLAG_VERR Vsync error interrupt flag clear + * @arg DVP_CLEAR_FLAG_FO FIFO overflow intterrupt flag clear + * @arg DVP_CLEAR_FLAG_FE FIFO empty interrupt flag clear + * @arg DVP_CLEAR_FLAG_LE Line end interrupt flag clear + * @arg DVP_CLEAR_FLAG_LS Line start interrupt flag clear + * @arg DVP_CLEAR_FLAG_FME Frame end interrupt flag clear + * @arg DVP_CLEAR_FLAG_FMS Frame start interrupt flag clear + * @retval None. + */ +#define __DVP_ClrFlag(_FLAG_) (CLEAR_BIT(DVP->INTSTS, _FLAG_)) + +/** + * @brief Enable DVP interrupts. + * @param _INT_ specifies the interrupt to be enable. + * This parameter can be any combination of the following values: + * @arg DVP_INTEN_HERR Hsync error interrupt enable + * @arg DVP_INTEN_VERR Vsync error interrupt enable + * @arg DVP_INTEN_FO FIFO overflow intterrupt enable + * @arg DVP_INTEN_FE FIFO empty interrupt enable + * @arg DVP_INTEN_LE Line end interrupt enable + * @arg DVP_INTEN_LS Line start interrupt enable + * @arg DVP_INTEN_FME Frame end interrupt enable + * @arg DVP_INTEN_FMS Frame start interrupt enable + * @retval None. + */ +#define __DVP_EnableInt(_INT_) (SET_BIT(DVP->INTEN, _INT_)) + +/** + * @brief Disable DVP interrupts. + * @param _INT_ specifies the interrupt to be disable. + * This parameter can be any combination of the following values: + * @arg DVP_INTEN_HERR Hsync error interrupt disable + * @arg DVP_INTEN_VERR Vsync error interrupt disable + * @arg DVP_INTEN_FO FIFO overflow intterrupt disable + * @arg DVP_INTEN_FE FIFO empty interrupt disable + * @arg DVP_INTEN_LE Line end interrupt disable + * @arg DVP_INTEN_LS Line start interrupt disable + * @arg DVP_INTEN_FME Frame end interrupt disable + * @arg DVP_INTEN_FMS Frame start interrupt disable + * @retval None. + */ +#define __DVP_DisableInt(_INT_) (CLEAR_BIT(DVP->INTEN, _INT_)) + +/** + * @brief Enable DVP DMA. + * @param None. + * @retval None. + */ +#define __DVP_EnableDMA() (SET_BIT(DVP->INTEN, DVP_INTEN_DMAEN)) + +/** + * @brief Enable DVP DMA. + * @param None. + * @retval None. + */ +#define __DVP_DisableDMA() (CLEAR_BIT(DVP->INTEN, DVP_INTEN_DMAEN)) + +/** + * @brief Checks whether the specified DVP interrupt has occurred or not. + * @param _INT_ specifies the DVP interrupt source to check. + * This parameter can be one of the following values: + * @arg DVP_MINT_HERR Hsync error interrupt + * @arg DVP_MINT_VERR Vsync error interrupt + * @arg DVP_MINT_FO FIFO overflow intterrupt + * @arg DVP_MINT_FW FIFO watermark interrupt + * @arg DVP_MINT_FF FIFO full interrupt + * @arg DVP_MINT_FE FIFO empty interrupt + * @arg DVP_MINT_LE Line end interrupt + * @arg DVP_MINT_LS Line start interrupt + * @arg DVP_MINT_FME Frame end interrupt + * @arg DVP_MINT_FMS Frame start interrupt + * @retval The state of _INT_ (SET or RESET). + */ +#define __DVP_GetIntMark(_INT_) (((DVP->MINTSTS) & (_INT_))==(_INT_)) + +/** + * @brief Config the positon of first capture pixel . + * @param _VST_ specifies the line positon. + * This parameter must be less than 2048. + * @param _HST_ specifies the pixel positon. + * This parameter must be less than 2048. + * @retval None. + */ +#define __DVP_SetStartSHIFT(_VST_,_HST_) (DVP->WST=((_VST_)<WSIZE=((_VLINE_)<FIFO)) + + +/** + * @} + */ + +/** @addtogroup DVP_Exported_Functions + * @{ + */ +void DVP_DeInit(void); +void DVP_Init(DVP_InitType* DVP_InitStruct); +void DVP_DafaultInitParam(DVP_InitType* DVP_InitStruct); +uint32_t DVP_GetFifoCount(void); +void DVP_ResetFifo(void); +void DVP_ConfigDma( FunctionalState Cmd); + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +#endif diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_eth.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_eth.h new file mode 100644 index 0000000000..4ff243d0ac --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_eth.h @@ -0,0 +1,1608 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @brief Ethernet functions. + * @file n32g45x_eth.h + * @author Nations + * @version v1.0.0 + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __N32G45X_ETH_H__ +#define __N32G45X_ETH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ETH + * @{ + */ + +/** @addtogroup ETH_Exported_Types + * @{ + */ + +/** + * @brief ETH MAC Init structure definition + * @note The user should not configure all the ETH_InitType structure's fields. + * By calling the ETH_InitStruct function the structures fields are set to their default values. + * Only the parameters that will be set to a non-default value should be configured. + */ +typedef struct +{ + uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref AutoNegotiation */ + + uint32_t Watchdog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + uint32_t Jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref Jabber */ + + uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t CarrierSense; /*!< Selects or not the Carrier Sense + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t SpeedMode; /*!< Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref SpeedMode */ + + uint32_t RxOwn; /*!< Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP + headers. This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t BackoffLimit; /*!< Selects the BackOff limit value + This parameter can be a value of @ref ETH_Back_Off_Limit + This parameer only valid in ETH_DUPLEX_MODE_HALF mode*/ + + uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t RxAll; /*!< Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t SrcAddrFilter; /*!< Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t PassCtrlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast Pause + frames) This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t DestAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: + None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: + HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ + + uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ + + uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t PauseLowThreshold; /*!< This field configures the threshold of the Pause to be checked for + automatic retransmission of Pause Frame + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t RxFlowCtrl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t TxFlowCtrl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ + + uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref + ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t RxStoreForward; /*!< Enables or disables the Receive store and forward mode + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t FlushRxFrame; /*!< Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t TxStoreForward; /*!< Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t TxThresholdCtrl; /*!< Selects or not the Transmit Threshold Control + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx DATFIFO to forward Undersized frames (frames + with no Error and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref + ETH_Forward_Undersized_Good_Frames */ + + uint32_t RxThresholdCtrl; /*!< Selects the threshold level of the Receive DATFIFO + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a + second frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t AddrAlignedBeats; /*!< Enables or disables the Address Aligned Beats + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t RxDMABurstLen; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t TxDMABurstLen; /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t DescSkipLen; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + + uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref ETH_DMA_Arbitration */ +} ETH_InitType; + +/** + * @brief ETH DMA Desciptors data structure definition + */ +typedef struct +{ + uint32_t Status; /*!< Status */ + uint32_t CtrlOrBufSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t Buf1Addr; /*!< Buffer1 address pointer */ + uint32_t Buf2OrNextDescAddr; /*!< Buffer2 or next descriptor address pointer */ +} ETH_DMADescType; + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Constants + * @{ + */ + +/** + * @addtogroup ETH_PHY_Registers + * @{ + */ +#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ + +#define PHY_RESET ((u16)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((u16)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGO ((u16)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGO ((u16)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((u16)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((u16)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((u16)0x0020) /*!< Auto-Negotioation process completed */ +#define PHY_LINKED_STATUS ((u16)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((u16)0x0002) /*!< Jabber condition detected */ + +#define PHY_READ_TO ((uint32_t)0x0004FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) < 0x20) +#define IS_ETH_PHY_REG(REG) ((REG) < 0x20) +/** + * @} + */ + +/** @addtogroup ENET_Buffers_setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + ETH_MAX_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /*!< Ethernet CRC */ +#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_PAYLOAD 46 /*!< Minimum Ethernet payload size */ +#define ETH_MAX_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ + +/* + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | Reserved[30:18] | Status[17:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Ctrl[31:22] | Buffer2 ByteCount[21:11] | Buffer1 ByteCount[10:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ----------------------------------------------------------------------------------------------- +*/ + +/* + * Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMA_TX_DESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMA_TX_DESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ +#define ETH_DMA_TX_DESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ +#define ETH_DMA_TX_DESC_ES \ + ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || \ + JT */ +#define ETH_DMA_TX_DESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ +#define ETH_DMA_TX_DESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMA_TX_DESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ +#define ETH_DMA_TX_DESC_LOC ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMA_TX_DESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMA_TX_DESC_LC ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMA_TX_DESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions \ + */ +#define ETH_DMA_TX_DESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ +#define ETH_DMA_TX_DESC_CC ((uint32_t)0x00000078) /*!< Collision Count */ +#define ETH_DMA_TX_DESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ +#define ETH_DMA_TX_DESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMA_TX_DESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ + +/* + * Bit definition of TDES1 register + */ +#define ETH_DMA_TX_DESC_IC ((uint32_t)0x80000000) /*!< Interrupt on Completion */ +#define ETH_DMA_TX_DESC_LS ((uint32_t)0x40000000) /*!< Last Segment */ +#define ETH_DMA_TX_DESC_FS ((uint32_t)0x20000000) /*!< First Segment */ + +#define ETH_DMA_TX_DESC_CIC ((uint32_t)0x18000000) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMA_TX_DESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMA_TX_DESC_CIC_IPV4_HEADER ((uint32_t)0x08000000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMA_TX_DESC_CIC_TCPUDPICMP_SEGMENT \ + ((uint32_t)0x10000000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMA_TX_DESC_CIC_TCPUDPICMP_FULL \ + ((uint32_t)0x18000000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ + +#define ETH_DMA_TX_DESC_DC ((uint32_t)0x04000000) /*!< Disable CRC */ +#define ETH_DMA_TX_DESC_TER ((uint32_t)0x02000000) /*!< Transmit End of Ring */ +#define ETH_DMA_TX_DESC_TCH ((uint32_t)0x01000000) /*!< Second Address Chained */ +#define ETH_DMA_TX_DESC_DP ((uint32_t)0x00800000) /*!< Disable Padding */ +#define ETH_DMA_TX_DESC_TTSE ((uint32_t)0x00400000) /*!< Transmit Time Stamp Enable */ +#define ETH_DMA_TX_DESC_TBS2 ((uint32_t)0x003FF800) /*!< Transmit Buffer2 Size */ +#define ETH_DMA_TX_DESC_TBS1 ((uint32_t)0x000007FF) /*!< Transmit Buffer1 Size */ + +/* + * Bit definition of TDES2 register + */ +#define ETH_DMA_TX_DESC_B1ADDR ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/* + * Bit definition of TDES3 register + */ +#define ETH_DMA_TX_DESC_B2ADDR ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/** + * @} + */ + +/** @addtogroup DMA_Rx_descriptor + * @{ + */ + +/* + DMA Rx Desciptor + -------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:26] | CTRL[25:24] | Reserved[23:22] | Buffer2 ByteCnt[21:11] | Buffer1 ByteCnt[10:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- +*/ + +/* + * Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMA_RX_DESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMA_RX_DESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMA_RX_DESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ +#define ETH_DMA_RX_DESC_ES \ + ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMA_RX_DESC_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */ +#define ETH_DMA_RX_DESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ +#define ETH_DMA_RX_DESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ +#define ETH_DMA_RX_DESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMA_RX_DESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMA_RX_DESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ +#define ETH_DMA_RX_DESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ +#define ETH_DMA_RX_DESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMA_RX_DESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ +#define ETH_DMA_RX_DESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMA_RX_DESC_RWT \ + ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMA_RX_DESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ +#define ETH_DMA_RX_DESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits \ + */ +#define ETH_DMA_RX_DESC_CE ((uint32_t)0x00000002) /*!< CRC error */ +#define ETH_DMA_RX_DESC_RMAPCE \ + ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum \ + Error */ + +/* + * Bit definition of RDES1 register + */ +#define ETH_DMA_RX_DESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ +#define ETH_DMA_RX_DESC_RBS2 ((uint32_t)0x003FF800) /*!< Receive Buffer2 Size */ +#define ETH_DMA_RX_DESC_RER ((uint32_t)0x02000000) /*!< Receive End of Ring */ +#define ETH_DMA_RX_DESC_RCH ((uint32_t)0x01000000) /*!< Second Address Chained */ +#define ETH_DMA_RX_DESC_RBS1 ((uint32_t)0x000007FF) /*!< Receive Buffer1 Size */ + +/* + * Bit definition of RDES2 register + */ +#define ETH_DMA_RX_DESC_B1ADDR ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/* + * Bit definition of RDES3 register + */ +#define ETH_DMA_RX_DESC_B2ADDR ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/** + * @} + */ + +/** @addtogroup AutoNegotiation + * @{ + */ +#define ETH_AUTONEG_ENABLE ((uint32_t)0x00000001) +#define ETH_AUTONEG_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_AUTONEG(CMDCTRL) (((CMDCTRL) == ETH_AUTONEG_ENABLE) || ((CMDCTRL) == ETH_AUTONEG_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_watchdog + * @{ + */ +#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000) +#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000) +#define IS_ETH_WATCHDOG(CMDCTRL) (((CMDCTRL) == ETH_WATCHDOG_ENABLE) || ((CMDCTRL) == ETH_WATCHDOG_DISABLE)) + +/** + * @} + */ + +/** @addtogroup Jabber + * @{ + */ +#define ETH_JABBER_ENABLE ((uint32_t)0x00000000) +#define ETH_JABBER_DISABLE ((uint32_t)0x00400000) +#define IS_ETH_JABBER(CMDCTRL) (((CMDCTRL) == ETH_JABBER_ENABLE) || ((CMDCTRL) == ETH_JABBER_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Inter_Frame_Gap + * @{ + */ +#define ETH_INTER_FRAME_GAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit \ + */ +#define ETH_INTER_FRAME_GAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit \ + */ +#define ETH_INTER_FRAME_GAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit \ + */ +#define ETH_INTER_FRAME_GAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit \ + */ +#define ETH_INTER_FRAME_GAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit \ + */ +#define ETH_INTER_FRAME_GAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit \ + */ +#define ETH_INTER_FRAME_GAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit \ + */ +#define ETH_INTER_FRAME_GAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit \ + */ +#define IS_ETH_INTER_FRAME_GAP(GAP) \ + (((GAP) == ETH_INTER_FRAME_GAP_96BIT) || ((GAP) == ETH_INTER_FRAME_GAP_88BIT) \ + || ((GAP) == ETH_INTER_FRAME_GAP_80BIT) || ((GAP) == ETH_INTER_FRAME_GAP_72BIT) \ + || ((GAP) == ETH_INTER_FRAME_GAP_64BIT) || ((GAP) == ETH_INTER_FRAME_GAP_56BIT) \ + || ((GAP) == ETH_INTER_FRAME_GAP_48BIT) || ((GAP) == ETH_INTER_FRAME_GAP_40BIT)) + +/** + * @} + */ + +/** @addtogroup ETH_Carrier_Sense + * @{ + */ +#define ETH_CARRIER_SENSE_ENABLE ((uint32_t)0x00000000) +#define ETH_CARRIER_SENSE_DISABLE ((uint32_t)0x00010000) +#define IS_ETH_CARRIER_SENSE(CMDCTRL) \ + (((CMDCTRL) == ETH_CARRIER_SENSE_ENABLE) || ((CMDCTRL) == ETH_CARRIER_SENSE_DISABLE)) + +/** + * @} + */ + +/** @addtogroup SpeedMode + * @{ + */ +#define ETH_SPEED_MODE_10M ((uint32_t)0x00000000) +#define ETH_SPEED_MODE_100M ((uint32_t)0x00004000) +#define IS_ETH_SPEED_MODE(SPEED) (((SPEED) == ETH_SPEED_MODE_10M) || ((SPEED) == ETH_SPEED_MODE_100M)) + +/** + * @} + */ + +/** @addtogroup ETH_Receive_Own + * @{ + */ +#define ETH_RX_OWN_ENABLE ((uint32_t)0x00000000) +#define ETH_RX_OWN_DISABLE ((uint32_t)0x00002000) +#define IS_ETH_RX_OWN(CMDCTRL) (((CMDCTRL) == ETH_RX_OWN_ENABLE) || ((CMDCTRL) == ETH_RX_OWN_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Loop_Back_Mode + * @{ + */ +#define ETH_LOOPBACK_MODE_ENABLE ((uint32_t)0x00001000) +#define ETH_LOOPBACK_MODE_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_LOOPBACK_MODE(CMDCTRL) \ + (((CMDCTRL) == ETH_LOOPBACK_MODE_ENABLE) || ((CMDCTRL) == ETH_LOOPBACK_MODE_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Duplex_Mode + * @{ + */ +#define ETH_DUPLEX_MODE_FULL ((uint32_t)0x00000800) +#define ETH_DUPLEX_MODE_HALF ((uint32_t)0x00000000) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_DUPLEX_MODE_FULL) || ((MODE) == ETH_DUPLEX_MODE_HALF)) + +/** + * @} + */ + +/** @addtogroup ETH_Checksum_Offload + * @{ + */ +#define ETH_CHECKSUM_OFFLOAD_ENABLE ((uint32_t)0x00000400) +#define ETH_CHECKSUM_OFFLOAD_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_CHECKSUM_OFFLOAD(CMDCTRL) \ + (((CMDCTRL) == ETH_CHECKSUM_OFFLOAD_ENABLE) || ((CMDCTRL) == ETH_CHECKSUM_OFFLOAD_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Retry_Transmission + * @{ + */ +#define ETH_RETRY_TRANSMISSION_ENABLE ((uint32_t)0x00000000) +#define ETH_RETRY_TRANSMISSION_DISABLE ((uint32_t)0x00000200) +#define IS_ETH_RETRY_TRANSMISSION(CMDCTRL) \ + (((CMDCTRL) == ETH_RETRY_TRANSMISSION_ENABLE) || ((CMDCTRL) == ETH_RETRY_TRANSMISSION_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Automatic_Pad_CRC_Strip + * @{ + */ +#define ETH_AUTO_PAD_CRC_STRIP_ENABLE ((uint32_t)0x00000080) +#define ETH_AUTO_PAD_CRC_STRIP_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_AUTO_PAD_CRC_STRIP(CMDCTRL) \ + (((CMDCTRL) == ETH_AUTO_PAD_CRC_STRIP_ENABLE) || ((CMDCTRL) == ETH_AUTO_PAD_CRC_STRIP_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Back_Off_Limit + * @{ + */ +#define ETH_BACKOFF_LIMIT_10 ((uint32_t)0x00000000) +#define ETH_BACKOFF_LIMIT_8 ((uint32_t)0x00000020) +#define ETH_BACKOFF_LIMIT_4 ((uint32_t)0x00000040) +#define ETH_BACKOFF_LIMIT_1 ((uint32_t)0x00000060) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) \ + (((LIMIT) == ETH_BACKOFF_LIMIT_10) || ((LIMIT) == ETH_BACKOFF_LIMIT_8) || ((LIMIT) == ETH_BACKOFF_LIMIT_4) \ + || ((LIMIT) == ETH_BACKOFF_LIMIT_1)) + +/** + * @} + */ + +/** @addtogroup ETH_Deferral_Check + * @{ + */ +#define ETH_DEFERRAL_CHECK_ENABLE ((uint32_t)0x00000010) +#define ETH_DEFERRAL_CHECK_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_DEFERRAL_CHECK(CMDCTRL) \ + (((CMDCTRL) == ETH_DEFERRAL_CHECK_ENABLE) || ((CMDCTRL) == ETH_DEFERRAL_CHECK_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Receive_All + * @{ + */ +#define ETH_RX_ALL_ENABLE ((uint32_t)0x80000000) +#define ETH_RX_ALL_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_RX_ALL(CMDCTRL) (((CMDCTRL) == ETH_RX_ALL_ENABLE) || ((CMDCTRL) == ETH_RX_ALL_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Source_Addr_Filter + * @{ + */ +#define ETH_SRC_ADDR_FILTER_NORMAL_ENABLE ((uint32_t)0x00000200) +#define ETH_SRC_ADDR_FILTER_INVERSE_ENABLE ((uint32_t)0x00000300) +#define ETH_SRC_ADDR_FILTER_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_SRC_ADDR_FILTER(CMDCTRL) \ + (((CMDCTRL) == ETH_SRC_ADDR_FILTER_NORMAL_ENABLE) || ((CMDCTRL) == ETH_SRC_ADDR_FILTER_INVERSE_ENABLE) \ + || ((CMDCTRL) == ETH_SRC_ADDR_FILTER_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Pass_Control_Frames + * @{ + */ +#define ETH_PASS_CTRL_FRAMES_BLOCK_ALL \ + ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PASS_CTRL_FRAMES_FORWARD_ALL \ + ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PASS_CTRL_FRAMES_FORWARD_PASSED_ADDR_FILTER \ + ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define IS_ETH_PASS_CTRL_FRAMES(PASS) \ + (((PASS) == ETH_PASS_CTRL_FRAMES_BLOCK_ALL) || ((PASS) == ETH_PASS_CTRL_FRAMES_FORWARD_ALL) \ + || ((PASS) == ETH_PASS_CTRL_FRAMES_FORWARD_PASSED_ADDR_FILTER)) + +/** + * @} + */ + +/** @addtogroup ETH_Broadcast_Frames_Reception + * @{ + */ +#define ETH_BROADCAST_FRAMES_RECEPTION_ENABLE ((uint32_t)0x00000000) +#define ETH_BROADCAST_FRAMES_RECEPTION_DISABLE ((uint32_t)0x00000020) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMDCTRL) \ + (((CMDCTRL) == ETH_BROADCAST_FRAMES_RECEPTION_ENABLE) || ((CMDCTRL) == ETH_BROADCAST_FRAMES_RECEPTION_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Destination_Addr_Filter + * @{ + */ +#define ETH_DEST_ADDR_FILTER_NORMAL ((uint32_t)0x00000000) +#define ETH_DEST_ADDR_FILTER_INVERSE ((uint32_t)0x00000008) +#define IS_ETH_DEST_ADDR_FILTER(FILTER) \ + (((FILTER) == ETH_DEST_ADDR_FILTER_NORMAL) || ((FILTER) == ETH_DEST_ADDR_FILTER_INVERSE)) + +/** + * @} + */ + +/** @addtogroup ETH_Promiscuous_Mode + * @{ + */ +#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001) +#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_PROMISCUOUS_MODE(CMDCTRL) \ + (((CMDCTRL) == ETH_PROMISCUOUS_MODE_ENABLE) || ((CMDCTRL) == ETH_PROMISCUOUS_MODE_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Multicast_Frames_Filter + * @{ + */ +#define ETH_MULTICAST_FRAMES_FILTER_PERFECT_HASH_TABLE ((uint32_t)0x00000404) +#define ETH_MULTICAST_FRAMES_FILTER_HASH_TABLE ((uint32_t)0x00000004) +#define ETH_MULTICAST_FRAMES_FILTER_PERFECT ((uint32_t)0x00000000) +#define ETH_MULTICAST_FRAMES_FILTER_NONE ((uint32_t)0x00000010) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) \ + (((FILTER) == ETH_MULTICAST_FRAMES_FILTER_PERFECT_HASH_TABLE) \ + || ((FILTER) == ETH_MULTICAST_FRAMES_FILTER_HASH_TABLE) || ((FILTER) == ETH_MULTICAST_FRAMES_FILTER_PERFECT) \ + || ((FILTER) == ETH_MULTICAST_FRAMES_FILTER_NONE)) + +/** + * @} + */ + +/** @addtogroup ETH_Unicast_Frames_Filter + * @{ + */ +#define ETH_UNICAST_FRAMES_FILTER_PERFECTHASHTABLE ((uint32_t)0x00000402) +#define ETH_UNICAST_FRAMES_FILTER_HASHTABLE ((uint32_t)0x00000002) +#define ETH_UNICAST_FRAMES_FILTER_PERFECT ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) \ + (((FILTER) == ETH_UNICAST_FRAMES_FILTER_PERFECTHASHTABLE) || ((FILTER) == ETH_UNICAST_FRAMES_FILTER_HASHTABLE) \ + || ((FILTER) == ETH_UNICAST_FRAMES_FILTER_PERFECT)) + +/** + * @} + */ + +/** @addtogroup ETH_Pause_Time + * @{ + */ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/** + * @} + */ + +/** @addtogroup ETH_Zero_Quanta_Pause + * @{ + */ +#define ETH_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000) +#define ETH_ZERO_QUANTA_PAUSE_DISABLE ((uint32_t)0x00000080) +#define IS_ETH_ZERO_QUANTA_PAUSE(CMDCTRL) \ + (((CMDCTRL) == ETH_ZERO_QUANTA_PAUSE_ENABLE) || ((CMDCTRL) == ETH_ZERO_QUANTA_PAUSE_DISABLE)) +/** + * @} + */ + +/** @addtogroup ETH_Pause_Low_Threshold + * @{ + */ +#define ETH_PAUSE_LOW_THRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ +#define ETH_PAUSE_LOW_THRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ +#define ETH_PAUSE_LOW_THRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ +#define ETH_PAUSE_LOW_THRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) \ + (((THRESHOLD) == ETH_PAUSE_LOW_THRESHOLD_MINUS4) || ((THRESHOLD) == ETH_PAUSE_LOW_THRESHOLD_MINUS28) \ + || ((THRESHOLD) == ETH_PAUSE_LOW_THRESHOLD_MINUS144) || ((THRESHOLD) == ETH_PAUSE_LOW_THRESHOLD_MINUS256)) + +/** + * @} + */ + +/** @addtogroup ETH_Unicast_Pause_Frame_Detect + * @{ + */ +#define ETH_UNICAST_PAUSE_FRAME_DETECT_ENABLE ((uint32_t)0x00000008) +#define ETH_UNICAST_PAUSE_FRAME_DETECT_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMDCTRL) \ + (((CMDCTRL) == ETH_UNICAST_PAUSE_FRAME_DETECT_ENABLE) || ((CMDCTRL) == ETH_UNICAST_PAUSE_FRAME_DETECT_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Receive_Flow_Control + * @{ + */ +#define ETH_RX_FLOW_CTRL_ENABLE ((uint32_t)0x00000004) +#define ETH_RX_FLOW_CTRL_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_RX_FLOW_CTRL(CMDCTRL) (((CMDCTRL) == ETH_RX_FLOW_CTRL_ENABLE) || ((CMDCTRL) == ETH_RX_FLOW_CTRL_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Transmit_Flow_Control + * @{ + */ +#define ETH_TX_FLOW_CTRL_ENABLE ((uint32_t)0x00000002) +#define ETH_TX_FLOW_CTRL_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_TX_FLOW_CTRL(CMDCTRL) (((CMDCTRL) == ETH_TX_FLOW_CTRL_ENABLE) || ((CMDCTRL) == ETH_TX_FLOW_CTRL_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_VLAN_Tag_Comparison + * @{ + */ +#define ETH_VLAN_TAG_COMPARISON_12BIT ((uint32_t)0x00010000) +#define ETH_VLAN_TAG_COMPARISON_16BIT ((uint32_t)0x00000000) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) \ + (((COMPARISON) == ETH_VLAN_TAG_COMPARISON_12BIT) || ((COMPARISON) == ETH_VLAN_TAG_COMPARISON_16BIT)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/** + * @} + */ + +/** @addtogroup ETH_MAC_Flags + * @{ + */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCTX ((uint32_t)0x00000040) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCRX ((uint32_t)0x00000020) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ +#define IS_ETH_MAC_GET_FLAG(FLAG) \ + (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCTX) || ((FLAG) == ETH_MAC_FLAG_MMCRX) \ + || ((FLAG) == ETH_MAC_FLAG_MMC) || ((FLAG) == ETH_MAC_FLAG_PMT)) +/** + * @} + */ + +/** @addtogroup ETH_MAC_Interrupts + * @{ + */ +#define ETH_MAC_INT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_INT_MMCTX ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ +#define ETH_MAC_INT_MMCRX ((uint32_t)0x00000020) /*!< MMC receive interrupt */ +#define ETH_MAC_INT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_INT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ +#define IS_ETH_MAC_INT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_INT(IT) \ + (((IT) == ETH_MAC_INT_TST) || ((IT) == ETH_MAC_INT_MMCTX) || ((IT) == ETH_MAC_INT_MMCRX) \ + || ((IT) == ETH_MAC_INT_MMC) || ((IT) == ETH_MAC_INT_PMT)) +/** + * @} + */ + +/** @addtogroup ETH_MAC_addresses + * @{ + */ +#define ETH_MAC_ADDR0 ((uint32_t)0x00000000) +#define ETH_MAC_ADDR1 ((uint32_t)0x00000008) +#define ETH_MAC_ADDR2 ((uint32_t)0x00000010) +#define ETH_MAC_ADDR3 ((uint32_t)0x00000018) +#define IS_ETH_MAC_ADDR0123(ADDRESS) \ + (((ADDRESS) == ETH_MAC_ADDR0) || ((ADDRESS) == ETH_MAC_ADDR1) || ((ADDRESS) == ETH_MAC_ADDR2) \ + || ((ADDRESS) == ETH_MAC_ADDR3)) +#define IS_ETH_MAC_ADDR123(ADDRESS) \ + (((ADDRESS) == ETH_MAC_ADDR1) || ((ADDRESS) == ETH_MAC_ADDR2) || ((ADDRESS) == ETH_MAC_ADDR3)) +/** + * @} + */ + +/** @addtogroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames + * @{ + */ +#define ETH_MAC_ADDR_FILTER_SA ((uint32_t)0x00000000) +#define ETH_MAC_ADDR_FILTER_DA ((uint32_t)0x00000008) +#define IS_ETH_MAC_ADDR_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDR_FILTER_SA) || ((FILTER) == ETH_MAC_ADDR_FILTER_DA)) +/** + * @} + */ + +/** @addtogroup ETH_MAC_addresses_filter_Mask_bytes + * @{ + */ +#define ETH_MAC_ADDR_MASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_ADDR_MASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_ADDR_MASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_ADDR_MASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_ADDR_MASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_ADDR_MASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ +#define IS_ETH_MAC_ADDR_MASK(INTEN) \ + (((INTEN) == ETH_MAC_ADDR_MASK_BYTE6) || ((INTEN) == ETH_MAC_ADDR_MASK_BYTE5) \ + || ((INTEN) == ETH_MAC_ADDR_MASK_BYTE4) || ((INTEN) == ETH_MAC_ADDR_MASK_BYTE3) \ + || ((INTEN) == ETH_MAC_ADDR_MASK_BYTE2) || ((INTEN) == ETH_MAC_ADDR_MASK_BYTE1)) + +/** + * @} + */ + +/** @addtogroup ETH_DMA_Tx_descriptor_flags + * @{ + */ +#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) \ + (((FLAG) == ETH_DMA_TX_DESC_OWN) || ((FLAG) == ETH_DMA_TX_DESC_IC) || ((FLAG) == ETH_DMA_TX_DESC_LS) \ + || ((FLAG) == ETH_DMA_TX_DESC_FS) || ((FLAG) == ETH_DMA_TX_DESC_DC) || ((FLAG) == ETH_DMA_TX_DESC_DP) \ + || ((FLAG) == ETH_DMA_TX_DESC_TTSE) || ((FLAG) == ETH_DMA_TX_DESC_TER) || ((FLAG) == ETH_DMA_TX_DESC_TCH) \ + || ((FLAG) == ETH_DMA_TX_DESC_TTSS) || ((FLAG) == ETH_DMA_TX_DESC_IHE) || ((FLAG) == ETH_DMA_TX_DESC_ES) \ + || ((FLAG) == ETH_DMA_TX_DESC_JT) || ((FLAG) == ETH_DMA_TX_DESC_FF) || ((FLAG) == ETH_DMA_TX_DESC_PCE) \ + || ((FLAG) == ETH_DMA_TX_DESC_LOC) || ((FLAG) == ETH_DMA_TX_DESC_NC) || ((FLAG) == ETH_DMA_TX_DESC_LC) \ + || ((FLAG) == ETH_DMA_TX_DESC_EC) || ((FLAG) == ETH_DMA_TX_DESC_VF) || ((FLAG) == ETH_DMA_TX_DESC_CC) \ + || ((FLAG) == ETH_DMA_TX_DESC_ED) || ((FLAG) == ETH_DMA_TX_DESC_UF) || ((FLAG) == ETH_DMA_TX_DESC_DB)) + +/** + * @} + */ + +/** @addtogroup ETH_DMA_Tx_descriptor_segment + * @{ + */ +#define ETH_DMA_TX_DESC_LAST_SEGMENT ((uint32_t)0x40000000) /*!< Last Segment */ +#define ETH_DMA_TX_DESC_FIRST_SEGMENT ((uint32_t)0x20000000) /*!< First Segment */ +#define IS_ETH_DMA_TX_DESC_SEGMENT(SEGMENT) \ + (((SEGMENT) == ETH_DMA_TX_DESC_LAST_SEGMENT) || ((SEGMENT) == ETH_DMA_TX_DESC_FIRST_SEGMENT)) + +/** + * @} + */ + +/** @addtogroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control + * @{ + */ +#define ETH_DMA_TX_DESC_CHECKSUM_BYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */ +#define ETH_DMA_TX_DESC_CHECKSUM_IPV4_HEADER ((uint32_t)0x08000000) /*!< IPv4 header checksum insertion */ +#define ETH_DMA_TX_DESC_CHECKSUM_TCPUDPICMP_SEGMENT \ + ((uint32_t)0x10000000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMA_TX_DESC_CHECKSUM_TCPUDPICMP_FULL \ + ((uint32_t)0x18000000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +#define IS_ETH_DMA_TX_DESC_CHECKSUM(CHECKSUM) \ + (((CHECKSUM) == ETH_DMA_TX_DESC_CHECKSUM_BYPASS) || ((CHECKSUM) == ETH_DMA_TX_DESC_CHECKSUM_IPV4_HEADER) \ + || ((CHECKSUM) == ETH_DMA_TX_DESC_CHECKSUM_TCPUDPICMP_SEGMENT) \ + || ((CHECKSUM) == ETH_DMA_TX_DESC_CHECKSUM_TCPUDPICMP_FULL)) + +#define IS_ETH_DMA_TX_DESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/** + * @} + */ + +/** @addtogroup ETH_DMA_Rx_descriptor_flags + * @{ + */ +#define IS_ETH_DMA_RX_DESC_GET_FLAG(FLAG) \ + (((FLAG) == ETH_DMA_RX_DESC_OWN) || ((FLAG) == ETH_DMA_RX_DESC_AFM) || ((FLAG) == ETH_DMA_RX_DESC_ES) \ + || ((FLAG) == ETH_DMA_RX_DESC_DE) || ((FLAG) == ETH_DMA_RX_DESC_SAF) || ((FLAG) == ETH_DMA_RX_DESC_LE) \ + || ((FLAG) == ETH_DMA_RX_DESC_OE) || ((FLAG) == ETH_DMA_RX_DESC_VLAN) || ((FLAG) == ETH_DMA_RX_DESC_FS) \ + || ((FLAG) == ETH_DMA_RX_DESC_LS) || ((FLAG) == ETH_DMA_RX_DESC_IPV4HCE) || ((FLAG) == ETH_DMA_RX_DESC_LC) \ + || ((FLAG) == ETH_DMA_RX_DESC_FT) || ((FLAG) == ETH_DMA_RX_DESC_RWT) || ((FLAG) == ETH_DMA_RX_DESC_RE) \ + || ((FLAG) == ETH_DMA_RX_DESC_DBE) || ((FLAG) == ETH_DMA_RX_DESC_CE) || ((FLAG) == ETH_DMA_RX_DESC_RMAPCE)) + +/** + * @} + */ + +/** @addtogroup ETH_DMA_Rx_descriptor_buffers_ + * @{ + */ +#define ETH_DMA_RX_DESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMA_RX_DESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) \ + (((BUFFER) == ETH_DMA_RX_DESC_BUFFER1) || ((BUFFER) == ETH_DMA_RX_DESC_BUFFER2)) + +/** + * @} + */ + +/** @addtogroup ETH_Drop_TCP_IP_Checksum_Error_Frame + * @{ + */ +#define ETH_DROP_TCPIP_CHECKSUM_ERROR_FRAME_ENABLE ((uint32_t)0x00000000) +#define ETH_DROP_TCPIP_CHECKSUM_ERROR_FRAME_DISABLE ((uint32_t)0x04000000) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMDCTRL) \ + (((CMDCTRL) == ETH_DROP_TCPIP_CHECKSUM_ERROR_FRAME_ENABLE) \ + || ((CMDCTRL) == ETH_DROP_TCPIP_CHECKSUM_ERROR_FRAME_DISABLE)) +/** + * @} + */ + +/** @addtogroup ETH_Receive_Store_Forward + * @{ + */ +#define ETH_RX_STORE_FORWARD_ENABLE ((uint32_t)0x02000000) +#define ETH_RX_STORE_FORWARD_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_RX_STORE_FORWARD(CMDCTRL) \ + (((CMDCTRL) == ETH_RX_STORE_FORWARD_ENABLE) || ((CMDCTRL) == ETH_RX_STORE_FORWARD_DISABLE)) +/** + * @} + */ + +/** @addtogroup ETH_Flush_Received_Frame + * @{ + */ +#define ETH_FLUSH_RX_FRAME_ENABLE ((uint32_t)0x00000000) +#define ETH_FLUSH_RX_FRAME_DISABLE ((uint32_t)0x01000000) +#define IS_ETH_FLUSH_RX_FRAME(CMDCTRL) \ + (((CMDCTRL) == ETH_FLUSH_RX_FRAME_ENABLE) || ((CMDCTRL) == ETH_FLUSH_RX_FRAME_DISABLE)) +/** + * @} + */ + +/** @addtogroup ETH_Transmit_Store_Forward + * @{ + */ +#define ETH_TX_STORE_FORWARD_ENABLE ((uint32_t)0x00200000) +#define ETH_TX_STORE_FORWARD_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_TX_STORE_FORWARD(CMDCTRL) \ + (((CMDCTRL) == ETH_TX_STORE_FORWARD_ENABLE) || ((CMDCTRL) == ETH_TX_STORE_FORWARD_DISABLE)) +/** + * @} + */ + +/** @addtogroup ETH_Transmit_Threshold_Control + * @{ + */ +#define ETH_TX_THRESHOLD_CTRL_64BYTES \ + ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit DATFIFO is 64 Bytes */ +#define ETH_TX_THRESHOLD_CTRL_128BYTES \ + ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit DATFIFO is 128 Bytes */ +#define ETH_TX_THRESHOLD_CTRL_192BYTES \ + ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit DATFIFO is 192 Bytes */ +#define ETH_TX_THRESHOLD_CTRL_256BYTES \ + ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit DATFIFO is 256 Bytes */ +#define ETH_TX_THRESHOLD_CTRL_40BYTES \ + ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit DATFIFO is 40 Bytes */ +#define ETH_TX_THRESHOLD_CTRL_32BYTES \ + ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit DATFIFO is 32 Bytes */ +#define ETH_TX_THRESHOLD_CTRL_24BYTES \ + ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit DATFIFO is 24 Bytes */ +#define ETH_TX_THRESHOLD_CTRL_16BYTES \ + ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit DATFIFO is 16 Bytes */ +#define IS_ETH_TX_THRESHOLD_CTRL(THRESHOLD) \ + (((THRESHOLD) == ETH_TX_THRESHOLD_CTRL_64BYTES) || ((THRESHOLD) == ETH_TX_THRESHOLD_CTRL_128BYTES) \ + || ((THRESHOLD) == ETH_TX_THRESHOLD_CTRL_192BYTES) || ((THRESHOLD) == ETH_TX_THRESHOLD_CTRL_256BYTES) \ + || ((THRESHOLD) == ETH_TX_THRESHOLD_CTRL_40BYTES) || ((THRESHOLD) == ETH_TX_THRESHOLD_CTRL_32BYTES) \ + || ((THRESHOLD) == ETH_TX_THRESHOLD_CTRL_24BYTES) || ((THRESHOLD) == ETH_TX_THRESHOLD_CTRL_16BYTES)) +/** + * @} + */ + +/** @addtogroup ETH_Forward_Error_Frames + * @{ + */ +#define ETH_FORWARD_ERROR_FRAMES_ENABLE ((uint32_t)0x00000080) +#define ETH_FORWARD_ERROR_FRAMES_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMDCTRL) \ + (((CMDCTRL) == ETH_FORWARD_ERROR_FRAMES_ENABLE) || ((CMDCTRL) == ETH_FORWARD_ERROR_FRAMES_DISABLE)) +/** + * @} + */ + +/** @addtogroup ETH_Forward_Undersized_Good_Frames + * @{ + */ +#define ETH_FORWARD_UNDERSIZED_GOOD_FRAMES_ENABLE ((uint32_t)0x00000040) +#define ETH_FORWARD_UNDERSIZED_GOOD_FRAMES_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMDCTRL) \ + (((CMDCTRL) == ETH_FORWARD_UNDERSIZED_GOOD_FRAMES_ENABLE) \ + || ((CMDCTRL) == ETH_FORWARD_UNDERSIZED_GOOD_FRAMES_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Receive_Threshold_Control + * @{ + */ +#define ETH_RX_THRESHOLD_CTRL_64BYTES \ + ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive DATFIFO is 64 Bytes */ +#define ETH_RX_THRESHOLD_CTRL_32BYTES \ + ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive DATFIFO is 32 Bytes */ +#define ETH_RX_THRESHOLD_CTRL_96BYTES \ + ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive DATFIFO is 96 Bytes */ +#define ETH_RX_THRESHOLD_CTRL_128BYTES \ + ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive DATFIFO is 128 Bytes */ +#define IS_ETH_RX_THRESHOLD_CTRL(THRESHOLD) \ + (((THRESHOLD) == ETH_RX_THRESHOLD_CTRL_64BYTES) || ((THRESHOLD) == ETH_RX_THRESHOLD_CTRL_32BYTES) \ + || ((THRESHOLD) == ETH_RX_THRESHOLD_CTRL_96BYTES) || ((THRESHOLD) == ETH_RX_THRESHOLD_CTRL_128BYTES)) +/** + * @} + */ + +/** @addtogroup ETH_Second_Frame_Operate + * @{ + */ +#define ETH_SECOND_FRAME_OPERATE_ENABLE ((uint32_t)0x00000004) +#define ETH_SECOND_FRAME_OPERATE_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_SECOND_FRAME_OPERATE(CMDCTRL) \ + (((CMDCTRL) == ETH_SECOND_FRAME_OPERATE_ENABLE) || ((CMDCTRL) == ETH_SECOND_FRAME_OPERATE_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Address_Aligned_Beats + * @{ + */ +#define ETH_ADDR_ALIGNED_BEATS_ENABLE ((uint32_t)0x02000000) +#define ETH_ADDR_ALIGNED_BEATS_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_ADDR_ALIGNED_BEATS(CMDCTRL) \ + (((CMDCTRL) == ETH_ADDR_ALIGNED_BEATS_ENABLE) || ((CMDCTRL) == ETH_ADDR_ALIGNED_BEATS_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Fixed_Burst + * @{ + */ +#define ETH_FIXED_BURST_ENABLE ((uint32_t)0x00010000) +#define ETH_FIXED_BURST_DISABLE ((uint32_t)0x00000000) +#define IS_ETH_FIXED_BURST(CMDCTRL) (((CMDCTRL) == ETH_FIXED_BURST_ENABLE) || ((CMDCTRL) == ETH_FIXED_BURST_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Rx_DMA_Burst_Length + * @{ + */ +#define ETH_RX_DMA_BURST_LEN_1BEAT \ + ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RX_DMA_BURST_LEN_2BEAT \ + ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RX_DMA_BURST_LEN_4BEAT \ + ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RX_DMA_BURST_LEN_8BEAT \ + ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RX_DMA_BURST_LEN_16BEAT \ + ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RX_DMA_BURST_LEN_32BEAT \ + ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RX_DMA_BURST_LEN_PBLX8_8BEAT \ + ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RX_DMA_BURST_LEN_PBLX8_16BEAT \ + ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RX_DMA_BURST_LEN_PBLX8_32BEAT \ + ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RX_DMA_BURST_LEN_PBLX8_64BEAT \ + ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RX_DMA_BURST_LEN_PBLX8_128BEAT \ + ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RX_DMA_BURST_LEN_PBLX8_256BEAT \ + ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define IS_ETH_RX_DMA_BURST_LEN(LENGTH) \ + (((LENGTH) == ETH_RX_DMA_BURST_LEN_1BEAT) || ((LENGTH) == ETH_RX_DMA_BURST_LEN_2BEAT) \ + || ((LENGTH) == ETH_RX_DMA_BURST_LEN_4BEAT) || ((LENGTH) == ETH_RX_DMA_BURST_LEN_8BEAT) \ + || ((LENGTH) == ETH_RX_DMA_BURST_LEN_16BEAT) || ((LENGTH) == ETH_RX_DMA_BURST_LEN_32BEAT) \ + || ((LENGTH) == ETH_RX_DMA_BURST_LEN_PBLX8_8BEAT) || ((LENGTH) == ETH_RX_DMA_BURST_LEN_PBLX8_16BEAT) \ + || ((LENGTH) == ETH_RX_DMA_BURST_LEN_PBLX8_32BEAT) || ((LENGTH) == ETH_RX_DMA_BURST_LEN_PBLX8_64BEAT) \ + || ((LENGTH) == ETH_RX_DMA_BURST_LEN_PBLX8_128BEAT) || ((LENGTH) == ETH_RX_DMA_BURST_LEN_PBLX8_256BEAT)) + +/** + * @} + */ + +/** @addtogroup ETH_Tx_DMA_Burst_Length + * @{ + */ +#define ETH_TX_DMA_BURST_LEN_1BEAT \ + ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TX_DMA_BURST_LEN_2BEAT \ + ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TX_DMA_BURST_LEN_4BEAT \ + ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TX_DMA_BURST_LEN_8BEAT \ + ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TX_DMA_BURST_LEN_16BEAT \ + ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TX_DMA_BURST_LEN_32BEAT \ + ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TX_DMA_BURST_LEN_PBLX8_8BEAT \ + ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TX_DMA_BURST_LEN_PBLX8_16BEAT \ + ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TX_DMA_BURST_LEN_PBLX8_32BEAT \ + ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TX_DMA_BURST_LEN_PBLX8_64BEAT \ + ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TX_DMA_BURST_LEN_PBLX8_128BEAT \ + ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TX_DMA_BURST_LEN_PBLX8_256BEAT \ + ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define IS_ETH_TX_DMA_BURST_LEN(LENGTH) \ + (((LENGTH) == ETH_TX_DMA_BURST_LEN_1BEAT) || ((LENGTH) == ETH_TX_DMA_BURST_LEN_2BEAT) \ + || ((LENGTH) == ETH_TX_DMA_BURST_LEN_4BEAT) || ((LENGTH) == ETH_TX_DMA_BURST_LEN_8BEAT) \ + || ((LENGTH) == ETH_TX_DMA_BURST_LEN_16BEAT) || ((LENGTH) == ETH_TX_DMA_BURST_LEN_32BEAT) \ + || ((LENGTH) == ETH_TX_DMA_BURST_LEN_PBLX8_8BEAT) || ((LENGTH) == ETH_TX_DMA_BURST_LEN_PBLX8_16BEAT) \ + || ((LENGTH) == ETH_TX_DMA_BURST_LEN_PBLX8_32BEAT) || ((LENGTH) == ETH_TX_DMA_BURST_LEN_PBLX8_64BEAT) \ + || ((LENGTH) == ETH_TX_DMA_BURST_LEN_PBLX8_128BEAT) || ((LENGTH) == ETH_TX_DMA_BURST_LEN_PBLX8_256BEAT)) + +#define IS_ETH_DMA_DESC_SKIP_LEN(LENGTH) ((LENGTH) <= 0x1F) + +/** + * @} + */ + +/** @addtogroup ETH_DMA_Arbitration + * @{ + */ +#define ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_1_1 ((uint32_t)0x00000000) +#define ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_2_1 ((uint32_t)0x00004000) +#define ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_3_1 ((uint32_t)0x00008000) +#define ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_4_1 ((uint32_t)0x0000C000) +#define ETH_DMA_ARBITRATION_RX_PRIOR_TX ((uint32_t)0x00000002) +#define IS_ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX(RATIO) \ + (((RATIO) == ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_1_1) || ((RATIO) == ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_2_1) \ + || ((RATIO) == ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_3_1) || ((RATIO) == ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_4_1) \ + || ((RATIO) == ETH_DMA_ARBITRATION_RX_PRIOR_TX)) +/** + * @} + */ + +/** @addtogroup ETH_DMA_Flags + * @{ + */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DATA_TRANSFER_ERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_READ_WRITE_ERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_ACCESS_ERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_EARLY_RX ((uint32_t)0x00004000) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FATAL_BUS_ERROR ((uint32_t)0x00002000) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_EARLY_TX ((uint32_t)0x00000400) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RX_WDG_TIMEOUT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RX_PROC_STOP ((uint32_t)0x00000100) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RX_BUF_UA ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_RX ((uint32_t)0x00000040) /*!< Receive flag */ +#define ETH_DMA_FLAG_TX_UNDERFLOW ((uint32_t)0x00000020) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RX_OVERFLOW ((uint32_t)0x00000010) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TX_JABBER_TIMEOUT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TX_BUF_UA ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TX_PROC_STOP ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_TX ((uint32_t)0x00000001) /*!< Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) \ + (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || ((FLAG) == ETH_DMA_FLAG_MMC) \ + || ((FLAG) == ETH_DMA_FLAG_DATA_TRANSFER_ERROR) || ((FLAG) == ETH_DMA_FLAG_READ_WRITE_ERROR) \ + || ((FLAG) == ETH_DMA_FLAG_ACCESS_ERROR) || ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) \ + || ((FLAG) == ETH_DMA_FLAG_EARLY_RX) || ((FLAG) == ETH_DMA_FLAG_FATAL_BUS_ERROR) \ + || ((FLAG) == ETH_DMA_FLAG_EARLY_TX) || ((FLAG) == ETH_DMA_FLAG_RX_WDG_TIMEOUT) \ + || ((FLAG) == ETH_DMA_FLAG_RX_PROC_STOP) || ((FLAG) == ETH_DMA_FLAG_RX_BUF_UA) || ((FLAG) == ETH_DMA_FLAG_RX) \ + || ((FLAG) == ETH_DMA_FLAG_TX_UNDERFLOW) || ((FLAG) == ETH_DMA_FLAG_RX_OVERFLOW) \ + || ((FLAG) == ETH_DMA_FLAG_TX_JABBER_TIMEOUT) || ((FLAG) == ETH_DMA_FLAG_TX_BUF_UA) \ + || ((FLAG) == ETH_DMA_FLAG_TX_PROC_STOP) || ((FLAG) == ETH_DMA_FLAG_TX)) +/** + * @} + */ + +/** @addtogroup ETH_DMA_Interrupts + * @{ + */ +#define ETH_DMA_INT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_INT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_INT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_INT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ +#define ETH_DMA_INT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ +#define ETH_DMA_INT_EARLY_RX ((uint32_t)0x00004000) /*!< Early receive interrupt */ +#define ETH_DMA_INT_FATAL_BUS_ERROR ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ +#define ETH_DMA_INT_EARLY_TX ((uint32_t)0x00000400) /*!< Early transmit interrupt */ +#define ETH_DMA_INT_RX_WDG_TIMEOUT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_INT_RX_PROC_STOP ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ +#define ETH_DMA_INT_RX_BUF_UA ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_INT_RX ((uint32_t)0x00000040) /*!< Receive interrupt */ +#define ETH_DMA_INT_TX_UNDERFLOW ((uint32_t)0x00000020) /*!< Underflow interrupt */ +#define ETH_DMA_INT_RX_OVERFLOW ((uint32_t)0x00000010) /*!< Overflow interrupt */ +#define ETH_DMA_INT_TX_JABBER_TIMEOUT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_INT_TX_BUF_UA ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_INT_TX_PROC_STOP ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_INT_TX ((uint32_t)0x00000001) /*!< Transmit interrupt */ + +#define IS_ETH_DMA_INT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_INT(IT) \ + (((IT) == ETH_DMA_INT_TST) || ((IT) == ETH_DMA_INT_PMT) || ((IT) == ETH_DMA_INT_MMC) || ((IT) == ETH_DMA_INT_NIS) \ + || ((IT) == ETH_DMA_INT_AIS) || ((IT) == ETH_DMA_INT_EARLY_RX) || ((IT) == ETH_DMA_INT_FATAL_BUS_ERROR) \ + || ((IT) == ETH_DMA_INT_EARLY_TX) || ((IT) == ETH_DMA_INT_RX_WDG_TIMEOUT) || ((IT) == ETH_DMA_INT_RX_PROC_STOP) \ + || ((IT) == ETH_DMA_INT_RX_BUF_UA) || ((IT) == ETH_DMA_INT_RX) || ((IT) == ETH_DMA_INT_TX_UNDERFLOW) \ + || ((IT) == ETH_DMA_INT_RX_OVERFLOW) || ((IT) == ETH_DMA_INT_TX_JABBER_TIMEOUT) \ + || ((IT) == ETH_DMA_INT_TX_BUF_UA) || ((IT) == ETH_DMA_INT_TX_PROC_STOP) || ((IT) == ETH_DMA_INT_TX)) + +/** + * @} + */ + +/** @addtogroup ETH_DMA_transmit_process_state_ + * @{ + */ +#define ETH_DMA_TX_PROC_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TX_PROC_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TX_PROC_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */ +#define ETH_DMA_TX_PROC_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TX_PROC_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TX_PROC_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + +/** @addtogroup ETH_DMA_receive_process_state_ + * @{ + */ +#define ETH_DMA_RX_PROC_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_RX_PROC_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_RX_PROC_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */ +#define ETH_DMA_RX_PROC_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_RX_PROC_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ +#define ETH_DMA_RX_PROC_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */ + +/** + * @} + */ + +/** @addtogroup ETH_DMA_overflow_ + * @{ + */ +#define ETH_DMA_OVERFLOW_RX_FIFO_COUNTER ((uint32_t)0x10000000) /*!< Overflow bit for DATFIFO overflow counter */ +#define ETH_DMA_OVERFLOW_MISSED_FRAME_COUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) \ + (((OVERFLOW) == ETH_DMA_OVERFLOW_RX_FIFO_COUNTER) || ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSED_FRAME_COUNTER)) + +/** + * @} + */ + +/** @addtogroup ETH_PMT_Flags + * @{ + */ +#define ETH_PMT_FLAG_RWKUPFILTRST ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_RWKPRCVD ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MGKPRCVD ((uint32_t)0x00000020) /*!< Magic Packet Received */ +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_RWKPRCVD) || ((FLAG) == ETH_PMT_FLAG_MGKPRCVD)) + +/** + * @} + */ + +/** @addtogroup ETH_MMC_Tx_Interrupts + * @{ + */ +#define ETH_MMC_INT_TXGFRMIS ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_INT_TXMCOLGFIS \ + ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_INT_TXSCOLGFIS \ + ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ + +/** + * @} + */ + +/** @addtogroup ETH_MMC_Rx_Interrupts + * @{ + */ +#define ETH_MMC_INT_RXUCGFIS \ + ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_INT_RXALGNERFIS \ + ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_INT_RXCRCERFIS ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ +#define IS_ETH_MMC_INT(IT) \ + (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && ((IT) != 0x00)) +#define IS_ETH_MMC_GET_INT(IT) \ + (((IT) == ETH_MMC_INT_TXGFRMIS) || ((IT) == ETH_MMC_INT_TXMCOLGFIS) || ((IT) == ETH_MMC_INT_TXSCOLGFIS) \ + || ((IT) == ETH_MMC_INT_RXUCGFIS) || ((IT) == ETH_MMC_INT_RXALGNERFIS) || ((IT) == ETH_MMC_INT_RXCRCERFIS)) +/** + * @} + */ + +/** @addtogroup ETH_MMC_Registers + * @{ + */ +#define ETH_MMCCTRL ((uint32_t)0x00000100) /*!< MMC CTRL register */ +#define ETH_MMCRXINT ((uint32_t)0x00000104) /*!< MMC RIR register */ +#define ETH_MMCTXINT ((uint32_t)0x00000108) /*!< MMC TIR register */ +#define ETH_MMCRXINTMSK ((uint32_t)0x0000010C) /*!< MMC RIMR register */ +#define ETH_MMCTXINTMSK ((uint32_t)0x00000110) /*!< MMC TIMR register */ +#define ETH_MMCTXGFASCCNT ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ +#define ETH_MMCTXGFAMSCCNT ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ +#define ETH_MMCTXGFCNT ((uint32_t)0x00000168) /*!< MMC TGFCR register */ +#define ETH_MMCRXFCECNT ((uint32_t)0x00000194) /*!< MMC RFCECR register */ +#define ETH_MMCRXFAECNT ((uint32_t)0x00000198) /*!< MMC RFAECR register */ +#define ETH_MMCRXGUFCNT ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ + +#define IS_ETH_MMC_REGISTER(REG) \ + (((REG) == ETH_MMCCTRL) || ((REG) == ETH_MMCRXINT) || ((REG) == ETH_MMCTXINT) || ((REG) == ETH_MMCRXINTMSK) \ + || ((REG) == ETH_MMCTXINTMSK) || ((REG) == ETH_MMCTXGFASCCNT) || ((REG) == ETH_MMCTXGFAMSCCNT) \ + || ((REG) == ETH_MMCTXGFCNT) || ((REG) == ETH_MMCRXFCECNT) || ((REG) == ETH_MMCRXFAECNT) \ + || ((REG) == ETH_MMCRXGUFCNT)) + +/** + * @} + */ + +/** @addtogroup ETH_PTP_time_update_method + * @{ + */ +#define ETH_PTP_FINE_UPDATE ((uint32_t)0x00000001) /*!< Fine Update method */ +#define ETH_PTP_COARSE_UPDATE ((uint32_t)0x00000000) /*!< Coarse Update method */ +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FINE_UPDATE) || ((UPDATE) == ETH_PTP_COARSE_UPDATE)) + +/** + * @} + */ + +/** @addtogroup ETH_PTP_Flags + * @{ + */ +#define ETH_PTP_FLAG_TSADDREG ((uint32_t)0x00000020) /*!< Addend Register Update */ +#define ETH_PTP_FLAG_TSTRIG ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSUPDT ((uint32_t)0x00000008) /*!< Time Stamp Update */ +#define ETH_PTP_FLAG_TSINIT ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ +#define IS_ETH_PTP_GET_FLAG(FLAG) \ + (((FLAG) == ETH_PTP_FLAG_TSADDREG) || ((FLAG) == ETH_PTP_FLAG_TSTRIG) || ((FLAG) == ETH_PTP_FLAG_TSUPDT) \ + || ((FLAG) == ETH_PTP_FLAG_TSINIT)) + +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/** + * @} + */ + +/** @addtogroup ETH_PTP_time_sign + * @{ + */ +#define ETH_PTP_POSITIVE_TIME ((uint32_t)0x00000000) /*!< Positive time value */ +#define ETH_PTP_NEGATIVE_TIME ((uint32_t)0x80000000) /*!< Negative time value */ +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_POSITIVE_TIME) || ((SIGN) == ETH_PTP_NEGATIVE_TIME)) + +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +#define ETH_PTPTSCTRL ((uint32_t)0x00000700) /*!< PTP TSCR register */ +#define ETH_PTPSSINC ((uint32_t)0x00000704) /*!< PTP SSIR register */ +#define ETH_PTPSEC ((uint32_t)0x00000708) /*!< PTP TSHR register */ +#define ETH_PTPNS ((uint32_t)0x0000070C) /*!< PTP TSLR register */ +#define ETH_PTPSECUP ((uint32_t)0x00000710) /*!< PTP TSHUR register */ +#define ETH_PTPNSUP ((uint32_t)0x00000714) /*!< PTP TSLUR register */ +#define ETH_PTPTSADD ((uint32_t)0x00000718) /*!< PTP TSAR register */ +#define ETH_PTPTTSEC ((uint32_t)0x0000071C) /*!< PTP TTHR register */ +#define ETH_PTPTTNS ((uint32_t)0x00000720) /* PTP TTLR register */ +#define IS_ETH_PTP_REGISTER(REG) \ + (((REG) == ETH_PTPTSCTRL) || ((REG) == ETH_PTPSSINC) || ((REG) == ETH_PTPSEC) || ((REG) == ETH_PTPNS) \ + || ((REG) == ETH_PTPSECUP) || ((REG) == ETH_PTPNSUP) || ((REG) == ETH_PTPTSADD) || ((REG) == ETH_PTPTTSEC) \ + || ((REG) == ETH_PTPTTNS)) + +/** + * @} + */ + +/** + * @} + */ +/** @addtogroup ETH_Exported_Macros + * @{ + */ +/** + * @} + */ + +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) + +/** + * @brief the function prototype of initialize PHY. + * @param ETH_InitStruct init struct of ETH MAC peripheral. + * @return whether initialization succeed: + * - ETH_ERROR initialization fail + * - ETH_SUCCESS initialization succeed + */ +typedef uint32_t (*ETH_InitPHY)(ETH_InitType* ETH_InitStruct); + +/** @addtogroup ETH_Exported_Functions + * @{ + */ +void ETH_DeInit(void); + +uint32_t ETH_Init(ETH_InitType* ETH_InitStruct, ETH_InitPHY callable); +void ETH_InitStruct(ETH_InitType* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +void ETH_EnableTxRx(void); +uint32_t ETH_TxPacket(u8* ppkt, u16 FrameLength); +uint32_t ETH_RxPacket(u8* ppkt, uint8_t checkErr); +uint32_t ETH_GetRxPacketSize(void); +void ETH_DropRxPacket(void); + +#define ETH_INTERFACE_RMII 0 +#define ETH_INTERFACE_MII 1 + +void ETH_ConfigGpio(uint8_t ETH_Interface, uint8_t remap); + +/* PHY */ +uint16_t ETH_ReadPhyRegister(u16 PHYAddress, u16 PHYReg); +uint32_t ETH_WritePhyRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); +uint32_t ETH_EnablePhyLoopBack(u16 PHYAddress, FunctionalState Cmd); + +/* MAC */ +void ETH_EnableMacTx(FunctionalState Cmd); +void ETH_EnableMacRx(FunctionalState Cmd); +FlagStatus ETH_GetFlowCtrlBusyStatus(void); +void ETH_GeneratePauseCtrlFrame(void); +void ETH_EnableBackPressureActivation(FunctionalState Cmd); +FlagStatus ETH_GetMacFlagStatus(uint32_t ETH_MAC_FLAG); +INTStatus ETH_GetMacIntStatus(uint32_t ETH_MAC_IT); +void ETH_EnableMacInt(uint32_t ETH_MAC_IT, FunctionalState Cmd); +void ETH_SetMacAddr(uint32_t MacAddr, u8* Addr); +void ETH_GetMacAddr(uint32_t MacAddr, u8* Addr); +void ETH_EnableMacAddrPerfectFilter(uint32_t MacAddr, FunctionalState Cmd); +void ETH_ConfigMacAddrFilter(uint32_t MacAddr, uint32_t Filter); +void ETH_ConfigMacAddrMaskBytesFilter(uint32_t MacAddr, uint32_t MaskByte); + +/* DMA Tx/Rx descriptors */ +void ETH_ConfigDmaTxDescInChainMode(ETH_DMADescType* DMATxDescTab, u8* TxBuff, uint32_t BufSize, uint32_t TxBuffCount); +void ETH_ConfigDmaTxDescInRingMode(ETH_DMADescType* DMATxDescTab, + u8* TxBuff1, + u8* TxBuff2, + uint32_t BufSize, + uint32_t TxBuffCount); +FlagStatus ETH_GetDmaTxDescFlagStatus(ETH_DMADescType* DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDmaTxDescCollisionCount(ETH_DMADescType* DMATxDesc); +void ETH_SetDmaTxDescOwn(ETH_DMADescType* DMATxDesc); +void ETH_EnableDmaTxDescTransmitInt(ETH_DMADescType* DMATxDesc, FunctionalState Cmd); +void ETH_ConfigDmaTxDescFrameSegment(ETH_DMADescType* DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_ConfigDmaTxDescChecksumInsertion(ETH_DMADescType* DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_EnableDmaTxDescCrc(ETH_DMADescType* DMATxDesc, FunctionalState Cmd); +void ETH_EnableDmaTxDescEndOfRing(ETH_DMADescType* DMATxDesc, FunctionalState Cmd); +void ETH_EnableDmaTxDescSecondAddrChained(ETH_DMADescType* DMATxDesc, FunctionalState Cmd); +void ETH_EnableDmaTxDescShortFramePadding(ETH_DMADescType* DMATxDesc, FunctionalState Cmd); +void ETH_EnableDmaTxDescTimeStamp(ETH_DMADescType* DMATxDesc, FunctionalState Cmd); +void ETH_ConfigDmaTxDescBufSize(ETH_DMADescType* DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_ConfigDmaRxDescInChainMode(ETH_DMADescType* DMARxDescTab, u8* RxBuff, uint32_t BufSize, uint32_t RxBuffCount); +void ETH_ConfigDmaRxDescInRingMode(ETH_DMADescType* DMARxDescTab, + u8* RxBuff1, + u8* RxBuff2, + uint32_t BuffSize, + uint32_t RxBuffCount); +FlagStatus ETH_GetDmaRxDescFlagStatus(ETH_DMADescType* DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDmaRxDescOwn(ETH_DMADescType* DMARxDesc); +uint32_t ETH_GetDmaRxDescFrameLen(__IO ETH_DMADescType* DMARxDesc); +void ETH_EnableDmaRxDescReceiveInt(ETH_DMADescType* DMARxDesc, FunctionalState Cmd); +void ETH_EnableDmaRxDescEndOfRing(ETH_DMADescType* DMARxDesc, FunctionalState Cmd); +void ETH_EnableDmaRxDescSecondAddrChained(ETH_DMADescType* DMARxDesc, FunctionalState Cmd); +uint32_t ETH_GetDmaRxDescBufSize(ETH_DMADescType* DMARxDesc, uint32_t DMARxDesc_Buffer); + +/* DMA */ +FlagStatus ETH_GetDmaFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_ClrDmaFlag(uint32_t ETH_DMA_FLAG); +INTStatus ETH_GetDmaIntStatus(uint32_t ETH_DMA_IT); +void ETH_ClrDmaIntPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTxProcState(void); +uint32_t ETH_GetRxProcState(void); +void ETH_FlushTxFifo(void); +FlagStatus ETH_GetFlushTxFifoStatus(void); +void ETH_EnableDmaTx(FunctionalState Cmd); +void ETH_EnableDmaRx(FunctionalState Cmd); +void ETH_EnableDmaInt(uint32_t ETH_DMA_IT, FunctionalState Cmd); +FlagStatus ETH_GetDmaOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescAddr(void); +uint32_t ETH_GetCurrentRxDescAddr(void); +uint32_t ETH_GetCurrentTxBufAddr(void); +uint32_t ETH_GetCurrentRxBufAddr(void); +void ETH_ResumeDmaTx(void); +void ETH_ResumeDmaRx(void); + +/* PMT */ +void ETH_ResetWakeUpFrameFilter(void); +void ETH_SetWakeUpFrameFilter(uint32_t* Buffer); +void ETH_EnableGlobalUnicastWakeUp(FunctionalState Cmd); +FlagStatus ETH_GetPmtFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_EnableWakeUpFrameDetection(FunctionalState Cmd); +void ETH_EnableMagicPacketDetection(FunctionalState Cmd); +void ETH_EnablePowerDown(FunctionalState Cmd); + +/* MMC */ +void ETH_EnableMmcCounterFreeze(FunctionalState Cmd); +void ETH_EnableMmcResetOnRead(FunctionalState Cmd); +void ETH_EnableMmcCounterRollover(FunctionalState Cmd); +void ETH_ResetMmcCounters(void); +void ETH_EnableMmcInt(uint32_t ETH_MMC_IT, FunctionalState Cmd); +INTStatus ETH_GetMmcIntStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMmcRegisterValue(uint32_t ETH_MMCReg); + +/* PTP */ +uint32_t ETH_TxPtpPacket(u8* ppkt, u16 FrameLength, uint32_t* PTPTxTab); +uint32_t ETH_RxPtpPacket(u8* ppkt, uint32_t* PTPRxTab); +void ETH_ConfigDmaPtpTxDescInChainMode(ETH_DMADescType* DMATxDescTab, + ETH_DMADescType* DMAPTPTxDescTab, + u8* TxBuff, + uint32_t TxBuffCount); +void ETH_ConfigDmaPtpRxDescInChainMode(ETH_DMADescType* DMARxDescTab, + ETH_DMADescType* DMAPTPRxDescTab, + u8* RxBuff, + uint32_t RxBuffCount); +void ETH_UpdatePtpTimeStampAddend(void); +void ETH_EnablePtpTimeStampIntTrigger(void); +void ETH_UpdatePtpTimeStamp(void); +void ETH_InitPtpTimeStamp(void); +void ETH_ConfigPtpUpdateMethod(uint32_t UpdateMethod); +void ETH_StartPTPTimeStamp(FunctionalState Cmd); +FlagStatus ETH_GetPtpFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPtpSubSecondInc(uint32_t SubSecondValue); +void ETH_SetPtpTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPtpTimeStampAddend(uint32_t Value); +void ETH_SetPtpTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPtpRegisterValue(uint32_t ETH_PTPReg); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_ETH_H__ */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_exti.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_exti.h new file mode 100644 index 0000000000..88c1bb7c28 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_exti.h @@ -0,0 +1,206 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_exti.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_EXTI_H__ +#define __N32G45X_EXTI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @addtogroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTI_ModeType; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTI_TriggerType; + +#define IS_EXTI_TRIGGER(TRIGGER) \ + (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \ + || ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_ModeType */ + + EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_ModeType */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitType; + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Constants + * @{ + */ + +/** @addtogroup EXTI_Lines + * @{ + */ + +#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS Wakeup from suspend event */ +#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the TSC event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFC00000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) \ + (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \ + || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \ + || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \ + || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \ + || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \ + || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21)) + +/** + * @} + */ + +/** @addtogroup EXTI_TSSEL_Line + * @{ + */ + + +#define IS_EXTI_TSSEL_LINE(LINE) \ + (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \ + || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \ + || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \ + || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \ + || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \ + || ((LINE) == EXTI_TSSEL_LINE15)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct); +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct); +void EXTI_TriggerSWInt(uint32_t EXTI_Line); +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line); +void EXTI_ClrStatusFlag(uint32_t EXTI_Line); +INTStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClrITPendBit(uint32_t EXTI_Line); +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_EXTI_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_flash.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_flash.h new file mode 100644 index 0000000000..947bc53ac9 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_flash.h @@ -0,0 +1,375 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_flash.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_FLASH_H__ +#define __N32G45X_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_RESERVED, + FLASH_ERR_PG, + FLASH_ERR_PV, + FLASH_ERR_WRP, + FLASH_COMPL, + FLASH_ERR_EV, + FLASH_ERR_RDP2, + FLASH_ERR_ADD, + FLASH_TIMEOUT +} FLASH_STS; + +typedef enum +{ + FLASH_SMP1 = 0, + FLASH_SMP2 +} FLASH_SMPSEL; + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Constants + * @{ + */ + +/** @addtogroup Flash_Latency + * @{ + */ + +#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */ +#define FLASH_LATENCY_4 ((uint32_t)0x00000004) /*!< FLASH Four Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) \ + (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \ + || ((LATENCY) == FLASH_LATENCY_3) || ((LATENCY) == FLASH_LATENCY_4)) +/** + * @} + */ + +/** @addtogroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS)) +/** + * @} + */ + +/** @addtogroup iCache_Enable_Disable + * @{ + */ + +#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */ +#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */ +#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS)) +/** + * @} + */ + +/** @addtogroup SMPSEL_SMP1_SMP2 + * @{ + */ + +#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */ +#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */ +#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2)) +/** + * @} + */ + +/* Values to be used with N32G45X devices */ +#define FLASH_WRP_Pages0to1 \ + ((uint32_t)0x00000001) /*!< N32G45X devices: \ + Write protection of page 0 to 1 */ +#define FLASH_WRP_Pages2to3 \ + ((uint32_t)0x00000002) /*!< N32G45X devices: \ + Write protection of page 2 to 3 */ +#define FLASH_WRP_Pages4to5 \ + ((uint32_t)0x00000004) /*!< N32G45X devices: \ + Write protection of page 4 to 5 */ +#define FLASH_WRP_Pages6to7 \ + ((uint32_t)0x00000008) /*!< N32G45X devices: \ + Write protection of page 6 to 7 */ +#define FLASH_WRP_Pages8to9 \ + ((uint32_t)0x00000010) /*!< N32G45X devices: \ + Write protection of page 8 to 9 */ +#define FLASH_WRP_Pages10to11 \ + ((uint32_t)0x00000020) /*!< N32G45X devices: \ + Write protection of page 10 to 11 */ +#define FLASH_WRP_Pages12to13 \ + ((uint32_t)0x00000040) /*!< N32G45X devices: \ + Write protection of page 12 to 13 */ +#define FLASH_WRP_Pages14to15 \ + ((uint32_t)0x00000080) /*!< N32G45X devices: \ + Write protection of page 14 to 15 */ +#define FLASH_WRP_Pages16to17 \ + ((uint32_t)0x00000100) /*!< N32G45X devices: \ + Write protection of page 16 to 17 */ +#define FLASH_WRP_Pages18to19 \ + ((uint32_t)0x00000200) /*!< N32G45X devices: \ + Write protection of page 18 to 19 */ +#define FLASH_WRP_Pages20to21 \ + ((uint32_t)0x00000400) /*!< N32G45X devices: \ + Write protection of page 20 to 21 */ +#define FLASH_WRP_Pages22to23 \ + ((uint32_t)0x00000800) /*!< N32G45X devices: \ + Write protection of page 22 to 23 */ +#define FLASH_WRP_Pages24to25 \ + ((uint32_t)0x00001000) /*!< N32G45X devices: \ + Write protection of page 24 to 25 */ +#define FLASH_WRP_Pages26to27 \ + ((uint32_t)0x00002000) /*!< N32G45X devices: \ + Write protection of page 26 to 27 */ +#define FLASH_WRP_Pages28to29 \ + ((uint32_t)0x00004000) /*!< N32G45X devices: \ + Write protection of page 28 to 29 */ +#define FLASH_WRP_Pages30to31 \ + ((uint32_t)0x00008000) /*!< N32G45X devices: \ + Write protection of page 30 to 31 */ +#define FLASH_WRP_Pages32to33 \ + ((uint32_t)0x00010000) /*!< N32G45X devices: \ + Write protection of page 32 to 33 */ +#define FLASH_WRP_Pages34to35 \ + ((uint32_t)0x00020000) /*!< N32G45X devices: \ + Write protection of page 34 to 35 */ +#define FLASH_WRP_Pages36to37 \ + ((uint32_t)0x00040000) /*!< N32G45X devices: \ + Write protection of page 36 to 37 */ +#define FLASH_WRP_Pages38to39 \ + ((uint32_t)0x00080000) /*!< N32G45X devices: \ + Write protection of page 38 to 39 */ +#define FLASH_WRP_Pages40to41 \ + ((uint32_t)0x00100000) /*!< N32G45X devices: \ + Write protection of page 40 to 41 */ +#define FLASH_WRP_Pages42to43 \ + ((uint32_t)0x00200000) /*!< N32G45X devices: \ + Write protection of page 42 to 43 */ +#define FLASH_WRP_Pages44to45 \ + ((uint32_t)0x00400000) /*!< N32G45X devices: \ + Write protection of page 44 to 45 */ +#define FLASH_WRP_Pages46to47 \ + ((uint32_t)0x00800000) /*!< N32G45X devices: \ + Write protection of page 46 to 47 */ +#define FLASH_WRP_Pages48to49 \ + ((uint32_t)0x01000000) /*!< N32G45X devices: \ + Write protection of page 48 to 49 */ +#define FLASH_WRP_Pages50to51 \ + ((uint32_t)0x02000000) /*!< N32G45X devices: \ + Write protection of page 50 to 51 */ +#define FLASH_WRP_Pages52to53 \ + ((uint32_t)0x04000000) /*!< N32G45X devices: \ + Write protection of page 52 to 53 */ +#define FLASH_WRP_Pages54to55 \ + ((uint32_t)0x08000000) /*!< N32G45X devices: \ + Write protection of page 54 to 55 */ +#define FLASH_WRP_Pages56to57 \ + ((uint32_t)0x10000000) /*!< N32G45X devices: \ + Write protection of page 56 to 57 */ +#define FLASH_WRP_Pages58to59 \ + ((uint32_t)0x20000000) /*!< N32G45X devices: \ + Write protection of page 58 to 59 */ +#define FLASH_WRP_Pages60to61 \ + ((uint32_t)0x40000000) /*!< N32G45X devices: \ + Write protection of page 60 to 61 */ +#define FLASH_WRP_Pages62to127 \ + ((uint32_t)0x80000000) /*!< N32G45X - 256KB devices: Write protection of page 62 to 127 */ +#define FLASH_WRP_Pages62to255 \ + ((uint32_t)0x80000000) /*!< N32G45X - 512KB devices: Write protection of page 62 to 255 */ + +#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRP_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP0_NORST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ +#define OB_STOP0_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP0_SOURCE(SOURCE) (((SOURCE) == OB_STOP0_NORST) || ((SOURCE) == OB_STOP0_RST)) + +/** + * @} + */ + +/** @addtogroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NORST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST)) + +/** + * @} + */ +/** @addtogroup FLASH_Interrupts + * @{ + */ +#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */ +#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */ +#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ + +#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000))) + +/** + * @} + */ + +/** @addtogroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */ +#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFFFFF83) == 0x00) && (FLAG != 0x00)) + +#define IS_FLASH_GET_FLAG(FLAG) \ + (((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \ + || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \ + || ((FLAG) == FLASH_FLAG_OBERR)) + +/** + * @} + */ + +/** @addtogroup FLASH_STS_CLRFLAG + * @{ + */ +#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR) + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for N32G45X devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf); +void FLASH_iCacheRST(void); +void FLASH_iCacheCmd(uint32_t FLASH_iCache); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address); +FLASH_STS FLASH_MassErase(void); +FLASH_STS FLASH_EraseOB(void); +FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data); +FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages); +FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd); +FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void); +FLASH_STS FLASH_ConfigUserOB(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOB(void); +uint32_t FLASH_GetWriteProtectionOB(void); +FlagStatus FLASH_GetReadOutProtectionSTS(void); +FlagStatus FLASH_GetReadOutProtectionL2STS(void); +FlagStatus FLASH_GetPrefetchBufSTS(void); +void FLASH_SetSMPSELStatus(FLASH_SMPSEL FLASH_smpsel); +FLASH_SMPSEL FLASH_GetSMPSELStatus(void); +void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd); +FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_STS FLASH_GetSTS(void); +FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_FLASH_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_gpio.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_gpio.h new file mode 100644 index 0000000000..9e7f88ca4d --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_gpio.h @@ -0,0 +1,468 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_gpio.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_GPIO_H__ +#define __N32G45X_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @addtogroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) \ + (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) \ + || ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG)) + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_INPUT = 0, + GPIO_Speed_2MHz = 1, + GPIO_Speed_10MHz, + GPIO_Speed_50MHz +} GPIO_SpeedType; +#define IS_GPIO_SPEED(SPEED) \ + (((SPEED) == GPIO_INPUT) || ((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) \ + || ((SPEED) == GPIO_Speed_50MHz)) + +/** + * @brief Configuration Mode enumeration + */ + +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIO_ModeType; + +#define IS_GPIO_MODE(MODE) \ + (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || ((MODE) == GPIO_Mode_IPD) \ + || ((MODE) == GPIO_Mode_IPU) || ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) \ + || ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIO_SpeedType GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_SpeedType */ + + GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_ModeType */ +} GPIO_InitType; + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} Bit_OperateType; + +#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET)) + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Constants + * @{ + */ + +/** @addtogroup GPIO_pins_define + * @{ + */ + +#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) \ + (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \ + || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \ + || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \ + || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15)) + +/** + * @} + */ + +/** @addtogroup GPIO_Remap_define + * @{ + */ + +#define GPIO_RMP_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ +#define GPIO_RMP_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ +#define GPIO_RMP_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ +#define GPIO_RMP_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ +#define GPIO_PART_RMP_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ +#define GPIO_ALL_RMP_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ +#define GPIO_PART1_RMP_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_PART2_RMP_TIM1 ((uint32_t)0x00160080) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_ALL_RMP_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PART2_RMP_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ +#define GPIO_ALL_RMP_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ +#define GPIO_PART1_RMP_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ +#define GPIO_ALL_RMP_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ +#define GPIO_RMP_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ +#define GPIO_RMP1_CAN1 ((uint32_t)0x001D2000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_RMP2_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_RMP3_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_RMP_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ +#define GPIO_RMP_TIM5CH4 ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_RMP_ADC1_ETRI ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_RMP_ADC1_ETRR ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_RMP_ADC2_ETRI ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_RMP_ADC2_ETRR ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_RMP_MII_RMII_SEL ((uint32_t)0x00200080) /*!< MII_RMII_SEL remapping */ +#define GPIO_RMP_SW_JTAG_NO_NJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_RMP_SW_JTAG_SW_ENABLE ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_RMP_SW_JTAG_DISABLE ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ + +/* AFIO_RMP_CFG2 */ +#define GPIO_Remap_XFMC_NADV ((uint32_t)0x80000400) /*!< XFMC_NADV Alternate Function mapping */ + +/* AFIO_RMP_CFG3 */ +#define GPIO_RMP_SDIO ((uint32_t)0x40000001) /*!< SDIO Alternate Function mapping */ +#define GPIO_RMP1_CAN2 ((uint32_t)0x40110002) /*!< CAN2 Alternate Function mapping */ +#define GPIO_RMP3_CAN2 ((uint32_t)0x40110006) /*!< CAN2 Alternate Function mapping */ +#define GPIO_RMP1_QSPI ((uint32_t)0x40140020) /*!< QSPI Alternate Function mapping */ +#define GPIO_RMP3_QSPI ((uint32_t)0x40140030) /*!< QSPI Alternate Function mapping */ +#define GPIO_RMP1_I2C2 ((uint32_t)0x40160040) /*!< I2C2 Alternate Function mapping */ +#define GPIO_RMP3_I2C2 ((uint32_t)0x401600C0) /*!< I2C2 Alternate Function mapping */ +#define GPIO_RMP2_I2C3 ((uint32_t)0x40180200) /*!< I2C3 Alternate Function mapping */ +#define GPIO_RMP3_I2C3 ((uint32_t)0x40180300) /*!< I2C3 Alternate Function mapping */ +#define GPIO_RMP1_I2C4 ((uint32_t)0x401A0400) /*!< I2C4 Alternate Function mapping */ +#define GPIO_RMP3_I2C4 ((uint32_t)0x401A0C00) /*!< I2C4 Alternate Function mapping */ +#define GPIO_RMP1_SPI2 ((uint32_t)0x401C1000) /*!< SPI2 Alternate Function mapping */ +#define GPIO_RMP2_SPI2 ((uint32_t)0x401C3000) /*!< SPI2 Alternate Function mapping */ +#define GPIO_RMP1_SPI3 ((uint32_t)0x401E4000) /*!< SPI3 Alternate Function mapping */ +#define GPIO_RMP2_SPI3 ((uint32_t)0x401E8000) /*!< SPI3 Alternate Function mapping */ +#define GPIO_RMP3_SPI3 ((uint32_t)0x401EC000) /*!< SPI3 Alternate Function mapping */ +#define GPIO_RMP1_ETH ((uint32_t)0x40300001) /*!< ETH Alternate Function mapping */ +#define GPIO_RMP2_ETH ((uint32_t)0x40300002) /*!< ETH Alternate Function mapping */ +#define GPIO_RMP3_ETH ((uint32_t)0x40300003) /*!< ETH Alternate Function mapping */ +#define GPIO_RMP1_SPI1 ((uint32_t)0x41200000) /*!< SPI1 Alternate Function mapping */ +#define GPIO_RMP2_SPI1 ((uint32_t)0x41200004) /*!< SPI1 Alternate Function mapping */ +#define GPIO_RMP3_SPI1 ((uint32_t)0x43200004) /*!< SPI1 Alternate Function mapping */ +#define GPIO_RMP1_USART2 ((uint32_t)0x44200000) /*!< USART2 Alternate Function mapping */ +#define GPIO_RMP2_USART2 ((uint32_t)0x44200008) /*!< USART2 Alternate Function mapping */ +#define GPIO_RMP3_USART2 ((uint32_t)0x46200008) /*!< USART2 Alternate Function mapping */ +#define GPIO_RMP1_UART4 ((uint32_t)0x40340010) /*!< UART4 Alternate Function mapping */ +#define GPIO_RMP2_UART4 ((uint32_t)0x40340020) /*!< UART4 Alternate Function mapping */ +#define GPIO_RMP3_UART4 ((uint32_t)0x40340030) /*!< UART4 Alternate Function mapping */ +#define GPIO_RMP1_UART5 ((uint32_t)0x40360040) /*!< UART5 Alternate Function mapping */ +#define GPIO_RMP2_UART5 ((uint32_t)0x40360080) /*!< UART5 Alternate Function mapping */ +#define GPIO_RMP3_UART5 ((uint32_t)0x403600C0) /*!< UART5 Alternate Function mapping */ +#define GPIO_RMP2_UART6 ((uint32_t)0x40380200) /*!< UART6 Alternate Function mapping */ +#define GPIO_RMP3_UART6 ((uint32_t)0x40380300) /*!< UART6 Alternate Function mapping */ +#define GPIO_RMP1_UART7 ((uint32_t)0x403A0400) /*!< UART7 Alternate Function mapping */ +#define GPIO_RMP3_UART7 ((uint32_t)0x403A0C00) /*!< UART7 Alternate Function mapping */ +#define GPIO_RMP1_XFMC ((uint32_t)0x403C1000) /*!< XFMC Alternate Function mapping */ +#define GPIO_RMP3_XFMC ((uint32_t)0x403C3000) /*!< XFMC Alternate Function mapping */ +#define GPIO_RMP1_TIM8 ((uint32_t)0x403E4000) /*!< TIM8 Alternate Function mapping */ +#define GPIO_RMP3_TIM8 ((uint32_t)0x403EC000) /*!< TIM8 Alternate Function mapping */ + +/* AFIO_RMP_CFG4 */ +#define GPIO_RMP1_COMP1 ((uint32_t)0x20100001) /*!< COMP1 Alternate Function mapping */ +#define GPIO_RMP2_COMP1 ((uint32_t)0x20100002) /*!< COMP1 Alternate Function mapping */ +#define GPIO_RMP3_COMP1 ((uint32_t)0x20100003) /*!< COMP1 Alternate Function mapping */ +#define GPIO_RMP1_COMP2 ((uint32_t)0x20120004) /*!< COMP2 Alternate Function mapping */ +#define GPIO_RMP2_COMP2 ((uint32_t)0x20120008) /*!< COMP2 Alternate Function mapping */ +#define GPIO_RMP3_COMP2 ((uint32_t)0x2012000C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_RMP1_COMP3 ((uint32_t)0x20140010) /*!< COMP3 Alternate Function mapping */ +#define GPIO_RMP3_COMP3 ((uint32_t)0x20140030) /*!< COMP3 Alternate Function mapping */ +#define GPIO_RMP1_COMP4 ((uint32_t)0x20160040) /*!< COMP4 Alternate Function mapping */ +#define GPIO_RMP3_COMP4 ((uint32_t)0x201600C0) /*!< COMP4 Alternate Function mapping */ +#define GPIO_RMP1_COMP5 ((uint32_t)0x20180100) /*!< COMP5 Alternate Function mapping */ +#define GPIO_RMP2_COMP5 ((uint32_t)0x20180200) /*!< COMP5 Alternate Function mapping */ +#define GPIO_RMP3_COMP5 ((uint32_t)0x20180300) /*!< COMP5 Alternate Function mapping */ +#define GPIO_RMP1_COMP6 ((uint32_t)0x201A0400) /*!< COMP6 Alternate Function mapping */ +#define GPIO_RMP3_COMP6 ((uint32_t)0x201A0C00) /*!< COMP6 Alternate Function mapping */ +#define GPIO_RMP_COMP7 ((uint32_t)0x20001000) /*!< COMP7 Alternate Function mapping */ +#define GPIO_RMP_ADC3_ETRI ((uint32_t)0x20004000) /*!< ADC3_ETRGINJ Alternate Function mapping */ +#define GPIO_RMP_ADC3_ETRR ((uint32_t)0x20008000) /*!< ADC3_ETRGREG Alternate Function mapping */ +#define GPIO_RMP_ADC4_ETRI ((uint32_t)0x20200001) /*!< ADC4_ETRGINJ Alternate Function mapping */ +#define GPIO_RMP_ADC4_ETRR ((uint32_t)0x20200002) /*!< ADC4_ETRGREG Alternate Function mapping */ +#define GPIO_RMP_TSC_OUT_CTRL ((uint32_t)0x20200004) /*!< TSC_OUT_CTRL Alternate Function mapping */ +#define GPIO_RMP_QSPI_XIP_EN ((uint32_t)0x20200008) /*!< QSPI_XIP_EN Alternate Function mapping */ +#define GPIO_RMP1_DVP ((uint32_t)0x20340010) /*!< DVP Alternate Function mapping */ +#define GPIO_RMP3_DVP ((uint32_t)0x20340030) /*!< DVP Alternate Function mapping */ +#define GPIO_Remap_SPI1_NSS ((uint32_t)0x20200040) /*!< SPI1 NSS Alternate Function mapping */ +#define GPIO_Remap_SPI2_NSS ((uint32_t)0x20200080) /*!< SPI2 NSS Alternate Function mapping */ +#define GPIO_Remap_SPI3_NSS ((uint32_t)0x20200100) /*!< SPI3 NSS Alternate Function mapping */ +#define GPIO_Remap_QSPI_MISO ((uint32_t)0x20200200) /*!< QSPI MISO Alternate Function mapping */ + +/* AFIO_RMP_CFG5 */ +#define GPIO_Remap_DET_EN_EGB4 ((uint32_t)0x10200080) /*!< EGB4 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_EGB3 ((uint32_t)0x10200040) /*!< EGB4 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_EGB2 ((uint32_t)0x10200020) /*!< EGB4 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_EGB1 ((uint32_t)0x10200010) /*!< EGB4 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_EGBN4 ((uint32_t)0x10200008) /*!< EGBN4 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_EGBN3 ((uint32_t)0x10200004) /*!< EGBN3 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_EGBN2 ((uint32_t)0x10200002) /*!< EGBN2 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_EGBN1 ((uint32_t)0x10200001) /*!< EGBN1 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_ECLAMP4 ((uint32_t)0x10008000) /*!< ECLAMP4 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_ECLAMP3 ((uint32_t)0x10004000) /*!< ECLAMP3 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_ECLAMP2 ((uint32_t)0x10002000) /*!< ECLAMP2 Detect Alternate Function mapping*/ +#define GPIO_Remap_DET_EN_ECLAMP1 ((uint32_t)0x10001000) /*!< ECLAMP1 Detect Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_EGB4 ((uint32_t)0x10000800) /*!< EGB4 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_EGB3 ((uint32_t)0x10000400) /*!< EGB3 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_EGB2 ((uint32_t)0x10000200) /*!< EGB2 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_EGB1 ((uint32_t)0x10000100) /*!< EGB1 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_EGBN4 ((uint32_t)0x10000080) /*!< EGBN4 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_EGBN3 ((uint32_t)0x10000040) /*!< EGBN3 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_EGBN2 ((uint32_t)0x10000020) /*!< EGBN2 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_EGBN1 ((uint32_t)0x10000010) /*!< EGBN1 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_ECLAMP4 ((uint32_t)0x10000008) /*!< ECLAMP4 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_ECLAMP3 ((uint32_t)0x10000004) /*!< ECLAMP3 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_ECLAMP2 ((uint32_t)0x10000002) /*!< ECLAMP2 Reset Alternate Function mapping*/ +#define GPIO_Remap_RST_EN_ECLAMP1 ((uint32_t)0x10000001) /*!< ECLAMP1 Reset Alternate Function mapping*/ + +#define IS_GPIO_REMAP(REMAP) \ + (((REMAP) == GPIO_RMP_SPI1) || ((REMAP) == GPIO_RMP_I2C1) || ((REMAP) == GPIO_RMP_USART1) \ + || ((REMAP) == GPIO_RMP_USART2) || ((REMAP) == GPIO_PART_RMP_USART3) || ((REMAP) == GPIO_ALL_RMP_USART3) \ + || ((REMAP) == GPIO_PART1_RMP_TIM1) || ((REMAP) == GPIO_ALL_RMP_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) \ + || ((REMAP) == GPIO_PART2_RMP_TIM2) || ((REMAP) == GPIO_ALL_RMP_TIM2) || ((REMAP) == GPIO_PART1_RMP_TIM3) \ + || ((REMAP) == GPIO_ALL_RMP_TIM3) || ((REMAP) == GPIO_RMP_TIM4) || ((REMAP) == GPIO_RMP1_CAN1) \ + || ((REMAP) == GPIO_RMP2_CAN1) || ((REMAP) == GPIO_RMP3_CAN1) || ((REMAP) == GPIO_RMP_PD01) || ((REMAP) == GPIO_RMP_TIM5CH4) \ + || ((REMAP) == GPIO_RMP_ADC1_ETRI) || ((REMAP) == GPIO_RMP_ADC1_ETRR) || ((REMAP) == GPIO_RMP_ADC2_ETRI) \ + || ((REMAP) == GPIO_RMP_ADC2_ETRR) || ((REMAP) == GPIO_RMP_SW_JTAG_NO_NJTRST) \ + || ((REMAP) == GPIO_RMP_SW_JTAG_SW_ENABLE) || ((REMAP) == GPIO_RMP_SW_JTAG_DISABLE) \ + || ((REMAP) == GPIO_Remap_XFMC_NADV) || ((REMAP) == GPIO_RMP_SDIO) || ((REMAP) == GPIO_RMP1_CAN2) \ + || ((REMAP) == GPIO_RMP3_CAN2) || ((REMAP) == GPIO_RMP1_QSPI) || ((REMAP) == GPIO_RMP3_QSPI) \ + || ((REMAP) == GPIO_RMP1_I2C2) || ((REMAP) == GPIO_RMP3_I2C2) || ((REMAP) == GPIO_RMP2_I2C3) \ + || ((REMAP) == GPIO_RMP3_I2C3) || ((REMAP) == GPIO_RMP1_I2C4) || ((REMAP) == GPIO_RMP3_I2C4) \ + || ((REMAP) == GPIO_RMP1_SPI2) || ((REMAP) == GPIO_RMP2_SPI2) || ((REMAP) == GPIO_RMP1_SPI3) \ + || ((REMAP) == GPIO_RMP2_SPI3) || ((REMAP) == GPIO_RMP3_SPI3) || ((REMAP) == GPIO_RMP1_ETH) \ + || ((REMAP) == GPIO_RMP2_ETH) || ((REMAP) == GPIO_RMP3_ETH) || ((REMAP) == GPIO_RMP1_SPI1) \ + || ((REMAP) == GPIO_RMP2_SPI1) || ((REMAP) == GPIO_RMP3_SPI1) || ((REMAP) == GPIO_RMP1_USART2) \ + || ((REMAP) == GPIO_RMP2_USART2) || ((REMAP) == GPIO_RMP3_USART2) || ((REMAP) == GPIO_RMP1_UART4) \ + || ((REMAP) == GPIO_RMP2_UART4) || ((REMAP) == GPIO_RMP3_UART4) || ((REMAP) == GPIO_RMP1_UART5) \ + || ((REMAP) == GPIO_RMP2_UART5) || ((REMAP) == GPIO_RMP3_UART5) || ((REMAP) == GPIO_RMP2_UART6) \ + || ((REMAP) == GPIO_RMP3_UART6) || ((REMAP) == GPIO_RMP1_UART7) || ((REMAP) == GPIO_RMP3_UART7) \ + || ((REMAP) == GPIO_RMP1_XFMC) || ((REMAP) == GPIO_RMP3_XFMC) || ((REMAP) == GPIO_RMP1_TIM8) \ + || ((REMAP) == GPIO_RMP3_TIM8) || ((REMAP) == GPIO_RMP1_COMP1) || ((REMAP) == GPIO_RMP2_COMP1) \ + || ((REMAP) == GPIO_RMP3_COMP1) || ((REMAP) == GPIO_RMP1_COMP2) || ((REMAP) == GPIO_RMP2_COMP2) \ + || ((REMAP) == GPIO_RMP3_COMP2) || ((REMAP) == GPIO_RMP1_COMP3) || ((REMAP) == GPIO_RMP3_COMP3) \ + || ((REMAP) == GPIO_RMP1_COMP4) || ((REMAP) == GPIO_RMP3_COMP4) || ((REMAP) == GPIO_RMP1_COMP5) \ + || ((REMAP) == GPIO_RMP2_COMP5) || ((REMAP) == GPIO_RMP3_COMP5) || ((REMAP) == GPIO_RMP1_COMP6) \ + || ((REMAP) == GPIO_RMP3_COMP6) || ((REMAP) == GPIO_RMP_COMP7) || ((REMAP) == GPIO_RMP_ADC3_ETRI) \ + || ((REMAP) == GPIO_RMP_ADC3_ETRR) || ((REMAP) == GPIO_RMP_ADC4_ETRI) || ((REMAP) == GPIO_RMP_ADC4_ETRR) \ + || ((REMAP) == GPIO_RMP_TSC_OUT_CTRL) || ((REMAP) == GPIO_RMP_QSPI_XIP_EN) || ((REMAP) == GPIO_RMP1_DVP) \ + || ((REMAP) == GPIO_RMP3_DVP) || ((REMAP) == GPIO_Remap_SPI1_NSS) || ((REMAP) == GPIO_Remap_SPI2_NSS) \ + || ((REMAP) == GPIO_Remap_SPI3_NSS) || ((REMAP) == GPIO_Remap_QSPI_MISO) || ((REMAP) == GPIO_RMP_MII_RMII_SEL) \ + || ((REMAP) == GPIO_PART2_RMP_TIM1) || ((REMAP) == GPIO_Remap_DET_EN_EGB4) || ((REMAP) == GPIO_Remap_DET_EN_EGB3) \ + || ((REMAP) == GPIO_Remap_DET_EN_EGB2) || ((REMAP) == GPIO_Remap_DET_EN_EGB1) \ + || ((REMAP) == GPIO_Remap_DET_EN_EGBN4) || ((REMAP) == GPIO_Remap_DET_EN_EGBN3) \ + || ((REMAP) == GPIO_Remap_DET_EN_EGBN2) || ((REMAP) == GPIO_Remap_DET_EN_EGBN1) \ + || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP4) || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP3) \ + || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP2) || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP1) \ + || ((REMAP) == GPIO_Remap_RST_EN_EGB4) || ((REMAP) == GPIO_Remap_RST_EN_EGB3) \ + || ((REMAP) == GPIO_Remap_RST_EN_EGB2) || ((REMAP) == GPIO_Remap_RST_EN_EGB1) \ + || ((REMAP) == GPIO_Remap_RST_EN_EGBN4) || ((REMAP) == GPIO_Remap_RST_EN_EGBN3) \ + || ((REMAP) == GPIO_Remap_RST_EN_EGBN2) || ((REMAP) == GPIO_Remap_RST_EN_EGBN1) \ + || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP4) || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP3) \ + || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP2) || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP1)) + +/** + * @} + */ + +/** @addtogroup GPIO_Port_Sources + * @{ + */ + +#define GPIOA_PORT_SOURCE ((uint8_t)0x00) +#define GPIOB_PORT_SOURCE ((uint8_t)0x01) +#define GPIOC_PORT_SOURCE ((uint8_t)0x02) +#define GPIOD_PORT_SOURCE ((uint8_t)0x03) +#define GPIOE_PORT_SOURCE ((uint8_t)0x04) +#define GPIOF_PORT_SOURCE ((uint8_t)0x05) +#define GPIOG_PORT_SOURCE ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE) || ((PORTSOURCE) == GPIOE_PORT_SOURCE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \ + (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOD_PORT_SOURCE) || ((PORTSOURCE) == GPIOE_PORT_SOURCE) \ + || ((PORTSOURCE) == GPIOF_PORT_SOURCE) || ((PORTSOURCE) == GPIOG_PORT_SOURCE)) + +/** + * @} + */ + +/** @addtogroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PIN_SOURCE0 ((uint8_t)0x00) +#define GPIO_PIN_SOURCE1 ((uint8_t)0x01) +#define GPIO_PIN_SOURCE2 ((uint8_t)0x02) +#define GPIO_PIN_SOURCE3 ((uint8_t)0x03) +#define GPIO_PIN_SOURCE4 ((uint8_t)0x04) +#define GPIO_PIN_SOURCE5 ((uint8_t)0x05) +#define GPIO_PIN_SOURCE6 ((uint8_t)0x06) +#define GPIO_PIN_SOURCE7 ((uint8_t)0x07) +#define GPIO_PIN_SOURCE8 ((uint8_t)0x08) +#define GPIO_PIN_SOURCE9 ((uint8_t)0x09) +#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A) +#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B) +#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C) +#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D) +#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E) +#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) \ + (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \ + || ((PINSOURCE) == GPIO_PIN_SOURCE15)) + +/** + * @} + */ + +/** @addtogroup Ethernet_Media_Interface + * @{ + */ +#define GPIO_ETH_MII_CFG ((uint32_t)0x00000000) +#define GPIO_ETH_RMII_CFG ((uint32_t)0x00800000) + +#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MII_CFG) || ((INTERFACE) == GPIO_ETH_RMII_CFG)) + +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_Module* GPIOx); +void GPIO_AFIOInitDefault(void); +void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct); +void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin); +uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin); +uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx); +void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd); +void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal); +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin); +void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource); +void GPIO_CtrlEventOutput(FunctionalState Cmd); +void GPIO_ConfigPinRemap(uint32_t RmpPin, FunctionalState Cmd); +void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource); +void GPIO_ETH_ConfigMediaInterface(uint32_t ETH_ConfigSel); +void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_GPIO_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_i2c.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_i2c.h new file mode 100644 index 0000000000..3d652306d9 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_i2c.h @@ -0,0 +1,665 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_i2c.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_I2C_H__ +#define __N32G45X_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @addtogroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t ClkSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t BusMode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_BusMode */ + + uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t OwnAddr1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t AckEnable; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitType; + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2) || ((PERIPH) == I2C3) || ((PERIPH) == I2C4)) +/** @addtogroup I2C_BusMode + * @{ + */ + +#define I2C_BUSMODE_I2C ((uint16_t)0x0000) +#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002) +#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A) +#define IS_I2C_BUS_MODE(MODE) \ + (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST)) +/** + * @} + */ + +/** @addtogroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2)) +/** + * @} + */ + +/** @addtogroup I2C_acknowledgement + * @{ + */ + +#define I2C_ACKEN ((uint16_t)0x0400) +#define I2C_ACKDIS ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS)) +/** + * @} + */ + +/** @addtogroup I2C_transfer_direction + * @{ + */ + +#define I2C_DIRECTION_SEND ((uint8_t)0x00) +#define I2C_DIRECTION_RECV ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV)) +/** + * @} + */ + +/** @addtogroup I2C_acknowledged_address + * @{ + */ + +#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000) +#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000) +#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT)) +/** + * @} + */ + +/** @addtogroup I2C_registers + * @{ + */ + +#define I2C_REG_CTRL1 ((uint8_t)0x00) +#define I2C_REG_CTRL2 ((uint8_t)0x04) +#define I2C_REG_OADDR1 ((uint8_t)0x08) +#define I2C_REG_OADDR2 ((uint8_t)0x0C) +#define I2C_REG_DAT ((uint8_t)0x10) +#define I2C_REG_STS1 ((uint8_t)0x14) +#define I2C_REG_STS2 ((uint8_t)0x18) +#define I2C_REG_CLKCTRL ((uint8_t)0x1C) +#define I2C_REG_TMRISE ((uint8_t)0x20) +#define IS_I2C_REG(REGISTER) \ + (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \ + || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \ + || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE)) +/** + * @} + */ + +/** @addtogroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBALERT_LOW ((uint16_t)0x2000) +#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF) +#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH)) +/** + * @} + */ + +/** @addtogroup I2C_PEC_position + * @{ + */ + +#define I2C_PEC_POS_NEXT ((uint16_t)0x0800) +#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT)) +/** + * @} + */ + +/** @addtogroup I2C_NCAK_position + * @{ + */ + +#define I2C_NACK_POS_NEXT ((uint16_t)0x0800) +#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT)) +/** + * @} + */ + +/** @addtogroup I2C_interrupts_definition + * @{ + */ + +#define I2C_INT_BUF ((uint16_t)0x0400) +#define I2C_INT_EVENT ((uint16_t)0x0200) +#define I2C_INT_ERR ((uint16_t)0x0100) +#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @addtogroup I2C_interrupts_definition + * @{ + */ + +#define I2C_INT_SMBALERT ((uint32_t)0x01008000) +#define I2C_INT_TIMOUT ((uint32_t)0x01004000) +#define I2C_INT_PECERR ((uint32_t)0x01001000) +#define I2C_INT_OVERRUN ((uint32_t)0x01000800) +#define I2C_INT_ACKFAIL ((uint32_t)0x01000400) +#define I2C_INT_ARLOST ((uint32_t)0x01000200) +#define I2C_INT_BUSERR ((uint32_t)0x01000100) +#define I2C_INT_TXDATE ((uint32_t)0x06000080) +#define I2C_INT_RXDATNE ((uint32_t)0x06000040) +#define I2C_INT_STOPF ((uint32_t)0x02000010) +#define I2C_INT_ADDR10F ((uint32_t)0x02000008) +#define I2C_INT_BYTEF ((uint32_t)0x02000004) +#define I2C_INT_ADDRF ((uint32_t)0x02000002) +#define I2C_INT_STARTBF ((uint32_t)0x02000001) + +#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_INT(IT) \ + (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \ + || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \ + || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \ + || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF)) +/** + * @} + */ + +/** @addtogroup I2C_flags_definition + * @{ + */ + +/** + * @brief STS2 register flags + */ + +#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000) +#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000) +#define I2C_FLAG_TRF ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSMODE ((uint32_t)0x00010000) + +/** + * @brief STS1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800) +#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400) +#define I2C_FLAG_ARLOST ((uint32_t)0x10000200) +#define I2C_FLAG_BUSERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXDATE ((uint32_t)0x10000080) +#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008) +#define I2C_FLAG_BYTEF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDRF ((uint32_t)0x10000002) +#define I2C_FLAG_STARTBF ((uint32_t)0x10000001) + +#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) \ + (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \ + || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \ + || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \ + || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \ + || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \ + || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \ + || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF)) +/** + * @} + */ + +/** @addtogroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateStart() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_SendAddr7bit() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_RecvData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_ConfigAck()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled + * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall()) + * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and + * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVT(EVENT) \ + (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \ + || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \ + || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \ + || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \ + || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \ + || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \ + || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \ + || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS)) +/** + * @} + */ + +/** @addtogroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @addtogroup I2C_clock_speed + * @{ + */ + +//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_Module* I2Cx); +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct); +void I2C_InitStruct(I2C_InitType* I2C_InitStruct); +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address); +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd); +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data); +uint8_t I2C_RecvData(I2C_Module* I2Cx); +void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register); +void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition); +void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition); +void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd); +uint8_t I2C_GetPec(I2C_Module* I2Cx); +void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (STS1 and STS2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occurred. + * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlag() function (see below). + * The returned value could be compared to events already defined in the + * library (n32g45x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlag() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXDATNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_Module* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT); +void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_iwdg.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_iwdg.h new file mode 100644 index 0000000000..9ace2b5b29 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_iwdg.h @@ -0,0 +1,145 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_iwdg.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_IWDG_H__ +#define __N32G45X_IWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @addtogroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Constants + * @{ + */ + +/** @addtogroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WRITE_ENABLE ((uint16_t)0x5555) +#define IWDG_WRITE_DISABLE ((uint16_t)0x0000) +#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE)) +/** + * @} + */ + +/** @addtogroup IWDG_prescaler + * @{ + */ + +#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00) +#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01) +#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02) +#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03) +#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04) +#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05) +#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER_DIV(PRESCALER) \ + (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \ + || ((PRESCALER) == IWDG_PRESCALER_DIV256)) +/** + * @} + */ + +/** @addtogroup IWDG_Flag + * @{ + */ + +#define IWDG_PVU_FLAG ((uint16_t)0x0001) +#define IWDG_CRVU_FLAG ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteConfig(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler); +void IWDG_CntReload(uint16_t Reload); +void IWDG_ReloadKey(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_IWDG_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_opamp.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_opamp.h new file mode 100644 index 0000000000..8273c7d16e --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_opamp.h @@ -0,0 +1,213 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_opamp.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_OPAMPMP_H__ +#define __N32G45X_OPAMPMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" +#include + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @{ + */ + +/** @addtogroup OPAMP_Exported_Constants + * @{ + */ +typedef enum +{ + OPAMP1 = 0, + OPAMP2 = 4, + OPAMP3 = 8, + OPAMP4 = 12, +} OPAMPX; + +// OPAMP_CS +typedef enum +{ + OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19), + OPAMP1_CS_VPSSEL_PA3 = (0x01L << 19), + OPAMP1_CS_VPSSEL_DAC2_PA5 = (0x02L << 19), + OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19), + OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19), + OPAMP2_CS_VPSSEL_PB0 = (0x01L << 19), + OPAMP2_CS_VPSSEL_PE8 = (0x02L << 19), + OPAMP3_CS_VPSSEL_PC9 = (0x00L << 19), + OPAMP3_CS_VPSSEL_PA1 = (0x01L << 19), + OPAMP3_CS_VPSSEL_DAC2_PA5 = (0x02L << 19), + OPAMP3_CS_VPSSEL_PC3 = (0x03L << 19), + OPAMP4_CS_VPSSEL_PC3 = (0x00L << 19), + OPAMP4_CS_VPSSEL_DAC1_PA4 = (0x01L << 19), + OPAMP4_CS_VPSSEL_PC5 = (0x02L << 19), +} OPAMP_CS_VPSSEL; +typedef enum +{ + OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17), + OPAMP1_CS_VMSSEL_PA2 = (0x01L << 17), + OPAMPx_CS_VMSSEL_FLOAT = (0x03L << 17), + OPAMP2_CS_VMSSEL_PA2 = (0x00L << 17), + OPAMP2_CS_VMSSEL_PA5 = (0x01L << 17), + OPAMP3_CS_VMSSEL_PC4 = (0x00L << 17), + OPAMP3_CS_VMSSEL_PB10 = (0x01L << 17), + OPAMP4_CS_VMSSEL_PB10 = (0x00L << 17), + OPAMP4_CS_VMSSEL_PC9 = (0x01L << 17), + OPAMP4_CS_VMSSEL_PD8 = (0x02L << 17), +} OPAMP_CS_VMSSEL; + +typedef enum +{ + OPAMP1_CS_VPSEL_PA1 = (0x00L << 8), + OPAMP1_CS_VPSEL_PA3 = (0x01L << 8), + OPAMP1_CS_VPSEL_DAC2_PA5 = (0x02L << 8), + OPAMP1_CS_VPSEL_PA7 = (0x03L << 8), + OPAMP2_CS_VPSEL_PA7 = (0x00L << 8), + OPAMP2_CS_VPSEL_PB0 = (0x01L << 8), + OPAMP2_CS_VPSEL_PE8 = (0x02L << 8), + OPAMP3_CS_VPSEL_PC9 = (0x00L << 8), + OPAMP3_CS_VPSEL_PA1 = (0x01L << 8), + OPAMP3_CS_VPSEL_DAC2_PA5 = (0x02L << 8), + OPAMP3_CS_VPSEL_PC3 = (0x03L << 8), + OPAMP4_CS_VPSEL_PC3 = (0x00L << 8), + OPAMP4_CS_VPSEL_DAC1_PA4 = (0x01L << 8), + OPAMP4_CS_VPSEL_PC5 = (0x02L << 8), +} OPAMP_CS_VPSEL; +typedef enum +{ + OPAMP1_CS_VMSEL_PA3 = (0x00L << 6), + OPAMP1_CS_VMSEL_PA2 = (0x01L << 6), + OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6), + OPAMP2_CS_VMSEL_PA2 = (0x00L << 6), + OPAMP2_CS_VMSEL_PA5 = (0x01L << 6), + OPAMP3_CS_VMSEL_PC4 = (0x00L << 6), + OPAMP3_CS_VMSEL_PB10 = (0x01L << 6), + OPAMP4_CS_VMSEL_PB10 = (0x00L << 6), + OPAMP4_CS_VMSEL_PC9 = (0x01L << 6), + OPAMP4_CS_VMSEL_PD8 = (0x02L << 6), +} OPAMP_CS_VMSEL; +typedef enum +{ + OPAMP_CS_PGA_GAIN_2 = (0x00 << 3), + OPAMP_CS_PGA_GAIN_4 = (0x01 << 3), + OPAMP_CS_PGA_GAIN_8 = (0x02 << 3), + OPAMP_CS_PGA_GAIN_16 = (0x03 << 3), + OPAMP_CS_PGA_GAIN_32 = (0x04 << 3), +} OPAMP_CS_PGA_GAIN; +typedef enum +{ + OPAMP_CS_EXT_OPAMP = (0x00 << 1), + OPAMP_CS_PGA_EN = (0x02 << 1), + OPAMP_CS_FOLLOW = (0x03 << 1), +} OPAMP_CS_MOD; + +// bit mask +#define OPAMP_CS_EN_MASK (0x01L << 0) +#define OPAMP_CS_MOD_MASK (0x03L << 1) +#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3) +#define OPAMP_CS_VMSEL_MASK (0x03L << 6) +#define OPAMP_CS_VPSEL_MASK (0x07L << 8) +#define OPAMP_CS_CALON_MASK (0x01L << 11) +#define OPAMP_CS_TSTREF_MASK (0x01L << 13) +#define OPAMP_CS_CALOUT_MASK (0x01L << 14) +#define OPAMP_CS_RANGE_MASK (0x01L << 15) +#define OPAMP_CS_TCMEN_MASK (0x01L << 16) +#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17) +#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19) +/** @addtogroup OPAMP_LOCK + * @{ + */ +#define OPAMP_LOCK_1 0x01L +#define OPAMP_LOCK_2 0x02L +#define OPAMP_LOCK_3 0x04L +#define OPAMP_LOCK_4 0x08L +/** + * @} + */ +/** + * @} + */ + +/** + * @brief OPAMP Init structure definition + */ + +typedef struct +{ + FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */ + + FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/ + + OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */ + + OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/ +} OPAMP_InitType; + +/** @addtogroup OPAMP_Exported_Functions + * @{ + */ + +void OPAMP_DeInit(void); +void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct); +void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct); +void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en); +void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain); +void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel); +void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel); +void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel); +void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel); +bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx); +void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en); +void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_ADC_H */ + /** + * @} + */ + /** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_pwr.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_pwr.h new file mode 100644 index 0000000000..7ee2e964a3 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_pwr.h @@ -0,0 +1,179 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_pwr.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_PWR_H__ +#define __N32G45X_PWR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @addtogroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Constants + * @{ + */ + +/** @addtogroup PVD_detection_level + * @{ + */ + +#define PWR_PVDRANGRE_2V2 ((uint32_t)0x00000000) +#define PWR_PVDRANGRE_2V3 ((uint32_t)0x00000020) +#define PWR_PVDRANGRE_2V4 ((uint32_t)0x00000040) +#define PWR_PVDRANGRE_2V5 ((uint32_t)0x00000060) +#define PWR_PVDRANGRE_2V6 ((uint32_t)0x00000080) +#define PWR_PVDRANGRE_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDRANGRE_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDRANGRE_2V9 ((uint32_t)0x000000E0) + +#define PWR_PVDRANGE_1V78 ((uint32_t)0x00000200) +#define PWR_PVDRANGE_1V88 ((uint32_t)0x00000220) +#define PWR_PVDRANGE_1V98 ((uint32_t)0x00000240) +#define PWR_PVDRANGE_2V08 ((uint32_t)0x00000260) +#define PWR_PVDRANGE_3V06 ((uint32_t)0x00000280) +#define PWR_PVDRANGE_3V24 ((uint32_t)0x000002A0) +#define PWR_PVDRANGE_3V42 ((uint32_t)0x000002C0) +#define PWR_PVDRANGE_3V60 ((uint32_t)0x000002E0) +#define IS_PWR_PVD_LEVEL(LEVEL) \ + (((LEVEL) == PWR_PVDRANGRE_2V2) || ((LEVEL) == PWR_PVDRANGRE_2V3) || ((LEVEL) == PWR_PVDRANGRE_2V4) \ + || ((LEVEL) == PWR_PVDRANGRE_2V5) || ((LEVEL) == PWR_PVDRANGRE_2V6) || ((LEVEL) == PWR_PVDRANGRE_2V7) \ + || ((LEVEL) == PWR_PVDRANGRE_2V8) || ((LEVEL) == PWR_PVDRANGRE_2V9) || ((LEVEL) == PWR_PVDRANGE_1V78) \ + || ((LEVEL) == PWR_PVDRANGE_1V88) || ((LEVEL) == PWR_PVDRANGE_1V98) || ((LEVEL) == PWR_PVDRANGE_2V08) \ + || ((LEVEL) == PWR_PVDRANGE_3V06) || ((LEVEL) == PWR_PVDRANGE_3V24) || ((LEVEL) == PWR_PVDRANGE_3V42) \ + || ((LEVEL) == PWR_PVDRANGE_3V60)) + +/** + * @} + */ + +/** @addtogroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_REGULATOR_ON ((uint32_t)0x00000000) +#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER)) +/** + * @} + */ + +/** @addtogroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/** + * @} + */ + +/** @addtogroup PWR_Flag + * @{ + */ + +#define PWR_WU_FLAG ((uint32_t)0x00000001) +#define PWR_SB_FLAG ((uint32_t)0x00000002) +#define PWR_PVDO_FLAG ((uint32_t)0x00000004) +#define PWR_VBATF_FLAG ((uint32_t)0x00000008) +#define IS_PWR_GET_FLAG(FLAG) \ + (((FLAG) == PWR_WU_FLAG) || ((FLAG) == PWR_SB_FLAG) || ((FLAG) == PWR_PVDO_FLAG) || ((FLAG) == PWR_VBATF_FLAG)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_WU_FLAG) || ((FLAG) == PWR_SB_FLAG) || ((FLAG) == PWR_VBATF_FLAG)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessEnable(FunctionalState Cmd); +void PWR_PvdEnable(FunctionalState Cmd); +void PWR_PvdRangeConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinEnable(FunctionalState Cmd); +void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry); +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry); +void PWR_EnterStandbyState(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_PWR_H__ */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_qspi.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_qspi.h new file mode 100644 index 0000000000..4b0a7caaf9 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_qspi.h @@ -0,0 +1,333 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_qspi.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_QSPI_H__ +#define __N32G45X_QSPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" +#include +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup QSPI + * @brief QSPI driver modules + * @{ + */ +//////////////////////////////////////////////////////////////////////////////////////////////////// +typedef enum +{ + STANDARD_SPI_FORMAT_SEL = 0, + DUAL_SPI_FORMAT_SEL, + QUAD_SPI_FORMAT_SEL, + XIP_SPI_FORMAT_SEL +} QSPI_FORMAT_SEL; + +typedef enum +{ + TX_AND_RX = 0, + TX_ONLY, + RX_ONLY +} QSPI_DATA_DIR; + +typedef enum +{ + QSPI_NSS_PORTA_SEL, + QSPI_NSS_PORTC_SEL, + QSPI_NSS_PORTF_SEL +} QSPI_NSS_PORT_SEL; + +typedef enum +{ + QSPI_NULL = 0, + QSPI_SUCCESS, +} QSPI_STATUS; +//////////////////////////////////////////////////////////////////////////////////////////////////// +typedef struct +{ + /*QSPI_CTRL0*/ + uint32_t DFS; + uint32_t FRF; + uint32_t SCPH; + uint32_t SCPOL; + uint32_t TMOD; + uint32_t SSTE; + uint32_t CFS; + uint32_t SPI_FRF; + + /*QSPI_CTRL1*/ + uint32_t NDF; + + /*QSPI_MW_CTRL*/ + uint32_t MWMOD; + uint32_t MC_DIR; + uint32_t MHS_EN; + + /*QSPI_BAUD*/ + uint32_t CLK_DIV; + + /*QSPI_TXFT*/ + uint32_t TXFT; + + /*QSPI_RXFT*/ + uint32_t RXFT; + + /*QSPI_TXFN*/ + uint32_t TXFN; + + /*QSPI_RXFN*/ + uint32_t RXFN; + + /*QSPI_RS_DELAY*/ + uint32_t SDCN; + uint32_t SES; + + /*QSPI_ENH_CTRL0*/ + uint32_t ENHANCED_TRANS_TYPE; + uint32_t ENHANCED_ADDR_LEN; + uint32_t ENHANCED_MD_BIT_EN; + uint32_t ENHANCED_INST_L; + uint32_t ENHANCED_WAIT_CYCLES; + uint32_t ENHANCED_SPI_DDR_EN; + uint32_t ENHANCED_INST_DDR_EN; + uint32_t ENHANCED_XIP_DFS_HC; + uint32_t ENHANCED_XIP_INST_EN; + uint32_t ENHANCED_XIP_CT_EN; + uint32_t ENHANCED_XIP_MBL; + uint32_t ENHANCED_CLK_STRETCH_EN; + + /*QSPI_DDR_TXDE*/ + uint32_t TXDE; + + /*QSPI_XIP_MODE*/ + uint32_t XIP_MD_BITS; + + /*QSPI_XIP_INCR_TOC*/ + uint32_t ITOC; + + /*QSPI_XIP_WRAP_TOC*/ + uint32_t WTOC; + + /*QSPI_XIP_CTRL*/ + uint32_t XIP_FRF; + uint32_t XIP_TRANS_TYPE; + uint32_t XIP_ADDR_LEN; + uint32_t XIP_INST_L; + uint32_t XIP_MD_BITS_EN; + uint32_t XIP_WAIT_CYCLES; + uint32_t XIP_DFS_HC; + uint32_t XIP_DDR_EN; + uint32_t XIP_INST_DDR_EN; + uint32_t XIP_INST_EN; + uint32_t XIP_CT_EN; + uint32_t XIP_MBL; + + /*QSPI_XIP_TOUT*/ + uint32_t XTOUT; + +} QSPI_InitType; +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define QSPI_TIME_OUT_CNT 200 + +#define IS_QSPI_SPI_FRF(SPI_FRF) \ + (((SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT)) + +#define IS_QSPI_CFS(CFS) ((((CFS) >= QSPI_CTRL0_CFS_2_BIT) && ((CFS) <= QSPI_CTRL0_CFS_16_BIT)) || ((CFS) == QSPI_CTRL0_CFS_1_BIT)) + +#define IS_QSPI_SSTE(SSTE) (((SSTE) == QSPI_CTRL0_SSTE_EN) || ((SSTE) == 0)) + +#define IS_QSPI_TMOD(TMOD) \ + (((TMOD) == QSPI_CTRL0_TMOD_TX_AND_RX) || ((TMOD) == QSPI_CTRL0_TMOD_TX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_RX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_EEPROM_READ)) + +#define IS_QSPI_SCPOL(SCPOL) (((SCPOL) == QSPI_CTRL0_SCPOL_LOW) || ((SCPOL) == QSPI_CTRL0_SCPOL_HIGH)) + +#define IS_QSPI_SCPH(SCPH) (((SCPH) == QSPI_CTRL0_SCPH_FIRST_EDGE) || ((SCPH) == QSPI_CTRL0_SCPH_SECOND_EDGE)) + +#define IS_QSPI_FRF(FRF) (((FRF) == QSPI_CTRL0_FRF_MOTOROLA) || ((FRF) == QSPI_CTRL0_FRF_TI) || ((FRF) == QSPI_CTRL0_FRF_MICROWIRE)) + +#define IS_QSPI_DFS(DFS) (((DFS) >= QSPI_CTRL0_DFS_4_BIT) && ((DFS) <= QSPI_CTRL0_DFS_32_BIT)) + + +#define IS_QSPI_NDF(NDF) (((NDF) <= 0xFFFF)) + +#define IS_QSPI_MWMOD(MWMOD) (((MWMOD) == QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL) || ((MWMOD) == QSPI_MW_CTRL_MWMOD_SEQUENTIAL)) + +#define IS_QSPI_MC_DIR(MC_DIR) (((MC_DIR) == QSPI_MW_CTRL_MC_DIR_RX) || ((MC_DIR) == QSPI_MW_CTRL_MC_DIR_TX)) + +#define IS_QSPI_MHS_EN(MHS_EN) (((MHS_EN) == QSPI_MW_CTRL_MHS_EN) || ((MHS_EN) == 0)) + +#define IS_QSPI_CLK_DIV(CLK_DIV) (((CLK_DIV) <= 0xFFFF)) + +#define IS_QSPI_TXFT(TXFT) (((TXFT) <= 0x1FFFFF)) + +#define IS_QSPI_RXFT(RXFT) (((RXFT) <= 0x1F)) + +#define IS_QSPI_TXFN(TXFN) (((TXFN) <= 0x3F)) + +#define IS_QSPI_RXFN(RXFN) (((RXFN) <= 0x3F)) + +#define IS_QSPI_DMA_CTRL(DMA_CTRL) (((DMA_CTRL) == QSPI_DMA_CTRL_TX_DMA_EN) || ((DMA_CTRL) == QSPI_DMA_CTRL_RX_DMA_EN)) + +#define IS_QSPI_DMATDL_CTRL(DMATDL_CTRL) (((DMATDL_CTRL) <= 0x3F)) + +#define IS_QSPI_DMARDL_CTRL(DMARDL_CTRL) (((DMARDL_CTRL) <= 0x3F)) + +#define IS_QSPI_SES(SES) (((SES) == QSPI_RS_DELAY_SES_RISING_EDGE) || ((SES) == QSPI_RS_DELAY_SES_FALLING_EDGE)) + +#define IS_QSPI_SDCN(SDCN) (((SDCN) <= 0xFF)) + +#define IS_QSPI_ENH_CLK_STRETCH_EN(ENH_CLK_STRETCH_EN) (((ENH_CLK_STRETCH_EN) == QSPI_ENH_CTRL0_CLK_STRETCH_EN) || ((ENH_CLK_STRETCH_EN) == 0)) + +#define IS_QSPI_ENH_XIP_MBL(ENH_XIP_MBL) \ + (((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_2_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_4_BIT) || \ + ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_8_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_16_BIT)) + +#define IS_QSPI_ENH_XIP_CT_EN(ENH_XIP_CT_EN) (((ENH_XIP_CT_EN) == QSPI_ENH_CTRL0_XIP_CT_EN) || ((ENH_XIP_CT_EN) == 0)) + +#define IS_QSPI_ENH_XIP_INST_EN(ENH_XIP_INST_EN) (((ENH_XIP_INST_EN) == QSPI_ENH_CTRL0_XIP_INST_EN) || ((ENH_XIP_INST_EN) == 0)) + +#define IS_QSPI_ENH_XIP_DFS_HC(ENH_XIP_DFS_HC) (((ENH_XIP_DFS_HC) == QSPI_ENH_CTRL0_XIP_DFS_HC) || ((ENH_XIP_DFS_HC) == 0)) + +#define IS_QSPI_ENH_INST_DDR_EN(ENH_INST_DDR_EN) (((ENH_INST_DDR_EN) == QSPI_ENH_CTRL0_INST_DDR_EN) || ((ENH_INST_DDR_EN) == 0)) + +#define IS_QSPI_ENH_SPI_DDR_EN(ENH_SPI_DDR_EN) (((ENH_SPI_DDR_EN) == QSPI_ENH_CTRL0_SPI_DDR_EN) || ((ENH_SPI_DDR_EN) == 0)) + +#define IS_QSPI_ENH_WAIT_CYCLES(ENH_WAIT_CYCLES) ((((ENH_WAIT_CYCLES) >= QSPI_ENH_CTRL0_WAIT_1CYCLES) && ((ENH_WAIT_CYCLES) <= QSPI_ENH_CTRL0_WAIT_31CYCLES)) || \ + ((ENH_WAIT_CYCLES) == 0)) + +#define IS_QSPI_ENH_INST_L(ENH_INST_L) \ + (((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) || \ + ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_8_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_16_LINE)) + +#define IS_QSPI_ENH_MD_BIT_EN(ENH_MD_BIT_EN) (((ENH_MD_BIT_EN) == QSPI_ENH_CTRL0_MD_BIT_EN) || ((ENH_MD_BIT_EN) == 0)) + +#define IS_QSPI_ENH_ADDR_LEN(ENH_ADDR_LEN) ((((ENH_ADDR_LEN) >= QSPI_ENH_CTRL0_ADDR_LEN_4_BIT) && ((ENH_ADDR_LEN) <= QSPI_ENH_CTRL0_ADDR_LEN_60_BIT)) || \ + ((ENH_ADDR_LEN) == 0)) + +#define IS_QSPI_ENH_TRANS_TYPE(ENH_TRANS_TYPE) (((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD) || \ + ((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF) || \ + ((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF)) + + +#define IS_QSPI_DDR_TXDE(DDR_TXDE) (((DDR_TXDE) <= 0xFF)) + +#define IS_QSPI_XIP_MODE(XIP_MODE) (((XIP_MODE) <= 0xFFFF)) + +#define IS_QSPI_XIP_INCR_TOC(XIP_INCR_TOC) (((XIP_INCR_TOC) <= 0xFFFF)) + +#define IS_QSPI_XIP_WRAP_TOC(XIP_WRAP_TOC) (((XIP_WRAP_TOC) <= 0xFFFF)) + +#define IS_QSPI_XIP_TOUT(XIP_TOUT) (((XIP_TOUT) <= 0xFF)) + +#define IS_QSPI_XIP_MBL(XIP_MBL) \ + (((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_2_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_4_BIT) || \ + ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_8_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_16_BIT)) + +#define IS_QSPI_XIP_CT_EN(XIP_CT_EN) (((XIP_CT_EN) == QSPI_XIP_CTRL_XIP_CT_EN) || ((XIP_CT_EN) == 0)) + +#define IS_QSPI_XIP_INST_EN(XIP_INST_EN) (((XIP_INST_EN) == QSPI_XIP_CTRL_XIP_INST_EN) || ((XIP_INST_EN) == 0)) + +#define IS_QSPI_INST_DDR_EN(INST_DDR_EN) (((INST_DDR_EN) == QSPI_XIP_CTRL_XIP_INST_EN) || ((INST_DDR_EN) == 0)) + +#define IS_QSPI_DDR_EN(DDR_EN) (((DDR_EN) == QSPI_XIP_CTRL_DDR_EN) || ((DDR_EN) == 0)) + +#define IS_QSPI_XIP_DFS_HC(XIP_DFS_HC) (((XIP_DFS_HC) == QSPI_XIP_CTRL_DFS_HC) || ((XIP_DFS_HC) == 0)) + +#define IS_QSPI_XIP_WAIT_CYCLES(XIP_WAIT_CYCLES) ((((XIP_WAIT_CYCLES) >= QSPI_XIP_CTRL_WAIT_1CYCLES) && ((XIP_WAIT_CYCLES) <= QSPI_XIP_CTRL_WAIT_31CYCLES)) || \ + ((XIP_WAIT_CYCLES) == 0)) + +#define IS_QSPI_XIP_MD_BIT_EN(XIP_MD_BIT_EN) (((XIP_MD_BIT_EN) == QSPI_XIP_CTRL_MD_BIT_EN) || ((XIP_MD_BIT_EN) == 0)) + +#define IS_QSPI_XIP_INST_L(XIP_INST_L) \ + (((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_0_LINE) || ((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_4_LINE) || \ + ((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_8_LINE) || ((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_16_LINE)) + +#define IS_QSPI_XIP_ADDR_LEN(XIP_ADDR_LEN) ((((XIP_ADDR_LEN) >= QSPI_XIP_CTRL_ADDR_4BIT) && ((XIP_ADDR_LEN) <= QSPI_XIP_CTRL_ADDR_60BIT)) || \ + ((XIP_ADDR_LEN) == 0)) + +#define IS_QSPI_XIP_TRANS_TYPE(XIP_TRANS_TYPE) (((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_STANDARD_SPI) || \ + ((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_ADDRESS_BY_XIP_FRF) || \ + ((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF)) + +#define IS_QSPI_XIP_FRF(XIP_FRF) (((XIP_FRF) == QSPI_XIP_CTRL_FRF_2_LINE) || ((XIP_FRF) == QSPI_XIP_CTRL_FRF_4_LINE) || ((XIP_FRF) == 0)) + + + + + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +void QSPI_Cmd(bool cmd); +void QSPI_XIP_Cmd(bool cmd); +void QSPI_DeInit(void); +void QspiInitConfig(QSPI_InitType* QSPI_InitStruct); +void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Output); +void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel); +uint16_t QSPI_GetITStatus(uint16_t FLAG); +void QSPI_ClearITFLAG(uint16_t FLAG); +void QSPI_XIP_ClearITFLAG(uint16_t FLAG); +bool GetQspiBusyStatus(void); +bool GetQspiTxDataBusyStatus(void); +bool GetQspiTxDataEmptyStatus(void); +bool GetQspiRxHaveDataStatus(void); +bool GetQspiRxDataFullStatus(void); +bool GetQspiTransmitErrorStatus(void); +bool GetQspiDataConflictErrorStatus(void); +void QspiSendWord(uint32_t SendData); +uint32_t QspiReadWord(void); +uint32_t QspiGetDataPointer(void); +uint32_t QspiReadRxFifoNum(void); +void ClrFifo(void); +uint32_t GetFifoData(uint32_t* pData, uint32_t Len); +void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt); +uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t LastRd); + + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_QSPI_H__ */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_rcc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_rcc.h new file mode 100644 index 0000000000..54befad93b --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_rcc.h @@ -0,0 +1,714 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_rcc.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_RCC_H__ +#define __N32G45X_RCC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */ + uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */ +} RCC_ClocksType; + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Constants + * @{ + */ + +/** @addtogroup HSE_configuration + * @{ + */ + +#define RC_HSE_DISABLE ((uint32_t)0x00000000) +#define RCC_HSE_ENABLE ((uint32_t)0x00010000) +#define RCC_HSE_BYPASS ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS)) + +/** + * @} + */ + +/** @addtogroup PLL_entry_clock_source + * @{ + */ + +#define RCC_PLL_SRC_HSI_DIV2 ((uint32_t)0x00000000) + +#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000) +#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000) +#define IS_RCC_PLL_SRC(SOURCE) \ + (((SOURCE) == RCC_PLL_SRC_HSI_DIV2) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2)) + +/** + * @} + */ + +/** @addtogroup PLL_multiplication_factor + * @{ + */ +#define RCC_PLL_MUL_2 ((uint32_t)0x00000000) +#define RCC_PLL_MUL_3 ((uint32_t)0x00040000) +#define RCC_PLL_MUL_4 ((uint32_t)0x00080000) +#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000) +#define RCC_PLL_MUL_6 ((uint32_t)0x00100000) +#define RCC_PLL_MUL_7 ((uint32_t)0x00140000) +#define RCC_PLL_MUL_8 ((uint32_t)0x00180000) +#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000) +#define RCC_PLL_MUL_10 ((uint32_t)0x00200000) +#define RCC_PLL_MUL_11 ((uint32_t)0x00240000) +#define RCC_PLL_MUL_12 ((uint32_t)0x00280000) +#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000) +#define RCC_PLL_MUL_14 ((uint32_t)0x00300000) +#define RCC_PLL_MUL_15 ((uint32_t)0x00340000) +#define RCC_PLL_MUL_16 ((uint32_t)0x00380000) +#define RCC_PLL_MUL_17 ((uint32_t)0x08000000) +#define RCC_PLL_MUL_18 ((uint32_t)0x08040000) +#define RCC_PLL_MUL_19 ((uint32_t)0x08080000) +#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000) +#define RCC_PLL_MUL_21 ((uint32_t)0x08100000) +#define RCC_PLL_MUL_22 ((uint32_t)0x08140000) +#define RCC_PLL_MUL_23 ((uint32_t)0x08180000) +#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000) +#define RCC_PLL_MUL_25 ((uint32_t)0x08200000) +#define RCC_PLL_MUL_26 ((uint32_t)0x08240000) +#define RCC_PLL_MUL_27 ((uint32_t)0x08280000) +#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000) +#define RCC_PLL_MUL_29 ((uint32_t)0x08300000) +#define RCC_PLL_MUL_30 ((uint32_t)0x08340000) +#define RCC_PLL_MUL_31 ((uint32_t)0x08380000) +#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000) +#define IS_RCC_PLL_MUL(MUL) \ + (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \ + || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \ + || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \ + || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \ + || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \ + || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \ + || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \ + || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \ + || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \ + || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32)) + +/** + * @} + */ + +/** @addtogroup System_clock_source + * @{ + */ + +#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_SYSCLK_SRC_HSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK)) +/** + * @} + */ + +/** @addtogroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0) +#define IS_RCC_SYSCLK_DIV(HCLK) \ + (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \ + || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \ + || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512)) +/** + * @} + */ + +/** @addtogroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_HCLK_DIV2 ((uint32_t)0x00000400) +#define RCC_HCLK_DIV4 ((uint32_t)0x00000500) +#define RCC_HCLK_DIV8 ((uint32_t)0x00000600) +#define RCC_HCLK_DIV16 ((uint32_t)0x00000700) +#define IS_RCC_HCLK_DIV(PCLK) \ + (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \ + || ((PCLK) == RCC_HCLK_DIV16)) +/** + * @} + */ + +/** @addtogroup RCC_Interrupt_source + * @{ + */ + +#define RCC_INT_LSIRDIF ((uint8_t)0x01) +#define RCC_INT_LSERDIF ((uint8_t)0x02) +#define RCC_INT_HSIRDIF ((uint8_t)0x04) +#define RCC_INT_HSERDIF ((uint8_t)0x08) +#define RCC_INT_PLLRDIF ((uint8_t)0x10) +#define RCC_INT_CLKSSIF ((uint8_t)0x80) + +#define IS_RCC_INT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_INT(IT) \ + (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \ + || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_CLKSSIF)) +#define IS_RCC_CLR_INT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @addtogroup USB_Device_clock_source + * @{ + */ + +#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00) +#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01) +#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02) +#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03) + +#define IS_RCC_USBCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \ + || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3)) +/** + * @} + */ + +/** @addtogroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000) +#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000) +#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000) +#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000) +#define IS_RCC_PCLK2_DIV(ADCCLK) \ + (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \ + || ((ADCCLK) == RCC_PCLK2_DIV8)) + +/** + * @} + */ + +/** @addtogroup RCC_CFGR2_Config + * @{ + */ +#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000) +#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000) +#define IS_RCC_TIM18CLKSRC(TIM18CLK) \ + (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK)) + +#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000) +#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000) +#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000) +#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000) +#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000) +#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000) +#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000) +#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000) +#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000) +#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000) +#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000) +#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000) +#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000) +#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000) +#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000) +#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000) +#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000) +#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000) +#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000) +#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000) +#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000) +#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000) +#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000) +#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000) +#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000) +#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000) +#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000) +#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000) +#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000) +#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000) +#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000) +#define IS_RCC_RNGCCLKPRE(DIV) \ + (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \ + || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32)) + +#define RCC_ETHCLK_SRC_IOINPUTCLK ((uint32_t)0x00000000) +#define RCC_ETHCLK_SRC_INTERNALCLK ((uint32_t)0x00100000) +#define IS_RCC_ETHCLK_SRC(ETHCLK) (((ETHCLK) == RCC_ETHCLK_SRC_IOINPUTCLK) || ((ETHCLK) == RCC_ETHCLK_SRC_INTERNALCLK)) + +#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00020000) +#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE)) + +#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00000800) +#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00001000) +#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00001800) +#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00002000) +#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00002800) +#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00003000) +#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00003800) +#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00004000) +#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00004800) +#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x00005000) +#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x00005800) +#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x00006000) +#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x00006800) +#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x00007000) +#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x00007800) +#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00008000) +#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00008800) +#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00009000) +#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00009800) +#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x0000A000) +#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x0000A800) +#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x0000B000) +#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x0000B800) +#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x0000C000) +#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x0000C800) +#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0000D000) +#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0000D800) +#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0000E000) +#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0000E800) +#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0000F000) +#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0000F800) +#define IS_RCC_ADC1MCLKPRE(DIV) \ + (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \ + || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \ + || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \ + || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \ + || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \ + || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \ + || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \ + || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \ + || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \ + || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \ + || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32)) + +#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) +#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100) +#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110) +#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120) +#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130) +#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140) +#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150) +#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160) +#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170) +#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180) +#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190) +#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0) +#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0) +#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0) +#define IS_RCC_ADCPLLCLKPRE(DIV) \ + (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \ + || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \ + || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \ + || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \ + || ((DIV) == RCC_ADC1MCLK_DIV15) || ((DIV) == RCC_ADCPLLCLK_DIV16) \ + || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0)) + +#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001) +#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002) +#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003) +#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004) +#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005) +#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006) +#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007) +#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008) +#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008) +#define IS_RCC_ADCHCLKPRE(DIV) \ + (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \ + || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \ + || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \ + || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00)) +/** + * @} + */ + +/** @addtogroup RCC_CFGR3_Config + * @{ + */ +#define RCC_BOR_RST_ENABLE ((uint32_t)0x00000040) + +#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000) +#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF) + +#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000) +#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000) +#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \ + (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE)) + +#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800) +#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001800) +#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00002800) +#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00003800) +#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00004800) +#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00005800) +#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00006800) +#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00007800) +#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00008800) +#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00009800) +#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x0000A800) +#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x0000B800) +#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x0000C800) +#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x0000D800) +#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x0000E800) +#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x0000F800) +#define IS_RCC_TRNG1MCLKPRE(VAL) \ + (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \ + || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \ + || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \ + || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \ + || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \ + || ((VAL) == RCC_TRNG1MCLK_DIV32)) + +/** + * @} + */ + +/** @addtogroup LSE_configuration + * @{ + */ + +#define RCC_LSE_DISABLE ((uint8_t)0x00) +#define RCC_LSE_ENABLE ((uint8_t)0x01) +#define RCC_LSE_BYPASS ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS)) +/** + * @} + */ + +/** @addtogroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLK_SRC_HSE_DIV128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SRC(SOURCE) \ + (((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV128)) +/** + * @} + */ + +/** @addtogroup AHB_peripheral + * @{ + */ + +#define RCC_AHB_PERIPH_DMA1 ((uint32_t)0x00000001) +#define RCC_AHB_PERIPH_DMA2 ((uint32_t)0x00000002) +#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004) +#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010) +#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040) +#define RCC_AHB_PERIPH_XFMC ((uint32_t)0x00000100) +#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200) +#define RCC_AHB_PERIPH_SDIO ((uint32_t)0x00000400) +#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800) +#define RCC_AHB_PERIPH_ADC1 ((uint32_t)0x00001000) +#define RCC_AHB_PERIPH_ADC2 ((uint32_t)0x00002000) +#define RCC_AHB_PERIPH_ADC3 ((uint32_t)0x00004000) +#define RCC_AHB_PERIPH_ADC4 ((uint32_t)0x00008000) +#define RCC_AHB_PERIPH_ETHMAC ((uint32_t)0x00010000) +#define RCC_AHB_PERIPH_QSPI ((uint32_t)0x00020000) + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFC02A8) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @addtogroup APB2_peripheral + * @{ + */ + +#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001) +#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2_PERIPH_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2_PERIPH_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2_PERIPH_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000) +#define RCC_APB2_PERIPH_DVP ((uint32_t)0x00010000) +#define RCC_APB2_PERIPH_UART6 ((uint32_t)0x00020000) +#define RCC_APB2_PERIPH_UART7 ((uint32_t)0x00040000) +#define RCC_APB2_PERIPH_I2C3 ((uint32_t)0x00080000) +#define RCC_APB2_PERIPH_I2C4 ((uint32_t)0x00100000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFE08602) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @addtogroup APB1_peripheral + * @{ + */ + +#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040) +#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080) +#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400) +#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800) +#define RCC_APB1_PERIPH_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1_PERIPH_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000) +#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000) +#define RCC_APB1_PERIPH_UART4 ((uint32_t)0x00080000) +#define RCC_APB1_PERIPH_UART5 ((uint32_t)0x00100000) +#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000) +#define RCC_APB1_PERIPH_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1_PERIPH_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1_PERIPH_BKP ((uint32_t)0x08000000) +#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000) +#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000) +#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x41013300) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +#define RCC_MCO_PLLCLK_DIV2 ((uint32_t)0x20000000) +#define RCC_MCO_PLLCLK_DIV3 ((uint32_t)0x30000000) +#define RCC_MCO_PLLCLK_DIV4 ((uint32_t)0x40000000) +#define RCC_MCO_PLLCLK_DIV5 ((uint32_t)0x50000000) +#define RCC_MCO_PLLCLK_DIV6 ((uint32_t)0x60000000) +#define RCC_MCO_PLLCLK_DIV7 ((uint32_t)0x70000000) +#define RCC_MCO_PLLCLK_DIV8 ((uint32_t)0x80000000) +#define RCC_MCO_PLLCLK_DIV9 ((uint32_t)0x90000000) +#define RCC_MCO_PLLCLK_DIV10 ((uint32_t)0xA0000000) +#define RCC_MCO_PLLCLK_DIV11 ((uint32_t)0xB0000000) +#define RCC_MCO_PLLCLK_DIV12 ((uint32_t)0xC0000000) +#define RCC_MCO_PLLCLK_DIV13 ((uint32_t)0xD0000000) +#define RCC_MCO_PLLCLK_DIV14 ((uint32_t)0xE0000000) +#define RCC_MCO_PLLCLK_DIV15 ((uint32_t)0xF0000000) +#define IS_RCC_MCOPLLCLKPRE(DIV) \ + (((DIV) == RCC_MCO_PLLCLK_DIV2) || ((DIV) == RCC_MCO_PLLCLK_DIV3) || ((DIV) == RCC_MCO_PLLCLK_DIV4) \ + || ((DIV) == RCC_MCO_PLLCLK_DIV5) || ((DIV) == RCC_MCO_PLLCLK_DIV6) || ((DIV) == RCC_MCO_PLLCLK_DIV7) \ + || ((DIV) == RCC_MCO_PLLCLK_DIV8) || ((DIV) == RCC_MCO_PLLCLK_DIV9) || ((DIV) == RCC_MCO_PLLCLK_DIV10) \ + || ((DIV) == RCC_MCO_PLLCLK_DIV11) || ((DIV) == RCC_MCO_PLLCLK_DIV12) || ((DIV) == RCC_MCO_PLLCLK_DIV13) \ + || ((DIV) == RCC_MCO_PLLCLK_DIV14) || ((DIV) == RCC_MCO_PLLCLK_DIV15)) + +/** @addtogroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NOCLK ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + +#define IS_RCC_MCO(MCO) \ + (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) \ + || ((MCO) == RCC_MCO_PLLCLK)) + +/** + * @} + */ + +/** @addtogroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSIRD ((uint8_t)0x21) +#define RCC_FLAG_HSERD ((uint8_t)0x31) +#define RCC_FLAG_PLLRD ((uint8_t)0x39) +#define RCC_FLAG_LSERD ((uint8_t)0x41) +#define RCC_FLAG_LSIRD ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x73) +#define RCC_FLAG_RETEMC ((uint8_t)0x74) +#define RCC_FLAG_BKPEMC ((uint8_t)0x75) +#define RCC_FLAG_RAMRST ((uint8_t)0x77) +#define RCC_FLAG_MMURST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#define IS_RCC_FLAG(FLAG) \ + (((FLAG) == RCC_FLAG_HSIRD) || ((FLAG) == RCC_FLAG_HSERD) || ((FLAG) == RCC_FLAG_PLLRD) \ + || ((FLAG) == RCC_FLAG_LSERD) || ((FLAG) == RCC_FLAG_LSIRD) || ((FLAG) == RCC_FLAG_BORRST) \ + || ((FLAG) == RCC_FLAG_RETEMC) || ((FLAG) == RCC_FLAG_BKPEMC) || ((FLAG) == RCC_FLAG_RAMRST) \ + || ((FLAG) == RCC_FLAG_MMURST) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) \ + || ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || ((FLAG) == RCC_FLAG_WWDGRST) \ + || ((FLAG) == RCC_FLAG_LPWRRST)) + +#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_ConfigHse(uint32_t RCC_HSE); +ErrorStatus RCC_WaitHseStable(void); +void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue); +void RCC_EnableHsi(FunctionalState Cmd); +void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_EnablePll(FunctionalState Cmd); + +void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSysclkSrc(void); +void RCC_ConfigHclk(uint32_t RCC_SYSCLK); +void RCC_ConfigPclk1(uint32_t RCC_HCLK); +void RCC_ConfigPclk2(uint32_t RCC_HCLK); +void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd); + +void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource); + +void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource); +void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler); +void RCC_ConfigEthClk(uint32_t RCC_ETHCLKSource); + +void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler); +void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd); +void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler); + +void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler); +void RCC_EnableTrng1mClk(FunctionalState Cmd); + +void RCC_ConfigLse(uint8_t RCC_LSE); +void RCC_EnableLsi(FunctionalState Cmd); +void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource); +void RCC_EnableRtcClk(FunctionalState Cmd); +void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks); +void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd); + +void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd); +void RCC_EnableBORReset(FunctionalState Cmd); +void RCC_EnableBackupReset(FunctionalState Cmd); +void RCC_EnableClockSecuritySystem(FunctionalState Cmd); +void RCC_ConfigMcoPllClk(uint32_t RCC_MCOPLLCLKPrescaler); +void RCC_ConfigMco(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClrFlag(void); +INTStatus RCC_GetIntStatus(uint8_t RccInt); +void RCC_ClrIntPendingBit(uint8_t RccInt); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_RCC_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_rtc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_rtc.h new file mode 100644 index 0000000000..8e8d94a810 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_rtc.h @@ -0,0 +1,662 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_rtc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_RTC_H__ +#define __N32G45X_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x7FFF */ +} RTC_InitType; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_12HOUR_FORMAT is selected or 0-23 range if + the RTC_24HOUR_FORMAT is selected. */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +} RTC_TimeType; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +} RTC_DateType; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter + must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this + parameter can be a value of @ref RTC_WeekDay_Definitions */ +} RTC_AlarmType; + +/** @addtogroup RTC_Exported_Constants + * @{ + */ + +/** @addtogroup RTC_Hour_Formats + * @{ + */ +#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000) +#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT)) +/** + * @} + */ + +/** @addtogroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + +/** @addtogroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @addtogroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_AM_H12 ((uint8_t)0x00) +#define RTC_PM_H12 ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12)) + +/** + * @} + */ + +/** @addtogroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @addtogroup RTC_Month_Date_Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRURY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @addtogroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) \ + (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \ + (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \ + || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +/** + * @} + */ + +/** @addtogroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000) +#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \ + (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY)) + +/** + * @} + */ + +/** @addtogroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000) +#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000) +#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000) +#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080) +#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @addtogroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_A_ALARM ((uint32_t)0x00000100) +#define RTC_B_ALARM ((uint32_t)0x00000200) +#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM)) +#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions + * @{ + */ +#define RTC_SUBS_MASK_ALL \ + ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \ + There is no comparison on sub seconds \ + for Alarm */ +#define RTC_SUBS_MASK_SS14_1 \ + ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \ + comparison. Only SS[0] is compared. */ +#define RTC_SUBS_MASK_SS14_2 \ + ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \ + comparison. Only SS[1:0] are compared */ +#define RTC_SUBS_MASK_SS14_3 \ + ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \ + comparison. Only SS[2:0] are compared */ +#define RTC_SUBS_MASK_SS14_4 \ + ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \ + comparison. Only SS[3:0] are compared */ +#define RTC_SUBS_MASK_SS14_5 \ + ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \ + comparison. Only SS[4:0] are compared */ +#define RTC_SUBS_MASK_SS14_6 \ + ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \ + comparison. Only SS[5:0] are compared */ +#define RTC_SUBS_MASK_SS14_7 \ + ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \ + comparison. Only SS[6:0] are compared */ +#define RTC_SUBS_MASK_SS14_8 \ + ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \ + comparison. Only SS[7:0] are compared */ +#define RTC_SUBS_MASK_SS14_9 \ + ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \ + comparison. Only SS[8:0] are compared */ +#define RTC_SUBS_MASK_SS14_10 \ + ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \ + comparison. Only SS[9:0] are compared */ +#define RTC_SUBS_MASK_SS14_11 \ + ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \ + comparison. Only SS[10:0] are compared */ +#define RTC_SUBS_MASK_SS14_12 \ + ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \ + comparison.Only SS[11:0] are compared */ +#define RTC_SUBS_MASK_SS14_13 \ + ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \ + comparison. Only SS[12:0] are compared */ +#define RTC_SUBS_MASK_SS14_14 \ + ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \ + comparison.Only SS[13:0] are compared */ +#define RTC_SUBS_MASK_NONE \ + ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \ + to activate alarm. */ +#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \ + (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \ + || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \ + || ((INTEN) == RTC_SUBS_MASK_NONE)) +/** + * @} + */ + +/** @addtogroup RTC_Alarm_Sub_Seconds_Value + * @{ + */ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Wakeup_Timer_Definitions + * @{ + */ +#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001) +#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002) +#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003) +#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004) + +#define IS_RTC_WKUP_CLOCK(CLOCK) \ + (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \ + || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \ + || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS)) +#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @addtogroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \ + (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING)) +/** + * @} + */ + +/** @addtogroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_OUTPUT_DIS ((uint32_t)0x00000000) +#define RTC_OUTPUT_ALA ((uint32_t)0x00200000) +#define RTC_OUTPUT_ALB ((uint32_t)0x00400000) +#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT_MODE(OUTPUT) \ + (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \ + || ((OUTPUT) == RTC_OUTPUT_WKUP)) + +/** + * @} + */ + +/** @addtogroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000) +#define RTC_OUTPOL_LOW ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW)) +/** + * @} + */ + + +/** @addtogroup RTC_Calib_Output_selection_Definitions + * @{ + */ +#define RTC_CALIB_OUTPUT_256HZ ((uint32_t)0x00000000) +#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ)) +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_period_Definitions + * @{ + */ +#define SMOOTH_CALIB_32SEC \ + ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 32s, else 2exp20 RTCCLK seconds */ +#define SMOOTH_CALIB_16SEC \ + ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 16s, else 2exp19 RTCCLK seconds */ +#define SMOOTH_CALIB_8SEC \ + ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \ + period is 8s, else 2exp18 RTCCLK seconds */ +#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \ + (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC)) + +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions + * @{ + */ +#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \ + ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \ + during a X -second window = Y - CALM[8:0]. \ + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \ + ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \ + during a 32-second window = CALM[8:0]. */ +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \ + (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET)) + +/** + * @} + */ + +/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) + +/** + * @} + */ + +/** @addtogroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000) +#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H)) + +#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000) +#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) \ + (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET)) +/** + * @} + */ + +/** @addtogroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL)) + +/** + * @} + */ +/** @addtogroup RTC_Add_Fraction_Of_Second_Value + * @{ + */ +#define RTC_SHIFT_SUB1S_DISABLE ((uint32_t)0x00000000) +#define RTC_SHIFT_SUB1S_ENABLE ((uint32_t)0x80000000) +#define IS_RTC_SHIFT_SUB1S(SEL) (((SEL) == RTC_SHIFT_SUB1S_DISABLE) || ((SEL) == RTC_SHIFT_SUB1S_ENABLE)) +/** + * @} + */ +/** @addtogroup RTC_Substract_1_Second_Parameter_Definitions + * @{ + */ +#define IS_RTC_SHIFT_ADFS(FS) ((FS) <= 0x00007FFF) + +/** + * @} + */ + +/** @addtogroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_FORMAT_BIN ((uint32_t)0x000000000) +#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) + +/** + * @} + */ + +/** @addtogroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_RECPF ((uint32_t)0x00010000) +#define RTC_FLAG_TISOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TISF ((uint32_t)0x00000800) +#define RTC_FLAG_WTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSYF ((uint32_t)0x00000020) +#define RTC_FLAG_INITSF ((uint32_t)0x00000010) +#define RTC_FLAG_SHOPF ((uint32_t)0x00000008) +#define RTC_FLAG_WTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALAWF ((uint32_t)0x00000001) +#define IS_RTC_GET_FLAG(FLAG) \ + (((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) \ + || ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || ((FLAG) == RTC_FLAG_RSYF) \ + || ((FLAG) == RTC_FLAG_WTWF) || ((FLAG) == RTC_FLAG_ALBWF) || ((FLAG) == RTC_FLAG_ALAWF) \ + || ((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_INITSF)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG)&0x00011fff) == (uint32_t)SET)) + +/** + * @} + */ + +/** @addtogroup RTC_Interrupts_Definitions + * @{ + */ + +#define RTC_INT_WUT ((uint32_t)0x00004000) +#define RTC_INT_ALRB ((uint32_t)0x00002000) +#define RTC_INT_ALRA ((uint32_t)0x00001000) + +#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_INT(IT) \ + (((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA)) +#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0x00007000) == (uint32_t)SET)) + +/** + * @} + */ + +/** @addtogroup RTC_Legacy + * @{ + */ +#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig +#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd + +/** + * @} + */ + +/** + * @} + */ + +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct); +void RTC_StructInit(RTC_InitType* RTC_InitStruct); +void RTC_EnableWriteProtection(FunctionalState Cmd); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd); +void RTC_EnableBypassShadow(FunctionalState Cmd); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +uint32_t RTC_GetSubSecond(void); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); + +/* Alarms (Alarm A and Alarm B) configuration functions **********************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd); +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd); + +/* Daylight Saving configuration functions ************************************/ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Coarse and Smooth Calibration configuration functions **********************/ +void RTC_EnableCalibOutput(FunctionalState Cmd); +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput); +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/* TimeStamp configuration functions ******************************************/ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct); +uint32_t RTC_GetTimeStampSubSecond(void); + +/* Output Type Config configuration functions *********************************/ +void RTC_ConfigOutputType(uint32_t RTC_OutputType); + +/* RTC_Shift_control_synchonisation_functions *********************************/ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAddFS, uint32_t RTC_ShiftSub1s); + +/* Interrupts and flags management functions **********************************/ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClrFlag(uint32_t RTC_FLAG); +INTStatus RTC_GetITStatus(uint32_t RTC_INT); +void RTC_ClrIntPendingBit(uint32_t RTC_INT); +/* WakeUp TSC function **********************************/ +void RTC_EnableWakeUpTsc(uint32_t count); +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_RTC_H__ */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_sdio.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_sdio.h new file mode 100644 index 0000000000..c70eb58b8b --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_sdio.h @@ -0,0 +1,494 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_sdio.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_SDIO_H__ +#define __N32G45X_SDIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @addtogroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t ClkEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t ClkBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t ClkPwrSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t BusWidth; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t HardwareClkCtrl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t ClkDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitType; + +typedef struct +{ + uint32_t CmdArgument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t ResponseType; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t WaitType; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t CPSMConfig; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitType; + +typedef struct +{ + uint32_t DatTimeout; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t DatLen; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t DatBlkSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t TransferDirection; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t DPSMConfig; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitType; + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Constants + * @{ + */ + +/** @addtogroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_CLKEDGE_RISING ((uint32_t)0x00000000) +#define SDIO_CLKEDGE_FALLING ((uint32_t)0x00002000) +#define IS_SDIO_CLK_EDGE(EDGE) (((EDGE) == SDIO_CLKEDGE_RISING) || ((EDGE) == SDIO_CLKEDGE_FALLING)) +/** + * @} + */ + +/** @addtogroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClkBYPASS_DISABLE ((uint32_t)0x00000000) +#define SDIO_ClkBYPASS_ENABLE ((uint32_t)0x00000400) +#define IS_SDIO_CLK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClkBYPASS_DISABLE) || ((BYPASS) == SDIO_ClkBYPASS_ENABLE)) +/** + * @} + */ + +/** @addtogroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_CLKPOWERSAVE_DISABLE ((uint32_t)0x00000000) +#define SDIO_CLKPOWERSAVE_ENABLE ((uint32_t)0x00000200) +#define IS_SDIO_CLK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLKPOWERSAVE_DISABLE) || ((SAVE) == SDIO_CLKPOWERSAVE_ENABLE)) +/** + * @} + */ + +/** @addtogroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BUSWIDTH_1B ((uint32_t)0x00000000) +#define SDIO_BUSWIDTH_4B ((uint32_t)0x00000800) +#define SDIO_BUSWIDTH_8B ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDTH(WIDE) \ + (((WIDE) == SDIO_BUSWIDTH_1B) || ((WIDE) == SDIO_BUSWIDTH_4B) || ((WIDE) == SDIO_BUSWIDTH_8B)) + +/** + * @} + */ + +/** @addtogroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HARDWARE_CLKCTRL_DISABLE ((uint32_t)0x00000000) +#define SDIO_HARDWARE_CLKCTRL_ENABLE ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_CLKCTRL(CONTROL) \ + (((CONTROL) == SDIO_HARDWARE_CLKCTRL_DISABLE) || ((CONTROL) == SDIO_HARDWARE_CLKCTRL_ENABLE)) +/** + * @} + */ + +/** @addtogroup SDIO_Power_State + * @{ + */ + +#define SDIO_POWER_CTRL_OFF ((uint32_t)0x00000000) +#define SDIO_POWER_CTRL_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_CTRL(STATE) (((STATE) == SDIO_POWER_CTRL_OFF) || ((STATE) == SDIO_POWER_CTRL_ON)) +/** + * @} + */ + +/** @addtogroup SDIO_Interrupt_sources + * @{ + */ + +#define SDIO_INT_CCRCERR ((uint32_t)0x00000001) +#define SDIO_INT_DCRCERR ((uint32_t)0x00000002) +#define SDIO_INT_CMDTIMEOUT ((uint32_t)0x00000004) +#define SDIO_INT_DATTIMEOUT ((uint32_t)0x00000008) +#define SDIO_INT_TXURERR ((uint32_t)0x00000010) +#define SDIO_INT_RXORERR ((uint32_t)0x00000020) +#define SDIO_INT_CMDRESPRECV ((uint32_t)0x00000040) +#define SDIO_INT_CMDSEND ((uint32_t)0x00000080) +#define SDIO_INT_DATEND ((uint32_t)0x00000100) +#define SDIO_INT_SBERR ((uint32_t)0x00000200) +#define SDIO_INT_DATBLKEND ((uint32_t)0x00000400) +#define SDIO_INT_CMDRUN ((uint32_t)0x00000800) +#define SDIO_INT_TXRUN ((uint32_t)0x00001000) +#define SDIO_INT_RXRUN ((uint32_t)0x00002000) +#define SDIO_INT_TFIFOHE ((uint32_t)0x00004000) +#define SDIO_INT_RFIFOHF ((uint32_t)0x00008000) +#define SDIO_INT_TFIFOF ((uint32_t)0x00010000) +#define SDIO_INT_RFIFOF ((uint32_t)0x00020000) +#define SDIO_INT_TFIFOE ((uint32_t)0x00040000) +#define SDIO_INT_RFIFOE ((uint32_t)0x00080000) +#define SDIO_INT_TDATVALID ((uint32_t)0x00100000) +#define SDIO_INT_RDATVALID ((uint32_t)0x00200000) +#define SDIO_INT_SDIOINT ((uint32_t)0x00400000) +#define SDIO_INT_CEATAF ((uint32_t)0x00800000) +#define IS_SDIO_INT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @addtogroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @addtogroup SDIO_Response_Type + * @{ + */ + +#define SDIO_RESP_NO ((uint32_t)0x00000000) +#define SDIO_RESP_SHORT ((uint32_t)0x00000040) +#define SDIO_RESP_LONG ((uint32_t)0x000000C0) +#define IS_SDIO_RESP(RESPONSE) \ + (((RESPONSE) == SDIO_RESP_NO) || ((RESPONSE) == SDIO_RESP_SHORT) || ((RESPONSE) == SDIO_RESP_LONG)) +/** + * @} + */ + +/** @addtogroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_WAIT_NO ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_WAIT_INT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_WAIT_PEND ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || ((WAIT) == SDIO_WAIT_INT) || ((WAIT) == SDIO_WAIT_PEND)) +/** + * @} + */ + +/** @addtogroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) +#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_ENABLE) || ((CPSM) == SDIO_CPSM_DISABLE)) +/** + * @} + */ + +/** @addtogroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESPONSE_1 ((uint32_t)0x00000000) +#define SDIO_RESPONSE_2 ((uint32_t)0x00000004) +#define SDIO_RESPONSE_3 ((uint32_t)0x00000008) +#define SDIO_RESPONSE_4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESPONSE(RESP) \ + (((RESP) == SDIO_RESPONSE_1) || ((RESP) == SDIO_RESPONSE_2) || ((RESP) == SDIO_RESPONSE_3) \ + || ((RESP) == SDIO_RESPONSE_4)) +/** + * @} + */ + +/** @addtogroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DAT_LEN(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @addtogroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DATBLK_SIZE_1B ((uint32_t)0x00000000) +#define SDIO_DATBLK_SIZE_2B ((uint32_t)0x00000010) +#define SDIO_DATBLK_SIZE_4B ((uint32_t)0x00000020) +#define SDIO_DATBLK_SIZE_8B ((uint32_t)0x00000030) +#define SDIO_DATBLK_SIZE_16B ((uint32_t)0x00000040) +#define SDIO_DATBLK_SIZE_32B ((uint32_t)0x00000050) +#define SDIO_DATBLK_SIZE_64B ((uint32_t)0x00000060) +#define SDIO_DATBLK_SIZE_128B ((uint32_t)0x00000070) +#define SDIO_DATBLK_SIZE_256B ((uint32_t)0x00000080) +#define SDIO_DATBLK_SIZE_512B ((uint32_t)0x00000090) +#define SDIO_DATBLK_SIZE_1024B ((uint32_t)0x000000A0) +#define SDIO_DATBLK_SIZE_2048B ((uint32_t)0x000000B0) +#define SDIO_DATBLK_SIZE_4096B ((uint32_t)0x000000C0) +#define SDIO_DATBLK_SIZE_8192B ((uint32_t)0x000000D0) +#define SDIO_DATBLK_SIZE_16384B ((uint32_t)0x000000E0) +#define IS_SDIO_BLK_SIZE(SIZE) \ + (((SIZE) == SDIO_DATBLK_SIZE_1B) || ((SIZE) == SDIO_DATBLK_SIZE_2B) || ((SIZE) == SDIO_DATBLK_SIZE_4B) \ + || ((SIZE) == SDIO_DATBLK_SIZE_8B) || ((SIZE) == SDIO_DATBLK_SIZE_16B) || ((SIZE) == SDIO_DATBLK_SIZE_32B) \ + || ((SIZE) == SDIO_DATBLK_SIZE_64B) || ((SIZE) == SDIO_DATBLK_SIZE_128B) || ((SIZE) == SDIO_DATBLK_SIZE_256B) \ + || ((SIZE) == SDIO_DATBLK_SIZE_512B) || ((SIZE) == SDIO_DATBLK_SIZE_1024B) || ((SIZE) == SDIO_DATBLK_SIZE_2048B) \ + || ((SIZE) == SDIO_DATBLK_SIZE_4096B) || ((SIZE) == SDIO_DATBLK_SIZE_8192B) \ + || ((SIZE) == SDIO_DATBLK_SIZE_16384B)) +/** + * @} + */ + +/** @addtogroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TRANSDIR_TOCARD ((uint32_t)0x00000000) +#define SDIO_TRANSDIR_TOSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIRECTION(DIR) (((DIR) == SDIO_TRANSDIR_TOCARD) || ((DIR) == SDIO_TRANSDIR_TOSDIO)) +/** + * @} + */ + +/** @addtogroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000) +#define SDIO_TRANSMODE_STREAM ((uint32_t)0x00000004) +#define IS_SDIO_TRANS_MODE(MODE) (((MODE) == SDIO_TRANSMODE_STREAM) || ((MODE) == SDIO_TRANSMODE_BLOCK)) +/** + * @} + */ + +/** @addtogroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) +#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_ENABLE) || ((DPSM) == SDIO_DPSM_DISABLE)) +/** + * @} + */ + +/** @addtogroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCERR ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCERR ((uint32_t)0x00000002) +#define SDIO_FLAG_CMDTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DATTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXURERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXORERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDRESPRECV ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSEND ((uint32_t)0x00000080) +#define SDIO_FLAG_DATEND ((uint32_t)0x00000100) +#define SDIO_FLAG_SBERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DATBLKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDRUN ((uint32_t)0x00000800) +#define SDIO_FLAG_TXRUN ((uint32_t)0x00001000) +#define SDIO_FLAG_RXRUN ((uint32_t)0x00002000) +#define SDIO_FLAG_TFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TDATVALID ((uint32_t)0x00100000) +#define SDIO_FLAG_RDATVALID ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOINT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAF ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) \ + (((FLAG) == SDIO_FLAG_CCRCERR) || ((FLAG) == SDIO_FLAG_DCRCERR) || ((FLAG) == SDIO_FLAG_CMDTIMEOUT) \ + || ((FLAG) == SDIO_FLAG_DATTIMEOUT) || ((FLAG) == SDIO_FLAG_TXURERR) || ((FLAG) == SDIO_FLAG_RXORERR) \ + || ((FLAG) == SDIO_FLAG_CMDRESPRECV) || ((FLAG) == SDIO_FLAG_CMDSEND) || ((FLAG) == SDIO_FLAG_DATEND) \ + || ((FLAG) == SDIO_FLAG_SBERR) || ((FLAG) == SDIO_FLAG_DATBLKEND) || ((FLAG) == SDIO_FLAG_CMDRUN) \ + || ((FLAG) == SDIO_FLAG_TXRUN) || ((FLAG) == SDIO_FLAG_RXRUN) || ((FLAG) == SDIO_FLAG_TFIFOHE) \ + || ((FLAG) == SDIO_FLAG_RFIFOHF) || ((FLAG) == SDIO_FLAG_TFIFOF) || ((FLAG) == SDIO_FLAG_RFIFOF) \ + || ((FLAG) == SDIO_FLAG_TFIFOE) || ((FLAG) == SDIO_FLAG_RFIFOE) || ((FLAG) == SDIO_FLAG_TDATVALID) \ + || ((FLAG) == SDIO_FLAG_RDATVALID) || ((FLAG) == SDIO_FLAG_SDIOINT) || ((FLAG) == SDIO_FLAG_CEATAF)) + +#define IS_SDIO_CLR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_INT(IT) \ + (((IT) == SDIO_INT_CCRCERR) || ((IT) == SDIO_INT_DCRCERR) || ((IT) == SDIO_INT_CMDTIMEOUT) \ + || ((IT) == SDIO_INT_DATTIMEOUT) || ((IT) == SDIO_INT_TXURERR) || ((IT) == SDIO_INT_RXORERR) \ + || ((IT) == SDIO_INT_CMDRESPRECV) || ((IT) == SDIO_INT_CMDSEND) || ((IT) == SDIO_INT_DATEND) \ + || ((IT) == SDIO_INT_SBERR) || ((IT) == SDIO_INT_DATBLKEND) || ((IT) == SDIO_INT_CMDRUN) \ + || ((IT) == SDIO_INT_TXRUN) || ((IT) == SDIO_INT_RXRUN) || ((IT) == SDIO_INT_TFIFOHE) \ + || ((IT) == SDIO_INT_RFIFOHF) || ((IT) == SDIO_INT_TFIFOF) || ((IT) == SDIO_INT_RFIFOF) \ + || ((IT) == SDIO_INT_TFIFOE) || ((IT) == SDIO_INT_RFIFOE) || ((IT) == SDIO_INT_TDATVALID) \ + || ((IT) == SDIO_INT_RDATVALID) || ((IT) == SDIO_INT_SDIOINT) || ((IT) == SDIO_INT_CEATAF)) + +#define IS_SDIO_CLR_INT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @addtogroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_RDWAIT_MODE_CLK ((uint32_t)0x00000001) +#define SDIO_RDWAIT_MODE_DAT2 ((uint32_t)0x00000000) +#define IS_SDIO_RDWAIT_MODE(MODE) (((MODE) == SDIO_RDWAIT_MODE_CLK) || ((MODE) == SDIO_RDWAIT_MODE_DAT2)) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitType* SDIO_InitStruct); +void SDIO_InitStruct(SDIO_InitType* SDIO_InitStruct); +void SDIO_EnableClock(FunctionalState Cmd); +void SDIO_SetPower(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPower(void); +void SDIO_ConfigInt(uint32_t SDIO_IT, FunctionalState Cmd); +void SDIO_DMACmd(FunctionalState Cmd); +void SDIO_SendCmd(SDIO_CmdInitType* SDIO_CmdInitStruct); +void SDIO_InitCmdStruct(SDIO_CmdInitType* SDIO_CmdInitStruct); +uint8_t SDIO_GetCmdResp(void); +uint32_t SDIO_GetResp(uint32_t SDIO_RESP); +void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct); +void SDIO_InitDataStruct(SDIO_DataInitType* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCountValue(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFifoCounter(void); +void SDIO_EnableReadWait(FunctionalState Cmd); +void SDIO_DisableReadWait(FunctionalState Cmd); +void SDIO_EnableSdioReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_EnableSdioOperation(FunctionalState Cmd); +void SDIO_EnableSendSdioSuspend(FunctionalState Cmd); +void SDIO_EnableCommandCompletion(FunctionalState Cmd); +void SDIO_EnableCEATAInt(FunctionalState Cmd); +void SDIO_EnableSendCEATA(FunctionalState Cmd); +FlagStatus SDIO_GetFlag(uint32_t SDIO_FLAG); +void SDIO_ClrFlag(uint32_t SDIO_FLAG); +INTStatus SDIO_GetIntStatus(uint32_t SDIO_IT); +void SDIO_ClrIntPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_SDIO_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_spi.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_spi.h new file mode 100644 index 0000000000..401fbe65a4 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_spi.h @@ -0,0 +1,471 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_spi.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_SPI_H__ +#define __N32G45X_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @addtogroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SpiMode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t DataLen; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t CLKPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */ +} SPI_InitType; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint16_t I2sMode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2sMode */ + + uint16_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref Standard */ + + uint16_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +} I2S_InitType; + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2) || ((PERIPH) == SPI3)) + +#define IS_SPI_2OR3_PERIPH(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3)) + +/** @addtogroup SPI_data_direction + * @{ + */ + +#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000) +#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400) +#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000) +#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000) +#define IS_SPI_DIR_MODE(MODE) \ + (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \ + || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX)) +/** + * @} + */ + +/** @addtogroup SPI_mode + * @{ + */ + +#define SPI_MODE_MASTER ((uint16_t)0x0104) +#define SPI_MODE_SLAVE ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE)) +/** + * @} + */ + +/** @addtogroup SPI_data_size + * @{ + */ + +#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800) +#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS)) +/** + * @} + */ + +/** @addtogroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CLKPOL_LOW ((uint16_t)0x0000) +#define SPI_CLKPOL_HIGH ((uint16_t)0x0002) +#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH)) +/** + * @} + */ + +/** @addtogroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000) +#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001) +#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE)) +/** + * @} + */ + +/** @addtogroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_SOFT ((uint16_t)0x0200) +#define SPI_NSS_HARD ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD)) +/** + * @} + */ + +/** @addtogroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000) +#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008) +#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010) +#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018) +#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020) +#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028) +#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030) +#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038) +#define IS_SPI_BR_PRESCALER(PRESCALER) \ + (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \ + || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \ + || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \ + || ((PRESCALER) == SPI_BR_PRESCALER_256)) +/** + * @} + */ + +/** @addtogroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FB_MSB ((uint16_t)0x0000) +#define SPI_FB_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB)) +/** + * @} + */ + +/** @addtogroup I2sMode + * @{ + */ + +#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000) +#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100) +#define I2S_MODE_MASTER_TX ((uint16_t)0x0200) +#define I2S_MODE_MASTER_RX ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) \ + (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \ + || ((MODE) == I2S_MODE_MASTER_RX)) +/** + * @} + */ + +/** @addtogroup Standard + * @{ + */ + +#define I2S_STD_PHILLIPS ((uint16_t)0x0000) +#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010) +#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020) +#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030) +#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) \ + (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \ + || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME)) +/** + * @} + */ + +/** @addtogroup I2S_Data_Format + * @{ + */ + +#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000) +#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001) +#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003) +#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005) +#define IS_I2S_DATA_FMT(FORMAT) \ + (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \ + || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS)) +/** + * @} + */ + +/** @addtogroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLK_ENABLE ((uint16_t)0x0200) +#define I2S_MCLK_DISABLE ((uint16_t)0x0000) +#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE)) +/** + * @} + */ + +/** @addtogroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AUDIO_FREQ_192K ((uint32_t)192000) +#define I2S_AUDIO_FREQ_96K ((uint32_t)96000) +#define I2S_AUDIO_FREQ_48K ((uint32_t)48000) +#define I2S_AUDIO_FREQ_44K ((uint32_t)44100) +#define I2S_AUDIO_FREQ_32K ((uint32_t)32000) +#define I2S_AUDIO_FREQ_22K ((uint32_t)22050) +#define I2S_AUDIO_FREQ_16K ((uint32_t)16000) +#define I2S_AUDIO_FREQ_11K ((uint32_t)11025) +#define I2S_AUDIO_FREQ_8K ((uint32_t)8000) +#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) \ + ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT)) +/** + * @} + */ + +/** @addtogroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CLKPOL_LOW ((uint16_t)0x0000) +#define I2S_CLKPOL_HIGH ((uint16_t)0x0008) +#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMA_TX ((uint16_t)0x0002) +#define SPI_I2S_DMA_RX ((uint16_t)0x0001) +#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @addtogroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSS_HIGH ((uint16_t)0x0100) +#define SPI_NSS_LOW ((uint16_t)0xFEFF) +#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW)) +/** + * @} + */ + +/** @addtogroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_TX ((uint8_t)0x00) +#define SPI_CRC_RX ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX)) +/** + * @} + */ + +/** @addtogroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF) +#define SPI_BIDIRECTION_TX ((uint16_t)0x4000) +#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_INT_TE ((uint8_t)0x71) +#define SPI_I2S_INT_RNE ((uint8_t)0x60) +#define SPI_I2S_INT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR)) +#define SPI_I2S_INT_OVER ((uint8_t)0x56) +#define SPI_INT_MODERR ((uint8_t)0x55) +#define SPI_INT_CRCERR ((uint8_t)0x54) +#define I2S_INT_UNDER ((uint8_t)0x53) +#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR)) +#define IS_SPI_I2S_GET_INT(IT) \ + (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \ + || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER)) +/** + * @} + */ + +/** @addtogroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001) +#define SPI_I2S_TE_FLAG ((uint16_t)0x0002) +#define I2S_CHSIDE_FLAG ((uint16_t)0x0004) +#define I2S_UNDER_FLAG ((uint16_t)0x0008) +#define SPI_CRCERR_FLAG ((uint16_t)0x0010) +#define SPI_MODERR_FLAG ((uint16_t)0x0020) +#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040) +#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080) +#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG)) +#define IS_SPI_I2S_GET_FLAG(FLAG) \ + (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \ + || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \ + || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG)) +/** + * @} + */ + +/** @addtogroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_Module* SPIx); +void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct); +void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct); +void SPI_InitStruct(SPI_InitType* SPI_InitStruct); +void I2S_InitStruct(I2S_InitType* I2S_InitStruct); +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd); +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd); +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx); +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen); +void SPI_TransmitCrcNext(SPI_Module* SPIx); +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd); +uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPoly(SPI_Module* SPIx); +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection); +FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_SPI_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_tim.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_tim.h new file mode 100644 index 0000000000..a67db96658 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_tim.h @@ -0,0 +1,1104 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_tim.h + * @author Nations + * @version v1.0.2 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_TIM_H__ +#define __N32G45X_TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" +#include "stdbool.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @addtogroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t CntMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t ClkDiv; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter + reaches zero, an update event is generated and counting restarts + from the REPCNT value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ + + bool CapCh1FromCompEn; /*!< channel 1 select capture in from comp if 1, from IOM if 0 + Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh2FromCompEn; /*!< channel 2 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh3FromCompEn; /*!< channel 3 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4,Tim5 valid*/ + bool CapCh4FromCompEn; /*!< channel 4 select capture in from comp if 1, from IOM if 0 + Tim2,Tim3,Tim4 valid*/ + bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0 + Tim2,Tim3,Tim4 valid*/ + bool CapEtrSelFromTscEn; /*!< etr select from TSC if 1, from IOM if 0 + Tim2,Tim4 valid*/ +} TIM_TimeBaseInitType; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t OcMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t OcPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t OcNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} OCInitType; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + uint16_t Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref Channel */ + + uint16_t IcPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t IcSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t IcFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitType; + +/** + * @brief BKDT structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t OssiState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + bool IomBreakEn; /*!< EXTENDMODE valid, open iom as break in*/ + bool LockUpBreakEn; /*!< EXTENDMODE valid, open lockup(haldfault) as break in*/ + bool PvdBreakEn; /*!< EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/ +} TIM_BDTRInitType; + +/** @addtogroup TIM_Exported_constants + * @{ + */ + +#define IsTimAllModule(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/* LIST1: TIM 1 and 8 */ +#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8 */ +#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IsTimList3Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \ + || ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList4Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \ + || ((PERIPH) == TIM8)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList5Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \ + || ((PERIPH) == TIM8)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList6Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \ + || ((PERIPH) == TIM8)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */ +#define IsTimList7Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8 */ +#define IsTimList8Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \ + || ((PERIPH) == TIM8)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */ +#define IsTimList9Module(PERIPH) \ + (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \ + || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8)) + +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMODE_TIMING ((uint16_t)0x0000) +#define TIM_OCMODE_ACTIVE ((uint16_t)0x0010) +#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020) +#define TIM_OCMODE_TOGGLE ((uint16_t)0x0030) +#define TIM_OCMODE_PWM1 ((uint16_t)0x0060) +#define TIM_OCMODE_PWM2 ((uint16_t)0x0070) +#define IsTimOcMode(MODE) \ + (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \ + || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2)) +#define IsTimOc(MODE) \ + (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \ + || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) \ + || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE)) +/** + * @} + */ + +/** @addtogroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMODE_SINGLE ((uint16_t)0x0008) +#define TIM_OPMODE_REPET ((uint16_t)0x0000) +#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET)) +/** + * @} + */ + +/** @addtogroup Channel + * @{ + */ + +#define TIM_CH_1 ((uint16_t)0x0000) +#define TIM_CH_2 ((uint16_t)0x0004) +#define TIM_CH_3 ((uint16_t)0x0008) +#define TIM_CH_4 ((uint16_t)0x000C) +#define IsTimCh(CHANNEL) \ + (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4)) +#define IsTimPwmInCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2)) +#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3)) +/** + * @} + */ + +/** @addtogroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CLK_DIV1 ((uint16_t)0x0000) +#define TIM_CLK_DIV2 ((uint16_t)0x0100) +#define TIM_CLK_DIV4 ((uint16_t)0x0200) +#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4)) +/** + * @} + */ + +/** @addtogroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CNT_MODE_UP ((uint16_t)0x0000) +#define TIM_CNT_MODE_DOWN ((uint16_t)0x0010) +#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020) +#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040) +#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060) +#define IsTimCntMode(MODE) \ + (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1) \ + || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OC_POLARITY_HIGH ((uint16_t)0x0000) +#define TIM_OC_POLARITY_LOW ((uint16_t)0x0002) +#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCN_POLARITY_HIGH ((uint16_t)0x0000) +#define TIM_OCN_POLARITY_LOW ((uint16_t)0x0008) +#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000) +#define TIM_OUTPUT_STATE_ENABLE ((uint16_t)0x0001) +#define IsTimOutputState(STATE) (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000) +#define TIM_OUTPUT_NSTATE_ENABLE ((uint16_t)0x0004) +#define IsTimOutputNState(STATE) (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CAP_CMP_ENABLE ((uint16_t)0x0001) +#define TIM_CAP_CMP_DISABLE ((uint16_t)0x0000) +#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CAP_CMP_N_ENABLE ((uint16_t)0x0004) +#define TIM_CAP_CMP_N_DISABLE ((uint16_t)0x0000) +#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE)) +/** + * @} + */ + +/** @addtogroup Break_Input_enable_disable + * @{ + */ + +#define TIM_BREAK_IN_ENABLE ((uint16_t)0x1000) +#define TIM_BREAK_IN_DISABLE ((uint16_t)0x0000) +#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE)) +/** + * @} + */ + +/** @addtogroup Break_Polarity + * @{ + */ + +#define TIM_BREAK_POLARITY_LOW ((uint16_t)0x0000) +#define TIM_BREAK_POLARITY_HIGH ((uint16_t)0x2000) +#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH)) +/** + * @} + */ + +/** @addtogroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AUTO_OUTPUT_ENABLE ((uint16_t)0x4000) +#define TIM_AUTO_OUTPUT_DISABLE ((uint16_t)0x0000) +#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE)) +/** + * @} + */ + +/** @addtogroup Lock_level + * @{ + */ + +#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000) +#define TIM_LOCK_LEVEL_1 ((uint16_t)0x0100) +#define TIM_LOCK_LEVEL_2 ((uint16_t)0x0200) +#define TIM_LOCK_LEVEL_3 ((uint16_t)0x0300) +#define IsTimLockLevel(LEVEL) \ + (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2) \ + || ((LEVEL) == TIM_LOCK_LEVEL_3)) +/** + * @} + */ + +/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSI_STATE_ENABLE ((uint16_t)0x0400) +#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000) +#define IsTimOssiState(STATE) (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE)) +/** + * @} + */ + +/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSR_STATE_ENABLE ((uint16_t)0x0800) +#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000) +#define IsTimOssrState(STATE) (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OC_IDLE_STATE_SET ((uint16_t)0x0100) +#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000) +#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCN_IDLE_STATE_SET ((uint16_t)0x0200) +#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000) +#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_IC_POLARITY_RISING ((uint16_t)0x0000) +#define TIM_IC_POLARITY_FALLING ((uint16_t)0x0002) +#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A) +#define IsTimIcPalaritySingleEdge(POLARITY) \ + (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING)) +#define IsTimIcPolarityAnyEdge(POLARITY) \ + (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING) \ + || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_IC_SELECTION_DIRECTTI \ + ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_IC_SELECTION_INDIRECTTI \ + ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IsTimIcSelection(SELECTION) \ + (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI) \ + || ((SELECTION) == TIM_IC_SELECTION_TRC)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. \ + */ +#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IsTimIcPrescaler(PRESCALER) \ + (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4) \ + || ((PRESCALER) == TIM_IC_PSC_DIV8)) +/** + * @} + */ + +/** @addtogroup TIM_interrupt_sources + * @{ + */ + +#define TIM_INT_UPDATE ((uint16_t)0x0001) +#define TIM_INT_CC1 ((uint16_t)0x0002) +#define TIM_INT_CC2 ((uint16_t)0x0004) +#define TIM_INT_CC3 ((uint16_t)0x0008) +#define TIM_INT_CC4 ((uint16_t)0x0010) +#define TIM_INT_COM ((uint16_t)0x0020) +#define TIM_INT_TRIG ((uint16_t)0x0040) +#define TIM_INT_BREAK ((uint16_t)0x0080) +#define IsTimInt(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IsTimGetInt(IT) \ + (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3) \ + || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABASE_CTRL1 ((uint16_t)0x0000) +#define TIM_DMABASE_CTRL2 ((uint16_t)0x0001) +#define TIM_DMABASE_SMCTRL ((uint16_t)0x0002) +#define TIM_DMABASE_DMAINTEN ((uint16_t)0x0003) +#define TIM_DMABASE_STS ((uint16_t)0x0004) +#define TIM_DMABASE_EVTGEN ((uint16_t)0x0005) +#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006) +#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007) +#define TIM_DMABASE_CAPCMPEN ((uint16_t)0x0008) +#define TIM_DMABASE_CNT ((uint16_t)0x0009) +#define TIM_DMABASE_PSC ((uint16_t)0x000A) +#define TIM_DMABASE_AR ((uint16_t)0x000B) +#define TIM_DMABASE_REPCNT ((uint16_t)0x000C) +#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D) +#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E) +#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F) +#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010) +#define TIM_DMABASE_BKDT ((uint16_t)0x0011) +#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012) +#define TIM_DMABASE_CAPCMPMOD3 ((uint16_t)0x0013) +#define TIM_DMABASE_CAPCMPDAT5 ((uint16_t)0x0014) +#define TIM_DMABASE_CAPCMPDAT6 ((uint16_t)0x0015) + +#define IsTimDmaBase(BASE) \ + (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \ + || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \ + || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) || ((BASE) == TIM_DMABASE_CAPCMPMOD3) \ + || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \ + || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \ + || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \ + || ((BASE) == TIM_DMABASE_CAPCMPDAT5) || ((BASE) == TIM_DMABASE_CAPCMPDAT6) || ((BASE) == TIM_DMABASE_BKDT) \ + || ((BASE) == TIM_DMABASE_DMACTRL)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABURST_LENGTH_1TRANSFER ((uint16_t)0x0000) +#define TIM_DMABURST_LENGTH_2TRANSFERS ((uint16_t)0x0100) +#define TIM_DMABURST_LENGTH_3TRANSFERS ((uint16_t)0x0200) +#define TIM_DMABURST_LENGTH_4TRANSFERS ((uint16_t)0x0300) +#define TIM_DMABURST_LENGTH_5TRANSFERS ((uint16_t)0x0400) +#define TIM_DMABURST_LENGTH_6TRANSFERS ((uint16_t)0x0500) +#define TIM_DMABURST_LENGTH_7TRANSFERS ((uint16_t)0x0600) +#define TIM_DMABURST_LENGTH_8TRANSFERS ((uint16_t)0x0700) +#define TIM_DMABURST_LENGTH_9TRANSFERS ((uint16_t)0x0800) +#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900) +#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00) +#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00) +#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00) +#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00) +#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00) +#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00) +#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000) +#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100) +#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200) +#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300) +#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400) +#define IsTimDmaLength(LENGTH) \ + (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS) \ + || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS)) +/** + * @} + */ + +/** @addtogroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_UPDATE ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_TRIG ((uint16_t)0x4000) +#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_EXT_TRG_PSC_OFF ((uint16_t)0x0000) +#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000) +#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000) +#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000) +#define IsTimExtPreDiv(PRESCALER) \ + (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2) \ + || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8)) +/** + * @} + */ + +/** @addtogroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TRIG_SEL_IN_TR0 ((uint16_t)0x0000) +#define TIM_TRIG_SEL_IN_TR1 ((uint16_t)0x0010) +#define TIM_TRIG_SEL_IN_TR2 ((uint16_t)0x0020) +#define TIM_TRIG_SEL_IN_TR3 ((uint16_t)0x0030) +#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040) +#define TIM_TRIG_SEL_TI1FP1 ((uint16_t)0x0050) +#define TIM_TRIG_SEL_TI2FP2 ((uint16_t)0x0060) +#define TIM_TRIG_SEL_ETRF ((uint16_t)0x0070) +#define IsTimTrigSel(SELECTION) \ + (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \ + || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3) \ + || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1) \ + || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF)) +#define IsTimInterTrigSel(SELECTION) \ + (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \ + || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3)) +/** + * @} + */ + +/** @addtogroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_EXT_CLK_SRC_TI1 ((uint16_t)0x0050) +#define TIM_EXT_CLK_SRC_TI2 ((uint16_t)0x0060) +#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040) +#define IsTimExtClkSrc(SOURCE) \ + (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED)) +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_EXT_TRIG_POLARITY_INVERTED ((uint16_t)0x8000) +#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000) +#define IsTimExtTrigPolarity(POLARITY) \ + (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED)) +/** + * @} + */ + +/** @addtogroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSC_RELOAD_MODE_UPDATE ((uint16_t)0x0000) +#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001) +#define IsTimPscReloadMode(RELOAD) \ + (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE)) +/** + * @} + */ + +/** @addtogroup TIM_Forced_Action + * @{ + */ + +#define TIM_FORCED_ACTION_ACTIVE ((uint16_t)0x0050) +#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040) +#define IsTimForceActive(OPERATE) (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE)) +/** + * @} + */ + +/** @addtogroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_ENCODE_MODE_TI1 ((uint16_t)0x0001) +#define TIM_ENCODE_MODE_TI2 ((uint16_t)0x0002) +#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003) +#define IsTimEncodeMode(MODE) \ + (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12)) +/** + * @} + */ + +/** @addtogroup TIM_Event_Source + * @{ + */ + +#define TIM_EVT_SRC_UPDATE ((uint16_t)0x0001) +#define TIM_EVT_SRC_CC1 ((uint16_t)0x0002) +#define TIM_EVT_SRC_CC2 ((uint16_t)0x0004) +#define TIM_EVT_SRC_CC3 ((uint16_t)0x0008) +#define TIM_EVT_SRC_CC4 ((uint16_t)0x0010) +#define TIM_EVT_SRC_COM ((uint16_t)0x0020) +#define TIM_EVT_SRC_TRIG ((uint16_t)0x0040) +#define TIM_EVT_SRC_BREAK ((uint16_t)0x0080) +#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @addtogroup TIM_Update_Source + * @{ + */ + +#define TIM_UPDATE_SRC_GLOBAL \ + ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OC_PRE_LOAD_ENABLE ((uint16_t)0x0008) +#define TIM_OC_PRE_LOAD_DISABLE ((uint16_t)0x0000) +#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OC_FAST_ENABLE ((uint16_t)0x0004) +#define TIM_OC_FAST_DISABLE ((uint16_t)0x0000) +#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE)) + +/** + * @} + */ + +/** @addtogroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OC_CLR_ENABLE ((uint16_t)0x0080) +#define TIM_OC_CLR_DISABLE ((uint16_t)0x0000) +#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGO_SRC_RESET ((uint16_t)0x0000) +#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010) +#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020) +#define TIM_TRGO_SRC_OC1 ((uint16_t)0x0030) +#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040) +#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050) +#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060) +#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070) +#define IsTimTrgoSrc(SOURCE) \ + (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE) \ + || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF) \ + || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF)) +/** + * @} + */ + +/** @addtogroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004) +#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005) +#define TIM_SLAVE_MODE_TRIG ((uint16_t)0x0006) +#define TIM_SLAVE_MODE_EXT1 ((uint16_t)0x0007) +#define IsTimSlaveMode(MODE) \ + (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG) \ + || ((MODE) == TIM_SLAVE_MODE_EXT1)) +/** + * @} + */ + +/** @addtogroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080) +#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000) +#define IsTimMasterSlaveMode(STATE) \ + (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE)) +/** + * @} + */ + +/** @addtogroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_UPDATE ((uint32_t)0x0001) +#define TIM_FLAG_CC1 ((uint32_t)0x0002) +#define TIM_FLAG_CC2 ((uint32_t)0x0004) +#define TIM_FLAG_CC3 ((uint32_t)0x0008) +#define TIM_FLAG_CC4 ((uint32_t)0x0010) +#define TIM_FLAG_COM ((uint32_t)0x0020) +#define TIM_FLAG_TRIG ((uint32_t)0x0040) +#define TIM_FLAG_BREAK ((uint32_t)0x0080) +#define TIM_FLAG_CC1OF ((uint32_t)0x0200) +#define TIM_FLAG_CC2OF ((uint32_t)0x0400) +#define TIM_FLAG_CC3OF ((uint32_t)0x0800) +#define TIM_FLAG_CC4OF ((uint32_t)0x1000) +#define TIM_FLAG_CC5 ((uint32_t)0x010000) +#define TIM_FLAG_CC6 ((uint32_t)0x020000) + +#define IsTimGetFlag(FLAG) \ + (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) \ + || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG) \ + || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) \ + || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5) \ + || ((FLAG) == TIM_FLAG_CC6)) + +#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @addtogroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @addtogroup TIM_External_Trigger_Filter + * @{ + */ + +#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +#define TIM_CC1EN ((uint32_t)1<<0) +#define TIM_CC1NEN ((uint32_t)1<<2) +#define TIM_CC2EN ((uint32_t)1<<4) +#define TIM_CC2NEN ((uint32_t)1<<6) +#define TIM_CC3EN ((uint32_t)1<<8) +#define TIM_CC3NEN ((uint32_t)1<<10) +#define TIM_CC4EN ((uint32_t)1<<12) +#define TIM_CC5EN ((uint32_t)1<<16) +#define TIM_CC6EN ((uint32_t)1<<20) + +#define IsAdvancedTimCCENFlag(FLAG) \ + (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \ + || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \ + || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) ) +#define IsGeneralTimCCENFlag(FLAG) \ + (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \ + || ((FLAG) == TIM_CC3EN) \ + || ((FLAG) == TIM_CC4EN) ) + +/** @addtogroup TIM_Legacy + * @{ + */ + +#define TIM_DMA_BURST_LEN_1BYTE TIM_DMABURST_LENGTH_1TRANSFER +#define TIM_DMA_BURST_LEN_2BYTES TIM_DMABURST_LENGTH_2TRANSFERS +#define TIM_DMA_BURST_LEN_3BYTES TIM_DMABURST_LENGTH_3TRANSFERS +#define TIM_DMA_BURST_LEN_4BYTES TIM_DMABURST_LENGTH_4TRANSFERS +#define TIM_DMA_BURST_LEN_5BYTES TIM_DMABURST_LENGTH_5TRANSFERS +#define TIM_DMA_BURST_LEN_6BYTES TIM_DMABURST_LENGTH_6TRANSFERS +#define TIM_DMA_BURST_LEN_7BYTES TIM_DMABURST_LENGTH_7TRANSFERS +#define TIM_DMA_BURST_LEN_8BYTES TIM_DMABURST_LENGTH_8TRANSFERS +#define TIM_DMA_BURST_LEN_9BYTES TIM_DMABURST_LENGTH_9TRANSFERS +#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS +#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS +#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS +#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS +#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS +#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS +#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS +#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS +#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_Module* TIMx); +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct); +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct); +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd); +void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource); +void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd); +void TIM_ConfigInternalClk(TIM_Module* TIMx); +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, + uint16_t TIM_TIxExternalCLKSource, + uint16_t IcPolarity, + uint16_t ICFilter); +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigExtTrig(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode); +void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, + uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, + uint16_t TIM_IC2Polarity); +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload); +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast); +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear); +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity); +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity); +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx); +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN); +void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode); +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter); +void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload); +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1); +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2); +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3); +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4); +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5); +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6); +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCap1(TIM_Module* TIMx); +uint16_t TIM_GetCap2(TIM_Module* TIMx); +uint16_t TIM_GetCap3(TIM_Module* TIMx); +uint16_t TIM_GetCap4(TIM_Module* TIMx); +uint16_t TIM_GetCap5(TIM_Module* TIMx); +uint16_t TIM_GetCap6(TIM_Module* TIMx); +uint16_t TIM_GetCnt(TIM_Module* TIMx); +uint16_t TIM_GetPrescaler(TIM_Module* TIMx); +uint16_t TIM_GetAutoReload(TIM_Module* TIMx); +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN); +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG); +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG); +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT); +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_TIM_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_tsc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_tsc.h new file mode 100644 index 0000000000..8ea7ca7799 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_tsc.h @@ -0,0 +1,509 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_tsc.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_TSC_H__ +#define __N32G45X_TSC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TSC + * @{ + */ + +/** + * @brief TSC error code + */ + typedef enum { + TSC_ERROR_OK = 0x00U, /*!< No error */ + TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */ + TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */ + TSC_ERROR_HW_MODE = 0x02U, /*!< Exit hw mode timeout */ + + }TSC_ErrorTypeDef; + /** + * @ + */ + +/** + * @brief TSC clock source + */ +#define TSC_CLK_SRC_LSI (0x00000000) /*!< LSI*/ +#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE) /*!< LSE */ +#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS) /*!< LSE bypass */ +/** + * @ + */ + + +/** + * @defgroup Detect_Period + */ +#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */ +#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */ +#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */ +#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */ +#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */ +#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */ +#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */ +#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */ +#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */ +#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */ +#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */ +#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */ +#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */ +/** + * @ + */ + +/** + * @defgroup Detect_Filter + */ +#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */ +#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */ +#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */ +#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */ +/** + * @ + */ + +/** + * @defgroup HW_Detect_Mode + */ +#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */ +#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_SHIFT) /*!< 0x00000040U Hardware detect mode enable */ +/** + * @ + */ + +/** + * @defgroup Detect_Type + */ +#define TSC_DET_TYPE_MASK (TSC_CTRL_LESS_DET_SEL_MASK|TSC_CTRL_GREAT_DET_SEL_MASK) +#define TSC_DET_TYPE_SHIFT (TSC_CTRL_LESS_DET_SEL_SHIFT) + +#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */ +#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000100U Less detect enable */ +#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000200U Great detect enable */ +#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000300U Both great and less detct enable */ +/** + * @ + */ + +/** + * @defgroup TSC_Interrupt + */ +#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */ +#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */ +/** + * @ + */ + +/** + * @defgroup TSC_Out + */ +#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */ +#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_SHIFT) /*!< TSC output to TIM4 ETR */ +#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_SHIFT) /*!< TSC output to TIM2 ETR and TIM2 CH1*/ +/** + * @ + */ + +/** + * @defgroup TSC_Flag + */ +#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_SHIFT) /*!< Flag of hardware detect mode */ + +#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_SHIFT) /*!< Flag of great detect type */ +#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_SHIFT) /*!< Flag of less detect type */ +#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */ +/** + * @ + */ + +/** + * @defgroup TSC_SW_Detect + */ +#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */ +#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_SHIFT) /*!< Enable software detect mode */ +/** + * @ + */ + +/** + * @defgroup TSC_PadOption + */ +#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */ +#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_SHIFT) /*!< Use external resistor */ +/** + * @ + */ + +/** + * @defgroup TSC_PadSpeed + */ +#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */ +#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */ +#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */ +#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */ +/** + * @ + */ + +/** + * @defgroup TSC_Constant + */ +#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SEL_MASK) +#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/ +#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/ +#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/ +#define TSC_TIMEOUT (SystemCoreClock>>4) /*TSC normal timeout */ +/** + * @ + */ + +/** + * @defgroup TSC_DetectMode + */ +#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/ +#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/ +/** + * @ + */ + +/* TSC Exported macros -----------------------------------------------------------*/ +/** @defgroup TSC_Exported_Macros + * @{ + */ + +/** @brief Enable the TSC HW detect mode + * @param None + * @retval None + */ +#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) + +/** @brief Disable the TSC HW detect mode + * @param None + * @retval None + */ +#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) + +/** @brief Config TSC detect period for HW detect mode + * @param __PERIOD__ specifies the TSC detect period during HW detect mode + * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK + * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK + * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK + * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK + * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK + * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK + * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK + * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK + * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK + * @retval None + */ +#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_MASK,__PERIOD__) + +/** @brief Config TSC detect filter for HW detect mode + * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode + * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse + * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse + * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse + * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse + * @retval None + */ +#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_MASK,__FILTER__) + +/** @brief Config TSC detect type for HW detect mode,less great or both + * @param __TYPE__ specifies the detect type of a sample during HW detect mode + * @arg TSC_DET_TYPE_NONE: Detect disable + * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time + * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time + * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta) + and also be less than (basee+delta) during a sample time + * @retval None + */ +#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \ + (TSC_CTRL_LESS_DET_SEL_MASK|TSC_CTRL_GREAT_DET_SEL_MASK), \ + __TYPE__) + +/** @brief Enable TSC interrupt + * @param None + * @retval None + */ +#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) + +/** @brief Disable TSC interrupt + * @param None + * @retval None + */ +#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) + +/** @brief Config the TSC output + * @param __OUT__ specifies where the TSC output should go + * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin + * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR + * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR + * @retval None + */ +#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \ + (TSC_CTRL_TM4_ETR_MASK|TSC_CTRL_TM2_ETR_CH1_MASK),\ + __OUT__) + +/** @brief Config the TSC channel + * @param __CHN__ specifies the pin of channels used for detect + * This parameter:bit[0:23] used,bit[24:31] must be 0 + * bitx: TSC channel x + * @retval None + */ +#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__) + +/** @brief Enable the TSC SW detect mode + * @param None + * @retval None + */ +#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) + +/** @brief Disable the TSC SW detect mode + * @param None + * @retval None + */ +#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) + +/** @brief Config the detect channel number during SW detect mode + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval None + */ +#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_MASK,__NUM__) + +/** @brief Config the pad charge type + * @param __OPT__ specifies which resistor is used for charge + * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used + * @arg TSC_PAD_EXTERNAL_RES: External resistor is used + * @retval None + */ +#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_MASK,__OPT__) + +/** @brief Config TSC speed + * @param __SPEED__ specifies the TSC speed range + * @arg TSC_PAD_SPEED_0: Low speed + * @arg TSC_PAD_SPEED_1: Middle speed + * @arg TSC_PAD_SPEED_2: Middle speed + * @arg TSC_PAD_SPEED_3: High speed + * @retval None + */ +#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_MASK,__SPEED__) + + +/** @brief Check if the HW detect mode is enable + * @param None + * @retval Current state of HW detect mode + */ +#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW)) + +/** @brief Check the detect type during HW detect mode + * @param __FLAG__ specifies the flag of detect type + * @arg TSC_FLAG_LESS_DET: Flag of less detect type + * @arg TSC_FLAG_GREAT_DET: Flag of great detect type + * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type + * @retval Current state of flag + */ +#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__)) + +/** @brief Get the number of channel which is detected now + * @param None + * @retval Current channel number + */ +#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_MASK) >> TSC_STS_CHN_NUM_SHIFT ) + +/** @brief Get the count value of pulse + * @param None + * @retval Pulse count of current channel + */ +#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_MASK ) >> TSC_STS_CNT_VAL_SHIFT ) + +/** @brief Get the base value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval base value of the channel + */ +#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHD_BASE_MASK ) >> TSC_THRHD_BASE_SHIFT) + +/** @brief Get the delta value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval delta value of the channel + */ +#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHD_DELTA_MASK ) >> TSC_THRHD_DELTA_SHIFT ) + +/** @brief Get the internal resist value of one channel + * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN + * @retval resist value of the channel + */ +#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESR_CHN_RESIST_MASK) + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TSC_Private_Macros + * @{ + */ +#define IS_TSC_DET_PERIOD(_PERIOD_) \ + (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \ + ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \ + ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \ + ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \ + ||((_PERIOD_)==TSC_DET_PERIOD_104) ) + +#define IS_TSC_FILTER(_FILTER_) \ + ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\ + ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) ) + +#define IS_TSC_DET_MODE(_MODE_) \ + ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) ) + +#define IS_TSC_DET_TYPE(_TYPE_) \ + ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \ + ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) ) + +#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE)) + +#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR)) + +#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SEL_MASK))) + +#define IS_TSC_CHN_NUMBER(_NUM_) ((uint32_t)(_NUM_)BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref Mode */ + + uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitType; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref Clock */ + + uint16_t Polarity; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitType; + +/** + * @} + */ + +/** @addtogroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) \ + (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) \ + || ((PERIPH) == UART5) || ((PERIPH) == UART6) || ((PERIPH) == UART7)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) \ + (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4)) +/** @addtogroup USART_Word_Length + * @{ + */ + +#define USART_WL_8B ((uint16_t)0x0000) +#define USART_WL_9B ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B)) +/** + * @} + */ + +/** @addtogroup USART_Stop_Bits + * @{ + */ + +#define USART_STPB_1 ((uint16_t)0x0000) +#define USART_STPB_0_5 ((uint16_t)0x1000) +#define USART_STPB_2 ((uint16_t)0x2000) +#define USART_STPB_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) \ + (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \ + || ((STOPBITS) == USART_STPB_1_5)) +/** + * @} + */ + +/** @addtogroup Parity + * @{ + */ + +#define USART_PE_NO ((uint16_t)0x0000) +#define USART_PE_EVEN ((uint16_t)0x0400) +#define USART_PE_ODD ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD)) +/** + * @} + */ + +/** @addtogroup Mode + * @{ + */ + +#define USART_MODE_RX ((uint16_t)0x0004) +#define USART_MODE_TX ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @addtogroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HFCTRL_NONE ((uint16_t)0x0000) +#define USART_HFCTRL_RTS ((uint16_t)0x0100) +#define USART_HFCTRL_CTS ((uint16_t)0x0200) +#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \ + || ((CONTROL) == USART_HFCTRL_RTS_CTS)) +/** + * @} + */ + +/** @addtogroup Clock + * @{ + */ +#define USART_CLK_DISABLE ((uint16_t)0x0000) +#define USART_CLK_ENABLE ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE)) +/** + * @} + */ + +/** @addtogroup USART_Clock_Polarity + * @{ + */ + +#define USART_CLKPOL_LOW ((uint16_t)0x0000) +#define USART_CLKPOL_HIGH ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH)) + +/** + * @} + */ + +/** @addtogroup USART_Clock_Phase + * @{ + */ + +#define USART_CLKPHA_1EDGE ((uint16_t)0x0000) +#define USART_CLKPHA_2EDGE ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE)) + +/** + * @} + */ + +/** @addtogroup USART_Last_Bit + * @{ + */ + +#define USART_CLKLB_DISABLE ((uint16_t)0x0000) +#define USART_CLKLB_ENABLE ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE)) +/** + * @} + */ + +/** @addtogroup USART_Interrupt_definition + * @{ + */ + +#define USART_INT_PEF ((uint16_t)0x0028) +#define USART_INT_TXDE ((uint16_t)0x0727) +#define USART_INT_TXC ((uint16_t)0x0626) +#define USART_INT_RXDNE ((uint16_t)0x0525) +#define USART_INT_IDLEF ((uint16_t)0x0424) +#define USART_INT_LINBD ((uint16_t)0x0846) +#define USART_INT_CTSF ((uint16_t)0x096A) +#define USART_INT_ERRF ((uint16_t)0x0060) +#define USART_INT_OREF ((uint16_t)0x0360) +#define USART_INT_NEF ((uint16_t)0x0260) +#define USART_INT_FEF ((uint16_t)0x0160) +#define IS_USART_CFG_INT(IT) \ + (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \ + || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \ + || ((IT) == USART_INT_ERRF)) +#define IS_USART_GET_INT(IT) \ + (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \ + || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \ + || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF)) +#define IS_USART_CLR_INT(IT) \ + (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF)) +/** + * @} + */ + +/** @addtogroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAREQ_TX ((uint16_t)0x0080) +#define USART_DMAREQ_RX ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @addtogroup USART_WakeUp_methods + * @{ + */ + +#define USART_WUM_IDLELINE ((uint16_t)0x0000) +#define USART_WUM_ADDRMASK ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK)) +/** + * @} + */ + +/** @addtogroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBDL_10B ((uint16_t)0x0000) +#define USART_LINBDL_11B ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B)) +/** + * @} + */ + +/** @addtogroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004) +#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL)) +/** + * @} + */ + +/** @addtogroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTSF ((uint16_t)0x0200) +#define USART_FLAG_LINBD ((uint16_t)0x0100) +#define USART_FLAG_TXDE ((uint16_t)0x0080) +#define USART_FLAG_TXC ((uint16_t)0x0040) +#define USART_FLAG_RXDNE ((uint16_t)0x0020) +#define USART_FLAG_IDLEF ((uint16_t)0x0010) +#define USART_FLAG_OREF ((uint16_t)0x0008) +#define USART_FLAG_NEF ((uint16_t)0x0004) +#define USART_FLAG_FEF ((uint16_t)0x0002) +#define USART_FLAG_PEF ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) \ + (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \ + || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \ + || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \ + || ((FLAG) == USART_FLAG_FEF)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \ + ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTSF)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_Module* USARTx); +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct); +void USART_StructInit(USART_InitType* USART_InitStruct); +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct); +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd); +void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd); +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr); +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode); +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd); +void USART_SendData(USART_Module* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_Module* USARTx); +void USART_SendBreak(USART_Module* USARTx); +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler); +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd); +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd); +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode); +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd); +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG); +void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG); +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT); +void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X_USART_H__ */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_wwdg.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_wwdg.h new file mode 100644 index 0000000000..6f7d32b91d --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_wwdg.h @@ -0,0 +1,122 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_wwdg.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_WWDG_H__ +#define __N32G45X_WWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @addtogroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Constants + * @{ + */ + +/** @addtogroup WWDG_Prescaler + * @{ + */ + +#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000) +#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080) +#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100) +#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER_DIV(PRESCALER) \ + (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \ + || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8)) +#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler); +void WWDG_SetWValue(uint8_t WindowValue); +void WWDG_EnableInt(void); +void WWDG_SetCnt(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetEWINTF(void); +void WWDG_ClrEWINTF(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G45X__WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_xfmc.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_xfmc.h new file mode 100644 index 0000000000..01948cde51 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_xfmc.h @@ -0,0 +1,820 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_xfmc.h + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32G45X_XFMC_H__ +#define __N32G45X_XFMC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g45x.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup XFMC + * @{ + */ + +/** @addtogroup XFMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ +typedef struct +{ + uint32_t AddrSetTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t AddrHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t DataSetTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 1 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t BusRecoveryCycle; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t ClkDiv; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t AccMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref XFMC_Access_Mode */ +} XFMC_NorSramTimingInitType; + +/** + * @brief XFMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + XFMC_Bank1_Block *Block; /*!< Specifies the NOR/SRAM memory bank block that will be used. + This parameter can be a XFMC_BANK1_BLOCK1 or XFMC_BANK1_BLOCK2 */ + + uint32_t DataAddrMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref XFMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref XFMC_Memory_Type */ + + uint32_t MemDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref XFMC_Data_Width */ + + uint32_t BurstAccMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref XFMC_Burst_Access_Mode */ + + uint32_t AsynchroWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref AsynchroWait */ + + uint32_t WaitSigPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref XFMC_Wait_Signal_Polarity */ + + uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref XFMC_Wrap_Mode */ + + uint32_t WaitSigConfig; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref XFMC_Wait_Timing */ + + uint32_t WriteEnable; /*!< Enables or disables the write operation in the selected bank by the XFMC. + This parameter can be a value of @ref XFMC_Write_Operation */ + + uint32_t WaitSigEnable; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref XFMC_Wait_Signal */ + + uint32_t ExtModeEnable; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref XFMC_Extended_Mode */ + + uint32_t WriteBurstEnable; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref XFMC_Write_Burst */ + + XFMC_NorSramTimingInitType* RWTimingStruct; /*!< Timing Parameters for write and read access + if the ExtendedMode is not used*/ + + XFMC_NorSramTimingInitType* WTimingStruct; /*!< Timing Parameters for write access if the + ExtendedMode is used*/ +} XFMC_NorSramInitTpye; + +/** + * @brief Timing parameters For XFMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t SetTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t WaitSetTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t HoldSetTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t HiZSetTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +} XFMC_NandTimingInitType; + +/** + * @brief XFMC NAND Init structure definition + */ + +typedef struct +{ + XFMC_Bank23_Module *Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be XFMC_BANK2 or XFMC_BANK3 */ + + uint32_t WaitFeatureEnable; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref XFMC_Wait_feature */ + + uint32_t MemDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref XFMC_Data_Width */ + + uint32_t EccEnable; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref XFMC_Ecc */ + + uint32_t EccPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref XFMC_ECC_Page_Size */ + + uint32_t TCLRSetTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t TARSetTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + XFMC_NandTimingInitType* CommSpaceTimingStruct; /*!< XFMC Common Space Timing */ + + XFMC_NandTimingInitType* AttrSpaceTimingStruct; /*!< XFMC Attribute Space Timing */ +} XFMC_NandInitType; + +/** + * @brief XFMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t WaitFeatureEnable; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref XFMC_Wait_feature */ + + uint32_t TCLRSetTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t TARSetTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + XFMC_NandTimingInitType* CommSpaceTimingStruct; /*!< XFMC Common Space Timing */ + + XFMC_NandTimingInitType* AttrSpaceTimingStruct; /*!< XFMC Attribute Space Timing */ + + XFMC_NandTimingInitType* XFMC_IOSpaceTimingStruct; /*!< XFMC IO Space Timing */ +} XFMC_PCCARDInitType; + +/** + * @} + */ + +/** @addtogroup XFMC_Exported_Constants + * @{ + */ + +/** @addtogroup XFMC_NORSRAM_Bank1_Reg_ResetValue + * @{ + */ +#define XFMC_NOR_SRAM_CR1_RESET ((uint32_t)0x000030DB) +#define XFMC_NOR_SRAM_CR2_RESET ((uint32_t)0x000030D2) +#define XFMC_NOR_SRAM_TR_RESET ((uint32_t)0x0FFFFFFF) +#define XFMC_NOR_SRAM_WTR_RESET ((uint32_t)0x0FFFFFFF) + +/** + * @} + */ + +/** @addtogroup XFMC_NAND_Bank23_Reg_ResetValue + * @{ + */ +#define XFMC_NAND_CTRL_RESET ((uint32_t)0x00000018) +#define XFMC_NAND_STS_RESET ((uint32_t)0x00000040) +#define XFMC_NAND_CMEMTM_RESET ((uint32_t)0xFCFCFCFC) +#define XFMC_NAND_ATTMEMTM_RESET ((uint32_t)0xFCFCFCFC) + +/** + * @} + */ + +#define IS_XFMC_NOR_SRAM_BLOCK(BLOCK) (((BLOCK) == XFMC_BANK1_BLOCK1) || ((BLOCK) == XFMC_BANK1_BLOCK2)) +#define IS_XFMC_NAND_BANK(BANK) (((BANK) == XFMC_BANK2) || ((BANK) == XFMC_BANK3)) + + +/** @addtogroup NOR_SRAM_Controller + * @{ + */ + +/** @addtogroup XFMC_Data_Address_Bus_Multiplexing + * @{ + */ +#define XFMC_NOR_SRAM_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_ENABLE (XFMC_BANK1_CR_MBEN) +/** + * @} + */ + +/** @addtogroup XFMC_Data_Address_Bus_Multiplexing + * @{ + */ +#define XFMC_NOR_SRAM_MUX_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_MUX_ENABLE (XFMC_BANK1_CR_MUXEN) +#define IS_XFMC_NOR_SRAM_MUX(MUX) (((MUX) == XFMC_NOR_SRAM_MUX_DISABLE) || ((MUX) == XFMC_NOR_SRAM_MUX_ENABLE)) +/** + * @} + */ + +/** @addtogroup XFMC_Memory_Type + * @{ + */ +#define XFMC_MEM_TYPE_SRAM ((uint32_t)0x00000000) +#define XFMC_MEM_TYPE_PSRAM (XFMC_BANK1_CR_MTYPE_0) +#define XFMC_MEM_TYPE_NOR (XFMC_BANK1_CR_MTYPE_1) +#define IS_XFMC_NOR_SRAM_MEMORY(MEMORY) \ + (((MEMORY) == XFMC_MEM_TYPE_SRAM) || ((MEMORY) == XFMC_MEM_TYPE_PSRAM) || ((MEMORY) == XFMC_MEM_TYPE_NOR)) +/** + * @} + */ + +/** @addtogroup XFMC_Data_Width + * @{ + */ +#define XFMC_NOR_SRAM_DATA_WIDTH_8B ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_DATA_WIDTH_16B (XFMC_BANK1_CR_MDBW_0) +#define IS_XFMC_NOR_SRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == XFMC_NOR_SRAM_DATA_WIDTH_8B) || ((WIDTH) == XFMC_NOR_SRAM_DATA_WIDTH_16B)) +/** + * @} + */ + +/** @addtogroup XFMC_Flash_Access_Enable + * @{ + */ +#define XFMC_NOR_SRAM_ACC_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_ACC_ENABLE (XFMC_BANK1_CR_ACCEN) +/** + * @} + */ + +/** @addtogroup XFMC_Burst_Access_Mode + * @{ + */ +#define XFMC_NOR_SRAM_BURST_MODE_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_BURST_MODE_ENABLE (XFMC_BANK1_CR_BURSTEN) +#define IS_XFMC_NOR_SRAM_BURSTMODE(STATE) (((STATE) == XFMC_NOR_SRAM_BURST_MODE_DISABLE) || ((STATE) == XFMC_NOR_SRAM_BURST_MODE_ENABLE)) +/** + * @} + */ + +/** @addtogroup XFMC_Wait_Signal_Polarity + * @{ + */ +#define XFMC_NOR_SRAM_WAIT_SIGNAL_LOW ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_WAIT_SIGNAL_HIGH (XFMC_BANK1_CR_WAITDIR) +#define IS_XFMC_NOR_SRAM_WAIT_POLARITY(POLARITY) \ + (((POLARITY) == XFMC_NOR_SRAM_WAIT_SIGNAL_LOW) || ((POLARITY) == XFMC_NOR_SRAM_WAIT_SIGNAL_HIGH)) +/** + * @} + */ + +/** @addtogroup XFMC_Wrap_Mode + * @{ + */ +#define XFMC_NOR_SRAM_WRAP_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_WRAP_ENABLE (XFMC_BANK1_CR_WRAPEN) +#define IS_XFMC_NOR_SRAM_WRAP_MODE(MODE) (((MODE) == XFMC_NOR_SRAM_WRAP_DISABLE) || ((MODE) == XFMC_NOR_SRAM_WRAP_ENABLE)) +/** + * @} + */ + +/** @addtogroup XFMC_Wait_Timing + * @{ + */ +#define XFMC_NOR_SRAM_NWAIT_BEFORE_STATE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_NWAIT_DURING_STATE (XFMC_BANK1_CR_WCFG) +#define IS_XFMC_NOR_SRAM_WAIT_SIGNAL_ACTIVE(ACTIVE) \ + (((ACTIVE) == XFMC_NOR_SRAM_NWAIT_BEFORE_STATE) || ((ACTIVE) == XFMC_NOR_SRAM_NWAIT_DURING_STATE)) +/** + * @} + */ + +/** @addtogroup XFMC_Write_Operation + * @{ + */ +#define XFMC_NOR_SRAM_WRITE_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_WRITE_ENABLE (XFMC_BANK1_CR_WREN) +#define IS_XFMC_NOR_SRAM_WRITE_OPERATION(OPERATION) (((OPERATION) == XFMC_NOR_SRAM_WRITE_DISABLE) || ((OPERATION) == XFMC_NOR_SRAM_WRITE_ENABLE)) +/** + * @} + */ + +/** @addtogroup XFMC_Wait_Signal + * @{ + */ +#define XFMC_NOR_SRAM_NWAIT_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_NWAIT_ENABLE (XFMC_BANK1_CR_WAITEN) +#define IS_XFMC_NOR_SRAM_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == XFMC_NOR_SRAM_NWAIT_DISABLE) || ((SIGNAL) == XFMC_NOR_SRAM_NWAIT_ENABLE)) +/** + * @} + */ + +/** @addtogroup XFMC_Extended_Mode + * @{ + */ +#define XFMC_NOR_SRAM_EXTENDED_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_EXTENDED_ENABLE (XFMC_BANK1_CR_EXTEN) +#define IS_XFMC_NOR_SRAM_EXTENDED_MODE(MODE) (((MODE) == XFMC_NOR_SRAM_EXTENDED_DISABLE) || ((MODE) == XFMC_NOR_SRAM_EXTENDED_ENABLE)) +/** + * @} + */ + +/** @addtogroup AsynchroWait + * @{ + */ +#define XFMC_NOR_SRAM_ASYNC_NWAIT_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_ASYNC_NWAIT_ENABLE (XFMC_BANK1_CR_WAITASYNC) +#define IS_XFMC_NOR_SRAM_ASYNWAIT(STATE) (((STATE) == XFMC_NOR_SRAM_ASYNC_NWAIT_DISABLE) || ((STATE) == XFMC_NOR_SRAM_ASYNC_NWAIT_ENABLE)) +/** + * @} + */ + + +/** @addtogroup XFMC_Write_Burst + * @{ + */ +#define XFMC_NOR_SRAM_BURST_WRITE_DISABLE ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_BURST_WRITE_ENABLE (XFMC_BANK1_CR_BURSTWREN) +#define IS_XFMC_NOR_SRAM_WRITE_BURST(BURST) (((BURST) == XFMC_NOR_SRAM_BURST_WRITE_DISABLE) || ((BURST) == XFMC_NOR_SRAM_BURST_WRITE_ENABLE)) +/** + * @} + */ + +/** + * @} End of NOR_SRAM_Controller + */ + + +/** @addtogroup NOR_SRAM_Time_Control + * @{ + */ + +/** @addtogroup XFMC_Address_Setup_Time + * @{ + */ +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_1HCLK (0x0UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_2HCLK (0x1UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_3HCLK (0x2UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_4HCLK (0x3UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_5HCLK (0x4UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_6HCLK (0x5UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_7HCLK (0x6UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_8HCLK (0x7UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_9HCLK (0x8UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_10HCLK (0x9UL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_11HCLK (0xAUL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_12HCLK (0xBUL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_13HCLK (0xCUL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_14HCLK (0xDUL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_15HCLK (0xEUL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_SETUP_TIME_16HCLK (0xFUL << XFMC_BANK1_TR_ADDBLD_SHIFT) +#define IS_XFMC_NOR_SRAM_ADDR_SETUP_TIME(TIME) (0==((TIME) & (~XFMC_BANK1_TR_ADDBLD_MASK))) +/** + * @} + */ + +/** @addtogroup XFMC_Address_Hold_Time + * @{ + */ +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_1HCLK (0x0UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_2HCLK (0x1UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_3HCLK (0x2UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_4HCLK (0x3UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_5HCLK (0x4UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_6HCLK (0x5UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_7HCLK (0x6UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_8HCLK (0x7UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_9HCLK (0x8UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_10HCLK (0x9UL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_11HCLK (0xAUL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_12HCLK (0xBUL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_13HCLK (0xCUL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_14HCLK (0xDUL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_15HCLK (0xEUL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define XFMC_NOR_SRAM_ADDR_HOLD_TIME_16HCLK (0xFUL << XFMC_BANK1_TR_ADDHLD_SHIFT) +#define IS_XFMC_NOR_SRAM_ADDR_HOLD_TIME(TIME) (0==((TIME) & (~XFMC_BANK1_TR_ADDHLD_MASK))) +/** + * @} + */ + +/** @addtogroup XFMC_Data_Setup_Time + * @{ + */ +#define XFMC_NOR_SRAM_DATA_SETUP_TIME_MIN (0x01UL << XFMC_BANK1_TR_DATABLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_SETUP_TIME_MAX (0xFFUL << XFMC_BANK1_TR_DATABLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_SETUP_TIME(x) ((x) << XFMC_BANK1_TR_DATABLD_SHIFT) +#define IS_XFMC_NOR_SRAM_DATASETUP_TIME(TIME) ( ((TIME) >= XFMC_NOR_SRAM_DATA_SETUP_TIME_MIN) \ + && ((TIME) <= XFMC_NOR_SRAM_DATA_SETUP_TIME_MAX) ) +/** + * @} + */ + +/** @addtogroup XFMC_Bus_Recovery_Time + * @{ + */ +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_1HCLK (0x0UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_2HCLK (0x1UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_3HCLK (0x2UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_4HCLK (0x3UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_5HCLK (0x4UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_6HCLK (0x5UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_7HCLK (0x6UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_8HCLK (0x7UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_9HCLK (0x8UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_10HCLK (0x9UL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_11HCLK (0xAUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_12HCLK (0xBUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_13HCLK (0xCUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_14HCLK (0xDUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_15HCLK (0xEUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define XFMC_NOR_SRAM_BUSRECOVERY_TIME_16HCLK (0xFUL << XFMC_BANK1_TR_BUSRECOVERY_SHIFT) +#define IS_XFMC_NOR_SRAM_BUSRECOVERY_TIME(TIME) (0==((TIME) & (~XFMC_BANK1_TR_BUSRECOVERY_MASK))) +/** + * @} + */ + +/** @addtogroup XFMC_CLK_Division + * @{ + */ +#define XFMC_NOR_SRAM_CLK_DIV_2 (0x1UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_3 (0x2UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_4 (0x3UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_5 (0x4UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_6 (0x5UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_7 (0x6UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_8 (0x7UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_9 (0x8UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_10 (0x9UL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_11 (0xAUL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_12 (0xBUL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_13 (0xCUL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_14 (0xDUL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_15 (0xEUL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define XFMC_NOR_SRAM_CLK_DIV_16 (0xFUL << XFMC_BANK1_TR_CLKDIV_SHIFT) +#define IS_XFMC_NOR_SRAM_CLK_DIV(DIV) ( ((DIV) >= XFMC_NOR_SRAM_CLK_DIV_2) \ + && ((DIV) <= XFMC_NOR_SRAM_CLK_DIV_16) ) +/** + * @} + */ + +/** @addtogroup XFMC_Data_Latency + * @{ + */ +#define XFMC_NOR_SRAM_DATA_LATENCY_2CLK (0x0UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_3CLK (0x1UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_4CLK (0x2UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_5CLK (0x3UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_6CLK (0x4UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_7CLK (0x5UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_8CLK (0x6UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_9CLK (0x7UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_10CLK (0x8UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_11CLK (0x9UL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_12CLK (0xAUL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_13CLK (0xBUL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_14CLK (0xCUL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_15CLK (0xDUL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_16CLK (0xEUL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define XFMC_NOR_SRAM_DATA_LATENCY_17CLK (0xFUL << XFMC_BANK1_TR_DATAHLD_SHIFT) +#define IS_XFMC_NOR_SRAM_DATA_LATENCY(TIME) (0==((TIME) & (~XFMC_BANK1_TR_DATAHLD_MASK))) +/** + * @} + */ + +/** @addtogroup XFMC_Access_Mode + * @{ + */ +#define XFMC_NOR_SRAM_ACC_MODE_A ((uint32_t)0x00000000) +#define XFMC_NOR_SRAM_ACC_MODE_B (0x1UL << XFMC_BANK1_TR_ACCMODE_SHIFT) +#define XFMC_NOR_SRAM_ACC_MODE_C (0x2UL << XFMC_BANK1_TR_ACCMODE_SHIFT) +#define XFMC_NOR_SRAM_ACC_MODE_D (0x3UL << XFMC_BANK1_TR_ACCMODE_SHIFT) +#define IS_XFMC_NOR_SRAM_ACCESS_MODE(MODE) ( ((MODE) == XFMC_NOR_SRAM_ACC_MODE_A) || ((MODE) == XFMC_NOR_SRAM_ACC_MODE_B) \ + || ((MODE) == XFMC_NOR_SRAM_ACC_MODE_C) || ((MODE) == XFMC_NOR_SRAM_ACC_MODE_D) ) +/** + * @} End of NOR_SRAM_Time_Control + */ + +/** + * @} + */ + +/** @addtogroup NAND_Controller + * @{ + */ + +/** @addtogroup XFMC_Wait_feature + * @{ + */ +#define XFMC_NAND_NWAIT_DISABLE ((uint32_t)0x00000000) +#define XFMC_NAND_NWAIT_ENABLE (XFMC_CTRL_WAITEN) +#define IS_XFMC_NAND_WAIT_FEATURE(FEATURE) \ + (((FEATURE) == XFMC_NAND_NWAIT_DISABLE) || ((FEATURE) == XFMC_NAND_NWAIT_ENABLE)) +/** + * @} + */ + +/** @addtogroup XFMC_Nand_Enable + * @{ + */ +#define XFMC_NAND_BANK_DISABLE ((uint32_t)0x00000000) +#define XFMC_NAND_BANK_ENABLE (XFMC_CTRL_BANKEN) +/** + * @} + */ + +/** @addtogroup XFMC_Bank23_Memory_Type + * @{ + */ +#define XFMC_BANK23_MEM_TYPE_NAND (XFMC_CTRL_MEMTYPE) +#define IS_XFMC_BANK23_MEM_TYPE(TYPE) ((TYPE) == XFMC_BANK23_MEM_TYPE_NAND) +/** + * @} + */ + +/** @addtogroup XFMC_Wait_feature + * @{ + */ +#define XFMC_NAND_BUS_WIDTH_8B ((uint32_t)0x00000000) +#define XFMC_NAND_BUS_WIDTH_16B (XFMC_CTRL_BUSWID_0) +#define IS_XFMC_NAND_BUS_WIDTH(WIDTH) (((WIDTH) == XFMC_NAND_BUS_WIDTH_8B)||((WIDTH) == XFMC_NAND_BUS_WIDTH_16B)) +/** + * @} + */ + +/** @addtogroup XFMC_Ecc + * @{ + */ +#define XFMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) +#define XFMC_NAND_ECC_ENABLE (XFMC_CTRL_ECCEN) +#define IS_XFMC_ECC_STATE(STATE) (((STATE) == XFMC_NAND_ECC_DISABLE) || ((STATE) == XFMC_NAND_ECC_ENABLE)) +/** + * @} + */ + +/** @addtogroup XFMC_CLE_RE_Delay + * @{ + */ +#define XFMC_NAND_CLE_DELAY_1HCLK (0x0UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_2HCLK (0x1UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_3HCLK (0x2UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_4HCLK (0x3UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_5HCLK (0x4UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_6HCLK (0x5UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_7HCLK (0x6UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_8HCLK (0x7UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_9HCLK (0x8UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_10HCLK (0x9UL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_11HCLK (0xAUL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_12HCLK (0xBUL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_13HCLK (0xCUL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_14HCLK (0xDUL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_15HCLK (0xEUL << XFMC_CTRL_CRDLY_SHIFT) +#define XFMC_NAND_CLE_DELAY_16HCLK (0xFUL << XFMC_CTRL_CRDLY_SHIFT) +#define IS_XFMC_NAND_CLE_DELAY(DELAY) (0==((DELAY) & (~XFMC_CTRL_CRDLY_MASK))) +/** + * @} + */ + +/** @addtogroup XFMC_ALE_RE_Delay + * @{ + */ +#define XFMC_NAND_ALE_DELAY_1HCLK (0x0UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_2HCLK (0x1UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_3HCLK (0x2UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_4HCLK (0x3UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_5HCLK (0x4UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_6HCLK (0x5UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_7HCLK (0x6UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_8HCLK (0x7UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_9HCLK (0x8UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_10HCLK (0x9UL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_11HCLK (0xAUL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_12HCLK (0xBUL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_13HCLK (0xCUL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_14HCLK (0xDUL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_15HCLK (0xEUL << XFMC_CTRL_ARDLY_SHIFT) +#define XFMC_NAND_ALE_DELAY_16HCLK (0xFUL << XFMC_CTRL_ARDLY_SHIFT) +#define IS_XFMC_NAND_ALE_DELAY(DELAY) (0==((DELAY) & (~XFMC_CTRL_ARDLY_MASK))) +/** + * @} + */ + +/** @addtogroup XFMC_ECC_Page_Size + * @{ + */ +#define XFMC_NAND_ECC_PAGE_256BYTES (0x0UL << XFMC_CTRL_ECCPGS_SHIFT) +#define XFMC_NAND_ECC_PAGE_512BYTES (0x1UL << XFMC_CTRL_ECCPGS_SHIFT) +#define XFMC_NAND_ECC_PAGE_1024BYTES (0x2UL << XFMC_CTRL_ECCPGS_SHIFT) +#define XFMC_NAND_ECC_PAGE_2048BYTES (0x3UL << XFMC_CTRL_ECCPGS_SHIFT) +#define XFMC_NAND_ECC_PAGE_4096BYTES (0x4UL << XFMC_CTRL_ECCPGS_SHIFT) +#define XFMC_NAND_ECC_PAGE_8192BYTES (0x5UL << XFMC_CTRL_ECCPGS_SHIFT) +#define IS_XFMC_NAND_ECC_PAGE_SIZE(SIZE) (0==((SIZE) & (~XFMC_CTRL_ECCPGS_MASK))) +/** + * @} + */ + +/** + * @} End of NAND_Controller + */ + +/** @addtogroup XFMC_StatusFlag + * @{ + */ +#define XFMC_NAND_FLAG_FIFO_EMPTY (XFMC_STS_FIFOEMPT) +#define IS_XFMC_NAND_FLAG(FLAG) ((FLAG)==XFMC_NAND_FLAG_FIFO_EMPTY) +/** + * @} + */ + + +/** @addtogroup XFMC_TimeController + * @{ + */ + +/** @addtogroup XFMC_Setup_Time + * @{ + */ +#define XFMC_NAND_SETUP_TIME_MIN (0x00000000) +#define XFMC_NAND_SETUP_TIME_MAX (0x000000FF) +#define XFMC_NAND_SETUP_TIME_DEFAULT (0x000000FC) +#define IS_XFMC_NAND_SETUP_TIME(TIME) ((TIME) <= XFMC_NAND_SETUP_TIME_MAX) +/** + * @} + */ + +/** @addtogroup XFMC_Wait_Time + * @{ + */ +#define XFMC_NAND_WAIT_TIME_MIN (0x00000001) +#define XFMC_NAND_WAIT_TIME_MAX (0x000000FF) +#define XFMC_NAND_WAIT_TIME_DEFAULT (0x000000FC) +#define IS_XFMC_NAND_WAIT_TIME(TIME) ( ((TIME) >= XFMC_NAND_WAIT_TIME_MIN) \ + && ((TIME) <= XFMC_NAND_WAIT_TIME_MAX) ) +/** + * @} + */ + +/** @addtogroup XFMC_Hold_Time + * @{ + */ +#define XFMC_NAND_HOLD_TIME_MIN (0x00000001) +#define XFMC_NAND_HOLD_TIME_MAX (0x000000FF) +#define XFMC_NAND_HOLD_TIME_DEFAULT (0x000000FC) +#define IS_XFMC_NAND_HOLD_TIME(TIME) ( ((TIME) >= XFMC_NAND_HOLD_TIME_MIN) \ + && ((TIME) <= XFMC_NAND_HOLD_TIME_MAX) ) +/** + * @} + */ + +/** @addtogroup XFMC_HiZ_Time + * @{ + */ +#define XFMC_NAND_HIZ_TIME_MIN (0x00000000) +#define XFMC_NAND_HIZ_TIME_MAX (0x000000FF) +#define XFMC_NAND_HIZ_TIME_DEFAULT (0x000000FC) +#define IS_XFMC_NAND_HIZ_TIME(TIME) ((TIME) <= XFMC_NAND_HIZ_TIME_MAX) +/** + * @} + */ + +/** + * @} End of XFMC_TimeController + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup XFMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup XFMC_Exported_Functions + * @{ + */ + +void XFMC_DeInitNorSram(XFMC_Bank1_Block *Block); +void XFMC_DeInitNand(XFMC_Bank23_Module *Bank); +void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct); +void XFMC_InitNand(XFMC_NandInitType* XFMC_NANDInitStruct); +void XFMC_InitNorSramStruct(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct); +void XFMC_InitNandStruct(XFMC_NandInitType* XFMC_NANDInitStruct); +void XFMC_EnableNorSram(XFMC_Bank1_Block *Block, FunctionalState Cmd); +void XFMC_EnableNand(XFMC_Bank23_Module *Bank, FunctionalState Cmd); +void XFMC_EnableNandEcc(XFMC_Bank23_Module *Bank, FunctionalState Cmd); +void XFMC_RestartNandEcc(XFMC_Bank23_Module *Bank); +uint32_t XFMC_GetEcc(XFMC_Bank23_Module *Bank); +FlagStatus XFMC_GetFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG); +void XFMC_ClrFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G45X_XFMC_H__ */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/misc.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/misc.c new file mode 100644 index 0000000000..274a8058cb --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/misc.c @@ -0,0 +1,229 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file misc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "misc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @addtogroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @addtogroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority + * 0 bits for subpriority + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains + * the configuration information for the specified NVIC peripheral. + */ +void NVIC_Init(NVIC_InitType* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset Vector Table base offset field. This value must be a multiple + * of 0x200. + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE. + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source. + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + //SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_adc.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_adc.c new file mode 100644 index 0000000000..b63dfb7117 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_adc.c @@ -0,0 +1,1465 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_adc.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_adc.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @addtogroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Defines + * @{ + */ + +/* ADC DISC_NUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISC_EN mask */ +#define CTRL1_DISC_EN_SET ((uint32_t)0x00000800) +#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF) + +/* ADC INJ_AUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC INJ_DISC_EN mask */ +#define CTRL1_INJ_DISC_EN_SET ((uint32_t)0x00001000) +#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF) + +/* ADC AWDG_CH mask */ +#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF) + +/* CTRL1 register Mask */ +#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF) + +/* ADC AD_ON mask */ +#define CTRL2_AD_ON_SET ((uint32_t)0x00000001) +#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTRL2_DMA_SET ((uint32_t)0x00000100) +#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF) + +/* ADC CAL mask */ +#define CTRL2_CAL_SET ((uint32_t)0x00000004) + +/* ADC SOFT_START mask */ +#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000) + +/* ADC EXT_TRIG mask */ +#define CTRL2_EXT_TRIG_SET ((uint32_t)0x00100000) +#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000) +#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF) + +/* ADC INJ_EXT_SEL mask */ +#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF) + +/* ADC INJ_EXT_TRIG mask */ +#define CTRL2_INJ_EXT_TRIG_SET ((uint32_t)0x00008000) +#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF) + +/* ADC INJ_SWSTART mask */ +#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET ((uint32_t)0x00208000) +#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000) +#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) + +/* CTRL2 register Mask */ +#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR4_SEQ_SET ((uint32_t)0x0000001F) +#define SQR3_SEQ_SET ((uint32_t)0x0000001F) +#define SQR2_SEQ_SET ((uint32_t)0x0000001F) +#define SQR1_SEQ_SET ((uint32_t)0x0000001F) + +/* RSEQ1 register Mask */ +#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSEQ_JSQ_SET ((uint32_t)0x0000001F) + +/* ADC INJ_LEN mask */ +#define JSEQ_INJ_LEN_SET ((uint32_t)0x00300000) +#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SAMPTx mask */ +#define SAMPT1_SMP_SET ((uint32_t)0x00000007) +#define SAMPT2_SMP_SET ((uint32_t)0x00000007) + +/* ADC JDATx registers offset */ +#define JDAT_OFFSET ((uint8_t)0x28) + +/* ADC1 DAT register base address */ +#define DAT_ADDR ((uint32_t)0x4001244C) + +/** + * @} + */ + +/** @addtogroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral. + */ +void ADC_DeInit(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + + if (ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC1, DISABLE); + } + else if (ADCx == ADC2) + { + /* Enable ADC2 reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC2, DISABLE); + } + else if (ADCx == ADC3) + { + /* Enable ADC2 reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC3, ENABLE); + /* Release ADC2 from reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC3, DISABLE); + } + else + { + if (ADCx == ADC4) + { + /* Enable ADC3 reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC4, ENABLE); + /* Release ADC3 from reset state */ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC4, DISABLE); + } + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral. + * @param ADC_InitStruct pointer to an ADC_InitType structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcWorkMode(ADC_InitStruct->WorkMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn)); + assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect)); + assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign)); + assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber)); + + /*---------------------------- ADCx CTRL1 Configuration -----------------*/ + /* Get the ADCx CTRL1 value */ + tmpreg1 = ADCx->CTRL1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CTRL1_CLR_MASK; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to WorkMode value */ + /* Set SCAN bit according to MultiChEn value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->WorkMode | ((uint32_t)ADC_InitStruct->MultiChEn << 8)); + /* Write to ADCx CTRL1 */ + ADCx->CTRL1 = tmpreg1; + + /*---------------------------- ADCx CTRL2 Configuration -----------------*/ + /* Get the ADCx CTRL2 value */ + tmpreg1 = ADCx->CTRL2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CTRL2_CLR_MASK; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to DatAlign value */ + /* Set EXTSEL bits according to ExtTrigSelect value */ + /* Set CONT bit according to ContinueConvEn value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect + | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1)); + /* Write to ADCx CTRL2 */ + ADCx->CTRL2 = tmpreg1; + + /*---------------------------- ADCx RSEQ1 Configuration -----------------*/ + /* Get the ADCx RSEQ1 value */ + tmpreg1 = ADCx->RSEQ1; + /* Clear L bits */ + tmpreg1 &= RSEQ1_CLR_MASK; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ChsNumber value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx RSEQ1 */ + ADCx->RSEQ1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized. + */ +void ADC_InitStruct(ADC_InitType* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the WorkMode member */ + ADC_InitStruct->WorkMode = ADC_WORKMODE_INDEPENDENT; + /* initialize the MultiChEn member */ + ADC_InitStruct->MultiChEn = DISABLE; + /* Initialize the ContinueConvEn member */ + ADC_InitStruct->ContinueConvEn = DISABLE; + /* Initialize the ExtTrigSelect member */ + ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1; + /* Initialize the DatAlign member */ + ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R; + /* Initialize the ChsNumber member */ + ADC_InitStruct->ChsNumber = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the AD_ON bit to wake up the ADC from power down mode */ + ADCx->CTRL2 |= CTRL2_AD_ON_SET; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CTRL2 &= CTRL2_AD_ON_RESET; + } +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcDmaModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CTRL2 |= CTRL2_DMA_SET; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CTRL2 &= CTRL2_DMA_RESET; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + * @param Cmd new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IsAdcInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (Cmd != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CTRL1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CTRL1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + */ +void ADC_StartCalibration(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Enable the selected ADC calibration process */ + ADCx->CTRL2 |= CTRL2_CAL_SET; +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of SOFT_START bit */ + if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET) + { + /* SOFT_START bit is set */ + bitstatus = SET; + } + else + { + /* SOFT_START bit is reset */ + bitstatus = RESET; + } + /* Return the SOFT_START bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Number specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + */ +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcSeqDiscNumberValid(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CTRL1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CTRL1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 |= CTRL1_DISC_EN_SET; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 &= CTRL1_DISC_EN_RESET; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + assert_param(IsAdcReqRankValid(Rank)); + assert_param(IsAdcSampleTime(ADC_SampleTime)); + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->RSEQ1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->RSEQ1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The Data conversion value. + */ +uint16_t ADC_GetDat(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t)ADCx->DAT; +} + +/** + * @brief Returns the last ADC1 and ADC2 OR last ADC3 and ADC4 conversion result data in dual mode. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionDat(ADC_Module* ADCx) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Return the dual mode conversion value */ + if(ADCx==ADC1 | ADCx==ADC2) + return (uint32_t)ADC1->DAT; + else + return (uint32_t)ADC3->DAT; +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJ_CONV_T4_CC3 Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC2 Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC4 Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T5_TRGO Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_T5_CC4 Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJ_CONV_NONE Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + */ +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpregister = ADCx->CTRL2; + /* Clear the old external event selection for injected group */ + tmpregister &= CTRL2_INJ_EXT_SEL_RESET; + /* Set the external event selection for injected group */ + tmpregister |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CTRL2 = tmpregister; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Cmd new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @return The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + /* Check the status of INJ_SWSTART bit */ + if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET) + { + /* INJ_SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* INJ_SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the INJ_SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles + * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles + * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles + * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles + * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles + * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles + * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles + * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles + */ +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + assert_param(IsAdcInjRankValid(Rank)); + assert_param(IsAdcSampleTime(ADC_SampleTime)); + + if (ADC_Channel == ADC_CH_18) + { + tmpreg1 = ADCx->SAMPT3; + tmpreg1 &= (~0x00000007); + tmpreg1 |= ADC_SampleTime; + ADCx->SAMPT3 = tmpreg1; + } + else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSEQ; + /* Get INJ_LEN value: Number = INJ_LEN+1 */ + tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */ + tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSEQ = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param Length The sequencer length. + * This parameter must be a number between 1 to 4. + */ +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjLenValid(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSEQ; + /* Clear the old injected sequnence lenght INJ_LEN bits */ + tmpreg1 &= JSEQ_INJ_LEN_RESET; + /* Set the injected sequnence lenght INJ_LEN bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSEQ = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_InjectedChannel the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_INJ_CH_1 Injected Channel1 selected + * @arg ADC_INJ_CH_2 Injected Channel2 selected + * @arg ADC_INJ_CH_3 Injected Channel3 selected + * @arg ADC_INJ_CH_4 Injected Channel4 selected + * @param Offset the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + */ +void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjCh(ADC_InjectedChannel)); + assert_param(IsAdcOffsetValid(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t*)tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_InjectedChannel the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_INJ_CH_1 Injected Channel1 selected + * @arg ADC_INJ_CH_2 Injected Channel2 selected + * @arg ADC_INJ_CH_3 Injected Channel3 selected + * @arg ADC_INJ_CH_4 Injected Channel4 selected + * @return The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInjCh(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDAT_OFFSET; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t)(*(__IO uint32_t*)tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_AnalogWatchdog the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel + * @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel + * @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel + * @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on all regular channel + * @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on all injected channel + * @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels + * @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog + */ +void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpregister = ADCx->CTRL1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpregister &= CTRL1_AWDG_MODE_RESET; + /* Set the analog watchdog enable mode */ + tmpregister |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CTRL1 = tmpregister; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param HighThreshold the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + */ +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcValid(HighThreshold)); + assert_param(IsAdcValid(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->WDGHIGH = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->WDGLOW = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_Channel the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_CH_0 ADC Channel0 selected + * @arg ADC_CH_1 ADC Channel1 selected + * @arg ADC_CH_2 ADC Channel2 selected + * @arg ADC_CH_3 ADC Channel3 selected + * @arg ADC_CH_4 ADC Channel4 selected + * @arg ADC_CH_5 ADC Channel5 selected + * @arg ADC_CH_6 ADC Channel6 selected + * @arg ADC_CH_7 ADC Channel7 selected + * @arg ADC_CH_8 ADC Channel8 selected + * @arg ADC_CH_9 ADC Channel9 selected + * @arg ADC_CH_10 ADC Channel10 selected + * @arg ADC_CH_11 ADC Channel11 selected + * @arg ADC_CH_12 ADC Channel12 selected + * @arg ADC_CH_13 ADC Channel13 selected + * @arg ADC_CH_14 ADC Channel14 selected + * @arg ADC_CH_15 ADC Channel15 selected + * @arg ADC_CH_16 ADC Channel16 selected + * @arg ADC_CH_17 ADC Channel17 selected + * @arg ADC_CH_18 ADC Channel18 selected + */ +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcChannel(ADC_Channel)); + /* Get the old register value */ + tmpregister = ADCx->CTRL1; + /* Clear the Analog watchdog channel select bits */ + tmpregister &= CTRL1_AWDG_CH_RESET; + /* Set the Analog watchdog channel */ + tmpregister |= ADC_Channel; + /* Store the new register value */ + ADCx->CTRL1 = tmpregister; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param Cmd new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + */ +void ADC_EnableTempSensorVrefint(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CTRL2 |= CTRL2_TSVREFE_SET; + _EnVref1p2() + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CTRL2 &= CTRL2_TSVREFE_RESET; + _DisVref1p2() + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWDG Analog watchdog flag + * @arg ADC_FLAG_ENDC End of conversion flag + * @arg ADC_FLAG_JENDC End of injected group conversion flag + * @arg ADC_FLAG_JSTR Start of injected group conversion flag + * @arg ADC_FLAG_STR Start of regular group conversion flag + * @return The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetFlag(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWDG Analog watchdog flag + * @arg ADC_FLAG_ENDC End of conversion flag + * @arg ADC_FLAG_JENDC End of injected group conversion flag + * @arg ADC_FLAG_JSTR Start of injected group conversion flag + * @arg ADC_FLAG_STR Start of regular group conversion flag + */ +void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcClrFlag(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->STS &= ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + * @return The new state of ADC_IT (SET or RESET). + */ +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT) +{ + INTStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT); + /* Check the status of the specified ADC interrupt */ + if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_IT specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_INT_ENDC End of conversion interrupt mask + * @arg ADC_INT_AWD Analog watchdog interrupt mask + * @arg ADC_INT_JENDC End of injected conversion interrupt mask + */ +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcInt(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->STS &= ~(uint32_t)itmask; +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStructEx. + * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral. + * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains + * the configuration information for the specified ADC peripheral. + */ +void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx) +{ + uint32_t tmpregister = 0; + /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/ + if (ADC_InitStructEx->SampSecondStyle) + ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK; + else + ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK); + + /*intial ADC_CTRL3 once initiall config*/ + tmpregister = ADCx->CTRL3; + if (ADC_InitStructEx->VbatMinitEn) + { + tmpregister |= ADC_CTRL3_VABTMEN_MSK; + _EnVref1p2() + } + else + { + tmpregister &= (~ADC_CTRL3_VABTMEN_MSK); + _DisVref1p2() + } + + if (ADC_InitStructEx->DeepPowerModEn) + tmpregister |= ADC_CTRL3_DPWMOD_MSK; + else + tmpregister &= (~ADC_CTRL3_DPWMOD_MSK); + + if (ADC_InitStructEx->JendcIntEn) + tmpregister |= ADC_CTRL3_JENDCAIEN_MSK; + else + tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK); + + if (ADC_InitStructEx->EndcIntEn) + tmpregister |= ADC_CTRL3_ENDCAIEN_MSK; + else + tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK); + + if (ADC_InitStructEx->CalAtuoLoadEn) + tmpregister |= ADC_CTRL3_CALALD_MSK; + else + tmpregister &= (~ADC_CTRL3_CALALD_MSK); + + if (ADC_InitStructEx->DifModCal) + tmpregister |= ADC_CTRL3_CALDIF_MSK; + else + tmpregister &= (~ADC_CTRL3_CALDIF_MSK); + + tmpregister &= (~ADC_CTRL3_RES_MSK); + tmpregister |= ADC_InitStructEx->ResBit; + + tmpregister &= (~ADC_CTRL3_CKMOD_MSK); + if(ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL) + tmpregister |= ADC_CTRL3_CKMOD_MSK; + + ADCx->CTRL3 = tmpregister; +} +/** + * @brief Configure differential channels enable. + * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral. + * @param DifChs differential channels,see @ADC_dif_sel_ch_definition. eg: ADC_DIFSEL_CHS_3|ADC_DIFSEL_CHS_4 + */ +void ADC_SetDifChsEnable(ADC_Module* ADCx,uint32_t DifChs) +{ + ADCx->DIFSEL = DifChs; +} +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ADC_FLAG_NEW specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_RDY ADC ready flag + * @arg ADC_FLAG_PD_RDY ADC powerdown ready flag + * @return The new state of ADC_FLAG_NEW (SET or RESET). + */ +FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsAdcModule(ADCx)); + assert_param(IsAdcGetFlag(ADC_FLAG_NEW)); + /* Check the status of the specified ADC flag */ + if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET) + { + /* ADC_FLAG_NEW is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG_NEW is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG_NEW status */ + return bitstatus; +} +/** + * @brief Set Adc calibration bypass or enable. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param en enable bypass calibration. + * This parameter can be one of the following values: + * @arg true bypass calibration + * @arg false not bypass calibration + */ +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en) +{ + uint32_t tmpregister = 0; + + tmpregister = ADCx->CTRL3; + if (en) + tmpregister |= ADC_CTRL3_BPCAL_MSK; + else + tmpregister &= (~ADC_CTRL3_BPCAL_MSK); + ADCx->CTRL3 = tmpregister; +} +/** + * @brief Set Adc trans bits width. + * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral. + * @param ResultBitNum specifies num with adc trans width. + * This parameter can be one of the following values: + * @arg ADC_RST_BIT_12 12 bit trans + * @arg ADC_RST_BIT_10 10 bit trans + * @arg ADC_RST_BIT_8 8 bit trans + * @arg ADC_RESULT_BIT_6 6 bit trans + */ +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum) +{ + uint32_t tmpregister = 0; + + tmpregister = ADCx->CTRL3; + tmpregister &= 0xFFFFFFFC; + tmpregister |= ResultBitNum; + ADCx->CTRL3 = tmpregister; + return; +} + +/** + * @brief Configures the ADCHCLK prescaler. + * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1 + * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2 + * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4 + * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6 + * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8 + * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10 + * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12 + * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32 + + * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable + * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1 + * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2 + * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4 + * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6 + * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8 + * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10 + * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12 + * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16 + * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32 + * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64 + * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256 + */ +void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler) +{ + if(ADC_ClkMode==ADC_CTRL3_CKMOD_AHB) + { + RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE); + RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler); + } + else + { + RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE); + RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_bkp.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_bkp.c new file mode 100644 index 0000000000..5c8a983be0 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_bkp.c @@ -0,0 +1,252 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_bkp.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_bkp.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @brief BKP driver modules + * @{ + */ + +/** @addtogroup BKP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup BKP_Private_Defines + * @{ + */ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CTRL Register ----*/ + +/* Alias word address of TP_ALEV bit */ +#define CTRL_OFFSET (BKP_OFFSET + 0x30) +#define TP_ALEV_BIT 0x01 +#define CTRL_TP_ALEV_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TP_ALEV_BIT * 4)) + +/* Alias word address of TP_EN bit */ +#define TP_EN_BIT 0x00 +#define CTRL_TP_EN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TP_EN_BIT * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of TPINT_EN bit */ +#define CTRLSTS_OFFSET (BKP_OFFSET + 0x34) +#define TPINT_EN_BIT 0x02 +#define CTRLSTS_TPINT_EN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPINT_EN_BIT * 4)) + +/* Alias word address of TINTF bit */ +#define TINTF_BIT 0x09 +#define CTRLSTS_TINTF_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TINTF_BIT * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BIT 0x08 +#define CTRLSTS_TEF_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TEF_BIT * 4)) + + +/** + * @} + */ + +/** @addtogroup BKP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup BKP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup BKP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup BKP_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the BKP peripheral registers to their default reset values. + */ +void BKP_DeInit(void) +{ + RCC_EnableBackupReset(ENABLE); + RCC_EnableBackupReset(DISABLE); +} + +/** + * @brief Configures the Tamper Pin active level. + * @param BKP_TamperPinLevel specifies the Tamper Pin active level. + * This parameter can be one of the following values: + * @arg BKP_TP_HIGH Tamper pin active on high level + * @arg BKP_TP_LOW Tamper pin active on low level + */ +void BKP_ConfigTPLevel(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TP_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t*)CTRL_TP_ALEV_BB = BKP_TamperPinLevel; +} + +/** + * @brief Enables or disables the Tamper Pin activation. + * @param Cmd new state of the Tamper Pin activation. + * This parameter can be: ENABLE or DISABLE. + */ +void BKP_TPEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_TP_EN_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the Tamper Pin Interrupt. + * @param Cmd new state of the Tamper Pin Interrupt. + * This parameter can be: ENABLE or DISABLE. + */ +void BKP_TPIntEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_TPINT_EN_BB = (uint32_t)Cmd; +} + + +/** + * @brief Writes user data to the specified Data Backup Register. + * @param BKP_DAT specifies the Data Backup Register. + * This parameter can be BKP_DATx where x:[1, 42] + * @param Data data to write + */ +void BKP_WriteBkpData(uint16_t BKP_DAT, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DAT(BKP_DAT)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DAT; + + *(__IO uint32_t*)tmp = Data; +} + +/** + * @brief Reads data from the specified Data Backup Register. + * @param BKP_DAT specifies the Data Backup Register. + * This parameter can be BKP_DATx where x:[1, 42] + * @return The content of the specified Data Backup Register + */ +uint16_t BKP_ReadBkpData(uint16_t BKP_DAT) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DAT(BKP_DAT)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DAT; + + return (*(__IO uint16_t*)tmp); +} + +/** + * @brief Checks whether the Tamper Pin Event flag is set or not. + * @return The new state of the Tamper Pin Event flag (SET or RESET). + */ +FlagStatus BKP_GetTEFlag(void) +{ + return (FlagStatus)(*(__IO uint32_t*)CTRLSTS_TEF_BB); +} + +/** + * @brief Clears Tamper Pin Event pending flag. + */ +void BKP_ClrTEFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CTRLSTS |= BKP_CTRLSTS_CLRTE; +} + +/** + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * @return The new state of the Tamper Pin Interrupt (SET or RESET). + */ +INTStatus BKP_GetTINTFlag(void) +{ + return (INTStatus)(*(__IO uint32_t*)CTRLSTS_TINTF_BB); +} + +/** + * @brief Clears Tamper Pin Interrupt pending bit. + */ +void BKP_ClrTINTFlag(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CTRLSTS |= BKP_CTRLSTS_CLRTINT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_can.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_can.c new file mode 100644 index 0000000000..6ec9f947e9 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_can.c @@ -0,0 +1,1478 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_can.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_can.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @addtogroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ +#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */ +#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTS register */ +#define CAN_FLAGS_TSTS ((uint32_t)0x08000000) +/* Flags in RFF1 register */ +#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000) +/* Flags in RFF0 register */ +#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000) +/* Flags in MSTS register */ +#define CAN_FLAGS_MSTS ((uint32_t)0x01000000) +/* Flags in ESTS register */ +#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t)0x00000003) +/** + * @} + */ + +/** @addtogroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_FunctionPrototypes + * @{ + */ + +static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit); + +/** + * @} + */ + +/** @addtogroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx where x can be 1 or 2 to select the CAN peripheral. + */ +void CAN_DeInit(CAN_Module* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitParam. + * @param CANx where x can be 1 or 2 to to select the CAN + * peripheral. + * @param CAN_InitParam pointer to a CAN_InitType structure that + * contains the configuration information for the + * CAN peripheral. + * @return Constant indicates initialization succeed which will be + * CAN_InitSTS_Failed or CAN_InitSTS_Success. + */ +uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam) +{ + uint8_t InitStatus = CAN_InitSTS_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP)); + assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode)); + assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW)); + assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1)); + assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2)); + assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler)); + + /* Exit from sleep mode */ + CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ); + + /* Request initialisation */ + CANx->MCTRL |= CAN_MCTRL_INIRQ; + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) + { + InitStatus = CAN_InitSTS_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitParam->TTCM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_TTCM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitParam->ABOM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_ABOM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitParam->AWKUM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_AWKUM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitParam->NART == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_NART; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART; + } + + /* Set the receive DATFIFO locked mode */ + if (CAN_InitParam->RFLM == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_RFLM; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM; + } + + /* Set the transmit DATFIFO priority */ + if (CAN_InitParam->TXFP == ENABLE) + { + CANx->MCTRL |= CAN_MCTRL_TXFP; + } + else + { + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP; + } + + /* Set the bit timing register */ + CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24) + | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20) + | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1); + + /* Request leave initialisation */ + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) + { + InitStatus = CAN_InitSTS_Failed; + } + else + { + InitStatus = CAN_InitSTS_Success; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN1 peripheral according to the specified + * parameters in the CAN_InitFilterStruct. + * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType + * structure that contains the configuration + * information. + */ +void CAN1_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num)); + assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num; + + /* Initialisation mode for the filter */ + CAN1->FMC |= FMC_FINITM; + + /* Filter Deactivation */ + CAN1->FA1 &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale) + { + /* 16-bit scale for the filter */ + CAN1->FS1 &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId); + } + + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale) + { + /* 32-bit scale for the filter */ + CAN1->FS1 |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId); + } + + /* Filter Mode */ + if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1 &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter DATFIFO assignment */ + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0) + { + /* DATFIFO 0 assignation for the filter */ + CAN1->FFA1 &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1) + { + /* DATFIFO 1 assignation for the filter */ + CAN1->FFA1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_InitFilterStruct->Filter_Act == ENABLE) + { + CAN1->FA1 |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMC &= ~FMC_FINITM; +} + +/** + * @brief Initializes the CAN2 peripheral according to the specified + * parameters in the CAN_InitFilterStruct. + * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType + * structure that contains the configuration + * information. + */ +void CAN2_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num)); + assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num; + + /* Initialisation mode for the filter */ + CAN2->FMC |= FMC_FINITM; + + /* Filter Deactivation */ + CAN2->FA1 &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale) + { + /* 16-bit scale for the filter */ + CAN2->FS1 &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN2->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN2->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId); + } + + if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale) + { + /* 32-bit scale for the filter */ + CAN2->FS1 |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN2->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId); + /* 32-bit mask or Second 32-bit identifier */ + CAN2->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 = + ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16) + | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId); + } + + /* Filter Mode */ + if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode) + { + /*Id/Mask mode for the filter*/ + CAN2->FM1 &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */ + { + /*Identifier list mode for the filter*/ + CAN2->FM1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter DATFIFO assignment */ + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0) + { + /* DATFIFO 0 assignation for the filter */ + CAN2->FFA1 &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1) + { + /* DATFIFO 1 assignation for the filter */ + CAN2->FFA1 |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_InitFilterStruct->Filter_Act == ENABLE) + { + CAN2->FA1 |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN2->FMC &= ~FMC_FINITM; +} + +/** + * @brief Fills each CAN_InitParam member with its default value. + * @param CAN_InitParam pointer to a CAN_InitType structure which + * will be initialized. + */ +void CAN_InitStruct(CAN_InitType* CAN_InitParam) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitParam->TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitParam->ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitParam->AWKUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitParam->NART = DISABLE; + + /* Initialize the receive DATFIFO locked mode */ + CAN_InitParam->RFLM = DISABLE; + + /* Initialize the transmit DATFIFO priority */ + CAN_InitParam->TXFP = DISABLE; + + /* Initialize the OperatingMode member */ + CAN_InitParam->OperatingMode = CAN_Normal_Mode; + + /* Initialize the RSJW member */ + CAN_InitParam->RSJW = CAN_RSJW_1tq; + + /* Initialize the TBS1 member */ + CAN_InitParam->TBS1 = CAN_TBS1_4tq; + + /* Initialize the TBS2 member */ + CAN_InitParam->TBS2 = CAN_TBS2_3tq; + + /* Initialize the BaudRatePrescaler member */ + CAN_InitParam->BaudRatePrescaler = 1; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param Cmd new state of the CAN peripheral. This parameter can + * be: ENABLE or DISABLE. + */ +void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCTRL |= MCTRL_DBGF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCTRL &= ~MCTRL_DBGF; + } +} + +/** + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param Cmd Mode new state , can be one of @ref FunctionalState. + * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last + * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 + * and TIME[15:8] in data byte 7 + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + */ +void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCTRL |= CAN_MCTRL_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT); + CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT); + CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT); + CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT); + CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT); + } +} +/** + * @brief Initiates the transmission of a message. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * @return The number of the mailbox that is used for transmission + * or CAN_TxSTS_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ID(TxMessage->IDE)); + assert_param(IS_CAN_RTRQ(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxSTS_NoMailBox; + } + + if (transmit_mailbox != CAN_TxSTS_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Standard_Id) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TMDL = + (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16) + | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TMDH = + (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16) + | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx where x can be 1 or 2 to to select the + * CAN peripheral. + * @param TransmitMailbox the number of the mailbox that is used for + * transmission. + * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed + * in an other case. + */ +uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2); + break; + default: + state = CAN_TxSTS_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): + state = CAN_TxSTS_Pending; + break; + /* transmit failed */ + case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0): + state = CAN_TxSTS_Failed; + break; + case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1): + state = CAN_TxSTS_Failed; + break; + case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2): + state = CAN_TxSTS_Failed; + break; + /* transmit succeeded */ + case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0): + state = CAN_TxSTS_Ok; + break; + case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1): + state = CAN_TxSTS_Ok; + break; + case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2): + state = CAN_TxSTS_Ok; + break; + default: + state = CAN_TxSTS_Failed; + break; + } + return (uint8_t)state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox Mailbox number. + */ +void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): + CANx->TSTS |= CAN_TSTS_ABRQM0; + break; + case (CAN_TXMAILBOX_1): + CANx->TSTS |= CAN_TSTS_ABRQM1; + break; + case (CAN_TXMAILBOX_2): + CANx->TSTS |= CAN_TSTS_ABRQM2; + break; + default: + break; + } +} + +/** + * @brief Receives a message. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + */ +void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI; + if (RxMessage->IDE == CAN_Standard_Id) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24); + /* Release the DATFIFO */ + /* Release FIFO0 */ + if (FIFONum == CAN_FIFO0) + { + CANx->RFF0 |= CAN_RFF0_RFFOM0; + } + /* Release FIFO1 */ + else /* FIFONum == CAN_FIFO1 */ + { + CANx->RFF1 |= CAN_RFF1_RFFOM1; + } +} + +/** + * @brief Releases the specified DATFIFO. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1. + */ +void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + /* Release FIFO0 */ + if (FIFONum == CAN_FIFO0) + { + CANx->RFF0 |= CAN_RFF0_RFFOM0; + } + /* Release FIFO1 */ + else /* FIFONum == CAN_FIFO1 */ + { + CANx->RFF1 |= CAN_RFF1_RFFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1. + * @return NbMessage : which is the number of pending message. + */ +uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum) +{ + uint8_t message_pending = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONum)); + if (FIFONum == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03); + } + else if (FIFONum == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + +/** + * @brief Select the CAN Operation mode. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_OperatingMode CAN Operating Mode. This parameter can be one + * of @ref CAN_operating_mode enumeration. + * @return status of the requested mode which can be + * - CAN_ModeSTS_Failed CAN failed entering the specific mode + * - CAN_ModeSTS_Success CAN Succeed entering the specific mode + + */ +uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeSTS_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INIAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_Operating_InitMode) + { + /* Request initialisation */ + CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else if (CAN_OperatingMode == CAN_Operating_NormalMode) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != 0) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else if (CAN_OperatingMode == CAN_Operating_SleepMode) + { + /* Request Sleep mode */ + CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ); + + /* Wait the acknowledge */ + while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) + { + status = CAN_ModeSTS_Failed; + } + else + { + status = CAN_ModeSTS_Success; + } + } + else + { + status = CAN_ModeSTS_Failed; + } + + return (uint8_t)status; +} + +/** + * @brief Enters the low power mode. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an + * other case. + */ +uint8_t CAN_EnterSleep(CAN_Module* CANx) +{ + uint8_t sleepstatus = CAN_SLEEP_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ); + + /* Sleep mode status */ + if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_SLEEP_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @return status: CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an + * other case. + */ +uint8_t CAN_WakeUp(CAN_Module* CANx) +{ + uint32_t wait_slak = SLPAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WKU_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ; + + /* Sleep mode status */ + while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00)) + { + wait_slak--; + } + if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WKU_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @return CAN_ErrorCode: specifies the Error code : + * - CAN_ERRORCODE_NoErr No Error + * - CAN_ERRORCODE_StuffErr Stuff Error + * - CAN_ERRORCODE_FormErr Form Error + * - CAN_ERRORCODE_ACKErr Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error + * - CAN_ERRORCODE_CRCErr CRC Error + * - CAN_ERRORCODE_SoftwareSetErr Software Set Error + */ + +uint8_t CAN_GetLastErrCode(CAN_Module* CANx) +{ + uint8_t errorcode = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC); + + /* Return the error code*/ + return errorcode; +} +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @return CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @return LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_INT specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * - CAN_INT_TME, + * - CAN_INT_FMP0, + * - CAN_INT_FF0, + * - CAN_INT_FOV0, + * - CAN_INT_FMP1, + * - CAN_INT_FF1, + * - CAN_INT_FOV1, + * - CAN_INT_EWG, + * - CAN_INT_EPV, + * - CAN_INT_LEC, + * - CAN_INT_ERR, + * - CAN_INT_WKU or + * - CAN_INT_SLK. + * @param Cmd new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_INT(CAN_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->INTE |= CAN_INT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->INTE &= ~CAN_INT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG specifies the flag to check. + * This parameter can be one of the following flags: + * - CAN_FLAG_EWGFL + * - CAN_FLAG_EPVFL + * - CAN_FLAG_BOFFL + * - CAN_FLAG_RQCPM0 + * - CAN_FLAG_RQCPM1 + * - CAN_FLAG_RQCPM2 + * - CAN_FLAG_FFMP1 + * - CAN_FLAG_FFULL1 + * - CAN_FLAG_FFOVR1 + * - CAN_FLAG_FFMP0 + * - CAN_FLAG_FFULL0 + * - CAN_FLAG_FFOVR0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @return The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG specifies the flag to clear. + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCPM0 + * - CAN_FLAG_RQCPM1 + * - CAN_FLAG_RQCPM2 + * - CAN_FLAG_FFULL1 + * - CAN_FLAG_FFOVR1 + * - CAN_FLAG_FFULL0 + * - CAN_FLAG_FFOVR0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + */ +void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */ + { + /* Clear the selected CAN flags */ + CANx->ESTS = (uint32_t)RESET; + } + else /* MSTS or TSTS or RFF0 or RFF1 */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET) + { + /* Receive Flags */ + CANx->RFF0 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET) + { + /* Receive Flags */ + CANx->RFF1 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSTS = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSTS = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_INT specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_INT_TME + * - CAN_INT_FMP0 + * - CAN_INT_FF0 + * - CAN_INT_FOV0 + * - CAN_INT_FMP1 + * - CAN_INT_FF1 + * - CAN_INT_FOV1 + * - CAN_INT_WKU + * - CAN_INT_SLK + * - CAN_INT_EWG + * - CAN_INT_EPV + * - CAN_INT_BOF + * - CAN_INT_LEC + * - CAN_INT_ERR + * @return The current state of CAN_INT (SET or RESET). + */ +INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT) +{ + INTStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_INT(CAN_INT)); + + /* check the enable interrupt bit */ + if ((CANx->INTE & CAN_INT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_INT) + { + case CAN_INT_TME: + /* Check CAN_TSTS_RQCPx bits */ + itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2); + break; + case CAN_INT_FMP0: + /* Check CAN_RFF0_FFMP0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0); + break; + case CAN_INT_FF0: + /* Check CAN_RFF0_FFULL0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0); + break; + case CAN_INT_FOV0: + /* Check CAN_RFF0_FFOVR0 bit */ + itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0); + break; + case CAN_INT_FMP1: + /* Check CAN_RFF1_FFMP1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1); + break; + case CAN_INT_FF1: + /* Check CAN_RFF1_FFULL1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1); + break; + case CAN_INT_FOV1: + /* Check CAN_RFF1_FFOVR1 bit */ + itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1); + break; + case CAN_INT_WKU: + /* Check CAN_MSTS_WKUINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT); + break; + case CAN_INT_SLK: + /* Check CAN_MSTS_SLAKINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT); + break; + case CAN_INT_EWG: + /* Check CAN_ESTS_EWGFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL); + break; + case CAN_INT_EPV: + /* Check CAN_ESTS_EPVFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL); + break; + case CAN_INT_BOF: + /* Check CAN_ESTS_BOFFL bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL); + break; + case CAN_INT_LEC: + /* Check CAN_ESTS_LEC bit */ + itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC); + break; + case CAN_INT_ERR: + /* Check CAN_MSTS_ERRINT bit */ + itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT); + break; + default: + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_INT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CANx where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_INT specifies the interrupt pending bit to clear. + * - CAN_INT_TME + * - CAN_INT_FF0 + * - CAN_INT_FOV0 + * - CAN_INT_FF1 + * - CAN_INT_FOV1 + * - CAN_INT_WKU + * - CAN_INT_SLK + * - CAN_INT_EWG + * - CAN_INT_EPV + * - CAN_INT_BOF + * - CAN_INT_LEC + * - CAN_INT_ERR + */ +void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_INT(CAN_INT)); + + switch (CAN_INT) + { + case CAN_INT_TME: + /* Clear CAN_TSTS_RQCPx (rc_w1)*/ + CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2; + break; + case CAN_INT_FF0: + /* Clear CAN_RFF0_FFULL0 (rc_w1)*/ + CANx->RFF0 = CAN_RFF0_FFULL0; + break; + case CAN_INT_FOV0: + /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/ + CANx->RFF0 = CAN_RFF0_FFOVR0; + break; + case CAN_INT_FF1: + /* Clear CAN_RFF1_FFULL1 (rc_w1)*/ + CANx->RFF1 = CAN_RFF1_FFULL1; + break; + case CAN_INT_FOV1: + /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/ + CANx->RFF1 = CAN_RFF1_FFOVR1; + break; + case CAN_INT_WKU: + /* Clear CAN_MSTS_WKUINT (rc_w1)*/ + CANx->MSTS = CAN_MSTS_WKUINT; + break; + case CAN_INT_SLK: + /* Clear CAN_MSTS_SLAKINT (rc_w1)*/ + CANx->MSTS = CAN_MSTS_SLAKINT; + break; + case CAN_INT_EWG: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_EPV: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_BOF: + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_INT_LEC: + /* Clear LEC bits */ + CANx->ESTS = RESET; + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + break; + case CAN_INT_ERR: + /*Clear LEC bits */ + CANx->ESTS = RESET; + /* Clear CAN_MSTS_ERRINT (rc_w1) */ + CANx->MSTS = CAN_MSTS_ERRINT; + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending + of the CAN Bus status*/ + break; + default: + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg specifies the CAN interrupt register to check. + * @param Int_Bit specifies the interrupt source bit to check. + * @return The new state of the CAN Interrupt (SET or RESET). + */ +static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit) +{ + INTStatus pendingbitstatus = RESET; + + if ((CAN_Reg & Int_Bit) != (uint32_t)RESET) + { + /* CAN_INT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_INT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_comp.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_comp.c new file mode 100644 index 0000000000..87841d7db4 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_comp.c @@ -0,0 +1,294 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_comp.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_comp.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @brief COMP driver modules + * @{ + */ + +/** @addtogroup COMP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Functions + * @{ + */ +#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) +/** + * @brief Deinitializes the COMP peripheral registers to their default reset values. + */ +void COMP_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, DISABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, DISABLE); +} +void COMP_StructInit(COMP_InitType* COMP_InitStruct) +{ + COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit + + COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */ + + COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK + + COMP_InitStruct->PolRev = false; // out polarity reverse + + COMP_InitStruct->OutSel = COMPX_CTRL_OUTSEL_NC; + COMP_InitStruct->InpSel = COMPX_CTRL_INPSEL_RES; + COMP_InitStruct->InmSel = COMPX_CTRL_INMSEL_RES; + + COMP_InitStruct->En = false; +} +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct) +{ + COMP_SingleType* pCS = &COMP->Cmp[COMPx]; + __IO uint32_t tmp; + + // filter + tmp = pCS->FILC; + SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK); + SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK); + SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK); + pCS->FILC = tmp; + // filter psc + pCS->FILP = COMP_InitStruct->ClkPsc; + + // ctrl + tmp = pCS->CTRL; + if (COMPx == COMP1) + { + if (COMP_InitStruct->InpDacConnect) + SetBit(tmp, COMP1_CTRL_INPDAC_MASK); + else + ClrBit(tmp, COMP1_CTRL_INPDAC_MASK); + } + SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK); + SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK); + if (COMP_InitStruct->PolRev) + SetBit(tmp, COMP_POL_MASK); + else + ClrBit(tmp, COMP_POL_MASK); + SetBitMsk(tmp, COMP_InitStruct->OutSel, COMP_CTRL_OUTSEL_MASK); + SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK); + SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK); + if (COMP_InitStruct->En) + SetBit(tmp, COMP_CTRL_EN_MASK); + else + ClrBit(tmp, COMP_CTRL_EN_MASK); + pCS->CTRL = tmp; +} +void COMP_Enable(COMPX COMPx, FunctionalState en) +{ + if (en) + SetBit(COMP->Cmp[COMPx].CTRL, COMP_CTRL_EN_MASK); + else + ClrBit(COMP->Cmp[COMPx].CTRL, COMP_CTRL_EN_MASK); +} + +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel) +{ + __IO uint32_t tmp = COMP->Cmp[COMPx].CTRL; + SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK); + COMP->Cmp[COMPx].CTRL = tmp; +} +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel) +{ + __IO uint32_t tmp = COMP->Cmp[COMPx].CTRL; + SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK); + COMP->Cmp[COMPx].CTRL = tmp; +} +void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig) +{ + __IO uint32_t tmp = COMP->Cmp[COMPx].CTRL; + SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK); + COMP->Cmp[COMPx].CTRL = tmp; +} +// Lock see @COMP_LOCK +void COMP_SetLock(uint32_t Lock) +{ + COMP->LOCK = Lock; +} +// IntEn see @COMP_INTEN_CMPIEN +void COMP_SetIntEn(uint32_t IntEn) +{ + COMP->INTEN = IntEn; +} +// return see @COMP_INTSTS_CMPIS +uint32_t COMP_GetIntSts(void) +{ + return COMP->INTSTS; +} +// parma range see @COMP_VREFSCL +// Vv2Trim,Vv1Trim max 63 +void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En) +{ + __IO uint32_t tmp = 0; + + SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK); + SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK); + SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK); + SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK); + + COMP->VREFSCL = tmp; +} +// SET when comp out 1 +// RESET when comp out 0 +FlagStatus COMP_GetOutStatus(COMPX COMPx) +{ + return (COMP->Cmp[COMPx].CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET; +} +// get one comp interrupt flags +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx) +{ + return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET; +} + +/** + * @brief Set the COMP filter clock Prescaler value. + * @param COMPx where x can be 1 to 7 to select the COMP peripheral. + * @param FilPreVal Prescaler Value,Div clock = FilPreVal+1. + * @return void + */ +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal) +{ + COMP->Cmp[COMPx].FILP=FilPreVal; +} + +/** + * @brief Set the COMP filter control value. + * @param COMPx where x can be 1 to 7 to select the COMP peripheral. + * @param FilEn 1 for enable ,0 or disable + * @param TheresNum num under this value is noise + * @param SampPW total sample number in a window + * @return void + */ +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW) +{ + COMP->Cmp[COMPx].FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK); +} + +/** + * @brief Set the COMP Hyst value. + * @param COMPx where x can be 1 to 7 to select the COMP peripheral. + * @param HYST specifies the HYST level. + * This parameter can be one of the following values: +* @arg COMP_CTRL_HYST_NO Hyst disable +* @arg COMP_CTRL_HYST_LOW Hyst level 5.1mV +* @arg COMP_CTRL_HYST_MID Hyst level 15mV +* @arg COMP_CTRL_HYST_HIGH Hyst level 25mV + * @return void + */ +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST) +{ + uint32_t tmp=COMP->Cmp[COMPx].CTRL; + tmp&=~COMP_CTRL_HYST_HIGH; + tmp|=HYST; + COMP->Cmp[COMPx].CTRL=tmp; +} + +/** + * @brief Set the COMP Blanking source . + * @param COMPx where x can be 1 to 7 to select the COMP peripheral. + * @param BLK specifies the blanking source . + * This parameter can be one of the following values: +* @arg COMP_CTRL_BLKING_NO Blanking disable +* @arg COMP_CTRL_BLKING_TIM1_OC5 Blanking source TIM1_OC5 +* @arg COMP_CTRL_BLKING_TIM8_OC5 Blanking source TIM8_OC5 + * @return void + */ +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK) +{ + uint32_t tmp=COMP->Cmp[COMPx].CTRL; + tmp&=~(7<<14); + tmp|=BLK; + COMP->Cmp[COMPx].CTRL=tmp; +} + + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_crc.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_crc.c new file mode 100644 index 0000000000..e4a9200105 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_crc.c @@ -0,0 +1,228 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_crc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_crc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @addtogroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DAT). + */ +void CRC32_ResetCrc(void) +{ + /* Reset CRC generator */ + CRC->CRC32CTRL = CRC32_CTRL_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data data word(32-bit) to compute its CRC + * @return 32-bit CRC + */ +uint32_t CRC32_CalcCrc(uint32_t Data) +{ + CRC->CRC32DAT = Data; + + return (CRC->CRC32DAT); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer pointer to the buffer containing the data to be computed + * @param BufferLength length of the buffer to be computed + * @return 32-bit CRC + */ +uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for (index = 0; index < BufferLength; index++) + { + CRC->CRC32DAT = pBuffer[index]; + } + return (CRC->CRC32DAT); +} + +/** + * @brief Returns the current CRC value. + * @return 32-bit CRC + */ +uint32_t CRC32_GetCrc(void) +{ + return (CRC->CRC32DAT); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue 8-bit value to be stored in the ID register + */ +void CRC32_SetIDat(uint8_t IDValue) +{ + CRC->CRC32IDAT = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @return 8-bit value of the ID register + */ +uint8_t CRC32_GetIDat(void) +{ + return (CRC->CRC32IDAT); +} + +// CRC16 add +void __CRC16_SetLittleEndianFmt(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL; +} +void __CRC16_SetBigEndianFmt(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL; +} +void __CRC16_SetCleanEnable(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL; +} +void __CRC16_SetCleanDisable(void) +{ + CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL; +} + +uint16_t __CRC16_CalcCrc(uint8_t Data) +{ + CRC->CRC16DAT = Data; + return (CRC->CRC16D); +} + +void __CRC16_SetCrc(uint8_t Data) +{ + CRC->CRC16DAT = Data; +} + +uint16_t __CRC16_GetCrc(void) +{ + return (CRC->CRC16D); +} + +void __CRC16_SetLRC(uint8_t Data) +{ + CRC->LRC = Data; +} + +uint8_t __CRC16_GetLRC(void) +{ + return (CRC->LRC); +} + +uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + CRC->CRC16D = 0x00; + // CRC16_SetCleanEnable(); + for (index = 0; index < BufferLength; index++) + { + CRC->CRC16DAT = pBuffer[index]; + } + return (CRC->CRC16D); +} + +uint16_t CRC16_CalcCRC(uint8_t Data) +{ + CRC->CRC16DAT = Data; + + return (CRC->CRC16D); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dac.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dac.c new file mode 100644 index 0000000000..ce1b0635ed --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dac.c @@ -0,0 +1,425 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_dac.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_dac.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @addtogroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Defines + * @{ + */ + +/* CTRL register Mask */ +#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DCH registers offsets */ +#define DR12CH1_OFFSET ((uint32_t)0x00000008) +#define DR12CH2_OFFSET ((uint32_t)0x00000014) +#define DR12DCH_OFFSET ((uint32_t)0x00000020) + +/* DATO register offset */ +#define DATO1_OFFSET ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @addtogroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param DAC_InitStruct pointer to a DAC_InitType structure that + * contains the configuration information for the specified DAC channel. + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput)); + /*---------------------------- DAC CTRL Configuration --------------------------*/ + /* Get the DAC CTRL value */ + tmpreg1 = DAC->CTRL; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CTRL_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave generation, + mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to Trigger value */ + /* Set WAVEx bits according to WaveGen value */ + /* Set MAMPx bits according to LfsrUnMaskTriAmp value */ + /* Set BOFFx bit according to BufferOutput value */ + tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp + | DAC_InitStruct->BufferOutput); + /* Calculate CTRL register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CTRL */ + DAC->CTRL = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct pointer to a DAC_InitType structure which will + * be initialized. + */ +void DAC_ClearStruct(DAC_InitType* DAC_InitStruct) +{ + /*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the Trigger member */ + DAC_InitStruct->Trigger = DAC_TRG_NONE; + /* Initialize the WaveGen member */ + DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE; + /* Initialize the LfsrUnMaskTriAmp member */ + DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0; + /* Initialize the BufferOutput member */ + DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_Enable(uint32_t DAC_Channel, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CTRL |= (DAC_CTRL_CH1EN << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CTRL &= ~(DAC_CTRL_CH1EN << DAC_Channel); + } +} + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_DmaEnable(uint32_t DAC_Channel, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CTRL |= (DAC_CTRL_DMA1EN << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CTRL &= ~(DAC_CTRL_DMA1EN << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param Cmd new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_SoftTrgEnable(uint32_t DAC_Channel, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SOTTR |= (uint32_t)DAC_SOTTR_TR1EN << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SOTTR &= ~((uint32_t)DAC_SOTTR_TR1EN << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param Cmd new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_DualSoftwareTrgEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SOTTR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SOTTR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @param DAC_Wave Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_WAVE_NOISE noise wave generation + * @arg DAC_WAVE_TRIANGLE triangle wave generation + * @param Cmd new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + */ +void DAC_WaveGenerationEnable(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState Cmd) +{ + /* Check the parameters */ + __IO uint32_t tmp = 0; + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + tmp=DAC->CTRL; + tmp&=~(3<<(DAC_Channel+6)); + if (Cmd != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + tmp |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + tmp &=~(3<<(DAC_Channel+6)); + } + DAC->CTRL = tmp; +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected + * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected + * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected + * @param Data Data to be loaded in the selected data holding register. + */ +void DAC_SetCh1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DR12CH1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t*)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align Specifies the data alignment for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected + * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected + * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected + * @param Data Data to be loaded in the selected data holding register. + */ +void DAC_SetCh2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DR12CH2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t*)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected + * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected + * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected + * @param Data2 Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1 Data for DAC Channel1 to be loaded in the selected data + * holding register. + */ +void DAC_SetDualChData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_ALIGN_R_8BIT) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DR12DCH_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t*)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 DAC Channel1 selected + * @arg DAC_CHANNEL_2 DAC Channel2 selected + * @return The selected DAC channel data output value. + */ +uint16_t DAC_GetOutputDataVal(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t)DAC_BASE; + tmp += DATO1_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t)(*(__IO uint32_t*)tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dbg.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dbg.c new file mode 100644 index 0000000000..3d660375ea --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dbg.c @@ -0,0 +1,263 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_dbg.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_dbg.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBG + * @brief DBG driver modules + * @{ + */ + +/** @addtogroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the UCID. + * @return UCID + */ + +void GetUCID(uint8_t *UCIDbuf) +{ + uint8_t num = 0; + uint32_t* ucid_addr = (void*)0; + uint32_t temp = 0; + + if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF260)) + { + ucid_addr = (uint32_t*)UCID_BASE; + } + else + { + ucid_addr = (uint32_t*)(0x1FFFF260); + } + + for (num = 0; num < UCID_LENGTH;) + { + temp = *(__IO uint32_t*)(ucid_addr++); + UCIDbuf[num++] = (temp & 0xFF); + UCIDbuf[num++] = (temp & 0xFF00) >> 8; + UCIDbuf[num++] = (temp & 0xFF0000) >> 16; + UCIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the UID. + * @return UID + */ + +void GetUID(uint8_t *UIDbuf) +{ + uint8_t num = 0; + uint32_t* uid_addr = (void*)0; + uint32_t temp = 0; + + if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF270)) + { + uid_addr = (uint32_t*)UID_BASE; + } + else + { + uid_addr = (uint32_t*)(0x1FFFF270); + } + + for (num = 0; num < UID_LENGTH;) + { + temp = *(__IO uint32_t*)(uid_addr++); + UIDbuf[num++] = (temp & 0xFF); + UIDbuf[num++] = (temp & 0xFF00) >> 8; + UIDbuf[num++] = (temp & 0xFF0000) >> 16; + UIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the DBGMCU_ID. + * @return DBGMCU_ID + */ + +void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf) +{ + uint8_t num = 0; + uint32_t* dbgid_addr = (void*)0; + uint32_t temp = 0; + + dbgid_addr = (uint32_t*)DBGMCU_ID_BASE; + for (num = 0; num < DBGMCU_ID_LENGTH;) + { + temp = *(__IO uint32_t*)(dbgid_addr++); + DBGMCU_IDbuf[num++] = (temp & 0xFF); + DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8; + DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16; + DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** + * @brief Returns the device revision number. + * @return Device revision identifier + */ +uint32_t DBG_GetRevNum(void) +{ + return (DBG->ID & 0x00FF); +} + +/** + * @brief Returns the device identifier. + * @return Device identifier + */ +uint32_t DBG_GetDevNum(void) +{ + uint32_t id = DBG->ID; + return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBG_Periph specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBG_SLEEP Keep debugger connection during SLEEP mode + * @arg DBG_STOP Keep debugger connection during STOP mode + * @arg DBG_STDBY Keep debugger connection during STANDBY mode + * @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted + * @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted + * @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted + * @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted + * @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted + * @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted + * @arg DBG_CAN1_STOP Debug CAN2 stopped when Core is halted + * @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted + * @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted + * @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted + * @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted + * @arg DBG_CAN2_STOP Debug CAN2 stopped when Core is halted + * @param Cmd new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + */ +void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBG_Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + DBG->CTRL |= DBG_Periph; + } + else + { + DBG->CTRL &= ~DBG_Periph; + } +} + +/** + * @brief Get FLASH size of this chip. + * + * @return FLASH size in bytes. + */ +uint32_t DBG_GetFlashSize(void) +{ + return (DBG->ID & 0x000F0000); +} + +/** + * @brief Get SRAM size of this chip. + * + * @return SRAM size in bytes. + */ +uint32_t DBG_GetSramSize(void) +{ + return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dma.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dma.c new file mode 100644 index 0000000000..a4bf607049 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dma.c @@ -0,0 +1,888 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_dma.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_dma.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @addtogroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @addtogroup DMA_Private_Defines + * @{ + */ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1)) +#define DMA1_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2)) +#define DMA1_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3)) +#define DMA1_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4)) +#define DMA1_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5)) +#define DMA1_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6)) +#define DMA1_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7)) +#define DMA1_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1)) +#define DMA2_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2)) +#define DMA2_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3)) +#define DMA2_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4)) +#define DMA2_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5)) +#define DMA2_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6)) +#define DMA2_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7)) +#define DMA2_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8)) + +/* DMA CHCFGx registers Masks, MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @addtogroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + */ +void DMA_DeInit(DMA_ChannelType* DMAyChx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAyChx)); + + /* Disable the selected DMAy Channelx */ + DMAyChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN); + + /* Reset DMAy Channelx control register */ + DMAyChx->CHCFG = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAyChx->TXNUM = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAyChx->PADDR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAyChx->MADDR = 0; + + if (DMAyChx == DMA1_CH1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->INTCLR |= DMA1_CH1_INT_MASK; + } + else if (DMAyChx == DMA1_CH2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->INTCLR |= DMA1_CH2_INT_MASK; + } + else if (DMAyChx == DMA1_CH3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->INTCLR |= DMA1_CH3_INT_MASK; + } + else if (DMAyChx == DMA1_CH4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->INTCLR |= DMA1_CH4_INT_MASK; + } + else if (DMAyChx == DMA1_CH5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->INTCLR |= DMA1_CH5_INT_MASK; + } + else if (DMAyChx == DMA1_CH6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->INTCLR |= DMA1_CH6_INT_MASK; + } + else if (DMAyChx == DMA1_CH7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->INTCLR |= DMA1_CH7_INT_MASK; + } + else if (DMAyChx == DMA1_CH8) + { + /* Reset interrupt pending bits for DMA1 Channel8 */ + DMA1->INTCLR |= DMA1_CH8_INT_MASK; + } + else if (DMAyChx == DMA2_CH1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->INTCLR |= DMA2_CH1_INT_MASK; + } + else if (DMAyChx == DMA2_CH2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->INTCLR |= DMA2_CH2_INT_MASK; + } + else if (DMAyChx == DMA2_CH3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->INTCLR |= DMA2_CH3_INT_MASK; + } + else if (DMAyChx == DMA2_CH4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->INTCLR |= DMA2_CH4_INT_MASK; + } + else if (DMAyChx == DMA2_CH5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->INTCLR |= DMA2_CH5_INT_MASK; + } + else if (DMAyChx == DMA2_CH6) + { + /* Reset interrupt pending bits for DMA2 Channel6 */ + DMA2->INTCLR |= DMA2_CH6_INT_MASK; + } + else if (DMAyChx == DMA2_CH7) + { + /* Reset interrupt pending bits for DMA2 Channel7 */ + DMA2->INTCLR |= DMA2_CH7_INT_MASK; + } + else + { + if (DMAyChx == DMA2_CH8) + { + /* Reset interrupt pending bits for DMA2 Channel8 */ + DMA2->INTCLR |= DMA2_CH8_INT_MASK; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitParam. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + * @param DMA_InitParam pointer to a DMA_InitType structure that + * contains the configuration information for the specified DMA Channel. + */ +void DMA_Init(DMA_ChannelType* DMAyChx, DMA_InitType* DMA_InitParam) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAyChx)); + assert_param(IS_DMA_DIR(DMA_InitParam->Direction)); + assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize)); + assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc)); + assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize)); + assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode)); + assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem)); + + /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/ + /* Get the DMAyChx CHCFG value */ + tmpregister = DMAyChx->CHCFG; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpregister &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to Direction value */ + /* Set CIRC bit according to CircularMode value */ + /* Set PINC bit according to PeriphInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to PeriphDataSize value */ + /* Set MSIZE bits according to MemDataSize value */ + /* Set PL bits according to Priority value */ + /* Set the MEM2MEM bit according to Mem2Mem value */ + tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc + | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize + | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem; + + /* Write to DMAy Channelx CHCFG */ + DMAyChx->CHCFG = tmpregister; + + /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/ + /* Write to DMAy Channelx TXNUM */ + DMAyChx->TXNUM = DMA_InitParam->BufSize; + + /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/ + /* Write to DMAy Channelx PADDR */ + DMAyChx->PADDR = DMA_InitParam->PeriphAddr; + + /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/ + /* Write to DMAy Channelx MADDR */ + DMAyChx->MADDR = DMA_InitParam->MemAddr; +} + +/** + * @brief Fills each DMA_InitParam member with its default value. + * @param DMA_InitParam pointer to a DMA_InitType structure which will + * be initialized. + */ +void DMA_StructInit(DMA_InitType* DMA_InitParam) +{ + /*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the PeriphAddr member */ + DMA_InitParam->PeriphAddr = 0; + /* Initialize the MemAddr member */ + DMA_InitParam->MemAddr = 0; + /* Initialize the Direction member */ + DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC; + /* Initialize the BufSize member */ + DMA_InitParam->BufSize = 0; + /* Initialize the PeriphInc member */ + DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE; + /* Initialize the DMA_MemoryInc member */ + DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE; + /* Initialize the PeriphDataSize member */ + DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + /* Initialize the MemDataSize member */ + DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the CircularMode member */ + DMA_InitParam->CircularMode = DMA_MODE_NORMAL; + /* Initialize the Priority member */ + DMA_InitParam->Priority = DMA_PRIORITY_LOW; + /* Initialize the Mem2Mem member */ + DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + * @param Cmd new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_EnableChannel(DMA_ChannelType* DMAyChx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAyChx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAyChx->CHCFG |= DMA_CHCFG1_CHEN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAyChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + * @param DMAInt specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_INT_TXC Transfer complete interrupt mask + * @arg DMA_INT_HTX Half transfer interrupt mask + * @arg DMA_INT_ERR Transfer error interrupt mask + * @param Cmd new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_ConfigInt(DMA_ChannelType* DMAyChx, uint32_t DMAInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAyChx)); + assert_param(IS_DMA_CONFIG_INT(DMAInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAyChx->CHCFG |= DMAInt; + } + else + { + /* Disable the selected DMA interrupts */ + DMAyChx->CHCFG &= ~DMAInt; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + * @param DataNumber The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAyChx is disabled. + */ +void DMA_SetCurrDataCounter(DMA_ChannelType* DMAyChx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAyChx)); + + /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/ + /* Write to DMAy Channelx TXNUM */ + DMAyChx->TXNUM = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + * @return The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAyChx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAyChx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAyChx->TXNUM)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMAyFlag specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1 DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1 DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1 DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1 DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2 DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2 DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2 DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2 DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3 DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3 DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3 DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3 DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4 DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4 DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4 DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4 DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5 DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5 DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5 DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5 DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6 DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6 DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6 DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6 DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7 DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7 DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7 DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7 DMA1 Channel7 transfer error flag. + * @arg DMA1_FLAG_GL8 DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC8 DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT8 DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE8 DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1 DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1 DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1 DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1 DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2 DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2 DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2 DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2 DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3 DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3 DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3 DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3 DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4 DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4 DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4 DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4 DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5 DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5 DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5 DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5 DMA2 Channel5 transfer error flag. + * @arg DMA2_FLAG_GL6 DMA1 Channel6 global flag. + * @arg DMA2_FLAG_TC6 DMA1 Channel6 transfer complete flag. + * @arg DMA2_FLAG_HT6 DMA1 Channel6 half transfer flag. + * @arg DMA2_FLAG_TE6 DMA1 Channel6 transfer error flag. + * @arg DMA2_FLAG_GL7 DMA1 Channel7 global flag. + * @arg DMA2_FLAG_TC7 DMA1 Channel7 transfer complete flag. + * @arg DMA2_FLAG_HT7 DMA1 Channel7 half transfer flag. + * @arg DMA2_FLAG_TE7 DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL8 DMA1 Channel7 global flag. + * @arg DMA2_FLAG_TC8 DMA1 Channel7 transfer complete flag. + * @arg DMA2_FLAG_HT8 DMA1 Channel7 half transfer flag. + * @arg DMA2_FLAG_TE8 DMA1 Channel7 transfer error flag. + * @param DMAy DMA1 or DMA2. + * This parameter can be one of the following values: + * @arg DMA1 . + * @arg DMA2 . + * @return The new state of DMAyFlag (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAyFlag, DMA_Module* DMAy) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAyFlag)); + + /* Calculate the used DMAy */ + /* Get DMAy INTSTS register value */ + tmpregister = DMAy->INTSTS; + + /* Check the status of the specified DMAy flag */ + if ((tmpregister & DMAyFlag) != (uint32_t)RESET) + { + /* DMAyFlag is set */ + bitstatus = SET; + } + else + { + /* DMAyFlag is reset */ + bitstatus = RESET; + } + + /* Return the DMAyFlag status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMAyFlag specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1 DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1 DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1 DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1 DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2 DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2 DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2 DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2 DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3 DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3 DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3 DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3 DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4 DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4 DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4 DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4 DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5 DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5 DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5 DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5 DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6 DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6 DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6 DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6 DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7 DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7 DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7 DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7 DMA1 Channel7 transfer error flag. + * @arg DMA1_FLAG_GL8 DMA1 Channel8 global flag. + * @arg DMA1_FLAG_TC8 DMA1 Channel8 transfer complete flag. + * @arg DMA1_FLAG_HT8 DMA1 Channel8 half transfer flag. + * @arg DMA1_FLAG_TE8 DMA1 Channel8 transfer error flag. + * @arg DMA2_FLAG_GL1 DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1 DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1 DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1 DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2 DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2 DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2 DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2 DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3 DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3 DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3 DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3 DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4 DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4 DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4 DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4 DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5 DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5 DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5 DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5 DMA2 Channel5 transfer error flag. + * @arg DMA2_FLAG_GL6 DMA2 Channel6 global flag. + * @arg DMA2_FLAG_TC6 DMA2 Channel6 transfer complete flag. + * @arg DMA2_FLAG_HT6 DMA2 Channel6 half transfer flag. + * @arg DMA2_FLAG_TE6 DMA2 Channel6 transfer error flag. + * @arg DMA2_FLAG_GL7 DMA2 Channel7 global flag. + * @arg DMA2_FLAG_TC7 DMA2 Channel7 transfer complete flag. + * @arg DMA2_FLAG_HT7 DMA2 Channel7 half transfer flag. + * @arg DMA2_FLAG_TE7 DMA2 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL8 DMA2 Channel8 global flag. + * @arg DMA2_FLAG_TC8 DMA2 Channel8 transfer complete flag. + * @arg DMA2_FLAG_HT8 DMA2 Channel8 half transfer flag. + * @arg DMA2_FLAG_TE8 DMA2 Channel8 transfer error flag. + * @param DMAy DMA1 or DMA2. + * This parameter can be one of the following values: + * @arg DMA1 . + * @arg DMA2 . + */ +void DMA_ClearFlag(uint32_t DMAyFlag, DMA_Module* DMAy) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAyFlag)); + + /* Calculate the used DMAy */ + /* Clear the selected DMAy flags */ + DMAy->INTCLR = DMAyFlag; +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMAy_IT specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_INT_GLB1 DMA1 Channel1 global interrupt. + * @arg DMA1_INT_TXC1 DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_INT_HTX1 DMA1 Channel1 half transfer interrupt. + * @arg DMA1_INT_ERR1 DMA1 Channel1 transfer error interrupt. + * @arg DMA1_INT_GLB2 DMA1 Channel2 global interrupt. + * @arg DMA1_INT_TXC2 DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_INT_HTX2 DMA1 Channel2 half transfer interrupt. + * @arg DMA1_INT_ERR2 DMA1 Channel2 transfer error interrupt. + * @arg DMA1_INT_GLB3 DMA1 Channel3 global interrupt. + * @arg DMA1_INT_TXC3 DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_INT_HTX3 DMA1 Channel3 half transfer interrupt. + * @arg DMA1_INT_ERR3 DMA1 Channel3 transfer error interrupt. + * @arg DMA1_INT_GLB4 DMA1 Channel4 global interrupt. + * @arg DMA1_INT_TXC4 DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_INT_HTX4 DMA1 Channel4 half transfer interrupt. + * @arg DMA1_INT_ERR4 DMA1 Channel4 transfer error interrupt. + * @arg DMA1_INT_GLB5 DMA1 Channel5 global interrupt. + * @arg DMA1_INT_TXC5 DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_INT_HTX5 DMA1 Channel5 half transfer interrupt. + * @arg DMA1_INT_ERR5 DMA1 Channel5 transfer error interrupt. + * @arg DMA1_INT_GLB6 DMA1 Channel6 global interrupt. + * @arg DMA1_INT_TXC6 DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_INT_HTX6 DMA1 Channel6 half transfer interrupt. + * @arg DMA1_INT_ERR6 DMA1 Channel6 transfer error interrupt. + * @arg DMA1_INT_GLB7 DMA1 Channel7 global interrupt. + * @arg DMA1_INT_TXC7 DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_INT_HTX7 DMA1 Channel7 half transfer interrupt. + * @arg DMA1_INT_ERR7 DMA1 Channel7 transfer error interrupt. + * @arg DMA1_INT_GLB8 DMA1 Channel8 global interrupt. + * @arg DMA1_INT_TXC8 DMA1 Channel8 transfer complete interrupt. + * @arg DMA1_INT_HTX8 DMA1 Channel8 half transfer interrupt. + * @arg DMA1_INT_ERR8 DMA1 Channel8 transfer error interrupt. + * @arg DMA2_INT_GLB1 DMA2 Channel1 global interrupt. + * @arg DMA2_INT_TXC1 DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_INT_HTX1 DMA2 Channel1 half transfer interrupt. + * @arg DMA2_INT_ERR1 DMA2 Channel1 transfer error interrupt. + * @arg DMA2_INT_GLB2 DMA2 Channel2 global interrupt. + * @arg DMA2_INT_TXC2 DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_INT_HTX2 DMA2 Channel2 half transfer interrupt. + * @arg DMA2_INT_ERR2 DMA2 Channel2 transfer error interrupt. + * @arg DMA2_INT_GLB3 DMA2 Channel3 global interrupt. + * @arg DMA2_INT_TXC3 DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_INT_HTX3 DMA2 Channel3 half transfer interrupt. + * @arg DMA2_INT_ERR3 DMA2 Channel3 transfer error interrupt. + * @arg DMA2_INT_GLB4 DMA2 Channel4 global interrupt. + * @arg DMA2_INT_TXC4 DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_INT_HTX4 DMA2 Channel4 half transfer interrupt. + * @arg DMA2_INT_ERR4 DMA2 Channel4 transfer error interrupt. + * @arg DMA2_INT_GLB5 DMA2 Channel5 global interrupt. + * @arg DMA2_INT_TXC5 DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_INT_HTX5 DMA2 Channel5 half transfer interrupt. + * @arg DMA2_INT_ERR5 DMA2 Channel5 transfer error interrupt. + * @arg DMA2_INT_GLB6 DMA2 Channel6 global interrupt. + * @arg DMA2_INT_TXC6 DMA2 Channel6 transfer complete interrupt. + * @arg DMA2_INT_HTX6 DMA2 Channel6 half transfer interrupt. + * @arg DMA2_INT_ERR6 DMA2 Channel6 transfer error interrupt. + * @arg DMA2_INT_GLB7 DMA2 Channel7 global interrupt. + * @arg DMA2_INT_TXC7 DMA2 Channel7 transfer complete interrupt. + * @arg DMA2_INT_HTX7 DMA2 Channel7 half transfer interrupt. + * @arg DMA2_INT_ERR7 DMA2 Channel7 transfer error interrupt. + * @arg DMA2_INT_GLB8 DMA2 Channel8 global interrupt. + * @arg DMA2_INT_TXC8 DMA2 Channel8 transfer complete interrupt. + * @arg DMA2_INT_HTX8 DMA2 Channel8 half transfer interrupt. + * @arg DMA2_INT_ERR8 DMA2 Channel8 transfer error interrupt. + * @param DMAy DMA1 or DMA2. + * This parameter can be one of the following values: + * @arg DMA1 . + * @arg DMA2 . + * @return The new state of DMAy_IT (SET or RESET). + */ +INTStatus DMA_GetIntStatus(uint32_t DMAy_IT, DMA_Module* DMAy) +{ + INTStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMAy_IT)); + + /* Calculate the used DMA */ + /* Get DMAy INTSTS register value */ + tmpregister = DMAy->INTSTS; + + /* Check the status of the specified DMAy interrupt */ + if ((tmpregister & DMAy_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMAInt status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's interrupt pending bits. + * @param DMAy_IT specifies the DMAy interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_INT_GLB1 DMA1 Channel1 global interrupt. + * @arg DMA1_INT_TXC1 DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_INT_HTX1 DMA1 Channel1 half transfer interrupt. + * @arg DMA1_INT_ERR1 DMA1 Channel1 transfer error interrupt. + * @arg DMA1_INT_GLB2 DMA1 Channel2 global interrupt. + * @arg DMA1_INT_TXC2 DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_INT_HTX2 DMA1 Channel2 half transfer interrupt. + * @arg DMA1_INT_ERR2 DMA1 Channel2 transfer error interrupt. + * @arg DMA1_INT_GLB3 DMA1 Channel3 global interrupt. + * @arg DMA1_INT_TXC3 DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_INT_HTX3 DMA1 Channel3 half transfer interrupt. + * @arg DMA1_INT_ERR3 DMA1 Channel3 transfer error interrupt. + * @arg DMA1_INT_GLB4 DMA1 Channel4 global interrupt. + * @arg DMA1_INT_TXC4 DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_INT_HTX4 DMA1 Channel4 half transfer interrupt. + * @arg DMA1_INT_ERR4 DMA1 Channel4 transfer error interrupt. + * @arg DMA1_INT_GLB5 DMA1 Channel5 global interrupt. + * @arg DMA1_INT_TXC5 DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_INT_HTX5 DMA1 Channel5 half transfer interrupt. + * @arg DMA1_INT_ERR5 DMA1 Channel5 transfer error interrupt. + * @arg DMA1_INT_GLB6 DMA1 Channel6 global interrupt. + * @arg DMA1_INT_TXC6 DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_INT_HTX6 DMA1 Channel6 half transfer interrupt. + * @arg DMA1_INT_ERR6 DMA1 Channel6 transfer error interrupt. + * @arg DMA1_INT_GLB7 DMA1 Channel7 global interrupt. + * @arg DMA1_INT_TXC7 DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_INT_HTX7 DMA1 Channel7 half transfer interrupt. + * @arg DMA1_INT_ERR7 DMA1 Channel7 transfer error interrupt. + * @arg DMA1_INT_GLB8 DMA1 Channel8 global interrupt. + * @arg DMA1_INT_TXC8 DMA1 Channel8 transfer complete interrupt. + * @arg DMA1_INT_HTX8 DMA1 Channel8 half transfer interrupt. + * @arg DMA1_INT_ERR8 DMA1 Channel8 transfer error interrupt. + * @arg DMA2_INT_GLB1 DMA2 Channel1 global interrupt. + * @arg DMA2_INT_TXC1 DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_INT_HTX1 DMA2 Channel1 half transfer interrupt. + * @arg DMA2_INT_ERR1 DMA2 Channel1 transfer error interrupt. + * @arg DMA2_INT_GLB2 DMA2 Channel2 global interrupt. + * @arg DMA2_INT_TXC2 DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_INT_HTX2 DMA2 Channel2 half transfer interrupt. + * @arg DMA2_INT_ERR2 DMA2 Channel2 transfer error interrupt. + * @arg DMA2_INT_GLB3 DMA2 Channel3 global interrupt. + * @arg DMA2_INT_TXC3 DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_INT_HTX3 DMA2 Channel3 half transfer interrupt. + * @arg DMA2_INT_ERR3 DMA2 Channel3 transfer error interrupt. + * @arg DMA2_INT_GLB4 DMA2 Channel4 global interrupt. + * @arg DMA2_INT_TXC4 DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_INT_HTX4 DMA2 Channel4 half transfer interrupt. + * @arg DMA2_INT_ERR4 DMA2 Channel4 transfer error interrupt. + * @arg DMA2_INT_GLB5 DMA2 Channel5 global interrupt. + * @arg DMA2_INT_TXC5 DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_INT_HTX5 DMA2 Channel5 half transfer interrupt. + * @arg DMA2_INT_ERR5 DMA2 Channel5 transfer error interrupt. + * @arg DMA2_INT_GLB6 DMA2 Channel6 global interrupt. + * @arg DMA2_INT_TXC6 DMA2 Channel6 transfer complete interrupt. + * @arg DMA2_INT_HTX6 DMA2 Channel6 half transfer interrupt. + * @arg DMA2_INT_ERR6 DMA2 Channel6 transfer error interrupt. + * @arg DMA2_INT_GLB7 DMA2 Channel7 global interrupt. + * @arg DMA2_INT_TXC7 DMA2 Channel7 transfer complete interrupt. + * @arg DMA2_INT_HTX7 DMA2 Channel7 half transfer interrupt. + * @arg DMA2_INT_ERR7 DMA2 Channel7 transfer error interrupt. + * @arg DMA2_INT_GLB8 DMA2 Channel8 global interrupt. + * @arg DMA2_INT_TXC8 DMA2 Channel8 transfer complete interrupt. + * @arg DMA2_INT_HTX8 DMA2 Channel8 half transfer interrupt. + * @arg DMA2_INT_ERR8 DMA2 Channel8 transfer error interrupt. + * @param DMAy DMA1 or DMA2. + * This parameter can be one of the following values: + * @arg DMA1 . + * @arg DMA2 . + */ +void DMA_ClrIntPendingBit(uint32_t DMAy_IT, DMA_Module* DMAy) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLR_INT(DMAy_IT)); + + /* Calculate the used DMAy */ + /* Clear the selected DMAy interrupt pending bits */ + DMAy->INTCLR = DMAy_IT; +} + +/** + * @brief Set the DMAy Channelx's remap request. + * @param DMAy_REMAP specifies the DMAy request. + * This parameter can be set by the following values: + * @arg DMA1_REMAP_ADC1 DMA1 Request For ADC1. + * @arg DMA1_REMAP_UART5_TX DMA1 Request For UART5_TX. + * @arg DMA1_REMAP_I2C3_TX DMA1 Request For I2C3_TX. + * @arg DMA1_REMAP_TIM2_CH3 DMA1 Request For TIM2_CH3. + * @arg DMA1_REMAP_TIM4_CH1 DMA1 Request For TIM4_CH1. + * @arg DMA1_REMAP_USART3_TX DMA1 Request For USART3_TX. + * @arg DMA1_REMAP_I2C3_RX DMA1 Request For I2C3_RX. + * @arg DMA1_REMAP_TIM1_CH1 DMA1 Request For TIM1_CH1. + * @arg DMA1_REMAP_TIM2_UP DMA1 Request For TIM2_UP. + * @arg DMA1_REMAP_TIM3_CH3 DMA1 Request For TIM3_CH3. + * @arg DMA1_REMAP_SPI1_RX DMA1 Request For SPI1_RX. + * @arg DMA1_REMAP_USART3_RX DMA1 Request For USART3_RX. + * @arg DMA1_REMAP_TIM1_CH2 DMA1 Request For TIM1_CH2. + * @arg DMA1_REMAP_TIM3_CH4 DMA1 Request For TIM3_CH4. + * @arg DMA1_REMAP_TIM3_UP DMA1 Request For TIM3_UP. + * @arg DMA1_REMAP_SPI1_TX DMA1 Request For SPI1_TX. + * @arg DMA1_REMAP_USART1_TX DMA1 Request For USART1_TX. + * @arg DMA1_REMAP_TIM1_CH4 DMA1 Request For TIM1_CH4. + * @arg DMA1_REMAP_TIM1_TRIG DMA1 Request For TIM1_TRIG. + * @arg DMA1_REMAP_TIM1_COM DMA1 Request For TIM1_COM. + * @arg DMA1_REMAP_TIM4_CH2 DMA1 Request For TIM4_CH2. + * @arg DMA1_REMAP_SPI_I2S2_RX DMA1 Request For SPI_I2S2_RX. + * @arg DMA1_REMAP_I2C2_TX DMA1 Request For I2C2_TX. + * @arg DMA1_REMAP_USART1_RX DMA1 Request For USART1_RX. + * @arg DMA1_REMAP_TIM1_UP DMA1 Request For TIM1_UP. + * @arg DMA1_REMAP_SPI_I2S2_TX DMA1 Request For SPI_I2S2_TX. + * @arg DMA1_REMAP_TIM4_CH3 DMA1 Request For TIM4_CH3. + * @arg DMA1_REMAP_I2C2_RX DMA1 Request For I2C2_RX. + * @arg DMA1_REMAP_TIM2_CH1 DMA1 Request For TIM2_CH1. + * @arg DMA1_REMAP_USART2_RX DMA1 Request For USART2_RX. + * @arg DMA1_REMAP_TIM1_CH3 DMA1 Request For TIM1_CH3. + * @arg DMA1_REMAP_TIM3_CH1 DMA1 Request For TIM3_CH1. + * @arg DMA1_REMAP_TIM3_TRIG DMA1 Request For TIM3_TRIG. + * @arg DMA1_REMAP_I2C1_TX DMA1 Request For I2C1_TX. + * @arg DMA1_REMAP_USART2_TX DMA1 Request For USART2_TX. + * @arg DMA1_REMAP_TIM2_CH2 DMA1 Request For TIM2_CH2. + * @arg DMA1_REMAP_TIM2_CH4 DMA1 Request For TIM2_CH4. + * @arg DMA1_REMAP_TIM4_UP DMA1 Request For TIM4_UP. + * @arg DMA1_REMAP_I2C1_RX DMA1 Request For I2C1_RX. + * @arg DMA1_REMAP_ADC2 DMA1 Request For ADC2. + * @arg DMA1_REMAP_UART5_RX DMA1 Request For UART5_RX. + * @arg DMA2_REMAP_TIM5_CH4 DMA2 Request For TIM5_CH4. + * @arg DMA2_REMAP_TIM5_TRIG DMA2 Request For TIM5_TRIG. + * @arg DMA2_REMAP_TIM8_CH3 DMA2 Request For TIM8_CH3. + * @arg DMA2_REMAP_TIM8_UP DMA2 Request For TIM8_UP. + * @arg DMA2_REMAP_SPI_I2S3_RX DMA2 Request For SPI_I2S3_RX. + * @arg DMA2_REMAP_UART6_RX DMA2 Request For UART6_RX. + * @arg DMA2_REMAP_TIM8_CH4 DMA2 Request For TIM8_CH4. + * @arg DMA2_REMAP_TIM8_TRIG DMA2 Request For TIM8_TRIG. + * @arg DMA2_REMAP_TIM8_COM DMA2 Request For TIM8_COM. + * @arg DMA2_REMAP_TIM5_CH3 DMA2 Request For TIM5_CH3. + * @arg DMA2_REMAP_TIM5_UP DMA2 Request For TIM5_UP. + * @arg DMA2_REMAP_SPI_I2S3_TX DMA2 Request For SPI_I2S3_TX. + * @arg DMA2_REMAP_UART6_TX DMA2 Request For UART6_TX. + * @arg DMA2_REMAP_TIM8_CH1 DMA2 Request For TIM8_CH1. + * @arg DMA2_REMAP_UART4_RX DMA2 Request For UART4_RX. + * @arg DMA2_REMAP_TIM6_UP DMA2 Request For TIM6_UP. + * @arg DMA2_REMAP_DAC1 DMA2 Request For DAC1. + * @arg DMA2_REMAP_TIM5_CH2 DMA2 Request For TIM5_CH2. + * @arg DMA2_REMAP_SDIO DMA2 Request For SDIO. + * @arg DMA2_REMAP_TIM7_UP DMA2 Request For TIM7_UP. + * @arg DMA2_REMAP_DAC2 DMA2 Request For DAC2. + * @arg DMA2_REMAP_ADC3 DMA2 Request For ADC3. + * @arg DMA2_REMAP_TIM8_CH2 DMA2 Request For TIM8_CH2. + * @arg DMA2_REMAP_TIM5_CH1 DMA2 Request For TIM5_CH1. + * @arg DMA2_REMAP_UART4_TX DMA2 Request For UART4_TX. + * @arg DMA2_REMAP_QSPI_RX DMA2 Request For QSPI_RX. + * @arg DMA2_REMAP_I2C4_TX DMA2 Request For I2C4_TX. + * @arg DMA2_REMAP_UART7_RX DMA2 Request For UART7_RX. + * @arg DMA2_REMAP_QSPI_TX DMA2 Request For QSPI_TX. + * @arg DMA2_REMAP_I2C4_RX DMA2 Request For I2C4_RX. + * @arg DMA2_REMAP_UART7_TX DMA2 Request For UART7_TX. + * @arg DMA2_REMAP_ADC4 DMA2 Request For ADC4. + * @arg DMA2_REMAP_DVP DMA2 Request For DVP. + * @param DMAy DMA1 or DMA2. + * This parameter can be one of the following values: + * @arg DMA1 . + * @arg DMA2 . + * @param DMAyChx where y can be 1 or 2 to select the DMA and + * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel. + * @param Cmd new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + */ +void DMA_RequestRemap(uint32_t DMAy_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAyChx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_DMA_REMAP(DMAy_REMAP)); + + if (Cmd != DISABLE) + { + /* Calculate the used DMAy */ + /* Set the selected DMAy remap request */ + DMAyChx->CHSEL = DMAy_REMAP; + DMAy->CHMAPEN = 1; + } + else + { + DMAy->CHMAPEN = 0; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dvp.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dvp.c new file mode 100644 index 0000000000..93ee89b00b --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dvp.c @@ -0,0 +1,166 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_dvp.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_dvp.h" +#include "n32g45x_rcc.h" + +/** + * @brief Deinitializes the DVP peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DVP_DeInit(void) +{ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_DVP, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_DVP, DISABLE); +} + +/** + * @brief Initializes the DVP peripheral according to the specified + * parameters in the DVP_InitStruct . + * @param DVP_InitStruct pointer to a DVP_InitType structure + * that contains the configuration information for the specified DVP + * peripheral. + * @retval None + */ +void DVP_Init( DVP_InitType* DVP_InitStruct) +{ + uint32_t tmpregister = 0x00; + + /* Check the parameters */ + assert_param(IS_DVP_LINE_CAPTURE(DVP_InitStruct->LineCapture)); + assert_param(IS_DVP_BYTE_CAPTURE(DVP_InitStruct->ByteCapture)); + assert_param(IS_DVP_DATA_INVERT(DVP_InitStruct->DataInvert)); + assert_param(IS_DVP_PIXEL_POLARITY(DVP_InitStruct->PixelClkPolarity)); + assert_param(IS_DVP_VSYNC_POLARITY(DVP_InitStruct->VsyncPolarity)); + assert_param(IS_DVP_HSYNC_POLARITY(DVP_InitStruct->HsyncPolarity)); + assert_param(IS_DVP_CAPTURE_MODE(DVP_InitStruct->CaptureMode)); + assert_param(IS_DVP_FIFOWATERMARK(DVP_InitStruct->FifoWatermark)); + + /*---------------------------- DVP CTRL Configuration -----------------------*/ + tmpregister = 0; + tmpregister |= DVP_InitStruct->LineCapture | DVP_InitStruct->ByteCapture + | DVP_InitStruct->DataInvert | DVP_InitStruct->PixelClkPolarity + | DVP_InitStruct->VsyncPolarity | DVP_InitStruct->HsyncPolarity + | DVP_InitStruct->CaptureMode | DVP_InitStruct->FifoWatermark; + DVP->CTRL = tmpregister; + + /*---------------------------- DVP WST Configuration -----------------------*/ + if (DVP_InitStruct->RowStart) + DVP_InitStruct->RowStart--; + + if (DVP_InitStruct->ColumnStart) + DVP_InitStruct->ColumnStart--; + + DVP->WST = ( (((uint32_t)(DVP_InitStruct->RowStart)) << DVP_WST_VST_SHIFT) \ + | (((uint32_t)(DVP_InitStruct->ColumnStart))<< DVP_WST_HST_SHIFT) ); + + /*---------------------------- DVP WSIZE Configuration -----------------------*/ + DVP->WSIZE = ( (((uint32_t)(DVP_InitStruct->ImageHeight-1)) << DVP_WSIZE_VLINE_SHIFT) \ + | (((uint32_t)(DVP_InitStruct->ImageWidth-1)) << DVP_WSIZE_HCNT_SHIFT) ); +} + +/** + * @brief Fills DVP_InitStruct member with its default value. + * @param DVP_InitStruct pointer to a DVP_InitType structure + * which will be initialized. + * @retval None + */ +void DVP_DafaultInitParam(DVP_InitType* DVP_InitStruct) +{ + /* DVP_InitStruct members default value */ + DVP_InitStruct->FifoWatermark = DVP_WATER_MARK_1; + DVP_InitStruct->LineCapture = DVP_LINE_CAPTURE_ALL; + DVP_InitStruct->ByteCapture = DVP_BYTE_CAPTURE_ALL; + DVP_InitStruct->DataInvert = DVP_DATA_NOTINVERT; + DVP_InitStruct->PixelClkPolarity = DVP_PIXEL_POLARITY_FALLING; + DVP_InitStruct->VsyncPolarity = DVP_VSYNC_POLARITY_LOW; + DVP_InitStruct->HsyncPolarity = DVP_HSYNC_POLARITY_HIGH; + DVP_InitStruct->CaptureMode = DVP_CAPTURE_MODE_SINGLE; + DVP_InitStruct->RowStart = 0; + DVP_InitStruct->ColumnStart = 0; + DVP_InitStruct->ImageHeight = 240; + DVP_InitStruct->ImageWidth = 320; +} + +/** + * @brief Enables or disables the DVP DMA interface. + * @param Cmd New state of the DMA Request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DVP_ConfigDma( FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* When DMA is enable, the FWM in CTRL1 should be set 1*/ + __DVP_SetFifoWatermark(DVP_WATER_MARK_1); + + __DVP_EnableDMA(); + } + else + { + __DVP_DisableDMA(); + } +} + +/** + * @brief Get the data length in FIFO. + * @param None. + * @retval Current date length in FIFO + */ +uint32_t DVP_GetFifoCount(void) +{ + if (__FIFOIsNotEmpty()) + return ((DVP->STS & DVP_STS_FCNT_MASK)>>DVP_STS_FCNT_SHIFT); + else + return 0; +} + +/** + * @brief Software Reset FIFO + * @param None. + * @retval None. + */ +void DVP_ResetFifo(void) +{ + __DVP_StopCapture(); + + DVP->CTRL |= DVP_FIFO_SOFT_RESET; + + while(DVP->CTRL & DVP_FIFO_SOFT_RESET); +} diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_eth.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_eth.c new file mode 100644 index 0000000000..ec645eee40 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_eth.c @@ -0,0 +1,3100 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_eth.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_eth.h" +#include "n32g45x_gpio.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ETH + * @brief ETH driver modules + * @{ + */ + +/** + * @brief Initialize GPIO pins for MII/RMII interface. + * + * @param ETH_Interface specifies the interface, can be the following values: + * @arg ETH_INTERFACE_RMII Reduced media-independent interface + * @arg ETH_INTERFACE_MII Media-independent interface + * @param remap remap mode, can be 0~3 + */ +void ETH_ConfigGpio(uint8_t ETH_Interface, uint8_t remap) +{ + GPIO_InitType GPIO_InitStructure; + uint32_t ETH_PA_O; + uint32_t ETH_PA_I; + uint32_t ETH_PB_O; + uint32_t ETH_PB_I; + uint32_t ETH_PC_O; + uint32_t ETH_PC_I; + uint32_t ETH_PD_O; + uint32_t ETH_PD_I; + if (ETH_Interface == ETH_INTERFACE_MII) + { + switch (remap) + { + case 0: + ETH_PA_O = GPIO_PIN_2; + ETH_PA_I = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_7; + ETH_PB_O = GPIO_PIN_8 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; + ETH_PB_I = GPIO_PIN_10 | GPIO_PIN_0 | GPIO_PIN_1; + ETH_PC_O = GPIO_PIN_1 | GPIO_PIN_2; + ETH_PC_I = GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; + ETH_PD_O = 0; + ETH_PD_I = 0; + break; + case 1: + ETH_PA_O = GPIO_PIN_2; + ETH_PA_I = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3; + ETH_PB_O = GPIO_PIN_8 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; + ETH_PB_I = GPIO_PIN_10; + ETH_PC_O = GPIO_PIN_1 | GPIO_PIN_2; + ETH_PC_I = GPIO_PIN_3; + ETH_PD_O = 0; + ETH_PD_I = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12; + GPIO_ConfigPinRemap(GPIO_RMP1_ETH, ENABLE); + break; + case 2: + ETH_PA_O = GPIO_PIN_2; + ETH_PA_I = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_7; + ETH_PB_O = GPIO_PIN_7 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; + ETH_PB_I = GPIO_PIN_10 | GPIO_PIN_0 | GPIO_PIN_1; + ETH_PC_O = GPIO_PIN_1 | GPIO_PIN_2; + ETH_PC_I = GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; + ETH_PD_O = 0; + ETH_PD_I = 0; + GPIO_ConfigPinRemap(GPIO_RMP2_ETH, ENABLE); + break; + case 3: + ETH_PA_O = GPIO_PIN_2; + ETH_PA_I = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3; + ETH_PB_O = GPIO_PIN_7 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; + ETH_PB_I = GPIO_PIN_10 | GPIO_PIN_0 | GPIO_PIN_1; + ETH_PC_O = GPIO_PIN_1 | GPIO_PIN_2; + ETH_PC_I = GPIO_PIN_3; + ETH_PD_O = 0; + ETH_PD_I = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10; + GPIO_ConfigPinRemap(GPIO_RMP3_ETH, ENABLE); + break; + default: + while (1) + ; + } + } + else /* RMII */ + { + switch (remap) + { + case 0: + case 2: + ETH_PA_O = GPIO_PIN_2; + ETH_PA_I = GPIO_PIN_1 | GPIO_PIN_7; + ETH_PB_O = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; + ETH_PB_I = 0; + ETH_PC_O = GPIO_PIN_1; + ETH_PC_I = GPIO_PIN_4 | GPIO_PIN_5; + ETH_PD_O = 0; + ETH_PD_I = 0; + break; + case 1: + case 3: + ETH_PA_O = GPIO_PIN_2; + ETH_PA_I = GPIO_PIN_1; + ETH_PB_O = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; + ETH_PB_I = 0; + ETH_PC_O = GPIO_PIN_1; + ETH_PC_I = 0; + ETH_PD_O = 0; + ETH_PD_I = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10; + GPIO_ConfigPinRemap(GPIO_RMP1_ETH, ENABLE); + break; + default: + while (1) + ; + } + } + if (ETH_PA_O) + { + /* Configure Ethernet PA and PA8 (MCO) as alternate function push-pull */ + GPIO_InitStructure.Pin = ETH_PA_O; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); + } + if (ETH_PB_O) + { + /* Configure Ethernet PB and PB5 (PPS) as alternate function push-pull */ + GPIO_InitStructure.Pin = ETH_PB_O; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); + } + if (ETH_PC_O) + { + /* Configure Ethernet PC as alternate function push-pull */ + GPIO_InitStructure.Pin = ETH_PC_O; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure); + } + if (ETH_PD_O) + { + /* Configure Ethernet PD as alternate function push-pull */ + GPIO_InitStructure.Pin = ETH_PD_O; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(GPIOD, &GPIO_InitStructure); + } + + if (ETH_PA_I) + { + /* Configure Ethernet PA as input */ + GPIO_InitStructure.Pin = ETH_PA_I; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); + } + if (ETH_PB_I) + { + /* Configure Ethernet PB as input */ + GPIO_InitStructure.Pin = ETH_PB_I; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); + } + if (ETH_PC_I) + { + /* Configure Ethernet PC as input */ + GPIO_InitStructure.Pin = ETH_PC_I; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure); + } + if (ETH_PD_I) + { + /* Configure Ethernet PD as input */ + GPIO_InitStructure.Pin = ETH_PD_I; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitPeripheral(GPIOD, &GPIO_InitStructure); + } +} + +/** @addtogroup ETH_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @addtogroup ETH_Private_Defines + * @{ + */ +/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ +__IO ETH_DMADescType* DMATxDescToSet; +__IO ETH_DMADescType* DMARxDescToGet; +__IO ETH_DMADescType* DMAPTPTxDescToSet; +__IO ETH_DMADescType* DMAPTPRxDescToGet; + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIADDR register Mask */ +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) + +/* ETHERNET MACCFG register Mask */ +#define MACCR_CLR_MASK ((uint32_t)0xFF20810F) + +/* ETHERNET MACFLWCTRL register Mask */ +#define MACFCR_CLR_MASK ((uint32_t)0x0000FF41) + +/* ETHERNET DMAOPMOD register Mask */ +#define DMAOMR_CLR_MASK ((uint32_t)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REG_LEN 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTER_SHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMA_TX_DESC_COLLISION_COUNTER_SHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMA_TX_DESC_BUF2_SIZE_SHIFT 11 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMA_RX_DESC_FRAME_LEN_SHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMA_RX_DESC_BUF2_SIZE_SHIFT 11 + +/** + * @} + */ + +/** @addtogroup ETH_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @addtogroup ETH_Private_Variables + * @{ + */ +/** + * @} + */ + +/** @addtogroup ETH_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @addtogroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ETHERNET peripheral registers to their default reset values. + */ +void ETH_DeInit(void) +{ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ETHMAC, ENABLE); + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ETHMAC, DISABLE); +} +/** + * @brief Initializes the ETHERNET peripheral according to the specified + * parameters in the ETH_InitStruct . + * @param ETH_InitStruct pointer to a ETH_InitType structure that contains + * the configuration information for the specified ETHERNET peripheral. + * @param callable a function pointer of @ref ETH_InitPHY + * @return ETH_ERROR: Ethernet initialization failed + * ETH_SUCCESS: Ethernet successfully initialized + */ +uint32_t ETH_Init(ETH_InitType* ETH_InitStruct, ETH_InitPHY callable) +{ + uint32_t tmpregister = 0; + RCC_ClocksType rcc_clocks; + uint32_t hclk = 60000000; + /* Check the parameters */ + /* MAC --------------------------*/ + assert_param(IS_ETH_AUTONEG(ETH_InitStruct->AutoNegotiation)); + assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->Watchdog)); + assert_param(IS_ETH_JABBER(ETH_InitStruct->Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->CarrierSense)); + assert_param(IS_ETH_SPEED_MODE(ETH_InitStruct->SpeedMode)); + assert_param(IS_ETH_RX_OWN(ETH_InitStruct->RxOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->LoopbackMode)); + assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->DuplexMode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->RetryTransmission)); + assert_param(IS_ETH_AUTO_PAD_CRC_STRIP(ETH_InitStruct->AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->BackoffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->DeferralCheck)); + assert_param(IS_ETH_RX_ALL(ETH_InitStruct->RxAll)); + assert_param(IS_ETH_SRC_ADDR_FILTER(ETH_InitStruct->SrcAddrFilter)); + assert_param(IS_ETH_PASS_CTRL_FRAMES(ETH_InitStruct->PassCtrlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->BroadcastFramesReception)); + assert_param(IS_ETH_DEST_ADDR_FILTER(ETH_InitStruct->DestAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->PauseTime)); + assert_param(IS_ETH_ZERO_QUANTA_PAUSE(ETH_InitStruct->ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->UnicastPauseFrameDetect)); + assert_param(IS_ETH_RX_FLOW_CTRL(ETH_InitStruct->RxFlowCtrl)); + assert_param(IS_ETH_TX_FLOW_CTRL(ETH_InitStruct->TxFlowCtrl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->VLANTagIdentifier)); + /* DMA --------------------------*/ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RX_STORE_FORWARD(ETH_InitStruct->RxStoreForward)); + assert_param(IS_ETH_FLUSH_RX_FRAME(ETH_InitStruct->FlushRxFrame)); + assert_param(IS_ETH_TX_STORE_FORWARD(ETH_InitStruct->TxStoreForward)); + assert_param(IS_ETH_TX_THRESHOLD_CTRL(ETH_InitStruct->TxThresholdCtrl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RX_THRESHOLD_CTRL(ETH_InitStruct->RxThresholdCtrl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->SecondFrameOperate)); + assert_param(IS_ETH_ADDR_ALIGNED_BEATS(ETH_InitStruct->AddrAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->FixedBurst)); + assert_param(IS_ETH_RX_DMA_BURST_LEN(ETH_InitStruct->RxDMABurstLen)); + assert_param(IS_ETH_TX_DMA_BURST_LEN(ETH_InitStruct->TxDMABurstLen)); + assert_param(IS_ETH_DMA_DESC_SKIP_LEN(ETH_InitStruct->DescSkipLen)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX(ETH_InitStruct->DMAArbitration)); + /*-------------------------------- MAC Config ------------------------------*/ + /*---------------------- ETHERNET MACMIIADDR Configuration -------------------*/ + /* Get the ETHERNET MACMIIADDR value */ + tmpregister = ETH->MACMIIADDR; + /* Clear CTRLSTS Clock Range CTRL[2:0] bits */ + tmpregister &= MACMIIAR_CR_MASK; + /* Get hclk frequency value */ + RCC_GetClocksFreqValue(&rcc_clocks); + hclk = rcc_clocks.HclkFreq; + /* Set CTRL bits depending on hclk value */ + if (/*(hclk >= 20000000) && */ (hclk < 35000000)) + { + /* CTRLSTS Clock Range between 20-35 MHz */ + tmpregister |= (uint32_t)ETH_MACMIIADDR_CR_DIV16; + } + else if ((hclk >= 35000000) && (hclk < 60000000)) + { + /* CTRLSTS Clock Range between 35-60 MHz */ + tmpregister |= (uint32_t)ETH_MACMIIADDR_CR_DIV26; + } + else if ((hclk >= 60000000) && (hclk <= 72000000)) + { + /* CTRLSTS Clock Range between 60-72 MHz */ + tmpregister |= (uint32_t)ETH_MACMIIADDR_CR_DIV42; + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CTRLSTS Clock Range */ + ETH->MACMIIADDR = (uint32_t)tmpregister; + /*-------------------- PHY initialization and configuration ----------------*/ + if (ETH_ERROR == callable(ETH_InitStruct)) + { + return ETH_ERROR; + } + + /*------------------------ ETHERNET MACCFG Configuration --------------------*/ + /* Get the ETHERNET MACCFG value */ + tmpregister = ETH->MACCFG; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpregister &= MACCR_CLR_MASK; + /* Set the WD bit according to Watchdog value */ + /* Set the JD: bit according to Jabber value */ + /* Set the IFG bit according to InterFrameGap value */ + /* Set the DCRS bit according to CarrierSense value */ + /* Set the FES bit according to SpeedMode value */ + /* Set the DO bit according to RxOwn value */ + /* Set the LM bit according to LoopbackMode value */ + /* Set the DM bit according to DuplexMode value */ + /* Set the IPC bit according to ChecksumOffload value */ + /* Set the DAT bit according to RetryTransmission value */ + /* Set the ACS bit according to AutomaticPadCRCStrip value */ + /* Set the BL bit according to BackoffLimit value */ + /* Set the DC bit according to DeferralCheck value */ + tmpregister |= (uint32_t)( + ETH_InitStruct->Watchdog | ETH_InitStruct->Jabber | ETH_InitStruct->InterFrameGap | ETH_InitStruct->CarrierSense + | ETH_InitStruct->SpeedMode | ETH_InitStruct->RxOwn | ETH_InitStruct->LoopbackMode | ETH_InitStruct->DuplexMode + | ETH_InitStruct->ChecksumOffload | ETH_InitStruct->RetryTransmission | ETH_InitStruct->AutomaticPadCRCStrip + | ETH_InitStruct->BackoffLimit | ETH_InitStruct->DeferralCheck); + /* Write to ETHERNET MACCFG */ + ETH->MACCFG = (uint32_t)tmpregister; + + /*----------------------- ETHERNET MACFFLT Configuration --------------------*/ + /* Set the RA bit according to RxAll value */ + /* Set the SAF and SAIF bits according to SrcAddrFilter value */ + /* Set the PCF bit according to PassCtrlFrames value */ + /* Set the DBF bit according to BroadcastFramesReception value */ + /* Set the DAIF bit according to DestAddrFilter value */ + /* Set the PEND bit according to PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to UnicastFramesFilter value */ + /* Write to ETHERNET MACFFLT */ + ETH->MACFFLT = (uint32_t)(ETH_InitStruct->RxAll | ETH_InitStruct->SrcAddrFilter | ETH_InitStruct->PassCtrlFrames + | ETH_InitStruct->BroadcastFramesReception | ETH_InitStruct->DestAddrFilter + | ETH_InitStruct->PromiscuousMode | ETH_InitStruct->MulticastFramesFilter + | ETH_InitStruct->UnicastFramesFilter); + /*--------------- ETHERNET MACHASHHI and MACHASHLO Configuration ---------------*/ + /* Write to ETHERNET MACHASHHI */ + ETH->MACHASHHI = (uint32_t)ETH_InitStruct->HashTableHigh; + /* Write to ETHERNET MACHASHLO */ + ETH->MACHASHLO = (uint32_t)ETH_InitStruct->HashTableLow; + /*----------------------- ETHERNET MACFLWCTRL Configuration --------------------*/ + /* Get the ETHERNET MACFLWCTRL value */ + tmpregister = ETH->MACFLWCTRL; + /* Clear xx bits */ + tmpregister &= MACFCR_CLR_MASK; + + /* Set the PT bit according to PauseTime value */ + /* Set the DZPQ bit according to ZeroQuantaPause value */ + /* Set the PLT bit according to PauseLowThreshold value */ + /* Set the UP bit according to UnicastPauseFrameDetect value */ + /* Set the RFE bit according to RxFlowCtrl value */ + /* Set the TFE bit according to TxFlowCtrl value */ + tmpregister |= (uint32_t)((ETH_InitStruct->PauseTime << 16) | ETH_InitStruct->ZeroQuantaPause + | ETH_InitStruct->PauseLowThreshold | ETH_InitStruct->UnicastPauseFrameDetect + | ETH_InitStruct->RxFlowCtrl | ETH_InitStruct->TxFlowCtrl); + /* Write to ETHERNET MACFLWCTRL */ + ETH->MACFLWCTRL = (uint32_t)tmpregister; + /*----------------------- ETHERNET MACVLANTAG Configuration -----------------*/ + /* Set the ETV bit according to VLANTagComparison value */ + /* Set the VL bit according to VLANTagIdentifier value */ + ETH->MACVLANTAG = (uint32_t)(ETH_InitStruct->VLANTagComparison | ETH_InitStruct->VLANTagIdentifier); + + /*-------------------------------- DMA Config ------------------------------*/ + /*----------------------- ETHERNET DMAOPMOD Configuration --------------------*/ + /* Get the ETHERNET DMAOPMOD value */ + tmpregister = ETH->DMAOPMOD; + /* Clear xx bits */ + tmpregister &= DMAOMR_CLR_MASK; + + /* Set the DT bit according to DropTCPIPChecksumErrorFrame value */ + /* Set the RSYF bit according to RxStoreForward value */ + /* Set the DFF bit according to FlushRxFrame value */ + /* Set the TSF bit according to TxStoreForward value */ + /* Set the TTC bit according to TxThresholdCtrl value */ + /* Set the FEF bit according to ForwardErrorFrames value */ + /* Set the FUF bit according to ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to RxThresholdCtrl value */ + /* Set the OSF bit according to SecondFrameOperate value */ + tmpregister |= + (uint32_t)(ETH_InitStruct->DropTCPIPChecksumErrorFrame | ETH_InitStruct->RxStoreForward + | ETH_InitStruct->FlushRxFrame | ETH_InitStruct->TxStoreForward | ETH_InitStruct->TxThresholdCtrl + | ETH_InitStruct->ForwardErrorFrames | ETH_InitStruct->ForwardUndersizedGoodFrames + | ETH_InitStruct->RxThresholdCtrl | ETH_InitStruct->SecondFrameOperate); + /* Write to ETHERNET DMAOPMOD */ + ETH->DMAOPMOD = (uint32_t)tmpregister; + + /*----------------------- ETHERNET DMABUSMOD Configuration --------------------*/ + /* Set the AAL bit according to AddrAlignedBeats value */ + /* Set the FB bit according to FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to RxDMABurstLen value */ + /* Set the PBL and 4*PBL bits according to TxDMABurstLen value */ + /* Set the DSL bit according to ETH_DesciptorSkipLength value */ + /* Set the PEND and DA bits according to DMAArbitration value */ + ETH->DMABUSMOD = + (uint32_t)(ETH_InitStruct->AddrAlignedBeats | ETH_InitStruct->FixedBurst | ETH_InitStruct->RxDMABurstLen + | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->TxDMABurstLen | (ETH_InitStruct->DescSkipLen << 2) | ETH_InitStruct->DMAArbitration + | ETH_DMABUSMOD_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Disable all MMC interrupt */ + ETH->MMCRXINTMSK = 0xffffffffUL; + ETH->MMCTXINTMSK = 0xffffffffUL; + ETH->MMCRXCOINTMSK = 0xffffffffUL; + + /* Return Ethernet configuration success */ + return ETH_SUCCESS; +} + +/** + * @brief Fills each ETH_InitStruct member with its default value. + * @param ETH_InitStruct pointer to a ETH_InitType structure which will be initialized. + */ +void ETH_InitStruct(ETH_InitType* ETH_InitStruct) +{ + /* ETH_InitStruct members default value */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->AutoNegotiation = ETH_AUTONEG_DISABLE; + ETH_InitStruct->Watchdog = ETH_WATCHDOG_ENABLE; + ETH_InitStruct->Jabber = ETH_JABBER_ENABLE; + ETH_InitStruct->InterFrameGap = ETH_INTER_FRAME_GAP_96BIT; + ETH_InitStruct->CarrierSense = ETH_CARRIER_SENSE_ENABLE; + ETH_InitStruct->SpeedMode = ETH_SPEED_MODE_10M; + ETH_InitStruct->RxOwn = ETH_RX_OWN_ENABLE; + ETH_InitStruct->LoopbackMode = ETH_LOOPBACK_MODE_DISABLE; + ETH_InitStruct->DuplexMode = ETH_DUPLEX_MODE_HALF; + ETH_InitStruct->ChecksumOffload = ETH_CHECKSUM_OFFLOAD_DISABLE; + ETH_InitStruct->RetryTransmission = ETH_RETRY_TRANSMISSION_ENABLE; + ETH_InitStruct->AutomaticPadCRCStrip = ETH_AUTO_PAD_CRC_STRIP_DISABLE; + ETH_InitStruct->BackoffLimit = ETH_BACKOFF_LIMIT_10; + ETH_InitStruct->DeferralCheck = ETH_DEFERRAL_CHECK_DISABLE; + ETH_InitStruct->RxAll = ETH_RX_ALL_DISABLE; + ETH_InitStruct->SrcAddrFilter = ETH_SRC_ADDR_FILTER_DISABLE; + ETH_InitStruct->PassCtrlFrames = ETH_PASS_CTRL_FRAMES_BLOCK_ALL; + ETH_InitStruct->BroadcastFramesReception = ETH_BROADCAST_FRAMES_RECEPTION_DISABLE; + ETH_InitStruct->DestAddrFilter = ETH_DEST_ADDR_FILTER_NORMAL; + ETH_InitStruct->PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; + ETH_InitStruct->MulticastFramesFilter = ETH_MULTICAST_FRAMES_FILTER_PERFECT; + ETH_InitStruct->UnicastFramesFilter = ETH_UNICAST_FRAMES_FILTER_PERFECT; + ETH_InitStruct->HashTableHigh = 0x0; + ETH_InitStruct->HashTableLow = 0x0; + ETH_InitStruct->PauseTime = 0x0; + ETH_InitStruct->ZeroQuantaPause = ETH_ZERO_QUANTA_PAUSE_DISABLE; + ETH_InitStruct->PauseLowThreshold = ETH_PAUSE_LOW_THRESHOLD_MINUS4; + ETH_InitStruct->UnicastPauseFrameDetect = ETH_UNICAST_PAUSE_FRAME_DETECT_DISABLE; + ETH_InitStruct->RxFlowCtrl = ETH_RX_FLOW_CTRL_DISABLE; + ETH_InitStruct->TxFlowCtrl = ETH_TX_FLOW_CTRL_DISABLE; + ETH_InitStruct->VLANTagComparison = ETH_VLAN_TAG_COMPARISON_16BIT; + ETH_InitStruct->VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->DropTCPIPChecksumErrorFrame = ETH_DROP_TCPIP_CHECKSUM_ERROR_FRAME_DISABLE; + ETH_InitStruct->RxStoreForward = ETH_RX_STORE_FORWARD_ENABLE; + ETH_InitStruct->FlushRxFrame = ETH_FLUSH_RX_FRAME_DISABLE; + ETH_InitStruct->TxStoreForward = ETH_TX_STORE_FORWARD_ENABLE; + ETH_InitStruct->TxThresholdCtrl = ETH_TX_THRESHOLD_CTRL_64BYTES; + ETH_InitStruct->ForwardErrorFrames = ETH_FORWARD_ERROR_FRAMES_DISABLE; + ETH_InitStruct->ForwardUndersizedGoodFrames = ETH_FORWARD_UNDERSIZED_GOOD_FRAMES_ENABLE; + ETH_InitStruct->RxThresholdCtrl = ETH_RX_THRESHOLD_CTRL_64BYTES; + ETH_InitStruct->SecondFrameOperate = ETH_SECOND_FRAME_OPERATE_DISABLE; + ETH_InitStruct->AddrAlignedBeats = ETH_ADDR_ALIGNED_BEATS_ENABLE; + ETH_InitStruct->FixedBurst = ETH_FIXED_BURST_DISABLE; + ETH_InitStruct->RxDMABurstLen = ETH_RX_DMA_BURST_LEN_1BEAT; + ETH_InitStruct->TxDMABurstLen = ETH_TX_DMA_BURST_LEN_1BEAT; + ETH_InitStruct->DescSkipLen = 0x0; + ETH_InitStruct->DMAArbitration = ETH_DMA_ARBITRATION_ROUND_ROBIN_RXTX_1_1; +} + +/** + * @brief Enables ENET MAC and DMA reception/transmission + */ +void ETH_EnableTxRx(void) +{ + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_EnableMacTx(ENABLE); + /* Flush Transmit DATFIFO */ + ETH_FlushTxFifo(); + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_EnableMacRx(ENABLE); + + /* Start DMA transmission */ + ETH_EnableDmaTx(ENABLE); + /* Start DMA reception */ + ETH_EnableDmaRx(ENABLE); +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * @param ppkt pointer to the application's packet buffer to transmit. + * @param FrameLength Tx Packet size. + * @return ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_TxPacket(uint8_t* ppkt, uint16_t FrameLength) +{ + uint32_t send_len = 0; + + while (send_len < FrameLength) + { + uint32_t offset = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if ((DMATxDescToSet->Status & ETH_DMA_TX_DESC_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + + uint16_t block_len = FrameLength - send_len; + if (block_len > ETH_DMA_TX_DESC_TBS1) + { + block_len = ETH_DMA_TX_DESC_TBS1; + } + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for (offset = 0; offset < block_len; offset++) + { + (*(__IO uint8_t*)((DMATxDescToSet->Buf1Addr) + offset)) = (*(ppkt + offset + send_len)); + } + + /* Setting the Frame Length: bits[10:0] */ + DMATxDescToSet->CtrlOrBufSize &= (~ETH_DMA_TX_DESC_TBS1); + DMATxDescToSet->CtrlOrBufSize |= block_len; + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + if (send_len == 0) + { + DMATxDescToSet->CtrlOrBufSize |= ETH_DMA_TX_DESC_FS; + } + send_len += block_len; + if (send_len == FrameLength) + { + DMATxDescToSet->CtrlOrBufSize |= ETH_DMA_TX_DESC_LS; + } + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMA_TX_DESC_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASTS & ETH_DMASTS_TU) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASTS = ETH_DMASTS_TU; + /* Resume DMA transmission*/ + ETH->DMATXPD = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + if ((DMATxDescToSet->CtrlOrBufSize & ETH_DMA_TX_DESC_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADescType*)(DMATxDescToSet->Buf2OrNextDescAddr); + } + else /* Ring Mode */ + { + if ((DMATxDescToSet->CtrlOrBufSize & ETH_DMA_TX_DESC_TER) != (uint32_t)RESET) + { + /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ + DMATxDescToSet = (ETH_DMADescType*)(ETH->DMATXDLADDR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = + (ETH_DMADescType*)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABUSMOD & ETH_DMABUSMOD_DSL))); + } + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt. + * @param ppkt pointer to the application packet receive buffer. + * @param checkErr whether check error + * @return ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_RxPacket(uint8_t* ppkt, uint8_t checkErr) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if (((checkErr && ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_ES) == (uint32_t)RESET)) || !checkErr) + && ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_LS) != (uint32_t)RESET) + && ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet */ + framelength = ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_FL) >> ETH_DMA_RX_DESC_FRAME_LEN_SHIFT); + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for (offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t*)((DMARxDescToGet->Buf1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMA_RX_DESC_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASTS & ETH_DMASTS_RU) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASTS = ETH_DMASTS_RU; + /* Resume DMA reception */ + ETH->DMARXPD = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if ((DMARxDescToGet->CtrlOrBufSize & ETH_DMA_RX_DESC_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADescType*)(DMARxDescToGet->Buf2OrNextDescAddr); + } + else /* Ring Mode */ + { + if ((DMARxDescToGet->CtrlOrBufSize & ETH_DMA_RX_DESC_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADescType*)(ETH->DMARXDLADDR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = + (ETH_DMADescType*)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABUSMOD & ETH_DMABUSMOD_DSL))); + } + } + + /* Return Frame Length/ERROR */ + return (framelength); +} + +/** + * @brief Get the size of received the received packet. + * @return framelength: received packet size + */ +uint32_t ETH_GetRxPacketSize(void) +{ + uint32_t frameLength = 0; + if (((DMARxDescToGet->Status & ETH_DMA_RX_DESC_OWN) == (uint32_t)RESET) + && ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_ES) == (uint32_t)RESET) + && ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_LS) != (uint32_t)RESET) + && ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_FS) != (uint32_t)RESET)) + { + /* Get the size of the packet: including 4 bytes of the CRC */ + frameLength = ETH_GetDmaRxDescFrameLen(DMARxDescToGet); + } + + /* Return Frame Length */ + return frameLength; +} + +/** + * @brief Drop a Received packet (too small packet, etc...) + */ +void ETH_DropRxPacket(void) +{ + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMA_RX_DESC_OWN; + /* Chained Mode */ + if ((DMARxDescToGet->CtrlOrBufSize & ETH_DMA_RX_DESC_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADescType*)(DMARxDescToGet->Buf2OrNextDescAddr); + } + else /* Ring Mode */ + { + if ((DMARxDescToGet->CtrlOrBufSize & ETH_DMA_RX_DESC_RER) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read: this will + be the first Rx descriptor in this case */ + DMARxDescToGet = (ETH_DMADescType*)(ETH->DMARXDLADDR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = + (ETH_DMADescType*)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABUSMOD & ETH_DMABUSMOD_DSL))); + } + } +} + +/*--------------------------------- PHY ------------------------------------*/ +/** + * @brief Read a PHY register + * @param PHYAddress PHY device address, is the index of one of supported 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR Tranceiver Basic Control Register + * @arg PHY_BSR Tranceiver Basic Status Register + * @arg PHY_SR Tranceiver Status Register + * @arg More PHY register could be read depending on the used PHY + * @return ETH_ERROR: in case of timeout + * MAC MIIDR register value: Data read from the selected PHY register (correct read ) + */ +uint16_t ETH_ReadPhyRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpregister = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIADDR value */ + tmpregister = ETH->MACMIIADDR; + /* Keep only the CTRLSTS Clock Range CTRL[2:0] bits value */ + tmpregister &= ~MACMIIAR_CR_MASK; + /* Prepare the MII address register value */ + tmpregister |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIADDR_PA); /* Set the PHY device address */ + tmpregister |= (((uint32_t)PHYReg << 6) & ETH_MACMIIADDR_MR); /* Set the PHY register address */ + tmpregister &= ~ETH_MACMIIADDR_MW; /* Set the read mode */ + tmpregister |= ETH_MACMIIADDR_MB; /* Set the MII Busy bit */ + /* Write the result value into the MII Address register */ + ETH->MACMIIADDR = tmpregister; + /* Check for the Busy flag */ + do + { + timeout++; + tmpregister = ETH->MACMIIADDR; + } while ((tmpregister & ETH_MACMIIADDR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if (timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + /* Return data register value */ + uint16_t ret = (uint16_t)(ETH->MACMIIDAT); + return ret; +} + +/** + * @brief Write to a PHY register + * @param PHYAddress PHY device address, is the index of one of supported 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR Tranceiver Control Register + * @arg More PHY register could be written depending on the used PHY + * @param PHYValue the value to write + * @return ETH_ERROR: in case of timeout + * ETH_SUCCESS: for correct write + */ +uint32_t ETH_WritePhyRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpregister = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIADDR value */ + tmpregister = ETH->MACMIIADDR; + /* Keep only the CTRLSTS Clock Range CTRL[2:0] bits value */ + tmpregister &= ~MACMIIAR_CR_MASK; + /* Prepare the MII register address value */ + tmpregister |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIADDR_PA); /* Set the PHY device address */ + tmpregister |= (((uint32_t)PHYReg << 6) & ETH_MACMIIADDR_MR); /* Set the PHY register address */ + tmpregister |= ETH_MACMIIADDR_MW; /* Set the write mode */ + tmpregister |= ETH_MACMIIADDR_MB; /* Set the MII Busy bit */ + /* Give the value to the MII data register */ + ETH->MACMIIDAT = PHYValue; + /* Write the result value into the MII Address register */ + ETH->MACMIIADDR = tmpregister; + /* Check for the Busy flag */ + do + { + timeout++; + tmpregister = ETH->MACMIIADDR; + } while ((tmpregister & ETH_MACMIIADDR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + /* Return ERROR in case of timeout */ + if (timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Enables or disables the PHY loopBack mode. + * @note: Don't be confused with ETH_MACLoopBackCmd function which enables internal + * loopback at MII level + * @param PHYAddress PHY device address, is the index of one of supported 32 PHY devices. + * This parameter can be one of the following values: + * @param Cmd new state of the PHY loopBack mode. + * This parameter can be: ENABLE or DISABLE. + * @return ETH_ERROR: in case of bad PHY configuration + * ETH_SUCCESS: for correct PHY configuration + */ +uint32_t ETH_EnablePhyLoopBack(uint16_t PHYAddress, FunctionalState Cmd) +{ + uint16_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Get the PHY configuration to update it */ + tmpregister = ETH_ReadPhyRegister(PHYAddress, PHY_BCR); + + if (Cmd != DISABLE) + { + /* Enable the PHY loopback mode */ + tmpregister |= PHY_LOOPBACK; + } + else + { + /* Disable the PHY loopback mode: normal mode */ + tmpregister &= (uint16_t)(~(uint16_t)PHY_LOOPBACK); + } + /* Update the PHY control register with the new configuration */ + if (ETH_WritePhyRegister(PHYAddress, PHY_BCR, tmpregister) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + /* Return SUCCESS */ + return ETH_ERROR; + } +} + +/*--------------------------------- MAC ------------------------------------*/ +/** + * @brief Enables or disables the MAC transmission. + * @param Cmd new state of the MAC transmission. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMacTx(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the MAC transmission */ + ETH->MACCFG |= ETH_MACCFG_TE; + } + else + { + /* Disable the MAC transmission */ + ETH->MACCFG &= ~ETH_MACCFG_TE; + } +} + +/** + * @brief Enables or disables the MAC reception. + * @param Cmd new state of the MAC reception. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMacRx(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the MAC reception */ + ETH->MACCFG |= ETH_MACCFG_RE; + } + else + { + /* Disable the MAC reception */ + ETH->MACCFG &= ~ETH_MACCFG_RE; + } +} + +/** + * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @return The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowCtrlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + /* The Flow Control register should not be written to until this bit is cleared */ + if ((ETH->MACFLWCTRL & ETH_MACFLWCTRL_FCB_BPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + */ +void ETH_GeneratePauseCtrlFrame(void) +{ + /* When Set In full duplex MAC initiates pause control frame */ + ETH->MACFLWCTRL |= ETH_MACFLWCTRL_FCB_BPA; +} + +/** + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * @param Cmd new state of the MAC BackPressure operation activation. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableBackPressureActivation(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Activate the MAC BackPressure operation */ + /* In Half duplex: during backpressure, when the MAC receives a new frame, + the transmitter starts sending a JAM pattern resulting in a collision */ + ETH->MACFLWCTRL |= ETH_MACFLWCTRL_FCB_BPA; + } + else + { + /* Desactivate the MAC BackPressure operation */ + ETH->MACFLWCTRL &= ~ETH_MACFLWCTRL_FCB_BPA; + } +} + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param ETH_MAC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCTX MMC transmit flag + * @arg ETH_MAC_FLAG_MMCRX MMC receive flag + * @arg ETH_MAC_FLAG_MMC MMC flag + * @arg ETH_MAC_FLAG_PMT PMT flag + * @return The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMacFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + if ((ETH->MACINTSTS & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * @param ETH_MAC_IT specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_INT_TST Time stamp trigger interrupt + * @arg ETH_MAC_INT_MMCTX MMC transmit interrupt + * @arg ETH_MAC_INT_MMCRX MMC receive interrupt + * @arg ETH_MAC_INT_MMC MMC interrupt + * @arg ETH_MAC_INT_PMT PMT interrupt + * @return The new state of ETHERNET MAC interrupt (SET or RESET). + */ +INTStatus ETH_GetMacIntStatus(uint32_t ETH_MAC_IT) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_INT(ETH_MAC_IT)); + if ((ETH->MACINTSTS & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * @param ETH_MAC_IT specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_INT_TST Time stamp trigger interrupt + * @arg ETH_MAC_INT_PMT PMT interrupt + * @param Cmd new state of the specified ETHERNET MAC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMacInt(uint32_t ETH_MAC_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_INT(ETH_MAC_IT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected ETHERNET MAC interrupts */ + ETH->MACINTMSK &= (~(uint32_t)ETH_MAC_IT); + } + else + { + /* Disable the selected ETHERNET MAC interrupts */ + ETH->MACINTMSK |= ETH_MAC_IT; + } +} + +/** + * @brief Configures the selected MAC address. + * @param MacAddr The MAC addres to configure. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR0 MAC Address0 + * @arg ETH_MAC_ADDR1 MAC Address1 + * @arg ETH_MAC_ADDR2 MAC Address2 + * @arg ETH_MAC_ADDR3 MAC Address3 + * @param Addr Pointer on MAC address buffer data (6 bytes). + */ +void ETH_SetMacAddr(uint32_t MacAddr, uint8_t* Addr) +{ + uint32_t tmpregister; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDR0123(MacAddr)); + + /* Calculate the selectecd MAC address high register */ + tmpregister = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + /* Load the selectecd MAC address high register */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + MacAddr)) = tmpregister; + /* Calculate the selectecd MAC address low register */ + tmpregister = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + /* Load the selectecd MAC address low register */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_LBASE + MacAddr)) = tmpregister; +} + +/** + * @brief Get the selected MAC address. + * @param MacAddr The MAC addres to return. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR0 MAC Address0 + * @arg ETH_MAC_ADDR1 MAC Address1 + * @arg ETH_MAC_ADDR2 MAC Address2 + * @arg ETH_MAC_ADDR3 MAC Address3 + * @param Addr Pointer on MAC address buffer data (6 bytes). + */ +void ETH_GetMacAddr(uint32_t MacAddr, uint8_t* Addr) +{ + uint32_t tmpregister; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDR0123(MacAddr)); + + /* Get the selectecd MAC address high register */ + tmpregister = (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + MacAddr)); + + /* Calculate the selectecd MAC address buffer */ + Addr[5] = ((tmpregister >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpregister & (uint8_t)0xFF); + /* Load the selectecd MAC address low register */ + tmpregister = (*(__IO uint32_t*)(ETH_MAC_ADDR_LBASE + MacAddr)); + /* Calculate the selectecd MAC address buffer */ + Addr[3] = ((tmpregister >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpregister >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpregister >> 8) & (uint8_t)0xFF); + Addr[0] = (tmpregister & (uint8_t)0xFF); +} + +/** + * @brief Enables or disables the Address filter module uses the specified + * ETHERNET MAC address for perfect filtering + * @param MacAddr specifies the ETHERNET MAC address to be used for prfect filtering. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR1 MAC Address1 + * @arg ETH_MAC_ADDR2 MAC Address2 + * @arg ETH_MAC_ADDR3 MAC Address3 + * @param Cmd new state of the specified ETHERNET MAC address use. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMacAddrPerfectFilter(uint32_t MacAddr, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDR123(MacAddr)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACADDR1HI_AE; + } + else + { + /* Disable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACADDR1HI_AE); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR1 MAC Address1 + * @arg ETH_MAC_ADDR2 MAC Address2 + * @arg ETH_MAC_ADDR3 MAC Address3 + * @param Filter specifies the used frame received field for comparaison + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR_FILTER_SA MAC Address is used to compare with the + * SA fields of the received frame. + * @arg ETH_MAC_ADDR_FILTER_DA MAC Address is used to compare with the + * DA fields of the received frame. + */ +void ETH_ConfigMacAddrFilter(uint32_t MacAddr, uint32_t Filter) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDR123(MacAddr)); + assert_param(IS_ETH_MAC_ADDR_FILTER(Filter)); + + if (Filter != ETH_MAC_ADDR_FILTER_DA) + { + /* The selected ETHERNET MAC address is used to compare with the SA fields of the + received frame. */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACADDR1HI_SA; + } + else + { + /* The selected ETHERNET MAC address is used to compare with the DA fields of the + received frame. */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACADDR1HI_SA); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDR1 MAC Address1 + * @arg ETH_MAC_ADDR2 MAC Address2 + * @arg ETH_MAC_ADDR3 MAC Address3 + * @param MaskByte specifies the used address bytes for comparaison + * This parameter can be any combination of the following values: + * @arg ETH_MAC_ADDR_MASK_BYTE6 Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_ADDR_MASK_BYTE5 Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_ADDR_MASK_BYTE4 Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_ADDR_MASK_BYTE3 Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_ADDR_MASK_BYTE2 Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_ADDR_MASK_BYTE1 Mask MAC Address low reg bits [7:0]. + */ +void ETH_ConfigMacAddrMaskBytesFilter(uint32_t MacAddr, uint32_t MaskByte) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDR123(MacAddr)); + assert_param(IS_ETH_MAC_ADDR_MASK(MaskByte)); + + /* Clear MBC bits in the selected MAC address high register */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACADDR1HI_MBC); + /* Set the selected Filetr mask bytes */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; +} +/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/ + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param DMATxDescTab Pointer on the first Tx desc list + * @param TxBuff Pointer on the first TxBuffer list + * @param BuffSize Buffer size of each descriptor + * @param TxBuffCount Number of the used Tx desc in the list + */ +void ETH_ConfigDmaTxDescInChainMode(ETH_DMADescType* DMATxDescTab, + uint8_t* TxBuff, + uint32_t BuffSize, + uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADescType* DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Second Address Chained bit */ + DMATxDesc->Status = 0; + DMATxDesc->CtrlOrBufSize = ETH_DMA_TX_DESC_TCH; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buf1Addr = (uint32_t)(&TxBuff[i * BuffSize]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if (i < (TxBuffCount - 1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buf2OrNextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buf2OrNextDescAddr = (uint32_t)DMATxDescTab; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATXDLADDR = (uint32_t)DMATxDescTab; +} + +/** + * @brief Initializes the DMA Tx descriptors in ring mode. + * @param DMATxDescTab Pointer on the first Tx desc list + * @param TxBuff1 Pointer on the first TxBuffer1 list + * @param TxBuff2 Pointer on the first TxBuffer2 list + * @param BuffSize Buffer size of each descriptor + * @param TxBuffCount Number of the used Tx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + */ +void ETH_ConfigDmaTxDescInRingMode(ETH_DMADescType* DMATxDescTab, + uint8_t* TxBuff1, + uint8_t* TxBuff2, + uint32_t BuffSize, + uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADescType* DMATxDesc; + uint32_t dsl = (ETH->DMABUSMOD & ETH_DMABUSMOD_DSL) >> 2; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + // DMATxDesc = DMATxDescTab + i; + DMATxDesc = (ETH_DMADescType*)((uint32_t)DMATxDescTab + i * (16 + 4 * dsl)); + /* Set Buffer1 address pointer */ + DMATxDesc->Buf1Addr = (uint32_t)(&TxBuff1[i * BuffSize]); + + /* Set Buffer2 address pointer */ + DMATxDesc->Buf2OrNextDescAddr = (uint32_t)(&TxBuff2[i * BuffSize]); + + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if (i == (TxBuffCount - 1)) + { + /* Set Transmit End of Ring bit */ + DMATxDesc->CtrlOrBufSize = ETH_DMA_TX_DESC_TER; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATXDLADDR = (uint32_t)DMATxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @param DMATxDesc pointer on a DMA Tx descriptor + * @param ETH_DMATxDescFlag specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_TX_DESC_OWN OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMA_TX_DESC_IC Interrupt on completetion + * @arg ETH_DMA_TX_DESC_LS Last Segment + * @arg ETH_DMA_TX_DESC_FS First Segment + * @arg ETH_DMA_TX_DESC_DC Disable CRC + * @arg ETH_DMA_TX_DESC_DP Disable Pad + * @arg ETH_DMA_TX_DESC_TTSE Transmit Time Stamp Enable + * @arg ETH_DMA_TX_DESC_TER Transmit End of Ring + * @arg ETH_DMA_TX_DESC_TCH Second Address Chained + * @arg ETH_DMA_TX_DESC_TTSS Tx Time Stamp Status + * @arg ETH_DMA_TX_DESC_IHE IP Header Error + * @arg ETH_DMA_TX_DESC_ES Error summary + * @arg ETH_DMA_TX_DESC_JT Jabber Timeout + * @arg ETH_DMA_TX_DESC_FF Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMA_TX_DESC_PCE Payload Checksum Error + * @arg ETH_DMA_TX_DESC_LOC Loss of Carrier: carrier lost during tramsmission + * @arg ETH_DMA_TX_DESC_NC No Carrier: no carrier signal from the tranceiver + * @arg ETH_DMA_TX_DESC_LC Late Collision: transmission aborted due to collision + * @arg ETH_DMA_TX_DESC_EC Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMA_TX_DESC_VF VLAN Frame + * @arg ETH_DMA_TX_DESC_CC Collision Count + * @arg ETH_DMA_TX_DESC_ED Excessive Deferral + * @arg ETH_DMA_TX_DESC_UF Underflow Error: late data arrival from the memory + * @arg ETH_DMA_TX_DESC_DB Deferred Bit + * @return The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDmaTxDescFlagStatus(ETH_DMADescType* DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMATXDESC_GET_FLAG(ETH_DMATxDescFlag)); + + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @param DMATxDesc pointer on a DMA Tx descriptor + * @return The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDmaTxDescCollisionCount(ETH_DMADescType* DMATxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMATxDesc->Status & ETH_DMA_TX_DESC_CC) >> ETH_DMA_TX_DESC_COLLISION_COUNTER_SHIFT); +} + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param DMATxDesc Pointer on a Tx desc + */ +void ETH_SetDmaTxDescOwn(ETH_DMADescType* DMATxDesc) +{ + /* Set the DMA Tx Desc Own bit */ + DMATxDesc->Status |= ETH_DMA_TX_DESC_OWN; +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc Pointer on a Tx desc + * @param Cmd new state of the DMA Tx Desc transmit interrupt. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaTxDescTransmitInt(ETH_DMADescType* DMATxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->CtrlOrBufSize |= ETH_DMA_TX_DESC_IC; + } + else + { + /* Disable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_TX_DESC_IC); + } +} + +/** + * @brief Set the specified DMA Tx Desc frame segment. + * @param DMATxDesc Pointer on a Tx desc + * @param DMATxDesc_FrameSegment specifies is the actual Tx desc contain last or first segment. + * This parameter can be one of the following values: + * @arg ETH_DMA_TX_DESC_LAST_SEGMENT actual Tx desc contain last segment + * @arg ETH_DMA_TX_DESC_FIRST_SEGMENT actual Tx desc contain first segment + */ +void ETH_ConfigDmaTxDescFrameSegment(ETH_DMADescType* DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TX_DESC_SEGMENT(DMATxDesc_FrameSegment)); + + /* Selects the DMA Tx Desc Frame segment */ + DMATxDesc->CtrlOrBufSize |= DMATxDesc_FrameSegment; +} + +/** + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @param DMATxDesc pointer on a DMA Tx descriptor + * @param DMATxDesc_Checksum specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMA_TX_DESC_CHECKSUM_BYPASS Checksum bypass + * @arg ETH_DMA_TX_DESC_CHECKSUM_IPV4_HEADER IPv4 header checksum + * @arg ETH_DMA_TX_DESC_CHECKSUM_TCPUDPICMP_SEGMENT TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be + * present + * @arg ETH_DMA_TX_DESC_CHECKSUM_TCPUDPICMP_FULL TCP/UDP/ICMP checksum fully in hardware including pseudo header + */ +void ETH_ConfigDmaTxDescChecksumInsertion(ETH_DMADescType* DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TX_DESC_CHECKSUM(DMATxDesc_Checksum)); + + /* Set the selected DMA Tx desc checksum insertion control */ + DMATxDesc->CtrlOrBufSize |= DMATxDesc_Checksum; +} + +/** + * @brief Enables or disables the DMA Tx Desc CRC. + * @param DMATxDesc pointer on a DMA Tx descriptor + * @param Cmd new state of the specified DMA Tx Desc CRC. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaTxDescCrc(ETH_DMADescType* DMATxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMA Tx Desc CRC */ + DMATxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_TX_DESC_DC); + } + else + { + /* Disable the selected DMA Tx Desc CRC */ + DMATxDesc->CtrlOrBufSize |= ETH_DMA_TX_DESC_DC; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc end of ring. + * @param DMATxDesc pointer on a DMA Tx descriptor + * @param Cmd new state of the specified DMA Tx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaTxDescEndOfRing(ETH_DMADescType* DMATxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMA Tx Desc end of ring */ + DMATxDesc->CtrlOrBufSize |= ETH_DMA_TX_DESC_TER; + } + else + { + /* Disable the selected DMA Tx Desc end of ring */ + DMATxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_TX_DESC_TER); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc second address chained. + * @param DMATxDesc pointer on a DMA Tx descriptor + * @param Cmd new state of the specified DMA Tx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaTxDescSecondAddrChained(ETH_DMADescType* DMATxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMA Tx Desc second address chained */ + DMATxDesc->CtrlOrBufSize |= ETH_DMA_TX_DESC_TCH; + } + else + { + /* Disable the selected DMA Tx Desc second address chained */ + DMATxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_TX_DESC_TCH); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param DMATxDesc pointer on a DMA Tx descriptor + * @param Cmd new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaTxDescShortFramePadding(ETH_DMADescType* DMATxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ + DMATxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_TX_DESC_DP); + } + else + { + /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ + DMATxDesc->CtrlOrBufSize |= ETH_DMA_TX_DESC_DP; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc time stamp. + * @param DMATxDesc pointer on a DMA Tx descriptor + * @param Cmd new state of the specified DMA Tx Desc time stamp. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaTxDescTimeStamp(ETH_DMADescType* DMATxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMA Tx Desc time stamp */ + DMATxDesc->CtrlOrBufSize |= ETH_DMA_TX_DESC_TTSE; + } + else + { + /* Disable the selected DMA Tx Desc time stamp */ + DMATxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_TX_DESC_TTSE); + } +} + +/** + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * @param DMATxDesc Pointer on a Tx desc + * @param BufferSize1 specifies the Tx desc buffer1 size. + * @param BufferSize2 specifies the Tx desc buffer2 size (put "0" if not used). + */ +void ETH_ConfigDmaTxDescBufSize(ETH_DMADescType* DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TX_DESC_BUFFER_SIZE(BufferSize1)); + assert_param(IS_ETH_DMA_TX_DESC_BUFFER_SIZE(BufferSize2)); + + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ + DMATxDesc->CtrlOrBufSize |= (BufferSize1 | (BufferSize2 << ETH_DMA_TX_DESC_BUF2_SIZE_SHIFT)); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab Pointer on the first Rx desc list + * @param RxBuff Pointer on the first RxBuffer list + * @param BuffSize the buffer size of each RxBuffer + * @param RxBuffCount Number of the used Rx desc in the list + */ +void ETH_ConfigDmaRxDescInChainMode(ETH_DMADescType* DMARxDescTab, + uint8_t* RxBuff, + uint32_t BuffSize, + uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADescType* DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for (i = 0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab + i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMA_RX_DESC_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->CtrlOrBufSize = ETH_DMA_RX_DESC_RCH | (uint32_t)(BuffSize & 0x1FFFUL); + /* Set Buffer1 address pointer */ + DMARxDesc->Buf1Addr = (uint32_t)(&RxBuff[i * BuffSize]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if (i < (RxBuffCount - 1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buf2OrNextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buf2OrNextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARXDLADDR = (uint32_t)DMARxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in ring mode. + * @param DMARxDescTab Pointer on the first Rx desc list + * @param RxBuff1 Pointer on the first RxBuffer1 list + * @param RxBuff2 Pointer on the first RxBuffer2 list + * @param BuffSize the buffer size of each RxBuffer + * @param RxBuffCount Number of the used Rx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + */ +void ETH_ConfigDmaRxDescInRingMode(ETH_DMADescType* DMARxDescTab, + uint8_t* RxBuff1, + uint8_t* RxBuff2, + uint32_t BuffSize, + uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADescType* DMARxDesc; + uint32_t dsl = (ETH->DMABUSMOD & ETH_DMABUSMOD_DSL) >> 2; + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for (i = 0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + // DMARxDesc = DMARxDescTab + i; + DMARxDesc = (ETH_DMADescType*)((uint32_t)DMARxDescTab + i * (16 + 4 * dsl)); + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMA_RX_DESC_OWN; + /* Set Buffer1 size */ + DMARxDesc->CtrlOrBufSize = BuffSize; + /* Set Buffer1 address pointer */ + DMARxDesc->Buf1Addr = (uint32_t)(&RxBuff1[i * BuffSize]); + + /* Set Buffer2 address pointer */ + DMARxDesc->Buf2OrNextDescAddr = (uint32_t)(&RxBuff2[i * BuffSize]); + + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if (i == (RxBuffCount - 1)) + { + /* Set Receive End of Ring bit */ + DMARxDesc->CtrlOrBufSize |= ETH_DMA_RX_DESC_RER; + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARXDLADDR = (uint32_t)DMARxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * @param DMARxDesc pointer on a DMA Rx descriptor + * @param ETH_DMARxDescFlag specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_RX_DESC_OWN OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMA_RX_DESC_AFM DA Filter Fail for the rx frame + * @arg ETH_DMA_RX_DESC_ES Error summary + * @arg ETH_DMA_RX_DESC_DE Desciptor error: no more descriptors for receive frame + * @arg ETH_DMA_RX_DESC_SAF SA Filter Fail for the received frame + * @arg ETH_DMA_RX_DESC_LE Frame size not matching with length field + * @arg ETH_DMA_RX_DESC_OE Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMA_RX_DESC_VLAN VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMA_RX_DESC_FS First descriptor of the frame + * @arg ETH_DMA_RX_DESC_LS Last descriptor of the frame + * @arg ETH_DMA_RX_DESC_IPV4HCE IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMA_RX_DESC_LC Late collision occurred during reception + * @arg ETH_DMA_RX_DESC_FT Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMA_RX_DESC_RWT Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMA_RX_DESC_RE Receive error: error reported by MII interface + * @arg ETH_DMA_RX_DESC_DE Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMA_RX_DESC_CE CRC error + * @arg ETH_DMA_RX_DESC_RMAPCE Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum + * Error + * @return The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDmaRxDescFlagStatus(ETH_DMADescType* DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_RX_DESC_GET_FLAG(ETH_DMARxDescFlag)); + if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param DMARxDesc Pointer on a Rx desc + */ +void ETH_SetDmaRxDescOwn(ETH_DMADescType* DMARxDesc) +{ + /* Set the DMA Rx Desc Own bit */ + DMARxDesc->Status |= ETH_DMA_RX_DESC_OWN; +} + +/** + * @brief Returns the specified DMA Rx Desc frame length. + * @param DMARxDesc pointer on a DMA Rx descriptor + * @return The Rx descriptor received frame length. + */ +uint32_t ETH_GetDmaRxDescFrameLen(__IO ETH_DMADescType* DMARxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMARxDesc->Status & ETH_DMA_RX_DESC_FL) >> ETH_DMA_RX_DESC_FRAME_LEN_SHIFT); +} + +/** + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * @param DMARxDesc Pointer on a Rx desc + * @param Cmd new state of the specified DMA Rx Desc interrupt. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaRxDescReceiveInt(ETH_DMADescType* DMARxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the DMA Rx Desc receive interrupt */ + DMARxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_RX_DESC_DIC); + } + else + { + /* Disable the DMA Rx Desc receive interrupt */ + DMARxDesc->CtrlOrBufSize |= ETH_DMA_RX_DESC_DIC; + } +} + +/** + * @brief Enables or disables the DMA Rx Desc end of ring. + * @param DMARxDesc pointer on a DMA Rx descriptor + * @param Cmd new state of the specified DMA Rx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaRxDescEndOfRing(ETH_DMADescType* DMARxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMA Rx Desc end of ring */ + DMARxDesc->CtrlOrBufSize |= ETH_DMA_RX_DESC_RER; + } + else + { + /* Disable the selected DMA Rx Desc end of ring */ + DMARxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_RX_DESC_RER); + } +} + +/** + * @brief Enables or disables the DMA Rx Desc second address chained. + * @param DMARxDesc pointer on a DMA Rx descriptor + * @param Cmd new state of the specified DMA Rx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaRxDescSecondAddrChained(ETH_DMADescType* DMARxDesc, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected DMA Rx Desc second address chained */ + DMARxDesc->CtrlOrBufSize |= ETH_DMA_RX_DESC_RCH; + } + else + { + /* Disable the selected DMA Rx Desc second address chained */ + DMARxDesc->CtrlOrBufSize &= (~(uint32_t)ETH_DMA_RX_DESC_RCH); + } +} + +/** + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * @param DMARxDesc pointer on a DMA Rx descriptor + * @param DMARxDesc_Buffer specifies the DMA Rx Desc buffer. + * This parameter can be any one of the following values: + * @arg ETH_DMA_RX_DESC_BUFFER1 DMA Rx Desc Buffer1 + * @arg ETH_DMA_RX_DESC_BUFFER2 DMA Rx Desc Buffer2 + * @return The Receive descriptor frame length. + */ +uint32_t ETH_GetDmaRxDescBufSize(ETH_DMADescType* DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); + + if (DMARxDesc_Buffer != ETH_DMA_RX_DESC_BUFFER1) + { + /* Return the DMA Rx Desc buffer2 size */ + return ((DMARxDesc->CtrlOrBufSize & ETH_DMA_RX_DESC_RBS2) >> ETH_DMA_RX_DESC_BUF2_SIZE_SHIFT); + } + else + { + /* Return the DMA Rx Desc buffer1 size */ + return (DMARxDesc->CtrlOrBufSize & ETH_DMA_RX_DESC_RBS1); + } +} + +/*--------------------------------- DMA ------------------------------------*/ +/** + * @brief Resets all MAC subsystem internal registers and logic. + */ +void ETH_SoftwareReset(void) +{ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH->DMABUSMOD |= ETH_DMABUSMOD_SWR; +} + +/** + * @brief Checks whether the ETHERNET software reset bit is set or not. + * @return The new state of DMA Bus Mode register STS bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if ((ETH->DMABUSMOD & ETH_DMABUSMOD_SWR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param ETH_DMA_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_FLAG_TST Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT PMT flag + * @arg ETH_DMA_FLAG_MMC MMC flag + * @arg ETH_DMA_FLAG_DATA_TRANSFER_ERROR Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_READ_WRITE_ERROR Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_ACCESS_ERROR Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_EARLY_RX Early receive flag + * @arg ETH_DMA_FLAG_FATAL_BUS_ERROR Fatal bus error flag + * @arg ETH_DMA_FLAG_EARLY_TX Early transmit flag + * @arg ETH_DMA_FLAG_RX_WDG_TIMEOUT Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RX_PROC_STOP Receive process stopped flag + * @arg ETH_DMA_FLAG_RX_BUF_UA Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RX Receive flag + * @arg ETH_DMA_FLAG_TX_UNDERFLOW Underflow flag + * @arg ETH_DMA_FLAG_RX_OVERFLOW Overflow flag + * @arg ETH_DMA_FLAG_TX_JABBER_TIMEOUT Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TX_BUF_UA Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TX_PROC_STOP Transmit process stopped flag + * @arg ETH_DMA_FLAG_TX Transmit flag + * @return The new state of ETH_DMA_FLAG (SET or RESET). + */ +FlagStatus ETH_GetDmaFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_INT(ETH_DMA_FLAG)); + if ((ETH->DMASTS & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET's DMA pending flag. + * @param ETH_DMA_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_FLAG_NIS Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_EARLY_RX Early receive flag + * @arg ETH_DMA_FLAG_FATAL_BUS_ERROR Fatal bus error flag + * @arg ETH_DMA_FLAG_ETI Early transmit flag + * @arg ETH_DMA_FLAG_RX_WDG_TIMEOUT Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RX_PROC_STOP Receive process stopped flag + * @arg ETH_DMA_FLAG_RX_BUF_UA Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RX Receive flag + * @arg ETH_DMA_FLAG_TX_UNDERFLOW Transmit Underflow flag + * @arg ETH_DMA_FLAG_RX_OVERFLOW Receive Overflow flag + * @arg ETH_DMA_FLAG_TX_JABBER_TIMEOUT Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TX_BUF_UA Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TX_PROC_STOP Transmit process stopped flag + * @arg ETH_DMA_FLAG_TX Transmit flag + */ +void ETH_ClrDmaFlag(uint32_t ETH_DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); + + /* Clear the selected ETHERNET DMA FLAG */ + ETH->DMASTS = (uint32_t)ETH_DMA_FLAG; +} + +/** + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * @param ETH_DMA_IT specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_INT_TST Time-stamp trigger interrupt + * @arg ETH_DMA_INT_PMT PMT interrupt + * @arg ETH_DMA_INT_MMC MMC interrupt + * @arg ETH_DMA_INT_NIS Normal interrupt summary + * @arg ETH_DMA_INT_AIS Abnormal interrupt summary + * @arg ETH_DMA_INT_EARLY_RX Early receive interrupt + * @arg ETH_DMA_INT_FATAL_BUS_ERROR Fatal bus error interrupt + * @arg ETH_DMA_INT_EARLY_TX Early transmit interrupt + * @arg ETH_DMA_INT_RX_WDG_TIMEOUT Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RX_PROC_STOP Receive process stopped interrupt + * @arg ETH_DMA_INT_RX_BUF_UA Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX Receive interrupt + * @arg ETH_DMA_INT_TX_UNDERFLOW Underflow interrupt + * @arg ETH_DMA_INT_RX_OVERFLOW Overflow interrupt + * @arg ETH_DMA_INT_TX_JABBER_TIMEOUT Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TX_BUF_UA Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TX_PROC_STOP Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX Transmit interrupt + * @return The new state of ETH_DMA_IT (SET or RESET). + */ +INTStatus ETH_GetDmaIntStatus(uint32_t ETH_DMA_IT) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_INT(ETH_DMA_IT)); + if ((ETH->DMASTS & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET's DMA IT pending bit. + * @param ETH_DMA_IT specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_INT_NIS Normal interrupt summary + * @arg ETH_DMA_INT_AIS Abnormal interrupt summary + * @arg ETH_DMA_INT_EARLY_RX Early receive interrupt + * @arg ETH_DMA_INT_FATAL_BUS_ERROR Fatal bus error interrupt + * @arg ETH_DMA_IT_ETI Early transmit interrupt + * @arg ETH_DMA_INT_RX_WDG_TIMEOUT Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RX_PROC_STOP Receive process stopped interrupt + * @arg ETH_DMA_INT_RX_BUF_UA Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX Receive interrupt + * @arg ETH_DMA_INT_TX_UNDERFLOW Transmit Underflow interrupt + * @arg ETH_DMA_INT_RX_OVERFLOW Receive Overflow interrupt + * @arg ETH_DMA_INT_TX_JABBER_TIMEOUT Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TX_BUF_UA Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TX_PROC_STOP Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX Transmit interrupt + */ +void ETH_ClrDmaIntPendingBit(uint32_t ETH_DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_INT(ETH_DMA_IT)); + + /* Clear the selected ETHERNET DMA IT */ + ETH->DMASTS = (uint32_t)ETH_DMA_IT; +} + +/** + * @brief Returns the ETHERNET DMA Transmit Process State. + * @return The new ETHERNET DMA Transmit Process State: + * This can be one of the following values: + * - ETH_DMA_TX_PROC_STOPPED : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TX_PROC_FETCHING : Running - fetching the Tx descriptor + * - ETH_DMA_TX_PROC_WAITING : Running - waiting for status + * - ETH_DMA_TX_PROC_READING : unning - reading the data from host memory + * - ETH_DMA_TX_PROC_SUSPENDED : Suspended - Tx Desciptor unavailabe + * - ETH_DMA_TX_PROC_CLOSING : Running - closing Rx descriptor + */ +uint32_t ETH_GetTxProcState(void) +{ + return ((uint32_t)(ETH->DMASTS & ETH_DMASTS_TI)); +} + +/** + * @brief Returns the ETHERNET DMA Receive Process State. + * @return The new ETHERNET DMA Receive Process State: + * This can be one of the following values: + * - ETH_DMA_RX_PROC_STOPPED : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_RX_PROC_FETCHING : Running - fetching the Rx descriptor + * - ETH_DMA_RX_PROC_WAITING : Running - waiting for packet + * - ETH_DMA_RX_PROC_SUSPENDED : Suspended - Rx Desciptor unavailable + * - ETH_DMA_RX_PROC_CLOSING : Running - closing descriptor + * - ETH_DMA_RX_PROC_QUEUING : Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetRxProcState(void) +{ + return ((uint32_t)(ETH->DMASTS & ETH_DMASTS_RI)); +} + +/** + * @brief Clears the ETHERNET transmit DATFIFO. + */ +void ETH_FlushTxFifo(void) +{ + /* Set the Flush Transmit DATFIFO bit */ + ETH->DMAOPMOD |= ETH_DMAOPMOD_FTF; +} + +/** + * @brief Checks whether the ETHERNET transmit DATFIFO bit is cleared or not. + * @return The new state of ETHERNET flush transmit DATFIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTxFifoStatus(void) +{ + FlagStatus bitstatus = RESET; + if ((ETH->DMAOPMOD & ETH_DMAOPMOD_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the DMA transmission. + * @param Cmd new state of the DMA transmission. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaTx(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the DMA transmission */ + ETH->DMAOPMOD |= ETH_DMAOPMOD_ST; + } + else + { + /* Disable the DMA transmission */ + ETH->DMAOPMOD &= ~ETH_DMAOPMOD_ST; + } +} + +/** + * @brief Enables or disables the DMA reception. + * @param Cmd new state of the DMA reception. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaRx(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the DMA reception */ + ETH->DMAOPMOD |= ETH_DMAOPMOD_SR; + } + else + { + /* Disable the DMA reception */ + ETH->DMAOPMOD &= ~ETH_DMAOPMOD_SR; + } +} + +/** + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * @param ETH_DMA_IT specifies the ETHERNET DMA interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_INT_NIS Normal interrupt summary + * @arg ETH_DMA_INT_AIS Abnormal interrupt summary + * @arg ETH_DMA_INT_EARLY_RX Early receive interrupt + * @arg ETH_DMA_INT_FATAL_BUS_ERROR Fatal bus error interrupt + * @arg ETH_DMA_INT_EARLY_TX Early transmit interrupt + * @arg ETH_DMA_INT_RX_WDG_TIMEOUT Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RX_PROC_STOP Receive process stopped interrupt + * @arg ETH_DMA_INT_RX_BUF_UA Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX Receive interrupt + * @arg ETH_DMA_INT_TX_UNDERFLOW Underflow interrupt + * @arg ETH_DMA_INT_RX_OVERFLOW Overflow interrupt + * @arg ETH_DMA_INT_TX_JABBER_TIMEOUT Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TX_BUF_UA Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TX_PROC_STOP Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX Transmit interrupt + * @param Cmd new state of the specified ETHERNET DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableDmaInt(uint32_t ETH_DMA_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_INT(ETH_DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH->DMAINTEN |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH->DMAINTEN &= (~(uint32_t)ETH_DMA_IT); + } +} + +/** + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @param ETH_DMA_Overflow specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_OVERFLOW_RX_FIFO_COUNTER Overflow for DATFIFO Overflow Counter + * @arg ETH_DMA_OVERFLOW_MISSED_FRAME_COUNTER Overflow for Missed Frame Counter + * @return The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDmaOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); + + if ((ETH->DMAMFBOCNT & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * @return The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCNT & ETH_DMAMFBOCNT_OVFFRMCNT) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTER_SHIFT)); +} + +/** + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * @return The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCNT) & ETH_DMAMFBOCNT_MISFRMCNT); +} + +/** + * @brief Get the ETHERNET DMA DMACHTXDESC register value. + * @return The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescAddr(void) +{ + return ((uint32_t)(ETH->DMACHTXDESC)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRXDESC register value. + * @return The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescAddr(void) +{ + return ((uint32_t)(ETH->DMACHRXDESC)); +} + +/** + * @brief Get the ETHERNET DMA DMACHTXBADDR register value. + * @return The value of the current Tx buffer address. + */ +uint32_t ETH_GetCurrentTxBufAddr(void) +{ + return ((uint32_t)(ETH->DMACHTXBADDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRXBADDR register value. + * @return The value of the current Rx buffer address. + */ +uint32_t ETH_GetCurrentRxBufAddr(void) +{ + return ((uint32_t)(ETH->DMACHRXBADDR)); +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register + * (the data written could be anything). This forces the DMA to resume transmission. + */ +void ETH_ResumeDmaTx(void) +{ + ETH->DMATXPD = 0; +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register + * (the data written could be anything). This forces the DMA to resume reception. + */ +void ETH_ResumeDmaRx(void) +{ + ETH->DMARXPD = 0; +} + +/*--------------------------------- PMT ------------------------------------*/ +/** + * @brief Reset Wakeup frame filter register pointer. + */ +void ETH_ResetWakeUpFrameFilter(void) +{ + /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ + ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_RWKUPFLTRST; +} + +/** + * @brief Populates the remote wakeup frame registers. + * @param Buffer Pointer on remote WakeUp Frame Filter Register buffer data (8 words). + */ +void ETH_SetWakeUpFrameFilter(uint32_t* Buffer) +{ + uint32_t i = 0; + + /* Fill Remote Wake-up Frame Filter register with Buffer data */ + for (i = 0; i < ETH_WAKEUP_REG_LEN; i++) + { + /* Write each time to the same register */ + ETH->MACRMTWUFRMFLT = Buffer[i]; + } +} + +/** + * @brief Enables or disables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param Cmd new state of the MAC Global Unicast Wake-Up. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableGlobalUnicastWakeUp(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_GLBLUCAST; + } + else + { + /* Disable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCTRLSTS &= ~ETH_MACPMTCTRLSTS_GLBLUCAST; + } +} + +/** + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @param ETH_PMT_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_RWKUPFILTRST Wake-Up Frame Filter Register Poniter Reset + * @arg ETH_PMT_FLAG_RWKPRCVD Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MGKPRCVD Magic Packet Received + * @return The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPmtFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); + + if ((ETH->MACPMTCTRLSTS & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * @param Cmd new state of the MAC Wake-Up Frame Detection. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableWakeUpFrameDetection(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_RWKPKTEN; + } + else + { + /* Disable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCTRLSTS &= ~ETH_MACPMTCTRLSTS_RWKPKTEN; + } +} + +/** + * @brief Enables or disables the MAC Magic Packet Detection. + * @param Cmd new state of the MAC Magic Packet Detection. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMagicPacketDetection(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_MGKPKTEN; + } + else + { + /* Disable the MAC Magic Packet Detection */ + ETH->MACPMTCTRLSTS &= ~ETH_MACPMTCTRLSTS_MGKPKTEN; + } +} + +/** + * @brief Enables or disables the MAC Power Down. + * @param Cmd new state of the MAC Power Down. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnablePowerDown(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_PWRDWN; + } + else + { + /* Disable the MAC Power Down */ + ETH->MACPMTCTRLSTS &= ~ETH_MACPMTCTRLSTS_PWRDWN; + } +} + +/*--------------------------------- MMC ------------------------------------*/ +/** + * @brief Enables or disables the MMC Counter Freeze. + * @param Cmd new state of the MMC Counter Freeze. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMmcCounterFreeze(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the MMC Counter Freeze */ + ETH->MMCCTRL |= ETH_MMCCTRL_CNTFREEZ; + } + else + { + /* Disable the MMC Counter Freeze */ + ETH->MMCCTRL &= ~ETH_MMCCTRL_CNTFREEZ; + } +} + +/** + * @brief Enables or disables the MMC Reset On Read. + * @param Cmd new state of the MMC Reset On Read. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMmcResetOnRead(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the MMC Counter reset on read */ + ETH->MMCCTRL |= ETH_MMCCTRL_RSTONRD; + } + else + { + /* Disable the MMC Counter reset on read */ + ETH->MMCCTRL &= ~ETH_MMCCTRL_RSTONRD; + } +} + +/** + * @brief Enables or disables the MMC Counter Stop Rollover. + * @param Cmd new state of the MMC Counter Stop Rollover. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMmcCounterRollover(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Disable the MMC Counter Stop Rollover */ + ETH->MMCCTRL &= ~ETH_MMCCTRL_CNTSTOPRO; + } + else + { + /* Enable the MMC Counter Stop Rollover */ + ETH->MMCCTRL |= ETH_MMCCTRL_CNTSTOPRO; + } +} + +/** + * @brief Resets the MMC Counters. + */ +void ETH_ResetMmcCounters(void) +{ + /* Resets the MMC Counters */ + ETH->MMCCTRL |= ETH_MMCCTRL_CNTRST; +} + +/** + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * @param ETH_MMC_IT specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_INT_TXGFRMIS When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_INT_TXMCOLGFIS When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_INT_TXSCOLGFIS When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_INT_RXUCGFIS When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_INT_RXALGNERFIS When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_INT_RXCRCERFIS When Rx crc error counter reaches half the maximum value + * @param Cmd new state of the specified ETHERNET MMC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_EnableMmcInt(uint32_t ETH_MMC_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_INT(ETH_MMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* Remove egister mak from IT */ + ETH_MMC_IT &= 0xEFFFFFFF; + + /* ETHERNET MMC Rx interrupts selected */ + if (Cmd != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCRXINTMSK &= (~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCRXINTMSK |= ETH_MMC_IT; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + if (Cmd != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCTXINTMSK &= (~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCTXINTMSK |= ETH_MMC_IT; + } + } +} + +/** + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * @param ETH_MMC_IT specifies the ETHERNET MMC interrupt. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TxFCGC When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TxMCGC When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TxSCGC When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RxUGFC When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RxAEC When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RxCEC When Rx crc error counter reaches half the maximum value + * @return The value of ETHERNET MMC IT (SET or RESET). + */ +INTStatus ETH_GetMmcIntStatus(uint32_t ETH_MMC_IT) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MMC_GET_INT(ETH_MMC_IT)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* ETHERNET MMC Rx interrupts selected */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + if ((((ETH->MMCRXINT & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRXINTMSK & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + if ((((ETH->MMCTXINT & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRXINTMSK & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Get the specified ETHERNET MMC register value. + * @param ETH_MMCReg specifies the ETHERNET MMC register. + * This parameter can be one of the following values: + * @arg ETH_MMCCTRL MMC CTRL register + * @arg ETH_MMCRXINT MMC RIR register + * @arg ETH_MMCTXINT MMC TIR register + * @arg ETH_MMCRXINTMSK MMC RIMR register + * @arg ETH_MMCTXINTMSK MMC TIMR register + * @arg ETH_MMCTXGFASCCNT MMC TGFSCCR register + * @arg ETH_MMCTXGFAMSCCNT MMC TGFMSCCR register + * @arg ETH_MMCTXGFCNT MMC TGFCR register + * @arg ETH_MMCRXFCECNT MMC RFCECR register + * @arg ETH_MMCRXFAECNT MMC RFAECR register + * @arg ETH_MMCRXGUFCNT MMC RGUFCRregister + * @return The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMmcRegisterValue(uint32_t ETH_MMCReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t*)(ETH_MAC_BASE + ETH_MMCReg)); +} +/*--------------------------------- PTP ------------------------------------*/ + +/** + * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. + */ +void ETH_UpdatePtpTimeStampAddend(void) +{ + /* Enable the PTP block update with the Time Stamp Addend register value */ + ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSADDREG; +} + +/** + * @brief Enable the PTP Time Stamp interrupt trigger + */ +void ETH_EnablePtpTimeStampIntTrigger(void) +{ + /* Enable the PTP target time interrupt */ + ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSTRIG; +} + +/** + * @brief Updated the PTP system time with the Time Stamp Update register value. + */ +void ETH_UpdatePtpTimeStamp(void) +{ + /* Enable the PTP system time update with the Time Stamp Update register value */ + ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSUPDT; +} + +/** + * @brief Initialize the PTP Time Stamp + */ +void ETH_InitPtpTimeStamp(void) +{ + /* Initialize the PTP Time Stamp */ + ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSINIT; +} + +/** + * @brief Selects the PTP Update method + * @param UpdateMethod the PTP Update method + * This parameter can be one of the following values: + * @arg ETH_PTP_FINE_UPDATE Fine Update method + * @arg ETH_PTP_COARSE_UPDATE Coarse Update method + */ +void ETH_ConfigPtpUpdateMethod(uint32_t UpdateMethod) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); + + if (UpdateMethod != ETH_PTP_COARSE_UPDATE) + { + /* Enable the PTP Fine Update method */ + ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSCFUPDT; + } + else + { + /* Disable the PTP Coarse Update method */ + ETH->PTPTSCTRL &= (~(uint32_t)ETH_PTPTSCTRL_TSCFUPDT); + } +} + +/** + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * @param Cmd new state of the PTP time stamp for transmit and receive frames + * This parameter can be: ENABLE or DISABLE. + */ +void ETH_StartPTPTimeStamp(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSENA; + } + else + { + /* Disable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCTRL &= (~(uint32_t)ETH_PTPTSCTRL_TSENA); + } +} + +/** + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * @param ETH_PTP_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PTP_FLAG_TSADDREG Addend Register Update + * @arg ETH_PTP_FLAG_TSTRIG Time Stamp Interrupt Trigger Enable + * @arg ETH_PTP_FLAG_TSUPDT Time Stamp Update + * @arg ETH_PTP_FLAG_TSINIT Time Stamp Initialize + * @return The new state of ETHERNET PTP Flag (SET or RESET). + */ +FlagStatus ETH_GetPtpFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); + + if ((ETH->PTPTSCTRL & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Sets the system time Sub-Second Increment value. + * @param SubSecondValue specifies the PTP Sub-Second Increment Register value. + */ +void ETH_SetPtpSubSecondInc(uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); + /* Set the PTP Sub-Second Increment Register */ + ETH->PTPSSINC = SubSecondValue; +} + +/** + * @brief Sets the Time Stamp update sign and values. + * @param Sign specifies the PTP Time update value sign. + * This parameter can be one of the following values: + * @arg ETH_PTP_POSITIVE_TIME positive time value. + * @arg ETH_PTP_NEGATIVE_TIME negative time value. + * @param SecondValue specifies the PTP Time update second value. + * @param SubSecondValue specifies the PTP Time update sub-second value. + * This parameter is a 31 bit value, bit32 correspond to the sign. + */ +void ETH_SetPtpTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + /* Set the PTP Time Update High Register */ + ETH->PTPSECUP = SecondValue; + + /* Set the PTP Time Update Low Register with sign */ + ETH->PTPNSUP = Sign | SubSecondValue; +} + +/** + * @brief Sets the Time Stamp Addend value. + * @param Value specifies the PTP Time Stamp Addend Register value. + */ +void ETH_SetPtpTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSADD = Value; +} + +/** + * @brief Sets the Target Time registers values. + * @param HighValue specifies the PTP Target Time High Register value. + * @param LowValue specifies the PTP Target Time Low Register value. + */ +void ETH_SetPtpTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + /* Set the PTP Target Time High Register */ + ETH->PTPTTSEC = HighValue; + /* Set the PTP Target Time Low Register */ + ETH->PTPTTNS = LowValue; +} + +/** + * @brief Get the specified ETHERNET PTP register value. + * @param ETH_PTPReg specifies the ETHERNET PTP register. + * This parameter can be one of the following values: + * @arg ETH_PTPTSCTRL Sub-Second Increment Register + * @arg ETH_PTPSSINC Sub-Second Increment Register + * @arg ETH_PTPSEC Time Stamp High Register + * @arg ETH_PTPNS Time Stamp Low Register + * @arg ETH_PTPSECUP Time Stamp High Update Register + * @arg ETH_PTPNSUP Time Stamp Low Update Register + * @arg ETH_PTPTSADD Time Stamp Addend Register + * @arg ETH_PTPTTSEC Target Time High Register + * @arg ETH_PTPTTNS Target Time Low Register + * @return The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPtpRegisterValue(uint32_t ETH_PTPReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t*)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * @param DMATxDescTab Pointer on the first Tx desc list + * @param DMAPTPTxDescTab Pointer on the first PTP Tx desc list + * @param TxBuff Pointer on the first TxBuffer list + * @param TxBuffCount Number of the used Tx desc in the list + */ +void ETH_ConfigDmaPtpTxDescInChainMode(ETH_DMADescType* DMATxDescTab, + ETH_DMADescType* DMAPTPTxDescTab, + uint8_t* TxBuff, + uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADescType* DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Second Address Chained bit and enable PTP */ + DMATxDesc->Status = 0; + DMATxDesc->CtrlOrBufSize = ETH_DMA_TX_DESC_TCH | ETH_DMA_TX_DESC_TTSE; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buf1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if (i < (TxBuffCount - 1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buf2OrNextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buf2OrNextDescAddr = (uint32_t)DMATxDescTab; + } + /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */ + (&DMAPTPTxDescTab[i])->Buf1Addr = DMATxDesc->Buf1Addr; + (&DMAPTPTxDescTab[i])->Buf2OrNextDescAddr = DMATxDesc->Buf2OrNextDescAddr; + } + /* Store on the last DMAPTPTxDescTab desc status record the first list address */ + (&DMAPTPTxDescTab[i - 1])->Status = (uint32_t)DMAPTPTxDescTab; + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATXDLADDR = (uint32_t)DMATxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab Pointer on the first Rx desc list + * @param DMAPTPRxDescTab Pointer on the first PTP Rx desc list + * @param RxBuff Pointer on the first RxBuffer list + * @param RxBuffCount Number of the used Rx desc in the list + */ +void ETH_ConfigDmaPtpRxDescInChainMode(ETH_DMADescType* DMARxDescTab, + ETH_DMADescType* DMAPTPRxDescTab, + uint8_t* RxBuff, + uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADescType* DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for (i = 0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab + i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMA_RX_DESC_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->CtrlOrBufSize = ETH_DMA_RX_DESC_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buf1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if (i < (RxBuffCount - 1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buf2OrNextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buf2OrNextDescAddr = (uint32_t)(DMARxDescTab); + } + /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */ + (&DMAPTPRxDescTab[i])->Buf1Addr = DMARxDesc->Buf1Addr; + (&DMAPTPRxDescTab[i])->Buf2OrNextDescAddr = DMARxDesc->Buf2OrNextDescAddr; + } + /* Store on the last DMAPTPRxDescTab desc status record the first list address */ + (&DMAPTPRxDescTab[i - 1])->Status = (uint32_t)DMAPTPRxDescTab; + + /* Set Receive Desciptor List Address Register */ + ETH->DMARXDLADDR = (uint32_t)DMARxDescTab; +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. + * @param ppkt pointer to application packet buffer to transmit. + * @param FrameLength Tx Packet size. + * @param PTPTxTab Pointer on the first PTP Tx table to store Time stamp values. + * @return ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_TxPtpPacket(uint8_t* ppkt, uint16_t FrameLength, uint32_t* PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if ((DMATxDescToSet->Status & ETH_DMA_TX_DESC_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for (offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t*)((DMAPTPTxDescToSet->Buf1Addr) + offset)) = (*(ppkt + offset)); + } + /* Setting the Frame Length: bits[10:0] */ + DMATxDescToSet->CtrlOrBufSize &= (~ETH_DMA_TX_DESC_TBS1); + DMATxDescToSet->CtrlOrBufSize |= (FrameLength & ETH_DMA_TX_DESC_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->CtrlOrBufSize |= ETH_DMA_TX_DESC_LS | ETH_DMA_TX_DESC_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMA_TX_DESC_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASTS & ETH_DMASTS_TU) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASTS = ETH_DMASTS_TU; + /* Resume DMA transmission*/ + ETH->DMATXPD = 0; + } + /* Wait for ETH_DMA_TX_DESC_TTSS flag to be set */ + do + { + timeout++; + } while (!(DMATxDescToSet->Status & ETH_DMA_TX_DESC_TTSS) && (timeout < 0xFFFF)); + /* Return ERROR in case of timeout */ + if (timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Clear the DMATxDescToSet status register TTSS flag */ + DMATxDescToSet->Status &= ~ETH_DMA_TX_DESC_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buf1Addr; + *PTPTxTab = DMATxDescToSet->Buf2OrNextDescAddr; + /* Update the ENET DMA current descriptor */ + /* Chained Mode */ + if ((DMATxDescToSet->CtrlOrBufSize & ETH_DMA_TX_DESC_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADescType*)(DMAPTPTxDescToSet->Buf2OrNextDescAddr); + if (DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADescType*)(DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else /* Ring Mode */ + { + if ((DMATxDescToSet->CtrlOrBufSize & ETH_DMA_TX_DESC_TER) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read: this will + be the first Tx descriptor in this case */ + DMATxDescToSet = (ETH_DMADescType*)(ETH->DMATXDLADDR); + DMAPTPTxDescToSet = (ETH_DMADescType*)(ETH->DMATXDLADDR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = + (ETH_DMADescType*)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABUSMOD & ETH_DMABUSMOD_DSL))); + DMAPTPTxDescToSet = + (ETH_DMADescType*)((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABUSMOD & ETH_DMABUSMOD_DSL))); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. + * @param ppkt pointer to application packet receive buffer. + * @param PTPRxTab Pointer on the first PTP Rx table to store Time stamp values. + * @return ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_RxPtpPacket(uint8_t* ppkt, uint32_t* PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ENET or CPU */ + if ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + if (((DMARxDescToGet->Status & ETH_DMA_RX_DESC_ES) == (uint32_t)RESET) + && ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_LS) != (uint32_t)RESET) + && ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMA_RX_DESC_FL) >> ETH_DMA_RX_DESC_FRAME_LEN_SHIFT) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for (offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t*)((DMAPTPRxDescToGet->Buf1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASTS & ETH_DMASTS_RU) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASTS = ETH_DMASTS_RU; + /* Resume DMA reception */ + ETH->DMARXPD = 0; + } + *PTPRxTab++ = DMARxDescToGet->Buf1Addr; + *PTPRxTab = DMARxDescToGet->Buf2OrNextDescAddr; + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status |= ETH_DMA_RX_DESC_OWN; + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if ((DMARxDescToGet->CtrlOrBufSize & ETH_DMA_RX_DESC_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADescType*)(DMAPTPRxDescToGet->Buf2OrNextDescAddr); + if (DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADescType*)(DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else /* Ring Mode */ + { + if ((DMARxDescToGet->CtrlOrBufSize & ETH_DMA_RX_DESC_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADescType*)(ETH->DMARXDLADDR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = + (ETH_DMADescType*)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABUSMOD & ETH_DMABUSMOD_DSL))); + } + } + /* Return Frame Length/ERROR */ + return (framelength); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_exti.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_exti.c new file mode 100644 index 0000000000..94e3598f0a --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_exti.c @@ -0,0 +1,286 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_exti.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_exti.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @addtogroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + */ +void EXTI_DeInit(void) +{ + EXTI->IMASK = 0x00000000; + EXTI->EMASK = 0x00000000; + EXTI->RT_CFG = 0x00000000; + EXTI->FT_CFG = 0x00000000; + EXTI->PEND = 0x000FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a EXTI_InitType structure + * that contains the configuration information for the EXTI peripheral. + */ +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line; + EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will + * be initialized. + */ +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + */ +void EXTI_TriggerSWInt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIE |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex External interrupt line x where x(0..19) + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + */ +void EXTI_ClrStatusFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PEND = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex External interrupt line x where x(0..19) + * @return The new state of EXTI_Line (SET or RESET). + */ +INTStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + INTStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMASK & EXTI_Line; + if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + */ +void EXTI_ClrITPendBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PEND = EXTI_Line; +} + +/** + * @brief Select one of EXTI inputs to the RTC TimeStamp event. + * @param EXTI_TSSEL_Line specifies the EXTI lines to select. + * This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15). + */ +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line)); + + EXTI->TSSEL &= EXTI_TSSEL_TSSEL_ALL; + EXTI->TSSEL |= EXTI_TSSEL_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_flash.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_flash.c new file mode 100644 index 0000000000..d0f612a1bf --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_flash.c @@ -0,0 +1,1124 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_flash.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_flash.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @addtogroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define AC_LATENCY_MSK ((uint32_t)0x000000F8) +#define AC_PRFTBE_MSK ((uint32_t)0xFFFFFFEF) +#define AC_ICAHEN_MSK ((uint32_t)0xFFFFFF7F) + +/* Flash Access Control Register bits */ +#define AC_PRFTBS_MSK ((uint32_t)0x00000020) +#define AC_ICAHRST_MSK ((uint32_t)0x00000040) + +/* Flash Control Register bits */ +#define CTRL_Set_PG ((uint32_t)0x00000001) +#define CTRL_Reset_PG ((uint32_t)0x00003FFE) +#define CTRL_Set_PER ((uint32_t)0x00000002) +#define CTRL_Reset_PER ((uint32_t)0x00003FFD) +#define CTRL_Set_MER ((uint32_t)0x00000004) +#define CTRL_Reset_MER ((uint32_t)0x00003FFB) +#define CTRL_Set_OPTPG ((uint32_t)0x00000010) +#define CTRL_Reset_OPTPG ((uint32_t)0x00003FEF) +#define CTRL_Set_OPTER ((uint32_t)0x00000020) +#define CTRL_Reset_OPTER ((uint32_t)0x00003FDF) +#define CTRL_Set_START ((uint32_t)0x00000040) +#define CTRL_Set_LOCK ((uint32_t)0x00000080) +#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF) +#define CTRL_SMPSEL_SMP1 ((uint32_t)0x00000000) +#define CTRL_SMPSEL_SMP2 ((uint32_t)0x00000100) + +/* FLASH Mask */ +#define RDPRTL1_MSK ((uint32_t)0x00000002) +#define RDPRTL2_MSK ((uint32_t)0x80000000) +#define OBR_USER_MSK ((uint32_t)0x0000001C) +#define WRP0_MSK ((uint32_t)0x000000FF) +#define WRP1_MSK ((uint32_t)0x0000FF00) +#define WRP2_MSK ((uint32_t)0x00FF0000) +#define WRP3_MSK ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define L1_RDP_Key ((uint32_t)0xFFFF00A5) +#define RDP_USER_Key ((uint32_t)0xFFF800A5) +#define L2_RDP_Key ((uint32_t)0xFFFF33CC) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Sets the code latency value. + * @note This function can be used for N32G45X devices. + * @param FLASH_Latency specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle + * @arg FLASH_LATENCY_1 FLASH One Latency cycle + * @arg FLASH_LATENCY_2 FLASH Two Latency cycles + * @arg FLASH_LATENCY_3 FLASH Three Latency cycles + * @arg FLASH_LATENCY_4 FLASH Four Latency cycles + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the AC register */ + tmpregister = FLASH->AC; + + /* Sets the Latency value */ + tmpregister &= AC_LATENCY_MSK; + tmpregister |= FLASH_Latency; + + /* Write the AC register */ + FLASH->AC = tmpregister; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for N32G45X devices. + * @param FLASH_PrefetchBuf specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable + */ +void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->AC &= AC_PRFTBE_MSK; + FLASH->AC |= FLASH_PrefetchBuf; +} + +/** + * @brief ICache Reset. + * @note This function can be used for N32G45X devices. + */ +void FLASH_iCacheRST(void) +{ + /* ICache Reset */ + FLASH->AC |= FLASH_AC_ICAHRST; +} + +/** + * @brief Enables or disables the iCache. + * @note This function can be used for N32G45X devices. + * @param FLASH_iCache specifies the iCache status. + * This parameter can be one of the following values: + * @arg FLASH_iCache_EN FLASH iCache Enable + * @arg FLASH_iCache_DIS FLASH iCache Disable + */ +void FLASH_iCacheCmd(uint32_t FLASH_iCache) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache)); + + /* Enable or disable the iCache */ + FLASH->AC &= AC_ICAHEN_MSK; + FLASH->AC |= FLASH_iCache; +} + +/** + * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2. + * @note This function can be used for N32G45X devices. + * @param FLASH_smpsel FLASH_SMP1 or FLASH_SMP2 + * @return FLASH SMPSEL (FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2). + */ +void FLASH_SetSMPSELStatus(FLASH_SMPSEL FLASH_smpsel) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel)); + + /* SMP1 or SMP2 */ + FLASH->CTRL &= CTRL_Reset_SMPSEL; + FLASH->CTRL |= FLASH_smpsel; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for N32G45X devices. + * - For N32G45X devices this function unlocks Bank1. + * to FLASH_UnlockBank1 function.. + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEY = FLASH_KEY1; + FLASH->KEY = FLASH_KEY2; +} + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for N32G45X devices. + * - For N32G45X devices this function Locks Bank1. + * to FLASH_LockBank1 function. + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the CTRL of Bank1 */ + FLASH->CTRL |= CTRL_Set_LOCK; +} + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for N32G45X devices. + * @param Page_Address The page address to be erased. + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address) +{ + FLASH_STS status = FLASH_COMPL; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CTRL |= CTRL_Set_PER; + FLASH->ADD = Page_Address; + FLASH->CTRL |= CTRL_Set_START; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CTRL &= CTRL_Reset_PER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all N32G45X devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_MassErase(void) +{ + FLASH_STS status = FLASH_COMPL; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CTRL |= CTRL_Set_MER; + FLASH->CTRL |= CTRL_Set_START; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CTRL &= CTRL_Reset_MER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for N32G45X devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EraseOB(void) +{ + uint32_t rdptmp = L1_RDP_Key; + + FLASH_STS status = FLASH_COMPL; + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdptmp = (L1_RDP_Key & FLASH_USER_USER); + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + /* Restore the last read protection Option Byte value */ + OB->USER_RDP = (uint32_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for N32G45X devices. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_STS status = FLASH_COMPL; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + if((Address & (uint32_t)0x3) != 0) + { + /* The programming address is not a multiple of 4 */ + status = FLASH_ERR_ADD; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to program the new word */ + FLASH->CTRL |= CTRL_Set_PG; + + *(__IO uint32_t*)Address = (uint32_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CTRL &= CTRL_Reset_PG; + } + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for N32G45X devices. + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804. + * @param Data specifies the data to be programmed(Data0 and Data1). + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data) +{ + FLASH_STS status = FLASH_COMPL; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + if (status == FLASH_COMPL) + { + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + *(__IO uint32_t*)Address = (uint32_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for N32G45X devices. + * @param FLASH_Pages specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b N32G45X_devices: value between FLASH_WRP_Pages0to1 and + * FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to255 + * @arg FLASH_WRP_AllPages + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_MSK); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24); + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTPG; + + if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF)) + { + OB->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL)) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + OB->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for N32G45X devices. + * @param Cmd new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd) +{ + uint32_t usertmp; + FLASH_STS status = FLASH_COMPL; + + usertmp = ((OBR_USER_MSK & FLASH->OBR) << 0x0E); + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + if (Cmd != DISABLE) + { + OB->USER_RDP = (FLASH_USER_USER & usertmp); + } + else + { + OB->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection L2. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for N32G45X devices. + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void) +{ + uint32_t usertmp; + FLASH_STS status = FLASH_COMPL; + + usertmp = ((OBR_USER_MSK & FLASH->OBR) << 0x0E); + + /* Get the actual read protection L1 Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() == RESET) + { + usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1); + } + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + + OB->USER_RDP = usertmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* Enables the read out protection L2 */ + OB->RDP2 = L2_RDP_Key; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + } + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for N32G45X devices. + * @param OB_IWDG Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW Software IWDG selected + * @arg OB_IWDG_HW Hardware IWDG selected + * @param OB_STOP Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP0_NORST No reset generated when entering in STOP + * @arg OB_STOP0_RST Reset generated when entering in STOP + * @param OB_STDBY Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg OB_STDBY_RST Reset generated when entering in STANDBY + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_ConfigUserOB(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + uint32_t rdptmp = RDP_USER_Key; + + FLASH_STS status = FLASH_COMPL; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP0_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_GetReadOutProtectionL2STS() != RESET) + { + status = FLASH_ERR_RDP2; + return status; + } + + /* Get the actual read protection Option Byte value */ + if (FLASH_GetReadOutProtectionSTS() != RESET) + { + rdptmp = 0xFFF80000; + } + + /* Authorize the small information block programming */ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; + + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= CTRL_Set_OPTER; + FLASH->CTRL |= CTRL_Set_START; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(EraseTimeout); + + if (status == FLASH_COMPL) + { + /* Clears the FLASH's pending flags */ + FLASH_ClearFlag(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= CTRL_Set_OPTPG; + /* Restore the last read protection Option Byte value */ + OB->USER_RDP = + (uint32_t)rdptmp + | ((uint32_t)(OB_IWDG | (uint32_t)(OB_STOP | (uint32_t)(OB_STDBY | ((uint32_t)0xF8)))) << 16); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOpt(ProgramTimeout); + + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= CTRL_Reset_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= CTRL_Reset_OPTER; + } + } + } + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for N32G45X devices. + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOB(void) +{ + /* Return the User Option Byte */ + return (uint32_t)((FLASH->OBR << 27) >> 29); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for N32G45X devices. + * @return The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOB(void) +{ + /* Return the Flash write protection Register value */ + return (uint32_t)(FLASH->WRP); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for N32G45X devices. + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionSTS(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRTL1_MSK) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Read Out Protection L2 Status is set or not. + * @note This function can be used for N32G45x devices. + * @return FLASH ReadOut Protection L2 Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionL2STS(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRTL2_MSK) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for N32G45X devices. + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufSTS(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2. + * @note This function can be used for N32G45X devices. + * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2). + */ +FLASH_SMPSEL FLASH_GetSMPSELStatus(void) +{ + FLASH_SMPSEL bitstatus = FLASH_SMP1; + + if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1) + { + bitstatus = FLASH_SMP2; + } + else + { + bitstatus = FLASH_SMP1; + } + /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for N32G45X devices. + * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR FLASH Error Interrupt + * @arg FLASH_INT_FERR EVERR PVERR Interrupt + * @arg FLASH_INT_EOP FLASH end of operation Interrupt + * @param Cmd new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FLASH_INT(FLASH_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CTRL |= FLASH_INT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CTRL &= ~(uint32_t)FLASH_INT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for N32G45X devices. + * @param FLASH_FLAG specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BUSY FLASH Busy flag + * @arg FLASH_FLAG_PGERR FLASH Program error flag + * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag + * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg FLASH_FLAG_EOP FLASH End of Operation flag + * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag + * @arg FLASH_FLAG_OBERR FLASH Option Byte error flag + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + if (FLASH_FLAG == FLASH_FLAG_OBERR) + { + if ((FLASH->OBR & FLASH_FLAG_OBERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @note This function can be used for N32G45X devices. + * @param FLASH_FLAG specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR FLASH Program error flag + * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag + * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg FLASH_FLAG_EOP FLASH End of Operation flag + * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->STS |= FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for N32G45X devices, it is equivalent + * to FLASH_GetBank1Status function. + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_GetSTS(void) +{ + FLASH_STS flashstatus = FLASH_COMPL; + + if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERR_PG; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PVERR) != 0) + { + flashstatus = FLASH_ERR_PV; + } + else + { + if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0) + { + flashstatus = FLASH_ERR_WRP; + } + else + { + if ((FLASH->STS & FLASH_FLAG_EVERR) != 0) + { + flashstatus = FLASH_ERR_EV; + } + else + { + flashstatus = FLASH_COMPL; + } + } + } + } + } + + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for N32G45X devices, + * it is equivalent to FLASH_WaitForLastBank1Operation.. + * @param Timeout FLASH programming Timeout + * @return FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL, + * FLASH_ERR_EV or FLASH_TIMEOUT. + */ +FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout) +{ + FLASH_STS status = FLASH_COMPL; + + /* Check for the Flash Status */ + status = FLASH_GetSTS(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while ((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetSTS(); + Timeout--; + } + if (Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_gpio.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_gpio.c new file mode 100644 index 0000000000..6a0400d4db --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_gpio.c @@ -0,0 +1,873 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_gpio.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_gpio.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @addtogroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- Event control register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + +/* --- RMP_CFG Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define MAPR_OFFSET (AFIO_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((u8)0x17) +#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +#define DBGAFR_NUMBITS_MAPR3_MASK ((uint32_t)0x40000000) +#define DBGAFR_NUMBITS_MAPR4_MASK ((uint32_t)0x20000000) +#define DBGAFR_NUMBITS_MAPR5_MASK ((uint32_t)0x10000000) +#define DBGAFR_NUMBITS_SPI1_MASK ((uint32_t)0x01000000) +#define DBGAFR_NUMBITS_USART2_MASK ((uint32_t)0x04000000) + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + */ +void GPIO_DeInit(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOE, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOF, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOF, DISABLE); + } + else if (GPIOx == GPIOG) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOG, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOG, DISABLE); + } + else + { + } +} + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + */ +void GPIO_AFIOInitDefault(void) +{ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_InitStruct pointer to a GPIO_InitType structure that + * contains the configuration information for the specified GPIO peripheral. + */ +void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpregister = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin)); + + /*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + /*---------------------------- GPIO PL_CFG Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpregister = GPIOx->PL_CFG; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpregister &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpregister |= (currentmode << pos); + /* Reset the corresponding POD bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->PBC = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding POD bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->PBSC = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->PL_CFG = tmpregister; + } + /*---------------------------- GPIO PH_CFG Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->Pin > 0x00FF) + { + tmpregister = GPIOx->PH_CFG; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpregister &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpregister |= (currentmode << pos); + /* Reset the corresponding POD bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->PBC = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding POD bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->PBSC = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->PH_CFG = tmpregister; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will + * be initialized. + */ +void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = GPIO_PIN_ALL; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @param Pin specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + + if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @return GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->PID); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @param Pin specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @return The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + + if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @return GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->POD); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @param Pin specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBSC = Pin; +} +void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + // assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBSC = Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @param Pin specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + GPIOx->PBC = Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @param Pin specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitCmd specifies the value to be written to the selected bit. + * This parameter can be one of the Bit_OperateType enum values: + * @arg Bit_RESET to clear the port pin + * @arg Bit_SET to set the port pin + */ +void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(Pin)); + assert_param(IS_GPIO_BIT_OPERATE(BitCmd)); + + if (BitCmd != Bit_RESET) + { + GPIOx->PBSC = Pin; + } + else + { + GPIOx->PBC = Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @param PortVal specifies the value to be written to the port output data register. + */ +void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->POD = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx where x can be (A..G) to select the GPIO peripheral. + * @param Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + */ +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(Pin)); + + tmp |= Pin; + /* Set LCKK bit */ + GPIOx->PLOCK_CFG = tmp; + /* Reset LCKK bit */ + GPIOx->PLOCK_CFG = Pin; + /* Set LCKK bit */ + GPIOx->PLOCK_CFG = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->PLOCK_CFG; + /* Read LCKK bit*/ + tmp = GPIOx->PLOCK_CFG; +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param PortSource selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * @param PinSource specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + */ +void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource) +{ + uint32_t tmpregister = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + + tmpregister = AFIO->ECTRL; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpregister &= EVCR_PORTPINCONFIG_MASK; + tmpregister |= (uint32_t)PortSource << 0x04; + tmpregister |= PinSource; + AFIO->ECTRL = tmpregister; +} + +/** + * @brief Enables or disables the Event Output. + * @param Cmd new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + */ +void GPIO_CtrlEventOutput(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param RmpPin selects the pin to remap. + * This parameter can be one of the following values: + * @arg GPIO_RMP_SPI1 SPI1 Alternate Function mapping + * @arg GPIO_RMP_I2C1 I2C1 Alternate Function mapping + * @arg GPIO_RMP_USART1 USART1 Alternate Function mapping + * @arg GPIO_RMP_USART2 USART2 Alternate Function mapping + * @arg GPIO_PART_RMP_USART3 USART3 Partial Alternate Function mapping + * @arg GPIO_ALL_RMP_USART3 USART3 Full Alternate Function mapping + * @arg GPIO_PART1_RMP_TIM1 TIM1 Partial Alternate Function mapping + * @arg GPIO_PART2_RMP_TIM1 TIM1 Partial Alternate Function mapping + * @arg GPIO_ALL_RMP_TIM1 TIM1 Full Alternate Function mapping + * @arg GPIO_PartialRemap1_TIM2 TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PART2_RMP_TIM2 TIM2 Partial2 Alternate Function mapping + * @arg GPIO_ALL_RMP_TIM2 TIM2 Full Alternate Function mapping + * @arg GPIO_PART1_RMP_TIM3 TIM3 Partial Alternate Function mapping + * @arg GPIO_ALL_RMP_TIM3 TIM3 Full Alternate Function mapping + * @arg GPIO_RMP_TIM4 TIM4 Alternate Function mapping + * @arg GPIO_RMP1_CAN1 CAN1 Alternate Function mapping + * @arg GPIO_RMP2_CAN1 CAN1 Alternate Function mapping + * @arg GPIO_RMP3_CAN1 CAN1 Alternate Function mapping + * @arg GPIO_RMP_PD01 PD01 Alternate Function mapping + * @arg GPIO_RMP_TIM5CH4 LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_RMP_ADC1_ETRI ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_RMP_ADC1_ETRR ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_RMP_ADC2_ETRI ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_RMP_ADC2_ETRR ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_RMP_SW_JTAG_NO_NJTRST Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * @arg GPIO_RMP_SW_JTAG_SW_ENABLE JTAG-DP Disabled and SW-DP Enabled + * @arg GPIO_RMP_SW_JTAG_DISABLE Full SWJ Disabled (JTAG-DP + SW-DP) + * @arg GPIO_Remap_XFMC_NADV XFMC NADV Alternate Function mapping + * @arg GPIO_RMP_SDIO SDIO Alternate Function mapping + * @arg GPIO_RMP1_CAN2 CAN2 Alternate Function mapping + * @arg GPIO_RMP3_CAN2 CAN2 Alternate Function mapping + * @arg GPIO_RMP1_QSPI QSPI Alternate Function mapping + * @arg GPIO_RMP3_QSPI QSPI Alternate Function mapping + * @arg GPIO_RMP1_I2C2 I2C2 Alternate Function mapping + * @arg GPIO_RMP3_I2C2 I2C2 Alternate Function mapping + * @arg GPIO_RMP2_I2C3 I2C3 Alternate Function mapping + * @arg GPIO_RMP3_I2C3 I2C3 Alternate Function mapping + * @arg GPIO_RMP1_I2C4 I2C4 Alternate Function mapping + * @arg GPIO_RMP3_I2C4 I2C4 Alternate Function mapping + * @arg GPIO_RMP1_SPI2 SPI2 Alternate Function mapping + * @arg GPIO_RMP2_SPI2 SPI2 Alternate Function mapping + * @arg GPIO_RMP1_SPI3 SPI3 Alternate Function mapping + * @arg GPIO_RMP2_SPI3 SPI3 Alternate Function mapping + * @arg GPIO_RMP1_ETH ETH Alternate Function mapping + * @arg GPIO_RMP2_ETH ETH Alternate Function mapping + * @arg GPIO_RMP3_ETH ETH Alternate Function mapping + * @arg GPIO_RMP1_SPI1 SPI1 Alternate Function mapping + * @arg GPIO_RMP2_SPI1 SPI1 Alternate Function mapping + * @arg GPIO_RMP3_SPI1 SPI1 Alternate Function mapping + * @arg GPIO_RMP1_USART2 USART2 Alternate Function mapping + * @arg GPIO_RMP2_USART2 USART2 Alternate Function mapping + * @arg GPIO_RMP3_USART2 USART2 Alternate Function mapping + * @arg GPIO_RMP1_UART4 UART4 Alternate Function mapping + * @arg GPIO_RMP2_UART4 UART4 Alternate Function mapping + * @arg GPIO_RMP3_UART4 UART4 Alternate Function mapping + * @arg GPIO_RMP1_UART5 UART5 Alternate Function mapping + * @arg GPIO_RMP2_UART5 UART5 Alternate Function mapping + * @arg GPIO_RMP3_UART5 UART5 Alternate Function mapping + * @arg GPIO_RMP2_UART6 UART6 Alternate Function mapping + * @arg GPIO_RMP3_UART6 UART6 Alternate Function mapping + * @arg GPIO_RMP1_UART7 UART7 Alternate Function mapping + * @arg GPIO_RMP3_UART7 UART7 Alternate Function mapping + * @arg GPIO_RMP1_XFMC XFMC Alternate Function mapping + * @arg GPIO_RMP3_XFMC XFMC Alternate Function mapping + * @arg GPIO_RMP1_TIM8 TIM8 Alternate Function mapping + * @arg GPIO_RMP3_TIM8 TIM8 Alternate Function mapping + * @arg GPIO_RMP1_COMP1 COMP1 Alternate Function mapping + * @arg GPIO_RMP2_COMP1 COMP1 Alternate Function mapping + * @arg GPIO_RMP3_COMP1 COMP1 Alternate Function mapping + * @arg GPIO_RMP1_COMP2 COMP2 Alternate Function mapping + * @arg GPIO_RMP2_COMP2 COMP2 Alternate Function mapping + * @arg GPIO_RMP3_COMP2 COMP2 Alternate Function mapping + * @arg GPIO_RMP1_COMP3 COMP3 Alternate Function mapping + * @arg GPIO_RMP3_COMP3 COMP3 Alternate Function mapping + * @arg GPIO_RMP1_COMP4 COMP4 Alternate Function mapping + * @arg GPIO_RMP3_COMP4 COMP4 Alternate Function mapping + * @arg GPIO_RMP1_COMP5 COMP5 Alternate Function mapping + * @arg GPIO_RMP2_COMP5 COMP5 Alternate Function mapping + * @arg GPIO_RMP3_COMP5 COMP5 Alternate Function mapping + * @arg GPIO_RMP3_UART5 UART5 Alternate Function mapping + * @arg GPIO_RMP1_COMP6 COMP6 Alternate Function mapping + * @arg GPIO_RMP3_COMP6 COMP6 Alternate Function mapping + * @arg GPIO_RMP_COMP7 COMP7 Alternate Function mapping + * @arg GPIO_RMP_ADC3_ETRI ADC3_ETRGINJ Alternate Function mapping + * @arg GPIO_RMP_ADC3_ETRR ADC3_ETRGREG Alternate Function mapping + * @arg GPIO_RMP_ADC4_ETRI ADC4_ETRGINJ Alternate Function mapping + * @arg GPIO_RMP_ADC4_ETRR ADC4_ETRGREG Alternate Function mapping + * @arg GPIO_RMP_TSC_OUT_CTRL TSC_OUT_CTRL Alternate Function mapping + * @arg GPIO_RMP_QSPI_XIP_EN QSPI_XIP_EN Alternate Function mapping + * @arg GPIO_RMP1_DVP DVP Alternate Function mapping + * @arg GPIO_RMP3_DVP DVP Alternate Function mapping + * @arg GPIO_Remap_SPI1_NSS SPI1 NSS Alternate Function mapping + * @arg GPIO_Remap_SPI2_NSS SPI2 NSS Alternate Function mapping + * @arg GPIO_Remap_SPI3_NSS SPI3 NSS Alternate Function mapping + * @arg GPIO_Remap_QSPI_MISO QSPI MISO Alternate Function mapping + * @arg GPIO_Remap_DET_EN_EGB4 EGB4 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_EGB3 EGB3 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_EGB2 EGB2 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_EGB1 EGB1 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_EGBN4 EGBN4 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_EGBN3 EGBN3 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_EGBN2 EGBN2 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_EGBN1 EGBN1 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_ECLAMP4 ECLAMP4 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_ECLAMP3 ECLAMP3 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_ECLAMP2 ECLAMP2 Detect Alternate Function mapping + * @arg GPIO_Remap_DET_EN_ECLAMP1 ECLAMP1 Detect Alternate Function mapping + * @arg GPIO_Remap_RST_EN_EGB4 EGB4 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_EGB3 EGB3 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_EGB2 EGB2 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_EGB1 EGB1 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_EGBN4 EGBN4 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_EGBN3 EGBN3 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_EGBN2 EGBN2 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_EGBN1 EGBN1 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_ECLAMP4 ECLAMP4 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_ECLAMP3 ECLAMP3 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_ECLAMP2 ECLAMP2 Reset Alternate Function mapping + * @arg GPIO_Remap_RST_EN_ECLAMP1 ECLAMP1 Reset Alternate Function mapping + * @param Cmd new state of the port pin remapping. + * This parameter can be: ENABLE or DISABLE. + */ +void GPIO_ConfigPinRemap(uint32_t RmpPin, FunctionalState Cmd) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpregister = 0x00, tmpmask = 0x00, tmp2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(RmpPin)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Check RmpPin relate AFIO RMP_CFG */ + if ((RmpPin & 0x80000000) == 0x80000000) + { + tmpregister = AFIO->RMP_CFG2; + } + else if ((RmpPin & 0x40000000) == 0x40000000) + { + tmpregister = AFIO->RMP_CFG3; + } + else if ((RmpPin & 0x20000000) == 0x20000000) + { + tmpregister = AFIO->RMP_CFG4; + } + else if ((RmpPin & 0x10000000) == 0x10000000) + { + tmpregister = AFIO->RMP_CFG5; + } + else + { + tmpregister = AFIO->RMP_CFG; + } + + tmpmask = (RmpPin & DBGAFR_POSITION_MASK) >> 16; + tmp = RmpPin & LSB_MASK; + + if ((RmpPin + & (DBGAFR_NUMBITS_MAPR5_MASK | DBGAFR_NUMBITS_MAPR4_MASK | DBGAFR_NUMBITS_MAPR3_MASK | DBGAFR_LOCATION_MASK + | DBGAFR_NUMBITS_MASK)) + == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpregister &= DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG &= DBGAFR_SWJCFG_MASK; + } + else if ((RmpPin & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + if ((RmpPin & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK) + { + tmp1 = (((uint32_t)0x03) << tmpmask) << 16; + } + else + { + tmp1 = ((uint32_t)0x03) << tmpmask; + } + tmpregister &= ~tmp1; + if ((RmpPin & 0x70000000) == 0x00000000) + { + tmpregister |= ~DBGAFR_SWJCFG_MASK; + } + } + else + {/*configuration AFIO RMP_CFG*/ + if ((RmpPin & DBGAFR_NUMBITS_SPI1_MASK) == DBGAFR_NUMBITS_SPI1_MASK) + { + if ((RmpPin & 0x00000004) == 0x00000004) + { + if ((RmpPin & 0x02000000) == 0x02000000) // GPIO_RMP3_SPI1 + { + tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); + if (Cmd != DISABLE) + { + tmp2 = AFIO->RMP_CFG; + tmp2 |= 0x00000001; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_SPI1 ENABLE + } + else + { + tmp2 = AFIO->RMP_CFG; + tmp2 &= 0xFFFFFFFE; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE + } + } + else + { + tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); // GPIO_RMP2_SPI1 + + tmp2 = AFIO->RMP_CFG; + tmp2 &= 0xFFFFFFFE; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE + } + } + else + { + tmpregister &= ~((tmp | 0x00000004) << (((RmpPin & 0x00200000) >> 21) * 16)); // clear + if (Cmd != DISABLE) // GPIO_RMP1_SPI1 + { + tmp2 = AFIO->RMP_CFG; + tmp2 |= 0x00000001; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_SPI1 ENABLE + } + else + { + tmp2 = AFIO->RMP_CFG; + tmp2 &= 0xFFFFFFFE; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE + } + } + } + else if ((RmpPin & DBGAFR_NUMBITS_USART2_MASK) == DBGAFR_NUMBITS_USART2_MASK) + { + if ((RmpPin & 0x00000008) == 0x00000008) + { + if ((RmpPin & 0x02000000) == 0x02000000) // GPIO_RMP3_USART2 + { + tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); + if (Cmd != DISABLE) + { + tmp2 = AFIO->RMP_CFG; + tmp2 |= 0x00000008; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_USART2 ENABLE + } + else + { + tmp2 = AFIO->RMP_CFG; + tmp2 &= 0xFFFFFFF7; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE + } + } + else + { + tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); // GPIO_RMP2_USART2 + + tmp2 = AFIO->RMP_CFG; + tmp2 &= 0xFFFFFFF7; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE + } + } + else // GPIO_RMP1_USART2 + { + tmpregister &= ~((tmp | 0x00000008) << (((RmpPin & 0x00200000) >> 21) * 16)); // clear + if (Cmd != DISABLE) + { + tmp2 = AFIO->RMP_CFG; + tmp2 |= 0x00000008; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_USART2 ENABLE + } + else + { + tmp2 = AFIO->RMP_CFG; + tmp2 &= 0xFFFFFFF7; + tmp2 |= ~DBGAFR_SWJCFG_MASK; + AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE + } + } + } + else + { + tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); + if ((RmpPin & 0x70000000) == 0x00000000) + { + tmpregister |= ~DBGAFR_SWJCFG_MASK; + } + } + } + + /*configuration AFIO RMP_CFG~RMP_CFG5*/ + if (Cmd != DISABLE) + { + tmpregister |= (tmp << (((RmpPin & 0x00200000) >> 21) * 16)); + } + + if ((RmpPin & 0x80000000) == 0x80000000) + { + AFIO->RMP_CFG2 = tmpregister; + } + else if ((RmpPin & 0x40000000) == 0x40000000) + { + AFIO->RMP_CFG3 = tmpregister; + } + else if ((RmpPin & 0x20000000) == 0x20000000) + { + AFIO->RMP_CFG4 = tmpregister; + } + else if ((RmpPin & 0x10000000) == 0x10000000) + { + AFIO->RMP_CFG5 = tmpregister; + } + else + { + AFIO->RMP_CFG = tmpregister; + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param PortSource selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * @param PinSource specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + */ +void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (PinSource & (uint8_t)0x03)); + AFIO->EXTI_CFG[PinSource >> 0x02] &= ~tmp; + AFIO->EXTI_CFG[PinSource >> 0x02] |= (((uint32_t)PortSource) << (0x04 * (PinSource & (uint8_t)0x03))); +} + +/** + * @brief Selects the Ethernet media interface. + * @note This function applies only to N32G45x Connectivity line devices. + * @param ETH_ConfigSel specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg GPIO_ETH_MII_CFG MII mode + * @arg GPIO_ETH_RMII_CFG RMII mode + */ +void GPIO_ETH_ConfigMediaInterface(uint32_t ETH_ConfigSel) +{ + assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(ETH_ConfigSel)); + + AFIO->RMP_CFG &= (uint32_t)(~0x00800000); + AFIO->RMP_CFG |= ETH_ConfigSel; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_i2c.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_i2c.c new file mode 100644 index 0000000000..f1b7f79249 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_i2c.c @@ -0,0 +1,1301 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_i2c.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_i2c.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @addtogroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CTRL1_SPEN_SET ((uint16_t)0x0001) +#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTRL1_START_SET ((uint16_t)0x0100) +#define CTRL1_START_RESET ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTRL1_STOP_SET ((uint16_t)0x0200) +#define CTRL1_STOP_RESET ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTRL1_ACK_SET ((uint16_t)0x0400) +#define CTRL1_ACK_RESET ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTRL1_GCEN_SET ((uint16_t)0x0040) +#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTRL1_SWRESET_SET ((uint16_t)0x8000) +#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTRL1_PEC_SET ((uint16_t)0x1000) +#define CTRL1_PEC_RESET ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTRL1_PECEN_SET ((uint16_t)0x0020) +#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTRL1_ARPEN_SET ((uint16_t)0x0010) +#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTRL1_NOEXTEND_SET ((uint16_t)0x0080) +#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTRL2_DMAEN_SET ((uint16_t)0x0800) +#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTRL2_DMALAST_SET ((uint16_t)0x1000) +#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADDR0_SET ((uint16_t)0x0001) +#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_DUALEN_SET ((uint16_t)0x0001) +#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000) + +/* I2C CHCFG mask */ +#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_MASK ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define INTEN_MASK ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @addtogroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + */ +void I2C_DeInit(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct pointer to a I2C_InitType structure that + * contains the configuration information for the specified I2C peripheral. + */ +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct) +{ + uint16_t tmpregister = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksType rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed)); + assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode)); + assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle)); + assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable)); + assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode)); + + /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/ + /* Get the I2Cx CTRL2 value */ + tmpregister = I2Cx->CTRL2; + /* Clear frequency FREQ[5:0] bits */ + tmpregister &= CTRL2_CLKFREQ_RESET; + /* Get pclk1 frequency value */ + RCC_GetClocksFreqValue(&rcc_clocks); + pclk1 = rcc_clocks.Pclk1Freq; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpregister |= freqrange; + /* Write to I2Cx CTRL2 */ + I2Cx->CTRL2 = tmpregister; + + /*---------------------------- I2Cx CHCFG Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TMRISE */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + /* Reset tmpregister value */ + /* Clear F/S, DUTY and CHCFG[11:0] bits */ + tmpregister = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->ClkSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed << 1)); + /* Test if CHCFG value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpregister |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TMRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + // else if((I2C_InitStruct->ClkSpeed > 100000)&&(I2C_InitStruct->ClkSpeed <= 400000))/*(I2C_InitStruct->ClkSpeed <= + // 400000)*/ + else + { + if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 3)); + } + else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_FMDUTYCYCLE_16_9; + } + + /* Test if CHCFG value is under 0x1*/ + if ((result & CLKCTRL_CLKCTRL_SET) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET); + /* Set Maximum Rise Time for fast mode */ + // if (I2C_InitStruct->ClkSpeed <= 400000) + { + I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + // else//add test + //{ + // I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)100) / (uint16_t)1000) + (uint16_t)1); + //} + } + /* Write to I2Cx CHCFG */ + I2Cx->CLKCTRL = tmpregister; + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + + /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/ + /* Get the I2Cx CTRL1 value */ + tmpregister = I2Cx->CTRL1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to BusMode value */ + /* Set ACK bit according to AckEnable value */ + tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable); + /* Write to I2Cx CTRL1 */ + I2Cx->CTRL1 = tmpregister; + + /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized. + */ +void I2C_InitStruct(I2C_InitType* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the ClkSpeed member */ + I2C_InitStruct->ClkSpeed = 5000; + /* Initialize the BusMode member */ + I2C_InitStruct->BusMode = I2C_BUSMODE_I2C; + /* Initialize the FmDutyCycle member */ + I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2; + /* Initialize the OwnAddr1 member */ + I2C_InitStruct->OwnAddr1 = 0; + /* Initialize the AckEnable member */ + I2C_InitStruct->AckEnable = I2C_ACKDIS; + /* Initialize the AddrMode member */ + I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CTRL2 |= CTRL2_DMAEN_SET; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CTRL2 &= CTRL2_DMAEN_RESET; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CTRL2 |= CTRL2_DMALAST_SET; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CTRL2 &= CTRL2_DMALAST_RESET; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Generate a START condition */ + I2Cx->CTRL1 |= CTRL1_START_SET; + } + else + { + /* Disable the START condition generation */ + I2Cx->CTRL1 &= CTRL1_START_RESET; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CTRL1 |= CTRL1_STOP_SET; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CTRL1 &= CTRL1_STOP_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CTRL1 |= CTRL1_ACK_SET; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CTRL1 &= CTRL1_ACK_RESET; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Address specifies the 7bit I2C own address2. + */ +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address) +{ + uint16_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpregister = I2Cx->OADDR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpregister &= OADDR2_ADDR2_RESET; + + /* Set I2Cx Own address2 */ + tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OADDR2 = tmpregister; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OADDR2 |= OADDR2_DUALEN_SET; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OADDR2 &= OADDR2_DUALEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable generall call */ + I2Cx->CTRL1 |= CTRL1_GCEN_SET; + } + else + { + /* Disable generall call */ + I2Cx->CTRL1 &= CTRL1_GCEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_INT_BUF Buffer interrupt mask + * @arg I2C_INT_EVENT Event interrupt mask + * @arg I2C_INT_ERR Error interrupt mask + * @param Cmd new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_I2C_CFG_INT(I2C_IT)); + + if (Cmd != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CTRL2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CTRL2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Data Byte to be transmitted.. + */ +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Write in the DAT register the data to be sent */ + I2Cx->DAT = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @return The value of the received data. + */ +uint8_t I2C_RecvData(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Return the data in the DAT register */ + return (uint8_t)I2Cx->DAT; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Address specifies the slave address which will be transmitted + * @param I2C_Direction specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_DIRECTION_SEND Transmitter mode + * @arg I2C_DIRECTION_RECV Receiver mode + */ +void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_DIRECTION_SEND) + { + /* Set the address bit0 for read */ + Address |= OADDR1_ADDR0_SET; + } + else + { + /* Reset the address bit0 for write */ + Address &= OADDR1_ADDR0_RESET; + } + /* Send the address */ + I2Cx->DAT = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_Register specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_REG_CTRL1 CTRL1 register. + * @arg I2C_REG_CTRL2 CTRL2 register. + * @arg I2C_REG_OADDR1 OADDR1 register. + * @arg I2C_REG_OADDR2 OADDR2 register. + * @arg I2C_REG_DAT DAT register. + * @arg I2C_REG_STS1 STS1 register. + * @arg I2C_REG_STS2 STS2 register. + * @arg I2C_REG_CLKCTRL CHCFG register. + * @arg I2C_REG_TMRISE TMRISE register. + * @return The value of the read register. + */ +uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_REG(I2C_Register)); + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t*)tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CTRL1 |= CTRL1_SWRESET_SET; + } + else + { + /* Peripheral not under reset */ + I2Cx->CTRL1 &= CTRL1_SWRESET_RESET; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACK_POS_NEXT) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_NACKPosition specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last + * received byte. + * @arg I2C_NACK_POS_CURRENT indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_ConfigPecLocation() + * but is intended to be used in I2C mode while I2C_ConfigPecLocation() + * is intended to used in SMBUS mode. + * + */ +void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POS(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACK_POS_NEXT) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CTRL1 |= I2C_NACK_POS_NEXT; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBALERT_LOW SMBAlert pin driven low + * @arg I2C_SMBALERT_HIGH SMBAlert pin driven high + */ +void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBALERT_LOW) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CTRL1 |= I2C_SMBALERT_LOW; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CTRL1 &= I2C_SMBALERT_HIGH; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CTRL1 |= CTRL1_PEC_SET; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CTRL1 &= CTRL1_PEC_RESET; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC + * @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_ConfigNackLocation() + * but is intended to be used in SMBUS mode while I2C_ConfigNackLocation() + * is intended to used in I2C mode. + * + */ +void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POS(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PEC_POS_NEXT) + { + /* Next byte in shift register is PEC */ + I2Cx->CTRL1 |= I2C_PEC_POS_NEXT; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CTRL1 |= CTRL1_PECEN_SET; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CTRL1 &= CTRL1_PECEN_RESET; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @return The PEC value. + */ +uint8_t I2C_GetPec(I2C_Module* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->STS2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CTRL1 |= CTRL1_ARPEN_SET; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CTRL1 &= CTRL1_ARPEN_RESET; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param Cmd new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + */ +void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param FmDutyCycle specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2 + * @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9 + */ +void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle)); + if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9; + } +} + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (STS1 and STS2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentioned limitation of I2C_GetFlag() function. + * The returned value could be compared to events already defined in the + * library (n32g45x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlag() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXDATNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * n32g45x_i2c.h file. + * + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1 + * @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1 + * @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1 + * @arg I2C_EVT_SLAVE_DATA_RECVD EV2 + * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2 + * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2 + * @arg I2C_EVT_SLAVE_DATA_SENDED EV3 + * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3 + * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3 + * @arg I2C_EVT_SLAVE_ACK_MISS EV3_2 + * @arg I2C_EVT_SLAVE_STOP_RECVD EV4 + * @arg I2C_EVT_MASTER_MODE_FLAG EV5 + * @arg I2C_EVT_MASTER_TXMODE_FLAG EV6 + * @arg I2C_EVT_MASTER_RXMODE_FLAG EV6 + * @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7 + * @arg I2C_EVT_MASTER_DATA_SENDING EV8 + * @arg I2C_EVT_MASTER_DATA_SENDED EV8_2 + * @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in n32g45x_i2c.h file. + * + * @return An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_EVT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in n32g45x_i2c.h file. + * + * @return The last event + */ +uint32_t I2C_GetLastEvent(I2C_Module* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Return status */ + return lastevent; +} + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode) + * @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode) + * @arg I2C_FLAG_TRF Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY Bus busy flag + * @arg I2C_FLAG_MSMODE Master/Slave flag + * @arg I2C_FLAG_SMBALERT SMBus Alert flag + * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR PEC error in reception flag + * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag + * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BUSERR Bus error flag + * @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BYTEF Byte transfer finished flag + * @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA" + * @arg I2C_FLAG_STARTBF Start bit flag (Master mode) + * @return The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_MASK; + + if (i2creg != 0) + { + /* Get the I2Cx STS1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx STS2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx STS2 register address */ + i2cxbase += 0x18; + } + + if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT SMBus Alert flag + * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR PEC error in reception flag + * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag + * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BUSERR Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STS1 register (I2C_GetFlag()) followed by a write operation + * to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STS1 (I2C_GetFlag()) followed by writing the + * second byte of the address in DAT register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STS1 register (I2C_GetFlag()) followed by a + * read/write to I2C_DAT register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetFlag()) followed by a read operation to + * I2C_STS2 register ((void)(I2Cx->STS2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1 + * register (I2C_GetFlag()) followed by a write operation to I2C_DAT + * register (I2C_SendData()). + */ +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_INT_SMBALERT SMBus Alert flag + * @arg I2C_INT_TIMOUT Timeout or Tlow error flag + * @arg I2C_INT_PECERR PEC error in reception flag + * @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode) + * @arg I2C_INT_ACKFAIL Acknowledge failure flag + * @arg I2C_INT_ARLOST Arbitration lost flag (Master mode) + * @arg I2C_INT_BUSERR Bus error flag + * @arg I2C_INT_TXDATE Data register empty flag (Transmitter) + * @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag + * @arg I2C_INT_STOPF Stop detection flag (Slave mode) + * @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode) + * @arg I2C_INT_BYTEF Byte transfer finished flag + * @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_INT_STARTBF Start bit flag (Master mode) + * @return The new state of I2C_IT (SET or RESET). + */ +INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT) +{ + INTStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_INT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2)); + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_MASK; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_INT_SMBALERT SMBus Alert interrupt + * @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt + * @arg I2C_INT_PECERR PEC error in reception interrupt + * @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode) + * @arg I2C_INT_ACKFAIL Acknowledge failure interrupt + * @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode) + * @arg I2C_INT_BUSERR Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to + * I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second + * byte of the address in I2C_DAT register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a + * read/write to I2C_DAT register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to + * I2C_STS2 register ((void)(I2Cx->STS2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to + * I2C_DAT register (I2C_SendData()). + */ +void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_CLR_INT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_iwdg.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_iwdg.c new file mode 100644 index 0000000000..36b2f4204a --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_iwdg.c @@ -0,0 +1,193 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_iwdg.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_iwdg.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @addtogroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KEY register bit mask */ +#define KEY_ReloadKey ((uint16_t)0xAAAA) +#define KEY_EnableKey ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers + */ +void IWDG_WriteConfig(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE(IWDG_WriteAccess)); + IWDG->KEY = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4 + * @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8 + * @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16 + * @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32 + * @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64 + * @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128 + * @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256 + */ +void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler)); + IWDG->PREDIV = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + */ +void IWDG_CntReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RELV = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + */ +void IWDG_ReloadKey(void) +{ + IWDG->KEY = KEY_ReloadKey; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + */ +void IWDG_Enable(void) +{ + IWDG->KEY = KEY_EnableKey; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_PVU_FLAG Prescaler Value Update on going + * @arg IWDG_CRVU_FLAG Reload Value Update on going + * @return The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_opamp.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_opamp.c new file mode 100644 index 0000000000..cbec2f80ff --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_opamp.c @@ -0,0 +1,201 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_opamp.c + * @author Nations + * @version v1.0.2 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_opamp.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @brief OPAMP driver modules + * @{ + */ + +/** @addtogroup OPAMP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Functions + * @{ + */ +#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) +/** + * @brief Deinitializes the OPAMP peripheral registers to their default reset values. + */ +void OPAMP_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, DISABLE); +} + +void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct) +{ + OPAMP_InitStruct->Gain = OPAMP_CS_PGA_GAIN_2; + OPAMP_InitStruct->HighVolRangeEn = ENABLE; + OPAMP_InitStruct->TimeAutoMuxEn = DISABLE; + OPAMP_InitStruct->Mod = OPAMP_CS_PGA_EN; +} + +void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + + SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK); + + if(OPAMP_InitStruct->HighVolRangeEn==ENABLE) + SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK); + else + ClrBit(tmp,OPAMP_CS_RANGE_MASK); + + if(OPAMP_InitStruct->TimeAutoMuxEn==ENABLE) + SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK); + else + ClrBit(tmp,OPAMP_CS_TCMEN_MASK); + + SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK); + *pCs = tmp; +} +void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + if (en) + SetBit(*pCs, OPAMP_CS_EN_MASK); + else + ClrBit(*pCs, OPAMP_CS_EN_MASK); +} + +void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK); + *pCs = tmp; +} +void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK); + *pCs = tmp; +} +void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK); + *pCs = tmp; +} +void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK); + *pCs = tmp; +} +void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + __IO uint32_t tmp = *pCs; + SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK); + *pCs = tmp; +} +bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false; +} +void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en) +{ + __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx; + if (en) + SetBit(*pCs, OPAMP_CS_CALON_MASK); + else + ClrBit(*pCs, OPAMP_CS_CALON_MASK); +} +// Lock see @OPAMP_LOCK +void OPAMP_SetLock(uint32_t Lock) +{ + OPAMP->LOCK = Lock; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_pwr.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_pwr.c new file mode 100644 index 0000000000..c00be0efd3 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_pwr.c @@ -0,0 +1,399 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_pwr.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_pwr.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @addtogroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CTRL Register ---*/ + +/* Alias word address of DBKP bit */ +#define CTRL_OFFSET (PWR_OFFSET + 0x00) +#define DBKP_BITN 0x08 +#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4)) + +/* Alias word address of PVDEN bit */ +#define PVDEN_BITN 0x04 +#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of WKUPEN bit */ +#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04) +#define WKUPEN_BITN 0x08 +#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTRL_PRS_MASK ((uint32_t)0xFFFFFD1F) + +/** + * @} + */ + +/** @addtogroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + */ +void PWR_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param Cmd new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_BackupAccessEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param Cmd new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_PvdEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDRANGRE_2V2 PVD detection level set to 2.2V + * @arg PWR_PVDRANGRE_2V3 PVD detection level set to 2.3V + * @arg PWR_PVDRANGRE_2V4 PVD detection level set to 2.4V + * @arg PWR_PVDRANGRE_2V5 PVD detection level set to 2.5V + * @arg PWR_PVDRANGRE_2V6 PVD detection level set to 2.6V + * @arg PWR_PVDRANGRE_2V7 PVD detection level set to 2.7V + * @arg PWR_PVDRANGRE_2V8 PVD detection level set to 2.8V + * @arg PWR_PVDRANGRE_2V9 PVD detection level set to 2.9V + */ +void PWR_PvdRangeConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpregister = PWR->CTRL; + /* Clear PRS[7:5] bits */ + tmpregister &= CTRL_PRS_MASK; + /* Set PRS[7:5] bits according to PWR_PVDLevel value */ + tmpregister |= PWR_PVDLevel; + /* Store the new value */ + PWR->CTRL = tmpregister; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param Cmd new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + */ +void PWR_WakeUpPinEnable(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_WKUPEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Enters SLEEP mode. + * @param SLEEPONEXIT specifies the SLEEPONEXIT state in SLEEP mode. + * This parameter can be one of the following values: + * @arg 0 SLEEP mode with SLEEPONEXIT disable + * @arg 1 SLEEP mode with SLEEPONEXIT enable + * @param PWR_STOPEntry specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI enter SLEEP mode with WFI instruction + * @arg PWR_STOPENTRY_WFE enter SLEEP mode with WFE instruction + */ +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry) +{ + // uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* CLEAR SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP); + + /* Select SLEEPONEXIT mode entry --------------------------------------------------*/ + if (SLEEPONEXIT == 1) + { + /* the MCU enters Sleep mode as soon as it exits the lowest priority INTSTS */ + SCB->SCR |= SCB_SCR_SLEEPONEXIT; + } + else if (SLEEPONEXIT == 0) + { + /* Sleep-now */ + SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPONEXIT); + } + + /* Select SLEEP mode entry --------------------------------------------------*/ + if (PWR_STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_ON STOP mode with regulator ON + * @arg PWR_REGULATOR_LOWPOWER STOP mode with regulator in low power mode + * @param PWR_STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI enter STOP mode with WFI instruction + * @arg PWR_STOPENTRY_WFE enter STOP mode with WFE instruction + */ +void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpregister = PWR->CTRL; + /* Clear PDS and LPS bits */ + tmpregister &= CTRL_DS_MASK; + /* Set LPS bit according to PWR_Regulator value */ + tmpregister |= PWR_Regulator; + /* Store the new value */ + PWR->CTRL = tmpregister; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry --------------------------------------------------*/ + if (PWR_STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** + * @brief Enters STOP2 mode. + * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction + * @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction + */ +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP2 mode ---------------------------------*/ + tmpregister = PWR->CTRL; + /* Clear PDS and LPS bits */ + tmpregister &= CTRL_DS_MASK; + /* Store the new value */ + PWR->CTRL = tmpregister; + /*STOP2 sleep mode control-stop2s*/ + PWR->CTRL2 |= PWR_CTRL2_STOP2S; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + // PWR_CTRL2.BIT0 STOP2S need? + /* Select STOP mode entry --------------------------------------------------*/ + if (PWR_STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** + * @brief Enters STANDBY mode. + */ +void PWR_EnterStandbyState(void) +{ + /* Clear Wake-up flag */ + PWR->CTRL |= PWR_CTRL_CWKUP; + /* Clear PDS and LPS bits */ + PWR->CTRL &= CTRL_DS_MASK; + /* Select STANDBY mode */ + PWR->CTRL |= PWR_CTRL_PDS; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; +/* This option is used to ensure that store operations are completed */ +#if defined(__CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_WU_FLAG Wake Up flag + * @arg PWR_SB_FLAG StandBy flag + * @arg PWR_PVDO_FLAG PVD Output + * @arg PWR_VBATF_FLAG VBAT flag + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CTRLSTS & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WU_FLAG Wake Up flag + * @arg PWR_SB_FLAG StandBy and VBAT flag + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CTRL |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_qspi.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_qspi.c new file mode 100644 index 0000000000..bbc1a644cd --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_qspi.c @@ -0,0 +1,612 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_qspi.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_qspi.h" + +/** + * @brief Control QSPI function switch. + * @param cmd select enable or disable QSPI. + */ +void QSPI_Cmd(bool cmd) +{ + if (cmd != DISABLE) + { + QSPI->SLAVE_EN = QSPI_SLAVE_EN_SEN; + QSPI->EN = QSPI_EN_QEN; + } + else + { + QSPI->SLAVE_EN &= ~QSPI_SLAVE_EN_SEN; + QSPI->EN &= ~QSPI_EN_QEN; + } +} +/** + * @brief Control QSPI XIP function switch. + * @param cmd select enable or disable QSPI XIP. + */ +void QSPI_XIP_Cmd(bool cmd) +{ + if (cmd != DISABLE) + { + QSPI->XIP_SLAVE_EN = QSPI_XIP_SLAVE_EN_SEN; + } + else + { + QSPI->XIP_SLAVE_EN &= ~QSPI_XIP_SLAVE_EN_SEN; + } +} +/** + * @brief Deinitializes the QSPI peripheral registers to its default reset values. + */ +void QSPI_DeInit(void) +{ + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_QSPI, ENABLE); + RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_QSPI, DISABLE); +} +/** + * @brief Merge configuration from the buffer of QSPI para struct, then write it into related registers. + * @param QSPI_InitStruct pointer to buffer of QSPI para struct. + */ +void QspiInitConfig(QSPI_InitType* QSPI_InitStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_QSPI_SPI_FRF(QSPI_InitStruct->SPI_FRF)); + assert_param(IS_QSPI_CFS(QSPI_InitStruct->CFS)); + assert_param(IS_QSPI_SSTE(QSPI_InitStruct->SSTE)); + assert_param(IS_QSPI_TMOD(QSPI_InitStruct->TMOD)); + assert_param(IS_QSPI_SCPOL(QSPI_InitStruct->SCPOL)); + assert_param(IS_QSPI_SCPH(QSPI_InitStruct->SCPH)); + assert_param(IS_QSPI_FRF(QSPI_InitStruct->FRF)); + assert_param(IS_QSPI_DFS(QSPI_InitStruct->DFS)); + assert_param(IS_QSPI_MWMOD(QSPI_InitStruct->MWMOD)); + assert_param(IS_QSPI_MC_DIR(QSPI_InitStruct->MC_DIR)); + assert_param(IS_QSPI_MHS_EN(QSPI_InitStruct->MHS_EN)); + assert_param(IS_QSPI_SES(QSPI_InitStruct->SES)); + assert_param(IS_QSPI_SDCN(QSPI_InitStruct->SDCN)); + + assert_param(IS_QSPI_ENH_CLK_STRETCH_EN(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN)); + assert_param(IS_QSPI_ENH_XIP_MBL(QSPI_InitStruct->ENHANCED_XIP_MBL)); + assert_param(IS_QSPI_ENH_XIP_CT_EN(QSPI_InitStruct->ENHANCED_XIP_CT_EN)); + assert_param(IS_QSPI_ENH_XIP_INST_EN(QSPI_InitStruct->ENHANCED_XIP_INST_EN)); + assert_param(IS_QSPI_ENH_XIP_DFS_HC(QSPI_InitStruct->ENHANCED_XIP_DFS_HC)); + assert_param(IS_QSPI_ENH_INST_DDR_EN(QSPI_InitStruct->ENHANCED_INST_DDR_EN)); + assert_param(IS_QSPI_ENH_SPI_DDR_EN(QSPI_InitStruct->ENHANCED_SPI_DDR_EN)); + assert_param(IS_QSPI_ENH_WAIT_CYCLES(QSPI_InitStruct->ENHANCED_WAIT_CYCLES)); + assert_param(IS_QSPI_ENH_INST_L(QSPI_InitStruct->ENHANCED_INST_L)); + assert_param(IS_QSPI_ENH_MD_BIT_EN(QSPI_InitStruct->ENHANCED_MD_BIT_EN)); + assert_param(IS_QSPI_ENH_ADDR_LEN(QSPI_InitStruct->ENHANCED_ADDR_LEN)); + assert_param(IS_QSPI_ENH_TRANS_TYPE(QSPI_InitStruct->ENHANCED_TRANS_TYPE)); + + assert_param(IS_QSPI_XIP_MBL(QSPI_InitStruct->XIP_MBL)); + assert_param(IS_QSPI_XIP_CT_EN(QSPI_InitStruct->XIP_CT_EN)); + assert_param(IS_QSPI_XIP_INST_EN(QSPI_InitStruct->XIP_INST_EN)); + assert_param(IS_QSPI_INST_DDR_EN(QSPI_InitStruct->XIP_INST_DDR_EN)); + assert_param(IS_QSPI_DDR_EN(QSPI_InitStruct->XIP_DDR_EN)); + assert_param(IS_QSPI_XIP_DFS_HC(QSPI_InitStruct->XIP_DFS_HC)); + assert_param(IS_QSPI_XIP_WAIT_CYCLES(QSPI_InitStruct->XIP_WAIT_CYCLES)); + assert_param(IS_QSPI_XIP_MD_BIT_EN(QSPI_InitStruct->XIP_MD_BITS_EN)); + assert_param(IS_QSPI_XIP_INST_L(QSPI_InitStruct->XIP_INST_L)); + assert_param(IS_QSPI_XIP_ADDR_LEN(QSPI_InitStruct->XIP_ADDR_LEN)); + assert_param(IS_QSPI_XIP_TRANS_TYPE(QSPI_InitStruct->XIP_TRANS_TYPE)); + assert_param(IS_QSPI_XIP_FRF(QSPI_InitStruct->XIP_FRF)); + + assert_param(IS_QSPI_XIP_MODE(QSPI_InitStruct->XIP_MD_BITS)); + assert_param(IS_QSPI_XIP_INCR_TOC(QSPI_InitStruct->ITOC)); + assert_param(IS_QSPI_XIP_WRAP_TOC(QSPI_InitStruct->WTOC)); + assert_param(IS_QSPI_XIP_TOUT(QSPI_InitStruct->XTOUT)); + + assert_param(IS_QSPI_NDF(QSPI_InitStruct->NDF)); + assert_param(IS_QSPI_CLK_DIV(QSPI_InitStruct->CLK_DIV)); + assert_param(IS_QSPI_TXFT(QSPI_InitStruct->TXFT)); + assert_param(IS_QSPI_RXFT(QSPI_InitStruct->RXFT)); + assert_param(IS_QSPI_TXFN(QSPI_InitStruct->TXFN)); + assert_param(IS_QSPI_RXFN(QSPI_InitStruct->RXFN)); + assert_param(IS_QSPI_DDR_TXDE(QSPI_InitStruct->TXDE)); + + if((QSPI_InitStruct->SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT) + { + tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD + | QSPI_InitStruct->SCPOL | QSPI_InitStruct->SCPH | QSPI_InitStruct->FRF | QSPI_InitStruct->DFS); + QSPI->CTRL0 = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(QSPI_InitStruct->MWMOD | QSPI_InitStruct->MC_DIR | QSPI_InitStruct->MHS_EN); + QSPI->MW_CTRL = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(QSPI_InitStruct->SES | QSPI_InitStruct->SDCN); + QSPI->RS_DELAY = tmpregister; + } + else if((QSPI_InitStruct->SPI_FRF == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || (QSPI_InitStruct->SPI_FRF == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT)) + { + tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD + | QSPI_InitStruct->SCPOL | QSPI_InitStruct->SCPH | QSPI_InitStruct->FRF | QSPI_InitStruct->DFS); + QSPI->CTRL0 = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(QSPI_InitStruct->MWMOD | QSPI_InitStruct->MC_DIR | QSPI_InitStruct->MHS_EN); + QSPI->MW_CTRL = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(QSPI_InitStruct->SES | QSPI_InitStruct->SDCN); + QSPI->RS_DELAY = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_XIP_MBL | QSPI_InitStruct->ENHANCED_XIP_CT_EN + | QSPI_InitStruct->ENHANCED_XIP_INST_EN | QSPI_InitStruct->ENHANCED_XIP_DFS_HC | QSPI_InitStruct->ENHANCED_INST_DDR_EN + | QSPI_InitStruct->ENHANCED_SPI_DDR_EN | QSPI_InitStruct->ENHANCED_WAIT_CYCLES | QSPI_InitStruct->ENHANCED_INST_L + | QSPI_InitStruct->ENHANCED_MD_BIT_EN | QSPI_InitStruct->ENHANCED_ADDR_LEN | QSPI_InitStruct->ENHANCED_TRANS_TYPE); + QSPI->ENH_CTRL0 = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(QSPI_InitStruct->XIP_MBL | QSPI_InitStruct->XIP_CT_EN | QSPI_InitStruct->XIP_INST_EN | QSPI_InitStruct->XIP_INST_DDR_EN + | QSPI_InitStruct->XIP_DDR_EN | QSPI_InitStruct->XIP_DFS_HC | QSPI_InitStruct->XIP_WAIT_CYCLES | QSPI_InitStruct->XIP_MD_BITS_EN + | QSPI_InitStruct->XIP_INST_L | QSPI_InitStruct->XIP_ADDR_LEN | QSPI_InitStruct->XIP_TRANS_TYPE | QSPI_InitStruct->XIP_FRF); + QSPI->XIP_CTRL = tmpregister; + + QSPI->XIP_MODE = QSPI_InitStruct->XIP_MD_BITS; + QSPI->XIP_INCR_TOC = QSPI_InitStruct->ITOC; + QSPI->XIP_WRAP_TOC = QSPI_InitStruct->WTOC; + QSPI->XIP_TOUT = QSPI_InitStruct->XTOUT; + } + QSPI->CTRL1 = QSPI_InitStruct->NDF; + QSPI->BAUD = QSPI_InitStruct->CLK_DIV; + QSPI->TXFT = QSPI_InitStruct->TXFT; + QSPI->RXFT = QSPI_InitStruct->RXFT; + QSPI->TXFN = QSPI_InitStruct->TXFN; + QSPI->RXFN = QSPI_InitStruct->RXFN; + QSPI->DDR_TXDE = QSPI_InitStruct->TXDE; +} +/** + * @brief Configure single GPIO port as GPIO_Mode_AF_PP. + * @param GPIOx x can be A to G to select the GPIO port. + * @param Pin This parameter can be GPIO_PIN_0~GPIO_PIN_15. + */ +static void QSPI_SingleGpioConfig(GPIO_Module* GPIOx, uint16_t Pin) +{ + GPIO_InitType GPIO_InitStructure; + + GPIO_InitStructure.Pin = Pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitPeripheral(GPIOx, &GPIO_InitStructure); +} +/** + * @brief Remap QSPI AFIO group by selecting the pin of NSS. + * @param qspi_nss_port_sel select the pin of NSS. + QSPI_NSS_PORTA_SEL:QSPI remap by PA4~PA7 and PC4~PC5. + QSPI_NSS_PORTC_SEL:QSPI remap by PC10~PC12 and PD0~PD2. + QSPI_NSS_PORTF_SEL:QSPI remap by PF0~PF5. + * @param IO1_Input IO1 Configure as input or not. + * @param IO3_Output IO3 Configure as output or not. + */ +void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Output) +{ + GPIO_InitType GPIO_InitStructure; + + switch (qspi_nss_port_sel) + { + case QSPI_NSS_PORTA_SEL: + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_QSPI, DISABLE); //clear two bits of qspi + + QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_4); // NSS + QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_5); // SCK + QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_6); // IO0 + if (IO1_Input) + { + GPIO_InitStructure.Pin = GPIO_PIN_7; // IO1 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_INPUT; + GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure); + } + else + { + QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_7); // IO1 + } + + if (IO3_Output) + { + GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_5; // IO2 and IO3 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure); + + GPIOC->PBSC |= GPIO_PIN_4 | GPIO_PIN_5; + } + else + { + QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_4); // IO2 + QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_5); // IO3 + } + break; + case QSPI_NSS_PORTC_SEL: + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_GPIOD | RCC_APB2_PERIPH_AFIO, ENABLE); + + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_QSPI, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP_QSPI_XIP_EN, ENABLE); + + QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_10); // NSS + QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_11); // SCK + QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_12); // IO0 + if (IO1_Input) + { + GPIO_InitStructure.Pin = GPIO_PIN_0; // IO1 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_INPUT; + GPIO_InitPeripheral(GPIOD, &GPIO_InitStructure); + } + else + { + QSPI_SingleGpioConfig(GPIOD, GPIO_PIN_0); // IO1 + } + + if (IO3_Output) + { + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2; // IO2 and IO3 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitPeripheral(GPIOD, &GPIO_InitStructure); + + GPIOD->PBSC |= GPIO_PIN_1 | GPIO_PIN_2; + } + else + { + QSPI_SingleGpioConfig(GPIOD, GPIO_PIN_1); // IO2 + QSPI_SingleGpioConfig(GPIOD, GPIO_PIN_2); // IO3 + } + break; + case QSPI_NSS_PORTF_SEL: + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOF | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP1_QSPI, ENABLE); + + QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_0); // NSS + QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_1); // SCK + QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_2); // IO0 + if (IO1_Input) + { + GPIO_InitStructure.Pin = GPIO_PIN_3; // IO1 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_INPUT; + GPIO_InitPeripheral(GPIOF, &GPIO_InitStructure); + } + else + { + QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_3); // IO1 + } + + if (IO3_Output) + { + GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_5; // IO2 and IO3 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitPeripheral(GPIOF, &GPIO_InitStructure); + + GPIOF->PBSC |= GPIO_PIN_4 | GPIO_PIN_5; + } + else + { + QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_4); // IO2 + QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_5); // IO3 + } + break; + default: + break; + } +} +/** + * @brief Configuration of QSPI DMA. + * @param TxRx transmit or receive data. + QSPI_DMA_CTRL_TX_DMA_EN:transmit data + QSPI_DMA_CTRL_RX_DMA_EN:receive data + * @param TxDataLevel dma transmit data level. + * @param RxDataLevel dma receive data level. + */ +void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel) +{ + assert_param(IS_QSPI_DMA_CTRL(TxRx)); + assert_param(IS_QSPI_DMATDL_CTRL(TxDataLevel)); + assert_param(IS_QSPI_DMARDL_CTRL(RxDataLevel)); + + QSPI->DMA_CTRL = 0x00; + + if (TxRx & QSPI_DMA_CTRL_TX_DMA_EN) + { + QSPI->DMATDL_CTRL = TxDataLevel; + QSPI->DMA_CTRL |= QSPI_DMA_CTRL_TX_DMA_EN; + } + if (TxRx & QSPI_DMA_CTRL_RX_DMA_EN) + { + QSPI->DMARDL_CTRL = RxDataLevel; + QSPI->DMA_CTRL |= QSPI_DMA_CTRL_RX_DMA_EN; + } +} +/** + * @brief Get the flag of interrupt status register. + * @param FLAG flag of related interrupt register. + */ +uint16_t QSPI_GetITStatus(uint16_t FLAG) +{ + uint16_t tmp = 0; + tmp = QSPI->ISTS & FLAG; + if (tmp) + return 1; + else + return 0; +} +/** + * @brief Clear the flag of related interrupt register. + * @param FLAG flag of related interrupt register. + */ +void QSPI_ClearITFLAG(uint16_t FLAG) +{ + volatile uint16_t tmp = 0; + + if (FLAG == QSPI_ISTS_TXFOIS) + tmp = QSPI->TXFOI_CLR; + if (FLAG == QSPI_ISTS_RXFOIS) + tmp = QSPI->RXFOI_CLR; + if (FLAG == QSPI_ISTS_RXFUIS) + tmp = QSPI->RXFUI_CLR; + if (FLAG == QSPI_ISTS_MMCIS) + tmp = QSPI->MMC_CLR; + if (FLAG == QSPI_ISTS) + tmp = QSPI->ICLR; +} +/** + * @brief Clear the flag of related interrupt register. + * @param FLAG flag of XRXFOIC interrupt register. + */ +void QSPI_XIP_ClearITFLAG(uint16_t FLAG) +{ + volatile uint16_t tmp = 0; + + if (FLAG == QSPI_XIP_RXFOI_CLR_XRXFOIC) + tmp = QSPI->XIP_RXFOI_CLR; +} +/** + * @brief Get QSPI status,busy or not. + * @return 1:QSPI busy;0:QSPI idle. + */ +bool GetQspiBusyStatus(void) +{ + if ((QSPI->STS & 0x01) == 0x01) + return 1; + return 0; +} +/** + * @brief Check transmit fifo full or not. + * @return 1: Transmit fifo full;0: Transmit fifo not full. + */ +bool GetQspiTxDataBusyStatus(void) +{ + if ((QSPI->STS & 0x02) == 0x00) + return 1; + return 0; +} +/** + * @brief Check transmit fifo empty or not. + * @return 1: Transmit fifo empty;0: Transmit fifo not empty. + */ +bool GetQspiTxDataEmptyStatus(void) +{ + if ((QSPI->STS & 0x04) == 0x04) + return 1; + return 0; +} +/** + * @brief Check receive fifo have data or not. + * @return 1:Receive fifo have data;0:Receive fifo empty. + */ +bool GetQspiRxHaveDataStatus(void) +{ + if ((QSPI->STS & 0x08) == 0x08) + return 1; + return 0; +} +/** + * @brief Check receive fifo full or not. + * @return 1: Receive fifo full;0: Receive fifo not full. + */ +bool GetQspiRxDataFullStatus(void) +{ + if ((QSPI->STS & 0x10) == 0x10) + return 1; + return 0; +} +/** + * @brief Check transmit error or not. + * @return 1: Transmit error;0: No transmit error. + */ +bool GetQspiTransmitErrorStatus(void) +{ + if ((QSPI->STS & 0x20) == 0x20) + return 1; + return 0; +} +/** + * @brief Check data conflict error or not. + * @return 1: Data conflict error;0: No data conflict error. + */ +bool GetQspiDataConflictErrorStatus(void) +{ + if ((QSPI->STS & 0x40) == 0x40) + return 1; + return 0; +} +/** + * @brief Write one data direct to QSPI DAT0 register to send. + * @param SendData: data to be send. + */ +void QspiSendWord(uint32_t SendData) +{ + QSPI->DAT0 = SendData; +} +/** + * @brief Read one data from QSPI DAT0 register. + * @return the value of QSPI DAT0 register. + */ +uint32_t QspiReadWord(void) +{ + return QSPI->DAT0; +} +/** + * @brief Get Pointer of QSPI DAT0 register. + * @return the pointer of QSPI DAT0 register. + */ +uint32_t QspiGetDataPointer(void) +{ + return (uint32_t)&QSPI->DAT0; +} +/** + * @brief Read value from QSPI RXFN register which shows the number of the data from receive fifo. + * @return the number of the data from receive fifo. + */ +uint32_t QspiReadRxFifoNum(void) +{ + return QSPI->RXFN; +} +/** + * @brief Read DAT0 register to clear fifo. + */ +void ClrFifo(void) +{ + uint32_t timeout = 0; + + while (GetQspiRxHaveDataStatus()) + { + QspiReadWord(); + if(++timeout >= 200) + { + break; + } + } +} +/** + * @brief Get data from fifo. + * @param pData pointer to buffer of getting fifo data. + * @param Len length of getting fifo data. + */ +uint32_t GetFifoData(uint32_t* pData, uint32_t Len) +{ + uint32_t cnt; + for (cnt = 0; cnt < Len; cnt++) + { + if (GetQspiRxHaveDataStatus()) + { + *pData++ = QspiReadWord(); + } + else + { + return QSPI_NULL; + } + } + + return QSPI_SUCCESS; +} +/** + * @brief Send words out from source data buffer and get returned datas into destination data buffer. + * @param pSrcData pointer to buffer of sending datas. + * @param pDstData pointer to buffer of getting returned datas. + * @param cnt number of sending datas. + */ +void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt) +{ + uint32_t num = 0; + uint32_t timeout = 0; + + while (num < cnt) + { + QspiSendWord(*(pSrcData++)); + num++; + } + while (!GetQspiRxHaveDataStatus()) + { + if(++timeout >= QSPI_TIME_OUT_CNT) + { + break; + } + } + timeout = 0; + while (QSPI->RXFN < cnt) + { + if(++timeout >= QSPI_TIME_OUT_CNT) + { + break; + } + } + num = 0; + while (num < cnt) + { + *(pDstData++) = QspiReadWord(); + num++; + } +} +/** + * @brief Send one word data and get returned words into destination data buffer. + * @param WrData one word to be sent. + * @param pRdData pointer to buffer of getting returned datas. + * @param LastRd whether go on to get returned datas. + 1:go on to get returned datas. + 0:end to get returned datas. + */ +uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t LastRd) +{ + uint32_t timeout1 = 0; + + QspiSendWord(WrData); //trammit + *pRdData = QspiReadWord(); + if(LastRd != 0) + { + while(!GetQspiRxHaveDataStatus()) //wait for data + { + if(++timeout1 >= QSPI_TIME_OUT_CNT) + { + return QSPI_NULL; //time out + } + } + + *pRdData = QspiReadWord(); //read data + return QSPI_SUCCESS; + } + + return QSPI_NULL; +} + + diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_rcc.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_rcc.c new file mode 100644 index 0000000000..6500ab33b1 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_rcc.c @@ -0,0 +1,1390 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_rcc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @addtogroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CTRL Register ---*/ + +/* Alias word address of HSIEN bit */ +#define CTRL_OFFSET (RCC_OFFSET + 0x00) +#define HSIEN_BITN 0x00 +#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4)) + +/* Alias word address of PLLEN bit */ +#define PLLEN_BITN 0x18 +#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4)) + +/* Alias word address of CLKSSEN bit */ +#define CLKSSEN_BITN 0x13 +#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4)) + +/* --- CFG Register ---*/ + +/* Alias word address of USBPRES bit */ +#define CFG_OFFSET (RCC_OFFSET + 0x04) + +#define USBPRES_BITN 0x16 +#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4)) + +#define USBPRE_Bit1Number 0x17 +#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4)) + +/* --- BDCTRL Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCTRL_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BITN 0x0F +#define BDCTRL_RTCEN_BB (PERIPH_BB_BASE + (BDCTRL_OFFSET * 32) + (RTCEN_BITN * 4)) + +/* Alias word address of BDSFTRST bit */ +#define BDSFTRST_BITN 0x10 +#define BDCTRL_BDSFTRST_BB (PERIPH_BB_BASE + (BDCTRL_OFFSET * 32) + (BDSFTRST_BITN * 4)) + +/* --- CTRLSTS Register ---*/ + +/* Alias word address of LSIEN bit */ +#define CTRLSTS_OFFSET (RCC_OFFSET + 0x24) +#define LSIEN_BITNUMBER 0x00 +#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_HSEBP_RESET ((uint32_t)0xFFFBFFFF) +#define CTRL_HSEBP_SET ((uint32_t)0x00040000) +#define CTRL_HSEEN_RESET ((uint32_t)0xFFFEFFFF) +#define CTRL_HSEEN_SET ((uint32_t)0x00010000) +#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF07) + +/* CFG register bit mask */ +#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF) + +#define CFG_PLLMULFCT_MASK ((uint32_t)0x083C0000) +#define CFG_PLLSRC_MASK ((uint32_t)0x00010000) +#define CFG_PLLHSEPRES_MASK ((uint32_t)0x00020000) +#define CFG_SCLKSTS_MASK ((uint32_t)0x0000000C) +#define CFG_SCLKSW_MASK ((uint32_t)0xFFFFFFFC) +#define CFG_AHBPRES_RESET_MASK ((uint32_t)0xFFFFFF0F) +#define CFG_AHBPRES_SET_MASK ((uint32_t)0x000000F0) +#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF) +#define CFG_APB1PRES_SET_MASK ((uint32_t)0x00000700) +#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF) +#define CFG_APB2PRES_SET_MASK ((uint32_t)0x00003800) + +/* CFG2 register bit mask */ +#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000) +#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF) +#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000) +#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF) +#define CFG2_ETHCLKSEL_SET_MASK ((uint32_t)0x00100000) +#define CFG2_ETHCLKSEL_RESET_MASK ((uint32_t)0xFFEFFFFF) +#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00000400) +#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFFFBFF) +#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0000F800) +#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF) +#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0) +#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F) +#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F) +#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0) + +/* CFG3 register bit mask */ +#define CFGR3_TRNG1MSEL_SET_MASK ((uint32_t)0x00020000) +#define CFGR3_TRNG1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF) +#define CFGR3_TRNG1MPRES_SET_MASK ((uint32_t)0x0000F800) +#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF) + +/* CTRLSTS register bit mask */ +#define CSR_RMRSTF_SET ((uint32_t)0x01000000) +#define CSR_RMVF_Reset ((uint32_t)0xfeffffff) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CLKINT register byte 2 (Bits[15:8]) base address */ +#define CLKINT_BYTE2_ADDR ((uint32_t)0x40021009) + +/* CLKINT register byte 3 (Bits[23:16]) base address */ +#define CLKINT_BYTE3_ADDR ((uint32_t)0x4002100A) + +/* CFG register byte 4 (Bits[31:24]) base address */ +#define CFG_BYTE4_ADDR ((uint32_t)0x40021007) + +/* BDCTRL register base address */ +#define BDCTRL_ADDR (PERIPH_BASE + BDCTRL_OFFSET) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Variables + * @{ + */ + +static const uint8_t s_ApbAhbPresTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static const uint8_t s_AdcHclkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32}; +static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256}; + +/** + * @} + */ + +/** @addtogroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + */ +void RCC_DeInit(void) +{ + /* Set HSIEN bit */ + RCC->CTRL |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */ + RCC->CFG &= (uint32_t)0xF8FFC000; + + /* Reset HSEON, CLKSSEN and PLLEN bits */ + RCC->CTRL &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CTRL &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES/OTGFSPRE bits */ + RCC->CFG &= (uint32_t)0xF700FFFF; + + /* Reset CFG2 register */ + RCC->CFG2 = 0x00003800; + + /* Reset CFG3 register */ + RCC->CFG3 = 0x00003800; + + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT = 0x009F0000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RC_HSE_DISABLE HSE oscillator OFF + * @arg RCC_HSE_ENABLE HSE oscillator ON + * @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +void RCC_ConfigHse(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CTRL &= CTRL_HSEEN_RESET; + /* Reset HSEBYP bit */ + RCC->CTRL &= CTRL_HSEBP_RESET; + /* Configure HSE (RC_HSE_DISABLE is already covered by the code section above) */ + switch (RCC_HSE) + { + case RCC_HSE_ENABLE: + /* Set HSEON bit */ + RCC->CTRL |= CTRL_HSEEN_SET; + break; + + case RCC_HSE_BYPASS: + /* Set HSEBYP and HSEON bits */ + RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @return An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitHseStable(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERD); + StartUpCounter++; + } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERD) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + */ +void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue)); + tmpregister = RCC->CTRL; + /* Clear HSITRIM[4:0] bits */ + tmpregister &= CTRL_HSITRIM_MASK; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpregister |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CTRL = tmpregister; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableHsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource specifies the PLL entry clock source. + * this parameter can be one of the following values: + * @arg RCC_PLL_SRC_HSI_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul specifies the PLL multiplication factor. + * this parameter can be RCC_PLLMul_x where x:[2,32] + */ +void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SRC(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpregister = RCC->CFG; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */ + tmpregister &= CFG_PLL_MASK; + /* Set the PLL configuration bits */ + tmpregister |= RCC_PLLSource | RCC_PLLMul; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnablePll(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_SRC_HSI HSI selected as system clock + * @arg RCC_SYSCLK_SRC_HSE HSE selected as system clock + * @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock + */ +void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource)); + tmpregister = RCC->CFG; + /* Clear SW[1:0] bits */ + tmpregister &= CFG_SCLKSW_MASK; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpregister |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Returns the clock source used as system clock. + * @return The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSysclkSrc(void) +{ + return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK + * @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512 + */ +void RCC_ConfigHclk(uint32_t RCC_SYSCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK)); + tmpregister = RCC->CFG; + /* Clear HPRE[3:0] bits */ + tmpregister &= CFG_AHBPRES_RESET_MASK; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpregister |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1 APB1 clock = HCLK + * @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2 + * @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4 + * @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8 + * @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16 + */ +void RCC_ConfigPclk1(uint32_t RCC_HCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK_DIV(RCC_HCLK)); + tmpregister = RCC->CFG; + /* Clear PPRE1[2:0] bits */ + tmpregister &= CFG_APB1PRES_RESET_MASK; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpregister |= RCC_HCLK; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1 APB2 clock = HCLK + * @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2 + * @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4 + * @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8 + * @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16 + */ +void RCC_ConfigPclk2(uint32_t RCC_HCLK) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK_DIV(RCC_HCLK)); + tmpregister = RCC->CFG; + /* Clear PPRE2[2:0] bits */ + tmpregister &= CFG_APB2PRES_RESET_MASK; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpregister |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RccInt specifies the RCC interrupt sources to be enabled or disabled. + * + * this parameter can be any combination of the following values + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * + * @param Cmd new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_INT(RccInt)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */ + *(__IO uint8_t*)CLKINT_BYTE2_ADDR |= RccInt; + } + else + { + /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */ + *(__IO uint8_t*)CLKINT_BYTE2_ADDR &= (uint8_t)~RccInt; + } +} + +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV1 PLL clock selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV2 PLL clock divided by 2 selected as USB clock source + * @arg RCC_USBCLK_SRC_PLLCLK_DIV3 PLL clock divided by 3 selected as USB clock source + */ +void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource)); + + *(__IO uint32_t*)CFG_USBPRES_BB = RCC_USBCLKSource; + *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1; +} + +/** + * @brief Configures the TIM1/8 clock (TIM1/8CLK). + * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source. + * This parameter can be one of the following values: + * @arg RCC_TIM18CLK_SRC_TIM18CLK + * @arg RCC_TIM18CLKSource_AHBCLK + */ +void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource)); + + tmpregister = RCC->CFG2; + /* Clear TIMCLK_SEL bits */ + tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK; + /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */ + tmpregister |= RCC_TIM18CLKSource; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the RNGCCLK prescaler. + * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler. + * This parameter can be one of the following values: + * @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1 + * @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2 + * @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3 + * ... + * @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31 + * @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32 + */ +void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear RNGCPRE[3:0] bits */ + tmpregister &= CFG2_RNGCPRES_RESET_MASK; + /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */ + tmpregister |= RCC_RNGCCLKPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ETH clock (ETHCLK). + * @param RCC_ETHCLKSource specifies the ETH clock source. + * This parameter can be on of the following values: + * @arg RCC_ETHCLK_SRC_IOINPUTCLK + * @arg RCC_ETHCLK_SRC_INTERNALCLK + */ +void RCC_ConfigEthClk(uint32_t RCC_ETHCLKSource) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ETHCLK_SRC(RCC_ETHCLKSource)); + + tmpregister = RCC->CFG2; + /* Clear ETHCLK_SEL bits */ + tmpregister &= CFG2_ETHCLKSEL_RESET_MASK; + /* Set ETHCLK_SEL bits according to RCC_ETHCLKSource value */ + tmpregister |= RCC_ETHCLKSource; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCx 1M clock (ADC1MCLK). + * @param RCC_ADC1MCLKSource specifies the ADC1M clock source. + * This parameter can be on of the following values: + * @arg RCC_ADC1MCLK_SRC_HSI + * @arg RCC_ADC1MCLK_SRC_HSE + * + * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1 + * @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2 + * @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3 + * ... + * @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31 + * @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32 + */ +void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource)); + assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */ + tmpregister &= CFG2_ADC1MSEL_RESET_MASK; + tmpregister &= CFG2_ADC1MPRES_RESET_MASK; + /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */ + tmpregister |= RCC_ADC1MCLKSource; + /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */ + tmpregister |= RCC_ADC1MPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK. + * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable + * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1 + * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2 + * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4 + * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6 + * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8 + * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10 + * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12 + * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16 + * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32 + * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64 + * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256 + * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256 + * + * @param Cmd specifies the ADCPLLCLK enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable ADCPLLCLK + * @arg DISABLE disable ADCPLLCLK + */ +void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + tmpregister = RCC->CFG2; + /* Clear ADCPLLPRES[4:0] bits */ + tmpregister &= CFG2_ADCPLLPRES_RESET_MASK; + + if (Cmd != DISABLE) + { + tmpregister |= RCC_ADCPLLCLKPrescaler; + } + else + { + tmpregister |= RCC_ADCPLLCLKPrescaler; + tmpregister &= RCC_ADCPLLCLK_DISABLE; + } + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the ADCHCLK prescaler. + * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler. + * This parameter can be on of the following values: + * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1 + * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2 + * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4 + * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6 + * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8 + * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10 + * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12 + * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32 + * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32 + */ +void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler)); + + tmpregister = RCC->CFG2; + /* Clear ADCHPRE[3:0] bits */ + tmpregister &= CFG2_ADCHPRES_RESET_MASK; + /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */ + tmpregister |= RCC_ADCHCLKPrescaler; + + /* Store the new value */ + RCC->CFG2 = tmpregister; +} + +/** + * @brief Configures the TRNG 1M clock (TRNG1MCLK). + * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source. + * This parameter can be on of the following values: + * @arg RCC_TRNG1MCLK_SRC_HSI + * @arg RCC_TRNG1MCLK_SRC_HSE + * + * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler. + * This parameter can be on of the following values: + * @arg RCC_TRNG1MCLKDiv_2 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/2 + * @arg RCC_TRNG1MCLKDiv_4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4 + * @arg RCC_TRNG1MCLKDiv_6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6 + * ... + * @arg RCC_TRNG1MCLKDiv_30 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/30 + * @arg RCC_TRNG1MCLKDiv_32 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/32 + */ +void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource)); + assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler)); + + tmpregister = RCC->CFG3; + /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */ + tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK; + tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK; + /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */ + tmpregister |= RCC_TRNG1MCLKSource; + /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */ + tmpregister |= RCC_TRNG1MPrescaler; + + /* Store the new value */ + RCC->CFG3 = tmpregister; +} + +/** + * @brief Enable/disable TRNG clock (TRNGCLK). + * @param Cmd specifies the TRNGCLK enable/disable selection. + * This parameter can be on of the following values: + * @arg ENABLE enable TRNGCLK + * @arg DISABLE disable TRNGCLK + */ +void RCC_EnableTrng1mClk(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE; + } + else + { + RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE; + } +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_DISABLE LSE oscillator OFF + * @arg RCC_LSE_ENABLE LSE oscillator ON + * @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock + */ +void RCC_ConfigLse(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t*)BDCTRL_ADDR = RCC_LSE_DISABLE; + /* Reset LSEBYP bit */ + *(__IO uint8_t*)BDCTRL_ADDR = RCC_LSE_DISABLE; + /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ENABLE: + /* Set LSEON bit */ + *(__IO uint8_t*)BDCTRL_ADDR = RCC_LSE_ENABLE; + break; + + case RCC_LSE_BYPASS: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t*)BDCTRL_ADDR = RCC_LSE_BYPASS | RCC_LSE_ENABLE; + break; + + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableLsi(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @param RCC_RTCCLKSource specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLK_SRC_LSE LSE selected as RTC clock + * @arg RCC_RTCCLK_SRC_LSI LSI selected as RTC clock + * @arg RCC_RTCCLK_SRC_HSE_DIV128 HSE clock divided by 128 selected as RTC clock + */ +void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource)); + + /* Clear the RTC clock source */ + RCC->BDCTRL &= (~0x00000300); + + /* Select the RTC clock source */ + RCC->BDCTRL |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function. + * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableRtcClk(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)BDCTRL_RTCEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold + * the clocks frequencies. + * @note The result of this function could be not correct when using + * fractional value for HSE crystal. + */ +void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks) +{ + uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0; + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFG & CFG_PLLMULFCT_MASK; + pllsource = RCC->CFG & CFG_PLLSRC_MASK; + + if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0) + { + pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0 + } + else + { + pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1 + } + + if (pllsource == 0x00) + { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + pllclk = (HSI_VALUE >> 1) * pllmull; + } + else + { + /* HSE selected as PLL clock entry */ + if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET) + { /* HSE oscillator clock divided by 2 */ + pllclk = (HSE_VALUE >> 1) * pllmull; + } + else + { + pllclk = HSE_VALUE * pllmull; + } + } + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFG & CFG_SCLKSTS_MASK; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SysclkFreq = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SysclkFreq = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + RCC_Clocks->SysclkFreq = pllclk; + break; + + default: + RCC_Clocks->SysclkFreq = HSI_VALUE; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFG & CFG_AHBPRES_SET_MASK; + tmp = tmp >> 4; + presc = s_ApbAhbPresTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFG & CFG_APB1PRES_SET_MASK; + tmp = tmp >> 8; + presc = s_ApbAhbPresTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFG & CFG_APB2PRES_SET_MASK; + tmp = tmp >> 11; + presc = s_ApbAhbPresTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc; + + /* Get ADCHCLK prescaler */ + tmp = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK; + presc = s_AdcHclkPresTable[tmp]; + /* ADCHCLK clock frequency */ + RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc; + /* Get ADCPLLCLK prescaler */ + tmp = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK; + tmp = tmp >> 4; + presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5 + /* ADCPLLCLK clock frequency */ + RCC_Clocks->AdcPllClkFreq = pllclk / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock. + * + * this parameter can be any combination of the following values: + * @arg RCC_AHB_PERIPH_DMA1 + * @arg RCC_AHB_PERIPH_DMA2 + * @arg RCC_AHB_PERIPH_SRAM + * @arg RCC_AHB_PERIPH_FLITF + * @arg RCC_AHB_PERIPH_CRC + * @arg RCC_AHB_PERIPH_XFMC + * @arg RCC_AHB_PERIPH_RNGC + * @arg RCC_AHB_PERIPH_SDIO + * @arg RCC_AHB_PERIPH_SAC + * @arg RCC_AHB_PERIPH_ADC1 + * @arg RCC_AHB_PERIPH_ADC2 + * @arg RCC_AHB_PERIPH_ADC3 + * @arg RCC_AHB_PERIPH_ADC4 + * @arg RCC_AHB_PERIPH_ETHMAC + * @arg RCC_AHB_PERIPH_QSPI + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + RCC->AHBPCLKEN |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCLKEN &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB, + * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_GPIOE, + * RCC_APB2_PERIPH_GPIOF, RCC_APB2_PERIPH_GPIOG, RCC_APB2_PERIPH_TIM1, + * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1, + * RCC_APB2_PERIPH_DVP, RCC_APB2_PERIPH_UART6, RCC_APB2_PERIPH_UART7, + * RCC_APB2_PERIPH_I2C3, RCC_APB2_PERIPH_I2C4 + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB2PCLKEN |= RCC_APB2Periph; + } + else + { + RCC->APB2PCLKEN &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4, + * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7, + * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_TSC, + * RCC_APB1_PERIPH_WWDG, RCC_APB1_PERIPH_SPI2, RCC_APB1_PERIPH_SPI3, + * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_UART4, + * RCC_APB1_PERIPH_UART5, RCC_APB1_PERIPH_I2C1, RCC_APB1_PERIPH_I2C2, + * RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN1, RCC_APB1_PERIPH_CAN2, RCC_APB1_PERIPH_BKP, + * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP + * + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB1PCLKEN |= RCC_APB1Periph; + } + else + { + RCC->APB1PCLKEN &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases AHB peripheral reset. + * @param RCC_AHBPeriph specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB_PERIPH_QSPI. + * RCC_AHB_PERIPH_ETHMAC. + * RCC_AHB_PERIPH_ADC4. + * RCC_AHB_PERIPH_ADC3. + * RCC_AHB_PERIPH_ADC2. + * RCC_AHB_PERIPH_ADC1. + * RCC_AHB_PERIPH_SAC. + * RCC_AHB_PERIPH_RNGC. + * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE. + */ +void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->AHBPRST |= RCC_AHBPeriph; + } + else + { + RCC->AHBPRST &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB, + * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_GPIOE, + * RCC_APB2_PERIPH_GPIOF, RCC_APB2_PERIPH_GPIOG, RCC_APB2_PERIPH_TIM1, + * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1, + * RCC_APB2_PERIPH_DVP, RCC_APB2_PERIPH_UART6, RCC_APB2_PERIPH_UART7, + * RCC_APB2_PERIPH_I2C3, RCC_APB2_PERIPH_I2C4 + * @param Cmd new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB2PRST |= RCC_APB2Periph; + } + else + { + RCC->APB2PRST &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4, + * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7, + * RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG, RCC_APB1_PERIPH_SPI2, + * RCC_APB1_PERIPH_SPI3, RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, + * RCC_APB1_PERIPH_UART4, RCC_APB1_PERIPH_UART5, RCC_APB1_PERIPH_I2C1, + * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN1, + * RCC_APB1_PERIPH_CAN2, RCC_APB1_PERIPH_BKP, RCC_APB1_PERIPH_PWR, + * RCC_APB1_PERIPH_DAC + * @param Cmd new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->APB1PRST |= RCC_APB1Periph; + } + else + { + RCC->APB1PRST &= ~RCC_APB1Periph; + } +} + +/** + * @brief BOR reset enable. + * @param Cmd new state of the BOR reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableBORReset(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + RCC->CFG3 |= RCC_BOR_RST_ENABLE; + } + else + { + RCC->CFG3 &= ~RCC_BOR_RST_ENABLE; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @param Cmd new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableBackupReset(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)BDCTRL_BDSFTRST_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param Cmd new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + */ +void RCC_EnableClockSecuritySystem(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Configures the MCO PLL clock prescaler. + * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler. + * This parameter can be on of the following values: + * @arg RCC_MCO_PLLCLK_DIV2 MCOPRE[3:0] = 0010, PLL Clock Divided By 2 + * @arg RCC_MCO_PLLCLK_DIV3 MCOPRE[3:0] = 0011, PLL Clock Divided By 3 + * @arg RCC_MCO_PLLCLK_DIV4 MCOPRE[3:0] = 0100, PLL Clock Divided By 4 + * @arg RCC_MCO_PLLCLK_DIV5 MCOPRE[3:0] = 0101, PLL Clock Divided By 5 + * ... + * @arg RCC_MCO_PLLCLK_DIV13 MCOPRE[3:0] = 1101, PLL Clock Divided By 13 + * @arg RCC_MCO_PLLCLK_DIV14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14 + * @arg RCC_MCO_PLLCLK_DIV15 MCOPRE[3:0] = 1111, PLL Clock Divided By 15 + */ +void RCC_ConfigMcoPllClk(uint32_t RCC_MCOPLLCLKPrescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_MCOPLLCLKPRE(RCC_MCOPLLCLKPrescaler)); + + tmpregister = RCC->CFG; + /* Clear MCOPRE[3:0] bits */ + tmpregister &= ((uint32_t)0x0FFFFFFF); + /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */ + tmpregister |= RCC_MCOPLLCLKPrescaler; + + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO specifies the clock source to output. + * + * this parameter can be one of the following values: + * @arg RCC_MCO_NOCLK No clock selected + * @arg RCC_MCO_SYSCLK System clock selected + * @arg RCC_MCO_HSI HSI oscillator clock selected + * @arg RCC_MCO_HSE HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK PLL clock divided by xx selected + * + */ +void RCC_ConfigMco(uint8_t RCC_MCO) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + tmpregister = RCC->CFG; + /* Clear MCO[2:0] bits */ + tmpregister &= ((uint32_t)0xF8FFFFFF); + /* Set MCO[2:0] bits according to RCC_MCO value */ + tmpregister |= ((uint32_t)(RCC_MCO << 24)); + + /* Store the new value */ + RCC->CFG = tmpregister; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG specifies the flag to check. + * + * this parameter can be one of the following values: + * @arg RCC_FLAG_HSIRD HSI oscillator clock ready + * @arg RCC_FLAG_HSERD HSE oscillator clock ready + * @arg RCC_FLAG_PLLRD PLL clock ready + * @arg RCC_FLAG_LSERD LSE oscillator clock ready + * @arg RCC_FLAG_LSIRD LSI oscillator clock ready + * @arg RCC_FLAG_BORRST BOR reset flag + * @arg RCC_FLAG_RETEMC Retention EMC reset flag + * @arg RCC_FLAG_BKPEMC BackUp EMC reset flag + * @arg RCC_FLAG_RAMRST RAM reset flag + * @arg RCC_FLAG_MMURST Mmu reset flag + * @arg RCC_FLAG_PINRST Pin reset + * @arg RCC_FLAG_PORRST POR/PDR reset + * @arg RCC_FLAG_SFTRST Software reset + * @arg RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST Window Watchdog reset + * @arg RCC_FLAG_LPWRRST Low Power reset + * + * @return The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CTRL register */ + { + statusreg = RCC->CTRL; + } + else if (tmp == 2) /* The flag to check is in BDCTRL register */ + { + statusreg = RCC->BDCTRL; + } + else /* The flag to check is in CTRLSTS register */ + { + statusreg = RCC->CTRLSTS; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +void RCC_ClrFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CTRLSTS |= CSR_RMRSTF_SET; + /* RMVF bit should be reset */ + RCC->CTRLSTS &= CSR_RMVF_Reset; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RccInt specifies the RCC interrupt source to check. + * + * this parameter can be one of the following values: + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * + * @arg RCC_INT_CLKSSIF Clock Security System interrupt + * + * @return The new state of RccInt (SET or RESET). + */ +INTStatus RCC_GetIntStatus(uint8_t RccInt) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_INT(RccInt)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CLKINT & RccInt) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RccInt status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RccInt specifies the interrupt pending bit to clear. + * + * this parameter can be any combination of the + * following values: + * @arg RCC_INT_LSIRDIF LSI ready interrupt + * @arg RCC_INT_LSERDIF LSE ready interrupt + * @arg RCC_INT_HSIRDIF HSI ready interrupt + * @arg RCC_INT_HSERDIF HSE ready interrupt + * @arg RCC_INT_PLLRDIF PLL ready interrupt + * + * @arg RCC_INT_CLKSSIF Clock Security System interrupt + */ +void RCC_ClrIntPendingBit(uint8_t RccInt) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLR_INT(RccInt)); + + /* Perform Byte access to RCC_CLKINT[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t*)CLKINT_BYTE3_ADDR = RccInt; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_rtc.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_rtc.c new file mode 100644 index 0000000000..8d1641c625 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_rtc.c @@ -0,0 +1,2010 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_rtc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_rtc.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F) + +#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF) +#define RTC_FLAGS_MASK \ + ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF \ + | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF \ + | RTC_FLAG_SHOPF)) + +#define INITMODE_TIMEOUT ((uint32_t)0x00002000) +#define SYNCHRO_TIMEOUT ((uint32_t)0x00008000) +#define RECALPF_TIMEOUT ((uint32_t)0x00001000) +#define SHPF_TIMEOUT ((uint32_t)0x00002000) + +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/** @addtogroup RTC_Private_Functions + * @{ + */ + +/** @addtogroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WRP. + (#) To Configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSYF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function + implements the above software sequence (RSYF clear and RSYF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TSH, DAT and CTRL registers */ + RTC->TSH = (uint32_t)0x00000000; + RTC->DATE = (uint32_t)0x00002101; + + /* Reset All CTRL bits except CTRL[2:0] */ + RTC->CTRL &= (uint32_t)0x00000007; + + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + /* Reset all RTC CTRL register bits */ + RTC->CTRL &= (uint32_t)0x00000000; + RTC->WKUPT = (uint32_t)0x0000FFFF; + RTC->PRE = (uint32_t)0x007F00FF; + RTC->ALARMA = (uint32_t)0x00000000; + RTC->ALARMB = (uint32_t)0x00000000; + RTC->SCTRL = (uint32_t)0x00000000; + RTC->CALIB = (uint32_t)0x00000000; + RTC->ALRMASS = (uint32_t)0x00000000; + RTC->ALRMBSS = (uint32_t)0x00000000; + + /* Reset INTSTS register and exit initialization mode */ + RTC->INITSTS = (uint32_t)0x00000000; + + RTC->OPT = (uint32_t)0x00000000; + RTC->TSCWKUPCTRL = (uint32_t)0x00000008; + RTC->TSCWKUPCNT = (uint32_t)0x000002FE; + + /* Wait till the RTC RSYF flag is set */ + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct pointer to a RTC_InitType structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CTRL HFMT Bit */ + RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT)); + /* Set RTC_CTRL register */ + RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /* Configure the RTC PRE */ + RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct pointer to a RTC_InitType structure which will be + * initialized. + */ +void RTC_StructInit(RTC_InitType* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_INITSTS[13:8]. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param Cmd new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableWriteProtection(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->INITSTS & RTC_INITSTS_INITF; + initcounter++; + } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_EnableWriteProtection(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSYF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TSH and RTC_DATE shadow registers. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear RSYF flag */ + RTC->INITSTS &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF; + synchrocounter++; + } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (status); +} + + + +/** + * @brief Enables or Disables the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param Cmd new state of the Bypass Shadow feature. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableBypassShadow(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Set the BYPS bit */ + RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS; + } + else + { + /* Reset the BYPS bit */ + RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + ##### Time and Date configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Calendar (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains + * the time configuration information for the RTC. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == RTC_FORMAT_BIN) + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->H12)); + } + else + { + RTC_TimeStruct->H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + tmpregister = RTC_Bcd2ToByte(RTC_TimeStruct->Hours); + assert_param(IS_RTC_12HOUR(tmpregister)); + assert_param(IS_RTC_H12(RTC_TimeStruct->H12)); + } + else + { + RTC_TimeStruct->H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds))); + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16)); + } + else + { + tmpregister = + (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TSH register */ + RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be + * initialized. + */ +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->H12 = RTC_AM_H12; + RTC_TimeStruct->Hours = 0; + RTC_TimeStruct->Minutes = 0; + RTC_TimeStruct->Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will + * contain the returned current time configuration. + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours); + RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes); + RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds); + } +} + +/** + * @brief Gets the RTC current Calendar Subseconds value. + * @return RTC current Calendar Subseconds value. + */ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpregister = 0; + + /* Get subseconds values from the correspondent registers*/ + tmpregister = (uint32_t)(RTC->SUBS); + + return (tmpregister); +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_DateStruct pointer to a RTC_DateType structure that contains + * the date configuration information for the RTC. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10)) + { + RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year))); + tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month); + assert_param(IS_RTC_MONTH(tmpregister)); + tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date); + assert_param(IS_RTC_DATE(tmpregister)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DATE register */ + RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct pointer to a RTC_DateType structure which will be + * initialized. + */ +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Date = 1; + RTC_DateStruct->Month = RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_DateStruct pointer to a RTC_DateType structure that will + * contain the returned current date configuration. + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year); + RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month); + RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date); + } +} + +/** + * @} + */ + +/** @addtogroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A and Alarm B) configuration functions + * +@verbatim + =============================================================================== + ##### Alarms (Alarm A and Alarm B) configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_EnableAlarm(DISABLE)). + * @param RTC_Format specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that + * contains the alarm configuration parameters. + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode)); + + if (RTC_Format == RTC_FORMAT_BIN) + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12)); + } + else + { + RTC_AlarmStruct->AlarmTime.H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE) + { + assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue)); + } + else + { + assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue)); + } + } + else + { + if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET) + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + assert_param(IS_RTC_12HOUR(tmpregister)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12)); + } + else + { + RTC_AlarmStruct->AlarmTime.H12 = 0x00; + assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE) + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister)); + } + else + { + tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = + (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds)) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm register */ + if (RTC_Alarm == RTC_A_ALARM) + { + RTC->ALARMA = (uint32_t)tmpregister; + } + else + { + RTC->ALARMB = (uint32_t)tmpregister; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which + * will be initialized. + */ +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12; + RTC_AlarmStruct->AlarmTime.Hours = 0; + RTC_AlarmStruct->AlarmTime.Minutes = 0; + RTC_AlarmStruct->AlarmTime.Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE; + RTC_AlarmStruct->DateWeekValue = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format. + * @arg RTC_FORMAT_BCD BCD data format. + * @param RTC_Alarm specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will + * contains the output alarm configuration values. + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)(RTC->ALARMA); + } + else + { + tmpregister = (uint32_t)(RTC->ALARMB); + } + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->AlarmTime.Hours = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16); + RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8); + RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU)); + RTC_AlarmStruct->AlarmTime.H12 = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16); + RTC_AlarmStruct->DateWeekValue = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24); + RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL); + RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL); + + if (RTC_Format == RTC_FORMAT_BIN) + { + RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes); + RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds); + RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param Cmd new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm state */ + if (Cmd != DISABLE) + { + RTC->CTRL |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8); + alarmcounter++; + } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @brief Configure the RTC AlarmA/B Subseconds value and mask.* + * @note This function is performed only when the Alarm is disabled. + * @param RTC_Alarm specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @param RTC_AlarmSubSecondValue specifies the Subseconds value. + * This parameter can be a value from 0 to 0x00007FFF. + * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask. + * This parameter can be any combination of the following values: + * @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked. + * There is no comparison on sub seconds for Alarm. + * @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison. + * Only SS[0] is compared + * @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison. + * Only SS[1:0] are compared + * @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison. + * Only SS[2:0] are compared + * @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison. + * Only SS[3:0] are compared + * @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison. + * Only SS[4:0] are compared. + * @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison. + * Only SS[5:0] are compared. + * @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison. + * Only SS[6:0] are compared. + * @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison. + * Only SS[7:0] are compared. + * @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison. + * Only SS[8:0] are compared. + * @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison. + * Only SS[9:0] are compared. + * @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison. + * Only SS[10:0] are compared. + * @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison. + * Only SS[11:0] are compared. + * @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison. + * Only SS[12:0] are compared. + * @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison. + * Only SS[13:0] are compared. + * @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match + * to activate alarm. + */ +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM_SEL(RTC_Alarm)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm A or Alarm B SubSecond registers */ + tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); + + if (RTC_Alarm == RTC_A_ALARM) + { + /* Configure the AlarmA SubSecond register */ + RTC->ALRMASS = tmpregister; + } + else + { + /* Configure the Alarm B SubSecond register */ + RTC->ALRMBSS = tmpregister; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Gets the RTC Alarm Subseconds value. + * @param RTC_Alarm specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_A_ALARM to select Alarm A. + * @arg RTC_B_ALARM to select Alarm B. + * @return RTC Alarm Subseconds value. + */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpregister = 0; + + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV); + } + else + { + tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV); + } + + return (tmpregister); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group4 WakeUp Timer configuration functions + * @brief WakeUp Timer configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp Timer configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Wakeup clock source. + * @note The WakeUp Clock source can only be changed when the RTC WakeUp + * is disabled (Use the RTC_EnableWakeUp(DISABLE)). + * @param RTC_WakeUpClock Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16. + * @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8. + * @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4. + * @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2. + * @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE. + */ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the Wakeup Timer clock source bits in CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL; + + /* Configure the clock source */ + RTC->CTRL |= (uint32_t)RTC_WakeUpClock; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configures the RTC Wakeup counter. + * @note The RTC WakeUp counter can only be written when the RTC WakeUp. + * is disabled (Use the RTC_EnableWakeUp(DISABLE)). + * @param RTC_WakeUpCounter specifies the WakeUp counter. + * This parameter can be a value from 0x0000 to 0xFFFF. + */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Wakeup Timer counter */ + RTC->WKUPT = (uint32_t)RTC_WakeUpCounter; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Returns the RTC WakeUp timer counter value. + * @return The RTC WakeUp Counter value. + */ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT)); +} + +/** + * @brief Enables or Disables the RTC WakeUp timer. + * @param Cmd new state of the WakeUp timer. + * This parameter can be: ENABLE or DISABLE. + */ +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN; + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group5 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + ##### Daylight Saving configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaving the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time). + * @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time). + * @param RTC_StoreOperation Specifies the value to be written in the BCK bit + * in CTRL register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_STORE_OPERATION_RESET BCK Bit Reset. + * @arg RTC_STORE_OPERATION_SET BCK Bit Set. + */ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP); + /* Clear the SU1H and AD1H bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H); + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @return RTC Day Light Saving stored operation. + * - RTC_STORE_OPERATION_RESET + * - RTC_STORE_OPERATION_SET + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CTRL & RTC_CTRL_BAKP); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group6 Output pin Configuration function + * @brief Output pin Configuration function + * +@verbatim + =============================================================================== + ##### Output pin Configuration function ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC Output source. + +@endverbatim + * @{ + */ + +// delay +static void Delay(__IO uint32_t nCount) +{ + for (; nCount != 0; nCount--) + ; +} + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_OUTPUT_DIS No output selected + * @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output. + * @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output. + * @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output. + * @param RTC_OutputPolarity Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OUTPOL_HIGH The output pin is high when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL). + * @arg RTC_OUTPOL_LOW The output pin is low when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL). + */ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + __IO uint32_t temp = 0; + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_MODE(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL); + + Delay(0xffff); + + /* Configure the output selection and polarity */ + RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @} + */ + +/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions + * @brief Coarse and Smooth Calibrations configuration functions + * +@verbatim + =============================================================================== + ##### Coarse and Smooth Calibrations configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RTC clock to be output through the relative + * pin. + * @param Cmd new state of the coarse calibration Output. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableCalibOutput(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CTRL |= (uint32_t)RTC_CTRL_COEN; + } + else + { + /* Disable the RTC clock output */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param RTC_CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz. + * @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz. + */ +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /*clear flags before config*/ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL); + + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)RTC_CalibOutput; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Configures the Smooth Calibration Settings. + * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be can be one of the following values: + * @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s. + * @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s. + * @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s. + * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added. + * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Calib registers are configured + * - ERROR: RTC Calib registers are not configured + */ +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue) +{ + ErrorStatus status = ERROR; + uint32_t recalpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* check if a calibration is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses + | (uint32_t)RTC_SmouthCalibMinusPulsesValue); + + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group8 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + ##### TimeStamp configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the + * falling edge of the related pin. + * @param Cmd new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Get the RTC_CTRL register and clear the bits to be configured */ + tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TSPOL | RTC_CTRL_TSEN)); + + /* Get the new configuration */ + if (Cmd != DISABLE) + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN); + } + else + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CTRL = (uint32_t)tmpregister; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN Binary data format + * @arg RTC_FORMAT_BCD BCD data format + * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will + * contains the TimeStamp date values. + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->Year = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours); + RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes); + RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month); + RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date); + RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay); + } +} + +/** + * @brief Get the RTC timestamp Subseconds value. + * @return RTC current timestamp Subseconds value. + */ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp subseconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSS); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group11 Output Type Config configuration functions + * @brief Output Type Config configuration functions + * +@verbatim + =============================================================================== + ##### Output Type Config configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in + * Push Pull mode. + */ +void RTC_ConfigOutputType(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE); + RTC->OPT |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group12 Shift control synchronisation functions + * @brief Shift control synchronisation functions + * +@verbatim + =============================================================================== + ##### Shift control synchronisation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register + * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFT_SUB1S_DISABLE Add one second to the clock calendar. + * @arg RTC_SHIFT_SUB1S_ENABLE No effect. + * @param RTC_ShiftAddFS Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @return An ErrorStatus enumeration value: + * - SUCCESS: RTC Shift registers are configured + * - ERROR: RTC Shift registers are not configured + */ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAddFS, uint32_t RTC_ShiftSub1s) +{ + ErrorStatus status = ERROR; + uint32_t shpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADFS(RTC_ShiftAddFS)); + assert_param(IS_RTC_SHIFT_SUB1S(RTC_ShiftSub1s)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Check if a Shift is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET) + { + + { + /* Configure the Shift settings */ + RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftAddFS) | (uint32_t)(RTC_ShiftSub1s); + + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @addtogroup RTC_Group13 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] All RTC interrupts are connected to the EXTI controller. + (+) To enable the RTC Alarm interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 17 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) + using the RTC_SetAlarm() and RTC_EnableAlarm() functions. + + (+) To enable the RTC Wakeup interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 20 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the + NVIC_Init() function. + (+) Configure the RTC to generate the RTC wakeup timer event using the + RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp() + functions. + + (+) To enable the RTC Tamper interrupt, the following sequence is required: + (+) Configure and enable the EXTI Line 19 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + (+) To enable the RTC TimeStamp interrupt, the following sequence is + required: + (+) Configure and enable the EXTI Line 19 in interrupt mode and select + the rising edge sensitivity using the EXTI_InitPeripheral() function. + (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using + the NVIC_Init() function. + (+) Configure the RTC to detect the RTC time-stamp event using the + RTC_EnableTimeStamp() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_INT_WUT WakeUp Timer interrupt mask. + * @arg RTC_INT_ALRB Alarm B interrupt mask. + * @arg RTC_INT_ALRA Alarm A interrupt mask. + * @param Cmd new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_INT(RTC_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL |= RTC_INT ; + } + else + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL &= (uint32_t) ~(RTC_INT); + } + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_RECPF RECALPF event flag. + * @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag. + * @arg RTC_FLAG_TISF Time Stamp event flag. + * @arg RTC_FLAG_WTF WakeUp Timer flag. + * @arg RTC_FLAG_ALBF Alarm B flag. + * @arg RTC_FLAG_ALAF Alarm A flag. + * @arg RTC_FLAG_INITF Initialization mode flag. + * @arg RTC_FLAG_RSYF Registers Synchronized flag. + * @arg RTC_FLAG_INITSF Registers Configured flag. + * @arg RTC_FLAG_SHOPF Shift operation pending flag. + * @arg RTC_FLAG_WTWF WakeUp Timer Write flag. + * @arg RTC_FLAG_ALBWF Alarm B Write flag. + * @arg RTC_FLAG_ALAWF Alarm A write flag. + * @return The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpregister & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG specifies the RTC flag to clear. + * This parameter can be any combination of the following values:. + * @arg RTC_FLAG_TISOVF Time Stamp Overflow flag. + * @arg RTC_FLAG_TISF Time Stamp event flag. + * @arg RTC_FLAG_WTF WakeUp Timer flag. + * @arg RTC_FLAG_ALBF Alarm B flag. + * @arg RTC_FLAG_ALAF Alarm A flag. + * @arg RTC_FLAG_RSYF Registers Synchronized flag. + */ +void RTC_ClrFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)( + (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x00011FFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_INT specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_INT_WUT WakeUp Timer interrupt. + * @arg RTC_INT_ALRB Alarm B interrupt. + * @arg RTC_INT_ALRA Alarm A interrupt. + * @return The new state of RTC_INT (SET or RESET). + */ +INTStatus RTC_GetITStatus(uint32_t RTC_INT) +{ + INTStatus bitstatus = RESET; + uint32_t tmpregister = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_INT(RTC_INT)); + + /* Get the Interrupt enable Status */ + enablestatus = (uint32_t)((RTC->CTRL & RTC_INT)); + + /* Get the Interrupt pending bit */ + tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4))); + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_INT specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_INT_WUT WakeUp Timer interrupt + * @arg RTC_INT_ALRB Alarm B interrupt + * @arg RTC_INT_ALRA Alarm A interrupt + */ +void RTC_ClrIntPendingBit(uint32_t RTC_INT) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_INT(RTC_INT)); + + /* Get the RTC_INITSTS Interrupt pending bits mask */ + tmpregister = (uint32_t)(RTC_INT >> 4); + + /* Clear the interrupt pending bits in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)( + (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value Byte to be converted. + * @return Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted. + * @return Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} +/** + * @brief Enable wakeup tsc functionand wakeup by the set time + * @param count wakeup time. + */ +void RTC_EnableWakeUpTsc(uint32_t count) +{ + // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1 + while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF)) + { + } + // enter config wakeup cnt mode + RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF; + // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI + RTC->TSCWKUPCNT = count; + // exit config wakeup cnt mode + RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF); + while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF)) + { + } + // TSC wakeup enable + RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_sdio.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_sdio.c new file mode 100644 index 0000000000..25a3bbd9a9 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_sdio.c @@ -0,0 +1,789 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_sdio.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_sdio.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @addtogroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCTRL Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BIT_NUMBER 0x08 +#define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BIT_NUMBER * 4)) + +/* --- CMDCTRL Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIO_SUSPEND_BIT_NUMBER 0x0B +#define CMD_SDIO_SUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIO_SUSPEND_BIT_NUMBER * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define EN_CMD_COMPL_BIT_NUMBER 0x0C +#define EN_CMD_COMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (EN_CMD_COMPL_BIT_NUMBER * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BIT_NUMBER 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BIT_NUMBER * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BIT_NUMBER 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BIT_NUMBER * 4)) + +/* --- DATCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BIT_NUMBER 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BIT_NUMBER * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BIT_NUMBER 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BIT_NUMBER * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BIT_NUMBER 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BIT_NUMBER * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BIT_NUMBER 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BIT_NUMBER * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BIT_NUMBER 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BIT_NUMBER * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCTRL Register ---*/ + +/* CLKCTRL register clear mask */ +#define CLKCTRL_CLR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define POWER_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DATCTRL Register ---*/ + +/* SDIO DATCTRL Clear Mask */ +#define DATCTRL_CLR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMDCTRL Register ---*/ + +/* CMDCTRL Register clear mask */ +#define CMD_CLR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDID_RESPONSE_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @addtogroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + */ +void SDIO_DeInit(void) +{ + SDIO->PWRCTRL = 0x00000000; + SDIO->CLKCTRL = 0x00000000; + SDIO->CMDARG = 0x00000000; + SDIO->CMDCTRL = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DATLEN = 0x00000000; + SDIO->DATCTRL = 0x00000000; + SDIO->INTCLR = 0x00C007FF; + SDIO->INTEN = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct pointer to a SDIO_InitType structure + * that contains the configuration information for the SDIO peripheral. + */ +void SDIO_Init(SDIO_InitType* SDIO_InitStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLK_EDGE(SDIO_InitStruct->ClkEdge)); + assert_param(IS_SDIO_CLK_BYPASS(SDIO_InitStruct->ClkBypass)); + assert_param(IS_SDIO_CLK_POWER_SAVE(SDIO_InitStruct->ClkPwrSave)); + assert_param(IS_SDIO_BUS_WIDTH(SDIO_InitStruct->BusWidth)); + assert_param(IS_SDIO_HARDWARE_CLKCTRL(SDIO_InitStruct->HardwareClkCtrl)); + + /*---------------------------- SDIO CLKCTRL Configuration ------------------------*/ + /* Get the SDIO CLKCTRL value */ + tmpregister = SDIO->CLKCTRL; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpregister &= CLKCTRL_CLR_MASK; + + /* Set CLKDIV bits according to ClkDiv value */ + /* Set PWRSAV bit according to ClkPwrSave value */ + /* Set BYPASS bit according to ClkBypass value */ + /* Set WIDBUS bits according to BusWidth value */ + /* Set NEGEDGE bits according to ClkEdge value */ + /* Set HWFC_EN bits according to HardwareClkCtrl value */ + tmpregister |= (SDIO_InitStruct->ClkDiv | SDIO_InitStruct->ClkPwrSave | SDIO_InitStruct->ClkBypass + | SDIO_InitStruct->BusWidth | SDIO_InitStruct->ClkEdge | SDIO_InitStruct->HardwareClkCtrl); + + /* Write to SDIO CLKCTRL */ + SDIO->CLKCTRL = tmpregister; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct pointer to an SDIO_InitType structure which + * will be initialized. + */ +void SDIO_InitStruct(SDIO_InitType* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->ClkDiv = 0x00; + SDIO_InitStruct->ClkEdge = SDIO_CLKEDGE_RISING; + SDIO_InitStruct->ClkBypass = SDIO_ClkBYPASS_DISABLE; + SDIO_InitStruct->ClkPwrSave = SDIO_CLKPOWERSAVE_DISABLE; + SDIO_InitStruct->BusWidth = SDIO_BUSWIDTH_1B; + SDIO_InitStruct->HardwareClkCtrl = SDIO_HARDWARE_CLKCTRL_DISABLE; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param Cmd new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. + */ +void SDIO_EnableClock(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)CLKCTRL_CLKEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_POWER_CTRL_OFF + * @arg SDIO_POWER_CTRL_ON + */ +void SDIO_SetPower(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_CTRL(SDIO_PowerState)); + + SDIO->PWRCTRL &= POWER_PWRCTRL_MASK; + SDIO->PWRCTRL |= SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @return Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPower(void) +{ + return (SDIO->PWRCTRL & (~POWER_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt + * @arg SDIO_INT_DATTIMEOUT Data timeout interrupt + * @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt + * @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt + * @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt + * @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_INT_DATBLKEND Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDRUN Command transfer in progress interrupt + * @arg SDIO_INT_TXRUN Data transmit in progress interrupt + * @arg SDIO_INT_RXRUN Data receive in progress interrupt + * @arg SDIO_INT_TFIFOHE Transmit DATFIFO Half Empty interrupt + * @arg SDIO_INT_RFIFOHF Receive DATFIFO Half Full interrupt + * @arg SDIO_INT_TFIFOF Transmit DATFIFO full interrupt + * @arg SDIO_INT_RFIFOF Receive DATFIFO full interrupt + * @arg SDIO_INT_TFIFOE Transmit DATFIFO empty interrupt + * @arg SDIO_INT_RFIFOE Receive DATFIFO empty interrupt + * @arg SDIO_INT_TDATVALID Data available in transmit DATFIFO interrupt + * @arg SDIO_INT_RDATVALID Data available in receive DATFIFO interrupt + * @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt + * @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61 interrupt + * @param Cmd new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void SDIO_ConfigInt(uint32_t SDIO_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SDIO_INT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->INTEN |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->INTEN &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param Cmd new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + */ +void SDIO_DMACmd(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)DCTRL_DMAEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct pointer to a SDIO_CmdInitType + * structure that contains the configuration information for the SDIO command. + */ +void SDIO_SendCmd(SDIO_CmdInitType* SDIO_CmdInitStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex)); + assert_param(IS_SDIO_RESP(SDIO_CmdInitStruct->ResponseType)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitType)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSMConfig)); + + /*---------------------------- SDIO CMDARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->CMDARG = SDIO_CmdInitStruct->CmdArgument; + + /*---------------------------- SDIO CMDCTRL Configuration ------------------------*/ + /* Get the SDIO CMDCTRL value */ + tmpregister = SDIO->CMDCTRL; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpregister &= CMD_CLR_MASK; + /* Set CMDINDEX bits according to CmdIndex value */ + /* Set WAITRESP bits according to ResponseType value */ + /* Set WAITINT and WAITPEND bits according to WaitType value */ + /* Set CPSMEN bits according to CPSMConfig value */ + tmpregister |= (uint32_t)SDIO_CmdInitStruct->CmdIndex | SDIO_CmdInitStruct->ResponseType + | SDIO_CmdInitStruct->WaitType | SDIO_CmdInitStruct->CPSMConfig; + + /* Write to SDIO CMDCTRL */ + SDIO->CMDCTRL = tmpregister; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct pointer to an SDIO_CmdInitType + * structure which will be initialized. + */ +void SDIO_InitCmdStruct(SDIO_CmdInitType* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->CmdArgument = 0x00; + SDIO_CmdInitStruct->CmdIndex = 0x00; + SDIO_CmdInitStruct->ResponseType = SDIO_RESP_NO; + SDIO_CmdInitStruct->WaitType = SDIO_WAIT_NO; + SDIO_CmdInitStruct->CPSMConfig = SDIO_CPSM_DISABLE; +} + +/** + * @brief Returns command index of last command for which response received. + * @return Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCmdResp(void) +{ + return (uint8_t)(SDIO->CMDRESP); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESPONSE_1 Response Register 1 + * @arg SDIO_RESPONSE_2 Response Register 2 + * @arg SDIO_RESPONSE_3 Response Register 3 + * @arg SDIO_RESPONSE_4 Response Register 4 + * @return The Corresponding response register value. + */ +uint32_t SDIO_GetResp(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESPONSE(SDIO_RESP)); + + tmp = SDID_RESPONSE_ADDR + SDIO_RESP; + + return (*(__IO uint32_t*)tmp); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct pointer to a SDIO_DataInitType structure that + * contains the configuration information for the SDIO command. + */ +void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct) +{ + uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DAT_LEN(SDIO_DataInitStruct->DatLen)); + assert_param(IS_SDIO_BLK_SIZE(SDIO_DataInitStruct->DatBlkSize)); + assert_param(IS_SDIO_TRANSFER_DIRECTION(SDIO_DataInitStruct->TransferDirection)); + assert_param(IS_SDIO_TRANS_MODE(SDIO_DataInitStruct->TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSMConfig)); + + /*---------------------------- SDIO DATTIMEOUT Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->DatTimeout; + + /*---------------------------- SDIO DATLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DATLEN = SDIO_DataInitStruct->DatLen; + + /*---------------------------- SDIO DATCTRL Configuration ----------------------*/ + /* Get the SDIO DATCTRL value */ + tmpregister = SDIO->DATCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpregister &= DATCTRL_CLR_MASK; + /* Set DEN bit according to DPSMConfig value */ + /* Set DTMODE bit according to TransferMode value */ + /* Set DTDIR bit according to TransferDirection value */ + /* Set DBCKSIZE bits according to DatBlkSize value */ + tmpregister |= (uint32_t)SDIO_DataInitStruct->DatBlkSize | SDIO_DataInitStruct->TransferDirection + | SDIO_DataInitStruct->TransferMode | SDIO_DataInitStruct->DPSMConfig; + + if(SDIO_DataInitStruct->TransferDirection) + { + tmpregister &= ~(1<<12); + } + else + { + tmpregister |= 1<<12; + } + + /* Write to SDIO DATCTRL */ + SDIO->DATCTRL = tmpregister; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct pointer to an SDIO_DataInitType structure which + * will be initialized. + */ +void SDIO_InitDataStruct(SDIO_DataInitType* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->DatTimeout = 0xFFFFFFFF; + SDIO_DataInitStruct->DatLen = 0x00; + SDIO_DataInitStruct->DatBlkSize = SDIO_DATBLK_SIZE_1B; + SDIO_DataInitStruct->TransferDirection = SDIO_TRANSDIR_TOCARD; + SDIO_DataInitStruct->TransferMode = SDIO_TRANSMODE_BLOCK; + SDIO_DataInitStruct->DPSMConfig = SDIO_DPSM_DISABLE; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @return Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCountValue(void) +{ + return SDIO->DATCOUNT; +} + +/** + * @brief Read one data word from Rx DATFIFO. + * @return Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->DATFIFO; +} + +/** + * @brief Write one data word to Tx DATFIFO. + * @param Data 32-bit data word to write. + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->DATFIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from DATFIFO. + * @return Remaining number of words. + */ +uint32_t SDIO_GetFifoCounter(void) +{ + return SDIO->FIFOCOUNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param Cmd new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + */ +void SDIO_EnableReadWait(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)DCTRL_RWSTART_BB = (uint32_t)Cmd; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param Cmd new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + */ +void SDIO_DisableReadWait(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)DCTRL_RWSTOP_BB = (uint32_t)Cmd; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode SD I/O Read Wait operation mode. + * This parameter can be: + * @arg SDIO_RDWAIT_MODE_CLK Read Wait control by stopping SDIOCLK + * @arg SDIO_RDWAIT_MODE_DAT2 Read Wait control using SDIO_DATA2 + */ +void SDIO_EnableSdioReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_RDWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t*)DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param Cmd new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + */ +void SDIO_EnableSdioOperation(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)DCTRL_SDIOEN_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param Cmd new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + */ +void SDIO_EnableSendSdioSuspend(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)CMD_SDIO_SUSPEND_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the command completion signal. + * @param Cmd new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + */ +void SDIO_EnableCommandCompletion(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)EN_CMD_COMPL_BB = (uint32_t)Cmd; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param Cmd new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. + */ +void SDIO_EnableCEATAInt(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)CMD_NIEN_BB = (uint32_t)((~((uint32_t)Cmd)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param Cmd new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. + */ +void SDIO_EnableSendCEATA(FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + *(__IO uint32_t*)CMD_ATACMD_BB = (uint32_t)Cmd; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCERR Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCERR Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CMDTIMEOUT Command response timeout + * @arg SDIO_FLAG_DATTIMEOUT Data timeout + * @arg SDIO_FLAG_TXURERR Transmit DATFIFO underrun error + * @arg SDIO_FLAG_RXORERR Received DATFIFO overrun error + * @arg SDIO_FLAG_CMDRESPRECV Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSEND Command sent (no response required) + * @arg SDIO_FLAG_DATEND Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_SBERR Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DATBLKEND Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDRUN Command transfer in progress + * @arg SDIO_FLAG_TXRUN Data transmit in progress + * @arg SDIO_FLAG_RXRUN Data receive in progress + * @arg SDIO_FLAG_TFIFOHE Transmit DATFIFO Half Empty + * @arg SDIO_FLAG_RFIFOHF Receive DATFIFO Half Full + * @arg SDIO_FLAG_TFIFOF Transmit DATFIFO full + * @arg SDIO_FLAG_RFIFOF Receive DATFIFO full + * @arg SDIO_FLAG_TFIFOE Transmit DATFIFO empty + * @arg SDIO_FLAG_RFIFOE Receive DATFIFO empty + * @arg SDIO_FLAG_TDATVALID Data available in transmit DATFIFO + * @arg SDIO_FLAG_RDATVALID Data available in receive DATFIFO + * @arg SDIO_FLAG_SDIOINT SD I/O interrupt received + * @arg SDIO_FLAG_CEATAF CE-ATA command completion signal received for CMD61 + * @return The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlag(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STS & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCERR Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCERR Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CMDTIMEOUT Command response timeout + * @arg SDIO_FLAG_DATTIMEOUT Data timeout + * @arg SDIO_FLAG_TXURERR Transmit DATFIFO underrun error + * @arg SDIO_FLAG_RXORERR Received DATFIFO overrun error + * @arg SDIO_FLAG_CMDRESPRECV Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSEND Command sent (no response required) + * @arg SDIO_FLAG_DATEND Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_SBERR Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DATBLKEND Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOINT SD I/O interrupt received + * @arg SDIO_FLAG_CEATAF CE-ATA command completion signal received for CMD61 + */ +void SDIO_ClrFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLR_FLAG(SDIO_FLAG)); + + SDIO->INTCLR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt + * @arg SDIO_INT_DATTIMEOUT Data timeout interrupt + * @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt + * @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt + * @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt + * @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_INT_DATBLKEND Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDRUN Command transfer in progress interrupt + * @arg SDIO_INT_TXRUN Data transmit in progress interrupt + * @arg SDIO_INT_RXRUN Data receive in progress interrupt + * @arg SDIO_INT_TFIFOHE Transmit DATFIFO Half Empty interrupt + * @arg SDIO_INT_RFIFOHF Receive DATFIFO Half Full interrupt + * @arg SDIO_INT_TFIFOF Transmit DATFIFO full interrupt + * @arg SDIO_INT_RFIFOF Receive DATFIFO full interrupt + * @arg SDIO_INT_TFIFOE Transmit DATFIFO empty interrupt + * @arg SDIO_INT_RFIFOE Receive DATFIFO empty interrupt + * @arg SDIO_INT_TDATVALID Data available in transmit DATFIFO interrupt + * @arg SDIO_INT_RDATVALID Data available in receive DATFIFO interrupt + * @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt + * @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61 interrupt + * @return The new state of SDIO_IT (SET or RESET). + */ +INTStatus SDIO_GetIntStatus(uint32_t SDIO_IT) +{ + INTStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_INT(SDIO_IT)); + if ((SDIO->STS & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param SDIO_IT specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt + * @arg SDIO_INT_DATTIMEOUT Data timeout interrupt + * @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt + * @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt + * @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt + * @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt + * @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61 + */ +void SDIO_ClrIntPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLR_INT(SDIO_IT)); + + SDIO->INTCLR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_spi.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_spi.c new file mode 100644 index 0000000000..d069e7fe0c --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_spi.c @@ -0,0 +1,862 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_spi.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_spi.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @addtogroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040) +#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400) +#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000) +#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004) +#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0x3040) +#define I2SCFG_CLR_MASK ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_MODE_ENABLE ((uint16_t)0xF7FF) +#define I2S_MODE_ENABLE ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLKSRC ((uint32_t)(0x00020000)) +#define I2S3_CLKSRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @addtogroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + */ +void SPI_I2S_DeInit(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct pointer to a SPI_InitType structure that + * contains the configuration information for the specified SPI peripheral. + */ +void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct) +{ + uint16_t tmpregister = 0; + + /* check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen)); + assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL)); + assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + + /*---------------------------- SPIx CTRL1 Configuration ------------------------*/ + /* Get the SPIx CTRL1 value */ + tmpregister = SPIx->CTRL1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */ + /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */ + /* Set LSBFirst bit according to FirstBit value */ + /* Set BR bits according to BaudRatePres value */ + /* Set CPOL bit according to CLKPOL value */ + /* Set CPHA bit according to CLKPHA value */ + tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode + | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA + | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit); + /* Write to SPIx CTRL1 */ + SPIx->CTRL1 = tmpregister; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */ + SPIx->I2SCFG &= SPI_MODE_ENABLE; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPOLY = SPI_InitStruct->CRCPoly; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct pointer to an I2S_InitType structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + */ +void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct) +{ + uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksType RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_2OR3_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat)); + assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency)); + assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL)); + + /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/ + /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */ + SPIx->I2SCFG &= I2SCFG_CLR_MASK; + SPIx->I2SPREDIV = 0x0002; + + /* Get the I2SCFG register value */ + tmpregister = SPIx->I2SCFG; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if (((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLKSRC; + } + else + { + /* The mask is relative to I2S3 */ + tmp = I2S3_CLKSRC; + } + + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreqValue(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SysclkFreq; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */ + i2sodd = (uint16_t)(i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPREDIV register the computed value */ + SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpregister |= (uint16_t)( + I2S_MODE_ENABLE + | (uint16_t)(I2S_InitStruct->I2sMode + | (uint16_t)(I2S_InitStruct->Standard + | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL)))); + + /* Write to SPIx I2SCFG */ + SPIx->I2SCFG = tmpregister; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized. + */ +void SPI_InitStruct(SPI_InitType* SPI_InitStruct) +{ + /*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the DataDirection member */ + SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + /* initialize the SpiMode member */ + SPI_InitStruct->SpiMode = SPI_MODE_SLAVE; + /* initialize the DataLen member */ + SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS; + /* Initialize the CLKPOL member */ + SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW; + /* Initialize the CLKPHA member */ + SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE; + /* Initialize the NSS member */ + SPI_InitStruct->NSS = SPI_NSS_HARD; + /* Initialize the BaudRatePres member */ + SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2; + /* Initialize the FirstBit member */ + SPI_InitStruct->FirstBit = SPI_FB_MSB; + /* Initialize the CRCPoly member */ + SPI_InitStruct->CRCPoly = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized. + */ +void I2S_InitStruct(I2S_InitType* I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2sMode member */ + I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX; + + /* Initialize the Standard member */ + I2S_InitStruct->Standard = I2S_STD_PHILLIPS; + + /* Initialize the DataFormat member */ + I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS; + + /* Initialize the MCLKEnable member */ + I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE; + + /* Initialize the AudioFrequency member */ + I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT; + + /* Initialize the CLKPOL member */ + I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @param Cmd new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx where x can be 2 or 3 to select the SPI peripheral. + * @param Cmd new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_2OR3_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask + * @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask + * @arg SPI_I2S_INT_ERR Error interrupt mask + * @param Cmd new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd) +{ + uint16_t itpos = 0, itmask = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CTRL2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CTRL2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request + * @param Cmd new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param Data Data to be transmitted. + */ +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Write in the DAT register the data to be sent */ + SPIx->DAT = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @return The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Return the data in the DAT register */ + return SPIx->DAT; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSS_HIGH Set NSS pin internally + * @arg SPI_NSS_LOW Reset NSS pin internally + */ +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSS_LOW) + { + /* Set NSS pin internally by software */ + SPIx->CTRL1 |= SPI_NSS_HIGH; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CTRL1 &= SPI_NSS_LOW; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @param Cmd new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @param DataLen specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit + * @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit + */ +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(DataLen)); + /* Clear DFF bit */ + SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS; + /* Set new DFF bit value */ + SPIx->CTRL1 |= DataLen; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + */ +void SPI_TransmitCrcNext(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @param Cmd new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + */ +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_TX Selects Tx CRC register + * @arg SPI_CRC_RX Selects Rx CRC register + * @return The selected CRC register value.. + */ +uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_RX) + { + /* Get the Tx CRC register */ + crcreg = SPIx->CRCTDAT; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->CRCRDAT; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @return The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPoly(SPI_Module* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPOLY; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral. + * @param DataDirection specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_BIDIRECTION_TX Selects Tx transmission direction + * @arg SPI_BIDIRECTION_RX Selects Rx receive direction + */ +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_BIDIRECTION(DataDirection)); + if (DataDirection == SPI_BIDIRECTION_TX) + { + /* Set the Tx only mode */ + SPIx->CTRL1 |= SPI_BIDIRECTION_TX; + } + else + { + /* Set the Rx only mode */ + SPIx->CTRL1 &= SPI_BIDIRECTION_RX; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_TE_FLAG Transmit buffer empty flag. + * @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag. + * @arg SPI_I2S_BUSY_FLAG Busy flag. + * @arg SPI_I2S_OVER_FLAG Overrun flag. + * @arg SPI_MODERR_FLAG Mode Fault flag. + * @arg SPI_CRCERR_FLAG CRC Error flag. + * @arg I2S_UNDER_FLAG Underrun Error flag. + * @arg I2S_CHSIDE_FLAG Channel Side flag. + * @return The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STS register (SPI_I2S_GetStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STS register (SPI_I2S_GetStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a + * write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI). + */ +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->STS = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_INT_TE Transmit buffer empty interrupt. + * @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt. + * @arg SPI_I2S_INT_OVER Overrun interrupt. + * @arg SPI_INT_MODERR Mode Fault interrupt. + * @arg SPI_INT_CRCERR CRC Error interrupt. + * @arg I2S_INT_UNDER Underrun Error interrupt. + * @return The new state of SPI_I2S_IT (SET or RESET). + */ +INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + INTStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CTRL2 & itmask); + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STS register (SPI_I2S_GetIntStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus()) + * followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable + * the SPI). + */ +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->STS = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_tim.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_tim.c new file mode 100644 index 0000000000..b26d86c0c3 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_tim.c @@ -0,0 +1,3292 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_tim.c + * @author Nations + * @version v1.0.2 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_tim.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @addtogroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCTRL_ETR_MASK ((uint16_t)0x00FF) +#define CAPCMPMOD_OFFSET ((uint16_t)0x0018) +#define CAPCMPEN_CCE_SET ((uint16_t)0x0001) +#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004) + +/** + * @} + */ + +/** @addtogroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter); +/** + * @} + */ + +/** @addtogroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + */ +void TIM_DeInit(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + + if (TIMx == TIM1) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE); + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType + * structure that contains the configuration information for the + * specified TIM peripheral. + */ +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode)); + assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv)); + + tmpcr1 = TIMx->CTRL1; + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode; + } + + if ((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv; + } + + TIMx->CTRL1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->AR = TIM_TimeBaseInitStruct->Period; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE; + + /*channel input from comp or iom*/ + tmpcr1 = TIMx->CTRL1; + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + if (TIM_TimeBaseInitStruct->CapCh1FromCompEn) + tmpcr1 |= (0x01L << 11); + else + tmpcr1 &= ~(0x01L << 11); + } + if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + if (TIM_TimeBaseInitStruct->CapCh2FromCompEn) + tmpcr1 |= (0x01L << 12); + else + tmpcr1 &= ~(0x01L << 12); + if (TIM_TimeBaseInitStruct->CapCh3FromCompEn) + tmpcr1 |= (0x01L << 13); + else + tmpcr1 &= ~(0x01L << 13); + } + if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + if (TIM_TimeBaseInitStruct->CapCh4FromCompEn) + tmpcr1 |= (0x01L << 14); + else + tmpcr1 &= ~(0x01L << 14); + } + /*etr input from comp or iom*/ + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn) + tmpcr1 |= (0x01L << 15); + else + tmpcr1 &= ~(0x01L << 15); + } + TIMx->CTRL1 = tmpcr1; + /*sel etr from iom or tsc*/ + tmpcr1 = TIMx->CTRL2; + if ((TIMx == TIM2) || (TIMx == TIM4)) + { + if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn) + tmpcr1 |= (0x01L << 8); + else + tmpcr1 &= ~(0x01L << 8); + } + TIMx->CTRL2 = tmpcr1; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN); + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + tmpccmrx = TIMx->CCMOD1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->OcMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->OcPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->OutputState; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->OcNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->OutputNState; + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->OcIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->OcNIdleState; + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT1 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + tmpccmrx = TIMx->CCMOD1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN)); + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT2 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + tmpccmrx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->OcMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState)); + assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity)); + assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState)); + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN)); + + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT3 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + tmpccmrx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT4 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel5 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 5: Reset the CC5E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + tmpccmrx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT5 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel6 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct pointer to a OCInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0; + uint32_t tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode)); + assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState)); + assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity)); + /* Disable the Channel 6: Reset the CC6E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN)); + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + /* Get the TIMx CTRL2 register value */ + tmpcr2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + tmpccmrx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = tmpcr2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT6 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IsTimCh(TIM_ICInitStruct->Channel)); + assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection)); + assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler)); + assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity)); + } + else + { + assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity)); + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + assert_param(IsTimList8Module(TIMx)); + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_2) + { + assert_param(IsTimList6Module(TIMx)); + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_3) + { + assert_param(IsTimList3Module(TIMx)); + /* TI3 Configuration */ + ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + assert_param(IsTimList3Module(TIMx)); + /* TI4 Configuration */ + ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure + * that contains the configuration information for the specified TIM peripheral. + */ +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_IC_POLARITY_RISING; + uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING) + { + icoppositepolarity = TIM_IC_POLARITY_FALLING; + } + else + { + icoppositepolarity = TIM_IC_POLARITY_RISING; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI) + { + icoppositeselection = TIM_IC_SELECTION_INDIRECTTI; + } + else + { + icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI2 Configuration */ + ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI1 Configuration */ + ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that + * contains the BKDT Register configuration information for the TIM peripheral. + */ +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + uint32_t tmp; + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState)); + assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState)); + assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel)); + assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break)); + assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel + | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity + | TIM_BDTRInitStruct->AutomaticOutput; + + /*cofigure other break in*/ + tmp = TIMx->CTRL1; + /*IOMBKPEN 0 meaning iom as break enable*/ + if (TIM_BDTRInitStruct->IomBreakEn) + tmp &= ~(0x01L << 10); + else + tmp |= (0x01L << 10); + if (TIM_BDTRInitStruct->LockUpBreakEn) + tmp |= (0x01L << 16); + else + tmp &= ~(0x01L << 16); + if (TIM_BDTRInitStruct->PvdBreakEn) + tmp |= (0x01L << 17); + else + tmp &= ~(0x01L << 17); + TIMx->CTRL1 = tmp; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType + * structure which will be initialized. + */ +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->Period = 0xFFFF; + TIM_TimeBaseInitStruct->Prescaler = 0x0000; + TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP; + TIM_TimeBaseInitStruct->RepetCnt = 0x0000; + + TIM_TimeBaseInitStruct->CapCh1FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh2FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh3FromCompEn = false; + TIM_TimeBaseInitStruct->CapCh4FromCompEn = false; + TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false; + TIM_TimeBaseInitStruct->CapEtrSelFromTscEn = false; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct pointer to a OCInitType structure which will + * be initialized. + */ +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING; + TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE; + TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE; + TIM_OCInitStruct->Pulse = 0x0000; + TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET; + TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will + * be initialized. + */ +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->Channel = TIM_CH_1; + TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI; + TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1; + TIM_ICInitStruct->IcFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which + * will be initialized. + */ +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE; + TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE; + TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = 0x00; + TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx where x can be 1 to 8 to select the TIMx peripheral. + * @param Cmd new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CTRL1 |= TIM_CTRL1_CNTEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx where x can be 1, 8 to select the TIMx peripheral. + * @param Cmd new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BKDT |= TIM_BKDT_MOEN; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx where x can be 1 to 8 to select the TIMx peripheral. + * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_INT_UPDATE TIM update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + * @param Cmd new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimInt(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DINTEN |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DINTEN &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_EventSource specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EVT_SRC_UPDATE Timer update Event source + * @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source + * @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source + * @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source + * @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source + * @arg TIM_EVT_SRC_COM Timer COM event source + * @arg TIM_EVT_SRC_TRIG Timer Trigger Event source + * @arg TIM_EVT_SRC_BREAK Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8. + */ +void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimEvtSrc(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EVTGEN = TIM_EventSource; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_DMABase DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL, + * TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN, + * TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN, + * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR, + * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2, + * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT, + * TIM_DMABASE_CAPCMPMOD3, TIM_DMABASE_CAPCMPDAT5, TIM_DMABASE_CAPCMPDAT6, + * TIM_DMABASE_DMACTRL. + * @param TIM_DMABurstLength DMA Burst length. + * This parameter can be one value between: + * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS. + */ +void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IsTimList4Module(TIMx)); + assert_param(IsTimDmaBase(TIM_DMABase)); + assert_param(IsTimDmaLength(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 + * to select the TIM peripheral. + * @param TIM_DMASource specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_UPDATE TIM update Interrupt source + * @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM TIM Commutation DMA source + * @arg TIM_DMA_TRIG TIM Trigger DMA source + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList9Module(TIMx)); + assert_param(IsTimDmaSrc(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DINTEN |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DINTEN &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 + * to select the TIM peripheral. + */ +void TIM_ConfigInternalClk(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral. + * @param TIM_InputTriggerSource Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 + * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 + * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 + * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 + */ +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimInterTrigSel(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource Trigger source. + * This parameter can be one of the following values: + * @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector + * @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1 + * @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2 + * @param IcPolarity specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param ICFilter specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + */ +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource)); + assert_param(IsTimIcPalaritySingleEdge(IcPolarity)); + assert_param(IsTimInCapFilter(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2) + { + ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + else + { + ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SLAVE_MODE_EXT1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL)); + tmpsmcr |= TIM_TRIG_SEL_ETRF; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCTRL |= TIM_SMCTRL_EXCEN; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. + * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. + * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. + * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. + * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + */ +void TIM_ConfigExtTrig(TIM_Module* TIMx, + uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler)); + assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity)); + assert_param(IsTimExtTrigFilter(ExtTRGFilter)); + tmpsmcr = TIMx->SMCTRL; + /* Reset the ETR Bits */ + tmpsmcr &= SMCTRL_ETR_MASK; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= + (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Prescaler specifies the Prescaler Register value + * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event. + * @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately. + */ +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimPscReloadMode(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EVTGEN = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param CntMode specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CNT_MODE_UP TIM Up Counting Mode + * @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode + * @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1 + * @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2 + * @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3 + */ +void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode) +{ + uint32_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimCntMode(CntMode)); + tmpcr1 = TIMx->CTRL1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + /* Set the Counter Mode */ + tmpcr1 |= CntMode; + /* Write to TIMx CTRL1 register */ + TIMx->CTRL1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 + * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 + * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 + * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 + * @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector + * @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1 + * @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2 + * @arg TIM_TRIG_SEL_ETRF External Trigger input + */ +void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimTrigSel(TIM_InputTriggerSource)); + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_FALLING IC Falling edge. + * @arg TIM_IC_POLARITY_RISING IC Rising edge. + * @param TIM_IC2Polarity specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_FALLING IC Falling edge. + * @arg TIM_IC_POLARITY_RISING IC Rising edge. + */ +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, + uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, + uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IsTimList5Module(TIMx)); + assert_param(IsTimEncodeMode(TIM_EncoderMode)); + assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity)); + assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity)); + + /* Get the TIMx SMCTRL register value */ + tmpsmcr = TIMx->SMCTRL; + + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + + /* Get the TIMx CCEN register value */ + tmpccer = TIMx->CCEN; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL))); + tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P))); + tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmcr; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF. + */ +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF. + */ +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF. + */ +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF. + */ +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 5 waveform to active or inactive level. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF. + */ +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD); + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint16_t)(TIM_ForcedAction); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Forces the TIMx output 6 waveform to active or inactive level. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF + * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF. + */ +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimForceActive(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD); + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on AR. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the AR Preload Bit */ + TIMx->CTRL1 |= TIM_CTRL1_ARPEN; + } + else + { + /* Reset the AR Preload Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx where x can be 1, 8 to select the TIMx peripheral + * @param Cmd new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the COM Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCUSEL; + } + else + { + /* Reset the COM Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param Cmd new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList4Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCDSEL; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 + * to select the TIMx peripheral + * @param Cmd new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList5Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CTRL2 |= TIM_CTRL2_CCPCTL; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT1. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT2. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT3. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT4. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT5. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC5PE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint16_t)(TIM_OCPreload); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCDAT6. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OC_PRE_LOAD_ENABLE + * @arg TIM_OC_PRE_LOAD_DISABLE + */ +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPreLoadState(TIM_OCPreload)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC6PE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select + * the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD1 register value */ + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 5 Fast feature. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4FE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCFast); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 6 Fast feature. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable + * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable + */ +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcFastState(TIM_OCFast)); + /* Get the TIMx CCMOD2 register value */ + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4FE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMOD1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr1 = TIMx->CCMOD1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr2 = TIMx->CCMOD2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF5 signal on an external event + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4CE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCClear); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF6 signal on an external event + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OC_CLR_ENABLE TIM Output clear enable + * @arg TIM_OC_CLR_DISABLE TIM Output clear disable + */ +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr3 = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcClrState(TIM_OCClear)); + tmpccmr3 = TIMx->CCMOD3; + /* Reset the OC4CE Bit */ + tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param OcPolarity specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P); + tmpccer |= OcPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx where x can be 1, 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP); + tmpccer |= OcNPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P); + tmpccer |= (uint32_t)(OcPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP); + tmpccer |= (uint32_t)(OcNPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P); + tmpccer |= (uint32_t)(OcPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcNPolarity specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCN_POLARITY_HIGH Output Compare active high + * @arg TIM_OCN_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcnPolarity(OcNPolarity)); + + tmpccer = TIMx->CCEN; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP); + tmpccer |= (uint32_t)(OcNPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P); + tmpccer |= (uint32_t)(OcPolarity << 12); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 5 polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC5 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC5P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P); + tmpccer |= (uint32_t)(OcPolarity << 16); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configures the TIMx channel 6 polarity. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param OcPolarity specifies the OC6 Polarity + * This parameter can be one of the following values: + * @arg TIM_OC_POLARITY_HIGH Output Compare active high + * @arg TIM_OC_POLARITY_LOW Output Compare active low + */ +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + assert_param(IsTimOcPolarity(OcPolarity)); + tmpccer = TIMx->CCEN; + /* Set or Reset the CC6P Bit */ + tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P); + tmpccer |= (uint32_t)(OcPolarity << 20); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @arg TIM_CH_4 TIM Channel 4 + * @param TIM_CCx specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE. + */ +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimCh(Channel)); + assert_param(IsTimCapCmpState(TIM_CCx)); + + tmp = CAPCMPEN_CCE_SET << Channel; + + /* Reset the CCxE Bit */ + TIMx->CCEN &= (uint32_t)~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx where x can be 1, 8 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE. + */ +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IsTimList2Module(TIMx)); + assert_param(IsTimComplementaryCh(Channel)); + assert_param(IsTimCapCmpNState(TIM_CCxN)); + + tmp = CAPCMPEN_CCNE_SET << Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCEN &= (uint32_t)~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel); +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CH_1 TIM Channel 1 + * @arg TIM_CH_2 TIM Channel 2 + * @arg TIM_CH_3 TIM Channel 3 + * @arg TIM_CH_4 TIM Channel 4 + * @param OcMode specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMODE_TIMING + * @arg TIM_OCMODE_ACTIVE + * @arg TIM_OCMODE_TOGGLE + * @arg TIM_OCMODE_PWM1 + * @arg TIM_OCMODE_PWM2 + * @arg TIM_FORCED_ACTION_ACTIVE + * @arg TIM_FORCED_ACTION_INACTIVE + */ +void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimCh(Channel)); + assert_param(IsTimOc(OcMode)); + + tmp = (uint32_t)TIMx; + tmp += CAPCMPMOD_OFFSET; + + tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCEN &= (uint16_t)~tmp1; + + if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3)) + { + tmp += (Channel >> 1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= OcMode; + } + else + { + tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CTRL1 |= TIM_CTRL1_UPDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_UpdateSource specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow. + */ +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimUpdateSrc(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL) + { + /* Set the URS Bit */ + TIMx->CTRL1 |= TIM_CTRL1_UPRS; + } + else + { + /* Reset the URS Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS); + } +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Cmd new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + */ +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CTRL2 |= TIM_CTRL2_TI1SEL; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_OPMode specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE + * @arg TIM_OPMODE_REPET + */ +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimOpMOde(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM); + /* Configure the OPM Mode */ + TIMx->CTRL1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral. + * @param TIM_TRGOSource specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO). + * + */ +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IsTimList7Module(TIMx)); + assert_param(IsTimTrgoSrc(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL); + /* Select the TRGO source */ + TIMx->CTRL2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_SlaveMode specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter. + */ +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimSlaveMode(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL); + /* Select the Slave Mode */ + TIMx->SMCTRL |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MASTER_SLAVE_MODE_DISABLE No action + */ +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD); + + /* Set or Reset the MSM Bit */ + TIMx->SMCTRL |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Counter specifies the Counter register new value. + */ +void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param Autoreload specifies the Autoreload register new value. + */ +void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Set the Autoreload Register value */ + TIMx->AR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param Compare1 specifies the Capture Compare1 register new value. + */ +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCDAT1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param Compare2 specifies the Capture Compare2 register new value. + */ +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCDAT2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3 specifies the Capture Compare3 register new value. + */ +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCDAT3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4 specifies the Capture Compare4 register new value. + */ +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT4 = Compare4; +} + +/** + * @brief Sets the TIMx Capture Compare5 Register value + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param Compare5 specifies the Capture Compare5 register new value. + */ +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT5 = Compare5; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @param Compare6 specifies the Capture Compare6 register new value. + */ +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT6 = Compare6; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMOD1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMOD2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_IC_PSC_DIV1 no prescaler + * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events + * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events + * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events + */ +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + assert_param(IsTimIcPrescaler(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLK_DIV1 TDTS = Tck_tim + * @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim + * @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim + */ +void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + assert_param(IsTimClkDiv(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD); + /* Set the CKD value */ + TIMx->CTRL1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @return Capture Compare 1 Register value. + */ +uint16_t TIM_GetCap1(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList8Module(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCDAT1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @return Capture Compare 2 Register value. + */ +uint16_t TIM_GetCap2(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList6Module(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCDAT2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @return Capture Compare 3 Register value. + */ +uint16_t TIM_GetCap3(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCDAT3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @return Capture Compare 4 Register value. + */ +uint16_t TIM_GetCap4(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCDAT4; +} + +/** + * @brief Gets the TIMx Input Capture 5 value. + * @param TIMx where x can be 1 8 to select the TIM peripheral. + * @return Capture Compare 5 Register value. + */ +uint16_t TIM_GetCap5(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Get the Capture 5 Register value */ + return TIMx->CCDAT5; +} + +/** + * @brief Gets the TIMx Input Capture 6 value. + * @param TIMx where x can be 1 or 8 to select the TIM peripheral. + * @return Capture Compare 6 Register value. + */ +uint16_t TIM_GetCap6(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimList1Module(TIMx)); + /* Get the Capture 6 Register value */ + return TIMx->CCDAT6; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Counter Register value. + */ +uint16_t TIM_GetCnt(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @return Prescaler Register value. + */ +uint16_t TIM_GetAutoReload(TIM_Module* TIMx) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->AR; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx where x can be 1 to 5 , 8 to select the TIM peripheral. + * @param TIM_CCEN specifies the Bit to check. + * This parameter can be one of the following values: + * @arg TIM_CC1EN CC1EN Bit + * @arg TIM_CC1NEN CC1NEN Bit + * @arg TIM_CC2EN CC2EN Bit + * @arg TIM_CC2NEN CC2NEN Bit + * @arg TIM_CC3EN CC3EN Bit + * @arg TIM_CC3NEN CC3NEN Bit + * @arg TIM_CC4EN CC4EN Bit + * @arg TIM_CC5EN CC5EN Bit + * @arg TIM_CC6EN CC6EN Bit + * @note + * - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8. + * @return The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsTimList3Module(TIMx)); + + if(TIMx==TIM1 || TIMx==TIM8) + { + assert_param(IsAdvancedTimCCENFlag(TIM_CCEN)); + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if(TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 ) + { + assert_param(IsGeneralTimCCENFlag(TIM_CCEN)); + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE TIM update Flag + * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM TIM Commutation Flag + * @arg TIM_FLAG_TRIG TIM Trigger Flag + * @arg TIM_FLAG_BREAK TIM Break Flag + * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag + * @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag + * @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_BREAK is used only with TIM1, TIM8. + * - TIM_FLAG_COM is used only with TIM1, TIM8. + * @return The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimGetFlag(TIM_FLAG)); + + if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_UPDATE TIM update Flag + * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM TIM Commutation Flag + * @arg TIM_FLAG_TRIG TIM Trigger Flag + * @arg TIM_FLAG_BREAK TIM Break Flag + * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_BREAK is used only with TIM1, TIM8. + * - TIM_FLAG_COM is used only with TIM1, TIM8. + */ +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimClrFlag(TIM_FLAG)); + + /* Clear the flags */ + TIMx->STS &= (uint32_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_INT_UPDATE TIM update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + * @return The new state of the TIM_IT(SET or RESET). + */ +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT) +{ + INTStatus bitstatus = RESET; + uint32_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimGetInt(TIM_IT)); + + itstatus = TIMx->STS & TIM_IT; + + itenable = TIMx->DINTEN & TIM_IT; + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_INT_UPDATE TIM1 update Interrupt source + * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source + * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source + * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source + * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source + * @arg TIM_INT_COM TIM Commutation Interrupt source + * @arg TIM_INT_TRIG TIM Trigger Interrupt source + * @arg TIM_INT_BREAK TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_INT_BREAK is used only with TIM1, TIM8. + * - TIM_INT_COM is used only with TIM1, TIM8. + */ +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IsTimAllModule(TIMx)); + assert_param(IsTimInt(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->STS &= (uint32_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2. + * @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN); + tmpccmr1 = TIMx->CCMOD1; + tmpccer = TIMx->CCEN; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F))); + tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmr1; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1. + * @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr1 = 0; + uint32_t tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN); + tmpccmr1 = TIMx->CCMOD1; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F))); + tmpccmr1 |= (uint16_t)(IcFilter << 12); + tmpccmr1 |= (uint16_t)(IcSelection << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmr1; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4. + * @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr2 = 0; + uint32_t tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN); + tmpccmr2 = TIMx->CCMOD2; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F))); + tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN); + } + + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmr2; + TIMx->CCEN = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param IcPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_IC_POLARITY_RISING + * @arg TIM_IC_POLARITY_FALLING + * @param IcSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4. + * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3. + * @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC. + * @param IcFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + */ +static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter) +{ + uint16_t tmpccmr2 = 0; + uint32_t tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN); + tmpccmr2 = TIMx->CCMOD2; + tmpccer = TIMx->CCEN; + tmp = (uint32_t)(IcPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F))); + tmpccmr2 |= (uint16_t)(IcSelection << 8); + tmpccmr2 |= (uint16_t)(IcFilter << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P)); + tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN); + } + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmr2; + TIMx->CCEN = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_tsc.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_tsc.c new file mode 100644 index 0000000000..c2f1b3816e --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_tsc.c @@ -0,0 +1,449 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_tsc.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x.h" +#include "n32g45x_tsc.h" + +/** +* @brief Init TSC config +* @param TSC_Init: TSC initialize structure +* @return : TSC_ErrorTypeDef +*/ +TSC_ErrorTypeDef TSC_Init(TSC_InitType* TSC_Init) +{ + uint32_t tempreg,timeout; + + assert_param(IS_TSC_DET_MODE(TSC_Init->Mode)); + assert_param(IS_TSC_DET_PERIOD(TSC_Init->Period)); + assert_param(IS_TSC_FILTER(TSC_Init->Filter)); + assert_param(IS_TSC_DET_TYPE(TSC_Init->Type)); + assert_param(IS_TSC_INT(TSC_Init->Int)); + assert_param(IS_TSC_OUT(TSC_Init->Out)); + assert_param(IS_TSC_CHN(TSC_Init->Chn)); + assert_param(IS_TSC_PAD_OPTION(TSC_Init->PadOpt)); + assert_param(IS_TSC_PAD_SPEED(TSC_Init->Speed)); + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /*TSC_CTRL config*/ + tempreg = 0; + if(TSC_Init->Mode == TSC_HW_DETECT_MODE) + { + tempreg |= TSC_Init->Period; + tempreg |= TSC_Init->Filter; + tempreg |= TSC_Init->Type; + tempreg |= TSC_Init->Int; + } + else + tempreg |= TSC_Init->Out; + + TSC->CTRL = tempreg; + + /*TSC_ANA_SEL config*/ + TSC->ANA_SEL = TSC_Init->PadOpt | TSC_Init->Speed; + + return TSC_ERROR_OK; +} + +/** + * @brief Config the clock source of TSC + * @param TSC_ClkSource specifies the clock source of TSC + * This parameter can be one of the following values: + * @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default) + * @arg TSC_CLK_SRC_LSE: TSC clock source is LSE,and LSE is oscillator + * @arg TSC_CLK_SRC_LSE_BYPASS: TSC clock source is LSE,and LSE is extennal clock + * @retval TSC error code + */ +TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource) +{ + uint32_t timeout; + + /*Enable PWR peripheral Clock*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE); + + if(TSC_CLK_SRC_LSI == TSC_ClkSource) + { + /*enable LSI clock*/ + RCC_EnableLsi(ENABLE); + + /*Wait LSI stable*/ + timeout = 0; + while(RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET) + { + if(++timeout >TSC_TIMEOUT) + return TSC_ERROR_CLOCK; + } + } + else if((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource)) + { + if(RCC_GetFlagStatus(RCC_FLAG_LSERD)==RESET) + { + // Set bit 8 of PWR_CTRL1.Open PWR DBP. + PWR_BackupAccessEnable(ENABLE); + RCC_ConfigLse(TSC_ClkSource); + timeout = 0; + while(RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET) + { + if(++timeout >TSC_TIMEOUT) + return TSC_ERROR_CLOCK; + } + } + } + else + return TSC_ERROR_PARAMETER; + + /*Enable TSC clk*/ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE); + + return TSC_ERROR_OK; +} + +/** +* @brief Configure internal charge resistor for some channels +* @param res: internal resistor selecte +* This parameter can be one of the following values: +* @arg TSC_RESR_CHN_RESIST_0: 1M OHM +* @arg TSC_RESR_CHN_RESIST_1: 882K OHM +* @arg TSC_RESR_CHN_RESIST_2: 756K OHM +* @arg TSC_RESR_CHN_RESIST_3: 630K OHM +* @arg TSC_RESR_CHN_RESIST_4: 504K OHM +* @arg TSC_RESR_CHN_RESIST_5: 378K OHM +* @arg TSC_RESR_CHN_RESIST_6: 252K OHM +* @arg TSC_RESR_CHN_RESIST_7: 126K OHM +* @param Channels: channels to be configed, as TSC_CHNEN defined +* This parameter:bit[0:23] used,bit[24:31] must be 0 +* bitx: TSC channel x +* @return: none +*/ +TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res ) +{ + uint32_t i,chn,timeout,nReg,nPos; + + assert_param(IS_TSC_CHN(Channels)); + assert_param(IS_TSC_RESISTOR_VALUE(res)); + + /*Check charge resistor value */ + if(res > TSC_RESR_CHN_RESIST_125K) + return TSC_ERROR_PARAMETER; + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /* Mask invalie bits*/ + chn = Channels & TSC_CHNEN_CHN_SEL_MASK; + + /* Set resistance for each channel one by one*/ + for (i = 0; i> 3; + nPos = (i & 0x7UL)*4; + MODIFY_REG(TSC->RESR[nReg],TSC_RESR_CHN_RESIST_MASK<>= 1; + } + + return TSC_ERROR_OK; +} + +/** +* @brief Configure threshold value for some channels +* @param Channels: channels to be configed, as TSC_CHNEN defined +* This parameter:bit[0:23] used,bit[24:31] must be 0 +* bitx: TSC channel x +* @param base: base value of threshold, 0-MAX_TSC_THRESHOLD_BASE +* @param delta: delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA +* @return: None +*/ +TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta) +{ + uint32_t i, chn,timeout; + assert_param(IS_TSC_CHN(Channels)); + assert_param(IS_TSC_THRESHOLD_BASE(base)); + assert_param(IS_TSC_THRESHOLD_DELTA(delta)); + + /*Check the base and delta value*/ + if( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA)) + return TSC_ERROR_PARAMETER; + + /* waiting tsc hw for idle status.*/ + timeout = 0; + do + { + __TSC_HW_DISABLE(); + + if(++timeout > TSC_TIMEOUT) + return TSC_ERROR_HW_MODE; + }while (__TSC_GET_HW_MODE()); + + /*Mask invalie bits*/ + chn = Channels & TSC_CHNEN_CHN_SEL_MASK; + + /* Set the base and delta for each channnel one by one*/ + for (i = 0; iTHRHD[i] = (base<>= 1; + } + + return TSC_ERROR_OK; +} + + +/** +* @brief Get parameters of one channel. +* @param ChnCfg: Pointer of TSC_ChnCfg structure. +* @param ChannelNum: The channel number of which we want to get parameters,must be less then MAX_TSC_HW_CHN +* @return: None +*/ +TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum) +{ + uint32_t nReg,nShift; + + assert_param(IS_TSC_CHN_NUMBER(ChannelNum)); + + /*Check channel number*/ + if(!(IS_TSC_CHN_NUMBER(ChannelNum))) + return TSC_ERROR_PARAMETER; + + /* Get the base and delta value for a channel*/ + ChnCfg->TSC_Base = (TSC->THRHD[ChannelNum] & TSC_THRHD_BASE_MASK) >> TSC_THRHD_BASE_SHIFT; + ChnCfg->TSC_Delta = (TSC->THRHD[ChannelNum] & TSC_THRHD_DELTA_MASK)>> TSC_THRHD_DELTA_SHIFT; + + /* Get the charge resistor type for a channel*/ + nReg = ChannelNum>>3; + nShift = (ChannelNum & 0x7UL)*4; + ChnCfg->TSC_Resistor = (TSC->RESR[nReg] >> nShift) & TSC_RESR_CHN_RESIST_MASK; + + return TSC_ERROR_OK; +} + + +/** + * @brief Get TSC status value. + * @param TSC_Def Pointer of TSC register. + * @param type TSC status type. + */ +uint32_t TSC_GetStatus(TSC_Module* TSC_Def, TSC_Status type) +{ + uint32_t value; + + if (TSC_Def) + { + switch (type) + { + case TSC_ALG_STS_CNTVALUE: + value = __TSC_GET_CHN_CNT(); + break; + + case TSC_ALG_STS_LESS_DET: + value = __TSC_GET_HW_DET_TYPE(TSC_DET_TYPE_LESS); + break; + + case TSC_ALG_STS_GREAT_DET: + value = __TSC_GET_HW_DET_TYPE(TSC_DET_TYPE_GREAT); + break; + + case TSC_ALG_STS_CHN_NUM: + value = __TSC_GET_CHN_NUMBER(); + break; + + case TSC_ALG_DET_DET_ST: + value = __TSC_GET_HW_MODE(); + break; + + default: + value = 0; + break; + } + } + + return value; +} + +/** + * @brief Enable/Disable hardware detection. + * @param TSC_Def Pointer of TSC register. + * @param Channels Set the channel. + * @param Cmd ENABLE:Enable hardware detection,DISALBE:Disable hardware detection. + * @note You can only output one channel at a time. + */ +void TSC_Cmd(TSC_Module* TSC_Def, uint32_t Channels, FunctionalState Cmd) +{ + if(TSC_Def != TSC) + return; + + if (Cmd != DISABLE) + { + // enable tsc channel + Channels &= TSC_CHNEN_CHN_SEL_MASK; + __TSC_CHN_CONFIG(Channels ); + + /* Enable the TSC */ + __TSC_HW_ENABLE(); + } + else + { + /* Disable the TSC */ + while (__TSC_GET_HW_MODE()) + { + __TSC_HW_DISABLE(); + } + + __TSC_CHN_CONFIG(0); + } +} + +/** + * @brief Toggle channels to output to TIMER2/TIMER4 by software mode. + * @param TSC_Def Pointer of TSC register. + * @param Channel Set the channel. + * @param TIMx Select timer. + * @param Cmd ENABLE:Enable hardware detection,DISALBE:Disable hardware detection. + * @note It can only output to TIMER2/TIMER4 by software mode.Other channels are not valid. + */ +void TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Module* TIMx, FunctionalState Cmd) +{ + uint32_t i; + + if(TSC_Def != TSC) + return; + + /* Disable the TSC HW MODE */ + while (__TSC_GET_HW_MODE()) + { + __TSC_HW_DISABLE(); + } + + // waiting tsc hw for idle status. + if ((TIMx != TIM2) && (TIMx != TIM4)) + { + return; + } + + if (Cmd == DISABLE) // Close output by software mode + { + __TSC_OUT_CONFIG(TSC_OUT_PIN); + __TSC_SW_DISABLE(); + } + else + { + for (i = 0; i < MAX_TSC_HW_CHN; i++) + { + if (Channel & 0x00000001) + { + __TSC_SW_CHN_NUM_CONFIG(i); + break; + } + + Channel >>= 1; + } + + // Select to output to specified TIMER. + if (TIMx == TIM4) + { + __TSC_OUT_CONFIG(TSC_OUT_TIM4_ETR); + } + else + { + __TSC_OUT_CONFIG(TSC_OUT_TIM2_ETR); + } + + __TSC_SW_ENABLE(); + } + + // delay time for tsc channel stabilize output + for (i = 0; i < 2000; i++) + { + } +} + +/** + * @brief Configure analog signal parameters. + * @param TSC_Def Pointer of TSC register. + * @param AnaoCfg Pointer of analog parameter structure. + */ +void TSC_SetAnaoCfg(TSC_Module* TSC_Def, TSC_AnaoCfg* AnaoCfg) +{ + if(TSC_Def != TSC) + return; + + if(AnaoCfg == 0) + return; + + __TSC_PAD_OPT_CONFIG(AnaoCfg->TSC_AnaoptrResisOption); + __TSC_PAD_SPEED_CONFIG(AnaoCfg->TSC_AnaoptrSpeedOption); +} + +/** + * @brief Configure channel parameters by channel or operation.Support configure several channels at the same time. + * @param TSC_Def Pointer of TSC register. + * @param ChnCfg Channel parameters. + * @param Channels Set the channels. + */ +void TSC_SetChannelCfg(TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channels) +{ + if(TSC_Def != TSC) + return; + + // Set resistance + TSC_ConfigInternalResistor(Channels, ChnCfg->TSC_Resistor); + + // Set the threshold of base and delta. + TSC_ConfigThreshold(Channels, ChnCfg->TSC_Base, ChnCfg->TSC_Delta); +} + + + diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_usart.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_usart.c new file mode 100644 index 0000000000..fa3ab8302e --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_usart.c @@ -0,0 +1,969 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_usart.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_usart.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @brief USART driver modules + * @{ + */ + +/** @addtogroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Defines + * @{ + */ + +#define CTRL1_UEN_SET ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CTRL1_RCVWU_SET ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CTRL1_SDBRK_SET ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */ +#define CTRL2_ADDR_MASK ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CTRL2_LINMEN_SET ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CTRL2_LINBDL_MASK ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CTRL2_STPB_CLR_MASK ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */ +#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */ + +#define CTRL3_SCMEN_SET ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CTRL3_SCNACK_SET ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CTRL3_HDMEN_SET ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CTRL3_CLR_MASK ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */ + +#define CTRL3_IRDAMEN_SET ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTP_LSB_MASK ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTP_MSB_MASK ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define INT_MASK ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + */ +void USART_DeInit(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_UART4, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_UART4, DISABLE); + } + else if (USARTx == UART5) + { + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_UART5, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_UART5, DISABLE); + } + else if (USARTx == UART6) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART6, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART6, DISABLE); + } + else + { + if (USARTx == UART7) + { + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART7, ENABLE); + RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART7, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct pointer to a USART_InitType structure + * that contains the configuration information for the specified USART + * peripheral. + */ +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct) +{ + uint32_t tmpregister = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksType RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /*---------------------------- USART CTRL2 Configuration -----------------------*/ + tmpregister = USARTx->CTRL2; + /* Clear STOP[13:12] bits */ + tmpregister &= CTRL2_STPB_CLR_MASK; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to StopBits value */ + tmpregister |= (uint32_t)USART_InitStruct->StopBits; + + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint16_t)tmpregister; + + /*---------------------------- USART CTRL1 Configuration -----------------------*/ + tmpregister = USARTx->CTRL1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to WordLength value */ + /* Set PCE and PS bits according to Parity value */ + /* Set TE and RE bits according to Mode value */ + tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode; + /* Write to USART CTRL1 */ + USARTx->CTRL1 = (uint16_t)tmpregister; + + /*---------------------------- USART CTRL3 Configuration -----------------------*/ + tmpregister = USARTx->CTRL3; + /* Clear CTSE and RTSE bits */ + tmpregister &= CTRL3_CLR_MASK; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to HardwareFlowControl value */ + tmpregister |= USART_InitStruct->HardwareFlowControl; + /* Write to USART CTRL3 */ + USARTx->CTRL3 = (uint16_t)tmpregister; + + /*---------------------------- USART PBC Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + if ((usartxbase == USART1_BASE) || (usartxbase == UART6_BASE) || (usartxbase == UART7_BASE)) + { + apbclock = RCC_ClocksStatus.Pclk2Freq; + } + else + { + apbclock = RCC_ClocksStatus.Pclk1Freq; + } + + /* Determine the integer part */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate))); + tmpregister = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpregister >> 4)); + + /* Implement the fractional part in the register */ + tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + + /* Write to USART PBC */ + USARTx->BRCF = (uint16_t)tmpregister; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct pointer to a USART_InitType structure + * which will be initialized. + */ +void USART_StructInit(USART_InitType* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->BaudRate = 9600; + USART_InitStruct->WordLength = USART_WL_8B; + USART_InitStruct->StopBits = USART_STPB_1; + USART_InitStruct->Parity = USART_PE_NO; + USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct pointer to a USART_ClockInitType + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4/UART5/UART6/UART7. + */ +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct) +{ + uint32_t tmpregister = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit)); + + /*---------------------------- USART CTRL2 Configuration -----------------------*/ + tmpregister = USARTx->CTRL2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpregister &= CTRL2_CLOCK_CLR_MASK; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to Clock value */ + /* Set CPOL bit according to Polarity value */ + /* Set CPHA bit according to Phase value */ + /* Set LBCL bit according to LastBit value */ + tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity + | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint16_t)tmpregister; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct pointer to a USART_ClockInitType + * structure which will be initialized. + */ +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->Clock = USART_CLK_DISABLE; + USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW; + USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; + USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param Cmd new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_UEN_SET; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_UEN_RESET; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_INT specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXDE Transmit Data Register empty interrupt + * @arg USART_INT_TXC Transmission complete interrupt + * @arg USART_INT_RXDNE Receive Data register not empty interrupt + * @arg USART_INT_IDLEF Idle line detection interrupt + * @arg USART_INT_PEF Parity Error interrupt + * @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error) + * @param Cmd new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CFG_INT(USART_INT)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + /* The CTS interrupt is not available for UART4/UART5/UART6/UART7 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_INT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_INT & INT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CTRL1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CTRL2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CTRL3 register */ + { + usartxbase += 0x14; + } + if (Cmd != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_DMAReq specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAREQ_TX USART DMA transmit request + * @arg USART_DMAREQ_RX USART DMA receive request + * @param Cmd new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_Addr Indicates the address of the USART node. + */ +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Addr)); + + /* Clear the USART address */ + USARTx->CTRL2 &= CTRL2_ADDR_MASK; + /* Set the USART address node */ + USARTx->CTRL2 |= USART_Addr; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_WakeUpMode specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WUM_IDLELINE WakeUp by an idle line detection + * @arg USART_WUM_ADDRMASK WakeUp by an address mark + */ +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUpMode)); + + USARTx->CTRL1 &= CTRL1_WUM_MASK; + USARTx->CTRL1 |= USART_WakeUpMode; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param Cmd new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_RCVWU_SET; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_RCVWU_RESET; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_LINBreakDetectLength specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBDL_10B 10-bit break detection + * @arg USART_LINBDL_11B 11-bit break detection + */ +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CTRL2 &= CTRL2_LINBDL_MASK; + USARTx->CTRL2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param Cmd new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 |= CTRL2_LINMEN_SET; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 &= CTRL2_LINMEN_RESET; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param Data the data to transmit. + */ +void USART_SendData(USART_Module* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DAT = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + */ +void USART_SendBreak(USART_Module* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CTRL1 |= CTRL1_SDBRK_SET; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime specifies the guard time. + * @note The guard time bits are not available for UART4/UART5/UART6/UART7. + */ +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTP &= GTP_LSB_MASK; + /* Set the USART guard time */ + USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_Prescaler specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + */ +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTP &= GTP_MSB_MASK; + /* Set the USART prescaler */ + USARTx->GTP |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param Cmd new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4/UART5/UART6/UART7. + */ +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCMEN_SET; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCMEN_RESET; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral. + * @param Cmd new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4/UART5/UART6/UART7. + */ +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + if (Cmd != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCNACK_SET; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCNACK_RESET; + } +} + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param Cmd new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_HDMEN_SET; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_HDMEN_RESET; + } +} + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_IrDAMode specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IRDAMODE_LOWPPWER + * @arg USART_IRDAMODE_NORMAL + */ +void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CTRL3 &= CTRL3_IRDALP_MASK; + USARTx->CTRL3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param Cmd new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + */ +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_IRDAMEN_SET; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LINBD LIN Break detection flag + * @arg USART_FLAG_TXDE Transmit data register empty flag + * @arg USART_FLAG_TXC Transmission Complete flag + * @arg USART_FLAG_RXDNE Receive data register not empty flag + * @arg USART_FLAG_IDLEF Idle Line detection flag + * @arg USART_FLAG_OREF OverRun Error flag + * @arg USART_FLAG_NEF Noise Error flag + * @arg USART_FLAG_FEF Framing Error flag + * @arg USART_FLAG_PEF Parity Error flag + * @return The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4/UART5/UART6/UART7 */ + if (USART_FLAG == USART_FLAG_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_FLAG specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LINBD LIN Break detection flag. + * @arg USART_FLAG_TXC Transmission Complete flag. + * @arg USART_FLAG_RXDNE Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + */ +void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4/UART5/UART6/UART7 */ + if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->STS = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_INT specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXDE Tansmit Data Register empty interrupt + * @arg USART_INT_TXC Transmission complete interrupt + * @arg USART_INT_RXDNE Receive Data register not empty interrupt + * @arg USART_INT_IDLEF Idle line detection interrupt + * @arg USART_INT_OREF OverRun Error interrupt + * @arg USART_INT_NEF Noise Error interrupt + * @arg USART_INT_FEF Framing Error interrupt + * @arg USART_INT_PEF Parity Error interrupt + * @return The new state of USART_INT (SET or RESET). + */ +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + INTStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_INT(USART_INT)); + /* The CTS interrupt is not available for UART4/UART5/UART6/UART7 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_INT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_INT & INT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CTRL1 register */ + { + itmask &= USARTx->CTRL1; + } + else if (usartreg == 0x02) /* The IT is in CTRL2 register */ + { + itmask &= USARTx->CTRL2; + } + else /* The IT is in CTRL3 register */ + { + itmask &= USARTx->CTRL3; + } + + bitpos = USART_INT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STS; + if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, UART6 or UART7. + * @param USART_INT specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5) + * @arg USART_INT_LINBD LIN Break detection interrupt + * @arg USART_INT_TXC Transmission complete interrupt. + * @arg USART_INT_RXDNE Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetIntStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetIntStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + */ +void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLR_INT(USART_INT)); + /* The CTS interrupt is not available for UART4/UART5/UART6/UART7 */ + if (USART_INT == USART_INT_CTSF) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_INT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STS = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_wwdg.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_wwdg.c new file mode 100644 index 0000000000..6510972c3e --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_wwdg.c @@ -0,0 +1,223 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_wwdg.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_wwdg.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @addtogroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFG_OFFADDR (WWDG_OFFADDR + 0x04) +#define EWINT_BIT 0x09 +#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CTRL register bit mask */ +#define CTRL_ACTB_SET ((uint32_t)0x00000080) + +/* CFG register bit mask */ +#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F) +#define CFG_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + */ +void WWDG_DeInit(void) +{ + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE); + RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8 + */ +void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler) +{ + uint32_t tmpregister = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpregister = WWDG->CFG & CFG_TIMERB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpregister |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFG = tmpregister; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + */ +void WWDG_SetWValue(uint8_t WindowValue) +{ + __IO uint32_t tmpregister = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WVALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpregister = WWDG->CFG & CFG_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpregister |= WindowValue & (uint32_t)BIT_MASK; + + /* Store the new value */ + WWDG->CFG = tmpregister; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + */ +void WWDG_EnableInt(void) +{ + *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + */ +void WWDG_SetCnt(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_CNT(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CTRL = Counter & BIT_MASK; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_CNT(Counter)); + WWDG->CTRL = CTRL_ACTB_SET | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetEWINTF(void) +{ + return (FlagStatus)(WWDG->STS); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + */ +void WWDG_ClrEWINTF(void) +{ + WWDG->STS = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_xfmc.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_xfmc.c new file mode 100644 index 0000000000..71b66f49c1 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_xfmc.c @@ -0,0 +1,536 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file n32g45x_xfmc.c + * @author Nations + * @version v1.0.1 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "n32g45x_xfmc.h" +#include "n32g45x_rcc.h" + +/** @addtogroup N32G45X_StdPeriph_Driver + * @{ + */ + +/** @addtogroup XFMC + * @brief XFMC driver modules + * @{ + */ + +/** @addtogroup XFMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @addtogroup XFMC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @addtogroup XFMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup XFMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @addtogroup XFMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup XFMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the XFMC NOR/SRAM Banks registers to their default + * reset values. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK1_BLOCK1 XFMC Bank1 NOR/SRAM1 + * @arg XFMC_BANK1_BLOCK2 XFMC Bank1 NOR/SRAM2 + * @retval None + */ +void XFMC_DeInitNorSram(XFMC_Bank1_Block *Block) +{ + /* Check the parameter */ + assert_param(IS_XFMC_NOR_SRAM_BLOCK(Block)); + + /* XFMC_BANK1_BLOCK1 */ + if (Block == XFMC_BANK1_BLOCK1) + { + Block->CRx = XFMC_NOR_SRAM_CR1_RESET; + } + /* XFMC_BANK1_BLOCK2 */ + else + { + Block->CRx = XFMC_NOR_SRAM_CR2_RESET; + } + + Block->TRx = XFMC_NOR_SRAM_TR_RESET; + Block->WTRx = XFMC_NOR_SRAM_WTR_RESET; +} + +/** + * @brief Deinitializes the XFMC NAND Banks registers to their default reset values. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK2_NAND XFMC Bank2 NAND + * @arg XFMC_BANK3_NAND XFMC Bank3 NAND + * @retval None + */ +void XFMC_DeInitNand(XFMC_Bank23_Module *Bank) +{ + /* Check the parameter */ + assert_param(IS_XFMC_NAND_BANK(Bank)); + + Bank->CTRLx = XFMC_NAND_CTRL_RESET; + Bank->STSx = XFMC_NAND_STS_RESET; + Bank->CMEMTMx = XFMC_NAND_CMEMTM_RESET; + Bank->ATTMEMTMx = XFMC_NAND_ATTMEMTM_RESET; +} + +/** + * @brief Initializes the XFMC NOR/SRAM Banks according to the specified + * parameters in the XFMC_NORSRAMInitStruct. + * @param XFMC_NORSRAMInitStruct pointer to a XFMC_NorSramInitTpye + * structure that contains the configuration information for + * the XFMC NOR/SRAM specified Banks. + * @retval None + */ +void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_XFMC_NOR_SRAM_BLOCK(XFMC_NORSRAMInitStruct->Block)); + assert_param(IS_XFMC_NOR_SRAM_MUX(XFMC_NORSRAMInitStruct->DataAddrMux)); + assert_param(IS_XFMC_NOR_SRAM_MEMORY(XFMC_NORSRAMInitStruct->MemType)); + assert_param(IS_XFMC_NOR_SRAM_MEMORY_WIDTH(XFMC_NORSRAMInitStruct->MemDataWidth)); + assert_param(IS_XFMC_NOR_SRAM_BURSTMODE(XFMC_NORSRAMInitStruct->BurstAccMode)); + assert_param(IS_XFMC_NOR_SRAM_ASYNWAIT(XFMC_NORSRAMInitStruct->AsynchroWait)); + assert_param(IS_XFMC_NOR_SRAM_WAIT_POLARITY(XFMC_NORSRAMInitStruct->WaitSigPolarity)); + assert_param(IS_XFMC_NOR_SRAM_WRAP_MODE(XFMC_NORSRAMInitStruct->WrapMode)); + assert_param(IS_XFMC_NOR_SRAM_WAIT_SIGNAL_ACTIVE(XFMC_NORSRAMInitStruct->WaitSigConfig)); + assert_param(IS_XFMC_NOR_SRAM_WRITE_OPERATION(XFMC_NORSRAMInitStruct->WriteEnable)); + assert_param(IS_XFMC_NOR_SRAM_WAITE_SIGNAL(XFMC_NORSRAMInitStruct->WaitSigEnable)); + assert_param(IS_XFMC_NOR_SRAM_EXTENDED_MODE(XFMC_NORSRAMInitStruct->ExtModeEnable)); + assert_param(IS_XFMC_NOR_SRAM_WRITE_BURST(XFMC_NORSRAMInitStruct->WriteBurstEnable)); + assert_param(IS_XFMC_NOR_SRAM_ADDR_SETUP_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime)); + assert_param(IS_XFMC_NOR_SRAM_ADDR_HOLD_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime)); + assert_param(IS_XFMC_NOR_SRAM_DATASETUP_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime)); + assert_param(IS_XFMC_NOR_SRAM_BUSRECOVERY_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle)); + assert_param(IS_XFMC_NOR_SRAM_CLK_DIV(XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv)); + assert_param(IS_XFMC_NOR_SRAM_DATA_LATENCY(XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency)); + assert_param(IS_XFMC_NOR_SRAM_ACCESS_MODE(XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode)); + + /* Bank1 NOR/SRAM control register configuration */ + XFMC_NORSRAMInitStruct->Block->CRx = XFMC_NORSRAMInitStruct->DataAddrMux + | XFMC_NORSRAMInitStruct->MemType + | XFMC_NORSRAMInitStruct->MemDataWidth + | XFMC_NORSRAMInitStruct->BurstAccMode + | XFMC_NORSRAMInitStruct->AsynchroWait + | XFMC_NORSRAMInitStruct->WaitSigPolarity + | XFMC_NORSRAMInitStruct->WrapMode + | XFMC_NORSRAMInitStruct->WaitSigConfig + | XFMC_NORSRAMInitStruct->WriteEnable + | XFMC_NORSRAMInitStruct->WaitSigEnable + | XFMC_NORSRAMInitStruct->ExtModeEnable + | XFMC_NORSRAMInitStruct->WriteBurstEnable; + + if (XFMC_NORSRAMInitStruct->MemType == XFMC_MEM_TYPE_NOR) + { + XFMC_NORSRAMInitStruct->Block->CRx |= (uint32_t)XFMC_NOR_SRAM_ACC_ENABLE; + } + + /* Bank1 NOR/SRAM timing register configuration */ + XFMC_NORSRAMInitStruct->Block->TRx = XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime + | XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime + | XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime + | XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle + | XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv + | XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency + | XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode; + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if (XFMC_NORSRAMInitStruct->ExtModeEnable == XFMC_NOR_SRAM_EXTENDED_ENABLE) + { + assert_param(IS_XFMC_NOR_SRAM_ADDR_SETUP_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime)); + assert_param(IS_XFMC_NOR_SRAM_ADDR_HOLD_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime)); + assert_param(IS_XFMC_NOR_SRAM_DATASETUP_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime)); + assert_param(IS_XFMC_NOR_SRAM_CLK_DIV(XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv)); + assert_param(IS_XFMC_NOR_SRAM_DATA_LATENCY(XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency)); + assert_param(IS_XFMC_NOR_SRAM_ACCESS_MODE(XFMC_NORSRAMInitStruct->WTimingStruct->AccMode)); + XFMC_NORSRAMInitStruct->Block->WTRx = XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime + | XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime + | (XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime << XFMC_BANK1_WTR_DATABLD_SHIFT) + | XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv + | XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency + | XFMC_NORSRAMInitStruct->WTimingStruct->AccMode; + } + else + { + XFMC_NORSRAMInitStruct->Block->WTRx = XFMC_NOR_SRAM_WTR_RESET; + } +} + +/** + * @brief Initializes the XFMC NAND Banks according to the specified + * parameters in the XFMC_NANDInitStruct. + * @param XFMC_NANDInitStruct pointer to a XFMC_NandInitType + * structure that contains the configuration information for the XFMC + * NAND specified Banks. + * @retval None + */ +void XFMC_InitNand(XFMC_NandInitType* XFMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param(IS_XFMC_NAND_BANK(XFMC_NANDInitStruct->Bank)); + assert_param(IS_XFMC_NAND_WAIT_FEATURE(XFMC_NANDInitStruct->WaitFeatureEnable)); + assert_param(IS_XFMC_NAND_BUS_WIDTH(XFMC_NANDInitStruct->MemDataWidth)); + assert_param(IS_XFMC_ECC_STATE(XFMC_NANDInitStruct->EccEnable)); + assert_param(IS_XFMC_NAND_ECC_PAGE_SIZE(XFMC_NANDInitStruct->EccPageSize)); + assert_param(IS_XFMC_NAND_CLE_DELAY(XFMC_NANDInitStruct->TCLRSetTime)); + assert_param(IS_XFMC_NAND_ALE_DELAY(XFMC_NANDInitStruct->TARSetTime)); + assert_param(IS_XFMC_NAND_SETUP_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime)); + assert_param(IS_XFMC_NAND_WAIT_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime)); + assert_param(IS_XFMC_NAND_HOLD_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime)); + assert_param(IS_XFMC_NAND_HIZ_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime)); + assert_param(IS_XFMC_NAND_SETUP_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime)); + assert_param(IS_XFMC_NAND_WAIT_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->WaitSetTime)); + assert_param(IS_XFMC_NAND_HOLD_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime)); + assert_param(IS_XFMC_NAND_HIZ_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime)); + + /* Set the tmppcr value according to XFMC_NANDInitStruct parameters */ + tmppcr = XFMC_BANK23_MEM_TYPE_NAND + | XFMC_NANDInitStruct->WaitFeatureEnable + | XFMC_NANDInitStruct->MemDataWidth + | XFMC_NANDInitStruct->EccEnable + | XFMC_NANDInitStruct->EccPageSize + | XFMC_NANDInitStruct->TCLRSetTime + | XFMC_NANDInitStruct->TARSetTime; + + /* Set tmppmem value according to XFMC_CommonSpaceTimingStructure parameters */ + tmppmem = (XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime << XFMC_CMEMTM_SET_SHIFT) + | (XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime << XFMC_CMEMTM_WAIT_SHIFT) + | (XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime << XFMC_CMEMTM_HLD_SHIFT) + | (XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime << XFMC_CMEMTM_HIZ_SHIFT); + + /* Set tmppatt value according to XFMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime <AttrSpaceTimingStruct->WaitSetTime << XFMC_ATTMEMTM_WAIT_SHIFT) + | (XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime << XFMC_ATTMEMTM_HLD_SHIFT) + | (XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime << XFMC_ATTMEMTM_HIZ_SHIFT); + + XFMC_NANDInitStruct->Bank->CTRLx = tmppcr; + XFMC_NANDInitStruct->Bank->CMEMTMx = tmppmem; + XFMC_NANDInitStruct->Bank->ATTMEMTMx = tmppatt; +} + +/** + * @brief Fills each XFMC_NORSRAMInitStruct member with its default value. + * @param XFMC_NORSRAMInitStruct pointer to a XFMC_NorSramInitTpye + * structure which will be initialized. + * @retval None + */ +void XFMC_InitNorSramStruct(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + XFMC_NORSRAMInitStruct->Block = XFMC_BANK1_BLOCK1; + XFMC_NORSRAMInitStruct->DataAddrMux = XFMC_NOR_SRAM_MUX_ENABLE; + XFMC_NORSRAMInitStruct->MemType = XFMC_MEM_TYPE_SRAM; + XFMC_NORSRAMInitStruct->MemDataWidth = XFMC_NOR_SRAM_DATA_WIDTH_8B; + XFMC_NORSRAMInitStruct->BurstAccMode = XFMC_NOR_SRAM_BURST_MODE_DISABLE; + XFMC_NORSRAMInitStruct->AsynchroWait = XFMC_NOR_SRAM_ASYNC_NWAIT_DISABLE; + XFMC_NORSRAMInitStruct->WaitSigPolarity = XFMC_NOR_SRAM_WAIT_SIGNAL_LOW; + XFMC_NORSRAMInitStruct->WrapMode = XFMC_NOR_SRAM_WRAP_DISABLE; + XFMC_NORSRAMInitStruct->WaitSigConfig = XFMC_NOR_SRAM_NWAIT_BEFORE_STATE; + XFMC_NORSRAMInitStruct->WriteEnable = XFMC_NOR_SRAM_WRITE_ENABLE; + XFMC_NORSRAMInitStruct->WaitSigEnable = XFMC_NOR_SRAM_NWAIT_ENABLE; + XFMC_NORSRAMInitStruct->ExtModeEnable = XFMC_NOR_SRAM_EXTENDED_DISABLE; + XFMC_NORSRAMInitStruct->WriteBurstEnable = XFMC_NOR_SRAM_BURST_WRITE_DISABLE; + XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime = XFMC_NOR_SRAM_ADDR_SETUP_TIME_16HCLK; + XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime = XFMC_NOR_SRAM_ADDR_HOLD_TIME_16HCLK; + XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime = XFMC_NOR_SRAM_DATA_SETUP_TIME_MAX; + XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle = XFMC_NOR_SRAM_BUSRECOVERY_TIME_16HCLK; + XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv = XFMC_NOR_SRAM_CLK_DIV_16; + XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency = XFMC_NOR_SRAM_DATA_LATENCY_17CLK; + XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode = XFMC_NOR_SRAM_ACC_MODE_A; + XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime = XFMC_NOR_SRAM_ADDR_SETUP_TIME_16HCLK; + XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime = XFMC_NOR_SRAM_ADDR_HOLD_TIME_16HCLK; + XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime = XFMC_NOR_SRAM_DATA_SETUP_TIME_MAX; + XFMC_NORSRAMInitStruct->WTimingStruct->BusRecoveryCycle = XFMC_NOR_SRAM_BUSRECOVERY_TIME_16HCLK; + XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv = XFMC_NOR_SRAM_CLK_DIV_16; + XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency = XFMC_NOR_SRAM_DATA_LATENCY_17CLK; + XFMC_NORSRAMInitStruct->WTimingStruct->AccMode = XFMC_NOR_SRAM_ACC_MODE_A; +} + +/** + * @brief Fills each XFMC_NANDInitStruct member with its default value. + * @param XFMC_NANDInitStruct pointer to a XFMC_NandInitType + * structure which will be initialized. + * @retval None + */ +void XFMC_InitNandStruct(XFMC_NandInitType* XFMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + XFMC_NANDInitStruct->Bank = XFMC_BANK2; + XFMC_NANDInitStruct->WaitFeatureEnable = XFMC_NAND_NWAIT_DISABLE; + XFMC_NANDInitStruct->MemDataWidth = XFMC_NAND_BUS_WIDTH_8B; + XFMC_NANDInitStruct->EccEnable = XFMC_NAND_ECC_DISABLE; + XFMC_NANDInitStruct->EccPageSize = XFMC_NAND_ECC_PAGE_256BYTES; + XFMC_NANDInitStruct->TCLRSetTime = XFMC_NAND_CLE_DELAY_1HCLK; + XFMC_NANDInitStruct->TARSetTime = XFMC_NAND_ALE_DELAY_1HCLK; + XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime = XFMC_NAND_SETUP_TIME_DEFAULT; + XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime = XFMC_NAND_WAIT_TIME_DEFAULT; + XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime = XFMC_NAND_HOLD_TIME_DEFAULT; + XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime = XFMC_NAND_HIZ_TIME_DEFAULT; + XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime = XFMC_NAND_SETUP_TIME_DEFAULT; + XFMC_NANDInitStruct->AttrSpaceTimingStruct->WaitSetTime = XFMC_NAND_WAIT_TIME_DEFAULT; + XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime = XFMC_NAND_HOLD_TIME_DEFAULT; + XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime = XFMC_NAND_HIZ_TIME_DEFAULT; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK1_BLOCK1 XFMC Bank1 NOR/SRAM block1 + * @arg XFMC_BANK1_BLOCK2 XFMC Bank1 NOR/SRAM block2 + * @param Cmd new state of the Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void XFMC_EnableNorSram(XFMC_Bank1_Block *Block, FunctionalState Cmd) +{ + assert_param(IS_XFMC_NOR_SRAM_BLOCK(Block)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + Block->CRx |= XFMC_NOR_SRAM_ENABLE; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + Block->CRx &= ~XFMC_NOR_SRAM_ENABLE; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK2 XFMC Bank2 NAND + * @arg XFMC_BANK3 XFMC Bank3 NAND + * @param Cmd new state of the Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void XFMC_EnableNand(XFMC_Bank23_Module *Bank, FunctionalState Cmd) +{ + assert_param(IS_XFMC_NAND_BANK(Bank)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + Bank->CTRLx |= XFMC_NAND_BANK_ENABLE; + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + Bank->CTRLx &= ~XFMC_NAND_BANK_ENABLE; + } +} + +/** + * @brief Enables or disables the XFMC NAND ECC feature. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK2 XFMC Bank2 NAND + * @arg XFMC_BANK3 XFMC Bank3 NAND + * @param Cmd new state of the XFMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void XFMC_EnableNandEcc(XFMC_Bank23_Module *Bank, FunctionalState Cmd) +{ + assert_param(IS_XFMC_NAND_BANK(Bank)); + assert_param(IS_FUNCTIONAL_STATE(Cmd)); + + if (Cmd != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + Bank->CTRLx |= XFMC_NAND_ECC_ENABLE; + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + Bank->CTRLx &= ~XFMC_NAND_ECC_ENABLE; + } +} + +/** + * @brief Clear ECC result and start a new ECC process. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK2 XFMC Bank2 NAND + * @arg XFMC_BANK3 XFMC Bank3 NAND + * @retval None + */ +void XFMC_RestartNandEcc(XFMC_Bank23_Module *Bank) +{ + Bank->CTRLx &= ~XFMC_NAND_ECC_ENABLE; + Bank->CTRLx |= XFMC_NAND_ECC_ENABLE; +} + +/** + * @brief Returns the error correction code register value. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK2 XFMC Bank2 NAND + * @arg XFMC_BANK3 XFMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t XFMC_GetEcc(XFMC_Bank23_Module *Bank) +{ + uint32_t tEccPageSize,tECC = 0; + + assert_param(IS_XFMC_NAND_BANK(Bank)); + + tEccPageSize = Bank->CTRLx & XFMC_CTRL_ECCPGS_MASK; + + switch(tEccPageSize) + { + case XFMC_NAND_ECC_PAGE_256BYTES: + tECC = Bank->ECCx & XFMC_ECC_PAGE_256BYTE_MASK; + break; + case XFMC_NAND_ECC_PAGE_512BYTES: + tECC = Bank->ECCx & XFMC_ECC_PAGE_512BYTE_MASK; + break; + case XFMC_NAND_ECC_PAGE_1024BYTES: + tECC = Bank->ECCx & XFMC_ECC_PBAE_1024BYTE_MASK; + break; + case XFMC_NAND_ECC_PAGE_2048BYTES: + tECC = Bank->ECCx & XFMC_ECC_PBAE_2048BYTE_MASK; + break; + case XFMC_NAND_ECC_PAGE_4096BYTES: + tECC = Bank->ECCx & XFMC_ECC_PBAE_4096BYTE_MASK; + break; + case XFMC_NAND_ECC_PAGE_8192BYTES: + tECC = Bank->ECCx & XFMC_ECC_PBAE_8192BYTE_MASK; + break; + default: + break; + } + + /* Return the error correction code value */ + return (tECC); +} + +/** + * @brief Checks whether the specified XFMC flag is set or not. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK2 XFMC Bank2 NAND + * @arg XFMC_BANK3 XFMC Bank3 NAND + * @param XFMC_FLAG specifies the flag to check. + * This parameter can be one of the following values: + * @arg XFMC_FLAG_FIFO_EMPTY Fifo empty Flag. + * @retval The new state of XFMC_FLAG (SET or RESET). + */ +FlagStatus XFMC_GetFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_XFMC_NAND_BANK(Bank)); + assert_param(IS_XFMC_NAND_FLAG(XFMC_FLAG)); + + /* Get the flag status */ + if ((Bank->STSx & XFMC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the XFMC's pending flags. + * @param Bank specifies the XFMC Bank to be used + * This parameter can be one of the following values: + * @arg XFMC_BANK2 XFMC Bank2 NAND + * @arg XFMC_BANK3 XFMC Bank3 NAND + * @param XFMC_FLAG specifies the flag to clear. + * This parameter can be one of the following values: + * @arg XFMC_FLAG_FIFO_EMPTY Fifo empty Flag. + * @retval None + */ +void XFMC_ClrFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_XFMC_NAND_BANK(Bank)); + assert_param(IS_XFMC_NAND_FLAG(XFMC_FLAG)); + + Bank->STSx &= ~XFMC_FLAG; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_core.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_core.h new file mode 100644 index 0000000000..c2a9d3d07e --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_core.h @@ -0,0 +1,264 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_CORE_H__ +#define __USB_CORE_H__ + +#include "n32g45x.h" + +/** + * @addtogroup N32G45X_USB_Driver + * @brief N32G45x USB low level driver + * @{ + */ + +typedef enum _CONTROL_STATE +{ + WaitSetup, /* 0 */ + SettingUp, /* 1 */ + InData, /* 2 */ + OutData, /* 3 */ + LastInData, /* 4 */ + LastOutData, /* 5 */ + WaitStatusIn, /* 7 */ + WaitStatusOut, /* 8 */ + Stalled, /* 9 */ + Pause /* 10 */ +} USB_ControlState; /* The state machine states of a control pipe */ + +typedef struct OneDescriptor +{ + uint8_t* Descriptor; + uint16_t Descriptor_Size; +} USB_OneDescriptor, *PONE_DESCRIPTOR; +/* All the request process routines return a value of this type + If the return value is not SUCCESS or NOT_READY, + the software will STALL the correspond endpoint */ +typedef enum _RESULT +{ + Success = 0, /* Process successfully */ + Error, + UnSupport, + Not_Ready /* The process has not been finished, endpoint will be + NAK to further request */ +} USB_Result; + +/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/ +typedef struct _ENDPOINT_INFO +{ + /* When send data out of the device, + CopyData() is used to get data buffer 'Length' bytes data + if Length is 0, + CopyData() returns the total length of the data + if the request is not supported, returns 0 + (NEW Feature ) + if CopyData() returns -1, the calling routine should not proceed + further and will resume the SETUP process by the class device + if Length is not 0, + CopyData() returns a pointer to indicate the data location + Usb_wLength is the data remain to be sent, + Usb_wOffset is the Offset of original data + When receive data from the host, + CopyData() is used to get user data buffer which is capable + of Length bytes data to copy data from the endpoint buffer. + if Length is 0, + CopyData() returns the available data length, + if Length is not 0, + CopyData() returns user buffer address + Usb_rLength is the data remain to be received, + Usb_rPointer is the Offset of data buffer + */ + uint16_t Usb_wLength; + uint16_t Usb_wOffset; + uint16_t PacketSize; + uint8_t* (*CopyData)(uint16_t Length); +} USB_EndpointMess; + +/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/ + +typedef struct _DEVICE +{ + uint8_t TotalEndpoint; /* Number of endpoints that are used */ + uint8_t TotalConfiguration; /* Number of configuration available */ +} USB_Device; + +typedef union +{ + uint16_t w; + struct BW + { + uint8_t bb1; + uint8_t bb0; + } bw; +} uint16_t_uint8_t; + +typedef struct _DEVICE_INFO +{ + uint8_t bmRequestType; /* bmRequestType */ + uint8_t bRequest; /* bRequest */ + uint16_t_uint8_t wValues; /* wValue */ + uint16_t_uint8_t wIndexs; /* wIndex */ + uint16_t_uint8_t wLengths; /* wLength */ + + uint8_t CtrlState; /* of type USB_ControlState */ + uint8_t CurrentFeature; + uint8_t CurrentConfiguration; /* Selected configuration */ + uint8_t CurrentInterface; /* Selected interface of current configuration */ + uint8_t CurrentAlternateSetting; /* Selected Alternate Setting of current + interface*/ + + USB_EndpointMess Ctrl_Info; +} USB_DeviceMess; + +typedef struct _DEVICE_PROP +{ + void (*Init)(void); /* Initialize the device */ + void (*Reset)(void); /* Reset routine of this device */ + + /* Device dependent process after the status stage */ + void (*Process_Status_IN)(void); + void (*Process_Status_OUT)(void); + + /* Procedure of process on setup stage of a class specified request with data stage */ + /* All class specified requests with data stage are processed in Class_Data_Setup + Class_Data_Setup() + responses to check all special requests and fills USB_EndpointMess + according to the request + If IN tokens are expected, then wLength & wOffset will be filled + with the total transferring bytes and the starting position + If OUT tokens are expected, then rLength & rOffset will be filled + with the total expected bytes and the starting position in the buffer + + If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT + + CAUTION: + Since GET_CONFIGURATION & GET_INTERFACE are highly related to + the individual classes, they will be checked and processed here. + */ + USB_Result (*Class_Data_Setup)(uint8_t RequestNo); + + /* Procedure of process on setup stage of a class specified request without data stage */ + /* All class specified requests without data stage are processed in Class_NoData_Setup + Class_NoData_Setup + responses to check all special requests and perform the request + + CAUTION: + Since SET_CONFIGURATION & SET_INTERFACE are highly related to + the individual classes, they will be checked and processed here. + */ + USB_Result (*Class_NoData_Setup)(uint8_t RequestNo); + + /*Class_Get_Interface_Setting + This function is used by the file usb_core.c to test if the selected Interface + and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by + the application. + This function is writing by user. It should return "SUCCESS" if the Interface + and Alternate Setting are supported by the application or "UNSUPPORT" if they + are not supported. */ + + USB_Result (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting); + + uint8_t* (*GetDeviceDescriptor)(uint16_t Length); + uint8_t* (*GetConfigDescriptor)(uint16_t Length); + uint8_t* (*GetStringDescriptor)(uint16_t Length); + + /* This field is not used in current library version. It is kept only for + compatibility with previous versions */ + void* RxEP_buffer; + + uint8_t MaxPacketSize; + +} DEVICE_PROP; + +typedef struct _USER_STANDARD_REQUESTS +{ + void (*User_GetConfiguration)(void); /* Get Configuration */ + void (*User_SetConfiguration)(void); /* Set Configuration */ + void (*User_GetInterface)(void); /* Get Interface */ + void (*User_SetInterface)(void); /* Set Interface */ + void (*User_GetStatus)(void); /* Get Status */ + void (*User_ClearFeature)(void); /* Clear Feature */ + void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */ + void (*User_SetDeviceFeature)(void); /* Set Device Feature */ + void (*User_SetDeviceAddress)(void); /* Set Device Address */ +} USER_STANDARD_REQUESTS; + +#define Type_Recipient (pInformation->bmRequestType & (REQUEST_TYPE | RECIPIENT)) + +#define Usb_rLength Usb_wLength +#define Usb_rOffset Usb_wOffset + +#define USBwValue wValues.w +#define USBwValue0 wValues.bw.bb0 +#define USBwValue1 wValues.bw.bb1 +#define USBwIndex wIndexs.w +#define USBwIndex0 wIndexs.bw.bb0 +#define USBwIndex1 wIndexs.bw.bb1 +#define USBwLength wLengths.w +#define USBwLength0 wLengths.bw.bb0 +#define USBwLength1 wLengths.bw.bb1 + +uint8_t USB_ProcessSetup0(void); +uint8_t USB_ProcessPost0(void); +uint8_t USB_ProcessOut0(void); +uint8_t USB_ProcessIn0(void); + +USB_Result Standard_SetEndPointFeature(void); +USB_Result Standard_SetDeviceFeature(void); + +uint8_t* Standard_GetConfiguration(uint16_t Length); +USB_Result Standard_SetConfiguration(void); +uint8_t* Standard_GetInterface(uint16_t Length); +USB_Result Standard_SetInterface(void); +uint8_t* Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc); + +uint8_t* Standard_GetStatus(uint16_t Length); +USB_Result Standard_ClearFeature(void); +void USB_SetDeviceAddress(uint8_t); +void USB_ProcessNop(void); + +extern DEVICE_PROP Device_Property; +extern USER_STANDARD_REQUESTS User_Standard_Requests; +extern USB_Device Device_Table; +extern USB_DeviceMess Device_Info; + +/* cells saving status during interrupt servicing */ +extern __IO uint16_t SaveRState; +extern __IO uint16_t SaveTState; + +/** + * @} + */ + +#endif /* __USB_CORE_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_def.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_def.h new file mode 100644 index 0000000000..b981786024 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_def.h @@ -0,0 +1,98 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_def.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_DEF_H__ +#define __USB_DEF_H__ + +/** + * @addtogroup N32G45X_USB_Driver + * @{ + */ + +typedef enum _RECIPIENT_TYPE +{ + DEVICE_RECIPIENT, /* Recipient device */ + INTERFACE_RECIPIENT, /* Recipient interface */ + ENDPOINT_RECIPIENT, /* Recipient endpoint */ + OTHER_RECIPIENT +} RECIPIENT_TYPE; + +typedef enum _STANDARD_REQUESTS +{ + GET_STATUS = 0, + CLR_FEATURE, + RESERVED1, + SET_FEATURE, + RESERVED2, + SET_ADDRESS, + GET_DESCRIPTOR, + SET_DESCRIPTOR, + GET_CONFIGURATION, + SET_CONFIGURATION, + GET_INTERFACE, + SET_INTERFACE, + TOTAL_SREQUEST, /* Total number of Standard request */ + SYNCH_FRAME = 12 +} STANDARD_REQUESTS; + +/* Definition of "USBwValue" */ +typedef enum _DESCRIPTOR_TYPE +{ + DEVICE_DESCRIPTOR = 1, + CONFIG_DESCRIPTOR, + STRING_DESCRIPTOR, + INTERFACE_DESCRIPTOR, + ENDPOINT_DESCRIPTOR +} DESCRIPTOR_TYPE; + +/* Feature selector of a SET_FEATURE or CLR_FEATURE */ +typedef enum _FEATURE_SELECTOR +{ + ENDPOINT_STALL, + DEVICE_REMOTE_WAKEUP +} FEATURE_SELECTOR; + +/* Definition of "bmRequestType" */ +#define REQUEST_TYPE 0x60 /* Mask to get request type */ +#define STANDARD_REQUEST 0x00 /* Standard request */ +#define CLASS_REQUEST 0x20 /* Class request */ +#define VENDOR_REQUEST 0x40 /* Vendor request */ + +#define RECIPIENT 0x1F /* Mask to get recipient */ + +/** + * @} + */ + +#endif /* __USB_DEF_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_init.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_init.h new file mode 100644 index 0000000000..6378061427 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_init.h @@ -0,0 +1,71 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_init.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_INIT_H__ +#define __USB_INIT_H__ + +#include "n32g45x.h" +#include "usb_core.h" + +/** + * @addtogroup N32G45X_USB_Driver + * @{ + */ + +void USB_Init(void); + +/* The number of current endpoint, it will be used to specify an endpoint */ +extern uint8_t EPindex; +/* The number of current device, it is an index to the Device_Table */ +/*extern uint8_t Device_no; */ +/* Points to the USB_DeviceMess structure of current device */ +/* The purpose of this register is to speed up the execution */ +extern USB_DeviceMess* pInformation; +/* Points to the DEVICE_PROP structure of current device */ +/* The purpose of this register is to speed up the execution */ +extern DEVICE_PROP* pProperty; +/* Temporary save the state of Rx & Tx status. */ +/* Whenever the Rx or Tx state is changed, its value is saved */ +/* in this variable first and will be set to the EPRB or EPRA */ +/* at the end of interrupt process */ +extern USER_STANDARD_REQUESTS* pUser_Standard_Requests; + +extern uint16_t SaveState; +extern uint16_t wInterrupt_Mask; + +/** + * @} + */ + +#endif /* __USB_INIT_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_int.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_int.h new file mode 100644 index 0000000000..77df5f0900 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_int.h @@ -0,0 +1,50 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_int.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_INT_H__ +#define __USB_INT_H__ + +/** + * @addtogroup N32G45X_USB_Driver + * @{ + */ + +void USB_CorrectTransferLp(void); +void USB_CorrectTransferHp(void); + +/** + * @} + */ + +#endif /* __USB_INT_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_lib.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_lib.h new file mode 100644 index 0000000000..3bd907dcac --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_lib.h @@ -0,0 +1,47 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_lib.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_LIB_H__ +#define __USB_LIB_H__ + +#include "usb_type.h" +#include "usb_regs.h" +#include "usb_def.h" +#include "usb_core.h" +#include "usb_init.h" +#include "usb_sil.h" +#include "usb_mem.h" +#include "usb_int.h" + +#endif /* __USB_LIB_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_mem.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_mem.h new file mode 100644 index 0000000000..362ccc48e5 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_mem.h @@ -0,0 +1,52 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_mem.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_MEM_H__ +#define __USB_MEM_H__ + +#include "n32g45x.h" + +/** + * @addtogroup N32G45X_USB_Driver + * @{ + */ + +void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +/** + * @} + */ + +#endif /*__USB_MEM_H__*/ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_regs.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_regs.h new file mode 100644 index 0000000000..61cb75c82f --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_regs.h @@ -0,0 +1,715 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_regs.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_REGS_H__ +#define __USB_REGS_H__ + +#include "n32g45x.h" + +/** + * @addtogroup N32G45X_USB_Driver + * @{ + */ + +typedef enum _EP_DBUF_DIR +{ + /* double buffered endpoint direction */ + EP_DBUF_ERR, + EP_DBUF_OUT, + EP_DBUF_IN +} EP_DBUF_DIR; + +/* endpoint buffer number */ +enum EP_BUF_NUM +{ + EP_NOBUF, + EP_BUF0, + EP_BUF1 +}; + +#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */ +#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */ + +/******************************************************************************/ +/* Special registers */ +/******************************************************************************/ +/* Pull up controller register */ +#define DP_CTRL ((__IO unsigned*)(0x40001820)) + +#define _EnPortPullup() (*DP_CTRL = (*DP_CTRL) | 0x10000000); +#define _DisPortPullup() (*DP_CTRL = (*DP_CTRL) & 0xEFFFFFFF); + +/******************************************************************************/ +/* General registers */ +/******************************************************************************/ + +/* Control register */ +#define USB_CTRL ((__IO unsigned*)(RegBase + 0x40)) +/* Interrupt status register */ +#define USB_STS ((__IO unsigned*)(RegBase + 0x44)) +/* Frame number register */ +#define USB_FN ((__IO unsigned*)(RegBase + 0x48)) +/* Device address register */ +#define USB_ADDR ((__IO unsigned*)(RegBase + 0x4C)) +/* Buffer Table address register */ +#define USB_BUFTAB ((__IO unsigned*)(RegBase + 0x50)) +/******************************************************************************/ +/* Endpoint registers */ +/******************************************************************************/ +#define EP0REG ((__IO unsigned*)(RegBase)) /* endpoint 0 register address */ + +/* Endpoint Addresses (w/direction) */ +#define EP0_OUT ((uint8_t)0x00) +#define EP0_IN ((uint8_t)0x80) +#define EP1_OUT ((uint8_t)0x01) +#define EP1_IN ((uint8_t)0x81) +#define EP2_OUT ((uint8_t)0x02) +#define EP2_IN ((uint8_t)0x82) +#define EP3_OUT ((uint8_t)0x03) +#define EP3_IN ((uint8_t)0x83) +#define EP4_OUT ((uint8_t)0x04) +#define EP4_IN ((uint8_t)0x84) +#define EP5_OUT ((uint8_t)0x05) +#define EP5_IN ((uint8_t)0x85) +#define EP6_OUT ((uint8_t)0x06) +#define EP6_IN ((uint8_t)0x86) +#define EP7_OUT ((uint8_t)0x07) +#define EP7_IN ((uint8_t)0x87) + +/* endpoints enumeration */ +#define ENDP0 ((uint8_t)0) +#define ENDP1 ((uint8_t)1) +#define ENDP2 ((uint8_t)2) +#define ENDP3 ((uint8_t)3) +#define ENDP4 ((uint8_t)4) +#define ENDP5 ((uint8_t)5) +#define ENDP6 ((uint8_t)6) +#define ENDP7 ((uint8_t)7) + +/******************************************************************************/ +/* USB_STS interrupt events */ +/******************************************************************************/ +#define STS_CTRS (0x8000) /* Correct TRansfer (clear-only bit) */ +#define STS_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ +#define STS_ERROR (0x2000) /* ERRor (clear-only bit) */ +#define STS_WKUP (0x1000) /* WaKe UP (clear-only bit) */ +#define STS_SUSPD (0x0800) /* SUSPend (clear-only bit) */ +#define STS_RST (0x0400) /* RESET (clear-only bit) */ +#define STS_SOF (0x0200) /* Start Of Frame (clear-only bit) */ +#define STS_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ + +#define STS_DIR (0x0010) /* DIRection of transaction (read-only bit) */ +#define STS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ + +#define CLR_CTRS (~STS_CTRS) /* clear Correct TRansfer bit */ +#define CLR_DOVR (~STS_DOVR) /* clear DMA OVeR/underrun bit*/ +#define CLR_ERROR (~STS_ERROR) /* clear ERRor bit */ +#define CLR_WKUP (~STS_WKUP) /* clear WaKe UP bit */ +#define CLR_SUSPD (~STS_SUSPD) /* clear SUSPend bit */ +#define CLR_RST (~STS_RST) /* clear RESET bit */ +#define CLR_SOF (~STS_SOF) /* clear Start Of Frame bit */ +#define CLR_ESOF (~STS_ESOF) /* clear Expected Start Of Frame bit */ + +/******************************************************************************/ +/* USB_CTRL control register bits definitions */ +/******************************************************************************/ +#define CTRL_CTRSM (0x8000) /* Correct TRansfer Mask */ +#define CTRL_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ +#define CTRL_ERRORM (0x2000) /* ERRor Mask */ +#define CTRL_WKUPM (0x1000) /* WaKe UP Mask */ +#define CTRL_SUSPDM (0x0800) /* SUSPend Mask */ +#define CTRL_RSTM (0x0400) /* RESET Mask */ +#define CTRL_SOFM (0x0200) /* Start Of Frame Mask */ +#define CTRL_ESOFM (0x0100) /* Expected Start Of Frame Mask */ + +#define CTRL_RESUM (0x0010) /* RESUME request */ +#define CTRL_FSUSPD (0x0008) /* Force SUSPend */ +#define CTRL_LP_MODE (0x0004) /* Low-power MODE */ +#define CTRL_PD (0x0002) /* Power DoWN */ +#define CTRL_FRST (0x0001) /* Force USB RESet */ + +/******************************************************************************/ +/* USB_FN Frame Number Register bit definitions */ +/******************************************************************************/ +#define FN_RXDP (0x8000) /* status of D+ data line */ +#define FN_RXDM (0x4000) /* status of D- data line */ +#define FN_LCK (0x2000) /* LoCKed */ +#define FN_LSOF (0x1800) /* Lost SOF */ +#define FN_FNUM (0x07FF) /* Frame Number */ +/******************************************************************************/ +/* USB_ADDR Device ADDRess bit definitions */ +/******************************************************************************/ +#define ADDR_EFUC (0x80) +#define ADDR_ADDR (0x7F) +/******************************************************************************/ +/* Endpoint register */ +/******************************************************************************/ +/* bit positions */ +#define EP_CTRS_RX (0x8000) /* EndPoint Correct TRansfer RX */ +#define EP_DATTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ +#define EPRX_STS (0x3000) /* EndPoint RX STATus bit field */ +#define EP_SETUP (0x0800) /* EndPoint SETUP */ +#define EP_T_FIELD (0x0600) /* EndPoint TYPE */ +#define EP_KIND (0x0100) /* EndPoint KIND */ +#define EP_CTRS_TX (0x0080) /* EndPoint Correct TRansfer TX */ +#define EP_DATTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ +#define EPTX_STS (0x0030) /* EndPoint TX STATus bit field */ +#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ + +/* EndPoint REGister INTEN (no toggle fields) */ +#define EPREG_MASK (EP_CTRS_RX | EP_SETUP | EP_T_FIELD | EP_KIND | EP_CTRS_TX | EPADDR_FIELD) + +/* EP_TYPE[1:0] EndPoint TYPE */ +#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */ +#define EP_BULK (0x0000) /* EndPoint BULK */ +#define EP_CONTROL (0x0200) /* EndPoint CONTROL */ +#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ +#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ +#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) + +/* EP_KIND EndPoint KIND */ +#define EPKIND_MASK (~EP_KIND & EPREG_MASK) + +/* STAT_TX[1:0] STATus for TX transfer */ +#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ +#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ +#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ +#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ +#define EPTX_DATTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ +#define EPTX_DATTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ +#define EPTX_DATTOGMASK (EPTX_STS | EPREG_MASK) + +/* STAT_RX[1:0] STATus for RX transfer */ +#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ +#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ +#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ +#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ +#define EPRX_DATTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ +#define EPRX_DATTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ +#define EPRX_DATTOGMASK (EPRX_STS | EPREG_MASK) + +/* USB_SetCtrl */ +#define _SetCNTR(wRegValue) (*USB_CTRL = (uint16_t)wRegValue) + +/* USB_SetSts */ +#define _SetISTR(wRegValue) (*USB_STS = (uint16_t)wRegValue) + +/* USB_SetAddr */ +#define _SetDADDR(wRegValue) (*USB_ADDR = (uint16_t)wRegValue) + +/* USB_SetBuftab */ +#define _SetBTABLE(wRegValue) (*USB_BUFTAB = (uint16_t)(wRegValue & 0xFFF8)) + +/* USB_GetCtrl */ +#define _GetCNTR() ((uint16_t)*USB_CTRL) + +/* USB_GetSts */ +#define _GetISTR() ((uint16_t)*USB_STS) + +/* USB_GetFn */ +#define _GetFNR() ((uint16_t)*USB_FN) + +/* USB_GetAddr */ +#define _GetDADDR() ((uint16_t)*USB_ADDR) + +/* USB_GetBTABLE */ +#define _GetBTABLE() ((uint16_t)*USB_BUFTAB) + +/* USB_SetEndPoint */ +#define _SetENDPOINT(bEpNum, wRegValue) (*(EP0REG + bEpNum) = (uint16_t)wRegValue) + +/* USB_GetEndPoint */ +#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum))) + +/******************************************************************************* + * Macro Name : USB_SetEpType + * Description : sets the type in the endpoint register(bits EP_TYPE[1:0]) + * Input : bEpNum: Endpoint Number. + * wType + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPType(bEpNum, wType) (_SetENDPOINT(bEpNum, ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType))) + +/******************************************************************************* + * Macro Name : USB_GetEpType + * Description : gets the type in the endpoint register(bits EP_TYPE[1:0]) + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : Endpoint Type + *******************************************************************************/ +#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) + +/******************************************************************************* + * Macro Name : SetEPTxStatus + * Description : sets the status for tx transfer (bits STAT_TX[1:0]). + * Input : bEpNum: Endpoint Number. + * wState: new state + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPTxStatus(bEpNum, wState) \ + { \ + register uint16_t _wRegVal; \ + _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DATTOGMASK; \ + /* toggle first bit ? */ \ + if ((EPTX_DATTOG1 & wState) != 0) \ + _wRegVal ^= EPTX_DATTOG1; \ + /* toggle second bit ? */ \ + if ((EPTX_DATTOG2 & wState) != 0) \ + _wRegVal ^= EPTX_DATTOG2; \ + _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \ + } /* _SetEPTxStatus */ + +/******************************************************************************* + * Macro Name : SetEPRxStatus + * Description : sets the status for rx transfer (bits STAT_TX[1:0]) + * Input : bEpNum: Endpoint Number. + * wState: new state. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPRxStatus(bEpNum, wState) \ + { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DATTOGMASK; \ + /* toggle first bit ? */ \ + if ((EPRX_DATTOG1 & wState) != 0) \ + _wRegVal ^= EPRX_DATTOG1; \ + /* toggle second bit ? */ \ + if ((EPRX_DATTOG2 & wState) != 0) \ + _wRegVal ^= EPRX_DATTOG2; \ + _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \ + } /* _SetEPRxStatus */ + +/******************************************************************************* + * Macro Name : SetEPRxTxStatus + * Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * Input : bEpNum: Endpoint Number. + * wStaterx: new state. + * wStatetx: new state. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPRxTxStatus(bEpNum, wStaterx, wStatetx) \ + { \ + register uint32_t _wRegVal; \ + \ + _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DATTOGMASK | EPTX_STS); \ + /* toggle first bit ? */ \ + if ((EPRX_DATTOG1 & wStaterx) != 0) \ + _wRegVal ^= EPRX_DATTOG1; \ + /* toggle second bit ? */ \ + if ((EPRX_DATTOG2 & wStaterx) != 0) \ + _wRegVal ^= EPRX_DATTOG2; \ + /* toggle first bit ? */ \ + if ((EPTX_DATTOG1 & wStatetx) != 0) \ + _wRegVal ^= EPTX_DATTOG1; \ + /* toggle second bit ? */ \ + if ((EPTX_DATTOG2 & wStatetx) != 0) \ + _wRegVal ^= EPTX_DATTOG2; \ + _SetENDPOINT(bEpNum, _wRegVal | EP_CTRS_RX | EP_CTRS_TX); \ + } /* _SetEPRxTxStatus */ +/******************************************************************************* + * Macro Name : USB_GetEpTxSts / USB_GetEpRxSts + * Description : gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : status . + *******************************************************************************/ +#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STS) + +#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STS) + +/******************************************************************************* + * Macro Name : USB_SetEpTxValid / USB_SetEpRxValid + * Description : sets directly the VALID tx/rx-status into the enpoint register + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) + +#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) + +/******************************************************************************* + * Macro Name : USB_GetTxStallSts / USB_GetRxStallSts. + * Description : checks stall condition in an endpoint. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : TRUE = endpoint in stall condition. + *******************************************************************************/ +#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) == EP_TX_STALL) +#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) == EP_RX_STALL) + +/******************************************************************************* + * Macro Name : USB_SetEpKind / USB_ClrEpKind. + * Description : set & clear EP_KIND bit. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEP_KIND(bEpNum) \ + (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | ((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)))) +#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPKIND_MASK)))) + +/******************************************************************************* + * Macro Name : USB_SetStsOut / USB_ClrStsOut. + * Description : Sets/clears directly STATUS_OUT bit in the endpoint register. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) +#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) + +/******************************************************************************* + * Macro Name : USB_SetEpDoubleBufer / USB_ClrEpDoubleBufer. + * Description : Sets/clears directly EP_KIND bit in the endpoint register. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) +#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) + +/******************************************************************************* + * Macro Name : USB_ClrEpCtrsRx / USB_ClrEpCtrsTx. + * Description : Clears bit CTR_RX / CTR_TX in the endpoint register. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) +#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) + +/******************************************************************************* + * Macro Name : USB_DattogRx / USB_DattogTx . + * Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _ToggleDTOG_RX(bEpNum) \ + (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK))) +#define _ToggleDTOG_TX(bEpNum) \ + (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK))) + +/******************************************************************************* + * Macro Name : USB_ClrDattogRx / USB_ClrDattogTx. + * Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _ClearDTOG_RX(bEpNum) \ + if ((_GetENDPOINT(bEpNum) & EP_DATTOG_RX) != 0) \ + _ToggleDTOG_RX(bEpNum) +#define _ClearDTOG_TX(bEpNum) \ + if ((_GetENDPOINT(bEpNum) & EP_DATTOG_TX) != 0) \ + _ToggleDTOG_TX(bEpNum) +/******************************************************************************* + * Macro Name : USB_SetEpAddress. + * Description : Sets address in an endpoint register. + * Input : bEpNum: Endpoint Number. + * bAddr: Address. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPAddress(bEpNum, bAddr) \ + _SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr) + +/******************************************************************************* + * Macro Name : USB_GetEpAddress. + * Description : Gets address in an endpoint register. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) + +#define _pEPTxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8) * 2 + PMAAddr)) +#define _pEPTxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 2) * 2 + PMAAddr)) +#define _pEPRxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 4) * 2 + PMAAddr)) +#define _pEPRxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 6) * 2 + PMAAddr)) + +/******************************************************************************* + * Macro Name : USB_SetEpTxAddr / USB_SetEpRxAddr. + * Description : sets address of the tx/rx buffer. + * Input : bEpNum: Endpoint Number. + * wAddr: address to be set (must be word aligned). + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPTxAddr(bEpNum, wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1)) +#define _SetEPRxAddr(bEpNum, wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1)) + +/******************************************************************************* + * Macro Name : USB_GetEpTxAddr / USB_GetEpRxAddr. + * Description : Gets address of the tx/rx buffer. + * Input : bEpNum: Endpoint Number. + * Output : None. + * Return : address of the buffer. + *******************************************************************************/ +#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum)) +#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum)) + +/******************************************************************************* + * Macro Name : USB_SetEpCntRxReg. + * Description : Sets counter of rx buffer with no. of blocks. + * Input : pdwReg: pointer to counter. + * wCount: Counter. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _BlocksOf32(dwReg, wCount, wNBlocks) \ + { \ + wNBlocks = wCount >> 5; \ + if ((wCount & 0x1f) == 0) \ + wNBlocks--; \ + *pdwReg = (uint32_t)((wNBlocks << 11) | 0x8000); \ + } /* _BlocksOf32 */ + +#define _BlocksOf2(dwReg, wCount, wNBlocks) \ + { \ + wNBlocks = wCount >> 1; \ + if ((wCount & 0x1) != 0) \ + wNBlocks++; \ + *pdwReg = (uint32_t)(wNBlocks << 10); \ + } /* _BlocksOf2 */ + +#define _SetEPCountRxReg(dwReg, wCount) \ + { \ + uint16_t wNBlocks; \ + if (wCount > 62) \ + { \ + _BlocksOf32(dwReg, wCount, wNBlocks); \ + } \ + else \ + { \ + _BlocksOf2(dwReg, wCount, wNBlocks); \ + } \ + } /* _SetEPCountRxReg */ + +#define _SetEPRxDblBuf0Count(bEpNum, wCount) \ + { \ + uint32_t* pdwReg = _pEPTxCount(bEpNum); \ + _SetEPCountRxReg(pdwReg, wCount); \ + } +/******************************************************************************* + * Macro Name : USB_SetEpTxCnt / USB_SetEpRxCnt. + * Description : sets counter for the tx/rx buffer. + * Input : bEpNum: endpoint number. + * wCount: Counter value. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPTxCount(bEpNum, wCount) (*_pEPTxCount(bEpNum) = wCount) +#define _SetEPRxCount(bEpNum, wCount) \ + { \ + uint32_t* pdwReg = _pEPRxCount(bEpNum); \ + _SetEPCountRxReg(pdwReg, wCount); \ + } +/******************************************************************************* + * Macro Name : USB_GetEpTxCnt / USB_GetEpRxCnt. + * Description : gets counter of the tx buffer. + * Input : bEpNum: endpoint number. + * Output : None. + * Return : Counter value. + *******************************************************************************/ +#define _GetEPTxCount(bEpNum) ((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff) +#define _GetEPRxCount(bEpNum) ((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff) + +/******************************************************************************* + * Macro Name : USB_SetEpDblBuf0Addr / USB_SetEpDblBuf1Addr. + * Description : Sets buffer 0/1 address in a double buffer endpoint. + * Input : bEpNum: endpoint number. + * : wBuf0Addr: buffer 0 address. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPDblBuf0Addr(bEpNum, wBuf0Addr) \ + { \ + _SetEPTxAddr(bEpNum, wBuf0Addr); \ + } +#define _SetEPDblBuf1Addr(bEpNum, wBuf1Addr) \ + { \ + _SetEPRxAddr(bEpNum, wBuf1Addr); \ + } + +/******************************************************************************* + * Macro Name : USB_SetEpDblBuferAddr. + * Description : Sets addresses in a double buffer endpoint. + * Input : bEpNum: endpoint number. + * : wBuf0Addr: buffer 0 address. + * : wBuf1Addr = buffer 1 address. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr) \ + { \ + _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); \ + _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); \ + } /* _SetEPDblBuffAddr */ + +/******************************************************************************* + * Macro Name : USB_GetEpDblBuf0Addr / USB_GetEpDblBuf1Addr. + * Description : Gets buffer 0/1 address of a double buffer endpoint. + * Input : bEpNum: endpoint number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) +#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) + +/******************************************************************************* + * Macro Name : USB_SetEpDblBuferCnt / USB_SetEpDblBuf0Cnt / USB_SetEpDblBuf1Cnt. + * Description : Gets buffer 0/1 address of a double buffer endpoint. + * Input : bEpNum: endpoint number. + * : bDir: endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * : wCount: Counter value + * Output : None. + * Return : None. + *******************************************************************************/ +#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) \ + { \ + if (bDir == EP_DBUF_OUT) \ + /* OUT endpoint */ \ + { \ + _SetEPRxDblBuf0Count(bEpNum, wCount); \ + } \ + else if (bDir == EP_DBUF_IN) \ + /* IN endpoint */ \ + *_pEPTxCount(bEpNum) = (uint32_t)wCount; \ + } /* USB_SetEpDblBuf0Cnt*/ + +#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) \ + { \ + if (bDir == EP_DBUF_OUT) \ + /* OUT endpoint */ \ + { \ + _SetEPRxCount(bEpNum, wCount); \ + } \ + else if (bDir == EP_DBUF_IN) \ + /* IN endpoint */ \ + *_pEPRxCount(bEpNum) = (uint32_t)wCount; \ + } /* USB_SetEpDblBuf1Cnt */ + +#define _SetEPDblBuffCount(bEpNum, bDir, wCount) \ + { \ + _SetEPDblBuf0Count(bEpNum, bDir, wCount); \ + _SetEPDblBuf1Count(bEpNum, bDir, wCount); \ + } /* _SetEPDblBuffCount */ + +/******************************************************************************* + * Macro Name : USB_GetEpDblBuf0Cnt / USB_GetEpDblBuf1Cnt. + * Description : Gets buffer 0/1 rx/tx counter for double buffering. + * Input : bEpNum: endpoint number. + * Output : None. + * Return : None. + *******************************************************************************/ +#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum)) +#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum)) + +extern __IO uint16_t wIstr; /* USB_STS register last read value */ + +void USB_SetCtrl(uint16_t /*wRegValue*/); +void USB_SetSts(uint16_t /*wRegValue*/); +void USB_SetAddr(uint16_t /*wRegValue*/); +void USB_SetBuftab(uint16_t /*wRegValue*/); +void USB_SetBuftab(uint16_t /*wRegValue*/); +uint16_t USB_GetCtrl(void); +uint16_t USB_GetSts(void); +uint16_t USB_GetFn(void); +uint16_t USB_GetAddr(void); +uint16_t USB_GetBTABLE(void); +void USB_SetEndPoint(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/); +uint16_t USB_GetEndPoint(uint8_t /*bEpNum*/); +void USB_SetEpType(uint8_t /*bEpNum*/, uint16_t /*wType*/); +uint16_t USB_GetEpType(uint8_t /*bEpNum*/); +void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/); +void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/); +void USB_SetDouBleBuferEpStall(uint8_t /*bEpNum*/, uint8_t bDir); +uint16_t USB_GetEpTxSts(uint8_t /*bEpNum*/); +uint16_t USB_GetEpRxSts(uint8_t /*bEpNum*/); +void USB_SetEpTxValid(uint8_t /*bEpNum*/); +void USB_SetEpRxValid(uint8_t /*bEpNum*/); +uint16_t USB_GetTxStallSts(uint8_t /*bEpNum*/); +uint16_t USB_GetRxStallSts(uint8_t /*bEpNum*/); +void USB_SetEpKind(uint8_t /*bEpNum*/); +void USB_ClrEpKind(uint8_t /*bEpNum*/); +void USB_SetStsOut(uint8_t /*bEpNum*/); +void USB_ClrStsOut(uint8_t /*bEpNum*/); +void USB_SetEpDoubleBufer(uint8_t /*bEpNum*/); +void USB_ClrEpDoubleBufer(uint8_t /*bEpNum*/); +void USB_ClrEpCtrsRx(uint8_t /*bEpNum*/); +void USB_ClrEpCtrsTx(uint8_t /*bEpNum*/); +void USB_DattogRx(uint8_t /*bEpNum*/); +void USB_DattogTx(uint8_t /*bEpNum*/); +void USB_ClrDattogRx(uint8_t /*bEpNum*/); +void USB_ClrDattogTx(uint8_t /*bEpNum*/); +void USB_SetEpAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/); +uint8_t USB_GetEpAddress(uint8_t /*bEpNum*/); +void USB_SetEpTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/); +void USB_SetEpRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/); +uint16_t USB_GetEpTxAddr(uint8_t /*bEpNum*/); +uint16_t USB_GetEpRxAddr(uint8_t /*bEpNum*/); +void USB_SetEpCntRxReg(uint32_t* /*pdwReg*/, uint16_t /*wCount*/); +void USB_SetEpTxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/); +void USB_SetEpRxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/); +uint16_t USB_GetEpTxCnt(uint8_t /*bEpNum*/); +uint16_t USB_GetEpRxCnt(uint8_t /*bEpNum*/); +void USB_SetEpDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/); +void USB_SetEpDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/); +void USB_SetEpDblBuferAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/); +uint16_t USB_GetEpDblBuf0Addr(uint8_t /*bEpNum*/); +uint16_t USB_GetEpDblBuf1Addr(uint8_t /*bEpNum*/); +void USB_SetEpDblBuferCnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); +void USB_SetEpDblBuf0Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); +void USB_SetEpDblBuf1Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); +uint16_t USB_GetEpDblBuf0Cnt(uint8_t /*bEpNum*/); +uint16_t USB_GetEpDblBuf1Cnt(uint8_t /*bEpNum*/); +EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/); +void USB_FreeUserBuf(uint8_t bEpNum /*bEpNum*/, uint8_t bDir); +uint16_t USB_ToWord(uint8_t, uint8_t); +uint16_t USB_ByteSwap(uint16_t); + +/** + * @} + */ + +#endif /* __USB_REGS_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_sil.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_sil.h new file mode 100644 index 0000000000..68439223b1 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_sil.h @@ -0,0 +1,53 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_sil.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_SIL_H__ +#define __USB_SIL_H__ + +#include "n32g45x.h" + +/** + * @addtogroup N32G45X_USB_Driver + * @{ + */ + +uint32_t USB_SilInit(void); +uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize); +uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer); + +/** + * @} + */ + +#endif /* __USB_SIL_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_type.h b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_type.h new file mode 100644 index 0000000000..3187a1408c --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_type.h @@ -0,0 +1,54 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_type.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_TYPE_H__ +#define __USB_TYPE_H__ + +#include "usb_conf.h" +#include + +/** + * @addtogroup N32G45X_USB_Driver + * @{ + */ + +#ifndef NULL +#define NULL ((void*)0) +#endif + +/** + * @} + */ + +#endif /* __USB_TYPE_H__ */ diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_core.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_core.c new file mode 100644 index 0000000000..ee7f4e74ca --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_core.c @@ -0,0 +1,950 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "usb_lib.h" + +#define ValBit(VAR, Place) (VAR & (1 << Place)) +#define SetBit(VAR, Place) (VAR |= (1 << Place)) +#define ClrBit(VAR, Place) (VAR &= ((1 << Place) ^ 255)) + +#define Send0LengthData() \ + { \ + _SetEPTxCount(ENDP0, 0); \ + vSetEPTxStatus(EP_TX_VALID); \ + } + +#define vSetEPRxStatus(st) (SaveRState = st) +#define vSetEPTxStatus(st) (SaveTState = st) + +#define USB_StatusIn() Send0LengthData() +#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID) + +#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */ +#define StatusInfo1 StatusInfo.bw.bb0 + +uint16_t_uint8_t StatusInfo; + +bool Data_Mul_MaxPacketSize = false; + +static void DataStageOut(void); +static void DataStageIn(void); +static void NoData_Setup0(void); +static void Data_Setup0(void); + +/** + * @brief Return the current configuration variable address. + * Input : Length - How many bytes are needed. + * @return Return 1 , if the request is invalid when "Length" is 0. + * Return "Buffer" if the "Length" is not 0. + */ +uint8_t* Standard_GetConfiguration(uint16_t Length) +{ + if (Length == 0) + { + pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentConfiguration); + return 0; + } + pUser_Standard_Requests->User_GetConfiguration(); + return (uint8_t*)&pInformation->CurrentConfiguration; +} + +/** + * @brief This routine is called to set the configuration value + * Then each class should configure device itself. + * @return + * - Success, if the request is performed. + * - UnSupport, if the request is invalid. + */ +USB_Result Standard_SetConfiguration(void) +{ + if ((pInformation->USBwValue0 <= Device_Table.TotalConfiguration) && (pInformation->USBwValue1 == 0) + && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/ + { + pInformation->CurrentConfiguration = pInformation->USBwValue0; + pUser_Standard_Requests->User_SetConfiguration(); + return Success; + } + else + { + return UnSupport; + } +} + +/** + * @brief Return the Alternate Setting of the current interface. + * Input : Length - How many bytes are needed. + * @return + * - NULL, if the request is invalid when "Length" is 0. + * - "Buffer" if the "Length" is not 0. + */ +uint8_t* Standard_GetInterface(uint16_t Length) +{ + if (Length == 0) + { + pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentAlternateSetting); + return 0; + } + pUser_Standard_Requests->User_GetInterface(); + return (uint8_t*)&pInformation->CurrentAlternateSetting; +} + +/** + * @brief This routine is called to set the interface. + * Then each class should configure the interface them self. + * @return + * - Success, if the request is performed. + * - UnSupport, if the request is invalid. + */ +USB_Result Standard_SetInterface(void) +{ + USB_Result Re; + /*Test if the specified Interface and Alternate Setting are supported by + the application Firmware*/ + Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0); + + if (pInformation->CurrentConfiguration != 0) + { + if ((Re != Success) || (pInformation->USBwIndex1 != 0) || (pInformation->USBwValue1 != 0)) + { + return UnSupport; + } + else if (Re == Success) + { + pUser_Standard_Requests->User_SetInterface(); + pInformation->CurrentInterface = pInformation->USBwIndex0; + pInformation->CurrentAlternateSetting = pInformation->USBwValue0; + return Success; + } + } + + return UnSupport; +} + +/** + * @brief Copy the device request data to "StatusInfo buffer". + * Input : - Length - How many bytes are needed. + * @return Return 0, if the request is at end of data block, + * or is invalid when "Length" is 0. + */ +uint8_t* Standard_GetStatus(uint16_t Length) +{ + if (Length == 0) + { + pInformation->Ctrl_Info.Usb_wLength = 2; + return 0; + } + + /* Reset Status Information */ + StatusInfo.w = 0; + + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + /*Get Device Status */ + uint8_t Feature = pInformation->CurrentFeature; + + /* Remote Wakeup enabled */ + if (ValBit(Feature, 5)) + { + SetBit(StatusInfo0, 1); + } + else + { + ClrBit(StatusInfo0, 1); + } + + /* Bus-powered */ + if (ValBit(Feature, 6)) + { + SetBit(StatusInfo0, 0); + } + else /* Self-powered */ + { + ClrBit(StatusInfo0, 0); + } + } + /*Interface Status*/ + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + { + return (uint8_t*)&StatusInfo; + } + /*Get EndPoint Status*/ + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + uint8_t Related_Endpoint; + uint8_t wIndex0 = pInformation->USBwIndex0; + + Related_Endpoint = (wIndex0 & 0x0f); + if (ValBit(wIndex0, 7)) + { + /* IN endpoint */ + if (_GetTxStallStatus(Related_Endpoint)) + { + SetBit(StatusInfo0, 0); /* IN Endpoint stalled */ + } + } + else + { + /* OUT endpoint */ + if (_GetRxStallStatus(Related_Endpoint)) + { + SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */ + } + } + } + else + { + return NULL; + } + pUser_Standard_Requests->User_GetStatus(); + return (uint8_t*)&StatusInfo; +} + +/** + * @brief Clear or disable a specific feature. + * @return - Return Success, if the request is performed. + * - Return UnSupport, if the request is invalid. + */ +USB_Result Standard_ClearFeature(void) +{ + uint32_t Type_Rec = Type_Recipient; + uint32_t Status; + + if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { /*Device Clear Feature*/ + ClrBit(pInformation->CurrentFeature, 5); + return Success; + } + else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { /*EndPoint Clear Feature*/ + USB_Device* pDev; + uint32_t Related_Endpoint; + uint32_t wIndex0; + uint32_t rEP; + + if ((pInformation->USBwValue != ENDPOINT_STALL) || (pInformation->USBwIndex1 != 0)) + { + return UnSupport; + } + + pDev = &Device_Table; + wIndex0 = pInformation->USBwIndex0; + rEP = wIndex0 & ~0x80; + Related_Endpoint = ENDP0 + rEP; + + if (ValBit(pInformation->USBwIndex0, 7)) + { + /*Get Status of endpoint & stall the request if the related_ENdpoint + is Disabled*/ + Status = _GetEPTxStatus(Related_Endpoint); + } + else + { + Status = _GetEPRxStatus(Related_Endpoint); + } + + if ((rEP >= pDev->TotalEndpoint) || (Status == 0) || (pInformation->CurrentConfiguration == 0)) + { + return UnSupport; + } + + if (wIndex0 & 0x80) + { + /* IN endpoint */ + if (_GetTxStallStatus(Related_Endpoint)) + { + USB_ClrDattogTx(Related_Endpoint); + SetEPTxStatus(Related_Endpoint, EP_TX_VALID); + } + } + else + { + /* OUT endpoint */ + if (_GetRxStallStatus(Related_Endpoint)) + { + if (Related_Endpoint == ENDP0) + { + /* After clear the STALL, enable the default endpoint receiver */ + USB_SetEpRxCnt(Related_Endpoint, Device_Property.MaxPacketSize); + _SetEPRxStatus(Related_Endpoint, EP_RX_VALID); + } + else + { + USB_ClrDattogRx(Related_Endpoint); + _SetEPRxStatus(Related_Endpoint, EP_RX_VALID); + } + } + } + pUser_Standard_Requests->User_ClearFeature(); + return Success; + } + + return UnSupport; +} + +/** + * @brief Set or enable a specific feature of EndPoint + * @return - Return Success, if the request is performed. + * - Return UnSupport, if the request is invalid. + */ +USB_Result Standard_SetEndPointFeature(void) +{ + uint32_t wIndex0; + uint32_t Related_Endpoint; + uint32_t rEP; + uint32_t Status; + + wIndex0 = pInformation->USBwIndex0; + rEP = wIndex0 & ~0x80; + Related_Endpoint = ENDP0 + rEP; + + if (ValBit(pInformation->USBwIndex0, 7)) + { + /* get Status of endpoint & stall the request if the related_ENdpoint + is Disabled*/ + Status = _GetEPTxStatus(Related_Endpoint); + } + else + { + Status = _GetEPRxStatus(Related_Endpoint); + } + + if (Related_Endpoint >= Device_Table.TotalEndpoint || pInformation->USBwValue != 0 || Status == 0 + || pInformation->CurrentConfiguration == 0) + { + return UnSupport; + } + else + { + if (wIndex0 & 0x80) + { + /* IN endpoint */ + _SetEPTxStatus(Related_Endpoint, EP_TX_STALL); + } + + else + { + /* OUT endpoint */ + _SetEPRxStatus(Related_Endpoint, EP_RX_STALL); + } + } + pUser_Standard_Requests->User_SetEndPointFeature(); + return Success; +} + +/** + * @brief Set or enable a specific feature of Device. + * @return - Return Success, if the request is performed. + * - Return UnSupport, if the request is invalid. + */ +USB_Result Standard_SetDeviceFeature(void) +{ + SetBit(pInformation->CurrentFeature, 5); + pUser_Standard_Requests->User_SetDeviceFeature(); + return Success; +} + +/** + * @brief Standard_GetDescriptorData is used for descriptors transfer. + * : This routine is used for the descriptors resident in Flash + * or RAM + * pDesc can be in either Flash or RAM + * The purpose of this routine is to have a versatile way to + * response descriptors request. It allows user to generate + * certain descriptors with software or read descriptors from + * external storage part by part. + * Input : - Length - Length of the data in this transfer. + * - pDesc - A pointer points to descriptor struct. + * The structure gives the initial address of the descriptor and + * its original size. + * @return Address of a part of the descriptor pointed by the Usb_ + * wOffset The buffer pointed by this address contains at least + * Length bytes. + */ +uint8_t* Standard_GetDescriptorData(uint16_t Length, USB_OneDescriptor* pDesc) +{ + uint32_t wOffset; + + wOffset = pInformation->Ctrl_Info.Usb_wOffset; + if (Length == 0) + { + pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset; + return 0; + } + + return pDesc->Descriptor + wOffset; +} + +/** + * @brief Data stage of a Control Write Transfer. + */ +void DataStageOut(void) +{ + USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info; + uint32_t save_rLength; + + save_rLength = pEPinfo->Usb_rLength; + + if (pEPinfo->CopyData && save_rLength) + { + uint8_t* Buffer; + uint32_t Length; + + Length = pEPinfo->PacketSize; + if (Length > save_rLength) + { + Length = save_rLength; + } + + Buffer = (*pEPinfo->CopyData)(Length); + pEPinfo->Usb_rLength -= Length; + pEPinfo->Usb_rOffset += Length; + + USB_CopyPMAToUserBuf(Buffer, USB_GetEpRxAddr(ENDP0), Length); + } + + if (pEPinfo->Usb_rLength != 0) + { + vSetEPRxStatus(EP_RX_VALID); /* re-enable for next data reception */ + USB_SetEpTxCnt(ENDP0, 0); + vSetEPTxStatus(EP_TX_VALID); /* Expect the host to abort the data OUT stage */ + } + /* Set the next State*/ + if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize) + { + pInformation->CtrlState = OutData; + } + else + { + if (pEPinfo->Usb_rLength > 0) + { + pInformation->CtrlState = LastOutData; + } + else if (pEPinfo->Usb_rLength == 0) + { + pInformation->CtrlState = WaitStatusIn; + USB_StatusIn(); + } + } +} + +/** + * @brief Data stage of a Control Read Transfer. + */ +void DataStageIn(void) +{ + USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info; + uint32_t save_wLength = pEPinfo->Usb_wLength; + uint32_t CtrlState = pInformation->CtrlState; + + uint8_t* DataBuffer; + uint32_t Length; + + if ((save_wLength == 0) && (CtrlState == LastInData)) + { + if (Data_Mul_MaxPacketSize == true) + { + /* No more data to send and empty packet */ + Send0LengthData(); + CtrlState = LastInData; + Data_Mul_MaxPacketSize = false; + } + else + { + /* No more data to send so STALL the TX Status*/ + CtrlState = WaitStatusOut; + vSetEPTxStatus(EP_TX_STALL); + } + + goto Expect_Status_Out; + } + + Length = pEPinfo->PacketSize; + CtrlState = (save_wLength <= Length) ? LastInData : InData; + + if (Length > save_wLength) + { + Length = save_wLength; + } + + DataBuffer = (*pEPinfo->CopyData)(Length); + + USB_CopyUserToPMABuf(DataBuffer, USB_GetEpTxAddr(ENDP0), Length); + + USB_SetEpTxCnt(ENDP0, Length); + + pEPinfo->Usb_wLength -= Length; + pEPinfo->Usb_wOffset += Length; + vSetEPTxStatus(EP_TX_VALID); + + USB_StatusOut(); /* Expect the host to abort the data IN stage */ + +Expect_Status_Out: + pInformation->CtrlState = CtrlState; +} + +/** + * @brief Proceed the processing of setup request without data stage. + */ +void NoData_Setup0(void) +{ + USB_Result Result = UnSupport; + uint32_t RequestNo = pInformation->bRequest; + uint32_t CtrlState; + + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + /* Device Request*/ + /* SET_CONFIGURATION*/ + if (RequestNo == SET_CONFIGURATION) + { + Result = Standard_SetConfiguration(); + } + + /*SET ADDRESS*/ + else if (RequestNo == SET_ADDRESS) + { + if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0) || (pInformation->USBwIndex != 0) + || (pInformation->CurrentConfiguration != 0)) + /* Device Address should be 127 or less*/ + { + CtrlState = Stalled; + goto exit_NoData_Setup0; + } + else + { + Result = Success; + } + } + /*SET FEATURE for Device*/ + else if (RequestNo == SET_FEATURE) + { + if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) && (pInformation->USBwIndex == 0)) + { + Result = Standard_SetDeviceFeature(); + } + else + { + Result = UnSupport; + } + } + /*Clear FEATURE for Device */ + else if (RequestNo == CLR_FEATURE) + { + if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP && pInformation->USBwIndex == 0 + && ValBit(pInformation->CurrentFeature, 5)) + { + Result = Standard_ClearFeature(); + } + else + { + Result = UnSupport; + } + } + } + + /* Interface Request*/ + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + { + /*SET INTERFACE*/ + if (RequestNo == SET_INTERFACE) + { + Result = Standard_SetInterface(); + } + } + + /* EndPoint Request*/ + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + /*CLEAR FEATURE for EndPoint*/ + if (RequestNo == CLR_FEATURE) + { + Result = Standard_ClearFeature(); + } + /* SET FEATURE for EndPoint*/ + else if (RequestNo == SET_FEATURE) + { + Result = Standard_SetEndPointFeature(); + } + } + else + { + Result = UnSupport; + } + + if (Result != Success) + { + Result = (*pProperty->Class_NoData_Setup)(RequestNo); + if (Result == Not_Ready) + { + CtrlState = Pause; + goto exit_NoData_Setup0; + } + } + + if (Result != Success) + { + CtrlState = Stalled; + goto exit_NoData_Setup0; + } + + CtrlState = WaitStatusIn; /* After no data stage SETUP */ + + USB_StatusIn(); + +exit_NoData_Setup0: + pInformation->CtrlState = CtrlState; + return; +} + +/** + * @brief Proceed the processing of setup request with data stage. + */ +void Data_Setup0(void) +{ + uint8_t* (*CopyRoutine)(uint16_t); + USB_Result Result; + uint32_t Request_No = pInformation->bRequest; + + uint32_t Related_Endpoint, Reserved; + uint32_t wOffset, Status; + + CopyRoutine = NULL; + wOffset = 0; + + /*GET DESCRIPTOR*/ + if (Request_No == GET_DESCRIPTOR) + { + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + uint8_t wValue1 = pInformation->USBwValue1; + if (wValue1 == DEVICE_DESCRIPTOR) + { + CopyRoutine = pProperty->GetDeviceDescriptor; + } + else if (wValue1 == CONFIG_DESCRIPTOR) + { + CopyRoutine = pProperty->GetConfigDescriptor; + } + else if (wValue1 == STRING_DESCRIPTOR) + { + CopyRoutine = pProperty->GetStringDescriptor; + } /* End of GET_DESCRIPTOR */ + } + } + + /*GET STATUS*/ + else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0) && (pInformation->USBwLength == 0x0002) + && (pInformation->USBwIndex1 == 0)) + { + /* GET STATUS for Device*/ + if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) && (pInformation->USBwIndex == 0)) + { + CopyRoutine = Standard_GetStatus; + } + + /* GET STATUS for Interface*/ + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + { + if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success) + && (pInformation->CurrentConfiguration != 0)) + { + CopyRoutine = Standard_GetStatus; + } + } + + /* GET STATUS for EndPoint*/ + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + Related_Endpoint = (pInformation->USBwIndex0 & 0x0f); + Reserved = pInformation->USBwIndex0 & 0x70; + + if (ValBit(pInformation->USBwIndex0, 7)) + { + /*Get Status of endpoint & stall the request if the related_ENdpoint + is Disabled*/ + Status = _GetEPTxStatus(Related_Endpoint); + } + else + { + Status = _GetEPRxStatus(Related_Endpoint); + } + + if ((Related_Endpoint < Device_Table.TotalEndpoint) && (Reserved == 0) && (Status != 0)) + { + CopyRoutine = Standard_GetStatus; + } + } + } + + /*GET CONFIGURATION*/ + else if (Request_No == GET_CONFIGURATION) + { + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + CopyRoutine = Standard_GetConfiguration; + } + } + /*GET INTERFACE*/ + else if (Request_No == GET_INTERFACE) + { + if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) && (pInformation->CurrentConfiguration != 0) + && (pInformation->USBwValue == 0) && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001) + && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success)) + { + CopyRoutine = Standard_GetInterface; + } + } + + if (CopyRoutine) + { + pInformation->Ctrl_Info.Usb_wOffset = wOffset; + pInformation->Ctrl_Info.CopyData = CopyRoutine; + /* sb in the original the cast to word was directly */ + /* now the cast is made step by step */ + (*CopyRoutine)(0); + Result = Success; + } + else + { + Result = (*pProperty->Class_Data_Setup)(pInformation->bRequest); + if (Result == Not_Ready) + { + pInformation->CtrlState = Pause; + return; + } + } + + if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF) + { + /* Data is not ready, wait it */ + pInformation->CtrlState = Pause; + return; + } + if ((Result == UnSupport) || (pInformation->Ctrl_Info.Usb_wLength == 0)) + { + /* Unsupported request */ + pInformation->CtrlState = Stalled; + return; + } + + if (ValBit(pInformation->bmRequestType, 7)) + { + /* Device ==> Host */ + __IO uint32_t wLength = pInformation->USBwLength; + + /* Restrict the data length to be the one host asks for */ + if (pInformation->Ctrl_Info.Usb_wLength > wLength) + { + pInformation->Ctrl_Info.Usb_wLength = wLength; + } + + else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength) + { + if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize) + { + Data_Mul_MaxPacketSize = false; + } + else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0) + { + Data_Mul_MaxPacketSize = true; + } + } + + pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize; + DataStageIn(); + } + else + { + pInformation->CtrlState = OutData; + vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */ + } + + return; +} + +/** + * @brief Get the device request data and dispatch to individual process. + * @return USB_ProcessPost0. + */ +uint8_t USB_ProcessSetup0(void) +{ + union + { + uint8_t* b; + uint16_t* w; + } pBuf; + + uint16_t offset = 1; + + pBuf.b = PMAAddr + (uint8_t*)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */ + + if (pInformation->CtrlState != Pause) + { + pInformation->bmRequestType = *pBuf.b++; /* bmRequestType */ + pInformation->bRequest = *pBuf.b++; /* bRequest */ + pBuf.w += offset; /* word not accessed because of 32 bits addressing */ + pInformation->USBwValue = USB_ByteSwap(*pBuf.w++); /* wValue */ + pBuf.w += offset; /* word not accessed because of 32 bits addressing */ + pInformation->USBwIndex = USB_ByteSwap(*pBuf.w++); /* wIndex */ + pBuf.w += offset; /* word not accessed because of 32 bits addressing */ + pInformation->USBwLength = *pBuf.w; /* wLength */ + } + + pInformation->CtrlState = SettingUp; + if (pInformation->USBwLength == 0) + { + /* Setup with no data stage */ + NoData_Setup0(); + } + else + { + /* Setup with data stage */ + Data_Setup0(); + } + return USB_ProcessPost0(); +} + +/** + * @brief Process the IN token on all default endpoint. + * @return USB_ProcessPost0. + */ +uint8_t USB_ProcessIn0(void) +{ + uint32_t CtrlState = pInformation->CtrlState; + + if ((CtrlState == InData) || (CtrlState == LastInData)) + { + DataStageIn(); + /* CtrlState may be changed outside the function */ + CtrlState = pInformation->CtrlState; + } + + else if (CtrlState == WaitStatusIn) + { + if ((pInformation->bRequest == SET_ADDRESS) && (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))) + { + USB_SetDeviceAddress(pInformation->USBwValue0); + pUser_Standard_Requests->User_SetDeviceAddress(); + } + (*pProperty->Process_Status_IN)(); + CtrlState = Stalled; + } + + else + { + CtrlState = Stalled; + } + + pInformation->CtrlState = CtrlState; + + return USB_ProcessPost0(); +} + +/** + * @brief Process the OUT token on all default endpoint. + * @return USB_ProcessPost0. + */ +uint8_t USB_ProcessOut0(void) +{ + uint32_t CtrlState = pInformation->CtrlState; + + if ((CtrlState == InData) || (CtrlState == LastInData)) + { + /* host aborts the transfer before finish */ + CtrlState = Stalled; + } + else if ((CtrlState == OutData) || (CtrlState == LastOutData)) + { + DataStageOut(); + CtrlState = pInformation->CtrlState; /* may be changed outside the function */ + } + + else if (CtrlState == WaitStatusOut) + { + (*pProperty->Process_Status_OUT)(); + CtrlState = Stalled; + } + + /* Unexpect state, STALL the endpoint */ + else + { + CtrlState = Stalled; + } + + pInformation->CtrlState = CtrlState; + + return USB_ProcessPost0(); +} + +/** + * @brief Stall the Endpoint 0 in case of error. + * @return + * - 0 if the control State is in Pause + * - 1 if not. + */ +uint8_t USB_ProcessPost0(void) +{ + USB_SetEpRxCnt(ENDP0, Device_Property.MaxPacketSize); + + if (pInformation->CtrlState == Stalled) + { + vSetEPRxStatus(EP_RX_STALL); + vSetEPTxStatus(EP_TX_STALL); + } + return (pInformation->CtrlState == Pause); +} + +/** + * @brief Set the device and all the used Endpoints addresses. + * @param Val device address. + */ +void USB_SetDeviceAddress(uint8_t Val) +{ + uint32_t i; + uint32_t nEP = Device_Table.TotalEndpoint; + + /* set address in every used endpoint */ + for (i = 0; i < nEP; i++) + { + _SetEPAddress((uint8_t)i, (uint8_t)i); + } /* for */ + _SetDADDR(Val | ADDR_EFUC); /* set device address and enable function */ +} + +/** + * @brief No operation function. + */ +void USB_ProcessNop(void) +{ +} diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_init.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_init.c new file mode 100644 index 0000000000..016aec225c --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_init.c @@ -0,0 +1,69 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_init.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "usb_lib.h" + +/* The number of current endpoint, it will be used to specify an endpoint */ +uint8_t EPindex; +/* The number of current device, it is an index to the Device_Table */ +/* uint8_t Device_no; */ +/* Points to the USB_DeviceMess structure of current device */ +/* The purpose of this register is to speed up the execution */ +USB_DeviceMess* pInformation; +/* Points to the DEVICE_PROP structure of current device */ +/* The purpose of this register is to speed up the execution */ +DEVICE_PROP* pProperty; +/* Temporary save the state of Rx & Tx status. */ +/* Whenever the Rx or Tx state is changed, its value is saved */ +/* in this variable first and will be set to the EPRB or EPRA */ +/* at the end of interrupt process */ +uint16_t SaveState; +uint16_t wInterrupt_Mask; +USB_DeviceMess Device_Info; +USER_STANDARD_REQUESTS* pUser_Standard_Requests; + +/** + * @brief USB system initialization + */ +void USB_Init(void) +{ + pInformation = &Device_Info; + pInformation->CtrlState = 2; + pProperty = &Device_Property; + pUser_Standard_Requests = &User_Standard_Requests; + /* Initialize devices one by one */ + pProperty->Init(); + /*Pull up DP*/ + _EnPortPullup(); +} diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_int.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_int.c new file mode 100644 index 0000000000..66f8d4fe2a --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_int.c @@ -0,0 +1,179 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_int.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "usb_lib.h" + +__IO uint16_t SaveRState; +__IO uint16_t SaveTState; + +extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */ +extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */ + +/** + * @brief Low priority Endpoint Correct Transfer interrupt's service routine. + */ +void USB_CorrectTransferLp(void) +{ + __IO uint16_t wEPVal = 0; + /* stay in loop while pending interrupts */ + while (((wIstr = _GetISTR()) & STS_CTRS) != 0) + { + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & STS_EP_ID); + if (EPindex == 0) + { + /* Decode and service control endpoint interrupt */ + /* calling related service routine */ + /* (USB_ProcessSetup0, USB_ProcessIn0, USB_ProcessOut0) */ + + /* save RX & TX status */ + /* and set both to NAK */ + + SaveRState = _GetENDPOINT(ENDP0); + SaveTState = SaveRState & EPTX_STS; + SaveRState &= EPRX_STS; + _SetEPRxTxStatus(ENDP0, EP_RX_NAK, EP_TX_NAK); + + /* DIR bit = origin of the interrupt */ + + if ((wIstr & STS_DIR) == 0) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTRS_TX = 1) always */ + + _ClearEP_CTR_TX(ENDP0); + USB_ProcessIn0(); + + /* before terminate set Tx & Rx status */ + + _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState); + return; + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + + wEPVal = _GetENDPOINT(ENDP0); + + if ((wEPVal & EP_SETUP) != 0) + { + _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */ + USB_ProcessSetup0(); + /* before terminate set Tx & Rx status */ + + _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState); + return; + } + + else if ((wEPVal & EP_CTRS_RX) != 0) + { + _ClearEP_CTR_RX(ENDP0); + USB_ProcessOut0(); + /* before terminate set Tx & Rx status */ + + _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState); + return; + } + } + } /* if(EPindex == 0) */ + else + { + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = _GetENDPOINT(EPindex); + if ((wEPVal & EP_CTRS_RX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_RX(EPindex); + + /* call OUT service function */ + (*pEpInt_OUT[EPindex - 1])(); + + } /* if((wEPVal & EP_CTRS_RX) */ + + if ((wEPVal & EP_CTRS_TX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_TX(EPindex); + + /* call IN service function */ + (*pEpInt_IN[EPindex - 1])(); + } /* if((wEPVal & EP_CTRS_TX) != 0) */ + + } /* if(EPindex == 0) else */ + + } /* while(...) */ +} + +/** + * @brief High Priority Endpoint Correct Transfer interrupt's service routine. + */ +void USB_CorrectTransferHp(void) +{ + uint32_t wEPVal = 0; + + while (((wIstr = _GetISTR()) & STS_CTRS) != 0) + { + _SetISTR((uint16_t)CLR_CTRS); /* clear CTR flag */ + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & STS_EP_ID); + /* process related endpoint register */ + wEPVal = _GetENDPOINT(EPindex); + if ((wEPVal & EP_CTRS_RX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_RX(EPindex); + + /* call OUT service function */ + (*pEpInt_OUT[EPindex - 1])(); + + } /* if((wEPVal & EP_CTRS_RX) */ + else if ((wEPVal & EP_CTRS_TX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_TX(EPindex); + + /* call IN service function */ + (*pEpInt_IN[EPindex - 1])(); + + } /* if((wEPVal & EP_CTRS_TX) != 0) */ + + } /* while(...) */ +} diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_mem.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_mem.c new file mode 100644 index 0000000000..539a76b7cc --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_mem.c @@ -0,0 +1,81 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_mem.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "usb_lib.h" +u8* EpOutDataPtrTmp; +u8* EpInDataPtrTmp; + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + */ +void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */ + uint32_t i, temp1, temp2; + uint16_t* pdwVal; + pdwVal = (uint16_t*)(wPMABufAddr * 2 + PMAAddr); + for (i = n; i != 0; i--) + { + temp1 = (uint16_t)*pbUsrBuf; + pbUsrBuf++; + temp2 = temp1 | (uint16_t)*pbUsrBuf << 8; + *pdwVal++ = temp2; + pdwVal++; + pbUsrBuf++; + EpInDataPtrTmp = pbUsrBuf; + } +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + */ +void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1; /* /2*/ + uint32_t i; + uint32_t* pdwVal; + pdwVal = (uint32_t*)(wPMABufAddr * 2 + PMAAddr); + for (i = n; i != 0; i--) + { + *(uint16_t*)pbUsrBuf++ = *pdwVal++; + pbUsrBuf++; + EpOutDataPtrTmp = pbUsrBuf; + } +} diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_regs.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_regs.c new file mode 100644 index 0000000000..9dc97c4db7 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_regs.c @@ -0,0 +1,598 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_regs.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "usb_lib.h" + +/** + * @brief Set the CTRL register value. + * @param wRegValue new register value. + */ +void USB_SetCtrl(uint16_t wRegValue) +{ + _SetCNTR(wRegValue); +} + +/** + * @brief returns the CTRL register value. + * @return CTRL register Value. + */ +uint16_t USB_GetCtrl(void) +{ + return (_GetCNTR()); +} + +/** + * @brief Set the STS register value. + * @param wRegValue new register value. + */ +void USB_SetSts(uint16_t wRegValue) +{ + _SetISTR(wRegValue); +} + +/** + * @brief Returns the STS register value. + * @return STS register Value + */ +uint16_t USB_GetSts(void) +{ + return (_GetISTR()); +} + +/** + * @brief Returns the FN register value. + * @return FN register Value + */ +uint16_t USB_GetFn(void) +{ + return (_GetFNR()); +} + +/** + * @brief Set the ADDR register value. + * @param wRegValue new register value. + */ +void USB_SetAddr(uint16_t wRegValue) +{ + _SetDADDR(wRegValue); +} + +/** + * @brief Returns the ADDR register value. + * @return ADDR register Value + */ +uint16_t USB_GetAddr(void) +{ + return (_GetDADDR()); +} + +/** + * @brief Set the BUFTAB. + * @param wRegValue New register value. + */ +void USB_SetBuftab(uint16_t wRegValue) +{ + _SetBTABLE(wRegValue); +} + +/** + * @brief Returns the BUFTAB register value. + * @return BUFTAB address. + */ +uint16_t USB_GetBTABLE(void) +{ + return (_GetBTABLE()); +} + +/** + * @brief Set the Endpoint register value. + * @param bEpNum Endpoint Number. + * @param wRegValue New register value. + */ +void USB_SetEndPoint(uint8_t bEpNum, uint16_t wRegValue) +{ + _SetENDPOINT(bEpNum, wRegValue); +} + +/** + * @brief Return the Endpoint register value. + * @param bEpNum Endpoint Number. + * @return Endpoint register value. + */ +uint16_t USB_GetEndPoint(uint8_t bEpNum) +{ + return (_GetENDPOINT(bEpNum)); +} + +/** + * @brief sets the type in the endpoint register. + * @param bEpNum Endpoint Number. + * @param wType type definition. + */ +void USB_SetEpType(uint8_t bEpNum, uint16_t wType) +{ + _SetEPType(bEpNum, wType); +} + +/** + * @brief Returns the endpoint type. + * @param bEpNum Endpoint Number. + * @return Endpoint Type + */ +uint16_t USB_GetEpType(uint8_t bEpNum) +{ + return (_GetEPType(bEpNum)); +} + +/** + * @brief Set the status of Tx endpoint. + * @param bEpNum Endpoint Number. + * @param wState new state. + */ +void SetEPTxStatus(uint8_t bEpNum, uint16_t wState) +{ + _SetEPTxStatus(bEpNum, wState); +} + +/** + * @brief Set the status of Rx endpoint. + * @param bEpNum Endpoint Number. + * @param wState new state. + */ +void SetEPRxStatus(uint8_t bEpNum, uint16_t wState) +{ + _SetEPRxStatus(bEpNum, wState); +} + +/** + * @brief sets the status for Double Buffer Endpoint to STALL + * @param bEpNum Endpoint Number. + * @param bDir Endpoint direction. + */ +void USB_SetDouBleBuferEpStall(uint8_t bEpNum, uint8_t bDir) +{ + uint16_t Endpoint_DTOG_Status; + Endpoint_DTOG_Status = USB_GetEndPoint(bEpNum); + if (bDir == EP_DBUF_OUT) + { /* OUT double buffered endpoint */ + _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DATTOG1); + } + else if (bDir == EP_DBUF_IN) + { /* IN double buffered endpoint */ + _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DATTOG1); + } +} + +/** + * @brief Returns the endpoint Tx status. + * @param bEpNum Endpoint Number. + * @return Endpoint TX Status + */ +uint16_t USB_GetEpTxSts(uint8_t bEpNum) +{ + return (_GetEPTxStatus(bEpNum)); +} + +/** + * @brief Returns the endpoint Rx status. + * @param bEpNum Endpoint Number. + * @return Endpoint RX Status + */ +uint16_t USB_GetEpRxSts(uint8_t bEpNum) +{ + return (_GetEPRxStatus(bEpNum)); +} + +/** + * @brief Valid the endpoint Tx Status. + * @param bEpNum Endpoint Number. + */ +void USB_SetEpTxValid(uint8_t bEpNum) +{ + _SetEPTxStatus(bEpNum, EP_TX_VALID); +} + +/** + * @brief Valid the endpoint Rx Status. + * @param bEpNum Endpoint Number. + */ +void USB_SetEpRxValid(uint8_t bEpNum) +{ + _SetEPRxStatus(bEpNum, EP_RX_VALID); +} + +/** + * @brief Clear the EP_KIND bit. + * @param bEpNum Endpoint Number. + */ +void USB_SetEpKind(uint8_t bEpNum) +{ + _SetEP_KIND(bEpNum); +} + +/** + * @brief set the EP_KIND bit. + * @param bEpNum Endpoint Number. + */ +void USB_ClrEpKind(uint8_t bEpNum) +{ + _ClearEP_KIND(bEpNum); +} +/** + * @brief Clear the Status Out of the related Endpoint + * @param bEpNum Endpoint Number. + */ +void USB_ClrStsOut(uint8_t bEpNum) +{ + _ClearEP_KIND(bEpNum); +} +/** + * @brief Set the Status Out of the related Endpoint + * @param bEpNum Endpoint Number. + */ +void USB_SetStsOut(uint8_t bEpNum) +{ + _SetEP_KIND(bEpNum); +} +/** + * @brief Enable the double buffer feature for the endpoint. + * @param bEpNum Endpoint Number. + */ +void USB_SetEpDoubleBufer(uint8_t bEpNum) +{ + _SetEP_KIND(bEpNum); +} +/** + * @brief Disable the double buffer feature for the endpoint. + * @param bEpNum Endpoint Number. + */ +void USB_ClrEpDoubleBufer(uint8_t bEpNum) +{ + _ClearEP_KIND(bEpNum); +} +/** + * @brief Returns the Stall status of the Tx endpoint. + * @param bEpNum Endpoint Number. + * @return Tx Stall status. + */ +uint16_t USB_GetTxStallSts(uint8_t bEpNum) +{ + return (_GetTxStallStatus(bEpNum)); +} +/** + * @brief Returns the Stall status of the Rx endpoint. + * @param bEpNum Endpoint Number. + * @return Rx Stall status. + */ +uint16_t USB_GetRxStallSts(uint8_t bEpNum) +{ + return (_GetRxStallStatus(bEpNum)); +} +/** + * @brief Clear the CTR_RX bit. + * @param bEpNum Endpoint Number. + */ +void USB_ClrEpCtrsRx(uint8_t bEpNum) +{ + _ClearEP_CTR_RX(bEpNum); +} +/** + * @brief Clear the CTR_TX bit. + * @param bEpNum Endpoint Number. + */ +void USB_ClrEpCtrsTx(uint8_t bEpNum) +{ + _ClearEP_CTR_TX(bEpNum); +} +/** + * @brief Toggle the DTOG_RX bit. + * @param bEpNum Endpoint Number. + */ +void USB_DattogRx(uint8_t bEpNum) +{ + _ToggleDTOG_RX(bEpNum); +} +/** + * @brief Toggle the DTOG_TX bit. + * @param bEpNum Endpoint Number. + */ +void USB_DattogTx(uint8_t bEpNum) +{ + _ToggleDTOG_TX(bEpNum); +} +/** + * @brief Clear the DTOG_RX bit. + * @param bEpNum Endpoint Number. + */ +void USB_ClrDattogRx(uint8_t bEpNum) +{ + _ClearDTOG_RX(bEpNum); +} +/** + * @brief Clear the DTOG_TX bit. + * @param bEpNum Endpoint Number. + */ +void USB_ClrDattogTx(uint8_t bEpNum) +{ + _ClearDTOG_TX(bEpNum); +} +/** + * @brief Set the endpoint address. + * @param bEpNum Endpoint Number. + * @param bAddr New endpoint address. + */ +void USB_SetEpAddress(uint8_t bEpNum, uint8_t bAddr) +{ + _SetEPAddress(bEpNum, bAddr); +} +/** + * @brief Get the endpoint address. + * @param bEpNum Endpoint Number. + * @return Endpoint address. + */ +uint8_t USB_GetEpAddress(uint8_t bEpNum) +{ + return (_GetEPAddress(bEpNum)); +} +/** + * @brief Set the endpoint Tx buffer address. + * @param bEpNum Endpoint Number. + * @param wAddr new address. + */ +void USB_SetEpTxAddr(uint8_t bEpNum, uint16_t wAddr) +{ + _SetEPTxAddr(bEpNum, wAddr); +} +/** + * @brief Set the endpoint Rx buffer address. + * @param bEpNum Endpoint Number. + * @param wAddr new address. + */ +void USB_SetEpRxAddr(uint8_t bEpNum, uint16_t wAddr) +{ + _SetEPRxAddr(bEpNum, wAddr); +} +/** + * @brief Returns the endpoint Tx buffer address. + * @param bEpNum Endpoint Number. + * @return Rx buffer address. + */ +uint16_t USB_GetEpTxAddr(uint8_t bEpNum) +{ + return (_GetEPTxAddr(bEpNum)); +} +/** + * @brief Returns the endpoint Rx buffer address. + * @param bEpNum Endpoint Number. + * @return Rx buffer address. + */ +uint16_t USB_GetEpRxAddr(uint8_t bEpNum) +{ + return (_GetEPRxAddr(bEpNum)); +} +/** + * @brief Set the Tx count. + * @param bEpNum Endpoint Number. + * @param wCount new count value. + */ +void USB_SetEpTxCnt(uint8_t bEpNum, uint16_t wCount) +{ + _SetEPTxCount(bEpNum, wCount); +} +/** + * @brief Set the Count Rx Register value. + * @param pdwReg point to the register. + * @param wCount the new register value. + */ +void USB_SetEpCntRxReg(uint32_t* pdwReg, uint16_t wCount) +{ + _SetEPCountRxReg(dwReg, wCount); +} +/** + * @brief Set the Rx count. + * @param bEpNum Endpoint Number. + * @param wCount the new count value. + */ +void USB_SetEpRxCnt(uint8_t bEpNum, uint16_t wCount) +{ + _SetEPRxCount(bEpNum, wCount); +} +/** + * @brief Get the Tx count. + * @param bEpNum Endpoint Number. + * @return Tx count value. + */ +uint16_t USB_GetEpTxCnt(uint8_t bEpNum) +{ + return (_GetEPTxCount(bEpNum)); +} +/** + * @brief Get the Rx count. + * @param bEpNum Endpoint Number. + * @return Rx count value. + */ +uint16_t USB_GetEpRxCnt(uint8_t bEpNum) +{ + return (_GetEPRxCount(bEpNum)); +} +/** + * @brief Set the addresses of the buffer 0 and 1. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr new address of buffer 0. + * @param wBuf1Addr new address of buffer 1. + */ +void USB_SetEpDblBuferAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr) +{ + _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr); +} +/** + * @brief Set the Buffer 1 address. + * @param bEpNum Endpoint Number + * @param wBuf0Addr new address. + */ +void USB_SetEpDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr) +{ + _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); +} +/** + * @brief Set the Buffer 1 address. + * @param bEpNum Endpoint Number + * @param wBuf1Addr new address. + */ +void USB_SetEpDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr) +{ + _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); +} +/** + * @brief Returns the address of the Buffer 0. + * @param bEpNum Endpoint Number. + */ +uint16_t USB_GetEpDblBuf0Addr(uint8_t bEpNum) +{ + return (_GetEPDblBuf0Addr(bEpNum)); +} +/** + * @brief Returns the address of the Buffer 1. + * @param bEpNum Endpoint Number. + * @return Address of the Buffer 1. + */ +uint16_t USB_GetEpDblBuf1Addr(uint8_t bEpNum) +{ + return (_GetEPDblBuf1Addr(bEpNum)); +} +/** + * @brief Set the number of bytes for a double Buffer endpoint. + * @param bEpNum + * @param bDir + * @param wCount + */ +void USB_SetEpDblBuferCnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) +{ + _SetEPDblBuffCount(bEpNum, bDir, wCount); +} +/** + * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint. + * @param bEpNum + * @param bDir + * @param wCount + */ +void USB_SetEpDblBuf0Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) +{ + _SetEPDblBuf0Count(bEpNum, bDir, wCount); +} +/** + * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint. + * @param bEpNum + * @param bDir + * @param wCount + */ +void USB_SetEpDblBuf1Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) +{ + _SetEPDblBuf1Count(bEpNum, bDir, wCount); +} +/** + * @brief Returns the number of byte received in the buffer 0 of a double Buffer endpoint. + * @param bEpNum Endpoint Number. + * @return Endpoint Buffer 0 count + */ +uint16_t USB_GetEpDblBuf0Cnt(uint8_t bEpNum) +{ + return (_GetEPDblBuf0Count(bEpNum)); +} +/** + * @brief Returns the number of data received in the buffer 1 of a double Buffer endpoint. + * @param bEpNum Endpoint Number. + * @return Endpoint Buffer 1 count. + */ +uint16_t USB_GetEpDblBuf1Cnt(uint8_t bEpNum) +{ + return (_GetEPDblBuf1Count(bEpNum)); +} +/** + * @brief gets direction of the double buffered endpoint + * @param bEpNum Endpoint Number. + * @return EP_DBUF_OUT, EP_DBUF_IN, EP_DBUF_ERR if the endpoint counter not yet programmed. + */ +EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum) +{ + if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0) + return (EP_DBUF_OUT); + else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0) + return (EP_DBUF_IN); + else + return (EP_DBUF_ERR); +} +/** + * @brief free buffer used from the application realizing it to the line toggles + * bit SW_BUF in the double buffered endpoint register + * @param bEpNum + * @param bDir + */ +void USB_FreeUserBuf(uint8_t bEpNum, uint8_t bDir) +{ + if (bDir == EP_DBUF_OUT) + { /* OUT double buffered endpoint */ + _ToggleDTOG_TX(bEpNum); + } + else if (bDir == EP_DBUF_IN) + { /* IN double buffered endpoint */ + _ToggleDTOG_RX(bEpNum); + } +} + +/** + * @brief merge two byte in a word. + * @param bh byte high + * @param bl bytes low. + * @return resulted word. + */ +uint16_t USB_ToWord(uint8_t bh, uint8_t bl) +{ + uint16_t wRet; + wRet = (uint16_t)bl | ((uint16_t)bh << 8); + return (wRet); +} +/** + * @brief Swap two byte in a word. + * @param wSwW word to Swap. + * @return resulted word. + */ +uint16_t USB_ByteSwap(uint16_t wSwW) +{ + uint8_t bTemp; + uint16_t wRet; + bTemp = (uint8_t)(wSwW & 0xff); + wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8); + return (wRet); +} diff --git a/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_sil.c b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_sil.c new file mode 100644 index 0000000000..930e661c83 --- /dev/null +++ b/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/src/usb_sil.c @@ -0,0 +1,83 @@ +/***************************************************************************** + * Copyright (c) 2019, Nations Technologies Inc. + * + * All rights reserved. + * **************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Nations' name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ****************************************************************************/ + +/** + * @file usb_sil.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. + */ +#include "usb_lib.h" + +/** + * @brief Initialize the USB Device IP and the Endpoint 0. + * @return Status. + */ +uint32_t USB_SilInit(void) +{ + /* USB interrupts initialization */ + /* clear pending interrupts */ + _SetISTR(0); + wInterrupt_Mask = IMR_MSK; + /* set interrupts mask */ + _SetCNTR(wInterrupt_Mask); + return 0; +} + +/** + * @brief Write a buffer of data to a selected endpoint. + * @param bEpAddr The address of the non control endpoint. + * @param pBufferPointer The pointer to the buffer of data to be written to the endpoint. + * @param wBufferSize Number of data to be written (in bytes). + * @return Status. + */ +uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize) +{ + /* Use the memory interface function to write to the selected endpoint */ + USB_CopyUserToPMABuf(pBufferPointer, USB_GetEpTxAddr(bEpAddr & 0x7F), wBufferSize); + /* Update the data length in the control register */ + USB_SetEpTxCnt((bEpAddr & 0x7F), wBufferSize); + return 0; +} + +/** + * @brief Write a buffer of data to a selected endpoint. + * @param bEpAddr The address of the non control endpoint. + * @param pBufferPointer The pointer to which will be saved the received data buffer. + * @return Number of received data (in Bytes). + */ +uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer) +{ + uint32_t DataLength = 0; + /* Get the number of received data on the selected Endpoint */ + DataLength = USB_GetEpRxCnt(bEpAddr & 0x7F); + /* Use the memory interface function to write to the selected endpoint */ + USB_CopyPMAToUserBuf(pBufferPointer, USB_GetEpRxAddr(bEpAddr & 0x7F), DataLength); + /* Return the number of received data */ + return DataLength; +} diff --git a/bsp/n32g452xx/Libraries/rt_drivers/SConscript b/bsp/n32g452xx/Libraries/rt_drivers/SConscript new file mode 100755 index 0000000000..1298ec7063 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/SConscript @@ -0,0 +1,64 @@ +# RT-Thread building script for component +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +src += ['drv_common.c'] + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['drv_wdt.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +if GetDepend(['BSP_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['BSP_USING_HWTIMER']): + src += ['drv_hwtimer.c'] + +if GetDepend(['BSP_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['BSP_USING_ETH', 'BSP_USING_LWIP']): + src += ['drv_eth.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): + src += ['drv_soft_i2c.c'] + +if GetDepend(['BSP_USING_ADC']): + src += Glob('drv_adc.c') + +if GetDepend('BSP_USING_SRAM'): + src += ['drv_sram.c'] + +if GetDepend('BSP_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('BSP_USING_ON_CHIP_FLASH'): + src += ['drv_flash.c'] + +if GetDepend(['BSP_USING_WDT']): + src += ['drv_wdt.c'] + +if GetDepend(['BSP_USING_CAN']): + src += ['drv_can.c'] + +if GetDepend(['BSP_USING_SDIO']): + src += ['drv_sdio.c'] + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c new file mode 100644 index 0000000000..8450b35014 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#include +#include "drv_adc.h" + +#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) +#define DRV_DEBUG +#define LOG_TAG "drv.adc" +#include + +struct n32_adc +{ + struct rt_adc_device n32_adc_device; + ADC_Module *ADC_Handler; + char *name; +}; + +static struct n32_adc n32_adc_obj[] = +{ +#ifdef BSP_USING_ADC1 + ADC1_CONFIG, +#endif + +#ifdef BSP_USING_ADC2 + ADC2_CONFIG, +#endif + +#ifdef BSP_USING_ADC3 + ADC3_CONFIG, +#endif +}; + +static rt_uint32_t n32_adc_get_channel(rt_uint32_t channel) +{ + rt_uint32_t n32_channel = 0; + + switch (channel) + { + case 0: + n32_channel = ADC_CH_0; + break; + case 1: + n32_channel = ADC_CH_1; + break; + case 2: + n32_channel = ADC_CH_2; + break; + case 3: + n32_channel = ADC_CH_3; + break; + case 4: + n32_channel = ADC_CH_4; + break; + case 5: + n32_channel = ADC_CH_5; + break; + case 6: + n32_channel = ADC_CH_6; + break; + case 7: + n32_channel = ADC_CH_7; + break; + case 8: + n32_channel = ADC_CH_8; + break; + case 9: + n32_channel = ADC_CH_9; + break; + case 10: + n32_channel = ADC_CH_10; + break; + case 11: + n32_channel = ADC_CH_11; + break; + case 12: + n32_channel = ADC_CH_12; + break; + case 13: + n32_channel = ADC_CH_13; + break; + case 14: + n32_channel = ADC_CH_14; + break; + case 15: + n32_channel = ADC_CH_15; + break; + case 16: + n32_channel = ADC_CH_16; + break; + case 17: + n32_channel = ADC_CH_17; + break; + } + + return n32_channel; +} + +static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + ADC_Module *n32_adc_handler; + ADC_InitType ADC_InitStructure; + RT_ASSERT(device != RT_NULL); + n32_adc_handler = device->parent.user_data; + + n32_msp_adc_init(n32_adc_handler); + + ADC_InitStruct(&ADC_InitStructure); + ADC_InitStructure.WorkMode = ADC_WORKMODE_INDEPENDENT; + ADC_InitStructure.MultiChEn = DISABLE; + ADC_InitStructure.ContinueConvEn = DISABLE; + ADC_InitStructure.ExtTrigSelect = ADC_EXT_TRIGCONV_NONE; + ADC_InitStructure.DatAlign = ADC_DAT_ALIGN_R; + ADC_InitStructure.ChsNumber = 1; + ADC_Init(n32_adc_handler, &ADC_InitStructure); + + /* ADCx regular channels configuration */ + ADC_ConfigRegularChannel(n32_adc_handler, n32_adc_get_channel(channel), 1, ADC_SAMP_TIME_28CYCLES5); + + /* Enable ADCx */ + ADC_Enable(n32_adc_handler, ENABLE); + + /* Start ADCx calibration */ + ADC_StartCalibration(n32_adc_handler); + /* Check the end of ADCx calibration */ + while(ADC_GetCalibrationStatus(n32_adc_handler)); + + if (enabled) + { + /* Enable ADC1 */ + ADC_Enable(n32_adc_handler, ENABLE); + } + else + { + /* Enable ADCx */ + ADC_Enable(n32_adc_handler, DISABLE); + } + + return RT_EOK; +} + +static rt_err_t n32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + ADC_Module *n32_adc_handler; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + n32_adc_handler = device->parent.user_data; + + /* Start ADCx Software Conversion */ + ADC_EnableSoftwareStartConv(n32_adc_handler, ENABLE); + + /* Wait for the ADC to convert */ + while(ADC_GetFlagStatus(n32_adc_handler, ADC_FLAG_ENDC) == RESET); + + /* get ADC value */ + *value = ADC_GetDat(n32_adc_handler); + + return RT_EOK; +} + +static const struct rt_adc_ops at_adc_ops = +{ + .enabled = n32_adc_enabled, + .convert = n32_get_adc_value, +}; + +static int rt_hw_adc_init(void) +{ + int result = RT_EOK; + int i = 0; + + for (i = 0; i < sizeof(n32_adc_obj) / sizeof(n32_adc_obj[0]); i++) + { + /* register ADC device */ + if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device, + n32_adc_obj[i].name, &at_adc_ops, + n32_adc_obj[i].ADC_Handler) == RT_EOK) + { + LOG_D("%s register success", n32_adc_obj[i].name); + } + else + { + LOG_E("%s register failed", n32_adc_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); + +#endif /* BSP_USING_ADC */ + diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.h new file mode 100644 index 0000000000..69ae05bcba --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) + +#ifndef ADC1_CONFIG +#define ADC1_CONFIG \ + { \ + .ADC_Handler = ADC1, \ + .name = "adc1", \ + } +#endif /* ADC1_CONFIG */ + +#ifndef ADC2_CONFIG +#define ADC2_CONFIG \ + { \ + .ADC_Handler = ADC2, \ + .name = "adc2", \ + } +#endif /* ADC2_CONFIG */ + +#ifndef ADC3_CONFIG +#define ADC3_CONFIG \ + { \ + .ADC_Handler = ADC3, \ + .name = "adc3", \ + } +#endif /* ADC3_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_common.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_common.c new file mode 100644 index 0000000000..b7bae8bf2c --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_common.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#include "drv_common.h" +#include "board.h" + +#ifdef RT_USING_SERIAL +#ifdef RT_USING_SERIAL_V2 +#include "drv_usart_v2.h" +#else +#include "drv_usart.h" +#endif +#endif + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_common.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_common.h new file mode 100644 index 0000000000..9f053e4a07 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_common.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include +#ifdef RT_USING_DEVICE +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void rt_hw_us_delay(rt_uint32_t us); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c new file mode 100644 index 0000000000..85839243c8 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#include +#include + +#ifdef BSP_USING_ON_CHIP_FLASH +#include "drv_flash.h" + +#if defined(PKG_USING_FAL) +#include "fal.h" +#endif + +//#define DRV_DEBUG +#define LOG_TAG "drv.flash" +#include + +/** + * @brief Gets the page of a given address + * @param addr: address of the flash memory + * @retval The page of a given address + */ +static rt_uint32_t get_page(uint32_t addr) +{ + rt_uint32_t page = 0; + + page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE); + + return page; +} + +/** + * Read data from flash. + * @note This operation's units is word. + * + * @param addr flash address + * @param buf buffer to store read data + * @param size read bytes size + * + * @return result + */ +int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size) +{ + size_t i; + + if ((addr + size) > N32_FLASH_END_ADDRESS) + { + LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return -RT_EINVAL; + } + + for (i = 0; i < size; i++, buf++, addr++) + { + *buf = *(rt_uint8_t *) addr; + } + + return size; +} + +/** + * Write data to flash. + * @note This operation's units is word. + * @note This operation must after erase. @see flash_erase. + * + * @param addr flash address + * @param buf the write data buffer + * @param size write bytes size + * + * @return result + */ +int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) +{ + rt_err_t result = RT_EOK; + rt_uint32_t end_addr = addr + size; + + if (addr % 4 != 0) + { + LOG_E("write addr must be 4-byte alignment"); + return -RT_EINVAL; + } + + if ((end_addr) > N32_FLASH_END_ADDRESS) + { + LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return -RT_EINVAL; + } + + FLASH_Unlock(); + + while (addr < end_addr) + { + if (FLASH_ProgramWord(addr, *((rt_uint32_t *)buf)) == FLASH_COMPL) + { + if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf) + { + result = -RT_ERROR; + break; + } + addr += 4; + buf += 4; + } + else + { + result = -RT_ERROR; + break; + } + } + + FLASH_Lock(); + + if (result != RT_EOK) + { + return result; + } + + return size; +} + +/** + * Erase data on flash . + * @note This operation is irreversible. + * @note This operation's units is different which on many chips. + * + * @param addr flash address + * @param size erase bytes size + * + * @return result + */ +int n32_flash_erase(rt_uint32_t addr, size_t size) +{ + rt_err_t result = RT_EOK; + rt_uint32_t end_addr = addr + size; + rt_uint32_t page_addr = 0; + + FLASH_Unlock(); + + if ((end_addr) > N32_FLASH_END_ADDRESS) + { + LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size)); + return -RT_EINVAL; + } + + while(addr < end_addr) + { + page_addr = get_page(addr); + + if(FLASH_EraseOnePage(page_addr) != FLASH_COMPL) + { + result = -RT_ERROR; + goto __exit; + } + + addr += FLASH_PAGE_SIZE; + } + + FLASH_Lock(); + +__exit: + if(result != RT_EOK) + { + return result; + } + + return size; +} + +#if defined(PKG_USING_FAL) + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); +static int fal_flash_erase(long offset, size_t size); + +const struct fal_flash_dev n32_onchip_flash = +{ + "onchip_flash", + N32_FLASH_START_ADRESS, + N32_FLASH_SIZE, + FLASH_PAGE_SIZE, + { + NULL, + fal_flash_read, + fal_flash_write, + fal_flash_erase + } +}; + +static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size) +{ + return n32_flash_read(n32_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size) +{ + return n32_flash_write(n32_onchip_flash.addr + offset, buf, size); +} + +static int fal_flash_erase(long offset, size_t size) +{ + return n32_flash_erase(n32_onchip_flash.addr + offset, size); +} + +#endif +#endif /* BSP_USING_ON_CHIP_FLASH */ diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.h new file mode 100644 index 0000000000..caac8795cb --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_flash.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#ifndef __DRV_FLASH_H__ +#define __DRV_FLASH_H__ + +#include +#include "rtdevice.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size); +int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size); +int n32_flash_erase(rt_uint32_t addr, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_FLASH_H__ */ diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c new file mode 100644 index 0000000000..40b59d1898 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c @@ -0,0 +1,867 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#include "drv_gpio.h" +#include +#include +#include "n32g45x.h" + +#ifdef RT_USING_PIN + +#define N32F10X_PIN_NUMBERS 64 //[48, 64, 100, 144 ] + +#define __N32_PIN(index, rcc, gpio, gpio_index) \ +{ \ +0, RCC_##rcc##_PERIPH_GPIO##gpio, GPIO##gpio, GPIO_PIN_##gpio_index \ +, GPIO##gpio##_PORT_SOURCE, GPIO_PIN_SOURCE##gpio_index \ +} +#define __N32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0} + +/* N32 GPIO driver */ +struct pin_index +{ + int index; + uint32_t rcc; + GPIO_Module *gpio; + uint32_t pin; + uint8_t port_source; + uint8_t pin_source; +}; + +static const struct pin_index pins[] = +{ +#if (N32F10X_PIN_NUMBERS == 48) + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(2, APB2, C, 13), + __N32_PIN(3, APB2, C, 14), + __N32_PIN(4, APB2, C, 15), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(10, APB2, A, 0), + __N32_PIN(11, APB2, A, 1), + __N32_PIN(12, APB2, A, 2), + __N32_PIN(13, APB2, A, 3), + __N32_PIN(14, APB2, A, 4), + __N32_PIN(15, APB2, A, 5), + __N32_PIN(16, APB2, A, 6), + __N32_PIN(17, APB2, A, 7), + __N32_PIN(18, APB2, B, 0), + __N32_PIN(19, APB2, B, 1), + __N32_PIN(20, APB2, B, 2), + __N32_PIN(21, APB2, B, 10), + __N32_PIN(22, APB2, B, 11), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(25, APB2, B, 12), + __N32_PIN(26, APB2, B, 13), + __N32_PIN(27, APB2, B, 14), + __N32_PIN(28, APB2, B, 15), + __N32_PIN(29, APB2, A, 8), + __N32_PIN(30, APB2, A, 9), + __N32_PIN(31, APB2, A, 10), + __N32_PIN(32, APB2, A, 11), + __N32_PIN(33, APB2, A, 12), + __N32_PIN(34, APB2, A, 13), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(37, APB2, A, 14), + __N32_PIN(38, APB2, A, 15), + __N32_PIN(39, APB2, B, 3), + __N32_PIN(40, APB2, B, 4), + __N32_PIN(41, APB2, B, 5), + __N32_PIN(42, APB2, B, 6), + __N32_PIN(43, APB2, B, 7), + __N32_PIN_DEFAULT, + __N32_PIN(45, APB2, B, 8), + __N32_PIN(46, APB2, B, 9), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + +#endif +#if (N32F10X_PIN_NUMBERS == 64) + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(2, APB2, C, 13), + __N32_PIN(3, APB2, C, 14), + __N32_PIN(4, APB2, C, 15), + __N32_PIN(5, APB2, D, 0), + __N32_PIN(6, APB2, D, 1), + __N32_PIN_DEFAULT, + __N32_PIN(8, APB2, C, 0), + __N32_PIN(9, APB2, C, 1), + __N32_PIN(10, APB2, C, 2), + __N32_PIN(11, APB2, C, 3), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(14, APB2, A, 0), + __N32_PIN(15, APB2, A, 1), + __N32_PIN(16, APB2, A, 2), + __N32_PIN(17, APB2, A, 3), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(20, APB2, A, 4), + __N32_PIN(21, APB2, A, 5), + __N32_PIN(22, APB2, A, 6), + __N32_PIN(23, APB2, A, 7), + __N32_PIN(24, APB2, C, 4), + __N32_PIN(25, APB2, C, 5), + __N32_PIN(26, APB2, B, 0), + __N32_PIN(27, APB2, B, 1), + __N32_PIN(28, APB2, B, 2), + __N32_PIN(29, APB2, B, 10), + __N32_PIN(30, APB2, B, 11), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(33, APB2, B, 12), + __N32_PIN(34, APB2, B, 13), + __N32_PIN(35, APB2, B, 14), + __N32_PIN(36, APB2, B, 15), + __N32_PIN(37, APB2, C, 6), + __N32_PIN(38, APB2, C, 7), + __N32_PIN(39, APB2, C, 8), + __N32_PIN(40, APB2, C, 9), + __N32_PIN(41, APB2, A, 8), + __N32_PIN(42, APB2, A, 9), + __N32_PIN(43, APB2, A, 10), + __N32_PIN(44, APB2, A, 11), + __N32_PIN(45, APB2, A, 12), + __N32_PIN(46, APB2, A, 13), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(49, APB2, A, 14), + __N32_PIN(50, APB2, A, 15), + __N32_PIN(51, APB2, C, 10), + __N32_PIN(52, APB2, C, 11), + __N32_PIN(53, APB2, C, 12), + __N32_PIN(54, APB2, D, 2), + __N32_PIN(55, APB2, B, 3), + __N32_PIN(56, APB2, B, 4), + __N32_PIN(57, APB2, B, 5), + __N32_PIN(58, APB2, B, 6), + __N32_PIN(59, APB2, B, 7), + __N32_PIN_DEFAULT, + __N32_PIN(61, APB2, B, 8), + __N32_PIN(62, APB2, B, 9), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, +#endif +#if (N32F10X_PIN_NUMBERS == 100) + __N32_PIN_DEFAULT, + __N32_PIN(1, APB2, E, 2), + __N32_PIN(2, APB2, E, 3), + __N32_PIN(3, APB2, E, 4), + __N32_PIN(4, APB2, E, 5), + __N32_PIN(5, APB2, E, 6), + __N32_PIN_DEFAULT, + __N32_PIN(7, APB2, C, 13), + __N32_PIN(8, APB2, C, 14), + __N32_PIN(9, APB2, C, 15), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(15, APB2, C, 0), + __N32_PIN(16, APB2, C, 1), + __N32_PIN(17, APB2, C, 2), + __N32_PIN(18, APB2, C, 3), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(23, APB2, A, 0), + __N32_PIN(24, APB2, A, 1), + __N32_PIN(25, APB2, A, 2), + __N32_PIN(26, APB2, A, 3), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(29, APB2, A, 4), + __N32_PIN(30, APB2, A, 5), + __N32_PIN(31, APB2, A, 6), + __N32_PIN(32, APB2, A, 7), + __N32_PIN(33, APB2, C, 4), + __N32_PIN(34, APB2, C, 5), + __N32_PIN(35, APB2, B, 0), + __N32_PIN(36, APB2, B, 1), + __N32_PIN(37, APB2, B, 2), + __N32_PIN(38, APB2, E, 7), + __N32_PIN(39, APB2, E, 8), + __N32_PIN(40, APB2, E, 9), + __N32_PIN(41, APB2, E, 10), + __N32_PIN(42, APB2, E, 11), + __N32_PIN(43, APB2, E, 12), + __N32_PIN(44, APB2, E, 13), + __N32_PIN(45, APB2, E, 14), + __N32_PIN(46, APB2, E, 15), + __N32_PIN(47, APB2, B, 10), + __N32_PIN(48, APB2, B, 11), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(51, APB2, B, 12), + __N32_PIN(52, APB2, B, 13), + __N32_PIN(53, APB2, B, 14), + __N32_PIN(54, APB2, B, 15), + __N32_PIN(55, APB2, D, 8), + __N32_PIN(56, APB2, D, 9), + __N32_PIN(57, APB2, D, 10), + __N32_PIN(58, APB2, D, 11), + __N32_PIN(59, APB2, D, 12), + __N32_PIN(60, APB2, D, 13), + __N32_PIN(61, APB2, D, 14), + __N32_PIN(62, APB2, D, 15), + __N32_PIN(63, APB2, C, 6), + __N32_PIN(64, APB2, C, 7), + __N32_PIN(65, APB2, C, 8), + __N32_PIN(66, APB2, C, 9), + __N32_PIN(67, APB2, A, 8), + __N32_PIN(68, APB2, A, 9), + __N32_PIN(69, APB2, A, 10), + __N32_PIN(70, APB2, A, 11), + __N32_PIN(71, APB2, A, 12), + __N32_PIN(72, APB2, A, 13), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(76, APB2, A, 14), + __N32_PIN(77, APB2, A, 15), + __N32_PIN(78, APB2, C, 10), + __N32_PIN(79, APB2, C, 11), + __N32_PIN(80, APB2, C, 12), + __N32_PIN(81, APB2, D, 0), + __N32_PIN(82, APB2, D, 1), + __N32_PIN(83, APB2, D, 2), + __N32_PIN(84, APB2, D, 3), + __N32_PIN(85, APB2, D, 4), + __N32_PIN(86, APB2, D, 5), + __N32_PIN(87, APB2, D, 6), + __N32_PIN(88, APB2, D, 7), + __N32_PIN(89, APB2, B, 3), + __N32_PIN(90, APB2, B, 4), + __N32_PIN(91, APB2, B, 5), + __N32_PIN(92, APB2, B, 6), + __N32_PIN(93, APB2, B, 7), + __N32_PIN_DEFAULT, + __N32_PIN(95, APB2, B, 8), + __N32_PIN(96, APB2, B, 9), + __N32_PIN(97, APB2, E, 0), + __N32_PIN(98, APB2, E, 1), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, +#endif +#if (N32F10X_PIN_NUMBERS == 144) + __N32_PIN_DEFAULT, + __N32_PIN(1, APB2, E, 2), + __N32_PIN(2, APB2, E, 3), + __N32_PIN(3, APB2, E, 4), + __N32_PIN(4, APB2, E, 5), + __N32_PIN(5, APB2, E, 6), + __N32_PIN_DEFAULT, + __N32_PIN(7, APB2, C, 13), + __N32_PIN(8, APB2, C, 14), + __N32_PIN(9, APB2, C, 15), + + __N32_PIN(10, APB2, F, 0), + __N32_PIN(11, APB2, F, 1), + __N32_PIN(12, APB2, F, 2), + __N32_PIN(13, APB2, F, 3), + __N32_PIN(14, APB2, F, 4), + __N32_PIN(15, APB2, F, 5), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(18, APB2, F, 6), + __N32_PIN(19, APB2, F, 7), + __N32_PIN(20, APB2, F, 8), + __N32_PIN(21, APB2, F, 9), + __N32_PIN(22, APB2, F, 10), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(26, APB2, C, 0), + __N32_PIN(27, APB2, C, 1), + __N32_PIN(28, APB2, C, 2), + __N32_PIN(29, APB2, C, 3), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(34, APB2, A, 0), + __N32_PIN(35, APB2, A, 1), + __N32_PIN(36, APB2, A, 2), + __N32_PIN(37, APB2, A, 3), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(40, APB2, A, 4), + __N32_PIN(41, APB2, A, 5), + __N32_PIN(42, APB2, A, 6), + __N32_PIN(43, APB2, A, 7), + __N32_PIN(44, APB2, C, 4), + __N32_PIN(45, APB2, C, 5), + __N32_PIN(46, APB2, B, 0), + __N32_PIN(47, APB2, B, 1), + __N32_PIN(48, APB2, B, 2), + __N32_PIN(49, APB2, F, 11), + __N32_PIN(50, APB2, F, 12), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(53, APB2, F, 13), + __N32_PIN(54, APB2, F, 14), + __N32_PIN(55, APB2, F, 15), + __N32_PIN(56, APB2, G, 0), + __N32_PIN(57, APB2, G, 1), + __N32_PIN(58, APB2, E, 7), + __N32_PIN(59, APB2, E, 8), + __N32_PIN(60, APB2, E, 9), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(63, APB2, E, 10), + __N32_PIN(64, APB2, E, 11), + __N32_PIN(65, APB2, E, 12), + __N32_PIN(66, APB2, E, 13), + __N32_PIN(67, APB2, E, 14), + __N32_PIN(68, APB2, E, 15), + __N32_PIN(69, APB2, B, 10), + __N32_PIN(70, APB2, B, 11), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(73, APB2, B, 12), + __N32_PIN(74, APB2, B, 13), + __N32_PIN(75, APB2, B, 14), + __N32_PIN(76, APB2, B, 15), + __N32_PIN(77, APB2, D, 8), + __N32_PIN(78, APB2, D, 9), + __N32_PIN(79, APB2, D, 10), + __N32_PIN(80, APB2, D, 11), + __N32_PIN(81, APB2, D, 12), + __N32_PIN(82, APB2, D, 13), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(85, APB2, D, 14), + __N32_PIN(86, APB2, D, 15), + __N32_PIN(87, APB2, G, 2), + __N32_PIN(88, APB2, G, 3), + __N32_PIN(89, APB2, G, 4), + __N32_PIN(90, APB2, G, 5), + __N32_PIN(91, APB2, G, 6), + __N32_PIN(92, APB2, G, 7), + __N32_PIN(93, APB2, G, 8), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(96, APB2, C, 6), + __N32_PIN(97, APB2, C, 7), + __N32_PIN(98, APB2, C, 8), + __N32_PIN(99, APB2, C, 9), + __N32_PIN(100, APB2, A, 8), + __N32_PIN(101, APB2, A, 9), + __N32_PIN(102, APB2, A, 10), + __N32_PIN(103, APB2, A, 11), + __N32_PIN(104, APB2, A, 12), + __N32_PIN(105, APB2, A, 13), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(109, APB2, A, 14), + __N32_PIN(110, APB2, A, 15), + __N32_PIN(111, APB2, C, 10), + __N32_PIN(112, APB2, C, 11), + __N32_PIN(113, APB2, C, 12), + __N32_PIN(114, APB2, D, 0), + __N32_PIN(115, APB2, D, 1), + __N32_PIN(116, APB2, D, 2), + __N32_PIN(117, APB2, D, 3), + __N32_PIN(118, APB2, D, 4), + __N32_PIN(119, APB2, D, 5), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(122, APB2, D, 6), + __N32_PIN(123, APB2, D, 7), + __N32_PIN(124, APB2, G, 9), + __N32_PIN(125, APB2, G, 10), + __N32_PIN(126, APB2, G, 11), + __N32_PIN(127, APB2, G, 12), + __N32_PIN(128, APB2, G, 13), + __N32_PIN(129, APB2, G, 14), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, + __N32_PIN(132, APB2, G, 15), + __N32_PIN(133, APB2, B, 3), + __N32_PIN(134, APB2, B, 4), + __N32_PIN(135, APB2, B, 5), + __N32_PIN(136, APB2, B, 6), + __N32_PIN(137, APB2, B, 7), + __N32_PIN_DEFAULT, + __N32_PIN(139, APB2, B, 8), + __N32_PIN(140, APB2, B, 9), + __N32_PIN(141, APB2, E, 0), + __N32_PIN(142, APB2, E, 1), + __N32_PIN_DEFAULT, + __N32_PIN_DEFAULT, +#endif +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + rt_uint32_t irqbit; + enum IRQn irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI_LINE0, EXTI0_IRQn }, + {GPIO_PIN_1, EXTI_LINE1, EXTI1_IRQn }, + {GPIO_PIN_2, EXTI_LINE2, EXTI2_IRQn }, + {GPIO_PIN_3, EXTI_LINE3, EXTI3_IRQn }, + {GPIO_PIN_4, EXTI_LINE4, EXTI4_IRQn }, + {GPIO_PIN_5, EXTI_LINE5, EXTI9_5_IRQn }, + {GPIO_PIN_6, EXTI_LINE6, EXTI9_5_IRQn }, + {GPIO_PIN_7, EXTI_LINE7, EXTI9_5_IRQn }, + {GPIO_PIN_8, EXTI_LINE8, EXTI9_5_IRQn }, + {GPIO_PIN_9, EXTI_LINE9, EXTI9_5_IRQn }, + {GPIO_PIN_10, EXTI_LINE10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI_LINE11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI_LINE12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI_LINE13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI_LINE14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI_LINE15, EXTI15_10_IRQn}, +}; +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items)/sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + if (value == PIN_LOW) + { + GPIO_ResetBits(index->gpio, index->pin); + } + else + { + GPIO_SetBits(index->gpio, index->pin); + } +} + +int n32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + + return value; +} + +void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitType GPIO_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* GPIO Periph clock enable */ + RCC_EnableAPB2PeriphClk(index->rcc, ENABLE); + + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.Pin = index->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + } + else + { + /* input setting:default. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + } + GPIO_InitPeripheral(index->gpio, &GPIO_InitStructure); +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for(i = 0; i < 32; i++) + { + if((0x01 << i) == bit) + { + return i; + } + } + return -1; +} +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if(mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; +rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if(pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args + ) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if(pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if(pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitType GPIO_InitStructure; + NVIC_InitType NVIC_InitStructure; + EXTI_InitType EXTI_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + if(enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if(pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + /* GPIO Periph clock enable */ + RCC_EnableAPB2PeriphClk(index->rcc, ENABLE); + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.Pin = index->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitPeripheral(index->gpio, &GPIO_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel= irqmap->irqno; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority= 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority= 2; + NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE; + NVIC_Init(&NVIC_InitStructure); + + GPIO_ConfigEXTILine(index->port_source, index->pin_source); + EXTI_InitStructure.EXTI_Line = irqmap->irqbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + switch(pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + } + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_InitPeripheral(&EXTI_InitStructure); + rt_hw_interrupt_enable(level); + } + else if(enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if(irqmap == RT_NULL) + { + return -RT_ENOSYS; + } + EXTI_InitStructure.EXTI_Line = irqmap->irqbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = DISABLE; + EXTI_InitPeripheral(&EXTI_InitStructure); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _n32_pin_ops = +{ + n32_pin_mode, + n32_pin_write, + n32_pin_read, + n32_pin_attach_irq, + n32_pin_dettach_irq, + n32_pin_irq_enable, +}; + +int n32_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_n32_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(n32_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + EXTI_ClrITPendBit(pin_irq_map[irqno].irqbit); + if(pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} +void EXTI0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(0); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(1); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(2); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(3); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(4); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI9_5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if(EXTI_GetITStatus(EXTI_LINE5) != RESET) + { + pin_irq_hdr(5); + } + if(EXTI_GetITStatus(EXTI_LINE6) != RESET) + { + pin_irq_hdr(6); + } + if(EXTI_GetITStatus(EXTI_LINE7) != RESET) + { + pin_irq_hdr(7); + } + if(EXTI_GetITStatus(EXTI_LINE8) != RESET) + { + pin_irq_hdr(8); + } + if(EXTI_GetITStatus(EXTI_LINE9) != RESET) + { + pin_irq_hdr(9); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI15_10_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if(EXTI_GetITStatus(EXTI_LINE10) != RESET) + { + pin_irq_hdr(10); + } + if(EXTI_GetITStatus(EXTI_LINE11) != RESET) + { + pin_irq_hdr(11); + } + if(EXTI_GetITStatus(EXTI_LINE12) != RESET) + { + pin_irq_hdr(12); + } + if(EXTI_GetITStatus(EXTI_LINE13) != RESET) + { + pin_irq_hdr(13); + } + if(EXTI_GetITStatus(EXTI_LINE14) != RESET) + { + pin_irq_hdr(14); + } + if(EXTI_GetITStatus(EXTI_LINE15) != RESET) + { + pin_irq_hdr(15); + } + /* leave interrupt */ + rt_interrupt_leave(); +} + + +#endif + diff --git a/components/libc/compilers/common/none-gcc/sys/stat.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h similarity index 64% rename from components/libc/compilers/common/none-gcc/sys/stat.h rename to bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h index c8f65df435..ae9bda7dce 100644 --- a/components/libc/compilers/common/none-gcc/sys/stat.h +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h @@ -5,9 +5,10 @@ * * Change Logs: * Date Author Notes + * 2015-01-05 Bernard the first version */ +#ifndef GPIO_H__ +#define GPIO_H__ - #ifndef __SYS_STAT_H__ - #define __SYS_STAT_H__ - #endif +#endif diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c new file mode 100644 index 0000000000..688186e920 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c @@ -0,0 +1,450 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#include +#include "drv_hwtimer.h" + +#define DRV_DEBUG +#define LOG_TAG "drv.hwtimer" +#include + +#ifdef BSP_USING_HWTIMER +enum +{ +#ifdef BSP_USING_HWTIM1 + TIM1_INDEX, +#endif + +#ifdef BSP_USING_HWTIM2 + TIM2_INDEX, +#endif + +#ifdef BSP_USING_HWTIM3 + TIM3_INDEX, +#endif + +#ifdef BSP_USING_HWTIM4 + TIM4_INDEX, +#endif + +#ifdef BSP_USING_HWTIM5 + TIM5_INDEX, +#endif + +#ifdef BSP_USING_HWTIM6 + TIM6_INDEX, +#endif + +#ifdef BSP_USING_HWTIM7 + TIM7_INDEX, +#endif + +#ifdef BSP_USING_HW_TIM8 + TIM8_INDEX, +#endif + +#ifdef BSP_USING_HWTIM9 + TIM9_INDEX, +#endif + +#ifdef BSP_USING_HWTIM10 + TIM10_INDEX, +#endif + +#ifdef BSP_USING_HWTIM11 + TIM11_INDEX, +#endif + +#ifdef BSP_USING_HWTIM12 + TIM12_INDEX, +#endif + +#ifdef BSP_USING_HWTIM13 + TIM13_INDEX, +#endif + +#ifdef BSP_USING_HWTIM14 + TIM14_INDEX, +#endif + +#ifdef BSP_USING_HWTIM15 + TIM15_INDEX, +#endif +}; + +struct n32_hwtimer +{ + rt_hwtimer_t time_device; + TIM_Module* tim_handle; + IRQn_Type tim_irqn; + char *name; +}; + +static struct n32_hwtimer n32_hwtimer_obj[] = +{ +#ifdef BSP_USING_HWTIM1 + TIM1_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM2 + TIM2_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM3 + TIM3_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM4 + TIM4_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM5 + TIM5_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM6 + TIM6_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM7 + TIM7_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM8 + TIM8_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM9 + TIM9_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM10 + TIM10_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM11 + TIM11_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM12 + TIM12_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM13 + TIM13_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM14 + TIM14_CONFIG, +#endif + +#ifdef BSP_USING_HWTIM15 + TIM15_CONFIG, +#endif +}; + +static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ + RCC_ClocksType RCC_ClockStruct; + TIM_TimeBaseInitType TIM_TimeBaseStructure; + NVIC_InitType NVIC_InitStructure; + uint32_t prescaler_value = 0; + TIM_Module *tim = RT_NULL; + struct n32_hwtimer *tim_device = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + if (state) + { + tim = (TIM_Module *)timer->parent.user_data; + tim_device = (struct n32_hwtimer *)timer; + + /* timer clock enable */ + n32_msp_hwtim_init(tim); + + /* timer init */ + RCC_GetClocksFreqValue(&RCC_ClockStruct); + /* Set timer clock is 1Mhz */ + prescaler_value = (uint32_t)(RCC_ClockStruct.SysclkFreq / 10000) - 1; + + TIM_TimeBaseStructure.Period = 10000 - 1; + rt_kprintf("Period=[%d]", TIM_TimeBaseStructure.Period); + TIM_TimeBaseStructure.Prescaler = prescaler_value; + rt_kprintf("Prescaler=[%d]", TIM_TimeBaseStructure.Prescaler); + TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseStructure.RepetCnt = 0; + + if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + { + TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP; + } + else + { + TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_DOWN; + } + + TIM_InitTimeBase(tim, &TIM_TimeBaseStructure); + + /* Enable the TIMx global Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = tim_device->tim_irqn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + TIM_ConfigInt(tim, TIM_INT_UPDATE ,ENABLE); + TIM_ClrIntPendingBit(tim, TIM_INT_UPDATE); + + LOG_D("%s init success", tim_device->name); + } +} + +static rt_err_t n32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +{ + rt_err_t result = RT_EOK; + TIM_Module *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_Module *)timer->parent.user_data; + + /* set tim cnt */ + TIM_SetCnt(tim, 0); + /* set tim arr */ + TIM_SetAutoReload(tim, t - 1); + if (opmode == HWTIMER_MODE_ONESHOT) + { + /* set timer to single mode */ + TIM_SelectOnePulseMode(tim, TIM_OPMODE_SINGLE); + } + else + { + TIM_SelectOnePulseMode(tim, TIM_OPMODE_REPET); + } + + /* start timer */ + TIM_Enable(tim, ENABLE); + + return result; +} + +static void n32_timer_stop(rt_hwtimer_t *timer) +{ + TIM_Module *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_Module *)timer->parent.user_data; + + /* stop timer */ + TIM_Enable(tim, DISABLE); + /* set tim cnt */ + TIM_SetCnt(tim, 0); +} + +static rt_uint32_t n32_timer_counter_get(rt_hwtimer_t *timer) +{ + TIM_Module *tim = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + + tim = (TIM_Module *)timer->parent.user_data; + + return tim->CNT; +} + +static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +{ + RCC_ClocksType RCC_ClockStruct; + TIM_Module *tim = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(arg != RT_NULL); + + tim = (TIM_Module *)timer->parent.user_data; + + switch(cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + rt_uint16_t val; + + /* set timer frequence */ + freq = *((rt_uint32_t *)arg); + + /* time init */ + RCC_GetClocksFreqValue(&RCC_ClockStruct); + + val = RCC_ClockStruct.SysclkFreq / freq; + + TIM_ConfigPrescaler(tim, val - 1, TIM_PSC_RELOAD_MODE_IMMEDIATE); + } + break; + default: + { + result = -RT_ENOSYS; + } + break; + } + + return result; +} + +static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_hwtimer_ops _ops = +{ + .init = n32_timer_init, + .start = n32_timer_start, + .stop = n32_timer_stop, + .count_get = n32_timer_counter_get, + .control = n32_timer_ctrl, +}; + +#ifdef BSP_USING_HWTIM2 +void TIM2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if(TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET) + { + + rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM2_INDEX].time_device); + TIM_ClrIntPendingBit(TIM2, TIM_INT_UPDATE); + + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_HWTIM3 +void TIM3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if(TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET) + { + + rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM3_INDEX].time_device); + TIM_ClrIntPendingBit(TIM3, TIM_INT_UPDATE); + + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_HWTIM4 +void TIM4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if(TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET) + { + + rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM4_INDEX].time_device); + TIM_ClrIntPendingBit(TIM4, TIM_INT_UPDATE); + + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_HWTIM5 +void TIM5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if(TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET) + { + + rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM5_INDEX].time_device); + TIM_ClrIntPendingBit(TIM5, TIM_INT_UPDATE); + + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_HWTIM6 +void TIM6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if(TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET) + { + + rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM6_INDEX].time_device); + TIM_ClrIntPendingBit(TIM6, TIM_INT_UPDATE); + + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_HWTIM7 +void TIM7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if(TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET) + { + + rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM7_INDEX].time_device); + TIM_ClrIntPendingBit(TIM7, TIM_INT_UPDATE); + + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +static int rt_hw_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(n32_hwtimer_obj) / sizeof(n32_hwtimer_obj[0]); i++) + { + n32_hwtimer_obj[i].time_device.info = &_info; + n32_hwtimer_obj[i].time_device.ops = &_ops; + if (rt_device_hwtimer_register(&n32_hwtimer_obj[i].time_device, n32_hwtimer_obj[i].name, n32_hwtimer_obj[i].tim_handle) == RT_EOK) + { + LOG_D("%s register success", n32_hwtimer_obj[i].name); + } + else + { + LOG_E("%s register failed", n32_hwtimer_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + +#endif /* BSP_USING_HWTIMER */ + + + + + + + diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h new file mode 100644 index 0000000000..ec2107a86e --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 4000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_HWTIM2 +#ifndef TIM2_CONFIG +#define TIM2_CONFIG \ + { \ + .tim_handle = TIM2, \ + .tim_irqn = TIM2_IRQn, \ + .name = "timer2", \ + } +#endif /* TIM2_CONFIG */ +#endif /* BSP_USING_HWTIM2 */ + +#ifdef BSP_USING_HWTIM3 +#ifndef TIM3_CONFIG +#define TIM3_CONFIG \ + { \ + .tim_handle = TIM3, \ + .tim_irqn = TIM3_IRQn, \ + .name = "timer3", \ + } +#endif /* TIM3_CONFIG */ +#endif /* BSP_USING_HWTIM3 */ + +#ifdef BSP_USING_HWTIM4 +#ifndef TIM4_CONFIG +#define TIM4_CONFIG \ + { \ + .tim_handle = TIM4, \ + .tim_irqn = TIM4_IRQn, \ + .name = "timer4", \ + } +#endif /* TIM4_CONFIG */ +#endif /* BSP_USING_HWTIM4 */ + +#ifdef BSP_USING_HWTIM5 +#ifndef TIM5_CONFIG +#define TIM5_CONFIG \ + { \ + .tim_handle = TIM5, \ + .tim_irqn = TIM5_IRQn, \ + .name = "timer5", \ + } +#endif /* TIM5_CONFIG */ +#endif /* BSP_USING_HWTIM5 */ + +#ifdef BSP_USING_HWTIM6 +#ifndef TIM6_CONFIG +#define TIM6_CONFIG \ + { \ + .tim_handle = TIM6, \ + .tim_irqn = TIM6_IRQn, \ + .name = "timer6", \ + } +#endif /* TIM6_CONFIG */ +#endif /* BSP_USING_HWTIM6 */ + +#ifdef BSP_USING_HWTIM7 +#ifndef TIM7_CONFIG +#define TIM7_CONFIG \ + { \ + .tim_handle = TIM7, \ + .tim_irqn = TIM7_IRQn, \ + .name = "timer7", \ + } +#endif /* TIM7_CONFIG */ +#endif /* BSP_USING_HWTIM7 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_CONFIG_H__ */ + diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_log.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_log.h new file mode 100644 index 0000000000..d91f70d37c --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-09 shelton first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c new file mode 100644 index 0000000000..f61402c9c3 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-1-13 Leo first version + */ + +#include +#include "drv_pwm.h" + +#ifdef RT_USING_PWM +#if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \ + !defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4) +#error "Please define at least one BSP_USING_TIMx_CHx" +#endif +#endif /* RT_USING_PWM */ + +#define DRV_DEBUG +#define LOG_TAG "drv.pwm" +#include + +#define MAX_PERIOD 65535 +struct rt_device_pwm pwm_device; + +struct n32_pwm +{ + struct rt_device_pwm pwm_device; + TIM_Module* tim_handle; + rt_uint8_t channel; + char *name; +}; + +static struct n32_pwm n32_pwm_obj[] = +{ +#ifdef BSP_USING_TIM3_CH1 + PWM1_TIM3_CONFIG, +#endif + +#ifdef BSP_USING_TIM3_CH2 + PWM2_TIM3_CONFIG, +#endif + +#ifdef BSP_USING_TIM3_CH3 + PWM3_TIM3_CONFIG, +#endif + +#ifdef BSP_USING_TIM3_CH4 + PWM4_TIM3_CONFIG, +#endif +}; + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); +static struct rt_pwm_ops drv_ops = +{ + drv_pwm_control +}; + +static rt_err_t drv_pwm_enable(TIM_Module* TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + /* Get the value of channel */ + rt_uint32_t channel = configuration->channel; + + if (!enable) + { + if(channel == 1) + { + TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE); + } + else if(channel == 2) + { + TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE); + } + else if(channel == 3) + { + TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE); + } + else if(channel == 4) + { + TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE); + } + } + else + { + if(channel == 1) + { + TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE); + } + else if(channel == 2) + { + TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE); + } + else if(channel == 3) + { + TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE); + } + else if(channel == 4) + { + TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE); + } + } + + TIM_Enable(TIMx, ENABLE); + + return RT_EOK; +} + +static rt_err_t drv_pwm_get(TIM_Module* TIMx, struct rt_pwm_configuration *configuration) +{ + RCC_ClocksType RCC_Clockstruct; + rt_uint32_t ar, div, cc1, cc2, cc3, cc4; + rt_uint32_t channel = configuration->channel; + rt_uint64_t tim_clock; + + ar = TIMx->AR; + div = TIMx->PSC; + cc1 = TIMx->CCDAT1; + cc2 = TIMx->CCDAT2; + cc3 = TIMx->CCDAT3; + cc4 = TIMx->CCDAT4; + + RCC_GetClocksFreqValue(&RCC_Clockstruct); + + tim_clock = RCC_Clockstruct.Pclk2Freq; + + /* Convert nanosecond to frequency and duty cycle. */ + tim_clock /= 1000000UL; + configuration->period = (ar + 1) * (div + 1) * 1000UL / tim_clock; + if(channel == 1) + configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock; + if(channel == 2) + configuration->pulse = (cc2 + 1) * (div+ 1) * 1000UL / tim_clock; + if(channel == 3) + configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock; + if(channel == 4) + configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock; + + return RT_EOK; +} + +static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *configuration) +{ + /* Init timer pin and enable clock */ + n32_msp_tim_init(TIMx); + + RCC_ClocksType RCC_Clock; + RCC_GetClocksFreqValue(&RCC_Clock); + rt_uint64_t input_clock; + if ((TIM1 == TIMx) || (TIM8 == TIMx)) + { + RCC_ConfigTim18Clk(RCC_TIM18CLK_SRC_SYSCLK); + input_clock = RCC_Clock.SysclkFreq; + } + else + { + if (1 == (RCC_Clock.HclkFreq/RCC_Clock.Pclk1Freq)) + input_clock = RCC_Clock.Pclk1Freq; + else + input_clock = RCC_Clock.Pclk1Freq * 2; + } + + /* Convert nanosecond to frequency and duty cycle. */ + rt_uint32_t period = (unsigned long long)configuration->period ; + rt_uint64_t psc = period / MAX_PERIOD + 1; + period = period / psc; + psc = psc * (input_clock / 1000000); + + /* TIMe base configuration */ + TIM_TimeBaseInitType TIM_TIMeBaseStructure; + TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure); + TIM_TIMeBaseStructure.Period = period; + TIM_TIMeBaseStructure.Prescaler = psc - 1; + TIM_TIMeBaseStructure.ClkDiv = 0; + TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP; + TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure); + + rt_uint32_t pulse = (unsigned long long)configuration->pulse; + /* PWM1 Mode configuration: Channel1 */ + OCInitType TIM_OCInitStructure; + TIM_InitOcStruct(&TIM_OCInitStructure); + TIM_OCInitStructure.OcMode = TIM_OCMODE_PWM1; + TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE; + TIM_OCInitStructure.Pulse = pulse; + TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH; + + rt_uint32_t channel = configuration->channel; + if(channel == 1) + { + TIM_InitOc1(TIMx, &TIM_OCInitStructure); + TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); + } + else if(channel == 2) + { + TIM_InitOc2(TIMx, &TIM_OCInitStructure); + TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); + } + else if(channel == 3) + { + TIM_InitOc3(TIMx, &TIM_OCInitStructure); + TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); + } + else if(channel == 4) + { + TIM_InitOc4(TIMx, &TIM_OCInitStructure); + TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE); + } + + TIM_ConfigArPreload(TIMx, ENABLE); + TIM_EnableCtrlPwmOutputs(TIMx, ENABLE); + + return RT_EOK; +} + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + TIM_Module *TIMx = (TIM_Module *)device->parent.user_data; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return drv_pwm_enable(TIMx, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable(TIMx, configuration, RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set(TIMx, configuration); + case PWM_CMD_GET: + return drv_pwm_get(TIMx, configuration); + default: + return RT_EINVAL; + } +} + +static int rt_hw_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + for(i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++) + { + if(rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK) + { + LOG_D("%s register success", n32_pwm_obj[i].name); + } + else + { + LOG_D("%s register failed", n32_pwm_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pwm_init); diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.h new file mode 100644 index 0000000000..489b37166f --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-1-13 Leo first version + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TIM3_CH1 +#ifndef PWM1_TIM3_CONFIG +#define PWM1_TIM3_CONFIG \ + { \ + .tim_handle = TIM3, \ + .name = "tim3pwm1", \ + .channel = 1 \ + } +#endif /* PWM1_TIM3_CONFIG */ +#endif /* BSP_USING_TIM3_CH1 */ + +#ifdef BSP_USING_TIM3_CH2 +#ifndef PWM2_TIM3_CONFIG +#define PWM2_TIM3_CONFIG \ + { \ + .tim_handle = TIM3, \ + .name = "tim3pwm2", \ + .channel = 2 \ + } +#endif /* PWM2_TIM3_CONFIG */ +#endif /* BSP_USING_TIM3_CH2 */ + +#ifdef BSP_USING_TIM3_CH3 +#ifndef PWM3_TIM3_CONFIG +#define PWM3_TIM3_CONFIG \ + { \ + .tim_handle = TIM3, \ + .name = "tim3pwm3", \ + .channel = 3 \ + } +#endif /* PWM3_TIM3_CONFIG */ +#endif /* BSP_USING_TIM3_CH3 */ + +#ifdef BSP_USING_TIM3_CH4 +#ifndef PWM4_TIM3_CONFIG +#define PWM4_TIM3_CONFIG \ + { \ + .tim_handle = TIM3, \ + .name = "tim3pwm4", \ + .channel = 4 \ + } +#endif /* PWM4_TIM3_CONFIG */ +#endif /* BSP_USING_TIM3_CH4 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..0b49dba5d7 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-09 shelton first version + */ + +#include +#include "drv_soft_i2c.h" + +#ifdef RT_USING_I2C + +#define LOG_TAG "drv.i2c" +#include + +#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) +#error "Please define at least one BSP_USING_I2Cx" +/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ +#endif + +static const struct n32_soft_i2c_config soft_i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C4 + I2C4_BUS_CONFIG, +#endif +}; + +static struct n32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; + +/** + * This function initializes the i2c pin. + * + * @param n32 i2c dirver class. + */ +static void n32_i2c_gpio_init(struct n32_i2c *i2c) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)i2c->ops.data; + + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param n32 config class. + * @param The sda pin state. + */ +static void n32_set_sda(void *data, rt_int32_t state) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + if (state) + { + rt_pin_write(cfg->sda, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param n32 config class. + * @param The scl pin state. + */ +static void n32_set_scl(void *data, rt_int32_t state) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + if (state) + { + rt_pin_write(cfg->scl, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t n32_get_sda(void *data) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t n32_get_scl(void *data) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + return rt_pin_read(cfg->scl); +} +/** + * The time delay function. + * + * @param microseconds. + */ +static void n32_udelay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +static const struct rt_i2c_bit_ops n32_bit_ops_default = +{ + .data = RT_NULL, + .set_sda = n32_set_sda, + .set_scl = n32_set_scl, + .get_sda = n32_get_sda, + .get_scl = n32_get_scl, + .udelay = n32_udelay, + .delay_us = 1, + .timeout = 100 +}; + +/** + * if i2c is locked, this function will unlock it + * + * @param n32 config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t n32_i2c_bus_unlock(const struct n32_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl, PIN_HIGH); + n32_udelay(100); + rt_pin_write(cfg->scl, PIN_LOW); + n32_udelay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/* I2C initialization function */ +int rt_hw_i2c_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct n32_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + i2c_obj[i].ops = n32_bit_ops_default; + i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; + i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; + n32_i2c_gpio_init(&i2c_obj[i]); + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); + RT_ASSERT(result == RT_EOK); + n32_i2c_bus_unlock(&soft_i2c_config[i]); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, + soft_i2c_config[i].sda); + } + + return RT_EOK; +} + +INIT_BOARD_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.h new file mode 100644 index 0000000000..af501c3e19 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-09 shelton first version + */ + +#ifndef __DRV_I2C__ +#define __DRV_I2C__ + +#include +#include +#include + +/* n32 config class */ +struct n32_soft_i2c_config +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *bus_name; +}; +/* n32 i2c dirver class */ +struct n32_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c_bus; +}; + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .scl = BSP_I2C1_SCL_PIN, \ + .sda = BSP_I2C1_SDA_PIN, \ + .bus_name = "i2c1", \ + } +#endif + +#ifdef BSP_USING_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .scl = BSP_I2C2_SCL_PIN, \ + .sda = BSP_I2C2_SDA_PIN, \ + .bus_name = "i2c2", \ + } +#endif + +#ifdef BSP_USING_I2C3 +#define I2C3_BUS_CONFIG \ + { \ + .scl = BSP_I2C3_SCL_PIN, \ + .sda = BSP_I2C3_SDA_PIN, \ + .bus_name = "i2c3", \ + } +#endif + +#ifdef BSP_USING_I2C4 +#define I2C4_BUS_CONFIG \ + { \ + .scl = BSP_I2C4_SCL_PIN, \ + .sda = BSP_I2C4_SDA_PIN, \ + .bus_name = "i2c4", \ + } +#endif +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c new file mode 100644 index 0000000000..b39298b9a0 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c @@ -0,0 +1,558 @@ +/* + * File : usart.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + * 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode + * 2013-05-13 aozima update for kehong-lingtai. + * 2015-01-31 armink make sure the serial transmit complete in putc() + * 2016-05-13 armink add DMA Rx mode + * 2017-01-19 aubr.cool add interrupt Tx mode + * 2017-04-13 aubr.cool correct Rx parity err + * 2021-08-20 breo.com first version + */ + +#include +#include +#include +#include "drv_usart.h" + +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +struct n32_uart +{ + USART_Module *uart_device; + IRQn_Type irq; + struct n32_uart_dma + { + /* dma channel */ + DMA_ChannelType *rx_ch; + DMA_Module *rx_dma_type; + /* dma global flag */ + uint32_t rx_gl_flag; + /* dma irq channel */ + uint8_t rx_irq_ch; + /* setting receive len */ + rt_size_t setting_recv_len; + /* last receive index */ + rt_size_t last_recv_index; + } dma; +}; + +static void DMA_Configuration(struct rt_serial_device *serial); + +static rt_err_t n32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct n32_uart* uart; + USART_InitType USART_InitStructure; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = (struct n32_uart *)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + RT_ASSERT((uart->uart_device) != RT_NULL); + n32_msp_usart_init(uart->uart_device); + + USART_InitStructure.BaudRate = cfg->baud_rate; + + if (cfg->data_bits == DATA_BITS_8) + { + USART_InitStructure.WordLength = USART_WL_8B; + } + else if (cfg->data_bits == DATA_BITS_9) + { + USART_InitStructure.WordLength = USART_WL_9B; + } + + if (cfg->stop_bits == STOP_BITS_1) + { + USART_InitStructure.StopBits = USART_STPB_1; + } + else if (cfg->stop_bits == STOP_BITS_2) + { + USART_InitStructure.StopBits = USART_STPB_2; + } + + if (cfg->parity == PARITY_NONE) + { + USART_InitStructure.Parity = USART_PE_NO; + } + else if (cfg->parity == PARITY_ODD) + { + USART_InitStructure.Parity = USART_PE_ODD; + } + else if (cfg->parity == PARITY_EVEN) + { + USART_InitStructure.Parity = USART_PE_EVEN; + } + + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_Init(uart->uart_device, &USART_InitStructure); + + /* Enable USART */ + USART_Enable(uart->uart_device, ENABLE); + + USART_ClrFlag(uart->uart_device, USART_FLAG_TXDE|USART_FLAG_TXC); + + return RT_EOK; +} + +static rt_err_t n32_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct n32_uart* uart; + rt_uint32_t ctrl_arg = (rt_uint32_t)(arg); + + RT_ASSERT(serial != RT_NULL); + uart = (struct n32_uart *)serial->parent.user_data; + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->irq); + /* disable interrupt */ + USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, DISABLE); + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->irq); + /* enable interrupt */ + USART_ConfigInt(uart->uart_device, USART_INT_RXDNE, ENABLE); + break; + /* USART config */ + case RT_DEVICE_CTRL_CONFIG : + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { + DMA_Configuration(serial); + } + break; + } + return RT_EOK; +} + +static int n32_uart_putc(struct rt_serial_device *serial, char c) +{ + struct n32_uart* uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct n32_uart *)serial->parent.user_data; + + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + if (!(uart->uart_device->STS & USART_FLAG_TXDE)) + { + USART_ConfigInt(uart->uart_device, USART_INT_TXC, ENABLE); + return -1; + } + uart->uart_device->DAT = c; + USART_ConfigInt(uart->uart_device, USART_INT_TXC, ENABLE); + } + else + { + uart->uart_device->DAT = c; + while (!(uart->uart_device->STS & USART_FLAG_TXC)); + } + + return 1; +} + +static int n32_uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct n32_uart* uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct n32_uart *)serial->parent.user_data; + + ch = -1; + if (uart->uart_device->STS & USART_FLAG_RXDNE) + { + ch = uart->uart_device->DAT & 0xff; + } + + return ch; +} + +/** + * Serial port receive idle process. This need add to uart idle ISR. + * + * @param serial serial device + */ +static void dma_uart_rx_idle_isr(struct rt_serial_device *serial) +{ + struct n32_uart *uart = (struct n32_uart *) serial->parent.user_data; + rt_size_t recv_total_index, recv_len; + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + recv_total_index = uart->dma.setting_recv_len - DMA_GetCurrDataCounter(uart->dma.rx_ch); + recv_len = recv_total_index - uart->dma.last_recv_index; + uart->dma.last_recv_index = recv_total_index; + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (recv_len) + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + + /* read a data for clear receive idle interrupt flag */ + USART_ReceiveData(uart->uart_device); + DMA_ClearFlag(uart->dma.rx_gl_flag, uart->dma.rx_dma_type); +} + +/** + * DMA receive done process. This need add to DMA receive done ISR. + * + * @param serial serial device + */ +static void dma_rx_done_isr(struct rt_serial_device *serial) +{ + struct n32_uart *uart = (struct n32_uart *) serial->parent.user_data; + rt_size_t recv_len; + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + recv_len = uart->dma.setting_recv_len - uart->dma.last_recv_index; + /* reset last recv index */ + uart->dma.last_recv_index = 0; + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (recv_len) + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + + DMA_ClearFlag(uart->dma.rx_gl_flag, uart->dma.rx_dma_type); +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct n32_uart *uart = (struct n32_uart *) serial->parent.user_data; + + RT_ASSERT(uart != RT_NULL); + + if(USART_GetIntStatus(uart->uart_device, USART_INT_RXDNE) != RESET) + { + if(USART_GetFlagStatus(uart->uart_device, USART_FLAG_PEF) == RESET) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + /* clear interrupt */ + USART_ClrIntPendingBit(uart->uart_device, USART_INT_RXDNE); + } + if(USART_GetIntStatus(uart->uart_device, USART_INT_IDLEF) != RESET) + { + dma_uart_rx_idle_isr(serial); + } + if (USART_GetIntStatus(uart->uart_device, USART_INT_TXC) != RESET) + { + /* clear interrupt */ + if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + USART_ConfigInt(uart->uart_device, USART_INT_TXC, DISABLE); + USART_ClrIntPendingBit(uart->uart_device, USART_INT_TXC); + } + if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_OREF) == SET) + { + n32_uart_getc(serial); + } +} + +static const struct rt_uart_ops n32_uart_ops = +{ + n32_uart_configure, + n32_uart_control, + n32_uart_putc, + n32_uart_getc, +}; + +#if defined(BSP_USING_UART1) +/* UART1 device driver structure */ +struct n32_uart uart1 = +{ + USART1, + USART1_IRQn, + { + DMA1_CH5, + DMA1, + DMA1_FLAG_GL5, + DMA1_Channel5_IRQn, + 0, + }, +}; +struct rt_serial_device serial1; + +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DMA1_Channel5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_rx_done_isr(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +/* UART2 device driver structure */ +struct n32_uart uart2 = +{ + USART2, + USART2_IRQn, + { + DMA1_CH6, + DMA1, + DMA1_FLAG_GL6, + DMA1_Channel6_IRQn, + 0, + }, +}; +struct rt_serial_device serial2; + +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DMA1_Channel6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_rx_done_isr(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +/* UART3 device driver structure */ +struct n32_uart uart3 = +{ + USART3, + USART3_IRQn, + { + DMA1_CH3, + DMA1, + DMA1_FLAG_GL3, + DMA1_Channel3_IRQn, + 0, + }, +}; +struct rt_serial_device serial3; + +void USART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial3); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DMA1_Channel3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_rx_done_isr(&serial3); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +/* UART4 device driver structure */ +struct n32_uart uart4 = +{ + UART4, + UART4_IRQn, + { + DMA2_CH3, + DMA2, + DMA2_FLAG_GL3, + DMA2_Channel3_IRQn, + 0, + }, +}; +struct rt_serial_device serial4; + +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial4); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void DMA2_Channel3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_rx_done_isr(&serial4); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +static void NVIC_Configuration(struct n32_uart* uart) +{ + NVIC_InitType NVIC_InitStructure; + + /* Enable the USART1 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = uart->irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +static void DMA_Configuration(struct rt_serial_device *serial) +{ + struct n32_uart *uart = (struct n32_uart *) serial->parent.user_data; + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + DMA_InitType DMA_InitStructure; + NVIC_InitType NVIC_InitStructure; + + uart->dma.setting_recv_len = serial->config.bufsz; + + /* enable transmit idle interrupt */ + USART_ConfigInt(uart->uart_device, USART_INT_IDLEF, ENABLE); + + /* DMA clock enable */ + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_DMA1, ENABLE); + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_DMA2, ENABLE); + + /* rx dma config */ + DMA_DeInit(uart->dma.rx_ch); + DMA_InitStructure.PeriphAddr = (uint32_t)&(uart->uart_device->DAT); + DMA_InitStructure.MemAddr = (uint32_t)(rx_fifo->buffer); + DMA_InitStructure.Direction = DMA_DIR_PERIPH_SRC; + DMA_InitStructure.BufSize = serial->config.bufsz; + DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE; + DMA_InitStructure.DMA_MemoryInc = DMA_MEM_INC_ENABLE; + DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + DMA_InitStructure.MemDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.CircularMode = DMA_MODE_CIRCULAR; + DMA_InitStructure.Priority = DMA_PRIORITY_HIGH; + DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE; + DMA_Init(uart->dma.rx_ch, &DMA_InitStructure); + DMA_ClearFlag(uart->dma.rx_gl_flag, uart->dma.rx_dma_type); + DMA_ConfigInt(uart->dma.rx_ch, DMA_INT_TXC, ENABLE); + USART_EnableDMA(uart->uart_device, USART_DMAREQ_RX, ENABLE); + DMA_EnableChannel(uart->dma.rx_ch, ENABLE); + + /* rx dma interrupt config */ + NVIC_InitStructure.NVIC_IRQChannel = uart->dma.rx_irq_ch; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +int rt_hw_usart_init(void) +{ + struct n32_uart* uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#if defined(BSP_USING_UART1) + uart = &uart1; + config.baud_rate = BAUD_RATE_115200; + + serial1.ops = &n32_uart_ops; + serial1.config = config; + + NVIC_Configuration(uart); + + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX, + uart); +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) + uart = &uart2; + + config.baud_rate = BAUD_RATE_115200; + serial2.ops = &n32_uart_ops; + serial2.config = config; + + NVIC_Configuration(uart); + + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX, + uart); +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) + uart = &uart3; + + config.baud_rate = BAUD_RATE_115200; + + serial3.ops = &n32_uart_ops; + serial3.config = config; + + NVIC_Configuration(uart); + + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX, + uart); +#endif /* BSP_USING_UART3 */ + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_usart_init); + diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h new file mode 100644 index 0000000000..4059092706 --- /dev/null +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + */ + +#ifndef __USART_H__ +#define __USART_H__ + + +#endif diff --git a/bsp/n32g452xx/n32g452xx-mini-system/.config b/bsp/n32g452xx/n32g452xx-mini-system/.config new file mode 100644 index 0000000000..4dc7a24334 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/.config @@ -0,0 +1,586 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_N32G452XX=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_RT_USING_GPIO=y +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_PWM=y +CONFIG_BSP_USING_TIM3=y +CONFIG_BSP_USING_TIM3_CH1=y +CONFIG_BSP_USING_TIM3_CH2=y +CONFIG_BSP_USING_TIM3_CH3=y +CONFIG_BSP_USING_TIM3_CH4=y +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_SDIO is not set diff --git a/bsp/n32g452xx/n32g452xx-mini-system/Kconfig b/bsp/n32g452xx/n32g452xx-mini-system/Kconfig new file mode 100755 index 0000000000..4645aae1e0 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/Kconfig @@ -0,0 +1,20 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" diff --git a/bsp/n32g452xx/n32g452xx-mini-system/README.md b/bsp/n32g452xx/n32g452xx-mini-system/README.md new file mode 100644 index 0000000000..68bd5b3d7e --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/README.md @@ -0,0 +1,116 @@ +# N32G452XX MINI-SYSTEM BSP 说明 + +## 简介 + +N32G452 MINI-SYSTEM 是国民技术推出的一款N32G452系列的评估板(目前市面还没有，以后也可能不会有)，其搭载的MCU主要资源参数如下： + +| 硬件 | 描述 | +| --------- | ------------- | +| 芯片型号 | N32G452RCL7 | +| CPU | ARM Cortex M4 | +| 主频 | 144M | +| 片内SRAM | 80K可扩展144K | +| 片内FLASH | 256K | + +## 编译说明 + +N32G452 MINI-SYSTEM 板级包支持MDK5开发环境和GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------------------------- | +| MDK5 | MDK533 | +| GCC | GCC 6.2.1 20161205 (release) | + +## 板载资源 + +- MCU：N32G452RCL7，主频 144MHz，256KB FLASH ，80KB可扩展到144KB RAM +- 常用接口：插针串口J8 +- 调试接口，JLINK、板载的 NS-LINK SWD 下载 + +## 外设支持 + +本 BSP 目前对外设驱动的支持情况如下： + +| 驱动 | 支持情况 | 备注 | +| --------- | -------- | :------------------------: | +| UART | 支持(已移植，已测试) | USART1/2/3 | +| GPIO | 支持(已移植，已测试) | PA0...PF7 | +| ADC | 支持(已移植，已测试) | ADC1/2 | +| PWM | 支持(已移植，已测试) | TMR1/2 | +| HWTIMER | 支持(已移植，已测试) | TMR6/7 | + +### IO在板级支持包中的映射情况 + +| IO号 | 板级包中的定义 | +| ---- | -------------- | +| PA9 | USART1_TX | +| PA10 | USART1_RX | +| PA2 | USART2_TX | +| PA3 | USART2_RX | +| PB10 | USART3_TX | +| PB11 | USART3_RX | +| PA4 | SPI1_NSS | +| PA5 | SPI1_SCK | +| PA6 | SPI1_MISO | +| PA7 | SPI1_MOSI | +| PB12 | SPI2_NSS | +| PB13 | SPI2_SCK | +| PB14 | SPI2_MISO | +| PB15 | SPI2_MOSI | +| PB6 | I2C1_SCL | +| PB7 | I2C1_SDA | +| PC8 | SDIO1_D0 | +| PC9 | SDIO1_D1 | +| PC10 | SDIO1_D2 | +| PC11 | SDIO1_D3 | +| PC12 | SDIO1_CK | +| PD2 | SDIO1_CMD | +| PA8 | PWM_TMR1_CH1 | +| PA11 | PWM_TMR1_CH4 | +| PA0 | PWM_TMR2_CH1 | +| PA1 | PWM_TMR2_CH2 | +| PC0 | ADC1/2_IN10 | +| PC1 | ADC1/2_IN11 | +| PC2 | ADC1/2_IN12 | +| PC3 | ADC1/2_IN13 | + +## 使用说明 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1 会周期性闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，在串口上可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Aug 19 2021 + 2006 - 2021 Copyright by rt-thread team +msh /> +``` + +## 注意事项 + +1. 使用 J-LINK 下载时，请设置下载完成自动复位（J-Flash设置步骤：`Options->Project settings->production->Start application`），否则下载完成后手动按键复位无法启动，初步定位问题原因为：芯片下电缓慢，参考《N32G43x系列芯片电源系统设计指南》或联系FAE了解情况。 + +## 联系人信息 + +维护人: + +- [LinYuanbo](https://github.com/Lim-LinYuanbo) +- [breo.com](https://github.com/breo-shenzhen) diff --git a/bsp/n32g452xx/n32g452xx-mini-system/SConscript b/bsp/n32g452xx/n32g452xx-mini-system/SConscript new file mode 100755 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/n32g452xx/n32g452xx-mini-system/SConstruct b/bsp/n32g452xx/n32g452xx-mini-system/SConstruct new file mode 100755 index 0000000000..f9dc643e92 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/SConstruct @@ -0,0 +1,62 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +print('SDK_ROOT=[%s]' %(SDK_ROOT)) + +if os.path.exists(SDK_ROOT + '/Libraries'): + libraries_path_prefix = SDK_ROOT + '/Libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries' +print('libraries_path_prefix=[%s]' %(libraries_path_prefix)) + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') +print('SDK_LIB=[%s]' %(SDK_LIB)) + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +n32_library = 'N32_Std_Driver' +rtconfig.BSP_LIBRARY_TYPE = n32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, n32_library, 'SConscript'))) + +# common include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'rt_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/n32g452xx/n32g452xx-mini-system/applications/SConscript b/bsp/n32g452xx/n32g452xx-mini-system/applications/SConscript new file mode 100755 index 0000000000..e08e694faf --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/n32g452xx/n32g452xx-mini-system/applications/main.c b/bsp/n32g452xx/n32g452xx-mini-system/applications/main.c new file mode 100644 index 0000000000..1807819992 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2015-07-29 Arda.Fu first implementation + */ +#include +#include + +/* defined the LED1 pin: PB5 */ +#define LED1_PIN 57 + +int main(void) +{ + uint32_t Speed = 200; + /* set LED1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_mdelay(Speed); + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_thread_mdelay(Speed); + } +} + diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig b/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig new file mode 100755 index 0000000000..8a4e0749d8 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig @@ -0,0 +1,162 @@ +menu "Hardware Drivers Config" + +config SOC_N32G452XX + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config RT_USING_SERIAL + bool "Enable USART (uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + default y + +endmenu + +menu "On-chip Peripheral Drivers" + + config RT_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_TIM3 + bool "Enable timer3 output PWM" + default n + if BSP_USING_TIM3 + config BSP_USING_TIM3_CH1 + bool "Enable TIM3 channel1 PWM" + default n + config BSP_USING_TIM3_CH2 + bool "Enable TIM3 channel2 PWM" + default n + config BSP_USING_TIM3_CH3 + bool "Enable TIM3 channel3 PWM" + default n + config BSP_USING_TIM3_CH4 + bool "Enable TIM3 channel4 PWM" + default n + endif + endif + + menuconfig BSP_USING_HWTIMER + bool "Enable HWTIMER" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_HWTIM3 + bool "Enable hardware timer3" + default n + config BSP_USING_HWTIM4 + bool "Enable hardware timer4" + default n + config BSP_USING_HWTIM5 + bool "Enable hardware timer5" + default n + config BSP_USING_HWTIM6 + bool "Enable hardware timer6" + default n + config BSP_USING_HWTIM7 + bool "Enable hardware timer7" + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 63 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 63 + default 23 + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using CAN1" + default n + config BSP_USING_CAN2 + bool "using CAN2" + default n + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default n + select RT_USING_SDIO + if BSP_USING_SDIO + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default n + endif +endmenu + +endmenu diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/SConscript b/bsp/n32g452xx/n32g452xx-mini-system/board/SConscript new file mode 100755 index 0000000000..5c446528c0 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/SConscript @@ -0,0 +1,27 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +msp/n32_msp.c +''') + +path = [cwd] +path += [cwd + '/msp'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/N32_Std_Driver/CMSIS/device/startup/startup_n32g45x_gcc.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/N32_Std_Driver/CMSIS/device/startup/startup_n32g45x.s'] + +CPPDEFINES = ['N32G45X'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/board.c b/bsp/n32g452xx/n32g452xx-mini-system/board/board.c new file mode 100644 index 0000000000..4405e28941 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/board.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 balanceTWK first version + */ + +#include +#include +#include + +#include + +#ifdef BSP_USING_SRAM +#include "drv_sram.h" +#endif +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial N32 board. + */ +void rt_hw_board_init() +{ + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); +#endif + + SystemClock_Config(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef BSP_USING_SRAM + rt_system_heap_init((void *)EXT_SRAM_BEGIN, (void *)EXT_SRAM_END); +#else + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +} diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/board.h b/bsp/n32g452xx/n32g452xx-mini-system/board/board.h new file mode 100644 index 0000000000..71f5ca48a0 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/board.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "n32_msp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Just only support for N32G452XX */ +#define N32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define FLASH_PAGE_SIZE (2 * 1024) +#define N32_FLASH_SIZE (256 * 1024) +#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <80>, Default: 80*/ +#define N32_SRAM_SIZE (80) +#define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END N32_SRAM_END + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds b/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds new file mode 100755 index 0000000000..0865f58953 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for N32G452xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 64KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.sct b/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.sct new file mode 100755 index 0000000000..b5a41c14f4 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00040000 { ; load region size_region + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00014000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c new file mode 100644 index 0000000000..09d2dd80bb --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c @@ -0,0 +1,520 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 breo.com first version + */ + + +#include +#include +#include "n32g45x.h" +#include "n32_msp.h" + +#ifdef BSP_USING_UART +void n32_msp_usart_init(void *Instance) +{ + GPIO_InitType GPIO_InitCtlStruct; + USART_Module *USARTx = (USART_Module *)Instance; + + GPIO_InitStruct(&GPIO_InitCtlStruct); + GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; +#ifdef BSP_USING_UART1 + if(USART1 == USARTx) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_9; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitCtlStruct.Pin = GPIO_PIN_10; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + } +#endif +#ifdef BSP_USING_UART2 + if(USART2 == USARTx) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_2; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitCtlStruct.Pin = GPIO_PIN_3; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + } +#endif +#ifdef BSP_USING_UART3 + if(USART3 == USARTx) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_10; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitCtlStruct.Pin = GPIO_PIN_11; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + } +#endif +#ifdef BSP_USING_UART4 + if(UART4 == USARTx) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_10; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitCtlStruct.Pin = GPIO_PIN_11; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + } +#endif + /* Add others */ +} +#endif /* BSP_USING_SERIAL */ + +#ifdef BSP_USING_SPI +void n32_msp_spi_init(void *Instance) +{ + GPIO_InitType GPIO_InitCtlStruct; + SPI_Module *SPIx = (SPI_Module *)Instance; + + GPIO_InitStruct(&GPIO_InitCtlStruct); + GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; +#ifdef BSP_USING_SPI1 + if(SPI1 == SPIx) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_4; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_5 | GPIO_PIN_7; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitCtlStruct.Pin = GPIO_PIN_6; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + } +#endif +#ifdef BSP_USING_SPI2 + if(SPI2 == SPIx) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_12; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_13 | GPIO_PIN_15; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitCtlStruct.Pin = GPIO_PIN_14; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + } +#endif + /* Add others */ +} +#endif /* BSP_USING_SPI */ + +#ifdef BSP_USING_SDIO +void n32_msp_sdio_init(void *Instance) +{ + GPIO_InitType GPIO_InitCtlStructure; + SDIO_Module *SDIOx = (SDIO_Module *)Instance; + + GPIO_InitStruct(&GPIO_InitCtlStructure); + GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz; + + if(SDIO == SDIOx) + { + /* if used dma ... */ + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_DMA2, ENABLE); + + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_SDIO, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_GPIOD, ENABLE); + GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStructure); + + GPIO_InitCtlStructure.Pin = GPIO_PIN_2; + GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStructure); + } +} +#endif /* BSP_USING_SDIO */ + +#ifdef BSP_USING_PWM +void n32_msp_tim_init(void *Instance) +{ + GPIO_InitType GPIO_InitCtlStructure; + GPIO_InitStruct(&GPIO_InitCtlStructure); + TIM_Module *TIMx = (TIM_Module *)Instance; + + if(TIMx == TIM1) + { + /* TIM1 clock enable */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE); + /* GPIOA clock enable */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + + /* GPIOA Configuration:TIM1 Channel1 and Channel4 as alternate function push-pull */ + GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_11; + GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz; + + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure); + } + + if(TIMx == TIM2) + { + /* TIM2 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE); + /* GPIOA clock enable */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + + /* GPIOA Configuration:TIM2 Channel1 and Channel2 as alternate function push-pull */ + GPIO_InitCtlStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1; + GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz; + + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure); + } + + if(TIMx == TIM3) + { + /* TIM3 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); + /* GPIOA clock enable */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA|RCC_APB2_PERIPH_GPIOB, ENABLE); + + GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure); + + GPIO_InitCtlStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStructure); + } +} +#endif /* BSP_USING_PWM */ + +#ifdef BSP_USING_ADC +void n32_msp_adc_init(void *Instance) +{ + GPIO_InitType GPIO_InitCtlStruct; + GPIO_InitStruct(&GPIO_InitCtlStruct); + ADC_Module *ADCx = (ADC_Module *)Instance; + +#ifdef BSP_USING_ADC1 + if(ADCx == ADC1) + { + /* ADC1 & GPIO clock enable */ + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE); + ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB,RCC_ADCHCLK_DIV8); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); + + /* Configure ADC Channel as analog input */ + GPIO_InitCtlStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN; + GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct); + } +#endif + +#ifdef BSP_USING_ADC2 + if(ADCx == ADC2) + { + /* ADC2 & GPIO clock enable */ + RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE); + ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB,RCC_ADCHCLK_DIV8); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); + + /* Configure ADC Channel as analog input */ + GPIO_InitCtlStruct.Pin = GPIO_PIN_1; + GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN; + GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct); + } +#endif +} +#endif /* BSP_USING_ADC */ + +#ifdef BSP_USING_HWTIMER +void n32_msp_hwtim_init(void *Instance) +{ + TIM_Module *TIMx = (TIM_Module *)Instance; + +#ifdef BSP_USING_HWTIM3 + if(TIMx == TIM3) + { + /* TIM3 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); + } +#endif + +#ifdef BSP_USING_HWTIM4 + if(TIMx == TIM4) + { + /* TIM4 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE); + } +#endif + +#ifdef BSP_USING_HWTIM5 + if(TIMx == TIM5) + { + /* TIM5 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE); + } +#endif + +#ifdef BSP_USING_HWTIM6 + if(TIMx == TIM6) + { + /* TIM6 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE); + } +#endif + +#ifdef BSP_USING_HWTIM7 + if(TIMx == TIM7) + { + /* TIM7 clock enable */ + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE); + } +#endif +} +#endif + +#ifdef BSP_USING_CAN +void n32_msp_can_init(void *Instance) +{ + GPIO_InitType GPIO_InitCtlStruct; + CAN_Module *CANx = (CAN_Module *)Instance; + + GPIO_InitStruct(&GPIO_InitCtlStruct); + GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz; +#ifdef BSP_USING_CAN1 + if(CAN1 == CANx) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN1, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_12; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitCtlStruct.Pin = GPIO_PIN_11; + GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct); + } +#endif +#ifdef BSP_USING_CAN2 + if(CAN2 == CANx) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + // GPIO_PinsRemapConfig(AFIO_MAP6_CAN2_0001, ENABLE); + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitCtlStruct.Pin = GPIO_PIN_6; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + + GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitCtlStruct.Pin = GPIO_PIN_5; + GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct); + } +#endif +} +#endif /* BSP_USING_CAN */ + +#ifdef RT_USING_FINSH +#include +#if defined(BSP_USING_UART2) || defined(BSP_USING_UART3) +static void uart_test_rw(rt_device_t uartx, const char *name) +{ + if (uartx == NULL) + { + uartx = rt_device_find(name); + rt_err_t err = rt_device_open(uartx, RT_DEVICE_FLAG_INT_RX|RT_DEVICE_FLAG_DMA_RX); + RT_ASSERT(err == RT_EOK); + } + rt_device_write(uartx, 0, name, strlen(name)); + rt_device_write(uartx, 0, "\r\n", 2); + uint8_t recv_buf[64] = {0x0}; + int ret = rt_device_read(uartx, 0, recv_buf, sizeof(recv_buf)); + if (ret != 0) + { + for (int i=0; iparent.name); + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} +static int hwtimer_init(const char *name) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; + rt_device_t hw_dev = RT_NULL; + rt_hwtimer_mode_t mode; + hw_dev = rt_device_find(name); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", name); + return RT_ERROR; + } + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", name); + return ret; + } + rt_device_set_rx_indicate(hw_dev, timeout_cb); + mode = HWTIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + timeout_s.sec = 5; + timeout_s.usec = 0; + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return RT_ERROR; + } + + rt_thread_mdelay(3500); + + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} + +static int hwtimer_sample(int argc, char *argv[]) +{ +#ifdef BSP_USING_HWTIM6 + hwtimer_init("timer6"); +#endif +#ifdef BSP_USING_HWTIM7 + hwtimer_init("timer7"); +#endif + return RT_EOK; +} +MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +#endif + +#ifdef RT_USING_PWM +static int pwm_set_test(const char *name, int ch, + rt_uint32_t period, rt_uint32_t pulse) +{ + struct rt_device_pwm *pwm_dev = (struct rt_device_pwm *)rt_device_find(name); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", name); + return RT_ERROR; + } + rt_pwm_set(pwm_dev, ch, period, pulse); + rt_pwm_enable(pwm_dev, ch); + return RT_EOK; +} +#define PWM_TEST_NAME_CH_1 "tim3pwm1" +#define PWM_TEST_NAME_CH_2 "tim3pwm2" +#define PWM_TEST_NAME_CH_3 "tim3pwm3" +#define PWM_TEST_NAME_CH_4 "tim3pwm4" +static int pwm_led_sample(int argc, char *argv[]) +{ + pwm_set_test(PWM_TEST_NAME_CH_1, 1, 1000, 200); + pwm_set_test(PWM_TEST_NAME_CH_2, 2, 1000, 400); + pwm_set_test(PWM_TEST_NAME_CH_3, 3, 1000, 600); + pwm_set_test(PWM_TEST_NAME_CH_4, 4, 1000, 700); + return RT_EOK; +} +MSH_CMD_EXPORT(pwm_led_sample, pwm sample); +static int pwm_led_sample_off(int argc, char *argv[]) +{ + struct rt_device_pwm *pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_TEST_NAME_CH_1); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_TEST_NAME_CH_1); + return RT_ERROR; + } + rt_pwm_disable(pwm_dev, 1); + return RT_EOK; +} +MSH_CMD_EXPORT(pwm_led_sample_off, pwm sample off); +#endif + +#endif + + diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h new file mode 100644 index 0000000000..b92c62a69f --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-13 shelton first version + */ + +#ifndef __N32_MSP_H__ +#define __N32_MSP_H__ + +void n32_msp_usart_init(void *Instance); +void n32_msp_spi_init(void *Instance); +void n32_msp_tim_init(void *Instance); +void n32_msp_sdio_init(void *Instance); +void n32_msp_adc_init(void *Instance); +void n32_msp_hwtim_init(void *Instance); +void n32_msp_can_init(void *Instance); + +#endif /* __N32_MSP_H__ */ + diff --git a/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h new file mode 100644 index 0000000000..dc79897be9 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h @@ -0,0 +1,188 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_PWM + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define SOC_N32G452XX + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define RT_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_USING_PWM +#define BSP_USING_TIM3 +#define BSP_USING_TIM3_CH1 +#define BSP_USING_TIM3_CH2 +#define BSP_USING_TIM3_CH3 +#define BSP_USING_TIM3_CH4 + +#endif diff --git a/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py new file mode 100755 index 0000000000..4a56028bfb --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py @@ -0,0 +1,170 @@ +import os + +print(os.path.abspath(__file__)) + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/gcc-arm-none-eabi-6_2-2016q4/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + +print('ARCH =[%s]' %(ARCH )) +print('CPU =[%s]' %(CPU )) +print('CROSS_TOOL =[%s]' %(CROSS_TOOL)) +print('RTT_ROOT =[%s]' %(RTT_ROOT )) +print('PLATFORM =[%s]' %(PLATFORM )) +print('EXEC_PATH =[%s]' %(EXEC_PATH )) +print('CC =[%s]' %(CC )) +print('AS =[%s]' %(AS )) +print('AR =[%s]' %(AR )) +print('LINK =[%s]' %(LINK )) +print('TARGET_EXT =[%s]' %(TARGET_EXT)) +print('DEVICE =[%s]' %(DEVICE )) +print('CFLAGS =[%s]' %(CFLAGS )) +print('AFLAGS =[%s]' %(AFLAGS )) +print('LFLAGS =[%s]' %(LFLAGS )) diff --git a/bsp/n32g452xx/n32g452xx-mini-system/template.uvprojx b/bsp/n32g452xx/n32g452xx-mini-system/template.uvprojx new file mode 100755 index 0000000000..22314f2a12 --- /dev/null +++ b/bsp/n32g452xx/n32g452xx-mini-system/template.uvprojx @@ -0,0 +1,399 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-n32 + 0x4 + ARM-ADS + 0 + + + N32G452RCL7 + Nationstech + Nationstech.N32G45x_DFP.1.0.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x24000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32G45x -FS08000000 -FL040000 -FP0($$Device:N32G452RCL7$Flash\N32G45x.FLM)) + 0 + $$Device:N32G452RCL7$firmware\CMSIS\device\n32g45x.h + + + + + + + + + + $$Device:N32G452RCL7$svd\N32G452.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x24000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x24000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/n32g452xx/tools/sdk_dist.py b/bsp/n32g452xx/tools/sdk_dist.py new file mode 100755 index 0000000000..00cd1b7b9d --- /dev/null +++ b/bsp/n32g452xx/tools/sdk_dist.py @@ -0,0 +1,20 @@ +import os +import sys +import shutil +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + +# BSP dist function +def dist_do_building(BSP_ROOT, dist_dir): + from mkdist import bsp_copy_files + import rtconfig + + print("=> copy n32 bsp library") + library_dir = os.path.join(dist_dir, 'Libraries') + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries') + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), + os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + + print("=> copy bsp drivers") + bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) diff --git a/bsp/nrf5x/docs/images/nrf52833.jpg b/bsp/nrf5x/docs/images/nrf52833.jpg new file mode 100644 index 0000000000..aed069b661 Binary files /dev/null and b/bsp/nrf5x/docs/images/nrf52833.jpg differ diff --git a/bsp/nrf5x/nrf52833/.config b/bsp/nrf5x/nrf52833/.config new file mode 100644 index 0000000000..271bf4aa40 --- /dev/null +++ b/bsp/nrf5x/nrf52833/.config @@ -0,0 +1,591 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +CONFIG_PKG_USING_NRFX=y +CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx" +# CONFIG_PKG_USING_NRFX_V210 is not set +CONFIG_PKG_USING_NRFX_LATEST_VERSION=y +CONFIG_PKG_NRFX_VER="latest" +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_NRF52833=y +CONFIG_SOC_NORDIC=y +CONFIG_BSP_BOARD_PCA_10100=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_PIN=8 +CONFIG_BSP_UART0_TX_PIN=6 + +# +# On-chip flash config +# +CONFIG_MCU_FLASH_START_ADDRESS=0x00000000 +CONFIG_MCU_FLASH_SIZE_KB=512 +CONFIG_MCU_SRAM_START_ADDRESS=0x20000000 +CONFIG_MCU_SRAM_SIZE_KB=128 +CONFIG_MCU_FLASH_PAGE_SIZE=0x1000 +CONFIG_NRFX_CLOCK_ENABLED=1 +CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7 +CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1 +CONFIG_NRFX_USING_UART=y +CONFIG_NRFX_UART_ENABLED=1 +CONFIG_NRFX_UART0_ENABLED=1 diff --git a/bsp/nrf5x/nrf52833/Kconfig b/bsp/nrf5x/nrf52833/Kconfig new file mode 100644 index 0000000000..3640eaa0ed --- /dev/null +++ b/bsp/nrf5x/nrf52833/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + diff --git a/bsp/nrf5x/nrf52833/README.md b/bsp/nrf5x/nrf52833/README.md new file mode 100644 index 0000000000..b07cf8e3a3 --- /dev/null +++ b/bsp/nrf5x/nrf52833/README.md @@ -0,0 +1,68 @@ +# nRF52833-PCA10010 BSP说明 + +## 简介 + +该文件夹主要存放所有主芯片为nRF52833的板级支持包。目前默认支持的开发板是官方[PCA10100](https://www.nordicsemi.com/Products/Development-hardware/nRF52833-DK) +本文主要内容如下： + +- 开发板资源介绍 +- 进阶使用方法 + +## 开发板介绍 + +PCA10100-nRF52833是Nordic 官方的开发板，搭载nRF52833 芯片，基于ARM Cortex-M4内核，最高主频64 MHz，具有丰富的外设资源。 + +开发板外观如下图所示 + +![nrf52833](../docs/images/nrf52833.jpg) + +PCA10100-nRF52833 开发板常用 **板载资源** 如下： + +- MCU：NRF52833，主频 64MHz，512KB FLASH ，128kB RAM +- MCU 外设: GPIO, UART, SPI, I2C(TWI), RTC,TIMER,NFC,QSPI,PWM,ADC,USB,I2S +- 板载设 + - LED：4个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 + - 按键：5个，4个USER and 1个RESET 。 + - USB: 1个 +- 常用接口：USB device、Arduino Uno 接口 +- 调试接口：板载 J-LINK 调试器。 + +开发板更多详细信息请参考NORDIC官方[PCA10100](https://www.nordicsemi.com/Products/Development-hardware/nRF52833-DK) + + + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------- | :----------: | :--------------------: | +| UART | 支持 | UART0 | + + + +### 进阶使用 + +此 BSP 默认只开启了串口 0 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + + + +## 支持其他开发板 + +客户可以将自己的开发板的.config文件和board/Kconfig文件到board/$(board_name)下面添加README.md即可，使用的时候替换.config文件 + +## 注意事项 + +## 联系人信息 + +维护人: + +- [RiceChen], 邮箱：<980307037@qq.com> \ No newline at end of file diff --git a/bsp/nrf5x/nrf52833/SConscript b/bsp/nrf5x/nrf52833/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/nrf5x/nrf52833/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nrf5x/nrf52833/SConstruct b/bsp/nrf5x/nrf52833/SConstruct new file mode 100644 index 0000000000..2ac1ce6674 --- /dev/null +++ b/bsp/nrf5x/nrf52833/SConstruct @@ -0,0 +1,57 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') +print(SDK_LIB) + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# include cmsis +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nrf5x/nrf52833/applications/SConscript b/bsp/nrf5x/nrf52833/applications/SConscript new file mode 100644 index 0000000000..fc2501998c --- /dev/null +++ b/bsp/nrf5x/nrf52833/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nrf5x/nrf52833/applications/application.c b/bsp/nrf5x/nrf52833/applications/application.c new file mode 100644 index 0000000000..87d0f04b86 --- /dev/null +++ b/bsp/nrf5x/nrf52833/applications/application.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-29 supperthomas first version + * + */ + +#include +#include + +int main(void) +{ + while (1) + { + rt_thread_mdelay(500); + } + return RT_EOK; +} + diff --git a/bsp/nrf5x/nrf52833/board/Kconfig b/bsp/nrf5x/nrf52833/board/Kconfig new file mode 100644 index 0000000000..8bcbba093b --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/Kconfig @@ -0,0 +1,116 @@ +menu "Hardware Drivers Config" + +config SOC_NRF52833 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config SOC_NORDIC + bool + default y + +choice + prompt "Select BSP board " + default BSP_BOARD_PCA_10100 + + config BSP_BOARD_PCA_10100 + bool "NRF52833 pca10100" + +endchoice + +menu "On-chip Peripheral Drivers" + config BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + config BSP_USING_UART0 + bool "Enable UART0" + default y + depends on BSP_USING_UART + + config BSP_UART0_RX_PIN + depends on BSP_USING_UART0 + int "uart0 rx pin number" + default 8 if BSP_BOARD_PCA_10100 + + config BSP_UART0_TX_PIN + depends on BSP_USING_UART0 + int "uart0 tx pin number" + default 6 if BSP_BOARD_PCA_10100 + + menu "On-chip flash config" + + config MCU_FLASH_START_ADDRESS + hex "MCU FLASH START ADDRESS" + default 0x00000000 + + config MCU_FLASH_SIZE_KB + int "MCU FLASH SIZE, MAX size 1024 KB" + default 1024 + + config MCU_SRAM_START_ADDRESS + hex "MCU RAM START ADDRESS" + default 0x20000000 + + config MCU_SRAM_SIZE_KB + int "MCU RAM SIZE" + default 256 + + config MCU_FLASH_PAGE_SIZE + hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000" + default 0x1000 + endmenu + +endmenu + +if SOC_NORDIC + config NRFX_CLOCK_ENABLED + int + default 1 + config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY + int + default 7 + config NRFX_CLOCK_CONFIG_LF_SRC + int + default 1 +endif + +if BSP_USING_UART + config NRFX_USING_UART + bool + default y + + config NRFX_UART_ENABLED + int + default 1 + + config NRFX_UART0_ENABLED + int + default 1 + depends on BSP_USING_UART0 +endif + +choice +prompt "BLE STACK" +default BLE_STACK_USING_NULL +help + Select the ble stack + +config BLE_STACK_USING_NULL + bool "not use the ble stack" + +config BSP_USING_SOFTDEVICE + select PKG_USING_NRF5X_SDK + bool "Nordic softdevice(perpheral)" + +config BSP_USING_NIMBLE + select PKG_USING_NIMBLE + select PKG_NIMBLE_BSP_NRF52840 + bool "use nimble stack(iot)" +endchoice + + +endmenu + + diff --git a/bsp/nrf5x/nrf52833/board/SConscript b/bsp/nrf5x/nrf52833/board/SConscript new file mode 100644 index 0000000000..27bcddd310 --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] +define = ['USE_APP_CONFIG'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define) +Return('group') diff --git a/bsp/nrf5x/nrf52833/board/board.c b/bsp/nrf5x/nrf52833/board/board.c new file mode 100644 index 0000000000..2cb94fb6fa --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/board.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-29 supperthomas first version + * + */ +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" +#include + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void clk_event_handler(nrfx_clock_evt_type_t event){} + +void SysTick_Configuration(void) +{ + nrfx_clock_init(clk_event_handler); + nrfx_clock_enable(); + nrfx_clock_lfclk_start(); + /* Set interrupt priority */ + NVIC_SetPriority(SysTick_IRQn, 0xf); + + /* Configure SysTick to interrupt at the requested rate. */ + nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND); + nrf_systick_val_clear(); + nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE + | NRF_SYSTICK_CSR_ENABLE); + +} + + +void rt_hw_board_init(void) +{ + rt_hw_interrupt_enable(0); + + SysTick_Configuration(); + +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_SERIAL + rt_hw_uart_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef BSP_USING_SOFTDEVICE + extern uint32_t Image$$RW_IRAM1$$Base; + uint32_t const *const m_ram_start = &Image$$RW_IRAM1$$Base; + if ((uint32_t)m_ram_start == 0x20000000) + { + rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start); + while (1); + } + else + { + rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start); + } +#endif + +} + diff --git a/bsp/nrf5x/nrf52833/board/board.h b/bsp/nrf5x/nrf52833/board/board.h new file mode 100644 index 0000000000..52e812fac6 --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/board.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-29 supperthomas first version + * + */ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include +#include +#include "nrf.h" + +#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024 +#define MCU_FLASH_END_ADDRESS ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE)) +#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024 +#define MCU_SRAM_END_ADDRESS (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end__; +#define HEAP_BEGIN ((void *)&__bss_end__) +#endif + + +#define HEAP_END (MCU_SRAM_END_ADDRESS) + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds b/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds new file mode 100644 index 0000000000..f91b8466ca --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/linker_scripts/link.lds @@ -0,0 +1,15 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 +} + +INCLUDE "packages/nrfx-v2.1.0/mdk/nrf_common.ld" + + + diff --git a/bsp/nrf5x/nrf52833/board/linker_scripts/link.sct b/bsp/nrf5x/nrf52833/board/linker_scripts/link.sct new file mode 100644 index 0000000000..a2f8ebd922 --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x100000 { ; load region size_region + ER_IROM1 0x00000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x40000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/nrf5x/nrf52833/board/nrfx_config.h b/bsp/nrf5x/nrf52833/board/nrfx_config.h new file mode 100644 index 0000000000..b006b6bcd5 --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/nrfx_config.h @@ -0,0 +1,47 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +// TODO - temporary redirection +#include + +#endif // NRFX_CONFIG_H__ diff --git a/bsp/nrf5x/nrf52833/board/nrfx_glue.h b/bsp/nrf5x/nrf52833/board/nrfx_glue.h new file mode 100644 index 0000000000..28025dafae --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/nrfx_glue.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif +#include +#include "nrf.h" +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +// Uncomment this line to use the standard MDK way of binding IRQ handlers +// at linking time. +#include + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_ASSERT(expression) + +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_STATIC_ASSERT(expression) + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to be set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) NVIC_SetPriority(irq_number, priority) + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) NVIC_EnableIRQ(irq_number) + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) +static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) +{ + return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); +} + + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) +static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) +{ + NVIC_DisableIRQ(irq_number); +} + + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) + +/** @brief Macro for entering into a critical section. */ +#define NRFX_CRITICAL_SECTION_ENTER() + +/** @brief Macro for exiting from a critical section. */ +#define NRFX_CRITICAL_SECTION_EXIT() + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +/** + * @brief Macro for delaying the code execution for at least the specified time. + * + * @param us_time Number of microseconds to wait. + */ +#define NRFX_DELAY_US(us_time) + +//------------------------------------------------------------------------------ + +/** @brief Atomic 32-bit unsigned type. */ +#define nrfx_atomic_t + +/** + * @brief Macro for storing a value to an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) + +/** + * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the OR operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_OR(p_data, value) + +/** + * @brief Macro for running a bitwise AND operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the AND operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_AND(p_data, value) + +/** + * @brief Macro for running a bitwise XOR operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the XOR operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) + +/** + * @brief Macro for running an addition operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the ADD operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) + +/** + * @brief Macro for running a subtraction operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the SUB operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined + * in a customized way and the default definitions from @c + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 0 + +//------------------------------------------------------------------------------ + +/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI_CHANNELS_USED 0 + +/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI_GROUPS_USED 0 + +/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */ +#define NRFX_PPI_CHANNELS_USED 0 + +/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */ +#define NRFX_PPI_GROUPS_USED 0 + +/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */ +#define NRFX_EGUS_USED 0 + +/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */ +#define NRFX_TIMERS_USED 0 + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/bsp/nrf5x/nrf52833/board/nrfx_log.h b/bsp/nrf5x/nrf52833/board/nrfx_log.h new file mode 100644 index 0000000000..80d8efbdf1 --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/nrfx_log.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_LOG_H__ +#define NRFX_LOG_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_log nrfx_log.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +/** + * @brief Macro for logging a message with the severity level ERROR. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_ERROR(format, ...) + +/** + * @brief Macro for logging a message with the severity level WARNING. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_WARNING(format, ...) + +/** + * @brief Macro for logging a message with the severity level INFO. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_INFO(format, ...) + +/** + * @brief Macro for logging a message with the severity level DEBUG. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_DEBUG(format, ...) + + +/** + * @brief Macro for logging a memory dump with the severity level ERROR. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level WARNING. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level INFO. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level DEBUG. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) + + +/** + * @brief Macro for getting the textual representation of a given error code. + * + * @param[in] error_code Error code. + * + * @return String containing the textual representation of the error code. + */ +#define NRFX_LOG_ERROR_STRING_GET(error_code) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LOG_H__ diff --git a/bsp/nrf5x/nrf52833/board/sdk_config.h b/bsp/nrf5x/nrf52833/board/sdk_config.h new file mode 100644 index 0000000000..25fa4938fa --- /dev/null +++ b/bsp/nrf5x/nrf52833/board/sdk_config.h @@ -0,0 +1,11701 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + + +#ifndef SDK_CONFIG_H +#define SDK_CONFIG_H +// <<< Use Configuration Wizard in Context Menu >>>\n +// nRF_BLE + +#include +//========================================================== +// BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module + + +#ifndef BLE_ADVERTISING_ENABLED +#define BLE_ADVERTISING_ENABLED 0 +#endif + +// BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands + + +#ifndef BLE_DTM_ENABLED +#define BLE_DTM_ENABLED 0 +#endif + +// BLE_RACP_ENABLED - ble_racp - Record Access Control Point library + + +#ifndef BLE_RACP_ENABLED +#define BLE_RACP_ENABLED 0 +#endif + +// NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) +//========================================================== +#ifndef NRF_BLE_QWR_ENABLED +#define NRF_BLE_QWR_ENABLED 0 +#endif +// NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests. +#ifndef NRF_BLE_QWR_MAX_ATTR +#define NRF_BLE_QWR_MAX_ATTR 0 +#endif + +// + +// PEER_MANAGER_ENABLED - peer_manager - Peer Manager +//========================================================== +#ifndef PEER_MANAGER_ENABLED +#define PEER_MANAGER_ENABLED 0 +#endif +// PM_MAX_REGISTRANTS - Number of event handlers that can be registered. +#ifndef PM_MAX_REGISTRANTS +#define PM_MAX_REGISTRANTS 3 +#endif + +// PM_FLASH_BUFFERS - Number of internal buffers for flash operations. +// Decrease this value to lower RAM usage. + +#ifndef PM_FLASH_BUFFERS +#define PM_FLASH_BUFFERS 4 +#endif + +// PM_CENTRAL_ENABLED - Enable/disable central-specific Peer Manager functionality. + + +// Enable/disable central-specific Peer Manager functionality. + +#ifndef PM_CENTRAL_ENABLED +#define PM_CENTRAL_ENABLED 1 +#endif + +// PM_SERVICE_CHANGED_ENABLED - Enable/disable the service changed management for GATT server in Peer Manager. + + +// If not using a GATT server, or using a server wihout a service changed characteristic, +// disable this to save code space. + +#ifndef PM_SERVICE_CHANGED_ENABLED +#define PM_SERVICE_CHANGED_ENABLED 1 +#endif + +// PM_PEER_RANKS_ENABLED - Enable/disable the peer rank management in Peer Manager. + + +// Set this to false to save code space if not using the peer rank API. + +#ifndef PM_PEER_RANKS_ENABLED +#define PM_PEER_RANKS_ENABLED 1 +#endif + +// PM_LESC_ENABLED - Enable/disable LESC support in Peer Manager. + + +// If set to true, you need to call nrf_ble_lesc_request_handler() in the main loop to respond to LESC-related BLE events. If LESC support is not required, set this to false to save code space. + +#ifndef PM_LESC_ENABLED +#define PM_LESC_ENABLED 0 +#endif + +// PM_RA_PROTECTION_ENABLED - Enable/disable protection against repeated pairing attempts in Peer Manager. +//========================================================== +#ifndef PM_RA_PROTECTION_ENABLED +#define PM_RA_PROTECTION_ENABLED 0 +#endif +// PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked. +#ifndef PM_RA_PROTECTION_TRACKED_PEERS_NUM +#define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8 +#endif + +// PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated. +#ifndef PM_RA_PROTECTION_MIN_WAIT_INTERVAL +#define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000 +#endif + +// PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated. +#ifndef PM_RA_PROTECTION_MAX_WAIT_INTERVAL +#define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000 +#endif + +// PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms). +// The waiting interval is gradually decreased when no new failed pairing attempts are made during reward period. + +#ifndef PM_RA_PROTECTION_REWARD_PERIOD +#define PM_RA_PROTECTION_REWARD_PERIOD 10000 +#endif + +// + +// PM_HANDLER_SEC_DELAY_MS - Delay before starting security. +// This might be necessary for interoperability reasons, especially as peripheral. + +#ifndef PM_HANDLER_SEC_DELAY_MS +#define PM_HANDLER_SEC_DELAY_MS 0 +#endif + +// + +// +//========================================================== + +// nRF_BLE_Services + +//========================================================== +// BLE_ANCS_C_ENABLED - ble_ancs_c - Apple Notification Service Client + + +#ifndef BLE_ANCS_C_ENABLED +#define BLE_ANCS_C_ENABLED 0 +#endif + +// BLE_ANS_C_ENABLED - ble_ans_c - Alert Notification Service Client + + +#ifndef BLE_ANS_C_ENABLED +#define BLE_ANS_C_ENABLED 0 +#endif + +// BLE_BAS_C_ENABLED - ble_bas_c - Battery Service Client + + +#ifndef BLE_BAS_C_ENABLED +#define BLE_BAS_C_ENABLED 0 +#endif + +// BLE_BAS_ENABLED - ble_bas - Battery Service +//========================================================== +#ifndef BLE_BAS_ENABLED +#define BLE_BAS_ENABLED 0 +#endif +// BLE_BAS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_BAS_CONFIG_LOG_ENABLED +#define BLE_BAS_CONFIG_LOG_ENABLED 0 +#endif +// BLE_BAS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_BAS_CONFIG_LOG_LEVEL +#define BLE_BAS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_BAS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_BAS_CONFIG_INFO_COLOR +#define BLE_BAS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_BAS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_BAS_CONFIG_DEBUG_COLOR +#define BLE_BAS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_CSCS_ENABLED - ble_cscs - Cycling Speed and Cadence Service + + +#ifndef BLE_CSCS_ENABLED +#define BLE_CSCS_ENABLED 0 +#endif + +// BLE_CTS_C_ENABLED - ble_cts_c - Current Time Service Client + + +#ifndef BLE_CTS_C_ENABLED +#define BLE_CTS_C_ENABLED 0 +#endif + +// BLE_DIS_ENABLED - ble_dis - Device Information Service + + +#ifndef BLE_DIS_ENABLED +#define BLE_DIS_ENABLED 0 +#endif + +// BLE_GLS_ENABLED - ble_gls - Glucose Service + + +#ifndef BLE_GLS_ENABLED +#define BLE_GLS_ENABLED 0 +#endif + +// BLE_HIDS_ENABLED - ble_hids - Human Interface Device Service + + +#ifndef BLE_HIDS_ENABLED +#define BLE_HIDS_ENABLED 0 +#endif + +// BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client + + +#ifndef BLE_HRS_C_ENABLED +#define BLE_HRS_C_ENABLED 0 +#endif + +// BLE_HRS_ENABLED - ble_hrs - Heart Rate Service + + +#ifndef BLE_HRS_ENABLED +#define BLE_HRS_ENABLED 0 +#endif + +// BLE_HTS_ENABLED - ble_hts - Health Thermometer Service + + +#ifndef BLE_HTS_ENABLED +#define BLE_HTS_ENABLED 0 +#endif + +// BLE_IAS_C_ENABLED - ble_ias_c - Immediate Alert Service Client + + +#ifndef BLE_IAS_C_ENABLED +#define BLE_IAS_C_ENABLED 0 +#endif + +// BLE_IAS_ENABLED - ble_ias - Immediate Alert Service +//========================================================== +#ifndef BLE_IAS_ENABLED +#define BLE_IAS_ENABLED 0 +#endif +// BLE_IAS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_IAS_CONFIG_LOG_ENABLED +#define BLE_IAS_CONFIG_LOG_ENABLED 0 +#endif +// BLE_IAS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_IAS_CONFIG_LOG_LEVEL +#define BLE_IAS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_IAS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_IAS_CONFIG_INFO_COLOR +#define BLE_IAS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_IAS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_IAS_CONFIG_DEBUG_COLOR +#define BLE_IAS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_LBS_C_ENABLED - ble_lbs_c - Nordic LED Button Service Client + + +#ifndef BLE_LBS_C_ENABLED +#define BLE_LBS_C_ENABLED 0 +#endif + +// BLE_LBS_ENABLED - ble_lbs - LED Button Service + + +#ifndef BLE_LBS_ENABLED +#define BLE_LBS_ENABLED 0 +#endif + +// BLE_LLS_ENABLED - ble_lls - Link Loss Service + + +#ifndef BLE_LLS_ENABLED +#define BLE_LLS_ENABLED 0 +#endif + +// BLE_NUS_C_ENABLED - ble_nus_c - Nordic UART Central Service + + +#ifndef BLE_NUS_C_ENABLED +#define BLE_NUS_C_ENABLED 0 +#endif + +// BLE_NUS_ENABLED - ble_nus - Nordic UART Service +//========================================================== +#ifndef BLE_NUS_ENABLED +#define BLE_NUS_ENABLED 0 +#endif +// BLE_NUS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_NUS_CONFIG_LOG_ENABLED +#define BLE_NUS_CONFIG_LOG_ENABLED 0 +#endif +// BLE_NUS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_NUS_CONFIG_LOG_LEVEL +#define BLE_NUS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_NUS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_NUS_CONFIG_INFO_COLOR +#define BLE_NUS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_NUS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_NUS_CONFIG_DEBUG_COLOR +#define BLE_NUS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_RSCS_C_ENABLED - ble_rscs_c - Running Speed and Cadence Client + + +#ifndef BLE_RSCS_C_ENABLED +#define BLE_RSCS_C_ENABLED 0 +#endif + +// BLE_RSCS_ENABLED - ble_rscs - Running Speed and Cadence Service + + +#ifndef BLE_RSCS_ENABLED +#define BLE_RSCS_ENABLED 0 +#endif + +// BLE_TPS_ENABLED - ble_tps - TX Power Service + + +#ifndef BLE_TPS_ENABLED +#define BLE_TPS_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Core + +//========================================================== +// NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU +//========================================================== +#ifndef NRF_MPU_LIB_ENABLED +#define NRF_MPU_LIB_ENABLED 0 +#endif +// NRF_MPU_LIB_CLI_CMDS - Enable CLI commands specific to the module. + + +#ifndef NRF_MPU_LIB_CLI_CMDS +#define NRF_MPU_LIB_CLI_CMDS 0 +#endif + +// + +// NRF_STACK_GUARD_ENABLED - nrf_stack_guard - Stack guard +//========================================================== +#ifndef NRF_STACK_GUARD_ENABLED +#define NRF_STACK_GUARD_ENABLED 0 +#endif +// NRF_STACK_GUARD_CONFIG_SIZE - Size of the stack guard. + +// <5=> 32 bytes +// <6=> 64 bytes +// <7=> 128 bytes +// <8=> 256 bytes +// <9=> 512 bytes +// <10=> 1024 bytes +// <11=> 2048 bytes +// <12=> 4096 bytes + +#ifndef NRF_STACK_GUARD_CONFIG_SIZE +#define NRF_STACK_GUARD_CONFIG_SIZE 7 +#endif + +// + +// +//========================================================== + +// nRF_Crypto + +//========================================================== +// NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library. +//========================================================== +#ifndef NRF_CRYPTO_ENABLED +#define NRF_CRYPTO_ENABLED 1 +#endif +// NRF_CRYPTO_ALLOCATOR - Memory allocator + + +// Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK. +// <0=> Default +// <1=> User macros +// <2=> On stack (alloca) +// <3=> C dynamic memory (malloc) +// <4=> SDK Memory Manager (nrf_malloc) + +#ifndef NRF_CRYPTO_ALLOCATOR +#define NRF_CRYPTO_ALLOCATOR 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_ENABLED - Enable the ARM Cryptocell CC310 reduced backend. + +// The CC310 hardware-accelerated cryptography backend with reduced functionality and footprint (only available on nRF52840). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310_BL. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310_BL. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED - CC310_BL SHA-256 hash functionality. + + +// CC310_BL backend implementation for hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED - nrf_cc310_bl buffers to RAM before running hash operation + + +// Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian +// Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU! + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED - Enable Interrupts while support using CC310 bl. + + +// Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_CC310_ENABLED - Enable the ARM Cryptocell CC310 backend. + +// The CC310 hardware-accelerated cryptography backend (only available on nRF52840). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CC310_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED - Enable the AES CBC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED - Enable the AES CTR mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED - Enable the AES ECB mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED - Enable the AES CBC_MAC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED - Enable the AES CMAC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED - Enable the AES CCM mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED - Enable the AES CCM* mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED - Enable the secp160r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED - Enable the secp160r2 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED - Enable the secp192r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED - Enable the secp384r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED - Enable the secp521r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED - Enable the secp160k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED - Enable the secp192k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED - Enable the secp224k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED - Enable the secp256k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED - Enable the Curve25519 curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED - Enable the Ed25519 curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED - CC310 SHA-256 hash functionality. + + +// CC310 backend implementation for hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED - CC310 SHA-512 hash functionality + + +// CC310 backend implementation for SHA-512 (in software). + +#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED - CC310 HMAC using SHA-256 + + +// CC310 backend implementation for HMAC using hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED - CC310 HMAC using SHA-512 + + +// CC310 backend implementation for HMAC using SHA-512 (in software). + +#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED - Enable RNG support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED - Enable Interrupts while support using CC310. + + +// Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used + +#ifndef NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_CIFRA_ENABLED - Enable the Cifra backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CIFRA_ENABLED +#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED - Enable the AES EAX mode using Cifra. + + +#ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED +#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED - Enable the mbed TLS backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED - Enable the AES CBC mode mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED - Enable the AES CTR mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED - Enable the AES CFB mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED - Enable the AES ECB mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED - Enable the AES CBC MAC mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED - Enable the AES CMAC mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED - Enable the AES CCM mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED - Enable the AES GCM mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve + + +// Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve + + +// Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve + + +// Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED - Enable secp384r1 (NIST 384-bit) curve + + +// Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED - Enable secp521r1 (NIST 521-bit) curve + + +// Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED - Enable secp192k1 (Koblitz 192-bit) curve + + +// Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED - Enable secp224k1 (Koblitz 224-bit) curve + + +// Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve + + +// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED - Enable bp256r1 (Brainpool 256-bit) curve + + +// Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED - Enable bp384r1 (Brainpool 384-bit) curve + + +// Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED - Enable bp512r1 (Brainpool 512-bit) curve + + +// Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED - Enable Curve25519 curve + + +// Enable this setting if you need Curve25519 support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED - Enable mbed TLS SHA-256 hash functionality. + + +// mbed TLS backend implementation for SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED - Enable mbed TLS SHA-512 hash functionality. + + +// mbed TLS backend implementation for SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED - Enable mbed TLS HMAC using SHA-256. + + +// mbed TLS backend implementation for HMAC using SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED - Enable mbed TLS HMAC using SHA-512. + + +// mbed TLS backend implementation for HMAC using SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED - Enable the micro-ecc backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve + + +// Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve + + +// Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve + + +// Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve + + +// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED - Enable the nRF HW RNG backend. + +// The nRF HW backend provide access to RNG peripheral in nRF5x devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED - Enable mbed TLS CTR-DRBG algorithm. + + +// Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding. + +#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_NRF_SW_ENABLED - Enable the legacy nRFx sw for crypto. + +// The nRF SW cryptography backend (only used in bootloader context). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_NRF_SW_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED - nRF SW hash backend support for SHA-256 + + +// The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_OBERON_ENABLED - Enable the Oberon backend + +// The Oberon backend +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_OBERON_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using Oberon. + + +#ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED - Enable secp256r1 curve + + +// Enable this setting if you need secp256r1 curve support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED - Enable Curve25519 ECDH + + +// Enable this setting if you need Curve25519 ECDH support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED - Enable Ed25519 signature scheme + + +// Enable this setting if you need Ed25519 support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED - Oberon SHA-256 hash functionality + + +// Oberon backend implementation for SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED - Oberon SHA-512 hash functionality + + +// Oberon backend implementation for SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED - Oberon HMAC using SHA-256 + + +// Oberon backend implementation for HMAC using SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED - Oberon HMAC using SHA-512 + + +// Oberon backend implementation for HMAC using SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_OPTIGA_ENABLED - Enable the nrf_crypto Optiga Trust X backend. + +// Enables the nrf_crypto backend for Optiga Trust X devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED - Optiga backend support for RNG + + +// The Optiga backend provide external chip RNG. + +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED - Optiga backend support for ECC secp256r1 + + +// The Optiga backend provide external chip ECC using secp256r1. + +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED - Big-endian byte order in raw Curve25519 data + + +// Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0. + +#ifndef NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED +#define NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED 0 +#endif + +// + +// +//========================================================== + +// nRF_DFU + +//========================================================== +// ble_dfu - Device Firmware Update + +//========================================================== +// BLE_DFU_ENABLED - Enable DFU Service. + + +#ifndef BLE_DFU_ENABLED +#define BLE_DFU_ENABLED 0 +#endif + +// NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS - Buttonless DFU supports bonds. + + +#ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS +#define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// nRF_Drivers + +//========================================================== +// COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer +//========================================================== +#ifndef COMP_ENABLED +#define COMP_ENABLED 0 +#endif +// COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef COMP_CONFIG_REF +#define COMP_CONFIG_REF 1 +#endif + +// COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef COMP_CONFIG_MAIN_MODE +#define COMP_CONFIG_MAIN_MODE 0 +#endif + +// COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef COMP_CONFIG_SPEED_MODE +#define COMP_CONFIG_SPEED_MODE 2 +#endif + +// COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef COMP_CONFIG_HYST +#define COMP_CONFIG_HYST 0 +#endif + +// COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef COMP_CONFIG_ISOURCE +#define COMP_CONFIG_ISOURCE 0 +#endif + +// COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_INPUT +#define COMP_CONFIG_INPUT 0 +#endif + +// COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_IRQ_PRIORITY +#define COMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer + + +#ifndef EGU_ENABLED +#define EGU_ENABLED 0 +#endif + +// GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver - legacy layer +//========================================================== +#ifndef GPIOTE_ENABLED +#define GPIOTE_ENABLED 0 +#endif +// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef GPIOTE_CONFIG_IRQ_PRIORITY +#define GPIOTE_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver - legacy layer +//========================================================== +#ifndef I2S_ENABLED +#define I2S_ENABLED 0 +#endif +// I2S_CONFIG_SCK_PIN - SCK pin <0-31> + + +#ifndef I2S_CONFIG_SCK_PIN +#define I2S_CONFIG_SCK_PIN 31 +#endif + +// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> + + +#ifndef I2S_CONFIG_LRCK_PIN +#define I2S_CONFIG_LRCK_PIN 30 +#endif + +// I2S_CONFIG_MCK_PIN - MCK pin +#ifndef I2S_CONFIG_MCK_PIN +#define I2S_CONFIG_MCK_PIN 255 +#endif + +// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> + + +#ifndef I2S_CONFIG_SDOUT_PIN +#define I2S_CONFIG_SDOUT_PIN 29 +#endif + +// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> + + +#ifndef I2S_CONFIG_SDIN_PIN +#define I2S_CONFIG_SDIN_PIN 28 +#endif + +// I2S_CONFIG_MASTER - Mode + +// <0=> Master +// <1=> Slave + +#ifndef I2S_CONFIG_MASTER +#define I2S_CONFIG_MASTER 0 +#endif + +// I2S_CONFIG_FORMAT - Format + +// <0=> I2S +// <1=> Aligned + +#ifndef I2S_CONFIG_FORMAT +#define I2S_CONFIG_FORMAT 0 +#endif + +// I2S_CONFIG_ALIGN - Alignment + +// <0=> Left +// <1=> Right + +#ifndef I2S_CONFIG_ALIGN +#define I2S_CONFIG_ALIGN 0 +#endif + +// I2S_CONFIG_SWIDTH - Sample width (bits) + +// <0=> 8 +// <1=> 16 +// <2=> 24 + +#ifndef I2S_CONFIG_SWIDTH +#define I2S_CONFIG_SWIDTH 1 +#endif + +// I2S_CONFIG_CHANNELS - Channels + +// <0=> Stereo +// <1=> Left +// <2=> Right + +#ifndef I2S_CONFIG_CHANNELS +#define I2S_CONFIG_CHANNELS 1 +#endif + +// I2S_CONFIG_MCK_SETUP - MCK behavior + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 + +#ifndef I2S_CONFIG_MCK_SETUP +#define I2S_CONFIG_MCK_SETUP 536870912 +#endif + +// I2S_CONFIG_RATIO - MCK/LRCK ratio + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x + +#ifndef I2S_CONFIG_RATIO +#define I2S_CONFIG_RATIO 2000 +#endif + +// I2S_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef I2S_CONFIG_IRQ_PRIORITY +#define I2S_CONFIG_IRQ_PRIORITY 6 +#endif + +// I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef I2S_CONFIG_LOG_ENABLED +#define I2S_CONFIG_LOG_ENABLED 0 +#endif +// I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef I2S_CONFIG_LOG_LEVEL +#define I2S_CONFIG_LOG_LEVEL 3 +#endif + +// I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_INFO_COLOR +#define I2S_CONFIG_INFO_COLOR 0 +#endif + +// I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_DEBUG_COLOR +#define I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver - legacy layer +//========================================================== +#ifndef LPCOMP_ENABLED +#define LPCOMP_ENABLED 0 +#endif +// LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#ifndef LPCOMP_CONFIG_REFERENCE +#define LPCOMP_CONFIG_REFERENCE 3 +#endif + +// LPCOMP_CONFIG_DETECTION - Detection + +// <0=> Crossing +// <1=> Up +// <2=> Down + +#ifndef LPCOMP_CONFIG_DETECTION +#define LPCOMP_CONFIG_DETECTION 2 +#endif + +// LPCOMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_INPUT +#define LPCOMP_CONFIG_INPUT 0 +#endif + +// LPCOMP_CONFIG_HYST - Hysteresis + + +#ifndef LPCOMP_CONFIG_HYST +#define LPCOMP_CONFIG_HYST 0 +#endif + +// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_IRQ_PRIORITY +#define LPCOMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver +//========================================================== +#ifndef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#endif + +// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver +//========================================================== +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef NRFX_COMP_CONFIG_REF +#define NRFX_COMP_CONFIG_REF 1 +#endif + +// NRFX_COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef NRFX_COMP_CONFIG_MAIN_MODE +#define NRFX_COMP_CONFIG_MAIN_MODE 0 +#endif + +// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef NRFX_COMP_CONFIG_SPEED_MODE +#define NRFX_COMP_CONFIG_SPEED_MODE 2 +#endif + +// NRFX_COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef NRFX_COMP_CONFIG_HYST +#define NRFX_COMP_CONFIG_HYST 0 +#endif + +// NRFX_COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef NRFX_COMP_CONFIG_ISOURCE +#define NRFX_COMP_CONFIG_ISOURCE 0 +#endif + +// NRFX_COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_INPUT +#define NRFX_COMP_CONFIG_INPUT 0 +#endif + +// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_INFO_COLOR +#define NRFX_COMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR +#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver +//========================================================== +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif +// NRFX_I2S_CONFIG_SCK_PIN - SCK pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SCK_PIN +#define NRFX_I2S_CONFIG_SCK_PIN 31 +#endif + +// NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> + + +#ifndef NRFX_I2S_CONFIG_LRCK_PIN +#define NRFX_I2S_CONFIG_LRCK_PIN 30 +#endif + +// NRFX_I2S_CONFIG_MCK_PIN - MCK pin +#ifndef NRFX_I2S_CONFIG_MCK_PIN +#define NRFX_I2S_CONFIG_MCK_PIN 255 +#endif + +// NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SDOUT_PIN +#define NRFX_I2S_CONFIG_SDOUT_PIN 29 +#endif + +// NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SDIN_PIN +#define NRFX_I2S_CONFIG_SDIN_PIN 28 +#endif + +// NRFX_I2S_CONFIG_MASTER - Mode + +// <0=> Master +// <1=> Slave + +#ifndef NRFX_I2S_CONFIG_MASTER +#define NRFX_I2S_CONFIG_MASTER 0 +#endif + +// NRFX_I2S_CONFIG_FORMAT - Format + +// <0=> I2S +// <1=> Aligned + +#ifndef NRFX_I2S_CONFIG_FORMAT +#define NRFX_I2S_CONFIG_FORMAT 0 +#endif + +// NRFX_I2S_CONFIG_ALIGN - Alignment + +// <0=> Left +// <1=> Right + +#ifndef NRFX_I2S_CONFIG_ALIGN +#define NRFX_I2S_CONFIG_ALIGN 0 +#endif + +// NRFX_I2S_CONFIG_SWIDTH - Sample width (bits) + +// <0=> 8 +// <1=> 16 +// <2=> 24 + +#ifndef NRFX_I2S_CONFIG_SWIDTH +#define NRFX_I2S_CONFIG_SWIDTH 1 +#endif + +// NRFX_I2S_CONFIG_CHANNELS - Channels + +// <0=> Stereo +// <1=> Left +// <2=> Right + +#ifndef NRFX_I2S_CONFIG_CHANNELS +#define NRFX_I2S_CONFIG_CHANNELS 1 +#endif + +// NRFX_I2S_CONFIG_MCK_SETUP - MCK behavior + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 + +#ifndef NRFX_I2S_CONFIG_MCK_SETUP +#define NRFX_I2S_CONFIG_MCK_SETUP 536870912 +#endif + +// NRFX_I2S_CONFIG_RATIO - MCK/LRCK ratio + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x + +#ifndef NRFX_I2S_CONFIG_RATIO +#define NRFX_I2S_CONFIG_RATIO 2000 +#endif + +// NRFX_I2S_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_INFO_COLOR +#define NRFX_I2S_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR +#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver +//========================================================== +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif +// NRFX_LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#ifndef NRFX_LPCOMP_CONFIG_REFERENCE +#define NRFX_LPCOMP_CONFIG_REFERENCE 3 +#endif + +// NRFX_LPCOMP_CONFIG_DETECTION - Detection + +// <0=> Crossing +// <1=> Up +// <2=> Down + +#ifndef NRFX_LPCOMP_CONFIG_DETECTION +#define NRFX_LPCOMP_CONFIG_DETECTION 2 +#endif + +// NRFX_LPCOMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_LPCOMP_CONFIG_INPUT +#define NRFX_LPCOMP_CONFIG_INPUT 0 +#endif + +// NRFX_LPCOMP_CONFIG_HYST - Hysteresis + + +#ifndef NRFX_LPCOMP_CONFIG_HYST +#define NRFX_LPCOMP_CONFIG_HYST 0 +#endif + +// NRFX_LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR +#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR +#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver +//========================================================== +#ifndef NRFX_NFCT_ENABLED +#define NRFX_NFCT_ENABLED 0 +#endif +// NRFX_NFCT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_NFCT_CONFIG_IRQ_PRIORITY +#define NRFX_NFCT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED +#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_NFCT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL +#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_NFCT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_NFCT_CONFIG_INFO_COLOR +#define NRFX_NFCT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_NFCT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR +#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver +//========================================================== +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef NRFX_PDM_CONFIG_MODE +#define NRFX_PDM_CONFIG_MODE 1 +#endif + +// NRFX_PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef NRFX_PDM_CONFIG_EDGE +#define NRFX_PDM_CONFIG_EDGE 0 +#endif + +// NRFX_PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ +#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// NRFX_PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_INFO_COLOR +#define NRFX_PDM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR +#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver +//========================================================== +#ifndef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED 0 +#endif +// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN +#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV +#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator +//========================================================== +#ifndef NRFX_PPI_ENABLED +#define NRFX_PPI_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PPI_CONFIG_LOG_ENABLED +#define NRFX_PPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PPI_CONFIG_LOG_LEVEL +#define NRFX_PPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_INFO_COLOR +#define NRFX_PPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR +#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver +//========================================================== +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif +// NRFX_PWM0_ENABLED - Enable PWM0 instance + + +#ifndef NRFX_PWM0_ENABLED +#define NRFX_PWM0_ENABLED 0 +#endif + +// NRFX_PWM1_ENABLED - Enable PWM1 instance + + +#ifndef NRFX_PWM1_ENABLED +#define NRFX_PWM1_ENABLED 0 +#endif + +// NRFX_PWM2_ENABLED - Enable PWM2 instance + + +#ifndef NRFX_PWM2_ENABLED +#define NRFX_PWM2_ENABLED 0 +#endif + +// NRFX_PWM3_ENABLED - Enable PWM3 instance + + +#ifndef NRFX_PWM3_ENABLED +#define NRFX_PWM3_ENABLED 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz + +#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK +#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE +#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE +#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE +#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE +#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_INFO_COLOR +#define NRFX_PWM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR +#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver +//========================================================== +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef NRFX_QDEC_CONFIG_REPORTPER +#define NRFX_QDEC_CONFIG_REPORTPER 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef NRFX_QDEC_CONFIG_SAMPLEPER +#define NRFX_QDEC_CONFIG_SAMPLEPER 7 +#endif + +// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_A +#define NRFX_QDEC_CONFIG_PIO_A 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_B +#define NRFX_QDEC_CONFIG_PIO_B 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_LED +#define NRFX_QDEC_CONFIG_PIO_LED 31 +#endif + +// NRFX_QDEC_CONFIG_LEDPRE - LED pre +#ifndef NRFX_QDEC_CONFIG_LEDPRE +#define NRFX_QDEC_CONFIG_LEDPRE 511 +#endif + +// NRFX_QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef NRFX_QDEC_CONFIG_LEDPOL +#define NRFX_QDEC_CONFIG_LEDPOL 1 +#endif + +// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef NRFX_QDEC_CONFIG_DBFEN +#define NRFX_QDEC_CONFIG_DBFEN 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN +#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_INFO_COLOR +#define NRFX_QDEC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR +#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver +//========================================================== +#ifndef NRFX_QSPI_ENABLED +#define NRFX_QSPI_ENABLED 0 +#endif +// NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> + + +#ifndef NRFX_QSPI_CONFIG_SCK_DELAY +#define NRFX_QSPI_CONFIG_SCK_DELAY 1 +#endif + +// NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. +#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET +#define NRFX_QSPI_CONFIG_XIP_OFFSET 0 +#endif + +// NRFX_QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. + +// <0=> FastRead +// <1=> Read2O +// <2=> Read2IO +// <3=> Read4O +// <4=> Read4IO + +#ifndef NRFX_QSPI_CONFIG_READOC +#define NRFX_QSPI_CONFIG_READOC 0 +#endif + +// NRFX_QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. + +// <0=> PP +// <1=> PP2O +// <2=> PP4O +// <3=> PP4IO + +#ifndef NRFX_QSPI_CONFIG_WRITEOC +#define NRFX_QSPI_CONFIG_WRITEOC 0 +#endif + +// NRFX_QSPI_CONFIG_ADDRMODE - Addressing mode. + +// <0=> 24bit +// <1=> 32bit + +#ifndef NRFX_QSPI_CONFIG_ADDRMODE +#define NRFX_QSPI_CONFIG_ADDRMODE 0 +#endif + +// NRFX_QSPI_CONFIG_MODE - SPI mode. + +// <0=> Mode 0 +// <1=> Mode 1 + +#ifndef NRFX_QSPI_CONFIG_MODE +#define NRFX_QSPI_CONFIG_MODE 0 +#endif + +// NRFX_QSPI_CONFIG_FREQUENCY - Frequency divider. + +// <0=> 32MHz/1 +// <1=> 32MHz/2 +// <2=> 32MHz/3 +// <3=> 32MHz/4 +// <4=> 32MHz/5 +// <5=> 32MHz/6 +// <6=> 32MHz/7 +// <7=> 32MHz/8 +// <8=> 32MHz/9 +// <9=> 32MHz/10 +// <10=> 32MHz/11 +// <11=> 32MHz/12 +// <12=> 32MHz/13 +// <13=> 32MHz/14 +// <14=> 32MHz/15 +// <15=> 32MHz/16 + +#ifndef NRFX_QSPI_CONFIG_FREQUENCY +#define NRFX_QSPI_CONFIG_FREQUENCY 15 +#endif + +// NRFX_QSPI_PIN_SCK - SCK pin value. +#ifndef NRFX_QSPI_PIN_SCK +#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_CSN - CSN pin value. +#ifndef NRFX_QSPI_PIN_CSN +#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO0 - IO0 pin value. +#ifndef NRFX_QSPI_PIN_IO0 +#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO1 - IO1 pin value. +#ifndef NRFX_QSPI_PIN_IO1 +#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO2 - IO2 pin value. +#ifndef NRFX_QSPI_PIN_IO2 +#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO3 - IO3 pin value. +#ifndef NRFX_QSPI_PIN_IO3 +#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver +//========================================================== +#ifndef NRFX_RNG_ENABLED +#define NRFX_RNG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION +#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RNG_CONFIG_LOG_ENABLED +#define NRFX_RNG_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RNG_CONFIG_LOG_LEVEL +#define NRFX_RNG_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_INFO_COLOR +#define NRFX_RNG_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR +#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver +//========================================================== +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif +// NRFX_RTC0_ENABLED - Enable RTC0 instance + + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 0 +#endif + +// NRFX_RTC1_ENABLED - Enable RTC1 instance + + +#ifndef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED 0 +#endif + +// NRFX_RTC2_ENABLED - Enable RTC2 instance + + +#ifndef NRFX_RTC2_ENABLED +#define NRFX_RTC2_ENABLED 0 +#endif + +// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRFX_RTC_MAXIMUM_LATENCY_US +#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY +#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE +#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver +//========================================================== +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif +// NRFX_SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef NRFX_SAADC_CONFIG_RESOLUTION +#define NRFX_SAADC_CONFIG_RESOLUTION 1 +#endif + +// NRFX_SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE +#define NRFX_SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// NRFX_SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef NRFX_SAADC_CONFIG_LP_MODE +#define NRFX_SAADC_CONFIG_LP_MODE 0 +#endif + +// NRFX_SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_INFO_COLOR +#define NRFX_SAADC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR +#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver +//========================================================== +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif +// NRFX_SPIM0_ENABLED - Enable SPIM0 instance + + +#ifndef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 0 +#endif + +// NRFX_SPIM1_ENABLED - Enable SPIM1 instance + + +#ifndef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED 0 +#endif + +// NRFX_SPIM2_ENABLED - Enable SPIM2 instance + + +#ifndef NRFX_SPIM2_ENABLED +#define NRFX_SPIM2_ENABLED 0 +#endif + +// NRFX_SPIM3_ENABLED - Enable SPIM3 instance + + +#ifndef NRFX_SPIM3_ENABLED +#define NRFX_SPIM3_ENABLED 0 +#endif + +// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features + + +#ifndef NRFX_SPIM_EXTENDED_ENABLED +#define NRFX_SPIM_EXTENDED_ENABLED 0 +#endif + +// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPIM_MISO_PULL_CFG +#define NRFX_SPIM_MISO_PULL_CFG 1 +#endif + +// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver +//========================================================== +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif +// NRFX_SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED 0 +#endif + +// NRFX_SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef NRFX_SPIS1_ENABLED +#define NRFX_SPIS1_ENABLED 0 +#endif + +// NRFX_SPIS2_ENABLED - Enable SPIS2 instance + + +#ifndef NRFX_SPIS2_ENABLED +#define NRFX_SPIS2_ENABLED 0 +#endif + +// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_DEF +#define NRFX_SPIS_DEFAULT_DEF 255 +#endif + +// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_ORC +#define NRFX_SPIS_DEFAULT_ORC 255 +#endif + +// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver +//========================================================== +#ifndef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED 0 +#endif +// NRFX_SPI0_ENABLED - Enable SPI0 instance + + +#ifndef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 0 +#endif + +// NRFX_SPI1_ENABLED - Enable SPI1 instance + + +#ifndef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED 0 +#endif + +// NRFX_SPI2_ENABLED - Enable SPI2 instance + + +#ifndef NRFX_SPI2_ENABLED +#define NRFX_SPI2_ENABLED 0 +#endif + +// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPI_MISO_PULL_CFG +#define NRFX_SPI_MISO_PULL_CFG 1 +#endif + +// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator +//========================================================== +#ifndef NRFX_SWI_ENABLED +#define NRFX_SWI_ENABLED 0 +#endif +// NRFX_EGU_ENABLED - Enable EGU support + + +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver + + +#ifndef NRFX_SWI0_DISABLED +#define NRFX_SWI0_DISABLED 0 +#endif + +// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver + + +#ifndef NRFX_SWI1_DISABLED +#define NRFX_SWI1_DISABLED 0 +#endif + +// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver + + +#ifndef NRFX_SWI2_DISABLED +#define NRFX_SWI2_DISABLED 0 +#endif + +// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver + + +#ifndef NRFX_SWI3_DISABLED +#define NRFX_SWI3_DISABLED 0 +#endif + +// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver + + +#ifndef NRFX_SWI4_DISABLED +#define NRFX_SWI4_DISABLED 0 +#endif + +// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver + + +#ifndef NRFX_SWI5_DISABLED +#define NRFX_SWI5_DISABLED 0 +#endif + +// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SWI_CONFIG_LOG_ENABLED +#define NRFX_SWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SWI_CONFIG_LOG_LEVEL +#define NRFX_SWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_INFO_COLOR +#define NRFX_SWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR +#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver +//========================================================== +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif +// NRFX_TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED 0 +#endif + +// NRFX_TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED 0 +#endif + +// NRFX_TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED 0 +#endif + +// NRFX_TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef NRFX_TIMER3_ENABLED +#define NRFX_TIMER3_ENABLED 0 +#endif + +// NRFX_TIMER4_ENABLED - Enable TIMER4 instance + + +#ifndef NRFX_TIMER4_ENABLED +#define NRFX_TIMER4_ENABLED 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE +#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver +//========================================================== +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif +// NRFX_TWIM0_ENABLED - Enable TWIM0 instance + + +#ifndef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 0 +#endif + +// NRFX_TWIM1_ENABLED - Enable TWIM1 instance + + +#ifndef NRFX_TWIM1_ENABLED +#define NRFX_TWIM1_ENABLED 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver +//========================================================== +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif +// NRFX_TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED 0 +#endif + +// NRFX_TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef NRFX_TWIS1_ENABLED +#define NRFX_TWIS1_ENABLED 0 +#endif + +// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver +//========================================================== +#ifndef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED 0 +#endif +// NRFX_TWI0_ENABLED - Enable TWI0 instance + + +#ifndef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 0 +#endif + +// NRFX_TWI1_ENABLED - Enable TWI1 instance + + +#ifndef NRFX_TWI1_ENABLED +#define NRFX_TWI1_ENABLED 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver +//========================================================== +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif +// NRFX_UARTE0_ENABLED - Enable UARTE0 instance +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 0 +#endif + +// NRFX_UARTE1_ENABLED - Enable UARTE1 instance +#ifndef NRFX_UARTE1_ENABLED +#define NRFX_UARTE1_ENABLED 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC +#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY +#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <8388608=> 31250 baud +// <10289152=> 38400 baud +// <15007744=> 56000 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver +//========================================================== +#ifndef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED 0 +#endif +// NRFX_UART0_ENABLED - Enable UART0 instance +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC +#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY +#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3866624=> 14400 baud +// <5152768=> 19200 baud +// <7729152=> 28800 baud +// <8388608=> 31250 baud +// <10309632=> 38400 baud +// <15007744=> 56000 baud +// <15462400=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61845504=> 230400 baud +// <67108864=> 250000 baud +// <123695104=> 460800 baud +// <247386112=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#endif + +// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 4 +#endif + +// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver +//========================================================== +#ifndef NRFX_USBD_ENABLED +#define NRFX_USBD_ENABLED 0 +#endif +// NRFX_USBD_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY +#define NRFX_USBD_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_USBD_CONFIG_DMASCHEDULER_MODE - USBD DMA scheduler working scheme + +// <0=> Prioritized access +// <1=> Round Robin + +#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_MODE +#define NRFX_USBD_CONFIG_DMASCHEDULER_MODE 0 +#endif + +// NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers + + +// This option gives priority to isochronous transfers. +// Enabling it assures that isochronous transfers are always processed, +// even if multiple other transfers are pending. +// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm +// function is called, so the option is independent of the algorithm chosen. + +#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST +#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 +#endif + +// NRFX_USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready + + +// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent. +// Else, there will be no response. + +#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP +#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0 +#endif + +// + +// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver +//========================================================== +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef NRFX_WDT_CONFIG_BEHAVIOUR +#define NRFX_WDT_CONFIG_BEHAVIOUR 1 +#endif + +// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE +#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRF_CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver - legacy layer +//========================================================== +#ifndef NRF_CLOCK_ENABLED +#define NRF_CLOCK_ENABLED 0 +#endif +// CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef CLOCK_CONFIG_LF_SRC +#define CLOCK_CONFIG_LF_SRC 1 +#endif + +// CLOCK_CONFIG_LF_CAL_ENABLED - Calibration enable for LF Clock Source + + +#ifndef CLOCK_CONFIG_LF_CAL_ENABLED +#define CLOCK_CONFIG_LF_CAL_ENABLED 0 +#endif + +// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef CLOCK_CONFIG_IRQ_PRIORITY +#define CLOCK_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver - legacy layer +//========================================================== +#ifndef PDM_ENABLED +#define PDM_ENABLED 0 +#endif +// PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef PDM_CONFIG_MODE +#define PDM_CONFIG_MODE 1 +#endif + +// PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef PDM_CONFIG_EDGE +#define PDM_CONFIG_EDGE 0 +#endif + +// PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef PDM_CONFIG_CLOCK_FREQ +#define PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PDM_CONFIG_IRQ_PRIORITY +#define PDM_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// POWER_ENABLED - nrf_drv_power - POWER peripheral driver - legacy layer +//========================================================== +#ifndef POWER_ENABLED +#define POWER_ENABLED 0 +#endif +// POWER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef POWER_CONFIG_IRQ_PRIORITY +#define POWER_CONFIG_IRQ_PRIORITY 6 +#endif + +// POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef POWER_CONFIG_DEFAULT_DCDCEN +#define POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef POWER_CONFIG_DEFAULT_DCDCENHV +#define POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver - legacy layer + + +#ifndef PPI_ENABLED +#define PPI_ENABLED 0 +#endif + +// PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver - legacy layer +//========================================================== +#ifndef PWM_ENABLED +#define PWM_ENABLED 0 +#endif +// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN +#define PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN +#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN +#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN +#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz + +#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK +#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE +#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE +#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE +#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef PWM_DEFAULT_CONFIG_STEP_MODE +#define PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// PWM0_ENABLED - Enable PWM0 instance + + +#ifndef PWM0_ENABLED +#define PWM0_ENABLED 0 +#endif + +// PWM1_ENABLED - Enable PWM1 instance + + +#ifndef PWM1_ENABLED +#define PWM1_ENABLED 0 +#endif + +// PWM2_ENABLED - Enable PWM2 instance + + +#ifndef PWM2_ENABLED +#define PWM2_ENABLED 0 +#endif + +// PWM3_ENABLED - Enable PWM3 instance + + +#ifndef PWM3_ENABLED +#define PWM3_ENABLED 0 +#endif + +// + +// QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver - legacy layer +//========================================================== +#ifndef QDEC_ENABLED +#define QDEC_ENABLED 0 +#endif +// QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef QDEC_CONFIG_REPORTPER +#define QDEC_CONFIG_REPORTPER 0 +#endif + +// QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef QDEC_CONFIG_SAMPLEPER +#define QDEC_CONFIG_SAMPLEPER 7 +#endif + +// QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_A +#define QDEC_CONFIG_PIO_A 31 +#endif + +// QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_B +#define QDEC_CONFIG_PIO_B 31 +#endif + +// QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_LED +#define QDEC_CONFIG_PIO_LED 31 +#endif + +// QDEC_CONFIG_LEDPRE - LED pre +#ifndef QDEC_CONFIG_LEDPRE +#define QDEC_CONFIG_LEDPRE 511 +#endif + +// QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef QDEC_CONFIG_LEDPOL +#define QDEC_CONFIG_LEDPOL 1 +#endif + +// QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef QDEC_CONFIG_DBFEN +#define QDEC_CONFIG_DBFEN 0 +#endif + +// QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef QDEC_CONFIG_SAMPLE_INTEN +#define QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QDEC_CONFIG_IRQ_PRIORITY +#define QDEC_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver - legacy layer +//========================================================== +#ifndef QSPI_ENABLED +#define QSPI_ENABLED 0 +#endif +// QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> + + +#ifndef QSPI_CONFIG_SCK_DELAY +#define QSPI_CONFIG_SCK_DELAY 1 +#endif + +// QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. +#ifndef QSPI_CONFIG_XIP_OFFSET +#define QSPI_CONFIG_XIP_OFFSET 0 +#endif + +// QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. + +// <0=> FastRead +// <1=> Read2O +// <2=> Read2IO +// <3=> Read4O +// <4=> Read4IO + +#ifndef QSPI_CONFIG_READOC +#define QSPI_CONFIG_READOC 0 +#endif + +// QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. + +// <0=> PP +// <1=> PP2O +// <2=> PP4O +// <3=> PP4IO + +#ifndef QSPI_CONFIG_WRITEOC +#define QSPI_CONFIG_WRITEOC 0 +#endif + +// QSPI_CONFIG_ADDRMODE - Addressing mode. + +// <0=> 24bit +// <1=> 32bit + +#ifndef QSPI_CONFIG_ADDRMODE +#define QSPI_CONFIG_ADDRMODE 0 +#endif + +// QSPI_CONFIG_MODE - SPI mode. + +// <0=> Mode 0 +// <1=> Mode 1 + +#ifndef QSPI_CONFIG_MODE +#define QSPI_CONFIG_MODE 0 +#endif + +// QSPI_CONFIG_FREQUENCY - Frequency divider. + +// <0=> 32MHz/1 +// <1=> 32MHz/2 +// <2=> 32MHz/3 +// <3=> 32MHz/4 +// <4=> 32MHz/5 +// <5=> 32MHz/6 +// <6=> 32MHz/7 +// <7=> 32MHz/8 +// <8=> 32MHz/9 +// <9=> 32MHz/10 +// <10=> 32MHz/11 +// <11=> 32MHz/12 +// <12=> 32MHz/13 +// <13=> 32MHz/14 +// <14=> 32MHz/15 +// <15=> 32MHz/16 + +#ifndef QSPI_CONFIG_FREQUENCY +#define QSPI_CONFIG_FREQUENCY 15 +#endif + +// QSPI_PIN_SCK - SCK pin value. +#ifndef QSPI_PIN_SCK +#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_CSN - CSN pin value. +#ifndef QSPI_PIN_CSN +#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO0 - IO0 pin value. +#ifndef QSPI_PIN_IO0 +#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO1 - IO1 pin value. +#ifndef QSPI_PIN_IO1 +#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO2 - IO2 pin value. +#ifndef QSPI_PIN_IO2 +#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO3 - IO3 pin value. +#ifndef QSPI_PIN_IO3 +#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QSPI_CONFIG_IRQ_PRIORITY +#define QSPI_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver - legacy layer +//========================================================== +#ifndef RNG_ENABLED +#define RNG_ENABLED 0 +#endif +// RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef RNG_CONFIG_ERROR_CORRECTION +#define RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// RNG_CONFIG_POOL_SIZE - Pool size +#ifndef RNG_CONFIG_POOL_SIZE +#define RNG_CONFIG_POOL_SIZE 64 +#endif + +// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RNG_CONFIG_IRQ_PRIORITY +#define RNG_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver - legacy layer +//========================================================== +#ifndef RTC_ENABLED +#define RTC_ENABLED 0 +#endif +// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef RTC_DEFAULT_CONFIG_FREQUENCY +#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef RTC_DEFAULT_CONFIG_RELIABLE +#define RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// RTC0_ENABLED - Enable RTC0 instance + + +#ifndef RTC0_ENABLED +#define RTC0_ENABLED 0 +#endif + +// RTC1_ENABLED - Enable RTC1 instance + + +#ifndef RTC1_ENABLED +#define RTC1_ENABLED 0 +#endif + +// RTC2_ENABLED - Enable RTC2 instance + + +#ifndef RTC2_ENABLED +#define RTC2_ENABLED 0 +#endif + +// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRF_MAXIMUM_LATENCY_US +#define NRF_MAXIMUM_LATENCY_US 2000 +#endif + +// + +// SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver - legacy layer +//========================================================== +#ifndef SAADC_ENABLED +#define SAADC_ENABLED 0 +#endif +// SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef SAADC_CONFIG_RESOLUTION +#define SAADC_CONFIG_RESOLUTION 1 +#endif + +// SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef SAADC_CONFIG_OVERSAMPLE +#define SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef SAADC_CONFIG_LP_MODE +#define SAADC_CONFIG_LP_MODE 0 +#endif + +// SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SAADC_CONFIG_IRQ_PRIORITY +#define SAADC_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// SPIS_ENABLED - nrf_drv_spis - SPIS peripheral driver - legacy layer +//========================================================== +#ifndef SPIS_ENABLED +#define SPIS_ENABLED 0 +#endif +// SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// SPIS_DEFAULT_MODE - Mode + +// <0=> MODE_0 +// <1=> MODE_1 +// <2=> MODE_2 +// <3=> MODE_3 + +#ifndef SPIS_DEFAULT_MODE +#define SPIS_DEFAULT_MODE 0 +#endif + +// SPIS_DEFAULT_BIT_ORDER - SPIS default bit order + +// <0=> MSB first +// <1=> LSB first + +#ifndef SPIS_DEFAULT_BIT_ORDER +#define SPIS_DEFAULT_BIT_ORDER 0 +#endif + +// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef SPIS_DEFAULT_DEF +#define SPIS_DEFAULT_DEF 255 +#endif + +// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_ORC 255 +#endif + +// SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef SPIS0_ENABLED +#define SPIS0_ENABLED 0 +#endif + +// SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef SPIS1_ENABLED +#define SPIS1_ENABLED 0 +#endif + +// SPIS2_ENABLED - Enable SPIS2 instance + + +#ifndef SPIS2_ENABLED +#define SPIS2_ENABLED 0 +#endif + +// + +// SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver - legacy layer +//========================================================== +#ifndef SPI_ENABLED +#define SPI_ENABLED 0 +#endif +// SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRF_SPI_DRV_MISO_PULLUP_CFG - MISO PIN pull-up configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRF_SPI_DRV_MISO_PULLUP_CFG +#define NRF_SPI_DRV_MISO_PULLUP_CFG 1 +#endif + +// SPI0_ENABLED - Enable SPI0 instance +//========================================================== +#ifndef SPI0_ENABLED +#define SPI0_ENABLED 0 +#endif +// SPI0_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI0_USE_EASY_DMA +#define SPI0_USE_EASY_DMA 1 +#endif + +// + +// SPI1_ENABLED - Enable SPI1 instance +//========================================================== +#ifndef SPI1_ENABLED +#define SPI1_ENABLED 0 +#endif +// SPI1_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI1_USE_EASY_DMA +#define SPI1_USE_EASY_DMA 1 +#endif + +// + +// SPI2_ENABLED - Enable SPI2 instance +//========================================================== +#ifndef SPI2_ENABLED +#define SPI2_ENABLED 0 +#endif +// SPI2_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI2_USE_EASY_DMA +#define SPI2_USE_EASY_DMA 1 +#endif + +// + +// + +// TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver - legacy layer +//========================================================== +#ifndef TIMER_ENABLED +#define TIMER_ENABLED 0 +#endif +// TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY +#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef TIMER_DEFAULT_CONFIG_MODE +#define TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef TIMER0_ENABLED +#define TIMER0_ENABLED 0 +#endif + +// TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef TIMER1_ENABLED +#define TIMER1_ENABLED 0 +#endif + +// TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef TIMER2_ENABLED +#define TIMER2_ENABLED 0 +#endif + +// TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef TIMER3_ENABLED +#define TIMER3_ENABLED 0 +#endif + +// TIMER4_ENABLED - Enable TIMER4 instance + + +#ifndef TIMER4_ENABLED +#define TIMER4_ENABLED 0 +#endif + +// + +// TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver - legacy layer +//========================================================== +#ifndef TWIS_ENABLED +#define TWIS_ENABLED 0 +#endif +// TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef TWIS0_ENABLED +#define TWIS0_ENABLED 0 +#endif + +// TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef TWIS1_ENABLED +#define TWIS1_ENABLED 0 +#endif + +// TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef TWIS_NO_SYNC_MODE +#define TWIS_NO_SYNC_MODE 0 +#endif + +// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef TWIS_DEFAULT_CONFIG_ADDR0 +#define TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef TWIS_DEFAULT_CONFIG_ADDR1 +#define TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL +#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL +#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver - legacy layer +//========================================================== +#ifndef TWI_ENABLED +#define TWI_ENABLED 0 +#endif +// TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef TWI_DEFAULT_CONFIG_FREQUENCY +#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init + + +#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT +#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 +#endif + +// TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// TWI0_ENABLED - Enable TWI0 instance +//========================================================== +#ifndef TWI0_ENABLED +#define TWI0_ENABLED 0 +#endif +// TWI0_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI0_USE_EASY_DMA +#define TWI0_USE_EASY_DMA 0 +#endif + +// + +// TWI1_ENABLED - Enable TWI1 instance +//========================================================== +#ifndef TWI1_ENABLED +#define TWI1_ENABLED 0 +#endif +// TWI1_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI1_USE_EASY_DMA +#define TWI1_USE_EASY_DMA 0 +#endif + +// + +// + +// UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver - legacy layer +//========================================================== +#ifndef UART_ENABLED +#define UART_ENABLED 0 +#endif +// UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef UART_DEFAULT_CONFIG_HWFC +#define UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef UART_DEFAULT_CONFIG_PARITY +#define UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef UART_DEFAULT_CONFIG_BAUDRATE +#define UART_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA + + +#ifndef UART_EASY_DMA_SUPPORT +#define UART_EASY_DMA_SUPPORT 1 +#endif + +// UART_LEGACY_SUPPORT - Driver supporting Legacy mode + + +#ifndef UART_LEGACY_SUPPORT +#define UART_LEGACY_SUPPORT 1 +#endif + +// UART0_ENABLED - Enable UART0 instance +//========================================================== +#ifndef UART0_ENABLED +#define UART0_ENABLED 0 +#endif +// UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA + + +#ifndef UART0_CONFIG_USE_EASY_DMA +#define UART0_CONFIG_USE_EASY_DMA 1 +#endif + +// + +// UART1_ENABLED - Enable UART1 instance +//========================================================== +#ifndef UART1_ENABLED +#define UART1_ENABLED 0 +#endif +// + +// + +// USBD_ENABLED - nrf_drv_usbd - Software Component +//========================================================== +#ifndef USBD_ENABLED +#define USBD_ENABLED 0 +#endif +// USBD_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef USBD_CONFIG_IRQ_PRIORITY +#define USBD_CONFIG_IRQ_PRIORITY 6 +#endif + +// USBD_CONFIG_DMASCHEDULER_MODE - USBD SMA scheduler working scheme + +// <0=> Prioritized access +// <1=> Round Robin + +#ifndef USBD_CONFIG_DMASCHEDULER_MODE +#define USBD_CONFIG_DMASCHEDULER_MODE 0 +#endif + +// USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers + + +// This option gives priority to isochronous transfers. +// Enabling it assures that isochronous transfers are always processed, +// even if multiple other transfers are pending. +// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm +// function is called, so the option is independent of the algorithm chosen. + +#ifndef USBD_CONFIG_DMASCHEDULER_ISO_BOOST +#define USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 +#endif + +// USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready + + +// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent. +// Else, there will be no response. +// NOTE: This option does not work on Engineering A chip. + +#ifndef USBD_CONFIG_ISO_IN_ZLP +#define USBD_CONFIG_ISO_IN_ZLP 0 +#endif + +// + +// WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver - legacy layer +//========================================================== +#ifndef WDT_ENABLED +#define WDT_ENABLED 0 +#endif +// WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef WDT_CONFIG_BEHAVIOUR +#define WDT_CONFIG_BEHAVIOUR 1 +#endif + +// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef WDT_CONFIG_RELOAD_VALUE +#define WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef WDT_CONFIG_IRQ_PRIORITY +#define WDT_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// +//========================================================== + +// nRF_Drivers_External + +//========================================================== +// NRF_TWI_SENSOR_ENABLED - nrf_twi_sensor - nRF TWI Sensor module + + +#ifndef NRF_TWI_SENSOR_ENABLED +#define NRF_TWI_SENSOR_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Libraries + +//========================================================== +// APP_GPIOTE_ENABLED - app_gpiote - GPIOTE events dispatcher + + +#ifndef APP_GPIOTE_ENABLED +#define APP_GPIOTE_ENABLED 0 +#endif + +// APP_PWM_ENABLED - app_pwm - PWM functionality + + +#ifndef APP_PWM_ENABLED +#define APP_PWM_ENABLED 0 +#endif + +// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler +//========================================================== +#ifndef APP_SCHEDULER_ENABLED +#define APP_SCHEDULER_ENABLED 0 +#endif +// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature + + +#ifndef APP_SCHEDULER_WITH_PAUSE +#define APP_SCHEDULER_WITH_PAUSE 0 +#endif + +// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling + + +#ifndef APP_SCHEDULER_WITH_PROFILER +#define APP_SCHEDULER_WITH_PROFILER 0 +#endif + +// + +// APP_SDCARD_ENABLED - app_sdcard - SD/MMC card support using SPI +//========================================================== +#ifndef APP_SDCARD_ENABLED +#define APP_SDCARD_ENABLED 0 +#endif +// APP_SDCARD_SPI_INSTANCE - SPI instance used + +// <0=> 0 +// <1=> 1 +// <2=> 2 + +#ifndef APP_SDCARD_SPI_INSTANCE +#define APP_SDCARD_SPI_INSTANCE 0 +#endif + +// APP_SDCARD_FREQ_INIT - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef APP_SDCARD_FREQ_INIT +#define APP_SDCARD_FREQ_INIT 67108864 +#endif + +// APP_SDCARD_FREQ_DATA - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef APP_SDCARD_FREQ_DATA +#define APP_SDCARD_FREQ_DATA 1073741824 +#endif + +// + +// APP_TIMER_ENABLED - app_timer - Application timer functionality +//========================================================== +#ifndef APP_TIMER_ENABLED +#define APP_TIMER_ENABLED 0 +#endif +// APP_TIMER_CONFIG_RTC_FREQUENCY - Configure RTC prescaler. + +// <0=> 32768 Hz +// <1=> 16384 Hz +// <3=> 8192 Hz +// <7=> 4096 Hz +// <15=> 2048 Hz +// <31=> 1024 Hz + +#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY +#define APP_TIMER_CONFIG_RTC_FREQUENCY 1 +#endif + +// APP_TIMER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY +#define APP_TIMER_CONFIG_IRQ_PRIORITY 6 +#endif + +// APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. +// Size of the queue depends on how many timers are used +// in the system, how often timers are started and overall +// system latency. If queue size is too small app_timer calls +// will fail. + +#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE +#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10 +#endif + +// APP_TIMER_CONFIG_USE_SCHEDULER - Enable scheduling app_timer events to app_scheduler + + +#ifndef APP_TIMER_CONFIG_USE_SCHEDULER +#define APP_TIMER_CONFIG_USE_SCHEDULER 0 +#endif + +// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on + + +// If option is enabled RTC is kept running even if there is no active timers. +// This option can be used when app_timer is used for timestamping. + +#ifndef APP_TIMER_KEEPS_RTC_ACTIVE +#define APP_TIMER_KEEPS_RTC_ACTIVE 0 +#endif + +// APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event. +// Maximum possible timeout that can be set is reduced by safe window. +// Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS. +// Since RTC is not stopped when processor is halted in debugging session, this value +// must cover it if debugging is needed. It is possible to halt processor for APP_TIMER_SAFE_WINDOW_MS +// without corrupting app_timer behavior. + +#ifndef APP_TIMER_SAFE_WINDOW_MS +#define APP_TIMER_SAFE_WINDOW_MS 300000 +#endif + +// App Timer Legacy configuration - Legacy configuration. + +//========================================================== +// APP_TIMER_WITH_PROFILER - Enable app_timer profiling + + +#ifndef APP_TIMER_WITH_PROFILER +#define APP_TIMER_WITH_PROFILER 0 +#endif + +// APP_TIMER_CONFIG_SWI_NUMBER - Configure SWI instance used. + + +#ifndef APP_TIMER_CONFIG_SWI_NUMBER +#define APP_TIMER_CONFIG_SWI_NUMBER 0 +#endif + +// +//========================================================== + +// + +// APP_USBD_AUDIO_ENABLED - app_usbd_audio - USB AUDIO class + + +#ifndef APP_USBD_AUDIO_ENABLED +#define APP_USBD_AUDIO_ENABLED 0 +#endif + +// APP_USBD_ENABLED - app_usbd - USB Device library +//========================================================== +#ifndef APP_USBD_ENABLED +#define APP_USBD_ENABLED 0 +#endif +// APP_USBD_VID - Vendor ID. <0x0000-0xFFFF> + + +// Note: This value is not editable in Configuration Wizard. +// Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/ + +#ifndef APP_USBD_VID +#define APP_USBD_VID 0 +#endif + +// APP_USBD_PID - Product ID. <0x0000-0xFFFF> + + +// Note: This value is not editable in Configuration Wizard. +// Selected Product ID + +#ifndef APP_USBD_PID +#define APP_USBD_PID 0 +#endif + +// APP_USBD_DEVICE_VER_MAJOR - Major device version <0-99> + + +// Major device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MAJOR +#define APP_USBD_DEVICE_VER_MAJOR 1 +#endif + +// APP_USBD_DEVICE_VER_MINOR - Minor device version <0-9> + + +// Minor device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MINOR +#define APP_USBD_DEVICE_VER_MINOR 0 +#endif + +// APP_USBD_DEVICE_VER_SUB - Sub-minor device version <0-9> + + +// Sub-minor device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_SUB +#define APP_USBD_DEVICE_VER_SUB 0 +#endif + +// APP_USBD_CONFIG_SELF_POWERED - Self-powered device, as opposed to bus-powered. + + +#ifndef APP_USBD_CONFIG_SELF_POWERED +#define APP_USBD_CONFIG_SELF_POWERED 1 +#endif + +// APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps. <0-500> + + +#ifndef APP_USBD_CONFIG_MAX_POWER +#define APP_USBD_CONFIG_MAX_POWER 100 +#endif + +// APP_USBD_CONFIG_POWER_EVENTS_PROCESS - Process power events. + + +// Enable processing power events in USB event handler. + +#ifndef APP_USBD_CONFIG_POWER_EVENTS_PROCESS +#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1 +#endif + +// APP_USBD_CONFIG_EVENT_QUEUE_ENABLE - Enable event queue. + +// This is the default configuration when all the events are placed into internal queue. +// Disable it when an external queue is used like app_scheduler or if you wish to process all events inside interrupts. +// Processing all events from the interrupt level adds requirement not to call any functions that modifies the USBD library state from the context higher than USB interrupt context. +// Functions that modify USBD state are functions for sleep, wakeup, start, stop, enable, and disable. +//========================================================== +#ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE +#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1 +#endif +// APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue. <16-64> + + +// The size of the queue for the events that would be processed in the main loop. + +#ifndef APP_USBD_CONFIG_EVENT_QUEUE_SIZE +#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32 +#endif + +// APP_USBD_CONFIG_SOF_HANDLING_MODE - Change SOF events handling mode. + + +// Normal queue - SOF events are pushed normally into the event queue. +// Compress queue - SOF events are counted and binded with other events or executed when the queue is empty. +// This prevents the queue from filling up with SOF events. +// Interrupt - SOF events are processed in interrupt. +// <0=> Normal queue +// <1=> Compress queue +// <2=> Interrupt + +#ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE +#define APP_USBD_CONFIG_SOF_HANDLING_MODE 1 +#endif + +// + +// APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE - Provide a function that generates timestamps for logs based on the current SOF. + + +// The function app_usbd_sof_timestamp_get is implemented if the logger is enabled. +// Use it when initializing the logger. +// SOF processing is always enabled when this configuration parameter is active. +// Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED. +// This means that it works even if the logging in this very module is disabled. + +#ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE +#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0 +#endif + +// APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor. <31-254> + + +// 31 characters can be stored in the internal USB buffer used for transfers. +// Any value higher than 31 creates an additional buffer just for descriptor strings. + +#ifndef APP_USBD_CONFIG_DESC_STRING_SIZE +#define APP_USBD_CONFIG_DESC_STRING_SIZE 31 +#endif + +// APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED - Enable UTF8 conversion. + + +// Enable UTF8-encoded characters. In normal processing, only ASCII characters are available. + +#ifndef APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED +#define APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED 0 +#endif + +// APP_USBD_STRINGS_LANGIDS - Supported languages identifiers. + +// Note: This value is not editable in Configuration Wizard. +// Comma-separated list of supported languages. +#ifndef APP_USBD_STRINGS_LANGIDS +#define APP_USBD_STRINGS_LANGIDS APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US) +#endif + +// APP_USBD_STRING_ID_MANUFACTURER - Define manufacturer string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_MANUFACTURER +#define APP_USBD_STRING_ID_MANUFACTURER 1 +#endif +// APP_USBD_STRINGS_MANUFACTURER_EXTERN - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN +#define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0 +#endif + +// APP_USBD_STRINGS_MANUFACTURER - String descriptor for the manufacturer name. + +// Note: This value is not editable in Configuration Wizard. +// Comma-separated list of manufacturer names for each defined language. +// Use @ref APP_USBD_STRING_DESC macro to create string descriptor from a NULL-terminated string. +// Use @ref APP_USBD_STRING_RAW8_DESC macro to create string descriptor from comma-separated uint8_t values. +// Use @ref APP_USBD_STRING_RAW16_DESC macro to create string descriptor from comma-separated uint16_t values. +// Alternatively, configure the macro to point to any internal variable pointer that already contains the descriptor. +// Setting string to NULL disables that string. +// The order of manufacturer names must be the same like in @ref APP_USBD_STRINGS_LANGIDS. +#ifndef APP_USBD_STRINGS_MANUFACTURER +#define APP_USBD_STRINGS_MANUFACTURER APP_USBD_STRING_DESC("Nordic Semiconductor") +#endif + +// + +// APP_USBD_STRING_ID_PRODUCT - Define product string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_PRODUCT +#define APP_USBD_STRING_ID_PRODUCT 2 +#endif +// APP_USBD_STRINGS_PRODUCT_EXTERN - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRINGS_PRODUCT_EXTERN +#define APP_USBD_STRINGS_PRODUCT_EXTERN 0 +#endif + +// APP_USBD_STRINGS_PRODUCT - String descriptor for the product name. + +// Note: This value is not editable in Configuration Wizard. +// List of product names that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRINGS_PRODUCT +#define APP_USBD_STRINGS_PRODUCT APP_USBD_STRING_DESC("nRF52 USB Product") +#endif + +// + +// APP_USBD_STRING_ID_SERIAL - Define serial number string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_SERIAL +#define APP_USBD_STRING_ID_SERIAL 3 +#endif +// APP_USBD_STRING_SERIAL_EXTERN - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRING_SERIAL_EXTERN +#define APP_USBD_STRING_SERIAL_EXTERN 0 +#endif + +// APP_USBD_STRING_SERIAL - String descriptor for the serial number. + +// Note: This value is not editable in Configuration Wizard. +// Serial number that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRING_SERIAL +#define APP_USBD_STRING_SERIAL APP_USBD_STRING_DESC("000000000000") +#endif + +// + +// APP_USBD_STRING_ID_CONFIGURATION - Define configuration string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_CONFIGURATION +#define APP_USBD_STRING_ID_CONFIGURATION 4 +#endif +// APP_USBD_STRING_CONFIGURATION_EXTERN - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable. + + +#ifndef APP_USBD_STRING_CONFIGURATION_EXTERN +#define APP_USBD_STRING_CONFIGURATION_EXTERN 0 +#endif + +// APP_USBD_STRINGS_CONFIGURATION - String descriptor for the device configuration. + +// Note: This value is not editable in Configuration Wizard. +// Configuration string that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRINGS_CONFIGURATION +#define APP_USBD_STRINGS_CONFIGURATION APP_USBD_STRING_DESC("Default configuration") +#endif + +// + +// APP_USBD_STRINGS_USER - Default values for user strings. + +// Note: This value is not editable in Configuration Wizard. +// This value stores all application specific user strings with the default initialization. +// The setup is done by X-macros. +// Expected macro parameters: +// @code +// X(mnemonic, [=str_idx], ...) +// @endcode +// - @c mnemonic: Mnemonic of the string descriptor that would be added to +// @ref app_usbd_string_desc_idx_t enumerator. +// - @c str_idx : String index value, can be set or left empty. +// For example, WinUSB driver requires descriptor to be present on 0xEE index. +// Then use X(USBD_STRING_WINUSB, =0xEE, (APP_USBD_STRING_DESC(...))) +// - @c ... : List of string descriptors for each defined language. +#ifndef APP_USBD_STRINGS_USER +#define APP_USBD_STRINGS_USER X(APP_USER_1, , APP_USBD_STRING_DESC("User 1")) +#endif + +// + +// APP_USBD_HID_ENABLED - app_usbd_hid - USB HID class +//========================================================== +#ifndef APP_USBD_HID_ENABLED +#define APP_USBD_HID_ENABLED 0 +#endif +// APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class. <0-255> + + +// 0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification. + +#ifndef APP_USBD_HID_DEFAULT_IDLE_RATE +#define APP_USBD_HID_DEFAULT_IDLE_RATE 0 +#endif + +// APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table. <1-255> + + +// Must be higher than the highest report ID used. + +#ifndef APP_USBD_HID_REPORT_IDLE_TABLE_SIZE +#define APP_USBD_HID_REPORT_IDLE_TABLE_SIZE 4 +#endif + +// + +// APP_USBD_HID_GENERIC_ENABLED - app_usbd_hid_generic - USB HID generic + + +#ifndef APP_USBD_HID_GENERIC_ENABLED +#define APP_USBD_HID_GENERIC_ENABLED 0 +#endif + +// APP_USBD_HID_KBD_ENABLED - app_usbd_hid_kbd - USB HID keyboard + + +#ifndef APP_USBD_HID_KBD_ENABLED +#define APP_USBD_HID_KBD_ENABLED 0 +#endif + +// APP_USBD_HID_MOUSE_ENABLED - app_usbd_hid_mouse - USB HID mouse + + +#ifndef APP_USBD_HID_MOUSE_ENABLED +#define APP_USBD_HID_MOUSE_ENABLED 0 +#endif + +// APP_USBD_MSC_ENABLED - app_usbd_msc - USB MSC class + + +#ifndef APP_USBD_MSC_ENABLED +#define APP_USBD_MSC_ENABLED 0 +#endif + +// CRC16_ENABLED - crc16 - CRC16 calculation routines + + +#ifndef CRC16_ENABLED +#define CRC16_ENABLED 0 +#endif + +// CRC32_ENABLED - crc32 - CRC32 calculation routines + + +#ifndef CRC32_ENABLED +#define CRC32_ENABLED 0 +#endif + +// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library + + +#ifndef ECC_ENABLED +#define ECC_ENABLED 0 +#endif + +// FDS_ENABLED - fds - Flash data storage module +//========================================================== +#ifndef FDS_ENABLED +#define FDS_ENABLED 0 +#endif +// Pages - Virtual page settings + +// Configure the number of virtual pages to use and their size. +//========================================================== +// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. +// One of the virtual pages is reserved by the system for garbage collection. +// Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection. +// The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. + +#ifndef FDS_VIRTUAL_PAGES +#define FDS_VIRTUAL_PAGES 3 +#endif + +// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual flash page. + + +// Expressed in number of 4-byte words. +// By default, a virtual page is the same size as a physical page. +// The size of a virtual page must be a multiple of the size of a physical page. +// <1024=> 1024 +// <2048=> 2048 + +#ifndef FDS_VIRTUAL_PAGE_SIZE +#define FDS_VIRTUAL_PAGE_SIZE 1024 +#endif + +// FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules. +// FDS module stores its data in the last pages of the flash memory. +// By setting this value, you can move flash end address used by the FDS. +// As a result the reserved space can be used by other modules. + +#ifndef FDS_VIRTUAL_PAGES_RESERVED +#define FDS_VIRTUAL_PAGES_RESERVED 0 +#endif + +// +//========================================================== + +// Backend - Backend configuration + +// Configure which nrf_fstorage backend is used by FDS to write to flash. +//========================================================== +// FDS_BACKEND - FDS flash backend. + + +// NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present. +// NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice. +// <1=> NRF_FSTORAGE_NVMC +// <2=> NRF_FSTORAGE_SD + +#ifndef FDS_BACKEND +#define FDS_BACKEND 2 +#endif + +// +//========================================================== + +// Queue - Queue settings + +//========================================================== +// FDS_OP_QUEUE_SIZE - Size of the internal queue. +// Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors. + +#ifndef FDS_OP_QUEUE_SIZE +#define FDS_OP_QUEUE_SIZE 4 +#endif + +// +//========================================================== + +// CRC - CRC functionality + +//========================================================== +// FDS_CRC_CHECK_ON_READ - Enable CRC checks. + +// Save a record's CRC when it is written to flash and check it when the record is opened. +// Records with an incorrect CRC can still be 'seen' by the user using FDS functions, but they cannot be opened. +// Additionally, they will not be garbage collected until they are deleted. +//========================================================== +#ifndef FDS_CRC_CHECK_ON_READ +#define FDS_CRC_CHECK_ON_READ 0 +#endif +// FDS_CRC_CHECK_ON_WRITE - Perform a CRC check on newly written records. + + +// Perform a CRC check on newly written records. +// This setting can be used to make sure that the record data was not altered while being written to flash. +// <1=> Enabled +// <0=> Disabled + +#ifndef FDS_CRC_CHECK_ON_WRITE +#define FDS_CRC_CHECK_ON_WRITE 0 +#endif + +// + +// +//========================================================== + +// Users - Number of users + +//========================================================== +// FDS_MAX_USERS - Maximum number of callbacks that can be registered. +#ifndef FDS_MAX_USERS +#define FDS_MAX_USERS 4 +#endif + +// +//========================================================== + +// + +// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release + + +#ifndef HARDFAULT_HANDLER_ENABLED +#define HARDFAULT_HANDLER_ENABLED 0 +#endif + +// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI +//========================================================== +#ifndef HCI_MEM_POOL_ENABLED +#define HCI_MEM_POOL_ENABLED 0 +#endif +// HCI_TX_BUF_SIZE - TX buffer size in bytes. +#ifndef HCI_TX_BUF_SIZE +#define HCI_TX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_SIZE - RX buffer size in bytes. +#ifndef HCI_RX_BUF_SIZE +#define HCI_RX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. +#ifndef HCI_RX_BUF_QUEUE_SIZE +#define HCI_RX_BUF_QUEUE_SIZE 4 +#endif + +// + +// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI +//========================================================== +#ifndef HCI_SLIP_ENABLED +#define HCI_SLIP_ENABLED 0 +#endif +// HCI_UART_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef HCI_UART_BAUDRATE +#define HCI_UART_BAUDRATE 30801920 +#endif + +// HCI_UART_FLOW_CONTROL - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef HCI_UART_FLOW_CONTROL +#define HCI_UART_FLOW_CONTROL 0 +#endif + +// HCI_UART_RX_PIN - UART RX pin +#ifndef HCI_UART_RX_PIN +#define HCI_UART_RX_PIN 31 +#endif + +// HCI_UART_TX_PIN - UART TX pin +#ifndef HCI_UART_TX_PIN +#define HCI_UART_TX_PIN 31 +#endif + +// HCI_UART_RTS_PIN - UART RTS pin +#ifndef HCI_UART_RTS_PIN +#define HCI_UART_RTS_PIN 31 +#endif + +// HCI_UART_CTS_PIN - UART CTS pin +#ifndef HCI_UART_CTS_PIN +#define HCI_UART_CTS_PIN 31 +#endif + +// + +// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport +//========================================================== +#ifndef HCI_TRANSPORT_ENABLED +#define HCI_TRANSPORT_ENABLED 0 +#endif +// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. +#ifndef HCI_MAX_PACKET_SIZE_IN_BITS +#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 +#endif + +// + +// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module + + +#ifndef LED_SOFTBLINK_ENABLED +#define LED_SOFTBLINK_ENABLED 0 +#endif + +// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module + + +#ifndef LOW_POWER_PWM_ENABLED +#define LOW_POWER_PWM_ENABLED 0 +#endif + +// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator +//========================================================== +#ifndef MEM_MANAGER_ENABLED +#define MEM_MANAGER_ENABLED 0 +#endif +// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> + + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT +#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 +#endif + +// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. +// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE +#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> + + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT +#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. +// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE +#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> + + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT +#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. +// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE +#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra large' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra large' block. +// Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra small' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra small' block. +// Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32 +#endif + +// MEM_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef MEM_MANAGER_CONFIG_LOG_ENABLED +#define MEM_MANAGER_CONFIG_LOG_ENABLED 0 +#endif +// MEM_MANAGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef MEM_MANAGER_CONFIG_LOG_LEVEL +#define MEM_MANAGER_CONFIG_LOG_LEVEL 3 +#endif + +// MEM_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MEM_MANAGER_CONFIG_INFO_COLOR +#define MEM_MANAGER_CONFIG_INFO_COLOR 0 +#endif + +// MEM_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR +#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. + + +#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK +#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 +#endif + +// + +// NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module +//========================================================== +#ifndef NRF_BALLOC_ENABLED +#define NRF_BALLOC_ENABLED 1 +#endif +// NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED +#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS +#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS +#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED - Enables basic checks in this module. + + +#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED +#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED - Enables double memory free check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED - Enables free memory corruption check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef NRF_BALLOC_CLI_CMDS +#define NRF_BALLOC_CLI_CMDS 0 +#endif + +// + +// + +// NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module +//========================================================== +#ifndef NRF_CSENSE_ENABLED +#define NRF_CSENSE_ENABLED 0 +#endif +// NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. +#ifndef NRF_CSENSE_PAD_HYSTERESIS +#define NRF_CSENSE_PAD_HYSTERESIS 15 +#endif + +// NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. +#ifndef NRF_CSENSE_PAD_DEVIATION +#define NRF_CSENSE_PAD_DEVIATION 70 +#endif + +// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. +#ifndef NRF_CSENSE_MIN_PAD_VALUE +#define NRF_CSENSE_MIN_PAD_VALUE 20 +#endif + +// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. +#ifndef NRF_CSENSE_MAX_PADS_NUMBER +#define NRF_CSENSE_MAX_PADS_NUMBER 20 +#endif + +// NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. +#ifndef NRF_CSENSE_MAX_VALUE +#define NRF_CSENSE_MAX_VALUE 1000 +#endif + +// NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. +// This is used when capacitive sensor does not use COMP. + +#ifndef NRF_CSENSE_OUTPUT_PIN +#define NRF_CSENSE_OUTPUT_PIN 26 +#endif + +// + +// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module +//========================================================== +#ifndef NRF_DRV_CSENSE_ENABLED +#define NRF_DRV_CSENSE_ENABLED 0 +#endif +// USE_COMP - Use the comparator to implement the capacitive sensor driver. + +// Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation. +//========================================================== +#ifndef USE_COMP +#define USE_COMP 0 +#endif +// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). +#ifndef TIMER0_FOR_CSENSE +#define TIMER0_FOR_CSENSE 1 +#endif + +// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). +#ifndef TIMER1_FOR_CSENSE +#define TIMER1_FOR_CSENSE 2 +#endif + +// MEASUREMENT_PERIOD - Single measurement period. +// Time of a single measurement can be calculated as +// T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). +// I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad. + +#ifndef MEASUREMENT_PERIOD +#define MEASUREMENT_PERIOD 20 +#endif + +// + +// + +// NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library +//========================================================== +#ifndef NRF_FSTORAGE_ENABLED +#define NRF_FSTORAGE_ENABLED 0 +#endif +// nrf_fstorage - Common settings + +// Common settings to all fstorage implementations +//========================================================== +// NRF_FSTORAGE_PARAM_CHECK_DISABLED - Disable user input validation + + +// If selected, use ASSERT to validate user input. +// This effectively removes user input validation in production code. +// Recommended setting: OFF, only enable this setting if size is a major concern. + +#ifndef NRF_FSTORAGE_PARAM_CHECK_DISABLED +#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0 +#endif + +// +//========================================================== + +// nrf_fstorage_sd - Implementation using the SoftDevice + +// Configuration options for the fstorage implementation using the SoftDevice +//========================================================== +// NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations +// Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM. + +#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE +#define NRF_FSTORAGE_SD_QUEUE_SIZE 4 +#endif + +// NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy +// Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error. +// The SoftDevice might fail to schedule flash access due to high BLE activity. + +#ifndef NRF_FSTORAGE_SD_MAX_RETRIES +#define NRF_FSTORAGE_SD_MAX_RETRIES 8 +#endif + +// NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation +// This value must be a multiple of four. +// Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity. +// This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write. +// That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs. + +#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE +#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096 +#endif + +// +//========================================================== + +// + +// NRF_GFX_ENABLED - nrf_gfx - GFX module + + +#ifndef NRF_GFX_ENABLED +#define NRF_GFX_ENABLED 0 +#endif + +// NRF_MEMOBJ_ENABLED - nrf_memobj - Linked memory allocator module + + +#ifndef NRF_MEMOBJ_ENABLED +#define NRF_MEMOBJ_ENABLED 1 +#endif + +// NRF_PWR_MGMT_ENABLED - nrf_pwr_mgmt - Power management module +//========================================================== +#ifndef NRF_PWR_MGMT_ENABLED +#define NRF_PWR_MGMT_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module. + +// Selected pin will be set when CPU is in sleep mode. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED +#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0 +#endif +// NRF_PWR_MGMT_SLEEP_DEBUG_PIN - Pin number + +// <0=> 0 (P0.0) +// <1=> 1 (P0.1) +// <2=> 2 (P0.2) +// <3=> 3 (P0.3) +// <4=> 4 (P0.4) +// <5=> 5 (P0.5) +// <6=> 6 (P0.6) +// <7=> 7 (P0.7) +// <8=> 8 (P0.8) +// <9=> 9 (P0.9) +// <10=> 10 (P0.10) +// <11=> 11 (P0.11) +// <12=> 12 (P0.12) +// <13=> 13 (P0.13) +// <14=> 14 (P0.14) +// <15=> 15 (P0.15) +// <16=> 16 (P0.16) +// <17=> 17 (P0.17) +// <18=> 18 (P0.18) +// <19=> 19 (P0.19) +// <20=> 20 (P0.20) +// <21=> 21 (P0.21) +// <22=> 22 (P0.22) +// <23=> 23 (P0.23) +// <24=> 24 (P0.24) +// <25=> 25 (P0.25) +// <26=> 26 (P0.26) +// <27=> 27 (P0.27) +// <28=> 28 (P0.28) +// <29=> 29 (P0.29) +// <30=> 30 (P0.30) +// <31=> 31 (P0.31) +// <32=> 32 (P1.0) +// <33=> 33 (P1.1) +// <34=> 34 (P1.2) +// <35=> 35 (P1.3) +// <36=> 36 (P1.4) +// <37=> 37 (P1.5) +// <38=> 38 (P1.6) +// <39=> 39 (P1.7) +// <40=> 40 (P1.8) +// <41=> 41 (P1.9) +// <42=> 42 (P1.10) +// <43=> 43 (P1.11) +// <44=> 44 (P1.12) +// <45=> 45 (P1.13) +// <46=> 46 (P1.14) +// <47=> 47 (P1.15) +// <4294967295=> Not connected + +#ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN +#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED - Enables CPU usage monitor. + + +// Module will trace percentage of CPU usage in one second intervals. + +#ifndef NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED +#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0 +#endif + +// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - Enable standby timeout. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED +#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds). +// Shutdown procedure will begin no earlier than after this number of seconds. + +#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S +#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED - Enables FPU event cleaning. + + +#ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED +#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0 +#endif + +// NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY - Blocked shutdown procedure will be retried every second. + + +#ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY +#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0 +#endif + +// NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - Module will use @ref app_scheduler. + + +#ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER +#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0 +#endif + +// NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers. +// The number of stages of the shutdown process. + +#ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT +#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3 +#endif + +// + +// NRF_QUEUE_ENABLED - nrf_queue - Queue module +//========================================================== +#ifndef NRF_QUEUE_ENABLED +#define NRF_QUEUE_ENABLED 0 +#endif +// NRF_QUEUE_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef NRF_QUEUE_CLI_CMDS +#define NRF_QUEUE_CLI_CMDS 0 +#endif + +// + +// NRF_SECTION_ITER_ENABLED - nrf_section_iter - Section iterator + + +#ifndef NRF_SECTION_ITER_ENABLED +#define NRF_SECTION_ITER_ENABLED 1 +#endif + +// NRF_SORTLIST_ENABLED - nrf_sortlist - Sorted list + + +#ifndef NRF_SORTLIST_ENABLED +#define NRF_SORTLIST_ENABLED 1 +#endif + +// NRF_SPI_MNGR_ENABLED - nrf_spi_mngr - SPI transaction manager + + +#ifndef NRF_SPI_MNGR_ENABLED +#define NRF_SPI_MNGR_ENABLED 0 +#endif + +// NRF_STRERROR_ENABLED - nrf_strerror - Library for converting error code to string. + + +#ifndef NRF_STRERROR_ENABLED +#define NRF_STRERROR_ENABLED 1 +#endif + +// NRF_TWI_MNGR_ENABLED - nrf_twi_mngr - TWI transaction manager + + +#ifndef NRF_TWI_MNGR_ENABLED +#define NRF_TWI_MNGR_ENABLED 0 +#endif + +// SLIP_ENABLED - slip - SLIP encoding and decoding + + +#ifndef SLIP_ENABLED +#define SLIP_ENABLED 0 +#endif + +// TASK_MANAGER_ENABLED - task_manager - Task manager. +//========================================================== +#ifndef TASK_MANAGER_ENABLED +#define TASK_MANAGER_ENABLED 0 +#endif +// TASK_MANAGER_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef TASK_MANAGER_CLI_CMDS +#define TASK_MANAGER_CLI_CMDS 0 +#endif + +// TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created +#ifndef TASK_MANAGER_CONFIG_MAX_TASKS +#define TASK_MANAGER_CONFIG_MAX_TASKS 2 +#endif + +// TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2) +#ifndef TASK_MANAGER_CONFIG_STACK_SIZE +#define TASK_MANAGER_CONFIG_STACK_SIZE 1024 +#endif + +// TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED - Enable stack profiling. + + +#ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED +#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1 +#endif + +// TASK_MANAGER_CONFIG_STACK_GUARD - Configures stack guard. + +// <0=> Disabled +// <4=> 32 bytes +// <5=> 64 bytes +// <6=> 128 bytes +// <7=> 256 bytes +// <8=> 512 bytes + +#ifndef TASK_MANAGER_CONFIG_STACK_GUARD +#define TASK_MANAGER_CONFIG_STACK_GUARD 7 +#endif + +// + +// app_button - buttons handling module + +//========================================================== +// BUTTON_ENABLED - Enables Button module + + +#ifndef BUTTON_ENABLED +#define BUTTON_ENABLED 0 +#endif + +// BUTTON_HIGH_ACCURACY_ENABLED - Enables GPIOTE high accuracy for buttons + + +#ifndef BUTTON_HIGH_ACCURACY_ENABLED +#define BUTTON_HIGH_ACCURACY_ENABLED 0 +#endif + +// +//========================================================== + +// app_usbd_cdc_acm - USB CDC ACM class + +//========================================================== +// APP_USBD_CDC_ACM_ENABLED - Enabling USBD CDC ACM Class library + + +#ifndef APP_USBD_CDC_ACM_ENABLED +#define APP_USBD_CDC_ACM_ENABLED 0 +#endif + +// APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE - Send ZLP on write with same size as endpoint + + +// If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint. +// This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent. + +#ifndef APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE +#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1 +#endif + +// +//========================================================== + +// nrf_cli - Command line interface + +//========================================================== +// NRF_CLI_ENABLED - Enable/disable the CLI module. + + +#ifndef NRF_CLI_ENABLED +#define NRF_CLI_ENABLED 0 +#endif + +// NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler. +#ifndef NRF_CLI_ARGC_MAX +#define NRF_CLI_ARGC_MAX 12 +#endif + +// NRF_CLI_BUILD_IN_CMDS_ENABLED - CLI built-in commands. + + +#ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED +#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1 +#endif + +// NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command. +#ifndef NRF_CLI_CMD_BUFF_SIZE +#define NRF_CLI_CMD_BUFF_SIZE 128 +#endif + +// NRF_CLI_ECHO_STATUS - CLI echo status. If set, echo is ON. + + +#ifndef NRF_CLI_ECHO_STATUS +#define NRF_CLI_ECHO_STATUS 1 +#endif + +// NRF_CLI_WILDCARD_ENABLED - Enable wildcard functionality for CLI commands. + + +#ifndef NRF_CLI_WILDCARD_ENABLED +#define NRF_CLI_WILDCARD_ENABLED 0 +#endif + +// NRF_CLI_METAKEYS_ENABLED - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u + + +#ifndef NRF_CLI_METAKEYS_ENABLED +#define NRF_CLI_METAKEYS_ENABLED 0 +#endif + +// NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size. +#ifndef NRF_CLI_PRINTF_BUFF_SIZE +#define NRF_CLI_PRINTF_BUFF_SIZE 23 +#endif + +// NRF_CLI_HISTORY_ENABLED - Enable CLI history mode. +//========================================================== +#ifndef NRF_CLI_HISTORY_ENABLED +#define NRF_CLI_HISTORY_ENABLED 1 +#endif +// NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history. +#ifndef NRF_CLI_HISTORY_ELEMENT_SIZE +#define NRF_CLI_HISTORY_ELEMENT_SIZE 32 +#endif + +// NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects. +#ifndef NRF_CLI_HISTORY_ELEMENT_COUNT +#define NRF_CLI_HISTORY_ELEMENT_COUNT 8 +#endif + +// + +// NRF_CLI_VT100_COLORS_ENABLED - CLI VT100 colors. + + +#ifndef NRF_CLI_VT100_COLORS_ENABLED +#define NRF_CLI_VT100_COLORS_ENABLED 1 +#endif + +// NRF_CLI_STATISTICS_ENABLED - Enable CLI statistics. + + +#ifndef NRF_CLI_STATISTICS_ENABLED +#define NRF_CLI_STATISTICS_ENABLED 1 +#endif + +// NRF_CLI_LOG_BACKEND - Enable logger backend interface. + + +#ifndef NRF_CLI_LOG_BACKEND +#define NRF_CLI_LOG_BACKEND 1 +#endif + +// NRF_CLI_USES_TASK_MANAGER_ENABLED - Enable CLI to use task_manager + + +#ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED +#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0 +#endif + +// +//========================================================== + +// nrf_fprintf - fprintf function. + +//========================================================== +// NRF_FPRINTF_ENABLED - Enable/disable fprintf module. + + +#ifndef NRF_FPRINTF_ENABLED +#define NRF_FPRINTF_ENABLED 1 +#endif + +// NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED - For each printed LF, function will add CR. + + +#ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED +#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1 +#endif + +// NRF_FPRINTF_DOUBLE_ENABLED - Enable IEEE-754 double precision formatting. + + +#ifndef NRF_FPRINTF_DOUBLE_ENABLED +#define NRF_FPRINTF_DOUBLE_ENABLED 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// nRF_Log + +//========================================================== +// NRF_LOG_ENABLED - nrf_log - Logger +//========================================================== +#ifndef NRF_LOG_ENABLED +#define NRF_LOG_ENABLED 0 +#endif +// Log message pool - Configuration of log message pool + +//========================================================== +// NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects. +// If a small value is set, then performance of logs processing +// is degraded because data is fragmented. Bigger value impacts +// RAM memory utilization. The size is set to fit a message with +// a timestamp and up to 2 arguments in a single memory object. + +#ifndef NRF_LOG_MSGPOOL_ELEMENT_SIZE +#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20 +#endif + +// NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects +// If a small value is set, then it may lead to a deadlock +// in certain cases if backend has high latency and holds +// multiple messages for long time. Bigger value impacts +// RAM memory usage. + +#ifndef NRF_LOG_MSGPOOL_ELEMENT_COUNT +#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8 +#endif + +// +//========================================================== + +// NRF_LOG_ALLOW_OVERFLOW - Configures behavior when circular buffer is full. + + +// If set then oldest logs are overwritten. Otherwise a +// marker is injected informing about overflow. + +#ifndef NRF_LOG_ALLOW_OVERFLOW +#define NRF_LOG_ALLOW_OVERFLOW 1 +#endif + +// NRF_LOG_BUFSIZE - Size of the buffer for storing logs (in bytes). + + +// Must be power of 2 and multiple of 4. +// If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum. +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 +// <2048=> 2048 +// <4096=> 4096 +// <8192=> 8192 +// <16384=> 16384 + +#ifndef NRF_LOG_BUFSIZE +#define NRF_LOG_BUFSIZE 1024 +#endif + +// NRF_LOG_CLI_CMDS - Enable CLI commands for the module. + + +#ifndef NRF_LOG_CLI_CMDS +#define NRF_LOG_CLI_CMDS 0 +#endif + +// NRF_LOG_DEFAULT_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LOG_DEFAULT_LEVEL +#define NRF_LOG_DEFAULT_LEVEL 3 +#endif + +// NRF_LOG_DEFERRED - Enable deffered logger. + + +// Log data is buffered and can be processed in idle. + +#ifndef NRF_LOG_DEFERRED +#define NRF_LOG_DEFERRED 1 +#endif + +// NRF_LOG_FILTERS_ENABLED - Enable dynamic filtering of logs. + + +#ifndef NRF_LOG_FILTERS_ENABLED +#define NRF_LOG_FILTERS_ENABLED 0 +#endif + +// NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED - Enable use of critical region for non deffered mode when flushing logs. + + +// When enabled NRF_LOG_FLUSH is called from critical section when non deffered mode is used. +// Log output will never be corrupted as access to the log backend is exclusive +// but system will spend significant amount of time in critical section + +#ifndef NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED +#define NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED 0 +#endif + +// NRF_LOG_STR_PUSH_BUFFER_SIZE - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH. + +// <16=> 16 +// <32=> 32 +// <64=> 64 +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 + +#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE +#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128 +#endif + +// NRF_LOG_STR_PUSH_BUFFER_SIZE - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH. + +// <16=> 16 +// <32=> 32 +// <64=> 64 +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 + +#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE +#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128 +#endif + +// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string +//========================================================== +#ifndef NRF_LOG_USES_COLORS +#define NRF_LOG_USES_COLORS 0 +#endif +// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_COLOR_DEFAULT +#define NRF_LOG_COLOR_DEFAULT 0 +#endif + +// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_ERROR_COLOR +#define NRF_LOG_ERROR_COLOR 2 +#endif + +// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_WARNING_COLOR +#define NRF_LOG_WARNING_COLOR 4 +#endif + +// + +// NRF_LOG_USES_TIMESTAMP - Enable timestamping + +// Function for getting the timestamp is provided by the user +//========================================================== +#ifndef NRF_LOG_USES_TIMESTAMP +#define NRF_LOG_USES_TIMESTAMP 0 +#endif +// NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency. +#ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY +#define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0 +#endif + +// + +// nrf_log module configuration + +//========================================================== +// nrf_log in nRF_Core + +//========================================================== +// NRF_MPU_LIB_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_MPU_LIB_CONFIG_LOG_ENABLED +#define NRF_MPU_LIB_CONFIG_LOG_ENABLED 0 +#endif +// NRF_MPU_LIB_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_MPU_LIB_CONFIG_LOG_LEVEL +#define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_MPU_LIB_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MPU_LIB_CONFIG_INFO_COLOR +#define NRF_MPU_LIB_CONFIG_INFO_COLOR 0 +#endif + +// NRF_MPU_LIB_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MPU_LIB_CONFIG_DEBUG_COLOR +#define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_STACK_GUARD_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_STACK_GUARD_CONFIG_LOG_ENABLED +#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0 +#endif +// NRF_STACK_GUARD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL +#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_STACK_GUARD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR +#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0 +#endif + +// NRF_STACK_GUARD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR +#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TASK_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TASK_MANAGER_CONFIG_LOG_ENABLED +#define TASK_MANAGER_CONFIG_LOG_ENABLED 0 +#endif +// TASK_MANAGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TASK_MANAGER_CONFIG_LOG_LEVEL +#define TASK_MANAGER_CONFIG_LOG_LEVEL 3 +#endif + +// TASK_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TASK_MANAGER_CONFIG_INFO_COLOR +#define TASK_MANAGER_CONFIG_INFO_COLOR 0 +#endif + +// TASK_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR +#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Drivers + +//========================================================== +// CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef CLOCK_CONFIG_LOG_ENABLED +#define CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef CLOCK_CONFIG_LOG_LEVEL +#define CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_INFO_COLOR +#define CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_DEBUG_COLOR +#define CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef COMP_CONFIG_LOG_ENABLED +#define COMP_CONFIG_LOG_ENABLED 0 +#endif +// COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef COMP_CONFIG_LOG_LEVEL +#define COMP_CONFIG_LOG_LEVEL 3 +#endif + +// COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_INFO_COLOR +#define COMP_CONFIG_INFO_COLOR 0 +#endif + +// COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_DEBUG_COLOR +#define COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef GPIOTE_CONFIG_LOG_ENABLED +#define GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef GPIOTE_CONFIG_LOG_LEVEL +#define GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_INFO_COLOR +#define GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_DEBUG_COLOR +#define GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef LPCOMP_CONFIG_LOG_ENABLED +#define LPCOMP_CONFIG_LOG_ENABLED 0 +#endif +// LPCOMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef LPCOMP_CONFIG_LOG_LEVEL +#define LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +// LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_INFO_COLOR +#define LPCOMP_CONFIG_INFO_COLOR 0 +#endif + +// LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_DEBUG_COLOR +#define LPCOMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// MAX3421E_HOST_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef MAX3421E_HOST_CONFIG_LOG_ENABLED +#define MAX3421E_HOST_CONFIG_LOG_ENABLED 0 +#endif +// MAX3421E_HOST_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef MAX3421E_HOST_CONFIG_LOG_LEVEL +#define MAX3421E_HOST_CONFIG_LOG_LEVEL 3 +#endif + +// MAX3421E_HOST_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MAX3421E_HOST_CONFIG_INFO_COLOR +#define MAX3421E_HOST_CONFIG_INFO_COLOR 0 +#endif + +// MAX3421E_HOST_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MAX3421E_HOST_CONFIG_DEBUG_COLOR +#define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef NRFX_USBD_CONFIG_LOG_ENABLED +#define NRFX_USBD_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_USBD_CONFIG_LOG_LEVEL +#define NRFX_USBD_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_USBD_CONFIG_INFO_COLOR +#define NRFX_USBD_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR +#define NRFX_USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PDM_CONFIG_LOG_ENABLED +#define PDM_CONFIG_LOG_ENABLED 0 +#endif +// PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PDM_CONFIG_LOG_LEVEL +#define PDM_CONFIG_LOG_LEVEL 3 +#endif + +// PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_INFO_COLOR +#define PDM_CONFIG_INFO_COLOR 0 +#endif + +// PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_DEBUG_COLOR +#define PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PPI_CONFIG_LOG_ENABLED +#define PPI_CONFIG_LOG_ENABLED 0 +#endif +// PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PPI_CONFIG_LOG_LEVEL +#define PPI_CONFIG_LOG_LEVEL 3 +#endif + +// PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_INFO_COLOR +#define PPI_CONFIG_INFO_COLOR 0 +#endif + +// PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_DEBUG_COLOR +#define PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PWM_CONFIG_LOG_ENABLED +#define PWM_CONFIG_LOG_ENABLED 0 +#endif +// PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PWM_CONFIG_LOG_LEVEL +#define PWM_CONFIG_LOG_LEVEL 3 +#endif + +// PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_INFO_COLOR +#define PWM_CONFIG_INFO_COLOR 0 +#endif + +// PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_DEBUG_COLOR +#define PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef QDEC_CONFIG_LOG_ENABLED +#define QDEC_CONFIG_LOG_ENABLED 0 +#endif +// QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef QDEC_CONFIG_LOG_LEVEL +#define QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_INFO_COLOR +#define QDEC_CONFIG_INFO_COLOR 0 +#endif + +// QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_DEBUG_COLOR +#define QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RNG_CONFIG_LOG_ENABLED +#define RNG_CONFIG_LOG_ENABLED 0 +#endif +// RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RNG_CONFIG_LOG_LEVEL +#define RNG_CONFIG_LOG_LEVEL 3 +#endif + +// RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_INFO_COLOR +#define RNG_CONFIG_INFO_COLOR 0 +#endif + +// RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_DEBUG_COLOR +#define RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED - Enables logging of random numbers. + + +#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED +#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0 +#endif + +// + +// RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RTC_CONFIG_LOG_ENABLED +#define RTC_CONFIG_LOG_ENABLED 0 +#endif +// RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RTC_CONFIG_LOG_LEVEL +#define RTC_CONFIG_LOG_LEVEL 3 +#endif + +// RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_INFO_COLOR +#define RTC_CONFIG_INFO_COLOR 0 +#endif + +// RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_DEBUG_COLOR +#define RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SAADC_CONFIG_LOG_ENABLED +#define SAADC_CONFIG_LOG_ENABLED 0 +#endif +// SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SAADC_CONFIG_LOG_LEVEL +#define SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_INFO_COLOR +#define SAADC_CONFIG_INFO_COLOR 0 +#endif + +// SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_DEBUG_COLOR +#define SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPIS_CONFIG_LOG_ENABLED +#define SPIS_CONFIG_LOG_ENABLED 0 +#endif +// SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPIS_CONFIG_LOG_LEVEL +#define SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_INFO_COLOR +#define SPIS_CONFIG_INFO_COLOR 0 +#endif + +// SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_DEBUG_COLOR +#define SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPI_CONFIG_LOG_ENABLED +#define SPI_CONFIG_LOG_ENABLED 0 +#endif +// SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPI_CONFIG_LOG_LEVEL +#define SPI_CONFIG_LOG_LEVEL 3 +#endif + +// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_INFO_COLOR +#define SPI_CONFIG_INFO_COLOR 0 +#endif + +// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_DEBUG_COLOR +#define SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TIMER_CONFIG_LOG_ENABLED +#define TIMER_CONFIG_LOG_ENABLED 0 +#endif +// TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TIMER_CONFIG_LOG_LEVEL +#define TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_INFO_COLOR +#define TIMER_CONFIG_INFO_COLOR 0 +#endif + +// TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_DEBUG_COLOR +#define TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWIS_CONFIG_LOG_ENABLED +#define TWIS_CONFIG_LOG_ENABLED 0 +#endif +// TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWIS_CONFIG_LOG_LEVEL +#define TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_INFO_COLOR +#define TWIS_CONFIG_INFO_COLOR 0 +#endif + +// TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_DEBUG_COLOR +#define TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWI_CONFIG_LOG_ENABLED +#define TWI_CONFIG_LOG_ENABLED 0 +#endif +// TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWI_CONFIG_LOG_LEVEL +#define TWI_CONFIG_LOG_LEVEL 3 +#endif + +// TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_INFO_COLOR +#define TWI_CONFIG_INFO_COLOR 0 +#endif + +// TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_DEBUG_COLOR +#define TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef UART_CONFIG_LOG_ENABLED +#define UART_CONFIG_LOG_ENABLED 0 +#endif +// UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef UART_CONFIG_LOG_LEVEL +#define UART_CONFIG_LOG_LEVEL 3 +#endif + +// UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_INFO_COLOR +#define UART_CONFIG_INFO_COLOR 0 +#endif + +// UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_DEBUG_COLOR +#define UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// USBD_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef USBD_CONFIG_LOG_ENABLED +#define USBD_CONFIG_LOG_ENABLED 0 +#endif +// USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef USBD_CONFIG_LOG_LEVEL +#define USBD_CONFIG_LOG_LEVEL 3 +#endif + +// USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef USBD_CONFIG_INFO_COLOR +#define USBD_CONFIG_INFO_COLOR 0 +#endif + +// USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef USBD_CONFIG_DEBUG_COLOR +#define USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef WDT_CONFIG_LOG_ENABLED +#define WDT_CONFIG_LOG_ENABLED 0 +#endif +// WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef WDT_CONFIG_LOG_LEVEL +#define WDT_CONFIG_LOG_LEVEL 3 +#endif + +// WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_INFO_COLOR +#define WDT_CONFIG_INFO_COLOR 0 +#endif + +// WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_DEBUG_COLOR +#define WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Libraries + +//========================================================== +// APP_BUTTON_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_BUTTON_CONFIG_LOG_ENABLED +#define APP_BUTTON_CONFIG_LOG_ENABLED 0 +#endif +// APP_BUTTON_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_BUTTON_CONFIG_LOG_LEVEL +#define APP_BUTTON_CONFIG_LOG_LEVEL 3 +#endif + +// APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. + + +// If module generates a lot of logs, initial log level can +// be decreased to prevent flooding. Severity level can be +// increased on instance basis. +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL +#define APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL 3 +#endif + +// APP_BUTTON_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_BUTTON_CONFIG_INFO_COLOR +#define APP_BUTTON_CONFIG_INFO_COLOR 0 +#endif + +// APP_BUTTON_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_BUTTON_CONFIG_DEBUG_COLOR +#define APP_BUTTON_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_TIMER_CONFIG_LOG_ENABLED +#define APP_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// APP_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_TIMER_CONFIG_LOG_LEVEL +#define APP_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// APP_TIMER_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. + + +// If module generates a lot of logs, initial log level can +// be decreased to prevent flooding. Severity level can be +// increased on instance basis. +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL +#define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3 +#endif + +// APP_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_TIMER_CONFIG_INFO_COLOR +#define APP_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// APP_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_TIMER_CONFIG_DEBUG_COLOR +#define APP_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED +#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL +#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_CDC_ACM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR +#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR +#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_CONFIG_LOG_ENABLED - Enable logging in the module. +//========================================================== +#ifndef APP_USBD_CONFIG_LOG_ENABLED +#define APP_USBD_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_CONFIG_LOG_LEVEL +#define APP_USBD_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CONFIG_INFO_COLOR +#define APP_USBD_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CONFIG_DEBUG_COLOR +#define APP_USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_DUMMY_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_DUMMY_CONFIG_LOG_ENABLED +#define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_DUMMY_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL +#define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_DUMMY_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR +#define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_DUMMY_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR +#define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_MSC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_MSC_CONFIG_LOG_ENABLED +#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_MSC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL +#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_MSC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_MSC_CONFIG_INFO_COLOR +#define APP_USBD_MSC_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_MSC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR +#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_ATFIFO_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_ATFIFO_CONFIG_LOG_ENABLED +#define NRF_ATFIFO_CONFIG_LOG_ENABLED 0 +#endif +// NRF_ATFIFO_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL +#define NRF_ATFIFO_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_ATFIFO_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_ATFIFO_CONFIG_INFO_COLOR +#define NRF_ATFIFO_CONFIG_INFO_COLOR 0 +#endif + +// NRF_ATFIFO_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR +#define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BALLOC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_LOG_ENABLED +#define NRF_BALLOC_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BALLOC_CONFIG_LOG_LEVEL +#define NRF_BALLOC_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. + + +// If module generates a lot of logs, initial log level can +// be decreased to prevent flooding. Severity level can be +// increased on instance basis. +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL +#define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3 +#endif + +// NRF_BALLOC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BALLOC_CONFIG_INFO_COLOR +#define NRF_BALLOC_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BALLOC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR +#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED +#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL +#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_BLE_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR +#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR +#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED +#define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL +#define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR +#define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR +#define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_UART_CONFIG_LOG_ENABLED +#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL +#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_UART_CONFIG_INFO_COLOR +#define NRF_CLI_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR +#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_LIBUARTE_CONFIG_LOG_ENABLED +#define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_LIBUARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL +#define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_LIBUARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR +#define NRF_LIBUARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_LIBUARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR +#define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_MEMOBJ_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_MEMOBJ_CONFIG_LOG_ENABLED +#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0 +#endif +// NRF_MEMOBJ_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL +#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_MEMOBJ_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR +#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0 +#endif + +// NRF_MEMOBJ_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR +#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_LOG_ENABLED +#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL +#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_PWR_MGMT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR +#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0 +#endif + +// NRF_PWR_MGMT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR +#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_QUEUE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_QUEUE_CONFIG_LOG_ENABLED +#define NRF_QUEUE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_QUEUE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_QUEUE_CONFIG_LOG_LEVEL +#define NRF_QUEUE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_QUEUE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_QUEUE_CONFIG_INFO_COLOR +#define NRF_QUEUE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_QUEUE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR +#define NRF_QUEUE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_ANT_LOG_ENABLED - Enable logging in SoftDevice handler (ANT) module. +//========================================================== +#ifndef NRF_SDH_ANT_LOG_ENABLED +#define NRF_SDH_ANT_LOG_ENABLED 0 +#endif +// NRF_SDH_ANT_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_ANT_LOG_LEVEL +#define NRF_SDH_ANT_LOG_LEVEL 3 +#endif + +// NRF_SDH_ANT_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_ANT_INFO_COLOR +#define NRF_SDH_ANT_INFO_COLOR 0 +#endif + +// NRF_SDH_ANT_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_ANT_DEBUG_COLOR +#define NRF_SDH_ANT_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_BLE_LOG_ENABLED - Enable logging in SoftDevice handler (BLE) module. +//========================================================== +#ifndef NRF_SDH_BLE_LOG_ENABLED +#define NRF_SDH_BLE_LOG_ENABLED 1 +#endif +// NRF_SDH_BLE_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_BLE_LOG_LEVEL +#define NRF_SDH_BLE_LOG_LEVEL 3 +#endif + +// NRF_SDH_BLE_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_BLE_INFO_COLOR +#define NRF_SDH_BLE_INFO_COLOR 0 +#endif + +// NRF_SDH_BLE_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_BLE_DEBUG_COLOR +#define NRF_SDH_BLE_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_LOG_ENABLED - Enable logging in SoftDevice handler module. +//========================================================== +#ifndef NRF_SDH_LOG_ENABLED +#define NRF_SDH_LOG_ENABLED 1 +#endif +// NRF_SDH_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_LOG_LEVEL +#define NRF_SDH_LOG_LEVEL 3 +#endif + +// NRF_SDH_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_INFO_COLOR +#define NRF_SDH_INFO_COLOR 0 +#endif + +// NRF_SDH_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_DEBUG_COLOR +#define NRF_SDH_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_SOC_LOG_ENABLED - Enable logging in SoftDevice handler (SoC) module. +//========================================================== +#ifndef NRF_SDH_SOC_LOG_ENABLED +#define NRF_SDH_SOC_LOG_ENABLED 1 +#endif +// NRF_SDH_SOC_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_SOC_LOG_LEVEL +#define NRF_SDH_SOC_LOG_LEVEL 3 +#endif + +// NRF_SDH_SOC_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_SOC_INFO_COLOR +#define NRF_SDH_SOC_INFO_COLOR 0 +#endif + +// NRF_SDH_SOC_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_SOC_DEBUG_COLOR +#define NRF_SDH_SOC_DEBUG_COLOR 0 +#endif + +// + +// NRF_SORTLIST_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_SORTLIST_CONFIG_LOG_ENABLED +#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0 +#endif +// NRF_SORTLIST_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL +#define NRF_SORTLIST_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_SORTLIST_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SORTLIST_CONFIG_INFO_COLOR +#define NRF_SORTLIST_CONFIG_INFO_COLOR 0 +#endif + +// NRF_SORTLIST_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR +#define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_TWI_SENSOR_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_TWI_SENSOR_CONFIG_LOG_ENABLED +#define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0 +#endif +// NRF_TWI_SENSOR_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL +#define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_TWI_SENSOR_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR +#define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0 +#endif + +// NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR +#define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PM_LOG_ENABLED - Enable logging in Peer Manager and its submodules. +//========================================================== +#ifndef PM_LOG_ENABLED +#define PM_LOG_ENABLED 1 +#endif +// PM_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PM_LOG_LEVEL +#define PM_LOG_LEVEL 3 +#endif + +// PM_LOG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PM_LOG_INFO_COLOR +#define PM_LOG_INFO_COLOR 0 +#endif + +// PM_LOG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PM_LOG_DEBUG_COLOR +#define PM_LOG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Serialization + +//========================================================== +// SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED +#define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0 +#endif +// SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL +#define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3 +#endif + +// SER_HAL_TRANSPORT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR +#define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0 +#endif + +// SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR +#define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// +//========================================================== + +// + +// NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED - nrf_log_str_formatter - Log string formatter + + +#ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED +#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1 +#endif + +// +//========================================================== + +// nRF_NFC + +//========================================================== +// NFC_AC_REC_ENABLED - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder + + +#ifndef NFC_AC_REC_ENABLED +#define NFC_AC_REC_ENABLED 0 +#endif + +// NFC_AC_REC_PARSER_ENABLED - nfc_ac_rec_parser - Alternative Carrier record parser + + +#ifndef NFC_AC_REC_PARSER_ENABLED +#define NFC_AC_REC_PARSER_ENABLED 0 +#endif + +// NFC_BLE_OOB_ADVDATA_ENABLED - nfc_ble_oob_advdata - AD data for OOB pairing encoder +//========================================================== +#ifndef NFC_BLE_OOB_ADVDATA_ENABLED +#define NFC_BLE_OOB_ADVDATA_ENABLED 0 +#endif +// ADVANCED_ADVDATA_SUPPORT - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs) + +// <1=> Enabled +// <0=> Disabled + +#ifndef ADVANCED_ADVDATA_SUPPORT +#define ADVANCED_ADVDATA_SUPPORT 0 +#endif + +// + +// NFC_BLE_OOB_ADVDATA_PARSER_ENABLED - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser + + +#ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED +#define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0 +#endif + +// NFC_BLE_PAIR_LIB_ENABLED - nfc_ble_pair_lib - Library parameters +//========================================================== +#ifndef NFC_BLE_PAIR_LIB_ENABLED +#define NFC_BLE_PAIR_LIB_ENABLED 0 +#endif +// NFC_BLE_PAIR_LIB_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_BLE_PAIR_LIB_LOG_ENABLED +#define NFC_BLE_PAIR_LIB_LOG_ENABLED 0 +#endif +// NFC_BLE_PAIR_LIB_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL +#define NFC_BLE_PAIR_LIB_LOG_LEVEL 3 +#endif + +// NFC_BLE_PAIR_LIB_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_BLE_PAIR_LIB_INFO_COLOR +#define NFC_BLE_PAIR_LIB_INFO_COLOR 0 +#endif + +// NFC_BLE_PAIR_LIB_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR +#define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0 +#endif + +// + +// NFC_BLE_PAIR_LIB_SECURITY_PARAMETERS - Common Peer Manager security parameters. + +//========================================================== +// BLE_NFC_SEC_PARAM_BOND - Enables device bonding. + +// If bonding is enabled at least one of the BLE_NFC_SEC_PARAM_KDIST options must be enabled. +//========================================================== +#ifndef BLE_NFC_SEC_PARAM_BOND +#define BLE_NFC_SEC_PARAM_BOND 1 +#endif +// BLE_NFC_SEC_PARAM_KDIST_OWN_ENC - Enables Long Term Key and Master Identification distribution by device. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC +#define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_OWN_ID - Enables Identity Resolving Key and Identity Address Information distribution by device. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID +#define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_PEER_ENC - Enables Long Term Key and Master Identification distribution by peer. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC +#define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_PEER_ID - Enables Identity Resolving Key and Identity Address Information distribution by peer. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID +#define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1 +#endif + +// + +// BLE_NFC_SEC_PARAM_MIN_KEY_SIZE - Minimal size of a security key. + +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// <16=> 16 + +#ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE +#define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7 +#endif + +// BLE_NFC_SEC_PARAM_MAX_KEY_SIZE - Maximal size of a security key. + +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// <16=> 16 + +#ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE +#define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16 +#endif + +// +//========================================================== + +// + +// NFC_BLE_PAIR_MSG_ENABLED - nfc_ble_pair_msg - NDEF message for OOB pairing encoder + + +#ifndef NFC_BLE_PAIR_MSG_ENABLED +#define NFC_BLE_PAIR_MSG_ENABLED 0 +#endif + +// NFC_CH_COMMON_ENABLED - nfc_ble_pair_common - OOB pairing common data + + +#ifndef NFC_CH_COMMON_ENABLED +#define NFC_CH_COMMON_ENABLED 0 +#endif + +// NFC_EP_OOB_REC_ENABLED - nfc_ep_oob_rec - EP record for BLE pairing encoder + + +#ifndef NFC_EP_OOB_REC_ENABLED +#define NFC_EP_OOB_REC_ENABLED 0 +#endif + +// NFC_HS_REC_ENABLED - nfc_hs_rec - Handover Select NDEF record encoder + + +#ifndef NFC_HS_REC_ENABLED +#define NFC_HS_REC_ENABLED 0 +#endif + +// NFC_LE_OOB_REC_ENABLED - nfc_le_oob_rec - LE record for BLE pairing encoder + + +#ifndef NFC_LE_OOB_REC_ENABLED +#define NFC_LE_OOB_REC_ENABLED 0 +#endif + +// NFC_LE_OOB_REC_PARSER_ENABLED - nfc_le_oob_rec_parser - LE record parser + + +#ifndef NFC_LE_OOB_REC_PARSER_ENABLED +#define NFC_LE_OOB_REC_PARSER_ENABLED 0 +#endif + +// NFC_NDEF_LAUNCHAPP_MSG_ENABLED - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag + + +#ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED +#define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0 +#endif + +// NFC_NDEF_LAUNCHAPP_REC_ENABLED - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag + + +#ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED +#define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0 +#endif + +// NFC_NDEF_MSG_ENABLED - nfc_ndef_msg - NFC NDEF Message generator module +//========================================================== +#ifndef NFC_NDEF_MSG_ENABLED +#define NFC_NDEF_MSG_ENABLED 0 +#endif +// NFC_NDEF_MSG_TAG_TYPE - NFC Tag Type + +// <2=> Type 2 Tag +// <4=> Type 4 Tag + +#ifndef NFC_NDEF_MSG_TAG_TYPE +#define NFC_NDEF_MSG_TAG_TYPE 2 +#endif + +// + +// NFC_NDEF_MSG_PARSER_ENABLED - nfc_ndef_msg_parser - NFC NDEF message parser module +//========================================================== +#ifndef NFC_NDEF_MSG_PARSER_ENABLED +#define NFC_NDEF_MSG_PARSER_ENABLED 0 +#endif +// NFC_NDEF_MSG_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_NDEF_MSG_PARSER_LOG_ENABLED +#define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0 +#endif +// NFC_NDEF_MSG_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL +#define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3 +#endif + +// NFC_NDEF_MSG_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR +#define NFC_NDEF_MSG_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_NDEF_RECORD_ENABLED - nfc_ndef_record - NFC NDEF Record generator module + + +#ifndef NFC_NDEF_RECORD_ENABLED +#define NFC_NDEF_RECORD_ENABLED 0 +#endif + +// NFC_NDEF_RECORD_PARSER_ENABLED - nfc_ndef_record_parser - NFC NDEF Record parser module +//========================================================== +#ifndef NFC_NDEF_RECORD_PARSER_ENABLED +#define NFC_NDEF_RECORD_PARSER_ENABLED 0 +#endif +// NFC_NDEF_RECORD_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_NDEF_RECORD_PARSER_LOG_ENABLED +#define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0 +#endif +// NFC_NDEF_RECORD_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL +#define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3 +#endif + +// NFC_NDEF_RECORD_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR +#define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_NDEF_TEXT_RECORD_ENABLED - nfc_text_rec - Encoding data for a text record for NFC Tag + + +#ifndef NFC_NDEF_TEXT_RECORD_ENABLED +#define NFC_NDEF_TEXT_RECORD_ENABLED 0 +#endif + +// NFC_NDEF_URI_MSG_ENABLED - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag + + +#ifndef NFC_NDEF_URI_MSG_ENABLED +#define NFC_NDEF_URI_MSG_ENABLED 0 +#endif + +// NFC_NDEF_URI_REC_ENABLED - nfc_uri_rec - Encoding data for a URI record for NFC Tag + + +#ifndef NFC_NDEF_URI_REC_ENABLED +#define NFC_NDEF_URI_REC_ENABLED 0 +#endif + +// NFC_PLATFORM_ENABLED - nfc_platform - NFC platform module for Clock control. +//========================================================== +#ifndef NFC_PLATFORM_ENABLED +#define NFC_PLATFORM_ENABLED 0 +#endif +// NFC_PLATFORM_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_PLATFORM_LOG_ENABLED +#define NFC_PLATFORM_LOG_ENABLED 0 +#endif +// NFC_PLATFORM_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_PLATFORM_LOG_LEVEL +#define NFC_PLATFORM_LOG_LEVEL 3 +#endif + +// NFC_PLATFORM_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_PLATFORM_INFO_COLOR +#define NFC_PLATFORM_INFO_COLOR 0 +#endif + +// NFC_PLATFORM_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_PLATFORM_DEBUG_COLOR +#define NFC_PLATFORM_DEBUG_COLOR 0 +#endif + +// + +// + +// NFC_T2T_PARSER_ENABLED - nfc_type_2_tag_parser - Parser for decoding Type 2 Tag data +//========================================================== +#ifndef NFC_T2T_PARSER_ENABLED +#define NFC_T2T_PARSER_ENABLED 0 +#endif +// NFC_T2T_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T2T_PARSER_LOG_ENABLED +#define NFC_T2T_PARSER_LOG_ENABLED 0 +#endif +// NFC_T2T_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T2T_PARSER_LOG_LEVEL +#define NFC_T2T_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T2T_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T2T_PARSER_INFO_COLOR +#define NFC_T2T_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_T4T_APDU_ENABLED - nfc_t4t_apdu - APDU encoder/decoder for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_APDU_ENABLED +#define NFC_T4T_APDU_ENABLED 0 +#endif +// NFC_T4T_APDU_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_APDU_LOG_ENABLED +#define NFC_T4T_APDU_LOG_ENABLED 0 +#endif +// NFC_T4T_APDU_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_APDU_LOG_LEVEL +#define NFC_T4T_APDU_LOG_LEVEL 3 +#endif + +// NFC_T4T_APDU_LOG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_APDU_LOG_COLOR +#define NFC_T4T_APDU_LOG_COLOR 0 +#endif + +// + +// + +// NFC_T4T_CC_FILE_PARSER_ENABLED - nfc_t4t_cc_file - Capability Container file for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_CC_FILE_PARSER_ENABLED +#define NFC_T4T_CC_FILE_PARSER_ENABLED 0 +#endif +// NFC_T4T_CC_FILE_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_CC_FILE_PARSER_LOG_ENABLED +#define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0 +#endif +// NFC_T4T_CC_FILE_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL +#define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T4T_CC_FILE_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR +#define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED - nfc_t4t_hl_detection_procedures - NDEF Detection Procedure for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED +#define NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED 0 +#endif +// NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED +#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0 +#endif +// NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL +#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3 +#endif + +// NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR +#define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0 +#endif + +// + +// APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage +#ifndef APDU_BUFF_SIZE +#define APDU_BUFF_SIZE 250 +#endif + +// CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage +#ifndef CC_STORAGE_BUFF_SIZE +#define CC_STORAGE_BUFF_SIZE 64 +#endif + +// + +// NFC_T4T_TLV_BLOCK_PARSER_ENABLED - nfc_t4t_tlv_block - TLV block for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_TLV_BLOCK_PARSER_ENABLED +#define NFC_T4T_TLV_BLOCK_PARSER_ENABLED 0 +#endif +// NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED +#define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0 +#endif +// NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL +#define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR +#define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// +//========================================================== + +// nRF_SoftDevice + +//========================================================== +// NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler +//========================================================== +#ifndef NRF_SDH_BLE_ENABLED +#define NRF_SDH_BLE_ENABLED 0 +#endif +// BLE Stack configuration - Stack configuration parameters + +// The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set. +// Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set. +//========================================================== +// NRF_SDH_BLE_GAP_DATA_LENGTH <27-251> + + +// Requested BLE GAP data length to be negotiated. + +#ifndef NRF_SDH_BLE_GAP_DATA_LENGTH +#define NRF_SDH_BLE_GAP_DATA_LENGTH 27 +#endif + +// NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. +#ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT +#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0 +#endif + +// NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links. +#ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT +#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0 +#endif + +// NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count. +// Maximum number of total concurrent connections using the default configuration. + +#ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT +#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1 +#endif + +// NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length. +// The time set aside for this connection on every connection interval in 1.25 ms units. + +#ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH +#define NRF_SDH_BLE_GAP_EVENT_LENGTH 6 +#endif + +// NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size. +#ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE +#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23 +#endif + +// NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4. +#ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE +#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408 +#endif + +// NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs. +#ifndef NRF_SDH_BLE_VS_UUID_COUNT +#define NRF_SDH_BLE_VS_UUID_COUNT 0 +#endif + +// NRF_SDH_BLE_SERVICE_CHANGED - Include the Service Changed characteristic in the Attribute Table. + + +#ifndef NRF_SDH_BLE_SERVICE_CHANGED +#define NRF_SDH_BLE_SERVICE_CHANGED 0 +#endif + +// +//========================================================== + +// BLE Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers. +// This setting configures the number of priority levels available for BLE event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_BLE_OBSERVER_PRIO_LEVELS +#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 4 +#endif + +// BLE Observers priorities - Invididual priorities + +//========================================================== +// BLE_ADV_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Advertising module. + +#ifndef BLE_ADV_BLE_OBSERVER_PRIO +#define BLE_ADV_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_ANCS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Apple Notification Service Client. + +#ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO +#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_ANS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Alert Notification Service Client. + +#ifndef BLE_ANS_C_BLE_OBSERVER_PRIO +#define BLE_ANS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BAS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Battery Service. + +#ifndef BLE_BAS_BLE_OBSERVER_PRIO +#define BLE_BAS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BAS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Battery Service Client. + +#ifndef BLE_BAS_C_BLE_OBSERVER_PRIO +#define BLE_BAS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BPS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Blood Pressure Service. + +#ifndef BLE_BPS_BLE_OBSERVER_PRIO +#define BLE_BPS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CONN_PARAMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Connection parameters module. + +#ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO +#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_CONN_STATE_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Connection State module. + +#ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO +#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0 +#endif + +// BLE_CSCS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service. + +#ifndef BLE_CSCS_BLE_OBSERVER_PRIO +#define BLE_CSCS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Current Time Service Client. + +#ifndef BLE_CTS_C_BLE_OBSERVER_PRIO +#define BLE_CTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_DB_DISC_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Database Discovery module. + +#ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO +#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_DFU_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the DFU Service. + +#ifndef BLE_DFU_BLE_OBSERVER_PRIO +#define BLE_DFU_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_DIS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Device Information Client. + +#ifndef BLE_DIS_C_BLE_OBSERVER_PRIO +#define BLE_DIS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_GLS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Glucose Service. + +#ifndef BLE_GLS_BLE_OBSERVER_PRIO +#define BLE_GLS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HIDS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Human Interface Device Service. + +#ifndef BLE_HIDS_BLE_OBSERVER_PRIO +#define BLE_HIDS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HRS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Heart Rate Service. + +#ifndef BLE_HRS_BLE_OBSERVER_PRIO +#define BLE_HRS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HRS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Heart Rate Service Client. + +#ifndef BLE_HRS_C_BLE_OBSERVER_PRIO +#define BLE_HRS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HTS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Health Thermometer Service. + +#ifndef BLE_HTS_BLE_OBSERVER_PRIO +#define BLE_HTS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_IAS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Immediate Alert Service. + +#ifndef BLE_IAS_BLE_OBSERVER_PRIO +#define BLE_IAS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_IAS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Immediate Alert Service Client. + +#ifndef BLE_IAS_C_BLE_OBSERVER_PRIO +#define BLE_IAS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LBS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the LED Button Service. + +#ifndef BLE_LBS_BLE_OBSERVER_PRIO +#define BLE_LBS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LBS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the LED Button Service Client. + +#ifndef BLE_LBS_C_BLE_OBSERVER_PRIO +#define BLE_LBS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LLS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Link Loss Service. + +#ifndef BLE_LLS_BLE_OBSERVER_PRIO +#define BLE_LLS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LNS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Location Navigation Service. + +#ifndef BLE_LNS_BLE_OBSERVER_PRIO +#define BLE_LNS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_NUS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the UART Service. + +#ifndef BLE_NUS_BLE_OBSERVER_PRIO +#define BLE_NUS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_NUS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the UART Central Service. + +#ifndef BLE_NUS_C_BLE_OBSERVER_PRIO +#define BLE_NUS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_OTS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Object transfer service. + +#ifndef BLE_OTS_BLE_OBSERVER_PRIO +#define BLE_OTS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_OTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Object transfer service client. + +#ifndef BLE_OTS_C_BLE_OBSERVER_PRIO +#define BLE_OTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_RSCS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Running Speed and Cadence Service. + +#ifndef BLE_RSCS_BLE_OBSERVER_PRIO +#define BLE_RSCS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_RSCS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Running Speed and Cadence Client. + +#ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO +#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_TPS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the TX Power Service. + +#ifndef BLE_TPS_BLE_OBSERVER_PRIO +#define BLE_TPS_BLE_OBSERVER_PRIO 2 +#endif + +// BSP_BTN_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Button Control module. + +#ifndef BSP_BTN_BLE_OBSERVER_PRIO +#define BSP_BTN_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_BMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Bond Management Service. + +#ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO +#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_CGMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service. + +#ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO +#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_ES_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Eddystone module. + +#ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO +#define NRF_BLE_ES_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT Service Client. + +#ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO +#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_GATT_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT module. + +#ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO +#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_GQ_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT Queue module. + +#ifndef NRF_BLE_GQ_BLE_OBSERVER_PRIO +#define NRF_BLE_GQ_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_QWR_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Queued writes module. + +#ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO +#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_SCAN_OBSERVER_PRIO +// Priority for dispatching the BLE events to the Scanning Module. + +#ifndef NRF_BLE_SCAN_OBSERVER_PRIO +#define NRF_BLE_SCAN_OBSERVER_PRIO 1 +#endif + +// PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module. +#ifndef PM_BLE_OBSERVER_PRIO +#define PM_BLE_OBSERVER_PRIO 1 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// NRF_SDH_ENABLED - nrf_sdh - SoftDevice handler +//========================================================== +#ifndef NRF_SDH_ENABLED +#define NRF_SDH_ENABLED 0 +#endif +// Dispatch model + +// This setting configures how Stack events are dispatched to the application. +//========================================================== +// NRF_SDH_DISPATCH_MODEL + + +// NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context. +// NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler. +// NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually. +// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT +// <1=> NRF_SDH_DISPATCH_MODEL_APPSH +// <2=> NRF_SDH_DISPATCH_MODEL_POLLING + +#ifndef NRF_SDH_DISPATCH_MODEL +#define NRF_SDH_DISPATCH_MODEL 0 +#endif + +// +//========================================================== + +// Clock - SoftDevice clock configuration + +//========================================================== +// NRF_SDH_CLOCK_LF_SRC - SoftDevice clock source. + +// <0=> NRF_CLOCK_LF_SRC_RC +// <1=> NRF_CLOCK_LF_SRC_XTAL +// <2=> NRF_CLOCK_LF_SRC_SYNTH + +#ifndef NRF_SDH_CLOCK_LF_SRC +#define NRF_SDH_CLOCK_LF_SRC 1 +#endif + +// NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. +#ifndef NRF_SDH_CLOCK_LF_RC_CTIV +#define NRF_SDH_CLOCK_LF_RC_CTIV 0 +#endif + +// NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. +// How often (in number of calibration intervals) the RC oscillator shall be calibrated +// if the temperature has not changed. + +#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV +#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0 +#endif + +// NRF_SDH_CLOCK_LF_ACCURACY - External clock accuracy used in the LL to compute timing. + +// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM +// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM +// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM +// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM +// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM +// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM +// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM +// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM +// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM +// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM +// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM +// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM + +#ifndef NRF_SDH_CLOCK_LF_ACCURACY +#define NRF_SDH_CLOCK_LF_ACCURACY 7 +#endif + +// +//========================================================== + +// SDH Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers. +// This setting configures the number of priority levels available for the SoftDevice request event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_REQ_OBSERVER_PRIO_LEVELS +#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2 +#endif + +// NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers. +// This setting configures the number of priority levels available for the SoftDevice state event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_STATE_OBSERVER_PRIO_LEVELS +#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2 +#endif + +// NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers. +// This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC). +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_STACK_OBSERVER_PRIO_LEVELS +#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2 +#endif + + +// State Observers priorities - Invididual priorities + +//========================================================== +// CLOCK_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to the Clock driver. + +#ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO +#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// POWER_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to the Power driver. + +#ifndef POWER_CONFIG_STATE_OBSERVER_PRIO +#define POWER_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// RNG_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to this module. + +#ifndef RNG_CONFIG_STATE_OBSERVER_PRIO +#define RNG_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// Stack Event Observers priorities - Invididual priorities + +//========================================================== +// NRF_SDH_ANT_STACK_OBSERVER_PRIO +// This setting configures the priority with which ANT events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC. +// Zero is the highest priority. + +#ifndef NRF_SDH_ANT_STACK_OBSERVER_PRIO +#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0 +#endif + +// NRF_SDH_BLE_STACK_OBSERVER_PRIO +// This setting configures the priority with which BLE events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC. +// Zero is the highest priority. + +#ifndef NRF_SDH_BLE_STACK_OBSERVER_PRIO +#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0 +#endif + +// NRF_SDH_SOC_STACK_OBSERVER_PRIO +// This setting configures the priority with which SoC events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE. +// Zero is the highest priority. + +#ifndef NRF_SDH_SOC_STACK_OBSERVER_PRIO +#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler +//========================================================== +#ifndef NRF_SDH_SOC_ENABLED +#define NRF_SDH_SOC_ENABLED 0 +#endif +// SoC Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers. +// This setting configures the number of priority levels available for the SoC event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS +#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2 +#endif + +// SoC Observers priorities - Invididual priorities + +//========================================================== +// BLE_DFU_SOC_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the DFU Service. + +#ifndef BLE_DFU_SOC_OBSERVER_PRIO +#define BLE_DFU_SOC_OBSERVER_PRIO 1 +#endif + +// CLOCK_CONFIG_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Clock driver. + +#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO +#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0 +#endif + +// POWER_CONFIG_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Power driver. + +#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO +#define POWER_CONFIG_SOC_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver +//========================================================== +#ifndef NRFX_NVMC_ENABLED +#define NRFX_NVMC_ENABLED 1 +#endif +// + +//========================================================== +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 1 +#endif +// <<< end of configuration section >>> +#endif //SDK_CONFIG_H + diff --git a/bsp/nrf5x/nrf52833/project.uvoptx b/bsp/nrf5x/nrf52833/project.uvoptx new file mode 100644 index 0000000000..fc7fc40878 --- /dev/null +++ b/bsp/nrf5x/nrf52833/project.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 5 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52833_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52833_xxAA$Flash\nrf52xxx_uicr.flm) + + + 0 + JL2CM3 + -U685119905 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52833_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52833_xxAA$Flash\nrf52xxx_uicr.flm) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/nrf5x/nrf52833/project.uvprojx b/bsp/nrf5x/nrf52833/project.uvprojx new file mode 100644 index 0000000000..d6dc2b2a7b --- /dev/null +++ b/bsp/nrf5x/nrf52833/project.uvprojx @@ -0,0 +1,636 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rtthread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + 0 + + + nRF52833_xxAA + Nordic Semiconductor + NordicSemiconductor.nRF_DeviceFamilyPack.8.35.0 + http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ + IRAM(0x20000000,0x00020000) IRAM2(0x00800000,0x00020000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52833_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52833_xxAA$Flash\nrf52xxx_uicr.flm)) + 0 + $$Device:nRF52833_xxAA$Device\Include\nrf.h + + + + + + + + + + $$Device:nRF52833_xxAA$SVD\nrf52833.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x800000 + 0x20000 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --reduce_paths + USE_APP_CONFIG, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\libraries\cmsis\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;..\..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74 + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + application.c + 1 + applications\application.c + + + + + CPU + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + drv_uart.c + 1 + ..\libraries\drivers\drv_uart.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + Kernel + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + + + + + + + diff --git a/bsp/nrf5x/nrf52833/rtconfig.h b/bsp/nrf5x/nrf52833/rtconfig.h new file mode 100644 index 0000000000..31522ebb66 --- /dev/null +++ b/bsp/nrf5x/nrf52833/rtconfig.h @@ -0,0 +1,196 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +#define PKG_USING_NRFX +#define PKG_USING_NRFX_LATEST_VERSION + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define SOC_NRF52833 +#define SOC_NORDIC +#define BSP_BOARD_PCA_10100 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_PIN 8 +#define BSP_UART0_TX_PIN 6 + +/* On-chip flash config */ + +#define MCU_FLASH_START_ADDRESS 0x00000000 +#define MCU_FLASH_SIZE_KB 512 +#define MCU_SRAM_START_ADDRESS 0x20000000 +#define MCU_SRAM_SIZE_KB 128 +#define MCU_FLASH_PAGE_SIZE 0x1000 +#define NRFX_CLOCK_ENABLED 1 +#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#define NRFX_USING_UART +#define NRFX_UART_ENABLED 1 +#define NRFX_UART0_ENABLED 1 + +#endif diff --git a/bsp/nrf5x/nrf52833/rtconfig.py b/bsp/nrf5x/nrf52833/rtconfig.py new file mode 100644 index 0000000000..c809814516 --- /dev/null +++ b/bsp/nrf5x/nrf52833/rtconfig.py @@ -0,0 +1,92 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'D:/SourceryGCC/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + print('================ERROR============================') + print('Not support iar yet!') + print('=================================================') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu='+CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"' + + CFLAGS += ' --c99' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nrf5x/nrf52833/template.uvoptx b/bsp/nrf5x/nrf52833/template.uvoptx new file mode 100644 index 0000000000..fc7fc40878 --- /dev/null +++ b/bsp/nrf5x/nrf52833/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 5 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52833_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52833_xxAA$Flash\nrf52xxx_uicr.flm) + + + 0 + JL2CM3 + -U685119905 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52833_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52833_xxAA$Flash\nrf52xxx_uicr.flm) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/nrf5x/nrf52833/template.uvprojx b/bsp/nrf5x/nrf52833/template.uvprojx new file mode 100644 index 0000000000..47e94f959e --- /dev/null +++ b/bsp/nrf5x/nrf52833/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + 0 + + + nRF52833_xxAA + Nordic Semiconductor + NordicSemiconductor.nRF_DeviceFamilyPack.8.35.0 + http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ + IRAM(0x20000000,0x00020000) IRAM2(0x00800000,0x00020000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52833_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52833_xxAA$Flash\nrf52xxx_uicr.flm)) + 0 + $$Device:nRF52833_xxAA$Device\Include\nrf.h + + + + + + + + + + $$Device:nRF52833_xxAA$SVD\nrf52833.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x800000 + 0x20000 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --reduce_paths + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74 + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --diag_suppress 6330 + + + + + + + + + + + + + + + diff --git a/bsp/nrf5x/nrf52840/board/Kconfig b/bsp/nrf5x/nrf52840/board/Kconfig index 0a332f8bf0..528bf981e4 100644 --- a/bsp/nrf5x/nrf52840/board/Kconfig +++ b/bsp/nrf5x/nrf52840/board/Kconfig @@ -108,12 +108,14 @@ menu "On-chip Peripheral Drivers" if BSP_USING_UART0 config BSP_UART0_RX_PIN int "uart0 rx pin number" - range 0 31 - default 8 + range 0 64 + default 8 if BSP_BOARD_PCA_10056 + default 42 if BSP_BOARD_ARDUINO_NANO_33_BLE config BSP_UART0_TX_PIN int "uart0 tx pin number" - range 0 31 - default 6 + range 0 64 + default 6 if BSP_BOARD_PCA_10056 + default 35 if BSP_BOARD_ARDUINO_NANO_33_BLE endif endif if BSP_USING_UART&&NRFX_USING_UARTE diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_sys.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_sys.c index 43b0c2cfb8..6bd1e90c6d 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_sys.c +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_sys.c @@ -271,7 +271,6 @@ E_SYS_USB0_ID nu_sys_usb0_role(void) #ifdef RT_USING_FINSH #include -FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char **argv) @@ -279,15 +278,14 @@ int cmd_reset(int argc, char **argv) rt_hw_cpu_reset(); return 0; } +MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system); int cmd_shutdown(int argc, char **argv) { rt_hw_cpu_shutdown(); return 0; } - -FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); -FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.); +MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system); int nu_clocks(int argc, char **argv) { diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c index c19d2dd34a..8d4538576b 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c @@ -310,15 +310,14 @@ int cmd_reset(int argc, char **argv) rt_hw_cpu_reset(); return 0; } +MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system); int cmd_shutdown(int argc, char **argv) { rt_hw_cpu_shutdown(); return 0; } - -FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); -FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.); +MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system); int nu_clocks(int argc, char **argv) { @@ -345,7 +344,7 @@ int nu_clocks(int argc, char **argv) return 0; } -MSH_CMD_EXPORT(nu_clocks, Get all system clocks); +MSH_CMD_EXPORT(nu_clocks, get all system clocks); #endif #ifdef RT_USING_INTERRUPT_INFO diff --git a/bsp/nv32f100x/board/src/board.c b/bsp/nv32f100x/board/src/board.c index 372099a6ba..75da79f9ee 100644 --- a/bsp/nv32f100x/board/src/board.c +++ b/bsp/nv32f100x/board/src/board.c @@ -98,21 +98,14 @@ void rt_hw_board_init() #ifdef RT_USING_HEAP rt_system_heap_init((void*)NV32_SRAM_BEGIN, (void*)NV32_SRAM_END); #endif - - - - } -long cmd_reset(int argc, char** argv) +int cmd_reset(int argc, char** argv) { NVIC_SystemReset(); return 0; } - -FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, Reset Board.); - - +MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system); /*@}*/ diff --git a/bsp/qemu-riscv-virt64/driver/plic.c b/bsp/qemu-riscv-virt64/driver/plic.c index f502bc9da0..6e2ec5e84e 100644 --- a/bsp/qemu-riscv-virt64/driver/plic.c +++ b/bsp/qemu-riscv-virt64/driver/plic.c @@ -7,7 +7,8 @@ * Date Author Notes * 2021-05-20 bigmagic first version */ -#include "rtthread.h" +#include +#include #include "plic.h" #include #include "encoding.h" diff --git a/bsp/qemu-riscv-virt64/driver/sbi.c b/bsp/qemu-riscv-virt64/driver/sbi.c index f848ec7810..129e8fcb0e 100644 --- a/bsp/qemu-riscv-virt64/driver/sbi.c +++ b/bsp/qemu-riscv-virt64/driver/sbi.c @@ -72,8 +72,8 @@ sbi_get_impl_version(void) void sbi_print_version(void) { - u_int major; - u_int minor; + int major; + int minor; /* For legacy SBI implementations. */ if (sbi_spec_version == 0) diff --git a/bsp/qemu-riscv-virt64/driver/sbi.h b/bsp/qemu-riscv-virt64/driver/sbi.h index b42d558f53..1e7ad6b4b8 100644 --- a/bsp/qemu-riscv-virt64/driver/sbi.h +++ b/bsp/qemu-riscv-virt64/driver/sbi.h @@ -48,6 +48,7 @@ #ifndef _MACHINE_SBI_H_ #define _MACHINE_SBI_H_ +#include #include /* SBI Specification Version */ diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c b/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c index cf88ebed5e..d8ab4eda8a 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c @@ -102,6 +102,6 @@ int _ac97_reg_dump(int argc, char **argv) AC97_DUMP(AC97_ADC_SLOT_MAP); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(_ac97_reg_dump, __cmd_ac97_dump, ac97 dump reg.); +MSH_CMD_EXPORT_ALIAS(_ac97_reg_dump, ac97_dump, ac97 dump reg); #endif diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c index 3498031d7b..9de431ed9b 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c @@ -391,5 +391,6 @@ int _aaci_pl041_reg_dump(int argc, char **argv) PL041_DUMP(PL041->dr4[0]); return 0; } -FINSH_FUNCTION_EXPORT_ALIAS(_aaci_pl041_reg_dump, __cmd_pl041_dump, aaci pl041 dump reg.); +MSH_CMD_EXPORT_ALIAS(_aaci_pl041_reg_dump, pl041_dump, aaci pl041 dump reg); + #endif diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c index a11707f7a2..5375955086 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c @@ -9,9 +9,12 @@ * 2020-10-30 bigmagic first version */ -#include #include + +#include #include +#include "board.h" + #include #include @@ -72,12 +75,12 @@ static struct rt_semaphore link_ack; static inline rt_uint32_t read32(void *addr) { - return (*((volatile unsigned int*)(addr))); + return (*((volatile unsigned int *)(addr))); } static inline void write32(void *addr, rt_uint32_t value) { - (*((volatile unsigned int*)(addr))) = value; + (*((volatile unsigned int *)(addr))) = value; } static void eth_rx_irq(int irq, void *param) @@ -380,7 +383,7 @@ static int bcmgenet_gmac_eth_start(void) /* Update MAC registers based on PHY property */ ret = bcmgenet_adjust_link(); - if(ret) + if (ret) { rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret); return ret; @@ -416,10 +419,10 @@ static rt_uint32_t prev_recv_cnt = 0; static rt_uint32_t cur_recv_cnt = 0; static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) { - void* desc_base; + void *desc_base; rt_uint32_t length = 0, addr = 0; rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX); - if(prod_index == index_flag) + if (prod_index == index_flag) { cur_recv_cnt = index_flag; index_flag = 0x7fffffff; @@ -428,7 +431,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) } else { - if(prev_recv_cnt == prod_index & 0xffff) + if (prev_recv_cnt == (prod_index & 0xffff)) { return 0; } @@ -437,15 +440,16 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) length = read32(desc_base + DMA_DESC_LENGTH_STATUS); length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; addr = read32(desc_base + DMA_DESC_ADDRESS_LO); + /* To cater for the IP headepr alignment the hardware does. - * This would actually not be needed if we don't program - * RBUF_ALIGN_2B - */ - rt_hw_cpu_dcache_invalidate(addr,length); + * This would actually not be needed if we don't program + * RBUF_ALIGN_2B + */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *) addr, length); *packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET); rx_index = rx_index + 1; - if(rx_index >= RX_DESCS) + if (rx_index >= RX_DESCS) { rx_index = 0; } @@ -453,7 +457,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) cur_recv_cnt = cur_recv_cnt + 1; - if(cur_recv_cnt > 0xffff) + if (cur_recv_cnt > 0xffff) { cur_recv_cnt = 0; } @@ -468,16 +472,16 @@ static int bcmgenet_gmac_eth_send(void *packet, int length) void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT; - rt_uint32_t prod_index, cons; - rt_uint32_t tries = 100; + rt_uint32_t prod_index; prod_index = read32(MAC_REG + TDMA_PROD_INDEX); len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; - rt_hw_cpu_dcache_clean((void*)packet, length); - write32((desc_base + DMA_DESC_ADDRESS_LO), packet); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)packet, length); + + write32((desc_base + DMA_DESC_ADDRESS_LO), (rt_uint32_t)packet); write32((desc_base + DMA_DESC_ADDRESS_HI), 0); write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat); @@ -631,7 +635,7 @@ struct pbuf *rt_eth_rx(rt_device_t device) if (recv_len > 0) { pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); - if(pbuf) + if (pbuf) { rt_memcpy(pbuf->payload, addr_point, recv_len); } diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.h b/bsp/raspberry-pi/raspi4-32/driver/mbox.h index 2c69bcf55a..7d59add27f 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/mbox.h +++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.h @@ -12,6 +12,7 @@ #define __MBOX_H__ #include +#include "board.h" //https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface //https://github.com/hermanhermitage/videocoreiv diff --git a/bsp/simulator/drivers/board.c b/bsp/simulator/drivers/board.c index 4facdfa1b2..17339d4e1a 100755 --- a/bsp/simulator/drivers/board.c +++ b/bsp/simulator/drivers/board.c @@ -84,7 +84,7 @@ void rt_hw_exit(void) #if defined(RT_USING_FINSH) #include FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_exit, exit, exit rt - thread); -FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_exit, __cmd_quit, exit rt-thread); +MSH_CMD_EXPORT_ALIAS(rt_hw_exit, quit, exit rt-thread); #endif /* RT_USING_FINSH */ /** diff --git a/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md b/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md index f19d86f436..2b677e7dfb 100644 --- a/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md +++ b/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md @@ -14,7 +14,7 @@ The main features of the new STM32 BSP framework are as follows: The BSP frame structure is shown in the figure below: -![BSP 框架图](./figures/frame.png) +![BSP frame structure](./figures_en/frame.png) Each BSP of the STM32 series consists of three parts, namely the general library, the BSP template and the specific development board BSP. The following table uses the F1 series BSP as an example to introduce these three parts: @@ -44,11 +44,11 @@ The first step in making a new BSP is to copy a BSP template of the same series The folder structure of the F1 series BSP template used in this example is as follows: -![F1 系列 BSP 模板文件夹内容](figures/bsp_template_dir.png) +![F1 series BSP template folder contents](figures_en/bsp_template_dir.png) Copy the `stm32f10x` folder under the template folder and change the name of the folder to `stm32f103-blue-pill`, as shown in the following figure: -![复制通用模板](./figures/copy.png) +![Copying common templates](./figures_en/copy.png) Modify the configuration file in the board folder. The modified content is shown in the following table: @@ -64,7 +64,7 @@ Modify the configuration file in the board folder. The modified content is shown Create a CubeMX project based on the target chip. The default CubeMX project is in the **CubeMX_Config** folder, double-click to open the `CubeMX_Config.ioc` project, as shown in the figure below: -![open_cubemx](figures/open_cubemx.png) +![open_cubemx](figures_en/open_cubemx.png) Change the chip model to STM32F103C8Tx in the CubeMX project. @@ -74,15 +74,15 @@ Configure the system clock, peripheral pins, etc. The steps are shown in the fig 1. Turn on the external clock, set the download mode, and turn on the serial peripherals (note that only the pins of the serial peripherals need to be selected, no other parameters need to be configured): - ![配置芯片引脚](./figures/CubeMX_1.png) + ![Configure chip pins](./figures_en/CubeMX_1.png) 2. Configure the system clock: - ![配置系统时钟](./figures/CubeMX_2.png) + ![Configuring the System Clock](./figures_en/CubeMX_2.png) 3. Set the project name and regenerate the CubeMX project at a specified address: - ![生成对应的配置代码](./figures/CubeMX_4.png) + ![Generate the corresponding configuration code](./figures_en/CubeMX_4.png) Note: When generating the code, do not check the following options (ie: Do not let it generate a peripheral initialization as a pair of .c/.h files per perioheral.) @@ -90,17 +90,17 @@ Configure the system clock, peripheral pins, etc. The steps are shown in the fig 4. The final project directory structure generated by CubeMX is shown in the figure below: - ![CubeMX 图7](./figures/CubeMX_5.png) + ![CubeMX 7](./figures_en/CubeMX_5.png) #### 3.2.2 Copy initialization function The function `SystemClock_Config()` is placed in the **board.c** file, which is responsible for initializing the system clock. When using the CubeMX tool to reconfigure the system clock, this function needs to be updated. This function is generated by the CubeMX tool and is placed in the file `board/CubeMX_Config/Src/main.c` by default. However, this file does not include in our project, so we need to copy this function from main.c to the board.c file. In the entire BSP making process, this function is the only function to be copied. The content of this function is as follows: -![board_1](./figures/board_1.png) +![board_1](./figures_en/board_1.png) The relevant parameters of FLASH and RAM are configured in the **board.h** file. What needs to be modified in this file is the parameters controlled by the two macros `STM32_FLASH_SIZE` and `STM32_SRAM_SIZE`. The flash size of the STM32F103C8Tx chip used in the BSP produced this time is 64k, and the size of the ram is 20k, so the file is modified as follows: -![修改 board.h](./figures/board_h.png) +![Modified board.h](./figures_en/board_h.png) #### 3.2.3 Heap memory configuration @@ -108,7 +108,7 @@ Normally, a part of the memory space in the system RAM will be used as heap memo In some series of chips, the chip RAM may be distributed in multiple discrete memory areas. At this time, the location of the heap memory can be in the same continuous memory area as the system memory, or it can be stored in a separate memory area. For example, on the L4 series of chips, the heap memory can be configured in a 96k memory space with a starting address of `0x20000000`, and the 32k memory space starting from `0x10000000` can be used as the system running memory. -![heap_config](figures/heap_config.png) +![heap_config](figures_en/heap_config.png) ### 3.3 Modify Kconfig configuration @@ -126,7 +126,7 @@ The modification of chip model and series is shown in the following table: Regarding the peripheral support options on the BSP, a BSP submitted for the first time only needs to support the GPIO driver and the serial port driver, which means only these two driver configuration items need to be retained in the configuration options, as shown in the following figure: -![修改 Kconfig](./figures/Kconfig.png) +![Modified Kconfig](./figures_en/Kconfig.png) ### 3.4 Modify project building related files @@ -134,19 +134,19 @@ Regarding the peripheral support options on the BSP, a BSP submitted for the fir **linker_scripts** The link file is as shown in the figure below: -![需要修改的链接脚本](./figures/linker_scripts.png) +![Link scripts that need to be modified](./figures_en/linker_scripts.png) The following uses the link script link.sct used by MDK as an example to demonstrate how to modify the link script: -![linkscripts_change](figures/linkscripts_change.png) +![linkscripts_change](figures_en/linkscripts_change.png) The chip used to make the BSP this time is STM32F103RB, and the FLASH is 128k, so modify the parameters of LR_IROM1 and ER_IROM1 to 0x00020000. The size of RAM is 20k, so modify the parameter of RW_IRAM1 to 0x00005000. Such a modification method is sufficient for general applications. If there are special requirements in the future, you need to modify it as required according to the syntax of the link script. When modifying the link script, you can refer to the [**3.2.3 Heap memory configuration**](# 3.2.3 Heap memory configuration) chapter to determine the BSP memory allocation. The other two link script files are link.icf used by IAR and link.lds used by the GCC compiler. The modification method is similar, as shown in the following figure: -![link_icf](figures/link_icf.png) +![link_icf](figures_en/link_icf.png) -![link_lds](figures/link_lds.png) +![link_lds](figures_en/link_lds.png) #### 3.4.2 Modify the build script @@ -154,7 +154,7 @@ The **SConscript** script determines the files to be added during the generation In this step, you need to modify the chip model and the address of the chip startup file. The modification content is shown in the figure below: -![修改启动文件和芯片型号](./figures/SConscript.png) +![Modify the startup file and chip model](./figures_en/SConscript.png) Note: If you cannot find the .s file of the corresponding series in the folder, it may be that multiple series of chips reuse the same startup file. At this time, you can generate the target chip project in CubeMX to see which startup file is used. Then modify the startup file name. @@ -162,15 +162,15 @@ Note: If you cannot find the .s file of the corresponding series in the folder, The **template** file is a template file for generating the MDK/IAR project. By modifying the file, you can set the chip model used in the project and the download method. The project template file of MDK4/MDK5/IAR, as shown in the figure below: -![MDK/IAR 工程模板](./figures/template_1.png) +![MDK/IAR engineering template](./figures_en/template_1.png) The following takes the modification of the MDK5 template as an example to introduce how to modify the template configuration: -![选择芯片型号](./figures/template_2.png) +![Select the chip model](./figures_en/template_2.png) Modify the program download method: -![配置下载方式](./figures/template_3.png) +![Configuring the Download Mode](./figures_en/template_3.png) ### 3.5 Regenerate the project @@ -180,17 +180,17 @@ Env tool is required to regenerate the project. Enter the command menuconfig in the Env interface to configure the project and generate a new rtconfig.h file. As shown below: -![输入menuconfig进入配置界面](./figures/menuconfig_1.png) +![Enter menuconfig to go to the configuration screen](./figures_en/menuconfig_1.png) #### 3.5.2 Rebuild the MDK/IAR project The following takes regenerating the MDK project as an example to introduce how to regenerate the BSP project. Use the Env tool to enter the command `scons --target=mdk5` to regenerate the project, as shown in the following figure: -![重新生成 BSP 工程](./figures/menuconfig_3.png) +![Regenerate the BSP project](./figures_en/menuconfig_3.png) Rebuild the project successfully: -![重新生成 BSP 工程](./figures/menuconfig_4.png) +![Regenerate the BSP project](./figures_en/menuconfig_4.png) At this point, the new BSP can be used. Next, we can use the commands `scons --target=mdk4` and `scons --target=iar` respectively to update the MDK4 and IAR projects so that the BSP becomes a complete BSP that can be submitted to GitHub (Making MDK4 project is optional). @@ -243,3 +243,4 @@ The specifications of making STM32 BSP are mainly divided into three aspects: en - When submitting libraries of different series of STM32, please refer to the HAL libraries of f1/f4 series and delete redundant library files. - Compile and test the BSP before submission to ensure that it compiles properly under different compilers. - Perform functional tests on the BSP before submission to ensure that the BSP meets the requirements in the engineering configuration chapter before submission. + diff --git a/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md b/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md index 05ac07a869..b24fd19616 100644 --- a/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md +++ b/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md @@ -14,7 +14,7 @@ By reading the ***Quickly Get Started*** section developers can quickly get thei ## Resources Introduction -[board](figures/stm32-nucleo-144.jpg) +[board](figures/stm32-nucleo-144.jpg) ### Description @@ -52,7 +52,7 @@ The STM32 Nucleo-144 board provides an affordable and flexible way for users to This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system. -![nucleo144_layout](figures/nucleo144_layout.jpg) +![nucleo144_layout](figures_en/nucleo144_layout.jpg) ### Hardware connection diff --git a/bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md b/bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md index 5cdddc3a2f..9eb9486dff 100644 --- a/bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md +++ b/bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md @@ -14,7 +14,7 @@ By reading the ***Quickly Get Started*** section developers can quickly get thei ## Resources Introduction -[![board](figures/stm32-nucleo-64.jpg)](figures/stm32-nucleo-64.jpg) +[![board](figures_en/stm32-nucleo-64.jpg)](figures/stm32-nucleo-64.jpg) ### Description @@ -50,7 +50,7 @@ The STM32 Nucleo-64 board provides an affordable and flexible way for users to t This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. 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stm32_configure(struct rt_serial_device *serial, struct serial_c uart = rt_container_of(serial, struct stm32_uart, serial); uart->handle.Instance = uart->config->Instance; uart->handle.Init.BaudRate = cfg->baud_rate; - uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; uart->handle.Init.Mode = UART_MODE_TX_RX; uart->handle.Init.OverSampling = UART_OVERSAMPLING_16; + switch (cfg->flowcontrol) + { + case RT_SERIAL_FLOWCONTROL_NONE: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + break; + case RT_SERIAL_FLOWCONTROL_CTSRTS: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS; + break; + default: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + break; + } + switch (cfg->data_bits) { case DATA_BITS_8: diff --git a/bsp/stm32/stm32f072-st-nucleo/SConstruct b/bsp/stm32/stm32f072-st-nucleo/SConstruct index 30f7822723..593ea85d6f 100644 --- a/bsp/stm32/stm32f072-st-nucleo/SConstruct +++ b/bsp/stm32/stm32f072-st-nucleo/SConstruct @@ -15,7 +15,7 @@ except: print(RTT_ROOT) exit(-1) -TARGET = 'rt-thread.' + rtconfig.TARGET_EXT +TARGET = 'rt-thread_acm32f030.' + rtconfig.TARGET_EXT DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], diff --git a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf index 63ea0d85b4..e2714da9d8 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f072-st-nucleo/board/linker_scripts/link.icf @@ -25,4 +25,4 @@ do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/stm32/stm32f072-st-nucleo/rtconfig.py b/bsp/stm32/stm32f072-st-nucleo/rtconfig.py index 00c8bc7413..f8b3d33eee 100644 --- a/bsp/stm32/stm32f072-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f072-st-nucleo/rtconfig.py @@ -23,7 +23,7 @@ elif CROSS_TOOL == 'keil': EXEC_PATH = r'C:/Keil_v5' elif CROSS_TOOL == 'iar': PLATFORM = 'iar' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + EXEC_PATH = r'D:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -57,7 +57,7 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' @@ -88,7 +88,7 @@ elif PLATFORM == 'armcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' @@ -138,7 +138,7 @@ elif PLATFORM == 'iar': LFLAGS += ' --entry __iar_program_start' CXXFLAGS = CFLAGS - + EXEC_PATH = EXEC_PATH + '/arm/bin/' POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/stm32/stm32f072-st-nucleo/template.ewp b/bsp/stm32/stm32f072-st-nucleo/template.ewp index 75b7527146..ae32e4f112 100644 --- a/bsp/stm32/stm32f072-st-nucleo/template.ewp +++ b/bsp/stm32/stm32f072-st-nucleo/template.ewp @@ -44,7 +44,7 @@